commit_title
stringlengths 13
124
| commit_body
stringlengths 0
1.9k
| release_summary
stringclasses 52
values | changes_summary
stringlengths 1
758
| release_affected_domains
stringclasses 33
values | release_affected_drivers
stringclasses 51
values | domain_of_changes
stringlengths 2
571
| language_set
stringclasses 983
values | diffstat_files
int64 1
300
| diffstat_insertions
int64 0
309k
| diffstat_deletions
int64 0
168k
| commit_diff
stringlengths 92
23.4M
| category
stringclasses 108
values | commit_hash
stringlengths 34
40
| related_people
stringlengths 0
370
| domain
stringclasses 21
values | subdomain
stringclasses 241
values | leaf_module
stringlengths 0
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mtd: spi-nor: add support for sst26vf016b
|
adds support for sst26vf016b, a smaller variant of the sst26vf064b. tested on a sama5d3 soc using the atmel,at91rm9200-spi controller. the dual read could not be tested.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for sst26vf016b
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['spi-nor']
|
['c']
| 1
| 2
| 0
|
--- diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c + { "sst26vf016b", info(0xbf2641, 0, 64 * 1024, 32, sect_4k | + spi_nor_dual_read) },
|
Memory Technology Devices (MTD)
|
67de34c20fa7a7aeae50c55dd2751e6df80c3e2c
|
joseph kust
|
drivers
|
mtd
|
spi-nor
|
mtd: spi-nor: add support for w25q32jwm
|
add support for the winbond w25q32jw-xm flashes. these have a programmable qe bit. there is also the w25q32jw-xq variant which shares the id with the w25q32dw and w25q32fw parts. the w25q32jw-xq has the qe bit hard strapped to 1, thus don't support the /hold and /wp pins.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for w25q32jwm
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['spi-nor']
|
['c']
| 1
| 5
| 0
|
--- diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c + { + "w25q32jwm", info(0xef8016, 0, 64 * 1024, 64, + sect_4k | spi_nor_dual_read | spi_nor_quad_read | + spi_nor_has_lock | spi_nor_has_tb) + },
|
Memory Technology Devices (MTD)
|
f3418718c0ec934013a36d717a00554d5fbcffc5
|
michael walle
|
drivers
|
mtd
|
spi-nor
|
mtd: spi-nor: add gigadevice gd25lq128d support
|
tested on the amlogic aml-libretech-pc platform which does not support dual or quad modes
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add gigadevice gd25lq128d support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['spi-nor']
|
['c']
| 1
| 5
| 0
|
--- diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c + { + "gd25lq128d", info(0xc86018, 0, 64 * 1024, 256, + sect_4k | spi_nor_dual_read | spi_nor_quad_read | + spi_nor_has_lock | spi_nor_has_tb) + },
|
Memory Technology Devices (MTD)
|
a56be671734ec5ab7fcfc9ac681d01698fc8bdf5
|
jerome brunet
|
drivers
|
mtd
|
spi-nor
|
mtd: spi-nor: intel-spi: add support for intel comet lake-v spi serial flash
|
intel comet lake-v has the same spi serial flash controller as kaby lake. add comet lake-v pci id to the driver list of supported devices.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for intel comet lake-v spi serial flash
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['spi-nor', 'intel-spi']
|
['c']
| 1
| 1
| 0
|
--- diff --git a/drivers/mtd/spi-nor/intel-spi-pci.c b/drivers/mtd/spi-nor/intel-spi-pci.c --- a/drivers/mtd/spi-nor/intel-spi-pci.c +++ b/drivers/mtd/spi-nor/intel-spi-pci.c + { pci_vdevice(intel, 0xa3a4), (unsigned long)&bxt_info },
|
Memory Technology Devices (MTD)
|
701a1676f313dbae578f31da4e06c5487c8aa7bb
|
mika westerberg
|
drivers
|
mtd
|
spi-nor
|
mtd: spi-nor: intel-spi: add support for intel jasper lake spi serial flash
|
intel jasper lake has the same spi serial flash controller as ice lake. add jasper lake pci id to the driver list of supported devices.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for intel jasper lake spi serial flash
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['spi-nor', 'intel-spi']
|
['c']
| 1
| 1
| 0
|
--- diff --git a/drivers/mtd/spi-nor/intel-spi-pci.c b/drivers/mtd/spi-nor/intel-spi-pci.c --- a/drivers/mtd/spi-nor/intel-spi-pci.c +++ b/drivers/mtd/spi-nor/intel-spi-pci.c + { pci_vdevice(intel, 0x4da4), (unsigned long)&bxt_info },
|
Memory Technology Devices (MTD)
|
307dd80885af7183696ab6d81d73afc7a5148df6
|
mika westerberg
|
drivers
|
mtd
|
spi-nor
|
mtd: spinand: add support for toshiba tc58cvg2s0hraij
|
toshiba recently launched new revisions of their serial slc nand series. tc58cvg2s0hraij is a refresh of previous series with minor improvements. basic parameters are same so lets add support for this new revision.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for toshiba tc58cvg2s0hraij
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['spinand']
|
['c']
| 1
| 10
| 0
|
--- diff --git a/drivers/mtd/nand/spi/toshiba.c b/drivers/mtd/nand/spi/toshiba.c --- a/drivers/mtd/nand/spi/toshiba.c +++ b/drivers/mtd/nand/spi/toshiba.c + /* 3.3v 4gb */ + spinand_info("tc58cvg2s0", 0xed, + nand_memorg(1, 4096, 256, 64, 2048, 40, 1, 1, 1), + nand_eccreq(8, 512), + spinand_info_op_variants(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + spinand_eccinfo(&tc58cxgxsx_ooblayout, + tc58cxgxsx_ecc_get_status)),
|
Memory Technology Devices (MTD)
|
9ee0f956cfbb87b19dfbbb9d588fef282eb5e95e
|
robert marko
|
drivers
|
mtd
|
nand, spi
|
iio: max31856: add option for setting mains filter rejection frequency
|
this sensor has an embedded notch filter for reducing interferences caused by the power mains. this filter can be tuned to reject either 50hz or 60hz (and harmonics).
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
provide more configuration options, also extending iio core
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['max31856']
|
['c']
| 1
| 50
| 0
|
--- diff --git a/drivers/iio/temperature/max31856.c b/drivers/iio/temperature/max31856.c --- a/drivers/iio/temperature/max31856.c +++ b/drivers/iio/temperature/max31856.c +#define max31856_cr0_filter_50hz bit(0) + bool filter_50hz; + if (data->filter_50hz) + reg_cr0_val |= max31856_cr0_filter_50hz; + else + reg_cr0_val &= ~max31856_cr0_filter_50hz; + +static ssize_t show_filter(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct max31856_data *data = iio_priv(indio_dev); + + return sprintf(buf, "%d ", data->filter_50hz ? 50 : 60); +} + +static ssize_t set_filter(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t len) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct max31856_data *data = iio_priv(indio_dev); + unsigned int freq; + int ret; + + ret = kstrtouint(buf, 10, &freq); + if (ret) + return ret; + + switch (freq) { + case 50: + data->filter_50hz = true; + break; + case 60: + data->filter_50hz = false; + break; + default: + return -einval; + } + + max31856_init(data); + return len; +} + +static iio_device_attr(in_temp_filter_notch_center_frequency, 0644, + show_filter, set_filter, 0); + &iio_dev_attr_in_temp_filter_notch_center_frequency.dev_attr.attr, + data->filter_50hz = false;
|
Industrial I/O (iio)
|
76aa41c17befa67b8727942d134eb65af501908b
|
andrea merello
|
drivers
|
iio
|
temperature
|
documentation: abi: document iio in_temp_filter_notch_center_frequency file
|
max31856 iio driver introduced a new attribute "in_temp_filter_notch_center_frequency". this patch adds it to the list of documented abi for sysfs-bus-iio
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
provide more configuration options, also extending iio core
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['max31856']
|
['sysfs-bus-iio']
| 1
| 7
| 0
|
--- diff --git a/documentation/abi/testing/sysfs-bus-iio b/documentation/abi/testing/sysfs-bus-iio --- a/documentation/abi/testing/sysfs-bus-iio +++ b/documentation/abi/testing/sysfs-bus-iio + +what: /sys/bus/iio/devices/iio:devicex/in_filter_notch_center_frequency +kernelversion: 5.5 +contact: linux-iio@vger.kernel.org +description: + center frequency in hz for a notch filter. used i.e. for line + noise suppression.
|
Industrial I/O (iio)
|
3f6bba19071eac393a7f39755e235b286a7bb09a
|
andrea merello
|
documentation
|
abi
|
testing
|
iio: max31856: add support for configuring the hw averaging
|
this sensor can perform samples averaging in hardware, but currently the driver leaves this setting alone (default is no averaging).
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
provide more configuration options, also extending iio core
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['max31856']
|
['c']
| 1
| 43
| 0
|
--- diff --git a/drivers/iio/temperature/max31856.c b/drivers/iio/temperature/max31856.c --- a/drivers/iio/temperature/max31856.c +++ b/drivers/iio/temperature/max31856.c +#include <linux/util_macros.h> +#define max31856_averaging_mask genmask(6, 4) +#define max31856_averaging_shift 4 + .info_mask_shared_by_type = + bit(iio_chan_info_oversampling_ratio) + .info_mask_shared_by_type = + bit(iio_chan_info_oversampling_ratio) + int averaging; + + reg_cr1_val &= ~max31856_averaging_mask; + reg_cr1_val |= data->averaging << max31856_averaging_shift; + + case iio_chan_info_oversampling_ratio: + *val = 1 << data->averaging; + return iio_val_int; +static int max31856_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + struct max31856_data *data = iio_priv(indio_dev); + int msb; + + switch (mask) { + case iio_chan_info_oversampling_ratio: + if (val > 16 || val < 1) + return -einval; + msb = fls(val) - 1; + /* round up to next 2pow if needed */ + if (bit(msb) < val) + msb++; + + data->averaging = msb; + max31856_init(data); + break; + + default: + return -einval; + } + + return 0; +} + + .write_raw = max31856_write_raw,
|
Industrial I/O (iio)
|
57a4274ce168d4e63a7b5f4a8a776f7bdd5666a9
|
andrea merello
|
drivers
|
iio
|
temperature
|
iio: core: add char type for sysfs attributes
|
this patch introduces iio_val_char type for standard iio attributes to allow for attributes that needs to be represented by character rather than a number. this is preparatory for introducing a new attribute whose purpose is to describe thermocouple type, that can be i.e. "j", "k", etc..
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
provide more configuration options, also extending iio core
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['max31856']
|
['c', 'h']
| 2
| 19
| 4
|
--- diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c + case iio_val_char: + return snprintf(buf, len, "%c", (char)vals[0]); - int integer, fract; + int integer, fract = 0; + bool is_char = false; + case iio_val_char: + is_char = true; + break; - ret = iio_str_to_fixpoint(buf, fract_mult, &integer, &fract); - if (ret) - return ret; + if (is_char) { + char ch; + + if (sscanf(buf, "%c", &ch) != 1) + return -einval; + integer = ch; + } else { + ret = iio_str_to_fixpoint(buf, fract_mult, &integer, &fract); + if (ret) + return ret; + } diff --git a/include/linux/iio/types.h b/include/linux/iio/types.h --- a/include/linux/iio/types.h +++ b/include/linux/iio/types.h +#define iio_val_char 12
|
Industrial I/O (iio)
|
8cb3403633146afe1ba81f79224679f5df2940d4
|
andrea merello
|
drivers
|
iio
|
iio
|
iio: core: add thermocouple_type standard attribute
|
we have a couple of thermocouple iio drivers, supporting several chips. some of them support only one specific thermocouple type (e.g. "k", "j"), one of them can be configured to work with several different thermocouple types.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
provide more configuration options, also extending iio core
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['max31856']
|
['c', 'h']
| 2
| 2
| 0
|
--- diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c + [iio_chan_info_thermocouple_type] = "thermocouple_type", diff --git a/include/linux/iio/types.h b/include/linux/iio/types.h --- a/include/linux/iio/types.h +++ b/include/linux/iio/types.h + iio_chan_info_thermocouple_type,
|
Industrial I/O (iio)
|
ddfb97d8f06c98fa5d80bbb6a997155a838161e9
|
andrea merello
|
drivers
|
iio
|
iio
|
documentation: abi: document iio thermocouple_type file
|
iio core layer gained a new sysfs standard attribute "thermocouple_type". this patch adds it to the list of documented abi for sysfs-bus-iio
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
provide more configuration options, also extending iio core
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['max31856']
|
['sysfs-bus-iio']
| 1
| 6
| 0
|
--- diff --git a/documentation/abi/testing/sysfs-bus-iio b/documentation/abi/testing/sysfs-bus-iio --- a/documentation/abi/testing/sysfs-bus-iio +++ b/documentation/abi/testing/sysfs-bus-iio + +what: /sys/bus/iio/devices/iio:devicex/in_temp_thermocouple_type +kernelversion: 5.5 +contact: linux-iio@vger.kernel.org +description: + one of the following thermocouple types: b, e, j, k, n, r, s, t.
|
Industrial I/O (iio)
|
83b9af6f283e95e9a9c2b5dc684d054278ac4728
|
andrea merello
|
documentation
|
abi
|
testing
|
iio: max31856: add support for runtime-configuring the thermocouple type
|
the sensor support various thermocouple types (e.g. j, k, n, ...). the driver allows to configure this parameter using a dt property.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
provide more configuration options, also extending iio core
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['max31856']
|
['c']
| 1
| 40
| 1
|
--- diff --git a/drivers/iio/temperature/max31856.c b/drivers/iio/temperature/max31856.c --- a/drivers/iio/temperature/max31856.c +++ b/drivers/iio/temperature/max31856.c +#include <linux/ctype.h> - bit(iio_chan_info_raw) | bit(iio_chan_info_scale), + bit(iio_chan_info_raw) | bit(iio_chan_info_scale) | + bit(iio_chan_info_thermocouple_type), +static const char max31856_tc_types[] = { + 'b', 'e', 'j', 'k', 'n', 'r', 's', 't' +}; + + case iio_chan_info_thermocouple_type: + *val = max31856_tc_types[data->thermocouple_type]; + return iio_val_char; +static int max31856_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + long mask) +{ + switch (mask) { + case iio_chan_info_thermocouple_type: + return iio_val_char; + default: + return iio_val_int; + } +} + + case iio_chan_info_thermocouple_type: + { + int tc_type = -1; + int i; + + for (i = 0; i < array_size(max31856_tc_types); i++) { + if (max31856_tc_types[i] == toupper(val)) { + tc_type = i; + break; + } + } + if (tc_type < 0) + return -einval; + data->thermocouple_type = tc_type; + max31856_init(data); + break; + } + .write_raw_get_fmt = max31856_write_raw_get_fmt,
|
Industrial I/O (iio)
|
ea4103070f03f789f305bdd1803d5d4c42f0b3b9
|
andrea merello
|
drivers
|
iio
|
temperature
|
iio: maxim_thermocouple: add thermocouple_type sysfs attribute
|
we added a sysfs abi for getting/setting the type of a thermocouple. this driver supports chips that support specific fixed thermocouple types; we cannot set it, but still we can add this sysfs attribute in ro mode to read-back the thermocouple type.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
provide more configuration options, also extending iio core
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['max31856']
|
['c']
| 1
| 41
| 3
|
- max6675 - max31855[k/j/n/s/t/e/r]asa family --- diff --git a/drivers/iio/temperature/maxim_thermocouple.c b/drivers/iio/temperature/maxim_thermocouple.c --- a/drivers/iio/temperature/maxim_thermocouple.c +++ b/drivers/iio/temperature/maxim_thermocouple.c +#include <linux/iio/sysfs.h> + max31855k, + max31855j, + max31855n, + max31855s, + max31855t, + max31855e, + max31855r, +}; + +static const char maxim_tc_types[] = { + 'k', '?', 'k', 'j', 'n', 's', 't', 'e', 'r' - bit(iio_chan_info_raw) | bit(iio_chan_info_scale), + bit(iio_chan_info_raw) | bit(iio_chan_info_scale) | + bit(iio_chan_info_thermocouple_type), - bit(iio_chan_info_raw) | bit(iio_chan_info_scale), + bit(iio_chan_info_raw) | bit(iio_chan_info_scale) | + bit(iio_chan_info_thermocouple_type), + char tc_type; + case iio_chan_info_thermocouple_type: + *val = data->tc_type; + ret = iio_val_char; + break; + const int chip_type = (id->driver_data == max6675) ? max6675 : max31855; - &maxim_thermocouple_chips[id->driver_data]; + &maxim_thermocouple_chips[chip_type]; + data->tc_type = maxim_tc_types[id->driver_data]; + if (id->driver_data == max31855) + dev_warn(&spi->dev, "generic max31855 id is deprecated please use more specific part type"); + + {"max31855k", max31855k}, + {"max31855j", max31855j}, + {"max31855n", max31855n}, + {"max31855s", max31855s}, + {"max31855t", max31855t}, + {"max31855e", max31855e}, + {"max31855r", max31855r}, + { .compatible = "maxim,max31855k" }, + { .compatible = "maxim,max31855j" }, + { .compatible = "maxim,max31855n" }, + { .compatible = "maxim,max31855s" }, + { .compatible = "maxim,max31855t" }, + { .compatible = "maxim,max31855e" }, + { .compatible = "maxim,max31855r" },
|
Industrial I/O (iio)
|
d7f6a749f30bc2296e0d92553aa9f4daad7bcf1f
|
andrea merello
|
drivers
|
iio
|
temperature
|
dt-bindings: iio: maxim_thermocouple: document new 'compatible' strings
|
now the maxim_thermocouple has new, more specific, 'compatible' strings for better distinguish the various supported chips.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
provide more configuration options, also extending iio core
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['max31856']
|
['txt']
| 1
| 5
| 2
|
--- diff --git a/documentation/devicetree/bindings/iio/temperature/maxim_thermocouple.txt b/documentation/devicetree/bindings/iio/temperature/maxim_thermocouple.txt --- a/documentation/devicetree/bindings/iio/temperature/maxim_thermocouple.txt +++ b/documentation/devicetree/bindings/iio/temperature/maxim_thermocouple.txt - - compatible: must be "maxim,max31855" or "maxim,max6675" + - compatible: must be "maxim,max6675" or one of the following: + "maxim,max31855k", "maxim,max31855j", "maxim,max31855n", + "maxim,max31855s", "maxim,max31855t", "maxim,max31855e", + "maxim,max31855r"; the generic "max,max31855" is deprecated. - reg: spi chip select number for the device - spi-max-frequency: must be 4300000 - spi-cpha: must be defined for max6675 to enable spi mode 1 - compatible = "maxim,max31855"; + compatible = "maxim,max31855k";
|
Industrial I/O (iio)
|
3922f930de9d83fab3dcdc432ac046d79583e430
|
andrea merello
|
documentation
|
devicetree
|
bindings, iio, temperature
|
iio: accel: add driver for the bma400
|
add a iio driver for the bosch bma400 3-axes ultra-low power accelerometer. the driver supports reading from the acceleration and temperature registers. the driver also supports reading and configuring the output data rate, oversampling ratio, and scale.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add driver for the bma400
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['accel']
|
['c', 'kconfig', 'maintainers', 'makefile', 'h']
| 6
| 1,004
| 0
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--- diff --git a/maintainers b/maintainers --- a/maintainers +++ b/maintainers +bosch sensortec bma400 accelerometer iio driver +m: dan robertson <dan@dlrobertson.com> +l: linux-iio@vger.kernel.org +s: maintained +f: drivers/iio/accel/bma400* +f: documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml + diff --git a/drivers/iio/accel/kconfig b/drivers/iio/accel/kconfig --- a/drivers/iio/accel/kconfig +++ b/drivers/iio/accel/kconfig +config bma400 + tristate "bosch bma400 3-axis accelerometer driver" + select regmap + select bma400_i2c if i2c + help + say y here if you want to build a driver for the bosch bma400 + triaxial acceleration sensor. + + to compile this driver as a module, choose m here: the + module will be called bma400_core and you will also get + bma400_i2c if i2c is enabled. + +config bma400_i2c + tristate + depends on bma400 + diff --git a/drivers/iio/accel/makefile b/drivers/iio/accel/makefile --- a/drivers/iio/accel/makefile +++ b/drivers/iio/accel/makefile +obj-$(config_bma400) += bma400_core.o +obj-$(config_bma400_i2c) += bma400_i2c.o diff --git a/drivers/iio/accel/bma400.h b/drivers/iio/accel/bma400.h --- /dev/null +++ b/drivers/iio/accel/bma400.h +/* spdx-license-identifier: gpl-2.0-only */ +/* + * register constants and other forward declarations needed by the bma400 + * sources. + * + * copyright 2019 dan robertson <dan@dlrobertson.com> + */ + +#ifndef _bma400_h_ +#define _bma400_h_ + +#include <linux/bits.h> +#include <linux/regmap.h> + +/* + * read-only registers + */ + +/* status and id registers */ +#define bma400_chip_id_reg 0x00 +#define bma400_err_reg 0x02 +#define bma400_status_reg 0x03 + +/* acceleration registers */ +#define bma400_x_axis_lsb_reg 0x04 +#define bma400_x_axis_msb_reg 0x05 +#define bma400_y_axis_lsb_reg 0x06 +#define bma400_y_axis_msb_reg 0x07 +#define bma400_z_axis_lsb_reg 0x08 +#define bma400_z_axis_msb_reg 0x09 + +/* sensor time registers */ +#define bma400_sensor_time0 0x0a +#define bma400_sensor_time1 0x0b +#define bma400_sensor_time2 0x0c + +/* event and interrupt registers */ +#define bma400_event_reg 0x0d +#define bma400_int_stat0_reg 0x0e +#define bma400_int_stat1_reg 0x0f +#define bma400_int_stat2_reg 0x10 + +/* temperature register */ +#define bma400_temp_data_reg 0x11 + +/* fifo length and data registers */ +#define bma400_fifo_length0_reg 0x12 +#define bma400_fifo_length1_reg 0x13 +#define bma400_fifo_data_reg 0x14 + +/* step count registers */ +#define bma400_step_cnt0_reg 0x15 +#define bma400_step_cnt1_reg 0x16 +#define bma400_step_cnt3_reg 0x17 +#define bma400_step_stat_reg 0x18 + +/* + * read-write configuration registers + */ +#define bma400_acc_config0_reg 0x19 +#define bma400_acc_config1_reg 0x1a +#define bma400_acc_config2_reg 0x1b +#define bma400_cmd_reg 0x7e + +/* chip id of bma 400 devices found in the chip id register. */ +#define bma400_id_reg_val 0x90 + +#define bma400_lp_osr_shift 5 +#define bma400_np_osr_shift 4 +#define bma400_scale_shift 6 + +#define bma400_two_bits_mask genmask(1, 0) +#define bma400_lp_osr_mask genmask(6, 5) +#define bma400_np_osr_mask genmask(5, 4) +#define bma400_acc_odr_mask genmask(3, 0) +#define bma400_acc_scale_mask genmask(7, 6) + +#define bma400_acc_odr_min_raw 0x05 +#define bma400_acc_odr_lp_raw 0x06 +#define bma400_acc_odr_max_raw 0x0b + +#define bma400_acc_odr_max_hz 800 +#define bma400_acc_odr_min_whole_hz 25 +#define bma400_acc_odr_min_hz 12 + +#define bma400_scale_min 38357 +#define bma400_scale_max 306864 + +extern const struct regmap_config bma400_regmap_config; + +int bma400_probe(struct device *dev, struct regmap *regmap, const char *name); + +int bma400_remove(struct device *dev); + +#endif diff --git a/drivers/iio/accel/bma400_core.c b/drivers/iio/accel/bma400_core.c --- /dev/null +++ b/drivers/iio/accel/bma400_core.c +// spdx-license-identifier: gpl-2.0-only +/* + * core iio driver for bosch bma400 triaxial acceleration sensor. + * + * copyright 2019 dan robertson <dan@dlrobertson.com> + * + * todo: + * - support for power management + * - support events and interrupts + * - create channel for step count + * - create channel for sensor time + */ + +#include <linux/bitops.h> +#include <linux/device.h> +#include <linux/iio/iio.h> +#include <linux/iio/sysfs.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/regmap.h> + +#include "bma400.h" + +/* + * the g-range selection may be one of 2g, 4g, 8, or 16g. the scale may + * be selected with the acc_range bits of the acc_config1 register. + * nb: this buffer is populated in the device init. + */ +static int bma400_scales[8]; + +/* + * see the acc_config1 section of the datasheet. + * nb: this buffer is populated in the device init. + */ +static int bma400_sample_freqs[14]; + +static const int bma400_osr_range[] = { 0, 1, 3 }; + +/* see the acc_config0 section of the datasheet */ +enum bma400_power_mode { + power_mode_sleep = 0x00, + power_mode_low = 0x01, + power_mode_normal = 0x02, + power_mode_invalid = 0x03, +}; + +struct bma400_sample_freq { + int hz; + int uhz; +}; + +struct bma400_data { + struct device *dev; + struct regmap *regmap; + struct mutex mutex; /* data register lock */ + struct iio_mount_matrix orientation; + enum bma400_power_mode power_mode; + struct bma400_sample_freq sample_freq; + int oversampling_ratio; + int scale; +}; + +static bool bma400_is_writable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case bma400_chip_id_reg: + case bma400_err_reg: + case bma400_status_reg: + case bma400_x_axis_lsb_reg: + case bma400_x_axis_msb_reg: + case bma400_y_axis_lsb_reg: + case bma400_y_axis_msb_reg: + case bma400_z_axis_lsb_reg: + case bma400_z_axis_msb_reg: + case bma400_sensor_time0: + case bma400_sensor_time1: + case bma400_sensor_time2: + case bma400_event_reg: + case bma400_int_stat0_reg: + case bma400_int_stat1_reg: + case bma400_int_stat2_reg: + case bma400_temp_data_reg: + case bma400_fifo_length0_reg: + case bma400_fifo_length1_reg: + case bma400_fifo_data_reg: + case bma400_step_cnt0_reg: + case bma400_step_cnt1_reg: + case bma400_step_cnt3_reg: + case bma400_step_stat_reg: + return false; + default: + return true; + } +} + +static bool bma400_is_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case bma400_err_reg: + case bma400_status_reg: + case bma400_x_axis_lsb_reg: + case bma400_x_axis_msb_reg: + case bma400_y_axis_lsb_reg: + case bma400_y_axis_msb_reg: + case bma400_z_axis_lsb_reg: + case bma400_z_axis_msb_reg: + case bma400_sensor_time0: + case bma400_sensor_time1: + case bma400_sensor_time2: + case bma400_event_reg: + case bma400_int_stat0_reg: + case bma400_int_stat1_reg: + case bma400_int_stat2_reg: + case bma400_temp_data_reg: + case bma400_fifo_length0_reg: + case bma400_fifo_length1_reg: + case bma400_fifo_data_reg: + case bma400_step_cnt0_reg: + case bma400_step_cnt1_reg: + case bma400_step_cnt3_reg: + case bma400_step_stat_reg: + return true; + default: + return false; + } +} + +const struct regmap_config bma400_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = bma400_cmd_reg, + .cache_type = regcache_rbtree, + .writeable_reg = bma400_is_writable_reg, + .volatile_reg = bma400_is_volatile_reg, +}; +export_symbol(bma400_regmap_config); + +static const struct iio_mount_matrix * +bma400_accel_get_mount_matrix(const struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct bma400_data *data = iio_priv(indio_dev); + + return &data->orientation; +} + +static const struct iio_chan_spec_ext_info bma400_ext_info[] = { + iio_mount_matrix(iio_shared_by_dir, bma400_accel_get_mount_matrix), + { } +}; + +#define bma400_acc_channel(_axis) { \ + .type = iio_accel, \ + .modified = 1, \ + .channel2 = iio_mod_##_axis, \ + .info_mask_separate = bit(iio_chan_info_raw), \ + .info_mask_shared_by_type = bit(iio_chan_info_samp_freq) | \ + bit(iio_chan_info_scale) | \ + bit(iio_chan_info_oversampling_ratio), \ + .info_mask_shared_by_type_available = bit(iio_chan_info_samp_freq) | \ + bit(iio_chan_info_scale) | \ + bit(iio_chan_info_oversampling_ratio), \ + .ext_info = bma400_ext_info, \ +} + +static const struct iio_chan_spec bma400_channels[] = { + bma400_acc_channel(x), + bma400_acc_channel(y), + bma400_acc_channel(z), + { + .type = iio_temp, + .info_mask_separate = bit(iio_chan_info_processed), + .info_mask_shared_by_type = bit(iio_chan_info_samp_freq), + }, +}; + +static int bma400_get_temp_reg(struct bma400_data *data, int *val, int *val2) +{ + unsigned int raw_temp; + int host_temp; + int ret; + + if (data->power_mode == power_mode_sleep) + return -ebusy; + + ret = regmap_read(data->regmap, bma400_temp_data_reg, &raw_temp); + if (ret) + return ret; + + host_temp = sign_extend32(raw_temp, 7); + /* + * the formula for the temp_data register in the datasheet + * is: x * 0.5 + 23 + */ + *val = (host_temp >> 1) + 23; + *val2 = (host_temp & 0x1) * 500000; + return iio_val_int_plus_micro; +} + +static int bma400_get_accel_reg(struct bma400_data *data, + const struct iio_chan_spec *chan, + int *val) +{ + __le16 raw_accel; + int lsb_reg; + int ret; + + if (data->power_mode == power_mode_sleep) + return -ebusy; + + switch (chan->channel2) { + case iio_mod_x: + lsb_reg = bma400_x_axis_lsb_reg; + break; + case iio_mod_y: + lsb_reg = bma400_y_axis_lsb_reg; + break; + case iio_mod_z: + lsb_reg = bma400_z_axis_lsb_reg; + break; + default: + dev_err(data->dev, "invalid axis channel modifier "); + return -einval; + } + + /* bulk read two registers, with the base being the lsb register */ + ret = regmap_bulk_read(data->regmap, lsb_reg, &raw_accel, + sizeof(raw_accel)); + if (ret) + return ret; + + *val = sign_extend32(le16_to_cpu(raw_accel), 11); + return iio_val_int; +} + +static void bma400_output_data_rate_from_raw(int raw, unsigned int *val, + unsigned int *val2) +{ + *val = bma400_acc_odr_max_hz >> (bma400_acc_odr_max_raw - raw); + if (raw > bma400_acc_odr_min_raw) + *val2 = 0; + else + *val2 = 500000; +} + +static int bma400_get_accel_output_data_rate(struct bma400_data *data) +{ + unsigned int val; + unsigned int odr; + int ret; + + switch (data->power_mode) { + case power_mode_low: + /* + * runs at a fixed rate in low-power mode. see section 4.3 + * in the datasheet. + */ + bma400_output_data_rate_from_raw(bma400_acc_odr_lp_raw, + &data->sample_freq.hz, + &data->sample_freq.uhz); + return 0; + case power_mode_normal: + /* + * in normal mode the odr can be found in the acc_config1 + * register. + */ + ret = regmap_read(data->regmap, bma400_acc_config1_reg, &val); + if (ret) + goto error; + + odr = val & bma400_acc_odr_mask; + if (odr < bma400_acc_odr_min_raw || + odr > bma400_acc_odr_max_raw) { + ret = -einval; + goto error; + } + + bma400_output_data_rate_from_raw(odr, &data->sample_freq.hz, + &data->sample_freq.uhz); + return 0; + case power_mode_sleep: + data->sample_freq.hz = 0; + data->sample_freq.uhz = 0; + return 0; + default: + ret = 0; + goto error; + } +error: + data->sample_freq.hz = -1; + data->sample_freq.uhz = -1; + return ret; +} + +static int bma400_set_accel_output_data_rate(struct bma400_data *data, + int hz, int uhz) +{ + unsigned int idx; + unsigned int odr; + unsigned int val; + int ret; + + if (hz >= bma400_acc_odr_min_whole_hz) { + if (uhz || hz > bma400_acc_odr_max_hz) + return -einval; + + /* note this works because min_whole_hz is odd */ + idx = __ffs(hz); + + if (hz >> idx != bma400_acc_odr_min_whole_hz) + return -einval; + + idx += bma400_acc_odr_min_raw + 1; + } else if (hz == bma400_acc_odr_min_hz && uhz == 500000) { + idx = bma400_acc_odr_min_raw; + } else { + return -einval; + } + + ret = regmap_read(data->regmap, bma400_acc_config1_reg, &val); + if (ret) + return ret; + + /* preserve the range and normal mode osr */ + odr = (~bma400_acc_odr_mask & val) | idx; + + ret = regmap_write(data->regmap, bma400_acc_config1_reg, odr); + if (ret) + return ret; + + bma400_output_data_rate_from_raw(idx, &data->sample_freq.hz, + &data->sample_freq.uhz); + return 0; +} + +static int bma400_get_accel_oversampling_ratio(struct bma400_data *data) +{ + unsigned int val; + unsigned int osr; + int ret; + + /* + * the oversampling ratio is stored in a different register + * based on the power-mode. in normal mode the osr is stored + * in acc_config1. in low-power mode it is stored in + * acc_config0. + */ + switch (data->power_mode) { + case power_mode_low: + ret = regmap_read(data->regmap, bma400_acc_config0_reg, &val); + if (ret) { + data->oversampling_ratio = -1; + return ret; + } + + osr = (val & bma400_lp_osr_mask) >> bma400_lp_osr_shift; + + data->oversampling_ratio = osr; + return 0; + case power_mode_normal: + ret = regmap_read(data->regmap, bma400_acc_config1_reg, &val); + if (ret) { + data->oversampling_ratio = -1; + return ret; + } + + osr = (val & bma400_np_osr_mask) >> bma400_np_osr_shift; + + data->oversampling_ratio = osr; + return 0; + case power_mode_sleep: + data->oversampling_ratio = 0; + return 0; + default: + data->oversampling_ratio = -1; + return -einval; + } +} + +static int bma400_set_accel_oversampling_ratio(struct bma400_data *data, + int val) +{ + unsigned int acc_config; + int ret; + + if (val & ~bma400_two_bits_mask) + return -einval; + + /* + * the oversampling ratio is stored in a different register + * based on the power-mode. + */ + switch (data->power_mode) { + case power_mode_low: + ret = regmap_read(data->regmap, bma400_acc_config0_reg, + &acc_config); + if (ret) + return ret; + + ret = regmap_write(data->regmap, bma400_acc_config0_reg, + (acc_config & ~bma400_lp_osr_mask) | + (val << bma400_lp_osr_shift)); + if (ret) { + dev_err(data->dev, "failed to write out osr "); + return ret; + } + + data->oversampling_ratio = val; + return 0; + case power_mode_normal: + ret = regmap_read(data->regmap, bma400_acc_config1_reg, + &acc_config); + if (ret) + return ret; + + ret = regmap_write(data->regmap, bma400_acc_config1_reg, + (acc_config & ~bma400_np_osr_mask) | + (val << bma400_np_osr_shift)); + if (ret) { + dev_err(data->dev, "failed to write out osr "); + return ret; + } + + data->oversampling_ratio = val; + return 0; + default: + return -einval; + } + return ret; +} + +static int bma400_accel_scale_to_raw(struct bma400_data *data, + unsigned int val) +{ + int raw; + + if (val == 0) + return -einval; + + /* note this works because bma400_scale_min is odd */ + raw = __ffs(val); + + if (val >> raw != bma400_scale_min) + return -einval; + + return raw; +} + +static int bma400_get_accel_scale(struct bma400_data *data) +{ + unsigned int raw_scale; + unsigned int val; + int ret; + + ret = regmap_read(data->regmap, bma400_acc_config1_reg, &val); + if (ret) + return ret; + + raw_scale = (val & bma400_acc_scale_mask) >> bma400_scale_shift; + if (raw_scale > bma400_two_bits_mask) + return -einval; + + data->scale = bma400_scale_min << raw_scale; + + return 0; +} + +static int bma400_set_accel_scale(struct bma400_data *data, unsigned int val) +{ + unsigned int acc_config; + int raw; + int ret; + + ret = regmap_read(data->regmap, bma400_acc_config1_reg, &acc_config); + if (ret) + return ret; + + raw = bma400_accel_scale_to_raw(data, val); + if (raw < 0) + return raw; + + ret = regmap_write(data->regmap, bma400_acc_config1_reg, + (acc_config & ~bma400_acc_scale_mask) | + (raw << bma400_scale_shift)); + if (ret) + return ret; + + data->scale = val; + return 0; +} + +static int bma400_get_power_mode(struct bma400_data *data) +{ + unsigned int val; + int ret; + + ret = regmap_read(data->regmap, bma400_status_reg, &val); + if (ret) { + dev_err(data->dev, "failed to read status register "); + return ret; + } + + data->power_mode = (val >> 1) & bma400_two_bits_mask; + return 0; +} + +static int bma400_set_power_mode(struct bma400_data *data, + enum bma400_power_mode mode) +{ + unsigned int val; + int ret; + + ret = regmap_read(data->regmap, bma400_acc_config0_reg, &val); + if (ret) + return ret; + + if (data->power_mode == mode) + return 0; + + if (mode == power_mode_invalid) + return -einval; + + /* preserve the low-power oversample ratio etc */ + ret = regmap_write(data->regmap, bma400_acc_config0_reg, + mode | (val & ~bma400_two_bits_mask)); + if (ret) { + dev_err(data->dev, "failed to write to power-mode "); + return ret; + } + + data->power_mode = mode; + + /* + * update our cached osr and odr based on the new + * power-mode. + */ + bma400_get_accel_output_data_rate(data); + bma400_get_accel_oversampling_ratio(data); + return 0; +} + +static void bma400_init_tables(void) +{ + int raw; + int i; + + for (i = 0; i + 1 < array_size(bma400_sample_freqs); i += 2) { + raw = (i / 2) + 5; + bma400_output_data_rate_from_raw(raw, &bma400_sample_freqs[i], + &bma400_sample_freqs[i + 1]); + } + + for (i = 0; i + 1 < array_size(bma400_scales); i += 2) { + raw = i / 2; + bma400_scales[i] = 0; + bma400_scales[i + 1] = bma400_scale_min << raw; + } +} + +static int bma400_init(struct bma400_data *data) +{ + unsigned int val; + int ret; + + /* try to read chip_id register. it must return 0x90. */ + ret = regmap_read(data->regmap, bma400_chip_id_reg, &val); + if (ret) { + dev_err(data->dev, "failed to read chip id register "); + goto out; + } + + if (val != bma400_id_reg_val) { + dev_err(data->dev, "chip id mismatch "); + ret = -enodev; + goto out; + } + + ret = bma400_get_power_mode(data); + if (ret) { + dev_err(data->dev, "failed to get the initial power-mode "); + goto out; + } + + if (data->power_mode != power_mode_normal) { + ret = bma400_set_power_mode(data, power_mode_normal); + if (ret) { + dev_err(data->dev, "failed to wake up the device "); + goto out; + } + /* + * todo: the datasheet waits 1500us here in the example, but + * lists 2/odr as the wakeup time. + */ + usleep_range(1500, 2000); + } + + bma400_init_tables(); + + ret = bma400_get_accel_output_data_rate(data); + if (ret) + goto out; + + ret = bma400_get_accel_oversampling_ratio(data); + if (ret) + goto out; + + ret = bma400_get_accel_scale(data); + if (ret) + goto out; + + /* + * once the interrupt engine is supported we might use the + * data_src_reg, but for now ensure this is set to the + * variable odr filter selectable by the sample frequency + * channel. + */ + return regmap_write(data->regmap, bma400_acc_config2_reg, 0x00); + +out: + return ret; +} + +static int bma400_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long mask) +{ + struct bma400_data *data = iio_priv(indio_dev); + int ret; + + switch (mask) { + case iio_chan_info_processed: + mutex_lock(&data->mutex); + ret = bma400_get_temp_reg(data, val, val2); + mutex_unlock(&data->mutex); + return ret; + case iio_chan_info_raw: + mutex_lock(&data->mutex); + ret = bma400_get_accel_reg(data, chan, val); + mutex_unlock(&data->mutex); + return ret; + case iio_chan_info_samp_freq: + switch (chan->type) { + case iio_accel: + if (data->sample_freq.hz < 0) + return -einval; + + *val = data->sample_freq.hz; + *val2 = data->sample_freq.uhz; + return iio_val_int_plus_micro; + case iio_temp: + /* + * runs at a fixed sampling frequency. see section 4.4 + * of the datasheet. + */ + *val = 6; + *val2 = 250000; + return iio_val_int_plus_micro; + default: + return -einval; + } + case iio_chan_info_scale: + *val = 0; + *val2 = data->scale; + return iio_val_int_plus_micro; + case iio_chan_info_oversampling_ratio: + /* + * todo: we could avoid this logic and returning -einval here if + * we set both the low-power and normal mode osr registers when + * we configure the device. + */ + if (data->oversampling_ratio < 0) + return -einval; + + *val = data->oversampling_ratio; + return iio_val_int; + default: + return -einval; + } +} + +static int bma400_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long mask) +{ + switch (mask) { + case iio_chan_info_scale: + *type = iio_val_int_plus_micro; + *vals = bma400_scales; + *length = array_size(bma400_scales); + return iio_avail_list; + case iio_chan_info_oversampling_ratio: + *type = iio_val_int; + *vals = bma400_osr_range; + *length = array_size(bma400_osr_range); + return iio_avail_range; + case iio_chan_info_samp_freq: + *type = iio_val_int_plus_micro; + *vals = bma400_sample_freqs; + *length = array_size(bma400_sample_freqs); + return iio_avail_list; + default: + return -einval; + } +} + +static int bma400_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int val, int val2, + long mask) +{ + struct bma400_data *data = iio_priv(indio_dev); + int ret; + + switch (mask) { + case iio_chan_info_samp_freq: + /* + * the sample frequency is readonly for the temperature + * register and a fixed value in low-power mode. + */ + if (chan->type != iio_accel) + return -einval; + + mutex_lock(&data->mutex); + ret = bma400_set_accel_output_data_rate(data, val, val2); + mutex_unlock(&data->mutex); + return ret; + case iio_chan_info_scale: + if (val != 0 || val2 > bma400_scale_max) + return -einval; + + mutex_lock(&data->mutex); + ret = bma400_set_accel_scale(data, val2); + mutex_unlock(&data->mutex); + return ret; + case iio_chan_info_oversampling_ratio: + mutex_lock(&data->mutex); + ret = bma400_set_accel_oversampling_ratio(data, val); + mutex_unlock(&data->mutex); + return ret; + default: + return -einval; + } +} + +static int bma400_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + long mask) +{ + switch (mask) { + case iio_chan_info_samp_freq: + return iio_val_int_plus_micro; + case iio_chan_info_scale: + return iio_val_int_plus_micro; + case iio_chan_info_oversampling_ratio: + return iio_val_int; + default: + return -einval; + } +} + +static const struct iio_info bma400_info = { + .read_raw = bma400_read_raw, + .read_avail = bma400_read_avail, + .write_raw = bma400_write_raw, + .write_raw_get_fmt = bma400_write_raw_get_fmt, +}; + +int bma400_probe(struct device *dev, struct regmap *regmap, const char *name) +{ + struct iio_dev *indio_dev; + struct bma400_data *data; + int ret; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); + if (!indio_dev) + return -enomem; + + data = iio_priv(indio_dev); + data->regmap = regmap; + data->dev = dev; + + ret = bma400_init(data); + if (ret) + return ret; + + ret = iio_read_mount_matrix(dev, "mount-matrix", &data->orientation); + if (ret) + return ret; + + mutex_init(&data->mutex); + indio_dev->dev.parent = dev; + indio_dev->name = name; + indio_dev->info = &bma400_info; + indio_dev->channels = bma400_channels; + indio_dev->num_channels = array_size(bma400_channels); + indio_dev->modes = indio_direct_mode; + + dev_set_drvdata(dev, indio_dev); + + return iio_device_register(indio_dev); +} +export_symbol(bma400_probe); + +int bma400_remove(struct device *dev) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct bma400_data *data = iio_priv(indio_dev); + int ret; + + mutex_lock(&data->mutex); + ret = bma400_set_power_mode(data, power_mode_sleep); + mutex_unlock(&data->mutex); + + iio_device_unregister(indio_dev); + + return ret; +} +export_symbol(bma400_remove); + +module_author("dan robertson <dan@dlrobertson.com>"); +module_description("bosch bma400 triaxial acceleration sensor core"); +module_license("gpl"); diff --git a/drivers/iio/accel/bma400_i2c.c b/drivers/iio/accel/bma400_i2c.c --- /dev/null +++ b/drivers/iio/accel/bma400_i2c.c +// spdx-license-identifier: gpl-2.0-only +/* + * i2c iio driver for bosch bma400 triaxial acceleration sensor. + * + * copyright 2019 dan robertson <dan@dlrobertson.com> + * + * i2c address is either 0x14 or 0x15 depending on sdo + */ +#include <linux/i2c.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/regmap.h> + +#include "bma400.h" + +static int bma400_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct regmap *regmap; + + regmap = devm_regmap_init_i2c(client, &bma400_regmap_config); + if (is_err(regmap)) { + dev_err(&client->dev, "failed to create regmap "); + return ptr_err(regmap); + } + + return bma400_probe(&client->dev, regmap, id->name); +} + +static int bma400_i2c_remove(struct i2c_client *client) +{ + return bma400_remove(&client->dev); +} + +static const struct i2c_device_id bma400_i2c_ids[] = { + { "bma400", 0 }, + { } +}; +module_device_table(i2c, bma400_i2c_ids); + +static const struct of_device_id bma400_of_i2c_match[] = { + { .compatible = "bosch,bma400" }, + { } +}; +module_device_table(of, bma400_of_i2c_match); + +static struct i2c_driver bma400_i2c_driver = { + .driver = { + .name = "bma400", + .of_match_table = bma400_of_i2c_match, + }, + .probe = bma400_i2c_probe, + .remove = bma400_i2c_remove, + .id_table = bma400_i2c_ids, +}; + +module_i2c_driver(bma400_i2c_driver); + +module_author("dan robertson <dan@dlrobertson.com>"); +module_description("bosch bma400 triaxial acceleration sensor (i2c)"); +module_license("gpl");
|
Industrial I/O (iio)
|
465c811f1f201a7554a95cf003bc06a239606e9b
|
dan robertson andy shevchenko andy shevchenko gmail com linus walleij linus walleij linaro org
|
drivers
|
iio
|
accel
|
iio: accel: bma180: bma254 support
|
this adds support for the bma254 variant of this accelerometer. the only difference for the simple iio driver is that values are 12 bit and the temperature offset differs by 1 degree.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
bma254 support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['accel', 'bma180']
|
['c', 'kconfig', 'txt']
| 3
| 100
| 19
|
--- diff --git a/documentation/devicetree/bindings/iio/accel/bma180.txt b/documentation/devicetree/bindings/iio/accel/bma180.txt --- a/documentation/devicetree/bindings/iio/accel/bma180.txt +++ b/documentation/devicetree/bindings/iio/accel/bma180.txt -* bosch bma180 / bma250 triaxial acceleration sensor +* bosch bma180 / bma25x triaxial acceleration sensor - - compatible : should be "bosch,bma180" or "bosch,bma250" + - compatible : should be one of: + "bosch,bma180" + "bosch,bma250" + "bosch,bma254" - reg : the i2c address of the sensor diff --git a/drivers/iio/accel/kconfig b/drivers/iio/accel/kconfig --- a/drivers/iio/accel/kconfig +++ b/drivers/iio/accel/kconfig - tristate "bosch bma180/bma250 3-axis accelerometer driver" + tristate "bosch bma180/bma25x 3-axis accelerometer driver" - bma250 triaxial acceleration sensor. + bma25x triaxial acceleration sensor. diff --git a/drivers/iio/accel/bma180.c b/drivers/iio/accel/bma180.c --- a/drivers/iio/accel/bma180.c +++ b/drivers/iio/accel/bma180.c + * bma254: 7-bit i2c slave address 0x18 or 0x19 + bma254, + u8 chip_id; + int center_temp; + u8 int_map_reg, int_enable_dataready_int1_mask; +#define bma250_id_reg_val 0x03 +#define bma254_id_reg_val 0xfa /* 250 decimal */ +#define bma254_range_reg 0x0f +#define bma254_bw_reg 0x10 +#define bma254_power_reg 0x11 +#define bma254_reset_reg 0x14 +#define bma254_int_enable_reg 0x17 +#define bma254_int_map_reg 0x1a +#define bma254_int_reset_reg 0x21 + +#define bma254_range_mask genmask(3, 0) /* range of accel values */ +#define bma254_bw_mask genmask(4, 0) /* accel bandwidth */ +#define bma254_suspend_mask bit(7) /* chip will sleep */ +#define bma254_lowpower_mask bit(6) +#define bma254_data_inten_mask bit(4) +#define bma254_int2_data_mask bit(7) +#define bma254_int1_data_mask bit(0) +#define bma254_int_reset_mask bit(7) /* reset pending interrupts */ + -static int bma250_bw_table[] = { 8, 16, 31, 63, 125, 250 }; /* hz */ -static int bma250_scale_table[] = { 0, 0, 0, 38344, 0, 76590, 0, 0, 153180, 0, +static int bma25x_bw_table[] = { 8, 16, 31, 63, 125, 250 }; /* hz */ +static int bma25x_scale_table[] = { 0, 0, 0, 38344, 0, 76590, 0, 0, 153180, 0, - if (ret != bma180_id_reg_val) + if (ret != data->part_info->chip_id) { + dev_err(&data->client->dev, "wrong chip id %d expected %d ", + ret, data->part_info->chip_id); + } -static int bma250_chip_config(struct bma180_data *data) +static int bma25x_chip_config(struct bma180_data *data) - ret = bma180_set_bits(data, bma250_int_map_reg, - bma250_int1_data_mask, 1); + /* + * this enables dataready interrupt on the int1 pin + * fixme: support using the int2 pin + */ + ret = bma180_set_bits(data, data->part_info->int_map_reg, + data->part_info->int_enable_dataready_int1_mask, 1); -static void bma250_chip_disable(struct bma180_data *data) +static void bma25x_chip_disable(struct bma180_data *data) - *val = 48; /* 0 lsb @ 24 degree c */ + *val = data->part_info->center_temp; +static const struct iio_chan_spec bma254_channels[] = { + bma180_acc_channel(x, 12), + bma180_acc_channel(y, 12), + bma180_acc_channel(z, 12), + bma180_temp_channel, + iio_chan_soft_timestamp(4), +}; + + .chip_id = bma180_id_reg_val, + .center_temp = 48, /* 0 lsb @ 24 degree c */ + .chip_id = bma250_id_reg_val, - .scale_table = bma250_scale_table, - .num_scales = array_size(bma250_scale_table), - .bw_table = bma250_bw_table, - .num_bw = array_size(bma250_bw_table), + .scale_table = bma25x_scale_table, + .num_scales = array_size(bma25x_scale_table), + .bw_table = bma25x_bw_table, + .num_bw = array_size(bma25x_bw_table), + .center_temp = 48, /* 0 lsb @ 24 degree c */ + .int_map_reg = bma250_int_map_reg, + .int_enable_dataready_int1_mask = bma250_int1_data_mask, - .chip_config = bma250_chip_config, - .chip_disable = bma250_chip_disable, + .chip_config = bma25x_chip_config, + .chip_disable = bma25x_chip_disable, + }, + [bma254] = { + .chip_id = bma254_id_reg_val, + .channels = bma254_channels, + .num_channels = array_size(bma254_channels), + .scale_table = bma25x_scale_table, + .num_scales = array_size(bma25x_scale_table), + .bw_table = bma25x_bw_table, + .num_bw = array_size(bma25x_bw_table), + .center_temp = 46, /* 0 lsb @ 23 degree c */ + .int_reset_reg = bma254_int_reset_reg, + .int_reset_mask = bma254_int_reset_mask, + .sleep_reg = bma254_power_reg, + .sleep_mask = bma254_suspend_mask, + .bw_reg = bma254_bw_reg, + .bw_mask = bma254_bw_mask, + .scale_reg = bma254_range_reg, + .scale_mask = bma254_range_mask, + .power_reg = bma254_power_reg, + .power_mask = bma254_lowpower_mask, + .lowpower_val = 1, + .int_enable_reg = bma254_int_enable_reg, + .int_enable_mask = bma254_data_inten_mask, + .int_map_reg = bma254_int_map_reg, + .int_enable_dataready_int1_mask = bma254_int1_data_mask, + .softreset_reg = bma254_reset_reg, + .chip_config = bma25x_chip_config, + .chip_disable = bma25x_chip_disable, + { "bma254", bma254 }, + { + .compatible = "bosch,bma254", + .data = (void *)bma254 + }, -module_description("bosch bma180/bma250 triaxial acceleration sensor"); +module_description("bosch bma180/bma25x triaxial acceleration sensor");
|
Industrial I/O (iio)
|
c1d1c4a62db5c4745b9e15cfee0daf0f774f73fc
|
linus walleij
|
documentation
|
devicetree
|
accel, bindings, iio
|
iio: accel: bma180: basic regulator support
|
this brings up the vdd and vddio regulators using the regulator framework. platforms that do not use regulators will provide stubs or dummy regulators.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
basic regulator support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['accel', 'bma180']
|
['c']
| 1
| 42
| 0
|
--- diff --git a/drivers/iio/accel/bma180.c b/drivers/iio/accel/bma180.c --- a/drivers/iio/accel/bma180.c +++ b/drivers/iio/accel/bma180.c +#include <linux/regulator/consumer.h> + struct regulator *vdd_supply; + struct regulator *vddio_supply; + data->vdd_supply = devm_regulator_get(dev, "vdd"); + if (is_err(data->vdd_supply)) { + if (ptr_err(data->vdd_supply) != -eprobe_defer) + dev_err(dev, "failed to get vdd regulator %d ", + (int)ptr_err(data->vdd_supply)); + return ptr_err(data->vdd_supply); + } + data->vddio_supply = devm_regulator_get(dev, "vddio"); + if (is_err(data->vddio_supply)) { + if (ptr_err(data->vddio_supply) != -eprobe_defer) + dev_err(dev, "failed to get vddio regulator %d ", + (int)ptr_err(data->vddio_supply)); + return ptr_err(data->vddio_supply); + } + /* typical voltage 2.4v these are min and max */ + ret = regulator_set_voltage(data->vdd_supply, 1620000, 3600000); + if (ret) + return ret; + ret = regulator_set_voltage(data->vddio_supply, 1200000, 3600000); + if (ret) + return ret; + ret = regulator_enable(data->vdd_supply); + if (ret) { + dev_err(dev, "failed to enable vdd regulator: %d ", ret); + return ret; + } + ret = regulator_enable(data->vddio_supply); + if (ret) { + dev_err(dev, "failed to enable vddio regulator: %d ", ret); + goto err_disable_vdd; + } + /* wait to make sure we started up properly (3 ms at least) */ + usleep_range(3000, 5000); + + regulator_disable(data->vddio_supply); +err_disable_vdd: + regulator_disable(data->vdd_supply); + regulator_disable(data->vddio_supply); + regulator_disable(data->vdd_supply);
|
Industrial I/O (iio)
|
c35aae7443023c08d406c9077c9e842b48cdb22f
|
linus walleij
|
drivers
|
iio
|
accel
|
iio: adc: add support for ad7091r5 adc
|
ad7091r5 is 4-channel, i2c, ultra low power,12-bit adc.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for ad7091r5 adc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['adc']
|
['c', 'kconfig', 'makefile', 'h']
| 5
| 401
| 0
|
--- diff --git a/drivers/iio/adc/kconfig b/drivers/iio/adc/kconfig --- a/drivers/iio/adc/kconfig +++ b/drivers/iio/adc/kconfig +config ad7091r5 + tristate "analog devices ad7091r5 adc driver" + depends on i2c + select regmap_i2c + help + say yes here to build support for analog devices ad7091r-5 adc. + diff --git a/drivers/iio/adc/makefile b/drivers/iio/adc/makefile --- a/drivers/iio/adc/makefile +++ b/drivers/iio/adc/makefile +obj-$(config_ad7091r5) += ad7091r5.o ad7091r-base.o diff --git a/drivers/iio/adc/ad7091r-base.c b/drivers/iio/adc/ad7091r-base.c --- /dev/null +++ b/drivers/iio/adc/ad7091r-base.c +// spdx-license-identifier: gpl-2.0 +/* + * ad7091rx analog to digital converter driver + * + * copyright 2014-2019 analog devices inc. + */ + +#include <linux/bitops.h> +#include <linux/iio/events.h> +#include <linux/iio/iio.h> +#include <linux/interrupt.h> +#include <linux/module.h> +#include <linux/regmap.h> + +#include "ad7091r-base.h" + +#define ad7091r_reg_result 0 +#define ad7091r_reg_channel 1 +#define ad7091r_reg_conf 2 +#define ad7091r_reg_alert 3 +#define ad7091r_reg_ch_low_limit(ch) ((ch) * 3 + 4) +#define ad7091r_reg_ch_high_limit(ch) ((ch) * 3 + 5) +#define ad7091r_reg_ch_hysteresis(ch) ((ch) * 3 + 6) + +/* ad7091r_reg_result */ +#define ad7091r_reg_result_ch_id(x) (((x) >> 13) & 0x3) +#define ad7091r_reg_result_conv_result(x) ((x) & 0xfff) + +/* ad7091r_reg_conf */ +#define ad7091r_reg_conf_auto bit(8) +#define ad7091r_reg_conf_cmd bit(10) + +#define ad7091r_reg_conf_mode_mask \ + (ad7091r_reg_conf_auto | ad7091r_reg_conf_cmd) + +enum ad7091r_mode { + ad7091r_mode_sample, + ad7091r_mode_command, + ad7091r_mode_autocycle, +}; + +struct ad7091r_state { + struct device *dev; + struct regmap *map; + const struct ad7091r_chip_info *chip_info; + enum ad7091r_mode mode; + struct mutex lock; /*lock to prevent concurent reads */ +}; + +static int ad7091r_set_mode(struct ad7091r_state *st, enum ad7091r_mode mode) +{ + int ret, conf; + + switch (mode) { + case ad7091r_mode_sample: + conf = 0; + break; + case ad7091r_mode_command: + conf = ad7091r_reg_conf_cmd; + break; + case ad7091r_mode_autocycle: + conf = ad7091r_reg_conf_auto; + break; + default: + return -einval; + } + + ret = regmap_update_bits(st->map, ad7091r_reg_conf, + ad7091r_reg_conf_mode_mask, conf); + if (ret) + return ret; + + st->mode = mode; + + return 0; +} + +static int ad7091r_set_channel(struct ad7091r_state *st, unsigned int channel) +{ + unsigned int dummy; + int ret; + + /* ad7091r_reg_channel specified which channels to be converted */ + ret = regmap_write(st->map, ad7091r_reg_channel, + bit(channel) | (bit(channel) << 8)); + if (ret) + return ret; + + /* + * there is a latency of one conversion before the channel conversion + * sequence is updated + */ + return regmap_read(st->map, ad7091r_reg_result, &dummy); +} + +static int ad7091r_read_one(struct iio_dev *iio_dev, + unsigned int channel, unsigned int *read_val) +{ + struct ad7091r_state *st = iio_priv(iio_dev); + unsigned int val; + int ret; + + ret = ad7091r_set_channel(st, channel); + if (ret) + return ret; + + ret = regmap_read(st->map, ad7091r_reg_result, &val); + if (ret) + return ret; + + if (ad7091r_reg_result_ch_id(val) != channel) + return -eio; + + *read_val = ad7091r_reg_result_conv_result(val); + + return 0; +} + +static int ad7091r_read_raw(struct iio_dev *iio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long m) +{ + struct ad7091r_state *st = iio_priv(iio_dev); + unsigned int read_val; + int ret; + + mutex_lock(&st->lock); + + switch (m) { + case iio_chan_info_raw: + if (st->mode != ad7091r_mode_command) { + ret = -ebusy; + goto unlock; + } + + ret = ad7091r_read_one(iio_dev, chan->channel, &read_val); + if (ret) + goto unlock; + + *val = read_val; + ret = iio_val_int; + break; + + default: + ret = -einval; + break; + } + +unlock: + mutex_unlock(&st->lock); + return ret; +} + +static const struct iio_info ad7091r_info = { + .read_raw = ad7091r_read_raw, +}; + +static irqreturn_t ad7091r_event_handler(int irq, void *private) +{ + struct ad7091r_state *st = (struct ad7091r_state *) private; + struct iio_dev *iio_dev = dev_get_drvdata(st->dev); + unsigned int i, read_val; + int ret; + s64 timestamp = iio_get_time_ns(iio_dev); + + ret = regmap_read(st->map, ad7091r_reg_alert, &read_val); + if (ret) + return irq_handled; + + for (i = 0; i < st->chip_info->num_channels; i++) { + if (read_val & bit(i * 2)) + iio_push_event(iio_dev, + iio_unmod_event_code(iio_voltage, i, + iio_ev_type_thresh, + iio_ev_dir_rising), timestamp); + if (read_val & bit(i * 2 + 1)) + iio_push_event(iio_dev, + iio_unmod_event_code(iio_voltage, i, + iio_ev_type_thresh, + iio_ev_dir_falling), timestamp); + } + + return irq_handled; +} + +int ad7091r_probe(struct device *dev, const char *name, + const struct ad7091r_chip_info *chip_info, + struct regmap *map, int irq) +{ + struct iio_dev *iio_dev; + struct ad7091r_state *st; + int ret; + + iio_dev = devm_iio_device_alloc(dev, sizeof(*st)); + if (!iio_dev) + return -enomem; + + st = iio_priv(iio_dev); + st->dev = dev; + st->chip_info = chip_info; + st->map = map; + + iio_dev->dev.parent = dev; + iio_dev->name = name; + iio_dev->info = &ad7091r_info; + iio_dev->modes = indio_direct_mode; + + iio_dev->num_channels = chip_info->num_channels; + iio_dev->channels = chip_info->channels; + + if (irq) { + ret = devm_request_threaded_irq(dev, irq, null, + ad7091r_event_handler, + irqf_trigger_falling | irqf_oneshot, name, st); + if (ret) + return ret; + } + + /* use command mode by default to convert only desired channels*/ + ret = ad7091r_set_mode(st, ad7091r_mode_command); + if (ret) + return ret; + + return devm_iio_device_register(dev, iio_dev); +} +export_symbol_gpl(ad7091r_probe); + +static bool ad7091r_writeable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ad7091r_reg_result: + case ad7091r_reg_alert: + return false; + default: + return true; + } +} + +static bool ad7091r_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ad7091r_reg_result: + case ad7091r_reg_alert: + return true; + default: + return false; + } +} + +const struct regmap_config ad7091r_regmap_config = { + .reg_bits = 8, + .val_bits = 16, + .writeable_reg = ad7091r_writeable_reg, + .volatile_reg = ad7091r_volatile_reg, +}; +export_symbol_gpl(ad7091r_regmap_config); + +module_author("beniamin bia <beniamin.bia@analog.com>"); +module_description("analog devices ad7091rx multi-channel converters"); +module_license("gpl v2"); diff --git a/drivers/iio/adc/ad7091r-base.h b/drivers/iio/adc/ad7091r-base.h --- /dev/null +++ b/drivers/iio/adc/ad7091r-base.h +/* spdx-license-identifier: gpl-2.0 */ +/* + * ad7091rx analog to digital converter driver + * + * copyright 2014-2019 analog devices inc. + */ + +#ifndef __drivers_iio_adc_ad7091r_base_h__ +#define __drivers_iio_adc_ad7091r_base_h__ + +struct device; +struct ad7091r_state; + +struct ad7091r_chip_info { + unsigned int num_channels; + const struct iio_chan_spec *channels; +}; + +extern const struct regmap_config ad7091r_regmap_config; + +int ad7091r_probe(struct device *dev, const char *name, + const struct ad7091r_chip_info *chip_info, + struct regmap *map, int irq); + +#endif /* __drivers_iio_adc_ad7091r_base_h__ */ diff --git a/drivers/iio/adc/ad7091r5.c b/drivers/iio/adc/ad7091r5.c --- /dev/null +++ b/drivers/iio/adc/ad7091r5.c +// spdx-license-identifier: gpl-2.0 +/* + * ad7091r5 analog to digital converter driver + * + * copyright 2014-2019 analog devices inc. + */ + +#include <linux/i2c.h> +#include <linux/iio/iio.h> +#include <linux/module.h> +#include <linux/regmap.h> + +#include "ad7091r-base.h" + +static const struct iio_event_spec ad7091r5_events[] = { + { + .type = iio_ev_type_thresh, + .dir = iio_ev_dir_rising, + .mask_separate = bit(iio_ev_info_value) | + bit(iio_ev_info_enable), + }, + { + .type = iio_ev_type_thresh, + .dir = iio_ev_dir_falling, + .mask_separate = bit(iio_ev_info_value) | + bit(iio_ev_info_enable), + }, + { + .type = iio_ev_type_thresh, + .dir = iio_ev_dir_either, + .mask_separate = bit(iio_ev_info_hysteresis), + }, +}; + +#define ad7091r_channel(idx, bits, ev, num_ev) { \ + .type = iio_voltage, \ + .info_mask_separate = bit(iio_chan_info_raw), \ + .indexed = 1, \ + .channel = idx, \ + .event_spec = ev, \ + .num_event_specs = num_ev, \ +} +static const struct iio_chan_spec ad7091r5_channels_irq[] = { + ad7091r_channel(0, 12, ad7091r5_events, array_size(ad7091r5_events)), + ad7091r_channel(1, 12, ad7091r5_events, array_size(ad7091r5_events)), + ad7091r_channel(2, 12, ad7091r5_events, array_size(ad7091r5_events)), + ad7091r_channel(3, 12, ad7091r5_events, array_size(ad7091r5_events)), +}; + +static const struct iio_chan_spec ad7091r5_channels_noirq[] = { + ad7091r_channel(0, 12, null, 0), + ad7091r_channel(1, 12, null, 0), + ad7091r_channel(2, 12, null, 0), + ad7091r_channel(3, 12, null, 0), +}; + +static const struct ad7091r_chip_info ad7091r5_chip_info_irq = { + .channels = ad7091r5_channels_irq, + .num_channels = array_size(ad7091r5_channels_irq), +}; + +static const struct ad7091r_chip_info ad7091r5_chip_info_noirq = { + .channels = ad7091r5_channels_noirq, + .num_channels = array_size(ad7091r5_channels_noirq), +}; + +static int ad7091r5_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + const struct ad7091r_chip_info *chip_info; + struct regmap *map = devm_regmap_init_i2c(i2c, &ad7091r_regmap_config); + + if (is_err(map)) + return ptr_err(map); + + if (i2c->irq) + chip_info = &ad7091r5_chip_info_irq; + else + chip_info = &ad7091r5_chip_info_noirq; + + return ad7091r_probe(&i2c->dev, id->name, chip_info, map, i2c->irq); +} + +static const struct of_device_id ad7091r5_dt_ids[] = { + { .compatible = "adi,ad7091r5" }, + {}, +}; +module_device_table(of, ad7091r5_dt_ids); + +static const struct i2c_device_id ad7091r5_i2c_ids[] = { + {"ad7091r5", 0}, + {} +}; +module_device_table(i2c, ad7091r5_i2c_ids); + +static struct i2c_driver ad7091r5_driver = { + .driver = { + .name = "ad7091r5", + .of_match_table = ad7091r5_dt_ids, + }, + .probe = ad7091r5_i2c_probe, + .id_table = ad7091r5_i2c_ids, +}; +module_i2c_driver(ad7091r5_driver); + +module_author("beniamin bia <beniamin.bia@analog.com>"); +module_description("analog devices ad7091r5 multi-channel adc driver"); +module_license("gpl v2");
|
Industrial I/O (iio)
|
ca69300173b642ba64118200172171ea5967b6c5
|
paul cercueil
|
drivers
|
iio
|
adc
|
iio: adc: ad7923: add support for the ad7908/ad7918/ad7928
|
the ad7928 is software compatible with the ad7923. the ad7908 and ad7918 are the 8 and 10-bit versions of the ad7928.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for the ad7908/ad7918/ad7928
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['adc', 'ad7923']
|
['c']
| 1
| 44
| 4
|
--- diff --git a/drivers/iio/adc/ad7923.c b/drivers/iio/adc/ad7923.c --- a/drivers/iio/adc/ad7923.c +++ b/drivers/iio/adc/ad7923.c - * ad7904/ad7914/ad7923/ad7924 spi adc driver + * ad7904/ad7914/ad7923/ad7924/ad7908/ad7918/ad7928 spi adc driver -#define ad7923_max_chan 4 + ad7908, + ad7918, + ad7928 +#define declare_ad7908_channels(name, bits) \ +const struct iio_chan_spec name ## _channels[] = { \ + ad7923_v_chan(0, bits), \ + ad7923_v_chan(1, bits), \ + ad7923_v_chan(2, bits), \ + ad7923_v_chan(3, bits), \ + ad7923_v_chan(4, bits), \ + ad7923_v_chan(5, bits), \ + ad7923_v_chan(6, bits), \ + ad7923_v_chan(7, bits), \ + iio_chan_soft_timestamp(8), \ +} + +static declare_ad7908_channels(ad7908, 8); +static declare_ad7908_channels(ad7918, 10); +static declare_ad7908_channels(ad7928, 12); + [ad7908] = { + .channels = ad7908_channels, + .num_channels = array_size(ad7908_channels), + }, + [ad7918] = { + .channels = ad7918_channels, + .num_channels = array_size(ad7918_channels), + }, + [ad7928] = { + .channels = ad7928_channels, + .num_channels = array_size(ad7928_channels), + }, - for_each_set_bit(i, active_scan_mask, ad7923_max_chan) { + /* + * for this driver the last channel is always the software timestamp so + * skip that one. + */ + for_each_set_bit(i, active_scan_mask, indio_dev->num_channels - 1) { + {"ad7908", ad7908}, + {"ad7918", ad7918}, + {"ad7928", ad7928}, + { .compatible = "adi,ad7908", }, + { .compatible = "adi,ad7918", }, + { .compatible = "adi,ad7928", }, -module_description("analog devices ad7904/ad7914/ad7923/ad7924 adc"); +module_description("analog devices ad7923 and similar adc");
|
Industrial I/O (iio)
|
851644a60d200c9a294de5a5594004bcf13d34c7
|
daniel junho alexandru ardelean alexandru ardelean analog com
|
drivers
|
iio
|
adc
|
iio: adc: new driver to support linear technology's ltc2496
|
this chip is similar to the ltc2497 adc, it just uses spi instead of i2c and so has a slightly different protocol. only the actual hardware access is different. the spi protocol is different enough to not be able to map the differences via a regmap.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
new driver to support linear technology's ltc2496
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['adc']
|
['c', 'kconfig', 'makefile', 'maintainers']
| 4
| 120
| 1
|
--- diff --git a/maintainers b/maintainers --- a/maintainers +++ b/maintainers -f: drivers/iio/adc/ltc2497* +f: drivers/iio/adc/ltc249* diff --git a/drivers/iio/adc/kconfig b/drivers/iio/adc/kconfig --- a/drivers/iio/adc/kconfig +++ b/drivers/iio/adc/kconfig +config ltc2496 + tristate "linear technology ltc2496 adc driver" + depends on spi + help + say yes here to build support for linear technology ltc2496 + 16-bit 8-/16-channel delta sigma adc. + + to compile this driver as a module, choose m here: the module will be + called ltc2496. + diff --git a/drivers/iio/adc/makefile b/drivers/iio/adc/makefile --- a/drivers/iio/adc/makefile +++ b/drivers/iio/adc/makefile +obj-$(config_ltc2496) += ltc2496.o ltc2497-core.o diff --git a/drivers/iio/adc/ltc2496.c b/drivers/iio/adc/ltc2496.c --- /dev/null +++ b/drivers/iio/adc/ltc2496.c +// spdx-license-identifier: gpl-2.0-only +/* + * ltc2496.c - driver for analog devices/linear technology ltc2496 adc + * + * based on ltc2497.c which has + * copyright (c) 2017 analog devices inc. + * + * licensed under the gpl-2. + * + * datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/2496fc.pdf + */ + +#include <linux/spi/spi.h> +#include <linux/iio/iio.h> +#include <linux/iio/driver.h> +#include <linux/module.h> +#include <linux/of.h> + +#include "ltc2497.h" + +struct ltc2496_driverdata { + /* this must be the first member */ + struct ltc2497core_driverdata common_ddata; + struct spi_device *spi; + + /* + * dma (thus cache coherency maintenance) requires the + * transfer buffers to live in their own cache lines. + */ + unsigned char rxbuf[3] ____cacheline_aligned; + unsigned char txbuf[3]; +}; + +static int ltc2496_result_and_measure(struct ltc2497core_driverdata *ddata, + u8 address, int *val) +{ + struct ltc2496_driverdata *st = + container_of(ddata, struct ltc2496_driverdata, common_ddata); + struct spi_transfer t = { + .tx_buf = st->txbuf, + .rx_buf = st->rxbuf, + .len = sizeof(st->txbuf), + }; + int ret; + + st->txbuf[0] = ltc2497_enable | address; + + ret = spi_sync_transfer(st->spi, &t, 1); + if (ret < 0) { + dev_err(&st->spi->dev, "spi_sync_transfer failed: %pe ", + err_ptr(ret)); + return ret; + } + + if (val) + *val = ((st->rxbuf[0] & 0x3f) << 12 | + st->rxbuf[1] << 4 | st->rxbuf[2] >> 4) - + (1 << 17); + + return 0; +} + +static int ltc2496_probe(struct spi_device *spi) +{ + struct iio_dev *indio_dev; + struct ltc2496_driverdata *st; + struct device *dev = &spi->dev; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); + if (!indio_dev) + return -enomem; + + st = iio_priv(indio_dev); + spi_set_drvdata(spi, indio_dev); + st->spi = spi; + st->common_ddata.result_and_measure = ltc2496_result_and_measure; + + return ltc2497core_probe(dev, indio_dev); +} + +static int ltc2496_remove(struct spi_device *spi) +{ + struct iio_dev *indio_dev = spi_get_drvdata(spi); + + ltc2497core_remove(indio_dev); + + return 0; +} + +static const struct of_device_id ltc2496_of_match[] = { + { .compatible = "lltc,ltc2496", }, + {}, +}; +module_device_table(of, ltc2496_of_match); + +static struct spi_driver ltc2496_driver = { + .driver = { + .name = "ltc2496", + .of_match_table = of_match_ptr(ltc2496_of_match), + }, + .probe = ltc2496_probe, + .remove = ltc2496_remove, +}; +module_spi_driver(ltc2496_driver); + +module_author("uwe kleine-konig <u.kleine-konig@pengutronix.de>"); +module_description("linear technology ltc2496 adc driver"); +module_license("gpl v2");
|
Industrial I/O (iio)
|
e4c5c4dfaa88e49f33e8c11b52c65c630c0b12a7
|
uwe kleine k nig
|
drivers
|
iio
|
adc
|
iio: imu: adis16480: add support for adis16490
|
the adis16490 is part of the same family with adis16495 and adis16497, the main difference is the temperature, accelerometer and gyroscope scales.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for adis16490
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['imu', 'adis16480']
|
['c']
| 1
| 17
| 0
|
--- diff --git a/drivers/iio/imu/adis16480.c b/drivers/iio/imu/adis16480.c --- a/drivers/iio/imu/adis16480.c +++ b/drivers/iio/imu/adis16480.c + adis16490, + [adis16490] = { + .channels = adis16485_channels, + .num_channels = array_size(adis16485_channels), + .gyro_max_val = 20000 << 16, + .gyro_max_scale = iio_degree_to_rad(100), + .accel_max_val = iio_m_s_2_to_g(16000 << 16), + .accel_max_scale = 8, + .temp_scale = 14285, /* 14.285 milli degree celsius */ + .int_clk = 4250000, + .max_dec_rate = 4250, + .filter_freqs = adis16495_def_filter_freqs, + .has_pps_clk_mode = true, + .timeouts = &adis16495_timeouts, + }, + { "adis16490", adis16490 }, + { .compatible = "adi,adis16490" },
|
Industrial I/O (iio)
|
80cbc848c4fa03580954ab6598e415b6b56a66ac
|
stefan popa
|
drivers
|
iio
|
imu
|
iio: imu: inv_mpu6050: add fifo temperature data support
|
add support of temperature data in fifo for all chips. enable unification of scan elements for icm20602. add macros for generating scan elements.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add fifo temperature data support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['imu', 'inv_mpu6050']
|
['c', 'h']
| 4
| 90
| 141
|
--- diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c + .temp_fifo_enable = false, +#define inv_mpu6050_temp_chan(_index) \ + { \ + .type = iio_temp, \ + .info_mask_separate = bit(iio_chan_info_raw) \ + | bit(iio_chan_info_offset) \ + | bit(iio_chan_info_scale), \ + .scan_index = _index, \ + .scan_type = { \ + .sign = 's', \ + .realbits = 16, \ + .storagebits = 16, \ + .shift = 0, \ + .endianness = iio_be, \ + }, \ + } + - /* - * note that temperature should only be via polled reading only, - * not the final scan elements output. - */ - { - .type = iio_temp, - .info_mask_separate = bit(iio_chan_info_raw) - | bit(iio_chan_info_offset) - | bit(iio_chan_info_scale), - .scan_index = -1, - }, + + inv_mpu6050_temp_chan(inv_mpu6050_scan_temp), + +#define inv_mpu6050_scan_mask_3axis_accel \ + (bit(inv_mpu6050_scan_accl_x) \ + | bit(inv_mpu6050_scan_accl_y) \ + | bit(inv_mpu6050_scan_accl_z)) + +#define inv_mpu6050_scan_mask_3axis_gyro \ + (bit(inv_mpu6050_scan_gyro_x) \ + | bit(inv_mpu6050_scan_gyro_y) \ + | bit(inv_mpu6050_scan_gyro_z)) + +#define inv_mpu6050_scan_mask_temp (bit(inv_mpu6050_scan_temp)) + - bit(inv_mpu6050_scan_accl_x) - | bit(inv_mpu6050_scan_accl_y) - | bit(inv_mpu6050_scan_accl_z), + inv_mpu6050_scan_mask_3axis_accel, + inv_mpu6050_scan_mask_3axis_accel | inv_mpu6050_scan_mask_temp, - bit(inv_mpu6050_scan_gyro_x) - | bit(inv_mpu6050_scan_gyro_y) - | bit(inv_mpu6050_scan_gyro_z), + inv_mpu6050_scan_mask_3axis_gyro, + inv_mpu6050_scan_mask_3axis_gyro | inv_mpu6050_scan_mask_temp, - bit(inv_mpu6050_scan_accl_x) - | bit(inv_mpu6050_scan_accl_y) - | bit(inv_mpu6050_scan_accl_z) - | bit(inv_mpu6050_scan_gyro_x) - | bit(inv_mpu6050_scan_gyro_y) - | bit(inv_mpu6050_scan_gyro_z), + inv_mpu6050_scan_mask_3axis_accel | inv_mpu6050_scan_mask_3axis_gyro, + inv_mpu6050_scan_mask_3axis_accel | inv_mpu6050_scan_mask_3axis_gyro + | inv_mpu6050_scan_mask_temp, - /* - * note that temperature should only be via polled reading only, - * not the final scan elements output. - */ - { - .type = iio_temp, - .info_mask_separate = bit(iio_chan_info_raw) - | bit(iio_chan_info_offset) - | bit(iio_chan_info_scale), - .scan_index = -1, - }, + + inv_mpu6050_temp_chan(inv_mpu6050_scan_temp), + - /* - * note that temperature should only be via polled reading only, - * not the final scan elements output. - */ - { - .type = iio_temp, - .info_mask_separate = bit(iio_chan_info_raw) - | bit(iio_chan_info_offset) - | bit(iio_chan_info_scale), - .scan_index = -1, - }, + + inv_mpu6050_temp_chan(inv_mpu6050_scan_temp), + +#define inv_mpu9x50_scan_mask_3axis_magn \ + (bit(inv_mpu9x50_scan_magn_x) \ + | bit(inv_mpu9x50_scan_magn_y) \ + | bit(inv_mpu9x50_scan_magn_z)) + - bit(inv_mpu6050_scan_accl_x) - | bit(inv_mpu6050_scan_accl_y) - | bit(inv_mpu6050_scan_accl_z), + inv_mpu6050_scan_mask_3axis_accel, + inv_mpu6050_scan_mask_3axis_accel | inv_mpu6050_scan_mask_temp, - bit(inv_mpu6050_scan_gyro_x) - | bit(inv_mpu6050_scan_gyro_y) - | bit(inv_mpu6050_scan_gyro_z), + inv_mpu6050_scan_mask_3axis_gyro, + inv_mpu6050_scan_mask_3axis_gyro | inv_mpu6050_scan_mask_temp, - bit(inv_mpu9x50_scan_magn_x) - | bit(inv_mpu9x50_scan_magn_y) - | bit(inv_mpu9x50_scan_magn_z), + inv_mpu9x50_scan_mask_3axis_magn, + inv_mpu9x50_scan_mask_3axis_magn | inv_mpu6050_scan_mask_temp, - bit(inv_mpu6050_scan_accl_x) - | bit(inv_mpu6050_scan_accl_y) - | bit(inv_mpu6050_scan_accl_z) - | bit(inv_mpu6050_scan_gyro_x) - | bit(inv_mpu6050_scan_gyro_y) - | bit(inv_mpu6050_scan_gyro_z), + inv_mpu6050_scan_mask_3axis_accel | inv_mpu6050_scan_mask_3axis_gyro, + inv_mpu6050_scan_mask_3axis_accel | inv_mpu6050_scan_mask_3axis_gyro + | inv_mpu6050_scan_mask_temp, - bit(inv_mpu6050_scan_accl_x) - | bit(inv_mpu6050_scan_accl_y) - | bit(inv_mpu6050_scan_accl_z) - | bit(inv_mpu9x50_scan_magn_x) - | bit(inv_mpu9x50_scan_magn_y) - | bit(inv_mpu9x50_scan_magn_z), + inv_mpu6050_scan_mask_3axis_accel | inv_mpu9x50_scan_mask_3axis_magn, + inv_mpu6050_scan_mask_3axis_accel | inv_mpu9x50_scan_mask_3axis_magn + | inv_mpu6050_scan_mask_temp, - bit(inv_mpu6050_scan_gyro_x) - | bit(inv_mpu6050_scan_gyro_y) - | bit(inv_mpu6050_scan_gyro_z) - | bit(inv_mpu9x50_scan_magn_x) - | bit(inv_mpu9x50_scan_magn_y) - | bit(inv_mpu9x50_scan_magn_z), + inv_mpu6050_scan_mask_3axis_gyro | inv_mpu9x50_scan_mask_3axis_magn, + inv_mpu6050_scan_mask_3axis_gyro | inv_mpu9x50_scan_mask_3axis_magn + | inv_mpu6050_scan_mask_temp, - bit(inv_mpu6050_scan_accl_x) - | bit(inv_mpu6050_scan_accl_y) - | bit(inv_mpu6050_scan_accl_z) - | bit(inv_mpu6050_scan_gyro_x) - | bit(inv_mpu6050_scan_gyro_y) - | bit(inv_mpu6050_scan_gyro_z) - | bit(inv_mpu9x50_scan_magn_x) - | bit(inv_mpu9x50_scan_magn_y) - | bit(inv_mpu9x50_scan_magn_z), + inv_mpu6050_scan_mask_3axis_accel | inv_mpu6050_scan_mask_3axis_gyro + | inv_mpu9x50_scan_mask_3axis_magn, + inv_mpu6050_scan_mask_3axis_accel | inv_mpu6050_scan_mask_3axis_gyro + | inv_mpu9x50_scan_mask_3axis_magn + | inv_mpu6050_scan_mask_temp, -static const struct iio_chan_spec inv_icm20602_channels[] = { - iio_chan_soft_timestamp(inv_icm20602_scan_timestamp), - { - .type = iio_temp, - .info_mask_separate = bit(iio_chan_info_raw) - | bit(iio_chan_info_offset) - | bit(iio_chan_info_scale), - .scan_index = inv_icm20602_scan_temp, - .scan_type = { - .sign = 's', - .realbits = 16, - .storagebits = 16, - .shift = 0, - .endianness = iio_be, - }, - }, - - inv_mpu6050_chan(iio_angl_vel, iio_mod_x, inv_icm20602_scan_gyro_x), - inv_mpu6050_chan(iio_angl_vel, iio_mod_y, inv_icm20602_scan_gyro_y), - inv_mpu6050_chan(iio_angl_vel, iio_mod_z, inv_icm20602_scan_gyro_z), - - inv_mpu6050_chan(iio_accel, iio_mod_y, inv_icm20602_scan_accl_y), - inv_mpu6050_chan(iio_accel, iio_mod_x, inv_icm20602_scan_accl_x), - inv_mpu6050_chan(iio_accel, iio_mod_z, inv_icm20602_scan_accl_z), -}; - - bit(inv_icm20602_scan_accl_x) - | bit(inv_icm20602_scan_accl_y) - | bit(inv_icm20602_scan_accl_z) - | bit(inv_icm20602_scan_temp), + inv_mpu6050_scan_mask_3axis_accel | inv_mpu6050_scan_mask_temp, - bit(inv_icm20602_scan_gyro_x) - | bit(inv_icm20602_scan_gyro_y) - | bit(inv_icm20602_scan_gyro_z) - | bit(inv_icm20602_scan_temp), + inv_mpu6050_scan_mask_3axis_gyro | inv_mpu6050_scan_mask_temp, - bit(inv_icm20602_scan_accl_x) - | bit(inv_icm20602_scan_accl_y) - | bit(inv_icm20602_scan_accl_z) - | bit(inv_icm20602_scan_gyro_x) - | bit(inv_icm20602_scan_gyro_y) - | bit(inv_icm20602_scan_gyro_z) - | bit(inv_icm20602_scan_temp), + inv_mpu6050_scan_mask_3axis_accel | inv_mpu6050_scan_mask_3axis_gyro + | inv_mpu6050_scan_mask_temp, - indio_dev->channels = inv_icm20602_channels; - indio_dev->num_channels = array_size(inv_icm20602_channels); + indio_dev->channels = inv_mpu_channels; + indio_dev->num_channels = array_size(inv_mpu_channels); diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h b/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h + * @temp_fifo_enable: enable temp data output + unsigned int temp_fifo_enable:1; +#define inv_mpu6050_bit_temp_out 0x80 -/* icm20602 fifo samples include temperature readings */ -#define inv_icm20602_bytes_per_temp_sensor 2 +/* fifo temperature sample size */ +#define inv_mpu6050_bytes_per_temp_sensor 2 -/* 6 + 6 + 7 (for mpu9x50) = 19 round up to 24 and plus 8 */ +/* 6 + 6 + 2 + 7 (for mpu9x50) = 21 round up to 24 and plus 8 */ + inv_mpu6050_scan_temp, -/* scan element definition for icm20602, which includes temperature */ -enum inv_icm20602_scan { - inv_icm20602_scan_accl_x, - inv_icm20602_scan_accl_y, - inv_icm20602_scan_accl_z, - inv_icm20602_scan_temp, - inv_icm20602_scan_gyro_x, - inv_icm20602_scan_gyro_y, - inv_icm20602_scan_gyro_z, - inv_icm20602_scan_timestamp, -}; - diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c + if (st->chip_config.temp_fifo_enable) + d |= inv_mpu6050_bit_temp_out; - if (st->chip_type == inv_icm20602) - bytes_per_datum += inv_icm20602_bytes_per_temp_sensor; + if (st->chip_config.temp_fifo_enable) + bytes_per_datum += inv_mpu6050_bytes_per_temp_sensor; diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c + + st->chip_config.temp_fifo_enable = + test_bit(inv_mpu6050_scan_temp, indio_dev->active_scan_mask);
|
Industrial I/O (iio)
|
2e4c0a5e25768097ecdb514ef453b423e932beea
|
jean baptiste maneyrol
|
drivers
|
iio
|
imu, inv_mpu6050
|
iio: imu: inv_mpu6050: add support of mpu9150 magnetometer
|
add support for driving mpu9150 magnetometer (ak8975) from mpu.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support of mpu9150 magnetometer
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['imu', 'inv_mpu6050']
|
['c']
| 4
| 104
| 36
|
--- diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c +static const struct iio_chan_spec inv_mpu9150_channels[] = { + iio_chan_soft_timestamp(inv_mpu9x50_scan_timestamp), + /* + * note that temperature should only be via polled reading only, + * not the final scan elements output. + */ + { + .type = iio_temp, + .info_mask_separate = bit(iio_chan_info_raw) + | bit(iio_chan_info_offset) + | bit(iio_chan_info_scale), + .scan_index = -1, + }, + inv_mpu6050_chan(iio_angl_vel, iio_mod_x, inv_mpu6050_scan_gyro_x), + inv_mpu6050_chan(iio_angl_vel, iio_mod_y, inv_mpu6050_scan_gyro_y), + inv_mpu6050_chan(iio_angl_vel, iio_mod_z, inv_mpu6050_scan_gyro_z), + + inv_mpu6050_chan(iio_accel, iio_mod_x, inv_mpu6050_scan_accl_x), + inv_mpu6050_chan(iio_accel, iio_mod_y, inv_mpu6050_scan_accl_y), + inv_mpu6050_chan(iio_accel, iio_mod_z, inv_mpu6050_scan_accl_z), + + /* magnetometer resolution is 13 bits */ + inv_mpu9x50_magn_chan(iio_mod_x, 13, inv_mpu9x50_scan_magn_x), + inv_mpu9x50_magn_chan(iio_mod_y, 13, inv_mpu9x50_scan_magn_y), + inv_mpu9x50_magn_chan(iio_mod_z, 13, inv_mpu9x50_scan_magn_z), +}; + + case inv_mpu9150: + indio_dev->channels = inv_mpu9150_channels; + indio_dev->num_channels = array_size(inv_mpu9150_channels); + indio_dev->available_scan_masks = inv_mpu9x50_scan_masks; + break; - /* - * use magnetometer inside the chip only if there is no i2c - * auxiliary device in use. - */ - if (!st->magn_disabled) { - indio_dev->channels = inv_mpu9250_channels; - indio_dev->num_channels = array_size(inv_mpu9250_channels); - indio_dev->available_scan_masks = inv_mpu9x50_scan_masks; - } else { - indio_dev->channels = inv_mpu_channels; - indio_dev->num_channels = array_size(inv_mpu_channels); - indio_dev->available_scan_masks = inv_mpu_scan_masks; - } + indio_dev->channels = inv_mpu9250_channels; + indio_dev->num_channels = array_size(inv_mpu9250_channels); + indio_dev->available_scan_masks = inv_mpu9x50_scan_masks; + /* + * use magnetometer inside the chip only if there is no i2c + * auxiliary device in use. otherwise going back to 6-axis only. + */ + if (st->magn_disabled) { + indio_dev->channels = inv_mpu_channels; + indio_dev->num_channels = array_size(inv_mpu_channels); + indio_dev->available_scan_masks = inv_mpu_scan_masks; + } diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_i2c.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_i2c.c --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_i2c.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_i2c.c + case inv_mpu9150: + case inv_mpu9150: diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_magn.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_magn.c --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_magn.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_magn.c - * mpu9250 magnetometer is an akm ak8963 chip on i2c aux bus + * mpu9xxx magnetometer are akm chips on i2c aux bus + * mpu9150 is ak8975 + * mpu9250 is ak8963 -#define inv_mpu_magn_bit_output_bit 0x10 +#define inv_mpu9250_magn_bit_output_bit 0x10 -#define inv_mpu_magn_reg_cntl2 0x0b -#define inv_mpu_magn_bit_srst 0x01 +#define inv_mpu9250_magn_reg_cntl2 0x0b +#define inv_mpu9250_magn_bit_srst 0x01 + case inv_mpu9150: + int32_t sensitivity; - /* reset chip */ - ret = inv_mpu_aux_write(st, inv_mpu_magn_i2c_addr, - inv_mpu_magn_reg_cntl2, - inv_mpu_magn_bit_srst); - if (ret) - return ret; + /* software reset for mpu925x only */ + switch (st->chip_type) { + case inv_mpu9250: + case inv_mpu9255: + ret = inv_mpu_aux_write(st, inv_mpu_magn_i2c_addr, + inv_mpu9250_magn_reg_cntl2, + inv_mpu9250_magn_bit_srst); + if (ret) + return ret; + break; + default: + break; + } + /* + * sensor sentivity + * 1 ut = 0.01 g and value is in micron (1e6) + * sensitvity = x ut * 0.01 * 1e6 + */ + switch (st->chip_type) { + case inv_mpu9150: + /* sensor sensitivity is 0.3 ut */ + sensitivity = 3000; + break; + case inv_mpu9250: + case inv_mpu9255: + /* sensor sensitivity in 16 bits mode: 0.15 ut */ + sensitivity = 1500; + break; + default: + return -einval; + } + - * sensor sentivity - * 0.15 ut in 16 bits mode - * 1 ut = 0.01 g and value is in micron (1e6) - * sensitvity = 0.15 ut * 0.01 * 1e6 - * - * raw_to_gauss = hadj * 1500 + * raw_to_gauss = hadj * sensitivity - st->magn_raw_to_gauss[0] = (((int32_t)asa[0] + 128) * 1500) / 256; - st->magn_raw_to_gauss[1] = (((int32_t)asa[1] + 128) * 1500) / 256; - st->magn_raw_to_gauss[2] = (((int32_t)asa[2] + 128) * 1500) / 256; + st->magn_raw_to_gauss[0] = (((int32_t)asa[0] + 128) * sensitivity) / 256; + st->magn_raw_to_gauss[1] = (((int32_t)asa[1] + 128) * sensitivity) / 256; + st->magn_raw_to_gauss[2] = (((int32_t)asa[2] + 128) * sensitivity) / 256; + uint8_t val; - /* add 16 bits mode */ - ret = regmap_write(st->map, inv_mpu6050_reg_i2c_slv_do(1), - inv_mpu_magn_bits_mode_single | - inv_mpu_magn_bit_output_bit); + /* add 16 bits mode for mpu925x */ + val = inv_mpu_magn_bits_mode_single; + switch (st->chip_type) { + case inv_mpu9250: + case inv_mpu9255: + val |= inv_mpu9250_magn_bit_output_bit; + break; + default: + break; + } + ret = regmap_write(st->map, inv_mpu6050_reg_i2c_slv_do(1), val); + case inv_mpu9150: diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c + case inv_mpu9150:
|
Industrial I/O (iio)
|
a2587eb032f1679dd695b9e5113bcb6b52e46e0a
|
jean baptiste maneyrol
|
drivers
|
iio
|
imu, inv_mpu6050
|
iio: ping: add parallax ping sensors
|
add support for parallax ping and laser ping sensors with just one pin for trigger and echo signal.
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this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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add parallax ping sensors
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
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['ping']
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['c', 'kconfig', 'makefile']
| 3
| 351
| 0
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--- diff --git a/drivers/iio/proximity/kconfig b/drivers/iio/proximity/kconfig --- a/drivers/iio/proximity/kconfig +++ b/drivers/iio/proximity/kconfig +config ping + tristate "parallax gpio bitbanged ranger sensors" + depends on gpiolib + help + say y here to build a driver for gpio bitbanged ranger sensors + with just one gpio for the trigger and echo. this driver can be + used to measure the distance of objects. + + actually supported are: + - parallax ping))) (ultrasonic) + - parallax laserping (time-of-flight) + + to compile this driver as a module, choose m here: the + module will be called ping. + diff --git a/drivers/iio/proximity/makefile b/drivers/iio/proximity/makefile --- a/drivers/iio/proximity/makefile +++ b/drivers/iio/proximity/makefile +obj-$(config_ping) += ping.o diff --git a/drivers/iio/proximity/ping.c b/drivers/iio/proximity/ping.c --- /dev/null +++ b/drivers/iio/proximity/ping.c +// spdx-license-identifier: gpl-2.0-or-later +/* + * ping: ultrasonic sensor for distance measuring by using only one gpios + * + * copyright (c) 2019 andreas klinger <ak@it-klinger.de> + * + * for details about the devices see: + * http://parallax.com/sites/default/files/downloads/28041-laserping-2m-rangefinder-guide.pdf + * http://parallax.com/sites/default/files/downloads/28015-ping-documentation-v1.6.pdf + * + * the measurement cycle as timing diagram looks like: + * + * gpio ___ ________________________ + * ping: __/ \____________/ \________________ + * ^ ^ ^ ^ + * |<->| interrupt interrupt + * udelay(5) (ts_rising) (ts_falling) + * |<---------------------->| + * . pulse time measured . + * . --> one round trip of ultra sonic waves + * ultra . . + * sonic _ _ _. . + * burst: _________/ \_/ \_/ \_________________________________________ + * . + * ultra . + * sonic _ _ _. + * echo: __________________________________/ \_/ \_/ \________________ + */ +#include <linux/err.h> +#include <linux/gpio/consumer.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/property.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/delay.h> +#include <linux/iio/iio.h> +#include <linux/iio/sysfs.h> + +struct ping_cfg { + unsigned long trigger_pulse_us; /* length of trigger pulse */ + int laserping_error; /* support error code in */ + /* pulse width of laser */ + /* ping sensors */ + s64 timeout_ns; /* timeout in ns */ +}; + +struct ping_data { + struct device *dev; + struct gpio_desc *gpiod_ping; + struct mutex lock; + int irqnr; + ktime_t ts_rising; + ktime_t ts_falling; + struct completion rising; + struct completion falling; + const struct ping_cfg *cfg; +}; + +static const struct ping_cfg pa_ping_cfg = { + .trigger_pulse_us = 5, + .laserping_error = 0, + .timeout_ns = 18500000, /* 3 meters */ +}; + +static const struct ping_cfg pa_laser_ping_cfg = { + .trigger_pulse_us = 5, + .laserping_error = 1, + .timeout_ns = 15500000, /* 2 meters plus error codes */ +}; + +static irqreturn_t ping_handle_irq(int irq, void *dev_id) +{ + struct iio_dev *indio_dev = dev_id; + struct ping_data *data = iio_priv(indio_dev); + ktime_t now = ktime_get(); + + if (gpiod_get_value(data->gpiod_ping)) { + data->ts_rising = now; + complete(&data->rising); + } else { + data->ts_falling = now; + complete(&data->falling); + } + + return irq_handled; +} + +static int ping_read(struct ping_data *data) +{ + int ret; + ktime_t ktime_dt; + s64 dt_ns; + u32 time_ns, distance_mm; + struct platform_device *pdev = to_platform_device(data->dev); + struct iio_dev *indio_dev = iio_priv_to_dev(data); + + /* + * just one read-echo-cycle can take place at a time + * ==> lock against concurrent reading calls + */ + mutex_lock(&data->lock); + + reinit_completion(&data->rising); + reinit_completion(&data->falling); + + gpiod_set_value(data->gpiod_ping, 1); + udelay(data->cfg->trigger_pulse_us); + gpiod_set_value(data->gpiod_ping, 0); + + ret = gpiod_direction_input(data->gpiod_ping); + if (ret < 0) { + mutex_unlock(&data->lock); + return ret; + } + + data->irqnr = gpiod_to_irq(data->gpiod_ping); + if (data->irqnr < 0) { + dev_err(data->dev, "gpiod_to_irq: %d ", data->irqnr); + mutex_unlock(&data->lock); + return data->irqnr; + } + + ret = request_irq(data->irqnr, ping_handle_irq, + irqf_trigger_rising | irqf_trigger_falling, + pdev->name, indio_dev); + if (ret < 0) { + dev_err(data->dev, "request_irq: %d ", ret); + mutex_unlock(&data->lock); + return ret; + } + + /* it should not take more than 20 ms until echo is rising */ + ret = wait_for_completion_killable_timeout(&data->rising, hz/50); + if (ret < 0) + goto err_reset_direction; + else if (ret == 0) { + ret = -etimedout; + goto err_reset_direction; + } + + /* it cannot take more than 50 ms until echo is falling */ + ret = wait_for_completion_killable_timeout(&data->falling, hz/20); + if (ret < 0) + goto err_reset_direction; + else if (ret == 0) { + ret = -etimedout; + goto err_reset_direction; + } + + ktime_dt = ktime_sub(data->ts_falling, data->ts_rising); + + free_irq(data->irqnr, indio_dev); + + ret = gpiod_direction_output(data->gpiod_ping, gpiod_out_low); + if (ret < 0) { + mutex_unlock(&data->lock); + return ret; + } + + mutex_unlock(&data->lock); + + dt_ns = ktime_to_ns(ktime_dt); + if (dt_ns > data->cfg->timeout_ns) { + dev_dbg(data->dev, "distance out of range: dt=%lldns ", + dt_ns); + return -eio; + } + + time_ns = dt_ns; + + /* + * read error code of laser ping sensor and give users chance to + * figure out error by using dynamic debuggging + */ + if (data->cfg->laserping_error) { + if ((time_ns > 12500000) && (time_ns <= 13500000)) { + dev_dbg(data->dev, "target too close or to far "); + return -eio; + } + if ((time_ns > 13500000) && (time_ns <= 14500000)) { + dev_dbg(data->dev, "internal sensor error "); + return -eio; + } + if ((time_ns > 14500000) && (time_ns <= 15500000)) { + dev_dbg(data->dev, "internal sensor timeout "); + return -eio; + } + } + + /* + * the speed as function of the temperature is approximately: + * + * speed = 331,5 + 0,6 * temp + * with temp in c + * and speed in m/s + * + * use 343,5 m/s as ultrasonic speed at 20 c here in absence of the + * temperature + * + * therefore: + * time 343,5 time * 232 + * distance = ------ * ------- = ------------ + * 10^6 2 1350800 + * with time in ns + * and distance in mm (one way) + * + * because we limit to 3 meters the multiplication with 232 just + * fits into 32 bit + */ + distance_mm = time_ns * 232 / 1350800; + + return distance_mm; + +err_reset_direction: + free_irq(data->irqnr, indio_dev); + mutex_unlock(&data->lock); + + if (gpiod_direction_output(data->gpiod_ping, gpiod_out_low)) + dev_dbg(data->dev, "error in gpiod_direction_output "); + return ret; +} + +static int ping_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *channel, int *val, + int *val2, long info) +{ + struct ping_data *data = iio_priv(indio_dev); + int ret; + + if (channel->type != iio_distance) + return -einval; + + switch (info) { + case iio_chan_info_raw: + ret = ping_read(data); + if (ret < 0) + return ret; + *val = ret; + return iio_val_int; + case iio_chan_info_scale: + /* + * maximum resolution in datasheet is 1 mm + * 1 lsb is 1 mm + */ + *val = 0; + *val2 = 1000; + return iio_val_int_plus_micro; + default: + return -einval; + } +} + +static const struct iio_info ping_iio_info = { + .read_raw = ping_read_raw, +}; + +static const struct iio_chan_spec ping_chan_spec[] = { + { + .type = iio_distance, + .info_mask_separate = + bit(iio_chan_info_raw) | + bit(iio_chan_info_scale), + }, +}; + +static const struct of_device_id of_ping_match[] = { + { .compatible = "parallax,ping", .data = &pa_ping_cfg}, + { .compatible = "parallax,laserping", .data = &pa_ping_cfg}, + {}, +}; + +module_device_table(of, of_ping_match); + +static int ping_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ping_data *data; + struct iio_dev *indio_dev; + + indio_dev = devm_iio_device_alloc(dev, sizeof(struct ping_data)); + if (!indio_dev) { + dev_err(dev, "failed to allocate iio device "); + return -enomem; + } + + data = iio_priv(indio_dev); + data->dev = dev; + data->cfg = of_device_get_match_data(dev); + + mutex_init(&data->lock); + init_completion(&data->rising); + init_completion(&data->falling); + + data->gpiod_ping = devm_gpiod_get(dev, "ping", gpiod_out_low); + if (is_err(data->gpiod_ping)) { + dev_err(dev, "failed to get ping-gpios: err=%ld ", + ptr_err(data->gpiod_ping)); + return ptr_err(data->gpiod_ping); + } + + if (gpiod_cansleep(data->gpiod_ping)) { + dev_err(data->dev, "cansleep-gpios not supported "); + return -enodev; + } + + platform_set_drvdata(pdev, indio_dev); + + indio_dev->name = "ping"; + indio_dev->dev.parent = &pdev->dev; + indio_dev->info = &ping_iio_info; + indio_dev->modes = indio_direct_mode; + indio_dev->channels = ping_chan_spec; + indio_dev->num_channels = array_size(ping_chan_spec); + + return devm_iio_device_register(dev, indio_dev); +} + +static struct platform_driver ping_driver = { + .probe = ping_probe, + .driver = { + .name = "ping-gpio", + .of_match_table = of_ping_match, + }, +}; + +module_platform_driver(ping_driver); + +module_author("andreas klinger <ak@it-klinger.de>"); +module_description("ping sensors for distance measuring using one gpios"); +module_license("gpl"); +module_alias("platform:ping");
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Industrial I/O (iio)
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7bb501f49ddb96365ef8d4fe882e5ceaa36215e4
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andreas klinger
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drivers
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iio
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proximity
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iio: pressure: add driver for dlh pressure sensors
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all sensors dlh is series of low voltage digital pressure sensors. additionally to pressure value sensors deliver a temperature value. sensors can be accessed over i2c and spi, this driver supports only i2c access.
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this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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add driver for dlh pressure sensors
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
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['pressure']
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['c', 'kconfig', 'makefile', 'maintainers']
| 4
| 395
| 0
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--- diff --git a/maintainers b/maintainers --- a/maintainers +++ b/maintainers +all sensors dlh series pressure sensors driver +m: tomislav denis <tomislav.denis@avl.com> +w: http://www.allsensors.com/ +s: maintained +l: linux-iio@vger.kernel.org +f: drivers/iio/pressure/dlhl60d.c + diff --git a/drivers/iio/pressure/kconfig b/drivers/iio/pressure/kconfig --- a/drivers/iio/pressure/kconfig +++ b/drivers/iio/pressure/kconfig +config dlhl60d + tristate "all sensors dlhl60d and dlhl60g low voltage digital pressure sensors" + depends on i2c + select iio_buffer + select iio_triggered_buffer + help + say yes here to build support for the all sensors dlh series + pressure sensors driver. + + to compile this driver as a module, choose m here: the module + will be called dlhl60d. + diff --git a/drivers/iio/pressure/makefile b/drivers/iio/pressure/makefile --- a/drivers/iio/pressure/makefile +++ b/drivers/iio/pressure/makefile +obj-$(config_dlhl60d) += dlhl60d.o diff --git a/drivers/iio/pressure/dlhl60d.c b/drivers/iio/pressure/dlhl60d.c --- /dev/null +++ b/drivers/iio/pressure/dlhl60d.c +// spdx-license-identifier: gpl-2.0 +/* + * all sensors dlh series low voltage digital pressure sensors + * + * copyright (c) 2019 avl ditest gmbh + * tomislav denis <tomislav.denis@avl.com> + * + * datasheet: http://www.allsensors.com/cad/ds-0355_rev_b.pdf + */ + +#include <linux/module.h> +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/iio/iio.h> +#include <linux/iio/buffer.h> +#include <linux/iio/trigger_consumer.h> +#include <linux/iio/triggered_buffer.h> +#include <asm/unaligned.h> + +/* commands */ +#define dlh_start_single 0xaa + +/* status bits */ +#define dlh_status_ok 0x40 + +/* dlh data format */ +#define dlh_num_read_bytes 7 +#define dlh_num_data_bytes 3 +#define dlh_num_pr_bits 24 +#define dlh_num_temp_bits 24 + +/* dlh timings */ +#define dlh_single_dut_ms 5 + +enum dhl_ids { + dlhl60d, + dlhl60g, +}; + +struct dlh_info { + u8 osdig; /* digital offset factor */ + unsigned int fss; /* full scale span (inch h2o) */ +}; + +struct dlh_state { + struct i2c_client *client; + struct dlh_info info; + bool use_interrupt; + struct completion completion; + u8 rx_buf[dlh_num_read_bytes] ____cacheline_aligned; +}; + +static struct dlh_info dlh_info_tbl[] = { + [dlhl60d] = { + .osdig = 2, + .fss = 120, + }, + [dlhl60g] = { + .osdig = 10, + .fss = 60, + }, +}; + + +static int dlh_cmd_start_single(struct dlh_state *st) +{ + int ret; + + ret = i2c_smbus_write_byte(st->client, dlh_start_single); + if (ret) + dev_err(&st->client->dev, + "%s: i2c write byte failed ", __func__); + + return ret; +} + +static int dlh_cmd_read_data(struct dlh_state *st) +{ + int ret; + + ret = i2c_master_recv(st->client, st->rx_buf, dlh_num_read_bytes); + if (ret < 0) { + dev_err(&st->client->dev, + "%s: i2c read block failed ", __func__); + return ret; + } + + if (st->rx_buf[0] != dlh_status_ok) { + dev_err(&st->client->dev, + "%s: invalid status 0x%02x ", __func__, st->rx_buf[0]); + return -ebusy; + } + + return 0; +} + +static int dlh_start_capture_and_read(struct dlh_state *st) +{ + int ret; + + if (st->use_interrupt) + reinit_completion(&st->completion); + + ret = dlh_cmd_start_single(st); + if (ret) + return ret; + + if (st->use_interrupt) { + ret = wait_for_completion_timeout(&st->completion, + msecs_to_jiffies(dlh_single_dut_ms)); + if (!ret) { + dev_err(&st->client->dev, + "%s: conversion timed out ", __func__); + return -etimedout; + } + } else { + mdelay(dlh_single_dut_ms); + } + + return dlh_cmd_read_data(st); +} + +static int dlh_read_direct(struct dlh_state *st, + unsigned int *pressure, unsigned int *temperature) +{ + int ret; + + ret = dlh_start_capture_and_read(st); + if (ret) + return ret; + + *pressure = get_unaligned_be32(&st->rx_buf[1]) >> 8; + *temperature = get_unaligned_be32(&st->rx_buf[3]) & + genmask(dlh_num_temp_bits - 1, 0); + + return 0; +} + +static int dlh_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *channel, int *value, + int *value2, long mask) +{ + struct dlh_state *st = iio_priv(indio_dev); + unsigned int pressure, temperature; + int ret; + s64 tmp; + s32 rem; + + switch (mask) { + case iio_chan_info_raw: + ret = iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + ret = dlh_read_direct(st, &pressure, &temperature); + iio_device_release_direct_mode(indio_dev); + if (ret) + return ret; + + switch (channel->type) { + case iio_pressure: + *value = pressure; + return iio_val_int; + + case iio_temp: + *value = temperature; + return iio_val_int; + + default: + return -einval; + } + case iio_chan_info_scale: + switch (channel->type) { + case iio_pressure: + tmp = div_s64(125ll * st->info.fss * 24909 * 100, + 1 << dlh_num_pr_bits); + tmp = div_s64_rem(tmp, 1000000000ll, &rem); + *value = tmp; + *value2 = rem; + return iio_val_int_plus_nano; + + case iio_temp: + *value = 125 * 1000; + *value2 = dlh_num_temp_bits; + return iio_val_fractional_log2; + + default: + return -einval; + } + case iio_chan_info_offset: + switch (channel->type) { + case iio_pressure: + *value = -125 * st->info.fss * 24909; + *value2 = 100 * st->info.osdig * 100000; + return iio_val_fractional; + + case iio_temp: + *value = -40 * 1000; + return iio_val_int; + + default: + return -einval; + } + } + + return -einval; +} + +static const struct iio_info dlh_info = { + .read_raw = dlh_read_raw, +}; + +static const struct iio_chan_spec dlh_channels[] = { + { + .type = iio_pressure, + .indexed = 1, + .info_mask_separate = bit(iio_chan_info_raw), + .info_mask_shared_by_type = + bit(iio_chan_info_scale) | + bit(iio_chan_info_offset), + .scan_index = 0, + .scan_type = { + .sign = 'u', + .realbits = dlh_num_pr_bits, + .storagebits = 32, + .shift = 8, + .endianness = iio_be, + }, + }, { + .type = iio_temp, + .indexed = 1, + .info_mask_separate = bit(iio_chan_info_raw), + .info_mask_shared_by_type = + bit(iio_chan_info_scale) | + bit(iio_chan_info_offset), + .scan_index = 1, + .scan_type = { + .sign = 'u', + .realbits = dlh_num_temp_bits, + .storagebits = 32, + .shift = 8, + .endianness = iio_be, + }, + } +}; + +static irqreturn_t dlh_trigger_handler(int irq, void *private) +{ + struct iio_poll_func *pf = private; + struct iio_dev *indio_dev = pf->indio_dev; + struct dlh_state *st = iio_priv(indio_dev); + int ret; + unsigned int chn, i = 0; + __be32 tmp_buf[2]; + + ret = dlh_start_capture_and_read(st); + if (ret) + goto out; + + for_each_set_bit(chn, indio_dev->active_scan_mask, + indio_dev->masklength) { + memcpy(tmp_buf + i, + &st->rx_buf[1] + chn * dlh_num_data_bytes, + dlh_num_data_bytes); + i++; + } + + iio_push_to_buffers(indio_dev, tmp_buf); + +out: + iio_trigger_notify_done(indio_dev->trig); + + return irq_handled; +} + +static irqreturn_t dlh_interrupt(int irq, void *private) +{ + struct iio_dev *indio_dev = private; + struct dlh_state *st = iio_priv(indio_dev); + + complete(&st->completion); + + return irq_handled; +}; + +static int dlh_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct dlh_state *st; + struct iio_dev *indio_dev; + int ret; + + if (!i2c_check_functionality(client->adapter, + i2c_func_i2c | i2c_func_smbus_write_byte)) { + dev_err(&client->dev, + "adapter doesn't support required i2c functionality "); + return -eopnotsupp; + } + + indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st)); + if (!indio_dev) { + dev_err(&client->dev, "failed to allocate iio device "); + return -enomem; + } + + i2c_set_clientdata(client, indio_dev); + + st = iio_priv(indio_dev); + st->info = dlh_info_tbl[id->driver_data]; + st->client = client; + st->use_interrupt = false; + + indio_dev->name = id->name; + indio_dev->dev.parent = &client->dev; + indio_dev->dev.of_node = client->dev.of_node; + indio_dev->info = &dlh_info; + indio_dev->modes = indio_direct_mode; + indio_dev->channels = dlh_channels; + indio_dev->num_channels = array_size(dlh_channels); + + if (client->irq > 0) { + ret = devm_request_threaded_irq(&client->dev, client->irq, + dlh_interrupt, null, + irqf_trigger_rising | irqf_oneshot, + id->name, indio_dev); + if (ret) { + dev_err(&client->dev, "failed to allocate threaded irq"); + return ret; + } + + st->use_interrupt = true; + init_completion(&st->completion); + } + + ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, + null, &dlh_trigger_handler, null); + if (ret) { + dev_err(&client->dev, "failed to setup iio buffer "); + return ret; + } + + ret = devm_iio_device_register(&client->dev, indio_dev); + if (ret) + dev_err(&client->dev, "failed to register iio device "); + + return ret; +} + +static const struct of_device_id dlh_of_match[] = { + { .compatible = "asc,dlhl60d" }, + { .compatible = "asc,dlhl60g" }, + {} +}; +module_device_table(of, dlh_of_match); + +static const struct i2c_device_id dlh_id[] = { + { "dlhl60d", dlhl60d }, + { "dlhl60g", dlhl60g }, + {} +}; +module_device_table(i2c, dlh_id); + +static struct i2c_driver dlh_driver = { + .driver = { + .name = "dlhl60d", + .of_match_table = dlh_of_match, + }, + .probe = dlh_probe, + .id_table = dlh_id, +}; +module_i2c_driver(dlh_driver); + +module_author("tomislav denis <tomislav.denis@avl.com>"); +module_description("driver for all sensors dlh series pressure sensors"); +module_license("gpl v2");
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Industrial I/O (iio)
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ac78c6aa4a5dcb1a28eb212fd39d362371b36b06
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tomislav denis
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drivers
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iio
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pressure
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mfd: ab8500-core: add device tree support for ab8505
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ab8505 support was never fully converted to the device tree. most of the mfd cells for ab8505 lack an "of_compatible", which prevents them from being configured through the device tree.
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this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add device tree support for ab8505
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['ab8500-core']
|
['c']
| 2
| 32
| 8
|
--- diff --git a/drivers/mfd/ab8500-core.c b/drivers/mfd/ab8500-core.c --- a/drivers/mfd/ab8500-core.c +++ b/drivers/mfd/ab8500-core.c + .of_compatible = "stericsson,ab8500-debug", + .of_compatible = "stericsson,ab8500-sysctrl", + .of_compatible = "stericsson,ab8505-regulator", - .of_compatible = "stericsson,abx500-clk", + .of_compatible = "stericsson,ab8500-clk", + .of_compatible = "stericsson,ab8500-rtc", + .of_compatible = "stericsson,ab8500-acc-det", + .of_compatible = "stericsson,ab8500-poweron-key", + .of_compatible = "stericsson,ab8500-pwm", + .of_compatible = "stericsson,ab8505-gpio", + .of_compatible = "stericsson,ab8500-usb", + .of_compatible = "stericsson,ab8500-codec", - { "ab8505-i2c", ab8500_version_ab8505 }, + { "ab8505-core", ab8500_version_ab8505 }, diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c --- a/drivers/mfd/db8500-prcmu.c +++ b/drivers/mfd/db8500-prcmu.c - struct resource ab8500_resource; + struct resource ab850x_resource; - .resources = &ab8500_resource, + .resources = &ab850x_resource, + const struct mfd_cell ab8505_cell = { + .name = "ab8505-core", + .of_compatible = "stericsson,ab8505", + .id = ab8500_version_ab8505, + .resources = &ab850x_resource, + .num_resources = 1, + }; + const struct mfd_cell *ab850x_cell; - if (of_device_is_compatible(np, ab8500_cell.of_compatible)) + if (of_device_is_compatible(np, ab8500_cell.of_compatible)) { + ab850x_cell = &ab8500_cell; + } + if (of_device_is_compatible(np, ab8505_cell.of_compatible)) { + ab850x_cell = &ab8505_cell; + break; + } - dev_info(parent, "could not find ab8500 node in the device tree "); + dev_info(parent, "could not find ab850x node in the device tree "); - of_irq_to_resource_table(np, &ab8500_resource, 1); + of_irq_to_resource_table(np, &ab850x_resource, 1); - return mfd_add_devices(parent, 0, &ab8500_cell, 1, null, 0, null); + return mfd_add_devices(parent, 0, ab850x_cell, 1, null, 0, null);
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Multi Function Devices (MFD)
|
1c0769d2093518b192a36eebab9134d597d4bc02
|
stephan gerhold
|
drivers
|
mfd
| |
mfd: bd71828: add power-key support
|
use gpio_keys to send power input-event to user-space when power button (short) press is detected.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add power-key support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['bd71828']
|
['c']
| 1
| 26
| 0
|
--- diff --git a/drivers/mfd/rohm-bd71828.c b/drivers/mfd/rohm-bd71828.c --- a/drivers/mfd/rohm-bd71828.c +++ b/drivers/mfd/rohm-bd71828.c +#include <linux/gpio_keys.h> +#include <linux/input.h> +static struct gpio_keys_button button = { + .code = key_power, + .gpio = -1, + .type = ev_key, +}; + +static struct gpio_keys_platform_data bd71828_powerkey_data = { + .buttons = &button, + .nbuttons = 1, + .name = "bd71828-pwrkey", +}; + + }, { + .name = "gpio-keys", + .platform_data = &bd71828_powerkey_data, + .pdata_size = sizeof(bd71828_powerkey_data), + ret = regmap_irq_get_virq(irq_data, bd71828_int_shortpush); + if (ret < 0) { + dev_err(&i2c->dev, "failed to get the power-key irq "); + return ret; + } + + button.irq = ret; +
|
Multi Function Devices (MFD)
|
e795bf725dabc918298e74cb29303ea6783f1874
|
matti vaittinen
|
drivers
|
mfd
| |
mfd: bd71828: support rohm bd71828 pmic - core
|
bd71828gw is a single-chip power management ic for battery-powered portable devices. the ic integrates 7 buck converters, 7 ldos, and a 1500 ma single-cell linear charger. also included is a coulomb counter, a real-time clock (rtc), 3 gpo/regulator control pins, hall input and a 32.768 khz clock gate.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
support rohm bd71828 pmic - core
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['bd71828']
|
['c', 'kconfig', 'makefile', 'h']
| 5
| 760
| 0
|
--- diff --git a/drivers/mfd/kconfig b/drivers/mfd/kconfig --- a/drivers/mfd/kconfig +++ b/drivers/mfd/kconfig +config mfd_rohm_bd71828 + tristate "rohm bd71828 power management ic" + depends on i2c=y + depends on of + select regmap_i2c + select regmap_irq + select mfd_core + help + select this option to get support for the rohm bd71828 power + management ic. bd71828gw is a single-chip power management ic for + battery-powered portable devices. the ic integrates 7 buck + converters, 7 ldos, and a 1500 ma single-cell linear charger. + also included is a coulomb counter, a real-time clock (rtc), and + a 32.768 khz clock gate. + diff --git a/drivers/mfd/makefile b/drivers/mfd/makefile --- a/drivers/mfd/makefile +++ b/drivers/mfd/makefile +obj-$(config_mfd_rohm_bd71828) += rohm-bd71828.o diff --git a/drivers/mfd/rohm-bd71828.c b/drivers/mfd/rohm-bd71828.c --- /dev/null +++ b/drivers/mfd/rohm-bd71828.c +// spdx-license-identifier: gpl-2.0-only +// +// copyright (c) 2019 rohm semiconductors +// +// rohm bd71828 pmic driver + +#include <linux/i2c.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/irq.h> +#include <linux/mfd/core.h> +#include <linux/mfd/rohm-bd71828.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regmap.h> +#include <linux/types.h> + +static const struct resource rtc_irqs[] = { + define_res_irq_named(bd71828_int_rtc0, "bd71828-rtc-alm-0"), + define_res_irq_named(bd71828_int_rtc1, "bd71828-rtc-alm-1"), + define_res_irq_named(bd71828_int_rtc2, "bd71828-rtc-alm-2"), +}; + +static struct mfd_cell bd71828_mfd_cells[] = { + { .name = "bd71828-pmic", }, + { .name = "bd71828-gpio", }, + { .name = "bd71828-led", .of_compatible = "rohm,bd71828-leds" }, + /* + * we use bd71837 driver to drive the clock block. only differences to + * bd70528 clock gate are the register address and mask. + */ + { .name = "bd71828-clk", }, + { .name = "bd71827-power", }, + { + .name = "bd71828-rtc", + .resources = rtc_irqs, + .num_resources = array_size(rtc_irqs), + }, +}; + +static const struct regmap_range volatile_ranges[] = { + { + .range_min = bd71828_reg_ps_ctrl_1, + .range_max = bd71828_reg_ps_ctrl_1, + }, { + .range_min = bd71828_reg_ps_ctrl_3, + .range_max = bd71828_reg_ps_ctrl_3, + }, { + .range_min = bd71828_reg_rtc_sec, + .range_max = bd71828_reg_rtc_year, + }, { + /* + * for now make all charger registers volatile because many + * needs to be and because the charger block is not that + * performance critical. + */ + .range_min = bd71828_reg_chg_state, + .range_max = bd71828_reg_chg_full, + }, { + .range_min = bd71828_reg_int_main, + .range_max = bd71828_reg_io_stat, + }, +}; + +static const struct regmap_access_table volatile_regs = { + .yes_ranges = &volatile_ranges[0], + .n_yes_ranges = array_size(volatile_ranges), +}; + +static struct regmap_config bd71828_regmap = { + .reg_bits = 8, + .val_bits = 8, + .volatile_table = &volatile_regs, + .max_register = bd71828_max_register, + .cache_type = regcache_rbtree, +}; + +/* + * mapping of main irq register bits to sub-irq register offsets so that we can + * access corect sub-irq registers based on bits that are set in main irq + * register. + */ + +static unsigned int bit0_offsets[] = {11}; /* rtc irq */ +static unsigned int bit1_offsets[] = {10}; /* temp irq */ +static unsigned int bit2_offsets[] = {6, 7, 8, 9}; /* bat mon irq */ +static unsigned int bit3_offsets[] = {5}; /* bat irq */ +static unsigned int bit4_offsets[] = {4}; /* chg irq */ +static unsigned int bit5_offsets[] = {3}; /* vsys irq */ +static unsigned int bit6_offsets[] = {1, 2}; /* dcin irq */ +static unsigned int bit7_offsets[] = {0}; /* buck irq */ + +static struct regmap_irq_sub_irq_map bd71828_sub_irq_offsets[] = { + regmap_irq_main_reg_offset(bit0_offsets), + regmap_irq_main_reg_offset(bit1_offsets), + regmap_irq_main_reg_offset(bit2_offsets), + regmap_irq_main_reg_offset(bit3_offsets), + regmap_irq_main_reg_offset(bit4_offsets), + regmap_irq_main_reg_offset(bit5_offsets), + regmap_irq_main_reg_offset(bit6_offsets), + regmap_irq_main_reg_offset(bit7_offsets), +}; + +static struct regmap_irq bd71828_irqs[] = { + regmap_irq_reg(bd71828_int_buck1_ocp, 0, bd71828_int_buck1_ocp_mask), + regmap_irq_reg(bd71828_int_buck2_ocp, 0, bd71828_int_buck2_ocp_mask), + regmap_irq_reg(bd71828_int_buck3_ocp, 0, bd71828_int_buck3_ocp_mask), + regmap_irq_reg(bd71828_int_buck4_ocp, 0, bd71828_int_buck4_ocp_mask), + regmap_irq_reg(bd71828_int_buck5_ocp, 0, bd71828_int_buck5_ocp_mask), + regmap_irq_reg(bd71828_int_buck6_ocp, 0, bd71828_int_buck6_ocp_mask), + regmap_irq_reg(bd71828_int_buck7_ocp, 0, bd71828_int_buck7_ocp_mask), + regmap_irq_reg(bd71828_int_pgfault, 0, bd71828_int_pgfault_mask), + /* dcin1 interrupts */ + regmap_irq_reg(bd71828_int_dcin_det, 1, bd71828_int_dcin_det_mask), + regmap_irq_reg(bd71828_int_dcin_rmv, 1, bd71828_int_dcin_rmv_mask), + regmap_irq_reg(bd71828_int_clps_out, 1, bd71828_int_clps_out_mask), + regmap_irq_reg(bd71828_int_clps_in, 1, bd71828_int_clps_in_mask), + /* dcin2 interrupts */ + regmap_irq_reg(bd71828_int_dcin_mon_res, 2, + bd71828_int_dcin_mon_res_mask), + regmap_irq_reg(bd71828_int_dcin_mon_det, 2, + bd71828_int_dcin_mon_det_mask), + regmap_irq_reg(bd71828_int_longpush, 2, bd71828_int_longpush_mask), + regmap_irq_reg(bd71828_int_midpush, 2, bd71828_int_midpush_mask), + regmap_irq_reg(bd71828_int_shortpush, 2, bd71828_int_shortpush_mask), + regmap_irq_reg(bd71828_int_push, 2, bd71828_int_push_mask), + regmap_irq_reg(bd71828_int_wdog, 2, bd71828_int_wdog_mask), + regmap_irq_reg(bd71828_int_swreset, 2, bd71828_int_swreset_mask), + /* vsys */ + regmap_irq_reg(bd71828_int_vsys_uv_res, 3, + bd71828_int_vsys_uv_res_mask), + regmap_irq_reg(bd71828_int_vsys_uv_det, 3, + bd71828_int_vsys_uv_det_mask), + regmap_irq_reg(bd71828_int_vsys_low_res, 3, + bd71828_int_vsys_low_res_mask), + regmap_irq_reg(bd71828_int_vsys_low_det, 3, + bd71828_int_vsys_low_det_mask), + regmap_irq_reg(bd71828_int_vsys_hall_in, 3, + bd71828_int_vsys_hall_in_mask), + regmap_irq_reg(bd71828_int_vsys_hall_toggle, 3, + bd71828_int_vsys_hall_toggle_mask), + regmap_irq_reg(bd71828_int_vsys_mon_res, 3, + bd71828_int_vsys_mon_res_mask), + regmap_irq_reg(bd71828_int_vsys_mon_det, 3, + bd71828_int_vsys_mon_det_mask), + /* charger */ + regmap_irq_reg(bd71828_int_chg_dcin_ilim, 4, + bd71828_int_chg_dcin_ilim_mask), + regmap_irq_reg(bd71828_int_chg_topoff_to_done, 4, + bd71828_int_chg_topoff_to_done_mask), + regmap_irq_reg(bd71828_int_chg_wdg_temp, 4, + bd71828_int_chg_wdg_temp_mask), + regmap_irq_reg(bd71828_int_chg_wdg_time, 4, + bd71828_int_chg_wdg_time_mask), + regmap_irq_reg(bd71828_int_chg_recharge_res, 4, + bd71828_int_chg_recharge_res_mask), + regmap_irq_reg(bd71828_int_chg_recharge_det, 4, + bd71828_int_chg_recharge_det_mask), + regmap_irq_reg(bd71828_int_chg_ranged_temp_transition, 4, + bd71828_int_chg_ranged_temp_transition_mask), + regmap_irq_reg(bd71828_int_chg_state_transition, 4, + bd71828_int_chg_state_transition_mask), + /* battery */ + regmap_irq_reg(bd71828_int_bat_temp_normal, 5, + bd71828_int_bat_temp_normal_mask), + regmap_irq_reg(bd71828_int_bat_temp_erange, 5, + bd71828_int_bat_temp_erange_mask), + regmap_irq_reg(bd71828_int_bat_temp_warn, 5, + bd71828_int_bat_temp_warn_mask), + regmap_irq_reg(bd71828_int_bat_removed, 5, + bd71828_int_bat_removed_mask), + regmap_irq_reg(bd71828_int_bat_detected, 5, + bd71828_int_bat_detected_mask), + regmap_irq_reg(bd71828_int_therm_removed, 5, + bd71828_int_therm_removed_mask), + regmap_irq_reg(bd71828_int_therm_detected, 5, + bd71828_int_therm_detected_mask), + /* battery mon 1 */ + regmap_irq_reg(bd71828_int_bat_dead, 6, bd71828_int_bat_dead_mask), + regmap_irq_reg(bd71828_int_bat_shortc_res, 6, + bd71828_int_bat_shortc_res_mask), + regmap_irq_reg(bd71828_int_bat_shortc_det, 6, + bd71828_int_bat_shortc_det_mask), + regmap_irq_reg(bd71828_int_bat_low_volt_res, 6, + bd71828_int_bat_low_volt_res_mask), + regmap_irq_reg(bd71828_int_bat_low_volt_det, 6, + bd71828_int_bat_low_volt_det_mask), + regmap_irq_reg(bd71828_int_bat_over_volt_res, 6, + bd71828_int_bat_over_volt_res_mask), + regmap_irq_reg(bd71828_int_bat_over_volt_det, 6, + bd71828_int_bat_over_volt_det_mask), + /* battery mon 2 */ + regmap_irq_reg(bd71828_int_bat_mon_res, 7, + bd71828_int_bat_mon_res_mask), + regmap_irq_reg(bd71828_int_bat_mon_det, 7, + bd71828_int_bat_mon_det_mask), + /* battery mon 3 (coulomb counter) */ + regmap_irq_reg(bd71828_int_bat_cc_mon1, 8, + bd71828_int_bat_cc_mon1_mask), + regmap_irq_reg(bd71828_int_bat_cc_mon2, 8, + bd71828_int_bat_cc_mon2_mask), + regmap_irq_reg(bd71828_int_bat_cc_mon3, 8, + bd71828_int_bat_cc_mon3_mask), + /* battery mon 4 */ + regmap_irq_reg(bd71828_int_bat_over_curr_1_res, 9, + bd71828_int_bat_over_curr_1_res_mask), + regmap_irq_reg(bd71828_int_bat_over_curr_1_det, 9, + bd71828_int_bat_over_curr_1_det_mask), + regmap_irq_reg(bd71828_int_bat_over_curr_2_res, 9, + bd71828_int_bat_over_curr_2_res_mask), + regmap_irq_reg(bd71828_int_bat_over_curr_2_det, 9, + bd71828_int_bat_over_curr_2_det_mask), + regmap_irq_reg(bd71828_int_bat_over_curr_3_res, 9, + bd71828_int_bat_over_curr_3_res_mask), + regmap_irq_reg(bd71828_int_bat_over_curr_3_det, 9, + bd71828_int_bat_over_curr_3_det_mask), + /* temperature */ + regmap_irq_reg(bd71828_int_temp_bat_low_res, 10, + bd71828_int_temp_bat_low_res_mask), + regmap_irq_reg(bd71828_int_temp_bat_low_det, 10, + bd71828_int_temp_bat_low_det_mask), + regmap_irq_reg(bd71828_int_temp_bat_hi_res, 10, + bd71828_int_temp_bat_hi_res_mask), + regmap_irq_reg(bd71828_int_temp_bat_hi_det, 10, + bd71828_int_temp_bat_hi_det_mask), + regmap_irq_reg(bd71828_int_temp_chip_over_125_res, 10, + bd71828_int_temp_chip_over_125_res_mask), + regmap_irq_reg(bd71828_int_temp_chip_over_125_det, 10, + bd71828_int_temp_chip_over_125_det_mask), + regmap_irq_reg(bd71828_int_temp_chip_over_vf_det, 10, + bd71828_int_temp_chip_over_vf_det_mask), + regmap_irq_reg(bd71828_int_temp_chip_over_vf_res, 10, + bd71828_int_temp_chip_over_vf_res_mask), + /* rtc alarm */ + regmap_irq_reg(bd71828_int_rtc0, 11, bd71828_int_rtc0_mask), + regmap_irq_reg(bd71828_int_rtc1, 11, bd71828_int_rtc1_mask), + regmap_irq_reg(bd71828_int_rtc2, 11, bd71828_int_rtc2_mask), +}; + +static struct regmap_irq_chip bd71828_irq_chip = { + .name = "bd71828_irq", + .main_status = bd71828_reg_int_main, + .irqs = &bd71828_irqs[0], + .num_irqs = array_size(bd71828_irqs), + .status_base = bd71828_reg_int_buck, + .mask_base = bd71828_reg_int_mask_buck, + .ack_base = bd71828_reg_int_buck, + .mask_invert = true, + .init_ack_masked = true, + .num_regs = 12, + .num_main_regs = 1, + .sub_reg_offsets = &bd71828_sub_irq_offsets[0], + .num_main_status_bits = 8, + .irq_reg_stride = 1, +}; + +static int bd71828_i2c_probe(struct i2c_client *i2c) +{ + struct rohm_regmap_dev *chip; + struct regmap_irq_chip_data *irq_data; + int ret; + + if (!i2c->irq) { + dev_err(&i2c->dev, "no irq configured "); + return -einval; + } + + chip = devm_kzalloc(&i2c->dev, sizeof(*chip), gfp_kernel); + if (!chip) + return -enomem; + + dev_set_drvdata(&i2c->dev, chip); + + chip->regmap = devm_regmap_init_i2c(i2c, &bd71828_regmap); + if (is_err(chip->regmap)) { + dev_err(&i2c->dev, "failed to initialize regmap "); + return ptr_err(chip->regmap); + } + + ret = devm_regmap_add_irq_chip(&i2c->dev, chip->regmap, + i2c->irq, irqf_oneshot, 0, + &bd71828_irq_chip, &irq_data); + if (ret) { + dev_err(&i2c->dev, "failed to add irq chip "); + return ret; + } + + dev_dbg(&i2c->dev, "registered %d irqs for chip ", + bd71828_irq_chip.num_irqs); + + ret = devm_mfd_add_devices(&i2c->dev, platform_devid_auto, + bd71828_mfd_cells, + array_size(bd71828_mfd_cells), null, 0, + regmap_irq_get_domain(irq_data)); + if (ret) + dev_err(&i2c->dev, "failed to create subdevices "); + + return ret; +} + +static const struct of_device_id bd71828_of_match[] = { + { .compatible = "rohm,bd71828", }, + { }, +}; +module_device_table(of, bd71828_of_match); + +static struct i2c_driver bd71828_drv = { + .driver = { + .name = "rohm-bd71828", + .of_match_table = bd71828_of_match, + }, + .probe_new = &bd71828_i2c_probe, +}; +module_i2c_driver(bd71828_drv); + +module_author("matti vaittinen <matti.vaittinen@fi.rohmeurope.com>"); +module_description("rohm bd71828 power management ic driver"); +module_license("gpl"); diff --git a/include/linux/mfd/rohm-bd71828.h b/include/linux/mfd/rohm-bd71828.h --- /dev/null +++ b/include/linux/mfd/rohm-bd71828.h +/* spdx-license-identifier: gpl-2.0-or-later */ +/* copyright (c) 2019 rohm semiconductors */ + +#ifndef __linux_mfd_bd71828_h__ +#define __linux_mfd_bd71828_h__ + +#include <linux/mfd/rohm-generic.h> + +/* regulator ids */ +enum { + bd71828_buck1, + bd71828_buck2, + bd71828_buck3, + bd71828_buck4, + bd71828_buck5, + bd71828_buck6, + bd71828_buck7, + bd71828_ldo1, + bd71828_ldo2, + bd71828_ldo3, + bd71828_ldo4, + bd71828_ldo5, + bd71828_ldo6, + bd71828_ldo_snvs, + bd71828_regulator_amount, +}; + +#define bd71828_buck1267_volts 0xef +#define bd71828_buck3_volts 0x10 +#define bd71828_buck4_volts 0x20 +#define bd71828_buck5_volts 0x10 +#define bd71828_ldo_volts 0x32 +/* ldo6 is fixed 1.8v voltage */ +#define bd71828_ldo_6_voltage 1800000 + +/* registers and masks*/ + +/* mode control */ +#define bd71828_reg_ps_ctrl_1 0x04 +#define bd71828_reg_ps_ctrl_2 0x05 +#define bd71828_reg_ps_ctrl_3 0x06 + +//#define bd71828_reg_swreset 0x06 +#define bd71828_mask_run_lvl_ctrl 0x30 + +/* regulator control masks */ + +#define bd71828_mask_ramp_delay 0x6 + +#define bd71828_mask_run_en 0x08 +#define bd71828_mask_susp_en 0x04 +#define bd71828_mask_idle_en 0x02 +#define bd71828_mask_lpsr_en 0x01 + +#define bd71828_mask_run0_en 0x01 +#define bd71828_mask_run1_en 0x02 +#define bd71828_mask_run2_en 0x04 +#define bd71828_mask_run3_en 0x08 + +#define bd71828_mask_dvs_buck1_ctrl 0x10 +#define bd71828_dvs_buck1_ctrl_i2c 0 +#define bd71828_dvs_buck1_use_runlvl 0x10 + +#define bd71828_mask_dvs_buck2_ctrl 0x20 +#define bd71828_dvs_buck2_ctrl_i2c 0 +#define bd71828_dvs_buck2_use_runlvl 0x20 + +#define bd71828_mask_dvs_buck6_ctrl 0x40 +#define bd71828_dvs_buck6_ctrl_i2c 0 +#define bd71828_dvs_buck6_use_runlvl 0x40 + +#define bd71828_mask_dvs_buck7_ctrl 0x80 +#define bd71828_dvs_buck7_ctrl_i2c 0 +#define bd71828_dvs_buck7_use_runlvl 0x80 + +#define bd71828_mask_buck1267_volt 0xff +#define bd71828_mask_buck3_volt 0x1f +#define bd71828_mask_buck4_volt 0x3f +#define bd71828_mask_buck5_volt 0x1f +#define bd71828_mask_ldo_volt 0x3f + +/* regulator control regs */ +#define bd71828_reg_buck1_en 0x08 +#define bd71828_reg_buck1_ctrl 0x09 +#define bd71828_reg_buck1_mode 0x0a +#define bd71828_reg_buck1_idle_volt 0x0b +#define bd71828_reg_buck1_susp_volt 0x0c +#define bd71828_reg_buck1_volt 0x0d + +#define bd71828_reg_buck2_en 0x12 +#define bd71828_reg_buck2_ctrl 0x13 +#define bd71828_reg_buck2_mode 0x14 +#define bd71828_reg_buck2_idle_volt 0x15 +#define bd71828_reg_buck2_susp_volt 0x16 +#define bd71828_reg_buck2_volt 0x17 + +#define bd71828_reg_buck3_en 0x1c +#define bd71828_reg_buck3_mode 0x1d +#define bd71828_reg_buck3_volt 0x1e + +#define bd71828_reg_buck4_en 0x1f +#define bd71828_reg_buck4_mode 0x20 +#define bd71828_reg_buck4_volt 0x21 + +#define bd71828_reg_buck5_en 0x22 +#define bd71828_reg_buck5_mode 0x23 +#define bd71828_reg_buck5_volt 0x24 + +#define bd71828_reg_buck6_en 0x25 +#define bd71828_reg_buck6_ctrl 0x26 +#define bd71828_reg_buck6_mode 0x27 +#define bd71828_reg_buck6_idle_volt 0x28 +#define bd71828_reg_buck6_susp_volt 0x29 +#define bd71828_reg_buck6_volt 0x2a + +#define bd71828_reg_buck7_en 0x2f +#define bd71828_reg_buck7_ctrl 0x30 +#define bd71828_reg_buck7_mode 0x31 +#define bd71828_reg_buck7_idle_volt 0x32 +#define bd71828_reg_buck7_susp_volt 0x33 +#define bd71828_reg_buck7_volt 0x34 + +#define bd71828_reg_ldo1_en 0x39 +#define bd71828_reg_ldo1_volt 0x3a +#define bd71828_reg_ldo2_en 0x3b +#define bd71828_reg_ldo2_volt 0x3c +#define bd71828_reg_ldo3_en 0x3d +#define bd71828_reg_ldo3_volt 0x3e +#define bd71828_reg_ldo4_en 0x3f +#define bd71828_reg_ldo4_volt 0x40 +#define bd71828_reg_ldo5_en 0x41 +#define bd71828_reg_ldo5_volt 0x43 +#define bd71828_reg_ldo5_volt_opt 0x42 +#define bd71828_reg_ldo6_en 0x44 +//#define bd71828_reg_ldo6_volt 0x4 +#define bd71828_reg_ldo7_en 0x45 +#define bd71828_reg_ldo7_volt 0x46 + +/* gpio */ + +#define bd71828_gpio_drive_mask 0x2 +#define bd71828_gpio_open_drain 0x0 +#define bd71828_gpio_push_pull 0x2 +#define bd71828_gpio_out_hi 0x1 +#define bd71828_gpio_out_lo 0x0 +#define bd71828_gpio_out_mask 0x1 + +#define bd71828_reg_gpio_ctrl1 0x47 +#define bd71828_reg_gpio_ctrl2 0x48 +#define bd71828_reg_gpio_ctrl3 0x49 +#define bd71828_reg_io_stat 0xed + +/* rtc */ +#define bd71828_reg_rtc_sec 0x4c +#define bd71828_reg_rtc_minute 0x4d +#define bd71828_reg_rtc_hour 0x4e +#define bd71828_reg_rtc_week 0x4f +#define bd71828_reg_rtc_day 0x50 +#define bd71828_reg_rtc_month 0x51 +#define bd71828_reg_rtc_year 0x52 + +#define bd71828_reg_rtc_alm0_sec 0x53 +#define bd71828_reg_rtc_alm0_minute 0x54 +#define bd71828_reg_rtc_alm0_hour 0x55 +#define bd71828_reg_rtc_alm0_week 0x56 +#define bd71828_reg_rtc_alm0_day 0x57 +#define bd71828_reg_rtc_alm0_month 0x58 +#define bd71828_reg_rtc_alm0_year 0x59 +#define bd71828_reg_rtc_alm0_mask 0x61 + +#define bd71828_reg_rtc_alm1_sec 0x5a +#define bd71828_reg_rtc_alm1_minute 0x5b +#define bd71828_reg_rtc_alm1_hour 0x5c +#define bd71828_reg_rtc_alm1_week 0x5d +#define bd71828_reg_rtc_alm1_day 0x5e +#define bd71828_reg_rtc_alm1_month 0x5f +#define bd71828_reg_rtc_alm1_year 0x60 +#define bd71828_reg_rtc_alm1_mask 0x62 + +#define bd71828_reg_rtc_alm2 0x63 + +/* charger/battey */ +#define bd71828_reg_chg_state 0x65 +#define bd71828_reg_chg_full 0xd2 + +/* clk */ +#define bd71828_reg_out32k 0x4b + +/* leds */ +#define bd71828_reg_led_ctrl 0x4a +#define bd71828_mask_led_amber 0x80 +#define bd71828_mask_led_green 0x40 +#define bd71828_led_on 0xff +#define bd71828_led_off 0x0 + +/* irq registers */ +#define bd71828_reg_int_mask_buck 0xd3 +#define bd71828_reg_int_mask_dcin1 0xd4 +#define bd71828_reg_int_mask_dcin2 0xd5 +#define bd71828_reg_int_mask_vsys 0xd6 +#define bd71828_reg_int_mask_chg 0xd7 +#define bd71828_reg_int_mask_bat 0xd8 +#define bd71828_reg_int_mask_bat_mon1 0xd9 +#define bd71828_reg_int_mask_bat_mon2 0xda +#define bd71828_reg_int_mask_bat_mon3 0xdb +#define bd71828_reg_int_mask_bat_mon4 0xdc +#define bd71828_reg_int_mask_temp 0xdd +#define bd71828_reg_int_mask_rtc 0xde + + +#define bd71828_reg_int_main 0xdf +#define bd71828_reg_int_buck 0xe0 +#define bd71828_reg_int_dcin1 0xe1 +#define bd71828_reg_int_dcin2 0xe2 +#define bd71828_reg_int_vsys 0xe3 +#define bd71828_reg_int_chg 0xe4 +#define bd71828_reg_int_bat 0xe5 +#define bd71828_reg_int_bat_mon1 0xe6 +#define bd71828_reg_int_bat_mon2 0xe7 +#define bd71828_reg_int_bat_mon3 0xe8 +#define bd71828_reg_int_bat_mon4 0xe9 +#define bd71828_reg_int_temp 0xea +#define bd71828_reg_int_rtc 0xeb +#define bd71828_reg_int_update 0xec + +#define bd71828_max_register bd71828_reg_io_stat + +/* masks for main irq register bits */ +enum { + bd71828_int_buck, +#define bd71828_int_buck_mask bit(bd71828_int_buck) + bd71828_int_dcin, +#define bd71828_int_dcin_mask bit(bd71828_int_dcin) + bd71828_int_vsys, +#define bd71828_int_vsys_mask bit(bd71828_int_vsys) + bd71828_int_chg, +#define bd71828_int_chg_mask bit(bd71828_int_chg) + bd71828_int_bat, +#define bd71828_int_bat_mask bit(bd71828_int_bat) + bd71828_int_bat_mon, +#define bd71828_int_bat_mon_mask bit(bd71828_int_bat_mon) + bd71828_int_temp, +#define bd71828_int_temp_mask bit(bd71828_int_temp) + bd71828_int_rtc, +#define bd71828_int_rtc_mask bit(bd71828_int_rtc) +}; + +/* interrupts */ +enum { + /* buck reg interrupts */ + bd71828_int_buck1_ocp, + bd71828_int_buck2_ocp, + bd71828_int_buck3_ocp, + bd71828_int_buck4_ocp, + bd71828_int_buck5_ocp, + bd71828_int_buck6_ocp, + bd71828_int_buck7_ocp, + bd71828_int_pgfault, + /* dcin1 interrupts */ + bd71828_int_dcin_det, + bd71828_int_dcin_rmv, + bd71828_int_clps_out, + bd71828_int_clps_in, + /* dcin2 interrupts */ + bd71828_int_dcin_mon_res, + bd71828_int_dcin_mon_det, + bd71828_int_longpush, + bd71828_int_midpush, + bd71828_int_shortpush, + bd71828_int_push, + bd71828_int_wdog, + bd71828_int_swreset, + /* vsys */ + bd71828_int_vsys_uv_res, + bd71828_int_vsys_uv_det, + bd71828_int_vsys_low_res, + bd71828_int_vsys_low_det, + bd71828_int_vsys_hall_in, + bd71828_int_vsys_hall_toggle, + bd71828_int_vsys_mon_res, + bd71828_int_vsys_mon_det, + /* charger */ + bd71828_int_chg_dcin_ilim, + bd71828_int_chg_topoff_to_done, + bd71828_int_chg_wdg_temp, + bd71828_int_chg_wdg_time, + bd71828_int_chg_recharge_res, + bd71828_int_chg_recharge_det, + bd71828_int_chg_ranged_temp_transition, + bd71828_int_chg_state_transition, + /* battery */ + bd71828_int_bat_temp_normal, + bd71828_int_bat_temp_erange, + bd71828_int_bat_temp_warn, + bd71828_int_bat_removed, + bd71828_int_bat_detected, + bd71828_int_therm_removed, + bd71828_int_therm_detected, + /* battery mon 1 */ + bd71828_int_bat_dead, + bd71828_int_bat_shortc_res, + bd71828_int_bat_shortc_det, + bd71828_int_bat_low_volt_res, + bd71828_int_bat_low_volt_det, + bd71828_int_bat_over_volt_res, + bd71828_int_bat_over_volt_det, + /* battery mon 2 */ + bd71828_int_bat_mon_res, + bd71828_int_bat_mon_det, + /* battery mon 3 (coulomb counter) */ + bd71828_int_bat_cc_mon1, + bd71828_int_bat_cc_mon2, + bd71828_int_bat_cc_mon3, + /* battery mon 4 */ + bd71828_int_bat_over_curr_1_res, + bd71828_int_bat_over_curr_1_det, + bd71828_int_bat_over_curr_2_res, + bd71828_int_bat_over_curr_2_det, + bd71828_int_bat_over_curr_3_res, + bd71828_int_bat_over_curr_3_det, + /* temperature */ + bd71828_int_temp_bat_low_res, + bd71828_int_temp_bat_low_det, + bd71828_int_temp_bat_hi_res, + bd71828_int_temp_bat_hi_det, + bd71828_int_temp_chip_over_125_res, + bd71828_int_temp_chip_over_125_det, + bd71828_int_temp_chip_over_vf_det, + bd71828_int_temp_chip_over_vf_res, + /* rtc alarm */ + bd71828_int_rtc0, + bd71828_int_rtc1, + bd71828_int_rtc2, +}; + +#define bd71828_int_buck1_ocp_mask 0x1 +#define bd71828_int_buck2_ocp_mask 0x2 +#define bd71828_int_buck3_ocp_mask 0x4 +#define bd71828_int_buck4_ocp_mask 0x8 +#define bd71828_int_buck5_ocp_mask 0x10 +#define bd71828_int_buck6_ocp_mask 0x20 +#define bd71828_int_buck7_ocp_mask 0x40 +#define bd71828_int_pgfault_mask 0x80 + +#define bd71828_int_dcin_det_mask 0x1 +#define bd71828_int_dcin_rmv_mask 0x2 +#define bd71828_int_clps_out_mask 0x4 +#define bd71828_int_clps_in_mask 0x8 + /* dcin2 interrupts */ +#define bd71828_int_dcin_mon_res_mask 0x1 +#define bd71828_int_dcin_mon_det_mask 0x2 +#define bd71828_int_longpush_mask 0x4 +#define bd71828_int_midpush_mask 0x8 +#define bd71828_int_shortpush_mask 0x10 +#define bd71828_int_push_mask 0x20 +#define bd71828_int_wdog_mask 0x40 +#define bd71828_int_swreset_mask 0x80 + /* vsys */ +#define bd71828_int_vsys_uv_res_mask 0x1 +#define bd71828_int_vsys_uv_det_mask 0x2 +#define bd71828_int_vsys_low_res_mask 0x4 +#define bd71828_int_vsys_low_det_mask 0x8 +#define bd71828_int_vsys_hall_in_mask 0x10 +#define bd71828_int_vsys_hall_toggle_mask 0x20 +#define bd71828_int_vsys_mon_res_mask 0x40 +#define bd71828_int_vsys_mon_det_mask 0x80 + /* charger */ +#define bd71828_int_chg_dcin_ilim_mask 0x1 +#define bd71828_int_chg_topoff_to_done_mask 0x2 +#define bd71828_int_chg_wdg_temp_mask 0x4 +#define bd71828_int_chg_wdg_time_mask 0x8 +#define bd71828_int_chg_recharge_res_mask 0x10 +#define bd71828_int_chg_recharge_det_mask 0x20 +#define bd71828_int_chg_ranged_temp_transition_mask 0x40 +#define bd71828_int_chg_state_transition_mask 0x80 + /* battery */ +#define bd71828_int_bat_temp_normal_mask 0x1 +#define bd71828_int_bat_temp_erange_mask 0x2 +#define bd71828_int_bat_temp_warn_mask 0x4 +#define bd71828_int_bat_removed_mask 0x10 +#define bd71828_int_bat_detected_mask 0x20 +#define bd71828_int_therm_removed_mask 0x40 +#define bd71828_int_therm_detected_mask 0x80 + /* battery mon 1 */ +#define bd71828_int_bat_dead_mask 0x2 +#define bd71828_int_bat_shortc_res_mask 0x4 +#define bd71828_int_bat_shortc_det_mask 0x8 +#define bd71828_int_bat_low_volt_res_mask 0x10 +#define bd71828_int_bat_low_volt_det_mask 0x20 +#define bd71828_int_bat_over_volt_res_mask 0x40 +#define bd71828_int_bat_over_volt_det_mask 0x80 + /* battery mon 2 */ +#define bd71828_int_bat_mon_res_mask 0x1 +#define bd71828_int_bat_mon_det_mask 0x2 + /* battery mon 3 (coulomb counter) */ +#define bd71828_int_bat_cc_mon1_mask 0x1 +#define bd71828_int_bat_cc_mon2_mask 0x2 +#define bd71828_int_bat_cc_mon3_mask 0x4 + /* battery mon 4 */ +#define bd71828_int_bat_over_curr_1_res_mask 0x1 +#define bd71828_int_bat_over_curr_1_det_mask 0x2 +#define bd71828_int_bat_over_curr_2_res_mask 0x4 +#define bd71828_int_bat_over_curr_2_det_mask 0x8 +#define bd71828_int_bat_over_curr_3_res_mask 0x10 +#define bd71828_int_bat_over_curr_3_det_mask 0x20 + /* temperature */ +#define bd71828_int_temp_bat_low_res_mask 0x1 +#define bd71828_int_temp_bat_low_det_mask 0x2 +#define bd71828_int_temp_bat_hi_res_mask 0x4 +#define bd71828_int_temp_bat_hi_det_mask 0x8 +#define bd71828_int_temp_chip_over_125_res_mask 0x10 +#define bd71828_int_temp_chip_over_125_det_mask 0x20 +#define bd71828_int_temp_chip_over_vf_res_mask 0x40 +#define bd71828_int_temp_chip_over_vf_det_mask 0x80 + /* rtc alarm */ +#define bd71828_int_rtc0_mask 0x1 +#define bd71828_int_rtc1_mask 0x2 +#define bd71828_int_rtc2_mask 0x4 + +#define bd71828_out32k_en 0x1 +#define bd71828_out_type_mask 0x2 +#define bd71828_out_type_open_drain 0x0 +#define bd71828_out_type_cmos 0x2 + +#endif /* __linux_mfd_bd71828_h__ */ diff --git a/include/linux/mfd/rohm-generic.h b/include/linux/mfd/rohm-generic.h --- a/include/linux/mfd/rohm-generic.h +++ b/include/linux/mfd/rohm-generic.h + rohm_chip_type_bd71828,
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Multi Function Devices (MFD)
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1c743ad523bb2f77a43a740a43c3b5bb9cbd82cd
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matti vaittinen
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include
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linux
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mfd
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mfd: da9062: add support for the da9062 gpios in the core
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currently the da9062 gpio's aren't available. the patch adds the support to make these available by adding a gpio device with the corresponding irq resources. furthermore the patch fixes a minor style issue for the onkey device.
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this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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add support for the da9062 gpios in the core
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
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['da9062']
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['c']
| 1
| 15
| 1
|
--- diff --git a/drivers/mfd/da9062-core.c b/drivers/mfd/da9062-core.c --- a/drivers/mfd/da9062-core.c +++ b/drivers/mfd/da9062-core.c +static struct resource da9062_gpio_resources[] = { + define_res_named(da9062_irq_gpi0, 1, "gpi0", ioresource_irq), + define_res_named(da9062_irq_gpi1, 1, "gpi1", ioresource_irq), + define_res_named(da9062_irq_gpi2, 1, "gpi2", ioresource_irq), + define_res_named(da9062_irq_gpi3, 1, "gpi3", ioresource_irq), + define_res_named(da9062_irq_gpi4, 1, "gpi4", ioresource_irq), +}; + - .of_compatible = "dlg,da9062-onkey", + .of_compatible = "dlg,da9062-onkey", + }, + { + .name = "da9062-gpio", + .num_resources = array_size(da9062_gpio_resources), + .resources = da9062_gpio_resources, + .of_compatible = "dlg,da9062-gpio",
|
Multi Function Devices (MFD)
|
1ea9bd88eeffd4e4505f3f93102bd4dad9f2471d
|
marco felsch linus walleij linus walleij linaro org adam thomson adam thomson opensource diasemi com
|
drivers
|
mfd
| |
mfd: intel-lpss: add intel jasper lake pci ids
|
intel jasper lake has the same lpss than intel ice lake. add the new ids to the list of supported devices.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add intel jasper lake pci ids
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel-lpss']
|
['c']
| 1
| 13
| 0
|
--- diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c --- a/drivers/mfd/intel-lpss-pci.c +++ b/drivers/mfd/intel-lpss-pci.c + /* jsl */ + { pci_vdevice(intel, 0x4da8), (kernel_ulong_t)&spt_uart_info }, + { pci_vdevice(intel, 0x4da9), (kernel_ulong_t)&spt_uart_info }, + { pci_vdevice(intel, 0x4daa), (kernel_ulong_t)&spt_info }, + { pci_vdevice(intel, 0x4dab), (kernel_ulong_t)&spt_info }, + { pci_vdevice(intel, 0x4daf), (kernel_ulong_t)&spt_uart_info }, + { pci_vdevice(intel, 0x4dc5), (kernel_ulong_t)&bxt_i2c_info }, + { pci_vdevice(intel, 0x4dc6), (kernel_ulong_t)&bxt_i2c_info }, + { pci_vdevice(intel, 0x4de8), (kernel_ulong_t)&bxt_i2c_info }, + { pci_vdevice(intel, 0x4de9), (kernel_ulong_t)&bxt_i2c_info }, + { pci_vdevice(intel, 0x4dea), (kernel_ulong_t)&bxt_i2c_info }, + { pci_vdevice(intel, 0x4deb), (kernel_ulong_t)&bxt_i2c_info }, + { pci_vdevice(intel, 0x4dfb), (kernel_ulong_t)&spt_info },
|
Multi Function Devices (MFD)
|
57b89dd220be5e48bdbf0352a673db5ef4bc905e
|
andy shevchenko
|
drivers
|
mfd
| |
mfd: ioc3: add driver for sgi ioc3 chip
|
sgi ioc3 chip has integrated ethernet, keyboard and mouse interface. it also supports connecting a superio chip for serial and parallel interfaces. ioc3 is used inside various sgi systemboards and add-on cards with different equipped external interfaces.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add driver for sgi ioc3 chip
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['ioc3']
|
['c', 'kconfig', 'makefile']
| 9
| 893
| 481
|
--- diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c - -static int __init sgi_ip27_rtc_devinit(void) -{ - struct resource res; - - memset(&res, 0, sizeof(res)); - res.start = xphysaddr(kl_config_ch_cons_info(master_nasid)->memory_base + - ioc3_bytebus_dev0); - res.end = res.start + 32767; - res.flags = ioresource_mem; - - return is_err(platform_device_register_simple("rtc-m48t35", -1, - &res, 1)); -} - -/* - * kludge make this a device_initcall after ioc3 resource conflicts - * are resolved - */ -late_initcall(sgi_ip27_rtc_devinit); diff --git a/drivers/mfd/kconfig b/drivers/mfd/kconfig --- a/drivers/mfd/kconfig +++ b/drivers/mfd/kconfig +config sgi_mfd_ioc3 + tristate "sgi ioc3 core driver" + depends on pci && mips && 64bit + select mfd_core + help + this option enables basic support for the sgi ioc3-based + controller cards. this option does not enable any specific + functions on such a card, but provides necessary infrastructure + for other drivers to utilize. + + if you have an sgi origin, octane, or a pci ioc3 card, + then say y. otherwise say n. + diff --git a/drivers/mfd/makefile b/drivers/mfd/makefile --- a/drivers/mfd/makefile +++ b/drivers/mfd/makefile +obj-$(config_sgi_mfd_ioc3) += ioc3.o diff --git a/drivers/mfd/ioc3.c b/drivers/mfd/ioc3.c --- /dev/null +++ b/drivers/mfd/ioc3.c +// spdx-license-identifier: gpl-2.0 +/* + * sgi ioc3 multifunction device driver + * + * copyright (c) 2018, 2019 thomas bogendoerfer <tbogendoerfer@suse.de> + * + * based on work by: + * stanislaw skowronek <skylark@unaligned.org> + * joshua kinard <kumba@gentoo.org> + * brent casavant <bcasavan@sgi.com> - ioc4 master driver + * pat gefre <pfg@sgi.com> - ioc3 serial port irq demuxer + */ + +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/interrupt.h> +#include <linux/mfd/core.h> +#include <linux/module.h> +#include <linux/pci.h> +#include <linux/platform_device.h> +#include <linux/platform_data/sgi-w1.h> +#include <linux/rtc/ds1685.h> + +#include <asm/pci/bridge.h> +#include <asm/sn/ioc3.h> + +#define ioc3_irq_serial_a 6 +#define ioc3_irq_serial_b 15 +#define ioc3_irq_kbd 22 + +/* bitmask for selecting which irqs are level triggered */ +#define ioc3_lvl_mask (bit(ioc3_irq_serial_a) | bit(ioc3_irq_serial_b)) + +#define m48t35_reg_size 32768 /* size of m48t35 registers */ + +/* 1.2 us latency timer (40 cycles at 33 mhz) */ +#define ioc3_latency 40 + +struct ioc3_priv_data { + struct irq_domain *domain; + struct ioc3 __iomem *regs; + struct pci_dev *pdev; + int domain_irq; +}; + +static void ioc3_irq_ack(struct irq_data *d) +{ + struct ioc3_priv_data *ipd = irq_data_get_irq_chip_data(d); + unsigned int hwirq = irqd_to_hwirq(d); + + writel(bit(hwirq), &ipd->regs->sio_ir); +} + +static void ioc3_irq_mask(struct irq_data *d) +{ + struct ioc3_priv_data *ipd = irq_data_get_irq_chip_data(d); + unsigned int hwirq = irqd_to_hwirq(d); + + writel(bit(hwirq), &ipd->regs->sio_iec); +} + +static void ioc3_irq_unmask(struct irq_data *d) +{ + struct ioc3_priv_data *ipd = irq_data_get_irq_chip_data(d); + unsigned int hwirq = irqd_to_hwirq(d); + + writel(bit(hwirq), &ipd->regs->sio_ies); +} + +static struct irq_chip ioc3_irq_chip = { + .name = "ioc3", + .irq_ack = ioc3_irq_ack, + .irq_mask = ioc3_irq_mask, + .irq_unmask = ioc3_irq_unmask, +}; + +static int ioc3_irq_domain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + /* set level irqs for every interrupt contained in ioc3_lvl_mask */ + if (bit(hwirq) & ioc3_lvl_mask) + irq_set_chip_and_handler(irq, &ioc3_irq_chip, handle_level_irq); + else + irq_set_chip_and_handler(irq, &ioc3_irq_chip, handle_edge_irq); + + irq_set_chip_data(irq, d->host_data); + return 0; +} + +static void ioc3_irq_domain_unmap(struct irq_domain *d, unsigned int irq) +{ + irq_set_chip_and_handler(irq, null, null); + irq_set_chip_data(irq, null); +} + +static const struct irq_domain_ops ioc3_irq_domain_ops = { + .map = ioc3_irq_domain_map, + .unmap = ioc3_irq_domain_unmap, +}; + +static void ioc3_irq_handler(struct irq_desc *desc) +{ + struct irq_domain *domain = irq_desc_get_handler_data(desc); + struct ioc3_priv_data *ipd = domain->host_data; + struct ioc3 __iomem *regs = ipd->regs; + u32 pending, mask; + unsigned int irq; + + pending = readl(®s->sio_ir); + mask = readl(®s->sio_ies); + pending &= mask; /* mask off not enabled interrupts */ + + if (pending) { + irq = irq_find_mapping(domain, __ffs(pending)); + if (irq) + generic_handle_irq(irq); + } else { + spurious_interrupt(); + } +} + +/* + * system boards/baseios use more interrupt pins of the bridge asic + * to which the ioc3 is connected. since the ioc3 mfd driver + * knows wiring of these extra pins, we use the map_irq function + * to get interrupts activated + */ +static int ioc3_map_irq(struct pci_dev *pdev, int slot, int pin) +{ + struct pci_host_bridge *hbrg = pci_find_host_bridge(pdev->bus); + + return hbrg->map_irq(pdev, slot, pin); +} + +static int ioc3_irq_domain_setup(struct ioc3_priv_data *ipd, int irq) +{ + struct irq_domain *domain; + struct fwnode_handle *fn; + + fn = irq_domain_alloc_named_fwnode("ioc3"); + if (!fn) + goto err; + + domain = irq_domain_create_linear(fn, 24, &ioc3_irq_domain_ops, ipd); + if (!domain) + goto err; + + irq_domain_free_fwnode(fn); + ipd->domain = domain; + + irq_set_chained_handler_and_data(irq, ioc3_irq_handler, domain); + ipd->domain_irq = irq; + return 0; + +err: + dev_err(&ipd->pdev->dev, "irq domain setup failed "); + return -enomem; +} + +static struct resource ioc3_uarta_resources[] = { + define_res_mem(offsetof(struct ioc3, sregs.uarta), + sizeof_field(struct ioc3, sregs.uarta)), + define_res_irq(ioc3_irq_serial_a) +}; + +static struct resource ioc3_uartb_resources[] = { + define_res_mem(offsetof(struct ioc3, sregs.uartb), + sizeof_field(struct ioc3, sregs.uartb)), + define_res_irq(ioc3_irq_serial_b) +}; + +static struct mfd_cell ioc3_serial_cells[] = { + { + .name = "ioc3-serial8250", + .resources = ioc3_uarta_resources, + .num_resources = array_size(ioc3_uarta_resources), + }, + { + .name = "ioc3-serial8250", + .resources = ioc3_uartb_resources, + .num_resources = array_size(ioc3_uartb_resources), + } +}; + +static int ioc3_serial_setup(struct ioc3_priv_data *ipd) +{ + int ret; + + /* set gpio pins for rs232/rs422 mode selection */ + writel(gpcr_uarta_modesel | gpcr_uartb_modesel, + &ipd->regs->gpcr_s); + /* select rs232 mode for uart a */ + writel(0, &ipd->regs->gppr[6]); + /* select rs232 mode for uart b */ + writel(0, &ipd->regs->gppr[7]); + + /* switch both ports to 16650 mode */ + writel(readl(&ipd->regs->port_a.sscr) & ~sscr_dma_en, + &ipd->regs->port_a.sscr); + writel(readl(&ipd->regs->port_b.sscr) & ~sscr_dma_en, + &ipd->regs->port_b.sscr); + udelay(1000); /* wait until mode switch is done */ + + ret = mfd_add_devices(&ipd->pdev->dev, platform_devid_auto, + ioc3_serial_cells, array_size(ioc3_serial_cells), + &ipd->pdev->resource[0], 0, ipd->domain); + if (ret) { + dev_err(&ipd->pdev->dev, "failed to add 16550 subdevs "); + return ret; + } + + return 0; +} + +static struct resource ioc3_kbd_resources[] = { + define_res_mem(offsetof(struct ioc3, serio), + sizeof_field(struct ioc3, serio)), + define_res_irq(ioc3_irq_kbd) +}; + +static struct mfd_cell ioc3_kbd_cells[] = { + { + .name = "ioc3-kbd", + .resources = ioc3_kbd_resources, + .num_resources = array_size(ioc3_kbd_resources), + } +}; + +static int ioc3_kbd_setup(struct ioc3_priv_data *ipd) +{ + int ret; + + ret = mfd_add_devices(&ipd->pdev->dev, platform_devid_auto, + ioc3_kbd_cells, array_size(ioc3_kbd_cells), + &ipd->pdev->resource[0], 0, ipd->domain); + if (ret) { + dev_err(&ipd->pdev->dev, "failed to add 16550 subdevs "); + return ret; + } + + return 0; +} + +static struct resource ioc3_eth_resources[] = { + define_res_mem(offsetof(struct ioc3, eth), + sizeof_field(struct ioc3, eth)), + define_res_mem(offsetof(struct ioc3, ssram), + sizeof_field(struct ioc3, ssram)), + define_res_irq(0) +}; + +static struct resource ioc3_w1_resources[] = { + define_res_mem(offsetof(struct ioc3, mcr), + sizeof_field(struct ioc3, mcr)), +}; +static struct sgi_w1_platform_data ioc3_w1_platform_data; + +static struct mfd_cell ioc3_eth_cells[] = { + { + .name = "ioc3-eth", + .resources = ioc3_eth_resources, + .num_resources = array_size(ioc3_eth_resources), + }, + { + .name = "sgi_w1", + .resources = ioc3_w1_resources, + .num_resources = array_size(ioc3_w1_resources), + .platform_data = &ioc3_w1_platform_data, + .pdata_size = sizeof(ioc3_w1_platform_data), + } +}; + +static int ioc3_eth_setup(struct ioc3_priv_data *ipd) +{ + int ret; + + /* enable one-wire bus */ + writel(gpcr_mlan_en, &ipd->regs->gpcr_s); + + /* generate unique identifier */ + snprintf(ioc3_w1_platform_data.dev_id, + sizeof(ioc3_w1_platform_data.dev_id), "ioc3-%012llx", + ipd->pdev->resource->start); + + ret = mfd_add_devices(&ipd->pdev->dev, platform_devid_auto, + ioc3_eth_cells, array_size(ioc3_eth_cells), + &ipd->pdev->resource[0], ipd->pdev->irq, null); + if (ret) { + dev_err(&ipd->pdev->dev, "failed to add eth/w1 subdev "); + return ret; + } + + return 0; +} + +static struct resource ioc3_m48t35_resources[] = { + define_res_mem(ioc3_bytebus_dev0, m48t35_reg_size) +}; + +static struct mfd_cell ioc3_m48t35_cells[] = { + { + .name = "rtc-m48t35", + .resources = ioc3_m48t35_resources, + .num_resources = array_size(ioc3_m48t35_resources), + } +}; + +static int ioc3_m48t35_setup(struct ioc3_priv_data *ipd) +{ + int ret; + + ret = mfd_add_devices(&ipd->pdev->dev, platform_devid_auto, + ioc3_m48t35_cells, array_size(ioc3_m48t35_cells), + &ipd->pdev->resource[0], 0, ipd->domain); + if (ret) + dev_err(&ipd->pdev->dev, "failed to add m48t35 subdev "); + + return ret; +} + +static struct ds1685_rtc_platform_data ip30_rtc_platform_data = { + .bcd_mode = false, + .no_irq = false, + .uie_unsupported = true, + .access_type = ds1685_reg_indirect, +}; + +static struct resource ioc3_rtc_ds1685_resources[] = { + define_res_mem(ioc3_bytebus_dev1, 1), + define_res_mem(ioc3_bytebus_dev2, 1), + define_res_irq(0) +}; + +static struct mfd_cell ioc3_ds1685_cells[] = { + { + .name = "rtc-ds1685", + .resources = ioc3_rtc_ds1685_resources, + .num_resources = array_size(ioc3_rtc_ds1685_resources), + .platform_data = &ip30_rtc_platform_data, + .pdata_size = sizeof(ip30_rtc_platform_data), + .id = platform_devid_none, + } +}; + +static int ioc3_ds1685_setup(struct ioc3_priv_data *ipd) +{ + int ret, irq; + + irq = ioc3_map_irq(ipd->pdev, 6, 0); + + ret = mfd_add_devices(&ipd->pdev->dev, 0, ioc3_ds1685_cells, + array_size(ioc3_ds1685_cells), + &ipd->pdev->resource[0], irq, null); + if (ret) + dev_err(&ipd->pdev->dev, "failed to add ds1685 subdev "); + + return ret; +}; + + +static struct resource ioc3_leds_resources[] = { + define_res_mem(offsetof(struct ioc3, gppr[0]), + sizeof_field(struct ioc3, gppr[0])), + define_res_mem(offsetof(struct ioc3, gppr[1]), + sizeof_field(struct ioc3, gppr[1])), +}; + +static struct mfd_cell ioc3_led_cells[] = { + { + .name = "ip30-leds", + .resources = ioc3_leds_resources, + .num_resources = array_size(ioc3_leds_resources), + .id = platform_devid_none, + } +}; + +static int ioc3_led_setup(struct ioc3_priv_data *ipd) +{ + int ret; + + ret = mfd_add_devices(&ipd->pdev->dev, 0, ioc3_led_cells, + array_size(ioc3_led_cells), + &ipd->pdev->resource[0], 0, ipd->domain); + if (ret) + dev_err(&ipd->pdev->dev, "failed to add led subdev "); + + return ret; +} + +static int ip27_baseio_setup(struct ioc3_priv_data *ipd) +{ + int ret, io_irq; + + io_irq = ioc3_map_irq(ipd->pdev, pci_slot(ipd->pdev->devfn), + pci_interrupt_intb); + ret = ioc3_irq_domain_setup(ipd, io_irq); + if (ret) + return ret; + + ret = ioc3_eth_setup(ipd); + if (ret) + return ret; + + ret = ioc3_serial_setup(ipd); + if (ret) + return ret; + + return ioc3_m48t35_setup(ipd); +} + +static int ip27_baseio6g_setup(struct ioc3_priv_data *ipd) +{ + int ret, io_irq; + + io_irq = ioc3_map_irq(ipd->pdev, pci_slot(ipd->pdev->devfn), + pci_interrupt_intb); + ret = ioc3_irq_domain_setup(ipd, io_irq); + if (ret) + return ret; + + ret = ioc3_eth_setup(ipd); + if (ret) + return ret; + + ret = ioc3_serial_setup(ipd); + if (ret) + return ret; + + ret = ioc3_m48t35_setup(ipd); + if (ret) + return ret; + + return ioc3_kbd_setup(ipd); +} + +static int ip27_mio_setup(struct ioc3_priv_data *ipd) +{ + int ret; + + ret = ioc3_irq_domain_setup(ipd, ipd->pdev->irq); + if (ret) + return ret; + + ret = ioc3_serial_setup(ipd); + if (ret) + return ret; + + return ioc3_kbd_setup(ipd); +} + +static int ip30_sysboard_setup(struct ioc3_priv_data *ipd) +{ + int ret, io_irq; + + io_irq = ioc3_map_irq(ipd->pdev, pci_slot(ipd->pdev->devfn), + pci_interrupt_intb); + ret = ioc3_irq_domain_setup(ipd, io_irq); + if (ret) + return ret; + + ret = ioc3_eth_setup(ipd); + if (ret) + return ret; + + ret = ioc3_serial_setup(ipd); + if (ret) + return ret; + + ret = ioc3_kbd_setup(ipd); + if (ret) + return ret; + + ret = ioc3_ds1685_setup(ipd); + if (ret) + return ret; + + return ioc3_led_setup(ipd); +} + +static int ioc3_menet_setup(struct ioc3_priv_data *ipd) +{ + int ret, io_irq; + + io_irq = ioc3_map_irq(ipd->pdev, pci_slot(ipd->pdev->devfn), + pci_interrupt_intb); + ret = ioc3_irq_domain_setup(ipd, io_irq); + if (ret) + return ret; + + ret = ioc3_eth_setup(ipd); + if (ret) + return ret; + + return ioc3_serial_setup(ipd); +} + +static int ioc3_menet4_setup(struct ioc3_priv_data *ipd) +{ + return ioc3_eth_setup(ipd); +} + +static int ioc3_cad_duo_setup(struct ioc3_priv_data *ipd) +{ + int ret, io_irq; + + io_irq = ioc3_map_irq(ipd->pdev, pci_slot(ipd->pdev->devfn), + pci_interrupt_intb); + ret = ioc3_irq_domain_setup(ipd, io_irq); + if (ret) + return ret; + + ret = ioc3_eth_setup(ipd); + if (ret) + return ret; + + return ioc3_kbd_setup(ipd); +} + +/* helper macro for filling ioc3_info array */ +#define ioc3_sid(_name, _sid, _setup) \ + { \ + .name = _name, \ + .sid = pci_vendor_id_sgi | (ioc3_subsys_ ## _sid << 16), \ + .setup = _setup, \ + } + +static struct { + const char *name; + u32 sid; + int (*setup)(struct ioc3_priv_data *ipd); +} ioc3_infos[] = { + ioc3_sid("ip27 baseio6g", ip27_baseio6g, &ip27_baseio6g_setup), + ioc3_sid("ip27 mio", ip27_mio, &ip27_mio_setup), + ioc3_sid("ip27 baseio", ip27_baseio, &ip27_baseio_setup), + ioc3_sid("ip29 system board", ip29_sysboard, &ip27_baseio6g_setup), + ioc3_sid("ip30 system board", ip30_sysboard, &ip30_sysboard_setup), + ioc3_sid("menet", menet, &ioc3_menet_setup), + ioc3_sid("menet4", menet4, &ioc3_menet4_setup) +}; +#undef ioc3_sid + +static int ioc3_setup(struct ioc3_priv_data *ipd) +{ + u32 sid; + int i; + + /* clear irqs */ + writel(~0, &ipd->regs->sio_iec); + writel(~0, &ipd->regs->sio_ir); + writel(0, &ipd->regs->eth.eier); + writel(~0, &ipd->regs->eth.eisr); + + /* read subsystem vendor id and subsystem id */ + pci_read_config_dword(ipd->pdev, pci_subsystem_vendor_id, &sid); + + for (i = 0; i < array_size(ioc3_infos); i++) + if (sid == ioc3_infos[i].sid) { + pr_info("ioc3: %s ", ioc3_infos[i].name); + return ioc3_infos[i].setup(ipd); + } + + /* treat everything not identified by pci subid as cad duo */ + pr_info("ioc3: cad duo "); + return ioc3_cad_duo_setup(ipd); +} + +static int ioc3_mfd_probe(struct pci_dev *pdev, + const struct pci_device_id *pci_id) +{ + struct ioc3_priv_data *ipd; + struct ioc3 __iomem *regs; + int ret; + + ret = pci_enable_device(pdev); + if (ret) + return ret; + + pci_write_config_byte(pdev, pci_latency_timer, ioc3_latency); + pci_set_master(pdev); + + ret = dma_set_mask_and_coherent(&pdev->dev, dma_bit_mask(64)); + if (ret) { + pr_err("%s: no usable dma configuration, aborting. ", + pci_name(pdev)); + goto out_disable_device; + } + + /* set up per-ioc3 data */ + ipd = devm_kzalloc(&pdev->dev, sizeof(struct ioc3_priv_data), + gfp_kernel); + if (!ipd) { + ret = -enomem; + goto out_disable_device; + } + ipd->pdev = pdev; + + /* + * map all ioc3 registers. these are shared between subdevices + * so the main ioc3 module manages them. + */ + regs = pci_ioremap_bar(pdev, 0); + if (!regs) { + dev_warn(&pdev->dev, "ioc3: unable to remap pci bar for %s. ", + pci_name(pdev)); + ret = -enomem; + goto out_disable_device; + } + ipd->regs = regs; + + /* track pci-device specific data */ + pci_set_drvdata(pdev, ipd); + + ret = ioc3_setup(ipd); + if (ret) { + /* remove all already added mfd devices */ + mfd_remove_devices(&ipd->pdev->dev); + if (ipd->domain) { + irq_domain_remove(ipd->domain); + free_irq(ipd->domain_irq, (void *)ipd); + } + pci_iounmap(pdev, regs); + goto out_disable_device; + } + + return 0; + +out_disable_device: + pci_disable_device(pdev); + return ret; +} + +static void ioc3_mfd_remove(struct pci_dev *pdev) +{ + struct ioc3_priv_data *ipd; + + ipd = pci_get_drvdata(pdev); + + /* clear and disable all irqs */ + writel(~0, &ipd->regs->sio_iec); + writel(~0, &ipd->regs->sio_ir); + + /* release resources */ + mfd_remove_devices(&ipd->pdev->dev); + if (ipd->domain) { + irq_domain_remove(ipd->domain); + free_irq(ipd->domain_irq, (void *)ipd); + } + pci_iounmap(pdev, ipd->regs); + pci_disable_device(pdev); +} + +static struct pci_device_id ioc3_mfd_id_table[] = { + { pci_vendor_id_sgi, pci_device_id_sgi_ioc3, pci_any_id, pci_any_id }, + { 0, }, +}; +module_device_table(pci, ioc3_mfd_id_table); + +static struct pci_driver ioc3_mfd_driver = { + .name = "ioc3", + .id_table = ioc3_mfd_id_table, + .probe = ioc3_mfd_probe, + .remove = ioc3_mfd_remove, +}; + +module_pci_driver(ioc3_mfd_driver); + +module_author("thomas bogendoerfer <tbogendoerfer@suse.de>"); +module_description("sgi ioc3 mfd driver"); +module_license("gpl v2"); diff --git a/drivers/net/ethernet/sgi/kconfig b/drivers/net/ethernet/sgi/kconfig --- a/drivers/net/ethernet/sgi/kconfig +++ b/drivers/net/ethernet/sgi/kconfig - depends on (pci && sgi_ip27) || sgi_ip32 + depends on (pci && sgi_mfd_ioc3) || sgi_ip32 ---help--- - depends on pci && sgi_ip27 + depends on pci && sgi_mfd_ioc3 + select crc16 ---help--- diff --git a/drivers/net/ethernet/sgi/ioc3-eth.c b/drivers/net/ethernet/sgi/ioc3-eth.c --- a/drivers/net/ethernet/sgi/ioc3-eth.c +++ b/drivers/net/ethernet/sgi/ioc3-eth.c - * o convert to using a ioc3 meta driver. -#include <linux/pci.h> +#include <linux/init.h> +#include <linux/crc16.h> - -#ifdef config_serial_8250 -#include <linux/serial_core.h> -#include <linux/serial_8250.h> -#include <linux/serial_reg.h> -#endif - +#include <linux/platform_device.h> +#include <linux/nvmem-consumer.h> -#include <asm/byteorder.h> -#include <asm/pgtable.h> -#include <linux/uaccess.h> -#include <asm/sn/types.h> +#define crc16_init 0 +#define crc16_valid 0xb001 + - struct ioc3 *all_regs; - struct net_device *dev; - struct pci_dev *pdev; - -static const char ioc3_str[] = "ioc3 ethernet"; - -#define ioc3_size 0x100000 - -static inline u32 mcr_pack(u32 pulse, u32 sample) -{ - return (pulse << 10) | (sample << 2); -} - -static int nic_wait(u32 __iomem *mcr) -{ - u32 m; - - do { - m = readl(mcr); - } while (!(m & 2)); - - return m & 1; -} - -static int nic_reset(u32 __iomem *mcr) -{ - int presence; - - writel(mcr_pack(500, 65), mcr); - presence = nic_wait(mcr); - - writel(mcr_pack(0, 500), mcr); - nic_wait(mcr); - - return presence; -} - -static inline int nic_read_bit(u32 __iomem *mcr) -{ - int result; - - writel(mcr_pack(6, 13), mcr); - result = nic_wait(mcr); - writel(mcr_pack(0, 100), mcr); - nic_wait(mcr); - - return result; -} - -static inline void nic_write_bit(u32 __iomem *mcr, int bit) -{ - if (bit) - writel(mcr_pack(6, 110), mcr); - else - writel(mcr_pack(80, 30), mcr); - - nic_wait(mcr); -} - -/* read a byte from an ibutton device - */ -static u32 nic_read_byte(u32 __iomem *mcr) -{ - u32 result = 0; - int i; - - for (i = 0; i < 8; i++) - result = (result >> 1) | (nic_read_bit(mcr) << 7); - - return result; -} - -/* write a byte to an ibutton device - */ -static void nic_write_byte(u32 __iomem *mcr, int byte) +static int ioc3eth_nvmem_match(struct device *dev, const void *data) - int i, bit; - - for (i = 8; i; i--) { - bit = byte & 1; - byte >>= 1; - - nic_write_bit(mcr, bit); - } -} + const char *name = dev_name(dev); + const char *prefix = data; + int prefix_len; -static u64 nic_find(u32 __iomem *mcr, int *last) -{ - int a, b, index, disc; - u64 address = 0; - - nic_reset(mcr); - /* search rom. */ - nic_write_byte(mcr, 0xf0); - - /* algorithm from ''book of ibutton standards''. */ - for (index = 0, disc = 0; index < 64; index++) { - a = nic_read_bit(mcr); - b = nic_read_bit(mcr); - - if (a && b) { - pr_warn("nic search failed (not fatal). "); - *last = 0; - return 0; - } + prefix_len = strlen(prefix); + if (strlen(name) < (prefix_len + 3)) + return 0; - if (!a && !b) { - if (index == *last) { - address |= 1ul << index; - } else if (index > *last) { - address &= ~(1ul << index); - disc = index; - } else if ((address & (1ul << index)) == 0) { - disc = index; - } - nic_write_bit(mcr, address & (1ul << index)); - continue; - } else { - if (a) - address |= 1ul << index; - else - address &= ~(1ul << index); - nic_write_bit(mcr, a); - continue; - } - } - - *last = disc; - - return address; -} - -static int nic_init(u32 __iomem *mcr) -{ - const char *unknown = "unknown"; - const char *type = unknown; - u8 crc; - u8 serial[6]; - int save = 0, i; - - while (1) { - u64 reg; - - reg = nic_find(mcr, &save); - - switch (reg & 0xff) { - case 0x91: - type = "ds1981u"; - break; - default: - if (save == 0) { - /* let the caller try again. */ - return -1; - } - continue; - } + if (memcmp(prefix, name, prefix_len) != 0) + return 0; - nic_reset(mcr); - - /* match rom. */ - nic_write_byte(mcr, 0x55); - for (i = 0; i < 8; i++) - nic_write_byte(mcr, (reg >> (i << 3)) & 0xff); - - reg >>= 8; /* shift out type. */ - for (i = 0; i < 6; i++) { - serial[i] = reg & 0xff; - reg >>= 8; - } - crc = reg & 0xff; - break; - } - - pr_info("found %s nic", type); - if (type != unknown) - pr_cont(" registration number %pm, crc %02x", serial, crc); - pr_cont(". "); + /* found nvmem device which is attached to our ioc3 + * now check for one wire family code 09, 89 and 91 + */ + if (memcmp(name + prefix_len, "09-", 3) == 0) + return 1; + if (memcmp(name + prefix_len, "89-", 3) == 0) + return 1; + if (memcmp(name + prefix_len, "91-", 3) == 0) + return 1; -/* read the nic (number-in-a-can) device used to store the mac address on - * sn0 / sn00 nodeboards and pci cards. - */ -static void ioc3_get_eaddr_nic(struct ioc3_private *ip) +static int ioc3eth_get_mac_addr(struct resource *res, u8 mac_addr[6]) - u32 __iomem *mcr = &ip->all_regs->mcr; - int tries = 2; /* there may be some problem with the battery? */ - u8 nic[14]; + struct nvmem_device *nvmem; + char prefix[24]; + u8 prom[16]; + int ret; - writel(1 << 21, &ip->all_regs->gpcr_s); - - while (tries--) { - if (!nic_init(mcr)) - break; - udelay(500); - } - - if (tries < 0) { - pr_err("failed to read mac address "); - return; - } + snprintf(prefix, sizeof(prefix), "ioc3-%012llx-", + res->start & ~0xffff); - /* read memory. */ - nic_write_byte(mcr, 0xf0); - nic_write_byte(mcr, 0x00); - nic_write_byte(mcr, 0x00); + nvmem = nvmem_device_find(prefix, ioc3eth_nvmem_match); + if (is_err(nvmem)) + return ptr_err(nvmem); - for (i = 13; i >= 0; i--) - nic[i] = nic_read_byte(mcr); + ret = nvmem_device_read(nvmem, 0, 16, prom); + nvmem_device_put(nvmem); + if (ret < 0) + return ret; - for (i = 2; i < 8; i++) - ip->dev->dev_addr[i - 2] = nic[i]; -} + /* check, if content is valid */ + if (prom[0] != 0x0a || + crc16(crc16_init, prom, 13) != crc16_valid) + return -einval; -/* ok, this is hosed by design. it's necessary to know what machine the - * nic is in in order to know how to read the nic address. we also have - * to know if it's a pci card or a nic in on the node board ... - */ -static void ioc3_get_eaddr(struct ioc3_private *ip) -{ - ioc3_get_eaddr_nic(ip); + for (i = 0; i < 6; i++) + mac_addr[i] = prom[10 - i]; - pr_info("ethernet address is %pm. ", ip->dev->dev_addr); + return 0; - word = ioc3_mdio_read(ip->dev, i, mii_physid1); + word = ioc3_mdio_read(ip->mii.dev, i, mii_physid1); - if (request_irq(dev->irq, ioc3_interrupt, irqf_shared, ioc3_str, dev)) { - netdev_err(dev, "can't get irq %d ", dev->irq); - - return -eagain; - } - -/* menet cards have four ioc3 chips, which are attached to two sets of - * pci slot resources each: the primary connections are on slots - * 0..3 and the secondaries are on 4..7 - * - * all four ethernets are brought out to connectors; six serial ports - * (a pair from each of the first three ioc3s) are brought out to - * minidins; all other subdevices are left swinging in the wind, leave - * them disabled. - */ - -static int ioc3_adjacent_is_ioc3(struct pci_dev *pdev, int slot) -{ - struct pci_dev *dev = pci_get_slot(pdev->bus, pci_devfn(slot, 0)); - int ret = 0; - - if (dev) { - if (dev->vendor == pci_vendor_id_sgi && - dev->device == pci_device_id_sgi_ioc3) - ret = 1; - pci_dev_put(dev); - } - - return ret; -} - -static int ioc3_is_menet(struct pci_dev *pdev) -{ - return !pdev->bus->parent && - ioc3_adjacent_is_ioc3(pdev, 0) && - ioc3_adjacent_is_ioc3(pdev, 1) && - ioc3_adjacent_is_ioc3(pdev, 2); -} - -#ifdef config_serial_8250 -/* note about serial ports and consoles: - * for console output, everyone uses the ioc3 uarta (offset 0x178) - * connected to the master node (look in ip27_setup_console() and - * ip27prom_console_write()). - * - * for serial (/dev/ttys0 etc), we can not have hardcoded serial port - * addresses on a partitioned machine. since we currently use the ioc3 - * serial ports, we use dynamic serial port discovery that the serial.c - * driver uses for pci/pnp ports (there is an entry for the sgi ioc3 - * boards in pci_boards[]). unfortunately, uarta's pio address is greater - * than uartb's, although uarta on o200s has traditionally been known as - * port 0. so, we just use one serial port from each ioc3 (since the - * serial driver adds addresses to get to higher ports). - * - * the first one to do a register_console becomes the preferred console - * (if there is no kernel command line console= directive). /dev/console - * (ie 5, 1) is then "aliased" into the device number returned by the - * "device" routine referred to in this console structure - * (ip27prom_console_dev). - * - * also look in ip27-pci.c:pci_fixup_ioc3() for some comments on working - * around ioc3 oddities in this respect. - * - * the ioc3 serials use a 22mhz clock rate with an additional divider which - * can be programmed in the scr register if the dlab bit is set. - * - * register to interrupt zero because we share the interrupt with - * the serial driver which we don't properly support yet. - * - * can't use upf_ioremap as the whole of ioc3 resources have already been - * registered. - */ -static unsigned int ioc3_serial_in(struct uart_port *p, int offset) -{ - return readb(p->membase + (offset ^ 3)); -} - -static void ioc3_serial_out(struct uart_port *p, int offset, int value) -{ - writeb(value, p->membase + (offset ^ 3)); -} - -static void ioc3_8250_register(struct ioc3_uartregs __iomem *uart) -{ -#define cosmisc_constant 6 - - struct uart_8250_port port = { - .port = { - .irq = 0, - .flags = upf_skip_test | upf_boot_autoconf, - .iotype = upio_mem, - .regshift = 0, - .uartclk = (22000000 << 1) / cosmisc_constant, - - .membase = (unsigned char __iomem *)uart, - .mapbase = (unsigned long)uart, - .serial_in = ioc3_serial_in, - .serial_out = ioc3_serial_out, - } - }; - unsigned char lcr; - - lcr = readb(&uart->iu_lcr); - writeb(lcr | uart_lcr_dlab, &uart->iu_lcr); - writeb(cosmisc_constant, &uart->iu_scr); - writeb(lcr, &uart->iu_lcr); - readb(&uart->iu_lcr); - serial8250_register_8250_port(&port); -} - -static void ioc3_serial_probe(struct pci_dev *pdev, struct ioc3 *ioc3) -{ - u32 sio_iec; - - /* we need to recognice and treat the fourth menet serial as it - * does not have an superio chip attached to it, therefore attempting - * to access it will result in bus errors. we call something an - * menet if pci slot 0, 1, 2 and 3 of a master pci bus all have an ioc3 - * in it. this is paranoid but we want to avoid blowing up on a - * showhorn pci box that happens to have 4 ioc3 cards in it so it's - * not paranoid enough ... - */ - if (ioc3_is_menet(pdev) && pci_slot(pdev->devfn) == 3) - return; - - /* switch ioc3 to pio mode. it probably already was but let's be - * paranoid - */ - writel(gpcr_uarta_modesel | gpcr_uartb_modesel, &ioc3->gpcr_s); - readl(&ioc3->gpcr_s); - writel(0, &ioc3->gppr[6]); - readl(&ioc3->gppr[6]); - writel(0, &ioc3->gppr[7]); - readl(&ioc3->gppr[7]); - writel(readl(&ioc3->port_a.sscr) & ~sscr_dma_en, &ioc3->port_a.sscr); - readl(&ioc3->port_a.sscr); - writel(readl(&ioc3->port_b.sscr) & ~sscr_dma_en, &ioc3->port_b.sscr); - readl(&ioc3->port_b.sscr); - /* disable all sa/b interrupts except for sa/b_int in sio_iec. */ - sio_iec = readl(&ioc3->sio_iec); - sio_iec &= ~(sio_ir_sa_tx_mt | sio_ir_sa_rx_full | - sio_ir_sa_rx_high | sio_ir_sa_rx_timer | - sio_ir_sa_delta_dcd | sio_ir_sa_delta_cts | - sio_ir_sa_tx_explicit | sio_ir_sa_memerr); - sio_iec |= sio_ir_sa_int; - sio_iec &= ~(sio_ir_sb_tx_mt | sio_ir_sb_rx_full | - sio_ir_sb_rx_high | sio_ir_sb_rx_timer | - sio_ir_sb_delta_dcd | sio_ir_sb_delta_cts | - sio_ir_sb_tx_explicit | sio_ir_sb_memerr); - sio_iec |= sio_ir_sb_int; - writel(sio_iec, &ioc3->sio_iec); - writel(0, &ioc3->port_a.sscr); - writel(0, &ioc3->port_b.sscr); - - ioc3_8250_register(&ioc3->sregs.uarta); - ioc3_8250_register(&ioc3->sregs.uartb); -} -#endif - -static int ioc3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) +static int ioc3eth_probe(struct platform_device *pdev) - unsigned int sw_physid1, sw_physid2; - struct net_device *dev = null; + u32 sw_physid1, sw_physid2, vendor, model, rev; - struct ioc3 *ioc3; - unsigned long ioc3_base, ioc3_size; - u32 vendor, model, rev; + struct net_device *dev; + struct resource *regs; + u8 mac_addr[6]; - /* configure dma attributes. */ - err = dma_set_mask_and_coherent(&pdev->dev, dma_bit_mask(64)); - if (err) { - pr_err("%s: no usable dma configuration, aborting. ", - pci_name(pdev)); - goto out; - } - - if (pci_enable_device(pdev)) - return -enodev; + regs = platform_get_resource(pdev, ioresource_mem, 0); + /* get mac addr from one wire prom */ + if (ioc3eth_get_mac_addr(regs, mac_addr)) + return -eprobe_defer; /* not available yet */ - if (!dev) { - err = -enomem; - goto out_disable; - } - - err = pci_request_regions(pdev, "ioc3"); - if (err) - goto out_free; + if (!dev) + return -enomem; - ip->dev = dev; - ip->dma_dev = &pdev->dev; - - dev->irq = pdev->irq; + ip->dma_dev = pdev->dev.parent; + ip->regs = devm_platform_ioremap_resource(pdev, 0); + if (!ip->regs) { + err = -enomem; + goto out_free; + } - ioc3_base = pci_resource_start(pdev, 0); - ioc3_size = pci_resource_len(pdev, 0); - ioc3 = (struct ioc3 *)ioremap(ioc3_base, ioc3_size); - if (!ioc3) { - pr_err("ioc3eth(%s): ioremap failed, goodbye. ", - pci_name(pdev)); + ip->ssram = devm_platform_ioremap_resource(pdev, 1); + if (!ip->ssram) { - goto out_res; + goto out_free; - ip->regs = &ioc3->eth; - ip->ssram = ioc3->ssram; - ip->all_regs = ioc3; -#ifdef config_serial_8250 - ioc3_serial_probe(pdev, ioc3); -#endif + dev->irq = platform_get_irq(pdev, 0); + if (dev->irq < 0) { + err = dev->irq; + goto out_free; + } + + if (devm_request_irq(&pdev->dev, dev->irq, ioc3_interrupt, + irqf_shared, "ioc3-eth", dev)) { + dev_err(&pdev->dev, "can't get irq %d ", dev->irq); + err = -enodev; + goto out_free; + } - ip->pdev = pdev; - - pr_err("ioc3-eth(%s): didn't find a phy, goodbye. ", - pci_name(pdev)); + netdev_err(dev, "didn't find a phy, goodbye. "); - ioc3_get_eaddr(ip); + memcpy(dev->dev_addr, mac_addr, eth_alen); -out_res: - pci_release_regions(pdev); -out_disable: - /* we should call pci_disable_device(pdev); here if the ioc3 wasn't - * such a weird device ... - */ -out: -static void ioc3_remove_one(struct pci_dev *pdev) +static int ioc3eth_remove(struct platform_device *pdev) - struct net_device *dev = pci_get_drvdata(pdev); + struct net_device *dev = platform_get_drvdata(pdev); - - iounmap(ip->all_regs); - pci_release_regions(pdev); - /* we should call pci_disable_device(pdev); here if the ioc3 wasn't - * such a weird device ... - */ -} -static const struct pci_device_id ioc3_pci_tbl[] = { - { pci_vendor_id_sgi, pci_device_id_sgi_ioc3, pci_any_id, pci_any_id }, - { 0 } -}; -module_device_table(pci, ioc3_pci_tbl); + return 0; +} -static struct pci_driver ioc3_driver = { - .name = "ioc3-eth", - .id_table = ioc3_pci_tbl, - .probe = ioc3_probe, - .remove = ioc3_remove_one, -}; - struct ioc3_private *ip = netdev_priv(dev); - - strlcpy(info->bus_info, pci_name(ip->pdev), sizeof(info->bus_info)); + strlcpy(info->bus_info, pci_name(to_pci_dev(dev->dev.parent)), + sizeof(info->bus_info)); -module_pci_driver(ioc3_driver); +static struct platform_driver ioc3eth_driver = { + .probe = ioc3eth_probe, + .remove = ioc3eth_remove, + .driver = { + .name = "ioc3-eth", + } +}; + +module_platform_driver(ioc3eth_driver); + diff --git a/drivers/tty/serial/8250/8250_ioc3.c b/drivers/tty/serial/8250/8250_ioc3.c --- /dev/null +++ b/drivers/tty/serial/8250/8250_ioc3.c +// spdx-license-identifier: gpl-2.0 +/* + * sgi ioc3 8250 uart driver + * + * copyright (c) 2019 thomas bogendoerfer <tbogendoerfer@suse.de> + * + * based on code copyright (c) 2005 stanislaw skowronek <skylark@unaligned.org> + * copyright (c) 2014 joshua kinard <kumba@gentoo.org> + */ + +#include <linux/module.h> +#include <linux/errno.h> +#include <linux/io.h> +#include <linux/platform_device.h> + +#include "8250.h" + +#define ioc3_uartclk (22000000 / 3) + +struct ioc3_8250_data { + int line; +}; + +static unsigned int ioc3_serial_in(struct uart_port *p, int offset) +{ + return readb(p->membase + (offset ^ 3)); +} + +static void ioc3_serial_out(struct uart_port *p, int offset, int value) +{ + writeb(value, p->membase + (offset ^ 3)); +} + +static int serial8250_ioc3_probe(struct platform_device *pdev) +{ + struct ioc3_8250_data *data; + struct uart_8250_port up; + struct resource *r; + void __iomem *membase; + int irq, line; + + r = platform_get_resource(pdev, ioresource_mem, 0); + if (!r) + return -enodev; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), gfp_kernel); + if (!data) + return -enomem; + + membase = devm_ioremap_nocache(&pdev->dev, r->start, resource_size(r)); + if (!membase) + return -enomem; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + irq = 0; /* no interrupt -> use polling */ + + /* register serial ports with 8250.c */ + memset(&up, 0, sizeof(struct uart_8250_port)); + up.port.iotype = upio_mem; + up.port.uartclk = ioc3_uartclk; + up.port.type = port_16550a; + up.port.irq = irq; + up.port.flags = (upf_boot_autoconf | upf_share_irq); + up.port.dev = &pdev->dev; + up.port.membase = membase; + up.port.mapbase = r->start; + up.port.serial_in = ioc3_serial_in; + up.port.serial_out = ioc3_serial_out; + line = serial8250_register_8250_port(&up); + if (line < 0) + return line; + + platform_set_drvdata(pdev, data); + return 0; +} + +static int serial8250_ioc3_remove(struct platform_device *pdev) +{ + struct ioc3_8250_data *data = platform_get_drvdata(pdev); + + serial8250_unregister_port(data->line); + return 0; +} + +static struct platform_driver serial8250_ioc3_driver = { + .probe = serial8250_ioc3_probe, + .remove = serial8250_ioc3_remove, + .driver = { + .name = "ioc3-serial8250", + } +}; + +module_platform_driver(serial8250_ioc3_driver); + +module_author("thomas bogendoerfer <tbogendoerfer@suse.de>"); +module_description("sgi ioc3 8250 uart driver"); +module_license("gpl"); diff --git a/drivers/tty/serial/8250/kconfig b/drivers/tty/serial/8250/kconfig --- a/drivers/tty/serial/8250/kconfig +++ b/drivers/tty/serial/8250/kconfig +config serial_8250_ioc3 + tristate "sgi ioc3 8250 uart support" + depends on sgi_mfd_ioc3 && serial_8250 + select serial_8250_extended + select serial_8250_share_irq + help + enable this if you have a sgi origin or octane machine. this module + provides basic serial support by directly driving the uart chip + behind the ioc3 device on those systems. maximum baud speed is + 38400bps using this driver. + diff --git a/drivers/tty/serial/8250/makefile b/drivers/tty/serial/8250/makefile --- a/drivers/tty/serial/8250/makefile +++ b/drivers/tty/serial/8250/makefile +obj-$(config_serial_8250_ioc3) += 8250_ioc3.o
|
Multi Function Devices (MFD)
|
0ce5ebd24d25f02c73940f047b12733d84b125e8
|
thomas bogendoerfer
|
drivers
|
mfd
|
8250, ethernet, serial, sgi, sgi-ip27
|
mfd: wcd934x: add support to wcd9340/wcd9341 codec
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qualcomm wcd9340/wcd9341 codec is a standalone hi-fi audio codec ic.
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this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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add support to wcd9340/wcd9341 codec
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
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['wcd934x']
|
['c', 'kconfig', 'makefile', 'h']
| 5
| 881
| 0
|
--- diff --git a/drivers/mfd/kconfig b/drivers/mfd/kconfig --- a/drivers/mfd/kconfig +++ b/drivers/mfd/kconfig +config mfd_wcd934x + tristate "support for wcd9340/wcd9341 codec" + depends on slimbus + select regmap + select regmap_slimbus + select regmap_irq + select mfd_core + help + support for the qualcomm wcd9340/wcd9341 codec. + this driver provides common support wcd934x audio codec and its + associated pin controller, soundwire controller and audio codec. + diff --git a/drivers/mfd/makefile b/drivers/mfd/makefile --- a/drivers/mfd/makefile +++ b/drivers/mfd/makefile +obj-$(config_mfd_wcd934x) += wcd934x.o diff --git a/drivers/mfd/wcd934x.c b/drivers/mfd/wcd934x.c --- /dev/null +++ b/drivers/mfd/wcd934x.c +// spdx-license-identifier: gpl-2.0 +// copyright (c) 2019, linaro limited + +#include <linux/clk.h> +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/mfd/core.h> +#include <linux/mfd/wcd934x/registers.h> +#include <linux/mfd/wcd934x/wcd934x.h> +#include <linux/module.h> +#include <linux/of_gpio.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/regulator/consumer.h> +#include <linux/slimbus.h> + +static const struct mfd_cell wcd934x_devices[] = { + { + .name = "wcd934x-codec", + }, { + .name = "wcd934x-gpio", + .of_compatible = "qcom,wcd9340-gpio", + }, { + .name = "wcd934x-soundwire", + .of_compatible = "qcom,soundwire-v1.3.0", + }, +}; + +static const struct regmap_irq wcd934x_irqs[] = { + [wcd934x_irq_slimbus] = { + .reg_offset = 0, + .mask = bit(0), + .type = { + .type_reg_offset = 0, + .types_supported = irq_type_edge_both, + .type_reg_mask = bit(0), + .type_level_low_val = bit(0), + .type_level_high_val = bit(0), + .type_falling_val = 0, + .type_rising_val = 0, + }, + }, + [wcd934x_irq_soundwire] = { + .reg_offset = 2, + .mask = bit(4), + .type = { + .type_reg_offset = 2, + .types_supported = irq_type_edge_both, + .type_reg_mask = bit(4), + .type_level_low_val = bit(4), + .type_level_high_val = bit(4), + .type_falling_val = 0, + .type_rising_val = 0, + }, + }, +}; + +static const struct regmap_irq_chip wcd934x_regmap_irq_chip = { + .name = "wcd934x_irq", + .status_base = wcd934x_intr_pin1_status0, + .mask_base = wcd934x_intr_pin1_mask0, + .ack_base = wcd934x_intr_pin1_clear0, + .type_base = wcd934x_intr_level0, + .num_type_reg = 4, + .type_in_mask = false, + .num_regs = 4, + .irqs = wcd934x_irqs, + .num_irqs = array_size(wcd934x_irqs), +}; + +static bool wcd934x_is_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case wcd934x_intr_pin1_status0...wcd934x_intr_pin2_clear3: + case wcd934x_swr_ahb_bridge_rd_data_0: + case wcd934x_swr_ahb_bridge_rd_data_1: + case wcd934x_swr_ahb_bridge_rd_data_2: + case wcd934x_swr_ahb_bridge_rd_data_3: + case wcd934x_swr_ahb_bridge_access_status: + case wcd934x_ana_mbhc_result_3: + case wcd934x_ana_mbhc_result_2: + case wcd934x_ana_mbhc_result_1: + case wcd934x_ana_mbhc_mech: + case wcd934x_ana_mbhc_elect: + case wcd934x_ana_mbhc_zdet: + case wcd934x_ana_micb2: + case wcd934x_ana_rco: + case wcd934x_ana_bias: + return true; + default: + return false; + } +}; + +static const struct regmap_range_cfg wcd934x_ranges[] = { + { .name = "wcd934x", + .range_min = 0x0, + .range_max = wcd934x_max_register, + .selector_reg = wcd934x_sel_register, + .selector_mask = wcd934x_sel_mask, + .selector_shift = wcd934x_sel_shift, + .window_start = wcd934x_window_start, + .window_len = wcd934x_window_length, + }, +}; + +static struct regmap_config wcd934x_regmap_config = { + .reg_bits = 16, + .val_bits = 8, + .cache_type = regcache_rbtree, + .max_register = 0xffff, + .can_multi_write = true, + .ranges = wcd934x_ranges, + .num_ranges = array_size(wcd934x_ranges), + .volatile_reg = wcd934x_is_volatile_register, +}; + +static int wcd934x_bring_up(struct wcd934x_ddata *ddata) +{ + struct regmap *regmap = ddata->regmap; + u16 id_minor, id_major; + int ret; + + ret = regmap_bulk_read(regmap, wcd934x_chip_tier_ctrl_chip_id_byte0, + (u8 *)&id_minor, sizeof(u16)); + if (ret) + return ret; + + ret = regmap_bulk_read(regmap, wcd934x_chip_tier_ctrl_chip_id_byte2, + (u8 *)&id_major, sizeof(u16)); + if (ret) + return ret; + + dev_info(ddata->dev, "wcd934x chip id major 0x%x, minor 0x%x ", + id_major, id_minor); + + regmap_write(regmap, wcd934x_codec_rpm_rst_ctl, 0x01); + regmap_write(regmap, wcd934x_sido_new_vout_a_startup, 0x19); + regmap_write(regmap, wcd934x_sido_new_vout_d_startup, 0x15); + /* add 1msec delay for vout to settle */ + usleep_range(1000, 1100); + regmap_write(regmap, wcd934x_codec_rpm_pwr_cdc_dig_hm_ctl, 0x5); + regmap_write(regmap, wcd934x_codec_rpm_pwr_cdc_dig_hm_ctl, 0x7); + regmap_write(regmap, wcd934x_codec_rpm_rst_ctl, 0x3); + regmap_write(regmap, wcd934x_codec_rpm_rst_ctl, 0x7); + regmap_write(regmap, wcd934x_codec_rpm_pwr_cdc_dig_hm_ctl, 0x3); + + return 0; +} + +static int wcd934x_slim_status_up(struct slim_device *sdev) +{ + struct device *dev = &sdev->dev; + struct wcd934x_ddata *ddata; + int ret; + + ddata = dev_get_drvdata(dev); + + ddata->regmap = regmap_init_slimbus(sdev, &wcd934x_regmap_config); + if (is_err(ddata->regmap)) { + dev_err(dev, "error allocating slim regmap "); + return ptr_err(ddata->regmap); + } + + ret = wcd934x_bring_up(ddata); + if (ret) { + dev_err(dev, "failed to bring up wcd934x: err = %d ", ret); + return ret; + } + + ret = devm_regmap_add_irq_chip(dev, ddata->regmap, ddata->irq, + irqf_trigger_high, 0, + &wcd934x_regmap_irq_chip, + &ddata->irq_data); + if (ret) { + dev_err(dev, "failed to add irq chip: err = %d ", ret); + return ret; + } + + ret = mfd_add_devices(dev, platform_devid_auto, wcd934x_devices, + array_size(wcd934x_devices), null, 0, null); + if (ret) { + dev_err(dev, "failed to add child devices: err = %d ", + ret); + return ret; + } + + return ret; +} + +static int wcd934x_slim_status(struct slim_device *sdev, + enum slim_device_status status) +{ + switch (status) { + case slim_device_status_up: + return wcd934x_slim_status_up(sdev); + case slim_device_status_down: + mfd_remove_devices(&sdev->dev); + break; + default: + return -einval; + } + + return 0; +} + +static int wcd934x_slim_probe(struct slim_device *sdev) +{ + struct device *dev = &sdev->dev; + struct device_node *np = dev->of_node; + struct wcd934x_ddata *ddata; + int reset_gpio, ret; + + ddata = devm_kzalloc(dev, sizeof(*ddata), gfp_kernel); + if (!ddata) + return -enomem; + + ddata->irq = of_irq_get(np, 0); + if (ddata->irq < 0) { + if (ddata->irq != -eprobe_defer) + dev_err(ddata->dev, "failed to get irq: err = %d ", + ddata->irq); + return ddata->irq; + } + + reset_gpio = of_get_named_gpio(np, "reset-gpios", 0); + if (reset_gpio < 0) { + dev_err(dev, "failed to get reset gpio: err = %d ", + reset_gpio); + return reset_gpio; + } + + ddata->extclk = devm_clk_get(dev, "extclk"); + if (is_err(ddata->extclk)) { + dev_err(dev, "failed to get extclk"); + return ptr_err(ddata->extclk); + } + + ddata->supplies[0].supply = "vdd-buck"; + ddata->supplies[1].supply = "vdd-buck-sido"; + ddata->supplies[2].supply = "vdd-tx"; + ddata->supplies[3].supply = "vdd-rx"; + ddata->supplies[4].supply = "vdd-io"; + + ret = regulator_bulk_get(dev, wcd934x_max_supply, ddata->supplies); + if (ret) { + dev_err(dev, "failed to get supplies: err = %d ", ret); + return ret; + } + + ret = regulator_bulk_enable(wcd934x_max_supply, ddata->supplies); + if (ret) { + dev_err(dev, "failed to enable supplies: err = %d ", ret); + return ret; + } + + /* + * for wcd934x, it takes about 600us for the vout_a and + * vout_d to be ready after buck_sido is powered up. + * sys_rst_n shouldn't be pulled high during this time + */ + usleep_range(600, 650); + gpio_direction_output(reset_gpio, 0); + msleep(20); + gpio_set_value(reset_gpio, 1); + msleep(20); + + ddata->dev = dev; + dev_set_drvdata(dev, ddata); + + return 0; +} + +static void wcd934x_slim_remove(struct slim_device *sdev) +{ + struct wcd934x_ddata *ddata = dev_get_drvdata(&sdev->dev); + + regulator_bulk_disable(wcd934x_max_supply, ddata->supplies); + mfd_remove_devices(&sdev->dev); + kfree(ddata); +} + +static const struct slim_device_id wcd934x_slim_id[] = { + { slim_manf_id_qcom, slim_prod_code_wcd9340, + slim_dev_idx_wcd9340, slim_dev_instance_id_wcd9340 }, + {} +}; + +static struct slim_driver wcd934x_slim_driver = { + .driver = { + .name = "wcd934x-slim", + }, + .probe = wcd934x_slim_probe, + .remove = wcd934x_slim_remove, + .device_status = wcd934x_slim_status, + .id_table = wcd934x_slim_id, +}; + +module_slim_driver(wcd934x_slim_driver); +module_description("wcd934x slim driver"); +module_license("gpl v2"); +module_alias("slim:217:250:*"); +module_author("srinivas kandagatla <srinivas.kandagatla@linaro.org>"); diff --git a/include/linux/mfd/wcd934x/registers.h b/include/linux/mfd/wcd934x/registers.h --- /dev/null +++ b/include/linux/mfd/wcd934x/registers.h +/* spdx-license-identifier: gpl-2.0 */ + +#ifndef _wcd934x_registers_h +#define _wcd934x_registers_h + +#define wcd934x_codec_rpm_clk_gate 0x0002 +#define wcd934x_codec_rpm_clk_gate_mask genmask(1, 0) +#define wcd934x_codec_rpm_clk_mclk_cfg 0x0003 +#define wcd934x_codec_rpm_clk_mclk_cfg_9p6mhz bit(0) +#define wcd934x_codec_rpm_clk_mclk_cfg_12p288mhz bit(1) +#define wcd934x_codec_rpm_clk_mclk_cfg_mclk_mask genmask(1, 0) +#define wcd934x_codec_rpm_rst_ctl 0x0009 +#define wcd934x_codec_rpm_pwr_cdc_dig_hm_ctl 0x0011 +#define wcd934x_chip_tier_ctrl_chip_id_byte0 0x0021 +#define wcd934x_chip_tier_ctrl_chip_id_byte2 0x0023 +#define wcd934x_chip_tier_ctrl_efuse_ctl 0x0025 +#define wcd934x_efuse_sense_state_mask genmask(4, 1) +#define wcd934x_efuse_sense_state_def 0x10 +#define wcd934x_efuse_sense_en_mask bit(0) +#define wcd934x_efuse_sense_enable bit(0) +#define wcd934x_chip_tier_ctrl_efuse_val_out14 0x0037 +#define wcd934x_chip_tier_ctrl_efuse_val_out15 0x0038 +#define wcd934x_chip_tier_ctrl_efuse_status 0x0039 +#define wcd934x_data_hub_sb_tx10_inp_cfg 0x006b +#define wcd934x_data_hub_sb_tx11_inp_cfg 0x006c +#define wcd934x_data_hub_sb_tx13_inp_cfg 0x006e +#define wcd934x_cpe_fll_config_ctl_2 0x0111 +#define wcd934x_cpe_ss_cparmad_bufrdy_int_period 0x0213 +#define wcd934x_cpe_ss_sva_cfg 0x0214 +#define wcd934x_cpe_ss_dmic0_ctl 0x0218 +#define wcd934x_cpe_ss_dmic1_ctl 0x0219 +#define wcd934x_dmic_rate_mask genmask(3, 1) +#define wcd934x_cpe_ss_dmic2_ctl 0x021a +#define wcd934x_cpe_ss_dmic_cfg 0x021b +#define wcd934x_cpe_ss_dmic_cfg 0x021b +#define wcd934x_cpe_ss_cpar_cfg 0x021c +#define wcd934x_intr_pin1_mask0 0x0409 +#define wcd934x_intr_pin1_status0 0x0411 +#define wcd934x_intr_pin1_clear0 0x0419 +#define wcd934x_intr_pin2_clear3 0x0434 +#define wcd934x_intr_level0 0x0461 +/* intr_reg 0 */ +#define wcd934x_irq_slimbus 0 +#define wcd934x_irq_misc 1 +#define wcd934x_irq_hph_pa_ocpl_fault 2 +#define wcd934x_irq_hph_pa_ocpr_fault 3 +#define wcd934x_irq_ear_pa_ocp_fault 4 +#define wcd934x_irq_hph_pa_cnpl_complete 5 +#define wcd934x_irq_hph_pa_cnpr_complete 6 +#define wcd934x_irq_ear_pa_cnp_complete 7 +/* intr_reg 1 */ +#define wcd934x_irq_mbhc_sw_det 8 +#define wcd934x_irq_mbhc_elect_ins_rem_det 9 +#define wcd934x_irq_mbhc_button_press_det 10 +#define wcd934x_irq_mbhc_button_release_det 11 +#define wcd934x_irq_mbhc_elect_ins_rem_leg_det 12 +#define wcd934x_irq_reserved_0 13 +#define wcd934x_irq_reserved_1 14 +#define wcd934x_irq_reserved_2 15 +/* intr_reg 2 */ +#define wcd934x_irq_line_pa1_cnp_complete 16 +#define wcd934x_irq_line_pa2_cnp_complete 17 +#define wcd934x_irq_slnq_analog_error 18 +#define wcd934x_irq_reserved_3 19 +#define wcd934x_irq_soundwire 20 +#define wcd934x_irq_vdd_dig_ramp_complete 21 +#define wcd934x_irq_rco_error 22 +#define wcd934x_irq_cpe_error 23 +/* intr_reg 3 */ +#define wcd934x_irq_mad_audio 24 +#define wcd934x_irq_mad_beacon 25 +#define wcd934x_irq_mad_ultrasound 26 +#define wcd934x_irq_vbat_attack 27 +#define wcd934x_irq_vbat_restore 28 +#define wcd934x_irq_cpe1_intr 29 +#define wcd934x_irq_reserved_4 30 +#define wcd934x_irq_slnq_digital 31 +#define wcd934x_num_irqs 32 +#define wcd934x_ana_bias 0x0601 +#define wcd934x_ana_bias_en_mask bit(7) +#define wcd934x_ana_bias_en bit(7) +#define wcd934x_ana_prechrg_en_mask bit(6) +#define wcd934x_ana_prechrg_en bit(6) +#define wcd934x_ana_prechrg_mode_mask bit(5) +#define wcd934x_ana_prechrg_mode_auto bit(5) +#define wcd934x_ana_rco 0x0603 +#define wcd934x_ana_rco_bg_en_mask bit(7) +#define wcd934x_ana_rco_bg_enable bit(7) +#define wcd934x_ana_buck_ctl 0x0606 +#define wcd934x_ana_buck_hi_accu_pre_enx_mask genmask(1, 0) +#define wcd934x_ana_buck_pre_en2_mask bit(0) +#define wcd934x_ana_buck_pre_en2_enable bit(0) +#define wcd934x_ana_buck_pre_en1_mask bit(1) +#define wcd934x_ana_buck_pre_en1_enable bit(1) +#define wcd934x_ana_buck_hi_accu_en_mask bit(2) +#define wcd934x_ana_buck_hi_accu_enable bit(2) +#define wcd934x_ana_rx_supplies 0x0608 +#define wcd934x_ana_hph 0x0609 +#define wcd934x_ana_ear 0x060a +#define wcd934x_ana_lo_1_2 0x060b +#define wcd934x_ana_amic1 0x060e +#define wcd934x_ana_amic2 0x060f +#define wcd934x_ana_amic3 0x0610 +#define wcd934x_ana_amic4 0x0611 +#define wcd934x_ana_mbhc_mech 0x0614 +#define wcd934x_ana_mbhc_elect 0x0615 +#define wcd934x_ana_mbhc_zdet 0x0616 +#define wcd934x_ana_mbhc_result_1 0x0617 +#define wcd934x_ana_mbhc_result_2 0x0618 +#define wcd934x_ana_mbhc_result_3 0x0619 +#define wcd934x_ana_micb1 0x0622 +#define wcd934x_micb_val_mask genmask(5, 0) +#define wcd934x_ana_micb_en_mask genmask(7, 6) +#define wcd934x_ana_micb_pull_up 0x80 +#define wcd934x_ana_micb_enable 0x40 +#define wcd934x_ana_micb_disable 0x0 +#define wcd934x_ana_micb2 0x0623 +#define wcd934x_ana_micb3 0x0625 +#define wcd934x_ana_micb4 0x0626 +#define wcd934x_bias_vbg_fine_adj 0x0629 +#define wcd934x_micb1_test_ctl_1 0x066b +#define wcd934x_micb1_test_ctl_2 0x066c +#define wcd934x_micb2_test_ctl_1 0x066e +#define wcd934x_micb3_test_ctl_1 0x0671 +#define wcd934x_micb4_test_ctl_1 0x0674 +#define wcd934x_classh_mode_1 0x0697 +#define wcd934x_classh_mode_2 0x0698 +#define wcd934x_classh_mode_3 0x0699 +#define wcd934x_classh_ctrl_vcl_1 0x069a +#define wcd934x_classh_ctrl_vcl_2 0x069b +#define wcd934x_classh_ctrl_ccl_1 0x069c +#define wcd934x_classh_ctrl_ccl_2 0x069d +#define wcd934x_classh_ctrl_ccl_3 0x069e +#define wcd934x_classh_ctrl_ccl_4 0x069f +#define wcd934x_classh_ctrl_ccl_5 0x06a0 +#define wcd934x_classh_buck_tmux_a_d 0x06a1 +#define wcd934x_classh_buck_sw_drv_cntl 0x06a2 +#define wcd934x_rx_ocp_ctl 0x06b6 +#define wcd934x_rx_ocp_count 0x06b7 +#define wcd934x_hph_cnp_en 0x06cb +#define wcd934x_hph_cnp_wg_ctl 0x06cc +#define wcd934x_hph_gm3_boost_en_mask bit(7) +#define wcd934x_hph_gm3_boost_enable bit(7) +#define wcd934x_hph_ocp_ctl 0x06ce +#define wcd934x_hph_l_en 0x06d3 +#define wcd934x_hph_gain_src_sel_mask bit(5) +#define wcd934x_hph_gain_src_sel_compander 0 +#define wcd934x_hph_gain_src_sel_register bit(5) +#define wcd934x_hph_l_test 0x06d4 +#define wcd934x_hph_r_en 0x06d6 +#define wcd934x_hph_r_test 0x06d7 +#define wcd934x_hph_ocp_det_mask bit(0) +#define wcd934x_hph_ocp_det_enable bit(0) +#define wcd934x_hph_ocp_det_disable 0 +#define wcd934x_diff_lo_lo2_compander 0x06ea +#define wcd934x_diff_lo_lo1_compander 0x06eb +#define wcd934x_clk_sys_mclk_prg 0x0711 +#define wcd934x_ext_clk_buf_en_mask bit(7) +#define wcd934x_ext_clk_buf_en bit(7) +#define wcd934x_ext_clk_div_ratio_mask genmask(5, 4) +#define wcd934x_ext_clk_div_by_2 0x10 +#define wcd934x_mclk_src_mask bit(1) +#define wcd934x_mclk_src_ext_clk 0 +#define wcd934x_mclk_src_mask bit(1) +#define wcd934x_mclk_en_mask bit(0) +#define wcd934x_mclk_en bit(0) +#define wcd934x_clk_sys_mclk2_prg1 0x0712 +#define wcd934x_clk_sys_mclk2_prg2 0x0713 +#define wcd934x_sido_new_vout_a_startup 0x071b +#define wcd934x_sido_new_vout_d_startup 0x071c +#define wcd934x_sido_new_vout_d_freq1 0x071d +#define wcd934x_sido_new_vout_d_freq2 0x071e +#define wcd934x_sido_ripple_freq_en_mask bit(0) +#define wcd934x_sido_ripple_freq_enable bit(0) +#define wcd934x_mbhc_new_ctl_2 0x0721 +#define wcd934x_tx_new_amic_4_5_sel 0x0727 +#define wcd934x_hph_new_int_rdac_hd2_ctl_l 0x0733 +#define wcd934x_hph_new_int_rdac_override_ctl 0x0735 +#define wcd934x_hph_new_int_rdac_hd2_ctl_r 0x0736 +#define wcd934x_hph_new_int_hph_timer1 0x073a +#define wcd934x_hph_autochop_timer_en_mask bit(1) +#define wcd934x_hph_autochop_timer_enable bit(1) +#define wcd934x_cdc_tx0_tx_path_ctl 0x0a31 +#define wcd934x_cdc_tx_path_ctl_pcm_rate_mask genmask(3, 0) +#define wcd934x_cdc_tx_path_ctl(dec) (0xa31 + dec * 0x10) +#define wcd934x_cdc_tx0_tx_path_cfg0 0x0a32 +#define wcd934x_cdc_tx0_tx_path_cfg1 0x0a33 +#define wcd934x_cdc_tx0_tx_vol_ctl 0x0a34 +#define wcd934x_cdc_tx0_tx_path_192_ctl 0x0a35 +#define wcd934x_cdc_tx0_tx_path_192_cfg 0x0a36 +#define wcd934x_cdc_tx0_tx_path_sec2 0x0a39 +#define wcd934x_hph_cutoff_freq_change_req_mask bit(1) +#define wcd934x_hph_cutoff_freq_change_req bit(1) +#define wcd934x_cdc_tx1_tx_path_ctl 0x0a41 +#define wcd934x_cdc_tx1_tx_path_cfg0 0x0a42 +#define wcd934x_cdc_tx1_tx_path_cfg1 0x0a43 +#define wcd934x_cdc_tx1_tx_vol_ctl 0x0a44 +#define wcd934x_cdc_tx2_tx_path_ctl 0x0a51 +#define wcd934x_cdc_tx2_tx_path_cfg0 0x0a52 +#define wcd934x_cdc_tx2_tx_path_cfg1 0x0a53 +#define wcd934x_cdc_tx2_tx_vol_ctl 0x0a54 +#define wcd934x_cdc_tx3_tx_path_ctl 0x0a61 +#define wcd934x_cdc_tx3_tx_path_cfg0 0x0a62 +#define wcd934x_cdc_tx3_tx_path_cfg1 0x0a63 +#define wcd934x_cdc_tx3_tx_vol_ctl 0x0a64 +#define wcd934x_cdc_tx3_tx_path_192_ctl 0x0a65 +#define wcd934x_cdc_tx3_tx_path_192_cfg 0x0a66 +#define wcd934x_cdc_tx4_tx_path_ctl 0x0a71 +#define wcd934x_cdc_tx4_tx_path_cfg0 0x0a72 +#define wcd934x_cdc_tx4_tx_path_cfg1 0x0a73 +#define wcd934x_cdc_tx4_tx_vol_ctl 0x0a74 +#define wcd934x_cdc_tx4_tx_path_192_ctl 0x0a75 +#define wcd934x_cdc_tx4_tx_path_192_cfg 0x0a76 +#define wcd934x_cdc_tx5_tx_path_ctl 0x0a81 +#define wcd934x_cdc_tx5_tx_path_cfg0 0x0a82 +#define wcd934x_cdc_tx5_tx_path_cfg1 0x0a83 +#define wcd934x_cdc_tx5_tx_vol_ctl 0x0a84 +#define wcd934x_cdc_tx5_tx_path_192_ctl 0x0a85 +#define wcd934x_cdc_tx5_tx_path_192_cfg 0x0a86 +#define wcd934x_cdc_tx6_tx_path_ctl 0x0a91 +#define wcd934x_cdc_tx6_tx_path_cfg0 0x0a92 +#define wcd934x_cdc_tx6_tx_path_cfg1 0x0a93 +#define wcd934x_cdc_tx6_tx_vol_ctl 0x0a94 +#define wcd934x_cdc_tx6_tx_path_192_ctl 0x0a95 +#define wcd934x_cdc_tx6_tx_path_192_cfg 0x0a96 +#define wcd934x_cdc_tx7_tx_path_ctl 0x0aa1 +#define wcd934x_cdc_tx7_tx_path_cfg0 0x0aa2 +#define wcd934x_cdc_tx7_tx_path_cfg1 0x0aa3 +#define wcd934x_cdc_tx7_tx_vol_ctl 0x0aa4 +#define wcd934x_cdc_tx7_tx_path_192_ctl 0x0aa5 +#define wcd934x_cdc_tx7_tx_path_192_cfg 0x0aa6 +#define wcd934x_cdc_tx8_tx_path_ctl 0x0ab1 +#define wcd934x_cdc_tx8_tx_path_cfg0 0x0ab2 +#define wcd934x_cdc_tx8_tx_path_cfg1 0x0ab3 +#define wcd934x_cdc_tx8_tx_vol_ctl 0x0ab4 +#define wcd934x_cdc_tx8_tx_path_192_ctl 0x0ab5 +#define wcd934x_cdc_tx8_tx_path_192_cfg 0x0ab6 +#define wcd934x_cdc_tx9_spkr_prot_path_cfg0 0x0ac3 +#define wcd934x_cdc_tx10_spkr_prot_path_cfg0 0x0ac7 +#define wcd934x_cdc_tx11_spkr_prot_path_cfg0 0x0acb +#define wcd934x_cdc_tx12_spkr_prot_path_cfg0 0x0acf +#define wcd934x_cdc_compander1_ctl0 0x0b01 +#define wcd934x_comp_clk_en_mask bit(0) +#define wcd934x_comp_clk_enable bit(0) +#define wcd934x_comp_soft_rst_mask bit(1) +#define wcd934x_comp_soft_rst_enable bit(1) +#define wcd934x_comp_halt_mask bit(2) +#define wcd934x_comp_halt bit(2) +#define wcd934x_comp_soft_rst_disable 0 +#define wcd934x_cdc_compander1_ctl7 0x0b08 +#define wcd934x_hph_low_pwr_mode_en_mask bit(5) +#define wcd934x_cdc_compander2_ctl7 0x0b10 +#define wcd934x_cdc_compander7_ctl3 0x0b34 +#define wcd934x_cdc_compander7_ctl7 0x0b38 +#define wcd934x_cdc_compander8_ctl3 0x0b3c +#define wcd934x_cdc_compander8_ctl7 0x0b40 +#define wcd934x_cdc_rx0_rx_path_ctl 0x0b41 +#define wcd934x_cdc_rx_pga_mute_en_mask bit(4) +#define wcd934x_cdc_rx_pga_mute_enable bit(4) +#define wcd934x_cdc_rx_pga_mute_disable 0 +#define wcd934x_rx_clk_en_mask bit(5) +#define wcd934x_rx_clk_enable bit(5) +#define wcd934x_rx_reset_mask bit(6) +#define wcd934x_rx_reset_enable bit(6) +#define wcd934x_rx_reset_disable 0 +#define wcd934x_rx_pcm_rate_mask genmask(3, 0) +#define wcd934x_rx_pcm_rate_f_48k 0x04 +#define wcd934x_cdc_rx_path_ctl(rx) (0xb41 + rx * 0x14) +#define wcd934x_cdc_mix_pcm_rate_mask genmask(3, 0) +#define wcd934x_cdc_rx0_rx_path_cfg0 0x0b42 +#define wcd934x_rx_dly_zn_en_mask bit(3) +#define wcd934x_rx_dly_zn_enable bit(3) +#define wcd934x_rx_dly_zn_disable 0 +#define wcd934x_cdc_rx0_rx_path_cfg1 0x0b43 +#define wcd934x_cdc_rx0_rx_path_cfg2 0x0b44 +#define wcd934x_cdc_rx0_rx_vol_ctl 0x0b45 +#define wcd934x_cdc_rx0_rx_path_mix_ctl 0x0b46 +#define wcd934x_cdc_rx_mix_clk_en_mask bit(5) +#define wcd934x_cdc_rx_mix_clk_enable bit(5) +#define wcd934x_cdc_rx_path_mix_ctl(rx) (0xb46 + rx * 0x14) +#define wcd934x_cdc_rx0_rx_path_mix_cfg 0x0b47 +#define wcd934x_cdc_rx0_rx_vol_mix_ctl 0x0b48 +#define wcd934x_cdc_rx0_rx_path_sec0 0x0b49 +#define wcd934x_cdc_rx0_rx_path_dsmdem_ctl 0x0b53 +#define wcd934x_cdc_rx1_rx_path_ctl 0x0b55 +#define wcd934x_rx_path_pga_mute_en_mask bit(4) +#define wcd934x_rx_path_pga_mute_enable bit(4) +#define wcd934x_cdc_rx_path_pga_mute_disable 0 +#define wcd934x_cdc_rx_path_clk_en_mask bit(5) +#define wcd934x_cdc_rx_path_clk_enable bit(5) +#define wcd934x_cdc_rx_path_clk_disable 0 +#define wcd934x_cdc_rx1_rx_path_cfg0 0x0b56 +#define wcd934x_hph_cmp_en_mask bit(1) +#define wcd934x_hph_cmp_enable bit(1) +#define wcd934x_hph_cmp_disable 0 +#define wcd934x_cdc_rx1_rx_path_cfg2 0x0b58 +#define wcd934x_cdc_rx1_rx_vol_ctl 0x0b59 +#define wcd934x_cdc_rx1_rx_path_mix_ctl 0x0b5a +#define wcd934x_cdc_rx1_rx_path_mix_cfg 0x0b5b +#define wcd934x_cdc_rx1_rx_vol_mix_ctl 0x0b5c +#define wcd934x_cdc_rx1_rx_path_sec0 0x0b5d +#define wcd934x_cdc_rx1_rx_path_sec3 0x0b60 +#define wcd934x_cdc_rx_path_sec_hd2_alpha_mask genmask(5, 2) +#define wcd934x_cdc_rx_path_sec_hd2_alpha_0p3125 0x14 +#define wcd934x_cdc_rx_path_sec_hd2_alpha_0p0000 0 +#define wcd934x_cdc_rx1_rx_path_dsmdem_ctl 0x0b67 +#define wcd934x_cdc_rx2_rx_path_ctl 0x0b69 +#define wcd934x_cdc_rx2_rx_path_cfg0 0x0b6a +#define wcd934x_cdc_rx_path_cfg_hd2_en_mask bit(2) +#define wcd934x_cdc_rx_path_cfg_hd2_enable bit(2) +#define wcd934x_cdc_rx_path_cfg_hd2_disable 0 +#define wcd934x_cdc_rx2_rx_path_cfg2 0x0b6c +#define wcd934x_cdc_rx2_rx_vol_ctl 0x0b6d +#define wcd934x_cdc_rx2_rx_path_mix_ctl 0x0b6e +#define wcd934x_cdc_rx2_rx_path_mix_cfg 0x0b6f +#define wcd934x_cdc_rx2_rx_vol_mix_ctl 0x0b70 +#define wcd934x_cdc_rx2_rx_path_sec0 0x0b71 +#define wcd934x_cdc_rx2_rx_path_sec3 0x0b74 +#define wcd934x_cdc_rx2_rx_path_dsmdem_ctl 0x0b7b +#define wcd934x_cdc_rx3_rx_path_ctl 0x0b7d +#define wcd934x_cdc_rx3_rx_path_cfg0 0x0b6e +#define wcd934x_cdc_rx3_rx_path_cfg2 0x0b80 +#define wcd934x_cdc_rx3_rx_vol_ctl 0x0b81 +#define wcd934x_cdc_rx3_rx_path_mix_ctl 0x0b82 +#define wcd934x_cdc_rx3_rx_path_mix_cfg 0x0b83 +#define wcd934x_cdc_rx3_rx_vol_mix_ctl 0x0b84 +#define wcd934x_cdc_rx3_rx_path_sec0 0x0b85 +#define wcd934x_cdc_rx3_rx_path_dsmdem_ctl 0x0b8f +#define wcd934x_cdc_rx4_rx_path_ctl 0x0b91 +#define wcd934x_cdc_rx4_rx_path_cfg0 0x0b92 +#define wcd934x_cdc_rx4_rx_path_cfg2 0x0b94 +#define wcd934x_cdc_rx4_rx_vol_ctl 0x0b95 +#define wcd934x_cdc_rx4_rx_path_mix_ctl 0x0b96 +#define wcd934x_cdc_rx4_rx_path_mix_cfg 0x0b97 +#define wcd934x_cdc_rx4_rx_vol_mix_ctl 0x0b98 +#define wcd934x_cdc_rx4_rx_path_sec0 0x0b99 +#define wcd934x_cdc_rx4_rx_path_dsmdem_ctl 0x0ba3 +#define wcd934x_cdc_rx7_rx_path_ctl 0x0bcd +#define wcd934x_cdc_rx7_rx_path_cfg0 0x0bce +#define wcd934x_cdc_rx7_rx_path_cfg1 0x0bcf +#define wcd934x_cdc_rx7_rx_path_cfg2 0x0bd0 +#define wcd934x_cdc_rx7_rx_vol_ctl 0x0bd1 +#define wcd934x_cdc_rx7_rx_path_mix_ctl 0x0bd2 +#define wcd934x_cdc_rx7_rx_path_mix_cfg 0x0bd3 +#define wcd934x_cdc_rx7_rx_vol_mix_ctl 0x0bd4 +#define wcd934x_cdc_rx7_rx_path_sec1 0x0bd6 +#define wcd934x_cdc_rx7_rx_path_mix_sec0 0x0bdd +#define wcd934x_cdc_rx7_rx_path_dsmdem_ctl 0x0bdf +#define wcd934x_cdc_rx8_rx_path_ctl 0x0be1 +#define wcd934x_cdc_rx8_rx_path_cfg0 0x0be2 +#define wcd934x_cdc_rx8_rx_path_cfg1 0x0be3 +#define wcd934x_rx_smart_boost_en_mask bit(0) +#define wcd934x_rx_smart_boost_enable bit(0) +#define wcd934x_rx_smart_boost_disable 0 +#define wcd934x_cdc_rx8_rx_path_cfg2 0x0be4 +#define wcd934x_cdc_rx8_rx_vol_ctl 0x0be5 +#define wcd934x_cdc_rx8_rx_path_mix_ctl 0x0be6 +#define wcd934x_cdc_rx8_rx_path_mix_cfg 0x0be7 +#define wcd934x_cdc_rx8_rx_vol_mix_ctl 0x0be8 +#define wcd934x_cdc_rx8_rx_path_sec1 0x0bea +#define wcd934x_cdc_rx8_rx_path_mix_sec0 0x0bf1 +#define wcd934x_cdc_rx8_rx_path_dsmdem_ctl 0x0bf3 +#define wcd934x_cdc_clsh_decay_ctrl 0x0c03 +#define wcd934x_cdc_clsh_k2_msb 0x0c0a +#define wcd934x_cdc_clsh_k2_lsb 0x0c0b +#define wcd934x_cdc_clsh_test0 0x0c0f +#define wcd934x_cdc_boost0_boost_path_ctl 0x0c19 +#define wcd934x_boost_path_clk_en_mask bit(4) +#define wcd934x_boost_path_clk_enable bit(4) +#define wcd934x_boost_path_clk_disable 0 +#define wcd934x_cdc_boost0_boost_ctl 0x0c1a +#define wcd934x_cdc_boost0_boost_cfg1 0x0c1b +#define wcd934x_cdc_boost0_boost_cfg2 0x0c1c +#define wcd934x_cdc_boost1_boost_path_ctl 0x0c21 +#define wcd934x_cdc_boost1_boost_ctl 0x0c22 +#define wcd934x_cdc_boost1_boost_cfg1 0x0c23 +#define wcd934x_cdc_boost1_boost_cfg2 0x0c24 +#define wcd934x_swr_ahb_bridge_rd_data_0 0x0c91 +#define wcd934x_swr_ahb_bridge_rd_data_1 0x0c92 +#define wcd934x_swr_ahb_bridge_rd_data_2 0x0c93 +#define wcd934x_swr_ahb_bridge_rd_data_3 0x0c94 +#define wcd934x_swr_ahb_bridge_access_status 0x0c96 +#define wcd934x_cdc_sidetone_src0_st_src_path_ctl 0x0cb5 +#define wcd934x_cdc_sidetone_src1_st_src_path_ctl 0x0cb9 +#define wcd934x_cdc_rx_inp_mux_rx_int0_cfg0 0x0d01 +#define wcd934x_cdc_rx_inp_mux_rx_int_cfg0(i) (0xd01 + i * 0x2) +#define wcd934x_cdc_rx_inp_mux_rx_int_sel_mask genmask(3, 0) +#define wcd934x_cdc_rx_inp_mux_rx_int0_cfg1 0x0d02 +#define wcd934x_cdc_rx_inp_mux_rx_int_cfg1(i) (0xd02 + i * 0x2) +#define wcd934x_cdc_rx_inp_mux_rx_int1_cfg0 0x0d03 +#define wcd934x_cdc_rx_inp_mux_rx_int1_cfg1 0x0d04 +#define wcd934x_cdc_rx_inp_mux_rx_int2_cfg0 0x0d05 +#define wcd934x_cdc_rx_inp_mux_rx_int2_cfg1 0x0d06 +#define wcd934x_cdc_rx_inp_mux_rx_int3_cfg0 0x0d07 +#define wcd934x_cdc_rx_inp_mux_rx_int3_cfg1 0x0d08 +#define wcd934x_cdc_rx_inp_mux_rx_int4_cfg0 0x0d09 +#define wcd934x_cdc_rx_inp_mux_rx_int4_cfg1 0x0d0a +#define wcd934x_cdc_rx_inp_mux_rx_int7_cfg0 0x0d0f +#define wcd934x_cdc_rx_inp_mux_rx_int7_cfg1 0x0d10 +#define wcd934x_cdc_rx_inp_mux_rx_int8_cfg0 0x0d11 +#define wcd934x_cdc_rx_inp_mux_rx_int8_cfg1 0x0d12 +#define wcd934x_cdc_rx_inp_mux_rx_mix_cfg0 0x0d13 +#define wcd934x_cdc_rx_inp_mux_rx_mix_cfg1 0x0d14 +#define wcd934x_cdc_rx_inp_mux_rx_mix_cfg2 0x0d15 +#define wcd934x_cdc_rx_inp_mux_rx_mix_cfg3 0x0d16 +#define wcd934x_cdc_rx_inp_mux_rx_mix_cfg4 0x0d17 +#define wcd934x_cdc_rx_inp_mux_sidetone_src_cfg0 0x0d18 +#define wcd934x_cdc_rx_inp_mux_sidetone_src_cfg1 0x0d19 +#define wcd934x_cdc_tx_inp_mux_adc_mux0_cfg0 0x0d1d +#define wcd934x_cdc_tx_inp_mux_adc_mux0_cfg1 0x0d1e +#define wcd934x_cdc_tx_inp_mux_adc_mux1_cfg0 0x0d1f +#define wcd934x_cdc_tx_inp_mux_adc_mux1_cfg1 0x0d20 +#define wcd934x_cdc_tx_inp_mux_adc_mux2_cfg0 0x0d21 +#define wcd934x_cdc_tx_inp_mux_adc_mux2_cfg1 0x0d22 +#define wcd934x_cdc_tx_inp_mux_adc_mux3_cfg0 0x0d23 +#define wcd934x_cdc_tx_inp_mux_adc_mux3_cfg1 0x0d25 +#define wcd934x_cdc_tx_inp_mux_adc_mux4_cfg0 0x0d26 +#define wcd934x_cdc_tx_inp_mux_adc_mux5_cfg0 0x0d27 +#define wcd934x_cdc_tx_inp_mux_adc_mux6_cfg0 0x0d28 +#define wcd934x_cdc_tx_inp_mux_adc_mux7_cfg0 0x0d29 +#define wcd934x_cdc_tx_inp_mux_adc_mux8_cfg0 0x0d2a +#define wcd934x_cdc_tx_inp_mux_adc_mux10_cfg0 0x0d2b +#define wcd934x_cdc_tx_inp_mux_adc_mux11_cfg0 0x0d2c +#define wcd934x_cdc_tx_inp_mux_adc_mux12_cfg0 0x0d2d +#define wcd934x_cdc_tx_inp_mux_adc_mux13_cfg0 0x0d2e +#define wcd934x_cdc_sidetone_iir_inp_mux_iir0_mix_cfg0 0x0d31 +#define wcd934x_cdc_sidetone_iir_inp_mux_iir0_mix_cfg1 0x0d32 +#define wcd934x_cdc_sidetone_iir_inp_mux_iir0_mix_cfg2 0x0d33 +#define wcd934x_cdc_sidetone_iir_inp_mux_iir0_mix_cfg3 0x0d34 +#define wcd934x_cdc_sidetone_iir_inp_mux_iir1_mix_cfg0 0x0d35 +#define wcd934x_cdc_sidetone_iir_inp_mux_iir1_mix_cfg1 0x0d36 +#define wcd934x_cdc_sidetone_iir_inp_mux_iir1_mix_cfg2 0x0d37 +#define wcd934x_cdc_sidetone_iir_inp_mux_iir1_mix_cfg3 0x0d38 +#define wcd934x_cdc_if_router_tx_mux_cfg0 0x0d3a +#define wcd934x_cdc_if_router_tx_mux_cfg1 0x0d3b +#define wcd934x_cdc_if_router_tx_mux_cfg2 0x0d3c +#define wcd934x_cdc_if_router_tx_mux_cfg3 0x0d3d +#define wcd934x_cdc_clk_rst_ctrl_mclk_control 0x0d41 +#define wcd934x_cdc_mclk_en_mask bit(0) +#define wcd934x_cdc_mclk_en_enable bit(0) +#define wcd934x_cdc_clk_rst_ctrl_fs_cnt_control 0x0d42 +#define wcd934x_cdc_fs_mclk_cnt_en_mask bit(0) +#define wcd934x_cdc_fs_mclk_cnt_enable bit(0) +#define wcd934x_cdc_clk_rst_ctrl_swr_control 0x0d43 +#define wcd934x_cdc_swr_clk_en_mask bit(0) +#define wcd934x_cdc_swr_clk_enable bit(0) +#define wcd934x_cdc_clk_rst_ctrl_dsd_control 0x0d44 +#define wcd934x_cdc_clk_rst_ctrl_asrc_share_control 0x0d45 +#define wcd934x_cdc_clk_rst_ctrl_gfm_control 0x0d46 +#define wcd934x_cdc_sidetone_iir0_iir_path_ctl 0x0d55 +#define wcd934x_cdc_sidetone_iir0_iir_gain_b1_ctl 0x0d56 +#define wcd934x_cdc_sidetone_iir0_iir_gain_b2_ctl 0x0d57 +#define wcd934x_cdc_sidetone_iir0_iir_gain_b3_ctl 0x0d58 +#define wcd934x_cdc_sidetone_iir0_iir_gain_b4_ctl 0x0d59 +#define wcd934x_cdc_sidetone_iir0_iir_gain_b5_ctl 0x0d5a +#define wcd934x_cdc_sidetone_iir0_iir_gain_b6_ctl 0x0d5b +#define wcd934x_cdc_sidetone_iir0_iir_gain_b7_ctl 0x0d5c +#define wcd934x_cdc_sidetone_iir0_iir_gain_b8_ctl 0x0d5d +#define wcd934x_cdc_sidetone_iir0_iir_ctl 0x0d5e +#define wcd934x_cdc_sidetone_iir0_iir_gain_timer_ctl 0x0d5f +#define wcd934x_cdc_sidetone_iir0_iir_coef_b1_ctl 0x0d60 +#define wcd934x_cdc_sidetone_iir0_iir_coef_b2_ctl 0x0d61 +#define wcd934x_cdc_sidetone_iir1_iir_path_ctl 0x0d65 +#define wcd934x_cdc_sidetone_iir1_iir_gain_b1_ctl 0x0d66 +#define wcd934x_cdc_sidetone_iir1_iir_gain_b2_ctl 0x0d67 +#define wcd934x_cdc_sidetone_iir1_iir_gain_b3_ctl 0x0d68 +#define wcd934x_cdc_sidetone_iir1_iir_gain_b4_ctl 0x0d69 +#define wcd934x_cdc_sidetone_iir1_iir_gain_b5_ctl 0x0d6a +#define wcd934x_cdc_sidetone_iir1_iir_gain_b6_ctl 0x0d6b +#define wcd934x_cdc_sidetone_iir1_iir_gain_b7_ctl 0x0d6c +#define wcd934x_cdc_sidetone_iir1_iir_gain_b8_ctl 0x0d6d +#define wcd934x_cdc_sidetone_iir1_iir_ctl 0x0d6e +#define wcd934x_cdc_sidetone_iir1_iir_gain_timer_ctl 0x0d6f +#define wcd934x_cdc_sidetone_iir1_iir_coef_b1_ctl 0x0d70 +#define wcd934x_cdc_sidetone_iir1_iir_coef_b2_ctl 0x0d71 +#define wcd934x_cdc_top_top_cfg1 0x0d82 +#define wcd934x_cdc_top_top_cfg7 0x0d88 +#define wcd934x_cdc_top_hphl_comp_lut 0x0d8b +#define wcd934x_cdc_top_hphr_comp_lut 0x0d90 +#define wcd934x_hph_lut_bypass_mask bit(7) +#define wcd934x_hph_lut_bypass_enable bit(7) +#define wcd934x_hph_lut_bypass_disable 0 +#define wcd934x_codec_cpr_wr_data_0 0x5001 +#define wcd934x_codec_cpr_wr_addr_0 0x5005 +#define wcd934x_codec_cpr_svs_cx_vdd 0x5022 +#define wcd934x_codec_cpr_svs2_cx_vdd 0x5023 +#define wcd934x_codec_cpr_svs2_min_cx_vdd 0x5027 +#define wcd934x_tlmm_dmic1_clk_pincfg 0x8015 +#define wcd934x_tlmm_dmic1_data_pincfg 0x8016 +#define wcd934x_tlmm_dmic2_clk_pincfg 0x8017 +#define wcd934x_tlmm_dmic2_data_pincfg 0x8018 +#define wcd934x_tlmm_dmic3_clk_pincfg 0x8019 +#define wcd934x_tlmm_dmic3_data_pincfg 0x801a +#define wcd934x_test_debug_pad_drvctl_0 0x803b +#define wcd934x_test_debug_npl_dly_test_1 0x803e + +#define wcd934x_max_register 0xffff +#define wcd934x_sel_register 0x800 +#define wcd934x_sel_mask 0xff +#define wcd934x_sel_shift 0x0 +#define wcd934x_window_start 0x800 +#define wcd934x_window_length 0x100 + +/* slimbus slave registers */ +#define wcd934x_slim_pgd_port_int_en0 0x30 +#define wcd934x_slim_pgd_port_int_status_rx_0 0x34 +#define wcd934x_slim_pgd_port_int_status_rx_1 0x35 +#define wcd934x_slim_pgd_port_int_status_tx_0 0x36 +#define wcd934x_slim_pgd_port_int_status_tx_1 0x37 +#define wcd934x_slim_pgd_port_int_clr_rx_0 0x38 +#define wcd934x_slim_pgd_port_int_clr_rx_1 0x39 +#define wcd934x_slim_pgd_port_int_clr_tx_0 0x3a +#define wcd934x_slim_pgd_port_int_clr_tx_1 0x3b +#define wcd934x_slim_pgd_port_int_rx_source0 0x60 +#define wcd934x_slim_pgd_port_int_tx_source0 0x70 +#define wcd934x_slim_pgd_rx_port_cfg(p) (0x30 + p) +#define wcd934x_slim_pgd_port_cfg(p) (0x40 + p) +#define wcd934x_slim_pgd_tx_port_cfg(p) (0x50 + p) +#define wcd934x_slim_pgd_port_int_src(p) (0x60 + p) +#define wcd934x_slim_pgd_port_int_status(p) (0x80 + p) +#define wcd934x_slim_pgd_tx_port_multi_chnl_0(p) (0x100 + 4 * p) +/* ports range from 10-16 */ +#define wcd934x_slim_pgd_tx_port_multi_chnl_1(p) (0x101 + 4 * p) +#define wcd934x_slim_pgd_rx_port_multi_chnl_0(p) (0x140 + 4 * p) + +#define slim_manf_id_qcom 0x217 +#define slim_prod_code_wcd9340 0x250 +#define slim_dev_idx_wcd9340 0x1 +#define slim_dev_instance_id_wcd9340 0 + +#endif diff --git a/include/linux/mfd/wcd934x/wcd934x.h b/include/linux/mfd/wcd934x/wcd934x.h --- /dev/null +++ b/include/linux/mfd/wcd934x/wcd934x.h +/* spdx-license-identifier: gpl-2.0 */ + +#ifndef __wcd934x_h__ +#define __wcd934x_h__ +#include <linux/clk.h> +#include <linux/regulator/consumer.h> +#include <linux/regmap.h> +#include <linux/slimbus.h> + +#define wcd934x_max_supply 5 + +/** + * struct wcd934x_ddata - wcd934x driver data + * + * @supplies: wcd934x regulator supplies + * @irq_data: wcd934x irq_chip data + * @regmap: wcd934x regmap pointer + * @extclk: external clock + * @dev: device instance of wcd934x slim device + * @irq: irq for wcd934x. + */ +struct wcd934x_ddata { + struct regulator_bulk_data supplies[wcd934x_max_supply]; + struct regmap_irq_chip_data *irq_data; + struct regmap *regmap; + struct clk *extclk; + struct device *dev; + int irq; +}; + +#endif /* __wcd934x_h__ */
|
Multi Function Devices (MFD)
|
6ac7e4d7ad70640310feedc2e5f1cb712685cb05
|
srinivas kandagatla
|
drivers
|
mfd
|
mfd, wcd934x
|
pwm: sun4i: add support for h6 pwm
|
now that sun4i pwm driver supports deasserting reset line and enabling bus clock, support for h6 pwm can be added.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for h6 pwm
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['sun4i']
|
['c']
| 1
| 9
| 0
|
--- diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c +static const struct sun4i_pwm_data sun50i_h6_pwm_data = { + .has_prescaler_bypass = true, + .has_direct_mod_clk_output = true, + .npwm = 2, +}; + + }, { + .compatible = "allwinner,sun50i-h6-pwm", + .data = &sun50i_h6_pwm_data,
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Pulse-Width Modulation (PWM)
|
fdd2c12e3761f0418596cd0e0156719a255d23c8
|
jernej skrabec
|
drivers
|
pwm
| |
i3c: master: cdns: add data hold delay support
|
this patch adds support for thd_del (data hold delay) to cadence i3c master constoller driver.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add data hold delay support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['i3c ', 'master', 'cdns']
|
['c']
| 1
| 44
| 5
|
--- diff --git a/drivers/i3c/master/i3c-master-cdns.c b/drivers/i3c/master/i3c-master-cdns.c --- a/drivers/i3c/master/i3c-master-cdns.c +++ b/drivers/i3c/master/i3c-master-cdns.c +#include <linux/of_device.h> +#define ctrl_thd_delay(x) (((x) << 24) & genmask(25, 24)) +#define thd_delay_max 3 +struct cdns_i3c_data { + u8 thd_delay_ns; +}; + + const struct cdns_i3c_data *devdata; +static u8 cdns_i3c_master_calculate_thd_delay(struct cdns_i3c_master *master) +{ + unsigned long sysclk_rate = clk_get_rate(master->sysclk); + u8 thd_delay = div_round_up(master->devdata->thd_delay_ns, + (nsec_per_sec / sysclk_rate)); + + /* every value greater than 3 is not valid. */ + if (thd_delay > thd_delay_max) + thd_delay = thd_delay_max; + + /* ctlr_thd_del value is encoded. */ + return (thd_delay_max - thd_delay); +} + + + /* + * configure data hold delay based on device-specific data. + * + * mipi i3c specification 1.0 defines non-zero minimal thd_pp timing on + * master output. this setting allows to meet this timing on master's + * soc outputs, regardless of pcb balancing. + */ + ctrl |= ctrl_thd_delay(cdns_i3c_master_calculate_thd_delay(master)); +static struct cdns_i3c_data cdns_i3c_devdata = { + .thd_delay_ns = 10, +}; + +static const struct of_device_id cdns_i3c_master_of_ids[] = { + { .compatible = "cdns,i3c-master", .data = &cdns_i3c_devdata }, + { /* sentinel */ }, +}; + + master->devdata = of_device_get_match_data(&pdev->dev); + if (!master->devdata) + return -einval; + -static const struct of_device_id cdns_i3c_master_of_ids[] = { - { .compatible = "cdns,i3c-master" }, - { /* sentinel */ }, -}; -
|
Inter-Integrated Circuit (I2C + I3C)
|
dbd6654329fcb0f5fc11d07997ddb61683c085f2
|
przemyslaw gaj
|
drivers
|
i3c
|
master
|
i2c: jz4780: add support for the x1000.
|
add support for probing i2c driver on the x1000 soc from ingenic. call the corresponding fifo parameter according to the device model obtained from the devicetree.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for the x1000
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['i2c ', 'jz4780']
|
['c']
| 1
| 116
| 40
|
--- diff --git a/drivers/i2c/busses/i2c-jz4780.c b/drivers/i2c/busses/i2c-jz4780.c --- a/drivers/i2c/busses/i2c-jz4780.c +++ b/drivers/i2c/busses/i2c-jz4780.c + * copyright (c) 2019 (zhou yanjie) <zhouyanjie@wanyeetech.com> +#include <linux/of_device.h> +#define x1000_i2c_sdahd 0x7c +#define x1000_i2c_dc_stop bit(9) + -#define tx_level 3 -#define rx_level (jz4780_i2c_fifo_len - tx_level - 1) + +#define x1000_i2c_fifo_len 64 +enum ingenic_i2c_version { + id_jz4780, + id_x1000, +}; + +/* ingenic_i2c_config: soc specific config data. */ +struct ingenic_i2c_config { + enum ingenic_i2c_version version; + + int fifosize; + int tx_level; + int rx_level; +}; + + const struct ingenic_i2c_config *cdata; - hold_time |= jz4780_i2c_sdahd_hdenb; - jz4780_i2c_writew(i2c, jz4780_i2c_sdahd, hold_time); + if (i2c->cdata->version >= id_x1000) { + jz4780_i2c_writew(i2c, x1000_i2c_sdahd, hold_time); + } else { + hold_time |= jz4780_i2c_sdahd_hdenb; + jz4780_i2c_writew(i2c, jz4780_i2c_sdahd, hold_time); + } - jz4780_i2c_writew(i2c, jz4780_i2c_sdahd, 0); + if (i2c->cdata->version >= id_x1000) + jz4780_i2c_writew(i2c, x1000_i2c_sdahd, 0); + else + jz4780_i2c_writew(i2c, jz4780_i2c_sdahd, 0); - tmp = jz4780_i2c_readw(i2c, jz4780_i2c_ctrl); - tmp &= ~jz4780_i2c_ctrl_stphld; - jz4780_i2c_writew(i2c, jz4780_i2c_ctrl, tmp); + if (i2c->cdata->version < id_x1000) { + tmp = jz4780_i2c_readw(i2c, jz4780_i2c_ctrl); + tmp &= ~jz4780_i2c_ctrl_stphld; + jz4780_i2c_writew(i2c, jz4780_i2c_ctrl, tmp); + } -static void jz4780_i2c_send_rcmd(struct jz4780_i2c *i2c, int cmd_count) +static void jz4780_i2c_send_rcmd(struct jz4780_i2c *i2c, + int cmd_count, + int cmd_left) - for (i = 0; i < cmd_count; i++) + for (i = 0; i < cmd_count - 1; i++) + jz4780_i2c_writew(i2c, jz4780_i2c_dc, jz4780_i2c_dc_read); + + if ((cmd_left == 0) && (i2c->cdata->version >= id_x1000)) + jz4780_i2c_writew(i2c, jz4780_i2c_dc, + jz4780_i2c_dc_read | x1000_i2c_dc_stop); + else - if (rd_left <= jz4780_i2c_fifo_len) + if (rd_left <= i2c->cdata->fifosize) - int max_send = (jz4780_i2c_fifo_len - 1) + int max_send = (i2c->cdata->fifosize - 1) - (i2c->rd_cmd_xfered - i2c->rd_data_xfered); - jz4780_i2c_fifo_len - - tx_level - 1); + i2c->cdata->fifosize + - i2c->cdata->tx_level - 1); - jz4780_i2c_send_rcmd(i2c, cmd_to_send); + cmd_left = i2c->rd_total_len - + i2c->rd_cmd_xfered; + jz4780_i2c_send_rcmd(i2c, + cmd_to_send, cmd_left); + - cmd_left = i2c->rd_total_len - i2c->rd_cmd_xfered; - tmp = jz4780_i2c_readw(i2c, jz4780_i2c_ctrl); - tmp &= ~jz4780_i2c_ctrl_stphld; - jz4780_i2c_writew(i2c, jz4780_i2c_ctrl, tmp); + if (i2c->cdata->version < id_x1000) { + tmp = jz4780_i2c_readw(i2c, + jz4780_i2c_ctrl); + tmp &= ~jz4780_i2c_ctrl_stphld; + jz4780_i2c_writew(i2c, + jz4780_i2c_ctrl, tmp); + } - (i2c->wt_len > 0)) { + (i2c->wt_len > 0)) { - jz4780_i2c_writew(i2c, jz4780_i2c_dc, - data); + if ((!i2c->stop_hold) && (i2c->cdata->version >= + id_x1000)) + data |= x1000_i2c_dc_stop; + jz4780_i2c_writew(i2c, jz4780_i2c_dc, data); - if (!i2c->stop_hold) { + if ((!i2c->stop_hold) && (i2c->cdata->version < + id_x1000)) { - jz4780_i2c_ctrl); + jz4780_i2c_ctrl); - jz4780_i2c_writew(i2c, jz4780_i2c_ctrl, - tmp); + jz4780_i2c_writew(i2c, + jz4780_i2c_ctrl, tmp); - if (len <= jz4780_i2c_fifo_len) + if (len <= i2c->cdata->fifosize) - jz4780_i2c_writew(i2c, jz4780_i2c_rxtl, rx_level); + jz4780_i2c_writew(i2c, jz4780_i2c_rxtl, i2c->cdata->rx_level); - jz4780_i2c_writew(i2c, jz4780_i2c_txtl, tx_level); + jz4780_i2c_writew(i2c, jz4780_i2c_txtl, i2c->cdata->tx_level); - tmp = jz4780_i2c_readw(i2c, jz4780_i2c_ctrl); - tmp |= jz4780_i2c_ctrl_stphld; - jz4780_i2c_writew(i2c, jz4780_i2c_ctrl, tmp); + if (i2c->cdata->version < id_x1000) { + tmp = jz4780_i2c_readw(i2c, jz4780_i2c_ctrl); + tmp |= jz4780_i2c_ctrl_stphld; + jz4780_i2c_writew(i2c, jz4780_i2c_ctrl, tmp); + } - jz4780_i2c_writew(i2c, jz4780_i2c_txtl, tx_level); + jz4780_i2c_writew(i2c, jz4780_i2c_txtl, i2c->cdata->tx_level); - tmp = jz4780_i2c_readw(i2c, jz4780_i2c_ctrl); - tmp |= jz4780_i2c_ctrl_stphld; - jz4780_i2c_writew(i2c, jz4780_i2c_ctrl, tmp); + if (i2c->cdata->version < id_x1000) { + tmp = jz4780_i2c_readw(i2c, jz4780_i2c_ctrl); + tmp |= jz4780_i2c_ctrl_stphld; + jz4780_i2c_writew(i2c, jz4780_i2c_ctrl, tmp); + } +static const struct ingenic_i2c_config jz4780_i2c_config = { + .version = id_jz4780, + + .fifosize = jz4780_i2c_fifo_len, + .tx_level = jz4780_i2c_fifo_len / 2, + .rx_level = jz4780_i2c_fifo_len / 2 - 1, +}; + +static const struct ingenic_i2c_config x1000_i2c_config = { + .version = id_x1000, + + .fifosize = x1000_i2c_fifo_len, + .tx_level = x1000_i2c_fifo_len / 2, + .rx_level = x1000_i2c_fifo_len / 2 - 1, +}; + - { .compatible = "ingenic,jz4780-i2c", }, + { .compatible = "ingenic,jz4780-i2c", .data = &jz4780_i2c_config }, + { .compatible = "ingenic,x1000-i2c", .data = &x1000_i2c_config }, + i2c->cdata = device_get_match_data(&pdev->dev); + if (!i2c->cdata) { + dev_err(&pdev->dev, "error: no device match found "); + return -enodev; + } + - tmp = jz4780_i2c_readw(i2c, jz4780_i2c_ctrl); - tmp &= ~jz4780_i2c_ctrl_stphld; - jz4780_i2c_writew(i2c, jz4780_i2c_ctrl, tmp); + if (i2c->cdata->version < id_x1000) { + tmp = jz4780_i2c_readw(i2c, jz4780_i2c_ctrl); + tmp &= ~jz4780_i2c_ctrl_stphld; + jz4780_i2c_writew(i2c, jz4780_i2c_ctrl, tmp); + }
|
Inter-Integrated Circuit (I2C + I3C)
|
21575a7a8d4c2593ca8d77b3793b35ab3464d99f
|
zhou yanjie paul cercueil paul crapouillou net
|
drivers
|
i2c
|
busses
|
i2c: parport-light: remove driver
|
the justification of a light version of the parport driver was less overhead for embedded systems. well, today, even if an embedded system still has a parport, it surely can handle the fully-fledged parport driver. remove it to reduce the maintenance burden.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
remove driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['i2c ', 'parport-light']
|
['c', 'kconfig', 'maintainers', 'rst', 'makefile']
| 6
| 0
| 323
|
--- diff --git a/documentation/i2c/busses/i2c-parport-light.rst b/documentation/i2c/busses/i2c-parport-light.rst --- a/documentation/i2c/busses/i2c-parport-light.rst +++ /dev/null -=============================== -kernel driver i2c-parport-light -=============================== - -author: jean delvare <jdelvare@suse.de> - -this driver is a light version of i2c-parport. it doesn't depend -on the parport driver, and uses direct i/o access instead. this might be -preferred on embedded systems where wasting memory for the clean but heavy -parport handling is not an option. the drawback is a reduced portability -and the impossibility to daisy-chain other parallel port devices. - -please see i2c-parport for documentation. - -module parameters: - -* type: type of adapter (see i2c-parport or modinfo) - -* base: base i/o address - default is 0x378 which is fairly common for parallel ports, at least on pc. - -* irq: optional irq - this must be passed if you want smbus alert support, assuming your adapter - actually supports this. diff --git a/documentation/i2c/busses/index.rst b/documentation/i2c/busses/index.rst --- a/documentation/i2c/busses/index.rst +++ b/documentation/i2c/busses/index.rst - i2c-parport-light diff --git a/maintainers b/maintainers --- a/maintainers +++ b/maintainers -f: documentation/i2c/busses/i2c-parport-light.rst -f: drivers/i2c/busses/i2c-parport-light.c diff --git a/drivers/i2c/busses/kconfig b/drivers/i2c/busses/kconfig --- a/drivers/i2c/busses/kconfig +++ b/drivers/i2c/busses/kconfig - another driver exists, named i2c-parport-light, which doesn't depend - on the parport driver. this is meant for embedded systems. don't say - y here if you intend to say y or m there. - -config i2c_parport_light - tristate "parallel port adapter (light)" - select i2c_algobit - select i2c_smbus - help - this supports parallel port i2c adapters such as the ones made by - philips or velleman, analog devices evaluation boards, and more. - basically any adapter using the parallel port as an i2c bus with - no extra chipset is supported by this driver, or could be. - - this driver is a light version of i2c-parport. it doesn't depend - on the parport driver, and uses direct i/o access instead. this - might be preferred on embedded systems where wasting memory for - the clean but heavy parport handling is not an option. the - drawback is a reduced portability and the impossibility to - daisy-chain other parallel port devices. - - don't say y here if you said y or m to i2c-parport. saying m to - both is possible but both modules should not be loaded at the same - time. - - this support is also available as a module. if so, the module - will be called i2c-parport-light. - diff --git a/drivers/i2c/busses/makefile b/drivers/i2c/busses/makefile --- a/drivers/i2c/busses/makefile +++ b/drivers/i2c/busses/makefile -obj-$(config_i2c_parport_light) += i2c-parport-light.o diff --git a/drivers/i2c/busses/i2c-parport-light.c b/drivers/i2c/busses/i2c-parport-light.c --- a/drivers/i2c/busses/i2c-parport-light.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-or-later -/* ------------------------------------------------------------------------ * - * i2c-parport-light.c i2c bus over parallel port * - * ------------------------------------------------------------------------ * - copyright (c) 2003-2010 jean delvare <jdelvare@suse.de> - - based on older i2c-velleman.c driver - copyright (c) 1995-2000 simon g. vogl - with some changes from: - frodo looijaard <frodol@dds.nl> - kyosti malkki <kmalkki@cc.hut.fi> - - * ------------------------------------------------------------------------ */ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/platform_device.h> -#include <linux/ioport.h> -#include <linux/i2c.h> -#include <linux/i2c-algo-bit.h> -#include <linux/i2c-smbus.h> -#include <linux/io.h> -#include "i2c-parport.h" - -#define default_base 0x378 -#define drvname "i2c-parport-light" - -static struct platform_device *pdev; - -static u16 base; -module_param_hw(base, ushort, ioport, 0); -module_parm_desc(base, "base i/o address"); - -static int irq; -module_param_hw(irq, int, irq, 0); -module_parm_desc(irq, "irq (optional)"); - -/* ----- low-level parallel port access ----------------------------------- */ - -static inline void port_write(unsigned char p, unsigned char d) -{ - outb(d, base+p); -} - -static inline unsigned char port_read(unsigned char p) -{ - return inb(base+p); -} - -/* ----- unified line operation functions --------------------------------- */ - -static inline void line_set(int state, const struct lineop *op) -{ - u8 oldval = port_read(op->port); - - /* touch only the bit(s) needed */ - if ((op->inverted && !state) || (!op->inverted && state)) - port_write(op->port, oldval | op->val); - else - port_write(op->port, oldval & ~op->val); -} - -static inline int line_get(const struct lineop *op) -{ - u8 oldval = port_read(op->port); - - return ((op->inverted && (oldval & op->val) != op->val) - || (!op->inverted && (oldval & op->val) == op->val)); -} - -/* ----- i2c algorithm call-back functions and structures ----------------- */ - -static void parport_setscl(void *data, int state) -{ - line_set(state, &adapter_parm[type].setscl); -} - -static void parport_setsda(void *data, int state) -{ - line_set(state, &adapter_parm[type].setsda); -} - -static int parport_getscl(void *data) -{ - return line_get(&adapter_parm[type].getscl); -} - -static int parport_getsda(void *data) -{ - return line_get(&adapter_parm[type].getsda); -} - -/* encapsulate the functions above in the correct structure - note that getscl will be set to null by the attaching code for adapters - that cannot read scl back */ -static struct i2c_algo_bit_data parport_algo_data = { - .setsda = parport_setsda, - .setscl = parport_setscl, - .getsda = parport_getsda, - .getscl = parport_getscl, - .udelay = 50, - .timeout = hz, -}; - -/* ----- driver registration ---------------------------------------------- */ - -static struct i2c_adapter parport_adapter = { - .owner = this_module, - .class = i2c_class_hwmon, - .algo_data = &parport_algo_data, - .name = "parallel port adapter (light)", -}; - -/* smbus alert support */ -static struct i2c_smbus_alert_setup alert_data = { -}; -static struct i2c_client *ara; -static struct lineop parport_ctrl_irq = { - .val = (1 << 4), - .port = port_ctrl, -}; - -static int i2c_parport_probe(struct platform_device *pdev) -{ - int err; - - /* reset hardware to a sane state (scl and sda high) */ - parport_setsda(null, 1); - parport_setscl(null, 1); - /* other init if needed (power on...) */ - if (adapter_parm[type].init.val) { - line_set(1, &adapter_parm[type].init); - /* give powered devices some time to settle */ - msleep(100); - } - - parport_adapter.dev.parent = &pdev->dev; - err = i2c_bit_add_bus(&parport_adapter); - if (err) { - dev_err(&pdev->dev, "unable to register with i2c "); - return err; - } - - /* setup smbus alert if supported */ - if (adapter_parm[type].smbus_alert && irq) { - alert_data.irq = irq; - ara = i2c_setup_smbus_alert(&parport_adapter, &alert_data); - if (ara) - line_set(1, &parport_ctrl_irq); - else - dev_warn(&pdev->dev, "failed to register ara client "); - } - - return 0; -} - -static int i2c_parport_remove(struct platform_device *pdev) -{ - if (ara) { - line_set(0, &parport_ctrl_irq); - i2c_unregister_device(ara); - ara = null; - } - i2c_del_adapter(&parport_adapter); - - /* un-init if needed (power off...) */ - if (adapter_parm[type].init.val) - line_set(0, &adapter_parm[type].init); - - return 0; -} - -static struct platform_driver i2c_parport_driver = { - .driver = { - .name = drvname, - }, - .probe = i2c_parport_probe, - .remove = i2c_parport_remove, -}; - -static int __init i2c_parport_device_add(u16 address) -{ - int err; - - pdev = platform_device_alloc(drvname, -1); - if (!pdev) { - err = -enomem; - printk(kern_err drvname ": device allocation failed "); - goto exit; - } - - err = platform_device_add(pdev); - if (err) { - printk(kern_err drvname ": device addition failed (%d) ", - err); - goto exit_device_put; - } - - return 0; - -exit_device_put: - platform_device_put(pdev); -exit: - return err; -} - -static int __init i2c_parport_init(void) -{ - int err; - - if (type < 0) { - printk(kern_err drvname ": adapter type unspecified "); - return -enodev; - } - - if (type >= array_size(adapter_parm)) { - printk(kern_err drvname ": invalid type (%d) ", type); - return -enodev; - } - - if (base == 0) { - pr_info(drvname ": using default base 0x%x ", default_base); - base = default_base; - } - - if (!request_region(base, 3, drvname)) - return -ebusy; - - if (irq != 0) - pr_info(drvname ": using irq %d ", irq); - - if (!adapter_parm[type].getscl.val) - parport_algo_data.getscl = null; - - /* sets global pdev as a side effect */ - err = i2c_parport_device_add(base); - if (err) - goto exit_release; - - err = platform_driver_register(&i2c_parport_driver); - if (err) - goto exit_device; - - return 0; - -exit_device: - platform_device_unregister(pdev); -exit_release: - release_region(base, 3); - return err; -} - -static void __exit i2c_parport_exit(void) -{ - platform_driver_unregister(&i2c_parport_driver); - platform_device_unregister(pdev); - release_region(base, 3); -} - -module_author("jean delvare <jdelvare@suse.de>"); -module_description("i2c bus over parallel port (light)"); -module_license("gpl"); - -module_init(i2c_parport_init); -module_exit(i2c_parport_exit);
|
Inter-Integrated Circuit (I2C + I3C)
|
710b65335c19eea696741eb2d5e45a39aa23d0bb
|
wolfram sang jean delvare jdelvare suse de
|
documentation
|
i2c
|
busses
|
i2c: i801: add support for intel comet lake pch-v
|
add support for intel comet lake pch-v which is based on intel kaby lake. difference between it and other comet lake variants is that former uses previous itco version 4 and latter use version 6 like intel cannon lake pch.
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this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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add support for intel comet lake pch-v
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['i2c ', 'i801']
|
['c']
| 1
| 4
| 0
|
--- diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c --- a/drivers/i2c/busses/i2c-i801.c +++ b/drivers/i2c/busses/i2c-i801.c + * comet lake-v (pch) 0xa3a3 32 hard yes yes yes +#define pci_device_id_intel_cometlake_v_smbus 0xa3a3 + { pci_device(pci_vendor_id_intel, pci_device_id_intel_cometlake_v_smbus) }, + case pci_device_id_intel_cometlake_v_smbus:
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Inter-Integrated Circuit (I2C + I3C)
|
f53938d2c79ae3c768dc92b1c3d898dfe820a491
|
jarkko nikula jean delvare jdelvare suse de
|
drivers
|
i2c
|
busses
|
i2c: designware: add acpi hid for hisilicon hip08-lite i2c controller
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add acpi hid hisi02a3 for hisilicon hip08 lite, which has different clock frequency from hip08 for i2c controller.
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this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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add acpi hid for hisilicon hip08-lite i2c controller
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['i2c ', 'designware']
|
['c']
| 1
| 1
| 0
|
--- diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c --- a/drivers/i2c/busses/i2c-designware-platdrv.c +++ b/drivers/i2c/busses/i2c-designware-platdrv.c + { "hisi02a3", 0 },
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Inter-Integrated Circuit (I2C + I3C)
|
dec0a81a7814c8a876e663e0627468e6b1a7d2fb
|
hanjun guo nikula jarkko nikula linux intel com andy shevchenko andriy shevchenko linux intel com sheng feng fengsheng huawei com
|
drivers
|
i2c
|
busses
|
hwmon: add support for enable attributes to hwmon core
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the hwmon abi supports enable attributes since commit fb41a710f84e ("hwmon: document the sensor enable attribute"), but did not add support for those attributes to the hwmon core. do that now.
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this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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add support for enable attributes to hwmon core
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['c', 'h']
| 2
| 22
| 4
|
--- diff --git a/drivers/hwmon/hwmon.c b/drivers/hwmon/hwmon.c --- a/drivers/hwmon/hwmon.c +++ b/drivers/hwmon/hwmon.c + [hwmon_temp_enable] = "temp%d_enable", + [hwmon_in_enable] = "in%d_enable", - [hwmon_in_enable] = "in%d_enable", + [hwmon_curr_enable] = "curr%d_enable", + [hwmon_power_enable] = "power%d_enable", + [hwmon_energy_enable] = "energy%d_enable", + [hwmon_humidity_enable] = "humidity%d_enable", + [hwmon_fan_enable] = "fan%d_enable", diff --git a/include/linux/hwmon.h b/include/linux/hwmon.h --- a/include/linux/hwmon.h +++ b/include/linux/hwmon.h - hwmon_temp_input = 0, + hwmon_temp_enable, + hwmon_temp_input, +#define hwmon_t_enable bit(hwmon_temp_enable) + hwmon_in_enable, - hwmon_in_enable, +#define hwmon_i_enable bit(hwmon_in_enable) -#define hwmon_i_enable bit(hwmon_in_enable) + hwmon_curr_enable, +#define hwmon_c_enable bit(hwmon_curr_enable) + hwmon_power_enable, +#define hwmon_p_enable bit(hwmon_power_enable) + hwmon_energy_enable, +#define hwmon_e_enable bit(hwmon_energy_enable) + hwmon_humidity_enable, +#define hwmon_h_enable bit(hwmon_humidity_enable) + hwmon_fan_enable, +#define hwmon_f_enable bit(hwmon_fan_enable)
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Hardware monitoring (hwmon)
|
002c6b545b85676539add33add8aa7f1f49cbfff
|
guenter roeck
|
include
|
linux
| |
hwmon: add intrusion templates
|
add templates for intrusion%d_alarm and intrusion%d_beep. note, these start at 0.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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add intrusion templates
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['c', 'h']
| 2
| 16
| 1
|
--- diff --git a/drivers/hwmon/hwmon.c b/drivers/hwmon/hwmon.c --- a/drivers/hwmon/hwmon.c +++ b/drivers/hwmon/hwmon.c - if (type == hwmon_in) + if (type == hwmon_in || type == hwmon_intrusion) +static const char * const hwmon_intrusion_attr_templates[] = { + [hwmon_intrusion_alarm] = "intrusion%d_alarm", + [hwmon_intrusion_beep] = "intrusion%d_beep", +}; + + [hwmon_intrusion] = hwmon_intrusion_attr_templates, + [hwmon_intrusion] = array_size(hwmon_intrusion_attr_templates), diff --git a/include/linux/hwmon.h b/include/linux/hwmon.h --- a/include/linux/hwmon.h +++ b/include/linux/hwmon.h + hwmon_intrusion, +enum hwmon_intrusion_attributes { + hwmon_intrusion_alarm, + hwmon_intrusion_beep, +}; +#define hwmon_intrusion_alarm bit(hwmon_intrusion_alarm) +#define hwmon_intrusion_beep bit(hwmon_intrusion_beep) +
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Hardware monitoring (hwmon)
|
4413405f931ef97ab1263ae3588e6f656ec220b7
|
dr david alan gilbert
|
include
|
linux
| |
hwmon: driver for max31730
|
max31730 is a 3-channel remote temperature sensor.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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driver for max31730
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['c', 'kconfig', 'makefile', 'rst']
| 5
| 497
| 1
|
--- diff --git a/documentation/hwmon/index.rst b/documentation/hwmon/index.rst --- a/documentation/hwmon/index.rst +++ b/documentation/hwmon/index.rst + max31730 diff --git a/documentation/hwmon/max31730.rst b/documentation/hwmon/max31730.rst --- /dev/null +++ b/documentation/hwmon/max31730.rst +kernel driver max31790 +====================== + +supported chips: + + * maxim max31730 + + prefix: 'max31730' + + addresses scanned: 0x1c, 0x1d, 0x1e, 0x1f, 0x4c, 0x4d, 0x4e, 0x4f + + datasheet: https://datasheets.maximintegrated.com/en/ds/max31730.pdf + +author: guenter roeck <linux@roeck-us.net> + + +description +----------- + +this driver implements support for maxim max31730. + +the max31730 temperature sensor monitors its own temperature and the +temperatures of three external diode-connected transistors. the operating +supply voltage is from 3.0v to 3.6v. resistance cancellation compensates +for high series resistance in circuit-board traces and the external thermal +diode, while beta compensation corrects for temperature-measurement +errors due to low-beta sensing transistors. + + +sysfs entries +------------- + +=================== == ======================================================= +temp[1-4]_enable rw temperature enable/disable + set to 0 to enable channel, 0 to disable +temp[1-4]_input ro temperature input +temp[2-4]_fault ro fault indicator for remote channels +temp[1-4]_max rw maximum temperature +temp[1-4]_max_alarm rw maximum temperature alarm +temp[1-4]_min rw minimum temperature. common for all channels. + only temp1_min is writeable. +temp[1-4]_min_alarm ro minimum temperature alarm +temp[2-4]_offset rw temperature offset for remote channels +=================== == ======================================================= diff --git a/drivers/hwmon/kconfig b/drivers/hwmon/kconfig --- a/drivers/hwmon/kconfig +++ b/drivers/hwmon/kconfig -tristate "max31722 temperature sensor" + tristate "max31722 temperature sensor" +config sensors_max31730 + tristate "max31730 temperature sensor" + depends on i2c + help + support for the maxim integrated max31730 3-channel remote + temperature sensor. + + this driver can also be built as a module. if so, the module + will be called max31730. + diff --git a/drivers/hwmon/makefile b/drivers/hwmon/makefile --- a/drivers/hwmon/makefile +++ b/drivers/hwmon/makefile +obj-$(config_sensors_max31730) += max31730.o diff --git a/drivers/hwmon/max31730.c b/drivers/hwmon/max31730.c --- /dev/null +++ b/drivers/hwmon/max31730.c +// spdx-license-identifier: gpl-2.0-or-later +/* + * driver for max31730 3-channel remote temperature sensor + * + * copyright (c) 2019 guenter roeck <linux@roeck-us.net> + */ + +#include <linux/bits.h> +#include <linux/err.h> +#include <linux/i2c.h> +#include <linux/init.h> +#include <linux/hwmon.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/slab.h> + +/* addresses scanned */ +static const unsigned short normal_i2c[] = { 0x1c, 0x1d, 0x1e, 0x1f, 0x4c, + 0x4d, 0x4e, 0x4f, i2c_client_end }; + +/* the max31730 registers */ +#define max31730_reg_temp 0x00 +#define max31730_reg_conf 0x13 +#define max31730_stop bit(7) +#define max31730_extrange bit(1) +#define max31730_reg_temp_offset 0x16 +#define max31730_temp_offset_baseline 0x77 +#define max31730_reg_offset_enable 0x17 +#define max31730_reg_temp_max 0x20 +#define max31730_reg_temp_min 0x30 +#define max31730_reg_status_high 0x32 +#define max31730_reg_status_low 0x33 +#define max31730_reg_channel_enable 0x35 +#define max31730_reg_temp_fault 0x36 + +#define max31730_reg_mfg_id 0x50 +#define max31730_mfg_id 0x4d +#define max31730_reg_mfg_rev 0x51 +#define max31730_mfg_rev 0x01 + +#define max31730_temp_min (-128000) +#define max31730_temp_max 127937 + +/* each client has this additional data */ +struct max31730_data { + struct i2c_client *client; + u8 orig_conf; + u8 current_conf; + u8 offset_enable; + u8 channel_enable; +}; + +/*-----------------------------------------------------------------------*/ + +static inline long max31730_reg_to_mc(s16 temp) +{ + return div_round_closest((temp >> 4) * 1000, 16); +} + +static int max31730_write_config(struct max31730_data *data, u8 set_mask, + u8 clr_mask) +{ + u8 value; + + clr_mask |= max31730_extrange; + value = data->current_conf & ~clr_mask; + value |= set_mask; + + if (data->current_conf != value) { + s32 err; + + err = i2c_smbus_write_byte_data(data->client, max31730_reg_conf, + value); + if (err) + return err; + data->current_conf = value; + } + return 0; +} + +static int max31730_set_enable(struct i2c_client *client, int reg, + u8 *confdata, int channel, bool enable) +{ + u8 regval = *confdata; + int err; + + if (enable) + regval |= bit(channel); + else + regval &= ~bit(channel); + + if (regval != *confdata) { + err = i2c_smbus_write_byte_data(client, reg, regval); + if (err) + return err; + *confdata = regval; + } + return 0; +} + +static int max31730_set_offset_enable(struct max31730_data *data, int channel, + bool enable) +{ + return max31730_set_enable(data->client, max31730_reg_offset_enable, + &data->offset_enable, channel, enable); +} + +static int max31730_set_channel_enable(struct max31730_data *data, int channel, + bool enable) +{ + return max31730_set_enable(data->client, max31730_reg_channel_enable, + &data->channel_enable, channel, enable); +} + +static int max31730_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + struct max31730_data *data = dev_get_drvdata(dev); + int regval, reg, offset; + + if (type != hwmon_temp) + return -einval; + + switch (attr) { + case hwmon_temp_input: + if (!(data->channel_enable & bit(channel))) + return -enodata; + reg = max31730_reg_temp + (channel * 2); + break; + case hwmon_temp_max: + reg = max31730_reg_temp_max + (channel * 2); + break; + case hwmon_temp_min: + reg = max31730_reg_temp_min; + break; + case hwmon_temp_enable: + *val = !!(data->channel_enable & bit(channel)); + return 0; + case hwmon_temp_offset: + if (!channel) + return -einval; + if (!(data->offset_enable & bit(channel))) { + *val = 0; + return 0; + } + offset = i2c_smbus_read_byte_data(data->client, + max31730_reg_temp_offset); + if (offset < 0) + return offset; + *val = (offset - max31730_temp_offset_baseline) * 125; + return 0; + case hwmon_temp_fault: + regval = i2c_smbus_read_byte_data(data->client, + max31730_reg_temp_fault); + if (regval < 0) + return regval; + *val = !!(regval & bit(channel)); + return 0; + case hwmon_temp_min_alarm: + regval = i2c_smbus_read_byte_data(data->client, + max31730_reg_status_low); + if (regval < 0) + return regval; + *val = !!(regval & bit(channel)); + return 0; + case hwmon_temp_max_alarm: + regval = i2c_smbus_read_byte_data(data->client, + max31730_reg_status_high); + if (regval < 0) + return regval; + *val = !!(regval & bit(channel)); + return 0; + default: + return -einval; + } + regval = i2c_smbus_read_word_swapped(data->client, reg); + if (regval < 0) + return regval; + + *val = max31730_reg_to_mc(regval); + + return 0; +} + +static int max31730_write(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long val) +{ + struct max31730_data *data = dev_get_drvdata(dev); + int reg, err; + + if (type != hwmon_temp) + return -einval; + + switch (attr) { + case hwmon_temp_max: + reg = max31730_reg_temp_max + channel * 2; + break; + case hwmon_temp_min: + reg = max31730_reg_temp_min; + break; + case hwmon_temp_enable: + if (val != 0 && val != 1) + return -einval; + return max31730_set_channel_enable(data, channel, val); + case hwmon_temp_offset: + val = clamp_val(val, -14875, 17000) + 14875; + val = div_round_closest(val, 125); + err = max31730_set_offset_enable(data, channel, + val != max31730_temp_offset_baseline); + if (err) + return err; + return i2c_smbus_write_byte_data(data->client, + max31730_reg_temp_offset, val); + default: + return -einval; + } + + val = clamp_val(val, max31730_temp_min, max31730_temp_max); + val = div_round_closest(val << 4, 1000) << 4; + + return i2c_smbus_write_word_swapped(data->client, reg, (u16)val); +} + +static umode_t max31730_is_visible(const void *data, + enum hwmon_sensor_types type, + u32 attr, int channel) +{ + switch (type) { + case hwmon_temp: + switch (attr) { + case hwmon_temp_input: + case hwmon_temp_min_alarm: + case hwmon_temp_max_alarm: + case hwmon_temp_fault: + return 0444; + case hwmon_temp_min: + return channel ? 0444 : 0644; + case hwmon_temp_offset: + case hwmon_temp_enable: + case hwmon_temp_max: + return 0644; + } + break; + default: + break; + } + return 0; +} + +static const struct hwmon_channel_info *max31730_info[] = { + hwmon_channel_info(chip, + hwmon_c_register_tz), + hwmon_channel_info(temp, + hwmon_t_input | hwmon_t_min | hwmon_t_max | + hwmon_t_enable | + hwmon_t_min_alarm | hwmon_t_max_alarm, + hwmon_t_input | hwmon_t_min | hwmon_t_max | + hwmon_t_offset | hwmon_t_enable | + hwmon_t_min_alarm | hwmon_t_max_alarm | + hwmon_t_fault, + hwmon_t_input | hwmon_t_min | hwmon_t_max | + hwmon_t_offset | hwmon_t_enable | + hwmon_t_min_alarm | hwmon_t_max_alarm | + hwmon_t_fault, + hwmon_t_input | hwmon_t_min | hwmon_t_max | + hwmon_t_offset | hwmon_t_enable | + hwmon_t_min_alarm | hwmon_t_max_alarm | + hwmon_t_fault + ), + null +}; + +static const struct hwmon_ops max31730_hwmon_ops = { + .is_visible = max31730_is_visible, + .read = max31730_read, + .write = max31730_write, +}; + +static const struct hwmon_chip_info max31730_chip_info = { + .ops = &max31730_hwmon_ops, + .info = max31730_info, +}; + +static void max31730_remove(void *data) +{ + struct max31730_data *max31730 = data; + struct i2c_client *client = max31730->client; + + i2c_smbus_write_byte_data(client, max31730_reg_conf, + max31730->orig_conf); +} + +static int +max31730_probe(struct i2c_client *client, const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct device *hwmon_dev; + struct max31730_data *data; + int status, err; + + if (!i2c_check_functionality(client->adapter, + i2c_func_smbus_byte_data | i2c_func_smbus_word_data)) + return -eio; + + data = devm_kzalloc(dev, sizeof(struct max31730_data), gfp_kernel); + if (!data) + return -enomem; + + data->client = client; + + /* cache original configuration and enable status */ + status = i2c_smbus_read_byte_data(client, max31730_reg_channel_enable); + if (status < 0) + return status; + data->channel_enable = status; + + status = i2c_smbus_read_byte_data(client, max31730_reg_offset_enable); + if (status < 0) + return status; + data->offset_enable = status; + + status = i2c_smbus_read_byte_data(client, max31730_reg_conf); + if (status < 0) + return status; + data->orig_conf = status; + data->current_conf = status; + + err = max31730_write_config(data, + data->channel_enable ? 0 : max31730_stop, + data->channel_enable ? max31730_stop : 0); + if (err) + return err; + + dev_set_drvdata(dev, data); + + err = devm_add_action_or_reset(dev, max31730_remove, data); + if (err) + return err; + + hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, + data, + &max31730_chip_info, + null); + return ptr_err_or_zero(hwmon_dev); +} + +static const struct i2c_device_id max31730_ids[] = { + { "max31730", 0, }, + { } +}; +module_device_table(i2c, max31730_ids); + +static const struct of_device_id __maybe_unused max31730_of_match[] = { + { + .compatible = "maxim,max31730", + }, + { }, +}; +module_device_table(of, max31730_of_match); + +static bool max31730_check_reg_temp(struct i2c_client *client, + int reg) +{ + int regval; + + regval = i2c_smbus_read_byte_data(client, reg + 1); + return regval < 0 || (regval & 0x0f); +} + +/* return 0 if detection is successful, -enodev otherwise */ +static int max31730_detect(struct i2c_client *client, + struct i2c_board_info *info) +{ + struct i2c_adapter *adapter = client->adapter; + int regval; + int i; + + if (!i2c_check_functionality(adapter, i2c_func_smbus_byte_data | + i2c_func_smbus_word_data)) + return -enodev; + + regval = i2c_smbus_read_byte_data(client, max31730_reg_mfg_id); + if (regval != max31730_mfg_id) + return -enodev; + regval = i2c_smbus_read_byte_data(client, max31730_reg_mfg_rev); + if (regval != max31730_mfg_rev) + return -enodev; + + /* lower 4 bit of temperature and limit registers must be 0 */ + if (max31730_check_reg_temp(client, max31730_reg_temp_min)) + return -enodev; + + for (i = 0; i < 4; i++) { + if (max31730_check_reg_temp(client, max31730_reg_temp + i * 2)) + return -enodev; + if (max31730_check_reg_temp(client, + max31730_reg_temp_max + i * 2)) + return -enodev; + } + + strlcpy(info->type, "max31730", i2c_name_size); + + return 0; +} + +static int __maybe_unused max31730_suspend(struct device *dev) +{ + struct max31730_data *data = dev_get_drvdata(dev); + + return max31730_write_config(data, max31730_stop, 0); +} + +static int __maybe_unused max31730_resume(struct device *dev) +{ + struct max31730_data *data = dev_get_drvdata(dev); + + return max31730_write_config(data, 0, max31730_stop); +} + +static simple_dev_pm_ops(max31730_pm_ops, max31730_suspend, max31730_resume); + +static struct i2c_driver max31730_driver = { + .class = i2c_class_hwmon, + .driver = { + .name = "max31730", + .of_match_table = of_match_ptr(max31730_of_match), + .pm = &max31730_pm_ops, + }, + .probe = max31730_probe, + .id_table = max31730_ids, + .detect = max31730_detect, + .address_list = normal_i2c, +}; + +module_i2c_driver(max31730_driver); + +module_author("guenter roeck <linux@roeck-us.net>"); +module_description("max31730 driver"); +module_license("gpl");
|
Hardware monitoring (hwmon)
|
d21ed22ba7b110746315dff56f62d76352ac5437
|
guenter roeck
|
drivers
|
hwmon
| |
hwmon: driver for disk and solid state drives with temperature sensors
|
reading the temperature of ata drives has been supported for years by userspace tools such as smarttools or hddtemp. the downside of such tools is that they need to run with super-user privilege, that the temperatures are not reported by standard tools such as 'sensors' or 'libsensors', and that drive temperatures are not available for use in the kernel's thermal subsystem.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
driver for disk and solid state drives with temperature sensors
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['c', 'kconfig', 'makefile', 'rst']
| 5
| 638
| 0
|
--- diff --git a/documentation/hwmon/drivetemp.rst b/documentation/hwmon/drivetemp.rst --- /dev/null +++ b/documentation/hwmon/drivetemp.rst +.. spdx-license-identifier: gpl-2.0 + +kernel driver drivetemp +======================= + + +references +---------- + +ans t13/1699-d +information technology - at attachment 8 - ata/atapi command set (ata8-acs) + +ans project t10/bsr incits 513 +information technology - scsi primary commands - 4 (spc-4) + +ans project incits 557 +information technology - scsi / ata translation - 5 (sat-5) + + +description +----------- + +this driver supports reporting the temperature of disk and solid state +drives with temperature sensors. + +if supported, it uses the ata sct command transport feature to read +the current drive temperature and, if available, temperature limits +as well as historic minimum and maximum temperatures. if sct command +transport is not supported, the driver uses smart attributes to read +the drive temperature. + + +sysfs entries +------------- + +only the temp1_input attribute is always available. other attributes are +available only if reported by the drive. all temperatures are reported in +milli-degrees celsius. + +======================= ===================================================== +temp1_input current drive temperature +temp1_lcrit minimum temperature limit. operating the device below + this temperature may cause physical damage to the + device. +temp1_min minimum recommended continuous operating limit +temp1_max maximum recommended continuous operating temperature +temp1_crit maximum temperature limit. operating the device above + this temperature may cause physical damage to the + device. +temp1_lowest minimum temperature seen this power cycle +temp1_highest maximum temperature seen this power cycle +======================= ===================================================== diff --git a/documentation/hwmon/index.rst b/documentation/hwmon/index.rst --- a/documentation/hwmon/index.rst +++ b/documentation/hwmon/index.rst + drivetemp diff --git a/drivers/hwmon/kconfig b/drivers/hwmon/kconfig --- a/drivers/hwmon/kconfig +++ b/drivers/hwmon/kconfig +config sensors_drivetemp + tristate "hard disk drives with temperature sensors" + depends on scsi && ata + help + if you say yes you get support for the temperature sensor on + hard disk drives. + + this driver can also be built as a module. if so, the module + will be called satatemp. + diff --git a/drivers/hwmon/makefile b/drivers/hwmon/makefile --- a/drivers/hwmon/makefile +++ b/drivers/hwmon/makefile +obj-$(config_sensors_drivetemp) += drivetemp.o diff --git a/drivers/hwmon/drivetemp.c b/drivers/hwmon/drivetemp.c --- /dev/null +++ b/drivers/hwmon/drivetemp.c +// spdx-license-identifier: gpl-2.0 +/* + * hwmon client for disk and solid state drives with temperature sensors + * copyright (c) 2019 zodiac inflight innovations + * + * with input from: + * hwmon client for s.m.a.r.t. hard disk drives with temperature sensors. + * (c) 2018 linus walleij + * + * hwmon: driver for scsi/ata temperature sensors + * by constantin baranov <const@mimas.ru>, submitted september 2009 + * + * this drive supports reporting the temperatire of sata drives. it can be + * easily extended to report the temperature of scsi drives. + * + * the primary means to read drive temperatures and temperature limits + * for ata drives is the sct command transport feature set as specified in + * ata8-acs. + * it can be used to read the current drive temperature, temperature limits, + * and historic minimum and maximum temperatures. the sct command transport + * feature set is documented in "at attachment 8 - ata/atapi command set + * (ata8-acs)". + * + * if the sct command transport feature set is not available, drive temperatures + * may be readable through smart attributes. since smart attributes are not well + * defined, this method is only used as fallback mechanism. + * + * there are three smart attributes which may report drive temperatures. + * those are defined as follows (from + * http://www.cropel.com/library/smart-attribute-list.aspx). + * + * 190 temperature temperature, monitored by a sensor somewhere inside + * the drive. raw value typicaly holds the actual + * temperature (hexadecimal) in its rightmost two digits. + * + * 194 temperature temperature, monitored by a sensor somewhere inside + * the drive. raw value typicaly holds the actual + * temperature (hexadecimal) in its rightmost two digits. + * + * 231 temperature temperature, monitored by a sensor somewhere inside + * the drive. raw value typicaly holds the actual + * temperature (hexadecimal) in its rightmost two digits. + * + * wikipedia defines attributes a bit differently. + * + * 190 temperature value is equal to (100-temp. c), allowing manufacturer + * difference or to set a minimum threshold which corresponds to a + * airflow maximum temperature. this also follows the convention of + * temperature 100 being a best-case value and lower values being + * undesirable. however, some older drives may instead + * report raw temperature (identical to 0xc2) or + * temperature minus 50 here. + * 194 temperature or indicates the device temperature, if the appropriate + * temperature sensor is fitted. lowest byte of the raw value contains + * celsius the exact temperature value (celsius degrees). + * 231 life left indicates the approximate ssd life left, in terms of + * (ssds) or program/erase cycles or available reserved blocks. + * temperature a normalized value of 100 represents a new drive, with + * a threshold value at 10 indicating a need for + * replacement. a value of 0 may mean that the drive is + * operating in read-only mode to allow data recovery. + * previously (pre-2010) occasionally used for drive + * temperature (more typically reported at 0xc2). + * + * common denominator is that the first raw byte reports the temperature + * in degrees c on almost all drives. some drives may report a fractional + * temperature in the second raw byte. + * + * known exceptions (from libatasmart): + * - samsung sv0412h and samsung sv1204h) report the temperature in 10th + * degrees c in the first two raw bytes. + * - a few maxtor drives report an unknown or bad value in attribute 194. + * - certain apple ssd drives report an unknown value in attribute 190. + * only certain firmware versions are affected. + * + * those exceptions affect older ata drives and are currently ignored. + * also, the second raw byte (possibly reporting the fractional temperature) + * is currently ignored. + * + * many drives also report temperature limits in additional smart data raw + * bytes. the format of those is not well defined and varies widely. + * the driver does not currently attempt to report those limits. + * + * according to data in smartmontools, attribute 231 is rarely used to report + * drive temperatures. at the same time, several drives report ssd life left + * in attribute 231, but do not support temperature sensors. for this reason, + * attribute 231 is currently ignored. + * + * following above definitions, temperatures are reported as follows. + * if sct command transport is supported, it is used to read the + * temperature and, if available, temperature limits. + * - otherwise, if smart attribute 194 is supported, it is used to read + * the temperature. + * - otherwise, if smart attribute 190 is supported, it is used to read + * the temperature. + */ + +#include <linux/ata.h> +#include <linux/bits.h> +#include <linux/device.h> +#include <linux/hwmon.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <scsi/scsi_cmnd.h> +#include <scsi/scsi_device.h> +#include <scsi/scsi_driver.h> +#include <scsi/scsi_proto.h> + +struct drivetemp_data { + struct list_head list; /* list of instantiated devices */ + struct mutex lock; /* protect data buffer accesses */ + struct scsi_device *sdev; /* scsi device */ + struct device *dev; /* instantiating device */ + struct device *hwdev; /* hardware monitoring device */ + u8 smartdata[ata_sect_size]; /* local buffer */ + int (*get_temp)(struct drivetemp_data *st, u32 attr, long *val); + bool have_temp_lowest; /* lowest temp in sct status */ + bool have_temp_highest; /* highest temp in sct status */ + bool have_temp_min; /* have min temp */ + bool have_temp_max; /* have max temp */ + bool have_temp_lcrit; /* have lower critical limit */ + bool have_temp_crit; /* have critical limit */ + int temp_min; /* min temp */ + int temp_max; /* max temp */ + int temp_lcrit; /* lower critical limit */ + int temp_crit; /* critical limit */ +}; + +static list_head(drivetemp_devlist); + +#define ata_max_smart_attrs 30 +#define smart_temp_prop_190 190 +#define smart_temp_prop_194 194 + +#define sct_status_req_addr 0xe0 +#define sct_status_version_low 0 /* log byte offsets */ +#define sct_status_version_high 1 +#define sct_status_temp 200 +#define sct_status_temp_lowest 201 +#define sct_status_temp_highest 202 +#define sct_read_log_addr 0xe1 +#define smart_read_log 0xd5 +#define smart_write_log 0xd6 + +#define invalid_temp 0x80 + +#define temp_is_valid(temp) ((temp) != invalid_temp) +#define temp_from_sct(temp) (((s8)(temp)) * 1000) + +static inline bool ata_id_smart_supported(u16 *id) +{ + return id[ata_id_command_set_1] & bit(0); +} + +static inline bool ata_id_smart_enabled(u16 *id) +{ + return id[ata_id_cfs_enable_1] & bit(0); +} + +static int drivetemp_scsi_command(struct drivetemp_data *st, + u8 ata_command, u8 feature, + u8 lba_low, u8 lba_mid, u8 lba_high) +{ + u8 scsi_cmd[max_command_size]; + int data_dir; + + memset(scsi_cmd, 0, sizeof(scsi_cmd)); + scsi_cmd[0] = ata_16; + if (ata_command == ata_cmd_smart && feature == smart_write_log) { + scsi_cmd[1] = (5 << 1); /* pio data-out */ + /* + * no off.line or cc, write to dev, block count in sector count + * field. + */ + scsi_cmd[2] = 0x06; + data_dir = dma_to_device; + } else { + scsi_cmd[1] = (4 << 1); /* pio data-in */ + /* + * no off.line or cc, read from dev, block count in sector count + * field. + */ + scsi_cmd[2] = 0x0e; + data_dir = dma_from_device; + } + scsi_cmd[4] = feature; + scsi_cmd[6] = 1; /* 1 sector */ + scsi_cmd[8] = lba_low; + scsi_cmd[10] = lba_mid; + scsi_cmd[12] = lba_high; + scsi_cmd[14] = ata_command; + + return scsi_execute_req(st->sdev, scsi_cmd, data_dir, + st->smartdata, ata_sect_size, null, hz, 5, + null); +} + +static int drivetemp_ata_command(struct drivetemp_data *st, u8 feature, + u8 select) +{ + return drivetemp_scsi_command(st, ata_cmd_smart, feature, select, + ata_smart_lbam_pass, ata_smart_lbah_pass); +} + +static int drivetemp_get_smarttemp(struct drivetemp_data *st, u32 attr, + long *temp) +{ + u8 *buf = st->smartdata; + bool have_temp = false; + u8 temp_raw; + u8 csum; + int err; + int i; + + err = drivetemp_ata_command(st, ata_smart_read_values, 0); + if (err) + return err; + + /* checksum the read value table */ + csum = 0; + for (i = 0; i < ata_sect_size; i++) + csum += buf[i]; + if (csum) { + dev_dbg(&st->sdev->sdev_gendev, + "checksum error reading smart values "); + return -eio; + } + + for (i = 0; i < ata_max_smart_attrs; i++) { + u8 *attr = buf + i * 12; + int id = attr[2]; + + if (!id) + continue; + + if (id == smart_temp_prop_190) { + temp_raw = attr[7]; + have_temp = true; + } + if (id == smart_temp_prop_194) { + temp_raw = attr[7]; + have_temp = true; + break; + } + } + + if (have_temp) { + *temp = temp_raw * 1000; + return 0; + } + + return -enxio; +} + +static int drivetemp_get_scttemp(struct drivetemp_data *st, u32 attr, long *val) +{ + u8 *buf = st->smartdata; + int err; + + err = drivetemp_ata_command(st, smart_read_log, sct_status_req_addr); + if (err) + return err; + switch (attr) { + case hwmon_temp_input: + *val = temp_from_sct(buf[sct_status_temp]); + break; + case hwmon_temp_lowest: + *val = temp_from_sct(buf[sct_status_temp_lowest]); + break; + case hwmon_temp_highest: + *val = temp_from_sct(buf[sct_status_temp_highest]); + break; + default: + err = -einval; + break; + } + return err; +} + +static int drivetemp_identify_sata(struct drivetemp_data *st) +{ + struct scsi_device *sdev = st->sdev; + u8 *buf = st->smartdata; + struct scsi_vpd *vpd; + bool is_ata, is_sata; + bool have_sct_data_table; + bool have_sct_temp; + bool have_smart; + bool have_sct; + u16 *ata_id; + u16 version; + long temp; + int err; + + /* scsi-ata translation present? */ + rcu_read_lock(); + vpd = rcu_dereference(sdev->vpd_pg89); + + /* + * verify that ata identify device data is included in ata information + * vpd and that the drive implements the sata protocol. + */ + if (!vpd || vpd->len < 572 || vpd->data[56] != ata_cmd_id_ata || + vpd->data[36] != 0x34) { + rcu_read_unlock(); + return -enodev; + } + ata_id = (u16 *)&vpd->data[60]; + is_ata = ata_id_is_ata(ata_id); + is_sata = ata_id_is_sata(ata_id); + have_sct = ata_id_sct_supported(ata_id); + have_sct_data_table = ata_id_sct_data_tables(ata_id); + have_smart = ata_id_smart_supported(ata_id) && + ata_id_smart_enabled(ata_id); + + rcu_read_unlock(); + + /* bail out if this is not a sata device */ + if (!is_ata || !is_sata) + return -enodev; + if (!have_sct) + goto skip_sct; + + err = drivetemp_ata_command(st, smart_read_log, sct_status_req_addr); + if (err) + goto skip_sct; + + version = (buf[sct_status_version_high] << 8) | + buf[sct_status_version_low]; + if (version != 2 && version != 3) + goto skip_sct; + + have_sct_temp = temp_is_valid(buf[sct_status_temp]); + if (!have_sct_temp) + goto skip_sct; + + st->have_temp_lowest = temp_is_valid(buf[sct_status_temp_lowest]); + st->have_temp_highest = temp_is_valid(buf[sct_status_temp_highest]); + + if (!have_sct_data_table) + goto skip_sct; + + /* request and read temperature history table */ + memset(buf, '', sizeof(st->smartdata)); + buf[0] = 5; /* data table command */ + buf[2] = 1; /* read table */ + buf[4] = 2; /* temperature history table */ + + err = drivetemp_ata_command(st, smart_write_log, sct_status_req_addr); + if (err) + goto skip_sct_data; + + err = drivetemp_ata_command(st, smart_read_log, sct_read_log_addr); + if (err) + goto skip_sct_data; + + /* + * temperature limits per at attachment 8 - + * ata/atapi command set (ata8-acs) + */ + st->have_temp_max = temp_is_valid(buf[6]); + st->have_temp_crit = temp_is_valid(buf[7]); + st->have_temp_min = temp_is_valid(buf[8]); + st->have_temp_lcrit = temp_is_valid(buf[9]); + + st->temp_max = temp_from_sct(buf[6]); + st->temp_crit = temp_from_sct(buf[7]); + st->temp_min = temp_from_sct(buf[8]); + st->temp_lcrit = temp_from_sct(buf[9]); + +skip_sct_data: + if (have_sct_temp) { + st->get_temp = drivetemp_get_scttemp; + return 0; + } +skip_sct: + if (!have_smart) + return -enodev; + st->get_temp = drivetemp_get_smarttemp; + return drivetemp_get_smarttemp(st, hwmon_temp_input, &temp); +} + +static int drivetemp_identify(struct drivetemp_data *st) +{ + struct scsi_device *sdev = st->sdev; + + /* bail out immediately if there is no inquiry data */ + if (!sdev->inquiry || sdev->inquiry_len < 16) + return -enodev; + + /* disk device? */ + if (sdev->type != type_disk && sdev->type != type_zbc) + return -enodev; + + return drivetemp_identify_sata(st); +} + +static int drivetemp_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + struct drivetemp_data *st = dev_get_drvdata(dev); + int err = 0; + + if (type != hwmon_temp) + return -einval; + + switch (attr) { + case hwmon_temp_input: + case hwmon_temp_lowest: + case hwmon_temp_highest: + mutex_lock(&st->lock); + err = st->get_temp(st, attr, val); + mutex_unlock(&st->lock); + break; + case hwmon_temp_lcrit: + *val = st->temp_lcrit; + break; + case hwmon_temp_min: + *val = st->temp_min; + break; + case hwmon_temp_max: + *val = st->temp_max; + break; + case hwmon_temp_crit: + *val = st->temp_crit; + break; + default: + err = -einval; + break; + } + return err; +} + +static umode_t drivetemp_is_visible(const void *data, + enum hwmon_sensor_types type, + u32 attr, int channel) +{ + const struct drivetemp_data *st = data; + + switch (type) { + case hwmon_temp: + switch (attr) { + case hwmon_temp_input: + return 0444; + case hwmon_temp_lowest: + if (st->have_temp_lowest) + return 0444; + break; + case hwmon_temp_highest: + if (st->have_temp_highest) + return 0444; + break; + case hwmon_temp_min: + if (st->have_temp_min) + return 0444; + break; + case hwmon_temp_max: + if (st->have_temp_max) + return 0444; + break; + case hwmon_temp_lcrit: + if (st->have_temp_lcrit) + return 0444; + break; + case hwmon_temp_crit: + if (st->have_temp_crit) + return 0444; + break; + default: + break; + } + break; + default: + break; + } + return 0; +} + +static const struct hwmon_channel_info *drivetemp_info[] = { + hwmon_channel_info(chip, + hwmon_c_register_tz), + hwmon_channel_info(temp, hwmon_t_input | + hwmon_t_lowest | hwmon_t_highest | + hwmon_t_min | hwmon_t_max | + hwmon_t_lcrit | hwmon_t_crit), + null +}; + +static const struct hwmon_ops drivetemp_ops = { + .is_visible = drivetemp_is_visible, + .read = drivetemp_read, +}; + +static const struct hwmon_chip_info drivetemp_chip_info = { + .ops = &drivetemp_ops, + .info = drivetemp_info, +}; + +/* + * the device argument points to sdev->sdev_dev. its parent is + * sdev->sdev_gendev, which we can use to get the scsi_device pointer. + */ +static int drivetemp_add(struct device *dev, struct class_interface *intf) +{ + struct scsi_device *sdev = to_scsi_device(dev->parent); + struct drivetemp_data *st; + int err; + + st = kzalloc(sizeof(*st), gfp_kernel); + if (!st) + return -enomem; + + st->sdev = sdev; + st->dev = dev; + mutex_init(&st->lock); + + if (drivetemp_identify(st)) { + err = -enodev; + goto abort; + } + + st->hwdev = hwmon_device_register_with_info(dev->parent, "drivetemp", + st, &drivetemp_chip_info, + null); + if (is_err(st->hwdev)) { + err = ptr_err(st->hwdev); + goto abort; + } + + list_add(&st->list, &drivetemp_devlist); + return 0; + +abort: + kfree(st); + return err; +} + +static void drivetemp_remove(struct device *dev, struct class_interface *intf) +{ + struct drivetemp_data *st, *tmp; + + list_for_each_entry_safe(st, tmp, &drivetemp_devlist, list) { + if (st->dev == dev) { + list_del(&st->list); + hwmon_device_unregister(st->hwdev); + kfree(st); + break; + } + } +} + +static struct class_interface drivetemp_interface = { + .add_dev = drivetemp_add, + .remove_dev = drivetemp_remove, +}; + +static int __init drivetemp_init(void) +{ + return scsi_register_interface(&drivetemp_interface); +} + +static void __exit drivetemp_exit(void) +{ + scsi_unregister_interface(&drivetemp_interface); +} + +module_init(drivetemp_init); +module_exit(drivetemp_exit); + +module_author("guenter roeck <linus@roeck-us.net>"); +module_description("hard drive temperature monitor"); +module_license("gpl");
|
Hardware monitoring (hwmon)
|
5b46903d8bf372e563bf2150d46b87fff197a109
|
guenter roeck
|
drivers
|
hwmon
| |
hwmon: (adm1177) add adm1177 hot swap controller and digital power monitor driver
|
adm1177 is a hot swap controller and digital power monitor with soft start pin.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add adm1177 hot swap controller and digital power monitor driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['adm1177']
|
['c', 'kconfig', 'makefile', 'rst']
| 5
| 336
| 0
|
--- diff --git a/documentation/hwmon/adm1177.rst b/documentation/hwmon/adm1177.rst --- /dev/null +++ b/documentation/hwmon/adm1177.rst +kernel driver adm1177 +===================== + +supported chips: + * analog devices adm1177 + prefix: 'adm1177' + datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/adm1177.pdf + +author: beniamin bia <beniamin.bia@analog.com> + + +description +----------- + +this driver supports hardware monitoring for analog devices adm1177 +hot-swap controller and digital power monitors with soft start pin. + + +usage notes +----------- + +this driver does not auto-detect devices. you will have to instantiate the +devices explicitly. please see documentation/i2c/instantiating-devices for +details. + + +sysfs entries +------------- + +the following attributes are supported. current maxim attribute +is read-write, all other attributes are read-only. + +in0_input measured voltage in microvolts. + +curr1_input measured current in microamperes. +curr1_max_alarm overcurrent alarm in microamperes. diff --git a/documentation/hwmon/index.rst b/documentation/hwmon/index.rst --- a/documentation/hwmon/index.rst +++ b/documentation/hwmon/index.rst + adm1177 diff --git a/drivers/hwmon/kconfig b/drivers/hwmon/kconfig --- a/drivers/hwmon/kconfig +++ b/drivers/hwmon/kconfig +config sensors_adm1177 + tristate "analog devices adm1177 and compatibles" + depends on i2c + help + if you say yes here you get support for analog devices adm1177 + sensor chips. + + this driver can also be built as a module. if so, the module + will be called adm1177. + diff --git a/drivers/hwmon/makefile b/drivers/hwmon/makefile --- a/drivers/hwmon/makefile +++ b/drivers/hwmon/makefile +obj-$(config_sensors_adm1177) += adm1177.o diff --git a/drivers/hwmon/adm1177.c b/drivers/hwmon/adm1177.c --- /dev/null +++ b/drivers/hwmon/adm1177.c +// spdx-license-identifier: gpl-2.0 +/* + * adm1177 hot swap controller and digital power monitor with soft start pin + * + * copyright 2015-2019 analog devices inc. + */ + +#include <linux/bits.h> +#include <linux/device.h> +#include <linux/hwmon.h> +#include <linux/i2c.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/regulator/consumer.h> + +/* command byte operations */ +#define adm1177_cmd_v_cont bit(0) +#define adm1177_cmd_i_cont bit(2) +#define adm1177_cmd_vrange bit(4) + +/* extended register */ +#define adm1177_reg_alert_th 2 + +#define adm1177_bits 12 + +/** + * struct adm1177_state - driver instance specific data + * @client pointer to i2c client + * @reg regulator info for the the power supply of the device + * @r_sense_uohm current sense resistor value + * @alert_threshold_ua current limit for shutdown + * @vrange_high internal voltage divider + */ +struct adm1177_state { + struct i2c_client *client; + struct regulator *reg; + u32 r_sense_uohm; + u32 alert_threshold_ua; + bool vrange_high; +}; + +static int adm1177_read_raw(struct adm1177_state *st, u8 num, u8 *data) +{ + return i2c_master_recv(st->client, data, num); +} + +static int adm1177_write_cmd(struct adm1177_state *st, u8 cmd) +{ + return i2c_smbus_write_byte(st->client, cmd); +} + +static int adm1177_write_alert_thr(struct adm1177_state *st, + u32 alert_threshold_ua) +{ + u64 val; + int ret; + + val = 0xffull * alert_threshold_ua * st->r_sense_uohm; + val = div_u64(val, 105840000u); + val = div_u64(val, 1000u); + if (val > 0xff) + val = 0xff; + + ret = i2c_smbus_write_byte_data(st->client, adm1177_reg_alert_th, + val); + if (ret) + return ret; + + st->alert_threshold_ua = alert_threshold_ua; + return 0; +} + +static int adm1177_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + struct adm1177_state *st = dev_get_drvdata(dev); + u8 data[3]; + long dummy; + int ret; + + switch (type) { + case hwmon_curr: + switch (attr) { + case hwmon_curr_input: + ret = adm1177_read_raw(st, 3, data); + if (ret < 0) + return ret; + dummy = (data[1] << 4) | (data[2] & 0xf); + /* + * convert to milliamperes + * ((105.84mv / 4096) x raw) / senseresistor(ohm) + */ + *val = div_u64((105840000ull * dummy), + 4096 * st->r_sense_uohm); + return 0; + case hwmon_curr_max_alarm: + *val = st->alert_threshold_ua; + return 0; + default: + return -eopnotsupp; + } + case hwmon_in: + ret = adm1177_read_raw(st, 3, data); + if (ret < 0) + return ret; + dummy = (data[0] << 4) | (data[2] >> 4); + /* + * convert to millivolts based on resistor devision + * (v_fullscale / 4096) * raw + */ + if (st->vrange_high) + dummy *= 26350; + else + dummy *= 6650; + + *val = div_round_closest(dummy, 4096); + return 0; + default: + return -eopnotsupp; + } +} + +static int adm1177_write(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long val) +{ + struct adm1177_state *st = dev_get_drvdata(dev); + + switch (type) { + case hwmon_curr: + switch (attr) { + case hwmon_curr_max_alarm: + adm1177_write_alert_thr(st, val); + return 0; + default: + return -eopnotsupp; + } + default: + return -eopnotsupp; + } +} + +static umode_t adm1177_is_visible(const void *data, + enum hwmon_sensor_types type, + u32 attr, int channel) +{ + const struct adm1177_state *st = data; + + switch (type) { + case hwmon_in: + switch (attr) { + case hwmon_in_input: + return 0444; + } + break; + case hwmon_curr: + switch (attr) { + case hwmon_curr_input: + if (st->r_sense_uohm) + return 0444; + return 0; + case hwmon_curr_max_alarm: + if (st->r_sense_uohm) + return 0644; + return 0; + } + break; + default: + break; + } + return 0; +} + +static const struct hwmon_channel_info *adm1177_info[] = { + hwmon_channel_info(curr, + hwmon_c_input | hwmon_c_max_alarm), + hwmon_channel_info(in, + hwmon_i_input), + null +}; + +static const struct hwmon_ops adm1177_hwmon_ops = { + .is_visible = adm1177_is_visible, + .read = adm1177_read, + .write = adm1177_write, +}; + +static const struct hwmon_chip_info adm1177_chip_info = { + .ops = &adm1177_hwmon_ops, + .info = adm1177_info, +}; + +static void adm1177_remove(void *data) +{ + struct adm1177_state *st = data; + + regulator_disable(st->reg); +} + +static int adm1177_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct device *hwmon_dev; + struct adm1177_state *st; + u32 alert_threshold_ua; + int ret; + + st = devm_kzalloc(dev, sizeof(*st), gfp_kernel); + if (!st) + return -enomem; + + st->client = client; + + st->reg = devm_regulator_get_optional(&client->dev, "vref"); + if (is_err(st->reg)) { + if (ptr_err(st->reg) == -eprobe_defer) + return -eprobe_defer; + + st->reg = null; + } else { + ret = regulator_enable(st->reg); + if (ret) + return ret; + ret = devm_add_action_or_reset(&client->dev, adm1177_remove, + st); + if (ret) + return ret; + } + + if (device_property_read_u32(dev, "shunt-resistor-micro-ohms", + &st->r_sense_uohm)) + st->r_sense_uohm = 0; + if (device_property_read_u32(dev, "adi,shutdown-threshold-microamp", + &alert_threshold_ua)) { + if (st->r_sense_uohm) + /* + * set maximum default value from datasheet based on + * shunt-resistor + */ + alert_threshold_ua = div_u64(105840000000, + st->r_sense_uohm); + else + alert_threshold_ua = 0; + } + st->vrange_high = device_property_read_bool(dev, + "adi,vrange-high-enable"); + if (alert_threshold_ua && st->r_sense_uohm) + adm1177_write_alert_thr(st, alert_threshold_ua); + + ret = adm1177_write_cmd(st, adm1177_cmd_v_cont | + adm1177_cmd_i_cont | + (st->vrange_high ? 0 : adm1177_cmd_vrange)); + if (ret) + return ret; + + hwmon_dev = + devm_hwmon_device_register_with_info(dev, client->name, st, + &adm1177_chip_info, null); + return ptr_err_or_zero(hwmon_dev); +} + +static const struct i2c_device_id adm1177_id[] = { + {"adm1177", 0}, + {} +}; +module_device_table(i2c, adm1177_id); + +static const struct of_device_id adm1177_dt_ids[] = { + { .compatible = "adi,adm1177" }, + {}, +}; +module_device_table(of, adm1177_dt_ids); + +static struct i2c_driver adm1177_driver = { + .class = i2c_class_hwmon, + .driver = { + .name = "adm1177", + .of_match_table = adm1177_dt_ids, + }, + .probe = adm1177_probe, + .id_table = adm1177_id, +}; +module_i2c_driver(adm1177_driver); + +module_author("beniamin bia <beniamin.bia@analog.com>"); +module_author("michael hennerich <michael.hennerich@analog.com>"); +module_description("analog devices adm1177 adc driver"); +module_license("gpl v2");
|
Hardware monitoring (hwmon)
|
09b08ac9e8d5869c1840de423cd361161964fe8e
|
beniamin bia
|
drivers
|
hwmon
| |
hwmon: (k10temp) add debugfs support
|
show thermal and svi registers for family 17h cpus.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add debugfs support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['k10temp']
|
['c']
| 1
| 77
| 1
|
--- diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c --- a/drivers/hwmon/k10temp.c +++ b/drivers/hwmon/k10temp.c +#include <linux/debugfs.h> +#ifdef config_debug_fs + +static void k10temp_smn_regs_show(struct seq_file *s, struct pci_dev *pdev, + u32 addr, int count) +{ + u32 reg; + int i; + + for (i = 0; i < count; i++) { + if (!(i & 3)) + seq_printf(s, "0x%06x: ", addr + i * 4); + amd_smn_read(amd_pci_dev_to_node_id(pdev), addr + i * 4, ®); + seq_printf(s, "%08x ", reg); + if ((i & 3) == 3) + seq_puts(s, " "); + } +} + +static int svi_show(struct seq_file *s, void *unused) +{ + struct k10temp_data *data = s->private; + + k10temp_smn_regs_show(s, data->pdev, f17h_m01h_svi, 32); + return 0; +} +define_show_attribute(svi); + +static int thm_show(struct seq_file *s, void *unused) +{ + struct k10temp_data *data = s->private; + + k10temp_smn_regs_show(s, data->pdev, + f17h_m01h_reported_temp_ctrl_offset, 256); + return 0; +} +define_show_attribute(thm); + +static void k10temp_debugfs_cleanup(void *ddir) +{ + debugfs_remove_recursive(ddir); +} + +static void k10temp_init_debugfs(struct k10temp_data *data) +{ + struct dentry *debugfs; + char name[32]; + + /* only show debugfs data for family 17h/18h cpus */ + if (!data->show_tdie) + return; + + scnprintf(name, sizeof(name), "k10temp-%s", pci_name(data->pdev)); + + debugfs = debugfs_create_dir(name, null); + if (debugfs) { + debugfs_create_file("svi", 0444, debugfs, data, &svi_fops); + debugfs_create_file("thm", 0444, debugfs, data, &thm_fops); + devm_add_action_or_reset(&data->pdev->dev, + k10temp_debugfs_cleanup, debugfs); + } +} + +#else + +static void k10temp_init_debugfs(struct k10temp_data *data) +{ +} + +#endif + - return ptr_err_or_zero(hwmon_dev); + if (is_err(hwmon_dev)) + return ptr_err(hwmon_dev); + + k10temp_init_debugfs(data); + + return 0;
|
Hardware monitoring (hwmon)
|
9c4a38f19ed2bda2df2765e98ed661daf61b2cb2
|
guenter roeck sebastian reichel sebastian reichel collabora com
|
drivers
|
hwmon
| |
hwmon: (k10temp) display up to eight sets of ccd temperatures
|
in hwinfo, we see support for tccd1, tccd3, tccd5, and tccd7 temperature sensors on zen2 based threadripper cpus. checking register maps on threadripper 3970x confirms smn register addresses and values for those sensors.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
display up to eight sets of ccd temperatures
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['k10temp']
|
['c']
| 1
| 41
| 41
|
--- diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c --- a/drivers/hwmon/k10temp.c +++ b/drivers/hwmon/k10temp.c - * - ccd1 and ccd2 register address information as well as the calculation to + * - ccd register address information as well as the calculation to - * - it is unknown if the mechanism to read ccd1/ccd2 temperature as well as - * current and voltage information works on higher-end ryzen cpus. - * information reported by windows tools suggests that additional sensors - * (both temperature and voltage/current) are supported, but their register - * location is currently unknown. -#define f17h_m70h_ccd1_temp 0x00059954 -#define f17h_m70h_ccd2_temp 0x00059958 + +#define f17h_m70h_ccd_temp(x) (0x00059954 + ((x) * 4)) +#define f17h_m70h_ccd_temp_valid bit(11) +#define f17h_m70h_ccd_temp_mask genmask(10, 0) - bool show_tccd1; - bool show_tccd2; + u32 show_tccd; + "tccd3", + "tccd4", + "tccd5", + "tccd6", + "tccd7", + "tccd8", - case 2: /* tccd1 */ - amd_smn_read(amd_pci_dev_to_node_id(data->pdev), - f17h_m70h_ccd1_temp, ®val); - *val = (regval & 0xfff) * 125 - 305000; - break; - case 3: /* tccd2 */ + case 2 ... 9: /* tccd{1-8} */ - f17h_m70h_ccd2_temp, ®val); - *val = (regval & 0xfff) * 125 - 305000; + f17h_m70h_ccd_temp(channel - 2), ®val); + *val = (regval & f17h_m70h_ccd_temp_mask) * 125 - 49000; - case 2: /* tccd1 */ - if (!data->show_tccd1) - return 0; - break; - case 3: /* tccd2 */ - if (!data->show_tccd2) + case 2 ... 9: /* tccd{1-8} */ + if (!(data->show_tccd & bit(channel - 2))) - case 2: /* tccd1 */ - if (!data->show_tccd1) - return 0; - break; - case 3: /* tccd2 */ - if (!data->show_tccd2) + case 2 ... 9: /* tccd{1-8} */ + if (!(data->show_tccd & bit(channel - 2))) + hwmon_t_input | hwmon_t_label, + hwmon_t_input | hwmon_t_label, + hwmon_t_input | hwmon_t_label, + hwmon_t_input | hwmon_t_label, + hwmon_t_input | hwmon_t_label, + hwmon_t_input | hwmon_t_label, +static void k10temp_get_ccd_support(struct pci_dev *pdev, + struct k10temp_data *data, int limit) +{ + u32 regval; + int i; + + for (i = 0; i < limit; i++) { + amd_smn_read(amd_pci_dev_to_node_id(pdev), + f17h_m70h_ccd_temp(i), ®val); + if (regval & f17h_m70h_ccd_temp_valid) + data->show_tccd |= bit(i); + } +} + - u32 regval; - + k10temp_get_ccd_support(pdev, data, 4); - amd_smn_read(amd_pci_dev_to_node_id(pdev), - f17h_m70h_ccd1_temp, ®val); - if (regval & 0xfff) - data->show_tccd1 = true; - - amd_smn_read(amd_pci_dev_to_node_id(pdev), - f17h_m70h_ccd2_temp, ®val); - if (regval & 0xfff) - data->show_tccd2 = true; + k10temp_get_ccd_support(pdev, data, 8);
|
Hardware monitoring (hwmon)
|
fd8bdb23b91876ac1e624337bb88dc1dcc21d67e
|
guenter roeck
|
drivers
|
hwmon
| |
hwmon: (k10temp) report temperatures per cpu die
|
zen2 reports reporting temperatures per cpu die (called core complex dies, or ccd, by amd). add support for it to the k10temp driver.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
report temperatures per cpu die
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['k10temp']
|
['c']
| 1
| 79
| 1
|
--- diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c --- a/drivers/hwmon/k10temp.c +++ b/drivers/hwmon/k10temp.c + * + * implementation notes: + * - ccd1 and ccd2 register address information as well as the calculation to + * convert raw register values is from https://github.com/ocerman/zenpower. + * the information is not confirmed from chip datasheets, but experiments + * suggest that it provides reasonable temperature values. +#define f17h_m70h_ccd1_temp 0x00059954 +#define f17h_m70h_ccd2_temp 0x00059958 + bool show_tccd1; + bool show_tccd2; + "tccd1", + "tccd2", + case 2: /* tccd1 */ + amd_smn_read(amd_pci_dev_to_node_id(data->pdev), + f17h_m70h_ccd1_temp, ®val); + *val = (regval & 0xfff) * 125 - 305000; + break; + case 3: /* tccd2 */ + amd_smn_read(amd_pci_dev_to_node_id(data->pdev), + f17h_m70h_ccd2_temp, ®val); + *val = (regval & 0xfff) * 125 - 305000; + break; - if (channel && !data->show_tdie) + switch (channel) { + case 0: /* tdie, or tctl if we don't show it */ + break; + case 1: /* tctl */ + if (!data->show_tdie) + return 0; + break; + case 2: /* tccd1 */ + if (!data->show_tccd1) + return 0; + break; + case 3: /* tccd2 */ + if (!data->show_tccd2) + return 0; + break; + default: + } + /* no labels if we don't show the die temperature */ + switch (channel) { + case 0: /* tdie */ + case 1: /* tctl */ + break; + case 2: /* tccd1 */ + if (!data->show_tccd1) + return 0; + break; + case 3: /* tccd2 */ + if (!data->show_tccd2) + return 0; + break; + default: + return 0; + } + hwmon_t_input | hwmon_t_label, + hwmon_t_input | hwmon_t_label, + u32 regval; + + + switch (boot_cpu_data.x86_model) { + case 0x1: /* zen */ + case 0x8: /* zen+ */ + case 0x11: /* zen apu */ + case 0x18: /* zen+ apu */ + break; + case 0x31: /* zen2 threadripper */ + case 0x71: /* zen2 */ + amd_smn_read(amd_pci_dev_to_node_id(pdev), + f17h_m70h_ccd1_temp, ®val); + if (regval & 0xfff) + data->show_tccd1 = true; + + amd_smn_read(amd_pci_dev_to_node_id(pdev), + f17h_m70h_ccd2_temp, ®val); + if (regval & 0xfff) + data->show_tccd2 = true; + break; + }
|
Hardware monitoring (hwmon)
|
c757938929c9e1de52e31400f673fac02e1f26bb
|
guenter roeck brad campbell lists fnarfbargle com bernhard gebetsberger bernhard gebetsberger gmx at holger kiehl holger kiehl dwd de michael larabel michael phoronix com jonathan mcdowell noodles earth li ken moffat zarniwhoop googlemail com darren salt devspam moreofthesa me uk
|
drivers
|
hwmon
| |
hwmon: (k10temp) show core and soc current and voltages on ryzen cpus
|
ryzen cpus report core and soc voltages and currents. add support for it to the k10temp driver.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
show core and soc current and voltages on ryzen cpus
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['k10temp']
|
['c']
| 1
| 131
| 3
|
--- diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c --- a/drivers/hwmon/k10temp.c +++ b/drivers/hwmon/k10temp.c + * - register addresses to read chip voltage and current are also from + * https://github.com/ocerman/zenpower, and not confirmed from chip + * datasheets. current calibration is board specific and not typically + * shared by board vendors. for this reason, current values are + * normalized to report 1a/lsb for core current and and 0.25a/lsb for soc + * current. reported values can be adjusted using the sensors configuration + * file. + * - it is unknown if the mechanism to read ccd1/ccd2 temperature as well as + * current and voltage information works on higher-end ryzen cpus. + * information reported by windows tools suggests that additional sensors + * (both temperature and voltage/current) are supported, but their register + * location is currently unknown. +#define f17h_m01h_svi 0x0005a000 +#define f17h_m01h_svi_tel_plane0 (f17h_m01h_svi + 0xc) +#define f17h_m01h_svi_tel_plane1 (f17h_m01h_svi + 0x10) + +#define cfactor_icore 1000000 /* 1a / lsb */ +#define cfactor_isoc 250000 /* 0.25a / lsb */ + + u32 svi_addr[2]; + bool show_current; + int cfactor[2]; +static bool is_threadripper(void) +{ + return strstr(boot_cpu_data.x86_model_id, "threadripper"); +} + +static bool is_epyc(void) +{ + return strstr(boot_cpu_data.x86_model_id, "epyc"); +} + +const char *k10temp_in_label[] = { + "vcore", + "vsoc", +}; + +const char *k10temp_curr_label[] = { + "icore", + "isoc", +}; + - *str = k10temp_temp_label[channel]; + switch (type) { + case hwmon_temp: + *str = k10temp_temp_label[channel]; + break; + case hwmon_in: + *str = k10temp_in_label[channel]; + break; + case hwmon_curr: + *str = k10temp_curr_label[channel]; + break; + default: + return -eopnotsupp; + } -static int k10temp_read(struct device *dev, enum hwmon_sensor_types type, - u32 attr, int channel, long *val) +static int k10temp_read_curr(struct device *dev, u32 attr, int channel, + long *val) +{ + struct k10temp_data *data = dev_get_drvdata(dev); + u32 regval; + + switch (attr) { + case hwmon_curr_input: + amd_smn_read(amd_pci_dev_to_node_id(data->pdev), + data->svi_addr[channel], ®val); + *val = div_round_closest(data->cfactor[channel] * + (regval & 0xff), + 1000); + break; + default: + return -eopnotsupp; + } + return 0; +} + +static int k10temp_read_in(struct device *dev, u32 attr, int channel, long *val) +{ + struct k10temp_data *data = dev_get_drvdata(dev); + u32 regval; + + switch (attr) { + case hwmon_in_input: + amd_smn_read(amd_pci_dev_to_node_id(data->pdev), + data->svi_addr[channel], ®val); + regval = (regval >> 16) & 0xff; + *val = div_round_closest(155000 - regval * 625, 100); + break; + default: + return -eopnotsupp; + } + return 0; +} + +static int k10temp_read_temp(struct device *dev, u32 attr, int channel, + long *val) +static int k10temp_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + switch (type) { + case hwmon_temp: + return k10temp_read_temp(dev, attr, channel, val); + case hwmon_in: + return k10temp_read_in(dev, attr, channel, val); + case hwmon_curr: + return k10temp_read_curr(dev, attr, channel, val); + default: + return -eopnotsupp; + } +} + + case hwmon_in: + case hwmon_curr: + if (!data->show_current) + return 0; + break; + hwmon_channel_info(in, + hwmon_i_input | hwmon_i_label, + hwmon_i_input | hwmon_i_label), + hwmon_channel_info(curr, + hwmon_c_input | hwmon_c_label, + hwmon_c_input | hwmon_c_label), + data->show_current = !is_threadripper() && !is_epyc(); + data->svi_addr[0] = f17h_m01h_svi_tel_plane0; + data->svi_addr[1] = f17h_m01h_svi_tel_plane1; + data->cfactor[0] = cfactor_icore; + data->cfactor[1] = cfactor_isoc; + data->show_current = !is_threadripper() && !is_epyc(); + data->cfactor[0] = cfactor_icore; + data->cfactor[1] = cfactor_isoc; + data->svi_addr[0] = f17h_m01h_svi_tel_plane1; + data->svi_addr[1] = f17h_m01h_svi_tel_plane0;
|
Hardware monitoring (hwmon)
|
b00647c46c9d7f6ee1ff6aaf335906101755e614
|
guenter roeck
|
drivers
|
hwmon
| |
hwmon: (pmbus/ibm-cffps) add new manufacturer debugfs entries
|
add support for a number of manufacturer-specific registers in the debugfs entries, as well as support to read and write the pmbus_on_off_config register through debugfs.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add new manufacturer debugfs entries
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['pmbus/ibm-cffps']
|
['c']
| 1
| 70
| 4
|
--- diff --git a/drivers/hwmon/pmbus/ibm-cffps.c b/drivers/hwmon/pmbus/ibm-cffps.c --- a/drivers/hwmon/pmbus/ibm-cffps.c +++ b/drivers/hwmon/pmbus/ibm-cffps.c +#define cffps_header_cmd 0x9c +#define cffps_max_power_out_cmd 0xa7 + cffps_debugfs_header, + cffps_debugfs_max_power_out, + cffps_debugfs_on_off_config, -static ssize_t ibm_cffps_debugfs_op(struct file *file, char __user *buf, - size_t count, loff_t *ppos) +static ssize_t ibm_cffps_debugfs_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos) - char data[i2c_smbus_block_max] = { 0 }; + char data[i2c_smbus_block_max + 2] = { 0 }; + case cffps_debugfs_header: + cmd = cffps_header_cmd; + break; + case cffps_debugfs_max_power_out: + rc = i2c_smbus_read_word_swapped(psu->client, + cffps_max_power_out_cmd); + if (rc < 0) + return rc; + + rc = snprintf(data, i2c_smbus_block_max, "%d", rc); + goto done; + case cffps_debugfs_on_off_config: + rc = i2c_smbus_read_byte_data(psu->client, + pmbus_on_off_config); + if (rc < 0) + return rc; + + rc = snprintf(data, 3, "%02x", rc); + goto done; +static ssize_t ibm_cffps_debugfs_write(struct file *file, + const char __user *buf, size_t count, + loff_t *ppos) +{ + u8 data; + ssize_t rc; + int *idxp = file->private_data; + int idx = *idxp; + struct ibm_cffps *psu = to_psu(idxp, idx); + + switch (idx) { + case cffps_debugfs_on_off_config: + pmbus_set_page(psu->client, 0); + + rc = simple_write_to_buffer(&data, 1, ppos, buf, count); + if (rc < 0) + return rc; + + rc = i2c_smbus_write_byte_data(psu->client, + pmbus_on_off_config, data); + if (rc) + return rc; + + rc = 1; + break; + default: + return -einval; + } + + return rc; +} + - .read = ibm_cffps_debugfs_op, + .read = ibm_cffps_debugfs_read, + .write = ibm_cffps_debugfs_write, + debugfs_create_file("header", 0444, ibm_cffps_dir, + &psu->debugfs_entries[cffps_debugfs_header], + &ibm_cffps_fops); + debugfs_create_file("max_power_out", 0444, ibm_cffps_dir, + &psu->debugfs_entries[cffps_debugfs_max_power_out], + &ibm_cffps_fops); + debugfs_create_file("on_off_config", 0644, ibm_cffps_dir, + &psu->debugfs_entries[cffps_debugfs_on_off_config], + &ibm_cffps_fops);
|
Hardware monitoring (hwmon)
|
abe508b66d23cf2ed18c991c200b957e92f4bfbc
|
eddie james
|
drivers
|
hwmon
|
pmbus
|
hwmon: (pmbus/ibm-cffps) add the vmon property for version 2
|
version 2 of the psu supports reading an auxiliary voltage. use the pmbus vmon property and associated virtual register to read it.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add the vmon property for version 2
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['pmbus/ibm-cffps']
|
['c']
| 1
| 5
| 1
|
--- diff --git a/drivers/hwmon/pmbus/ibm-cffps.c b/drivers/hwmon/pmbus/ibm-cffps.c --- a/drivers/hwmon/pmbus/ibm-cffps.c +++ b/drivers/hwmon/pmbus/ibm-cffps.c +#define cffps_12vcs_vout_cmd 0xde + case pmbus_virt_read_vmon: + rc = pmbus_read_word_data(client, page, cffps_12vcs_vout_cmd); + break; - pmbus_have_status_fan12, + pmbus_have_status_fan12 | pmbus_have_vmon,
|
Hardware monitoring (hwmon)
|
1952d79a0d2635c9130a48a598dd2f1eea70c45b
|
eddie james
|
drivers
|
hwmon
|
pmbus
|
hwmon: (pmbus/ucd9000) add support for ucd90320 power sequencer
|
add support for the ucd90320 chip and its expanded set of gpio pins.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for ucd90320 power sequencer
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['pmbus/ucd9000']
|
['c', 'kconfig', 'rst']
| 3
| 40
| 17
|
--- diff --git a/documentation/hwmon/ucd9000.rst b/documentation/hwmon/ucd9000.rst --- a/documentation/hwmon/ucd9000.rst +++ b/documentation/hwmon/ucd9000.rst - * ti ucd90120, ucd90124, ucd90160, ucd9090, and ucd90910 + * ti ucd90120, ucd90124, ucd90160, ucd90320, ucd9090, and ucd90910 - prefixes: 'ucd90120', 'ucd90124', 'ucd90160', 'ucd9090', 'ucd90910' + prefixes: 'ucd90120', 'ucd90124', 'ucd90160', 'ucd90320', 'ucd9090', + 'ucd90910' - http://focus.ti.com/lit/ds/symlink/ucd90120.pdf - http://focus.ti.com/lit/ds/symlink/ucd90124.pdf - http://focus.ti.com/lit/ds/symlink/ucd90160.pdf + - http://focus.ti.com/lit/ds/symlink/ucd90320.pdf - http://focus.ti.com/lit/ds/symlink/ucd9090.pdf - http://focus.ti.com/lit/ds/symlink/ucd90910.pdf +the ucd90320 is a 32-rail pmbus/i2c addressable power-supply sequencer and +monitor. the 24 integrated adc channels (amonx) monitor the power supply +voltage, current, and temperature. of the 84 gpio pins, 8 can be used as +digital monitors (dmonx), 32 to enable the power supply (enx), 24 for margining +(marx), 16 for logical gpo, and 32 gpis for cascading, and system function. + diff --git a/drivers/hwmon/pmbus/kconfig b/drivers/hwmon/pmbus/kconfig --- a/drivers/hwmon/pmbus/kconfig +++ b/drivers/hwmon/pmbus/kconfig - tristate "ti ucd90120, ucd90124, ucd90160, ucd9090, ucd90910" + tristate "ti ucd90120, ucd90124, ucd90160, ucd90320, ucd9090, ucd90910" - ucd90120, ucd90124, ucd90160, ucd9090, ucd90910, sequencer and system - health controllers. + ucd90120, ucd90124, ucd90160, ucd90320, ucd9090, ucd90910, sequencer + and system health controllers. diff --git a/drivers/hwmon/pmbus/ucd9000.c b/drivers/hwmon/pmbus/ucd9000.c --- a/drivers/hwmon/pmbus/ucd9000.c +++ b/drivers/hwmon/pmbus/ucd9000.c -enum chips { ucd9000, ucd90120, ucd90124, ucd90160, ucd9090, ucd90910 }; +enum chips { ucd9000, ucd90120, ucd90124, ucd90160, ucd90320, ucd9090, + ucd90910 }; -#define ucd9000_mon_page(x) ((x) & 0x0f) +#define ucd9000_mon_page(x) ((x) & 0x1f) +#define ucd90320_num_gpios 84 +#define ucd90320_gpi_count 32 + {"ucd90320", ucd90320}, + { + .compatible = "ti,ucd90320", + .data = (void *)ucd90320 + }, + case ucd90320: + data->gpio.ngpio = ucd90320_num_gpios; + break; - int ret; + int ret, i; - * attribute only created for devices with gpi fault bits at bits - * 16-23, which is the second byte of the response. + * gpi fault bits are in sets of 8, two bytes from end of response. - *val = !!(buffer[1] & bit(entry->index)); + i = ret - 3 - entry->index / 8; + if (i >= 0) + *val = !!(buffer[i] & bit(entry->index % 8)); - int i; + int i, gpi_count; - * and ucd90910 report gpi faults in their mfr_status register, so only - * create the gpi fault debugfs attributes for those chips. + * ucd90320, and ucd90910 report gpi faults in their mfr_status + * register, so only create the gpi fault debugfs attributes for those + * chips. - mid->driver_data == ucd90910) { + mid->driver_data == ucd90320 || mid->driver_data == ucd90910) { + gpi_count = mid->driver_data == ucd90320 ? ucd90320_gpi_count + : ucd9000_gpi_count; - ucd9000_gpi_count, sizeof(*entries), + gpi_count, sizeof(*entries), - for (i = 0; i < ucd9000_gpi_count; i++) { + for (i = 0; i < gpi_count; i++) {
|
Hardware monitoring (hwmon)
|
a470f11c5ba2febbbba941167e106c726bc1297b
|
jim wright
|
drivers
|
hwmon
|
pmbus
|
hwmon: (pmbus) add max20796 to devices supported by generic pmbus driver
|
max20796 is a dual-phase scalable integrated voltage regulator with pmbus interface.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add max20796 to devices supported by generic pmbus driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['pmbus']
|
['c', 'kconfig', 'rst']
| 3
| 13
| 2
|
--- diff --git a/documentation/hwmon/pmbus.rst b/documentation/hwmon/pmbus.rst --- a/documentation/hwmon/pmbus.rst +++ b/documentation/hwmon/pmbus.rst + * maxim max20796 + + prefix: 'max20796' + + addresses scanned: - + + datasheet: + + not published + diff --git a/drivers/hwmon/pmbus/kconfig b/drivers/hwmon/pmbus/kconfig --- a/drivers/hwmon/pmbus/kconfig +++ b/drivers/hwmon/pmbus/kconfig - mdt040, ncp4200, ncp4208, pdt003, pdt006, pdt012, tps40400, tps544b20, - tps544b25, tps544c20, tps544c25, and udt020. + max20796, mdt040, ncp4200, ncp4208, pdt003, pdt006, pdt012, tps40400, + tps544b20, tps544b25, tps544c20, tps544c25, and udt020. diff --git a/drivers/hwmon/pmbus/pmbus.c b/drivers/hwmon/pmbus/pmbus.c --- a/drivers/hwmon/pmbus/pmbus.c +++ b/drivers/hwmon/pmbus/pmbus.c + {"max20796", (kernel_ulong_t)&pmbus_info_one},
|
Hardware monitoring (hwmon)
|
1a1ea120afdff06174c62101020005949e0b2056
|
guenter roeck
|
drivers
|
hwmon
|
pmbus
|
hwmon: (pmbus/core) add support for vid mode detection per page bases
|
add support for vid protocol detection per page bases, instead of detecting it based on "pmbu_vout" readout from page 0 for all the pages supported by particular device. the reason that some devices allows to configure different vid modes per page within the same device. patch modifies the field "vrm_version" within the structure "pmbus_driver_info" to be per page array.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for vid mode calculation per page bases
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['pmbus']
|
['c', 'h']
| 6
| 53
| 46
|
--- diff --git a/drivers/hwmon/pmbus/max20751.c b/drivers/hwmon/pmbus/max20751.c --- a/drivers/hwmon/pmbus/max20751.c +++ b/drivers/hwmon/pmbus/max20751.c - .vrm_version = vr12, + .vrm_version[0] = vr12, diff --git a/drivers/hwmon/pmbus/pmbus.c b/drivers/hwmon/pmbus/pmbus.c --- a/drivers/hwmon/pmbus/pmbus.c +++ b/drivers/hwmon/pmbus/pmbus.c - int vout_mode; + int vout_mode, i; - info->vrm_version = vr11; + for (i = 0; i < info->pages; i++) + info->vrm_version[i] = vr11; diff --git a/drivers/hwmon/pmbus/pmbus.h b/drivers/hwmon/pmbus/pmbus.h --- a/drivers/hwmon/pmbus/pmbus.h +++ b/drivers/hwmon/pmbus/pmbus.h - enum vrm_version vrm_version; + enum vrm_version vrm_version[pmbus_pages]; /* vrm version per page */ diff --git a/drivers/hwmon/pmbus/pmbus_core.c b/drivers/hwmon/pmbus/pmbus_core.c --- a/drivers/hwmon/pmbus/pmbus_core.c +++ b/drivers/hwmon/pmbus/pmbus_core.c - switch (data->info->vrm_version) { + switch (data->info->vrm_version[sensor->page]) { diff --git a/drivers/hwmon/pmbus/pxe1610.c b/drivers/hwmon/pmbus/pxe1610.c --- a/drivers/hwmon/pmbus/pxe1610.c +++ b/drivers/hwmon/pmbus/pxe1610.c - if (pmbus_check_byte_register(client, 0, pmbus_vout_mode)) { - u8 vout_mode; - int ret; - - /* read the register with vout scaling value.*/ - ret = pmbus_read_byte_data(client, 0, pmbus_vout_mode); - if (ret < 0) - return ret; - - vout_mode = ret & genmask(4, 0); - - switch (vout_mode) { - case 1: - info->vrm_version = vr12; - break; - case 2: - info->vrm_version = vr13; - break; - default: - return -enodev; + int i; + + for (i = 0; i < pxe1610_num_pages; i++) { + if (pmbus_check_byte_register(client, i, pmbus_vout_mode)) { + u8 vout_mode; + int ret; + + /* read the register with vout scaling value.*/ + ret = pmbus_read_byte_data(client, i, pmbus_vout_mode); + if (ret < 0) + return ret; + + vout_mode = ret & genmask(4, 0); + + switch (vout_mode) { + case 1: + info->vrm_version[i] = vr12; + break; + case 2: + info->vrm_version[i] = vr13; + break; + default: + return -enodev; + } diff --git a/drivers/hwmon/pmbus/tps53679.c b/drivers/hwmon/pmbus/tps53679.c --- a/drivers/hwmon/pmbus/tps53679.c +++ b/drivers/hwmon/pmbus/tps53679.c - int ret; - - /* read the register with vout scaling value.*/ - ret = pmbus_read_byte_data(client, 0, pmbus_vout_mode); - if (ret < 0) - return ret; - - vout_params = ret & genmask(4, 0); - - switch (vout_params) { - case tps53679_prot_vr13_10mv: - case tps53679_prot_vr12_5_10mv: - info->vrm_version = vr13; - break; - case tps53679_prot_vr13_5mv: - case tps53679_prot_vr12_5mv: - case tps53679_prot_imvp8_5mv: - info->vrm_version = vr12; - break; - default: - return -einval; + int i, ret; + + for (i = 0; i < tps53679_page_num; i++) { + /* read the register with vout scaling value.*/ + ret = pmbus_read_byte_data(client, i, pmbus_vout_mode); + if (ret < 0) + return ret; + + vout_params = ret & genmask(4, 0); + + switch (vout_params) { + case tps53679_prot_vr13_10mv: + case tps53679_prot_vr12_5_10mv: + info->vrm_version[i] = vr13; + break; + case tps53679_prot_vr13_5mv: + case tps53679_prot_vr12_5mv: + case tps53679_prot_imvp8_5mv: + info->vrm_version[i] = vr12; + break; + default: + return -einval; + }
|
Hardware monitoring (hwmon)
|
b9fa0a3acfd86c7d02cf0aac5105c0297bf3c5b0
|
vadim pasternak
|
drivers
|
hwmon
|
pmbus
|
hwmon: (pmbus/core) add support for intel imvp9 and amd 6.25mv modes
|
extend "vrm_version" with the type for intel imvp9 and amd 6.25mv vid modes. add calculation for those types.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for vid mode calculation per page bases
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['pmbus']
|
['h', 'c']
| 2
| 9
| 1
|
--- diff --git a/drivers/hwmon/pmbus/pmbus.h b/drivers/hwmon/pmbus/pmbus.h --- a/drivers/hwmon/pmbus/pmbus.h +++ b/drivers/hwmon/pmbus/pmbus.h -enum vrm_version { vr11 = 0, vr12, vr13 }; +enum vrm_version { vr11 = 0, vr12, vr13, imvp9, amd625mv }; diff --git a/drivers/hwmon/pmbus/pmbus_core.c b/drivers/hwmon/pmbus/pmbus_core.c --- a/drivers/hwmon/pmbus/pmbus_core.c +++ b/drivers/hwmon/pmbus/pmbus_core.c + case imvp9: + if (val >= 0x01) + rv = 200 + (val - 1) * 10; + break; + case amd625mv: + if (val >= 0x0 && val <= 0xd8) + rv = div_round_closest(155000 - val * 625, 100); + break;
|
Hardware monitoring (hwmon)
|
9d72340b6ade9457fc79c7059fcc62e5b888f9a5
|
vadim pasternak
|
drivers
|
hwmon
|
pmbus
|
hwmon: (pmbus/tps53679) extend device list supported by driver
|
extends driver with support of the additional devices: texas instruments dual channel dcap+ multiphase controllers: tps53688.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for vid mode calculation per page bases
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['pmbus']
|
['c', 'kconfig']
| 2
| 4
| 2
|
--- diff --git a/drivers/hwmon/pmbus/kconfig b/drivers/hwmon/pmbus/kconfig --- a/drivers/hwmon/pmbus/kconfig +++ b/drivers/hwmon/pmbus/kconfig - tristate "ti tps53679" + tristate "ti tps53679, tps53688" - tps53679. + tps53679, tps53688 diff --git a/drivers/hwmon/pmbus/tps53679.c b/drivers/hwmon/pmbus/tps53679.c --- a/drivers/hwmon/pmbus/tps53679.c +++ b/drivers/hwmon/pmbus/tps53679.c + {"tps53688", 0}, + {.compatible = "ti,tps53688"},
|
Hardware monitoring (hwmon)
|
583dc921275c5a0cc7f657550cbf0caae7bf49c3
|
vadim pasternak
|
drivers
|
hwmon
|
pmbus
|
hwmon: (pmbus) add support for infineon multi-phase xdpe122 family controllers
|
add support for devices xdpe12254, xdpe12284.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for vid mode calculation per page bases
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['pmbus']
|
['c', 'kconfig', 'makefile']
| 3
| 127
| 0
|
--- diff --git a/drivers/hwmon/pmbus/kconfig b/drivers/hwmon/pmbus/kconfig --- a/drivers/hwmon/pmbus/kconfig +++ b/drivers/hwmon/pmbus/kconfig +config sensors_xdpe122 + tristate "infineon xdpe122 family" + help + if you say yes here you get hardware monitoring support for infineon + xdpe12254, xdpe12284, device. + + this driver can also be built as a module. if so, the module will + be called xdpe12284. + diff --git a/drivers/hwmon/pmbus/makefile b/drivers/hwmon/pmbus/makefile --- a/drivers/hwmon/pmbus/makefile +++ b/drivers/hwmon/pmbus/makefile +obj-$(config_sensors_xdpe122) += xdpe12284.o diff --git a/drivers/hwmon/pmbus/xdpe12284.c b/drivers/hwmon/pmbus/xdpe12284.c --- /dev/null +++ b/drivers/hwmon/pmbus/xdpe12284.c +// spdx-license-identifier: gpl-2.0-or-later +/* + * hardware monitoring driver for infineon multi-phase digital vr controllers + * + * copyright (c) 2020 mellanox technologies. all rights reserved. + */ + +#include <linux/err.h> +#include <linux/i2c.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include "pmbus.h" + +#define xdpe122_prot_vr12_5mv 0x01 /* vr12.0 mode, 5-mv dac */ +#define xdpe122_prot_vr12_5_10mv 0x02 /* vr12.5 mode, 10-mv dac */ +#define xdpe122_prot_imvp9_10mv 0x03 /* imvp9 mode, 10-mv dac */ +#define xdpe122_amd_625mv 0x10 /* amd mode 6.25mv */ +#define xdpe122_page_num 2 + +static int xdpe122_identify(struct i2c_client *client, + struct pmbus_driver_info *info) +{ + u8 vout_params; + int i, ret; + + for (i = 0; i < xdpe122_page_num; i++) { + /* read the register with vout scaling value.*/ + ret = pmbus_read_byte_data(client, i, pmbus_vout_mode); + if (ret < 0) + return ret; + + vout_params = ret & genmask(4, 0); + + switch (vout_params) { + case xdpe122_prot_vr12_5_10mv: + info->vrm_version[i] = vr13; + break; + case xdpe122_prot_vr12_5mv: + info->vrm_version[i] = vr12; + break; + case xdpe122_prot_imvp9_10mv: + info->vrm_version[i] = imvp9; + break; + case xdpe122_amd_625mv: + info->vrm_version[i] = amd625mv; + break; + default: + return -einval; + } + } + + return 0; +} + +static struct pmbus_driver_info xdpe122_info = { + .pages = xdpe122_page_num, + .format[psc_voltage_in] = linear, + .format[psc_voltage_out] = vid, + .format[psc_temperature] = linear, + .format[psc_current_in] = linear, + .format[psc_current_out] = linear, + .format[psc_power] = linear, + .func[0] = pmbus_have_vin | pmbus_have_vout | pmbus_have_status_vout | + pmbus_have_iin | pmbus_have_iout | pmbus_have_status_iout | + pmbus_have_temp | pmbus_have_status_temp | + pmbus_have_pout | pmbus_have_pin | pmbus_have_status_input, + .func[1] = pmbus_have_vin | pmbus_have_vout | pmbus_have_status_vout | + pmbus_have_iin | pmbus_have_iout | pmbus_have_status_iout | + pmbus_have_temp | pmbus_have_status_temp | + pmbus_have_pout | pmbus_have_pin | pmbus_have_status_input, + .identify = xdpe122_identify, +}; + +static int xdpe122_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct pmbus_driver_info *info; + + info = devm_kmemdup(&client->dev, &xdpe122_info, sizeof(*info), + gfp_kernel); + if (!info) + return -enomem; + + return pmbus_do_probe(client, id, info); +} + +static const struct i2c_device_id xdpe122_id[] = { + {"xdpe12254", 0}, + {"xdpe12284", 0}, + {} +}; + +module_device_table(i2c, xdpe122_id); + +static const struct of_device_id __maybe_unused xdpe122_of_match[] = { + {.compatible = "infineon, xdpe12254"}, + {.compatible = "infineon, xdpe12284"}, + {} +}; +module_device_table(of, xdpe122_of_match); + +static struct i2c_driver xdpe122_driver = { + .driver = { + .name = "xdpe12284", + .of_match_table = of_match_ptr(xdpe122_of_match), + }, + .probe = xdpe122_probe, + .remove = pmbus_do_remove, + .id_table = xdpe122_id, +}; + +module_i2c_driver(xdpe122_driver); + +module_author("vadim pasternak <vadimp@mellanox.com>"); +module_description("pmbus driver for infineon xdpe122 family"); +module_license("gpl");
|
Hardware monitoring (hwmon)
|
aaafb7c8eb1c53d50ac1857f3b997baeac383378
|
vadim pasternak
|
drivers
|
hwmon
|
pmbus
|
docs: hwmon: include 'xdpe12284.rst' into docs
|
add documentation for 'xdpe122' devices.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for vid mode calculation per page bases
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['pmbus']
|
['rst']
| 2
| 102
| 0
|
--- diff --git a/documentation/hwmon/index.rst b/documentation/hwmon/index.rst --- a/documentation/hwmon/index.rst +++ b/documentation/hwmon/index.rst + xdpe12284 diff --git a/documentation/hwmon/xdpe12284.rst b/documentation/hwmon/xdpe12284.rst --- /dev/null +++ b/documentation/hwmon/xdpe12284.rst +.. spdx-license-identifier: gpl-2.0 + +kernel driver xdpe122 +===================== + +supported chips: + + * infineon xdpe12254 + + prefix: 'xdpe12254' + + * infineon xdpe12284 + + prefix: 'xdpe12284' + +authors: + + vadim pasternak <vadimp@mellanox.com> + +description +----------- + +this driver implements support for infineon multi-phase xdpe122 family +dual loop voltage regulators. +the family includes xdpe12284 and xdpe12254 devices. +the devices from this family complaint with: +- intel vr13 and vr13hc rev 1.3, imvp8 rev 1.2 and impvp9 rev 1.3 dc-dc + converter specification. +- intel svid rev 1.9. protocol. +- pmbus rev 1.3 interface. + +devices support linear format for reading input voltage, input and output current, +input and output power and temperature. +device supports vid format for reading output voltage. the below modes are +supported: +- vr12.0 mode, 5-mv dac - 0x01. +- vr12.5 mode, 10-mv dac - 0x02. +- imvp9 mode, 5-mv dac - 0x03. +- amd mode 6.25mv - 0x10. + +devices support two pages for telemetry. + +the driver provides for current: input, maximum and critical thresholds +and maximum and critical alarms. critical thresholds and critical alarm are +supported only for current output. +the driver exports the following attributes for via the sysfs files, where +indexes 1, 2 are for "iin" and 3, 4 for "iout": + +**curr[3-4]_crit** + +**curr[3-4]_crit_alarm** + +**curr[1-4]_input** + +**curr[1-4]_label** + +**curr[1-4]_max** + +**curr[1-4]_max_alarm** + +the driver provides for voltage: input, critical and low critical thresholds +and critical and low critical alarms. +the driver exports the following attributes for via the sysfs files, where +indexes 1, 2 are for "vin" and 3, 4 for "vout": + +**in[1-4]_crit** + +**in[1-4_crit_alarm** + +**in[1-4]_input** + +**in[1-4_label** + +**in[1-4]_lcrit** + +**in[1-41_lcrit_alarm** + +the driver provides for power: input and alarms. power alarm is supported only +for power input. +the driver exports the following attributes for via the sysfs files, where +indexes 1, 2 are for "pin" and 3, 4 for "pout": + +**power[1-2]_alarm** + +**power[1-4]_input** + +**power[1-4]_label** + +the driver provides for temperature: input, maximum and critical thresholds +and maximum and critical alarms. +the driver exports the following attributes for via the sysfs files: + +**temp[1-2]_crit** + +**temp[1-2]_crit_alarm** + +**temp[1-2]_input** + +**temp[1-2]_max** + +**temp[1-2]_max_alarm**
|
Hardware monitoring (hwmon)
|
971dfd8cdcd60fcf78566e3d1e20d865fc4073b5
|
vadim pasternak
|
documentation
|
hwmon
| |
hwmon: (pmbus) driver for max20730, max20734, and max20743
|
add support for maxim max20730, max20734, max20743 integrated, step-down switching regulators with pmbus support.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
driver for max20730, max20734, and max20743
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['pmbus']
|
['c', 'kconfig', 'makefile', 'rst']
| 5
| 457
| 0
|
--- diff --git a/documentation/hwmon/index.rst b/documentation/hwmon/index.rst --- a/documentation/hwmon/index.rst +++ b/documentation/hwmon/index.rst + max20730 diff --git a/documentation/hwmon/max20730.rst b/documentation/hwmon/max20730.rst --- /dev/null +++ b/documentation/hwmon/max20730.rst +.. spdx-license-identifier: gpl-2.0-or-later + +kernel driver max20730 +====================== + +supported chips: + + * maxim max20730 + + prefix: 'max20730' + + addresses scanned: - + + datasheet: https://datasheets.maximintegrated.com/en/ds/max20730.pdf + + * maxim max20734 + + prefix: 'max20734' + + addresses scanned: - + + datasheet: https://datasheets.maximintegrated.com/en/ds/max20734.pdf + + * maxim max20743 + + prefix: 'max20743' + + addresses scanned: - + + datasheet: https://datasheets.maximintegrated.com/en/ds/max20743.pdf + +author: guenter roeck <linux@roeck-us.net> + + +description +----------- + +this driver implements support for maxim max20730, max20734, and max20743 +integrated, step-down switching regulators with pmbus support. + +the driver is a client driver to the core pmbus driver. +please see documentation/hwmon/pmbus.rst for details on pmbus client drivers. + + +usage notes +----------- + +this driver does not auto-detect devices. you will have to instantiate the +devices explicitly. please see documentation/i2c/instantiating-devices.rst for +details. + + +sysfs entries +------------- + +=================== ===== ======================================================= +curr1_crit rw/ro critical output current. please see datasheet for + supported limits. read-only if the chip is + write protected; read-write otherwise. +curr1_crit_alarm ro output current critical alarm +curr1_input ro output current +curr1_label ro 'iout1' +in1_alarm ro input voltage alarm +in1_input ro input voltage +in1_label ro 'vin' +in2_alarm ro output voltage alarm +in2_input ro output voltage +in2_label ro 'vout1' +temp1_crit rw/ro critical temeperature. supported values are 130 or 150 + degrees c. read-only if the chip is write protected; + read-write otherwise. +temp1_crit_alarm ro temperature critical alarm +temp1_input ro chip temperature +=================== ===== ======================================================= diff --git a/drivers/hwmon/pmbus/kconfig b/drivers/hwmon/pmbus/kconfig --- a/drivers/hwmon/pmbus/kconfig +++ b/drivers/hwmon/pmbus/kconfig +config sensors_max20730 + tristate "maxim max20730, max20734, max20743" + help + if you say yes here you get hardware monitoring support for maxim + max20730, max20734, and max20743. + + this driver can also be built as a module. if so, the module will + be called max20730. + diff --git a/drivers/hwmon/pmbus/makefile b/drivers/hwmon/pmbus/makefile --- a/drivers/hwmon/pmbus/makefile +++ b/drivers/hwmon/pmbus/makefile +obj-$(config_sensors_max20730) += max20730.o diff --git a/drivers/hwmon/pmbus/max20730.c b/drivers/hwmon/pmbus/max20730.c --- /dev/null +++ b/drivers/hwmon/pmbus/max20730.c +// spdx-license-identifier: gpl-2.0-or-later +/* + * driver for max20730, max20734, and max20743 integrated, step-down + * switching regulators + * + * copyright 2019 google llc. + */ + +#include <linux/bits.h> +#include <linux/err.h> +#include <linux/i2c.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/of_device.h> +#include <linux/pmbus.h> +#include <linux/util_macros.h> +#include "pmbus.h" + +enum chips { + max20730, + max20734, + max20743 +}; + +struct max20730_data { + enum chips id; + struct pmbus_driver_info info; + struct mutex lock; /* used to protect against parallel writes */ + u16 mfr_devset1; +}; + +#define to_max20730_data(x) container_of(x, struct max20730_data, info) + +#define max20730_mfr_devset1 0xd2 + +/* + * convert discreet value to direct data format. strictly speaking, all passed + * values are constants, so we could do that calculation manually. on the + * downside, that would make the driver more difficult to maintain, so lets + * use this approach. + */ +static u16 val_to_direct(int v, enum pmbus_sensor_classes class, + const struct pmbus_driver_info *info) +{ + int r = info->r[class] - 3; /* take milli-units into account */ + int b = info->b[class] * 1000; + long d; + + d = v * info->m[class] + b; + /* + * r < 0 is true for all callers, so we don't need to bother + * about the r > 0 case. + */ + while (r < 0) { + d = div_round_closest(d, 10); + r++; + } + return (u16)d; +} + +static long direct_to_val(u16 w, enum pmbus_sensor_classes class, + const struct pmbus_driver_info *info) +{ + int r = info->r[class] - 3; + int b = info->b[class] * 1000; + int m = info->m[class]; + long d = (s16)w; + + if (m == 0) + return 0; + + while (r < 0) { + d *= 10; + r++; + } + d = (d - b) / m; + return d; +} + +static u32 max_current[][5] = { + [max20730] = { 13000, 16600, 20100, 23600 }, + [max20734] = { 21000, 27000, 32000, 38000 }, + [max20743] = { 18900, 24100, 29200, 34100 }, +}; + +static int max20730_read_word_data(struct i2c_client *client, int page, int reg) +{ + const struct pmbus_driver_info *info = pmbus_get_driver_info(client); + const struct max20730_data *data = to_max20730_data(info); + int ret = 0; + u32 max_c; + + switch (reg) { + case pmbus_ot_fault_limit: + switch ((data->mfr_devset1 >> 11) & 0x3) { + case 0x0: + ret = val_to_direct(150000, psc_temperature, info); + break; + case 0x1: + ret = val_to_direct(130000, psc_temperature, info); + break; + default: + ret = -enodata; + break; + } + break; + case pmbus_iout_oc_fault_limit: + max_c = max_current[data->id][(data->mfr_devset1 >> 5) & 0x3]; + ret = val_to_direct(max_c, psc_current_out, info); + break; + default: + ret = -enodata; + break; + } + return ret; +} + +static int max20730_write_word_data(struct i2c_client *client, int page, + int reg, u16 word) +{ + struct pmbus_driver_info *info; + struct max20730_data *data; + u16 devset1; + int ret = 0; + int idx; + + info = (struct pmbus_driver_info *)pmbus_get_driver_info(client); + data = to_max20730_data(info); + + mutex_lock(&data->lock); + devset1 = data->mfr_devset1; + + switch (reg) { + case pmbus_ot_fault_limit: + devset1 &= ~(bit(11) | bit(12)); + if (direct_to_val(word, psc_temperature, info) < 140000) + devset1 |= bit(11); + break; + case pmbus_iout_oc_fault_limit: + devset1 &= ~(bit(5) | bit(6)); + + idx = find_closest(direct_to_val(word, psc_current_out, info), + max_current[data->id], 4); + devset1 |= (idx << 5); + break; + default: + ret = -enodata; + break; + } + + if (!ret && devset1 != data->mfr_devset1) { + ret = i2c_smbus_write_word_data(client, max20730_mfr_devset1, + devset1); + if (!ret) { + data->mfr_devset1 = devset1; + pmbus_clear_cache(client); + } + } + mutex_unlock(&data->lock); + return ret; +} + +static const struct pmbus_driver_info max20730_info[] = { + [max20730] = { + .pages = 1, + .read_word_data = max20730_read_word_data, + .write_word_data = max20730_write_word_data, + + /* source : maxim an6042 */ + .format[psc_temperature] = direct, + .m[psc_temperature] = 21, + .b[psc_temperature] = 5887, + .r[psc_temperature] = -1, + + .format[psc_voltage_in] = direct, + .m[psc_voltage_in] = 3609, + .b[psc_voltage_in] = 0, + .r[psc_voltage_in] = -2, + + /* + * values in the datasheet are adjusted for temperature and + * for the relationship between vin and vout. + * unfortunately, the data sheet suggests that vout measurement + * may be scaled with a resistor array. this is indeed the case + * at least on the evaulation boards. as a result, any in-driver + * adjustments would either be wrong or require elaborate means + * to configure the scaling. instead of doing that, just report + * raw values and let userspace handle adjustments. + */ + .format[psc_current_out] = direct, + .m[psc_current_out] = 153, + .b[psc_current_out] = 4976, + .r[psc_current_out] = -1, + + .format[psc_voltage_out] = linear, + + .func[0] = pmbus_have_vin | + pmbus_have_vout | pmbus_have_status_vout | + pmbus_have_iout | pmbus_have_status_iout | + pmbus_have_temp | pmbus_have_status_temp, + }, + [max20734] = { + .pages = 1, + .read_word_data = max20730_read_word_data, + .write_word_data = max20730_write_word_data, + + /* source : maxim an6209 */ + .format[psc_temperature] = direct, + .m[psc_temperature] = 21, + .b[psc_temperature] = 5887, + .r[psc_temperature] = -1, + + .format[psc_voltage_in] = direct, + .m[psc_voltage_in] = 3592, + .b[psc_voltage_in] = 0, + .r[psc_voltage_in] = -2, + + .format[psc_current_out] = direct, + .m[psc_current_out] = 111, + .b[psc_current_out] = 3461, + .r[psc_current_out] = -1, + + .format[psc_voltage_out] = linear, + + .func[0] = pmbus_have_vin | + pmbus_have_vout | pmbus_have_status_vout | + pmbus_have_iout | pmbus_have_status_iout | + pmbus_have_temp | pmbus_have_status_temp, + }, + [max20743] = { + .pages = 1, + .read_word_data = max20730_read_word_data, + .write_word_data = max20730_write_word_data, + + /* source : maxim an6042 */ + .format[psc_temperature] = direct, + .m[psc_temperature] = 21, + .b[psc_temperature] = 5887, + .r[psc_temperature] = -1, + + .format[psc_voltage_in] = direct, + .m[psc_voltage_in] = 3597, + .b[psc_voltage_in] = 0, + .r[psc_voltage_in] = -2, + + .format[psc_current_out] = direct, + .m[psc_current_out] = 95, + .b[psc_current_out] = 5014, + .r[psc_current_out] = -1, + + .format[psc_voltage_out] = linear, + + .func[0] = pmbus_have_vin | + pmbus_have_vout | pmbus_have_status_vout | + pmbus_have_iout | pmbus_have_status_iout | + pmbus_have_temp | pmbus_have_status_temp, + }, +}; + +static int max20730_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + u8 buf[i2c_smbus_block_max + 1]; + struct max20730_data *data; + enum chips chip_id; + int ret; + + if (!i2c_check_functionality(client->adapter, + i2c_func_smbus_read_byte_data | + i2c_func_smbus_read_word_data | + i2c_func_smbus_block_data)) + return -enodev; + + ret = i2c_smbus_read_block_data(client, pmbus_mfr_id, buf); + if (ret < 0) { + dev_err(&client->dev, "failed to read manufacturer id "); + return ret; + } + if (ret != 5 || strncmp(buf, "maxim", 5)) { + buf[ret] = ''; + dev_err(dev, "unsupported manufacturer id '%s' ", buf); + return -enodev; + } + + /* + * the chips support reading pmbus_mfr_model. on both max20730 + * and max20734, reading it returns m20743. presumably that is + * the reason why the command is not documented. unfortunately, + * that means that there is no reliable means to detect the chip. + * however, we can at least detect the chip series. compare + * the returned value against 'm20743' and bail out if there is + * a mismatch. if that doesn't work for all chips, we may have + * to remove this check. + */ + ret = i2c_smbus_read_block_data(client, pmbus_mfr_model, buf); + if (ret < 0) { + dev_err(dev, "failed to read manufacturer model "); + return ret; + } + if (ret != 6 || strncmp(buf, "m20743", 6)) { + buf[ret] = ''; + dev_err(dev, "unsupported manufacturer model '%s' ", buf); + return -enodev; + } + + ret = i2c_smbus_read_block_data(client, pmbus_mfr_revision, buf); + if (ret < 0) { + dev_err(dev, "failed to read manufacturer revision "); + return ret; + } + if (ret != 1 || buf[0] != 'f') { + buf[ret] = ''; + dev_err(dev, "unsupported manufacturer revision '%s' ", buf); + return -enodev; + } + + if (client->dev.of_node) + chip_id = (enum chips)of_device_get_match_data(dev); + else + chip_id = id->driver_data; + + data = devm_kzalloc(dev, sizeof(*data), gfp_kernel); + if (!data) + return -enomem; + data->id = chip_id; + mutex_init(&data->lock); + memcpy(&data->info, &max20730_info[chip_id], sizeof(data->info)); + + ret = i2c_smbus_read_word_data(client, max20730_mfr_devset1); + if (ret < 0) + return ret; + data->mfr_devset1 = ret; + + return pmbus_do_probe(client, id, &data->info); +} + +static const struct i2c_device_id max20730_id[] = { + { "max20730", max20730 }, + { "max20734", max20734 }, + { "max20743", max20743 }, + { }, +}; + +module_device_table(i2c, max20730_id); + +static const struct of_device_id max20730_of_match[] = { + { .compatible = "maxim,max20730", .data = (void *)max20730 }, + { .compatible = "maxim,max20734", .data = (void *)max20734 }, + { .compatible = "maxim,max20743", .data = (void *)max20743 }, + { }, +}; + +module_device_table(of, max20730_of_match); + +static struct i2c_driver max20730_driver = { + .driver = { + .name = "max20730", + .of_match_table = max20730_of_match, + }, + .probe = max20730_probe, + .remove = pmbus_do_remove, + .id_table = max20730_id, +}; + +module_i2c_driver(max20730_driver); + +module_author("guenter roeck <linux@roeck-us.net>"); +module_description("pmbus driver for maxim max20730 / max20734 / max20743"); +module_license("gpl");
|
Hardware monitoring (hwmon)
|
cce209581a61d01f2b7309bed68d22fd8af34ee4
|
guenter roeck
|
drivers
|
hwmon
|
pmbus
|
hwmon: (w83627ehf) remove nct6775 and nct6776 support
|
the nct6775 and nct6776 are supported by the separate nct6775.c driver, so remove the code from the w83627ehf driver.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
remove nct6775 and nct6776 support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['w83627ehf']
|
['c', 'kconfig']
| 2
| 41
| 441
|
--- diff --git a/drivers/hwmon/kconfig b/drivers/hwmon/kconfig --- a/drivers/hwmon/kconfig +++ b/drivers/hwmon/kconfig - tristate "winbond w83627ehf/ehg/dhg/uhg, w83667hg, nct6775f, nct6776f" + tristate "winbond w83627ehf/ehg/dhg/uhg, w83667hg" - this driver also supports nuvoton w83667hg, w83667hg-b, nct6775f - (also known as w83667hg-i), and nct6776f. + this driver also supports nuvoton w83667hg and w83667hg-b. diff --git a/drivers/hwmon/w83627ehf.c b/drivers/hwmon/w83627ehf.c --- a/drivers/hwmon/w83627ehf.c +++ b/drivers/hwmon/w83627ehf.c - * nct6775f 9 4 3 9 0xb470 0xc1 0x5ca3 - * nct6776f 9 5 3 9 0xc330 0xc1 0x5ca3 - w83667hg, w83667hg_b, nct6775, nct6776, + w83667hg, w83667hg_b, - "nct6775", - "nct6776", -#define sio_nct6775_id 0xb470 -#define sio_nct6776_id 0xc330 -/* nct6775f has its own fan divider registers */ -#define nct6775_reg_fandiv1 0x506 -#define nct6775_reg_fandiv2 0x507 -#define nct6775_reg_fan_debounce 0xf0 - -static const u16 nct6775_reg_target[] = { 0x101, 0x201, 0x301 }; -static const u16 nct6775_reg_fan_mode[] = { 0x102, 0x202, 0x302 }; -static const u16 nct6775_reg_fan_stop_output[] = { 0x105, 0x205, 0x305 }; -static const u16 nct6775_reg_fan_start_output[] = { 0x106, 0x206, 0x306 }; -static const u16 nct6775_reg_fan_stop_time[] = { 0x107, 0x207, 0x307 }; -static const u16 nct6775_reg_pwm[] = { 0x109, 0x209, 0x309 }; -static const u16 nct6775_reg_fan_max_output[] = { 0x10a, 0x20a, 0x30a }; -static const u16 nct6775_reg_fan_step_output[] = { 0x10b, 0x20b, 0x30b }; -static const u16 nct6775_reg_fan[] = { 0x630, 0x632, 0x634, 0x636, 0x638 }; -static const u16 nct6776_reg_fan_min[] = { 0x63a, 0x63c, 0x63e, 0x640, 0x642}; - -static const u16 nct6775_reg_temp[] - = { 0x27, 0x150, 0x250, 0x73, 0x75, 0x77, 0x62b, 0x62c, 0x62d }; -static const u16 nct6775_reg_temp_config[] - = { 0, 0x152, 0x252, 0, 0, 0, 0x628, 0x629, 0x62a }; -static const u16 nct6775_reg_temp_hyst[] - = { 0x3a, 0x153, 0x253, 0, 0, 0, 0x673, 0x678, 0x67d }; -static const u16 nct6775_reg_temp_over[] - = { 0x39, 0x155, 0x255, 0, 0, 0, 0x672, 0x677, 0x67c }; -static const u16 nct6775_reg_temp_source[] - = { 0x621, 0x622, 0x623, 0x100, 0x200, 0x300, 0x624, 0x625, 0x626 }; - -static const char *const nct6775_temp_label[] = { - "", - "systin", - "cputin", - "auxtin", - "amd sb-tsi", - "peci agent 0", - "peci agent 1", - "peci agent 2", - "peci agent 3", - "peci agent 4", - "peci agent 5", - "peci agent 6", - "peci agent 7", - "pch_chip_cpu_max_temp", - "pch_chip_temp", - "pch_cpu_temp", - "pch_mch_temp", - "pch_dim0_temp", - "pch_dim1_temp", - "pch_dim2_temp", - "pch_dim3_temp" -}; - -static const char *const nct6776_temp_label[] = { - "", - "systin", - "cputin", - "auxtin", - "smbusmaster 0", - "smbusmaster 1", - "smbusmaster 2", - "smbusmaster 3", - "smbusmaster 4", - "smbusmaster 5", - "smbusmaster 6", - "smbusmaster 7", - "peci agent 0", - "peci agent 1", - "pch_chip_cpu_max_temp", - "pch_chip_temp", - "pch_cpu_temp", - "pch_mch_temp", - "pch_dim0_temp", - "pch_dim1_temp", - "pch_dim2_temp", - "pch_dim3_temp", - "byte_temp" -}; - -#define num_reg_temp array_size(nct6775_reg_temp) +#define num_reg_temp array_size(w83627ehf_reg_temp) -static unsigned int fan_from_reg13(u16 reg, unsigned int divreg) -{ - if ((reg & 0xff1f) == 0xff1f) - return 0; - - reg = (reg & 0x1f) | ((reg & 0xff00) >> 3); - - if (reg == 0) - return 0; - - return 1350000u / reg; -} - -static unsigned int fan_from_reg16(u16 reg, unsigned int divreg) -{ - if (reg == 0 || reg == 0xffff) - return 0; - - /* - * even though the registers are 16 bit wide, the fan divisor - * still applies. - */ - return 1350000u / (reg << divreg); -} - -/* this function assumes that the caller holds data->update_lock */ -static void nct6775_write_fan_div(struct w83627ehf_data *data, int nr) -{ - u8 reg; - - switch (nr) { - case 0: - reg = (w83627ehf_read_value(data, nct6775_reg_fandiv1) & 0x70) - | (data->fan_div[0] & 0x7); - w83627ehf_write_value(data, nct6775_reg_fandiv1, reg); - break; - case 1: - reg = (w83627ehf_read_value(data, nct6775_reg_fandiv1) & 0x7) - | ((data->fan_div[1] << 4) & 0x70); - w83627ehf_write_value(data, nct6775_reg_fandiv1, reg); - break; - case 2: - reg = (w83627ehf_read_value(data, nct6775_reg_fandiv2) & 0x70) - | (data->fan_div[2] & 0x7); - w83627ehf_write_value(data, nct6775_reg_fandiv2, reg); - break; - case 3: - reg = (w83627ehf_read_value(data, nct6775_reg_fandiv2) & 0x7) - | ((data->fan_div[3] << 4) & 0x70); - w83627ehf_write_value(data, nct6775_reg_fandiv2, reg); - break; - } -} - - if (data->kind == nct6776) - ; /* no dividers, do nothing */ - else if (data->kind == nct6775) - nct6775_write_fan_div(data, nr); - else - w83627ehf_write_fan_div(data, nr); -} - -static void nct6775_update_fan_div(struct w83627ehf_data *data) -{ - u8 i; - - i = w83627ehf_read_value(data, nct6775_reg_fandiv1); - data->fan_div[0] = i & 0x7; - data->fan_div[1] = (i & 0x70) >> 4; - i = w83627ehf_read_value(data, nct6775_reg_fandiv2); - data->fan_div[2] = i & 0x7; - if (data->has_fan & (1<<3)) - data->fan_div[3] = (i & 0x70) >> 4; + w83627ehf_write_fan_div(data, nr); - if (data->kind == nct6776) - ; /* no dividers, do nothing */ - else if (data->kind == nct6775) - nct6775_update_fan_div(data); - else - w83627ehf_update_fan_div(data); -} - -static void nct6775_update_pwm(struct w83627ehf_data *data) -{ - int i; - int pwmcfg, fanmodecfg; - - for (i = 0; i < data->pwm_num; i++) { - pwmcfg = w83627ehf_read_value(data, - w83627ehf_reg_pwm_enable[i]); - fanmodecfg = w83627ehf_read_value(data, - nct6775_reg_fan_mode[i]); - data->pwm_mode[i] = - ((pwmcfg >> w83627ehf_pwm_mode_shift[i]) & 1) ? 0 : 1; - data->pwm_enable[i] = ((fanmodecfg >> 4) & 7) + 1; - data->tolerance[i] = fanmodecfg & 0x0f; - data->pwm[i] = w83627ehf_read_value(data, data->reg_pwm[i]); - } + w83627ehf_update_fan_div(data); - struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev); - - if (sio_data->kind == nct6775 || sio_data->kind == nct6776) - nct6775_update_pwm(data); - else - w83627ehf_update_pwm(data); + w83627ehf_update_pwm(data); - struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev); - && (reg >= 0xff || (sio_data->kind == nct6775 - && reg == 0x00)) + && reg >= 0xff - /* on nct67766f, dc mode is only supported for pwm1 */ - if (data->kind == nct6776 && channel && val != 1) - return -einval; - - /* smartfan iii mode is not supported on nct6776f */ - if (data->kind == nct6776 && val == 4) - return -einval; - if (data->kind == nct6775 || data->kind == nct6776) { - reg = w83627ehf_read_value(data, - nct6775_reg_fan_mode[channel]); - reg &= 0x0f; - reg |= (val - 1) << 4; - w83627ehf_write_value(data, - nct6775_reg_fan_mode[channel], reg); - } else { - reg = w83627ehf_read_value(data, - w83627ehf_reg_pwm_enable[channel]); - reg &= ~(0x03 << w83627ehf_pwm_enable_shift[channel]); - reg |= (val - 1) << w83627ehf_pwm_enable_shift[channel]; - w83627ehf_write_value(data, w83627ehf_reg_pwm_enable[channel], - reg); - } + reg = w83627ehf_read_value(data, + w83627ehf_reg_pwm_enable[channel]); + reg &= ~(0x03 << w83627ehf_pwm_enable_shift[channel]); + reg |= (val - 1) << w83627ehf_pwm_enable_shift[channel]; + w83627ehf_write_value(data, w83627ehf_reg_pwm_enable[channel], + reg); - if (data->kind == nct6775 || data->kind == nct6776) { - /* limit tolerance further for nct6776f */ - if (data->kind == nct6776 && val > 7) - val = 7; - reg = w83627ehf_read_value(data, nct6775_reg_fan_mode[nr]); + reg = w83627ehf_read_value(data, w83627ehf_reg_tolerance[nr]); + if (nr == 1) + reg = (reg & 0x0f) | (val << 4); + else - w83627ehf_write_value(data, nct6775_reg_fan_mode[nr], reg); - } else { - reg = w83627ehf_read_value(data, w83627ehf_reg_tolerance[nr]); - if (nr == 1) - reg = (reg & 0x0f) | (val << 4); - else - reg = (reg & 0xf0) | val; - w83627ehf_write_value(data, w83627ehf_reg_tolerance[nr], reg); - } + w83627ehf_write_value(data, w83627ehf_reg_tolerance[nr], reg); -static void w82627ehf_swap_tempreg(struct w83627ehf_data *data, - int r1, int r2) -{ - swap(data->temp_src[r1], data->temp_src[r2]); - swap(data->reg_temp[r1], data->reg_temp[r2]); - swap(data->reg_temp_over[r1], data->reg_temp_over[r2]); - swap(data->reg_temp_hyst[r1], data->reg_temp_hyst[r2]); - swap(data->reg_temp_config[r1], data->reg_temp_config[r2]); -} - - if (sio_data->kind == nct6775) { - /* on nct6775, fan4 shares pins with the fdc interface */ - fan3pin = 1; - fan4pin = !(superio_inb(sio_data->sioreg, 0x2a) & 0x80); - fan4min = 0; - fan5pin = 0; - } else if (sio_data->kind == nct6776) { - bool gpok = superio_inb(sio_data->sioreg, 0x27) & 0x80; - - superio_select(sio_data->sioreg, w83627ehf_ld_hwm); - regval = superio_inb(sio_data->sioreg, sio_reg_enable); - - if (regval & 0x80) - fan3pin = gpok; - else - fan3pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x40); - - if (regval & 0x40) - fan4pin = gpok; - else - fan4pin = !!(superio_inb(sio_data->sioreg, 0x1c) & 0x01); - - if (regval & 0x20) - fan5pin = gpok; - else - fan5pin = !!(superio_inb(sio_data->sioreg, 0x1c) & 0x02); - - fan4min = fan4pin; - } else if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) { + if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) { - if (sio_data->kind == nct6775 || sio_data->kind == nct6776) { - /* - * nct6775f and nct6776f don't have the w83627ehf_reg_fandiv1 - * register - */ - data->has_fan |= (fan4pin << 3) | (fan5pin << 4); - data->has_fan_min |= (fan4min << 3) | (fan5pin << 4); - } else { - /* - * it looks like fan4 and fan5 pins can be alternatively used - * as fan on/off switches, but fan5 control is write only :/ - * we assume that if the serial interface is disabled, designers - * connected fan5 as input unless they are emitting log 1, which - * is not the default. - */ - regval = w83627ehf_read_value(data, w83627ehf_reg_fandiv1); - if ((regval & (1 << 2)) && fan4pin) { - data->has_fan |= (1 << 3); - data->has_fan_min |= (1 << 3); - } - if (!(regval & (1 << 1)) && fan5pin) { - data->has_fan |= (1 << 4); - data->has_fan_min |= (1 << 4); - } + /* + * it looks like fan4 and fan5 pins can be alternatively used + * as fan on/off switches, but fan5 control is write only :/ + * we assume that if the serial interface is disabled, designers + * connected fan5 as input unless they are emitting log 1, which + * is not the default. + */ + regval = w83627ehf_read_value(data, w83627ehf_reg_fandiv1); + if ((regval & (1 << 2)) && fan4pin) { + data->has_fan |= (1 << 3); + data->has_fan_min |= (1 << 3); + } + if (!(regval & (1 << 1)) && fan5pin) { + data->has_fan |= (1 << 4); + data->has_fan_min |= (1 << 4); - if (data->kind != nct6776) - return 0444; - else - return 0; + return 0444; - if (channel == 0 || - (channel == 1 && data->kind == nct6776)) + if (channel == 0) - /* 667hg, nct6775f, and nct6776f have 3 pwms, and 627uhg has only 2 */ + /* 667hg has 3 pwms, and 627uhg has only 2 */ - case nct6775: - case nct6776: - if (sio_data->kind == nct6775 || sio_data->kind == nct6776) { - int mask = 0; - - /* - * display temperature sensor output only if it monitors - * a source other than one already reported. always display - * first three temperature registers, though. - */ - for (i = 0; i < num_reg_temp; i++) { - u8 src; - - data->reg_temp[i] = nct6775_reg_temp[i]; - data->reg_temp_over[i] = nct6775_reg_temp_over[i]; - data->reg_temp_hyst[i] = nct6775_reg_temp_hyst[i]; - data->reg_temp_config[i] = nct6775_reg_temp_config[i]; - - src = w83627ehf_read_value(data, - nct6775_reg_temp_source[i]); - src &= 0x1f; - if (src && !(mask & (1 << src))) { - data->have_temp |= 1 << i; - mask |= 1 << src; - } - - data->temp_src[i] = src; - - /* - * now do some register swapping if index 0..2 don't - * point to systin(1), cpuin(2), and auxin(3). - * idea is to have the first three attributes - * report systin, cpuin, and auxin if possible - * without overriding the basic system configuration. - */ - if (i > 0 && data->temp_src[0] != 1 - && data->temp_src[i] == 1) - w82627ehf_swap_tempreg(data, 0, i); - if (i > 1 && data->temp_src[1] != 2 - && data->temp_src[i] == 2) - w82627ehf_swap_tempreg(data, 1, i); - if (i > 2 && data->temp_src[2] != 3 - && data->temp_src[i] == 3) - w82627ehf_swap_tempreg(data, 2, i); - } - if (sio_data->kind == nct6776) { - /* - * on nct6776, auxtin and vin3 pins are shared. - * only way to detect it is to check if auxtin is used - * as a temperature source, and if that source is - * enabled. - * - * if that is the case, disable in6, which reports vin3. - * otherwise disable temp3. - */ - if (data->temp_src[2] == 3) { - u8 reg; - - if (data->reg_temp_config[2]) - reg = w83627ehf_read_value(data, - data->reg_temp_config[2]); - else - reg = 0; /* assume auxtin is used */ - - if (reg & 0x01) - data->have_temp &= ~(1 << 2); - else - data->in6_skip = 1; - } - data->temp_label = nct6776_temp_label; - } else { - data->temp_label = nct6775_temp_label; - } - data->have_temp_offset = data->have_temp & 0x07; - for (i = 0; i < 3; i++) { - if (data->temp_src[i] > 3) - data->have_temp_offset &= ~(1 << i); - } - } else if (sio_data->kind == w83667hg_b) { + if (sio_data->kind == w83667hg_b) { - if (sio_data->kind == nct6775) { - data->has_fan_div = true; - data->fan_from_reg = fan_from_reg16; - data->fan_from_reg_min = fan_from_reg8; - data->reg_pwm = nct6775_reg_pwm; - data->reg_target = nct6775_reg_target; - data->reg_fan = nct6775_reg_fan; - data->reg_fan_min = w83627ehf_reg_fan_min; - data->reg_fan_start_output = nct6775_reg_fan_start_output; - data->reg_fan_stop_output = nct6775_reg_fan_stop_output; - data->reg_fan_stop_time = nct6775_reg_fan_stop_time; - data->reg_fan_max_output = nct6775_reg_fan_max_output; - data->reg_fan_step_output = nct6775_reg_fan_step_output; - } else if (sio_data->kind == nct6776) { - data->has_fan_div = false; - data->fan_from_reg = fan_from_reg13; - data->fan_from_reg_min = fan_from_reg13; - data->reg_pwm = nct6775_reg_pwm; - data->reg_target = nct6775_reg_target; - data->reg_fan = nct6775_reg_fan; - data->reg_fan_min = nct6776_reg_fan_min; - data->reg_fan_start_output = nct6775_reg_fan_start_output; - data->reg_fan_stop_output = nct6775_reg_fan_stop_output; - data->reg_fan_stop_time = nct6775_reg_fan_stop_time; - } else if (sio_data->kind == w83667hg_b) { + if (sio_data->kind == w83667hg_b) { - if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b || - sio_data->kind == nct6775 || sio_data->kind == nct6776) { + if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) { - if (fan_debounce && - (sio_data->kind == nct6775 || sio_data->kind == nct6776)) { - u8 tmp; - - superio_select(sio_data->sioreg, w83627ehf_ld_hwm); - tmp = superio_inb(sio_data->sioreg, nct6775_reg_fan_debounce); - if (sio_data->kind == nct6776) - superio_outb(sio_data->sioreg, nct6775_reg_fan_debounce, - 0x3e | tmp); - else - superio_outb(sio_data->sioreg, nct6775_reg_fan_debounce, - 0x1e | tmp); - pr_info("enabled fan debounce for chip %s ", data->name); - } - - struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev); - if (sio_data->kind == nct6775) { - data->fandiv1 = w83627ehf_read_value(data, nct6775_reg_fandiv1); - data->fandiv2 = w83627ehf_read_value(data, nct6775_reg_fandiv2); - } - struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev); - if (sio_data->kind == nct6775) { - w83627ehf_write_value(data, nct6775_reg_fandiv1, data->fandiv1); - w83627ehf_write_value(data, nct6775_reg_fandiv2, data->fandiv2); - } - static const char sio_name_nct6775[] __initconst = "nct6775f"; - static const char sio_name_nct6776[] __initconst = "nct6776f"; - case sio_nct6775_id: - sio_data->kind = nct6775; - sio_name = sio_name_nct6775; - break; - case sio_nct6776_id: - sio_data->kind = nct6776; - sio_name = sio_name_nct6776; - break;
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Hardware monitoring (hwmon)
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3207408ab4cbe242d48471ce4e10047022a65232
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dr david alan gilbert guenter roeck linux roeck us net
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drivers
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hwmon
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gpio: add support for the xylon logicvc gpios
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the logicvc display hardware block comes with gpio capabilities that must be exposed separately from the main driver (as gpios) for use with regulators and panels. a syscon is used to share the same regmap across the two drivers.
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this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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add support for the xylon logicvc gpios
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
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[]
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['c', 'kconfig', 'makefile']
| 3
| 177
| 0
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--- diff --git a/drivers/gpio/kconfig b/drivers/gpio/kconfig --- a/drivers/gpio/kconfig +++ b/drivers/gpio/kconfig +config gpio_logicvc + tristate "xylon logicvc gpio support" + depends on mfd_syscon && of + help + say yes here to support gpio functionality of the xylon logicvc + programmable logic block. diff --git a/drivers/gpio/makefile b/drivers/gpio/makefile --- a/drivers/gpio/makefile +++ b/drivers/gpio/makefile +obj-$(config_gpio_logicvc) += gpio-logicvc.o diff --git a/drivers/gpio/gpio-logicvc.c b/drivers/gpio/gpio-logicvc.c --- /dev/null +++ b/drivers/gpio/gpio-logicvc.c +// spdx-license-identifier: gpl-2.0+ +/* + * copyright (c) 2019 bootlin + * author: paul kocialkowski <paul.kocialkowski@bootlin.com> + */ + +#include <linux/err.h> +#include <linux/gpio/driver.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/mfd/syscon.h> + +#define logicvc_ctrl_reg 0x40 +#define logicvc_ctrl_gpio_shift 11 +#define logicvc_ctrl_gpio_bits 5 + +#define logicvc_power_ctrl_reg 0x78 +#define logicvc_power_ctrl_gpio_shift 0 +#define logicvc_power_ctrl_gpio_bits 4 + +struct logicvc_gpio { + struct gpio_chip chip; + struct regmap *regmap; +}; + +static void logicvc_gpio_offset(struct logicvc_gpio *logicvc, unsigned offset, + unsigned int *reg, unsigned int *bit) +{ + if (offset >= logicvc_ctrl_gpio_bits) { + *reg = logicvc_power_ctrl_reg; + + /* to the (virtual) power ctrl offset. */ + offset -= logicvc_ctrl_gpio_bits; + /* to the actual bit offset in reg. */ + offset += logicvc_power_ctrl_gpio_shift; + } else { + *reg = logicvc_ctrl_reg; + + /* to the actual bit offset in reg. */ + offset += logicvc_ctrl_gpio_shift; + } + + *bit = bit(offset); +} + +static int logicvc_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct logicvc_gpio *logicvc = gpiochip_get_data(chip); + unsigned int reg, bit, value; + int ret; + + logicvc_gpio_offset(logicvc, offset, ®, &bit); + + ret = regmap_read(logicvc->regmap, reg, &value); + if (ret) + return ret; + + return !!(value & bit); +} + +static void logicvc_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct logicvc_gpio *logicvc = gpiochip_get_data(chip); + unsigned int reg, bit; + + logicvc_gpio_offset(logicvc, offset, ®, &bit); + + regmap_update_bits(logicvc->regmap, reg, bit, value ? bit : 0); +} + +static int logicvc_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + /* pins are always configured as output, so just set the value. */ + logicvc_gpio_set(chip, offset, value); + + return 0; +} + +static struct regmap_config logicvc_gpio_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .name = "logicvc-gpio", +}; + +static int logicvc_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *of_node = dev->of_node; + struct logicvc_gpio *logicvc; + int ret; + + logicvc = devm_kzalloc(dev, sizeof(*logicvc), gfp_kernel); + if (!logicvc) + return -enomem; + + /* try to get regmap from parent first. */ + logicvc->regmap = syscon_node_to_regmap(of_node->parent); + + /* grab our own regmap if that fails. */ + if (is_err(logicvc->regmap)) { + struct resource res; + void __iomem *base; + + ret = of_address_to_resource(of_node, 0, &res); + if (ret) { + dev_err(dev, "failed to get resource from address "); + return ret; + } + + base = devm_ioremap_resource(dev, &res); + if (is_err(base)) { + dev_err(dev, "failed to map i/o base "); + return ptr_err(base); + } + + logicvc_gpio_regmap_config.max_register = resource_size(&res) - + logicvc_gpio_regmap_config.reg_stride; + + logicvc->regmap = + devm_regmap_init_mmio(dev, base, + &logicvc_gpio_regmap_config); + if (is_err(logicvc->regmap)) { + dev_err(dev, "failed to create regmap for i/o "); + return ptr_err(logicvc->regmap); + } + } + + logicvc->chip.parent = dev; + logicvc->chip.owner = this_module; + logicvc->chip.label = dev_name(dev); + logicvc->chip.base = -1; + logicvc->chip.ngpio = logicvc_ctrl_gpio_bits + + logicvc_power_ctrl_gpio_bits; + logicvc->chip.get = logicvc_gpio_get; + logicvc->chip.set = logicvc_gpio_set; + logicvc->chip.direction_output = logicvc_gpio_direction_output; + + platform_set_drvdata(pdev, logicvc); + + return devm_gpiochip_add_data(dev, &logicvc->chip, logicvc); +} + +static const struct of_device_id logicivc_gpio_of_table[] = { + { + .compatible = "xylon,logicvc-3.02.a-gpio", + }, + { } +}; + +module_device_table(of, logicivc_gpio_of_table); + +static struct platform_driver logicvc_gpio_driver = { + .driver = { + .name = "gpio-logicvc", + .of_match_table = logicivc_gpio_of_table, + }, + .probe = logicvc_gpio_probe, +}; + +module_platform_driver(logicvc_gpio_driver); + +module_author("paul kocialkowski <paul.kocialkowski@bootlin.com>"); +module_description("xylon logicvc gpio driver"); +module_license("gpl");
|
General Purpose I/O (gpio)
|
c16485ad8e023b2188d19f0ace3bc2af500884e1
|
paul kocialkowski
|
drivers
|
gpio
| |
gpio: bd71828: initial support for rohm bd71828 pmic gpios
|
rohm bd71828 pmic contains 4 pins which can be configured by otp to be used for general purposes. first 3 can be used as outputs and 4.th pin can be used as input. allow them to be controlled via gpio framework.
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this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
initial support for rohm bd71828 pmic gpios
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['bd71828']
|
['c', 'kconfig', 'makefile']
| 3
| 172
| 0
|
--- diff --git a/drivers/gpio/kconfig b/drivers/gpio/kconfig --- a/drivers/gpio/kconfig +++ b/drivers/gpio/kconfig +config gpio_bd71828 + tristate "rohm bd71828 gpio support" + depends on mfd_rohm_bd71828 + help + support for gpios on rohm bd71828 pmic. there are three gpios + available on the rohm pmic in total. the gpios are limited to + outputs only and pins must be configured to gpio outputs by + otp. enable this only if you want to use these pins as outputs. + + this driver can also be built as a module. if so, the module + will be called gpio-bd71828. + diff --git a/drivers/gpio/makefile b/drivers/gpio/makefile --- a/drivers/gpio/makefile +++ b/drivers/gpio/makefile +obj-$(config_gpio_bd71828) += gpio-bd71828.o diff --git a/drivers/gpio/gpio-bd71828.c b/drivers/gpio/gpio-bd71828.c --- /dev/null +++ b/drivers/gpio/gpio-bd71828.c +// spdx-license-identifier: gpl-2.0-only +// copyright (c) 2018 rohm semiconductors + +#include <linux/gpio/driver.h> +#include <linux/mfd/rohm-bd71828.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#define gpio_out_reg(off) (bd71828_reg_gpio_ctrl1 + (off)) +#define hall_gpio_offset 3 + +/* + * these defines can be removed when + * "gpio: add definition for gpio direction" + * (9208b1e77d6e8e9776f34f46ef4079ecac9c3c25 in gpio tree) gets merged, + */ +#ifndef gpio_line_direction_in + #define gpio_line_direction_in 1 + #define gpio_line_direction_out 0 +#endif + +struct bd71828_gpio { + struct rohm_regmap_dev chip; + struct gpio_chip gpio; +}; + +static void bd71828_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + int ret; + struct bd71828_gpio *bdgpio = gpiochip_get_data(chip); + u8 val = (value) ? bd71828_gpio_out_hi : bd71828_gpio_out_lo; + + /* + * the hall input pin can only be used as input. if this is the pin + * we are dealing with - then we are done + */ + if (offset == hall_gpio_offset) + return; + + ret = regmap_update_bits(bdgpio->chip.regmap, gpio_out_reg(offset), + bd71828_gpio_out_mask, val); + if (ret) + dev_err(bdgpio->chip.dev, "could not set gpio to %d ", value); +} + +static int bd71828_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + int ret; + unsigned int val; + struct bd71828_gpio *bdgpio = gpiochip_get_data(chip); + + if (offset == hall_gpio_offset) + ret = regmap_read(bdgpio->chip.regmap, bd71828_reg_io_stat, + &val); + else + ret = regmap_read(bdgpio->chip.regmap, gpio_out_reg(offset), + &val); + if (!ret) + ret = (val & bd71828_gpio_out_mask); + + return ret; +} + +static int bd71828_gpio_set_config(struct gpio_chip *chip, unsigned int offset, + unsigned long config) +{ + struct bd71828_gpio *bdgpio = gpiochip_get_data(chip); + + if (offset == hall_gpio_offset) + return -enotsupp; + + switch (pinconf_to_config_param(config)) { + case pin_config_drive_open_drain: + return regmap_update_bits(bdgpio->chip.regmap, + gpio_out_reg(offset), + bd71828_gpio_drive_mask, + bd71828_gpio_open_drain); + case pin_config_drive_push_pull: + return regmap_update_bits(bdgpio->chip.regmap, + gpio_out_reg(offset), + bd71828_gpio_drive_mask, + bd71828_gpio_push_pull); + default: + break; + } + return -enotsupp; +} + +static int bd71828_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + /* + * pin usage is selected by otp data. we can't read it runtime. hence + * we trust that if the pin is not excluded by "gpio-reserved-ranges" + * the otp configuration is set to out. (other pins but hall input pin + * on bd71828 can't really be used for general purpose input - input + * states are used for specific cases like regulator control or + * pmic_on_req. + */ + if (offset == hall_gpio_offset) + return gpio_line_direction_in; + + return gpio_line_direction_out; +} + +static int bd71828_probe(struct platform_device *pdev) +{ + struct bd71828_gpio *bdgpio; + struct rohm_regmap_dev *bd71828; + + bd71828 = dev_get_drvdata(pdev->dev.parent); + if (!bd71828) { + dev_err(&pdev->dev, "no mfd driver data "); + return -einval; + } + + bdgpio = devm_kzalloc(&pdev->dev, sizeof(*bdgpio), + gfp_kernel); + if (!bdgpio) + return -enomem; + + bdgpio->chip.dev = &pdev->dev; + bdgpio->gpio.parent = pdev->dev.parent; + bdgpio->gpio.label = "bd71828-gpio"; + bdgpio->gpio.owner = this_module; + bdgpio->gpio.get_direction = bd71828_get_direction; + bdgpio->gpio.set_config = bd71828_gpio_set_config; + bdgpio->gpio.can_sleep = true; + bdgpio->gpio.get = bd71828_gpio_get; + bdgpio->gpio.set = bd71828_gpio_set; + bdgpio->gpio.base = -1; + + /* + * see if we need some implementation to mark some pins as + * not controllable based on dt info or if core can handle + * "gpio-reserved-ranges" and exclude them from control + */ + bdgpio->gpio.ngpio = 4; + bdgpio->gpio.of_node = pdev->dev.parent->of_node; + bdgpio->chip.regmap = bd71828->regmap; + + return devm_gpiochip_add_data(&pdev->dev, &bdgpio->gpio, + bdgpio); +} + +static struct platform_driver bd71828_gpio = { + .driver = { + .name = "bd71828-gpio" + }, + .probe = bd71828_probe, +}; + +module_platform_driver(bd71828_gpio); + +module_author("matti vaittinen <matti.vaittinen@fi.rohmeurope.com>"); +module_description("bd71828 voltage regulator driver"); +module_license("gpl"); +module_alias("platform:bd71828-gpio");
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General Purpose I/O (gpio)
|
c31f625d06c9166f753a2f21ac9c3f859647ca9f
|
matti vaittinen
|
drivers
|
gpio
| |
gpio/sifive: add gpio driver for sifive socs
|
adds the gpio driver for sifive risc-v socs.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add gpio driver for sifive socs
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['sifive']
|
['c', 'kconfig', 'makefile']
| 3
| 262
| 0
|
--- diff --git a/drivers/gpio/kconfig b/drivers/gpio/kconfig --- a/drivers/gpio/kconfig +++ b/drivers/gpio/kconfig +config gpio_sifive + bool "sifive gpio support" + depends on of_gpio && irq_domain_hierarchy + select gpio_generic + select gpiolib_irqchip + select regmap_mmio + help + say yes here to support the gpio device on sifive socs. + diff --git a/drivers/gpio/makefile b/drivers/gpio/makefile --- a/drivers/gpio/makefile +++ b/drivers/gpio/makefile +obj-$(config_gpio_sifive) += gpio-sifive.o diff --git a/drivers/gpio/gpio-sifive.c b/drivers/gpio/gpio-sifive.c --- /dev/null +++ b/drivers/gpio/gpio-sifive.c +// spdx-license-identifier: gpl-2.0 +/* + * copyright (c) 2019 sifive + */ + +#include <linux/bitops.h> +#include <linux/device.h> +#include <linux/errno.h> +#include <linux/of_irq.h> +#include <linux/gpio/driver.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/spinlock.h> +#include <linux/regmap.h> + +#define sifive_gpio_input_val 0x00 +#define sifive_gpio_input_en 0x04 +#define sifive_gpio_output_en 0x08 +#define sifive_gpio_output_val 0x0c +#define sifive_gpio_rise_ie 0x18 +#define sifive_gpio_rise_ip 0x1c +#define sifive_gpio_fall_ie 0x20 +#define sifive_gpio_fall_ip 0x24 +#define sifive_gpio_high_ie 0x28 +#define sifive_gpio_high_ip 0x2c +#define sifive_gpio_low_ie 0x30 +#define sifive_gpio_low_ip 0x34 +#define sifive_gpio_output_xor 0x40 + +#define sifive_gpio_max 32 +#define sifive_gpio_irq_offset 7 + +struct sifive_gpio { + void __iomem *base; + struct gpio_chip gc; + struct regmap *regs; + u32 irq_state; + unsigned int trigger[sifive_gpio_max]; + unsigned int irq_parent[sifive_gpio_max]; +}; + +static void sifive_gpio_set_ie(struct sifive_gpio *chip, unsigned int offset) +{ + unsigned long flags; + unsigned int trigger; + + spin_lock_irqsave(&chip->gc.bgpio_lock, flags); + trigger = (chip->irq_state & bit(offset)) ? chip->trigger[offset] : 0; + regmap_update_bits(chip->regs, sifive_gpio_rise_ie, bit(offset), + (trigger & irq_type_edge_rising) ? bit(offset) : 0); + regmap_update_bits(chip->regs, sifive_gpio_fall_ie, bit(offset), + (trigger & irq_type_edge_falling) ? bit(offset) : 0); + regmap_update_bits(chip->regs, sifive_gpio_high_ie, bit(offset), + (trigger & irq_type_level_high) ? bit(offset) : 0); + regmap_update_bits(chip->regs, sifive_gpio_low_ie, bit(offset), + (trigger & irq_type_level_low) ? bit(offset) : 0); + spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags); +} + +static int sifive_gpio_irq_set_type(struct irq_data *d, unsigned int trigger) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct sifive_gpio *chip = gpiochip_get_data(gc); + int offset = irqd_to_hwirq(d); + + if (offset < 0 || offset >= gc->ngpio) + return -einval; + + chip->trigger[offset] = trigger; + sifive_gpio_set_ie(chip, offset); + return 0; +} + +static void sifive_gpio_irq_enable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct sifive_gpio *chip = gpiochip_get_data(gc); + int offset = irqd_to_hwirq(d) % sifive_gpio_max; + u32 bit = bit(offset); + unsigned long flags; + + irq_chip_enable_parent(d); + + /* switch to input */ + gc->direction_input(gc, offset); + + spin_lock_irqsave(&gc->bgpio_lock, flags); + /* clear any sticky pending interrupts */ + regmap_write(chip->regs, sifive_gpio_rise_ip, bit); + regmap_write(chip->regs, sifive_gpio_fall_ip, bit); + regmap_write(chip->regs, sifive_gpio_high_ip, bit); + regmap_write(chip->regs, sifive_gpio_low_ip, bit); + spin_unlock_irqrestore(&gc->bgpio_lock, flags); + + /* enable interrupts */ + assign_bit(offset, (unsigned long *)&chip->irq_state, 1); + sifive_gpio_set_ie(chip, offset); +} + +static void sifive_gpio_irq_disable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct sifive_gpio *chip = gpiochip_get_data(gc); + int offset = irqd_to_hwirq(d) % sifive_gpio_max; + + assign_bit(offset, (unsigned long *)&chip->irq_state, 0); + sifive_gpio_set_ie(chip, offset); + irq_chip_disable_parent(d); +} + +static void sifive_gpio_irq_eoi(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct sifive_gpio *chip = gpiochip_get_data(gc); + int offset = irqd_to_hwirq(d) % sifive_gpio_max; + u32 bit = bit(offset); + unsigned long flags; + + spin_lock_irqsave(&gc->bgpio_lock, flags); + /* clear all pending interrupts */ + regmap_write(chip->regs, sifive_gpio_rise_ip, bit); + regmap_write(chip->regs, sifive_gpio_fall_ip, bit); + regmap_write(chip->regs, sifive_gpio_high_ip, bit); + regmap_write(chip->regs, sifive_gpio_low_ip, bit); + spin_unlock_irqrestore(&gc->bgpio_lock, flags); + + irq_chip_eoi_parent(d); +} + +static struct irq_chip sifive_gpio_irqchip = { + .name = "sifive-gpio", + .irq_set_type = sifive_gpio_irq_set_type, + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_enable = sifive_gpio_irq_enable, + .irq_disable = sifive_gpio_irq_disable, + .irq_eoi = sifive_gpio_irq_eoi, +}; + +static int sifive_gpio_child_to_parent_hwirq(struct gpio_chip *gc, + unsigned int child, + unsigned int child_type, + unsigned int *parent, + unsigned int *parent_type) +{ + *parent_type = irq_type_none; + *parent = child + sifive_gpio_irq_offset; + return 0; +} + +static const struct regmap_config sifive_gpio_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, + .disable_locking = true, +}; + +static int sifive_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = pdev->dev.of_node; + struct device_node *irq_parent; + struct irq_domain *parent; + struct gpio_irq_chip *girq; + struct sifive_gpio *chip; + int ret, ngpio; + + chip = devm_kzalloc(dev, sizeof(*chip), gfp_kernel); + if (!chip) + return -enomem; + + chip->base = devm_platform_ioremap_resource(pdev, 0); + if (is_err(chip->base)) { + dev_err(dev, "failed to allocate device memory "); + return ptr_err(chip->base); + } + + chip->regs = devm_regmap_init_mmio(dev, chip->base, + &sifive_gpio_regmap_config); + if (is_err(chip->regs)) + return ptr_err(chip->regs); + + ngpio = of_irq_count(node); + if (ngpio >= sifive_gpio_max) { + dev_err(dev, "too many gpio interrupts (max=%d) ", + sifive_gpio_max); + return -enxio; + } + + irq_parent = of_irq_find_parent(node); + if (!irq_parent) { + dev_err(dev, "no irq parent node "); + return -enodev; + } + parent = irq_find_host(irq_parent); + if (!parent) { + dev_err(dev, "no irq parent domain "); + return -enodev; + } + + ret = bgpio_init(&chip->gc, dev, 4, + chip->base + sifive_gpio_input_val, + chip->base + sifive_gpio_output_val, + null, + chip->base + sifive_gpio_output_en, + chip->base + sifive_gpio_input_en, + 0); + if (ret) { + dev_err(dev, "unable to init generic gpio "); + return ret; + } + + /* disable all gpio interrupts before enabling parent interrupts */ + regmap_write(chip->regs, sifive_gpio_rise_ie, 0); + regmap_write(chip->regs, sifive_gpio_fall_ie, 0); + regmap_write(chip->regs, sifive_gpio_high_ie, 0); + regmap_write(chip->regs, sifive_gpio_low_ie, 0); + chip->irq_state = 0; + + chip->gc.base = -1; + chip->gc.ngpio = ngpio; + chip->gc.label = dev_name(dev); + chip->gc.parent = dev; + chip->gc.owner = this_module; + girq = &chip->gc.irq; + girq->chip = &sifive_gpio_irqchip; + girq->fwnode = of_node_to_fwnode(node); + girq->parent_domain = parent; + girq->child_to_parent_hwirq = sifive_gpio_child_to_parent_hwirq; + girq->handler = handle_bad_irq; + girq->default_type = irq_type_none; + + platform_set_drvdata(pdev, chip); + return gpiochip_add_data(&chip->gc, chip); +} + +static const struct of_device_id sifive_gpio_match[] = { + { .compatible = "sifive,gpio0" }, + { .compatible = "sifive,fu540-c000-gpio" }, + { }, +}; + +static struct platform_driver sifive_gpio_driver = { + .probe = sifive_gpio_probe, + .driver = { + .name = "sifive_gpio", + .of_match_table = of_match_ptr(sifive_gpio_match), + }, +}; +builtin_platform_driver(sifive_gpio_driver)
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General Purpose I/O (gpio)
|
96868dce644d002383f6d5eb575a6ce3c8779f39
|
yash shah bartosz golaszewski bgolaszewski baylibre com linus walleij linus walleij linaro org
|
drivers
|
gpio
| |
gpio: wcd934x: add support to wcd934x gpio controller
|
this patch adds support to wcd934x gpio block found in wcd9340/wc9341 audio codecs.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support to wcd934x gpio controller
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['wcd934x']
|
['c', 'kconfig', 'makefile']
| 3
| 129
| 0
|
--- diff --git a/drivers/gpio/kconfig b/drivers/gpio/kconfig --- a/drivers/gpio/kconfig +++ b/drivers/gpio/kconfig +config gpio_wcd934x + tristate "qualcomm technologies inc wcd9340/wcd9341 gpio controller driver" + depends on mfd_wcd934x && of_gpio + help + this driver is to supprot gpio block found on the qualcomm technologies + inc wcd9340/wcd9341 audio codec. + diff --git a/drivers/gpio/makefile b/drivers/gpio/makefile --- a/drivers/gpio/makefile +++ b/drivers/gpio/makefile +obj-$(config_gpio_wcd934x) += gpio-wcd934x.o diff --git a/drivers/gpio/gpio-wcd934x.c b/drivers/gpio/gpio-wcd934x.c --- /dev/null +++ b/drivers/gpio/gpio-wcd934x.c +// spdx-license-identifier: gpl-2.0 +// copyright (c) 2019, linaro limited + +#include <linux/module.h> +#include <linux/gpio/driver.h> +#include <linux/regmap.h> +#include <linux/slab.h> +#include <linux/of_device.h> + +#define wcd_pin_mask(p) bit(p - 1) +#define wcd_reg_dir_ctl_offset 0x42 +#define wcd_reg_val_ctl_offset 0x43 +#define wcd934x_npins 5 + +struct wcd_gpio_data { + struct regmap *map; + struct gpio_chip chip; +}; + +static int wcd_gpio_get_direction(struct gpio_chip *chip, unsigned int pin) +{ + struct wcd_gpio_data *data = gpiochip_get_data(chip); + unsigned int value; + int ret; + + ret = regmap_read(data->map, wcd_reg_dir_ctl_offset, &value); + if (ret < 0) + return ret; + + if (value & wcd_pin_mask(pin)) + return gpio_line_direction_out; + + return gpio_line_direction_in; +} + +static int wcd_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) +{ + struct wcd_gpio_data *data = gpiochip_get_data(chip); + + return regmap_update_bits(data->map, wcd_reg_dir_ctl_offset, + wcd_pin_mask(pin), 0); +} + +static int wcd_gpio_direction_output(struct gpio_chip *chip, unsigned int pin, + int val) +{ + struct wcd_gpio_data *data = gpiochip_get_data(chip); + + regmap_update_bits(data->map, wcd_reg_dir_ctl_offset, + wcd_pin_mask(pin), wcd_pin_mask(pin)); + + return regmap_update_bits(data->map, wcd_reg_val_ctl_offset, + wcd_pin_mask(pin), + val ? wcd_pin_mask(pin) : 0); +} + +static int wcd_gpio_get(struct gpio_chip *chip, unsigned int pin) +{ + struct wcd_gpio_data *data = gpiochip_get_data(chip); + int value; + + regmap_read(data->map, wcd_reg_val_ctl_offset, &value); + + return !!(value && wcd_pin_mask(pin)); +} + +static void wcd_gpio_set(struct gpio_chip *chip, unsigned int pin, int val) +{ + wcd_gpio_direction_output(chip, pin, val); +} + +static int wcd_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct wcd_gpio_data *data; + struct gpio_chip *chip; + + data = devm_kzalloc(dev, sizeof(*data), gfp_kernel); + if (!data) + return -enomem; + + data->map = dev_get_regmap(dev->parent, null); + if (!data->map) { + dev_err(dev, "%s: failed to get regmap ", __func__); + return -einval; + } + + chip = &data->chip; + chip->direction_input = wcd_gpio_direction_input; + chip->direction_output = wcd_gpio_direction_output; + chip->get_direction = wcd_gpio_get_direction; + chip->get = wcd_gpio_get; + chip->set = wcd_gpio_set; + chip->parent = dev; + chip->base = -1; + chip->ngpio = wcd934x_npins; + chip->label = dev_name(dev); + chip->of_gpio_n_cells = 2; + chip->can_sleep = false; + + return devm_gpiochip_add_data(dev, chip, data); +} + +static const struct of_device_id wcd_gpio_of_match[] = { + { .compatible = "qcom,wcd9340-gpio" }, + { .compatible = "qcom,wcd9341-gpio" }, + { } +}; +module_device_table(of, wcd_gpio_of_match); + +static struct platform_driver wcd_gpio_driver = { + .driver = { + .name = "wcd934x-gpio", + .of_match_table = wcd_gpio_of_match, + }, + .probe = wcd_gpio_probe, +}; + +module_platform_driver(wcd_gpio_driver); +module_description("qualcomm technologies, inc wcd gpio control driver"); +module_license("gpl v2");
|
General Purpose I/O (gpio)
|
59c324683400b41caa6d85b091e812ee3d5415c3
|
srinivas kandagatla
|
drivers
|
gpio
| |
leds: lm3692x: allow to configure over voltage protection
|
overvoltage protection is currently using the default of 29v. make it configurable via dt.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
allow to configure over voltage protection
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['lm3692x']
|
['c']
| 1
| 30
| 4
|
--- diff --git a/drivers/leds/leds-lm3692x.c b/drivers/leds/leds-lm3692x.c --- a/drivers/leds/leds-lm3692x.c +++ b/drivers/leds/leds-lm3692x.c + + u8 boost_ctrl; - ret = regmap_write(led->regmap, lm3692x_boost_ctrl, - lm3692x_boost_sw_1mhz | - lm3692x_boost_sw_no_shift | - lm3692x_ocp_prot_1_5a); + ret = regmap_write(led->regmap, lm3692x_boost_ctrl, led->boost_ctrl); + u32 ovp; + led->boost_ctrl = lm3692x_boost_sw_1mhz | + lm3692x_boost_sw_no_shift | + lm3692x_ocp_prot_1_5a; + ret = device_property_read_u32(&led->client->dev, + "ti,ovp-microvolt", &ovp); + if (ret) { + led->boost_ctrl |= lm3692x_ovp_29v; + } else { + switch (ovp) { + case 17000000: + break; + case 21000000: + led->boost_ctrl |= lm3692x_ovp_21v; + break; + case 25000000: + led->boost_ctrl |= lm3692x_ovp_25v; + break; + case 29000000: + led->boost_ctrl |= lm3692x_ovp_29v; + break; + default: + dev_err(&led->client->dev, "invalid ovp %d ", ovp); + return -einval; + } + } +
|
Leds
|
cffd61a5c7755546154539dcd7f36590e91e002f
|
guido g nther pavel machek pavel ucw cz
|
drivers
|
leds
| |
leds: tps6105x: add driver for mfd chip led mode
|
this driver adds support for the led operational mode of the tps6105x mfd device.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add driver for mfd chip led mode
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['tps6105x']
|
['c', 'kconfig', 'makefile']
| 3
| 100
| 0
|
--- diff --git a/drivers/leds/kconfig b/drivers/leds/kconfig --- a/drivers/leds/kconfig +++ b/drivers/leds/kconfig +config leds_tps6105x + tristate "led support for ti tps6105x" + depends on leds_class + depends on tps6105x + default y if tps6105x + help + this driver supports tps61050/tps61052 led chips. + it is a single boost converter primarily for white leds and + audio amplifiers. + diff --git a/drivers/leds/makefile b/drivers/leds/makefile --- a/drivers/leds/makefile +++ b/drivers/leds/makefile +obj-$(config_leds_tps6105x) += leds-tps6105x.o diff --git a/drivers/leds/leds-tps6105x.c b/drivers/leds/leds-tps6105x.c --- /dev/null +++ b/drivers/leds/leds-tps6105x.c +// spdx-license-identifier: gpl-2.0-only +/* + * copyright (c) 2019 sven van asbroeck + */ + +#include <linux/leds.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/mfd/tps6105x.h> +#include <linux/regmap.h> + +struct tps6105x_priv { + struct regmap *regmap; + struct led_classdev cdev; + struct fwnode_handle *fwnode; +}; + +static void tps6105x_handle_put(void *data) +{ + struct tps6105x_priv *priv = data; + + fwnode_handle_put(priv->fwnode); +} + +static int tps6105x_brightness_set(struct led_classdev *cdev, + enum led_brightness brightness) +{ + struct tps6105x_priv *priv = container_of(cdev, struct tps6105x_priv, + cdev); + + return regmap_update_bits(priv->regmap, tps6105x_reg_0, + tps6105x_reg0_torchc_mask, + brightness << tps6105x_reg0_torchc_shift); +} + +static int tps6105x_led_probe(struct platform_device *pdev) +{ + struct tps6105x *tps6105x = dev_get_platdata(&pdev->dev); + struct tps6105x_platform_data *pdata = tps6105x->pdata; + struct led_init_data init_data = { }; + struct tps6105x_priv *priv; + int ret; + + /* this instance is not set for torch mode so bail out */ + if (pdata->mode != tps6105x_mode_torch) { + dev_info(&pdev->dev, + "chip not in torch mode, exit probe"); + return -einval; + } + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), gfp_kernel); + if (!priv) + return -enomem; + /* fwnode/devicetree is optional. null is allowed for priv->fwnode */ + priv->fwnode = device_get_next_child_node(pdev->dev.parent, null); + ret = devm_add_action_or_reset(&pdev->dev, tps6105x_handle_put, priv); + if (ret) + return ret; + priv->regmap = tps6105x->regmap; + priv->cdev.brightness_set_blocking = tps6105x_brightness_set; + priv->cdev.max_brightness = 7; + init_data.devicename = "tps6105x"; + init_data.default_label = ":torch"; + init_data.fwnode = priv->fwnode; + + ret = regmap_update_bits(tps6105x->regmap, tps6105x_reg_0, + tps6105x_reg0_mode_mask | + tps6105x_reg0_torchc_mask, + tps6105x_reg0_mode_torch << + tps6105x_reg0_mode_shift); + if (ret) + return ret; + + return devm_led_classdev_register_ext(&pdev->dev, &priv->cdev, + &init_data); +} + +static struct platform_driver led_driver = { + .probe = tps6105x_led_probe, + .driver = { + .name = "tps6105x-leds", + }, +}; + +module_platform_driver(led_driver); + +module_description("tps6105x led driver"); +module_author("sven van asbroeck <thesven73@gmail.com>"); +module_license("gpl v2");
|
Leds
|
b3b42b4a383c11daf34b6e4e997bd0d0bb83f02b
|
sven van asbroeck jacek anaszewski jacek anaszewski gmail com
|
drivers
|
leds
| |
dmaengine: create symlinks between dma channels and slaves
|
currently it is not easy to find out which dma channels are in use, and which slave devices are using which channels.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
create symlinks between dma channels and slaves, because currently it is not easy to find out which dma channels are in use, and which slave devices are using which channels
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['c', 'h']
| 2
| 35
| 6
|
--- diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c +#define dma_slave_name "slave" + - if (chan) { - /* valid channel found or requester needs to be deferred */ - if (!is_err(chan) || ptr_err(chan) == -eprobe_defer) - return chan; - } + if (ptr_err(chan) == -eprobe_defer) + return chan; + + if (!is_err_or_null(chan)) + goto found; - return chan ? chan : err_ptr(-eprobe_defer); + if (!is_err_or_null(chan)) + goto found; + + return err_ptr(-eprobe_defer); + +found: + chan->slave = dev; + chan->name = kasprintf(gfp_kernel, "dma:%s", name); + if (!chan->name) + return err_ptr(-enomem); + + if (sysfs_create_link(&chan->dev->device.kobj, &dev->kobj, + dma_slave_name)) + dev_err(dev, "cannot create dma %s symlink ", dma_slave_name); + if (sysfs_create_link(&dev->kobj, &chan->dev->device.kobj, chan->name)) + dev_err(dev, "cannot create dma %s symlink ", chan->name); + return chan; + if (chan->slave) { + sysfs_remove_link(&chan->slave->kobj, chan->name); + kfree(chan->name); + chan->name = null; + chan->slave = null; + } + sysfs_remove_link(&chan->dev->device.kobj, dma_slave_name); diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h + * @slave: ptr to the device using this channel + * @name: backlink name for sysfs + struct device *slave; + const char *name;
|
DMA engines
|
71723a96b8b1367fefc18f60025dae792477d602
|
geert uytterhoeven
|
include
|
linux
| |
dmaengine: jz4780: add support for the x1830.
|
add support for probing the dma-jz4780 driver on the x1830 soc.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for the x1830
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['jz4780']
|
['c']
| 1
| 7
| 0
|
--- diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c --- a/drivers/dma/dma-jz4780.c +++ b/drivers/dma/dma-jz4780.c +static const struct jz4780_dma_soc_data x1830_dma_soc_data = { + .nb_channels = 32, + .transfer_ord_max = 7, + .flags = jz_soc_data_programmable_dma, +}; + + { .compatible = "ingenic,x1830-dma", .data = &x1830_dma_soc_data },
|
DMA engines
|
20f5a659554a6e684da0806939bddf8f6537e936
|
zhou yanjie
|
drivers
|
dma
| |
dmaengine: fsl-edma: add edma support for qoriq ls1028a platform
|
our platforms(such as ls1021a, ls1012a, ls1043a, ls1046a, ls1028a) with below registers(chcfg0 - chcfg15) of edma as follows: *-----------------------------------------------------------* | offset | others | ls1028a | |--------------|--------------------|-----------------------| | 0x0 | chcfg0 | chcfg3 | |--------------|--------------------|-----------------------| | 0x1 | chcfg1 | chcfg2 | |--------------|--------------------|-----------------------| | 0x2 | chcfg2 | chcfg1 | |--------------|--------------------|-----------------------| | 0x3 | chcfg3 | chcfg0 | |--------------|--------------------|-----------------------| | ... | ...... | ...... | |--------------|--------------------|-----------------------| | 0xc | chcfg12 | chcfg15 | |--------------|--------------------|-----------------------| | 0xd | chcfg13 | chcfg14 | |--------------|--------------------|-----------------------| | 0xe | chcfg14 | chcfg13 | |--------------|--------------------|-----------------------| | 0xf | chcfg15 | chcfg12 | *-----------------------------------------------------------*
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add edma support for qoriq ls1028a platform
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['fsl-edma']
|
['c', 'h']
| 3
| 14
| 0
|
--- diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c + int endian_diff[4] = {3, 1, -1, -3}; + + if (fsl_chan->edma->drvdata->mux_swap) + ch_off += endian_diff[ch_off % 4]; + diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h + bool mux_swap; diff --git a/drivers/dma/fsl-edma.c b/drivers/dma/fsl-edma.c --- a/drivers/dma/fsl-edma.c +++ b/drivers/dma/fsl-edma.c +static struct fsl_edma_drvdata ls1028a_data = { + .version = v1, + .dmamuxs = dmamux_nr, + .mux_swap = true, + .setup_irq = fsl_edma_irq_init, +}; + + { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data},
|
DMA engines
|
ed5a0ab41555032a944c18bd5f8eb275c740f856
|
peng ma
|
drivers
|
dma
| |
dmaengine: hisilicon: add kunpeng dma engine support
|
this patch adds a driver for hisilicon kunpeng dma engine. this dma engine which is an pcie iep offers 30 channels, each channel has a send queue, a complete queue and an interrupt to help to do tasks. this dma engine can do memory copy between memory blocks or between memory and device buffer.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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add kunpeng dma engine support
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
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['hisilicon']
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['c', 'kconfig', 'makefile']
| 3
| 620
| 0
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--- diff --git a/drivers/dma/kconfig b/drivers/dma/kconfig --- a/drivers/dma/kconfig +++ b/drivers/dma/kconfig +config hisi_dma + tristate "hisilicon dma engine support" + depends on arm64 || (compile_test && pci_msi) + select dma_engine + select dma_virtual_channels + help + support hisilicon kunpeng dma engine. + diff --git a/drivers/dma/makefile b/drivers/dma/makefile --- a/drivers/dma/makefile +++ b/drivers/dma/makefile +obj-$(config_hisi_dma) += hisi_dma.o diff --git a/drivers/dma/hisi_dma.c b/drivers/dma/hisi_dma.c --- /dev/null +++ b/drivers/dma/hisi_dma.c +// spdx-license-identifier: gpl-2.0-only +/* copyright(c) 2019 hisilicon limited. */ +#include <linux/bitfield.h> +#include <linux/dmaengine.h> +#include <linux/init.h> +#include <linux/iopoll.h> +#include <linux/module.h> +#include <linux/pci.h> +#include <linux/spinlock.h> +#include "virt-dma.h" + +#define hisi_dma_sq_base_l 0x0 +#define hisi_dma_sq_base_h 0x4 +#define hisi_dma_sq_depth 0x8 +#define hisi_dma_sq_tail_ptr 0xc +#define hisi_dma_cq_base_l 0x10 +#define hisi_dma_cq_base_h 0x14 +#define hisi_dma_cq_depth 0x18 +#define hisi_dma_cq_head_ptr 0x1c +#define hisi_dma_ctrl0 0x20 +#define hisi_dma_ctrl0_queue_en_s 0 +#define hisi_dma_ctrl0_queue_pause_s 4 +#define hisi_dma_ctrl1 0x24 +#define hisi_dma_ctrl1_queue_reset_s 0 +#define hisi_dma_q_fsm_sts 0x30 +#define hisi_dma_fsm_sts_mask genmask(3, 0) +#define hisi_dma_int_sts 0x40 +#define hisi_dma_int_sts_mask genmask(12, 0) +#define hisi_dma_int_msk 0x44 +#define hisi_dma_mode 0x217c +#define hisi_dma_offset 0x100 + +#define hisi_dma_msi_num 30 +#define hisi_dma_chan_num 30 +#define hisi_dma_q_depth_val 1024 + +#define pci_bar_2 2 + +enum hisi_dma_mode { + ep = 0, + rc, +}; + +enum hisi_dma_chan_status { + disable = -1, + idle = 0, + run, + cpl, + pause, + halt, + abort, + wait, + buffclr, +}; + +struct hisi_dma_sqe { + __le32 dw0; +#define opcode_mask genmask(3, 0) +#define opcode_small_package 0x1 +#define opcode_m2m 0x4 +#define local_irq_en bit(8) +#define attr_src_mask genmask(14, 12) + __le32 dw1; + __le32 dw2; +#define attr_dst_mask genmask(26, 24) + __le32 length; + __le64 src_addr; + __le64 dst_addr; +}; + +struct hisi_dma_cqe { + __le32 rsv0; + __le32 rsv1; + __le16 sq_head; + __le16 rsv2; + __le16 rsv3; + __le16 w0; +#define status_mask genmask(15, 1) +#define status_succ 0x0 +#define valid_bit bit(0) +}; + +struct hisi_dma_desc { + struct virt_dma_desc vd; + struct hisi_dma_sqe sqe; +}; + +struct hisi_dma_chan { + struct virt_dma_chan vc; + struct hisi_dma_dev *hdma_dev; + struct hisi_dma_sqe *sq; + struct hisi_dma_cqe *cq; + dma_addr_t sq_dma; + dma_addr_t cq_dma; + u32 sq_tail; + u32 cq_head; + u32 qp_num; + enum hisi_dma_chan_status status; + struct hisi_dma_desc *desc; +}; + +struct hisi_dma_dev { + struct pci_dev *pdev; + void __iomem *base; + struct dma_device dma_dev; + u32 chan_num; + u32 chan_depth; + struct hisi_dma_chan chan[]; +}; + +static inline struct hisi_dma_chan *to_hisi_dma_chan(struct dma_chan *c) +{ + return container_of(c, struct hisi_dma_chan, vc.chan); +} + +static inline struct hisi_dma_desc *to_hisi_dma_desc(struct virt_dma_desc *vd) +{ + return container_of(vd, struct hisi_dma_desc, vd); +} + +static inline void hisi_dma_chan_write(void __iomem *base, u32 reg, u32 index, + u32 val) +{ + writel_relaxed(val, base + reg + index * hisi_dma_offset); +} + +static inline void hisi_dma_update_bit(void __iomem *addr, u32 pos, bool val) +{ + u32 tmp; + + tmp = readl_relaxed(addr); + tmp = val ? tmp | bit(pos) : tmp & ~bit(pos); + writel_relaxed(tmp, addr); +} + +static void hisi_dma_free_irq_vectors(void *data) +{ + pci_free_irq_vectors(data); +} + +static void hisi_dma_pause_dma(struct hisi_dma_dev *hdma_dev, u32 index, + bool pause) +{ + void __iomem *addr = hdma_dev->base + hisi_dma_ctrl0 + index * + hisi_dma_offset; + + hisi_dma_update_bit(addr, hisi_dma_ctrl0_queue_pause_s, pause); +} + +static void hisi_dma_enable_dma(struct hisi_dma_dev *hdma_dev, u32 index, + bool enable) +{ + void __iomem *addr = hdma_dev->base + hisi_dma_ctrl0 + index * + hisi_dma_offset; + + hisi_dma_update_bit(addr, hisi_dma_ctrl0_queue_en_s, enable); +} + +static void hisi_dma_mask_irq(struct hisi_dma_dev *hdma_dev, u32 qp_index) +{ + hisi_dma_chan_write(hdma_dev->base, hisi_dma_int_msk, qp_index, + hisi_dma_int_sts_mask); +} + +static void hisi_dma_unmask_irq(struct hisi_dma_dev *hdma_dev, u32 qp_index) +{ + void __iomem *base = hdma_dev->base; + + hisi_dma_chan_write(base, hisi_dma_int_sts, qp_index, + hisi_dma_int_sts_mask); + hisi_dma_chan_write(base, hisi_dma_int_msk, qp_index, 0); +} + +static void hisi_dma_do_reset(struct hisi_dma_dev *hdma_dev, u32 index) +{ + void __iomem *addr = hdma_dev->base + hisi_dma_ctrl1 + index * + hisi_dma_offset; + + hisi_dma_update_bit(addr, hisi_dma_ctrl1_queue_reset_s, 1); +} + +static void hisi_dma_reset_qp_point(struct hisi_dma_dev *hdma_dev, u32 index) +{ + hisi_dma_chan_write(hdma_dev->base, hisi_dma_sq_tail_ptr, index, 0); + hisi_dma_chan_write(hdma_dev->base, hisi_dma_cq_head_ptr, index, 0); +} + +static void hisi_dma_reset_hw_chan(struct hisi_dma_chan *chan) +{ + struct hisi_dma_dev *hdma_dev = chan->hdma_dev; + u32 index = chan->qp_num, tmp; + int ret; + + hisi_dma_pause_dma(hdma_dev, index, true); + hisi_dma_enable_dma(hdma_dev, index, false); + hisi_dma_mask_irq(hdma_dev, index); + + ret = readl_relaxed_poll_timeout(hdma_dev->base + + hisi_dma_q_fsm_sts + index * hisi_dma_offset, tmp, + field_get(hisi_dma_fsm_sts_mask, tmp) != run, 10, 1000); + if (ret) { + dev_err(&hdma_dev->pdev->dev, "disable channel timeout! "); + warn_on(1); + } + + hisi_dma_do_reset(hdma_dev, index); + hisi_dma_reset_qp_point(hdma_dev, index); + hisi_dma_pause_dma(hdma_dev, index, false); + hisi_dma_enable_dma(hdma_dev, index, true); + hisi_dma_unmask_irq(hdma_dev, index); + + ret = readl_relaxed_poll_timeout(hdma_dev->base + + hisi_dma_q_fsm_sts + index * hisi_dma_offset, tmp, + field_get(hisi_dma_fsm_sts_mask, tmp) == idle, 10, 1000); + if (ret) { + dev_err(&hdma_dev->pdev->dev, "reset channel timeout! "); + warn_on(1); + } +} + +static void hisi_dma_free_chan_resources(struct dma_chan *c) +{ + struct hisi_dma_chan *chan = to_hisi_dma_chan(c); + struct hisi_dma_dev *hdma_dev = chan->hdma_dev; + + hisi_dma_reset_hw_chan(chan); + vchan_free_chan_resources(&chan->vc); + + memset(chan->sq, 0, sizeof(struct hisi_dma_sqe) * hdma_dev->chan_depth); + memset(chan->cq, 0, sizeof(struct hisi_dma_cqe) * hdma_dev->chan_depth); + chan->sq_tail = 0; + chan->cq_head = 0; + chan->status = disable; +} + +static void hisi_dma_desc_free(struct virt_dma_desc *vd) +{ + kfree(to_hisi_dma_desc(vd)); +} + +static struct dma_async_tx_descriptor * +hisi_dma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dst, dma_addr_t src, + size_t len, unsigned long flags) +{ + struct hisi_dma_chan *chan = to_hisi_dma_chan(c); + struct hisi_dma_desc *desc; + + desc = kzalloc(sizeof(*desc), gfp_nowait); + if (!desc) + return null; + + desc->sqe.length = cpu_to_le32(len); + desc->sqe.src_addr = cpu_to_le64(src); + desc->sqe.dst_addr = cpu_to_le64(dst); + + return vchan_tx_prep(&chan->vc, &desc->vd, flags); +} + +static enum dma_status +hisi_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + return dma_cookie_status(c, cookie, txstate); +} + +static void hisi_dma_start_transfer(struct hisi_dma_chan *chan) +{ + struct hisi_dma_sqe *sqe = chan->sq + chan->sq_tail; + struct hisi_dma_dev *hdma_dev = chan->hdma_dev; + struct hisi_dma_desc *desc; + struct virt_dma_desc *vd; + + vd = vchan_next_desc(&chan->vc); + if (!vd) { + dev_err(&hdma_dev->pdev->dev, "no issued task! "); + chan->desc = null; + return; + } + list_del(&vd->node); + desc = to_hisi_dma_desc(vd); + chan->desc = desc; + + memcpy(sqe, &desc->sqe, sizeof(struct hisi_dma_sqe)); + + /* update other field in sqe */ + sqe->dw0 = cpu_to_le32(field_prep(opcode_mask, opcode_m2m)); + sqe->dw0 |= cpu_to_le32(local_irq_en); + + /* make sure data has been updated in sqe */ + wmb(); + + /* update sq tail, point to new sqe position */ + chan->sq_tail = (chan->sq_tail + 1) % hdma_dev->chan_depth; + + /* update sq_tail to trigger a new task */ + hisi_dma_chan_write(hdma_dev->base, hisi_dma_sq_tail_ptr, chan->qp_num, + chan->sq_tail); +} + +static void hisi_dma_issue_pending(struct dma_chan *c) +{ + struct hisi_dma_chan *chan = to_hisi_dma_chan(c); + unsigned long flags; + + spin_lock_irqsave(&chan->vc.lock, flags); + + if (vchan_issue_pending(&chan->vc)) + hisi_dma_start_transfer(chan); + + spin_unlock_irqrestore(&chan->vc.lock, flags); +} + +static int hisi_dma_terminate_all(struct dma_chan *c) +{ + struct hisi_dma_chan *chan = to_hisi_dma_chan(c); + unsigned long flags; + list_head(head); + + spin_lock_irqsave(&chan->vc.lock, flags); + + hisi_dma_pause_dma(chan->hdma_dev, chan->qp_num, true); + if (chan->desc) { + vchan_terminate_vdesc(&chan->desc->vd); + chan->desc = null; + } + + vchan_get_all_descriptors(&chan->vc, &head); + + spin_unlock_irqrestore(&chan->vc.lock, flags); + + vchan_dma_desc_free_list(&chan->vc, &head); + hisi_dma_pause_dma(chan->hdma_dev, chan->qp_num, false); + + return 0; +} + +static void hisi_dma_synchronize(struct dma_chan *c) +{ + struct hisi_dma_chan *chan = to_hisi_dma_chan(c); + + vchan_synchronize(&chan->vc); +} + +static int hisi_dma_alloc_qps_mem(struct hisi_dma_dev *hdma_dev) +{ + size_t sq_size = sizeof(struct hisi_dma_sqe) * hdma_dev->chan_depth; + size_t cq_size = sizeof(struct hisi_dma_cqe) * hdma_dev->chan_depth; + struct device *dev = &hdma_dev->pdev->dev; + struct hisi_dma_chan *chan; + int i; + + for (i = 0; i < hdma_dev->chan_num; i++) { + chan = &hdma_dev->chan[i]; + chan->sq = dmam_alloc_coherent(dev, sq_size, &chan->sq_dma, + gfp_kernel); + if (!chan->sq) + return -enomem; + + chan->cq = dmam_alloc_coherent(dev, cq_size, &chan->cq_dma, + gfp_kernel); + if (!chan->cq) + return -enomem; + } + + return 0; +} + +static void hisi_dma_init_hw_qp(struct hisi_dma_dev *hdma_dev, u32 index) +{ + struct hisi_dma_chan *chan = &hdma_dev->chan[index]; + u32 hw_depth = hdma_dev->chan_depth - 1; + void __iomem *base = hdma_dev->base; + + /* set sq, cq base */ + hisi_dma_chan_write(base, hisi_dma_sq_base_l, index, + lower_32_bits(chan->sq_dma)); + hisi_dma_chan_write(base, hisi_dma_sq_base_h, index, + upper_32_bits(chan->sq_dma)); + hisi_dma_chan_write(base, hisi_dma_cq_base_l, index, + lower_32_bits(chan->cq_dma)); + hisi_dma_chan_write(base, hisi_dma_cq_base_h, index, + upper_32_bits(chan->cq_dma)); + + /* set sq, cq depth */ + hisi_dma_chan_write(base, hisi_dma_sq_depth, index, hw_depth); + hisi_dma_chan_write(base, hisi_dma_cq_depth, index, hw_depth); + + /* init sq tail and cq head */ + hisi_dma_chan_write(base, hisi_dma_sq_tail_ptr, index, 0); + hisi_dma_chan_write(base, hisi_dma_cq_head_ptr, index, 0); +} + +static void hisi_dma_enable_qp(struct hisi_dma_dev *hdma_dev, u32 qp_index) +{ + hisi_dma_init_hw_qp(hdma_dev, qp_index); + hisi_dma_unmask_irq(hdma_dev, qp_index); + hisi_dma_enable_dma(hdma_dev, qp_index, true); +} + +static void hisi_dma_disable_qp(struct hisi_dma_dev *hdma_dev, u32 qp_index) +{ + hisi_dma_reset_hw_chan(&hdma_dev->chan[qp_index]); +} + +static void hisi_dma_enable_qps(struct hisi_dma_dev *hdma_dev) +{ + int i; + + for (i = 0; i < hdma_dev->chan_num; i++) { + hdma_dev->chan[i].qp_num = i; + hdma_dev->chan[i].hdma_dev = hdma_dev; + hdma_dev->chan[i].vc.desc_free = hisi_dma_desc_free; + vchan_init(&hdma_dev->chan[i].vc, &hdma_dev->dma_dev); + hisi_dma_enable_qp(hdma_dev, i); + } +} + +static void hisi_dma_disable_qps(struct hisi_dma_dev *hdma_dev) +{ + int i; + + for (i = 0; i < hdma_dev->chan_num; i++) { + hisi_dma_disable_qp(hdma_dev, i); + tasklet_kill(&hdma_dev->chan[i].vc.task); + } +} + +static irqreturn_t hisi_dma_irq(int irq, void *data) +{ + struct hisi_dma_chan *chan = data; + struct hisi_dma_dev *hdma_dev = chan->hdma_dev; + struct hisi_dma_desc *desc; + struct hisi_dma_cqe *cqe; + unsigned long flags; + + spin_lock_irqsave(&chan->vc.lock, flags); + + desc = chan->desc; + cqe = chan->cq + chan->cq_head; + if (desc) { + if (field_get(status_mask, cqe->w0) == status_succ) { + chan->cq_head = (chan->cq_head + 1) % + hdma_dev->chan_depth; + hisi_dma_chan_write(hdma_dev->base, + hisi_dma_cq_head_ptr, chan->qp_num, + chan->cq_head); + vchan_cookie_complete(&desc->vd); + } else { + dev_err(&hdma_dev->pdev->dev, "task error! "); + } + + chan->desc = null; + } + + spin_unlock_irqrestore(&chan->vc.lock, flags); + + return irq_handled; +} + +static int hisi_dma_request_qps_irq(struct hisi_dma_dev *hdma_dev) +{ + struct pci_dev *pdev = hdma_dev->pdev; + int i, ret; + + for (i = 0; i < hdma_dev->chan_num; i++) { + ret = devm_request_irq(&pdev->dev, pci_irq_vector(pdev, i), + hisi_dma_irq, irqf_shared, "hisi_dma", + &hdma_dev->chan[i]); + if (ret) + return ret; + } + + return 0; +} + +/* this function enables all hw channels in a device */ +static int hisi_dma_enable_hw_channels(struct hisi_dma_dev *hdma_dev) +{ + int ret; + + ret = hisi_dma_alloc_qps_mem(hdma_dev); + if (ret) { + dev_err(&hdma_dev->pdev->dev, "fail to allocate qp memory! "); + return ret; + } + + ret = hisi_dma_request_qps_irq(hdma_dev); + if (ret) { + dev_err(&hdma_dev->pdev->dev, "fail to request qp irq! "); + return ret; + } + + hisi_dma_enable_qps(hdma_dev); + + return 0; +} + +static void hisi_dma_disable_hw_channels(void *data) +{ + hisi_dma_disable_qps(data); +} + +static void hisi_dma_set_mode(struct hisi_dma_dev *hdma_dev, + enum hisi_dma_mode mode) +{ + writel_relaxed(mode == rc ? 1 : 0, hdma_dev->base + hisi_dma_mode); +} + +static int hisi_dma_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + struct device *dev = &pdev->dev; + struct hisi_dma_dev *hdma_dev; + struct dma_device *dma_dev; + size_t dev_size; + int ret; + + ret = pcim_enable_device(pdev); + if (ret) { + dev_err(dev, "failed to enable device mem! "); + return ret; + } + + ret = pcim_iomap_regions(pdev, 1 << pci_bar_2, pci_name(pdev)); + if (ret) { + dev_err(dev, "failed to remap i/o region! "); + return ret; + } + + ret = pci_set_dma_mask(pdev, dma_bit_mask(64)); + if (ret) + return ret; + + ret = pci_set_consistent_dma_mask(pdev, dma_bit_mask(64)); + if (ret) + return ret; + + dev_size = sizeof(struct hisi_dma_chan) * hisi_dma_chan_num + + sizeof(*hdma_dev); + hdma_dev = devm_kzalloc(dev, dev_size, gfp_kernel); + if (!hdma_dev) + return -einval; + + hdma_dev->base = pcim_iomap_table(pdev)[pci_bar_2]; + hdma_dev->pdev = pdev; + hdma_dev->chan_num = hisi_dma_chan_num; + hdma_dev->chan_depth = hisi_dma_q_depth_val; + + pci_set_drvdata(pdev, hdma_dev); + pci_set_master(pdev); + + ret = pci_alloc_irq_vectors(pdev, hisi_dma_msi_num, hisi_dma_msi_num, + pci_irq_msi); + if (ret < 0) { + dev_err(dev, "failed to allocate msi vectors! "); + return ret; + } + + ret = devm_add_action_or_reset(dev, hisi_dma_free_irq_vectors, pdev); + if (ret) + return ret; + + dma_dev = &hdma_dev->dma_dev; + dma_cap_set(dma_memcpy, dma_dev->cap_mask); + dma_dev->device_free_chan_resources = hisi_dma_free_chan_resources; + dma_dev->device_prep_dma_memcpy = hisi_dma_prep_dma_memcpy; + dma_dev->device_tx_status = hisi_dma_tx_status; + dma_dev->device_issue_pending = hisi_dma_issue_pending; + dma_dev->device_terminate_all = hisi_dma_terminate_all; + dma_dev->device_synchronize = hisi_dma_synchronize; + dma_dev->directions = bit(dma_mem_to_mem); + dma_dev->dev = dev; + init_list_head(&dma_dev->channels); + + hisi_dma_set_mode(hdma_dev, rc); + + ret = hisi_dma_enable_hw_channels(hdma_dev); + if (ret < 0) { + dev_err(dev, "failed to enable hw channel! "); + return ret; + } + + ret = devm_add_action_or_reset(dev, hisi_dma_disable_hw_channels, + hdma_dev); + if (ret) + return ret; + + ret = dmaenginem_async_device_register(dma_dev); + if (ret < 0) + dev_err(dev, "failed to register device! "); + + return ret; +} + +static const struct pci_device_id hisi_dma_pci_tbl[] = { + { pci_device(pci_vendor_id_huawei, 0xa122) }, + { 0, } +}; + +static struct pci_driver hisi_dma_pci_driver = { + .name = "hisi_dma", + .id_table = hisi_dma_pci_tbl, + .probe = hisi_dma_probe, +}; + +module_pci_driver(hisi_dma_pci_driver); + +module_author("zhou wang <wangzhou1@hisilicon.com>"); +module_author("zhenfa qiu <qiuzhenfa@hisilicon.com>"); +module_description("hisilicon kunpeng dma controller driver"); +module_license("gpl v2"); +module_device_table(pci, hisi_dma_pci_tbl);
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DMA engines
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e9f08b65250d73ab70e79e194813f52b8d306784
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zhou wang
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drivers
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dma
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x86/asm: add iosubmit_cmds512() based on movdir64b cpu instruction
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with the introduction of movdir64b instruction, there is now an instruction that can write 64 bytes of data atomically.
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this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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idxd driver for intel data streaming accelerator
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
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[]
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['h']
| 1
| 36
| 0
|
--- diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h +/** + * iosubmit_cmds512 - copy data to single mmio location, in 512-bit units + * @__dst: destination, in mmio space (must be 512-bit aligned) + * @src: source + * @count: number of 512 bits quantities to submit + * + * submit data from kernel space to mmio space, in units of 512 bits at a + * time. order of access is not guaranteed, nor is a memory barrier + * performed afterwards. + * + * warning: do not use this helper unless your driver has checked that the cpu + * instruction is supported on the platform. + */ +static inline void iosubmit_cmds512(void __iomem *__dst, const void *src, + size_t count) +{ + /* + * note that this isn't an "on-stack copy", just definition of "dst" + * as a pointer to 64-bytes of stuff that is going to be overwritten. + * in the movdir64b case that may be needed as you can use the + * movdir64b instruction to copy arbitrary memory around. this trick + * lets the compiler know how much gets clobbered. + */ + volatile struct { char _[64]; } *dst = __dst; + const u8 *from = src; + const u8 *end = from + count * 64; + + while (from < end) { + /* movdir64b [rdx], rax */ + asm volatile(".byte 0x66, 0x0f, 0x38, 0xf8, 0x02" + : "=m" (dst) + : "d" (from), "a" (dst)); + from += 64; + } +} +
|
DMA engines
|
232bb01bb8ad2f88aefbd88b0d3fe3f9a253502b
|
dave jiang
|
arch
|
x86
|
asm, include
|
dmaengine: break out channel registration
|
in preparation for dynamic channel registration, the code segment that does the channel registration is broken out to its own function.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
idxd driver for intel data streaming accelerator
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['c']
| 1
| 81
| 54
|
--- diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c +static int __dma_async_device_channel_register(struct dma_device *device, + struct dma_chan *chan, + int chan_id) +{ + int rc = 0; + int chancnt = device->chancnt; + atomic_t *idr_ref; + struct dma_chan *tchan; + + tchan = list_first_entry_or_null(&device->channels, + struct dma_chan, device_node); + if (tchan->dev) { + idr_ref = tchan->dev->idr_ref; + } else { + idr_ref = kmalloc(sizeof(*idr_ref), gfp_kernel); + if (!idr_ref) + return -enomem; + atomic_set(idr_ref, 0); + } + + chan->local = alloc_percpu(typeof(*chan->local)); + if (!chan->local) + goto err_out; + chan->dev = kzalloc(sizeof(*chan->dev), gfp_kernel); + if (!chan->dev) { + free_percpu(chan->local); + chan->local = null; + goto err_out; + } + + /* + * when the chan_id is a negative value, we are dynamically adding + * the channel. otherwise we are static enumerating. + */ + chan->chan_id = chan_id < 0 ? chancnt : chan_id; + chan->dev->device.class = &dma_devclass; + chan->dev->device.parent = device->dev; + chan->dev->chan = chan; + chan->dev->idr_ref = idr_ref; + chan->dev->dev_id = device->dev_id; + atomic_inc(idr_ref); + dev_set_name(&chan->dev->device, "dma%dchan%d", + device->dev_id, chan->chan_id); + + rc = device_register(&chan->dev->device); + if (rc) + goto err_out; + chan->client_count = 0; + device->chancnt = chan->chan_id + 1; + + return 0; + + err_out: + free_percpu(chan->local); + kfree(chan->dev); + if (atomic_dec_return(idr_ref) == 0) + kfree(idr_ref); + return rc; +} + +static void __dma_async_device_channel_unregister(struct dma_device *device, + struct dma_chan *chan) +{ + warn_once(!device->device_release && chan->client_count, + "%s called while %d clients hold a reference ", + __func__, chan->client_count); + mutex_lock(&dma_list_mutex); + chan->dev->chan = null; + mutex_unlock(&dma_list_mutex); + device_unregister(&chan->dev->device); + free_percpu(chan->local); +} + - int chancnt = 0, rc; + int rc, i = 0; - atomic_t *idr_ref; - idr_ref = kmalloc(sizeof(*idr_ref), gfp_kernel); - if (!idr_ref) - return -enomem; - if (rc != 0) { - kfree(idr_ref); + if (rc != 0) - } - - atomic_set(idr_ref, 0); - rc = -enomem; - chan->local = alloc_percpu(typeof(*chan->local)); - if (chan->local == null) + rc = __dma_async_device_channel_register(device, chan, i++); + if (rc < 0) - chan->dev = kzalloc(sizeof(*chan->dev), gfp_kernel); - if (chan->dev == null) { - free_percpu(chan->local); - chan->local = null; - goto err_out; - } - - chan->chan_id = chancnt++; - chan->dev->device.class = &dma_devclass; - chan->dev->device.parent = device->dev; - chan->dev->chan = chan; - chan->dev->idr_ref = idr_ref; - chan->dev->dev_id = device->dev_id; - atomic_inc(idr_ref); - dev_set_name(&chan->dev->device, "dma%dchan%d", - device->dev_id, chan->chan_id); - - rc = device_register(&chan->dev->device); - if (rc) { - free_percpu(chan->local); - chan->local = null; - kfree(chan->dev); - atomic_dec(idr_ref); - goto err_out; - } - chan->client_count = 0; - if (!chancnt) { + if (!device->chancnt) { - device->chancnt = chancnt; - - if (atomic_read(idr_ref) == 0) { + if (!device->chancnt) { - kfree(idr_ref); - list_for_each_entry(chan, &device->channels, device_node) { - warn_once(!device->device_release && chan->client_count, - "%s called while %d clients hold a reference ", - __func__, chan->client_count); - mutex_lock(&dma_list_mutex); - chan->dev->chan = null; - mutex_unlock(&dma_list_mutex); - device_unregister(&chan->dev->device); - free_percpu(chan->local); - } + list_for_each_entry(chan, &device->channels, device_node) + __dma_async_device_channel_unregister(device, chan);
|
DMA engines
|
d2fb0a0438384fee08a418025f743913020033ce
|
dave jiang
|
drivers
|
dma
| |
dmaengine: add support to dynamic register/unregister of channels
|
with the channel registration routines broken out, now add support code to allow independent registering and unregistering of channels in a hotplug fashion.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
idxd driver for intel data streaming accelerator
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['c', 'h']
| 2
| 30
| 8
|
--- diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c +int dma_async_device_channel_register(struct dma_device *device, + struct dma_chan *chan) +{ + int rc; + + rc = __dma_async_device_channel_register(device, chan, -1); + if (rc < 0) + return rc; + + dma_channel_rebalance(); + return 0; +} +export_symbol_gpl(dma_async_device_channel_register); + + list_del(&chan->device_node); + device->chancnt--; +void dma_async_device_channel_unregister(struct dma_device *device, + struct dma_chan *chan) +{ + __dma_async_device_channel_unregister(device, chan); + dma_channel_rebalance(); +} +export_symbol_gpl(dma_async_device_channel_unregister); + - if (!device->chancnt) { - dev_err(device->dev, "%s: device has no channels! ", __func__); - rc = -enodev; - goto err_out; - } - - struct dma_chan *chan; + struct dma_chan *chan, *n; - list_for_each_entry(chan, &device->channels, device_node) + list_for_each_entry_safe(chan, n, &device->channels, device_node) diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h +int dma_async_device_channel_register(struct dma_device *device, + struct dma_chan *chan); +void dma_async_device_channel_unregister(struct dma_device *device, + struct dma_chan *chan);
|
DMA engines
|
e81274cd6b5264809384066e09a5253708822522
|
dave jiang
|
include
|
linux
| |
dmaengine: idxd: init and probe for intel data accelerators
|
the idxd driver introduces the intel data stream accelerator [1] that will be available on future intel xeon cpus. one of the kernel access point for the driver is through the dmaengine subsystem. it will initially provide the dma copy service to the kernel.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
idxd driver for intel data streaming accelerator
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['c', 'kconfig', 'maintainers', 'makefile', 'h']
| 10
| 2,093
| 0
|
--- diff --git a/maintainers b/maintainers --- a/maintainers +++ b/maintainers +intel iadx driver +m: dave jiang <dave.jiang@intel.com> +l: dmaengine@vger.kernel.org +s: supported +f: drivers/dma/idxd/* +f: include/uapi/linux/idxd.h +f: include/linux/idxd.h + diff --git a/drivers/dma/kconfig b/drivers/dma/kconfig --- a/drivers/dma/kconfig +++ b/drivers/dma/kconfig +config intel_idxd + tristate "intel data accelerators support" + depends on pci && x86_64 + select dma_engine + select sbitmap + help + enable support for the intel(r) data accelerators present + in intel xeon cpu. + + say y if you have such a platform. + + if unsure, say n. + diff --git a/drivers/dma/makefile b/drivers/dma/makefile --- a/drivers/dma/makefile +++ b/drivers/dma/makefile +obj-$(config_intel_idxd) += idxd/ diff --git a/drivers/dma/idxd/makefile b/drivers/dma/idxd/makefile --- /dev/null +++ b/drivers/dma/idxd/makefile +obj-$(config_intel_idxd) += idxd.o +idxd-y := init.o irq.o device.o diff --git a/drivers/dma/idxd/device.c b/drivers/dma/idxd/device.c --- /dev/null +++ b/drivers/dma/idxd/device.c +// spdx-license-identifier: gpl-2.0 +/* copyright(c) 2019 intel corporation. all rights rsvd. */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/pci.h> +#include <linux/io-64-nonatomic-lo-hi.h> +#include <uapi/linux/idxd.h> +#include "idxd.h" +#include "registers.h" + +static int idxd_cmd_wait(struct idxd_device *idxd, u32 *status, int timeout); +static int idxd_cmd_send(struct idxd_device *idxd, int cmd_code, u32 operand); + +/* interrupt control bits */ +int idxd_mask_msix_vector(struct idxd_device *idxd, int vec_id) +{ + struct pci_dev *pdev = idxd->pdev; + int msixcnt = pci_msix_vec_count(pdev); + union msix_perm perm; + u32 offset; + + if (vec_id < 0 || vec_id >= msixcnt) + return -einval; + + offset = idxd->msix_perm_offset + vec_id * 8; + perm.bits = ioread32(idxd->reg_base + offset); + perm.ignore = 1; + iowrite32(perm.bits, idxd->reg_base + offset); + + return 0; +} + +void idxd_mask_msix_vectors(struct idxd_device *idxd) +{ + struct pci_dev *pdev = idxd->pdev; + int msixcnt = pci_msix_vec_count(pdev); + int i, rc; + + for (i = 0; i < msixcnt; i++) { + rc = idxd_mask_msix_vector(idxd, i); + if (rc < 0) + dev_warn(&pdev->dev, + "failed disabling msix vec %d ", i); + } +} + +int idxd_unmask_msix_vector(struct idxd_device *idxd, int vec_id) +{ + struct pci_dev *pdev = idxd->pdev; + int msixcnt = pci_msix_vec_count(pdev); + union msix_perm perm; + u32 offset; + + if (vec_id < 0 || vec_id >= msixcnt) + return -einval; + + offset = idxd->msix_perm_offset + vec_id * 8; + perm.bits = ioread32(idxd->reg_base + offset); + perm.ignore = 0; + iowrite32(perm.bits, idxd->reg_base + offset); + + return 0; +} + +void idxd_unmask_error_interrupts(struct idxd_device *idxd) +{ + union genctrl_reg genctrl; + + genctrl.bits = ioread32(idxd->reg_base + idxd_genctrl_offset); + genctrl.softerr_int_en = 1; + iowrite32(genctrl.bits, idxd->reg_base + idxd_genctrl_offset); +} + +void idxd_mask_error_interrupts(struct idxd_device *idxd) +{ + union genctrl_reg genctrl; + + genctrl.bits = ioread32(idxd->reg_base + idxd_genctrl_offset); + genctrl.softerr_int_en = 0; + iowrite32(genctrl.bits, idxd->reg_base + idxd_genctrl_offset); +} + +static void free_hw_descs(struct idxd_wq *wq) +{ + int i; + + for (i = 0; i < wq->num_descs; i++) + kfree(wq->hw_descs[i]); + + kfree(wq->hw_descs); +} + +static int alloc_hw_descs(struct idxd_wq *wq, int num) +{ + struct device *dev = &wq->idxd->pdev->dev; + int i; + int node = dev_to_node(dev); + + wq->hw_descs = kcalloc_node(num, sizeof(struct dsa_hw_desc *), + gfp_kernel, node); + if (!wq->hw_descs) + return -enomem; + + for (i = 0; i < num; i++) { + wq->hw_descs[i] = kzalloc_node(sizeof(*wq->hw_descs[i]), + gfp_kernel, node); + if (!wq->hw_descs[i]) { + free_hw_descs(wq); + return -enomem; + } + } + + return 0; +} + +static void free_descs(struct idxd_wq *wq) +{ + int i; + + for (i = 0; i < wq->num_descs; i++) + kfree(wq->descs[i]); + + kfree(wq->descs); +} + +static int alloc_descs(struct idxd_wq *wq, int num) +{ + struct device *dev = &wq->idxd->pdev->dev; + int i; + int node = dev_to_node(dev); + + wq->descs = kcalloc_node(num, sizeof(struct idxd_desc *), + gfp_kernel, node); + if (!wq->descs) + return -enomem; + + for (i = 0; i < num; i++) { + wq->descs[i] = kzalloc_node(sizeof(*wq->descs[i]), + gfp_kernel, node); + if (!wq->descs[i]) { + free_descs(wq); + return -enomem; + } + } + + return 0; +} + +/* wq control bits */ +int idxd_wq_alloc_resources(struct idxd_wq *wq) +{ + struct idxd_device *idxd = wq->idxd; + struct idxd_group *group = wq->group; + struct device *dev = &idxd->pdev->dev; + int rc, num_descs, i; + + num_descs = wq->size + + idxd->hw.gen_cap.max_descs_per_engine * group->num_engines; + wq->num_descs = num_descs; + + rc = alloc_hw_descs(wq, num_descs); + if (rc < 0) + return rc; + + wq->compls_size = num_descs * sizeof(struct dsa_completion_record); + wq->compls = dma_alloc_coherent(dev, wq->compls_size, + &wq->compls_addr, gfp_kernel); + if (!wq->compls) { + rc = -enomem; + goto fail_alloc_compls; + } + + rc = alloc_descs(wq, num_descs); + if (rc < 0) + goto fail_alloc_descs; + + rc = sbitmap_init_node(&wq->sbmap, num_descs, -1, gfp_kernel, + dev_to_node(dev)); + if (rc < 0) + goto fail_sbitmap_init; + + for (i = 0; i < num_descs; i++) { + struct idxd_desc *desc = wq->descs[i]; + + desc->hw = wq->hw_descs[i]; + desc->completion = &wq->compls[i]; + desc->compl_dma = wq->compls_addr + + sizeof(struct dsa_completion_record) * i; + desc->id = i; + desc->wq = wq; + } + + return 0; + + fail_sbitmap_init: + free_descs(wq); + fail_alloc_descs: + dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr); + fail_alloc_compls: + free_hw_descs(wq); + return rc; +} + +void idxd_wq_free_resources(struct idxd_wq *wq) +{ + struct device *dev = &wq->idxd->pdev->dev; + + free_hw_descs(wq); + free_descs(wq); + dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr); + sbitmap_free(&wq->sbmap); +} + +int idxd_wq_enable(struct idxd_wq *wq) +{ + struct idxd_device *idxd = wq->idxd; + struct device *dev = &idxd->pdev->dev; + u32 status; + int rc; + + lockdep_assert_held(&idxd->dev_lock); + + if (wq->state == idxd_wq_enabled) { + dev_dbg(dev, "wq %d already enabled ", wq->id); + return -enxio; + } + + rc = idxd_cmd_send(idxd, idxd_cmd_enable_wq, wq->id); + if (rc < 0) + return rc; + rc = idxd_cmd_wait(idxd, &status, idxd_reg_timeout); + if (rc < 0) + return rc; + + if (status != idxd_cmdsts_success && + status != idxd_cmdsts_err_wq_enabled) { + dev_dbg(dev, "wq enable failed: %#x ", status); + return -enxio; + } + + wq->state = idxd_wq_enabled; + dev_dbg(dev, "wq %d enabled ", wq->id); + return 0; +} + +int idxd_wq_disable(struct idxd_wq *wq) +{ + struct idxd_device *idxd = wq->idxd; + struct device *dev = &idxd->pdev->dev; + u32 status, operand; + int rc; + + lockdep_assert_held(&idxd->dev_lock); + dev_dbg(dev, "disabling wq %d ", wq->id); + + if (wq->state != idxd_wq_enabled) { + dev_dbg(dev, "wq %d in wrong state: %d ", wq->id, wq->state); + return 0; + } + + operand = bit(wq->id % 16) | ((wq->id / 16) << 16); + rc = idxd_cmd_send(idxd, idxd_cmd_disable_wq, operand); + if (rc < 0) + return rc; + rc = idxd_cmd_wait(idxd, &status, idxd_reg_timeout); + if (rc < 0) + return rc; + + if (status != idxd_cmdsts_success) { + dev_dbg(dev, "wq disable failed: %#x ", status); + return -enxio; + } + + wq->state = idxd_wq_disabled; + dev_dbg(dev, "wq %d disabled ", wq->id); + return 0; +} + +/* device control bits */ +static inline bool idxd_is_enabled(struct idxd_device *idxd) +{ + union gensts_reg gensts; + + gensts.bits = ioread32(idxd->reg_base + idxd_genstats_offset); + + if (gensts.state == idxd_device_state_enabled) + return true; + return false; +} + +static int idxd_cmd_wait(struct idxd_device *idxd, u32 *status, int timeout) +{ + u32 sts, to = timeout; + + lockdep_assert_held(&idxd->dev_lock); + sts = ioread32(idxd->reg_base + idxd_cmdsts_offset); + while (sts & idxd_cmdsts_active && --to) { + cpu_relax(); + sts = ioread32(idxd->reg_base + idxd_cmdsts_offset); + } + + if (to == 0 && sts & idxd_cmdsts_active) { + dev_warn(&idxd->pdev->dev, "%s timed out! ", __func__); + *status = 0; + return -ebusy; + } + + *status = sts; + return 0; +} + +static int idxd_cmd_send(struct idxd_device *idxd, int cmd_code, u32 operand) +{ + union idxd_command_reg cmd; + int rc; + u32 status; + + lockdep_assert_held(&idxd->dev_lock); + rc = idxd_cmd_wait(idxd, &status, idxd_reg_timeout); + if (rc < 0) + return rc; + + memset(&cmd, 0, sizeof(cmd)); + cmd.cmd = cmd_code; + cmd.operand = operand; + dev_dbg(&idxd->pdev->dev, "%s: sending cmd: %#x op: %#x ", + __func__, cmd_code, operand); + iowrite32(cmd.bits, idxd->reg_base + idxd_cmd_offset); + + return 0; +} + +int idxd_device_enable(struct idxd_device *idxd) +{ + struct device *dev = &idxd->pdev->dev; + int rc; + u32 status; + + lockdep_assert_held(&idxd->dev_lock); + if (idxd_is_enabled(idxd)) { + dev_dbg(dev, "device already enabled "); + return -enxio; + } + + rc = idxd_cmd_send(idxd, idxd_cmd_enable_device, 0); + if (rc < 0) + return rc; + rc = idxd_cmd_wait(idxd, &status, idxd_reg_timeout); + if (rc < 0) + return rc; + + /* if the command is successful or if the device was enabled */ + if (status != idxd_cmdsts_success && + status != idxd_cmdsts_err_dev_enabled) { + dev_dbg(dev, "%s: err_code: %#x ", __func__, status); + return -enxio; + } + + idxd->state = idxd_dev_enabled; + return 0; +} + +int idxd_device_disable(struct idxd_device *idxd) +{ + struct device *dev = &idxd->pdev->dev; + int rc; + u32 status; + + lockdep_assert_held(&idxd->dev_lock); + if (!idxd_is_enabled(idxd)) { + dev_dbg(dev, "device is not enabled "); + return 0; + } + + rc = idxd_cmd_send(idxd, idxd_cmd_disable_device, 0); + if (rc < 0) + return rc; + rc = idxd_cmd_wait(idxd, &status, idxd_reg_timeout); + if (rc < 0) + return rc; + + /* if the command is successful or if the device was disabled */ + if (status != idxd_cmdsts_success && + !(status & idxd_cmdsts_err_dis_dev_en)) { + dev_dbg(dev, "%s: err_code: %#x ", __func__, status); + rc = -enxio; + return rc; + } + + idxd->state = idxd_dev_conf_ready; + return 0; +} + +int __idxd_device_reset(struct idxd_device *idxd) +{ + u32 status; + int rc; + + rc = idxd_cmd_send(idxd, idxd_cmd_reset_device, 0); + if (rc < 0) + return rc; + rc = idxd_cmd_wait(idxd, &status, idxd_reg_timeout); + if (rc < 0) + return rc; + + return 0; +} + +int idxd_device_reset(struct idxd_device *idxd) +{ + unsigned long flags; + int rc; + + spin_lock_irqsave(&idxd->dev_lock, flags); + rc = __idxd_device_reset(idxd); + spin_unlock_irqrestore(&idxd->dev_lock, flags); + return rc; +} + +/* device configuration bits */ +static void idxd_group_config_write(struct idxd_group *group) +{ + struct idxd_device *idxd = group->idxd; + struct device *dev = &idxd->pdev->dev; + int i; + u32 grpcfg_offset; + + dev_dbg(dev, "writing group %d cfg registers ", group->id); + + /* setup grpwqcfg */ + for (i = 0; i < 4; i++) { + grpcfg_offset = idxd->grpcfg_offset + + group->id * 64 + i * sizeof(u64); + iowrite64(group->grpcfg.wqs[i], + idxd->reg_base + grpcfg_offset); + dev_dbg(dev, "grpcfg wq[%d:%d: %#x]: %#llx ", + group->id, i, grpcfg_offset, + ioread64(idxd->reg_base + grpcfg_offset)); + } + + /* setup grpengcfg */ + grpcfg_offset = idxd->grpcfg_offset + group->id * 64 + 32; + iowrite64(group->grpcfg.engines, idxd->reg_base + grpcfg_offset); + dev_dbg(dev, "grpcfg engs[%d: %#x]: %#llx ", group->id, + grpcfg_offset, ioread64(idxd->reg_base + grpcfg_offset)); + + /* setup grpflags */ + grpcfg_offset = idxd->grpcfg_offset + group->id * 64 + 40; + iowrite32(group->grpcfg.flags.bits, idxd->reg_base + grpcfg_offset); + dev_dbg(dev, "grpflags flags[%d: %#x]: %#x ", + group->id, grpcfg_offset, + ioread32(idxd->reg_base + grpcfg_offset)); +} + +static int idxd_groups_config_write(struct idxd_device *idxd) + +{ + union gencfg_reg reg; + int i; + struct device *dev = &idxd->pdev->dev; + + /* setup bandwidth token limit */ + if (idxd->token_limit) { + reg.bits = ioread32(idxd->reg_base + idxd_gencfg_offset); + reg.token_limit = idxd->token_limit; + iowrite32(reg.bits, idxd->reg_base + idxd_gencfg_offset); + } + + dev_dbg(dev, "gencfg(%#x): %#x ", idxd_gencfg_offset, + ioread32(idxd->reg_base + idxd_gencfg_offset)); + + for (i = 0; i < idxd->max_groups; i++) { + struct idxd_group *group = &idxd->groups[i]; + + idxd_group_config_write(group); + } + + return 0; +} + +static int idxd_wq_config_write(struct idxd_wq *wq) +{ + struct idxd_device *idxd = wq->idxd; + struct device *dev = &idxd->pdev->dev; + u32 wq_offset; + int i; + + if (!wq->group) + return 0; + + memset(&wq->wqcfg, 0, sizeof(union wqcfg)); + + /* byte 0-3 */ + wq->wqcfg.wq_size = wq->size; + + if (wq->size == 0) { + dev_warn(dev, "incorrect work queue size: 0 "); + return -einval; + } + + /* bytes 4-7 */ + wq->wqcfg.wq_thresh = wq->threshold; + + /* byte 8-11 */ + wq->wqcfg.priv = 1; /* kernel, therefore priv */ + wq->wqcfg.mode = 1; + + wq->wqcfg.priority = wq->priority; + + /* bytes 12-15 */ + wq->wqcfg.max_xfer_shift = idxd->hw.gen_cap.max_xfer_shift; + wq->wqcfg.max_batch_shift = idxd->hw.gen_cap.max_batch_shift; + + dev_dbg(dev, "wq %d cfgs ", wq->id); + for (i = 0; i < 8; i++) { + wq_offset = idxd->wqcfg_offset + wq->id * 32 + i * sizeof(u32); + iowrite32(wq->wqcfg.bits[i], idxd->reg_base + wq_offset); + dev_dbg(dev, "wq[%d][%d][%#x]: %#x ", + wq->id, i, wq_offset, + ioread32(idxd->reg_base + wq_offset)); + } + + return 0; +} + +static int idxd_wqs_config_write(struct idxd_device *idxd) +{ + int i, rc; + + for (i = 0; i < idxd->max_wqs; i++) { + struct idxd_wq *wq = &idxd->wqs[i]; + + rc = idxd_wq_config_write(wq); + if (rc < 0) + return rc; + } + + return 0; +} + +static void idxd_group_flags_setup(struct idxd_device *idxd) +{ + int i; + + /* tc-a 0 and tc-b 1 should be defaults */ + for (i = 0; i < idxd->max_groups; i++) { + struct idxd_group *group = &idxd->groups[i]; + + if (group->tc_a == -1) + group->grpcfg.flags.tc_a = 0; + else + group->grpcfg.flags.tc_a = group->tc_a; + if (group->tc_b == -1) + group->grpcfg.flags.tc_b = 1; + else + group->grpcfg.flags.tc_b = group->tc_b; + group->grpcfg.flags.use_token_limit = group->use_token_limit; + group->grpcfg.flags.tokens_reserved = group->tokens_reserved; + if (group->tokens_allowed) + group->grpcfg.flags.tokens_allowed = + group->tokens_allowed; + else + group->grpcfg.flags.tokens_allowed = idxd->max_tokens; + } +} + +static int idxd_engines_setup(struct idxd_device *idxd) +{ + int i, engines = 0; + struct idxd_engine *eng; + struct idxd_group *group; + + for (i = 0; i < idxd->max_groups; i++) { + group = &idxd->groups[i]; + group->grpcfg.engines = 0; + } + + for (i = 0; i < idxd->max_engines; i++) { + eng = &idxd->engines[i]; + group = eng->group; + + if (!group) + continue; + + group->grpcfg.engines |= bit(eng->id); + engines++; + } + + if (!engines) + return -einval; + + return 0; +} + +static int idxd_wqs_setup(struct idxd_device *idxd) +{ + struct idxd_wq *wq; + struct idxd_group *group; + int i, j, configured = 0; + struct device *dev = &idxd->pdev->dev; + + for (i = 0; i < idxd->max_groups; i++) { + group = &idxd->groups[i]; + for (j = 0; j < 4; j++) + group->grpcfg.wqs[j] = 0; + } + + for (i = 0; i < idxd->max_wqs; i++) { + wq = &idxd->wqs[i]; + group = wq->group; + + if (!wq->group) + continue; + if (!wq->size) + continue; + + if (!wq_dedicated(wq)) { + dev_warn(dev, "no shared workqueue support. "); + return -einval; + } + + group->grpcfg.wqs[wq->id / 64] |= bit(wq->id % 64); + configured++; + } + + if (configured == 0) + return -einval; + + return 0; +} + +int idxd_device_config(struct idxd_device *idxd) +{ + int rc; + + lockdep_assert_held(&idxd->dev_lock); + rc = idxd_wqs_setup(idxd); + if (rc < 0) + return rc; + + rc = idxd_engines_setup(idxd); + if (rc < 0) + return rc; + + idxd_group_flags_setup(idxd); + + rc = idxd_wqs_config_write(idxd); + if (rc < 0) + return rc; + + rc = idxd_groups_config_write(idxd); + if (rc < 0) + return rc; + + return 0; +} diff --git a/drivers/dma/idxd/idxd.h b/drivers/dma/idxd/idxd.h --- /dev/null +++ b/drivers/dma/idxd/idxd.h +/* spdx-license-identifier: gpl-2.0 */ +/* copyright(c) 2019 intel corporation. all rights rsvd. */ +#ifndef _idxd_h_ +#define _idxd_h_ + +#include <linux/sbitmap.h> +#include <linux/percpu-rwsem.h> +#include <linux/wait.h> +#include "registers.h" + +#define idxd_driver_version "1.00" + +extern struct kmem_cache *idxd_desc_pool; + +#define idxd_reg_timeout 50 +#define idxd_drain_timeout 5000 + +enum idxd_type { + idxd_type_unknown = -1, + idxd_type_dsa = 0, + idxd_type_max +}; + +#define idxd_name_size 128 + +struct idxd_device_driver { + struct device_driver drv; +}; + +struct idxd_irq_entry { + struct idxd_device *idxd; + int id; + struct llist_head pending_llist; + struct list_head work_list; +}; + +struct idxd_group { + struct device conf_dev; + struct idxd_device *idxd; + struct grpcfg grpcfg; + int id; + int num_engines; + int num_wqs; + bool use_token_limit; + u8 tokens_allowed; + u8 tokens_reserved; + int tc_a; + int tc_b; +}; + +#define idxd_max_priority 0xf + +enum idxd_wq_state { + idxd_wq_disabled = 0, + idxd_wq_enabled, +}; + +enum idxd_wq_flag { + wq_flag_dedicated = 0, +}; + +enum idxd_wq_type { + idxd_wqt_none = 0, + idxd_wqt_kernel, +}; + +#define idxd_allocated_batch_size 128u +#define wq_name_size 1024 +#define wq_type_size 10 + +struct idxd_wq { + void __iomem *dportal; + struct device conf_dev; + struct idxd_device *idxd; + int id; + enum idxd_wq_type type; + struct idxd_group *group; + int client_count; + struct mutex wq_lock; /* mutex for workqueue */ + u32 size; + u32 threshold; + u32 priority; + enum idxd_wq_state state; + unsigned long flags; + union wqcfg wqcfg; + atomic_t dq_count; /* dedicated queue flow control */ + u32 vec_ptr; /* interrupt steering */ + struct dsa_hw_desc **hw_descs; + int num_descs; + struct dsa_completion_record *compls; + dma_addr_t compls_addr; + int compls_size; + struct idxd_desc **descs; + struct sbitmap sbmap; + struct percpu_rw_semaphore submit_lock; + wait_queue_head_t submit_waitq; + char name[wq_name_size + 1]; +}; + +struct idxd_engine { + struct device conf_dev; + int id; + struct idxd_group *group; + struct idxd_device *idxd; +}; + +/* shadow registers */ +struct idxd_hw { + u32 version; + union gen_cap_reg gen_cap; + union wq_cap_reg wq_cap; + union group_cap_reg group_cap; + union engine_cap_reg engine_cap; + struct opcap opcap; +}; + +enum idxd_device_state { + idxd_dev_halted = -1, + idxd_dev_disabled = 0, + idxd_dev_conf_ready, + idxd_dev_enabled, +}; + +enum idxd_device_flag { + idxd_flag_configurable = 0, +}; + +struct idxd_device { + enum idxd_type type; + struct device conf_dev; + struct list_head list; + struct idxd_hw hw; + enum idxd_device_state state; + unsigned long flags; + int id; + + struct pci_dev *pdev; + void __iomem *reg_base; + + spinlock_t dev_lock; /* spinlock for device */ + struct idxd_group *groups; + struct idxd_wq *wqs; + struct idxd_engine *engines; + + int num_groups; + + u32 msix_perm_offset; + u32 wqcfg_offset; + u32 grpcfg_offset; + u32 perfmon_offset; + + u64 max_xfer_bytes; + u32 max_batch_size; + int max_groups; + int max_engines; + int max_tokens; + int max_wqs; + int max_wq_size; + int token_limit; + + union sw_err_reg sw_err; + + struct msix_entry *msix_entries; + int num_wq_irqs; + struct idxd_irq_entry *irq_entries; +}; + +/* idxd software descriptor */ +struct idxd_desc { + struct dsa_hw_desc *hw; + dma_addr_t desc_dma; + struct dsa_completion_record *completion; + dma_addr_t compl_dma; + struct llist_node llnode; + struct list_head list; + int id; + struct idxd_wq *wq; +}; + +#define confdev_to_idxd(dev) container_of(dev, struct idxd_device, conf_dev) +#define confdev_to_wq(dev) container_of(dev, struct idxd_wq, conf_dev) + +static inline bool wq_dedicated(struct idxd_wq *wq) +{ + return test_bit(wq_flag_dedicated, &wq->flags); +} + +static inline void idxd_set_type(struct idxd_device *idxd) +{ + struct pci_dev *pdev = idxd->pdev; + + if (pdev->device == pci_device_id_intel_dsa_spr0) + idxd->type = idxd_type_dsa; + else + idxd->type = idxd_type_unknown; +} + +const char *idxd_get_dev_name(struct idxd_device *idxd); + +/* device interrupt control */ +irqreturn_t idxd_irq_handler(int vec, void *data); +irqreturn_t idxd_misc_thread(int vec, void *data); +irqreturn_t idxd_wq_thread(int irq, void *data); +void idxd_mask_error_interrupts(struct idxd_device *idxd); +void idxd_unmask_error_interrupts(struct idxd_device *idxd); +void idxd_mask_msix_vectors(struct idxd_device *idxd); +int idxd_mask_msix_vector(struct idxd_device *idxd, int vec_id); +int idxd_unmask_msix_vector(struct idxd_device *idxd, int vec_id); + +/* device control */ +int idxd_device_enable(struct idxd_device *idxd); +int idxd_device_disable(struct idxd_device *idxd); +int idxd_device_reset(struct idxd_device *idxd); +int __idxd_device_reset(struct idxd_device *idxd); +void idxd_device_cleanup(struct idxd_device *idxd); +int idxd_device_config(struct idxd_device *idxd); +void idxd_device_wqs_clear_state(struct idxd_device *idxd); + +/* work queue control */ +int idxd_wq_alloc_resources(struct idxd_wq *wq); +void idxd_wq_free_resources(struct idxd_wq *wq); +int idxd_wq_enable(struct idxd_wq *wq); +int idxd_wq_disable(struct idxd_wq *wq); + +#endif diff --git a/drivers/dma/idxd/init.c b/drivers/dma/idxd/init.c --- /dev/null +++ b/drivers/dma/idxd/init.c +// spdx-license-identifier: gpl-2.0 +/* copyright(c) 2019 intel corporation. all rights rsvd. */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/pci.h> +#include <linux/interrupt.h> +#include <linux/delay.h> +#include <linux/dma-mapping.h> +#include <linux/workqueue.h> +#include <linux/aer.h> +#include <linux/fs.h> +#include <linux/io-64-nonatomic-lo-hi.h> +#include <linux/device.h> +#include <linux/idr.h> +#include <uapi/linux/idxd.h> +#include "registers.h" +#include "idxd.h" + +module_version(idxd_driver_version); +module_license("gpl v2"); +module_author("intel corporation"); + +#define drv_name "idxd" + +static struct idr idxd_idrs[idxd_type_max]; +static struct mutex idxd_idr_lock; + +static struct pci_device_id idxd_pci_tbl[] = { + /* dsa ver 1.0 platforms */ + { pci_vdevice(intel, pci_device_id_intel_dsa_spr0) }, + { 0, } +}; +module_device_table(pci, idxd_pci_tbl); + +static char *idxd_name[] = { + "dsa", +}; + +const char *idxd_get_dev_name(struct idxd_device *idxd) +{ + return idxd_name[idxd->type]; +} + +static int idxd_setup_interrupts(struct idxd_device *idxd) +{ + struct pci_dev *pdev = idxd->pdev; + struct device *dev = &pdev->dev; + struct msix_entry *msix; + struct idxd_irq_entry *irq_entry; + int i, msixcnt; + int rc = 0; + + msixcnt = pci_msix_vec_count(pdev); + if (msixcnt < 0) { + dev_err(dev, "not msi-x interrupt capable. "); + goto err_no_irq; + } + + idxd->msix_entries = devm_kzalloc(dev, sizeof(struct msix_entry) * + msixcnt, gfp_kernel); + if (!idxd->msix_entries) { + rc = -enomem; + goto err_no_irq; + } + + for (i = 0; i < msixcnt; i++) + idxd->msix_entries[i].entry = i; + + rc = pci_enable_msix_exact(pdev, idxd->msix_entries, msixcnt); + if (rc) { + dev_err(dev, "failed enabling %d msix entries. ", msixcnt); + goto err_no_irq; + } + dev_dbg(dev, "enabled %d msix vectors ", msixcnt); + + /* + * we implement 1 completion list per msi-x entry except for + * entry 0, which is for errors and others. + */ + idxd->irq_entries = devm_kcalloc(dev, msixcnt, + sizeof(struct idxd_irq_entry), + gfp_kernel); + if (!idxd->irq_entries) { + rc = -enomem; + goto err_no_irq; + } + + for (i = 0; i < msixcnt; i++) { + idxd->irq_entries[i].id = i; + idxd->irq_entries[i].idxd = idxd; + } + + msix = &idxd->msix_entries[0]; + irq_entry = &idxd->irq_entries[0]; + rc = devm_request_threaded_irq(dev, msix->vector, idxd_irq_handler, + idxd_misc_thread, 0, "idxd-misc", + irq_entry); + if (rc < 0) { + dev_err(dev, "failed to allocate misc interrupt. "); + goto err_no_irq; + } + + dev_dbg(dev, "allocated idxd-misc handler on msix vector %d ", + msix->vector); + + /* first msi-x entry is not for wq interrupts */ + idxd->num_wq_irqs = msixcnt - 1; + + for (i = 1; i < msixcnt; i++) { + msix = &idxd->msix_entries[i]; + irq_entry = &idxd->irq_entries[i]; + + init_llist_head(&idxd->irq_entries[i].pending_llist); + init_list_head(&idxd->irq_entries[i].work_list); + rc = devm_request_threaded_irq(dev, msix->vector, + idxd_irq_handler, + idxd_wq_thread, 0, + "idxd-portal", irq_entry); + if (rc < 0) { + dev_err(dev, "failed to allocate irq %d. ", + msix->vector); + goto err_no_irq; + } + dev_dbg(dev, "allocated idxd-msix %d for vector %d ", + i, msix->vector); + } + + idxd_unmask_error_interrupts(idxd); + + return 0; + + err_no_irq: + /* disable error interrupt generation */ + idxd_mask_error_interrupts(idxd); + pci_disable_msix(pdev); + dev_err(dev, "no usable interrupts "); + return rc; +} + +static void idxd_wqs_free_lock(struct idxd_device *idxd) +{ + int i; + + for (i = 0; i < idxd->max_wqs; i++) { + struct idxd_wq *wq = &idxd->wqs[i]; + + percpu_free_rwsem(&wq->submit_lock); + } +} + +static int idxd_setup_internals(struct idxd_device *idxd) +{ + struct device *dev = &idxd->pdev->dev; + int i; + + idxd->groups = devm_kcalloc(dev, idxd->max_groups, + sizeof(struct idxd_group), gfp_kernel); + if (!idxd->groups) + return -enomem; + + for (i = 0; i < idxd->max_groups; i++) { + idxd->groups[i].idxd = idxd; + idxd->groups[i].id = i; + idxd->groups[i].tc_a = -1; + idxd->groups[i].tc_b = -1; + } + + idxd->wqs = devm_kcalloc(dev, idxd->max_wqs, sizeof(struct idxd_wq), + gfp_kernel); + if (!idxd->wqs) + return -enomem; + + idxd->engines = devm_kcalloc(dev, idxd->max_engines, + sizeof(struct idxd_engine), gfp_kernel); + if (!idxd->engines) + return -enomem; + + for (i = 0; i < idxd->max_wqs; i++) { + struct idxd_wq *wq = &idxd->wqs[i]; + int rc; + + wq->id = i; + wq->idxd = idxd; + mutex_init(&wq->wq_lock); + atomic_set(&wq->dq_count, 0); + init_waitqueue_head(&wq->submit_waitq); + rc = percpu_init_rwsem(&wq->submit_lock); + if (rc < 0) { + idxd_wqs_free_lock(idxd); + return rc; + } + } + + for (i = 0; i < idxd->max_engines; i++) { + idxd->engines[i].idxd = idxd; + idxd->engines[i].id = i; + } + + return 0; +} + +static void idxd_read_table_offsets(struct idxd_device *idxd) +{ + union offsets_reg offsets; + struct device *dev = &idxd->pdev->dev; + + offsets.bits[0] = ioread64(idxd->reg_base + idxd_table_offset); + offsets.bits[1] = ioread64(idxd->reg_base + idxd_table_offset + + sizeof(u64)); + idxd->grpcfg_offset = offsets.grpcfg * 0x100; + dev_dbg(dev, "idxd group config offset: %#x ", idxd->grpcfg_offset); + idxd->wqcfg_offset = offsets.wqcfg * 0x100; + dev_dbg(dev, "idxd work queue config offset: %#x ", + idxd->wqcfg_offset); + idxd->msix_perm_offset = offsets.msix_perm * 0x100; + dev_dbg(dev, "idxd msix permission offset: %#x ", + idxd->msix_perm_offset); + idxd->perfmon_offset = offsets.perfmon * 0x100; + dev_dbg(dev, "idxd perfmon offset: %#x ", idxd->perfmon_offset); +} + +static void idxd_read_caps(struct idxd_device *idxd) +{ + struct device *dev = &idxd->pdev->dev; + int i; + + /* reading generic capabilities */ + idxd->hw.gen_cap.bits = ioread64(idxd->reg_base + idxd_gencap_offset); + dev_dbg(dev, "gen_cap: %#llx ", idxd->hw.gen_cap.bits); + idxd->max_xfer_bytes = 1ull << idxd->hw.gen_cap.max_xfer_shift; + dev_dbg(dev, "max xfer size: %llu bytes ", idxd->max_xfer_bytes); + idxd->max_batch_size = 1u << idxd->hw.gen_cap.max_batch_shift; + dev_dbg(dev, "max batch size: %u ", idxd->max_batch_size); + if (idxd->hw.gen_cap.config_en) + set_bit(idxd_flag_configurable, &idxd->flags); + + /* reading group capabilities */ + idxd->hw.group_cap.bits = + ioread64(idxd->reg_base + idxd_grpcap_offset); + dev_dbg(dev, "group_cap: %#llx ", idxd->hw.group_cap.bits); + idxd->max_groups = idxd->hw.group_cap.num_groups; + dev_dbg(dev, "max groups: %u ", idxd->max_groups); + idxd->max_tokens = idxd->hw.group_cap.total_tokens; + dev_dbg(dev, "max tokens: %u ", idxd->max_tokens); + + /* read engine capabilities */ + idxd->hw.engine_cap.bits = + ioread64(idxd->reg_base + idxd_engcap_offset); + dev_dbg(dev, "engine_cap: %#llx ", idxd->hw.engine_cap.bits); + idxd->max_engines = idxd->hw.engine_cap.num_engines; + dev_dbg(dev, "max engines: %u ", idxd->max_engines); + + /* read workqueue capabilities */ + idxd->hw.wq_cap.bits = ioread64(idxd->reg_base + idxd_wqcap_offset); + dev_dbg(dev, "wq_cap: %#llx ", idxd->hw.wq_cap.bits); + idxd->max_wq_size = idxd->hw.wq_cap.total_wq_size; + dev_dbg(dev, "total workqueue size: %u ", idxd->max_wq_size); + idxd->max_wqs = idxd->hw.wq_cap.num_wqs; + dev_dbg(dev, "max workqueues: %u ", idxd->max_wqs); + + /* reading operation capabilities */ + for (i = 0; i < 4; i++) { + idxd->hw.opcap.bits[i] = ioread64(idxd->reg_base + + idxd_opcap_offset + i * sizeof(u64)); + dev_dbg(dev, "opcap[%d]: %#llx ", i, idxd->hw.opcap.bits[i]); + } +} + +static struct idxd_device *idxd_alloc(struct pci_dev *pdev, + void __iomem * const *iomap) +{ + struct device *dev = &pdev->dev; + struct idxd_device *idxd; + + idxd = devm_kzalloc(dev, sizeof(struct idxd_device), gfp_kernel); + if (!idxd) + return null; + + idxd->pdev = pdev; + idxd->reg_base = iomap[idxd_mmio_bar]; + spin_lock_init(&idxd->dev_lock); + + return idxd; +} + +static int idxd_probe(struct idxd_device *idxd) +{ + struct pci_dev *pdev = idxd->pdev; + struct device *dev = &pdev->dev; + int rc; + + dev_dbg(dev, "%s entered and resetting device ", __func__); + rc = idxd_device_reset(idxd); + if (rc < 0) + return rc; + dev_dbg(dev, "idxd reset complete "); + + idxd_read_caps(idxd); + idxd_read_table_offsets(idxd); + + rc = idxd_setup_internals(idxd); + if (rc) + goto err_setup; + + rc = idxd_setup_interrupts(idxd); + if (rc) + goto err_setup; + + dev_dbg(dev, "idxd interrupt setup complete. "); + + mutex_lock(&idxd_idr_lock); + idxd->id = idr_alloc(&idxd_idrs[idxd->type], idxd, 0, 0, gfp_kernel); + mutex_unlock(&idxd_idr_lock); + if (idxd->id < 0) { + rc = -enomem; + goto err_idr_fail; + } + + dev_dbg(dev, "idxd device %d probed successfully ", idxd->id); + return 0; + + err_idr_fail: + idxd_mask_error_interrupts(idxd); + idxd_mask_msix_vectors(idxd); + err_setup: + return rc; +} + +static int idxd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + void __iomem * const *iomap; + struct device *dev = &pdev->dev; + struct idxd_device *idxd; + int rc; + unsigned int mask; + + rc = pcim_enable_device(pdev); + if (rc) + return rc; + + dev_dbg(dev, "mapping bars "); + mask = (1 << idxd_mmio_bar); + rc = pcim_iomap_regions(pdev, mask, drv_name); + if (rc) + return rc; + + iomap = pcim_iomap_table(pdev); + if (!iomap) + return -enomem; + + dev_dbg(dev, "set dma masks "); + rc = pci_set_dma_mask(pdev, dma_bit_mask(64)); + if (rc) + rc = pci_set_dma_mask(pdev, dma_bit_mask(32)); + if (rc) + return rc; + + rc = pci_set_consistent_dma_mask(pdev, dma_bit_mask(64)); + if (rc) + rc = pci_set_consistent_dma_mask(pdev, dma_bit_mask(32)); + if (rc) + return rc; + + dev_dbg(dev, "alloc idxd context "); + idxd = idxd_alloc(pdev, iomap); + if (!idxd) + return -enomem; + + idxd_set_type(idxd); + + dev_dbg(dev, "set pci master "); + pci_set_master(pdev); + pci_set_drvdata(pdev, idxd); + + idxd->hw.version = ioread32(idxd->reg_base + idxd_ver_offset); + rc = idxd_probe(idxd); + if (rc) { + dev_err(dev, "intel(r) idxd dma engine init failed "); + return -enodev; + } + + dev_info(&pdev->dev, "intel(r) accelerator device (v%x) ", + idxd->hw.version); + + return 0; +} + +static void idxd_shutdown(struct pci_dev *pdev) +{ + struct idxd_device *idxd = pci_get_drvdata(pdev); + int rc, i; + struct idxd_irq_entry *irq_entry; + int msixcnt = pci_msix_vec_count(pdev); + unsigned long flags; + + spin_lock_irqsave(&idxd->dev_lock, flags); + rc = idxd_device_disable(idxd); + spin_unlock_irqrestore(&idxd->dev_lock, flags); + if (rc) + dev_err(&pdev->dev, "disabling device failed "); + + dev_dbg(&pdev->dev, "%s called ", __func__); + idxd_mask_msix_vectors(idxd); + idxd_mask_error_interrupts(idxd); + + for (i = 0; i < msixcnt; i++) { + irq_entry = &idxd->irq_entries[i]; + synchronize_irq(idxd->msix_entries[i].vector); + if (i == 0) + continue; + } +} + +static void idxd_remove(struct pci_dev *pdev) +{ + struct idxd_device *idxd = pci_get_drvdata(pdev); + + dev_dbg(&pdev->dev, "%s called ", __func__); + idxd_shutdown(pdev); + idxd_wqs_free_lock(idxd); + mutex_lock(&idxd_idr_lock); + idr_remove(&idxd_idrs[idxd->type], idxd->id); + mutex_unlock(&idxd_idr_lock); +} + +static struct pci_driver idxd_pci_driver = { + .name = drv_name, + .id_table = idxd_pci_tbl, + .probe = idxd_pci_probe, + .remove = idxd_remove, + .shutdown = idxd_shutdown, +}; + +static int __init idxd_init_module(void) +{ + int err, i; + + /* + * if the cpu does not support write512, there's no point in + * enumerating the device. we can not utilize it. + */ + if (!boot_cpu_has(x86_feature_movdir64b)) { + pr_warn("idxd driver failed to load without movdir64b. "); + return -enodev; + } + + pr_info("%s: intel(r) accelerator devices driver %s ", + drv_name, idxd_driver_version); + + mutex_init(&idxd_idr_lock); + for (i = 0; i < idxd_type_max; i++) + idr_init(&idxd_idrs[i]); + + err = pci_register_driver(&idxd_pci_driver); + if (err) + return err; + + return 0; +} +module_init(idxd_init_module); + +static void __exit idxd_exit_module(void) +{ + pci_unregister_driver(&idxd_pci_driver); +} +module_exit(idxd_exit_module); diff --git a/drivers/dma/idxd/irq.c b/drivers/dma/idxd/irq.c --- /dev/null +++ b/drivers/dma/idxd/irq.c +// spdx-license-identifier: gpl-2.0 +/* copyright(c) 2019 intel corporation. all rights rsvd. */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/pci.h> +#include <linux/io-64-nonatomic-lo-hi.h> +#include <uapi/linux/idxd.h> +#include "idxd.h" +#include "registers.h" + +void idxd_device_wqs_clear_state(struct idxd_device *idxd) +{ + int i; + + lockdep_assert_held(&idxd->dev_lock); + for (i = 0; i < idxd->max_wqs; i++) { + struct idxd_wq *wq = &idxd->wqs[i]; + + wq->state = idxd_wq_disabled; + } +} + +static int idxd_restart(struct idxd_device *idxd) +{ + int i, rc; + + lockdep_assert_held(&idxd->dev_lock); + + rc = __idxd_device_reset(idxd); + if (rc < 0) + goto out; + + rc = idxd_device_config(idxd); + if (rc < 0) + goto out; + + rc = idxd_device_enable(idxd); + if (rc < 0) + goto out; + + for (i = 0; i < idxd->max_wqs; i++) { + struct idxd_wq *wq = &idxd->wqs[i]; + + if (wq->state == idxd_wq_enabled) { + rc = idxd_wq_enable(wq); + if (rc < 0) { + dev_warn(&idxd->pdev->dev, + "unable to re-enable wq %s ", + dev_name(&wq->conf_dev)); + } + } + } + + return 0; + + out: + idxd_device_wqs_clear_state(idxd); + idxd->state = idxd_dev_halted; + return rc; +} + +irqreturn_t idxd_irq_handler(int vec, void *data) +{ + struct idxd_irq_entry *irq_entry = data; + struct idxd_device *idxd = irq_entry->idxd; + + idxd_mask_msix_vector(idxd, irq_entry->id); + return irq_wake_thread; +} + +irqreturn_t idxd_misc_thread(int vec, void *data) +{ + struct idxd_irq_entry *irq_entry = data; + struct idxd_device *idxd = irq_entry->idxd; + struct device *dev = &idxd->pdev->dev; + union gensts_reg gensts; + u32 cause, val = 0; + int i, rc; + bool err = false; + + cause = ioread32(idxd->reg_base + idxd_intcause_offset); + + if (cause & idxd_intc_err) { + spin_lock_bh(&idxd->dev_lock); + for (i = 0; i < 4; i++) + idxd->sw_err.bits[i] = ioread64(idxd->reg_base + + idxd_swerr_offset + i * sizeof(u64)); + iowrite64(idxd_swerr_ack, idxd->reg_base + idxd_swerr_offset); + spin_unlock_bh(&idxd->dev_lock); + val |= idxd_intc_err; + + for (i = 0; i < 4; i++) + dev_warn(dev, "err[%d]: %#16.16llx ", + i, idxd->sw_err.bits[i]); + err = true; + } + + if (cause & idxd_intc_cmd) { + /* driver does use command interrupts */ + val |= idxd_intc_cmd; + } + + if (cause & idxd_intc_occupy) { + /* driver does not utilize occupancy interrupt */ + val |= idxd_intc_occupy; + } + + if (cause & idxd_intc_perfmon_ovfl) { + /* + * driver does not utilize perfmon counter overflow interrupt + * yet. + */ + val |= idxd_intc_perfmon_ovfl; + } + + val ^= cause; + if (val) + dev_warn_once(dev, "unexpected interrupt cause bits set: %#x ", + val); + + iowrite32(cause, idxd->reg_base + idxd_intcause_offset); + if (!err) + return irq_handled; + + gensts.bits = ioread32(idxd->reg_base + idxd_genstats_offset); + if (gensts.state == idxd_device_state_halt) { + spin_lock_bh(&idxd->dev_lock); + if (gensts.reset_type == idxd_device_reset_software) { + rc = idxd_restart(idxd); + if (rc < 0) + dev_err(&idxd->pdev->dev, + "idxd restart failed, device halt."); + } else { + idxd_device_wqs_clear_state(idxd); + idxd->state = idxd_dev_halted; + dev_err(&idxd->pdev->dev, + "idxd halted, need %s. ", + gensts.reset_type == idxd_device_reset_flr ? + "flr" : "system reset"); + } + spin_unlock_bh(&idxd->dev_lock); + } + + idxd_unmask_msix_vector(idxd, irq_entry->id); + return irq_handled; +} + +irqreturn_t idxd_wq_thread(int irq, void *data) +{ + struct idxd_irq_entry *irq_entry = data; + + idxd_unmask_msix_vector(irq_entry->idxd, irq_entry->id); + + return irq_handled; +} diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h --- /dev/null +++ b/drivers/dma/idxd/registers.h +/* spdx-license-identifier: gpl-2.0 */ +/* copyright(c) 2019 intel corporation. all rights rsvd. */ +#ifndef _idxd_registers_h_ +#define _idxd_registers_h_ + +/* pci config */ +#define pci_device_id_intel_dsa_spr0 0x0b25 + +#define idxd_mmio_bar 0 +#define idxd_wq_bar 2 + +/* mmio device bar0 registers */ +#define idxd_ver_offset 0x00 +#define idxd_ver_major_mask 0xf0 +#define idxd_ver_minor_mask 0x0f +#define get_idxd_ver_major(x) (((x) & idxd_ver_major_mask) >> 4) +#define get_idxd_ver_minor(x) ((x) & idxd_ver_minor_mask) + +union gen_cap_reg { + struct { + u64 block_on_fault:1; + u64 overlap_copy:1; + u64 cache_control_mem:1; + u64 cache_control_cache:1; + u64 rsvd:3; + u64 int_handle_req:1; + u64 dest_readback:1; + u64 drain_readback:1; + u64 rsvd2:6; + u64 max_xfer_shift:5; + u64 max_batch_shift:4; + u64 max_ims_mult:6; + u64 config_en:1; + u64 max_descs_per_engine:8; + u64 rsvd3:24; + }; + u64 bits; +} __packed; +#define idxd_gencap_offset 0x10 + +union wq_cap_reg { + struct { + u64 total_wq_size:16; + u64 num_wqs:8; + u64 rsvd:24; + u64 shared_mode:1; + u64 dedicated_mode:1; + u64 rsvd2:1; + u64 priority:1; + u64 occupancy:1; + u64 occupancy_int:1; + u64 rsvd3:10; + }; + u64 bits; +} __packed; +#define idxd_wqcap_offset 0x20 + +union group_cap_reg { + struct { + u64 num_groups:8; + u64 total_tokens:8; + u64 token_en:1; + u64 token_limit:1; + u64 rsvd:46; + }; + u64 bits; +} __packed; +#define idxd_grpcap_offset 0x30 + +union engine_cap_reg { + struct { + u64 num_engines:8; + u64 rsvd:56; + }; + u64 bits; +} __packed; + +#define idxd_engcap_offset 0x38 + +#define idxd_opcap_noop 0x0001 +#define idxd_opcap_batch 0x0002 +#define idxd_opcap_memmove 0x0008 +struct opcap { + u64 bits[4]; +}; + +#define idxd_opcap_offset 0x40 + +#define idxd_table_offset 0x60 +union offsets_reg { + struct { + u64 grpcfg:16; + u64 wqcfg:16; + u64 msix_perm:16; + u64 ims:16; + u64 perfmon:16; + u64 rsvd:48; + }; + u64 bits[2]; +} __packed; + +#define idxd_gencfg_offset 0x80 +union gencfg_reg { + struct { + u32 token_limit:8; + u32 rsvd:4; + u32 user_int_en:1; + u32 rsvd2:19; + }; + u32 bits; +} __packed; + +#define idxd_genctrl_offset 0x88 +union genctrl_reg { + struct { + u32 softerr_int_en:1; + u32 rsvd:31; + }; + u32 bits; +} __packed; + +#define idxd_genstats_offset 0x90 +union gensts_reg { + struct { + u32 state:2; + u32 reset_type:2; + u32 rsvd:28; + }; + u32 bits; +} __packed; + +enum idxd_device_status_state { + idxd_device_state_disabled = 0, + idxd_device_state_enabled, + idxd_device_state_drain, + idxd_device_state_halt, +}; + +enum idxd_device_reset_type { + idxd_device_reset_software = 0, + idxd_device_reset_flr, + idxd_device_reset_warm, + idxd_device_reset_cold, +}; + +#define idxd_intcause_offset 0x98 +#define idxd_intc_err 0x01 +#define idxd_intc_cmd 0x02 +#define idxd_intc_occupy 0x04 +#define idxd_intc_perfmon_ovfl 0x08 + +#define idxd_cmd_offset 0xa0 +union idxd_command_reg { + struct { + u32 operand:20; + u32 cmd:5; + u32 rsvd:6; + u32 int_req:1; + }; + u32 bits; +} __packed; + +enum idxd_cmd { + idxd_cmd_enable_device = 1, + idxd_cmd_disable_device, + idxd_cmd_drain_all, + idxd_cmd_abort_all, + idxd_cmd_reset_device, + idxd_cmd_enable_wq, + idxd_cmd_disable_wq, + idxd_cmd_drain_wq, + idxd_cmd_abort_wq, + idxd_cmd_reset_wq, + idxd_cmd_drain_pasid, + idxd_cmd_abort_pasid, + idxd_cmd_request_int_handle, +}; + +#define idxd_cmdsts_offset 0xa8 +union cmdsts_reg { + struct { + u8 err; + u16 result; + u8 rsvd:7; + u8 active:1; + }; + u32 bits; +} __packed; +#define idxd_cmdsts_active 0x80000000 + +enum idxd_cmdsts_err { + idxd_cmdsts_success = 0, + idxd_cmdsts_inval_cmd, + idxd_cmdsts_inval_wqidx, + idxd_cmdsts_hw_err, + /* enable device errors */ + idxd_cmdsts_err_dev_enabled = 0x10, + idxd_cmdsts_err_config, + idxd_cmdsts_err_busmaster_en, + idxd_cmdsts_err_pasid_inval, + idxd_cmdsts_err_wq_size_erange, + idxd_cmdsts_err_grp_config, + idxd_cmdsts_err_grp_config2, + idxd_cmdsts_err_grp_config3, + idxd_cmdsts_err_grp_config4, + /* enable wq errors */ + idxd_cmdsts_err_dev_noten = 0x20, + idxd_cmdsts_err_wq_enabled, + idxd_cmdsts_err_wq_size, + idxd_cmdsts_err_wq_prior, + idxd_cmdsts_err_wq_mode, + idxd_cmdsts_err_bof_en, + idxd_cmdsts_err_pasid_en, + idxd_cmdsts_err_max_batch_size, + idxd_cmdsts_err_max_xfer_size, + /* disable device errors */ + idxd_cmdsts_err_dis_dev_en = 0x31, + /* disable wq, drain wq, abort wq, reset wq */ + idxd_cmdsts_err_dev_not_en, + /* request interrupt handle */ + idxd_cmdsts_err_inval_int_idx = 0x41, + idxd_cmdsts_err_no_handle, +}; + +#define idxd_swerr_offset 0xc0 +#define idxd_swerr_valid 0x00000001 +#define idxd_swerr_overflow 0x00000002 +#define idxd_swerr_ack (idxd_swerr_valid | idxd_swerr_overflow) +union sw_err_reg { + struct { + u64 valid:1; + u64 overflow:1; + u64 desc_valid:1; + u64 wq_idx_valid:1; + u64 batch:1; + u64 fault_rw:1; + u64 priv:1; + u64 rsvd:1; + u64 error:8; + u64 wq_idx:8; + u64 rsvd2:8; + u64 operation:8; + u64 pasid:20; + u64 rsvd3:4; + + u64 batch_idx:16; + u64 rsvd4:16; + u64 invalid_flags:32; + + u64 fault_addr; + + u64 rsvd5; + }; + u64 bits[4]; +} __packed; + +union msix_perm { + struct { + u32 rsvd:2; + u32 ignore:1; + u32 pasid_en:1; + u32 rsvd2:8; + u32 pasid:20; + }; + u32 bits; +} __packed; + +union group_flags { + struct { + u32 tc_a:3; + u32 tc_b:3; + u32 rsvd:1; + u32 use_token_limit:1; + u32 tokens_reserved:8; + u32 rsvd2:4; + u32 tokens_allowed:8; + u32 rsvd3:4; + }; + u32 bits; +} __packed; + +struct grpcfg { + u64 wqs[4]; + u64 engines; + union group_flags flags; +} __packed; + +union wqcfg { + struct { + /* bytes 0-3 */ + u16 wq_size; + u16 rsvd; + + /* bytes 4-7 */ + u16 wq_thresh; + u16 rsvd1; + + /* bytes 8-11 */ + u32 mode:1; /* shared or dedicated */ + u32 bof:1; /* block on fault */ + u32 rsvd2:2; + u32 priority:4; + u32 pasid:20; + u32 pasid_en:1; + u32 priv:1; + u32 rsvd3:2; + + /* bytes 12-15 */ + u32 max_xfer_shift:5; + u32 max_batch_shift:4; + u32 rsvd4:23; + + /* bytes 16-19 */ + u16 occupancy_inth; + u16 occupancy_table_sel:1; + u16 rsvd5:15; + + /* bytes 20-23 */ + u16 occupancy_limit; + u16 occupancy_int_en:1; + u16 rsvd6:15; + + /* bytes 24-27 */ + u16 occupancy; + u16 occupancy_int:1; + u16 rsvd7:12; + u16 mode_support:1; + u16 wq_state:2; + + /* bytes 28-31 */ + u32 rsvd8; + }; + u32 bits[8]; +} __packed; +#endif diff --git a/include/uapi/linux/idxd.h b/include/uapi/linux/idxd.h --- /dev/null +++ b/include/uapi/linux/idxd.h +/* spdx-license-identifier: gpl-2.0 with linux-syscall-note */ +/* copyright(c) 2019 intel corporation. all rights rsvd. */ +#ifndef _usr_idxd_h_ +#define _usr_idxd_h_ + +#ifdef __kernel__ +#include <linux/types.h> +#else +#include <stdint.h> +#endif + +/* descriptor flags */ +#define idxd_op_flag_fence 0x0001 +#define idxd_op_flag_bof 0x0002 +#define idxd_op_flag_crav 0x0004 +#define idxd_op_flag_rcr 0x0008 +#define idxd_op_flag_rci 0x0010 +#define idxd_op_flag_crsts 0x0020 +#define idxd_op_flag_cr 0x0080 +#define idxd_op_flag_cc 0x0100 +#define idxd_op_flag_addr1_tcs 0x0200 +#define idxd_op_flag_addr2_tcs 0x0400 +#define idxd_op_flag_addr3_tcs 0x0800 +#define idxd_op_flag_cr_tcs 0x1000 +#define idxd_op_flag_stord 0x2000 +#define idxd_op_flag_drdbk 0x4000 +#define idxd_op_flag_dsts 0x8000 + +/* opcode */ +enum dsa_opcode { + dsa_opcode_noop = 0, + dsa_opcode_batch, + dsa_opcode_drain, + dsa_opcode_memmove, + dsa_opcode_memfill, + dsa_opcode_compare, + dsa_opcode_compval, + dsa_opcode_cr_delta, + dsa_opcode_ap_delta, + dsa_opcode_dualcast, + dsa_opcode_crcgen = 0x10, + dsa_opcode_copy_crc, + dsa_opcode_dif_check, + dsa_opcode_dif_ins, + dsa_opcode_dif_strp, + dsa_opcode_dif_updt, + dsa_opcode_cflush = 0x20, +}; + +/* completion record status */ +enum dsa_completion_status { + dsa_comp_none = 0, + dsa_comp_success, + dsa_comp_success_pred, + dsa_comp_page_fault_nobof, + dsa_comp_page_fault_ir, + dsa_comp_batch_fail, + dsa_comp_batch_page_fault, + dsa_comp_dr_offset_noinc, + dsa_comp_dr_offset_erange, + dsa_comp_dif_err, + dsa_comp_bad_opcode = 0x10, + dsa_comp_invalid_flags, + dsa_comp_nozero_reserve, + dsa_comp_xfer_erange, + dsa_comp_desc_cnt_erange, + dsa_comp_dr_erange, + dsa_comp_overlap_buffers, + dsa_comp_dcast_err, + dsa_comp_desclist_align, + dsa_comp_int_handle_inval, + dsa_comp_cra_xlat, + dsa_comp_cra_align, + dsa_comp_addr_align, + dsa_comp_priv_bad, + dsa_comp_traffic_class_conf, + dsa_comp_pfault_rdba, + dsa_comp_hw_err1, + dsa_comp_hw_err_drb, + dsa_comp_translation_fail, +}; + +#define dsa_comp_status_mask 0x7f +#define dsa_comp_status_write 0x80 + +struct dsa_batch_desc { + uint32_t pasid:20; + uint32_t rsvd:11; + uint32_t priv:1; + uint32_t flags:24; + uint32_t opcode:8; + uint64_t completion_addr; + uint64_t desc_list_addr; + uint64_t rsvd1; + uint32_t desc_count; + uint16_t interrupt_handle; + uint16_t rsvd2; + uint8_t rsvd3[24]; +} __attribute__((packed)); + +struct dsa_hw_desc { + uint32_t pasid:20; + uint32_t rsvd:11; + uint32_t priv:1; + uint32_t flags:24; + uint32_t opcode:8; + uint64_t completion_addr; + union { + uint64_t src_addr; + uint64_t rdback_addr; + uint64_t pattern; + }; + union { + uint64_t dst_addr; + uint64_t rdback_addr2; + uint64_t src2_addr; + uint64_t comp_pattern; + }; + uint32_t xfer_size; + uint16_t int_handle; + uint16_t rsvd1; + union { + uint8_t expected_res; + struct { + uint64_t delta_addr; + uint32_t max_delta_size; + }; + uint32_t delta_rec_size; + uint64_t dest2; + /* crc */ + struct { + uint32_t crc_seed; + uint32_t crc_rsvd; + uint64_t seed_addr; + }; + /* dif check or strip */ + struct { + uint8_t src_dif_flags; + uint8_t dif_chk_res; + uint8_t dif_chk_flags; + uint8_t dif_chk_res2[5]; + uint32_t chk_ref_tag_seed; + uint16_t chk_app_tag_mask; + uint16_t chk_app_tag_seed; + }; + /* dif insert */ + struct { + uint8_t dif_ins_res; + uint8_t dest_dif_flag; + uint8_t dif_ins_flags; + uint8_t dif_ins_res2[13]; + uint32_t ins_ref_tag_seed; + uint16_t ins_app_tag_mask; + uint16_t ins_app_tag_seed; + }; + /* dif update */ + struct { + uint8_t src_upd_flags; + uint8_t upd_dest_flags; + uint8_t dif_upd_flags; + uint8_t dif_upd_res[5]; + uint32_t src_ref_tag_seed; + uint16_t src_app_tag_mask; + uint16_t src_app_tag_seed; + uint32_t dest_ref_tag_seed; + uint16_t dest_app_tag_mask; + uint16_t dest_app_tag_seed; + }; + + uint8_t op_specific[24]; + }; +} __attribute__((packed)); + +struct dsa_raw_desc { + uint64_t field[8]; +} __attribute__((packed)); + +/* + * the status field will be modified by hardware, therefore it should be + * volatile and prevent the compiler from optimize the read. + */ +struct dsa_completion_record { + volatile uint8_t status; + union { + uint8_t result; + uint8_t dif_status; + }; + uint16_t rsvd; + uint32_t bytes_completed; + uint64_t fault_addr; + union { + uint16_t delta_rec_size; + uint16_t crc_val; + + /* dif check & strip */ + struct { + uint32_t dif_chk_ref_tag; + uint16_t dif_chk_app_tag_mask; + uint16_t dif_chk_app_tag; + }; + + /* dif insert */ + struct { + uint64_t dif_ins_res; + uint32_t dif_ins_ref_tag; + uint16_t dif_ins_app_tag_mask; + uint16_t dif_ins_app_tag; + }; + + /* dif update */ + struct { + uint32_t dif_upd_src_ref_tag; + uint16_t dif_upd_src_app_tag_mask; + uint16_t dif_upd_src_app_tag; + uint32_t dif_upd_dest_ref_tag; + uint16_t dif_upd_dest_app_tag_mask; + uint16_t dif_upd_dest_app_tag; + }; + + uint8_t op_specific[16]; + }; +} __attribute__((packed)); + +struct dsa_raw_completion_record { + uint64_t field[4]; +} __attribute__((packed)); + +#endif
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DMA engines
|
bfe1d56091c1a404b3d4ce7e9809d745fc4453bb
|
dave jiang
|
include
|
uapi
|
idxd, linux
|
dmaengine: idxd: add configuration component of driver
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the device is left unconfigured when the driver is loaded. various components are configured via the driver sysfs attributes. once configuration is done, the device can be enabled by writing the device name to the bind attribute of the device driver sysfs. disabling can be done similarly. also the individual work queues can also be enabled and disabled through the bind/unbind attributes. a constructed hierarchy is created through the struct device framework in order to provide appropriate configuration points and device state and status. this hierarchy is presented off the virtual dsa bus.
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this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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idxd driver for intel data streaming accelerator
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
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[]
|
['c', 'makefile', 'h']
| 6
| 1,536
| 3
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--- diff --git a/drivers/dma/idxd/makefile b/drivers/dma/idxd/makefile --- a/drivers/dma/idxd/makefile +++ b/drivers/dma/idxd/makefile -idxd-y := init.o irq.o device.o +idxd-y := init.o irq.o device.o sysfs.o diff --git a/drivers/dma/idxd/device.c b/drivers/dma/idxd/device.c --- a/drivers/dma/idxd/device.c +++ b/drivers/dma/idxd/device.c + if (wq->type != idxd_wqt_kernel) + return 0; + + if (wq->type != idxd_wqt_kernel) + return; + +int idxd_wq_map_portal(struct idxd_wq *wq) +{ + struct idxd_device *idxd = wq->idxd; + struct pci_dev *pdev = idxd->pdev; + struct device *dev = &pdev->dev; + resource_size_t start; + + start = pci_resource_start(pdev, idxd_wq_bar); + start = start + wq->id * idxd_portal_size; + + wq->dportal = devm_ioremap(dev, start, idxd_portal_size); + if (!wq->dportal) + return -enomem; + dev_dbg(dev, "wq %d portal mapped at %p ", wq->id, wq->dportal); + + return 0; +} + +void idxd_wq_unmap_portal(struct idxd_wq *wq) +{ + struct device *dev = &wq->idxd->pdev->dev; + + devm_iounmap(dev, wq->dportal); +} + diff --git a/drivers/dma/idxd/idxd.h b/drivers/dma/idxd/idxd.h --- a/drivers/dma/idxd/idxd.h +++ b/drivers/dma/idxd/idxd.h + int nr_tokens; /* non-reserved tokens */ +static inline void idxd_wq_get(struct idxd_wq *wq) +{ + wq->client_count++; +} + +static inline void idxd_wq_put(struct idxd_wq *wq) +{ + wq->client_count--; +} + +static inline int idxd_wq_refcount(struct idxd_wq *wq) +{ + return wq->client_count; +}; + +int idxd_register_bus_type(void); +void idxd_unregister_bus_type(void); +int idxd_setup_sysfs(struct idxd_device *idxd); +void idxd_cleanup_sysfs(struct idxd_device *idxd); +int idxd_register_driver(void); +void idxd_unregister_driver(void); +int idxd_wq_map_portal(struct idxd_wq *wq); +void idxd_wq_unmap_portal(struct idxd_wq *wq); diff --git a/drivers/dma/idxd/init.c b/drivers/dma/idxd/init.c --- a/drivers/dma/idxd/init.c +++ b/drivers/dma/idxd/init.c + idxd->nr_tokens = idxd->max_tokens; + rc = idxd_setup_sysfs(idxd); + if (rc) { + dev_err(dev, "idxd sysfs setup failed "); + return -enodev; + } + + idxd->state = idxd_dev_conf_ready; + + idxd_cleanup_sysfs(idxd); + err = idxd_register_bus_type(); + if (err < 0) + return err; + + err = idxd_register_driver(); + if (err < 0) + goto err_idxd_driver_register; + - return err; + goto err_pci_register; + +err_pci_register: + idxd_unregister_driver(); +err_idxd_driver_register: + idxd_unregister_bus_type(); + return err; + idxd_unregister_bus_type(); diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h --- a/drivers/dma/idxd/registers.h +++ b/drivers/dma/idxd/registers.h +#define idxd_portal_size 0x4000 -#define idxd_swerr_valid 0x00000001 +#define idxd_swerr_valid 0x00000001 diff --git a/drivers/dma/idxd/sysfs.c b/drivers/dma/idxd/sysfs.c --- /dev/null +++ b/drivers/dma/idxd/sysfs.c +// spdx-license-identifier: gpl-2.0 +/* copyright(c) 2019 intel corporation. all rights rsvd. */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/pci.h> +#include <linux/device.h> +#include <linux/io-64-nonatomic-lo-hi.h> +#include <uapi/linux/idxd.h> +#include "registers.h" +#include "idxd.h" + +static char *idxd_wq_type_names[] = { + [idxd_wqt_none] = "none", + [idxd_wqt_kernel] = "kernel", +}; + +static void idxd_conf_device_release(struct device *dev) +{ + dev_dbg(dev, "%s for %s ", __func__, dev_name(dev)); +} + +static struct device_type idxd_group_device_type = { + .name = "group", + .release = idxd_conf_device_release, +}; + +static struct device_type idxd_wq_device_type = { + .name = "wq", + .release = idxd_conf_device_release, +}; + +static struct device_type idxd_engine_device_type = { + .name = "engine", + .release = idxd_conf_device_release, +}; + +static struct device_type dsa_device_type = { + .name = "dsa", + .release = idxd_conf_device_release, +}; + +static inline bool is_dsa_dev(struct device *dev) +{ + return dev ? dev->type == &dsa_device_type : false; +} + +static inline bool is_idxd_dev(struct device *dev) +{ + return is_dsa_dev(dev); +} + +static inline bool is_idxd_wq_dev(struct device *dev) +{ + return dev ? dev->type == &idxd_wq_device_type : false; +} + +static int idxd_config_bus_match(struct device *dev, + struct device_driver *drv) +{ + int matched = 0; + + if (is_idxd_dev(dev)) { + struct idxd_device *idxd = confdev_to_idxd(dev); + + if (idxd->state != idxd_dev_conf_ready) + return 0; + matched = 1; + } else if (is_idxd_wq_dev(dev)) { + struct idxd_wq *wq = confdev_to_wq(dev); + struct idxd_device *idxd = wq->idxd; + + if (idxd->state < idxd_dev_conf_ready) + return 0; + + if (wq->state != idxd_wq_disabled) { + dev_dbg(dev, "%s not disabled ", dev_name(dev)); + return 0; + } + matched = 1; + } + + if (matched) + dev_dbg(dev, "%s matched ", dev_name(dev)); + + return matched; +} + +static int idxd_config_bus_probe(struct device *dev) +{ + int rc; + unsigned long flags; + + dev_dbg(dev, "%s called ", __func__); + + if (is_idxd_dev(dev)) { + struct idxd_device *idxd = confdev_to_idxd(dev); + + if (idxd->state != idxd_dev_conf_ready) { + dev_warn(dev, "device not ready for config "); + return -ebusy; + } + + spin_lock_irqsave(&idxd->dev_lock, flags); + + /* perform idxd configuration and enabling */ + rc = idxd_device_config(idxd); + if (rc < 0) { + spin_unlock_irqrestore(&idxd->dev_lock, flags); + dev_warn(dev, "device config failed: %d ", rc); + return rc; + } + + /* start device */ + rc = idxd_device_enable(idxd); + if (rc < 0) { + spin_unlock_irqrestore(&idxd->dev_lock, flags); + dev_warn(dev, "device enable failed: %d ", rc); + return rc; + } + + spin_unlock_irqrestore(&idxd->dev_lock, flags); + dev_info(dev, "device %s enabled ", dev_name(dev)); + + return 0; + } else if (is_idxd_wq_dev(dev)) { + struct idxd_wq *wq = confdev_to_wq(dev); + struct idxd_device *idxd = wq->idxd; + + mutex_lock(&wq->wq_lock); + + if (idxd->state != idxd_dev_enabled) { + mutex_unlock(&wq->wq_lock); + dev_warn(dev, "enabling while device not enabled. "); + return -eperm; + } + + if (wq->state != idxd_wq_disabled) { + mutex_unlock(&wq->wq_lock); + dev_warn(dev, "wq %d already enabled. ", wq->id); + return -ebusy; + } + + if (!wq->group) { + mutex_unlock(&wq->wq_lock); + dev_warn(dev, "wq not attached to group. "); + return -einval; + } + + if (strlen(wq->name) == 0) { + mutex_unlock(&wq->wq_lock); + dev_warn(dev, "wq name not set. "); + return -einval; + } + + rc = idxd_wq_alloc_resources(wq); + if (rc < 0) { + mutex_unlock(&wq->wq_lock); + dev_warn(dev, "wq resource alloc failed "); + return rc; + } + + spin_lock_irqsave(&idxd->dev_lock, flags); + rc = idxd_device_config(idxd); + if (rc < 0) { + spin_unlock_irqrestore(&idxd->dev_lock, flags); + mutex_unlock(&wq->wq_lock); + dev_warn(dev, "writing wq %d config failed: %d ", + wq->id, rc); + return rc; + } + + rc = idxd_wq_enable(wq); + if (rc < 0) { + spin_unlock_irqrestore(&idxd->dev_lock, flags); + mutex_unlock(&wq->wq_lock); + dev_warn(dev, "wq %d enabling failed: %d ", + wq->id, rc); + return rc; + } + spin_unlock_irqrestore(&idxd->dev_lock, flags); + + rc = idxd_wq_map_portal(wq); + if (rc < 0) { + dev_warn(dev, "wq portal mapping failed: %d ", rc); + rc = idxd_wq_disable(wq); + if (rc < 0) + dev_warn(dev, "idxd wq disable failed "); + spin_unlock_irqrestore(&idxd->dev_lock, flags); + mutex_unlock(&wq->wq_lock); + return rc; + } + + wq->client_count = 0; + + dev_info(dev, "wq %s enabled ", dev_name(&wq->conf_dev)); + mutex_unlock(&wq->wq_lock); + return 0; + } + + return -enodev; +} + +static void disable_wq(struct idxd_wq *wq) +{ + struct idxd_device *idxd = wq->idxd; + struct device *dev = &idxd->pdev->dev; + unsigned long flags; + int rc; + + mutex_lock(&wq->wq_lock); + dev_dbg(dev, "%s removing wq %s ", __func__, dev_name(&wq->conf_dev)); + if (wq->state == idxd_wq_disabled) { + mutex_unlock(&wq->wq_lock); + return; + } + + if (idxd_wq_refcount(wq)) + dev_warn(dev, "clients has claim on wq %d: %d ", + wq->id, idxd_wq_refcount(wq)); + + idxd_wq_unmap_portal(wq); + + spin_lock_irqsave(&idxd->dev_lock, flags); + rc = idxd_wq_disable(wq); + spin_unlock_irqrestore(&idxd->dev_lock, flags); + + idxd_wq_free_resources(wq); + wq->client_count = 0; + mutex_unlock(&wq->wq_lock); + + if (rc < 0) + dev_warn(dev, "failed to disable %s: %d ", + dev_name(&wq->conf_dev), rc); + else + dev_info(dev, "wq %s disabled ", dev_name(&wq->conf_dev)); +} + +static int idxd_config_bus_remove(struct device *dev) +{ + int rc; + unsigned long flags; + + dev_dbg(dev, "%s called for %s ", __func__, dev_name(dev)); + + /* disable workqueue here */ + if (is_idxd_wq_dev(dev)) { + struct idxd_wq *wq = confdev_to_wq(dev); + + disable_wq(wq); + } else if (is_idxd_dev(dev)) { + struct idxd_device *idxd = confdev_to_idxd(dev); + int i; + + dev_dbg(dev, "%s removing dev %s ", __func__, + dev_name(&idxd->conf_dev)); + for (i = 0; i < idxd->max_wqs; i++) { + struct idxd_wq *wq = &idxd->wqs[i]; + + if (wq->state == idxd_wq_disabled) + continue; + dev_warn(dev, "active wq %d on disable %s. ", i, + dev_name(&idxd->conf_dev)); + device_release_driver(&wq->conf_dev); + } + + spin_lock_irqsave(&idxd->dev_lock, flags); + rc = idxd_device_disable(idxd); + spin_unlock_irqrestore(&idxd->dev_lock, flags); + if (rc < 0) + dev_warn(dev, "device disable failed "); + else + dev_info(dev, "device %s disabled ", dev_name(dev)); + } + + return 0; +} + +static void idxd_config_bus_shutdown(struct device *dev) +{ + dev_dbg(dev, "%s called ", __func__); +} + +static struct bus_type dsa_bus_type = { + .name = "dsa", + .match = idxd_config_bus_match, + .probe = idxd_config_bus_probe, + .remove = idxd_config_bus_remove, + .shutdown = idxd_config_bus_shutdown, +}; + +static struct bus_type *idxd_bus_types[] = { + &dsa_bus_type +}; + +static struct idxd_device_driver dsa_drv = { + .drv = { + .name = "dsa", + .bus = &dsa_bus_type, + .owner = this_module, + .mod_name = kbuild_modname, + }, +}; + +static struct idxd_device_driver *idxd_drvs[] = { + &dsa_drv +}; + +static struct bus_type *idxd_get_bus_type(struct idxd_device *idxd) +{ + return idxd_bus_types[idxd->type]; +} + +static struct device_type *idxd_get_device_type(struct idxd_device *idxd) +{ + if (idxd->type == idxd_type_dsa) + return &dsa_device_type; + else + return null; +} + +/* idxd generic driver setup */ +int idxd_register_driver(void) +{ + int i, rc; + + for (i = 0; i < idxd_type_max; i++) { + rc = driver_register(&idxd_drvs[i]->drv); + if (rc < 0) + goto drv_fail; + } + + return 0; + +drv_fail: + for (; i > 0; i--) + driver_unregister(&idxd_drvs[i]->drv); + return rc; +} + +void idxd_unregister_driver(void) +{ + int i; + + for (i = 0; i < idxd_type_max; i++) + driver_unregister(&idxd_drvs[i]->drv); +} + +/* idxd engine attributes */ +static ssize_t engine_group_id_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_engine *engine = + container_of(dev, struct idxd_engine, conf_dev); + + if (engine->group) + return sprintf(buf, "%d ", engine->group->id); + else + return sprintf(buf, "%d ", -1); +} + +static ssize_t engine_group_id_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct idxd_engine *engine = + container_of(dev, struct idxd_engine, conf_dev); + struct idxd_device *idxd = engine->idxd; + long id; + int rc; + struct idxd_group *prevg, *group; + + rc = kstrtol(buf, 10, &id); + if (rc < 0) + return -einval; + + if (!test_bit(idxd_flag_configurable, &idxd->flags)) + return -eperm; + + if (id > idxd->max_groups - 1 || id < -1) + return -einval; + + if (id == -1) { + if (engine->group) { + engine->group->num_engines--; + engine->group = null; + } + return count; + } + + group = &idxd->groups[id]; + prevg = engine->group; + + if (prevg) + prevg->num_engines--; + engine->group = &idxd->groups[id]; + engine->group->num_engines++; + + return count; +} + +static struct device_attribute dev_attr_engine_group = + __attr(group_id, 0644, engine_group_id_show, + engine_group_id_store); + +static struct attribute *idxd_engine_attributes[] = { + &dev_attr_engine_group.attr, + null, +}; + +static const struct attribute_group idxd_engine_attribute_group = { + .attrs = idxd_engine_attributes, +}; + +static const struct attribute_group *idxd_engine_attribute_groups[] = { + &idxd_engine_attribute_group, + null, +}; + +/* group attributes */ + +static void idxd_set_free_tokens(struct idxd_device *idxd) +{ + int i, tokens; + + for (i = 0, tokens = 0; i < idxd->max_groups; i++) { + struct idxd_group *g = &idxd->groups[i]; + + tokens += g->tokens_reserved; + } + + idxd->nr_tokens = idxd->max_tokens - tokens; +} + +static ssize_t group_tokens_reserved_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct idxd_group *group = + container_of(dev, struct idxd_group, conf_dev); + + return sprintf(buf, "%u ", group->tokens_reserved); +} + +static ssize_t group_tokens_reserved_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct idxd_group *group = + container_of(dev, struct idxd_group, conf_dev); + struct idxd_device *idxd = group->idxd; + unsigned long val; + int rc; + + rc = kstrtoul(buf, 10, &val); + if (rc < 0) + return -einval; + + if (!test_bit(idxd_flag_configurable, &idxd->flags)) + return -eperm; + + if (idxd->state == idxd_dev_enabled) + return -eperm; + + if (idxd->token_limit == 0) + return -eperm; + + if (val > idxd->max_tokens) + return -einval; + + if (val > idxd->nr_tokens) + return -einval; + + group->tokens_reserved = val; + idxd_set_free_tokens(idxd); + return count; +} + +static struct device_attribute dev_attr_group_tokens_reserved = + __attr(tokens_reserved, 0644, group_tokens_reserved_show, + group_tokens_reserved_store); + +static ssize_t group_tokens_allowed_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct idxd_group *group = + container_of(dev, struct idxd_group, conf_dev); + + return sprintf(buf, "%u ", group->tokens_allowed); +} + +static ssize_t group_tokens_allowed_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct idxd_group *group = + container_of(dev, struct idxd_group, conf_dev); + struct idxd_device *idxd = group->idxd; + unsigned long val; + int rc; + + rc = kstrtoul(buf, 10, &val); + if (rc < 0) + return -einval; + + if (!test_bit(idxd_flag_configurable, &idxd->flags)) + return -eperm; + + if (idxd->state == idxd_dev_enabled) + return -eperm; + + if (idxd->token_limit == 0) + return -eperm; + if (val < 4 * group->num_engines || + val > group->tokens_reserved + idxd->nr_tokens) + return -einval; + + group->tokens_allowed = val; + return count; +} + +static struct device_attribute dev_attr_group_tokens_allowed = + __attr(tokens_allowed, 0644, group_tokens_allowed_show, + group_tokens_allowed_store); + +static ssize_t group_use_token_limit_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct idxd_group *group = + container_of(dev, struct idxd_group, conf_dev); + + return sprintf(buf, "%u ", group->use_token_limit); +} + +static ssize_t group_use_token_limit_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct idxd_group *group = + container_of(dev, struct idxd_group, conf_dev); + struct idxd_device *idxd = group->idxd; + unsigned long val; + int rc; + + rc = kstrtoul(buf, 10, &val); + if (rc < 0) + return -einval; + + if (!test_bit(idxd_flag_configurable, &idxd->flags)) + return -eperm; + + if (idxd->state == idxd_dev_enabled) + return -eperm; + + if (idxd->token_limit == 0) + return -eperm; + + group->use_token_limit = !!val; + return count; +} + +static struct device_attribute dev_attr_group_use_token_limit = + __attr(use_token_limit, 0644, group_use_token_limit_show, + group_use_token_limit_store); + +static ssize_t group_engines_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_group *group = + container_of(dev, struct idxd_group, conf_dev); + int i, rc = 0; + char *tmp = buf; + struct idxd_device *idxd = group->idxd; + + for (i = 0; i < idxd->max_engines; i++) { + struct idxd_engine *engine = &idxd->engines[i]; + + if (!engine->group) + continue; + + if (engine->group->id == group->id) + rc += sprintf(tmp + rc, "engine%d.%d ", + idxd->id, engine->id); + } + + rc--; + rc += sprintf(tmp + rc, " "); + + return rc; +} + +static struct device_attribute dev_attr_group_engines = + __attr(engines, 0444, group_engines_show, null); + +static ssize_t group_work_queues_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_group *group = + container_of(dev, struct idxd_group, conf_dev); + int i, rc = 0; + char *tmp = buf; + struct idxd_device *idxd = group->idxd; + + for (i = 0; i < idxd->max_wqs; i++) { + struct idxd_wq *wq = &idxd->wqs[i]; + + if (!wq->group) + continue; + + if (wq->group->id == group->id) + rc += sprintf(tmp + rc, "wq%d.%d ", + idxd->id, wq->id); + } + + rc--; + rc += sprintf(tmp + rc, " "); + + return rc; +} + +static struct device_attribute dev_attr_group_work_queues = + __attr(work_queues, 0444, group_work_queues_show, null); + +static ssize_t group_traffic_class_a_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct idxd_group *group = + container_of(dev, struct idxd_group, conf_dev); + + return sprintf(buf, "%d ", group->tc_a); +} + +static ssize_t group_traffic_class_a_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct idxd_group *group = + container_of(dev, struct idxd_group, conf_dev); + struct idxd_device *idxd = group->idxd; + long val; + int rc; + + rc = kstrtol(buf, 10, &val); + if (rc < 0) + return -einval; + + if (!test_bit(idxd_flag_configurable, &idxd->flags)) + return -eperm; + + if (idxd->state == idxd_dev_enabled) + return -eperm; + + if (val < 0 || val > 7) + return -einval; + + group->tc_a = val; + return count; +} + +static struct device_attribute dev_attr_group_traffic_class_a = + __attr(traffic_class_a, 0644, group_traffic_class_a_show, + group_traffic_class_a_store); + +static ssize_t group_traffic_class_b_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct idxd_group *group = + container_of(dev, struct idxd_group, conf_dev); + + return sprintf(buf, "%d ", group->tc_b); +} + +static ssize_t group_traffic_class_b_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct idxd_group *group = + container_of(dev, struct idxd_group, conf_dev); + struct idxd_device *idxd = group->idxd; + long val; + int rc; + + rc = kstrtol(buf, 10, &val); + if (rc < 0) + return -einval; + + if (!test_bit(idxd_flag_configurable, &idxd->flags)) + return -eperm; + + if (idxd->state == idxd_dev_enabled) + return -eperm; + + if (val < 0 || val > 7) + return -einval; + + group->tc_b = val; + return count; +} + +static struct device_attribute dev_attr_group_traffic_class_b = + __attr(traffic_class_b, 0644, group_traffic_class_b_show, + group_traffic_class_b_store); + +static struct attribute *idxd_group_attributes[] = { + &dev_attr_group_work_queues.attr, + &dev_attr_group_engines.attr, + &dev_attr_group_use_token_limit.attr, + &dev_attr_group_tokens_allowed.attr, + &dev_attr_group_tokens_reserved.attr, + &dev_attr_group_traffic_class_a.attr, + &dev_attr_group_traffic_class_b.attr, + null, +}; + +static const struct attribute_group idxd_group_attribute_group = { + .attrs = idxd_group_attributes, +}; + +static const struct attribute_group *idxd_group_attribute_groups[] = { + &idxd_group_attribute_group, + null, +}; + +/* idxd work queue attribs */ +static ssize_t wq_clients_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_wq *wq = container_of(dev, struct idxd_wq, conf_dev); + + return sprintf(buf, "%d ", wq->client_count); +} + +static struct device_attribute dev_attr_wq_clients = + __attr(clients, 0444, wq_clients_show, null); + +static ssize_t wq_state_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_wq *wq = container_of(dev, struct idxd_wq, conf_dev); + + switch (wq->state) { + case idxd_wq_disabled: + return sprintf(buf, "disabled "); + case idxd_wq_enabled: + return sprintf(buf, "enabled "); + } + + return sprintf(buf, "unknown "); +} + +static struct device_attribute dev_attr_wq_state = + __attr(state, 0444, wq_state_show, null); + +static ssize_t wq_group_id_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_wq *wq = container_of(dev, struct idxd_wq, conf_dev); + + if (wq->group) + return sprintf(buf, "%u ", wq->group->id); + else + return sprintf(buf, "-1 "); +} + +static ssize_t wq_group_id_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct idxd_wq *wq = container_of(dev, struct idxd_wq, conf_dev); + struct idxd_device *idxd = wq->idxd; + long id; + int rc; + struct idxd_group *prevg, *group; + + rc = kstrtol(buf, 10, &id); + if (rc < 0) + return -einval; + + if (!test_bit(idxd_flag_configurable, &idxd->flags)) + return -eperm; + + if (wq->state != idxd_wq_disabled) + return -eperm; + + if (id > idxd->max_groups - 1 || id < -1) + return -einval; + + if (id == -1) { + if (wq->group) { + wq->group->num_wqs--; + wq->group = null; + } + return count; + } + + group = &idxd->groups[id]; + prevg = wq->group; + + if (prevg) + prevg->num_wqs--; + wq->group = group; + group->num_wqs++; + return count; +} + +static struct device_attribute dev_attr_wq_group_id = + __attr(group_id, 0644, wq_group_id_show, wq_group_id_store); + +static ssize_t wq_mode_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct idxd_wq *wq = container_of(dev, struct idxd_wq, conf_dev); + + return sprintf(buf, "%s ", + wq_dedicated(wq) ? "dedicated" : "shared"); +} + +static ssize_t wq_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct idxd_wq *wq = container_of(dev, struct idxd_wq, conf_dev); + struct idxd_device *idxd = wq->idxd; + + if (!test_bit(idxd_flag_configurable, &idxd->flags)) + return -eperm; + + if (wq->state != idxd_wq_disabled) + return -eperm; + + if (sysfs_streq(buf, "dedicated")) { + set_bit(wq_flag_dedicated, &wq->flags); + wq->threshold = 0; + } else { + return -einval; + } + + return count; +} + +static struct device_attribute dev_attr_wq_mode = + __attr(mode, 0644, wq_mode_show, wq_mode_store); + +static ssize_t wq_size_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct idxd_wq *wq = container_of(dev, struct idxd_wq, conf_dev); + + return sprintf(buf, "%u ", wq->size); +} + +static ssize_t wq_size_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct idxd_wq *wq = container_of(dev, struct idxd_wq, conf_dev); + unsigned long size; + struct idxd_device *idxd = wq->idxd; + int rc; + + rc = kstrtoul(buf, 10, &size); + if (rc < 0) + return -einval; + + if (!test_bit(idxd_flag_configurable, &idxd->flags)) + return -eperm; + + if (wq->state != idxd_wq_disabled) + return -eperm; + + if (size > idxd->max_wq_size) + return -einval; + + wq->size = size; + return count; +} + +static struct device_attribute dev_attr_wq_size = + __attr(size, 0644, wq_size_show, wq_size_store); + +static ssize_t wq_priority_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_wq *wq = container_of(dev, struct idxd_wq, conf_dev); + + return sprintf(buf, "%u ", wq->priority); +} + +static ssize_t wq_priority_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct idxd_wq *wq = container_of(dev, struct idxd_wq, conf_dev); + unsigned long prio; + struct idxd_device *idxd = wq->idxd; + int rc; + + rc = kstrtoul(buf, 10, &prio); + if (rc < 0) + return -einval; + + if (!test_bit(idxd_flag_configurable, &idxd->flags)) + return -eperm; + + if (wq->state != idxd_wq_disabled) + return -eperm; + + if (prio > idxd_max_priority) + return -einval; + + wq->priority = prio; + return count; +} + +static struct device_attribute dev_attr_wq_priority = + __attr(priority, 0644, wq_priority_show, wq_priority_store); + +static ssize_t wq_type_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_wq *wq = container_of(dev, struct idxd_wq, conf_dev); + + switch (wq->type) { + case idxd_wqt_kernel: + return sprintf(buf, "%s ", + idxd_wq_type_names[idxd_wqt_kernel]); + case idxd_wqt_none: + default: + return sprintf(buf, "%s ", + idxd_wq_type_names[idxd_wqt_none]); + } + + return -einval; +} + +static ssize_t wq_type_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct idxd_wq *wq = container_of(dev, struct idxd_wq, conf_dev); + enum idxd_wq_type old_type; + + if (wq->state != idxd_wq_disabled) + return -eperm; + + old_type = wq->type; + if (sysfs_streq(buf, idxd_wq_type_names[idxd_wqt_kernel])) + wq->type = idxd_wqt_kernel; + else + wq->type = idxd_wqt_none; + + /* if we are changing queue type, clear the name */ + if (wq->type != old_type) + memset(wq->name, 0, wq_name_size + 1); + + return count; +} + +static struct device_attribute dev_attr_wq_type = + __attr(type, 0644, wq_type_show, wq_type_store); + +static ssize_t wq_name_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_wq *wq = container_of(dev, struct idxd_wq, conf_dev); + + return sprintf(buf, "%s ", wq->name); +} + +static ssize_t wq_name_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct idxd_wq *wq = container_of(dev, struct idxd_wq, conf_dev); + + if (wq->state != idxd_wq_disabled) + return -eperm; + + if (strlen(buf) > wq_name_size || strlen(buf) == 0) + return -einval; + + memset(wq->name, 0, wq_name_size + 1); + strncpy(wq->name, buf, wq_name_size); + strreplace(wq->name, ' ', ''); + return count; +} + +static struct device_attribute dev_attr_wq_name = + __attr(name, 0644, wq_name_show, wq_name_store); + +static struct attribute *idxd_wq_attributes[] = { + &dev_attr_wq_clients.attr, + &dev_attr_wq_state.attr, + &dev_attr_wq_group_id.attr, + &dev_attr_wq_mode.attr, + &dev_attr_wq_size.attr, + &dev_attr_wq_priority.attr, + &dev_attr_wq_type.attr, + &dev_attr_wq_name.attr, + null, +}; + +static const struct attribute_group idxd_wq_attribute_group = { + .attrs = idxd_wq_attributes, +}; + +static const struct attribute_group *idxd_wq_attribute_groups[] = { + &idxd_wq_attribute_group, + null, +}; + +/* idxd device attribs */ +static ssize_t max_work_queues_size_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct idxd_device *idxd = + container_of(dev, struct idxd_device, conf_dev); + + return sprintf(buf, "%u ", idxd->max_wq_size); +} +static device_attr_ro(max_work_queues_size); + +static ssize_t max_groups_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_device *idxd = + container_of(dev, struct idxd_device, conf_dev); + + return sprintf(buf, "%u ", idxd->max_groups); +} +static device_attr_ro(max_groups); + +static ssize_t max_work_queues_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_device *idxd = + container_of(dev, struct idxd_device, conf_dev); + + return sprintf(buf, "%u ", idxd->max_wqs); +} +static device_attr_ro(max_work_queues); + +static ssize_t max_engines_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_device *idxd = + container_of(dev, struct idxd_device, conf_dev); + + return sprintf(buf, "%u ", idxd->max_engines); +} +static device_attr_ro(max_engines); + +static ssize_t numa_node_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_device *idxd = + container_of(dev, struct idxd_device, conf_dev); + + return sprintf(buf, "%d ", dev_to_node(&idxd->pdev->dev)); +} +static device_attr_ro(numa_node); + +static ssize_t max_batch_size_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_device *idxd = + container_of(dev, struct idxd_device, conf_dev); + + return sprintf(buf, "%u ", idxd->max_batch_size); +} +static device_attr_ro(max_batch_size); + +static ssize_t max_transfer_size_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct idxd_device *idxd = + container_of(dev, struct idxd_device, conf_dev); + + return sprintf(buf, "%llu ", idxd->max_xfer_bytes); +} +static device_attr_ro(max_transfer_size); + +static ssize_t op_cap_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_device *idxd = + container_of(dev, struct idxd_device, conf_dev); + + return sprintf(buf, "%#llx ", idxd->hw.opcap.bits[0]); +} +static device_attr_ro(op_cap); + +static ssize_t configurable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_device *idxd = + container_of(dev, struct idxd_device, conf_dev); + + return sprintf(buf, "%u ", + test_bit(idxd_flag_configurable, &idxd->flags)); +} +static device_attr_ro(configurable); + +static ssize_t clients_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_device *idxd = + container_of(dev, struct idxd_device, conf_dev); + unsigned long flags; + int count = 0, i; + + spin_lock_irqsave(&idxd->dev_lock, flags); + for (i = 0; i < idxd->max_wqs; i++) { + struct idxd_wq *wq = &idxd->wqs[i]; + + count += wq->client_count; + } + spin_unlock_irqrestore(&idxd->dev_lock, flags); + + return sprintf(buf, "%d ", count); +} +static device_attr_ro(clients); + +static ssize_t state_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_device *idxd = + container_of(dev, struct idxd_device, conf_dev); + + switch (idxd->state) { + case idxd_dev_disabled: + case idxd_dev_conf_ready: + return sprintf(buf, "disabled "); + case idxd_dev_enabled: + return sprintf(buf, "enabled "); + case idxd_dev_halted: + return sprintf(buf, "halted "); + } + + return sprintf(buf, "unknown "); +} +static device_attr_ro(state); + +static ssize_t errors_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_device *idxd = + container_of(dev, struct idxd_device, conf_dev); + int i, out = 0; + unsigned long flags; + + spin_lock_irqsave(&idxd->dev_lock, flags); + for (i = 0; i < 4; i++) + out += sprintf(buf + out, "%#018llx ", idxd->sw_err.bits[i]); + spin_unlock_irqrestore(&idxd->dev_lock, flags); + out--; + out += sprintf(buf + out, " "); + return out; +} +static device_attr_ro(errors); + +static ssize_t max_tokens_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_device *idxd = + container_of(dev, struct idxd_device, conf_dev); + + return sprintf(buf, "%u ", idxd->max_tokens); +} +static device_attr_ro(max_tokens); + +static ssize_t token_limit_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_device *idxd = + container_of(dev, struct idxd_device, conf_dev); + + return sprintf(buf, "%u ", idxd->token_limit); +} + +static ssize_t token_limit_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct idxd_device *idxd = + container_of(dev, struct idxd_device, conf_dev); + unsigned long val; + int rc; + + rc = kstrtoul(buf, 10, &val); + if (rc < 0) + return -einval; + + if (idxd->state == idxd_dev_enabled) + return -eperm; + + if (!test_bit(idxd_flag_configurable, &idxd->flags)) + return -eperm; + + if (!idxd->hw.group_cap.token_limit) + return -eperm; + + if (val > idxd->hw.group_cap.total_tokens) + return -einval; + + idxd->token_limit = val; + return count; +} +static device_attr_rw(token_limit); + +static struct attribute *idxd_device_attributes[] = { + &dev_attr_max_groups.attr, + &dev_attr_max_work_queues.attr, + &dev_attr_max_work_queues_size.attr, + &dev_attr_max_engines.attr, + &dev_attr_numa_node.attr, + &dev_attr_max_batch_size.attr, + &dev_attr_max_transfer_size.attr, + &dev_attr_op_cap.attr, + &dev_attr_configurable.attr, + &dev_attr_clients.attr, + &dev_attr_state.attr, + &dev_attr_errors.attr, + &dev_attr_max_tokens.attr, + &dev_attr_token_limit.attr, + null, +}; + +static const struct attribute_group idxd_device_attribute_group = { + .attrs = idxd_device_attributes, +}; + +static const struct attribute_group *idxd_attribute_groups[] = { + &idxd_device_attribute_group, + null, +}; + +static int idxd_setup_engine_sysfs(struct idxd_device *idxd) +{ + struct device *dev = &idxd->pdev->dev; + int i, rc; + + for (i = 0; i < idxd->max_engines; i++) { + struct idxd_engine *engine = &idxd->engines[i]; + + engine->conf_dev.parent = &idxd->conf_dev; + dev_set_name(&engine->conf_dev, "engine%d.%d", + idxd->id, engine->id); + engine->conf_dev.bus = idxd_get_bus_type(idxd); + engine->conf_dev.groups = idxd_engine_attribute_groups; + engine->conf_dev.type = &idxd_engine_device_type; + dev_dbg(dev, "engine device register: %s ", + dev_name(&engine->conf_dev)); + rc = device_register(&engine->conf_dev); + if (rc < 0) { + put_device(&engine->conf_dev); + goto cleanup; + } + } + + return 0; + +cleanup: + while (i--) { + struct idxd_engine *engine = &idxd->engines[i]; + + device_unregister(&engine->conf_dev); + } + return rc; +} + +static int idxd_setup_group_sysfs(struct idxd_device *idxd) +{ + struct device *dev = &idxd->pdev->dev; + int i, rc; + + for (i = 0; i < idxd->max_groups; i++) { + struct idxd_group *group = &idxd->groups[i]; + + group->conf_dev.parent = &idxd->conf_dev; + dev_set_name(&group->conf_dev, "group%d.%d", + idxd->id, group->id); + group->conf_dev.bus = idxd_get_bus_type(idxd); + group->conf_dev.groups = idxd_group_attribute_groups; + group->conf_dev.type = &idxd_group_device_type; + dev_dbg(dev, "group device register: %s ", + dev_name(&group->conf_dev)); + rc = device_register(&group->conf_dev); + if (rc < 0) { + put_device(&group->conf_dev); + goto cleanup; + } + } + + return 0; + +cleanup: + while (i--) { + struct idxd_group *group = &idxd->groups[i]; + + device_unregister(&group->conf_dev); + } + return rc; +} + +static int idxd_setup_wq_sysfs(struct idxd_device *idxd) +{ + struct device *dev = &idxd->pdev->dev; + int i, rc; + + for (i = 0; i < idxd->max_wqs; i++) { + struct idxd_wq *wq = &idxd->wqs[i]; + + wq->conf_dev.parent = &idxd->conf_dev; + dev_set_name(&wq->conf_dev, "wq%d.%d", idxd->id, wq->id); + wq->conf_dev.bus = idxd_get_bus_type(idxd); + wq->conf_dev.groups = idxd_wq_attribute_groups; + wq->conf_dev.type = &idxd_wq_device_type; + dev_dbg(dev, "wq device register: %s ", + dev_name(&wq->conf_dev)); + rc = device_register(&wq->conf_dev); + if (rc < 0) { + put_device(&wq->conf_dev); + goto cleanup; + } + } + + return 0; + +cleanup: + while (i--) { + struct idxd_wq *wq = &idxd->wqs[i]; + + device_unregister(&wq->conf_dev); + } + return rc; +} + +static int idxd_setup_device_sysfs(struct idxd_device *idxd) +{ + struct device *dev = &idxd->pdev->dev; + int rc; + char devname[idxd_name_size]; + + sprintf(devname, "%s%d", idxd_get_dev_name(idxd), idxd->id); + idxd->conf_dev.parent = dev; + dev_set_name(&idxd->conf_dev, "%s", devname); + idxd->conf_dev.bus = idxd_get_bus_type(idxd); + idxd->conf_dev.groups = idxd_attribute_groups; + idxd->conf_dev.type = idxd_get_device_type(idxd); + + dev_dbg(dev, "idxd device register: %s ", dev_name(&idxd->conf_dev)); + rc = device_register(&idxd->conf_dev); + if (rc < 0) { + put_device(&idxd->conf_dev); + return rc; + } + + return 0; +} + +int idxd_setup_sysfs(struct idxd_device *idxd) +{ + struct device *dev = &idxd->pdev->dev; + int rc; + + rc = idxd_setup_device_sysfs(idxd); + if (rc < 0) { + dev_dbg(dev, "device sysfs registering failed: %d ", rc); + return rc; + } + + rc = idxd_setup_wq_sysfs(idxd); + if (rc < 0) { + /* unregister conf dev */ + dev_dbg(dev, "work queue sysfs registering failed: %d ", rc); + return rc; + } + + rc = idxd_setup_group_sysfs(idxd); + if (rc < 0) { + /* unregister conf dev */ + dev_dbg(dev, "group sysfs registering failed: %d ", rc); + return rc; + } + + rc = idxd_setup_engine_sysfs(idxd); + if (rc < 0) { + /* unregister conf dev */ + dev_dbg(dev, "engine sysfs registering failed: %d ", rc); + return rc; + } + + return 0; +} + +void idxd_cleanup_sysfs(struct idxd_device *idxd) +{ + int i; + + for (i = 0; i < idxd->max_wqs; i++) { + struct idxd_wq *wq = &idxd->wqs[i]; + + device_unregister(&wq->conf_dev); + } + + for (i = 0; i < idxd->max_engines; i++) { + struct idxd_engine *engine = &idxd->engines[i]; + + device_unregister(&engine->conf_dev); + } + + for (i = 0; i < idxd->max_groups; i++) { + struct idxd_group *group = &idxd->groups[i]; + + device_unregister(&group->conf_dev); + } + + device_unregister(&idxd->conf_dev); +} + +int idxd_register_bus_type(void) +{ + int i, rc; + + for (i = 0; i < idxd_type_max; i++) { + rc = bus_register(idxd_bus_types[i]); + if (rc < 0) + goto bus_err; + } + + return 0; + +bus_err: + for (; i > 0; i--) + bus_unregister(idxd_bus_types[i]); + return rc; +} + +void idxd_unregister_bus_type(void) +{ + int i; + + for (i = 0; i < idxd_type_max; i++) + bus_unregister(idxd_bus_types[i]); +}
|
DMA engines
|
c52ca478233c172b2d322b5241d6279a8661cbba
|
dave jiang
|
drivers
|
dma
|
idxd
|
dmaengine: idxd: add sysfs abi for idxd driver
|
add the sysfs abi information for idxd driver in documentation/abi/stable directory.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
idxd driver for intel data streaming accelerator
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['sysfs-driver-dma-idxd']
| 1
| 171
| 0
|
--- diff --git a/documentation/abi/stable/sysfs-driver-dma-idxd b/documentation/abi/stable/sysfs-driver-dma-idxd --- /dev/null +++ b/documentation/abi/stable/sysfs-driver-dma-idxd +what: sys/bus/dsa/devices/dsa<m>/cdev_major +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the major number that the character device driver assigned to + this device. + +what: sys/bus/dsa/devices/dsa<m>/errors +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the error information for this device. + +what: sys/bus/dsa/devices/dsa<m>/max_batch_size +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the largest number of work descriptors in a batch. + +what: sys/bus/dsa/devices/dsa<m>/max_work_queues_size +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the maximum work queue size supported by this device. + +what: sys/bus/dsa/devices/dsa<m>/max_engines +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the maximum number of engines supported by this device. + +what: sys/bus/dsa/devices/dsa<m>/max_groups +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the maximum number of groups can be created under this device. + +what: sys/bus/dsa/devices/dsa<m>/max_tokens +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the total number of bandwidth tokens supported by this device. + the bandwidth tokens represent resources within the dsa + implementation, and these resources are allocated by engines to + support operations. + +what: sys/bus/dsa/devices/dsa<m>/max_transfer_size +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the number of bytes to be read from the source address to + perform the operation. the maximum transfer size is dependent on + the workqueue the descriptor was submitted to. + +what: sys/bus/dsa/devices/dsa<m>/max_work_queues +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the maximum work queue number that this device supports. + +what: sys/bus/dsa/devices/dsa<m>/numa_node +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the numa node number for this device. + +what: sys/bus/dsa/devices/dsa<m>/op_cap +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the operation capability bit mask specify the operation types + supported by the this device. + +what: sys/bus/dsa/devices/dsa<m>/state +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the state information of this device. it can be either enabled + or disabled. + +what: sys/bus/dsa/devices/dsa<m>/group<m>.<n> +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the assigned group under this device. + +what: sys/bus/dsa/devices/dsa<m>/engine<m>.<n> +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the assigned engine under this device. + +what: sys/bus/dsa/devices/dsa<m>/wq<m>.<n> +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the assigned work queue under this device. + +what: sys/bus/dsa/devices/dsa<m>/configurable +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: to indicate if this device is configurable or not. + +what: sys/bus/dsa/devices/dsa<m>/token_limit +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the maximum number of bandwidth tokens that may be in use at + one time by operations that access low bandwidth memory in the + device. + +what: sys/bus/dsa/devices/wq<m>.<n>/group_id +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the group id that this work queue belongs to. + +what: sys/bus/dsa/devices/wq<m>.<n>/size +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the work queue size for this work queue. + +what: sys/bus/dsa/devices/wq<m>.<n>/type +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the type of this work queue, it can be "kernel" type for work + queue usages in the kernel space or "user" type for work queue + usages by applications in user space. + +what: sys/bus/dsa/devices/wq<m>.<n>/cdev_minor +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the minor number assigned to this work queue by the character + device driver. + +what: sys/bus/dsa/devices/wq<m>.<n>/mode +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the work queue mode type for this work queue. + +what: sys/bus/dsa/devices/wq<m>.<n>/priority +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the priority value of this work queue, it is a vlue relative to + other work queue in the same group to control quality of service + for dispatching work from multiple workqueues in the same group. + +what: sys/bus/dsa/devices/wq<m>.<n>/state +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the current state of the work queue. + +what: sys/bus/dsa/devices/wq<m>.<n>/threshold +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the number of entries in this work queue that may be filled + via a limited portal. + +what: sys/bus/dsa/devices/engine<m>.<n>/group_id +date: oct 25, 2019 +kernelversion: 5.6.0 +contact: dmaengine@vger.kernel.org +description: the group that this engine belongs to.
|
DMA engines
|
b131ad593884cb3decc4950f807af2faffc05a3c
|
jing lin
|
documentation
|
abi
|
stable
|
dmaengine: idxd: add descriptor manipulation routines
|
this commit adds helper functions for dsa descriptor allocation, submission, and free operations.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
idxd driver for intel data streaming accelerator
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['h', 'c', 'makefile']
| 3
| 102
| 1
|
--- diff --git a/drivers/dma/idxd/makefile b/drivers/dma/idxd/makefile --- a/drivers/dma/idxd/makefile +++ b/drivers/dma/idxd/makefile -idxd-y := init.o irq.o device.o sysfs.o +idxd-y := init.o irq.o device.o sysfs.o submit.o diff --git a/drivers/dma/idxd/idxd.h b/drivers/dma/idxd/idxd.h --- a/drivers/dma/idxd/idxd.h +++ b/drivers/dma/idxd/idxd.h +enum idxd_op_type { + idxd_op_block = 0, + idxd_op_nonblock = 1, +}; + +/* submission */ +int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc); +struct idxd_desc *idxd_alloc_desc(struct idxd_wq *wq, enum idxd_op_type optype); +void idxd_free_desc(struct idxd_wq *wq, struct idxd_desc *desc); + diff --git a/drivers/dma/idxd/submit.c b/drivers/dma/idxd/submit.c --- /dev/null +++ b/drivers/dma/idxd/submit.c +// spdx-license-identifier: gpl-2.0 +/* copyright(c) 2019 intel corporation. all rights rsvd. */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/pci.h> +#include <uapi/linux/idxd.h> +#include "idxd.h" +#include "registers.h" + +struct idxd_desc *idxd_alloc_desc(struct idxd_wq *wq, enum idxd_op_type optype) +{ + struct idxd_desc *desc; + int idx; + struct idxd_device *idxd = wq->idxd; + + if (idxd->state != idxd_dev_enabled) + return err_ptr(-eio); + + if (optype == idxd_op_block) + percpu_down_read(&wq->submit_lock); + else if (!percpu_down_read_trylock(&wq->submit_lock)) + return err_ptr(-ebusy); + + if (!atomic_add_unless(&wq->dq_count, 1, wq->size)) { + int rc; + + if (optype == idxd_op_nonblock) { + percpu_up_read(&wq->submit_lock); + return err_ptr(-eagain); + } + + percpu_up_read(&wq->submit_lock); + percpu_down_write(&wq->submit_lock); + rc = wait_event_interruptible(wq->submit_waitq, + atomic_add_unless(&wq->dq_count, + 1, wq->size) || + idxd->state != idxd_dev_enabled); + percpu_up_write(&wq->submit_lock); + if (rc < 0) + return err_ptr(-eintr); + if (idxd->state != idxd_dev_enabled) + return err_ptr(-eio); + } else { + percpu_up_read(&wq->submit_lock); + } + + idx = sbitmap_get(&wq->sbmap, 0, false); + if (idx < 0) { + atomic_dec(&wq->dq_count); + return err_ptr(-eagain); + } + + desc = wq->descs[idx]; + memset(desc->hw, 0, sizeof(struct dsa_hw_desc)); + memset(desc->completion, 0, sizeof(struct dsa_completion_record)); + return desc; +} + +void idxd_free_desc(struct idxd_wq *wq, struct idxd_desc *desc) +{ + atomic_dec(&wq->dq_count); + + sbitmap_clear_bit(&wq->sbmap, desc->id); + wake_up(&wq->submit_waitq); +} + +int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc) +{ + struct idxd_device *idxd = wq->idxd; + int vec = desc->hw->int_handle; + + if (idxd->state != idxd_dev_enabled) + return -eio; + + /* + * the wmb() flushes writes to coherent dma data before possibly + * triggering a dma read. the wmb() is necessary even on up because + * the recipient is a device. + */ + wmb(); + iosubmit_cmds512(wq->dportal, desc->hw, 1); + + /* + * pending the descriptor to the lockless list for the irq_entry + * that we designated the descriptor to. + */ + llist_add(&desc->llnode, &idxd->irq_entries[vec].pending_llist); + + return 0; +}
|
DMA engines
|
d1dfe5b8ac644a0ffccfe7af22abed7c80b34702
|
dave jiang
|
drivers
|
dma
|
idxd
|
dmaengine: idxd: connect idxd to dmaengine subsystem
|
add plumbing for dmaengine subsystem connection. the driver register a dma device per dsa device. the channels are dynamically registered when a workqueue is configured to be "kernel:dmanegine" type.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
idxd driver for intel data streaming accelerator
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['c', 'makefile', 'h']
| 8
| 391
| 2
|
--- diff --git a/drivers/dma/idxd/makefile b/drivers/dma/idxd/makefile --- a/drivers/dma/idxd/makefile +++ b/drivers/dma/idxd/makefile -idxd-y := init.o irq.o device.o sysfs.o submit.o +idxd-y := init.o irq.o device.o sysfs.o submit.o dma.o diff --git a/drivers/dma/idxd/device.c b/drivers/dma/idxd/device.c --- a/drivers/dma/idxd/device.c +++ b/drivers/dma/idxd/device.c +#include <linux/dmaengine.h> +#include "../dmaengine.h" + + dma_async_tx_descriptor_init(&desc->txd, &wq->dma_chan); + desc->txd.tx_submit = idxd_dma_tx_submit; diff --git a/drivers/dma/idxd/dma.c b/drivers/dma/idxd/dma.c --- /dev/null +++ b/drivers/dma/idxd/dma.c +// spdx-license-identifier: gpl-2.0 +/* copyright(c) 2019 intel corporation. all rights rsvd. */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/pci.h> +#include <linux/device.h> +#include <linux/io-64-nonatomic-lo-hi.h> +#include <linux/dmaengine.h> +#include <uapi/linux/idxd.h> +#include "../dmaengine.h" +#include "registers.h" +#include "idxd.h" + +static inline struct idxd_wq *to_idxd_wq(struct dma_chan *c) +{ + return container_of(c, struct idxd_wq, dma_chan); +} + +void idxd_dma_complete_txd(struct idxd_desc *desc, + enum idxd_complete_type comp_type) +{ + struct dma_async_tx_descriptor *tx; + struct dmaengine_result res; + int complete = 1; + + if (desc->completion->status == dsa_comp_success) + res.result = dma_trans_noerror; + else if (desc->completion->status) + res.result = dma_trans_write_failed; + else if (comp_type == idxd_complete_abort) + res.result = dma_trans_aborted; + else + complete = 0; + + tx = &desc->txd; + if (complete && tx->cookie) { + dma_cookie_complete(tx); + dma_descriptor_unmap(tx); + dmaengine_desc_get_callback_invoke(tx, &res); + tx->callback = null; + tx->callback_result = null; + } +} + +static void op_flag_setup(unsigned long flags, u32 *desc_flags) +{ + *desc_flags = idxd_op_flag_crav | idxd_op_flag_rcr; + if (flags & dma_prep_interrupt) + *desc_flags |= idxd_op_flag_rci; +} + +static inline void set_completion_address(struct idxd_desc *desc, + u64 *compl_addr) +{ + *compl_addr = desc->compl_dma; +} + +static inline void idxd_prep_desc_common(struct idxd_wq *wq, + struct dsa_hw_desc *hw, char opcode, + u64 addr_f1, u64 addr_f2, u64 len, + u64 compl, u32 flags) +{ + struct idxd_device *idxd = wq->idxd; + + hw->flags = flags; + hw->opcode = opcode; + hw->src_addr = addr_f1; + hw->dst_addr = addr_f2; + hw->xfer_size = len; + hw->priv = !!(wq->type == idxd_wqt_kernel); + hw->completion_addr = compl; + + /* + * descriptor completion vectors are 1-8 for msix. we will round + * robin through the 8 vectors. + */ + wq->vec_ptr = (wq->vec_ptr % idxd->num_wq_irqs) + 1; + hw->int_handle = wq->vec_ptr; +} + +static struct dma_async_tx_descriptor * +idxd_dma_submit_memcpy(struct dma_chan *c, dma_addr_t dma_dest, + dma_addr_t dma_src, size_t len, unsigned long flags) +{ + struct idxd_wq *wq = to_idxd_wq(c); + u32 desc_flags; + struct idxd_device *idxd = wq->idxd; + struct idxd_desc *desc; + + if (wq->state != idxd_wq_enabled) + return null; + + if (len > idxd->max_xfer_bytes) + return null; + + op_flag_setup(flags, &desc_flags); + desc = idxd_alloc_desc(wq, idxd_op_block); + if (is_err(desc)) + return null; + + idxd_prep_desc_common(wq, desc->hw, dsa_opcode_memmove, + dma_src, dma_dest, len, desc->compl_dma, + desc_flags); + + desc->txd.flags = flags; + + return &desc->txd; +} + +static int idxd_dma_alloc_chan_resources(struct dma_chan *chan) +{ + struct idxd_wq *wq = to_idxd_wq(chan); + struct device *dev = &wq->idxd->pdev->dev; + + idxd_wq_get(wq); + dev_dbg(dev, "%s: client_count: %d ", __func__, + idxd_wq_refcount(wq)); + return 0; +} + +static void idxd_dma_free_chan_resources(struct dma_chan *chan) +{ + struct idxd_wq *wq = to_idxd_wq(chan); + struct device *dev = &wq->idxd->pdev->dev; + + idxd_wq_put(wq); + dev_dbg(dev, "%s: client_count: %d ", __func__, + idxd_wq_refcount(wq)); +} + +static enum dma_status idxd_dma_tx_status(struct dma_chan *dma_chan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + return dma_cookie_status(dma_chan, cookie, txstate); +} + +/* + * issue_pending() does not need to do anything since tx_submit() does the job + * already. + */ +static void idxd_dma_issue_pending(struct dma_chan *dma_chan) +{ +} + +dma_cookie_t idxd_dma_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct dma_chan *c = tx->chan; + struct idxd_wq *wq = to_idxd_wq(c); + dma_cookie_t cookie; + int rc; + struct idxd_desc *desc = container_of(tx, struct idxd_desc, txd); + + cookie = dma_cookie_assign(tx); + + rc = idxd_submit_desc(wq, desc); + if (rc < 0) { + idxd_free_desc(wq, desc); + return rc; + } + + return cookie; +} + +static void idxd_dma_release(struct dma_device *device) +{ +} + +int idxd_register_dma_device(struct idxd_device *idxd) +{ + struct dma_device *dma = &idxd->dma_dev; + + init_list_head(&dma->channels); + dma->dev = &idxd->pdev->dev; + + dma->device_release = idxd_dma_release; + + if (idxd->hw.opcap.bits[0] & idxd_opcap_memmove) { + dma_cap_set(dma_memcpy, dma->cap_mask); + dma->device_prep_dma_memcpy = idxd_dma_submit_memcpy; + } + + dma->device_tx_status = idxd_dma_tx_status; + dma->device_issue_pending = idxd_dma_issue_pending; + dma->device_alloc_chan_resources = idxd_dma_alloc_chan_resources; + dma->device_free_chan_resources = idxd_dma_free_chan_resources; + + return dma_async_device_register(&idxd->dma_dev); +} + +void idxd_unregister_dma_device(struct idxd_device *idxd) +{ + dma_async_device_unregister(&idxd->dma_dev); +} + +int idxd_register_dma_channel(struct idxd_wq *wq) +{ + struct idxd_device *idxd = wq->idxd; + struct dma_device *dma = &idxd->dma_dev; + struct dma_chan *chan = &wq->dma_chan; + int rc; + + memset(&wq->dma_chan, 0, sizeof(struct dma_chan)); + chan->device = dma; + list_add_tail(&chan->device_node, &dma->channels); + rc = dma_async_device_channel_register(dma, chan); + if (rc < 0) + return rc; + + return 0; +} + +void idxd_unregister_dma_channel(struct idxd_wq *wq) +{ + dma_async_device_channel_unregister(&wq->idxd->dma_dev, &wq->dma_chan); +} diff --git a/drivers/dma/idxd/idxd.h b/drivers/dma/idxd/idxd.h --- a/drivers/dma/idxd/idxd.h +++ b/drivers/dma/idxd/idxd.h +#include <linux/dmaengine.h> +enum idxd_complete_type { + idxd_complete_normal = 0, + idxd_complete_abort, +}; + + struct dma_chan dma_chan; + + struct dma_device dma_dev; + struct dma_async_tx_descriptor txd; +/* dmaengine */ +int idxd_register_dma_device(struct idxd_device *idxd); +void idxd_unregister_dma_device(struct idxd_device *idxd); +int idxd_register_dma_channel(struct idxd_wq *wq); +void idxd_unregister_dma_channel(struct idxd_wq *wq); +void idxd_parse_completion_status(u8 status, enum dmaengine_tx_result *res); +void idxd_dma_complete_txd(struct idxd_desc *desc, + enum idxd_complete_type comp_type); +dma_cookie_t idxd_dma_tx_submit(struct dma_async_tx_descriptor *tx); + diff --git a/drivers/dma/idxd/init.c b/drivers/dma/idxd/init.c --- a/drivers/dma/idxd/init.c +++ b/drivers/dma/idxd/init.c +#include <linux/dmaengine.h> +#include "../dmaengine.h" +static void idxd_flush_pending_llist(struct idxd_irq_entry *ie) +{ + struct idxd_desc *desc, *itr; + struct llist_node *head; + + head = llist_del_all(&ie->pending_llist); + if (!head) + return; + + llist_for_each_entry_safe(desc, itr, head, llnode) { + idxd_dma_complete_txd(desc, idxd_complete_abort); + idxd_free_desc(desc->wq, desc); + } +} + +static void idxd_flush_work_list(struct idxd_irq_entry *ie) +{ + struct idxd_desc *desc, *iter; + + list_for_each_entry_safe(desc, iter, &ie->work_list, list) { + list_del(&desc->list); + idxd_dma_complete_txd(desc, idxd_complete_abort); + idxd_free_desc(desc->wq, desc); + } +} + + idxd_flush_pending_llist(irq_entry); + idxd_flush_work_list(irq_entry); diff --git a/drivers/dma/idxd/irq.c b/drivers/dma/idxd/irq.c --- a/drivers/dma/idxd/irq.c +++ b/drivers/dma/idxd/irq.c +#include <linux/dmaengine.h> +#include "../dmaengine.h" +static int irq_process_pending_llist(struct idxd_irq_entry *irq_entry, + int *processed) +{ + struct idxd_desc *desc, *t; + struct llist_node *head; + int queued = 0; + + head = llist_del_all(&irq_entry->pending_llist); + if (!head) + return 0; + + llist_for_each_entry_safe(desc, t, head, llnode) { + if (desc->completion->status) { + idxd_dma_complete_txd(desc, idxd_complete_normal); + idxd_free_desc(desc->wq, desc); + (*processed)++; + } else { + list_add_tail(&desc->list, &irq_entry->work_list); + queued++; + } + } + + return queued; +} + +static int irq_process_work_list(struct idxd_irq_entry *irq_entry, + int *processed) +{ + struct list_head *node, *next; + int queued = 0; + + if (list_empty(&irq_entry->work_list)) + return 0; + + list_for_each_safe(node, next, &irq_entry->work_list) { + struct idxd_desc *desc = + container_of(node, struct idxd_desc, list); + + if (desc->completion->status) { + list_del(&desc->list); + /* process and callback */ + idxd_dma_complete_txd(desc, idxd_complete_normal); + idxd_free_desc(desc->wq, desc); + (*processed)++; + } else { + queued++; + } + } + + return queued; +} + + int rc, processed = 0, retry = 0; + + /* + * there are two lists we are processing. the pending_llist is where + * submmiter adds all the submitted descriptor after sending it to + * the workqueue. it's a lockless singly linked list. the work_list + * is the common linux double linked list. we are in a scenario of + * multiple producers and a single consumer. the producers are all + * the kernel submitters of descriptors, and the consumer is the + * kernel irq handler thread for the msix vector when using threaded + * irq. to work with the restrictions of llist to remain lockless, + * we are doing the following steps: + * 1. iterate through the work_list and process any completed + * descriptor. delete the completed entries during iteration. + * 2. llist_del_all() from the pending list. + * 3. iterate through the llist that was deleted from the pending list + * and process the completed entries. + * 4. if the entry is still waiting on hardware, list_add_tail() to + * the work_list. + * 5. repeat until no more descriptors. + */ + do { + rc = irq_process_work_list(irq_entry, &processed); + if (rc != 0) { + retry++; + continue; + } + + rc = irq_process_pending_llist(irq_entry, &processed); + } while (rc != 0 && retry != 10); + if (processed == 0) + return irq_none; + diff --git a/drivers/dma/idxd/submit.c b/drivers/dma/idxd/submit.c --- a/drivers/dma/idxd/submit.c +++ b/drivers/dma/idxd/submit.c - llist_add(&desc->llnode, &idxd->irq_entries[vec].pending_llist); + if (desc->hw->flags & idxd_op_flag_rci) + llist_add(&desc->llnode, + &idxd->irq_entries[vec].pending_llist); diff --git a/drivers/dma/idxd/sysfs.c b/drivers/dma/idxd/sysfs.c --- a/drivers/dma/idxd/sysfs.c +++ b/drivers/dma/idxd/sysfs.c +static inline bool is_idxd_wq_dmaengine(struct idxd_wq *wq) +{ + if (wq->type == idxd_wqt_kernel && + strcmp(wq->name, "dmaengine") == 0) + return true; + return false; +} + + rc = idxd_register_dma_device(idxd); + if (rc < 0) { + spin_unlock_irqrestore(&idxd->dev_lock, flags); + dev_dbg(dev, "failed to register dmaengine device "); + return rc; + } + + if (is_idxd_wq_dmaengine(wq)) { + rc = idxd_register_dma_channel(wq); + if (rc < 0) { + dev_dbg(dev, "dma channel register failed "); + mutex_unlock(&wq->wq_lock); + return rc; + } + } + + if (is_idxd_wq_dmaengine(wq)) + idxd_unregister_dma_channel(wq); + + idxd_unregister_dma_device(idxd);
|
DMA engines
|
8f47d1a5e545f903cd049c42da31a3be36178447
|
dave jiang
|
drivers
|
dma
|
idxd
|
dmaengine: idxd: add char driver to expose submission portal to userland
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create a char device region that will allow acquisition of user portals in order to allow applications to submit dma operations. a char device will be created per work queue that gets exposed. the workqueue type "user" is used to mark a work queue for user char device. for example if the workqueue 0 of dsa device 0 is marked for char device, then a device node of /dev/dsa/wq0.0 will be created.
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this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
idxd driver for intel data streaming accelerator
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
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[]
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['c', 'makefile', 'h']
| 8
| 422
| 5
|
--- diff --git a/drivers/dma/idxd/makefile b/drivers/dma/idxd/makefile --- a/drivers/dma/idxd/makefile +++ b/drivers/dma/idxd/makefile -idxd-y := init.o irq.o device.o sysfs.o submit.o dma.o +idxd-y := init.o irq.o device.o sysfs.o submit.o dma.o cdev.o diff --git a/drivers/dma/idxd/cdev.c b/drivers/dma/idxd/cdev.c --- /dev/null +++ b/drivers/dma/idxd/cdev.c +// spdx-license-identifier: gpl-2.0 +/* copyright(c) 2019 intel corporation. all rights rsvd. */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/pci.h> +#include <linux/device.h> +#include <linux/sched/task.h> +#include <linux/intel-svm.h> +#include <linux/io-64-nonatomic-lo-hi.h> +#include <linux/cdev.h> +#include <linux/fs.h> +#include <linux/poll.h> +#include <uapi/linux/idxd.h> +#include "registers.h" +#include "idxd.h" + +struct idxd_cdev_context { + const char *name; + dev_t devt; + struct ida minor_ida; +}; + +/* + * ictx is an array based off of accelerator types. enum idxd_type + * is used as index + */ +static struct idxd_cdev_context ictx[idxd_type_max] = { + { .name = "dsa" }, +}; + +struct idxd_user_context { + struct idxd_wq *wq; + struct task_struct *task; + unsigned int flags; +}; + +enum idxd_cdev_cleanup { + cdev_normal = 0, + cdev_failed, +}; + +static void idxd_cdev_dev_release(struct device *dev) +{ + dev_dbg(dev, "releasing cdev device "); + kfree(dev); +} + +static struct device_type idxd_cdev_device_type = { + .name = "idxd_cdev", + .release = idxd_cdev_dev_release, +}; + +static inline struct idxd_cdev *inode_idxd_cdev(struct inode *inode) +{ + struct cdev *cdev = inode->i_cdev; + + return container_of(cdev, struct idxd_cdev, cdev); +} + +static inline struct idxd_wq *idxd_cdev_wq(struct idxd_cdev *idxd_cdev) +{ + return container_of(idxd_cdev, struct idxd_wq, idxd_cdev); +} + +static inline struct idxd_wq *inode_wq(struct inode *inode) +{ + return idxd_cdev_wq(inode_idxd_cdev(inode)); +} + +static int idxd_cdev_open(struct inode *inode, struct file *filp) +{ + struct idxd_user_context *ctx; + struct idxd_device *idxd; + struct idxd_wq *wq; + struct device *dev; + struct idxd_cdev *idxd_cdev; + + wq = inode_wq(inode); + idxd = wq->idxd; + dev = &idxd->pdev->dev; + idxd_cdev = &wq->idxd_cdev; + + dev_dbg(dev, "%s called ", __func__); + + if (idxd_wq_refcount(wq) > 1 && wq_dedicated(wq)) + return -ebusy; + + ctx = kzalloc(sizeof(*ctx), gfp_kernel); + if (!ctx) + return -enomem; + + ctx->wq = wq; + filp->private_data = ctx; + idxd_wq_get(wq); + return 0; +} + +static int idxd_cdev_release(struct inode *node, struct file *filep) +{ + struct idxd_user_context *ctx = filep->private_data; + struct idxd_wq *wq = ctx->wq; + struct idxd_device *idxd = wq->idxd; + struct device *dev = &idxd->pdev->dev; + + dev_dbg(dev, "%s called ", __func__); + filep->private_data = null; + + kfree(ctx); + idxd_wq_put(wq); + return 0; +} + +static int check_vma(struct idxd_wq *wq, struct vm_area_struct *vma, + const char *func) +{ + struct device *dev = &wq->idxd->pdev->dev; + + if ((vma->vm_end - vma->vm_start) > page_size) { + dev_info_ratelimited(dev, + "%s: %s: mapping too large: %lu ", + current->comm, func, + vma->vm_end - vma->vm_start); + return -einval; + } + + return 0; +} + +static int idxd_cdev_mmap(struct file *filp, struct vm_area_struct *vma) +{ + struct idxd_user_context *ctx = filp->private_data; + struct idxd_wq *wq = ctx->wq; + struct idxd_device *idxd = wq->idxd; + struct pci_dev *pdev = idxd->pdev; + phys_addr_t base = pci_resource_start(pdev, idxd_wq_bar); + unsigned long pfn; + int rc; + + dev_dbg(&pdev->dev, "%s called ", __func__); + rc = check_vma(wq, vma, __func__); + + vma->vm_flags |= vm_dontcopy; + pfn = (base + idxd_get_wq_portal_full_offset(wq->id, + idxd_portal_limited)) >> page_shift; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + vma->vm_private_data = ctx; + + return io_remap_pfn_range(vma, vma->vm_start, pfn, page_size, + vma->vm_page_prot); +} + +static __poll_t idxd_cdev_poll(struct file *filp, + struct poll_table_struct *wait) +{ + struct idxd_user_context *ctx = filp->private_data; + struct idxd_wq *wq = ctx->wq; + struct idxd_device *idxd = wq->idxd; + struct idxd_cdev *idxd_cdev = &wq->idxd_cdev; + unsigned long flags; + __poll_t out = 0; + + poll_wait(filp, &idxd_cdev->err_queue, wait); + spin_lock_irqsave(&idxd->dev_lock, flags); + if (idxd->sw_err.valid) + out = epollin | epollrdnorm; + spin_unlock_irqrestore(&idxd->dev_lock, flags); + + return out; +} + +static const struct file_operations idxd_cdev_fops = { + .owner = this_module, + .open = idxd_cdev_open, + .release = idxd_cdev_release, + .mmap = idxd_cdev_mmap, + .poll = idxd_cdev_poll, +}; + +int idxd_cdev_get_major(struct idxd_device *idxd) +{ + return major(ictx[idxd->type].devt); +} + +static int idxd_wq_cdev_dev_setup(struct idxd_wq *wq) +{ + struct idxd_device *idxd = wq->idxd; + struct idxd_cdev *idxd_cdev = &wq->idxd_cdev; + struct idxd_cdev_context *cdev_ctx; + struct device *dev; + int minor, rc; + + idxd_cdev->dev = kzalloc(sizeof(*idxd_cdev->dev), gfp_kernel); + if (!idxd_cdev->dev) + return -enomem; + + dev = idxd_cdev->dev; + dev->parent = &idxd->pdev->dev; + dev_set_name(dev, "%s/wq%u.%u", idxd_get_dev_name(idxd), + idxd->id, wq->id); + dev->bus = idxd_get_bus_type(idxd); + + cdev_ctx = &ictx[wq->idxd->type]; + minor = ida_simple_get(&cdev_ctx->minor_ida, 0, minormask, gfp_kernel); + if (minor < 0) { + rc = minor; + goto ida_err; + } + + dev->devt = mkdev(major(cdev_ctx->devt), minor); + dev->type = &idxd_cdev_device_type; + rc = device_register(dev); + if (rc < 0) { + dev_err(&idxd->pdev->dev, "device register failed "); + put_device(dev); + goto dev_reg_err; + } + idxd_cdev->minor = minor; + + return 0; + + dev_reg_err: + ida_simple_remove(&cdev_ctx->minor_ida, minor(dev->devt)); + ida_err: + kfree(dev); + idxd_cdev->dev = null; + return rc; +} + +static void idxd_wq_cdev_cleanup(struct idxd_wq *wq, + enum idxd_cdev_cleanup cdev_state) +{ + struct idxd_cdev *idxd_cdev = &wq->idxd_cdev; + struct idxd_cdev_context *cdev_ctx; + + cdev_ctx = &ictx[wq->idxd->type]; + if (cdev_state == cdev_normal) + cdev_del(&idxd_cdev->cdev); + device_unregister(idxd_cdev->dev); + /* + * the device_type->release() will be called on the device and free + * the allocated struct device. we can just forget it. + */ + ida_simple_remove(&cdev_ctx->minor_ida, idxd_cdev->minor); + idxd_cdev->dev = null; + idxd_cdev->minor = -1; +} + +int idxd_wq_add_cdev(struct idxd_wq *wq) +{ + struct idxd_cdev *idxd_cdev = &wq->idxd_cdev; + struct cdev *cdev = &idxd_cdev->cdev; + struct device *dev; + int rc; + + rc = idxd_wq_cdev_dev_setup(wq); + if (rc < 0) + return rc; + + dev = idxd_cdev->dev; + cdev_init(cdev, &idxd_cdev_fops); + cdev_set_parent(cdev, &dev->kobj); + rc = cdev_add(cdev, dev->devt, 1); + if (rc) { + dev_dbg(&wq->idxd->pdev->dev, "cdev_add failed: %d ", rc); + idxd_wq_cdev_cleanup(wq, cdev_failed); + return rc; + } + + init_waitqueue_head(&idxd_cdev->err_queue); + return 0; +} + +void idxd_wq_del_cdev(struct idxd_wq *wq) +{ + idxd_wq_cdev_cleanup(wq, cdev_normal); +} + +int idxd_cdev_register(void) +{ + int rc, i; + + for (i = 0; i < idxd_type_max; i++) { + ida_init(&ictx[i].minor_ida); + rc = alloc_chrdev_region(&ictx[i].devt, 0, minormask, + ictx[i].name); + if (rc) + return rc; + } + + return 0; +} + +void idxd_cdev_remove(void) +{ + int i; + + for (i = 0; i < idxd_type_max; i++) { + unregister_chrdev_region(ictx[i].devt, minormask); + ida_destroy(&ictx[i].minor_ida); + } +} diff --git a/drivers/dma/idxd/device.c b/drivers/dma/idxd/device.c --- a/drivers/dma/idxd/device.c +++ b/drivers/dma/idxd/device.c - wq->wqcfg.priv = 1; /* kernel, therefore priv */ + wq->wqcfg.priv = !!(wq->type == idxd_wqt_kernel); diff --git a/drivers/dma/idxd/idxd.h b/drivers/dma/idxd/idxd.h --- a/drivers/dma/idxd/idxd.h +++ b/drivers/dma/idxd/idxd.h +#include <linux/cdev.h> + idxd_wqt_user, +}; + +struct idxd_cdev { + struct cdev cdev; + struct device *dev; + int minor; + struct wait_queue_head err_queue; + struct idxd_cdev idxd_cdev; + int major; +extern struct bus_type dsa_bus_type; + +enum idxd_portal_prot { + idxd_portal_unlimited = 0, + idxd_portal_limited, +}; + +static inline int idxd_get_wq_portal_offset(enum idxd_portal_prot prot) +{ + return prot * 0x1000; +} + +static inline int idxd_get_wq_portal_full_offset(int wq_id, + enum idxd_portal_prot prot) +{ + return ((wq_id * 4) << page_shift) + idxd_get_wq_portal_offset(prot); +} + +struct bus_type *idxd_get_bus_type(struct idxd_device *idxd); +/* cdev */ +int idxd_cdev_register(void); +void idxd_cdev_remove(void); +int idxd_cdev_get_major(struct idxd_device *idxd); +int idxd_wq_add_cdev(struct idxd_wq *wq); +void idxd_wq_del_cdev(struct idxd_wq *wq); + diff --git a/drivers/dma/idxd/init.c b/drivers/dma/idxd/init.c --- a/drivers/dma/idxd/init.c +++ b/drivers/dma/idxd/init.c + wq->idxd_cdev.minor = -1; + idxd->major = idxd_cdev_get_major(idxd); + + err = idxd_cdev_register(); + if (err) + goto err_cdev_register; + + idxd_cdev_remove(); +err_cdev_register: + idxd_cdev_remove(); diff --git a/drivers/dma/idxd/irq.c b/drivers/dma/idxd/irq.c --- a/drivers/dma/idxd/irq.c +++ b/drivers/dma/idxd/irq.c + + if (idxd->sw_err.valid && idxd->sw_err.wq_idx_valid) { + int id = idxd->sw_err.wq_idx; + struct idxd_wq *wq = &idxd->wqs[id]; + + if (wq->type == idxd_wqt_user) + wake_up_interruptible(&wq->idxd_cdev.err_queue); + } else { + int i; + + for (i = 0; i < idxd->max_wqs; i++) { + struct idxd_wq *wq = &idxd->wqs[i]; + + if (wq->type == idxd_wqt_user) + wake_up_interruptible(&wq->idxd_cdev.err_queue); + } + } + diff --git a/drivers/dma/idxd/submit.c b/drivers/dma/idxd/submit.c --- a/drivers/dma/idxd/submit.c +++ b/drivers/dma/idxd/submit.c + void __iomem *portal; + portal = wq->dportal + idxd_get_wq_portal_offset(idxd_portal_unlimited); - iosubmit_cmds512(wq->dportal, desc->hw, 1); + iosubmit_cmds512(portal, desc->hw, 1); diff --git a/drivers/dma/idxd/sysfs.c b/drivers/dma/idxd/sysfs.c --- a/drivers/dma/idxd/sysfs.c +++ b/drivers/dma/idxd/sysfs.c + [idxd_wqt_user] = "user", +static inline bool is_idxd_wq_cdev(struct idxd_wq *wq) +{ + return wq->type == idxd_wqt_user ? true : false; +} + + if (!try_module_get(this_module)) + return -enxio; + + } else if (is_idxd_wq_cdev(wq)) { + rc = idxd_wq_add_cdev(wq); + if (rc < 0) { + dev_dbg(dev, "cdev creation failed "); + mutex_unlock(&wq->wq_lock); + return rc; + } + else if (is_idxd_wq_cdev(wq)) + idxd_wq_del_cdev(wq); + module_put(this_module); + -static struct bus_type dsa_bus_type = { +struct bus_type dsa_bus_type = { -static struct bus_type *idxd_get_bus_type(struct idxd_device *idxd) +struct bus_type *idxd_get_bus_type(struct idxd_device *idxd) + case idxd_wqt_user: + return sprintf(buf, "%s ", + idxd_wq_type_names[idxd_wqt_user]); + else if (sysfs_streq(buf, idxd_wq_type_names[idxd_wqt_user])) + wq->type = idxd_wqt_user; +static ssize_t wq_cdev_minor_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_wq *wq = container_of(dev, struct idxd_wq, conf_dev); + + return sprintf(buf, "%d ", wq->idxd_cdev.minor); +} + +static struct device_attribute dev_attr_wq_cdev_minor = + __attr(cdev_minor, 0444, wq_cdev_minor_show, null); + + &dev_attr_wq_cdev_minor.attr, +static ssize_t cdev_major_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_device *idxd = + container_of(dev, struct idxd_device, conf_dev); + + return sprintf(buf, "%u ", idxd->major); +} +static device_attr_ro(cdev_major); + + &dev_attr_cdev_major.attr,
|
DMA engines
|
42d279f9137ab7d5503836baec2739284b278d8f
|
dave jiang
|
drivers
|
dma
|
idxd
|
dmaengine: store module owner in dma_device struct
|
dma_chan_to_owner() dereferences the driver from the struct device to obtain the owner and call module_[get|put](). however, if the backing device is unbound before the dma_device is unregistered, the driver will be cleared and this will cause a null pointer dereference.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
plx switch dma engine driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['c', 'h']
| 2
| 5
| 1
|
--- diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c - return chan->device->dev->driver->owner; + return chan->device->owner; + device->owner = device->dev->driver->owner; + diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h + * @owner: owner module (automatically set based on the provided dev) + struct module *owner;
|
DMA engines
|
dae7a589c18a4d979d5f14b09374e871b995ceb1
|
logan gunthorpe
|
include
|
linux
| |
dmaengine: call module_put() after device_free_chan_resources()
|
the module reference is taken to ensure the callbacks still exist when they are called. if the channel holds the last reference to the module, the module can disappear before device_free_chan_resources() is called and would cause a call into free'd memory.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
plx switch dma engine driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['c']
| 1
| 2
| 1
|
--- diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c - module_put(dma_chan_to_owner(chan)); + module_put(dma_chan_to_owner(chan)); +
|
DMA engines
|
686607106f1fe163f7d017561f3622f39a291de8
|
logan gunthorpe
|
drivers
|
dma
| |
dmaengine: plx-dma: introduce plx dma engine pci driver skeleton
|
some plx switches can expose dma engines via extra pci functions on the upstream port. each function will have one dma channel.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
plx switch dma engine driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['c', 'kconfig', 'makefile', 'maintainers']
| 4
| 165
| 0
|
--- diff --git a/maintainers b/maintainers --- a/maintainers +++ b/maintainers +plx dma driver +m: logan gunthorpe <logang@deltatee.com> +s: maintained +f: drivers/dma/plx_dma.c + diff --git a/drivers/dma/kconfig b/drivers/dma/kconfig --- a/drivers/dma/kconfig +++ b/drivers/dma/kconfig +config plx_dma + tristate "plx expresslane pex switch dma engine support" + depends on pci + select dma_engine + help + some plx expresslane pci switches support additional dma engines. + these are exposed via extra functions on the switch's + upstream port. each function exposes one dma channel. + diff --git a/drivers/dma/makefile b/drivers/dma/makefile --- a/drivers/dma/makefile +++ b/drivers/dma/makefile +obj-$(config_plx_dma) += plx_dma.o diff --git a/drivers/dma/plx_dma.c b/drivers/dma/plx_dma.c --- /dev/null +++ b/drivers/dma/plx_dma.c +// spdx-license-identifier: gpl-2.0 +/* + * microsemi switchtec(tm) pcie management driver + * copyright (c) 2019, logan gunthorpe <logang@deltatee.com> + * copyright (c) 2019, gigaio networks, inc + */ + +#include "dmaengine.h" + +#include <linux/dmaengine.h> +#include <linux/kref.h> +#include <linux/list.h> +#include <linux/module.h> +#include <linux/pci.h> + +module_description("plx expresslane pex pci switch dma engine"); +module_version("0.1"); +module_license("gpl"); +module_author("logan gunthorpe"); + +struct plx_dma_dev { + struct dma_device dma_dev; + struct dma_chan dma_chan; + void __iomem *bar; +}; + +static void plx_dma_release(struct dma_device *dma_dev) +{ + struct plx_dma_dev *plxdev = + container_of(dma_dev, struct plx_dma_dev, dma_dev); + + put_device(dma_dev->dev); + kfree(plxdev); +} + +static int plx_dma_create(struct pci_dev *pdev) +{ + struct plx_dma_dev *plxdev; + struct dma_device *dma; + struct dma_chan *chan; + int rc; + + plxdev = kzalloc(sizeof(*plxdev), gfp_kernel); + if (!plxdev) + return -enomem; + + plxdev->bar = pcim_iomap_table(pdev)[0]; + + dma = &plxdev->dma_dev; + dma->chancnt = 1; + init_list_head(&dma->channels); + dma->copy_align = dmaengine_align_1_byte; + dma->dev = get_device(&pdev->dev); + + dma->device_release = plx_dma_release; + + chan = &plxdev->dma_chan; + chan->device = dma; + dma_cookie_init(chan); + list_add_tail(&chan->device_node, &dma->channels); + + rc = dma_async_device_register(dma); + if (rc) { + pci_err(pdev, "failed to register dma device: %d ", rc); + free_irq(pci_irq_vector(pdev, 0), plxdev); + kfree(plxdev); + return rc; + } + + pci_set_drvdata(pdev, plxdev); + + return 0; +} + +static int plx_dma_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + int rc; + + rc = pcim_enable_device(pdev); + if (rc) + return rc; + + rc = pci_set_dma_mask(pdev, dma_bit_mask(48)); + if (rc) + rc = pci_set_dma_mask(pdev, dma_bit_mask(32)); + if (rc) + return rc; + + rc = pci_set_consistent_dma_mask(pdev, dma_bit_mask(48)); + if (rc) + rc = pci_set_consistent_dma_mask(pdev, dma_bit_mask(32)); + if (rc) + return rc; + + rc = pcim_iomap_regions(pdev, 1, kbuild_modname); + if (rc) + return rc; + + rc = pci_alloc_irq_vectors(pdev, 1, 1, pci_irq_all_types); + if (rc <= 0) + return rc; + + pci_set_master(pdev); + + rc = plx_dma_create(pdev); + if (rc) + goto err_free_irq_vectors; + + pci_info(pdev, "plx dma channel registered "); + + return 0; + +err_free_irq_vectors: + pci_free_irq_vectors(pdev); + return rc; +} + +static void plx_dma_remove(struct pci_dev *pdev) +{ + struct plx_dma_dev *plxdev = pci_get_drvdata(pdev); + + free_irq(pci_irq_vector(pdev, 0), plxdev); + + plxdev->bar = null; + dma_async_device_unregister(&plxdev->dma_dev); + + pci_free_irq_vectors(pdev); +} + +static const struct pci_device_id plx_dma_pci_tbl[] = { + { + .vendor = pci_vendor_id_plx, + .device = 0x87d0, + .subvendor = pci_any_id, + .subdevice = pci_any_id, + .class = pci_class_system_other << 8, + .class_mask = 0xffffffff, + }, + {0} +}; +module_device_table(pci, plx_dma_pci_tbl); + +static struct pci_driver plx_dma_pci_driver = { + .name = kbuild_modname, + .id_table = plx_dma_pci_tbl, + .probe = plx_dma_probe, + .remove = plx_dma_remove, +}; +module_pci_driver(plx_dma_pci_driver);
|
DMA engines
|
905ca51e63be794331e09ff74ccddd44393d3378
|
logan gunthorpe
|
drivers
|
dma
| |
dmaengine: plx-dma: implement hardware initialization and cleanup
|
allocate dma coherent memory for the ring of dma descriptors and program the appropriate hardware registers.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
plx switch dma engine driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['c']
| 1
| 370
| 0
|
--- diff --git a/drivers/dma/plx_dma.c b/drivers/dma/plx_dma.c --- a/drivers/dma/plx_dma.c +++ b/drivers/dma/plx_dma.c +#define plx_reg_desc_ring_addr 0x214 +#define plx_reg_desc_ring_addr_hi 0x218 +#define plx_reg_desc_ring_next_addr 0x21c +#define plx_reg_desc_ring_count 0x220 +#define plx_reg_desc_ring_last_addr 0x224 +#define plx_reg_desc_ring_last_size 0x228 +#define plx_reg_pref_limit 0x234 +#define plx_reg_ctrl 0x238 +#define plx_reg_ctrl2 0x23a +#define plx_reg_intr_ctrl 0x23c +#define plx_reg_intr_status 0x23e + +#define plx_reg_pref_limit_pref_four 8 + +#define plx_reg_ctrl_graceful_pause bit(0) +#define plx_reg_ctrl_abort bit(1) +#define plx_reg_ctrl_write_back_en bit(2) +#define plx_reg_ctrl_start bit(3) +#define plx_reg_ctrl_ring_stop_mode bit(4) +#define plx_reg_ctrl_desc_mode_block (0 << 5) +#define plx_reg_ctrl_desc_mode_on_chip (1 << 5) +#define plx_reg_ctrl_desc_mode_off_chip (2 << 5) +#define plx_reg_ctrl_desc_invalid bit(8) +#define plx_reg_ctrl_graceful_pause_done bit(9) +#define plx_reg_ctrl_abort_done bit(10) +#define plx_reg_ctrl_imm_pause_done bit(12) +#define plx_reg_ctrl_in_progress bit(30) + +#define plx_reg_ctrl_reset_val (plx_reg_ctrl_desc_invalid | \ + plx_reg_ctrl_graceful_pause_done | \ + plx_reg_ctrl_abort_done | \ + plx_reg_ctrl_imm_pause_done) + +#define plx_reg_ctrl_start_val (plx_reg_ctrl_write_back_en | \ + plx_reg_ctrl_desc_mode_off_chip | \ + plx_reg_ctrl_start | \ + plx_reg_ctrl_reset_val) + +#define plx_reg_ctrl2_max_txfr_size_64b 0 +#define plx_reg_ctrl2_max_txfr_size_128b 1 +#define plx_reg_ctrl2_max_txfr_size_256b 2 +#define plx_reg_ctrl2_max_txfr_size_512b 3 +#define plx_reg_ctrl2_max_txfr_size_1kb 4 +#define plx_reg_ctrl2_max_txfr_size_2kb 5 +#define plx_reg_ctrl2_max_txfr_size_4b 7 + +#define plx_reg_intr_crtl_error_en bit(0) +#define plx_reg_intr_crtl_inv_desc_en bit(1) +#define plx_reg_intr_crtl_abort_done_en bit(3) +#define plx_reg_intr_crtl_pause_done_en bit(4) +#define plx_reg_intr_crtl_imm_pause_done_en bit(5) + +#define plx_reg_intr_status_error bit(0) +#define plx_reg_intr_status_inv_desc bit(1) +#define plx_reg_intr_status_desc_done bit(2) +#define plx_reg_intr_crtl_abort_done bit(3) + +struct plx_dma_hw_std_desc { + __le32 flags_and_size; + __le16 dst_addr_hi; + __le16 src_addr_hi; + __le32 dst_addr_lo; + __le32 src_addr_lo; +}; + +#define plx_desc_size_mask 0x7ffffff +#define plx_desc_flag_valid bit(31) +#define plx_desc_flag_int_when_done bit(30) + +#define plx_desc_wb_success bit(30) +#define plx_desc_wb_rd_fail bit(29) +#define plx_desc_wb_wr_fail bit(28) + +#define plx_dma_ring_count 2048 + +struct plx_dma_desc { + struct dma_async_tx_descriptor txd; + struct plx_dma_hw_std_desc *hw; + u32 orig_size; +}; + + struct pci_dev __rcu *pdev; + struct tasklet_struct desc_task; + + spinlock_t ring_lock; + bool ring_active; + int head; + int tail; + struct plx_dma_hw_std_desc *hw_ring; + dma_addr_t hw_ring_dma; + struct plx_dma_desc **desc_ring; +static struct plx_dma_dev *chan_to_plx_dma_dev(struct dma_chan *c) +{ + return container_of(c, struct plx_dma_dev, dma_chan); +} + +static struct plx_dma_desc *plx_dma_get_desc(struct plx_dma_dev *plxdev, int i) +{ + return plxdev->desc_ring[i & (plx_dma_ring_count - 1)]; +} + +static void plx_dma_process_desc(struct plx_dma_dev *plxdev) +{ + struct dmaengine_result res; + struct plx_dma_desc *desc; + u32 flags; + + spin_lock_bh(&plxdev->ring_lock); + + while (plxdev->tail != plxdev->head) { + desc = plx_dma_get_desc(plxdev, plxdev->tail); + + flags = le32_to_cpu(read_once(desc->hw->flags_and_size)); + + if (flags & plx_desc_flag_valid) + break; + + res.residue = desc->orig_size - (flags & plx_desc_size_mask); + + if (flags & plx_desc_wb_success) + res.result = dma_trans_noerror; + else if (flags & plx_desc_wb_wr_fail) + res.result = dma_trans_write_failed; + else + res.result = dma_trans_read_failed; + + dma_cookie_complete(&desc->txd); + dma_descriptor_unmap(&desc->txd); + dmaengine_desc_get_callback_invoke(&desc->txd, &res); + desc->txd.callback = null; + desc->txd.callback_result = null; + + plxdev->tail++; + } + + spin_unlock_bh(&plxdev->ring_lock); +} + +static void plx_dma_abort_desc(struct plx_dma_dev *plxdev) +{ + struct dmaengine_result res; + struct plx_dma_desc *desc; + + plx_dma_process_desc(plxdev); + + spin_lock_bh(&plxdev->ring_lock); + + while (plxdev->tail != plxdev->head) { + desc = plx_dma_get_desc(plxdev, plxdev->tail); + + res.residue = desc->orig_size; + res.result = dma_trans_aborted; + + dma_cookie_complete(&desc->txd); + dma_descriptor_unmap(&desc->txd); + dmaengine_desc_get_callback_invoke(&desc->txd, &res); + desc->txd.callback = null; + desc->txd.callback_result = null; + + plxdev->tail++; + } + + spin_unlock_bh(&plxdev->ring_lock); +} + +static void __plx_dma_stop(struct plx_dma_dev *plxdev) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(1000); + u32 val; + + val = readl(plxdev->bar + plx_reg_ctrl); + if (!(val & ~plx_reg_ctrl_graceful_pause)) + return; + + writel(plx_reg_ctrl_reset_val | plx_reg_ctrl_graceful_pause, + plxdev->bar + plx_reg_ctrl); + + while (!time_after(jiffies, timeout)) { + val = readl(plxdev->bar + plx_reg_ctrl); + if (val & plx_reg_ctrl_graceful_pause_done) + break; + + cpu_relax(); + } + + if (!(val & plx_reg_ctrl_graceful_pause_done)) + dev_err(plxdev->dma_dev.dev, + "timeout waiting for graceful pause! "); + + writel(plx_reg_ctrl_reset_val | plx_reg_ctrl_graceful_pause, + plxdev->bar + plx_reg_ctrl); + + writel(0, plxdev->bar + plx_reg_desc_ring_count); + writel(0, plxdev->bar + plx_reg_desc_ring_addr); + writel(0, plxdev->bar + plx_reg_desc_ring_addr_hi); + writel(0, plxdev->bar + plx_reg_desc_ring_next_addr); +} + +static void plx_dma_stop(struct plx_dma_dev *plxdev) +{ + rcu_read_lock(); + if (!rcu_dereference(plxdev->pdev)) { + rcu_read_unlock(); + return; + } + + __plx_dma_stop(plxdev); + + rcu_read_unlock(); +} + +static void plx_dma_desc_task(unsigned long data) +{ + struct plx_dma_dev *plxdev = (void *)data; + + plx_dma_process_desc(plxdev); +} + +static irqreturn_t plx_dma_isr(int irq, void *devid) +{ + struct plx_dma_dev *plxdev = devid; + u32 status; + + status = readw(plxdev->bar + plx_reg_intr_status); + + if (!status) + return irq_none; + + if (status & plx_reg_intr_status_desc_done && plxdev->ring_active) + tasklet_schedule(&plxdev->desc_task); + + writew(status, plxdev->bar + plx_reg_intr_status); + + return irq_handled; +} + +static int plx_dma_alloc_desc(struct plx_dma_dev *plxdev) +{ + struct plx_dma_desc *desc; + int i; + + plxdev->desc_ring = kcalloc(plx_dma_ring_count, + sizeof(*plxdev->desc_ring), gfp_kernel); + if (!plxdev->desc_ring) + return -enomem; + + for (i = 0; i < plx_dma_ring_count; i++) { + desc = kzalloc(sizeof(*desc), gfp_kernel); + if (!desc) + goto free_and_exit; + + dma_async_tx_descriptor_init(&desc->txd, &plxdev->dma_chan); + desc->hw = &plxdev->hw_ring[i]; + plxdev->desc_ring[i] = desc; + } + + return 0; + +free_and_exit: + for (i = 0; i < plx_dma_ring_count; i++) + kfree(plxdev->desc_ring[i]); + kfree(plxdev->desc_ring); + return -enomem; +} + +static int plx_dma_alloc_chan_resources(struct dma_chan *chan) +{ + struct plx_dma_dev *plxdev = chan_to_plx_dma_dev(chan); + size_t ring_sz = plx_dma_ring_count * sizeof(*plxdev->hw_ring); + int rc; + + plxdev->head = plxdev->tail = 0; + plxdev->hw_ring = dma_alloc_coherent(plxdev->dma_dev.dev, ring_sz, + &plxdev->hw_ring_dma, gfp_kernel); + if (!plxdev->hw_ring) + return -enomem; + + rc = plx_dma_alloc_desc(plxdev); + if (rc) + goto out_free_hw_ring; + + rcu_read_lock(); + if (!rcu_dereference(plxdev->pdev)) { + rcu_read_unlock(); + rc = -enodev; + goto out_free_hw_ring; + } + + writel(plx_reg_ctrl_reset_val, plxdev->bar + plx_reg_ctrl); + writel(lower_32_bits(plxdev->hw_ring_dma), + plxdev->bar + plx_reg_desc_ring_addr); + writel(upper_32_bits(plxdev->hw_ring_dma), + plxdev->bar + plx_reg_desc_ring_addr_hi); + writel(lower_32_bits(plxdev->hw_ring_dma), + plxdev->bar + plx_reg_desc_ring_next_addr); + writel(plx_dma_ring_count, plxdev->bar + plx_reg_desc_ring_count); + writel(plx_reg_pref_limit_pref_four, plxdev->bar + plx_reg_pref_limit); + + plxdev->ring_active = true; + + rcu_read_unlock(); + + return plx_dma_ring_count; + +out_free_hw_ring: + dma_free_coherent(plxdev->dma_dev.dev, ring_sz, plxdev->hw_ring, + plxdev->hw_ring_dma); + return rc; +} + +static void plx_dma_free_chan_resources(struct dma_chan *chan) +{ + struct plx_dma_dev *plxdev = chan_to_plx_dma_dev(chan); + size_t ring_sz = plx_dma_ring_count * sizeof(*plxdev->hw_ring); + struct pci_dev *pdev; + int irq = -1; + int i; + + spin_lock_bh(&plxdev->ring_lock); + plxdev->ring_active = false; + spin_unlock_bh(&plxdev->ring_lock); + + plx_dma_stop(plxdev); + + rcu_read_lock(); + pdev = rcu_dereference(plxdev->pdev); + if (pdev) + irq = pci_irq_vector(pdev, 0); + rcu_read_unlock(); + + if (irq > 0) + synchronize_irq(irq); + + tasklet_kill(&plxdev->desc_task); + + plx_dma_abort_desc(plxdev); + + for (i = 0; i < plx_dma_ring_count; i++) + kfree(plxdev->desc_ring[i]); + + kfree(plxdev->desc_ring); + dma_free_coherent(plxdev->dma_dev.dev, ring_sz, plxdev->hw_ring, + plxdev->hw_ring_dma); + +} + + rc = request_irq(pci_irq_vector(pdev, 0), plx_dma_isr, 0, + kbuild_modname, plxdev); + if (rc) { + kfree(plxdev); + return rc; + } + + spin_lock_init(&plxdev->ring_lock); + tasklet_init(&plxdev->desc_task, plx_dma_desc_task, + (unsigned long)plxdev); + + rcu_init_pointer(plxdev->pdev, pdev); + dma->device_alloc_chan_resources = plx_dma_alloc_chan_resources; + dma->device_free_chan_resources = plx_dma_free_chan_resources; + rcu_assign_pointer(plxdev->pdev, null); + synchronize_rcu(); + + spin_lock_bh(&plxdev->ring_lock); + plxdev->ring_active = false; + spin_unlock_bh(&plxdev->ring_lock); + + __plx_dma_stop(plxdev); + plx_dma_abort_desc(plxdev); +
|
DMA engines
|
c2dbcaa8c672d7ecc96c7a62fd6a34c9d3821bdb
|
logan gunthorpe
|
drivers
|
dma
| |
dmaengine: plx-dma: implement descriptor submission
|
on prep, a spin lock is taken and the next entry in the circular buffer is filled. on submit, the valid bit is set in the hardware descriptor and the lock is released.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
plx switch dma engine driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['c']
| 1
| 119
| 0
|
--- diff --git a/drivers/dma/plx_dma.c b/drivers/dma/plx_dma.c --- a/drivers/dma/plx_dma.c +++ b/drivers/dma/plx_dma.c +#include <linux/circ_buf.h> +static struct plx_dma_desc *to_plx_desc(struct dma_async_tx_descriptor *txd) +{ + return container_of(txd, struct plx_dma_desc, txd); +} + +static struct dma_async_tx_descriptor *plx_dma_prep_memcpy(struct dma_chan *c, + dma_addr_t dma_dst, dma_addr_t dma_src, size_t len, + unsigned long flags) + __acquires(plxdev->ring_lock) +{ + struct plx_dma_dev *plxdev = chan_to_plx_dma_dev(c); + struct plx_dma_desc *plxdesc; + + spin_lock_bh(&plxdev->ring_lock); + if (!plxdev->ring_active) + goto err_unlock; + + if (!circ_space(plxdev->head, plxdev->tail, plx_dma_ring_count)) + goto err_unlock; + + if (len > plx_desc_size_mask) + goto err_unlock; + + plxdesc = plx_dma_get_desc(plxdev, plxdev->head); + plxdev->head++; + + plxdesc->hw->dst_addr_lo = cpu_to_le32(lower_32_bits(dma_dst)); + plxdesc->hw->dst_addr_hi = cpu_to_le16(upper_32_bits(dma_dst)); + plxdesc->hw->src_addr_lo = cpu_to_le32(lower_32_bits(dma_src)); + plxdesc->hw->src_addr_hi = cpu_to_le16(upper_32_bits(dma_src)); + + plxdesc->orig_size = len; + + if (flags & dma_prep_interrupt) + len |= plx_desc_flag_int_when_done; + + plxdesc->hw->flags_and_size = cpu_to_le32(len); + plxdesc->txd.flags = flags; + + /* return with the lock held, it will be released in tx_submit */ + + return &plxdesc->txd; + +err_unlock: + /* + * keep sparse happy by restoring an even lock count on + * this lock. + */ + __acquire(plxdev->ring_lock); + + spin_unlock_bh(&plxdev->ring_lock); + return null; +} + +static dma_cookie_t plx_dma_tx_submit(struct dma_async_tx_descriptor *desc) + __releases(plxdev->ring_lock) +{ + struct plx_dma_dev *plxdev = chan_to_plx_dma_dev(desc->chan); + struct plx_dma_desc *plxdesc = to_plx_desc(desc); + dma_cookie_t cookie; + + cookie = dma_cookie_assign(desc); + + /* + * ensure the descriptor updates are visible to the dma device + * before setting the valid bit. + */ + wmb(); + + plxdesc->hw->flags_and_size |= cpu_to_le32(plx_desc_flag_valid); + + spin_unlock_bh(&plxdev->ring_lock); + + return cookie; +} + +static enum dma_status plx_dma_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, struct dma_tx_state *txstate) +{ + struct plx_dma_dev *plxdev = chan_to_plx_dma_dev(chan); + enum dma_status ret; + + ret = dma_cookie_status(chan, cookie, txstate); + if (ret == dma_complete) + return ret; + + plx_dma_process_desc(plxdev); + + return dma_cookie_status(chan, cookie, txstate); +} + +static void plx_dma_issue_pending(struct dma_chan *chan) +{ + struct plx_dma_dev *plxdev = chan_to_plx_dma_dev(chan); + + rcu_read_lock(); + if (!rcu_dereference(plxdev->pdev)) { + rcu_read_unlock(); + return; + } + + /* + * ensure the valid bits are visible before starting the + * dma engine. + */ + wmb(); + + writew(plx_reg_ctrl_start_val, plxdev->bar + plx_reg_ctrl); + + rcu_read_unlock(); +} + + desc->txd.tx_submit = plx_dma_tx_submit; + + dma_cap_set(dma_memcpy, dma->cap_mask); + dma->device_prep_dma_memcpy = plx_dma_prep_memcpy; + dma->device_issue_pending = plx_dma_issue_pending; + dma->device_tx_status = plx_dma_tx_status;
|
DMA engines
|
4d3df16840a2bba5a345326426380e1381d976d2
|
logan gunthorpe
|
drivers
|
dma
| |
dmaengine: sun4i: add support for cyclic requests with dedicated dma
|
currently the cyclic transfers can be used only with normal dmas. they can be used by pcm_dmaengine module, which is required for implementing sound with sun4i-hdmi encoder. this is so because the controller can accept audio only from a dedicated dma.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for cyclic requests with dedicated dma
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['sun4i']
|
['c']
| 1
| 24
| 21
|
--- diff --git a/drivers/dma/sun4i-dma.c b/drivers/dma/sun4i-dma.c --- a/drivers/dma/sun4i-dma.c +++ b/drivers/dma/sun4i-dma.c + u8 ram_type, io_mode, linear_mode; - if (vchan->is_dedicated) { - /* - * as we are using this just for audio data, we need to use - * normal dma. there is nothing stopping us from supporting - * dedicated dma here as well, so if a client comes up and - * requires it, it will be simple to implement it. - */ - dev_err(chan2dev(chan), - "cyclic transfers are only supported on normal dma "); - return null; - } - - /* figure out the endpoints and the address we need */ + if (vchan->is_dedicated) { + io_mode = sun4i_ddma_addr_mode_io; + linear_mode = sun4i_ddma_addr_mode_linear; + ram_type = sun4i_ddma_drq_type_sdram; + } else { + io_mode = sun4i_ndma_addr_mode_io; + linear_mode = sun4i_ndma_addr_mode_linear; + ram_type = sun4i_ndma_drq_type_sdram; + } + - endpoints = sun4i_dma_cfg_src_drq_type(sun4i_ndma_drq_type_sdram) | - sun4i_dma_cfg_dst_drq_type(vchan->endpoint) | - sun4i_dma_cfg_dst_addr_mode(sun4i_ndma_addr_mode_io); + endpoints = sun4i_dma_cfg_dst_drq_type(vchan->endpoint) | + sun4i_dma_cfg_dst_addr_mode(io_mode) | + sun4i_dma_cfg_src_drq_type(ram_type); - endpoints = sun4i_dma_cfg_src_drq_type(vchan->endpoint) | - sun4i_dma_cfg_src_addr_mode(sun4i_ndma_addr_mode_io) | - sun4i_dma_cfg_dst_drq_type(sun4i_ndma_drq_type_sdram); + endpoints = sun4i_dma_cfg_dst_drq_type(ram_type) | + sun4i_dma_cfg_src_drq_type(vchan->endpoint) | + sun4i_dma_cfg_src_addr_mode(io_mode); - promise = generate_ndma_promise(chan, src, dest, - plength, sconfig, dir); + if (vchan->is_dedicated) + promise = generate_ddma_promise(chan, src, dest, + plength, sconfig); + else + promise = generate_ndma_promise(chan, src, dest, + plength, sconfig, dir); +
|
DMA engines
|
ffc079a4accc2bd02758eb93cb8efcb3bfee1891
|
stefan mavrodiev
|
drivers
|
dma
| |
bindings: soc: ti: add documentation for k3 ringacc
|
the ring accelerator (ringacc or ra) provides hardware acceleration to enable straightforward passing of work between a producer and a consumer. there is one ringacc module per navss on ti am65x and j721e.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add texas instruments udma support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['txt']
| 1
| 59
| 0
|
--- diff --git a/documentation/devicetree/bindings/soc/ti/k3-ringacc.txt b/documentation/devicetree/bindings/soc/ti/k3-ringacc.txt --- /dev/null +++ b/documentation/devicetree/bindings/soc/ti/k3-ringacc.txt +* texas instruments k3 navigatorss ring accelerator + +the ring accelerator (ra) is a machine which converts read/write accesses +from/to a constant address into corresponding read/write accesses from/to a +circular data structure in memory. the ra eliminates the need for each dma +controller which needs to access ring elements from having to know the current +state of the ring (base address, current offset). the dma controller +performs a read or write access to a specific address range (which maps to the +source interface on the ra) and the ra replaces the address for the transaction +with a new address which corresponds to the head or tail element of the ring +(head for reads, tail for writes). + +the ring accelerator is a hardware module that is responsible for accelerating +management of the packet queues. the k3 socs can have more than one ra instances + +required properties: +- compatible : must be "ti,am654-navss-ringacc"; +- reg : should contain register location and length of the following + named register regions. +- reg-names : should be + "rt" - the ra ring real-time control/status registers + "fifos" - the ra queues registers + "proxy_gcfg" - the ra proxy global config registers + "proxy_target" - the ra proxy datapath registers +- ti,num-rings : number of rings supported by ra +- ti,sci-rm-range-gp-rings : ti-sci rm subtype for gp ring range +- ti,sci : phandle on ti-sci compatible system controller node +- ti,sci-dev-id : ti-sci device id of the ring accelerator +- msi-parent : phandle for "ti,sci-inta" interrupt controller + +optional properties: + -- ti,dma-ring-reset-quirk : enable ringacc / udma ring state interoperability + issue software w/a + +example: + +ringacc: ringacc@3c000000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x0 0x3c000000 0x0 0x400000>, + <0x0 0x38000000 0x0 0x400000>, + <0x0 0x31120000 0x0 0x100>, + <0x0 0x33000000 0x0 0x40000>; + reg-names = "rt", "fifos", + "proxy_gcfg", "proxy_target"; + ti,num-rings = <818>; + ti,sci-rm-range-gp-rings = <0x2>; /* gp ring range */ + ti,dma-ring-reset-quirk; + ti,sci = <&dmsc>; + ti,sci-dev-id = <187>; + msi-parent = <&inta_main_udmass>; +}; + +client: + +dma_ipx: dma_ipx@<addr> { + ... + ti,ringacc = <&ringacc>; + ... +}
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DMA engines
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59be028f811bb9caf3079a5873602c6e333d8ddf
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grygorii strashko
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documentation
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devicetree
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bindings, soc, ti
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soc: ti: k3: add navss ringacc driver
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the ring accelerator (ringacc or ra) provides hardware acceleration to enable straightforward passing of work between a producer and a consumer. there is one ringacc module per navss on ti am65x socs.
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this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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add texas instruments udma support
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
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[]
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['c', 'kconfig', 'makefile', 'h']
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- ring mode - messaging mode - credentials mode - queue manager mode - ti,sci: phandle on ti-sci firmware controller dt node - ti,sci-dev-id: ti-sci device identifier as per ti-sci firmware spec --- diff --git a/drivers/soc/ti/kconfig b/drivers/soc/ti/kconfig --- a/drivers/soc/ti/kconfig +++ b/drivers/soc/ti/kconfig +config ti_k3_ringacc + bool "k3 ring accelerator sub system" + depends on arch_k3 || compile_test + depends on ti_sci_inta_irqchip + help + say y here to support the k3 ring accelerator module. + the ring accelerator (ringacc or ra) provides hardware acceleration + to enable straightforward passing of work between a producer + and a consumer. there is one ringacc module per navss on ti am65x socs + if unsure, say n. + diff --git a/drivers/soc/ti/makefile b/drivers/soc/ti/makefile --- a/drivers/soc/ti/makefile +++ b/drivers/soc/ti/makefile +obj-$(config_ti_k3_ringacc) += k3-ringacc.o diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c --- /dev/null +++ b/drivers/soc/ti/k3-ringacc.c +// spdx-license-identifier: gpl-2.0 +/* + * ti k3 navss ring accelerator subsystem driver + * + * copyright (c) 2019 texas instruments incorporated - http://www.ti.com + */ + +#include <linux/dma-mapping.h> +#include <linux/io.h> +#include <linux/init.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/soc/ti/k3-ringacc.h> +#include <linux/soc/ti/ti_sci_protocol.h> +#include <linux/soc/ti/ti_sci_inta_msi.h> +#include <linux/of_irq.h> +#include <linux/irqdomain.h> + +static list_head(k3_ringacc_list); +static define_mutex(k3_ringacc_list_lock); + +#define k3_ringacc_cfg_ring_size_elcnt_mask genmask(19, 0) + +/** + * struct k3_ring_rt_regs - the ra realtime control/status registers region + * + * @resv_16: reserved + * @db: ring doorbell register + * @resv_4: reserved + * @occ: ring occupancy register + * @indx: ring current index register + * @hwocc: ring hardware occupancy register + * @hwindx: ring hardware current index register + */ +struct k3_ring_rt_regs { + u32 resv_16[4]; + u32 db; + u32 resv_4[1]; + u32 occ; + u32 indx; + u32 hwocc; + u32 hwindx; +}; + +#define k3_ringacc_rt_regs_step 0x1000 + +/** + * struct k3_ring_fifo_regs - the ring accelerator queues registers region + * + * @head_data: ring head entry data registers + * @tail_data: ring tail entry data registers + * @peek_head_data: ring peek head entry data regs + * @peek_tail_data: ring peek tail entry data regs + */ +struct k3_ring_fifo_regs { + u32 head_data[128]; + u32 tail_data[128]; + u32 peek_head_data[128]; + u32 peek_tail_data[128]; +}; + +/** + * struct k3_ringacc_proxy_gcfg_regs - ra proxy global config mmio region + * + * @revision: revision register + * @config: config register + */ +struct k3_ringacc_proxy_gcfg_regs { + u32 revision; + u32 config; +}; + +#define k3_ringacc_proxy_cfg_threads_mask genmask(15, 0) + +/** + * struct k3_ringacc_proxy_target_regs - proxy datapath mmio region + * + * @control: proxy control register + * @status: proxy status register + * @resv_512: reserved + * @data: proxy data register + */ +struct k3_ringacc_proxy_target_regs { + u32 control; + u32 status; + u8 resv_512[504]; + u32 data[128]; +}; + +#define k3_ringacc_proxy_target_step 0x1000 +#define k3_ringacc_proxy_not_used (-1) + +enum k3_ringacc_proxy_access_mode { + proxy_access_mode_head = 0, + proxy_access_mode_tail = 1, + proxy_access_mode_peek_head = 2, + proxy_access_mode_peek_tail = 3, +}; + +#define k3_ringacc_fifo_window_size_bytes (512u) +#define k3_ringacc_fifo_regs_step 0x1000 +#define k3_ringacc_max_db_ring_cnt (127u) + +struct k3_ring_ops { + int (*push_tail)(struct k3_ring *ring, void *elm); + int (*push_head)(struct k3_ring *ring, void *elm); + int (*pop_tail)(struct k3_ring *ring, void *elm); + int (*pop_head)(struct k3_ring *ring, void *elm); +}; + +/** + * struct k3_ring - ra ring descriptor + * + * @rt: ring control/status registers + * @fifos: ring queues registers + * @proxy: ring proxy datapath registers + * @ring_mem_dma: ring buffer dma address + * @ring_mem_virt: ring buffer virt address + * @ops: ring operations + * @size: ring size in elements + * @elm_size: size of the ring element + * @mode: ring mode + * @flags: flags + * @free: number of free elements + * @occ: ring occupancy + * @windex: write index (only for @k3_ringacc_ring_mode_ring) + * @rindex: read index (only for @k3_ringacc_ring_mode_ring) + * @ring_id: ring id + * @parent: pointer on struct @k3_ringacc + * @use_count: use count for shared rings + * @proxy_id: ra ring proxy id (only if @k3_ringacc_ring_use_proxy) + */ +struct k3_ring { + struct k3_ring_rt_regs __iomem *rt; + struct k3_ring_fifo_regs __iomem *fifos; + struct k3_ringacc_proxy_target_regs __iomem *proxy; + dma_addr_t ring_mem_dma; + void *ring_mem_virt; + struct k3_ring_ops *ops; + u32 size; + enum k3_ring_size elm_size; + enum k3_ring_mode mode; + u32 flags; +#define k3_ring_flag_busy bit(1) +#define k3_ring_flag_shared bit(2) + u32 free; + u32 occ; + u32 windex; + u32 rindex; + u32 ring_id; + struct k3_ringacc *parent; + u32 use_count; + int proxy_id; +}; + +/** + * struct k3_ringacc - rings accelerator descriptor + * + * @dev: pointer on ra device + * @proxy_gcfg: ra proxy global config registers + * @proxy_target_base: ra proxy datapath region + * @num_rings: number of ring in ra + * @rings_inuse: bitfield for ring usage tracking + * @rm_gp_range: general purpose rings range from tisci + * @dma_ring_reset_quirk: dma reset w/a enable + * @num_proxies: number of ra proxies + * @proxy_inuse: bitfield for proxy usage tracking + * @rings: array of rings descriptors (struct @k3_ring) + * @list: list of ras in the system + * @req_lock: protect rings allocation + * @tisci: pointer ti-sci handle + * @tisci_ring_ops: ti-sci rings ops + * @tisci_dev_id: ti-sci device id + */ +struct k3_ringacc { + struct device *dev; + struct k3_ringacc_proxy_gcfg_regs __iomem *proxy_gcfg; + void __iomem *proxy_target_base; + u32 num_rings; /* number of rings in ringacc module */ + unsigned long *rings_inuse; + struct ti_sci_resource *rm_gp_range; + + bool dma_ring_reset_quirk; + u32 num_proxies; + unsigned long *proxy_inuse; + + struct k3_ring *rings; + struct list_head list; + struct mutex req_lock; /* protect rings allocation */ + + const struct ti_sci_handle *tisci; + const struct ti_sci_rm_ringacc_ops *tisci_ring_ops; + u32 tisci_dev_id; +}; + +static long k3_ringacc_ring_get_fifo_pos(struct k3_ring *ring) +{ + return k3_ringacc_fifo_window_size_bytes - + (4 << ring->elm_size); +} + +static void *k3_ringacc_get_elm_addr(struct k3_ring *ring, u32 idx) +{ + return (ring->ring_mem_virt + idx * (4 << ring->elm_size)); +} + +static int k3_ringacc_ring_push_mem(struct k3_ring *ring, void *elem); +static int k3_ringacc_ring_pop_mem(struct k3_ring *ring, void *elem); + +static struct k3_ring_ops k3_ring_mode_ring_ops = { + .push_tail = k3_ringacc_ring_push_mem, + .pop_head = k3_ringacc_ring_pop_mem, +}; + +static int k3_ringacc_ring_push_io(struct k3_ring *ring, void *elem); +static int k3_ringacc_ring_pop_io(struct k3_ring *ring, void *elem); +static int k3_ringacc_ring_push_head_io(struct k3_ring *ring, void *elem); +static int k3_ringacc_ring_pop_tail_io(struct k3_ring *ring, void *elem); + +static struct k3_ring_ops k3_ring_mode_msg_ops = { + .push_tail = k3_ringacc_ring_push_io, + .push_head = k3_ringacc_ring_push_head_io, + .pop_tail = k3_ringacc_ring_pop_tail_io, + .pop_head = k3_ringacc_ring_pop_io, +}; + +static int k3_ringacc_ring_push_head_proxy(struct k3_ring *ring, void *elem); +static int k3_ringacc_ring_push_tail_proxy(struct k3_ring *ring, void *elem); +static int k3_ringacc_ring_pop_head_proxy(struct k3_ring *ring, void *elem); +static int k3_ringacc_ring_pop_tail_proxy(struct k3_ring *ring, void *elem); + +static struct k3_ring_ops k3_ring_mode_proxy_ops = { + .push_tail = k3_ringacc_ring_push_tail_proxy, + .push_head = k3_ringacc_ring_push_head_proxy, + .pop_tail = k3_ringacc_ring_pop_tail_proxy, + .pop_head = k3_ringacc_ring_pop_head_proxy, +}; + +static void k3_ringacc_ring_dump(struct k3_ring *ring) +{ + struct device *dev = ring->parent->dev; + + dev_dbg(dev, "dump ring: %d ", ring->ring_id); + dev_dbg(dev, "dump mem virt %p, dma %pad ", ring->ring_mem_virt, + &ring->ring_mem_dma); + dev_dbg(dev, "dump elmsize %d, size %d, mode %d, proxy_id %d ", + ring->elm_size, ring->size, ring->mode, ring->proxy_id); + + dev_dbg(dev, "dump ring_rt_regs: db%08x ", readl(&ring->rt->db)); + dev_dbg(dev, "dump occ%08x ", readl(&ring->rt->occ)); + dev_dbg(dev, "dump indx%08x ", readl(&ring->rt->indx)); + dev_dbg(dev, "dump hwocc%08x ", readl(&ring->rt->hwocc)); + dev_dbg(dev, "dump hwindx%08x ", readl(&ring->rt->hwindx)); + + if (ring->ring_mem_virt) + print_hex_dump_debug("dump ring_mem_virt ", dump_prefix_none, + 16, 1, ring->ring_mem_virt, 16 * 8, false); +} + +struct k3_ring *k3_ringacc_request_ring(struct k3_ringacc *ringacc, + int id, u32 flags) +{ + int proxy_id = k3_ringacc_proxy_not_used; + + mutex_lock(&ringacc->req_lock); + + if (id == k3_ringacc_ring_id_any) { + /* request for any general purpose ring */ + struct ti_sci_resource_desc *gp_rings = + &ringacc->rm_gp_range->desc[0]; + unsigned long size; + + size = gp_rings->start + gp_rings->num; + id = find_next_zero_bit(ringacc->rings_inuse, size, + gp_rings->start); + if (id == size) + goto error; + } else if (id < 0) { + goto error; + } + + if (test_bit(id, ringacc->rings_inuse) && + !(ringacc->rings[id].flags & k3_ring_flag_shared)) + goto error; + else if (ringacc->rings[id].flags & k3_ring_flag_shared) + goto out; + + if (flags & k3_ringacc_ring_use_proxy) { + proxy_id = find_next_zero_bit(ringacc->proxy_inuse, + ringacc->num_proxies, 0); + if (proxy_id == ringacc->num_proxies) + goto error; + } + + if (proxy_id != k3_ringacc_proxy_not_used) { + set_bit(proxy_id, ringacc->proxy_inuse); + ringacc->rings[id].proxy_id = proxy_id; + dev_dbg(ringacc->dev, "giving ring#%d proxy#%d ", id, + proxy_id); + } else { + dev_dbg(ringacc->dev, "giving ring#%d ", id); + } + + set_bit(id, ringacc->rings_inuse); +out: + ringacc->rings[id].use_count++; + mutex_unlock(&ringacc->req_lock); + return &ringacc->rings[id]; + +error: + mutex_unlock(&ringacc->req_lock); + return null; +} +export_symbol_gpl(k3_ringacc_request_ring); + +static void k3_ringacc_ring_reset_sci(struct k3_ring *ring) +{ + struct k3_ringacc *ringacc = ring->parent; + int ret; + + ret = ringacc->tisci_ring_ops->config( + ringacc->tisci, + ti_sci_msg_value_rm_ring_count_valid, + ringacc->tisci_dev_id, + ring->ring_id, + 0, + 0, + ring->size, + 0, + 0, + 0); + if (ret) + dev_err(ringacc->dev, "tisci reset ring fail (%d) ring_idx %d ", + ret, ring->ring_id); +} + +void k3_ringacc_ring_reset(struct k3_ring *ring) +{ + if (!ring || !(ring->flags & k3_ring_flag_busy)) + return; + + ring->occ = 0; + ring->free = 0; + ring->rindex = 0; + ring->windex = 0; + + k3_ringacc_ring_reset_sci(ring); +} +export_symbol_gpl(k3_ringacc_ring_reset); + +static void k3_ringacc_ring_reconfig_qmode_sci(struct k3_ring *ring, + enum k3_ring_mode mode) +{ + struct k3_ringacc *ringacc = ring->parent; + int ret; + + ret = ringacc->tisci_ring_ops->config( + ringacc->tisci, + ti_sci_msg_value_rm_ring_mode_valid, + ringacc->tisci_dev_id, + ring->ring_id, + 0, + 0, + 0, + mode, + 0, + 0); + if (ret) + dev_err(ringacc->dev, "tisci reconf qmode fail (%d) ring_idx %d ", + ret, ring->ring_id); +} + +void k3_ringacc_ring_reset_dma(struct k3_ring *ring, u32 occ) +{ + if (!ring || !(ring->flags & k3_ring_flag_busy)) + return; + + if (!ring->parent->dma_ring_reset_quirk) + goto reset; + + if (!occ) + occ = readl(&ring->rt->occ); + + if (occ) { + u32 db_ring_cnt, db_ring_cnt_cur; + + dev_dbg(ring->parent->dev, "%s %u occ: %u ", __func__, + ring->ring_id, occ); + /* ti-sci ring reset */ + k3_ringacc_ring_reset_sci(ring); + + /* + * setup the ring in ring/doorbell mode (if not already in this + * mode) + */ + if (ring->mode != k3_ringacc_ring_mode_ring) + k3_ringacc_ring_reconfig_qmode_sci( + ring, k3_ringacc_ring_mode_ring); + /* + * ring the doorbell 2**22 ringocc times. + * this will wrap the internal udmap ring state occupancy + * counter (which is 21-bits wide) to 0. + */ + db_ring_cnt = (1u << 22) - occ; + + while (db_ring_cnt != 0) { + /* + * ring the doorbell with the maximum count each + * iteration if possible to minimize the total + * of writes + */ + if (db_ring_cnt > k3_ringacc_max_db_ring_cnt) + db_ring_cnt_cur = k3_ringacc_max_db_ring_cnt; + else + db_ring_cnt_cur = db_ring_cnt; + + writel(db_ring_cnt_cur, &ring->rt->db); + db_ring_cnt -= db_ring_cnt_cur; + } + + /* restore the original ring mode (if not ring mode) */ + if (ring->mode != k3_ringacc_ring_mode_ring) + k3_ringacc_ring_reconfig_qmode_sci(ring, ring->mode); + } + +reset: + /* reset the ring */ + k3_ringacc_ring_reset(ring); +} +export_symbol_gpl(k3_ringacc_ring_reset_dma); + +static void k3_ringacc_ring_free_sci(struct k3_ring *ring) +{ + struct k3_ringacc *ringacc = ring->parent; + int ret; + + ret = ringacc->tisci_ring_ops->config( + ringacc->tisci, + ti_sci_msg_value_rm_all_no_order, + ringacc->tisci_dev_id, + ring->ring_id, + 0, + 0, + 0, + 0, + 0, + 0); + if (ret) + dev_err(ringacc->dev, "tisci ring free fail (%d) ring_idx %d ", + ret, ring->ring_id); +} + +int k3_ringacc_ring_free(struct k3_ring *ring) +{ + struct k3_ringacc *ringacc; + + if (!ring) + return -einval; + + ringacc = ring->parent; + + dev_dbg(ring->parent->dev, "flags: 0x%08x ", ring->flags); + + if (!test_bit(ring->ring_id, ringacc->rings_inuse)) + return -einval; + + mutex_lock(&ringacc->req_lock); + + if (--ring->use_count) + goto out; + + if (!(ring->flags & k3_ring_flag_busy)) + goto no_init; + + k3_ringacc_ring_free_sci(ring); + + dma_free_coherent(ringacc->dev, + ring->size * (4 << ring->elm_size), + ring->ring_mem_virt, ring->ring_mem_dma); + ring->flags = 0; + ring->ops = null; + if (ring->proxy_id != k3_ringacc_proxy_not_used) { + clear_bit(ring->proxy_id, ringacc->proxy_inuse); + ring->proxy = null; + ring->proxy_id = k3_ringacc_proxy_not_used; + } + +no_init: + clear_bit(ring->ring_id, ringacc->rings_inuse); + +out: + mutex_unlock(&ringacc->req_lock); + return 0; +} +export_symbol_gpl(k3_ringacc_ring_free); + +u32 k3_ringacc_get_ring_id(struct k3_ring *ring) +{ + if (!ring) + return -einval; + + return ring->ring_id; +} +export_symbol_gpl(k3_ringacc_get_ring_id); + +u32 k3_ringacc_get_tisci_dev_id(struct k3_ring *ring) +{ + if (!ring) + return -einval; + + return ring->parent->tisci_dev_id; +} +export_symbol_gpl(k3_ringacc_get_tisci_dev_id); + +int k3_ringacc_get_ring_irq_num(struct k3_ring *ring) +{ + int irq_num; + + if (!ring) + return -einval; + + irq_num = ti_sci_inta_msi_get_virq(ring->parent->dev, ring->ring_id); + if (irq_num <= 0) + irq_num = -einval; + return irq_num; +} +export_symbol_gpl(k3_ringacc_get_ring_irq_num); + +static int k3_ringacc_ring_cfg_sci(struct k3_ring *ring) +{ + struct k3_ringacc *ringacc = ring->parent; + u32 ring_idx; + int ret; + + if (!ringacc->tisci) + return -einval; + + ring_idx = ring->ring_id; + ret = ringacc->tisci_ring_ops->config( + ringacc->tisci, + ti_sci_msg_value_rm_all_no_order, + ringacc->tisci_dev_id, + ring_idx, + lower_32_bits(ring->ring_mem_dma), + upper_32_bits(ring->ring_mem_dma), + ring->size, + ring->mode, + ring->elm_size, + 0); + if (ret) + dev_err(ringacc->dev, "tisci config ring fail (%d) ring_idx %d ", + ret, ring_idx); + + return ret; +} + +int k3_ringacc_ring_cfg(struct k3_ring *ring, struct k3_ring_cfg *cfg) +{ + struct k3_ringacc *ringacc = ring->parent; + int ret = 0; + + if (!ring || !cfg) + return -einval; + if (cfg->elm_size > k3_ringacc_ring_elsize_256 || + cfg->mode >= k3_ringacc_ring_mode_invalid || + cfg->size & ~k3_ringacc_cfg_ring_size_elcnt_mask || + !test_bit(ring->ring_id, ringacc->rings_inuse)) + return -einval; + + if (cfg->mode == k3_ringacc_ring_mode_message && + ring->proxy_id == k3_ringacc_proxy_not_used && + cfg->elm_size > k3_ringacc_ring_elsize_8) { + dev_err(ringacc->dev, + "message mode must use proxy for %u element size ", + 4 << ring->elm_size); + return -einval; + } + + /* + * in case of shared ring only the first user (master user) can + * configure the ring. the sequence should be by the client: + * ring = k3_ringacc_request_ring(ringacc, ring_id, 0); # master user + * k3_ringacc_ring_cfg(ring, cfg); # master configuration + * k3_ringacc_request_ring(ringacc, ring_id, k3_ring_flag_shared); + * k3_ringacc_request_ring(ringacc, ring_id, k3_ring_flag_shared); + */ + if (ring->use_count != 1) + return 0; + + ring->size = cfg->size; + ring->elm_size = cfg->elm_size; + ring->mode = cfg->mode; + ring->occ = 0; + ring->free = 0; + ring->rindex = 0; + ring->windex = 0; + + if (ring->proxy_id != k3_ringacc_proxy_not_used) + ring->proxy = ringacc->proxy_target_base + + ring->proxy_id * k3_ringacc_proxy_target_step; + + switch (ring->mode) { + case k3_ringacc_ring_mode_ring: + ring->ops = &k3_ring_mode_ring_ops; + break; + case k3_ringacc_ring_mode_message: + if (ring->proxy) + ring->ops = &k3_ring_mode_proxy_ops; + else + ring->ops = &k3_ring_mode_msg_ops; + break; + default: + ring->ops = null; + ret = -einval; + goto err_free_proxy; + }; + + ring->ring_mem_virt = dma_alloc_coherent(ringacc->dev, + ring->size * (4 << ring->elm_size), + &ring->ring_mem_dma, gfp_kernel); + if (!ring->ring_mem_virt) { + dev_err(ringacc->dev, "failed to alloc ring mem "); + ret = -enomem; + goto err_free_ops; + } + + ret = k3_ringacc_ring_cfg_sci(ring); + + if (ret) + goto err_free_mem; + + ring->flags |= k3_ring_flag_busy; + ring->flags |= (cfg->flags & k3_ringacc_ring_shared) ? + k3_ring_flag_shared : 0; + + k3_ringacc_ring_dump(ring); + + return 0; + +err_free_mem: + dma_free_coherent(ringacc->dev, + ring->size * (4 << ring->elm_size), + ring->ring_mem_virt, + ring->ring_mem_dma); +err_free_ops: + ring->ops = null; +err_free_proxy: + ring->proxy = null; + return ret; +} +export_symbol_gpl(k3_ringacc_ring_cfg); + +u32 k3_ringacc_ring_get_size(struct k3_ring *ring) +{ + if (!ring || !(ring->flags & k3_ring_flag_busy)) + return -einval; + + return ring->size; +} +export_symbol_gpl(k3_ringacc_ring_get_size); + +u32 k3_ringacc_ring_get_free(struct k3_ring *ring) +{ + if (!ring || !(ring->flags & k3_ring_flag_busy)) + return -einval; + + if (!ring->free) + ring->free = ring->size - readl(&ring->rt->occ); + + return ring->free; +} +export_symbol_gpl(k3_ringacc_ring_get_free); + +u32 k3_ringacc_ring_get_occ(struct k3_ring *ring) +{ + if (!ring || !(ring->flags & k3_ring_flag_busy)) + return -einval; + + return readl(&ring->rt->occ); +} +export_symbol_gpl(k3_ringacc_ring_get_occ); + +u32 k3_ringacc_ring_is_full(struct k3_ring *ring) +{ + return !k3_ringacc_ring_get_free(ring); +} +export_symbol_gpl(k3_ringacc_ring_is_full); + +enum k3_ringacc_access_mode { + k3_ringacc_access_mode_push_head, + k3_ringacc_access_mode_pop_head, + k3_ringacc_access_mode_push_tail, + k3_ringacc_access_mode_pop_tail, + k3_ringacc_access_mode_peek_head, + k3_ringacc_access_mode_peek_tail, +}; + +#define k3_ringacc_proxy_mode(x) (((x) & 0x3) << 16) +#define k3_ringacc_proxy_elsize(x) (((x) & 0x7) << 24) +static int k3_ringacc_ring_cfg_proxy(struct k3_ring *ring, + enum k3_ringacc_proxy_access_mode mode) +{ + u32 val; + + val = ring->ring_id; + val |= k3_ringacc_proxy_mode(mode); + val |= k3_ringacc_proxy_elsize(ring->elm_size); + writel(val, &ring->proxy->control); + return 0; +} + +static int k3_ringacc_ring_access_proxy(struct k3_ring *ring, void *elem, + enum k3_ringacc_access_mode access_mode) +{ + void __iomem *ptr; + + ptr = (void __iomem *)&ring->proxy->data; + + switch (access_mode) { + case k3_ringacc_access_mode_push_head: + case k3_ringacc_access_mode_pop_head: + k3_ringacc_ring_cfg_proxy(ring, proxy_access_mode_head); + break; + case k3_ringacc_access_mode_push_tail: + case k3_ringacc_access_mode_pop_tail: + k3_ringacc_ring_cfg_proxy(ring, proxy_access_mode_tail); + break; + default: + return -einval; + } + + ptr += k3_ringacc_ring_get_fifo_pos(ring); + + switch (access_mode) { + case k3_ringacc_access_mode_pop_head: + case k3_ringacc_access_mode_pop_tail: + dev_dbg(ring->parent->dev, + "proxy:memcpy_fromio(x): --> ptr(%p), mode:%d ", ptr, + access_mode); + memcpy_fromio(elem, ptr, (4 << ring->elm_size)); + ring->occ--; + break; + case k3_ringacc_access_mode_push_tail: + case k3_ringacc_access_mode_push_head: + dev_dbg(ring->parent->dev, + "proxy:memcpy_toio(x): --> ptr(%p), mode:%d ", ptr, + access_mode); + memcpy_toio(ptr, elem, (4 << ring->elm_size)); + ring->free--; + break; + default: + return -einval; + } + + dev_dbg(ring->parent->dev, "proxy: free%d occ%d ", ring->free, + ring->occ); + return 0; +} + +static int k3_ringacc_ring_push_head_proxy(struct k3_ring *ring, void *elem) +{ + return k3_ringacc_ring_access_proxy(ring, elem, + k3_ringacc_access_mode_push_head); +} + +static int k3_ringacc_ring_push_tail_proxy(struct k3_ring *ring, void *elem) +{ + return k3_ringacc_ring_access_proxy(ring, elem, + k3_ringacc_access_mode_push_tail); +} + +static int k3_ringacc_ring_pop_head_proxy(struct k3_ring *ring, void *elem) +{ + return k3_ringacc_ring_access_proxy(ring, elem, + k3_ringacc_access_mode_pop_head); +} + +static int k3_ringacc_ring_pop_tail_proxy(struct k3_ring *ring, void *elem) +{ + return k3_ringacc_ring_access_proxy(ring, elem, + k3_ringacc_access_mode_pop_head); +} + +static int k3_ringacc_ring_access_io(struct k3_ring *ring, void *elem, + enum k3_ringacc_access_mode access_mode) +{ + void __iomem *ptr; + + switch (access_mode) { + case k3_ringacc_access_mode_push_head: + case k3_ringacc_access_mode_pop_head: + ptr = (void __iomem *)&ring->fifos->head_data; + break; + case k3_ringacc_access_mode_push_tail: + case k3_ringacc_access_mode_pop_tail: + ptr = (void __iomem *)&ring->fifos->tail_data; + break; + default: + return -einval; + } + + ptr += k3_ringacc_ring_get_fifo_pos(ring); + + switch (access_mode) { + case k3_ringacc_access_mode_pop_head: + case k3_ringacc_access_mode_pop_tail: + dev_dbg(ring->parent->dev, + "memcpy_fromio(x): --> ptr(%p), mode:%d ", ptr, + access_mode); + memcpy_fromio(elem, ptr, (4 << ring->elm_size)); + ring->occ--; + break; + case k3_ringacc_access_mode_push_tail: + case k3_ringacc_access_mode_push_head: + dev_dbg(ring->parent->dev, + "memcpy_toio(x): --> ptr(%p), mode:%d ", ptr, + access_mode); + memcpy_toio(ptr, elem, (4 << ring->elm_size)); + ring->free--; + break; + default: + return -einval; + } + + dev_dbg(ring->parent->dev, "free%d index%d occ%d index%d ", ring->free, + ring->windex, ring->occ, ring->rindex); + return 0; +} + +static int k3_ringacc_ring_push_head_io(struct k3_ring *ring, void *elem) +{ + return k3_ringacc_ring_access_io(ring, elem, + k3_ringacc_access_mode_push_head); +} + +static int k3_ringacc_ring_push_io(struct k3_ring *ring, void *elem) +{ + return k3_ringacc_ring_access_io(ring, elem, + k3_ringacc_access_mode_push_tail); +} + +static int k3_ringacc_ring_pop_io(struct k3_ring *ring, void *elem) +{ + return k3_ringacc_ring_access_io(ring, elem, + k3_ringacc_access_mode_pop_head); +} + +static int k3_ringacc_ring_pop_tail_io(struct k3_ring *ring, void *elem) +{ + return k3_ringacc_ring_access_io(ring, elem, + k3_ringacc_access_mode_pop_head); +} + +static int k3_ringacc_ring_push_mem(struct k3_ring *ring, void *elem) +{ + void *elem_ptr; + + elem_ptr = k3_ringacc_get_elm_addr(ring, ring->windex); + + memcpy(elem_ptr, elem, (4 << ring->elm_size)); + + ring->windex = (ring->windex + 1) % ring->size; + ring->free--; + writel(1, &ring->rt->db); + + dev_dbg(ring->parent->dev, "ring_push_mem: free%d index%d ", + ring->free, ring->windex); + + return 0; +} + +static int k3_ringacc_ring_pop_mem(struct k3_ring *ring, void *elem) +{ + void *elem_ptr; + + elem_ptr = k3_ringacc_get_elm_addr(ring, ring->rindex); + + memcpy(elem, elem_ptr, (4 << ring->elm_size)); + + ring->rindex = (ring->rindex + 1) % ring->size; + ring->occ--; + writel(-1, &ring->rt->db); + + dev_dbg(ring->parent->dev, "ring_pop_mem: occ%d index%d pos_ptr%p ", + ring->occ, ring->rindex, elem_ptr); + return 0; +} + +int k3_ringacc_ring_push(struct k3_ring *ring, void *elem) +{ + int ret = -eopnotsupp; + + if (!ring || !(ring->flags & k3_ring_flag_busy)) + return -einval; + + dev_dbg(ring->parent->dev, "ring_push: free%d index%d ", ring->free, + ring->windex); + + if (k3_ringacc_ring_is_full(ring)) + return -enomem; + + if (ring->ops && ring->ops->push_tail) + ret = ring->ops->push_tail(ring, elem); + + return ret; +} +export_symbol_gpl(k3_ringacc_ring_push); + +int k3_ringacc_ring_push_head(struct k3_ring *ring, void *elem) +{ + int ret = -eopnotsupp; + + if (!ring || !(ring->flags & k3_ring_flag_busy)) + return -einval; + + dev_dbg(ring->parent->dev, "ring_push_head: free%d index%d ", + ring->free, ring->windex); + + if (k3_ringacc_ring_is_full(ring)) + return -enomem; + + if (ring->ops && ring->ops->push_head) + ret = ring->ops->push_head(ring, elem); + + return ret; +} +export_symbol_gpl(k3_ringacc_ring_push_head); + +int k3_ringacc_ring_pop(struct k3_ring *ring, void *elem) +{ + int ret = -eopnotsupp; + + if (!ring || !(ring->flags & k3_ring_flag_busy)) + return -einval; + + if (!ring->occ) + ring->occ = k3_ringacc_ring_get_occ(ring); + + dev_dbg(ring->parent->dev, "ring_pop: occ%d index%d ", ring->occ, + ring->rindex); + + if (!ring->occ) + return -enodata; + + if (ring->ops && ring->ops->pop_head) + ret = ring->ops->pop_head(ring, elem); + + return ret; +} +export_symbol_gpl(k3_ringacc_ring_pop); + +int k3_ringacc_ring_pop_tail(struct k3_ring *ring, void *elem) +{ + int ret = -eopnotsupp; + + if (!ring || !(ring->flags & k3_ring_flag_busy)) + return -einval; + + if (!ring->occ) + ring->occ = k3_ringacc_ring_get_occ(ring); + + dev_dbg(ring->parent->dev, "ring_pop_tail: occ%d index%d ", ring->occ, + ring->rindex); + + if (!ring->occ) + return -enodata; + + if (ring->ops && ring->ops->pop_tail) + ret = ring->ops->pop_tail(ring, elem); + + return ret; +} +export_symbol_gpl(k3_ringacc_ring_pop_tail); + +struct k3_ringacc *of_k3_ringacc_get_by_phandle(struct device_node *np, + const char *property) +{ + struct device_node *ringacc_np; + struct k3_ringacc *ringacc = err_ptr(-eprobe_defer); + struct k3_ringacc *entry; + + ringacc_np = of_parse_phandle(np, property, 0); + if (!ringacc_np) + return err_ptr(-enodev); + + mutex_lock(&k3_ringacc_list_lock); + list_for_each_entry(entry, &k3_ringacc_list, list) + if (entry->dev->of_node == ringacc_np) { + ringacc = entry; + break; + } + mutex_unlock(&k3_ringacc_list_lock); + of_node_put(ringacc_np); + + return ringacc; +} +export_symbol_gpl(of_k3_ringacc_get_by_phandle); + +static int k3_ringacc_probe_dt(struct k3_ringacc *ringacc) +{ + struct device_node *node = ringacc->dev->of_node; + struct device *dev = ringacc->dev; + struct platform_device *pdev = to_platform_device(dev); + int ret; + + if (!node) { + dev_err(dev, "device tree info unavailable "); + return -enodev; + } + + ret = of_property_read_u32(node, "ti,num-rings", &ringacc->num_rings); + if (ret) { + dev_err(dev, "ti,num-rings read failure %d ", ret); + return ret; + } + + ringacc->dma_ring_reset_quirk = + of_property_read_bool(node, "ti,dma-ring-reset-quirk"); + + ringacc->tisci = ti_sci_get_by_phandle(node, "ti,sci"); + if (is_err(ringacc->tisci)) { + ret = ptr_err(ringacc->tisci); + if (ret != -eprobe_defer) + dev_err(dev, "ti,sci read fail %d ", ret); + ringacc->tisci = null; + return ret; + } + + ret = of_property_read_u32(node, "ti,sci-dev-id", + &ringacc->tisci_dev_id); + if (ret) { + dev_err(dev, "ti,sci-dev-id read fail %d ", ret); + return ret; + } + + pdev->id = ringacc->tisci_dev_id; + + ringacc->rm_gp_range = devm_ti_sci_get_of_resource(ringacc->tisci, dev, + ringacc->tisci_dev_id, + "ti,sci-rm-range-gp-rings"); + if (is_err(ringacc->rm_gp_range)) { + dev_err(dev, "failed to allocate msi interrupts "); + return ptr_err(ringacc->rm_gp_range); + } + + return ti_sci_inta_msi_domain_alloc_irqs(ringacc->dev, + ringacc->rm_gp_range); +} + +static int k3_ringacc_probe(struct platform_device *pdev) +{ + struct k3_ringacc *ringacc; + void __iomem *base_fifo, *base_rt; + struct device *dev = &pdev->dev; + struct resource *res; + int ret, i; + + ringacc = devm_kzalloc(dev, sizeof(*ringacc), gfp_kernel); + if (!ringacc) + return -enomem; + + ringacc->dev = dev; + mutex_init(&ringacc->req_lock); + + dev->msi_domain = of_msi_get_domain(dev, dev->of_node, + domain_bus_ti_sci_inta_msi); + if (!dev->msi_domain) { + dev_err(dev, "failed to get msi domain "); + return -eprobe_defer; + } + + ret = k3_ringacc_probe_dt(ringacc); + if (ret) + return ret; + + res = platform_get_resource_byname(pdev, ioresource_mem, "rt"); + base_rt = devm_ioremap_resource(dev, res); + if (is_err(base_rt)) + return ptr_err(base_rt); + + res = platform_get_resource_byname(pdev, ioresource_mem, "fifos"); + base_fifo = devm_ioremap_resource(dev, res); + if (is_err(base_fifo)) + return ptr_err(base_fifo); + + res = platform_get_resource_byname(pdev, ioresource_mem, "proxy_gcfg"); + ringacc->proxy_gcfg = devm_ioremap_resource(dev, res); + if (is_err(ringacc->proxy_gcfg)) + return ptr_err(ringacc->proxy_gcfg); + + res = platform_get_resource_byname(pdev, ioresource_mem, + "proxy_target"); + ringacc->proxy_target_base = devm_ioremap_resource(dev, res); + if (is_err(ringacc->proxy_target_base)) + return ptr_err(ringacc->proxy_target_base); + + ringacc->num_proxies = readl(&ringacc->proxy_gcfg->config) & + k3_ringacc_proxy_cfg_threads_mask; + + ringacc->rings = devm_kzalloc(dev, + sizeof(*ringacc->rings) * + ringacc->num_rings, + gfp_kernel); + ringacc->rings_inuse = devm_kcalloc(dev, + bits_to_longs(ringacc->num_rings), + sizeof(unsigned long), gfp_kernel); + ringacc->proxy_inuse = devm_kcalloc(dev, + bits_to_longs(ringacc->num_proxies), + sizeof(unsigned long), gfp_kernel); + + if (!ringacc->rings || !ringacc->rings_inuse || !ringacc->proxy_inuse) + return -enomem; + + for (i = 0; i < ringacc->num_rings; i++) { + ringacc->rings[i].rt = base_rt + + k3_ringacc_rt_regs_step * i; + ringacc->rings[i].fifos = base_fifo + + k3_ringacc_fifo_regs_step * i; + ringacc->rings[i].parent = ringacc; + ringacc->rings[i].ring_id = i; + ringacc->rings[i].proxy_id = k3_ringacc_proxy_not_used; + } + dev_set_drvdata(dev, ringacc); + + ringacc->tisci_ring_ops = &ringacc->tisci->ops.rm_ring_ops; + + mutex_lock(&k3_ringacc_list_lock); + list_add_tail(&ringacc->list, &k3_ringacc_list); + mutex_unlock(&k3_ringacc_list_lock); + + dev_info(dev, "ring accelerator probed rings:%u, gp-rings[%u,%u] sci-dev-id:%u ", + ringacc->num_rings, + ringacc->rm_gp_range->desc[0].start, + ringacc->rm_gp_range->desc[0].num, + ringacc->tisci_dev_id); + dev_info(dev, "dma-ring-reset-quirk: %s ", + ringacc->dma_ring_reset_quirk ? "enabled" : "disabled"); + dev_info(dev, "ra proxy rev. %08x, num_proxies:%u ", + readl(&ringacc->proxy_gcfg->revision), ringacc->num_proxies); + return 0; +} + +/* match table for of_platform binding */ +static const struct of_device_id k3_ringacc_of_match[] = { + { .compatible = "ti,am654-navss-ringacc", }, + {}, +}; + +static struct platform_driver k3_ringacc_driver = { + .probe = k3_ringacc_probe, + .driver = { + .name = "k3-ringacc", + .of_match_table = k3_ringacc_of_match, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver(k3_ringacc_driver); diff --git a/include/linux/soc/ti/k3-ringacc.h b/include/linux/soc/ti/k3-ringacc.h --- /dev/null +++ b/include/linux/soc/ti/k3-ringacc.h +/* spdx-license-identifier: gpl-2.0 */ +/* + * k3 ring accelerator (ra) subsystem interface + * + * copyright (c) 2019 texas instruments incorporated - http://www.ti.com + */ + +#ifndef __soc_ti_k3_ringacc_api_h_ +#define __soc_ti_k3_ringacc_api_h_ + +#include <linux/types.h> + +struct device_node; + +/** + * enum k3_ring_mode - &struct k3_ring_cfg mode + * + * ra ring operational modes + * + * @k3_ringacc_ring_mode_ring: exposed ring mode for sw direct access + * @k3_ringacc_ring_mode_message: messaging mode. messaging mode requires + * that all accesses to the queue must go through this ip so that all + * accesses to the memory are controlled and ordered. this ip then + * controls the entire state of the queue, and sw has no directly control, + * such as through doorbells and cannot access the storage memory directly. + * this is particularly useful when more than one sw or hw entity can be + * the producer and/or consumer at the same time + * @k3_ringacc_ring_mode_credentials: credentials mode is message mode plus + * stores credentials with each message, requiring the element size to be + * doubled to fit the credentials. any exposed memory should be protected + * by a firewall from unwanted access + */ +enum k3_ring_mode { + k3_ringacc_ring_mode_ring = 0, + k3_ringacc_ring_mode_message, + k3_ringacc_ring_mode_credentials, + k3_ringacc_ring_mode_invalid +}; + +/** + * enum k3_ring_size - &struct k3_ring_cfg elm_size + * + * ra ring element's sizes in bytes. + */ +enum k3_ring_size { + k3_ringacc_ring_elsize_4 = 0, + k3_ringacc_ring_elsize_8, + k3_ringacc_ring_elsize_16, + k3_ringacc_ring_elsize_32, + k3_ringacc_ring_elsize_64, + k3_ringacc_ring_elsize_128, + k3_ringacc_ring_elsize_256, + k3_ringacc_ring_elsize_invalid +}; + +struct k3_ringacc; +struct k3_ring; + +/** + * enum k3_ring_cfg - ra ring configuration structure + * + * @size: ring size, number of elements + * @elm_size: ring element size + * @mode: ring operational mode + * @flags: ring configuration flags. possible values: + * @k3_ringacc_ring_shared: when set allows to request the same ring + * few times. it's usable when the same ring is used as free host pd ring + * for different flows, for example. + * note: locking should be done by consumer if required + */ +struct k3_ring_cfg { + u32 size; + enum k3_ring_size elm_size; + enum k3_ring_mode mode; +#define k3_ringacc_ring_shared bit(1) + u32 flags; +}; + +#define k3_ringacc_ring_id_any (-1) + +/** + * of_k3_ringacc_get_by_phandle - find a ra by phandle property + * @np: device node + * @propname: property name containing phandle on ra node + * + * returns pointer on the ra - struct k3_ringacc + * or -enodev if not found, + * or -eprobe_defer if not yet registered + */ +struct k3_ringacc *of_k3_ringacc_get_by_phandle(struct device_node *np, + const char *property); + +#define k3_ringacc_ring_use_proxy bit(1) + +/** + * k3_ringacc_request_ring - request ring from ringacc + * @ringacc: pointer on ringacc + * @id: ring id or k3_ringacc_ring_id_any for any general purpose ring + * @flags: + * @k3_ringacc_ring_use_proxy: if set - proxy will be allocated and + * used to access ring memory. sopported only for rings in + * message/credentials/queue mode. + * + * returns pointer on the ring - struct k3_ring + * or null in case of failure. + */ +struct k3_ring *k3_ringacc_request_ring(struct k3_ringacc *ringacc, + int id, u32 flags); + +/** + * k3_ringacc_ring_reset - ring reset + * @ring: pointer on ring + * + * resets ring internal state ((hw)occ, (hw)idx). + */ +void k3_ringacc_ring_reset(struct k3_ring *ring); +/** + * k3_ringacc_ring_reset - ring reset for dma rings + * @ring: pointer on ring + * + * resets ring internal state ((hw)occ, (hw)idx). should be used for rings + * which are read by k3 udma, like tx or free host pd rings. + */ +void k3_ringacc_ring_reset_dma(struct k3_ring *ring, u32 occ); + +/** + * k3_ringacc_ring_free - ring free + * @ring: pointer on ring + * + * resets ring and free all alocated resources. + */ +int k3_ringacc_ring_free(struct k3_ring *ring); + +/** + * k3_ringacc_get_ring_id - get the ring id + * @ring: pointer on ring + * + * returns the ring id + */ +u32 k3_ringacc_get_ring_id(struct k3_ring *ring); + +/** + * k3_ringacc_get_ring_irq_num - get the irq number for the ring + * @ring: pointer on ring + * + * returns the interrupt number which can be used to request the interrupt + */ +int k3_ringacc_get_ring_irq_num(struct k3_ring *ring); + +/** + * k3_ringacc_ring_cfg - ring configure + * @ring: pointer on ring + * @cfg: ring configuration parameters (see &struct k3_ring_cfg) + * + * configures ring, including ring memory allocation. + * returns 0 on success, errno otherwise. + */ +int k3_ringacc_ring_cfg(struct k3_ring *ring, struct k3_ring_cfg *cfg); + +/** + * k3_ringacc_ring_get_size - get ring size + * @ring: pointer on ring + * + * returns ring size in number of elements. + */ +u32 k3_ringacc_ring_get_size(struct k3_ring *ring); + +/** + * k3_ringacc_ring_get_free - get free elements + * @ring: pointer on ring + * + * returns number of free elements in the ring. + */ +u32 k3_ringacc_ring_get_free(struct k3_ring *ring); + +/** + * k3_ringacc_ring_get_occ - get ring occupancy + * @ring: pointer on ring + * + * returns total number of valid entries on the ring + */ +u32 k3_ringacc_ring_get_occ(struct k3_ring *ring); + +/** + * k3_ringacc_ring_is_full - checks if ring is full + * @ring: pointer on ring + * + * returns true if the ring is full + */ +u32 k3_ringacc_ring_is_full(struct k3_ring *ring); + +/** + * k3_ringacc_ring_push - push element to the ring tail + * @ring: pointer on ring + * @elem: pointer on ring element buffer + * + * push one ring element to the ring tail. size of the ring element is + * determined by ring configuration &struct k3_ring_cfg elm_size. + * + * returns 0 on success, errno otherwise. + */ +int k3_ringacc_ring_push(struct k3_ring *ring, void *elem); + +/** + * k3_ringacc_ring_pop - pop element from the ring head + * @ring: pointer on ring + * @elem: pointer on ring element buffer + * + * push one ring element from the ring head. size of the ring element is + * determined by ring configuration &struct k3_ring_cfg elm_size.. + * + * returns 0 on success, errno otherwise. + */ +int k3_ringacc_ring_pop(struct k3_ring *ring, void *elem); + +/** + * k3_ringacc_ring_push_head - push element to the ring head + * @ring: pointer on ring + * @elem: pointer on ring element buffer + * + * push one ring element to the ring head. size of the ring element is + * determined by ring configuration &struct k3_ring_cfg elm_size. + * + * returns 0 on success, errno otherwise. + * not supported by ring modes: k3_ringacc_ring_mode_ring + */ +int k3_ringacc_ring_push_head(struct k3_ring *ring, void *elem); + +/** + * k3_ringacc_ring_pop_tail - pop element from the ring tail + * @ring: pointer on ring + * @elem: pointer on ring element buffer + * + * push one ring element from the ring tail. size of the ring element is + * determined by ring configuration &struct k3_ring_cfg elm_size. + * + * returns 0 on success, errno otherwise. + * not supported by ring modes: k3_ringacc_ring_mode_ring + */ +int k3_ringacc_ring_pop_tail(struct k3_ring *ring, void *elem); + +u32 k3_ringacc_get_tisci_dev_id(struct k3_ring *ring); + +#endif /* __soc_ti_k3_ringacc_api_h_ */
|
DMA engines
|
3277e8aa2504d97e022ecb9777d784ac1a439d36
|
grygorii strashko
|
include
|
linux
|
soc, ti
|
dmaengine: doc: add sections for per descriptor metadata support
|
update the provider and client documentation with details about the metadata support.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add texas instruments udma support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['rst']
| 2
| 135
| 0
|
--- diff --git a/documentation/driver-api/dmaengine/client.rst b/documentation/driver-api/dmaengine/client.rst --- a/documentation/driver-api/dmaengine/client.rst +++ b/documentation/driver-api/dmaengine/client.rst + optional: per descriptor metadata + --------------------------------- + dmaengine provides two ways for metadata support. + + desc_metadata_client + + the metadata buffer is allocated/provided by the client driver and it is + attached to the descriptor. + + .. code-block:: c + + int dmaengine_desc_attach_metadata(struct dma_async_tx_descriptor *desc, + void *data, size_t len); + + desc_metadata_engine + + the metadata buffer is allocated/managed by the dma driver. the client + driver can ask for the pointer, maximum size and the currently used size of + the metadata and can directly update or read it. + + becasue the dma driver manages the memory area containing the metadata, + clients must make sure that they do not try to access or get the pointer + after their transfer completion callback has run for the descriptor. + if no completion callback has been defined for the transfer, then the + metadata must not be accessed after issue_pending. + in other words: if the aim is to read back metadata after the transfer is + completed, then the client must use completion callback. + + .. code-block:: c + + void *dmaengine_desc_get_metadata_ptr(struct dma_async_tx_descriptor *desc, + size_t *payload_len, size_t *max_len); + + int dmaengine_desc_set_metadata_len(struct dma_async_tx_descriptor *desc, + size_t payload_len); + + client drivers can query if a given mode is supported with: + + .. code-block:: c + + bool dmaengine_is_metadata_mode_supported(struct dma_chan *chan, + enum dma_desc_metadata_mode mode); + + depending on the used mode client drivers must follow different flow. + + desc_metadata_client + + - dma_mem_to_dev / dev_mem_to_mem: + 1. prepare the descriptor (dmaengine_prep_*) + construct the metadata in the client's buffer + 2. use dmaengine_desc_attach_metadata() to attach the buffer to the + descriptor + 3. submit the transfer + - dma_dev_to_mem: + 1. prepare the descriptor (dmaengine_prep_*) + 2. use dmaengine_desc_attach_metadata() to attach the buffer to the + descriptor + 3. submit the transfer + 4. when the transfer is completed, the metadata should be available in the + attached buffer + + desc_metadata_engine + + - dma_mem_to_dev / dev_mem_to_mem: + 1. prepare the descriptor (dmaengine_prep_*) + 2. use dmaengine_desc_get_metadata_ptr() to get the pointer to the + engine's metadata area + 3. update the metadata at the pointer + 4. use dmaengine_desc_set_metadata_len() to tell the dma engine the + amount of data the client has placed into the metadata buffer + 5. submit the transfer + - dma_dev_to_mem: + 1. prepare the descriptor (dmaengine_prep_*) + 2. submit the transfer + 3. on transfer completion, use dmaengine_desc_get_metadata_ptr() to get + the pointer to the engine's metadata area + 4. read out the metadata from the pointer + + .. note:: + + when desc_metadata_engine mode is used the metadata area for the descriptor + is no longer valid after the transfer has been completed (valid up to the + point when the completion callback returns if used). + + mixed use of desc_metadata_client / desc_metadata_engine is not allowed, + client drivers must use either of the modes per descriptor. + diff --git a/documentation/driver-api/dmaengine/provider.rst b/documentation/driver-api/dmaengine/provider.rst --- a/documentation/driver-api/dmaengine/provider.rst +++ b/documentation/driver-api/dmaengine/provider.rst +per descriptor metadata support +------------------------------- +some data movement architecture (dma controller and peripherals) uses metadata +associated with a transaction. the dma controller role is to transfer the +payload and the metadata alongside. +the metadata itself is not used by the dma engine itself, but it contains +parameters, keys, vectors, etc for peripheral or from the peripheral. + +the dmaengine framework provides a generic ways to facilitate the metadata for +descriptors. depending on the architecture the dma driver can implement either +or both of the methods and it is up to the client driver to choose which one +to use. + +- desc_metadata_client + + the metadata buffer is allocated/provided by the client driver and it is + attached (via the dmaengine_desc_attach_metadata() helper to the descriptor. + + from the dma driver the following is expected for this mode: + - dma_mem_to_dev / dev_mem_to_mem + the data from the provided metadata buffer should be prepared for the dma + controller to be sent alongside of the payload data. either by copying to a + hardware descriptor, or highly coupled packet. + - dma_dev_to_mem + on transfer completion the dma driver must copy the metadata to the client + provided metadata buffer before notifying the client about the completion. + after the transfer completion, dma drivers must not touch the metadata + buffer provided by the client. + +- desc_metadata_engine + + the metadata buffer is allocated/managed by the dma driver. the client driver + can ask for the pointer, maximum size and the currently used size of the + metadata and can directly update or read it. dmaengine_desc_get_metadata_ptr() + and dmaengine_desc_set_metadata_len() is provided as helper functions. + + from the dma driver the following is expected for this mode: + - get_metadata_ptr + should return a pointer for the metadata buffer, the maximum size of the + metadata buffer and the currently used / valid (if any) bytes in the buffer. + - set_metadata_len + it is called by the clients after it have placed the metadata to the buffer + to let the dma driver know the number of valid bytes provided. + + note: since the client will ask for the metadata pointer in the completion + callback (in dma_dev_to_mem case) the dma driver must ensure that the + descriptor is not freed up prior the callback is called. + -----------------
|
DMA engines
|
7d083ae983573de16e3ab0bfd47486996d211417
|
peter ujfalusi tero kristo t kristo ti com grygorii strashko grygorii strashko ti com keerthy j keerthy ti com
|
documentation
|
driver-api
|
dmaengine
|
dmaengine: add metadata_ops for dma_async_tx_descriptor
|
the metadata is best described as side band data or parameters traveling alongside the data dmad by the dma engine. it is data which is understood by the peripheral and the peripheral driver only, the dma engine see it only as data block and it is not interpreting it in any way.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add texas instruments udma support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['c', 'h']
| 2
| 185
| 0
|
--- diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c +static inline int desc_check_and_set_metadata_mode( + struct dma_async_tx_descriptor *desc, enum dma_desc_metadata_mode mode) +{ + /* make sure that the metadata mode is not mixed */ + if (!desc->desc_metadata_mode) { + if (dmaengine_is_metadata_mode_supported(desc->chan, mode)) + desc->desc_metadata_mode = mode; + else + return -enotsupp; + } else if (desc->desc_metadata_mode != mode) { + return -einval; + } + + return 0; +} + +int dmaengine_desc_attach_metadata(struct dma_async_tx_descriptor *desc, + void *data, size_t len) +{ + int ret; + + if (!desc) + return -einval; + + ret = desc_check_and_set_metadata_mode(desc, desc_metadata_client); + if (ret) + return ret; + + if (!desc->metadata_ops || !desc->metadata_ops->attach) + return -enotsupp; + + return desc->metadata_ops->attach(desc, data, len); +} +export_symbol_gpl(dmaengine_desc_attach_metadata); + +void *dmaengine_desc_get_metadata_ptr(struct dma_async_tx_descriptor *desc, + size_t *payload_len, size_t *max_len) +{ + int ret; + + if (!desc) + return err_ptr(-einval); + + ret = desc_check_and_set_metadata_mode(desc, desc_metadata_engine); + if (ret) + return err_ptr(ret); + + if (!desc->metadata_ops || !desc->metadata_ops->get_ptr) + return err_ptr(-enotsupp); + + return desc->metadata_ops->get_ptr(desc, payload_len, max_len); +} +export_symbol_gpl(dmaengine_desc_get_metadata_ptr); + +int dmaengine_desc_set_metadata_len(struct dma_async_tx_descriptor *desc, + size_t payload_len) +{ + int ret; + + if (!desc) + return -einval; + + ret = desc_check_and_set_metadata_mode(desc, desc_metadata_engine); + if (ret) + return ret; + + if (!desc->metadata_ops || !desc->metadata_ops->set_len) + return -enotsupp; + + return desc->metadata_ops->set_len(desc, payload_len); +} +export_symbol_gpl(dmaengine_desc_set_metadata_len); + diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h +/** + * enum dma_desc_metadata_mode - per descriptor metadata mode types supported + * @desc_metadata_client - the metadata buffer is allocated/provided by the + * client driver and it is attached (via the dmaengine_desc_attach_metadata() + * helper) to the descriptor. + * + * client drivers interested to use this mode can follow: + * - dma_mem_to_dev / dev_mem_to_mem: + * 1. prepare the descriptor (dmaengine_prep_*) + * construct the metadata in the client's buffer + * 2. use dmaengine_desc_attach_metadata() to attach the buffer to the + * descriptor + * 3. submit the transfer + * - dma_dev_to_mem: + * 1. prepare the descriptor (dmaengine_prep_*) + * 2. use dmaengine_desc_attach_metadata() to attach the buffer to the + * descriptor + * 3. submit the transfer + * 4. when the transfer is completed, the metadata should be available in the + * attached buffer + * + * @desc_metadata_engine - the metadata buffer is allocated/managed by the dma + * driver. the client driver can ask for the pointer, maximum size and the + * currently used size of the metadata and can directly update or read it. + * dmaengine_desc_get_metadata_ptr() and dmaengine_desc_set_metadata_len() is + * provided as helper functions. + * + * note: the metadata area for the descriptor is no longer valid after the + * transfer has been completed (valid up to the point when the completion + * callback returns if used). + * + * client drivers interested to use this mode can follow: + * - dma_mem_to_dev / dev_mem_to_mem: + * 1. prepare the descriptor (dmaengine_prep_*) + * 2. use dmaengine_desc_get_metadata_ptr() to get the pointer to the engine's + * metadata area + * 3. update the metadata at the pointer + * 4. use dmaengine_desc_set_metadata_len() to tell the dma engine the amount + * of data the client has placed into the metadata buffer + * 5. submit the transfer + * - dma_dev_to_mem: + * 1. prepare the descriptor (dmaengine_prep_*) + * 2. submit the transfer + * 3. on transfer completion, use dmaengine_desc_get_metadata_ptr() to get the + * pointer to the engine's metadata area + * 4. read out the metadata from the pointer + * + * note: the two mode is not compatible and clients must use one mode for a + * descriptor. + */ +enum dma_desc_metadata_mode { + desc_metadata_none = 0, + desc_metadata_client = bit(0), + desc_metadata_engine = bit(1), +}; + +struct dma_async_tx_descriptor; + +struct dma_descriptor_metadata_ops { + int (*attach)(struct dma_async_tx_descriptor *desc, void *data, + size_t len); + + void *(*get_ptr)(struct dma_async_tx_descriptor *desc, + size_t *payload_len, size_t *max_len); + int (*set_len)(struct dma_async_tx_descriptor *desc, + size_t payload_len); +}; + + * @desc_metadata_mode: core managed metadata mode to protect mixed use of + * desc_metadata_client or desc_metadata_engine. otherwise + * desc_metadata_none + * @metadata_ops: dma driver provided metadata mode ops, need to be set by the + * dma driver if metadata mode is supported with the descriptor + enum dma_desc_metadata_mode desc_metadata_mode; + struct dma_descriptor_metadata_ops *metadata_ops; + * @desc_metadata_modes: supported metadata modes by the dma device + enum dma_desc_metadata_mode desc_metadata_modes; +static inline bool dmaengine_is_metadata_mode_supported(struct dma_chan *chan, + enum dma_desc_metadata_mode mode) +{ + if (!chan) + return false; + + return !!(chan->device->desc_metadata_modes & mode); +} + +#ifdef config_dma_engine +int dmaengine_desc_attach_metadata(struct dma_async_tx_descriptor *desc, + void *data, size_t len); +void *dmaengine_desc_get_metadata_ptr(struct dma_async_tx_descriptor *desc, + size_t *payload_len, size_t *max_len); +int dmaengine_desc_set_metadata_len(struct dma_async_tx_descriptor *desc, + size_t payload_len); +#else /* config_dma_engine */ +static inline int dmaengine_desc_attach_metadata( + struct dma_async_tx_descriptor *desc, void *data, size_t len) +{ + return -einval; +} +static inline void *dmaengine_desc_get_metadata_ptr( + struct dma_async_tx_descriptor *desc, size_t *payload_len, + size_t *max_len) +{ + return null; +} +static inline int dmaengine_desc_set_metadata_len( + struct dma_async_tx_descriptor *desc, size_t payload_len) +{ + return -einval; +} +#endif /* config_dma_engine */ +
|
DMA engines
|
4db8fd32ed2be7cc510e51e43ec3349aa64074a9
|
peter ujfalusi
|
include
|
linux
| |
dmaengine: add support for reporting dma cached data amount
|
a dma hardware can have big cache or fifo and the amount of data sitting in the dma fabric can be an interest for the clients.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add texas instruments udma support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['h']
| 2
| 10
| 0
|
--- diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h --- a/drivers/dma/dmaengine.h +++ b/drivers/dma/dmaengine.h + state->in_flight_bytes = 0; +static inline void dma_set_in_flight_bytes(struct dma_tx_state *state, + u32 in_flight_bytes) +{ + if (state) + state->in_flight_bytes = in_flight_bytes; +} + diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h + * @in_flight_bytes: amount of data in bytes cached by the dma. + u32 in_flight_bytes;
|
DMA engines
|
6755ec06d1333765d2b935e4e4a5bd011332bac6
|
peter ujfalusi
|
include
|
linux
| |
dmaengine: add helper function to convert direction value to text
|
dmaengine_get_direction_text() can be useful when the direction is printed out. the text is easier to comprehend than the number.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add texas instruments udma support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['h']
| 1
| 19
| 0
|
--- diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h + +static inline char * +dmaengine_get_direction_text(enum dma_transfer_direction dir) +{ + switch (dir) { + case dma_dev_to_mem: + return "dev_to_mem"; + case dma_mem_to_dev: + return "mem_to_dev"; + case dma_mem_to_mem: + return "mem_to_mem"; + case dma_dev_to_dev: + return "dev_to_dev"; + default: + break; + } + + return "invalid"; +}
|
DMA engines
|
816ebf48442eef1c61db26d2ec055f5c8ac83b21
|
peter ujfalusi
|
include
|
linux
| |
dmaengine: ti: add cppi5 header for k3 navss/udma
|
the k3 dma architecture uses cppi5 (communications port programming interface) specified descriptors over psi-l bus within navss.
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this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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add texas instruments udma support
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
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[]
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['h']
| 1
| 1,059
| 0
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--- diff --git a/include/linux/dma/ti-cppi5.h b/include/linux/dma/ti-cppi5.h --- /dev/null +++ b/include/linux/dma/ti-cppi5.h +/* spdx-license-identifier: gpl-2.0 */ +/* + * cppi5 descriptors interface + * + * copyright (c) 2019 texas instruments incorporated - http://www.ti.com + */ + +#ifndef __ti_cppi5_h__ +#define __ti_cppi5_h__ + +#include <linux/bitops.h> +#include <linux/printk.h> +#include <linux/bug.h> + +/** + * struct cppi5_desc_hdr_t - descriptor header, present in all types of + * descriptors + * @pkt_info0: packet info word 0 (n/a in buffer desc) + * @pkt_info0: packet info word 1 (n/a in buffer desc) + * @pkt_info0: packet info word 2 (n/a in buffer desc) + * @src_dst_tag: packet info word 3 (n/a in buffer desc) + */ +struct cppi5_desc_hdr_t { + u32 pkt_info0; + u32 pkt_info1; + u32 pkt_info2; + u32 src_dst_tag; +} __packed; + +/** + * struct cppi5_host_desc_t - host-mode packet and buffer descriptor definition + * @hdr: descriptor header + * @next_desc: word 4/5: linking word + * @buf_ptr: word 6/7: buffer pointer + * @buf_info1: word 8: buffer valid data length + * @org_buf_len: word 9: original buffer length + * @org_buf_ptr: word 10/11: original buffer pointer + * @epib[0]: extended packet info data (optional, 4 words), and/or + * protocol specific data (optional, 0-128 bytes in + * multiples of 4), and/or + * other software data (0-n bytes, optional) + */ +struct cppi5_host_desc_t { + struct cppi5_desc_hdr_t hdr; + u64 next_desc; + u64 buf_ptr; + u32 buf_info1; + u32 org_buf_len; + u64 org_buf_ptr; + u32 epib[0]; +} __packed; + +#define cppi5_desc_min_align (16u) + +#define cppi5_info0_hdesc_epib_size (16u) +#define cppi5_info0_hdesc_psdata_max_size (128u) + +#define cppi5_info0_hdesc_type_shift (30u) +#define cppi5_info0_hdesc_type_mask genmask(31, 30) +#define cppi5_info0_desc_type_val_host (1u) +#define cppi5_info0_desc_type_val_mono (2u) +#define cppi5_info0_desc_type_val_tr (3u) +#define cppi5_info0_hdesc_epib_present bit(29) +/* + * protocol specific words location: + * 0 - located in the descriptor, + * 1 = located in the sop buffer immediately prior to the data. + */ +#define cppi5_info0_hdesc_psinfo_location bit(28) +#define cppi5_info0_hdesc_psinfo_size_shift (22u) +#define cppi5_info0_hdesc_psinfo_size_mask genmask(27, 22) +#define cppi5_info0_hdesc_pktlen_shift (0) +#define cppi5_info0_hdesc_pktlen_mask genmask(21, 0) + +#define cppi5_info1_desc_pkterror_shift (28u) +#define cppi5_info1_desc_pkterror_mask genmask(31, 28) +#define cppi5_info1_hdesc_psflgs_shift (24u) +#define cppi5_info1_hdesc_psflgs_mask genmask(27, 24) +#define cppi5_info1_desc_pktid_shift (14u) +#define cppi5_info1_desc_pktid_mask genmask(23, 14) +#define cppi5_info1_desc_flowid_shift (0) +#define cppi5_info1_desc_flowid_mask genmask(13, 0) +#define cppi5_info1_desc_flowid_default cppi5_info1_desc_flowid_mask + +#define cppi5_info2_hdesc_pkttype_shift (27u) +#define cppi5_info2_hdesc_pkttype_mask genmask(31, 27) +/* return policy: 0 - entire packet 1 - each buffer */ +#define cppi5_info2_hdesc_retpolicy bit(18) +/* + * early return: + * 0 = desc pointers should be returned after all reads have been completed + * 1 = desc pointers should be returned immediately upon fetching + * the descriptor and beginning to transfer data. + */ +#define cppi5_info2_hdesc_earlyret bit(17) +/* + * return push policy: + * 0 = descriptor must be returned to tail of queue + * 1 = descriptor must be returned to head of queue + */ +#define cppi5_info2_desc_retpushpolicy bit(16) +#define cppi5_info2_desc_retp_mask genmask(18, 16) + +#define cppi5_info2_desc_retq_shift (0) +#define cppi5_info2_desc_retq_mask genmask(15, 0) + +#define cppi5_info3_desc_srctag_shift (16u) +#define cppi5_info3_desc_srctag_mask genmask(31, 16) +#define cppi5_info3_desc_dsttag_shift (0) +#define cppi5_info3_desc_dsttag_mask genmask(15, 0) + +#define cppi5_bufinfo1_hdesc_data_len_shift (0) +#define cppi5_bufinfo1_hdesc_data_len_mask genmask(27, 0) + +#define cppi5_obufinfo0_hdesc_buf_len_shift (0) +#define cppi5_obufinfo0_hdesc_buf_len_mask genmask(27, 0) + +/** + * struct cppi5_desc_epib_t - host packet descriptor extended packet info block + * @timestamp: word 0: application specific timestamp + * @sw_info0: word 1: software info 0 + * @sw_info1: word 1: software info 1 + * @sw_info2: word 1: software info 2 + */ +struct cppi5_desc_epib_t { + u32 timestamp; /* w0: application specific timestamp */ + u32 sw_info0; /* w1: software info 0 */ + u32 sw_info1; /* w2: software info 1 */ + u32 sw_info2; /* w3: software info 2 */ +}; + +/** + * struct cppi5_monolithic_desc_t - monolithic-mode packet descriptor + * @hdr: descriptor header + * @epib[0]: extended packet info data (optional, 4 words), and/or + * protocol specific data (optional, 0-128 bytes in + * multiples of 4), and/or + * other software data (0-n bytes, optional) + */ +struct cppi5_monolithic_desc_t { + struct cppi5_desc_hdr_t hdr; + u32 epib[0]; +}; + +#define cppi5_info2_mdesc_data_offset_shift (18u) +#define cppi5_info2_mdesc_data_offset_mask genmask(26, 18) + +/* + * reload count: + * 0 = finish the packet and place the descriptor back on the return queue + * 1-0x1ff = vector to the reload index and resume processing + * 0x1ff indicates perpetual loop, infinite reload until the channel is stopped + */ +#define cppi5_info0_trdesc_rldcnt_shift (20u) +#define cppi5_info0_trdesc_rldcnt_mask genmask(28, 20) +#define cppi5_info0_trdesc_rldcnt_max (0x1ff) +#define cppi5_info0_trdesc_rldcnt_infinite cppi5_info0_trdesc_rldcnt_max +#define cppi5_info0_trdesc_rldidx_shift (14u) +#define cppi5_info0_trdesc_rldidx_mask genmask(19, 14) +#define cppi5_info0_trdesc_rldidx_max (0x3f) +#define cppi5_info0_trdesc_lastidx_shift (0) +#define cppi5_info0_trdesc_lastidx_mask genmask(13, 0) + +#define cppi5_info1_trdesc_recsize_shift (24u) +#define cppi5_info1_trdesc_recsize_mask genmask(26, 24) +#define cppi5_info1_trdesc_recsize_val_16b (0) +#define cppi5_info1_trdesc_recsize_val_32b (1u) +#define cppi5_info1_trdesc_recsize_val_64b (2u) +#define cppi5_info1_trdesc_recsize_val_128b (3u) + +static inline void cppi5_desc_dump(void *desc, u32 size) +{ + print_hex_dump(kern_err, "dump udmap_desc: ", dump_prefix_none, + 32, 4, desc, size, false); +} + +#define cppi5_tdcm_marker (0x1) +/** + * cppi5_desc_is_tdcm - check if the paddr indicates teardown complete message + * @paddr: physical address of the packet popped from the ring + * + * returns true if the address indicates tdcm + */ +static inline bool cppi5_desc_is_tdcm(dma_addr_t paddr) +{ + return (paddr & cppi5_tdcm_marker) ? true : false; +} + +/** + * cppi5_desc_get_type - get descriptor type + * @desc_hdr: packet descriptor/tr header + * + * returns descriptor type: + * cppi5_info0_desc_type_val_host + * cppi5_info0_desc_type_val_mono + * cppi5_info0_desc_type_val_tr + */ +static inline u32 cppi5_desc_get_type(struct cppi5_desc_hdr_t *desc_hdr) +{ + return (desc_hdr->pkt_info0 & cppi5_info0_hdesc_type_mask) >> + cppi5_info0_hdesc_type_shift; +} + +/** + * cppi5_desc_get_errflags - get error flags from desc + * @desc_hdr: packet/tr descriptor header + * + * returns error flags from packet/tr descriptor + */ +static inline u32 cppi5_desc_get_errflags(struct cppi5_desc_hdr_t *desc_hdr) +{ + return (desc_hdr->pkt_info1 & cppi5_info1_desc_pkterror_mask) >> + cppi5_info1_desc_pkterror_shift; +} + +/** + * cppi5_desc_get_pktids - get packet and flow ids from desc + * @desc_hdr: packet/tr descriptor header + * @pkt_id: packet id + * @flow_id: flow id + * + * returns packet and flow ids from packet/tr descriptor + */ +static inline void cppi5_desc_get_pktids(struct cppi5_desc_hdr_t *desc_hdr, + u32 *pkt_id, u32 *flow_id) +{ + *pkt_id = (desc_hdr->pkt_info1 & cppi5_info1_desc_pktid_mask) >> + cppi5_info1_desc_pktid_shift; + *flow_id = (desc_hdr->pkt_info1 & cppi5_info1_desc_flowid_mask) >> + cppi5_info1_desc_flowid_shift; +} + +/** + * cppi5_desc_set_pktids - set packet and flow ids in desc + * @desc_hdr: packet/tr descriptor header + * @pkt_id: packet id + * @flow_id: flow id + */ +static inline void cppi5_desc_set_pktids(struct cppi5_desc_hdr_t *desc_hdr, + u32 pkt_id, u32 flow_id) +{ + desc_hdr->pkt_info1 &= ~(cppi5_info1_desc_pktid_mask | + cppi5_info1_desc_flowid_mask); + desc_hdr->pkt_info1 |= (pkt_id << cppi5_info1_desc_pktid_shift) & + cppi5_info1_desc_pktid_mask; + desc_hdr->pkt_info1 |= (flow_id << cppi5_info1_desc_flowid_shift) & + cppi5_info1_desc_flowid_mask; +} + +/** + * cppi5_desc_set_retpolicy - set packet return policy in desc + * @desc_hdr: packet/tr descriptor header + * @flags: fags, supported values + * cppi5_info2_hdesc_retpolicy + * cppi5_info2_hdesc_earlyret + * cppi5_info2_desc_retpushpolicy + * @return_ring_id: packet return queue/ring id, value 0xffff reserved + */ +static inline void cppi5_desc_set_retpolicy(struct cppi5_desc_hdr_t *desc_hdr, + u32 flags, u32 return_ring_id) +{ + desc_hdr->pkt_info2 &= ~(cppi5_info2_desc_retp_mask | + cppi5_info2_desc_retq_mask); + desc_hdr->pkt_info2 |= flags & cppi5_info2_desc_retp_mask; + desc_hdr->pkt_info2 |= return_ring_id & cppi5_info2_desc_retq_mask; +} + +/** + * cppi5_desc_get_tags_ids - get packet src/dst tags from desc + * @desc_hdr: packet/tr descriptor header + * @src_tag_id: source tag + * @dst_tag_id: dest tag + * + * returns packet src/dst tags from packet/tr descriptor + */ +static inline void cppi5_desc_get_tags_ids(struct cppi5_desc_hdr_t *desc_hdr, + u32 *src_tag_id, u32 *dst_tag_id) +{ + if (src_tag_id) + *src_tag_id = (desc_hdr->src_dst_tag & + cppi5_info3_desc_srctag_mask) >> + cppi5_info3_desc_srctag_shift; + if (dst_tag_id) + *dst_tag_id = desc_hdr->src_dst_tag & + cppi5_info3_desc_dsttag_mask; +} + +/** + * cppi5_desc_set_tags_ids - set packet src/dst tags in hdesc + * @desc_hdr: packet/tr descriptor header + * @src_tag_id: source tag + * @dst_tag_id: dest tag + * + * returns packet src/dst tags from packet/tr descriptor + */ +static inline void cppi5_desc_set_tags_ids(struct cppi5_desc_hdr_t *desc_hdr, + u32 src_tag_id, u32 dst_tag_id) +{ + desc_hdr->src_dst_tag = (src_tag_id << cppi5_info3_desc_srctag_shift) & + cppi5_info3_desc_srctag_mask; + desc_hdr->src_dst_tag |= dst_tag_id & cppi5_info3_desc_dsttag_mask; +} + +/** + * cppi5_hdesc_calc_size - calculate host packet descriptor size + * @epib: is epib present + * @psdata_size: psdata size + * @sw_data_size: swdata size + * + * returns required host packet descriptor size + * 0 - if psdata > cppi5_info0_hdesc_psdata_max_size + */ +static inline u32 cppi5_hdesc_calc_size(bool epib, u32 psdata_size, + u32 sw_data_size) +{ + u32 desc_size; + + if (psdata_size > cppi5_info0_hdesc_psdata_max_size) + return 0; + + desc_size = sizeof(struct cppi5_host_desc_t) + psdata_size + + sw_data_size; + + if (epib) + desc_size += cppi5_info0_hdesc_epib_size; + + return align(desc_size, cppi5_desc_min_align); +} + +/** + * cppi5_hdesc_init - init host packet descriptor size + * @desc: host packet descriptor + * @flags: supported values + * cppi5_info0_hdesc_epib_present + * cppi5_info0_hdesc_psinfo_location + * @psdata_size: psdata size + * + * returns required host packet descriptor size + * 0 - if psdata > cppi5_info0_hdesc_psdata_max_size + */ +static inline void cppi5_hdesc_init(struct cppi5_host_desc_t *desc, u32 flags, + u32 psdata_size) +{ + desc->hdr.pkt_info0 = (cppi5_info0_desc_type_val_host << + cppi5_info0_hdesc_type_shift) | (flags); + desc->hdr.pkt_info0 |= ((psdata_size >> 2) << + cppi5_info0_hdesc_psinfo_size_shift) & + cppi5_info0_hdesc_psinfo_size_mask; + desc->next_desc = 0; +} + +/** + * cppi5_hdesc_update_flags - replace descriptor flags + * @desc: host packet descriptor + * @flags: supported values + * cppi5_info0_hdesc_epib_present + * cppi5_info0_hdesc_psinfo_location + */ +static inline void cppi5_hdesc_update_flags(struct cppi5_host_desc_t *desc, + u32 flags) +{ + desc->hdr.pkt_info0 &= ~(cppi5_info0_hdesc_epib_present | + cppi5_info0_hdesc_psinfo_location); + desc->hdr.pkt_info0 |= flags; +} + +/** + * cppi5_hdesc_update_psdata_size - replace psdata size + * @desc: host packet descriptor + * @psdata_size: psdata size + */ +static inline void +cppi5_hdesc_update_psdata_size(struct cppi5_host_desc_t *desc, u32 psdata_size) +{ + desc->hdr.pkt_info0 &= ~cppi5_info0_hdesc_psinfo_size_mask; + desc->hdr.pkt_info0 |= ((psdata_size >> 2) << + cppi5_info0_hdesc_psinfo_size_shift) & + cppi5_info0_hdesc_psinfo_size_mask; +} + +/** + * cppi5_hdesc_get_psdata_size - get psdata size in bytes + * @desc: host packet descriptor + */ +static inline u32 cppi5_hdesc_get_psdata_size(struct cppi5_host_desc_t *desc) +{ + u32 psdata_size = 0; + + if (!(desc->hdr.pkt_info0 & cppi5_info0_hdesc_psinfo_location)) + psdata_size = (desc->hdr.pkt_info0 & + cppi5_info0_hdesc_psinfo_size_mask) >> + cppi5_info0_hdesc_psinfo_size_shift; + + return (psdata_size << 2); +} + +/** + * cppi5_hdesc_get_pktlen - get packet length from hdesc + * @desc: host packet descriptor + * + * returns packet length from host packet descriptor + */ +static inline u32 cppi5_hdesc_get_pktlen(struct cppi5_host_desc_t *desc) +{ + return (desc->hdr.pkt_info0 & cppi5_info0_hdesc_pktlen_mask); +} + +/** + * cppi5_hdesc_set_pktlen - set packet length in hdesc + * @desc: host packet descriptor + */ +static inline void cppi5_hdesc_set_pktlen(struct cppi5_host_desc_t *desc, + u32 pkt_len) +{ + desc->hdr.pkt_info0 &= ~cppi5_info0_hdesc_pktlen_mask; + desc->hdr.pkt_info0 |= (pkt_len & cppi5_info0_hdesc_pktlen_mask); +} + +/** + * cppi5_hdesc_get_psflags - get protocol specific flags from hdesc + * @desc: host packet descriptor + * + * returns protocol specific flags from host packet descriptor + */ +static inline u32 cppi5_hdesc_get_psflags(struct cppi5_host_desc_t *desc) +{ + return (desc->hdr.pkt_info1 & cppi5_info1_hdesc_psflgs_mask) >> + cppi5_info1_hdesc_psflgs_shift; +} + +/** + * cppi5_hdesc_set_psflags - set protocol specific flags in hdesc + * @desc: host packet descriptor + */ +static inline void cppi5_hdesc_set_psflags(struct cppi5_host_desc_t *desc, + u32 ps_flags) +{ + desc->hdr.pkt_info1 &= ~cppi5_info1_hdesc_psflgs_mask; + desc->hdr.pkt_info1 |= (ps_flags << + cppi5_info1_hdesc_psflgs_shift) & + cppi5_info1_hdesc_psflgs_mask; +} + +/** + * cppi5_hdesc_get_errflags - get packet type from hdesc + * @desc: host packet descriptor + */ +static inline u32 cppi5_hdesc_get_pkttype(struct cppi5_host_desc_t *desc) +{ + return (desc->hdr.pkt_info2 & cppi5_info2_hdesc_pkttype_mask) >> + cppi5_info2_hdesc_pkttype_shift; +} + +/** + * cppi5_hdesc_get_errflags - set packet type in hdesc + * @desc: host packet descriptor + * @pkt_type: packet type + */ +static inline void cppi5_hdesc_set_pkttype(struct cppi5_host_desc_t *desc, + u32 pkt_type) +{ + desc->hdr.pkt_info2 &= ~cppi5_info2_hdesc_pkttype_mask; + desc->hdr.pkt_info2 |= + (pkt_type << cppi5_info2_hdesc_pkttype_shift) & + cppi5_info2_hdesc_pkttype_mask; +} + +/** + * cppi5_hdesc_attach_buf - attach buffer to hdesc + * @desc: host packet descriptor + * @buf: buffer physical address + * @buf_data_len: buffer length + * @obuf: original buffer physical address + * @obuf_len: original buffer length + * + * attaches buffer to host packet descriptor + */ +static inline void cppi5_hdesc_attach_buf(struct cppi5_host_desc_t *desc, + dma_addr_t buf, u32 buf_data_len, + dma_addr_t obuf, u32 obuf_len) +{ + desc->buf_ptr = buf; + desc->buf_info1 = buf_data_len & cppi5_bufinfo1_hdesc_data_len_mask; + desc->org_buf_ptr = obuf; + desc->org_buf_len = obuf_len & cppi5_obufinfo0_hdesc_buf_len_mask; +} + +static inline void cppi5_hdesc_get_obuf(struct cppi5_host_desc_t *desc, + dma_addr_t *obuf, u32 *obuf_len) +{ + *obuf = desc->org_buf_ptr; + *obuf_len = desc->org_buf_len & cppi5_obufinfo0_hdesc_buf_len_mask; +} + +static inline void cppi5_hdesc_reset_to_original(struct cppi5_host_desc_t *desc) +{ + desc->buf_ptr = desc->org_buf_ptr; + desc->buf_info1 = desc->org_buf_len; +} + +/** + * cppi5_hdesc_link_hbdesc - link host buffer descriptor to hdesc + * @desc: host packet descriptor + * @buf_desc: host buffer descriptor physical address + * + * add and link host buffer descriptor to hdesc + */ +static inline void cppi5_hdesc_link_hbdesc(struct cppi5_host_desc_t *desc, + dma_addr_t hbuf_desc) +{ + desc->next_desc = hbuf_desc; +} + +static inline dma_addr_t +cppi5_hdesc_get_next_hbdesc(struct cppi5_host_desc_t *desc) +{ + return (dma_addr_t)desc->next_desc; +} + +static inline void cppi5_hdesc_reset_hbdesc(struct cppi5_host_desc_t *desc) +{ + desc->hdr = (struct cppi5_desc_hdr_t) { 0 }; + desc->next_desc = 0; +} + +/** + * cppi5_hdesc_epib_present - check if epib present + * @desc_hdr: packet descriptor/tr header + * + * returns true if epib present in the packet + */ +static inline bool cppi5_hdesc_epib_present(struct cppi5_desc_hdr_t *desc_hdr) +{ + return !!(desc_hdr->pkt_info0 & cppi5_info0_hdesc_epib_present); +} + +/** + * cppi5_hdesc_get_psdata - get pointer on psdata + * @desc: host packet descriptor + * + * returns pointer on psdata in hdesc. + * null - if ps_data placed at the start of data buffer. + */ +static inline void *cppi5_hdesc_get_psdata(struct cppi5_host_desc_t *desc) +{ + u32 psdata_size; + void *psdata; + + if (desc->hdr.pkt_info0 & cppi5_info0_hdesc_psinfo_location) + return null; + + psdata_size = (desc->hdr.pkt_info0 & + cppi5_info0_hdesc_psinfo_size_mask) >> + cppi5_info0_hdesc_psinfo_size_shift; + + if (!psdata_size) + return null; + + psdata = &desc->epib; + + if (cppi5_hdesc_epib_present(&desc->hdr)) + psdata += cppi5_info0_hdesc_epib_size; + + return psdata; +} + +/** + * cppi5_hdesc_get_swdata - get pointer on swdata + * @desc: host packet descriptor + * + * returns pointer on swdata in hdesc. + * note. it's caller responsibility to be sure hdesc actually has swdata. + */ +static inline void *cppi5_hdesc_get_swdata(struct cppi5_host_desc_t *desc) +{ + u32 psdata_size = 0; + void *swdata; + + if (!(desc->hdr.pkt_info0 & cppi5_info0_hdesc_psinfo_location)) + psdata_size = (desc->hdr.pkt_info0 & + cppi5_info0_hdesc_psinfo_size_mask) >> + cppi5_info0_hdesc_psinfo_size_shift; + + swdata = &desc->epib; + + if (cppi5_hdesc_epib_present(&desc->hdr)) + swdata += cppi5_info0_hdesc_epib_size; + + swdata += (psdata_size << 2); + + return swdata; +} + +/* ================================== tr ================================== */ + +#define cppi5_tr_type_shift (0u) +#define cppi5_tr_type_mask genmask(3, 0) +#define cppi5_tr_static bit(4) +#define cppi5_tr_wait bit(5) +#define cppi5_tr_event_size_shift (6u) +#define cppi5_tr_event_size_mask genmask(7, 6) +#define cppi5_tr_trigger0_shift (8u) +#define cppi5_tr_trigger0_mask genmask(9, 8) +#define cppi5_tr_trigger0_type_shift (10u) +#define cppi5_tr_trigger0_type_mask genmask(11, 10) +#define cppi5_tr_trigger1_shift (12u) +#define cppi5_tr_trigger1_mask genmask(13, 12) +#define cppi5_tr_trigger1_type_shift (14u) +#define cppi5_tr_trigger1_type_mask genmask(15, 14) +#define cppi5_tr_cmd_id_shift (16u) +#define cppi5_tr_cmd_id_mask genmask(23, 16) +#define cppi5_tr_csf_flags_shift (24u) +#define cppi5_tr_csf_flags_mask genmask(31, 24) +#define cppi5_tr_csf_sa_indirect bit(0) +#define cppi5_tr_csf_da_indirect bit(1) +#define cppi5_tr_csf_supr_evt bit(2) +#define cppi5_tr_csf_eol_adv_shift (4u) +#define cppi5_tr_csf_eol_adv_mask genmask(6, 4) +#define cppi5_tr_csf_eop bit(7) + +/** + * enum cppi5_tr_types - tr types + * @cppi5_tr_type0: one dimensional data move + * @cppi5_tr_type1: two dimensional data move + * @cppi5_tr_type2: three dimensional data move + * @cppi5_tr_type3: four dimensional data move + * @cppi5_tr_type4: four dimensional data move with data formatting + * @cppi5_tr_type5: four dimensional cache warm + * @cppi5_tr_type8: four dimensional block move + * @cppi5_tr_type9: four dimensional block move with repacking + * @cppi5_tr_type10: two dimensional block move + * @cppi5_tr_type11: two dimensional block move with repacking + * @cppi5_tr_type15: four dimensional block move with repacking and + * indirection + */ +enum cppi5_tr_types { + cppi5_tr_type0 = 0, + cppi5_tr_type1, + cppi5_tr_type2, + cppi5_tr_type3, + cppi5_tr_type4, + cppi5_tr_type5, + /* type6-7: reserved */ + cppi5_tr_type8 = 8, + cppi5_tr_type9, + cppi5_tr_type10, + cppi5_tr_type11, + /* type12-14: reserved */ + cppi5_tr_type15 = 15, + cppi5_tr_type_max +}; + +/** + * enum cppi5_tr_event_size - tr flags event_size field specifies when an event + * is generated for each tr. + * @cppi5_tr_event_size_completion: when tr is complete and all status for + * the tr has been received + * @cppi5_tr_event_size_icnt1_dec: type 0: when the last data transaction + * is sent for the tr + * type 1-11: when icnt1 is decremented + * @cppi5_tr_event_size_icnt2_dec: type 0-1,10-11: when the last data + * transaction is sent for the tr + * all other types: when icnt2 is + * decremented + * @cppi5_tr_event_size_icnt3_dec: type 0-2,10-11: when the last data + * transaction is sent for the tr + * all other types: when icnt3 is + * decremented + */ +enum cppi5_tr_event_size { + cppi5_tr_event_size_completion, + cppi5_tr_event_size_icnt1_dec, + cppi5_tr_event_size_icnt2_dec, + cppi5_tr_event_size_icnt3_dec, + cppi5_tr_event_size_max +}; + +/** + * enum cppi5_tr_trigger - tr flags triggerx field specifies the type of trigger + * used to enable the tr to transfer data as specified + * by triggerx_type field. + * @cppi5_tr_trigger_none: no trigger + * @cppi5_tr_trigger_global0: global trigger 0 + * @cppi5_tr_trigger_global1: global trigger 1 + * @cppi5_tr_trigger_local_event: local event + */ +enum cppi5_tr_trigger { + cppi5_tr_trigger_none, + cppi5_tr_trigger_global0, + cppi5_tr_trigger_global1, + cppi5_tr_trigger_local_event, + cppi5_tr_trigger_max +}; + +/** + * enum cppi5_tr_trigger_type - tr flags triggerx_type field specifies the type + * of data transfer that will be enabled by + * receiving a trigger as specified by triggerx. + * @cppi5_tr_trigger_type_icnt1_dec: the second inner most loop (icnt1) will + * be decremented by 1 + * @cppi5_tr_trigger_type_icnt2_dec: the third inner most loop (icnt2) will + * be decremented by 1 + * @cppi5_tr_trigger_type_icnt3_dec: the outer most loop (icnt3) will be + * decremented by 1 + * @cppi5_tr_trigger_type_all: the entire tr will be allowed to + * complete + */ +enum cppi5_tr_trigger_type { + cppi5_tr_trigger_type_icnt1_dec, + cppi5_tr_trigger_type_icnt2_dec, + cppi5_tr_trigger_type_icnt3_dec, + cppi5_tr_trigger_type_all, + cppi5_tr_trigger_type_max +}; + +typedef u32 cppi5_tr_flags_t; + +/** + * struct cppi5_tr_type0_t - type 0 (one dimensional data move) tr (16 byte) + * @flags: tr flags (type, triggers, event, configuration) + * @icnt0: total loop iteration count for level 0 (innermost) + * @_reserved: not used + * @addr: starting address for the source data or destination data + */ +struct cppi5_tr_type0_t { + cppi5_tr_flags_t flags; + u16 icnt0; + u16 _reserved; + u64 addr; +} __aligned(16) __packed; + +/** + * struct cppi5_tr_type1_t - type 1 (two dimensional data move) tr (32 byte) + * @flags: tr flags (type, triggers, event, configuration) + * @icnt0: total loop iteration count for level 0 (innermost) + * @icnt1: total loop iteration count for level 1 + * @addr: starting address for the source data or destination data + * @dim1: signed dimension for loop level 1 + */ +struct cppi5_tr_type1_t { + cppi5_tr_flags_t flags; + u16 icnt0; + u16 icnt1; + u64 addr; + s32 dim1; +} __aligned(32) __packed; + +/** + * struct cppi5_tr_type2_t - type 2 (three dimensional data move) tr (32 byte) + * @flags: tr flags (type, triggers, event, configuration) + * @icnt0: total loop iteration count for level 0 (innermost) + * @icnt1: total loop iteration count for level 1 + * @addr: starting address for the source data or destination data + * @dim1: signed dimension for loop level 1 + * @icnt2: total loop iteration count for level 2 + * @_reserved: not used + * @dim2: signed dimension for loop level 2 + */ +struct cppi5_tr_type2_t { + cppi5_tr_flags_t flags; + u16 icnt0; + u16 icnt1; + u64 addr; + s32 dim1; + u16 icnt2; + u16 _reserved; + s32 dim2; +} __aligned(32) __packed; + +/** + * struct cppi5_tr_type3_t - type 3 (four dimensional data move) tr (32 byte) + * @flags: tr flags (type, triggers, event, configuration) + * @icnt0: total loop iteration count for level 0 (innermost) + * @icnt1: total loop iteration count for level 1 + * @addr: starting address for the source data or destination data + * @dim1: signed dimension for loop level 1 + * @icnt2: total loop iteration count for level 2 + * @icnt3: total loop iteration count for level 3 (outermost) + * @dim2: signed dimension for loop level 2 + * @dim3: signed dimension for loop level 3 + */ +struct cppi5_tr_type3_t { + cppi5_tr_flags_t flags; + u16 icnt0; + u16 icnt1; + u64 addr; + s32 dim1; + u16 icnt2; + u16 icnt3; + s32 dim2; + s32 dim3; +} __aligned(32) __packed; + +/** + * struct cppi5_tr_type15_t - type 15 (four dimensional block copy with + * repacking and indirection support) tr (64 byte) + * @flags: tr flags (type, triggers, event, configuration) + * @icnt0: total loop iteration count for level 0 (innermost) for + * source + * @icnt1: total loop iteration count for level 1 for source + * @addr: starting address for the source data + * @dim1: signed dimension for loop level 1 for source + * @icnt2: total loop iteration count for level 2 for source + * @icnt3: total loop iteration count for level 3 (outermost) for + * source + * @dim2: signed dimension for loop level 2 for source + * @dim3: signed dimension for loop level 3 for source + * @_reserved: not used + * @ddim1: signed dimension for loop level 1 for destination + * @daddr: starting address for the destination data + * @ddim2: signed dimension for loop level 2 for destination + * @ddim3: signed dimension for loop level 3 for destination + * @dicnt0: total loop iteration count for level 0 (innermost) for + * destination + * @dicnt1: total loop iteration count for level 1 for destination + * @dicnt2: total loop iteration count for level 2 for destination + * @sicnt3: total loop iteration count for level 3 (outermost) for + * destination + */ +struct cppi5_tr_type15_t { + cppi5_tr_flags_t flags; + u16 icnt0; + u16 icnt1; + u64 addr; + s32 dim1; + u16 icnt2; + u16 icnt3; + s32 dim2; + s32 dim3; + u32 _reserved; + s32 ddim1; + u64 daddr; + s32 ddim2; + s32 ddim3; + u16 dicnt0; + u16 dicnt1; + u16 dicnt2; + u16 dicnt3; +} __aligned(64) __packed; + +/** + * struct cppi5_tr_resp_t - tr response record + * @status: status type and info + * @_reserved: not used + * @cmd_id: command id for the tr for tr identification + * @flags: configuration specific flags + */ +struct cppi5_tr_resp_t { + u8 status; + u8 _reserved; + u8 cmd_id; + u8 flags; +} __packed; + +#define cppi5_tr_response_status_type_shift (0u) +#define cppi5_tr_response_status_type_mask genmask(3, 0) +#define cppi5_tr_response_status_info_shift (4u) +#define cppi5_tr_response_status_info_mask genmask(7, 4) +#define cppi5_tr_response_cmdid_shift (16u) +#define cppi5_tr_response_cmdid_mask genmask(23, 16) +#define cppi5_tr_response_cfg_specific_shift (24u) +#define cppi5_tr_response_cfg_specific_mask genmask(31, 24) + +/** + * enum cppi5_tr_resp_status_type - tr response status type field is used to + * determine what type of status is being + * returned. + * @cppi5_tr_response_status_none: no error, completion: completed + * @cppi5_tr_response_status_transfer_err: transfer error, completion: none + * or partially completed + * @cppi5_tr_response_status_aborted_err: aborted error, completion: none + * or partially completed + * @cppi5_tr_response_status_submission_err: submission error, completion: + * none + * @cppi5_tr_response_status_unsupported_err: unsupported error, completion: + * none + * @cppi5_tr_response_status_transfer_exception: transfer exception, completion: + * partially completed + * @cppi5_tr_response_status__teardown_flush: teardown flush, completion: none + */ +enum cppi5_tr_resp_status_type { + cppi5_tr_response_status_none, + cppi5_tr_response_status_transfer_err, + cppi5_tr_response_status_aborted_err, + cppi5_tr_response_status_submission_err, + cppi5_tr_response_status_unsupported_err, + cppi5_tr_response_status_transfer_exception, + cppi5_tr_response_status__teardown_flush, + cppi5_tr_response_status_max +}; + +/** + * enum cppi5_tr_resp_status_submission - tr response status field values which + * corresponds submission error + * @cppi5_tr_response_status_submission_icnt0: icnt0 was 0 + * @cppi5_tr_response_status_submission_fifo_full: channel fifo was full when tr + * received + * @cppi5_tr_response_status_submission_own: channel is not owned by the + * submitter + */ +enum cppi5_tr_resp_status_submission { + cppi5_tr_response_status_submission_icnt0, + cppi5_tr_response_status_submission_fifo_full, + cppi5_tr_response_status_submission_own, + cppi5_tr_response_status_submission_max +}; + +/** + * enum cppi5_tr_resp_status_unsupported - tr response status field values which + * corresponds unsupported error + * @cppi5_tr_response_status_unsupported_tr_type: tr type not supported + * @cppi5_tr_response_status_unsupported_static: static not supported + * @cppi5_tr_response_status_unsupported_eol: eol not supported + * @cppi5_tr_response_status_unsupported_cfg_specific: configuration specific + * not supported + * @cppi5_tr_response_status_unsupported_amode: amode not supported + * @cppi5_tr_response_status_unsupported_eltype: eltype not supported + * @cppi5_tr_response_status_unsupported_dfmt: dfmt not supported + * @cppi5_tr_response_status_unsupported_sectr: sectr not supported + * @cppi5_tr_response_status_unsupported_amode_specific: amode specific field + * not supported + */ +enum cppi5_tr_resp_status_unsupported { + cppi5_tr_response_status_unsupported_tr_type, + cppi5_tr_response_status_unsupported_static, + cppi5_tr_response_status_unsupported_eol, + cppi5_tr_response_status_unsupported_cfg_specific, + cppi5_tr_response_status_unsupported_amode, + cppi5_tr_response_status_unsupported_eltype, + cppi5_tr_response_status_unsupported_dfmt, + cppi5_tr_response_status_unsupported_sectr, + cppi5_tr_response_status_unsupported_amode_specific, + cppi5_tr_response_status_unsupported_max +}; + +/** + * cppi5_trdesc_calc_size - calculate tr descriptor size + * @tr_count: number of tr records + * @tr_size: nominal size of tr record (max) [16, 32, 64, 128] + * + * returns required tr descriptor size + */ +static inline size_t cppi5_trdesc_calc_size(u32 tr_count, u32 tr_size) +{ + /* + * the size of a tr descriptor is: + * 1 x tr_size : the first 16 bytes is used by the packet info block + + * tr_count x tr_size : transfer request records + + * tr_count x sizeof(struct cppi5_tr_resp_t) : transfer response records + */ + return tr_size * (tr_count + 1) + + sizeof(struct cppi5_tr_resp_t) * tr_count; +} + +/** + * cppi5_trdesc_init - init tr descriptor + * @desc: tr descriptor + * @tr_count: number of tr records + * @tr_size: nominal size of tr record (max) [16, 32, 64, 128] + * @reload_idx: absolute index to jump to on the 2nd and following passes + * through the tr packet. + * @reload_count: number of times to jump from last entry to reload_idx. 0x1ff + * indicates infinite looping. + * + * init tr descriptor + */ +static inline void cppi5_trdesc_init(struct cppi5_desc_hdr_t *desc_hdr, + u32 tr_count, u32 tr_size, u32 reload_idx, + u32 reload_count) +{ + desc_hdr->pkt_info0 = cppi5_info0_desc_type_val_tr << + cppi5_info0_hdesc_type_shift; + desc_hdr->pkt_info0 |= + (reload_count << cppi5_info0_trdesc_rldcnt_shift) & + cppi5_info0_trdesc_rldcnt_mask; + desc_hdr->pkt_info0 |= + (reload_idx << cppi5_info0_trdesc_rldidx_shift) & + cppi5_info0_trdesc_rldidx_mask; + desc_hdr->pkt_info0 |= (tr_count - 1) & cppi5_info0_trdesc_lastidx_mask; + + desc_hdr->pkt_info1 |= ((ffs(tr_size >> 4) - 1) << + cppi5_info1_trdesc_recsize_shift) & + cppi5_info1_trdesc_recsize_mask; +} + +/** + * cppi5_tr_init - init tr record + * @flags: pointer to the tr's flags + * @type: tr type + * @static_tr: tr is static + * @wait: wait for tr completion before allow the next tr to start + * @event_size: output event generation cfg + * @cmd_id: tr identifier (application specifics) + * + * init tr record + */ +static inline void cppi5_tr_init(cppi5_tr_flags_t *flags, + enum cppi5_tr_types type, bool static_tr, + bool wait, enum cppi5_tr_event_size event_size, + u32 cmd_id) +{ + *flags = type; + *flags |= (event_size << cppi5_tr_event_size_shift) & + cppi5_tr_event_size_mask; + + *flags |= (cmd_id << cppi5_tr_cmd_id_shift) & + cppi5_tr_cmd_id_mask; + + if (static_tr && (type == cppi5_tr_type8 || type == cppi5_tr_type9)) + *flags |= cppi5_tr_static; + + if (wait) + *flags |= cppi5_tr_wait; +} + +/** + * cppi5_tr_set_trigger - configure trigger0/1 and trigger0/1_type + * @flags: pointer to the tr's flags + * @trigger0: trigger0 selection + * @trigger0_type: type of data transfer that will be enabled by trigger0 + * @trigger1: trigger1 selection + * @trigger1_type: type of data transfer that will be enabled by trigger1 + * + * configure the triggers for the tr + */ +static inline void cppi5_tr_set_trigger(cppi5_tr_flags_t *flags, + enum cppi5_tr_trigger trigger0, + enum cppi5_tr_trigger_type trigger0_type, + enum cppi5_tr_trigger trigger1, + enum cppi5_tr_trigger_type trigger1_type) +{ + *flags &= ~(cppi5_tr_trigger0_mask | cppi5_tr_trigger0_type_mask | + cppi5_tr_trigger1_mask | cppi5_tr_trigger1_type_mask); + *flags |= (trigger0 << cppi5_tr_trigger0_shift) & + cppi5_tr_trigger0_mask; + *flags |= (trigger0_type << cppi5_tr_trigger0_type_shift) & + cppi5_tr_trigger0_type_mask; + + *flags |= (trigger1 << cppi5_tr_trigger1_shift) & + cppi5_tr_trigger1_mask; + *flags |= (trigger1_type << cppi5_tr_trigger1_type_shift) & + cppi5_tr_trigger1_type_mask; +} + +/** + * cppi5_tr_cflag_set - update the configuration specific flags + * @flags: pointer to the tr's flags + * @csf: configuration specific flags + * + * set a bit in configuration specific flags section of the tr flags. + */ +static inline void cppi5_tr_csf_set(cppi5_tr_flags_t *flags, u32 csf) +{ + *flags &= ~cppi5_tr_csf_flags_mask; + *flags |= (csf << cppi5_tr_csf_flags_shift) & + cppi5_tr_csf_flags_mask; +} + +#endif /* __ti_cppi5_h__ */
|
DMA engines
|
69bafc318560d02dc07e3b52af0d7cf5fc036bfe
|
peter ujfalusi
|
include
|
linux
|
dma
|
dmaengine: ti: k3 psi-l remote endpoint configuration
|
in k3 architecture the dma operates within threads. one end of the thread is udmap, the other is on the peripheral side.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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add texas instruments udma support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
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[]
|
['c', 'kconfig', 'makefile', 'h']
| 7
| 604
| 0
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--- diff --git a/drivers/dma/ti/kconfig b/drivers/dma/ti/kconfig --- a/drivers/dma/ti/kconfig +++ b/drivers/dma/ti/kconfig +config ti_k3_psil + bool + diff --git a/drivers/dma/ti/makefile b/drivers/dma/ti/makefile --- a/drivers/dma/ti/makefile +++ b/drivers/dma/ti/makefile +obj-$(config_ti_k3_psil) += k3-psil.o k3-psil-am654.o k3-psil-j721e.o diff --git a/drivers/dma/ti/k3-psil-am654.c b/drivers/dma/ti/k3-psil-am654.c --- /dev/null +++ b/drivers/dma/ti/k3-psil-am654.c +// spdx-license-identifier: gpl-2.0 +/* + * copyright (c) 2019 texas instruments incorporated - http://www.ti.com + * author: peter ujfalusi <peter.ujfalusi@ti.com> + */ + +#include <linux/kernel.h> + +#include "k3-psil-priv.h" + +#define psil_pdma_xy_tr(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = psil_ep_pdma_xy, \ + }, \ + } + +#define psil_pdma_xy_pkt(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = psil_ep_pdma_xy, \ + .pkt_mode = 1, \ + }, \ + } + +#define psil_ethernet(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = psil_ep_native, \ + .pkt_mode = 1, \ + .needs_epib = 1, \ + .psd_size = 16, \ + }, \ + } + +#define psil_sa2ul(x, tx) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = psil_ep_native, \ + .pkt_mode = 1, \ + .needs_epib = 1, \ + .psd_size = 64, \ + .notdpkt = tx, \ + }, \ + } + +/* psi-l source thread ids, used for rx (dma_dev_to_mem) */ +struct psil_ep am654_src_ep_map[] = { + /* sa2ul */ + psil_sa2ul(0x4000, 0), + psil_sa2ul(0x4001, 0), + psil_sa2ul(0x4002, 0), + psil_sa2ul(0x4003, 0), + /* pru_icssg0 */ + psil_ethernet(0x4100), + psil_ethernet(0x4101), + psil_ethernet(0x4102), + psil_ethernet(0x4103), + /* pru_icssg1 */ + psil_ethernet(0x4200), + psil_ethernet(0x4201), + psil_ethernet(0x4202), + psil_ethernet(0x4203), + /* pru_icssg2 */ + psil_ethernet(0x4300), + psil_ethernet(0x4301), + psil_ethernet(0x4302), + psil_ethernet(0x4303), + /* pdma0 - mcasps */ + psil_pdma_xy_tr(0x4400), + psil_pdma_xy_tr(0x4401), + psil_pdma_xy_tr(0x4402), + /* pdma1 - spi0-4 */ + psil_pdma_xy_pkt(0x4500), + psil_pdma_xy_pkt(0x4501), + psil_pdma_xy_pkt(0x4502), + psil_pdma_xy_pkt(0x4503), + psil_pdma_xy_pkt(0x4504), + psil_pdma_xy_pkt(0x4505), + psil_pdma_xy_pkt(0x4506), + psil_pdma_xy_pkt(0x4507), + psil_pdma_xy_pkt(0x4508), + psil_pdma_xy_pkt(0x4509), + psil_pdma_xy_pkt(0x450a), + psil_pdma_xy_pkt(0x450b), + psil_pdma_xy_pkt(0x450c), + psil_pdma_xy_pkt(0x450d), + psil_pdma_xy_pkt(0x450e), + psil_pdma_xy_pkt(0x450f), + psil_pdma_xy_pkt(0x4510), + psil_pdma_xy_pkt(0x4511), + psil_pdma_xy_pkt(0x4512), + psil_pdma_xy_pkt(0x4513), + /* pdma1 - usart0-2 */ + psil_pdma_xy_pkt(0x4514), + psil_pdma_xy_pkt(0x4515), + psil_pdma_xy_pkt(0x4516), + /* cpsw0 */ + psil_ethernet(0x7000), + /* mcu_pdma0 - adcs */ + psil_pdma_xy_tr(0x7100), + psil_pdma_xy_tr(0x7101), + psil_pdma_xy_tr(0x7102), + psil_pdma_xy_tr(0x7103), + /* mcu_pdma1 - mcu_spi0-2 */ + psil_pdma_xy_pkt(0x7200), + psil_pdma_xy_pkt(0x7201), + psil_pdma_xy_pkt(0x7202), + psil_pdma_xy_pkt(0x7203), + psil_pdma_xy_pkt(0x7204), + psil_pdma_xy_pkt(0x7205), + psil_pdma_xy_pkt(0x7206), + psil_pdma_xy_pkt(0x7207), + psil_pdma_xy_pkt(0x7208), + psil_pdma_xy_pkt(0x7209), + psil_pdma_xy_pkt(0x720a), + psil_pdma_xy_pkt(0x720b), + /* mcu_pdma1 - mcu_usart0 */ + psil_pdma_xy_pkt(0x7212), +}; + +/* psi-l destination thread ids, used for tx (dma_mem_to_dev) */ +struct psil_ep am654_dst_ep_map[] = { + /* sa2ul */ + psil_sa2ul(0xc000, 1), + psil_sa2ul(0xc001, 1), + /* pru_icssg0 */ + psil_ethernet(0xc100), + psil_ethernet(0xc101), + psil_ethernet(0xc102), + psil_ethernet(0xc103), + psil_ethernet(0xc104), + psil_ethernet(0xc105), + psil_ethernet(0xc106), + psil_ethernet(0xc107), + /* pru_icssg1 */ + psil_ethernet(0xc200), + psil_ethernet(0xc201), + psil_ethernet(0xc202), + psil_ethernet(0xc203), + psil_ethernet(0xc204), + psil_ethernet(0xc205), + psil_ethernet(0xc206), + psil_ethernet(0xc207), + /* pru_icssg2 */ + psil_ethernet(0xc300), + psil_ethernet(0xc301), + psil_ethernet(0xc302), + psil_ethernet(0xc303), + psil_ethernet(0xc304), + psil_ethernet(0xc305), + psil_ethernet(0xc306), + psil_ethernet(0xc307), + /* cpsw0 */ + psil_ethernet(0xf000), + psil_ethernet(0xf001), + psil_ethernet(0xf002), + psil_ethernet(0xf003), + psil_ethernet(0xf004), + psil_ethernet(0xf005), + psil_ethernet(0xf006), + psil_ethernet(0xf007), +}; + +struct psil_ep_map am654_ep_map = { + .name = "am654", + .src = am654_src_ep_map, + .src_count = array_size(am654_src_ep_map), + .dst = am654_dst_ep_map, + .dst_count = array_size(am654_dst_ep_map), +}; diff --git a/drivers/dma/ti/k3-psil-j721e.c b/drivers/dma/ti/k3-psil-j721e.c --- /dev/null +++ b/drivers/dma/ti/k3-psil-j721e.c +// spdx-license-identifier: gpl-2.0 +/* + * copyright (c) 2019 texas instruments incorporated - http://www.ti.com + * author: peter ujfalusi <peter.ujfalusi@ti.com> + */ + +#include <linux/kernel.h> + +#include "k3-psil-priv.h" + +#define psil_pdma_xy_tr(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = psil_ep_pdma_xy, \ + }, \ + } + +#define psil_pdma_xy_pkt(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = psil_ep_pdma_xy, \ + .pkt_mode = 1, \ + }, \ + } + +#define psil_pdma_mcasp(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = psil_ep_pdma_xy, \ + .pdma_acc32 = 1, \ + .pdma_burst = 1, \ + }, \ + } + +#define psil_ethernet(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = psil_ep_native, \ + .pkt_mode = 1, \ + .needs_epib = 1, \ + .psd_size = 16, \ + }, \ + } + +#define psil_sa2ul(x, tx) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = psil_ep_native, \ + .pkt_mode = 1, \ + .needs_epib = 1, \ + .psd_size = 64, \ + .notdpkt = tx, \ + }, \ + } + +/* psi-l source thread ids, used for rx (dma_dev_to_mem) */ +struct psil_ep j721e_src_ep_map[] = { + /* sa2ul */ + psil_sa2ul(0x4000, 0), + psil_sa2ul(0x4001, 0), + psil_sa2ul(0x4002, 0), + psil_sa2ul(0x4003, 0), + /* pru_icssg0 */ + psil_ethernet(0x4100), + psil_ethernet(0x4101), + psil_ethernet(0x4102), + psil_ethernet(0x4103), + /* pru_icssg1 */ + psil_ethernet(0x4200), + psil_ethernet(0x4201), + psil_ethernet(0x4202), + psil_ethernet(0x4203), + /* pdma6 (psil_pdma_mcasp_g0) - mcasp0-2 */ + psil_pdma_mcasp(0x4400), + psil_pdma_mcasp(0x4401), + psil_pdma_mcasp(0x4402), + /* pdma7 (psil_pdma_mcasp_g1) - mcasp3-11 */ + psil_pdma_mcasp(0x4500), + psil_pdma_mcasp(0x4501), + psil_pdma_mcasp(0x4502), + psil_pdma_mcasp(0x4503), + psil_pdma_mcasp(0x4504), + psil_pdma_mcasp(0x4505), + psil_pdma_mcasp(0x4506), + psil_pdma_mcasp(0x4507), + psil_pdma_mcasp(0x4508), + /* pdma8 (pdma_misc_g0) - spi0-1 */ + psil_pdma_xy_pkt(0x4600), + psil_pdma_xy_pkt(0x4601), + psil_pdma_xy_pkt(0x4602), + psil_pdma_xy_pkt(0x4603), + psil_pdma_xy_pkt(0x4604), + psil_pdma_xy_pkt(0x4605), + psil_pdma_xy_pkt(0x4606), + psil_pdma_xy_pkt(0x4607), + /* pdma9 (pdma_misc_g1) - spi2-3 */ + psil_pdma_xy_pkt(0x460c), + psil_pdma_xy_pkt(0x460d), + psil_pdma_xy_pkt(0x460e), + psil_pdma_xy_pkt(0x460f), + psil_pdma_xy_pkt(0x4610), + psil_pdma_xy_pkt(0x4611), + psil_pdma_xy_pkt(0x4612), + psil_pdma_xy_pkt(0x4613), + /* pdma10 (pdma_misc_g2) - spi4-5 */ + psil_pdma_xy_pkt(0x4618), + psil_pdma_xy_pkt(0x4619), + psil_pdma_xy_pkt(0x461a), + psil_pdma_xy_pkt(0x461b), + psil_pdma_xy_pkt(0x461c), + psil_pdma_xy_pkt(0x461d), + psil_pdma_xy_pkt(0x461e), + psil_pdma_xy_pkt(0x461f), + /* pdma11 (pdma_misc_g3) */ + psil_pdma_xy_pkt(0x4624), + psil_pdma_xy_pkt(0x4625), + psil_pdma_xy_pkt(0x4626), + psil_pdma_xy_pkt(0x4627), + psil_pdma_xy_pkt(0x4628), + psil_pdma_xy_pkt(0x4629), + psil_pdma_xy_pkt(0x4630), + psil_pdma_xy_pkt(0x463a), + /* pdma13 (pdma_usart_g0) - uart0-1 */ + psil_pdma_xy_pkt(0x4700), + psil_pdma_xy_pkt(0x4701), + /* pdma14 (pdma_usart_g1) - uart2-3 */ + psil_pdma_xy_pkt(0x4702), + psil_pdma_xy_pkt(0x4703), + /* pdma15 (pdma_usart_g2) - uart4-9 */ + psil_pdma_xy_pkt(0x4704), + psil_pdma_xy_pkt(0x4705), + psil_pdma_xy_pkt(0x4706), + psil_pdma_xy_pkt(0x4707), + psil_pdma_xy_pkt(0x4708), + psil_pdma_xy_pkt(0x4709), + /* cpsw9 */ + psil_ethernet(0x4a00), + /* cpsw0 */ + psil_ethernet(0x7000), + /* mcu_pdma0 (mcu_pdma_misc_g0) - spi0 */ + psil_pdma_xy_pkt(0x7100), + psil_pdma_xy_pkt(0x7101), + psil_pdma_xy_pkt(0x7102), + psil_pdma_xy_pkt(0x7103), + /* mcu_pdma1 (mcu_pdma_misc_g1) - spi1-2 */ + psil_pdma_xy_pkt(0x7200), + psil_pdma_xy_pkt(0x7201), + psil_pdma_xy_pkt(0x7202), + psil_pdma_xy_pkt(0x7203), + psil_pdma_xy_pkt(0x7204), + psil_pdma_xy_pkt(0x7205), + psil_pdma_xy_pkt(0x7206), + psil_pdma_xy_pkt(0x7207), + /* mcu_pdma2 (mcu_pdma_misc_g2) - uart0 */ + psil_pdma_xy_pkt(0x7300), + /* mcu_pdma_adc - adc0-1 */ + psil_pdma_xy_tr(0x7400), + psil_pdma_xy_tr(0x7401), + psil_pdma_xy_tr(0x7402), + psil_pdma_xy_tr(0x7403), + /* sa2ul */ + psil_sa2ul(0x7500, 0), + psil_sa2ul(0x7501, 0), +}; + +/* psi-l destination thread ids, used for tx (dma_mem_to_dev) */ +struct psil_ep j721e_dst_ep_map[] = { + /* sa2ul */ + psil_sa2ul(0xc000, 1), + psil_sa2ul(0xc001, 1), + /* pru_icssg0 */ + psil_ethernet(0xc100), + psil_ethernet(0xc101), + psil_ethernet(0xc102), + psil_ethernet(0xc103), + psil_ethernet(0xc104), + psil_ethernet(0xc105), + psil_ethernet(0xc106), + psil_ethernet(0xc107), + /* pru_icssg1 */ + psil_ethernet(0xc200), + psil_ethernet(0xc201), + psil_ethernet(0xc202), + psil_ethernet(0xc203), + psil_ethernet(0xc204), + psil_ethernet(0xc205), + psil_ethernet(0xc206), + psil_ethernet(0xc207), + /* cpsw9 */ + psil_ethernet(0xca00), + psil_ethernet(0xca01), + psil_ethernet(0xca02), + psil_ethernet(0xca03), + psil_ethernet(0xca04), + psil_ethernet(0xca05), + psil_ethernet(0xca06), + psil_ethernet(0xca07), + /* cpsw0 */ + psil_ethernet(0xf000), + psil_ethernet(0xf001), + psil_ethernet(0xf002), + psil_ethernet(0xf003), + psil_ethernet(0xf004), + psil_ethernet(0xf005), + psil_ethernet(0xf006), + psil_ethernet(0xf007), + /* sa2ul */ + psil_sa2ul(0xf500, 1), +}; + +struct psil_ep_map j721e_ep_map = { + .name = "j721e", + .src = j721e_src_ep_map, + .src_count = array_size(j721e_src_ep_map), + .dst = j721e_dst_ep_map, + .dst_count = array_size(j721e_dst_ep_map), +}; diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h --- /dev/null +++ b/drivers/dma/ti/k3-psil-priv.h +/* spdx-license-identifier: gpl-2.0 */ +/* + * copyright (c) 2019 texas instruments incorporated - http://www.ti.com + */ + +#ifndef k3_psil_priv_h_ +#define k3_psil_priv_h_ + +#include <linux/dma/k3-psil.h> + +struct psil_ep { + u32 thread_id; + struct psil_endpoint_config ep_config; +}; + +/** + * struct psil_ep_map - psi-l thread id configuration maps + * @name: name of the map, set it to the name of the soc + * @src: array of source psi-l thread configurations + * @src_count: number of entries in the src array + * @dst: array of destination psi-l thread configurations + * @dst_count: number of entries in the dst array + * + * in case of symmetric configuration for a matching src/dst thread (for example + * 0x4400 and 0xc400) only the src configuration can be present. if no dst + * configuration found the code will look for (dst_thread_id & ~0x8000) to find + * the symmetric match. + */ +struct psil_ep_map { + char *name; + struct psil_ep *src; + int src_count; + struct psil_ep *dst; + int dst_count; +}; + +struct psil_endpoint_config *psil_get_ep_config(u32 thread_id); + +#endif /* k3_psil_priv_h_ */ diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c --- /dev/null +++ b/drivers/dma/ti/k3-psil.c +// spdx-license-identifier: gpl-2.0 +/* + * copyright (c) 2019 texas instruments incorporated - http://www.ti.com + * author: peter ujfalusi <peter.ujfalusi@ti.com> + */ + +#include <linux/kernel.h> +#include <linux/device.h> +#include <linux/init.h> +#include <linux/mutex.h> +#include <linux/of.h> + +#include "k3-psil-priv.h" + +extern struct psil_ep_map am654_ep_map; +extern struct psil_ep_map j721e_ep_map; + +static define_mutex(ep_map_mutex); +static struct psil_ep_map *soc_ep_map; + +struct psil_endpoint_config *psil_get_ep_config(u32 thread_id) +{ + int i; + + mutex_lock(&ep_map_mutex); + if (!soc_ep_map) { + if (of_machine_is_compatible("ti,am654")) { + soc_ep_map = &am654_ep_map; + } else if (of_machine_is_compatible("ti,j721e")) { + soc_ep_map = &j721e_ep_map; + } else { + pr_err("psil: no compatible machine found for map "); + return err_ptr(-enotsupp); + } + pr_debug("%s: using map for %s ", __func__, soc_ep_map->name); + } + mutex_unlock(&ep_map_mutex); + + if (thread_id & k3_psil_dst_thread_id_offset && soc_ep_map->dst) { + /* check in destination thread map */ + for (i = 0; i < soc_ep_map->dst_count; i++) { + if (soc_ep_map->dst[i].thread_id == thread_id) + return &soc_ep_map->dst[i].ep_config; + } + } + + thread_id &= ~k3_psil_dst_thread_id_offset; + if (soc_ep_map->src) { + for (i = 0; i < soc_ep_map->src_count; i++) { + if (soc_ep_map->src[i].thread_id == thread_id) + return &soc_ep_map->src[i].ep_config; + } + } + + return err_ptr(-enoent); +} +export_symbol_gpl(psil_get_ep_config); + +int psil_set_new_ep_config(struct device *dev, const char *name, + struct psil_endpoint_config *ep_config) +{ + struct psil_endpoint_config *dst_ep_config; + struct of_phandle_args dma_spec; + u32 thread_id; + int index; + + if (!dev || !dev->of_node) + return -einval; + + index = of_property_match_string(dev->of_node, "dma-names", name); + if (index < 0) + return index; + + if (of_parse_phandle_with_args(dev->of_node, "dmas", "#dma-cells", + index, &dma_spec)) + return -enoent; + + thread_id = dma_spec.args[0]; + + dst_ep_config = psil_get_ep_config(thread_id); + if (is_err(dst_ep_config)) { + pr_err("psil: thread id 0x%04x not defined in map ", + thread_id); + of_node_put(dma_spec.np); + return ptr_err(dst_ep_config); + } + + memcpy(dst_ep_config, ep_config, sizeof(*dst_ep_config)); + + of_node_put(dma_spec.np); + return 0; +} +export_symbol_gpl(psil_set_new_ep_config); diff --git a/include/linux/dma/k3-psil.h b/include/linux/dma/k3-psil.h --- /dev/null +++ b/include/linux/dma/k3-psil.h +/* spdx-license-identifier: gpl-2.0 */ +/* + * copyright (c) 2019 texas instruments incorporated - http://www.ti.com + */ + +#ifndef k3_psil_h_ +#define k3_psil_h_ + +#include <linux/types.h> + +#define k3_psil_dst_thread_id_offset 0x8000 + +struct device; + +/** + * enum udma_tp_level - channel throughput levels + * @udma_tp_normal: normal channel + * @udma_tp_high: high throughput channel + * @udma_tp_ultrahigh: ultra high throughput channel + */ +enum udma_tp_level { + udma_tp_normal = 0, + udma_tp_high, + udma_tp_ultrahigh, + udma_tp_last, +}; + +/** + * enum psil_endpoint_type - psi-l endpoint type + * @psil_ep_native: normal channel + * @psil_ep_pdma_xy: xy mode pdma + * @psil_ep_pdma_mcan: mcan mode pdma + * @psil_ep_pdma_aasrc: aasrc mode pdma + */ +enum psil_endpoint_type { + psil_ep_native = 0, + psil_ep_pdma_xy, + psil_ep_pdma_mcan, + psil_ep_pdma_aasrc, +}; + +/** + * struct psil_endpoint_config - psi-l endpoint configuration + * @ep_type: psi-l endpoint type + * @pkt_mode: if set, the channel must be in packet mode, otherwise in + * tr mode + * @notdpkt: tdcm must be suppressed on the tx channel + * @needs_epib: endpoint needs epib + * @psd_size: if set, psdata is used by the endpoint + * @channel_tpl: desired throughput level for the channel + * @pdma_acc32: acc32 must be enabled on the pdma side + * @pdma_burst: burst must be enabled on the pdma side + */ +struct psil_endpoint_config { + enum psil_endpoint_type ep_type; + + unsigned pkt_mode:1; + unsigned notdpkt:1; + unsigned needs_epib:1; + u32 psd_size; + enum udma_tp_level channel_tpl; + + /* pdma properties, valid for psil_ep_pdma_* */ + unsigned pdma_acc32:1; + unsigned pdma_burst:1; +}; + +int psil_set_new_ep_config(struct device *dev, const char *name, + struct psil_endpoint_config *ep_config); + +#endif /* k3_psil_h_ */
|
DMA engines
|
8c6bb62f6b4a24c446511e8f894251946dcc2ef1
|
peter ujfalusi
|
include
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linux
|
dma, ti
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dt-bindings: dma: ti: add document for k3 udma
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new binding document for texas instruments k3 navss unified dma peripheral root complex (udma-p).
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this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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add texas instruments udma support
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
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[]
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['yaml']
| 1
| 184
| 0
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--- diff --git a/documentation/devicetree/bindings/dma/ti/k3-udma.yaml b/documentation/devicetree/bindings/dma/ti/k3-udma.yaml --- /dev/null +++ b/documentation/devicetree/bindings/dma/ti/k3-udma.yaml +# spdx-license-identifier: (gpl-2.0-only or bsd-2-clause) +%yaml 1.2 +--- +$id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: texas instruments k3 navss unified dma device tree bindings + +maintainers: + - peter ujfalusi <peter.ujfalusi@ti.com> + +description: | + the udma-p is intended to perform similar (but significantly upgraded) + functions as the packet-oriented dma used on previous soc devices. the udma-p + module supports the transmission and reception of various packet types. + the udma-p architecture facilitates the segmentation and reassembly of soc dma + data structure compliant packets to/from smaller data blocks that are natively + compatible with the specific requirements of each connected peripheral. + multiple tx and rx channels are provided within the dma which allow multiple + segmentation or reassembly operations to be ongoing. the dma controller + maintains state information for each of the channels which allows packet + segmentation and reassembly operations to be time division multiplexed between + channels in order to share the underlying dma hardware. an external dma + scheduler is used to control the ordering and rate at which this multiplexing + occurs for transmit operations. the ordering and rate of receive operations + is indirectly controlled by the order in which blocks are pushed into the dma + on the rx psi-l interface. + + the udma-p also supports acting as both a utc and udma-c for its internal + channels. channels in the udma-p can be configured to be either packet-based + or third-party channels on a channel by channel basis. + + all transfers within navss is done between psi-l source and destination + threads. + the peripherals serviced by udma can be psi-l native (sa2ul, cpsw, etc) or + legacy, non psi-l native peripherals. in the later case a special, small pdma + is tasked to act as a bridge between the psi-l fabric and the legacy + peripheral. + + pdmas can be configured via udmap peer registers to match with the + configuration of the legacy peripheral. + +allof: + - $ref: "../dma-controller.yaml#" + +properties: + "#dma-cells": + const: 1 + description: | + the cell is the psi-l thread id of the remote (to udmap) end. + valid ranges for thread id depends on the data movement direction: + for source thread ids (rx): 0 - 0x7fff + for destination thread ids (tx): 0x8000 - 0xffff + + please refer to the device documentation for the psi-l thread map and also + the psi-l peripheral chapter for the correct thread id. + + compatible: + enum: + - ti,am654-navss-main-udmap + - ti,am654-navss-mcu-udmap + - ti,j721e-navss-main-udmap + - ti,j721e-navss-mcu-udmap + + reg: + maxitems: 3 + + reg-names: + items: + - const: gcfg + - const: rchanrt + - const: tchanrt + + msi-parent: true + + ti,sci: + description: phandle to ti-sci compatible system controller node + allof: + - $ref: /schemas/types.yaml#/definitions/phandle + + ti,sci-dev-id: + description: ti-sci device id of udmap + allof: + - $ref: /schemas/types.yaml#/definitions/uint32 + + ti,ringacc: + description: phandle to the ring accelerator node + allof: + - $ref: /schemas/types.yaml#/definitions/phandle + + ti,sci-rm-range-tchan: + description: | + array of udma tchan resource subtypes for resource allocation for this + host + allof: + - $ref: /schemas/types.yaml#/definitions/uint32-array + minitems: 1 + # should be enough + maxitems: 255 + + ti,sci-rm-range-rchan: + description: | + array of udma rchan resource subtypes for resource allocation for this + host + allof: + - $ref: /schemas/types.yaml#/definitions/uint32-array + minitems: 1 + # should be enough + maxitems: 255 + + ti,sci-rm-range-rflow: + description: | + array of udma rflow resource subtypes for resource allocation for this + host + allof: + - $ref: /schemas/types.yaml#/definitions/uint32-array + minitems: 1 + # should be enough + maxitems: 255 + +required: + - compatible + - "#dma-cells" + - reg + - reg-names + - msi-parent + - ti,sci + - ti,sci-dev-id + - ti,ringacc + - ti,sci-rm-range-tchan + - ti,sci-rm-range-rchan + - ti,sci-rm-range-rflow + +examples: + - |+ + cbass_main { + #address-cells = <2>; + #size-cells = <2>; + + cbass_main_navss: navss@30800000 { + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; + dma-coherent; + dma-ranges; + ranges; + + ti,sci-dev-id = <118>; + + main_udmap: dma-controller@31150000 { + compatible = "ti,am654-navss-main-udmap"; + reg = <0x0 0x31150000 0x0 0x100>, + <0x0 0x34000000 0x0 0x100000>, + <0x0 0x35000000 0x0 0x100000>; + reg-names = "gcfg", "rchanrt", "tchanrt"; + #dma-cells = <1>; + + ti,ringacc = <&ringacc>; + + msi-parent = <&inta_main_udmass>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <188>; + + ti,sci-rm-range-tchan = <0x1>, /* tx_hchan */ + <0x2>; /* tx_chan */ + ti,sci-rm-range-rchan = <0x4>, /* rx_hchan */ + <0x5>; /* rx_chan */ + ti,sci-rm-range-rflow = <0x6>; /* gp rflow */ + }; + }; + + mcasp0: mcasp@02b00000 { + dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; + dma-names = "tx", "rx"; + }; + + crypto: crypto@4e00000 { + compatible = "ti,sa2ul-crypto"; + + dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, <&main_udmap 0x4001>; + dma-names = "tx", "rx1", "rx2"; + }; + };
|
DMA engines
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d3cd299bb151c1c8579c782bf6ef2cb01ebf6e5e
|
peter ujfalusi
|
documentation
|
devicetree
|
bindings, dma, ti
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dmaengine: ti: new driver for k3 udma
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split patch for review containing: defines, structs, io and low level functions and interrupt callbacks.
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this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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add texas instruments udma support
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
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[]
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['c', 'kconfig', 'makefile', 'h']
| 4
| 3,505
| 0
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- mem_to_mem (tr mode) - dev_to_mem (packet / tr mode) - mem_to_dev (packet / tr mode) - cyclic (packet / tr mode) - metadata for descriptors --- diff --git a/drivers/dma/ti/kconfig b/drivers/dma/ti/kconfig --- a/drivers/dma/ti/kconfig +++ b/drivers/dma/ti/kconfig +config ti_k3_udma + bool "texas instruments udma support" + depends on arch_k3 || compile_test + depends on ti_sci_protocol + depends on ti_sci_inta_irqchip + select dma_engine + select dma_virtual_channels + select ti_k3_ringacc + select ti_k3_psil + help + enable support for the ti udma (unified dma) controller. this + dma engine is used in am65x and j721e. + diff --git a/drivers/dma/ti/makefile b/drivers/dma/ti/makefile --- a/drivers/dma/ti/makefile +++ b/drivers/dma/ti/makefile +obj-$(config_ti_k3_udma) += k3-udma.o diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c --- /dev/null +++ b/drivers/dma/ti/k3-udma.c +// spdx-license-identifier: gpl-2.0 +/* + * copyright (c) 2019 texas instruments incorporated - http://www.ti.com + * author: peter ujfalusi <peter.ujfalusi@ti.com> + */ + +#include <linux/kernel.h> +#include <linux/dmaengine.h> +#include <linux/dma-mapping.h> +#include <linux/dmapool.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/spinlock.h> +#include <linux/of.h> +#include <linux/of_dma.h> +#include <linux/of_device.h> +#include <linux/of_irq.h> +#include <linux/workqueue.h> +#include <linux/completion.h> +#include <linux/soc/ti/k3-ringacc.h> +#include <linux/soc/ti/ti_sci_protocol.h> +#include <linux/soc/ti/ti_sci_inta_msi.h> +#include <linux/dma/ti-cppi5.h> + +#include "../virt-dma.h" +#include "k3-udma.h" +#include "k3-psil-priv.h" + +struct udma_static_tr { + u8 elsize; /* rpstr0 */ + u16 elcnt; /* rpstr0 */ + u16 bstcnt; /* rpstr1 */ +}; + +#define k3_udma_max_rflows 1024 +#define k3_udma_default_ring_size 16 + +/* how src/dst tag should be updated by udma in the descriptor's word 3 */ +#define udma_rflow_srctag_none 0 +#define udma_rflow_srctag_cfg_tag 1 +#define udma_rflow_srctag_flow_id 2 +#define udma_rflow_srctag_src_tag 4 + +#define udma_rflow_dsttag_none 0 +#define udma_rflow_dsttag_cfg_tag 1 +#define udma_rflow_dsttag_flow_id 2 +#define udma_rflow_dsttag_dst_tag_lo 4 +#define udma_rflow_dsttag_dst_tag_hi 5 + +struct udma_chan; + +enum udma_mmr { + mmr_gcfg = 0, + mmr_rchanrt, + mmr_tchanrt, + mmr_last, +}; + +static const char * const mmr_names[] = { "gcfg", "rchanrt", "tchanrt" }; + +struct udma_tchan { + void __iomem *reg_rt; + + int id; + struct k3_ring *t_ring; /* transmit ring */ + struct k3_ring *tc_ring; /* transmit completion ring */ +}; + +struct udma_rflow { + int id; + struct k3_ring *fd_ring; /* free descriptor ring */ + struct k3_ring *r_ring; /* receive ring */ +}; + +struct udma_rchan { + void __iomem *reg_rt; + + int id; +}; + +#define udma_flag_pdma_acc32 bit(0) +#define udma_flag_pdma_burst bit(1) + +struct udma_match_data { + u32 psil_base; + bool enable_memcpy_support; + u32 flags; + u32 statictr_z_mask; + u32 rchan_oes_offset; + + u8 tpl_levels; + u32 level_start_idx[]; +}; + +struct udma_dev { + struct dma_device ddev; + struct device *dev; + void __iomem *mmrs[mmr_last]; + const struct udma_match_data *match_data; + + size_t desc_align; /* alignment to use for descriptors */ + + struct udma_tisci_rm tisci_rm; + + struct k3_ringacc *ringacc; + + struct work_struct purge_work; + struct list_head desc_to_purge; + spinlock_t lock; + + int tchan_cnt; + int echan_cnt; + int rchan_cnt; + int rflow_cnt; + unsigned long *tchan_map; + unsigned long *rchan_map; + unsigned long *rflow_gp_map; + unsigned long *rflow_gp_map_allocated; + unsigned long *rflow_in_use; + + struct udma_tchan *tchans; + struct udma_rchan *rchans; + struct udma_rflow *rflows; + + struct udma_chan *channels; + u32 psil_base; +}; + +struct udma_hwdesc { + size_t cppi5_desc_size; + void *cppi5_desc_vaddr; + dma_addr_t cppi5_desc_paddr; + + /* tr descriptor internal pointers */ + void *tr_req_base; + struct cppi5_tr_resp_t *tr_resp_base; +}; + +struct udma_desc { + struct virt_dma_desc vd; + + bool terminated; + + enum dma_transfer_direction dir; + + struct udma_static_tr static_tr; + u32 residue; + + unsigned int sglen; + unsigned int desc_idx; /* only used for cyclic in packet mode */ + unsigned int tr_idx; + + u32 metadata_size; + void *metadata; /* pointer to provided metadata buffer (epip, psdata) */ + + unsigned int hwdesc_count; + struct udma_hwdesc hwdesc[0]; +}; + +enum udma_chan_state { + udma_chan_is_idle = 0, /* not active, no teardown is in progress */ + udma_chan_is_active, /* normal operation */ + udma_chan_is_terminating, /* channel is being terminated */ +}; + +struct udma_tx_drain { + struct delayed_work work; + unsigned long jiffie; + u32 residue; +}; + +struct udma_chan_config { + bool pkt_mode; /* tr or packet */ + bool needs_epib; /* epib is needed for the communication or not */ + u32 psd_size; /* size of protocol specific data */ + u32 metadata_size; /* (needs_epib ? 16:0) + psd_size */ + u32 hdesc_size; /* size of a packet descriptor in packet mode */ + bool notdpkt; /* suppress sending tdc packet */ + int remote_thread_id; + u32 src_thread; + u32 dst_thread; + enum psil_endpoint_type ep_type; + bool enable_acc32; + bool enable_burst; + enum udma_tp_level channel_tpl; /* channel throughput level */ + + enum dma_transfer_direction dir; +}; + +struct udma_chan { + struct virt_dma_chan vc; + struct dma_slave_config cfg; + struct udma_dev *ud; + struct udma_desc *desc; + struct udma_desc *terminated_desc; + struct udma_static_tr static_tr; + char *name; + + struct udma_tchan *tchan; + struct udma_rchan *rchan; + struct udma_rflow *rflow; + + bool psil_paired; + + int irq_num_ring; + int irq_num_udma; + + bool cyclic; + bool paused; + + enum udma_chan_state state; + struct completion teardown_completed; + + struct udma_tx_drain tx_drain; + + u32 bcnt; /* number of bytes completed since the start of the channel */ + u32 in_ring_cnt; /* number of descriptors in flight */ + + /* channel configuration parameters */ + struct udma_chan_config config; + + /* dmapool for packet mode descriptors */ + bool use_dma_pool; + struct dma_pool *hdesc_pool; + + u32 id; +}; + +static inline struct udma_dev *to_udma_dev(struct dma_device *d) +{ + return container_of(d, struct udma_dev, ddev); +} + +static inline struct udma_chan *to_udma_chan(struct dma_chan *c) +{ + return container_of(c, struct udma_chan, vc.chan); +} + +static inline struct udma_desc *to_udma_desc(struct dma_async_tx_descriptor *t) +{ + return container_of(t, struct udma_desc, vd.tx); +} + +/* generic register access functions */ +static inline u32 udma_read(void __iomem *base, int reg) +{ + return readl(base + reg); +} + +static inline void udma_write(void __iomem *base, int reg, u32 val) +{ + writel(val, base + reg); +} + +static inline void udma_update_bits(void __iomem *base, int reg, + u32 mask, u32 val) +{ + u32 tmp, orig; + + orig = readl(base + reg); + tmp = orig & ~mask; + tmp |= (val & mask); + + if (tmp != orig) + writel(tmp, base + reg); +} + +/* tchanrt */ +static inline u32 udma_tchanrt_read(struct udma_tchan *tchan, int reg) +{ + if (!tchan) + return 0; + return udma_read(tchan->reg_rt, reg); +} + +static inline void udma_tchanrt_write(struct udma_tchan *tchan, int reg, + u32 val) +{ + if (!tchan) + return; + udma_write(tchan->reg_rt, reg, val); +} + +static inline void udma_tchanrt_update_bits(struct udma_tchan *tchan, int reg, + u32 mask, u32 val) +{ + if (!tchan) + return; + udma_update_bits(tchan->reg_rt, reg, mask, val); +} + +/* rchanrt */ +static inline u32 udma_rchanrt_read(struct udma_rchan *rchan, int reg) +{ + if (!rchan) + return 0; + return udma_read(rchan->reg_rt, reg); +} + +static inline void udma_rchanrt_write(struct udma_rchan *rchan, int reg, + u32 val) +{ + if (!rchan) + return; + udma_write(rchan->reg_rt, reg, val); +} + +static inline void udma_rchanrt_update_bits(struct udma_rchan *rchan, int reg, + u32 mask, u32 val) +{ + if (!rchan) + return; + udma_update_bits(rchan->reg_rt, reg, mask, val); +} + +static int navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread) +{ + struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; + + dst_thread |= k3_psil_dst_thread_id_offset; + return tisci_rm->tisci_psil_ops->pair(tisci_rm->tisci, + tisci_rm->tisci_navss_dev_id, + src_thread, dst_thread); +} + +static int navss_psil_unpair(struct udma_dev *ud, u32 src_thread, + u32 dst_thread) +{ + struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; + + dst_thread |= k3_psil_dst_thread_id_offset; + return tisci_rm->tisci_psil_ops->unpair(tisci_rm->tisci, + tisci_rm->tisci_navss_dev_id, + src_thread, dst_thread); +} + +static void udma_reset_uchan(struct udma_chan *uc) +{ + memset(&uc->config, 0, sizeof(uc->config)); + uc->config.remote_thread_id = -1; + uc->state = udma_chan_is_idle; +} + +static void udma_dump_chan_stdata(struct udma_chan *uc) +{ + struct device *dev = uc->ud->dev; + u32 offset; + int i; + + if (uc->config.dir == dma_mem_to_dev || uc->config.dir == dma_mem_to_mem) { + dev_dbg(dev, "tchan state data: "); + for (i = 0; i < 32; i++) { + offset = udma_tchan_rt_stdata_reg + i * 4; + dev_dbg(dev, "trt_stdata[%02d]: 0x%08x ", i, + udma_tchanrt_read(uc->tchan, offset)); + } + } + + if (uc->config.dir == dma_dev_to_mem || uc->config.dir == dma_mem_to_mem) { + dev_dbg(dev, "rchan state data: "); + for (i = 0; i < 32; i++) { + offset = udma_rchan_rt_stdata_reg + i * 4; + dev_dbg(dev, "rrt_stdata[%02d]: 0x%08x ", i, + udma_rchanrt_read(uc->rchan, offset)); + } + } +} + +static inline dma_addr_t udma_curr_cppi5_desc_paddr(struct udma_desc *d, + int idx) +{ + return d->hwdesc[idx].cppi5_desc_paddr; +} + +static inline void *udma_curr_cppi5_desc_vaddr(struct udma_desc *d, int idx) +{ + return d->hwdesc[idx].cppi5_desc_vaddr; +} + +static struct udma_desc *udma_udma_desc_from_paddr(struct udma_chan *uc, + dma_addr_t paddr) +{ + struct udma_desc *d = uc->terminated_desc; + + if (d) { + dma_addr_t desc_paddr = udma_curr_cppi5_desc_paddr(d, + d->desc_idx); + + if (desc_paddr != paddr) + d = null; + } + + if (!d) { + d = uc->desc; + if (d) { + dma_addr_t desc_paddr = udma_curr_cppi5_desc_paddr(d, + d->desc_idx); + + if (desc_paddr != paddr) + d = null; + } + } + + return d; +} + +static void udma_free_hwdesc(struct udma_chan *uc, struct udma_desc *d) +{ + if (uc->use_dma_pool) { + int i; + + for (i = 0; i < d->hwdesc_count; i++) { + if (!d->hwdesc[i].cppi5_desc_vaddr) + continue; + + dma_pool_free(uc->hdesc_pool, + d->hwdesc[i].cppi5_desc_vaddr, + d->hwdesc[i].cppi5_desc_paddr); + + d->hwdesc[i].cppi5_desc_vaddr = null; + } + } else if (d->hwdesc[0].cppi5_desc_vaddr) { + struct udma_dev *ud = uc->ud; + + dma_free_coherent(ud->dev, d->hwdesc[0].cppi5_desc_size, + d->hwdesc[0].cppi5_desc_vaddr, + d->hwdesc[0].cppi5_desc_paddr); + + d->hwdesc[0].cppi5_desc_vaddr = null; + } +} + +static void udma_purge_desc_work(struct work_struct *work) +{ + struct udma_dev *ud = container_of(work, typeof(*ud), purge_work); + struct virt_dma_desc *vd, *_vd; + unsigned long flags; + list_head(head); + + spin_lock_irqsave(&ud->lock, flags); + list_splice_tail_init(&ud->desc_to_purge, &head); + spin_unlock_irqrestore(&ud->lock, flags); + + list_for_each_entry_safe(vd, _vd, &head, node) { + struct udma_chan *uc = to_udma_chan(vd->tx.chan); + struct udma_desc *d = to_udma_desc(&vd->tx); + + udma_free_hwdesc(uc, d); + list_del(&vd->node); + kfree(d); + } + + /* if more to purge, schedule the work again */ + if (!list_empty(&ud->desc_to_purge)) + schedule_work(&ud->purge_work); +} + +static void udma_desc_free(struct virt_dma_desc *vd) +{ + struct udma_dev *ud = to_udma_dev(vd->tx.chan->device); + struct udma_chan *uc = to_udma_chan(vd->tx.chan); + struct udma_desc *d = to_udma_desc(&vd->tx); + unsigned long flags; + + if (uc->terminated_desc == d) + uc->terminated_desc = null; + + if (uc->use_dma_pool) { + udma_free_hwdesc(uc, d); + kfree(d); + return; + } + + spin_lock_irqsave(&ud->lock, flags); + list_add_tail(&vd->node, &ud->desc_to_purge); + spin_unlock_irqrestore(&ud->lock, flags); + + schedule_work(&ud->purge_work); +} + +static bool udma_is_chan_running(struct udma_chan *uc) +{ + u32 trt_ctl = 0; + u32 rrt_ctl = 0; + + if (uc->tchan) + trt_ctl = udma_tchanrt_read(uc->tchan, udma_tchan_rt_ctl_reg); + if (uc->rchan) + rrt_ctl = udma_rchanrt_read(uc->rchan, udma_rchan_rt_ctl_reg); + + if (trt_ctl & udma_chan_rt_ctl_en || rrt_ctl & udma_chan_rt_ctl_en) + return true; + + return false; +} + +static bool udma_is_chan_paused(struct udma_chan *uc) +{ + u32 val, pause_mask; + + switch (uc->desc->dir) { + case dma_dev_to_mem: + val = udma_rchanrt_read(uc->rchan, + udma_rchan_rt_peer_rt_en_reg); + pause_mask = udma_peer_rt_en_pause; + break; + case dma_mem_to_dev: + val = udma_tchanrt_read(uc->tchan, + udma_tchan_rt_peer_rt_en_reg); + pause_mask = udma_peer_rt_en_pause; + break; + case dma_mem_to_mem: + val = udma_tchanrt_read(uc->tchan, udma_tchan_rt_ctl_reg); + pause_mask = udma_chan_rt_ctl_pause; + break; + default: + return false; + } + + if (val & pause_mask) + return true; + + return false; +} + +static void udma_sync_for_device(struct udma_chan *uc, int idx) +{ + struct udma_desc *d = uc->desc; + + if (uc->cyclic && uc->config.pkt_mode) { + dma_sync_single_for_device(uc->ud->dev, + d->hwdesc[idx].cppi5_desc_paddr, + d->hwdesc[idx].cppi5_desc_size, + dma_to_device); + } else { + int i; + + for (i = 0; i < d->hwdesc_count; i++) { + if (!d->hwdesc[i].cppi5_desc_vaddr) + continue; + + dma_sync_single_for_device(uc->ud->dev, + d->hwdesc[i].cppi5_desc_paddr, + d->hwdesc[i].cppi5_desc_size, + dma_to_device); + } + } +} + +static int udma_push_to_ring(struct udma_chan *uc, int idx) +{ + struct udma_desc *d = uc->desc; + + struct k3_ring *ring = null; + int ret = -einval; + + switch (uc->config.dir) { + case dma_dev_to_mem: + ring = uc->rflow->fd_ring; + break; + case dma_mem_to_dev: + case dma_mem_to_mem: + ring = uc->tchan->t_ring; + break; + default: + break; + } + + if (ring) { + dma_addr_t desc_addr = udma_curr_cppi5_desc_paddr(d, idx); + + wmb(); /* ensure that writes are not moved over this point */ + udma_sync_for_device(uc, idx); + ret = k3_ringacc_ring_push(ring, &desc_addr); + uc->in_ring_cnt++; + } + + return ret; +} + +static int udma_pop_from_ring(struct udma_chan *uc, dma_addr_t *addr) +{ + struct k3_ring *ring = null; + int ret = -enoent; + + switch (uc->config.dir) { + case dma_dev_to_mem: + ring = uc->rflow->r_ring; + break; + case dma_mem_to_dev: + case dma_mem_to_mem: + ring = uc->tchan->tc_ring; + break; + default: + break; + } + + if (ring && k3_ringacc_ring_get_occ(ring)) { + struct udma_desc *d = null; + + ret = k3_ringacc_ring_pop(ring, addr); + if (ret) + return ret; + + /* teardown completion */ + if (cppi5_desc_is_tdcm(*addr)) + return ret; + + d = udma_udma_desc_from_paddr(uc, *addr); + + if (d) + dma_sync_single_for_cpu(uc->ud->dev, *addr, + d->hwdesc[0].cppi5_desc_size, + dma_from_device); + rmb(); /* ensure that reads are not moved before this point */ + + if (!ret) + uc->in_ring_cnt--; + } + + return ret; +} + +static void udma_reset_rings(struct udma_chan *uc) +{ + struct k3_ring *ring1 = null; + struct k3_ring *ring2 = null; + + switch (uc->config.dir) { + case dma_dev_to_mem: + if (uc->rchan) { + ring1 = uc->rflow->fd_ring; + ring2 = uc->rflow->r_ring; + } + break; + case dma_mem_to_dev: + case dma_mem_to_mem: + if (uc->tchan) { + ring1 = uc->tchan->t_ring; + ring2 = uc->tchan->tc_ring; + } + break; + default: + break; + } + + if (ring1) + k3_ringacc_ring_reset_dma(ring1, + k3_ringacc_ring_get_occ(ring1)); + if (ring2) + k3_ringacc_ring_reset(ring2); + + /* make sure we are not leaking memory by stalled descriptor */ + if (uc->terminated_desc) { + udma_desc_free(&uc->terminated_desc->vd); + uc->terminated_desc = null; + } + + uc->in_ring_cnt = 0; +} + +static void udma_reset_counters(struct udma_chan *uc) +{ + u32 val; + + if (uc->tchan) { + val = udma_tchanrt_read(uc->tchan, udma_tchan_rt_bcnt_reg); + udma_tchanrt_write(uc->tchan, udma_tchan_rt_bcnt_reg, val); + + val = udma_tchanrt_read(uc->tchan, udma_tchan_rt_sbcnt_reg); + udma_tchanrt_write(uc->tchan, udma_tchan_rt_sbcnt_reg, val); + + val = udma_tchanrt_read(uc->tchan, udma_tchan_rt_pcnt_reg); + udma_tchanrt_write(uc->tchan, udma_tchan_rt_pcnt_reg, val); + + val = udma_tchanrt_read(uc->tchan, udma_tchan_rt_peer_bcnt_reg); + udma_tchanrt_write(uc->tchan, udma_tchan_rt_peer_bcnt_reg, val); + } + + if (uc->rchan) { + val = udma_rchanrt_read(uc->rchan, udma_rchan_rt_bcnt_reg); + udma_rchanrt_write(uc->rchan, udma_rchan_rt_bcnt_reg, val); + + val = udma_rchanrt_read(uc->rchan, udma_rchan_rt_sbcnt_reg); + udma_rchanrt_write(uc->rchan, udma_rchan_rt_sbcnt_reg, val); + + val = udma_rchanrt_read(uc->rchan, udma_rchan_rt_pcnt_reg); + udma_rchanrt_write(uc->rchan, udma_rchan_rt_pcnt_reg, val); + + val = udma_rchanrt_read(uc->rchan, udma_rchan_rt_peer_bcnt_reg); + udma_rchanrt_write(uc->rchan, udma_rchan_rt_peer_bcnt_reg, val); + } + + uc->bcnt = 0; +} + +static int udma_reset_chan(struct udma_chan *uc, bool hard) +{ + switch (uc->config.dir) { + case dma_dev_to_mem: + udma_rchanrt_write(uc->rchan, udma_rchan_rt_peer_rt_en_reg, 0); + udma_rchanrt_write(uc->rchan, udma_rchan_rt_ctl_reg, 0); + break; + case dma_mem_to_dev: + udma_tchanrt_write(uc->tchan, udma_tchan_rt_ctl_reg, 0); + udma_tchanrt_write(uc->tchan, udma_tchan_rt_peer_rt_en_reg, 0); + break; + case dma_mem_to_mem: + udma_rchanrt_write(uc->rchan, udma_rchan_rt_ctl_reg, 0); + udma_tchanrt_write(uc->tchan, udma_tchan_rt_ctl_reg, 0); + break; + default: + return -einval; + } + + /* reset all counters */ + udma_reset_counters(uc); + + /* hard reset: re-initialize the channel to reset */ + if (hard) { + struct udma_chan_config ucc_backup; + int ret; + + memcpy(&ucc_backup, &uc->config, sizeof(uc->config)); + uc->ud->ddev.device_free_chan_resources(&uc->vc.chan); + + /* restore the channel configuration */ + memcpy(&uc->config, &ucc_backup, sizeof(uc->config)); + ret = uc->ud->ddev.device_alloc_chan_resources(&uc->vc.chan); + if (ret) + return ret; + + /* + * setting forced teardown after forced reset helps recovering + * the rchan. + */ + if (uc->config.dir == dma_dev_to_mem) + udma_rchanrt_write(uc->rchan, udma_rchan_rt_ctl_reg, + udma_chan_rt_ctl_en | + udma_chan_rt_ctl_tdown | + udma_chan_rt_ctl_ftdown); + } + uc->state = udma_chan_is_idle; + + return 0; +} + +static void udma_start_desc(struct udma_chan *uc) +{ + struct udma_chan_config *ucc = &uc->config; + + if (ucc->pkt_mode && (uc->cyclic || ucc->dir == dma_dev_to_mem)) { + int i; + + /* push all descriptors to ring for packet mode cyclic or rx */ + for (i = 0; i < uc->desc->sglen; i++) + udma_push_to_ring(uc, i); + } else { + udma_push_to_ring(uc, 0); + } +} + +static bool udma_chan_needs_reconfiguration(struct udma_chan *uc) +{ + /* only pdmas have statictr */ + if (uc->config.ep_type == psil_ep_native) + return false; + + /* check if the statictr configuration has changed for tx */ + if (memcmp(&uc->static_tr, &uc->desc->static_tr, sizeof(uc->static_tr))) + return true; + + return false; +} + +static int udma_start(struct udma_chan *uc) +{ + struct virt_dma_desc *vd = vchan_next_desc(&uc->vc); + + if (!vd) { + uc->desc = null; + return -enoent; + } + + list_del(&vd->node); + + uc->desc = to_udma_desc(&vd->tx); + + /* channel is already running and does not need reconfiguration */ + if (udma_is_chan_running(uc) && !udma_chan_needs_reconfiguration(uc)) { + udma_start_desc(uc); + goto out; + } + + /* make sure that we clear the teardown bit, if it is set */ + udma_reset_chan(uc, false); + + /* push descriptors before we start the channel */ + udma_start_desc(uc); + + switch (uc->desc->dir) { + case dma_dev_to_mem: + /* config remote tr */ + if (uc->config.ep_type == psil_ep_pdma_xy) { + u32 val = pdma_static_tr_y(uc->desc->static_tr.elcnt) | + pdma_static_tr_x(uc->desc->static_tr.elsize); + const struct udma_match_data *match_data = + uc->ud->match_data; + + if (uc->config.enable_acc32) + val |= pdma_static_tr_xy_acc32; + if (uc->config.enable_burst) + val |= pdma_static_tr_xy_burst; + + udma_rchanrt_write(uc->rchan, + udma_rchan_rt_peer_static_tr_xy_reg, val); + + udma_rchanrt_write(uc->rchan, + udma_rchan_rt_peer_static_tr_z_reg, + pdma_static_tr_z(uc->desc->static_tr.bstcnt, + match_data->statictr_z_mask)); + + /* save the current statictr configuration */ + memcpy(&uc->static_tr, &uc->desc->static_tr, + sizeof(uc->static_tr)); + } + + udma_rchanrt_write(uc->rchan, udma_rchan_rt_ctl_reg, + udma_chan_rt_ctl_en); + + /* enable remote */ + udma_rchanrt_write(uc->rchan, udma_rchan_rt_peer_rt_en_reg, + udma_peer_rt_en_enable); + + break; + case dma_mem_to_dev: + /* config remote tr */ + if (uc->config.ep_type == psil_ep_pdma_xy) { + u32 val = pdma_static_tr_y(uc->desc->static_tr.elcnt) | + pdma_static_tr_x(uc->desc->static_tr.elsize); + + if (uc->config.enable_acc32) + val |= pdma_static_tr_xy_acc32; + if (uc->config.enable_burst) + val |= pdma_static_tr_xy_burst; + + udma_tchanrt_write(uc->tchan, + udma_tchan_rt_peer_static_tr_xy_reg, val); + + /* save the current statictr configuration */ + memcpy(&uc->static_tr, &uc->desc->static_tr, + sizeof(uc->static_tr)); + } + + /* enable remote */ + udma_tchanrt_write(uc->tchan, udma_tchan_rt_peer_rt_en_reg, + udma_peer_rt_en_enable); + + udma_tchanrt_write(uc->tchan, udma_tchan_rt_ctl_reg, + udma_chan_rt_ctl_en); + + break; + case dma_mem_to_mem: + udma_rchanrt_write(uc->rchan, udma_rchan_rt_ctl_reg, + udma_chan_rt_ctl_en); + udma_tchanrt_write(uc->tchan, udma_tchan_rt_ctl_reg, + udma_chan_rt_ctl_en); + + break; + default: + return -einval; + } + + uc->state = udma_chan_is_active; +out: + + return 0; +} + +static int udma_stop(struct udma_chan *uc) +{ + enum udma_chan_state old_state = uc->state; + + uc->state = udma_chan_is_terminating; + reinit_completion(&uc->teardown_completed); + + switch (uc->config.dir) { + case dma_dev_to_mem: + udma_rchanrt_write(uc->rchan, udma_rchan_rt_peer_rt_en_reg, + udma_peer_rt_en_enable | + udma_peer_rt_en_teardown); + break; + case dma_mem_to_dev: + udma_tchanrt_write(uc->tchan, udma_tchan_rt_peer_rt_en_reg, + udma_peer_rt_en_enable | + udma_peer_rt_en_flush); + udma_tchanrt_write(uc->tchan, udma_tchan_rt_ctl_reg, + udma_chan_rt_ctl_en | + udma_chan_rt_ctl_tdown); + break; + case dma_mem_to_mem: + udma_tchanrt_write(uc->tchan, udma_tchan_rt_ctl_reg, + udma_chan_rt_ctl_en | + udma_chan_rt_ctl_tdown); + break; + default: + uc->state = old_state; + complete_all(&uc->teardown_completed); + return -einval; + } + + return 0; +} + +static void udma_cyclic_packet_elapsed(struct udma_chan *uc) +{ + struct udma_desc *d = uc->desc; + struct cppi5_host_desc_t *h_desc; + + h_desc = d->hwdesc[d->desc_idx].cppi5_desc_vaddr; + cppi5_hdesc_reset_to_original(h_desc); + udma_push_to_ring(uc, d->desc_idx); + d->desc_idx = (d->desc_idx + 1) % d->sglen; +} + +static inline void udma_fetch_epib(struct udma_chan *uc, struct udma_desc *d) +{ + struct cppi5_host_desc_t *h_desc = d->hwdesc[0].cppi5_desc_vaddr; + + memcpy(d->metadata, h_desc->epib, d->metadata_size); +} + +static bool udma_is_desc_really_done(struct udma_chan *uc, struct udma_desc *d) +{ + u32 peer_bcnt, bcnt; + + /* only tx towards pdma is affected */ + if (uc->config.ep_type == psil_ep_native || + uc->config.dir != dma_mem_to_dev) + return true; + + peer_bcnt = udma_tchanrt_read(uc->tchan, udma_tchan_rt_peer_bcnt_reg); + bcnt = udma_tchanrt_read(uc->tchan, udma_tchan_rt_bcnt_reg); + + if (peer_bcnt < bcnt) { + uc->tx_drain.residue = bcnt - peer_bcnt; + uc->tx_drain.jiffie = jiffies; + return false; + } + + return true; +} + +static void udma_check_tx_completion(struct work_struct *work) +{ + struct udma_chan *uc = container_of(work, typeof(*uc), + tx_drain.work.work); + bool desc_done = true; + u32 residue_diff; + unsigned long jiffie_diff, delay; + + if (uc->desc) { + residue_diff = uc->tx_drain.residue; + jiffie_diff = uc->tx_drain.jiffie; + desc_done = udma_is_desc_really_done(uc, uc->desc); + } + + if (!desc_done) { + jiffie_diff = uc->tx_drain.jiffie - jiffie_diff; + residue_diff -= uc->tx_drain.residue; + if (residue_diff) { + /* try to guess when we should check next time */ + residue_diff /= jiffie_diff; + delay = uc->tx_drain.residue / residue_diff / 3; + if (jiffies_to_msecs(delay) < 5) + delay = 0; + } else { + /* no progress, check again in 1 second */ + delay = hz; + } + + schedule_delayed_work(&uc->tx_drain.work, delay); + } else if (uc->desc) { + struct udma_desc *d = uc->desc; + + uc->bcnt += d->residue; + udma_start(uc); + vchan_cookie_complete(&d->vd); + } +} + +static irqreturn_t udma_ring_irq_handler(int irq, void *data) +{ + struct udma_chan *uc = data; + struct udma_desc *d; + unsigned long flags; + dma_addr_t paddr = 0; + + if (udma_pop_from_ring(uc, &paddr) || !paddr) + return irq_handled; + + spin_lock_irqsave(&uc->vc.lock, flags); + + /* teardown completion message */ + if (cppi5_desc_is_tdcm(paddr)) { + /* compensate our internal pop/push counter */ + uc->in_ring_cnt++; + + complete_all(&uc->teardown_completed); + + if (uc->terminated_desc) { + udma_desc_free(&uc->terminated_desc->vd); + uc->terminated_desc = null; + } + + if (!uc->desc) + udma_start(uc); + + goto out; + } + + d = udma_udma_desc_from_paddr(uc, paddr); + + if (d) { + dma_addr_t desc_paddr = udma_curr_cppi5_desc_paddr(d, + d->desc_idx); + if (desc_paddr != paddr) { + dev_err(uc->ud->dev, "not matching descriptors! "); + goto out; + } + + if (uc->cyclic) { + /* push the descriptor back to the ring */ + if (d == uc->desc) { + udma_cyclic_packet_elapsed(uc); + vchan_cyclic_callback(&d->vd); + } + } else { + bool desc_done = false; + + if (d == uc->desc) { + desc_done = udma_is_desc_really_done(uc, d); + + if (desc_done) { + uc->bcnt += d->residue; + udma_start(uc); + } else { + schedule_delayed_work(&uc->tx_drain.work, + 0); + } + } + + if (desc_done) + vchan_cookie_complete(&d->vd); + } + } +out: + spin_unlock_irqrestore(&uc->vc.lock, flags); + + return irq_handled; +} + +static irqreturn_t udma_udma_irq_handler(int irq, void *data) +{ + struct udma_chan *uc = data; + struct udma_desc *d; + unsigned long flags; + + spin_lock_irqsave(&uc->vc.lock, flags); + d = uc->desc; + if (d) { + d->tr_idx = (d->tr_idx + 1) % d->sglen; + + if (uc->cyclic) { + vchan_cyclic_callback(&d->vd); + } else { + /* todo: figure out the real amount of data */ + uc->bcnt += d->residue; + udma_start(uc); + vchan_cookie_complete(&d->vd); + } + } + + spin_unlock_irqrestore(&uc->vc.lock, flags); + + return irq_handled; +} + +static struct udma_rflow *__udma_get_rflow(struct udma_dev *ud, int id) +{ + /* + * attempt to request rflow by id can be made for any rflow + * if not in use with assumption that caller knows what's doing. + * ti-sci fw will perform additional permission check ant way, it's + * safe + */ + + if (id < 0 || id >= ud->rflow_cnt) + return err_ptr(-enoent); + + if (test_bit(id, ud->rflow_in_use)) + return err_ptr(-enoent); + + /* gp rflow has to be allocated first */ + if (!test_bit(id, ud->rflow_gp_map) && + !test_bit(id, ud->rflow_gp_map_allocated)) + return err_ptr(-einval); + + dev_dbg(ud->dev, "get rflow%d ", id); + set_bit(id, ud->rflow_in_use); + return &ud->rflows[id]; +} + +static void __udma_put_rflow(struct udma_dev *ud, struct udma_rflow *rflow) +{ + if (!test_bit(rflow->id, ud->rflow_in_use)) { + dev_err(ud->dev, "attempt to put unused rflow%d ", rflow->id); + return; + } + + dev_dbg(ud->dev, "put rflow%d ", rflow->id); + clear_bit(rflow->id, ud->rflow_in_use); +} + +#define udma_reserve_resource(res) \ +static struct udma_##res *__udma_reserve_##res(struct udma_dev *ud, \ + enum udma_tp_level tpl, \ + int id) \ +{ \ + if (id >= 0) { \ + if (test_bit(id, ud->res##_map)) { \ + dev_err(ud->dev, "res##%d is in use ", id); \ + return err_ptr(-enoent); \ + } \ + } else { \ + int start; \ + \ + if (tpl >= ud->match_data->tpl_levels) \ + tpl = ud->match_data->tpl_levels - 1; \ + \ + start = ud->match_data->level_start_idx[tpl]; \ + \ + id = find_next_zero_bit(ud->res##_map, ud->res##_cnt, \ + start); \ + if (id == ud->res##_cnt) { \ + return err_ptr(-enoent); \ + } \ + } \ + \ + set_bit(id, ud->res##_map); \ + return &ud->res##s[id]; \ +} + +udma_reserve_resource(tchan); +udma_reserve_resource(rchan); + +static int udma_get_tchan(struct udma_chan *uc) +{ + struct udma_dev *ud = uc->ud; + + if (uc->tchan) { + dev_dbg(ud->dev, "chan%d: already have tchan%d allocated ", + uc->id, uc->tchan->id); + return 0; + } + + uc->tchan = __udma_reserve_tchan(ud, uc->config.channel_tpl, -1); + if (is_err(uc->tchan)) + return ptr_err(uc->tchan); + + return 0; +} + +static int udma_get_rchan(struct udma_chan *uc) +{ + struct udma_dev *ud = uc->ud; + + if (uc->rchan) { + dev_dbg(ud->dev, "chan%d: already have rchan%d allocated ", + uc->id, uc->rchan->id); + return 0; + } + + uc->rchan = __udma_reserve_rchan(ud, uc->config.channel_tpl, -1); + if (is_err(uc->rchan)) + return ptr_err(uc->rchan); + + return 0; +} + +static int udma_get_chan_pair(struct udma_chan *uc) +{ + struct udma_dev *ud = uc->ud; + const struct udma_match_data *match_data = ud->match_data; + int chan_id, end; + + if ((uc->tchan && uc->rchan) && uc->tchan->id == uc->rchan->id) { + dev_info(ud->dev, "chan%d: already have %d pair allocated ", + uc->id, uc->tchan->id); + return 0; + } + + if (uc->tchan) { + dev_err(ud->dev, "chan%d: already have tchan%d allocated ", + uc->id, uc->tchan->id); + return -ebusy; + } else if (uc->rchan) { + dev_err(ud->dev, "chan%d: already have rchan%d allocated ", + uc->id, uc->rchan->id); + return -ebusy; + } + + /* can be optimized, but let's have it like this for now */ + end = min(ud->tchan_cnt, ud->rchan_cnt); + /* try to use the highest tpl channel pair for mem_to_mem channels */ + chan_id = match_data->level_start_idx[match_data->tpl_levels - 1]; + for (; chan_id < end; chan_id++) { + if (!test_bit(chan_id, ud->tchan_map) && + !test_bit(chan_id, ud->rchan_map)) + break; + } + + if (chan_id == end) + return -enoent; + + set_bit(chan_id, ud->tchan_map); + set_bit(chan_id, ud->rchan_map); + uc->tchan = &ud->tchans[chan_id]; + uc->rchan = &ud->rchans[chan_id]; + + return 0; +} + +static int udma_get_rflow(struct udma_chan *uc, int flow_id) +{ + struct udma_dev *ud = uc->ud; + + if (!uc->rchan) { + dev_err(ud->dev, "chan%d: does not have rchan?? ", uc->id); + return -einval; + } + + if (uc->rflow) { + dev_dbg(ud->dev, "chan%d: already have rflow%d allocated ", + uc->id, uc->rflow->id); + return 0; + } + + uc->rflow = __udma_get_rflow(ud, flow_id); + if (is_err(uc->rflow)) + return ptr_err(uc->rflow); + + return 0; +} + +static void udma_put_rchan(struct udma_chan *uc) +{ + struct udma_dev *ud = uc->ud; + + if (uc->rchan) { + dev_dbg(ud->dev, "chan%d: put rchan%d ", uc->id, + uc->rchan->id); + clear_bit(uc->rchan->id, ud->rchan_map); + uc->rchan = null; + } +} + +static void udma_put_tchan(struct udma_chan *uc) +{ + struct udma_dev *ud = uc->ud; + + if (uc->tchan) { + dev_dbg(ud->dev, "chan%d: put tchan%d ", uc->id, + uc->tchan->id); + clear_bit(uc->tchan->id, ud->tchan_map); + uc->tchan = null; + } +} + +static void udma_put_rflow(struct udma_chan *uc) +{ + struct udma_dev *ud = uc->ud; + + if (uc->rflow) { + dev_dbg(ud->dev, "chan%d: put rflow%d ", uc->id, + uc->rflow->id); + __udma_put_rflow(ud, uc->rflow); + uc->rflow = null; + } +} + +static void udma_free_tx_resources(struct udma_chan *uc) +{ + if (!uc->tchan) + return; + + k3_ringacc_ring_free(uc->tchan->t_ring); + k3_ringacc_ring_free(uc->tchan->tc_ring); + uc->tchan->t_ring = null; + uc->tchan->tc_ring = null; + + udma_put_tchan(uc); +} + +static int udma_alloc_tx_resources(struct udma_chan *uc) +{ + struct k3_ring_cfg ring_cfg; + struct udma_dev *ud = uc->ud; + int ret; + + ret = udma_get_tchan(uc); + if (ret) + return ret; + + uc->tchan->t_ring = k3_ringacc_request_ring(ud->ringacc, + uc->tchan->id, 0); + if (!uc->tchan->t_ring) { + ret = -ebusy; + goto err_tx_ring; + } + + uc->tchan->tc_ring = k3_ringacc_request_ring(ud->ringacc, -1, 0); + if (!uc->tchan->tc_ring) { + ret = -ebusy; + goto err_txc_ring; + } + + memset(&ring_cfg, 0, sizeof(ring_cfg)); + ring_cfg.size = k3_udma_default_ring_size; + ring_cfg.elm_size = k3_ringacc_ring_elsize_8; + ring_cfg.mode = k3_ringacc_ring_mode_message; + + ret = k3_ringacc_ring_cfg(uc->tchan->t_ring, &ring_cfg); + ret |= k3_ringacc_ring_cfg(uc->tchan->tc_ring, &ring_cfg); + + if (ret) + goto err_ringcfg; + + return 0; + +err_ringcfg: + k3_ringacc_ring_free(uc->tchan->tc_ring); + uc->tchan->tc_ring = null; +err_txc_ring: + k3_ringacc_ring_free(uc->tchan->t_ring); + uc->tchan->t_ring = null; +err_tx_ring: + udma_put_tchan(uc); + + return ret; +} + +static void udma_free_rx_resources(struct udma_chan *uc) +{ + if (!uc->rchan) + return; + + if (uc->rflow) { + struct udma_rflow *rflow = uc->rflow; + + k3_ringacc_ring_free(rflow->fd_ring); + k3_ringacc_ring_free(rflow->r_ring); + rflow->fd_ring = null; + rflow->r_ring = null; + + udma_put_rflow(uc); + } + + udma_put_rchan(uc); +} + +static int udma_alloc_rx_resources(struct udma_chan *uc) +{ + struct udma_dev *ud = uc->ud; + struct k3_ring_cfg ring_cfg; + struct udma_rflow *rflow; + int fd_ring_id; + int ret; + + ret = udma_get_rchan(uc); + if (ret) + return ret; + + /* for mem_to_mem we don't need rflow or rings */ + if (uc->config.dir == dma_mem_to_mem) + return 0; + + ret = udma_get_rflow(uc, uc->rchan->id); + if (ret) { + ret = -ebusy; + goto err_rflow; + } + + rflow = uc->rflow; + fd_ring_id = ud->tchan_cnt + ud->echan_cnt + uc->rchan->id; + rflow->fd_ring = k3_ringacc_request_ring(ud->ringacc, fd_ring_id, 0); + if (!rflow->fd_ring) { + ret = -ebusy; + goto err_rx_ring; + } + + rflow->r_ring = k3_ringacc_request_ring(ud->ringacc, -1, 0); + if (!rflow->r_ring) { + ret = -ebusy; + goto err_rxc_ring; + } + + memset(&ring_cfg, 0, sizeof(ring_cfg)); + + if (uc->config.pkt_mode) + ring_cfg.size = sg_max_segments; + else + ring_cfg.size = k3_udma_default_ring_size; + + ring_cfg.elm_size = k3_ringacc_ring_elsize_8; + ring_cfg.mode = k3_ringacc_ring_mode_message; + + ret = k3_ringacc_ring_cfg(rflow->fd_ring, &ring_cfg); + ring_cfg.size = k3_udma_default_ring_size; + ret |= k3_ringacc_ring_cfg(rflow->r_ring, &ring_cfg); + + if (ret) + goto err_ringcfg; + + return 0; + +err_ringcfg: + k3_ringacc_ring_free(rflow->r_ring); + rflow->r_ring = null; +err_rxc_ring: + k3_ringacc_ring_free(rflow->fd_ring); + rflow->fd_ring = null; +err_rx_ring: + udma_put_rflow(uc); +err_rflow: + udma_put_rchan(uc); + + return ret; +} + +#define tisci_tchan_valid_params ( \ + ti_sci_msg_value_rm_udmap_ch_pause_on_err_valid | \ + ti_sci_msg_value_rm_udmap_ch_tx_filt_einfo_valid | \ + ti_sci_msg_value_rm_udmap_ch_tx_filt_pswords_valid | \ + ti_sci_msg_value_rm_udmap_ch_chan_type_valid | \ + ti_sci_msg_value_rm_udmap_ch_tx_supr_tdpkt_valid | \ + ti_sci_msg_value_rm_udmap_ch_fetch_size_valid | \ + ti_sci_msg_value_rm_udmap_ch_cq_qnum_valid) + +#define tisci_rchan_valid_params ( \ + ti_sci_msg_value_rm_udmap_ch_pause_on_err_valid | \ + ti_sci_msg_value_rm_udmap_ch_fetch_size_valid | \ + ti_sci_msg_value_rm_udmap_ch_cq_qnum_valid | \ + ti_sci_msg_value_rm_udmap_ch_chan_type_valid | \ + ti_sci_msg_value_rm_udmap_ch_rx_ignore_short_valid | \ + ti_sci_msg_value_rm_udmap_ch_rx_ignore_long_valid | \ + ti_sci_msg_value_rm_udmap_ch_rx_flowid_start_valid | \ + ti_sci_msg_value_rm_udmap_ch_rx_flowid_cnt_valid) + +static int udma_tisci_m2m_channel_config(struct udma_chan *uc) +{ + struct udma_dev *ud = uc->ud; + struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; + const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops; + struct udma_tchan *tchan = uc->tchan; + struct udma_rchan *rchan = uc->rchan; + int ret = 0; + + /* non synchronized - mem to mem type of transfer */ + int tc_ring = k3_ringacc_get_ring_id(tchan->tc_ring); + struct ti_sci_msg_rm_udmap_tx_ch_cfg req_tx = { 0 }; + struct ti_sci_msg_rm_udmap_rx_ch_cfg req_rx = { 0 }; + + req_tx.valid_params = tisci_tchan_valid_params; + req_tx.nav_id = tisci_rm->tisci_dev_id; + req_tx.index = tchan->id; + req_tx.tx_chan_type = ti_sci_rm_udmap_chan_type_3rdp_bcopy_pbrr; + req_tx.tx_fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2; + req_tx.txcq_qnum = tc_ring; + + ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx); + if (ret) { + dev_err(ud->dev, "tchan%d cfg failed %d ", tchan->id, ret); + return ret; + } + + req_rx.valid_params = tisci_rchan_valid_params; + req_rx.nav_id = tisci_rm->tisci_dev_id; + req_rx.index = rchan->id; + req_rx.rx_fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2; + req_rx.rxcq_qnum = tc_ring; + req_rx.rx_chan_type = ti_sci_rm_udmap_chan_type_3rdp_bcopy_pbrr; + + ret = tisci_ops->rx_ch_cfg(tisci_rm->tisci, &req_rx); + if (ret) + dev_err(ud->dev, "rchan%d alloc failed %d ", rchan->id, ret); + + return ret; +} + +static int udma_tisci_tx_channel_config(struct udma_chan *uc) +{ + struct udma_dev *ud = uc->ud; + struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; + const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops; + struct udma_tchan *tchan = uc->tchan; + int tc_ring = k3_ringacc_get_ring_id(tchan->tc_ring); + struct ti_sci_msg_rm_udmap_tx_ch_cfg req_tx = { 0 }; + u32 mode, fetch_size; + int ret = 0; + + if (uc->config.pkt_mode) { + mode = ti_sci_rm_udmap_chan_type_pkt_pbrr; + fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib, + uc->config.psd_size, 0); + } else { + mode = ti_sci_rm_udmap_chan_type_3rdp_pbrr; + fetch_size = sizeof(struct cppi5_desc_hdr_t); + } + + req_tx.valid_params = tisci_tchan_valid_params; + req_tx.nav_id = tisci_rm->tisci_dev_id; + req_tx.index = tchan->id; + req_tx.tx_chan_type = mode; + req_tx.tx_supr_tdpkt = uc->config.notdpkt; + req_tx.tx_fetch_size = fetch_size >> 2; + req_tx.txcq_qnum = tc_ring; + + ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx); + if (ret) + dev_err(ud->dev, "tchan%d cfg failed %d ", tchan->id, ret); + + return ret; +} + +static int udma_tisci_rx_channel_config(struct udma_chan *uc) +{ + struct udma_dev *ud = uc->ud; + struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; + const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops; + struct udma_rchan *rchan = uc->rchan; + int fd_ring = k3_ringacc_get_ring_id(uc->rflow->fd_ring); + int rx_ring = k3_ringacc_get_ring_id(uc->rflow->r_ring); + struct ti_sci_msg_rm_udmap_rx_ch_cfg req_rx = { 0 }; + struct ti_sci_msg_rm_udmap_flow_cfg flow_req = { 0 }; + u32 mode, fetch_size; + int ret = 0; + + if (uc->config.pkt_mode) { + mode = ti_sci_rm_udmap_chan_type_pkt_pbrr; + fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib, + uc->config.psd_size, 0); + } else { + mode = ti_sci_rm_udmap_chan_type_3rdp_pbrr; + fetch_size = sizeof(struct cppi5_desc_hdr_t); + } + + req_rx.valid_params = tisci_rchan_valid_params; + req_rx.nav_id = tisci_rm->tisci_dev_id; + req_rx.index = rchan->id; + req_rx.rx_fetch_size = fetch_size >> 2; + req_rx.rxcq_qnum = rx_ring; + req_rx.rx_chan_type = mode; + + ret = tisci_ops->rx_ch_cfg(tisci_rm->tisci, &req_rx); + if (ret) { + dev_err(ud->dev, "rchan%d cfg failed %d ", rchan->id, ret); + return ret; + } + + flow_req.valid_params = + ti_sci_msg_value_rm_udmap_flow_einfo_present_valid | + ti_sci_msg_value_rm_udmap_flow_psinfo_present_valid | + ti_sci_msg_value_rm_udmap_flow_error_handling_valid | + ti_sci_msg_value_rm_udmap_flow_desc_type_valid | + ti_sci_msg_value_rm_udmap_flow_dest_qnum_valid | + ti_sci_msg_value_rm_udmap_flow_src_tag_hi_sel_valid | + ti_sci_msg_value_rm_udmap_flow_src_tag_lo_sel_valid | + ti_sci_msg_value_rm_udmap_flow_dest_tag_hi_sel_valid | + ti_sci_msg_value_rm_udmap_flow_dest_tag_lo_sel_valid | + ti_sci_msg_value_rm_udmap_flow_fdq0_sz0_qnum_valid | + ti_sci_msg_value_rm_udmap_flow_fdq1_qnum_valid | + ti_sci_msg_value_rm_udmap_flow_fdq2_qnum_valid | + ti_sci_msg_value_rm_udmap_flow_fdq3_qnum_valid; + + flow_req.nav_id = tisci_rm->tisci_dev_id; + flow_req.flow_index = rchan->id; + + if (uc->config.needs_epib) + flow_req.rx_einfo_present = 1; + else + flow_req.rx_einfo_present = 0; + if (uc->config.psd_size) + flow_req.rx_psinfo_present = 1; + else + flow_req.rx_psinfo_present = 0; + flow_req.rx_error_handling = 1; + flow_req.rx_dest_qnum = rx_ring; + flow_req.rx_src_tag_hi_sel = udma_rflow_srctag_none; + flow_req.rx_src_tag_lo_sel = udma_rflow_srctag_src_tag; + flow_req.rx_dest_tag_hi_sel = udma_rflow_dsttag_dst_tag_hi; + flow_req.rx_dest_tag_lo_sel = udma_rflow_dsttag_dst_tag_lo; + flow_req.rx_fdq0_sz0_qnum = fd_ring; + flow_req.rx_fdq1_qnum = fd_ring; + flow_req.rx_fdq2_qnum = fd_ring; + flow_req.rx_fdq3_qnum = fd_ring; + + ret = tisci_ops->rx_flow_cfg(tisci_rm->tisci, &flow_req); + + if (ret) + dev_err(ud->dev, "flow%d config failed: %d ", rchan->id, ret); + + return 0; +} + +static int udma_alloc_chan_resources(struct dma_chan *chan) +{ + struct udma_chan *uc = to_udma_chan(chan); + struct udma_dev *ud = to_udma_dev(chan->device); + const struct udma_match_data *match_data = ud->match_data; + struct k3_ring *irq_ring; + u32 irq_udma_idx; + int ret; + + if (uc->config.pkt_mode || uc->config.dir == dma_mem_to_mem) { + uc->use_dma_pool = true; + /* in case of mem_to_mem we have maximum of two trs */ + if (uc->config.dir == dma_mem_to_mem) { + uc->config.hdesc_size = cppi5_trdesc_calc_size( + sizeof(struct cppi5_tr_type15_t), 2); + uc->config.pkt_mode = false; + } + } + + if (uc->use_dma_pool) { + uc->hdesc_pool = dma_pool_create(uc->name, ud->ddev.dev, + uc->config.hdesc_size, + ud->desc_align, + 0); + if (!uc->hdesc_pool) { + dev_err(ud->ddev.dev, + "descriptor pool allocation failed "); + uc->use_dma_pool = false; + return -enomem; + } + } + + /* + * make sure that the completion is in a known state: + * no teardown, the channel is idle + */ + reinit_completion(&uc->teardown_completed); + complete_all(&uc->teardown_completed); + uc->state = udma_chan_is_idle; + + switch (uc->config.dir) { + case dma_mem_to_mem: + /* non synchronized - mem to mem type of transfer */ + dev_dbg(uc->ud->dev, "%s: chan%d as mem-to-mem ", __func__, + uc->id); + + ret = udma_get_chan_pair(uc); + if (ret) + return ret; + + ret = udma_alloc_tx_resources(uc); + if (ret) + return ret; + + ret = udma_alloc_rx_resources(uc); + if (ret) { + udma_free_tx_resources(uc); + return ret; + } + + uc->config.src_thread = ud->psil_base + uc->tchan->id; + uc->config.dst_thread = (ud->psil_base + uc->rchan->id) | + k3_psil_dst_thread_id_offset; + + irq_ring = uc->tchan->tc_ring; + irq_udma_idx = uc->tchan->id; + + ret = udma_tisci_m2m_channel_config(uc); + break; + case dma_mem_to_dev: + /* slave transfer synchronized - mem to dev (tx) trasnfer */ + dev_dbg(uc->ud->dev, "%s: chan%d as mem-to-dev ", __func__, + uc->id); + + ret = udma_alloc_tx_resources(uc); + if (ret) { + uc->config.remote_thread_id = -1; + return ret; + } + + uc->config.src_thread = ud->psil_base + uc->tchan->id; + uc->config.dst_thread = uc->config.remote_thread_id; + uc->config.dst_thread |= k3_psil_dst_thread_id_offset; + + irq_ring = uc->tchan->tc_ring; + irq_udma_idx = uc->tchan->id; + + ret = udma_tisci_tx_channel_config(uc); + break; + case dma_dev_to_mem: + /* slave transfer synchronized - dev to mem (rx) trasnfer */ + dev_dbg(uc->ud->dev, "%s: chan%d as dev-to-mem ", __func__, + uc->id); + + ret = udma_alloc_rx_resources(uc); + if (ret) { + uc->config.remote_thread_id = -1; + return ret; + } + + uc->config.src_thread = uc->config.remote_thread_id; + uc->config.dst_thread = (ud->psil_base + uc->rchan->id) | + k3_psil_dst_thread_id_offset; + + irq_ring = uc->rflow->r_ring; + irq_udma_idx = match_data->rchan_oes_offset + uc->rchan->id; + + ret = udma_tisci_rx_channel_config(uc); + break; + default: + /* can not happen */ + dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u) ", + __func__, uc->id, uc->config.dir); + return -einval; + } + + /* check if the channel configuration was successful */ + if (ret) + goto err_res_free; + + if (udma_is_chan_running(uc)) { + dev_warn(ud->dev, "chan%d: is running! ", uc->id); + udma_stop(uc); + if (udma_is_chan_running(uc)) { + dev_err(ud->dev, "chan%d: won't stop! ", uc->id); + goto err_res_free; + } + } + + /* psi-l pairing */ + ret = navss_psil_pair(ud, uc->config.src_thread, uc->config.dst_thread); + if (ret) { + dev_err(ud->dev, "psi-l pairing failed: 0x%04x -> 0x%04x ", + uc->config.src_thread, uc->config.dst_thread); + goto err_res_free; + } + + uc->psil_paired = true; + + uc->irq_num_ring = k3_ringacc_get_ring_irq_num(irq_ring); + if (uc->irq_num_ring <= 0) { + dev_err(ud->dev, "failed to get ring irq (index: %u) ", + k3_ringacc_get_ring_id(irq_ring)); + ret = -einval; + goto err_psi_free; + } + + ret = request_irq(uc->irq_num_ring, udma_ring_irq_handler, + irqf_trigger_high, uc->name, uc); + if (ret) { + dev_err(ud->dev, "chan%d: ring irq request failed ", uc->id); + goto err_irq_free; + } + + /* event from udma (tr events) only needed for slave tr mode channels */ + if (is_slave_direction(uc->config.dir) && !uc->config.pkt_mode) { + uc->irq_num_udma = ti_sci_inta_msi_get_virq(ud->dev, + irq_udma_idx); + if (uc->irq_num_udma <= 0) { + dev_err(ud->dev, "failed to get udma irq (index: %u) ", + irq_udma_idx); + free_irq(uc->irq_num_ring, uc); + ret = -einval; + goto err_irq_free; + } + + ret = request_irq(uc->irq_num_udma, udma_udma_irq_handler, 0, + uc->name, uc); + if (ret) { + dev_err(ud->dev, "chan%d: udma irq request failed ", + uc->id); + free_irq(uc->irq_num_ring, uc); + goto err_irq_free; + } + } else { + uc->irq_num_udma = 0; + } + + udma_reset_rings(uc); + + init_delayed_work_onstack(&uc->tx_drain.work, + udma_check_tx_completion); + return 0; + +err_irq_free: + uc->irq_num_ring = 0; + uc->irq_num_udma = 0; +err_psi_free: + navss_psil_unpair(ud, uc->config.src_thread, uc->config.dst_thread); + uc->psil_paired = false; +err_res_free: + udma_free_tx_resources(uc); + udma_free_rx_resources(uc); + + udma_reset_uchan(uc); + + if (uc->use_dma_pool) { + dma_pool_destroy(uc->hdesc_pool); + uc->use_dma_pool = false; + } + + return ret; +} + +static int udma_slave_config(struct dma_chan *chan, + struct dma_slave_config *cfg) +{ + struct udma_chan *uc = to_udma_chan(chan); + + memcpy(&uc->cfg, cfg, sizeof(uc->cfg)); + + return 0; +} + +static struct udma_desc *udma_alloc_tr_desc(struct udma_chan *uc, + size_t tr_size, int tr_count, + enum dma_transfer_direction dir) +{ + struct udma_hwdesc *hwdesc; + struct cppi5_desc_hdr_t *tr_desc; + struct udma_desc *d; + u32 reload_count = 0; + u32 ring_id; + + switch (tr_size) { + case 16: + case 32: + case 64: + case 128: + break; + default: + dev_err(uc->ud->dev, "unsupported tr size of %zu ", tr_size); + return null; + } + + /* we have only one descriptor containing multiple trs */ + d = kzalloc(sizeof(*d) + sizeof(d->hwdesc[0]), gfp_nowait); + if (!d) + return null; + + d->sglen = tr_count; + + d->hwdesc_count = 1; + hwdesc = &d->hwdesc[0]; + + /* allocate memory for dma ring descriptor */ + if (uc->use_dma_pool) { + hwdesc->cppi5_desc_size = uc->config.hdesc_size; + hwdesc->cppi5_desc_vaddr = dma_pool_zalloc(uc->hdesc_pool, + gfp_nowait, + &hwdesc->cppi5_desc_paddr); + } else { + hwdesc->cppi5_desc_size = cppi5_trdesc_calc_size(tr_size, + tr_count); + hwdesc->cppi5_desc_size = align(hwdesc->cppi5_desc_size, + uc->ud->desc_align); + hwdesc->cppi5_desc_vaddr = dma_alloc_coherent(uc->ud->dev, + hwdesc->cppi5_desc_size, + &hwdesc->cppi5_desc_paddr, + gfp_nowait); + } + + if (!hwdesc->cppi5_desc_vaddr) { + kfree(d); + return null; + } + + /* start of the tr req records */ + hwdesc->tr_req_base = hwdesc->cppi5_desc_vaddr + tr_size; + /* start address of the tr response array */ + hwdesc->tr_resp_base = hwdesc->tr_req_base + tr_size * tr_count; + + tr_desc = hwdesc->cppi5_desc_vaddr; + + if (uc->cyclic) + reload_count = cppi5_info0_trdesc_rldcnt_infinite; + + if (dir == dma_dev_to_mem) + ring_id = k3_ringacc_get_ring_id(uc->rflow->r_ring); + else + ring_id = k3_ringacc_get_ring_id(uc->tchan->tc_ring); + + cppi5_trdesc_init(tr_desc, tr_count, tr_size, 0, reload_count); + cppi5_desc_set_pktids(tr_desc, uc->id, + cppi5_info1_desc_flowid_default); + cppi5_desc_set_retpolicy(tr_desc, 0, ring_id); + + return d; +} + +static struct udma_desc * +udma_prep_slave_sg_tr(struct udma_chan *uc, struct scatterlist *sgl, + unsigned int sglen, enum dma_transfer_direction dir, + unsigned long tx_flags, void *context) +{ + enum dma_slave_buswidth dev_width; + struct scatterlist *sgent; + struct udma_desc *d; + size_t tr_size; + struct cppi5_tr_type1_t *tr_req = null; + unsigned int i; + u32 burst; + + if (dir == dma_dev_to_mem) { + dev_width = uc->cfg.src_addr_width; + burst = uc->cfg.src_maxburst; + } else if (dir == dma_mem_to_dev) { + dev_width = uc->cfg.dst_addr_width; + burst = uc->cfg.dst_maxburst; + } else { + dev_err(uc->ud->dev, "%s: bad direction? ", __func__); + return null; + } + + if (!burst) + burst = 1; + + /* now allocate and setup the descriptor. */ + tr_size = sizeof(struct cppi5_tr_type1_t); + d = udma_alloc_tr_desc(uc, tr_size, sglen, dir); + if (!d) + return null; + + d->sglen = sglen; + + tr_req = d->hwdesc[0].tr_req_base; + for_each_sg(sgl, sgent, sglen, i) { + d->residue += sg_dma_len(sgent); + + cppi5_tr_init(&tr_req[i].flags, cppi5_tr_type1, false, false, + cppi5_tr_event_size_completion, 0); + cppi5_tr_csf_set(&tr_req[i].flags, cppi5_tr_csf_supr_evt); + + tr_req[i].addr = sg_dma_address(sgent); + tr_req[i].icnt0 = burst * dev_width; + tr_req[i].dim1 = burst * dev_width; + tr_req[i].icnt1 = sg_dma_len(sgent) / tr_req[i].icnt0; + } + + cppi5_tr_csf_set(&tr_req[i - 1].flags, cppi5_tr_csf_eop); + + return d; +} + +static int udma_configure_statictr(struct udma_chan *uc, struct udma_desc *d, + enum dma_slave_buswidth dev_width, + u16 elcnt) +{ + if (uc->config.ep_type != psil_ep_pdma_xy) + return 0; + + /* bus width translates to the element size (es) */ + switch (dev_width) { + case dma_slave_buswidth_1_byte: + d->static_tr.elsize = 0; + break; + case dma_slave_buswidth_2_bytes: + d->static_tr.elsize = 1; + break; + case dma_slave_buswidth_3_bytes: + d->static_tr.elsize = 2; + break; + case dma_slave_buswidth_4_bytes: + d->static_tr.elsize = 3; + break; + case dma_slave_buswidth_8_bytes: + d->static_tr.elsize = 4; + break; + default: /* not reached */ + return -einval; + } + + d->static_tr.elcnt = elcnt; + + /* + * pdma must to close the packet when the channel is in packet mode. + * for tr mode when the channel is not cyclic we also need pdma to close + * the packet otherwise the transfer will stall because pdma holds on + * the data it has received from the peripheral. + */ + if (uc->config.pkt_mode || !uc->cyclic) { + unsigned int div = dev_width * elcnt; + + if (uc->cyclic) + d->static_tr.bstcnt = d->residue / d->sglen / div; + else + d->static_tr.bstcnt = d->residue / div; + + if (uc->config.dir == dma_dev_to_mem && + d->static_tr.bstcnt > uc->ud->match_data->statictr_z_mask) + return -einval; + } else { + d->static_tr.bstcnt = 0; + } + + return 0; +} + +static struct udma_desc * +udma_prep_slave_sg_pkt(struct udma_chan *uc, struct scatterlist *sgl, + unsigned int sglen, enum dma_transfer_direction dir, + unsigned long tx_flags, void *context) +{ + struct scatterlist *sgent; + struct cppi5_host_desc_t *h_desc = null; + struct udma_desc *d; + u32 ring_id; + unsigned int i; + + d = kzalloc(sizeof(*d) + sglen * sizeof(d->hwdesc[0]), gfp_nowait); + if (!d) + return null; + + d->sglen = sglen; + d->hwdesc_count = sglen; + + if (dir == dma_dev_to_mem) + ring_id = k3_ringacc_get_ring_id(uc->rflow->r_ring); + else + ring_id = k3_ringacc_get_ring_id(uc->tchan->tc_ring); + + for_each_sg(sgl, sgent, sglen, i) { + struct udma_hwdesc *hwdesc = &d->hwdesc[i]; + dma_addr_t sg_addr = sg_dma_address(sgent); + struct cppi5_host_desc_t *desc; + size_t sg_len = sg_dma_len(sgent); + + hwdesc->cppi5_desc_vaddr = dma_pool_zalloc(uc->hdesc_pool, + gfp_nowait, + &hwdesc->cppi5_desc_paddr); + if (!hwdesc->cppi5_desc_vaddr) { + dev_err(uc->ud->dev, + "descriptor%d allocation failed ", i); + + udma_free_hwdesc(uc, d); + kfree(d); + return null; + } + + d->residue += sg_len; + hwdesc->cppi5_desc_size = uc->config.hdesc_size; + desc = hwdesc->cppi5_desc_vaddr; + + if (i == 0) { + cppi5_hdesc_init(desc, 0, 0); + /* flow and packed id */ + cppi5_desc_set_pktids(&desc->hdr, uc->id, + cppi5_info1_desc_flowid_default); + cppi5_desc_set_retpolicy(&desc->hdr, 0, ring_id); + } else { + cppi5_hdesc_reset_hbdesc(desc); + cppi5_desc_set_retpolicy(&desc->hdr, 0, 0xffff); + } + + /* attach the sg buffer to the descriptor */ + cppi5_hdesc_attach_buf(desc, sg_addr, sg_len, sg_addr, sg_len); + + /* attach link as host buffer descriptor */ + if (h_desc) + cppi5_hdesc_link_hbdesc(h_desc, + hwdesc->cppi5_desc_paddr); + + if (dir == dma_mem_to_dev) + h_desc = desc; + } + + if (d->residue >= sz_4m) { + dev_err(uc->ud->dev, + "%s: transfer size %u is over the supported 4m range ", + __func__, d->residue); + udma_free_hwdesc(uc, d); + kfree(d); + return null; + } + + h_desc = d->hwdesc[0].cppi5_desc_vaddr; + cppi5_hdesc_set_pktlen(h_desc, d->residue); + + return d; +} + +static int udma_attach_metadata(struct dma_async_tx_descriptor *desc, + void *data, size_t len) +{ + struct udma_desc *d = to_udma_desc(desc); + struct udma_chan *uc = to_udma_chan(desc->chan); + struct cppi5_host_desc_t *h_desc; + u32 psd_size = len; + u32 flags = 0; + + if (!uc->config.pkt_mode || !uc->config.metadata_size) + return -enotsupp; + + if (!data || len > uc->config.metadata_size) + return -einval; + + if (uc->config.needs_epib && len < cppi5_info0_hdesc_epib_size) + return -einval; + + h_desc = d->hwdesc[0].cppi5_desc_vaddr; + if (d->dir == dma_mem_to_dev) + memcpy(h_desc->epib, data, len); + + if (uc->config.needs_epib) + psd_size -= cppi5_info0_hdesc_epib_size; + + d->metadata = data; + d->metadata_size = len; + if (uc->config.needs_epib) + flags |= cppi5_info0_hdesc_epib_present; + + cppi5_hdesc_update_flags(h_desc, flags); + cppi5_hdesc_update_psdata_size(h_desc, psd_size); + + return 0; +} + +static void *udma_get_metadata_ptr(struct dma_async_tx_descriptor *desc, + size_t *payload_len, size_t *max_len) +{ + struct udma_desc *d = to_udma_desc(desc); + struct udma_chan *uc = to_udma_chan(desc->chan); + struct cppi5_host_desc_t *h_desc; + + if (!uc->config.pkt_mode || !uc->config.metadata_size) + return err_ptr(-enotsupp); + + h_desc = d->hwdesc[0].cppi5_desc_vaddr; + + *max_len = uc->config.metadata_size; + + *payload_len = cppi5_hdesc_epib_present(&h_desc->hdr) ? + cppi5_info0_hdesc_epib_size : 0; + *payload_len += cppi5_hdesc_get_psdata_size(h_desc); + + return h_desc->epib; +} + +static int udma_set_metadata_len(struct dma_async_tx_descriptor *desc, + size_t payload_len) +{ + struct udma_desc *d = to_udma_desc(desc); + struct udma_chan *uc = to_udma_chan(desc->chan); + struct cppi5_host_desc_t *h_desc; + u32 psd_size = payload_len; + u32 flags = 0; + + if (!uc->config.pkt_mode || !uc->config.metadata_size) + return -enotsupp; + + if (payload_len > uc->config.metadata_size) + return -einval; + + if (uc->config.needs_epib && payload_len < cppi5_info0_hdesc_epib_size) + return -einval; + + h_desc = d->hwdesc[0].cppi5_desc_vaddr; + + if (uc->config.needs_epib) { + psd_size -= cppi5_info0_hdesc_epib_size; + flags |= cppi5_info0_hdesc_epib_present; + } + + cppi5_hdesc_update_flags(h_desc, flags); + cppi5_hdesc_update_psdata_size(h_desc, psd_size); + + return 0; +} + +static struct dma_descriptor_metadata_ops metadata_ops = { + .attach = udma_attach_metadata, + .get_ptr = udma_get_metadata_ptr, + .set_len = udma_set_metadata_len, +}; + +static struct dma_async_tx_descriptor * +udma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sglen, enum dma_transfer_direction dir, + unsigned long tx_flags, void *context) +{ + struct udma_chan *uc = to_udma_chan(chan); + enum dma_slave_buswidth dev_width; + struct udma_desc *d; + u32 burst; + + if (dir != uc->config.dir) { + dev_err(chan->device->dev, + "%s: chan%d is for %s, not supporting %s ", + __func__, uc->id, + dmaengine_get_direction_text(uc->config.dir), + dmaengine_get_direction_text(dir)); + return null; + } + + if (dir == dma_dev_to_mem) { + dev_width = uc->cfg.src_addr_width; + burst = uc->cfg.src_maxburst; + } else if (dir == dma_mem_to_dev) { + dev_width = uc->cfg.dst_addr_width; + burst = uc->cfg.dst_maxburst; + } else { + dev_err(chan->device->dev, "%s: bad direction? ", __func__); + return null; + } + + if (!burst) + burst = 1; + + if (uc->config.pkt_mode) + d = udma_prep_slave_sg_pkt(uc, sgl, sglen, dir, tx_flags, + context); + else + d = udma_prep_slave_sg_tr(uc, sgl, sglen, dir, tx_flags, + context); + + if (!d) + return null; + + d->dir = dir; + d->desc_idx = 0; + d->tr_idx = 0; + + /* static tr for remote pdma */ + if (udma_configure_statictr(uc, d, dev_width, burst)) { + dev_err(uc->ud->dev, + "%s: statictr z is limted to maximum 4095 (%u) ", + __func__, d->static_tr.bstcnt); + + udma_free_hwdesc(uc, d); + kfree(d); + return null; + } + + if (uc->config.metadata_size) + d->vd.tx.metadata_ops = &metadata_ops; + + return vchan_tx_prep(&uc->vc, &d->vd, tx_flags); +} + +static struct udma_desc * +udma_prep_dma_cyclic_tr(struct udma_chan *uc, dma_addr_t buf_addr, + size_t buf_len, size_t period_len, + enum dma_transfer_direction dir, unsigned long flags) +{ + enum dma_slave_buswidth dev_width; + struct udma_desc *d; + size_t tr_size; + struct cppi5_tr_type1_t *tr_req; + unsigned int i; + unsigned int periods = buf_len / period_len; + u32 burst; + + if (dir == dma_dev_to_mem) { + dev_width = uc->cfg.src_addr_width; + burst = uc->cfg.src_maxburst; + } else if (dir == dma_mem_to_dev) { + dev_width = uc->cfg.dst_addr_width; + burst = uc->cfg.dst_maxburst; + } else { + dev_err(uc->ud->dev, "%s: bad direction? ", __func__); + return null; + } + + if (!burst) + burst = 1; + + /* now allocate and setup the descriptor. */ + tr_size = sizeof(struct cppi5_tr_type1_t); + d = udma_alloc_tr_desc(uc, tr_size, periods, dir); + if (!d) + return null; + + tr_req = d->hwdesc[0].tr_req_base; + for (i = 0; i < periods; i++) { + cppi5_tr_init(&tr_req[i].flags, cppi5_tr_type1, false, false, + cppi5_tr_event_size_completion, 0); + + tr_req[i].addr = buf_addr + period_len * i; + tr_req[i].icnt0 = dev_width; + tr_req[i].icnt1 = period_len / dev_width; + tr_req[i].dim1 = dev_width; + + if (!(flags & dma_prep_interrupt)) + cppi5_tr_csf_set(&tr_req[i].flags, + cppi5_tr_csf_supr_evt); + } + + return d; +} + +static struct udma_desc * +udma_prep_dma_cyclic_pkt(struct udma_chan *uc, dma_addr_t buf_addr, + size_t buf_len, size_t period_len, + enum dma_transfer_direction dir, unsigned long flags) +{ + struct udma_desc *d; + u32 ring_id; + int i; + int periods = buf_len / period_len; + + if (periods > (k3_udma_default_ring_size - 1)) + return null; + + if (period_len >= sz_4m) + return null; + + d = kzalloc(sizeof(*d) + periods * sizeof(d->hwdesc[0]), gfp_nowait); + if (!d) + return null; + + d->hwdesc_count = periods; + + /* todo: re-check this... */ + if (dir == dma_dev_to_mem) + ring_id = k3_ringacc_get_ring_id(uc->rflow->r_ring); + else + ring_id = k3_ringacc_get_ring_id(uc->tchan->tc_ring); + + for (i = 0; i < periods; i++) { + struct udma_hwdesc *hwdesc = &d->hwdesc[i]; + dma_addr_t period_addr = buf_addr + (period_len * i); + struct cppi5_host_desc_t *h_desc; + + hwdesc->cppi5_desc_vaddr = dma_pool_zalloc(uc->hdesc_pool, + gfp_nowait, + &hwdesc->cppi5_desc_paddr); + if (!hwdesc->cppi5_desc_vaddr) { + dev_err(uc->ud->dev, + "descriptor%d allocation failed ", i); + + udma_free_hwdesc(uc, d); + kfree(d); + return null; + } + + hwdesc->cppi5_desc_size = uc->config.hdesc_size; + h_desc = hwdesc->cppi5_desc_vaddr; + + cppi5_hdesc_init(h_desc, 0, 0); + cppi5_hdesc_set_pktlen(h_desc, period_len); + + /* flow and packed id */ + cppi5_desc_set_pktids(&h_desc->hdr, uc->id, + cppi5_info1_desc_flowid_default); + cppi5_desc_set_retpolicy(&h_desc->hdr, 0, ring_id); + + /* attach each period to a new descriptor */ + cppi5_hdesc_attach_buf(h_desc, + period_addr, period_len, + period_addr, period_len); + } + + return d; +} + +static struct dma_async_tx_descriptor * +udma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, + size_t period_len, enum dma_transfer_direction dir, + unsigned long flags) +{ + struct udma_chan *uc = to_udma_chan(chan); + enum dma_slave_buswidth dev_width; + struct udma_desc *d; + u32 burst; + + if (dir != uc->config.dir) { + dev_err(chan->device->dev, + "%s: chan%d is for %s, not supporting %s ", + __func__, uc->id, + dmaengine_get_direction_text(uc->config.dir), + dmaengine_get_direction_text(dir)); + return null; + } + + uc->cyclic = true; + + if (dir == dma_dev_to_mem) { + dev_width = uc->cfg.src_addr_width; + burst = uc->cfg.src_maxburst; + } else if (dir == dma_mem_to_dev) { + dev_width = uc->cfg.dst_addr_width; + burst = uc->cfg.dst_maxburst; + } else { + dev_err(uc->ud->dev, "%s: bad direction? ", __func__); + return null; + } + + if (!burst) + burst = 1; + + if (uc->config.pkt_mode) + d = udma_prep_dma_cyclic_pkt(uc, buf_addr, buf_len, period_len, + dir, flags); + else + d = udma_prep_dma_cyclic_tr(uc, buf_addr, buf_len, period_len, + dir, flags); + + if (!d) + return null; + + d->sglen = buf_len / period_len; + + d->dir = dir; + d->residue = buf_len; + + /* static tr for remote pdma */ + if (udma_configure_statictr(uc, d, dev_width, burst)) { + dev_err(uc->ud->dev, + "%s: statictr z is limted to maximum 4095 (%u) ", + __func__, d->static_tr.bstcnt); + + udma_free_hwdesc(uc, d); + kfree(d); + return null; + } + + if (uc->config.metadata_size) + d->vd.tx.metadata_ops = &metadata_ops; + + return vchan_tx_prep(&uc->vc, &d->vd, flags); +} + +static struct dma_async_tx_descriptor * +udma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, + size_t len, unsigned long tx_flags) +{ + struct udma_chan *uc = to_udma_chan(chan); + struct udma_desc *d; + struct cppi5_tr_type15_t *tr_req; + int num_tr; + size_t tr_size = sizeof(struct cppi5_tr_type15_t); + u16 tr0_cnt0, tr0_cnt1, tr1_cnt0; + + if (uc->config.dir != dma_mem_to_mem) { + dev_err(chan->device->dev, + "%s: chan%d is for %s, not supporting %s ", + __func__, uc->id, + dmaengine_get_direction_text(uc->config.dir), + dmaengine_get_direction_text(dma_mem_to_mem)); + return null; + } + + if (len < sz_64k) { + num_tr = 1; + tr0_cnt0 = len; + tr0_cnt1 = 1; + } else { + unsigned long align_to = __ffs(src | dest); + + if (align_to > 3) + align_to = 3; + /* + * keep simple: tr0: sz_64k-alignment blocks, + * tr1: the remaining + */ + num_tr = 2; + tr0_cnt0 = (sz_64k - bit(align_to)); + if (len / tr0_cnt0 >= sz_64k) { + dev_err(uc->ud->dev, "size %zu is not supported ", + len); + return null; + } + + tr0_cnt1 = len / tr0_cnt0; + tr1_cnt0 = len % tr0_cnt0; + } + + d = udma_alloc_tr_desc(uc, tr_size, num_tr, dma_mem_to_mem); + if (!d) + return null; + + d->dir = dma_mem_to_mem; + d->desc_idx = 0; + d->tr_idx = 0; + d->residue = len; + + tr_req = d->hwdesc[0].tr_req_base; + + cppi5_tr_init(&tr_req[0].flags, cppi5_tr_type15, false, true, + cppi5_tr_event_size_completion, 0); + cppi5_tr_csf_set(&tr_req[0].flags, cppi5_tr_csf_supr_evt); + + tr_req[0].addr = src; + tr_req[0].icnt0 = tr0_cnt0; + tr_req[0].icnt1 = tr0_cnt1; + tr_req[0].icnt2 = 1; + tr_req[0].icnt3 = 1; + tr_req[0].dim1 = tr0_cnt0; + + tr_req[0].daddr = dest; + tr_req[0].dicnt0 = tr0_cnt0; + tr_req[0].dicnt1 = tr0_cnt1; + tr_req[0].dicnt2 = 1; + tr_req[0].dicnt3 = 1; + tr_req[0].ddim1 = tr0_cnt0; + + if (num_tr == 2) { + cppi5_tr_init(&tr_req[1].flags, cppi5_tr_type15, false, true, + cppi5_tr_event_size_completion, 0); + cppi5_tr_csf_set(&tr_req[1].flags, cppi5_tr_csf_supr_evt); + + tr_req[1].addr = src + tr0_cnt1 * tr0_cnt0; + tr_req[1].icnt0 = tr1_cnt0; + tr_req[1].icnt1 = 1; + tr_req[1].icnt2 = 1; + tr_req[1].icnt3 = 1; + + tr_req[1].daddr = dest + tr0_cnt1 * tr0_cnt0; + tr_req[1].dicnt0 = tr1_cnt0; + tr_req[1].dicnt1 = 1; + tr_req[1].dicnt2 = 1; + tr_req[1].dicnt3 = 1; + } + + cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, cppi5_tr_csf_eop); + + if (uc->config.metadata_size) + d->vd.tx.metadata_ops = &metadata_ops; + + return vchan_tx_prep(&uc->vc, &d->vd, tx_flags); +} + +static void udma_issue_pending(struct dma_chan *chan) +{ + struct udma_chan *uc = to_udma_chan(chan); + unsigned long flags; + + spin_lock_irqsave(&uc->vc.lock, flags); + + /* if we have something pending and no active descriptor, then */ + if (vchan_issue_pending(&uc->vc) && !uc->desc) { + /* + * start a descriptor if the channel is not [marked as + * terminating _and_ it is still running (teardown has not + * completed yet)]. + */ + if (!(uc->state == udma_chan_is_terminating && + udma_is_chan_running(uc))) + udma_start(uc); + } + + spin_unlock_irqrestore(&uc->vc.lock, flags); +} + +static enum dma_status udma_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct udma_chan *uc = to_udma_chan(chan); + enum dma_status ret; + unsigned long flags; + + spin_lock_irqsave(&uc->vc.lock, flags); + + ret = dma_cookie_status(chan, cookie, txstate); + + if (ret == dma_in_progress && udma_is_chan_paused(uc)) + ret = dma_paused; + + if (ret == dma_complete || !txstate) + goto out; + + if (uc->desc && uc->desc->vd.tx.cookie == cookie) { + u32 peer_bcnt = 0; + u32 bcnt = 0; + u32 residue = uc->desc->residue; + u32 delay = 0; + + if (uc->desc->dir == dma_mem_to_dev) { + bcnt = udma_tchanrt_read(uc->tchan, + udma_tchan_rt_sbcnt_reg); + + if (uc->config.ep_type != psil_ep_native) { + peer_bcnt = udma_tchanrt_read(uc->tchan, + udma_tchan_rt_peer_bcnt_reg); + + if (bcnt > peer_bcnt) + delay = bcnt - peer_bcnt; + } + } else if (uc->desc->dir == dma_dev_to_mem) { + bcnt = udma_rchanrt_read(uc->rchan, + udma_rchan_rt_bcnt_reg); + + if (uc->config.ep_type != psil_ep_native) { + peer_bcnt = udma_rchanrt_read(uc->rchan, + udma_rchan_rt_peer_bcnt_reg); + + if (peer_bcnt > bcnt) + delay = peer_bcnt - bcnt; + } + } else { + bcnt = udma_tchanrt_read(uc->tchan, + udma_tchan_rt_bcnt_reg); + } + + bcnt -= uc->bcnt; + if (bcnt && !(bcnt % uc->desc->residue)) + residue = 0; + else + residue -= bcnt % uc->desc->residue; + + if (!residue && (uc->config.dir == dma_dev_to_mem || !delay)) { + ret = dma_complete; + delay = 0; + } + + dma_set_residue(txstate, residue); + dma_set_in_flight_bytes(txstate, delay); + + } else { + ret = dma_complete; + } + +out: + spin_unlock_irqrestore(&uc->vc.lock, flags); + return ret; +} + +static int udma_pause(struct dma_chan *chan) +{ + struct udma_chan *uc = to_udma_chan(chan); + + if (!uc->desc) + return -einval; + + /* pause the channel */ + switch (uc->desc->dir) { + case dma_dev_to_mem: + udma_rchanrt_update_bits(uc->rchan, + udma_rchan_rt_peer_rt_en_reg, + udma_peer_rt_en_pause, + udma_peer_rt_en_pause); + break; + case dma_mem_to_dev: + udma_tchanrt_update_bits(uc->tchan, + udma_tchan_rt_peer_rt_en_reg, + udma_peer_rt_en_pause, + udma_peer_rt_en_pause); + break; + case dma_mem_to_mem: + udma_tchanrt_update_bits(uc->tchan, udma_tchan_rt_ctl_reg, + udma_chan_rt_ctl_pause, + udma_chan_rt_ctl_pause); + break; + default: + return -einval; + } + + return 0; +} + +static int udma_resume(struct dma_chan *chan) +{ + struct udma_chan *uc = to_udma_chan(chan); + + if (!uc->desc) + return -einval; + + /* resume the channel */ + switch (uc->desc->dir) { + case dma_dev_to_mem: + udma_rchanrt_update_bits(uc->rchan, + udma_rchan_rt_peer_rt_en_reg, + udma_peer_rt_en_pause, 0); + + break; + case dma_mem_to_dev: + udma_tchanrt_update_bits(uc->tchan, + udma_tchan_rt_peer_rt_en_reg, + udma_peer_rt_en_pause, 0); + break; + case dma_mem_to_mem: + udma_tchanrt_update_bits(uc->tchan, udma_tchan_rt_ctl_reg, + udma_chan_rt_ctl_pause, 0); + break; + default: + return -einval; + } + + return 0; +} + +static int udma_terminate_all(struct dma_chan *chan) +{ + struct udma_chan *uc = to_udma_chan(chan); + unsigned long flags; + list_head(head); + + spin_lock_irqsave(&uc->vc.lock, flags); + + if (udma_is_chan_running(uc)) + udma_stop(uc); + + if (uc->desc) { + uc->terminated_desc = uc->desc; + uc->desc = null; + uc->terminated_desc->terminated = true; + cancel_delayed_work(&uc->tx_drain.work); + } + + uc->paused = false; + + vchan_get_all_descriptors(&uc->vc, &head); + spin_unlock_irqrestore(&uc->vc.lock, flags); + vchan_dma_desc_free_list(&uc->vc, &head); + + return 0; +} + +static void udma_synchronize(struct dma_chan *chan) +{ + struct udma_chan *uc = to_udma_chan(chan); + unsigned long timeout = msecs_to_jiffies(1000); + + vchan_synchronize(&uc->vc); + + if (uc->state == udma_chan_is_terminating) { + timeout = wait_for_completion_timeout(&uc->teardown_completed, + timeout); + if (!timeout) { + dev_warn(uc->ud->dev, "chan%d teardown timeout! ", + uc->id); + udma_dump_chan_stdata(uc); + udma_reset_chan(uc, true); + } + } + + udma_reset_chan(uc, false); + if (udma_is_chan_running(uc)) + dev_warn(uc->ud->dev, "chan%d refused to stop! ", uc->id); + + cancel_delayed_work_sync(&uc->tx_drain.work); + udma_reset_rings(uc); +} + +static void udma_desc_pre_callback(struct virt_dma_chan *vc, + struct virt_dma_desc *vd, + struct dmaengine_result *result) +{ + struct udma_chan *uc = to_udma_chan(&vc->chan); + struct udma_desc *d; + + if (!vd) + return; + + d = to_udma_desc(&vd->tx); + + if (d->metadata_size) + udma_fetch_epib(uc, d); + + /* provide residue information for the client */ + if (result) { + void *desc_vaddr = udma_curr_cppi5_desc_vaddr(d, d->desc_idx); + + if (cppi5_desc_get_type(desc_vaddr) == + cppi5_info0_desc_type_val_host) { + result->residue = d->residue - + cppi5_hdesc_get_pktlen(desc_vaddr); + if (result->residue) + result->result = dma_trans_aborted; + else + result->result = dma_trans_noerror; + } else { + result->residue = 0; + result->result = dma_trans_noerror; + } + } +} + +/* + * this tasklet handles the completion of a dma descriptor by + * calling its callback and freeing it. + */ +static void udma_vchan_complete(unsigned long arg) +{ + struct virt_dma_chan *vc = (struct virt_dma_chan *)arg; + struct virt_dma_desc *vd, *_vd; + struct dmaengine_desc_callback cb; + list_head(head); + + spin_lock_irq(&vc->lock); + list_splice_tail_init(&vc->desc_completed, &head); + vd = vc->cyclic; + if (vd) { + vc->cyclic = null; + dmaengine_desc_get_callback(&vd->tx, &cb); + } else { + memset(&cb, 0, sizeof(cb)); + } + spin_unlock_irq(&vc->lock); + + udma_desc_pre_callback(vc, vd, null); + dmaengine_desc_callback_invoke(&cb, null); + + list_for_each_entry_safe(vd, _vd, &head, node) { + struct dmaengine_result result; + + dmaengine_desc_get_callback(&vd->tx, &cb); + + list_del(&vd->node); + + udma_desc_pre_callback(vc, vd, &result); + dmaengine_desc_callback_invoke(&cb, &result); + + vchan_vdesc_fini(vd); + } +} + +static void udma_free_chan_resources(struct dma_chan *chan) +{ + struct udma_chan *uc = to_udma_chan(chan); + struct udma_dev *ud = to_udma_dev(chan->device); + + udma_terminate_all(chan); + if (uc->terminated_desc) { + udma_reset_chan(uc, false); + udma_reset_rings(uc); + } + + cancel_delayed_work_sync(&uc->tx_drain.work); + destroy_delayed_work_on_stack(&uc->tx_drain.work); + + if (uc->irq_num_ring > 0) { + free_irq(uc->irq_num_ring, uc); + + uc->irq_num_ring = 0; + } + if (uc->irq_num_udma > 0) { + free_irq(uc->irq_num_udma, uc); + + uc->irq_num_udma = 0; + } + + /* release psi-l pairing */ + if (uc->psil_paired) { + navss_psil_unpair(ud, uc->config.src_thread, + uc->config.dst_thread); + uc->psil_paired = false; + } + + vchan_free_chan_resources(&uc->vc); + tasklet_kill(&uc->vc.task); + + udma_free_tx_resources(uc); + udma_free_rx_resources(uc); + udma_reset_uchan(uc); + + if (uc->use_dma_pool) { + dma_pool_destroy(uc->hdesc_pool); + uc->use_dma_pool = false; + } +} + +static struct platform_driver udma_driver; + +static bool udma_dma_filter_fn(struct dma_chan *chan, void *param) +{ + struct udma_chan_config *ucc; + struct psil_endpoint_config *ep_config; + struct udma_chan *uc; + struct udma_dev *ud; + u32 *args; + + if (chan->device->dev->driver != &udma_driver.driver) + return false; + + uc = to_udma_chan(chan); + ucc = &uc->config; + ud = uc->ud; + args = param; + + ucc->remote_thread_id = args[0]; + + if (ucc->remote_thread_id & k3_psil_dst_thread_id_offset) + ucc->dir = dma_mem_to_dev; + else + ucc->dir = dma_dev_to_mem; + + ep_config = psil_get_ep_config(ucc->remote_thread_id); + if (is_err(ep_config)) { + dev_err(ud->dev, "no configuration for psi-l thread 0x%04x ", + ucc->remote_thread_id); + ucc->dir = dma_mem_to_mem; + ucc->remote_thread_id = -1; + return false; + } + + ucc->pkt_mode = ep_config->pkt_mode; + ucc->channel_tpl = ep_config->channel_tpl; + ucc->notdpkt = ep_config->notdpkt; + ucc->ep_type = ep_config->ep_type; + + if (ucc->ep_type != psil_ep_native) { + const struct udma_match_data *match_data = ud->match_data; + + if (match_data->flags & udma_flag_pdma_acc32) + ucc->enable_acc32 = ep_config->pdma_acc32; + if (match_data->flags & udma_flag_pdma_burst) + ucc->enable_burst = ep_config->pdma_burst; + } + + ucc->needs_epib = ep_config->needs_epib; + ucc->psd_size = ep_config->psd_size; + ucc->metadata_size = + (ucc->needs_epib ? cppi5_info0_hdesc_epib_size : 0) + + ucc->psd_size; + + if (ucc->pkt_mode) + ucc->hdesc_size = align(sizeof(struct cppi5_host_desc_t) + + ucc->metadata_size, ud->desc_align); + + dev_dbg(ud->dev, "chan%d: remote thread: 0x%04x (%s) ", uc->id, + ucc->remote_thread_id, dmaengine_get_direction_text(ucc->dir)); + + return true; +} + +static struct dma_chan *udma_of_xlate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + struct udma_dev *ud = ofdma->of_dma_data; + dma_cap_mask_t mask = ud->ddev.cap_mask; + struct dma_chan *chan; + + if (dma_spec->args_count != 1) + return null; + + chan = __dma_request_channel(&mask, udma_dma_filter_fn, + &dma_spec->args[0], ofdma->of_node); + if (!chan) { + dev_err(ud->dev, "get channel fail in %s. ", __func__); + return err_ptr(-einval); + } + + return chan; +} + +static struct udma_match_data am654_main_data = { + .psil_base = 0x1000, + .enable_memcpy_support = true, + .statictr_z_mask = genmask(11, 0), + .rchan_oes_offset = 0x2000, + .tpl_levels = 2, + .level_start_idx = { + [0] = 8, /* normal channels */ + [1] = 0, /* high throughput channels */ + }, +}; + +static struct udma_match_data am654_mcu_data = { + .psil_base = 0x6000, + .enable_memcpy_support = false, /* mem_to_mem is slow via mcu udma */ + .statictr_z_mask = genmask(11, 0), + .rchan_oes_offset = 0x2000, + .tpl_levels = 2, + .level_start_idx = { + [0] = 2, /* normal channels */ + [1] = 0, /* high throughput channels */ + }, +}; + +static struct udma_match_data j721e_main_data = { + .psil_base = 0x1000, + .enable_memcpy_support = true, + .flags = udma_flag_pdma_acc32 | udma_flag_pdma_burst, + .statictr_z_mask = genmask(23, 0), + .rchan_oes_offset = 0x400, + .tpl_levels = 3, + .level_start_idx = { + [0] = 16, /* normal channels */ + [1] = 4, /* high throughput channels */ + [2] = 0, /* ultra high throughput channels */ + }, +}; + +static struct udma_match_data j721e_mcu_data = { + .psil_base = 0x6000, + .enable_memcpy_support = false, /* mem_to_mem is slow via mcu udma */ + .flags = udma_flag_pdma_acc32 | udma_flag_pdma_burst, + .statictr_z_mask = genmask(23, 0), + .rchan_oes_offset = 0x400, + .tpl_levels = 2, + .level_start_idx = { + [0] = 2, /* normal channels */ + [1] = 0, /* high throughput channels */ + }, +}; + +static const struct of_device_id udma_of_match[] = { + { + .compatible = "ti,am654-navss-main-udmap", + .data = &am654_main_data, + }, + { + .compatible = "ti,am654-navss-mcu-udmap", + .data = &am654_mcu_data, + }, { + .compatible = "ti,j721e-navss-main-udmap", + .data = &j721e_main_data, + }, { + .compatible = "ti,j721e-navss-mcu-udmap", + .data = &j721e_mcu_data, + }, + { /* sentinel */ }, +}; + +static int udma_get_mmrs(struct platform_device *pdev, struct udma_dev *ud) +{ + struct resource *res; + int i; + + for (i = 0; i < mmr_last; i++) { + res = platform_get_resource_byname(pdev, ioresource_mem, + mmr_names[i]); + ud->mmrs[i] = devm_ioremap_resource(&pdev->dev, res); + if (is_err(ud->mmrs[i])) + return ptr_err(ud->mmrs[i]); + } + + return 0; +} + +static int udma_setup_resources(struct udma_dev *ud) +{ + struct device *dev = ud->dev; + int ch_count, ret, i, j; + u32 cap2, cap3; + struct ti_sci_resource_desc *rm_desc; + struct ti_sci_resource *rm_res, irq_res; + struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; + static const char * const range_names[] = { "ti,sci-rm-range-tchan", + "ti,sci-rm-range-rchan", + "ti,sci-rm-range-rflow" }; + + cap2 = udma_read(ud->mmrs[mmr_gcfg], 0x28); + cap3 = udma_read(ud->mmrs[mmr_gcfg], 0x2c); + + ud->rflow_cnt = cap3 & 0x3fff; + ud->tchan_cnt = cap2 & 0x1ff; + ud->echan_cnt = (cap2 >> 9) & 0x1ff; + ud->rchan_cnt = (cap2 >> 18) & 0x1ff; + ch_count = ud->tchan_cnt + ud->rchan_cnt; + + ud->tchan_map = devm_kmalloc_array(dev, bits_to_longs(ud->tchan_cnt), + sizeof(unsigned long), gfp_kernel); + ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans), + gfp_kernel); + ud->rchan_map = devm_kmalloc_array(dev, bits_to_longs(ud->rchan_cnt), + sizeof(unsigned long), gfp_kernel); + ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), + gfp_kernel); + ud->rflow_gp_map = devm_kmalloc_array(dev, bits_to_longs(ud->rflow_cnt), + sizeof(unsigned long), + gfp_kernel); + ud->rflow_gp_map_allocated = devm_kcalloc(dev, + bits_to_longs(ud->rflow_cnt), + sizeof(unsigned long), + gfp_kernel); + ud->rflow_in_use = devm_kcalloc(dev, bits_to_longs(ud->rflow_cnt), + sizeof(unsigned long), + gfp_kernel); + ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows), + gfp_kernel); + + if (!ud->tchan_map || !ud->rchan_map || !ud->rflow_gp_map || + !ud->rflow_gp_map_allocated || !ud->tchans || !ud->rchans || + !ud->rflows || !ud->rflow_in_use) + return -enomem; + + /* + * rx flows with the same ids as rx channels are reserved to be used + * as default flows if remote hw can't generate flow_ids. those + * rx flows can be requested only explicitly by id. + */ + bitmap_set(ud->rflow_gp_map_allocated, 0, ud->rchan_cnt); + + /* by default no gp rflows are assigned to linux */ + bitmap_set(ud->rflow_gp_map, 0, ud->rflow_cnt); + + /* get resource ranges from tisci */ + for (i = 0; i < rm_range_last; i++) + tisci_rm->rm_ranges[i] = + devm_ti_sci_get_of_resource(tisci_rm->tisci, dev, + tisci_rm->tisci_dev_id, + (char *)range_names[i]); + + /* tchan ranges */ + rm_res = tisci_rm->rm_ranges[rm_range_tchan]; + if (is_err(rm_res)) { + bitmap_zero(ud->tchan_map, ud->tchan_cnt); + } else { + bitmap_fill(ud->tchan_map, ud->tchan_cnt); + for (i = 0; i < rm_res->sets; i++) { + rm_desc = &rm_res->desc[i]; + bitmap_clear(ud->tchan_map, rm_desc->start, + rm_desc->num); + dev_dbg(dev, "ti-sci-res: tchan: %d:%d ", + rm_desc->start, rm_desc->num); + } + } + irq_res.sets = rm_res->sets; + + /* rchan and matching default flow ranges */ + rm_res = tisci_rm->rm_ranges[rm_range_rchan]; + if (is_err(rm_res)) { + bitmap_zero(ud->rchan_map, ud->rchan_cnt); + } else { + bitmap_fill(ud->rchan_map, ud->rchan_cnt); + for (i = 0; i < rm_res->sets; i++) { + rm_desc = &rm_res->desc[i]; + bitmap_clear(ud->rchan_map, rm_desc->start, + rm_desc->num); + dev_dbg(dev, "ti-sci-res: rchan: %d:%d ", + rm_desc->start, rm_desc->num); + } + } + + irq_res.sets += rm_res->sets; + irq_res.desc = kcalloc(irq_res.sets, sizeof(*irq_res.desc), gfp_kernel); + rm_res = tisci_rm->rm_ranges[rm_range_tchan]; + for (i = 0; i < rm_res->sets; i++) { + irq_res.desc[i].start = rm_res->desc[i].start; + irq_res.desc[i].num = rm_res->desc[i].num; + } + rm_res = tisci_rm->rm_ranges[rm_range_rchan]; + for (j = 0; j < rm_res->sets; j++, i++) { + irq_res.desc[i].start = rm_res->desc[j].start + + ud->match_data->rchan_oes_offset; + irq_res.desc[i].num = rm_res->desc[j].num; + } + ret = ti_sci_inta_msi_domain_alloc_irqs(ud->dev, &irq_res); + kfree(irq_res.desc); + if (ret) { + dev_err(ud->dev, "failed to allocate msi interrupts "); + return ret; + } + + /* gp rflow ranges */ + rm_res = tisci_rm->rm_ranges[rm_range_rflow]; + if (is_err(rm_res)) { + /* all gp flows are assigned exclusively to linux */ + bitmap_clear(ud->rflow_gp_map, ud->rchan_cnt, + ud->rflow_cnt - ud->rchan_cnt); + } else { + for (i = 0; i < rm_res->sets; i++) { + rm_desc = &rm_res->desc[i]; + bitmap_clear(ud->rflow_gp_map, rm_desc->start, + rm_desc->num); + dev_dbg(dev, "ti-sci-res: rflow: %d:%d ", + rm_desc->start, rm_desc->num); + } + } + + ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt); + ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt); + if (!ch_count) + return -enodev; + + ud->channels = devm_kcalloc(dev, ch_count, sizeof(*ud->channels), + gfp_kernel); + if (!ud->channels) + return -enomem; + + dev_info(dev, "channels: %d (tchan: %u, rchan: %u, gp-rflow: %u) ", + ch_count, + ud->tchan_cnt - bitmap_weight(ud->tchan_map, ud->tchan_cnt), + ud->rchan_cnt - bitmap_weight(ud->rchan_map, ud->rchan_cnt), + ud->rflow_cnt - bitmap_weight(ud->rflow_gp_map, + ud->rflow_cnt)); + + return ch_count; +} + +#define ti_udmac_buswidths (bit(dma_slave_buswidth_1_byte) | \ + bit(dma_slave_buswidth_2_bytes) | \ + bit(dma_slave_buswidth_3_bytes) | \ + bit(dma_slave_buswidth_4_bytes) | \ + bit(dma_slave_buswidth_8_bytes)) + +static int udma_probe(struct platform_device *pdev) +{ + struct device_node *navss_node = pdev->dev.parent->of_node; + struct device *dev = &pdev->dev; + struct udma_dev *ud; + const struct of_device_id *match; + int i, ret; + int ch_count; + + ret = dma_coerce_mask_and_coherent(dev, dma_bit_mask(48)); + if (ret) + dev_err(dev, "failed to set dma mask stuff "); + + ud = devm_kzalloc(dev, sizeof(*ud), gfp_kernel); + if (!ud) + return -enomem; + + ret = udma_get_mmrs(pdev, ud); + if (ret) + return ret; + + ud->tisci_rm.tisci = ti_sci_get_by_phandle(dev->of_node, "ti,sci"); + if (is_err(ud->tisci_rm.tisci)) + return ptr_err(ud->tisci_rm.tisci); + + ret = of_property_read_u32(dev->of_node, "ti,sci-dev-id", + &ud->tisci_rm.tisci_dev_id); + if (ret) { + dev_err(dev, "ti,sci-dev-id read failure %d ", ret); + return ret; + } + pdev->id = ud->tisci_rm.tisci_dev_id; + + ret = of_property_read_u32(navss_node, "ti,sci-dev-id", + &ud->tisci_rm.tisci_navss_dev_id); + if (ret) { + dev_err(dev, "navss ti,sci-dev-id read failure %d ", ret); + return ret; + } + + ud->tisci_rm.tisci_udmap_ops = &ud->tisci_rm.tisci->ops.rm_udmap_ops; + ud->tisci_rm.tisci_psil_ops = &ud->tisci_rm.tisci->ops.rm_psil_ops; + + ud->ringacc = of_k3_ringacc_get_by_phandle(dev->of_node, "ti,ringacc"); + if (is_err(ud->ringacc)) + return ptr_err(ud->ringacc); + + dev->msi_domain = of_msi_get_domain(dev, dev->of_node, + domain_bus_ti_sci_inta_msi); + if (!dev->msi_domain) { + dev_err(dev, "failed to get msi domain "); + return -eprobe_defer; + } + + match = of_match_node(udma_of_match, dev->of_node); + if (!match) { + dev_err(dev, "no compatible match found "); + return -enodev; + } + ud->match_data = match->data; + + dma_cap_set(dma_slave, ud->ddev.cap_mask); + dma_cap_set(dma_cyclic, ud->ddev.cap_mask); + + ud->ddev.device_alloc_chan_resources = udma_alloc_chan_resources; + ud->ddev.device_config = udma_slave_config; + ud->ddev.device_prep_slave_sg = udma_prep_slave_sg; + ud->ddev.device_prep_dma_cyclic = udma_prep_dma_cyclic; + ud->ddev.device_issue_pending = udma_issue_pending; + ud->ddev.device_tx_status = udma_tx_status; + ud->ddev.device_pause = udma_pause; + ud->ddev.device_resume = udma_resume; + ud->ddev.device_terminate_all = udma_terminate_all; + ud->ddev.device_synchronize = udma_synchronize; + + ud->ddev.device_free_chan_resources = udma_free_chan_resources; + ud->ddev.src_addr_widths = ti_udmac_buswidths; + ud->ddev.dst_addr_widths = ti_udmac_buswidths; + ud->ddev.directions = bit(dma_dev_to_mem) | bit(dma_mem_to_dev); + ud->ddev.residue_granularity = dma_residue_granularity_burst; + ud->ddev.copy_align = dmaengine_align_8_bytes; + ud->ddev.desc_metadata_modes = desc_metadata_client | + desc_metadata_engine; + if (ud->match_data->enable_memcpy_support) { + dma_cap_set(dma_memcpy, ud->ddev.cap_mask); + ud->ddev.device_prep_dma_memcpy = udma_prep_dma_memcpy; + ud->ddev.directions |= bit(dma_mem_to_mem); + } + + ud->ddev.dev = dev; + ud->dev = dev; + ud->psil_base = ud->match_data->psil_base; + + init_list_head(&ud->ddev.channels); + init_list_head(&ud->desc_to_purge); + + ch_count = udma_setup_resources(ud); + if (ch_count <= 0) + return ch_count; + + spin_lock_init(&ud->lock); + init_work(&ud->purge_work, udma_purge_desc_work); + + ud->desc_align = 64; + if (ud->desc_align < dma_get_cache_alignment()) + ud->desc_align = dma_get_cache_alignment(); + + for (i = 0; i < ud->tchan_cnt; i++) { + struct udma_tchan *tchan = &ud->tchans[i]; + + tchan->id = i; + tchan->reg_rt = ud->mmrs[mmr_tchanrt] + i * 0x1000; + } + + for (i = 0; i < ud->rchan_cnt; i++) { + struct udma_rchan *rchan = &ud->rchans[i]; + + rchan->id = i; + rchan->reg_rt = ud->mmrs[mmr_rchanrt] + i * 0x1000; + } + + for (i = 0; i < ud->rflow_cnt; i++) { + struct udma_rflow *rflow = &ud->rflows[i]; + + rflow->id = i; + } + + for (i = 0; i < ch_count; i++) { + struct udma_chan *uc = &ud->channels[i]; + + uc->ud = ud; + uc->vc.desc_free = udma_desc_free; + uc->id = i; + uc->tchan = null; + uc->rchan = null; + uc->config.remote_thread_id = -1; + uc->config.dir = dma_mem_to_mem; + uc->name = devm_kasprintf(dev, gfp_kernel, "%s chan%d", + dev_name(dev), i); + + vchan_init(&uc->vc, &ud->ddev); + /* use custom vchan completion handling */ + tasklet_init(&uc->vc.task, udma_vchan_complete, + (unsigned long)&uc->vc); + init_completion(&uc->teardown_completed); + } + + ret = dma_async_device_register(&ud->ddev); + if (ret) { + dev_err(dev, "failed to register slave dma engine: %d ", ret); + return ret; + } + + platform_set_drvdata(pdev, ud); + + ret = of_dma_controller_register(dev->of_node, udma_of_xlate, ud); + if (ret) { + dev_err(dev, "failed to register of_dma controller "); + dma_async_device_unregister(&ud->ddev); + } + + return ret; +} + +static struct platform_driver udma_driver = { + .driver = { + .name = "ti-udma", + .of_match_table = udma_of_match, + .suppress_bind_attrs = true, + }, + .probe = udma_probe, +}; +builtin_platform_driver(udma_driver); diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h --- /dev/null +++ b/drivers/dma/ti/k3-udma.h +/* spdx-license-identifier: gpl-2.0 */ +/* + * copyright (c) 2019 texas instruments incorporated - http://www.ti.com + */ + +#ifndef k3_udma_h_ +#define k3_udma_h_ + +#include <linux/soc/ti/ti_sci_protocol.h> + +/* global registers */ +#define udma_rev_reg 0x0 +#define udma_perf_ctl_reg 0x4 +#define udma_emu_ctl_reg 0x8 +#define udma_psil_to_reg 0x10 +#define udma_utc_ctl_reg 0x1c +#define udma_cap_reg(i) (0x20 + ((i) * 4)) +#define udma_rx_flow_id_fw_oes_reg 0x80 +#define udma_rx_flow_id_fw_status_reg 0x88 + +/* tx chan rt regs */ +#define udma_tchan_rt_ctl_reg 0x0 +#define udma_tchan_rt_swtrig_reg 0x8 +#define udma_tchan_rt_stdata_reg 0x80 + +#define udma_tchan_rt_peer_reg(i) (0x200 + ((i) * 0x4)) +#define udma_tchan_rt_peer_static_tr_xy_reg \ + udma_tchan_rt_peer_reg(0) /* psi-l: 0x400 */ +#define udma_tchan_rt_peer_static_tr_z_reg \ + udma_tchan_rt_peer_reg(1) /* psi-l: 0x401 */ +#define udma_tchan_rt_peer_bcnt_reg \ + udma_tchan_rt_peer_reg(4) /* psi-l: 0x404 */ +#define udma_tchan_rt_peer_rt_en_reg \ + udma_tchan_rt_peer_reg(8) /* psi-l: 0x408 */ + +#define udma_tchan_rt_pcnt_reg 0x400 +#define udma_tchan_rt_bcnt_reg 0x408 +#define udma_tchan_rt_sbcnt_reg 0x410 + +/* rx chan rt regs */ +#define udma_rchan_rt_ctl_reg 0x0 +#define udma_rchan_rt_swtrig_reg 0x8 +#define udma_rchan_rt_stdata_reg 0x80 + +#define udma_rchan_rt_peer_reg(i) (0x200 + ((i) * 0x4)) +#define udma_rchan_rt_peer_static_tr_xy_reg \ + udma_rchan_rt_peer_reg(0) /* psi-l: 0x400 */ +#define udma_rchan_rt_peer_static_tr_z_reg \ + udma_rchan_rt_peer_reg(1) /* psi-l: 0x401 */ +#define udma_rchan_rt_peer_bcnt_reg \ + udma_rchan_rt_peer_reg(4) /* psi-l: 0x404 */ +#define udma_rchan_rt_peer_rt_en_reg \ + udma_rchan_rt_peer_reg(8) /* psi-l: 0x408 */ + +#define udma_rchan_rt_pcnt_reg 0x400 +#define udma_rchan_rt_bcnt_reg 0x408 +#define udma_rchan_rt_sbcnt_reg 0x410 + +/* udma_tchan_rt_ctl_reg/udma_rchan_rt_ctl_reg */ +#define udma_chan_rt_ctl_en bit(31) +#define udma_chan_rt_ctl_tdown bit(30) +#define udma_chan_rt_ctl_pause bit(29) +#define udma_chan_rt_ctl_ftdown bit(28) +#define udma_chan_rt_ctl_error bit(0) + +/* udma_tchan_rt_peer_rt_en_reg/udma_rchan_rt_peer_rt_en_reg (psi-l: 0x408) */ +#define udma_peer_rt_en_enable bit(31) +#define udma_peer_rt_en_teardown bit(30) +#define udma_peer_rt_en_pause bit(29) +#define udma_peer_rt_en_flush bit(28) +#define udma_peer_rt_en_idle bit(1) + +/* + * udma_tchan_rt_peer_static_tr_xy_reg / + * udma_rchan_rt_peer_static_tr_xy_reg + */ +#define pdma_static_tr_x_mask genmask(26, 24) +#define pdma_static_tr_x_shift (24) +#define pdma_static_tr_y_mask genmask(11, 0) +#define pdma_static_tr_y_shift (0) + +#define pdma_static_tr_y(x) \ + (((x) << pdma_static_tr_y_shift) & pdma_static_tr_y_mask) +#define pdma_static_tr_x(x) \ + (((x) << pdma_static_tr_x_shift) & pdma_static_tr_x_mask) + +#define pdma_static_tr_xy_acc32 bit(30) +#define pdma_static_tr_xy_burst bit(31) + +/* + * udma_tchan_rt_peer_static_tr_z_reg / + * udma_rchan_rt_peer_static_tr_z_reg + */ +#define pdma_static_tr_z(x, mask) ((x) & (mask)) + +struct udma_dev; +struct udma_tchan; +struct udma_rchan; +struct udma_rflow; + +enum udma_rm_range { + rm_range_tchan = 0, + rm_range_rchan, + rm_range_rflow, + rm_range_last, +}; + +struct udma_tisci_rm { + const struct ti_sci_handle *tisci; + const struct ti_sci_rm_udmap_ops *tisci_udmap_ops; + u32 tisci_dev_id; + + /* tisci information for psi-l thread pairing/unpairing */ + const struct ti_sci_rm_psil_ops *tisci_psil_ops; + u32 tisci_navss_dev_id; + + struct ti_sci_resource *rm_ranges[rm_range_last]; +}; + +#endif /* k3_udma_h_ */
|
DMA engines
|
25dcb5dd7b7ce5587c1df18f584ff78f51a68a94
|
peter ujfalusi
|
drivers
|
dma
|
ti
|
dmaengine: ti: k3-udma: add glue layer for non dmaengine users
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certain users can not use right now the dmaengine api due to missing features in the core. prime example is networking.
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this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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add texas instruments udma support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['c', 'kconfig', 'makefile', 'h']
| 7
| 1,567
| 1
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- most psi-l native peripheral use extra rflow ranges on a receive channel - it is also possible to have different free descriptor rings per rflow - out of order completion of descriptors on a channel - when we have several queues to handle different priority packets the - the notion of prep_slave_sg is not matching with what the streaming type - streaming type of operation - ability to fill the free descriptor ring with descriptors in - the descriptors are not backed with exact size data buffers as we don't - napi type of operation (polling instead of interrupt driven transfer) - without this we can not sustain gigabit speeds and we need to support napi - not to limit this to networking, but other high performance operations --- diff --git a/drivers/dma/ti/kconfig b/drivers/dma/ti/kconfig --- a/drivers/dma/ti/kconfig +++ b/drivers/dma/ti/kconfig +config ti_k3_udma_glue_layer + bool "texas instruments udma glue layer for non dmaengine users" + depends on arch_k3 || compile_test + depends on ti_k3_udma + help + say y here to support the k3 navss dma glue interface + if unsure, say n. + diff --git a/drivers/dma/ti/makefile b/drivers/dma/ti/makefile --- a/drivers/dma/ti/makefile +++ b/drivers/dma/ti/makefile +obj-$(config_ti_k3_udma_glue_layer) += k3-udma-glue.o diff --git a/drivers/dma/ti/k3-udma-glue.c b/drivers/dma/ti/k3-udma-glue.c --- /dev/null +++ b/drivers/dma/ti/k3-udma-glue.c +// spdx-license-identifier: gpl-2.0 +/* + * k3 navss dma glue interface + * + * copyright (c) 2019 texas instruments incorporated - http://www.ti.com + * + */ + +#include <linux/atomic.h> +#include <linux/delay.h> +#include <linux/dma-mapping.h> +#include <linux/io.h> +#include <linux/init.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/soc/ti/k3-ringacc.h> +#include <linux/dma/ti-cppi5.h> +#include <linux/dma/k3-udma-glue.h> + +#include "k3-udma.h" +#include "k3-psil-priv.h" + +struct k3_udma_glue_common { + struct device *dev; + struct udma_dev *udmax; + const struct udma_tisci_rm *tisci_rm; + struct k3_ringacc *ringacc; + u32 src_thread; + u32 dst_thread; + + u32 hdesc_size; + bool epib; + u32 psdata_size; + u32 swdata_size; +}; + +struct k3_udma_glue_tx_channel { + struct k3_udma_glue_common common; + + struct udma_tchan *udma_tchanx; + int udma_tchan_id; + + struct k3_ring *ringtx; + struct k3_ring *ringtxcq; + + bool psil_paired; + + int virq; + + atomic_t free_pkts; + bool tx_pause_on_err; + bool tx_filt_einfo; + bool tx_filt_pswords; + bool tx_supr_tdpkt; +}; + +struct k3_udma_glue_rx_flow { + struct udma_rflow *udma_rflow; + int udma_rflow_id; + struct k3_ring *ringrx; + struct k3_ring *ringrxfdq; + + int virq; +}; + +struct k3_udma_glue_rx_channel { + struct k3_udma_glue_common common; + + struct udma_rchan *udma_rchanx; + int udma_rchan_id; + bool remote; + + bool psil_paired; + + u32 swdata_size; + int flow_id_base; + + struct k3_udma_glue_rx_flow *flows; + u32 flow_num; + u32 flows_ready; +}; + +#define k3_udmax_tdown_timeout_us 1000 + +static int of_k3_udma_glue_parse(struct device_node *udmax_np, + struct k3_udma_glue_common *common) +{ + common->ringacc = of_k3_ringacc_get_by_phandle(udmax_np, + "ti,ringacc"); + if (is_err(common->ringacc)) + return ptr_err(common->ringacc); + + common->udmax = of_xudma_dev_get(udmax_np, null); + if (is_err(common->udmax)) + return ptr_err(common->udmax); + + common->tisci_rm = xudma_dev_get_tisci_rm(common->udmax); + + return 0; +} + +static int of_k3_udma_glue_parse_chn(struct device_node *chn_np, + const char *name, struct k3_udma_glue_common *common, + bool tx_chn) +{ + struct psil_endpoint_config *ep_config; + struct of_phandle_args dma_spec; + u32 thread_id; + int ret = 0; + int index; + + if (unlikely(!name)) + return -einval; + + index = of_property_match_string(chn_np, "dma-names", name); + if (index < 0) + return index; + + if (of_parse_phandle_with_args(chn_np, "dmas", "#dma-cells", index, + &dma_spec)) + return -enoent; + + thread_id = dma_spec.args[0]; + + if (tx_chn && !(thread_id & k3_psil_dst_thread_id_offset)) { + ret = -einval; + goto out_put_spec; + } + + if (!tx_chn && (thread_id & k3_psil_dst_thread_id_offset)) { + ret = -einval; + goto out_put_spec; + } + + /* get psil endpoint config */ + ep_config = psil_get_ep_config(thread_id); + if (is_err(ep_config)) { + dev_err(common->dev, + "no configuration for psi-l thread 0x%04x ", + thread_id); + ret = ptr_err(ep_config); + goto out_put_spec; + } + + common->epib = ep_config->needs_epib; + common->psdata_size = ep_config->psd_size; + + if (tx_chn) + common->dst_thread = thread_id; + else + common->src_thread = thread_id; + + ret = of_k3_udma_glue_parse(dma_spec.np, common); + +out_put_spec: + of_node_put(dma_spec.np); + return ret; +}; + +static void k3_udma_glue_dump_tx_chn(struct k3_udma_glue_tx_channel *tx_chn) +{ + struct device *dev = tx_chn->common.dev; + + dev_dbg(dev, "dump_tx_chn: " + "udma_tchan_id: %d " + "src_thread: %08x " + "dst_thread: %08x ", + tx_chn->udma_tchan_id, + tx_chn->common.src_thread, + tx_chn->common.dst_thread); +} + +static void k3_udma_glue_dump_tx_rt_chn(struct k3_udma_glue_tx_channel *chn, + char *mark) +{ + struct device *dev = chn->common.dev; + + dev_dbg(dev, "=== dump ===> %s ", mark); + dev_dbg(dev, "0x%08x: %08x ", udma_tchan_rt_ctl_reg, + xudma_tchanrt_read(chn->udma_tchanx, udma_tchan_rt_ctl_reg)); + dev_dbg(dev, "0x%08x: %08x ", udma_tchan_rt_peer_rt_en_reg, + xudma_tchanrt_read(chn->udma_tchanx, + udma_tchan_rt_peer_rt_en_reg)); + dev_dbg(dev, "0x%08x: %08x ", udma_tchan_rt_pcnt_reg, + xudma_tchanrt_read(chn->udma_tchanx, udma_tchan_rt_pcnt_reg)); + dev_dbg(dev, "0x%08x: %08x ", udma_tchan_rt_bcnt_reg, + xudma_tchanrt_read(chn->udma_tchanx, udma_tchan_rt_bcnt_reg)); + dev_dbg(dev, "0x%08x: %08x ", udma_tchan_rt_sbcnt_reg, + xudma_tchanrt_read(chn->udma_tchanx, udma_tchan_rt_sbcnt_reg)); +} + +static int k3_udma_glue_cfg_tx_chn(struct k3_udma_glue_tx_channel *tx_chn) +{ + const struct udma_tisci_rm *tisci_rm = tx_chn->common.tisci_rm; + struct ti_sci_msg_rm_udmap_tx_ch_cfg req; + + memset(&req, 0, sizeof(req)); + + req.valid_params = ti_sci_msg_value_rm_udmap_ch_pause_on_err_valid | + ti_sci_msg_value_rm_udmap_ch_tx_filt_einfo_valid | + ti_sci_msg_value_rm_udmap_ch_tx_filt_pswords_valid | + ti_sci_msg_value_rm_udmap_ch_chan_type_valid | + ti_sci_msg_value_rm_udmap_ch_tx_supr_tdpkt_valid | + ti_sci_msg_value_rm_udmap_ch_fetch_size_valid | + ti_sci_msg_value_rm_udmap_ch_cq_qnum_valid; + req.nav_id = tisci_rm->tisci_dev_id; + req.index = tx_chn->udma_tchan_id; + if (tx_chn->tx_pause_on_err) + req.tx_pause_on_err = 1; + if (tx_chn->tx_filt_einfo) + req.tx_filt_einfo = 1; + if (tx_chn->tx_filt_pswords) + req.tx_filt_pswords = 1; + req.tx_chan_type = ti_sci_rm_udmap_chan_type_pkt_pbrr; + if (tx_chn->tx_supr_tdpkt) + req.tx_supr_tdpkt = 1; + req.tx_fetch_size = tx_chn->common.hdesc_size >> 2; + req.txcq_qnum = k3_ringacc_get_ring_id(tx_chn->ringtxcq); + + return tisci_rm->tisci_udmap_ops->tx_ch_cfg(tisci_rm->tisci, &req); +} + +struct k3_udma_glue_tx_channel *k3_udma_glue_request_tx_chn(struct device *dev, + const char *name, struct k3_udma_glue_tx_channel_cfg *cfg) +{ + struct k3_udma_glue_tx_channel *tx_chn; + int ret; + + tx_chn = devm_kzalloc(dev, sizeof(*tx_chn), gfp_kernel); + if (!tx_chn) + return err_ptr(-enomem); + + tx_chn->common.dev = dev; + tx_chn->common.swdata_size = cfg->swdata_size; + tx_chn->tx_pause_on_err = cfg->tx_pause_on_err; + tx_chn->tx_filt_einfo = cfg->tx_filt_einfo; + tx_chn->tx_filt_pswords = cfg->tx_filt_pswords; + tx_chn->tx_supr_tdpkt = cfg->tx_supr_tdpkt; + + /* parse of udmap channel */ + ret = of_k3_udma_glue_parse_chn(dev->of_node, name, + &tx_chn->common, true); + if (ret) + goto err; + + tx_chn->common.hdesc_size = cppi5_hdesc_calc_size(tx_chn->common.epib, + tx_chn->common.psdata_size, + tx_chn->common.swdata_size); + + /* request and cfg udmap tx channel */ + tx_chn->udma_tchanx = xudma_tchan_get(tx_chn->common.udmax, -1); + if (is_err(tx_chn->udma_tchanx)) { + ret = ptr_err(tx_chn->udma_tchanx); + dev_err(dev, "udmax tchanx get err %d ", ret); + goto err; + } + tx_chn->udma_tchan_id = xudma_tchan_get_id(tx_chn->udma_tchanx); + + atomic_set(&tx_chn->free_pkts, cfg->txcq_cfg.size); + + /* request and cfg rings */ + tx_chn->ringtx = k3_ringacc_request_ring(tx_chn->common.ringacc, + tx_chn->udma_tchan_id, 0); + if (!tx_chn->ringtx) { + ret = -enodev; + dev_err(dev, "failed to get tx ring %u ", + tx_chn->udma_tchan_id); + goto err; + } + + tx_chn->ringtxcq = k3_ringacc_request_ring(tx_chn->common.ringacc, + -1, 0); + if (!tx_chn->ringtxcq) { + ret = -enodev; + dev_err(dev, "failed to get txcq ring "); + goto err; + } + + ret = k3_ringacc_ring_cfg(tx_chn->ringtx, &cfg->tx_cfg); + if (ret) { + dev_err(dev, "failed to cfg ringtx %d ", ret); + goto err; + } + + ret = k3_ringacc_ring_cfg(tx_chn->ringtxcq, &cfg->txcq_cfg); + if (ret) { + dev_err(dev, "failed to cfg ringtx %d ", ret); + goto err; + } + + /* request and cfg psi-l */ + tx_chn->common.src_thread = + xudma_dev_get_psil_base(tx_chn->common.udmax) + + tx_chn->udma_tchan_id; + + ret = k3_udma_glue_cfg_tx_chn(tx_chn); + if (ret) { + dev_err(dev, "failed to cfg tchan %d ", ret); + goto err; + } + + ret = xudma_navss_psil_pair(tx_chn->common.udmax, + tx_chn->common.src_thread, + tx_chn->common.dst_thread); + if (ret) { + dev_err(dev, "psi-l request err %d ", ret); + goto err; + } + + tx_chn->psil_paired = true; + + /* reset tx rt registers */ + k3_udma_glue_disable_tx_chn(tx_chn); + + k3_udma_glue_dump_tx_chn(tx_chn); + + return tx_chn; + +err: + k3_udma_glue_release_tx_chn(tx_chn); + return err_ptr(ret); +} +export_symbol_gpl(k3_udma_glue_request_tx_chn); + +void k3_udma_glue_release_tx_chn(struct k3_udma_glue_tx_channel *tx_chn) +{ + if (tx_chn->psil_paired) { + xudma_navss_psil_unpair(tx_chn->common.udmax, + tx_chn->common.src_thread, + tx_chn->common.dst_thread); + tx_chn->psil_paired = false; + } + + if (!is_err_or_null(tx_chn->udma_tchanx)) + xudma_tchan_put(tx_chn->common.udmax, + tx_chn->udma_tchanx); + + if (tx_chn->ringtxcq) + k3_ringacc_ring_free(tx_chn->ringtxcq); + + if (tx_chn->ringtx) + k3_ringacc_ring_free(tx_chn->ringtx); +} +export_symbol_gpl(k3_udma_glue_release_tx_chn); + +int k3_udma_glue_push_tx_chn(struct k3_udma_glue_tx_channel *tx_chn, + struct cppi5_host_desc_t *desc_tx, + dma_addr_t desc_dma) +{ + u32 ringtxcq_id; + + if (!atomic_add_unless(&tx_chn->free_pkts, -1, 0)) + return -enomem; + + ringtxcq_id = k3_ringacc_get_ring_id(tx_chn->ringtxcq); + cppi5_desc_set_retpolicy(&desc_tx->hdr, 0, ringtxcq_id); + + return k3_ringacc_ring_push(tx_chn->ringtx, &desc_dma); +} +export_symbol_gpl(k3_udma_glue_push_tx_chn); + +int k3_udma_glue_pop_tx_chn(struct k3_udma_glue_tx_channel *tx_chn, + dma_addr_t *desc_dma) +{ + int ret; + + ret = k3_ringacc_ring_pop(tx_chn->ringtxcq, desc_dma); + if (!ret) + atomic_inc(&tx_chn->free_pkts); + + return ret; +} +export_symbol_gpl(k3_udma_glue_pop_tx_chn); + +int k3_udma_glue_enable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn) +{ + u32 txrt_ctl; + + txrt_ctl = udma_peer_rt_en_enable; + xudma_tchanrt_write(tx_chn->udma_tchanx, + udma_tchan_rt_peer_rt_en_reg, + txrt_ctl); + + txrt_ctl = xudma_tchanrt_read(tx_chn->udma_tchanx, + udma_tchan_rt_ctl_reg); + txrt_ctl |= udma_chan_rt_ctl_en; + xudma_tchanrt_write(tx_chn->udma_tchanx, udma_tchan_rt_ctl_reg, + txrt_ctl); + + k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn en"); + return 0; +} +export_symbol_gpl(k3_udma_glue_enable_tx_chn); + +void k3_udma_glue_disable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn) +{ + k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn dis1"); + + xudma_tchanrt_write(tx_chn->udma_tchanx, udma_tchan_rt_ctl_reg, 0); + + xudma_tchanrt_write(tx_chn->udma_tchanx, + udma_tchan_rt_peer_rt_en_reg, 0); + k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn dis2"); +} +export_symbol_gpl(k3_udma_glue_disable_tx_chn); + +void k3_udma_glue_tdown_tx_chn(struct k3_udma_glue_tx_channel *tx_chn, + bool sync) +{ + int i = 0; + u32 val; + + k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn tdown1"); + + xudma_tchanrt_write(tx_chn->udma_tchanx, udma_tchan_rt_ctl_reg, + udma_chan_rt_ctl_en | udma_chan_rt_ctl_tdown); + + val = xudma_tchanrt_read(tx_chn->udma_tchanx, udma_tchan_rt_ctl_reg); + + while (sync && (val & udma_chan_rt_ctl_en)) { + val = xudma_tchanrt_read(tx_chn->udma_tchanx, + udma_tchan_rt_ctl_reg); + udelay(1); + if (i > k3_udmax_tdown_timeout_us) { + dev_err(tx_chn->common.dev, "tx tdown timeout "); + break; + } + i++; + } + + val = xudma_tchanrt_read(tx_chn->udma_tchanx, + udma_tchan_rt_peer_rt_en_reg); + if (sync && (val & udma_peer_rt_en_enable)) + dev_err(tx_chn->common.dev, "tx tdown peer not stopped "); + k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn tdown2"); +} +export_symbol_gpl(k3_udma_glue_tdown_tx_chn); + +void k3_udma_glue_reset_tx_chn(struct k3_udma_glue_tx_channel *tx_chn, + void *data, + void (*cleanup)(void *data, dma_addr_t desc_dma)) +{ + dma_addr_t desc_dma; + int occ_tx, i, ret; + + /* reset txcq as it is not input for udma - expected to be empty */ + if (tx_chn->ringtxcq) + k3_ringacc_ring_reset(tx_chn->ringtxcq); + + /* + * txq reset need to be special way as it is input for udma and its + * state cached by udma, so: + * 1) save txq occ + * 2) clean up txq and call callback .cleanup() for each desc + * 3) reset txq in a special way + */ + occ_tx = k3_ringacc_ring_get_occ(tx_chn->ringtx); + dev_dbg(tx_chn->common.dev, "tx reset occ_tx %u ", occ_tx); + + for (i = 0; i < occ_tx; i++) { + ret = k3_ringacc_ring_pop(tx_chn->ringtx, &desc_dma); + if (ret) { + dev_err(tx_chn->common.dev, "tx reset pop %d ", ret); + break; + } + cleanup(data, desc_dma); + } + + k3_ringacc_ring_reset_dma(tx_chn->ringtx, occ_tx); +} +export_symbol_gpl(k3_udma_glue_reset_tx_chn); + +u32 k3_udma_glue_tx_get_hdesc_size(struct k3_udma_glue_tx_channel *tx_chn) +{ + return tx_chn->common.hdesc_size; +} +export_symbol_gpl(k3_udma_glue_tx_get_hdesc_size); + +u32 k3_udma_glue_tx_get_txcq_id(struct k3_udma_glue_tx_channel *tx_chn) +{ + return k3_ringacc_get_ring_id(tx_chn->ringtxcq); +} +export_symbol_gpl(k3_udma_glue_tx_get_txcq_id); + +int k3_udma_glue_tx_get_irq(struct k3_udma_glue_tx_channel *tx_chn) +{ + tx_chn->virq = k3_ringacc_get_ring_irq_num(tx_chn->ringtxcq); + + return tx_chn->virq; +} +export_symbol_gpl(k3_udma_glue_tx_get_irq); + +static int k3_udma_glue_cfg_rx_chn(struct k3_udma_glue_rx_channel *rx_chn) +{ + const struct udma_tisci_rm *tisci_rm = rx_chn->common.tisci_rm; + struct ti_sci_msg_rm_udmap_rx_ch_cfg req; + int ret; + + memset(&req, 0, sizeof(req)); + + req.valid_params = ti_sci_msg_value_rm_udmap_ch_fetch_size_valid | + ti_sci_msg_value_rm_udmap_ch_cq_qnum_valid | + ti_sci_msg_value_rm_udmap_ch_chan_type_valid | + ti_sci_msg_value_rm_udmap_ch_rx_flowid_start_valid | + ti_sci_msg_value_rm_udmap_ch_rx_flowid_cnt_valid; + + req.nav_id = tisci_rm->tisci_dev_id; + req.index = rx_chn->udma_rchan_id; + req.rx_fetch_size = rx_chn->common.hdesc_size >> 2; + /* + * todo: we can't support rxcq_qnum/rchan[a]_rcq cfg with current sysfw + * and udmax impl, so just configure it to invalid value. + * req.rxcq_qnum = k3_ringacc_get_ring_id(rx_chn->flows[0].ringrx); + */ + req.rxcq_qnum = 0xffff; + if (rx_chn->flow_num && rx_chn->flow_id_base != rx_chn->udma_rchan_id) { + /* default flow + extra ones */ + req.flowid_start = rx_chn->flow_id_base; + req.flowid_cnt = rx_chn->flow_num; + } + req.rx_chan_type = ti_sci_rm_udmap_chan_type_pkt_pbrr; + + ret = tisci_rm->tisci_udmap_ops->rx_ch_cfg(tisci_rm->tisci, &req); + if (ret) + dev_err(rx_chn->common.dev, "rchan%d cfg failed %d ", + rx_chn->udma_rchan_id, ret); + + return ret; +} + +static void k3_udma_glue_release_rx_flow(struct k3_udma_glue_rx_channel *rx_chn, + u32 flow_num) +{ + struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_num]; + + if (is_err_or_null(flow->udma_rflow)) + return; + + if (flow->ringrxfdq) + k3_ringacc_ring_free(flow->ringrxfdq); + + if (flow->ringrx) + k3_ringacc_ring_free(flow->ringrx); + + xudma_rflow_put(rx_chn->common.udmax, flow->udma_rflow); + flow->udma_rflow = null; + rx_chn->flows_ready--; +} + +static int k3_udma_glue_cfg_rx_flow(struct k3_udma_glue_rx_channel *rx_chn, + u32 flow_idx, + struct k3_udma_glue_rx_flow_cfg *flow_cfg) +{ + struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_idx]; + const struct udma_tisci_rm *tisci_rm = rx_chn->common.tisci_rm; + struct device *dev = rx_chn->common.dev; + struct ti_sci_msg_rm_udmap_flow_cfg req; + int rx_ring_id; + int rx_ringfdq_id; + int ret = 0; + + flow->udma_rflow = xudma_rflow_get(rx_chn->common.udmax, + flow->udma_rflow_id); + if (is_err(flow->udma_rflow)) { + ret = ptr_err(flow->udma_rflow); + dev_err(dev, "udmax rflow get err %d ", ret); + goto err; + } + + if (flow->udma_rflow_id != xudma_rflow_get_id(flow->udma_rflow)) { + xudma_rflow_put(rx_chn->common.udmax, flow->udma_rflow); + return -enodev; + } + + /* request and cfg rings */ + flow->ringrx = k3_ringacc_request_ring(rx_chn->common.ringacc, + flow_cfg->ring_rxq_id, 0); + if (!flow->ringrx) { + ret = -enodev; + dev_err(dev, "failed to get rx ring "); + goto err; + } + + flow->ringrxfdq = k3_ringacc_request_ring(rx_chn->common.ringacc, + flow_cfg->ring_rxfdq0_id, 0); + if (!flow->ringrxfdq) { + ret = -enodev; + dev_err(dev, "failed to get rxfdq ring "); + goto err; + } + + ret = k3_ringacc_ring_cfg(flow->ringrx, &flow_cfg->rx_cfg); + if (ret) { + dev_err(dev, "failed to cfg ringrx %d ", ret); + goto err; + } + + ret = k3_ringacc_ring_cfg(flow->ringrxfdq, &flow_cfg->rxfdq_cfg); + if (ret) { + dev_err(dev, "failed to cfg ringrxfdq %d ", ret); + goto err; + } + + if (rx_chn->remote) { + rx_ring_id = ti_sci_resource_null; + rx_ringfdq_id = ti_sci_resource_null; + } else { + rx_ring_id = k3_ringacc_get_ring_id(flow->ringrx); + rx_ringfdq_id = k3_ringacc_get_ring_id(flow->ringrxfdq); + } + + memset(&req, 0, sizeof(req)); + + req.valid_params = + ti_sci_msg_value_rm_udmap_flow_einfo_present_valid | + ti_sci_msg_value_rm_udmap_flow_psinfo_present_valid | + ti_sci_msg_value_rm_udmap_flow_error_handling_valid | + ti_sci_msg_value_rm_udmap_flow_desc_type_valid | + ti_sci_msg_value_rm_udmap_flow_dest_qnum_valid | + ti_sci_msg_value_rm_udmap_flow_src_tag_hi_sel_valid | + ti_sci_msg_value_rm_udmap_flow_src_tag_lo_sel_valid | + ti_sci_msg_value_rm_udmap_flow_dest_tag_hi_sel_valid | + ti_sci_msg_value_rm_udmap_flow_dest_tag_lo_sel_valid | + ti_sci_msg_value_rm_udmap_flow_fdq0_sz0_qnum_valid | + ti_sci_msg_value_rm_udmap_flow_fdq1_qnum_valid | + ti_sci_msg_value_rm_udmap_flow_fdq2_qnum_valid | + ti_sci_msg_value_rm_udmap_flow_fdq3_qnum_valid; + req.nav_id = tisci_rm->tisci_dev_id; + req.flow_index = flow->udma_rflow_id; + if (rx_chn->common.epib) + req.rx_einfo_present = 1; + if (rx_chn->common.psdata_size) + req.rx_psinfo_present = 1; + if (flow_cfg->rx_error_handling) + req.rx_error_handling = 1; + req.rx_desc_type = 0; + req.rx_dest_qnum = rx_ring_id; + req.rx_src_tag_hi_sel = 0; + req.rx_src_tag_lo_sel = flow_cfg->src_tag_lo_sel; + req.rx_dest_tag_hi_sel = 0; + req.rx_dest_tag_lo_sel = 0; + req.rx_fdq0_sz0_qnum = rx_ringfdq_id; + req.rx_fdq1_qnum = rx_ringfdq_id; + req.rx_fdq2_qnum = rx_ringfdq_id; + req.rx_fdq3_qnum = rx_ringfdq_id; + + ret = tisci_rm->tisci_udmap_ops->rx_flow_cfg(tisci_rm->tisci, &req); + if (ret) { + dev_err(dev, "flow%d config failed: %d ", flow->udma_rflow_id, + ret); + goto err; + } + + rx_chn->flows_ready++; + dev_dbg(dev, "flow%d config done. ready:%d ", + flow->udma_rflow_id, rx_chn->flows_ready); + + return 0; +err: + k3_udma_glue_release_rx_flow(rx_chn, flow_idx); + return ret; +} + +static void k3_udma_glue_dump_rx_chn(struct k3_udma_glue_rx_channel *chn) +{ + struct device *dev = chn->common.dev; + + dev_dbg(dev, "dump_rx_chn: " + "udma_rchan_id: %d " + "src_thread: %08x " + "dst_thread: %08x " + "epib: %d " + "hdesc_size: %u " + "psdata_size: %u " + "swdata_size: %u " + "flow_id_base: %d " + "flow_num: %d ", + chn->udma_rchan_id, + chn->common.src_thread, + chn->common.dst_thread, + chn->common.epib, + chn->common.hdesc_size, + chn->common.psdata_size, + chn->common.swdata_size, + chn->flow_id_base, + chn->flow_num); +} + +static void k3_udma_glue_dump_rx_rt_chn(struct k3_udma_glue_rx_channel *chn, + char *mark) +{ + struct device *dev = chn->common.dev; + + dev_dbg(dev, "=== dump ===> %s ", mark); + + dev_dbg(dev, "0x%08x: %08x ", udma_rchan_rt_ctl_reg, + xudma_rchanrt_read(chn->udma_rchanx, udma_rchan_rt_ctl_reg)); + dev_dbg(dev, "0x%08x: %08x ", udma_rchan_rt_peer_rt_en_reg, + xudma_rchanrt_read(chn->udma_rchanx, + udma_rchan_rt_peer_rt_en_reg)); + dev_dbg(dev, "0x%08x: %08x ", udma_rchan_rt_pcnt_reg, + xudma_rchanrt_read(chn->udma_rchanx, udma_rchan_rt_pcnt_reg)); + dev_dbg(dev, "0x%08x: %08x ", udma_rchan_rt_bcnt_reg, + xudma_rchanrt_read(chn->udma_rchanx, udma_rchan_rt_bcnt_reg)); + dev_dbg(dev, "0x%08x: %08x ", udma_rchan_rt_sbcnt_reg, + xudma_rchanrt_read(chn->udma_rchanx, udma_rchan_rt_sbcnt_reg)); +} + +static int +k3_udma_glue_allocate_rx_flows(struct k3_udma_glue_rx_channel *rx_chn, + struct k3_udma_glue_rx_channel_cfg *cfg) +{ + int ret; + + /* default rflow */ + if (cfg->flow_id_use_rxchan_id) + return 0; + + /* not a gp rflows */ + if (rx_chn->flow_id_base != -1 && + !xudma_rflow_is_gp(rx_chn->common.udmax, rx_chn->flow_id_base)) + return 0; + + /* allocate range of gp rflows */ + ret = xudma_alloc_gp_rflow_range(rx_chn->common.udmax, + rx_chn->flow_id_base, + rx_chn->flow_num); + if (ret < 0) { + dev_err(rx_chn->common.dev, "udmax reserve_rflow %d cnt:%d err: %d ", + rx_chn->flow_id_base, rx_chn->flow_num, ret); + return ret; + } + rx_chn->flow_id_base = ret; + + return 0; +} + +static struct k3_udma_glue_rx_channel * +k3_udma_glue_request_rx_chn_priv(struct device *dev, const char *name, + struct k3_udma_glue_rx_channel_cfg *cfg) +{ + struct k3_udma_glue_rx_channel *rx_chn; + int ret, i; + + if (cfg->flow_id_num <= 0) + return err_ptr(-einval); + + if (cfg->flow_id_num != 1 && + (cfg->def_flow_cfg || cfg->flow_id_use_rxchan_id)) + return err_ptr(-einval); + + rx_chn = devm_kzalloc(dev, sizeof(*rx_chn), gfp_kernel); + if (!rx_chn) + return err_ptr(-enomem); + + rx_chn->common.dev = dev; + rx_chn->common.swdata_size = cfg->swdata_size; + rx_chn->remote = false; + + /* parse of udmap channel */ + ret = of_k3_udma_glue_parse_chn(dev->of_node, name, + &rx_chn->common, false); + if (ret) + goto err; + + rx_chn->common.hdesc_size = cppi5_hdesc_calc_size(rx_chn->common.epib, + rx_chn->common.psdata_size, + rx_chn->common.swdata_size); + + /* request and cfg udmap rx channel */ + rx_chn->udma_rchanx = xudma_rchan_get(rx_chn->common.udmax, -1); + if (is_err(rx_chn->udma_rchanx)) { + ret = ptr_err(rx_chn->udma_rchanx); + dev_err(dev, "udmax rchanx get err %d ", ret); + goto err; + } + rx_chn->udma_rchan_id = xudma_rchan_get_id(rx_chn->udma_rchanx); + + rx_chn->flow_num = cfg->flow_id_num; + rx_chn->flow_id_base = cfg->flow_id_base; + + /* use rx channel id as flow id: target dev can't generate flow_id */ + if (cfg->flow_id_use_rxchan_id) + rx_chn->flow_id_base = rx_chn->udma_rchan_id; + + rx_chn->flows = devm_kcalloc(dev, rx_chn->flow_num, + sizeof(*rx_chn->flows), gfp_kernel); + if (!rx_chn->flows) { + ret = -enomem; + goto err; + } + + ret = k3_udma_glue_allocate_rx_flows(rx_chn, cfg); + if (ret) + goto err; + + for (i = 0; i < rx_chn->flow_num; i++) + rx_chn->flows[i].udma_rflow_id = rx_chn->flow_id_base + i; + + /* request and cfg psi-l */ + rx_chn->common.dst_thread = + xudma_dev_get_psil_base(rx_chn->common.udmax) + + rx_chn->udma_rchan_id; + + ret = k3_udma_glue_cfg_rx_chn(rx_chn); + if (ret) { + dev_err(dev, "failed to cfg rchan %d ", ret); + goto err; + } + + /* init default rx flow only if flow_num = 1 */ + if (cfg->def_flow_cfg) { + ret = k3_udma_glue_cfg_rx_flow(rx_chn, 0, cfg->def_flow_cfg); + if (ret) + goto err; + } + + ret = xudma_navss_psil_pair(rx_chn->common.udmax, + rx_chn->common.src_thread, + rx_chn->common.dst_thread); + if (ret) { + dev_err(dev, "psi-l request err %d ", ret); + goto err; + } + + rx_chn->psil_paired = true; + + /* reset rx rt registers */ + k3_udma_glue_disable_rx_chn(rx_chn); + + k3_udma_glue_dump_rx_chn(rx_chn); + + return rx_chn; + +err: + k3_udma_glue_release_rx_chn(rx_chn); + return err_ptr(ret); +} + +static struct k3_udma_glue_rx_channel * +k3_udma_glue_request_remote_rx_chn(struct device *dev, const char *name, + struct k3_udma_glue_rx_channel_cfg *cfg) +{ + struct k3_udma_glue_rx_channel *rx_chn; + int ret, i; + + if (cfg->flow_id_num <= 0 || + cfg->flow_id_use_rxchan_id || + cfg->def_flow_cfg || + cfg->flow_id_base < 0) + return err_ptr(-einval); + + /* + * remote rx channel is under control of remote cpu core, so + * linux can only request and manipulate by dedicated rx flows + */ + + rx_chn = devm_kzalloc(dev, sizeof(*rx_chn), gfp_kernel); + if (!rx_chn) + return err_ptr(-enomem); + + rx_chn->common.dev = dev; + rx_chn->common.swdata_size = cfg->swdata_size; + rx_chn->remote = true; + rx_chn->udma_rchan_id = -1; + rx_chn->flow_num = cfg->flow_id_num; + rx_chn->flow_id_base = cfg->flow_id_base; + rx_chn->psil_paired = false; + + /* parse of udmap channel */ + ret = of_k3_udma_glue_parse_chn(dev->of_node, name, + &rx_chn->common, false); + if (ret) + goto err; + + rx_chn->common.hdesc_size = cppi5_hdesc_calc_size(rx_chn->common.epib, + rx_chn->common.psdata_size, + rx_chn->common.swdata_size); + + rx_chn->flows = devm_kcalloc(dev, rx_chn->flow_num, + sizeof(*rx_chn->flows), gfp_kernel); + if (!rx_chn->flows) { + ret = -enomem; + goto err; + } + + ret = k3_udma_glue_allocate_rx_flows(rx_chn, cfg); + if (ret) + goto err; + + for (i = 0; i < rx_chn->flow_num; i++) + rx_chn->flows[i].udma_rflow_id = rx_chn->flow_id_base + i; + + k3_udma_glue_dump_rx_chn(rx_chn); + + return rx_chn; + +err: + k3_udma_glue_release_rx_chn(rx_chn); + return err_ptr(ret); +} + +struct k3_udma_glue_rx_channel * +k3_udma_glue_request_rx_chn(struct device *dev, const char *name, + struct k3_udma_glue_rx_channel_cfg *cfg) +{ + if (cfg->remote) + return k3_udma_glue_request_remote_rx_chn(dev, name, cfg); + else + return k3_udma_glue_request_rx_chn_priv(dev, name, cfg); +} +export_symbol_gpl(k3_udma_glue_request_rx_chn); + +void k3_udma_glue_release_rx_chn(struct k3_udma_glue_rx_channel *rx_chn) +{ + int i; + + if (is_err_or_null(rx_chn->common.udmax)) + return; + + if (rx_chn->psil_paired) { + xudma_navss_psil_unpair(rx_chn->common.udmax, + rx_chn->common.src_thread, + rx_chn->common.dst_thread); + rx_chn->psil_paired = false; + } + + for (i = 0; i < rx_chn->flow_num; i++) + k3_udma_glue_release_rx_flow(rx_chn, i); + + if (xudma_rflow_is_gp(rx_chn->common.udmax, rx_chn->flow_id_base)) + xudma_free_gp_rflow_range(rx_chn->common.udmax, + rx_chn->flow_id_base, + rx_chn->flow_num); + + if (!is_err_or_null(rx_chn->udma_rchanx)) + xudma_rchan_put(rx_chn->common.udmax, + rx_chn->udma_rchanx); +} +export_symbol_gpl(k3_udma_glue_release_rx_chn); + +int k3_udma_glue_rx_flow_init(struct k3_udma_glue_rx_channel *rx_chn, + u32 flow_idx, + struct k3_udma_glue_rx_flow_cfg *flow_cfg) +{ + if (flow_idx >= rx_chn->flow_num) + return -einval; + + return k3_udma_glue_cfg_rx_flow(rx_chn, flow_idx, flow_cfg); +} +export_symbol_gpl(k3_udma_glue_rx_flow_init); + +u32 k3_udma_glue_rx_flow_get_fdq_id(struct k3_udma_glue_rx_channel *rx_chn, + u32 flow_idx) +{ + struct k3_udma_glue_rx_flow *flow; + + if (flow_idx >= rx_chn->flow_num) + return -einval; + + flow = &rx_chn->flows[flow_idx]; + + return k3_ringacc_get_ring_id(flow->ringrxfdq); +} +export_symbol_gpl(k3_udma_glue_rx_flow_get_fdq_id); + +u32 k3_udma_glue_rx_get_flow_id_base(struct k3_udma_glue_rx_channel *rx_chn) +{ + return rx_chn->flow_id_base; +} +export_symbol_gpl(k3_udma_glue_rx_get_flow_id_base); + +int k3_udma_glue_rx_flow_enable(struct k3_udma_glue_rx_channel *rx_chn, + u32 flow_idx) +{ + struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_idx]; + const struct udma_tisci_rm *tisci_rm = rx_chn->common.tisci_rm; + struct device *dev = rx_chn->common.dev; + struct ti_sci_msg_rm_udmap_flow_cfg req; + int rx_ring_id; + int rx_ringfdq_id; + int ret = 0; + + if (!rx_chn->remote) + return -einval; + + rx_ring_id = k3_ringacc_get_ring_id(flow->ringrx); + rx_ringfdq_id = k3_ringacc_get_ring_id(flow->ringrxfdq); + + memset(&req, 0, sizeof(req)); + + req.valid_params = + ti_sci_msg_value_rm_udmap_flow_dest_qnum_valid | + ti_sci_msg_value_rm_udmap_flow_fdq0_sz0_qnum_valid | + ti_sci_msg_value_rm_udmap_flow_fdq1_qnum_valid | + ti_sci_msg_value_rm_udmap_flow_fdq2_qnum_valid | + ti_sci_msg_value_rm_udmap_flow_fdq3_qnum_valid; + req.nav_id = tisci_rm->tisci_dev_id; + req.flow_index = flow->udma_rflow_id; + req.rx_dest_qnum = rx_ring_id; + req.rx_fdq0_sz0_qnum = rx_ringfdq_id; + req.rx_fdq1_qnum = rx_ringfdq_id; + req.rx_fdq2_qnum = rx_ringfdq_id; + req.rx_fdq3_qnum = rx_ringfdq_id; + + ret = tisci_rm->tisci_udmap_ops->rx_flow_cfg(tisci_rm->tisci, &req); + if (ret) { + dev_err(dev, "flow%d enable failed: %d ", flow->udma_rflow_id, + ret); + } + + return ret; +} +export_symbol_gpl(k3_udma_glue_rx_flow_enable); + +int k3_udma_glue_rx_flow_disable(struct k3_udma_glue_rx_channel *rx_chn, + u32 flow_idx) +{ + struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_idx]; + const struct udma_tisci_rm *tisci_rm = rx_chn->common.tisci_rm; + struct device *dev = rx_chn->common.dev; + struct ti_sci_msg_rm_udmap_flow_cfg req; + int ret = 0; + + if (!rx_chn->remote) + return -einval; + + memset(&req, 0, sizeof(req)); + req.valid_params = + ti_sci_msg_value_rm_udmap_flow_dest_qnum_valid | + ti_sci_msg_value_rm_udmap_flow_fdq0_sz0_qnum_valid | + ti_sci_msg_value_rm_udmap_flow_fdq1_qnum_valid | + ti_sci_msg_value_rm_udmap_flow_fdq2_qnum_valid | + ti_sci_msg_value_rm_udmap_flow_fdq3_qnum_valid; + req.nav_id = tisci_rm->tisci_dev_id; + req.flow_index = flow->udma_rflow_id; + req.rx_dest_qnum = ti_sci_resource_null; + req.rx_fdq0_sz0_qnum = ti_sci_resource_null; + req.rx_fdq1_qnum = ti_sci_resource_null; + req.rx_fdq2_qnum = ti_sci_resource_null; + req.rx_fdq3_qnum = ti_sci_resource_null; + + ret = tisci_rm->tisci_udmap_ops->rx_flow_cfg(tisci_rm->tisci, &req); + if (ret) { + dev_err(dev, "flow%d disable failed: %d ", flow->udma_rflow_id, + ret); + } + + return ret; +} +export_symbol_gpl(k3_udma_glue_rx_flow_disable); + +int k3_udma_glue_enable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn) +{ + u32 rxrt_ctl; + + if (rx_chn->remote) + return -einval; + + if (rx_chn->flows_ready < rx_chn->flow_num) + return -einval; + + rxrt_ctl = xudma_rchanrt_read(rx_chn->udma_rchanx, + udma_rchan_rt_ctl_reg); + rxrt_ctl |= udma_chan_rt_ctl_en; + xudma_rchanrt_write(rx_chn->udma_rchanx, udma_rchan_rt_ctl_reg, + rxrt_ctl); + + xudma_rchanrt_write(rx_chn->udma_rchanx, + udma_rchan_rt_peer_rt_en_reg, + udma_peer_rt_en_enable); + + k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt en"); + return 0; +} +export_symbol_gpl(k3_udma_glue_enable_rx_chn); + +void k3_udma_glue_disable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn) +{ + k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt dis1"); + + xudma_rchanrt_write(rx_chn->udma_rchanx, + udma_rchan_rt_peer_rt_en_reg, + 0); + xudma_rchanrt_write(rx_chn->udma_rchanx, udma_rchan_rt_ctl_reg, 0); + + k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt dis2"); +} +export_symbol_gpl(k3_udma_glue_disable_rx_chn); + +void k3_udma_glue_tdown_rx_chn(struct k3_udma_glue_rx_channel *rx_chn, + bool sync) +{ + int i = 0; + u32 val; + + if (rx_chn->remote) + return; + + k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt tdown1"); + + xudma_rchanrt_write(rx_chn->udma_rchanx, udma_rchan_rt_peer_rt_en_reg, + udma_peer_rt_en_enable | udma_peer_rt_en_teardown); + + val = xudma_rchanrt_read(rx_chn->udma_rchanx, udma_rchan_rt_ctl_reg); + + while (sync && (val & udma_chan_rt_ctl_en)) { + val = xudma_rchanrt_read(rx_chn->udma_rchanx, + udma_rchan_rt_ctl_reg); + udelay(1); + if (i > k3_udmax_tdown_timeout_us) { + dev_err(rx_chn->common.dev, "rx tdown timeout "); + break; + } + i++; + } + + val = xudma_rchanrt_read(rx_chn->udma_rchanx, + udma_rchan_rt_peer_rt_en_reg); + if (sync && (val & udma_peer_rt_en_enable)) + dev_err(rx_chn->common.dev, "tx tdown peer not stopped "); + k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt tdown2"); +} +export_symbol_gpl(k3_udma_glue_tdown_rx_chn); + +void k3_udma_glue_reset_rx_chn(struct k3_udma_glue_rx_channel *rx_chn, + u32 flow_num, void *data, + void (*cleanup)(void *data, dma_addr_t desc_dma), bool skip_fdq) +{ + struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_num]; + struct device *dev = rx_chn->common.dev; + dma_addr_t desc_dma; + int occ_rx, i, ret; + + /* reset rxcq as it is not input for udma - expected to be empty */ + occ_rx = k3_ringacc_ring_get_occ(flow->ringrx); + dev_dbg(dev, "rx reset flow %u occ_rx %u ", flow_num, occ_rx); + if (flow->ringrx) + k3_ringacc_ring_reset(flow->ringrx); + + /* skip rx fdq in case one fdq is used for the set of flows */ + if (skip_fdq) + return; + + /* + * rx fdq reset need to be special way as it is input for udma and its + * state cached by udma, so: + * 1) save rx fdq occ + * 2) clean up rx fdq and call callback .cleanup() for each desc + * 3) reset rx fdq in a special way + */ + occ_rx = k3_ringacc_ring_get_occ(flow->ringrxfdq); + dev_dbg(dev, "rx reset flow %u occ_rx_fdq %u ", flow_num, occ_rx); + + for (i = 0; i < occ_rx; i++) { + ret = k3_ringacc_ring_pop(flow->ringrxfdq, &desc_dma); + if (ret) { + dev_err(dev, "rx reset pop %d ", ret); + break; + } + cleanup(data, desc_dma); + } + + k3_ringacc_ring_reset_dma(flow->ringrxfdq, occ_rx); +} +export_symbol_gpl(k3_udma_glue_reset_rx_chn); + +int k3_udma_glue_push_rx_chn(struct k3_udma_glue_rx_channel *rx_chn, + u32 flow_num, struct cppi5_host_desc_t *desc_rx, + dma_addr_t desc_dma) +{ + struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_num]; + + return k3_ringacc_ring_push(flow->ringrxfdq, &desc_dma); +} +export_symbol_gpl(k3_udma_glue_push_rx_chn); + +int k3_udma_glue_pop_rx_chn(struct k3_udma_glue_rx_channel *rx_chn, + u32 flow_num, dma_addr_t *desc_dma) +{ + struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_num]; + + return k3_ringacc_ring_pop(flow->ringrx, desc_dma); +} +export_symbol_gpl(k3_udma_glue_pop_rx_chn); + +int k3_udma_glue_rx_get_irq(struct k3_udma_glue_rx_channel *rx_chn, + u32 flow_num) +{ + struct k3_udma_glue_rx_flow *flow; + + flow = &rx_chn->flows[flow_num]; + + flow->virq = k3_ringacc_get_ring_irq_num(flow->ringrx); + + return flow->virq; +} +export_symbol_gpl(k3_udma_glue_rx_get_irq); diff --git a/drivers/dma/ti/k3-udma-private.c b/drivers/dma/ti/k3-udma-private.c --- /dev/null +++ b/drivers/dma/ti/k3-udma-private.c +// spdx-license-identifier: gpl-2.0 +/* + * copyright (c) 2019 texas instruments incorporated - http://www.ti.com + * author: peter ujfalusi <peter.ujfalusi@ti.com> + */ + +int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread) +{ + return navss_psil_pair(ud, src_thread, dst_thread); +} +export_symbol(xudma_navss_psil_pair); + +int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread, u32 dst_thread) +{ + return navss_psil_unpair(ud, src_thread, dst_thread); +} +export_symbol(xudma_navss_psil_unpair); + +struct udma_dev *of_xudma_dev_get(struct device_node *np, const char *property) +{ + struct device_node *udma_node = np; + struct platform_device *pdev; + struct udma_dev *ud; + + if (property) { + udma_node = of_parse_phandle(np, property, 0); + if (!udma_node) { + pr_err("udma node is not found "); + return err_ptr(-enodev); + } + } + + pdev = of_find_device_by_node(udma_node); + if (!pdev) { + pr_debug("udma device not found "); + return err_ptr(-eprobe_defer); + } + + if (np != udma_node) + of_node_put(udma_node); + + ud = platform_get_drvdata(pdev); + if (!ud) { + pr_debug("udma has not been probed "); + return err_ptr(-eprobe_defer); + } + + return ud; +} +export_symbol(of_xudma_dev_get); + +u32 xudma_dev_get_psil_base(struct udma_dev *ud) +{ + return ud->psil_base; +} +export_symbol(xudma_dev_get_psil_base); + +struct udma_tisci_rm *xudma_dev_get_tisci_rm(struct udma_dev *ud) +{ + return &ud->tisci_rm; +} +export_symbol(xudma_dev_get_tisci_rm); + +int xudma_alloc_gp_rflow_range(struct udma_dev *ud, int from, int cnt) +{ + return __udma_alloc_gp_rflow_range(ud, from, cnt); +} +export_symbol(xudma_alloc_gp_rflow_range); + +int xudma_free_gp_rflow_range(struct udma_dev *ud, int from, int cnt) +{ + return __udma_free_gp_rflow_range(ud, from, cnt); +} +export_symbol(xudma_free_gp_rflow_range); + +bool xudma_rflow_is_gp(struct udma_dev *ud, int id) +{ + return !test_bit(id, ud->rflow_gp_map); +} +export_symbol(xudma_rflow_is_gp); + +#define xudma_get_put_resource(res) \ +struct udma_##res *xudma_##res##_get(struct udma_dev *ud, int id) \ +{ \ + return __udma_reserve_##res(ud, false, id); \ +} \ +export_symbol(xudma_##res##_get); \ + \ +void xudma_##res##_put(struct udma_dev *ud, struct udma_##res *p) \ +{ \ + clear_bit(p->id, ud->res##_map); \ +} \ +export_symbol(xudma_##res##_put) +xudma_get_put_resource(tchan); +xudma_get_put_resource(rchan); + +struct udma_rflow *xudma_rflow_get(struct udma_dev *ud, int id) +{ + return __udma_get_rflow(ud, id); +} +export_symbol(xudma_rflow_get); + +void xudma_rflow_put(struct udma_dev *ud, struct udma_rflow *p) +{ + __udma_put_rflow(ud, p); +} +export_symbol(xudma_rflow_put); + +#define xudma_get_resource_id(res) \ +int xudma_##res##_get_id(struct udma_##res *p) \ +{ \ + return p->id; \ +} \ +export_symbol(xudma_##res##_get_id) +xudma_get_resource_id(tchan); +xudma_get_resource_id(rchan); +xudma_get_resource_id(rflow); + +/* exported register access functions */ +#define xudma_rt_io_functions(res) \ +u32 xudma_##res##rt_read(struct udma_##res *p, int reg) \ +{ \ + return udma_##res##rt_read(p, reg); \ +} \ +export_symbol(xudma_##res##rt_read); \ + \ +void xudma_##res##rt_write(struct udma_##res *p, int reg, u32 val) \ +{ \ + udma_##res##rt_write(p, reg, val); \ +} \ +export_symbol(xudma_##res##rt_write) +xudma_rt_io_functions(tchan); +xudma_rt_io_functions(rchan); diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c +/** + * __udma_alloc_gp_rflow_range - alloc range of gp rx flows + * @ud: udma device + * @from: start the search from this flow id number + * @cnt: number of consecutive flow ids to allocate + * + * allocate range of rx flow ids for future use, those flows can be requested + * only using explicit flow id number. if @from is set to -1 it will try to find + * first free range. if @from is positive value it will force allocation only + * of the specified range of flows. + * + * returns -enomem if can't find free range. + * -eexist if requested range is busy. + * -einval if wrong input values passed. + * returns flow id on success. + */ +static int __udma_alloc_gp_rflow_range(struct udma_dev *ud, int from, int cnt) +{ + int start, tmp_from; + declare_bitmap(tmp, k3_udma_max_rflows); + + tmp_from = from; + if (tmp_from < 0) + tmp_from = ud->rchan_cnt; + /* default flows can't be allocated and accessible only by id */ + if (tmp_from < ud->rchan_cnt) + return -einval; + + if (tmp_from + cnt > ud->rflow_cnt) + return -einval; + + bitmap_or(tmp, ud->rflow_gp_map, ud->rflow_gp_map_allocated, + ud->rflow_cnt); + + start = bitmap_find_next_zero_area(tmp, + ud->rflow_cnt, + tmp_from, cnt, 0); + if (start >= ud->rflow_cnt) + return -enomem; + + if (from >= 0 && start != from) + return -eexist; + + bitmap_set(ud->rflow_gp_map_allocated, start, cnt); + return start; +} + +static int __udma_free_gp_rflow_range(struct udma_dev *ud, int from, int cnt) +{ + if (from < ud->rchan_cnt) + return -einval; + if (from + cnt > ud->rflow_cnt) + return -einval; + + bitmap_clear(ud->rflow_gp_map_allocated, from, cnt); + return 0; +} + - .enable_memcpy_support = false, /* mem_to_mem is slow via mcu udma */ + .enable_memcpy_support = true, /* test: dma domains */ + +/* private interfaces to udma */ +#include "k3-udma-private.c" diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h --- a/drivers/dma/ti/k3-udma.h +++ b/drivers/dma/ti/k3-udma.h +/* direct access to udma low lever resources for the glue layer */ +int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread); +int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread, + u32 dst_thread); + +struct udma_dev *of_xudma_dev_get(struct device_node *np, const char *property); +void xudma_dev_put(struct udma_dev *ud); +u32 xudma_dev_get_psil_base(struct udma_dev *ud); +struct udma_tisci_rm *xudma_dev_get_tisci_rm(struct udma_dev *ud); + +int xudma_alloc_gp_rflow_range(struct udma_dev *ud, int from, int cnt); +int xudma_free_gp_rflow_range(struct udma_dev *ud, int from, int cnt); + +struct udma_tchan *xudma_tchan_get(struct udma_dev *ud, int id); +struct udma_rchan *xudma_rchan_get(struct udma_dev *ud, int id); +struct udma_rflow *xudma_rflow_get(struct udma_dev *ud, int id); + +void xudma_tchan_put(struct udma_dev *ud, struct udma_tchan *p); +void xudma_rchan_put(struct udma_dev *ud, struct udma_rchan *p); +void xudma_rflow_put(struct udma_dev *ud, struct udma_rflow *p); + +int xudma_tchan_get_id(struct udma_tchan *p); +int xudma_rchan_get_id(struct udma_rchan *p); +int xudma_rflow_get_id(struct udma_rflow *p); + +u32 xudma_tchanrt_read(struct udma_tchan *tchan, int reg); +void xudma_tchanrt_write(struct udma_tchan *tchan, int reg, u32 val); +u32 xudma_rchanrt_read(struct udma_rchan *rchan, int reg); +void xudma_rchanrt_write(struct udma_rchan *rchan, int reg, u32 val); +bool xudma_rflow_is_gp(struct udma_dev *ud, int id); + diff --git a/include/linux/dma/k3-udma-glue.h b/include/linux/dma/k3-udma-glue.h --- /dev/null +++ b/include/linux/dma/k3-udma-glue.h +/* spdx-license-identifier: gpl-2.0 */ +/* + * copyright (c) 2019 texas instruments incorporated - http://www.ti.com + */ + +#ifndef k3_udma_glue_h_ +#define k3_udma_glue_h_ + +#include <linux/types.h> +#include <linux/soc/ti/k3-ringacc.h> +#include <linux/dma/ti-cppi5.h> + +struct k3_udma_glue_tx_channel_cfg { + struct k3_ring_cfg tx_cfg; + struct k3_ring_cfg txcq_cfg; + + bool tx_pause_on_err; + bool tx_filt_einfo; + bool tx_filt_pswords; + bool tx_supr_tdpkt; + u32 swdata_size; +}; + +struct k3_udma_glue_tx_channel; + +struct k3_udma_glue_tx_channel *k3_udma_glue_request_tx_chn(struct device *dev, + const char *name, struct k3_udma_glue_tx_channel_cfg *cfg); + +void k3_udma_glue_release_tx_chn(struct k3_udma_glue_tx_channel *tx_chn); +int k3_udma_glue_push_tx_chn(struct k3_udma_glue_tx_channel *tx_chn, + struct cppi5_host_desc_t *desc_tx, + dma_addr_t desc_dma); +int k3_udma_glue_pop_tx_chn(struct k3_udma_glue_tx_channel *tx_chn, + dma_addr_t *desc_dma); +int k3_udma_glue_enable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn); +void k3_udma_glue_disable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn); +void k3_udma_glue_tdown_tx_chn(struct k3_udma_glue_tx_channel *tx_chn, + bool sync); +void k3_udma_glue_reset_tx_chn(struct k3_udma_glue_tx_channel *tx_chn, + void *data, void (*cleanup)(void *data, dma_addr_t desc_dma)); +u32 k3_udma_glue_tx_get_hdesc_size(struct k3_udma_glue_tx_channel *tx_chn); +u32 k3_udma_glue_tx_get_txcq_id(struct k3_udma_glue_tx_channel *tx_chn); +int k3_udma_glue_tx_get_irq(struct k3_udma_glue_tx_channel *tx_chn); + +enum { + k3_udma_glue_src_tag_lo_keep = 0, + k3_udma_glue_src_tag_lo_use_flow_reg = 1, + k3_udma_glue_src_tag_lo_use_remote_flow_id = 2, + k3_udma_glue_src_tag_lo_use_remote_src_tag = 4, +}; + +/** + * k3_udma_glue_rx_flow_cfg - udma rx flow cfg + * + * @rx_cfg: rx ring configuration + * @rxfdq_cfg: rx free host pd ring configuration + * @ring_rxq_id: rx ring id (or -1 for any) + * @ring_rxfdq0_id: rx free host pd ring (fdq) if (or -1 for any) + * @rx_error_handling: rx error handling mode (0 - drop, 1 - re-try) + * @src_tag_lo_sel: rx source tag low byte selector in host pd + */ +struct k3_udma_glue_rx_flow_cfg { + struct k3_ring_cfg rx_cfg; + struct k3_ring_cfg rxfdq_cfg; + int ring_rxq_id; + int ring_rxfdq0_id; + bool rx_error_handling; + int src_tag_lo_sel; +}; + +/** + * k3_udma_glue_rx_channel_cfg - udma rx channel cfg + * + * @psdata_size: sw data is present in host pd of @swdata_size bytes + * @flow_id_base: first flow_id used by channel. + * if @flow_id_base = -1 - range of gp rflows will be + * allocated dynamically. + * @flow_id_num: number of rx flows used by channel + * @flow_id_use_rxchan_id: use rx channel id as flow id, + * used only if @flow_id_num = 1 + * @remote indication that rx channel is remote - some remote cpu + * core owns and control the rx channel. linux host only + * allowed to attach and configure rx flow within rx + * channel. if set - not rx channel operation will be + * performed by k3 navss dma glue interface. + * @def_flow_cfg default rx flow configuration, + * used only if @flow_id_num = 1 + */ +struct k3_udma_glue_rx_channel_cfg { + u32 swdata_size; + int flow_id_base; + int flow_id_num; + bool flow_id_use_rxchan_id; + bool remote; + + struct k3_udma_glue_rx_flow_cfg *def_flow_cfg; +}; + +struct k3_udma_glue_rx_channel; + +struct k3_udma_glue_rx_channel *k3_udma_glue_request_rx_chn( + struct device *dev, + const char *name, + struct k3_udma_glue_rx_channel_cfg *cfg); + +void k3_udma_glue_release_rx_chn(struct k3_udma_glue_rx_channel *rx_chn); +int k3_udma_glue_enable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn); +void k3_udma_glue_disable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn); +void k3_udma_glue_tdown_rx_chn(struct k3_udma_glue_rx_channel *rx_chn, + bool sync); +int k3_udma_glue_push_rx_chn(struct k3_udma_glue_rx_channel *rx_chn, + u32 flow_num, struct cppi5_host_desc_t *desc_tx, + dma_addr_t desc_dma); +int k3_udma_glue_pop_rx_chn(struct k3_udma_glue_rx_channel *rx_chn, + u32 flow_num, dma_addr_t *desc_dma); +int k3_udma_glue_rx_flow_init(struct k3_udma_glue_rx_channel *rx_chn, + u32 flow_idx, struct k3_udma_glue_rx_flow_cfg *flow_cfg); +u32 k3_udma_glue_rx_flow_get_fdq_id(struct k3_udma_glue_rx_channel *rx_chn, + u32 flow_idx); +u32 k3_udma_glue_rx_get_flow_id_base(struct k3_udma_glue_rx_channel *rx_chn); +int k3_udma_glue_rx_get_irq(struct k3_udma_glue_rx_channel *rx_chn, + u32 flow_num); +void k3_udma_glue_rx_put_irq(struct k3_udma_glue_rx_channel *rx_chn, + u32 flow_num); +void k3_udma_glue_reset_rx_chn(struct k3_udma_glue_rx_channel *rx_chn, + u32 flow_num, void *data, + void (*cleanup)(void *data, dma_addr_t desc_dma), + bool skip_fdq); +int k3_udma_glue_rx_flow_enable(struct k3_udma_glue_rx_channel *rx_chn, + u32 flow_idx); +int k3_udma_glue_rx_flow_disable(struct k3_udma_glue_rx_channel *rx_chn, + u32 flow_idx); + +#endif /* k3_udma_glue_h_ */
|
DMA engines
|
d702419134133db1eab2067dc6ea5723467fd917
|
grygorii strashko
|
include
|
linux
|
dma, ti
|
hwrng: iproc-rng200 - add support for bcm2711
|
bcm2711 features a rng200 hardware random number generator block. so make the driver available.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
iproc-rng200 - add support for bcm2711
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
[]
|
['c', 'kconfig']
| 2
| 2
| 1
|
--- diff --git a/drivers/char/hw_random/kconfig b/drivers/char/hw_random/kconfig --- a/drivers/char/hw_random/kconfig +++ b/drivers/char/hw_random/kconfig - depends on arch_bcm_iproc || arch_brcmstb + depends on arch_bcm_iproc || arch_bcm2835 || arch_brcmstb ---help--- diff --git a/drivers/char/hw_random/iproc-rng200.c b/drivers/char/hw_random/iproc-rng200.c --- a/drivers/char/hw_random/iproc-rng200.c +++ b/drivers/char/hw_random/iproc-rng200.c + { .compatible = "brcm,bcm2711-rng200", },
|
Hardware Random Number Generator (hwrng)
|
0f95b09a5f624964d520c8f6a2674090fb98ae25
|
stefan wahren matthias brugger mbrugger suse com florian fainelli f fainelli gmail com
|
drivers
|
char
|
hw_random
|
crypto: caam - add support for i.mx8m mini
|
the i.mx8m mini uses the same crypto engine as the i.mx8mq, but the driver is restricting the check to just the i.mx8mq.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for i.mx8m mini
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['caam']
|
['c']
| 1
| 3
| 1
|
--- diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c - of_machine_is_compatible("fsl,imx8mq")) { + of_machine_is_compatible("fsl,imx8mq") || + of_machine_is_compatible("fsl,imx8mm")) { + { .soc_id = "i.mx8mm", .data = &caam_imx7_data },
|
Cryptography hardware acceleration
|
112e7b7b6a2e33fbc5624991694d4a630f99e04e
|
adam ford
|
drivers
|
crypto
|
caam
|
crypto: caam - add support for i.mx8m nano
|
add support for the crypto engine used in i.mx8mn (i.mx 8m "nano"), which is very similar to the one used in i.mx8mq, i.mx8mm.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for i.mx8m nano
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['caam']
|
['c']
| 1
| 4
| 4
|
--- diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c - * apparently on i.mx8mq it doesn't matter if virt_en == 1 + * apparently on i.mx8mq, 8mm, 8mn it doesn't matter if virt_en == 1 - of_machine_is_compatible("fsl,imx8mm")) { + of_machine_is_compatible("fsl,imx8mm") || + of_machine_is_compatible("fsl,imx8mn")) { - { .soc_id = "i.mx8mq", .data = &caam_imx7_data }, - { .soc_id = "i.mx8mm", .data = &caam_imx7_data }, + { .soc_id = "i.mx8m*", .data = &caam_imx7_data },
|
Cryptography hardware acceleration
|
2a2fbf20ad80f66cfd8e5018a7c4bfc4238c3228
|
horia geant
|
drivers
|
crypto
|
caam
|
crypto: caam - add support for i.mx8m plus
|
add support for the crypto engine used in i.mx8mp (i.mx 8m "plus"), which is very similar to the one used in i.mx8mq, i.mx8mm, i.mx8mn.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for i.mx8m plus
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['caam']
|
['c']
| 1
| 3
| 2
|
--- diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c - * apparently on i.mx8mq, 8mm, 8mn it doesn't matter if virt_en == 1 + * apparently on i.mx8m{q,m,n,p} it doesn't matter if virt_en == 1 - of_machine_is_compatible("fsl,imx8mn")) { + of_machine_is_compatible("fsl,imx8mn") || + of_machine_is_compatible("fsl,imx8mp")) {
|
Cryptography hardware acceleration
|
7e2b89fb4a2e636ad94fe47b76257c3cc0234666
|
horia geant
|
drivers
|
crypto
|
caam
|
crypto: ccp - add tee support for raven ridge
|
adds a pci device entry for raven ridge. raven ridge is an apu with a dedicated amd secure processor having trusted execution environment (tee) support. the tee provides a secure environment for running trusted applications (tas) which implement security-sensitive parts of a feature.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add tee support for raven ridge
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['ccp']
|
['c', 'makefile', 'h']
| 7
| 431
| 4
|
--- diff --git a/drivers/crypto/ccp/makefile b/drivers/crypto/ccp/makefile --- a/drivers/crypto/ccp/makefile +++ b/drivers/crypto/ccp/makefile - sev-dev.o + sev-dev.o \ + tee-dev.o diff --git a/drivers/crypto/ccp/psp-dev.c b/drivers/crypto/ccp/psp-dev.c --- a/drivers/crypto/ccp/psp-dev.c +++ b/drivers/crypto/ccp/psp-dev.c +#include "tee-dev.h" + + if (psp->tee_irq_handler) + psp->tee_irq_handler(irq, psp->tee_irq_data, status); +static int psp_init(struct psp_device *psp, unsigned int capability) +{ + int ret; + + if (!psp_check_sev_support(psp, capability)) { + ret = sev_dev_init(psp); + if (ret) + return ret; + } + + if (!psp_check_tee_support(psp, capability)) { + ret = tee_dev_init(psp); + if (ret) + return ret; + } + + return 0; +} + - ret = sev_dev_init(psp); + ret = psp_init(psp, capability); + tee_dev_destroy(psp); + +void psp_set_tee_irq_handler(struct psp_device *psp, psp_irq_handler_t handler, + void *data) +{ + psp->tee_irq_data = data; + psp->tee_irq_handler = handler; +} + +void psp_clear_tee_irq_handler(struct psp_device *psp) +{ + psp_set_tee_irq_handler(psp, null, null); +} + diff --git a/drivers/crypto/ccp/psp-dev.h b/drivers/crypto/ccp/psp-dev.h --- a/drivers/crypto/ccp/psp-dev.h +++ b/drivers/crypto/ccp/psp-dev.h + psp_irq_handler_t tee_irq_handler; + void *tee_irq_data; + + void *tee_data; +void psp_set_tee_irq_handler(struct psp_device *psp, psp_irq_handler_t handler, + void *data); +void psp_clear_tee_irq_handler(struct psp_device *psp); + diff --git a/drivers/crypto/ccp/sp-dev.h b/drivers/crypto/ccp/sp-dev.h --- a/drivers/crypto/ccp/sp-dev.h +++ b/drivers/crypto/ccp/sp-dev.h - * copyright (c) 2017-2018 advanced micro devices, inc. + * copyright (c) 2017-2019 advanced micro devices, inc. +struct tee_vdata { + const unsigned int cmdresp_reg; + const unsigned int cmdbuff_addr_lo_reg; + const unsigned int cmdbuff_addr_hi_reg; + const unsigned int ring_wptr_reg; + const unsigned int ring_rptr_reg; +}; + + const struct tee_vdata *tee; diff --git a/drivers/crypto/ccp/sp-pci.c b/drivers/crypto/ccp/sp-pci.c --- a/drivers/crypto/ccp/sp-pci.c +++ b/drivers/crypto/ccp/sp-pci.c - * copyright (c) 2013,2018 advanced micro devices, inc. + * copyright (c) 2013,2019 advanced micro devices, inc. +static const struct tee_vdata teev1 = { + .cmdresp_reg = 0x10544, + .cmdbuff_addr_lo_reg = 0x10548, + .cmdbuff_addr_hi_reg = 0x1054c, + .ring_wptr_reg = 0x10550, + .ring_rptr_reg = 0x10554, +}; + + +static const struct psp_vdata pspv3 = { + .tee = &teev1, + .feature_reg = 0x109fc, + .inten_reg = 0x10690, + .intsts_reg = 0x10694, +}; +#endif + }, + { /* 4 */ + .bar = 2, +#ifdef config_crypto_dev_sp_ccp + .ccp_vdata = &ccpv5a, +#endif +#ifdef config_crypto_dev_sp_psp + .psp_vdata = &pspv3, + { pci_vdevice(amd, 0x15df), (kernel_ulong_t)&dev_vdata[4] }, diff --git a/drivers/crypto/ccp/tee-dev.c b/drivers/crypto/ccp/tee-dev.c --- /dev/null +++ b/drivers/crypto/ccp/tee-dev.c +// spdx-license-identifier: mit +/* + * amd trusted execution environment (tee) interface + * + * author: rijo thomas <rijo-john.thomas@amd.com> + * author: devaraj rangasamy <devaraj.rangasamy@amd.com> + * + * copyright 2019 advanced micro devices, inc. + */ + +#include <linux/types.h> +#include <linux/mutex.h> +#include <linux/delay.h> +#include <linux/slab.h> +#include <linux/gfp.h> +#include <linux/psp-sev.h> + +#include "psp-dev.h" +#include "tee-dev.h" + +static bool psp_dead; + +static int tee_alloc_ring(struct psp_tee_device *tee, int ring_size) +{ + struct ring_buf_manager *rb_mgr = &tee->rb_mgr; + void *start_addr; + + if (!ring_size) + return -einval; + + /* we need actual physical address instead of dma address, since + * trusted os running on amd secure processor will map this region + */ + start_addr = (void *)__get_free_pages(gfp_kernel, get_order(ring_size)); + if (!start_addr) + return -enomem; + + rb_mgr->ring_start = start_addr; + rb_mgr->ring_size = ring_size; + rb_mgr->ring_pa = __psp_pa(start_addr); + + return 0; +} + +static void tee_free_ring(struct psp_tee_device *tee) +{ + struct ring_buf_manager *rb_mgr = &tee->rb_mgr; + + if (!rb_mgr->ring_start) + return; + + free_pages((unsigned long)rb_mgr->ring_start, + get_order(rb_mgr->ring_size)); + + rb_mgr->ring_start = null; + rb_mgr->ring_size = 0; + rb_mgr->ring_pa = 0; +} + +static int tee_wait_cmd_poll(struct psp_tee_device *tee, unsigned int timeout, + unsigned int *reg) +{ + /* ~10ms sleep per loop => nloop = timeout * 100 */ + int nloop = timeout * 100; + + while (--nloop) { + *reg = ioread32(tee->io_regs + tee->vdata->cmdresp_reg); + if (*reg & psp_cmdresp_resp) + return 0; + + usleep_range(10000, 10100); + } + + dev_err(tee->dev, "tee: command timed out, disabling psp "); + psp_dead = true; + + return -etimedout; +} + +static +struct tee_init_ring_cmd *tee_alloc_cmd_buffer(struct psp_tee_device *tee) +{ + struct tee_init_ring_cmd *cmd; + + cmd = kzalloc(sizeof(*cmd), gfp_kernel); + if (!cmd) + return null; + + cmd->hi_addr = upper_32_bits(tee->rb_mgr.ring_pa); + cmd->low_addr = lower_32_bits(tee->rb_mgr.ring_pa); + cmd->size = tee->rb_mgr.ring_size; + + dev_dbg(tee->dev, "tee: ring address: high = 0x%x low = 0x%x size = %u ", + cmd->hi_addr, cmd->low_addr, cmd->size); + + return cmd; +} + +static inline void tee_free_cmd_buffer(struct tee_init_ring_cmd *cmd) +{ + kfree(cmd); +} + +static int tee_init_ring(struct psp_tee_device *tee) +{ + int ring_size = max_ring_buffer_entries * sizeof(struct tee_ring_cmd); + struct tee_init_ring_cmd *cmd; + phys_addr_t cmd_buffer; + unsigned int reg; + int ret; + + build_bug_on(sizeof(struct tee_ring_cmd) != 1024); + + ret = tee_alloc_ring(tee, ring_size); + if (ret) { + dev_err(tee->dev, "tee: ring allocation failed %d ", ret); + return ret; + } + + tee->rb_mgr.wptr = 0; + + cmd = tee_alloc_cmd_buffer(tee); + if (!cmd) { + tee_free_ring(tee); + return -enomem; + } + + cmd_buffer = __psp_pa((void *)cmd); + + /* send command buffer details to trusted os by writing to + * cpu-psp message registers + */ + + iowrite32(lower_32_bits(cmd_buffer), + tee->io_regs + tee->vdata->cmdbuff_addr_lo_reg); + iowrite32(upper_32_bits(cmd_buffer), + tee->io_regs + tee->vdata->cmdbuff_addr_hi_reg); + iowrite32(tee_ring_init_cmd, + tee->io_regs + tee->vdata->cmdresp_reg); + + ret = tee_wait_cmd_poll(tee, tee_default_timeout, ®); + if (ret) { + dev_err(tee->dev, "tee: ring init command timed out "); + tee_free_ring(tee); + goto free_buf; + } + + if (reg & psp_cmdresp_err_mask) { + dev_err(tee->dev, "tee: ring init command failed (%#010x) ", + reg & psp_cmdresp_err_mask); + tee_free_ring(tee); + ret = -eio; + } + +free_buf: + tee_free_cmd_buffer(cmd); + + return ret; +} + +static void tee_destroy_ring(struct psp_tee_device *tee) +{ + unsigned int reg; + int ret; + + if (!tee->rb_mgr.ring_start) + return; + + if (psp_dead) + goto free_ring; + + iowrite32(tee_ring_destroy_cmd, + tee->io_regs + tee->vdata->cmdresp_reg); + + ret = tee_wait_cmd_poll(tee, tee_default_timeout, ®); + if (ret) { + dev_err(tee->dev, "tee: ring destroy command timed out "); + } else if (reg & psp_cmdresp_err_mask) { + dev_err(tee->dev, "tee: ring destroy command failed (%#010x) ", + reg & psp_cmdresp_err_mask); + } + +free_ring: + tee_free_ring(tee); +} + +int tee_dev_init(struct psp_device *psp) +{ + struct device *dev = psp->dev; + struct psp_tee_device *tee; + int ret; + + ret = -enomem; + tee = devm_kzalloc(dev, sizeof(*tee), gfp_kernel); + if (!tee) + goto e_err; + + psp->tee_data = tee; + + tee->dev = dev; + tee->psp = psp; + + tee->io_regs = psp->io_regs; + + tee->vdata = (struct tee_vdata *)psp->vdata->tee; + if (!tee->vdata) { + ret = -enodev; + dev_err(dev, "tee: missing driver data "); + goto e_err; + } + + ret = tee_init_ring(tee); + if (ret) { + dev_err(dev, "tee: failed to init ring buffer "); + goto e_err; + } + + dev_notice(dev, "tee enabled "); + + return 0; + +e_err: + psp->tee_data = null; + + dev_notice(dev, "tee initialization failed "); + + return ret; +} + +void tee_dev_destroy(struct psp_device *psp) +{ + struct psp_tee_device *tee = psp->tee_data; + + if (!tee) + return; + + tee_destroy_ring(tee); +} diff --git a/drivers/crypto/ccp/tee-dev.h b/drivers/crypto/ccp/tee-dev.h --- /dev/null +++ b/drivers/crypto/ccp/tee-dev.h +/* spdx-license-identifier: mit */ +/* + * copyright 2019 advanced micro devices, inc. + * + * author: rijo thomas <rijo-john.thomas@amd.com> + * author: devaraj rangasamy <devaraj.rangasamy@amd.com> + * + */ + +/* this file describes the tee communication interface between host and amd + * secure processor + */ + +#ifndef __tee_dev_h__ +#define __tee_dev_h__ + +#include <linux/device.h> +#include <linux/mutex.h> + +#define tee_default_timeout 10 +#define max_buffer_size 992 + +/** + * enum tee_ring_cmd_id - tee interface commands for ring buffer configuration + * @tee_ring_init_cmd: initialize ring buffer + * @tee_ring_destroy_cmd: destroy ring buffer + * @tee_ring_max_cmd: maximum command id + */ +enum tee_ring_cmd_id { + tee_ring_init_cmd = 0x00010000, + tee_ring_destroy_cmd = 0x00020000, + tee_ring_max_cmd = 0x000f0000, +}; + +/** + * struct tee_init_ring_cmd - command to init tee ring buffer + * @low_addr: bits [31:0] of the physical address of ring buffer + * @hi_addr: bits [63:32] of the physical address of ring buffer + * @size: size of ring buffer in bytes + */ +struct tee_init_ring_cmd { + u32 low_addr; + u32 hi_addr; + u32 size; +}; + +#define max_ring_buffer_entries 32 + +/** + * struct ring_buf_manager - helper structure to manage ring buffer. + * @ring_start: starting address of ring buffer + * @ring_size: size of ring buffer in bytes + * @ring_pa: physical address of ring buffer + * @wptr: index to the last written entry in ring buffer + */ +struct ring_buf_manager { + void *ring_start; + u32 ring_size; + phys_addr_t ring_pa; + u32 wptr; +}; + +struct psp_tee_device { + struct device *dev; + struct psp_device *psp; + void __iomem *io_regs; + struct tee_vdata *vdata; + struct ring_buf_manager rb_mgr; +}; + +/** + * enum tee_cmd_state - tee command states for the ring buffer interface + * @tee_cmd_state_init: initial state of command when sent from host + * @tee_cmd_state_process: command being processed by tee environment + * @tee_cmd_state_completed: command processing completed + */ +enum tee_cmd_state { + tee_cmd_state_init, + tee_cmd_state_process, + tee_cmd_state_completed, +}; + +/** + * struct tee_ring_cmd - structure of the command buffer in tee ring + * @cmd_id: refers to &enum tee_cmd_id. command id for the ring buffer + * interface + * @cmd_state: refers to &enum tee_cmd_state + * @status: status of tee command execution + * @res0: reserved region + * @pdata: private data (currently unused) + * @res1: reserved region + * @buf: tee command specific buffer + */ +struct tee_ring_cmd { + u32 cmd_id; + u32 cmd_state; + u32 status; + u32 res0[1]; + u64 pdata; + u32 res1[2]; + u8 buf[max_buffer_size]; + + /* total size: 1024 bytes */ +} __packed; + +int tee_dev_init(struct psp_device *psp); +void tee_dev_destroy(struct psp_device *psp); + +#endif /* __tee_dev_h__ */
|
Cryptography hardware acceleration
|
33960acccfbd7f24d443cb3d0312ac28abe62bae
|
rijo thomas
|
drivers
|
crypto
|
ccp
|
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