commit_title
stringlengths 13
124
| commit_body
stringlengths 0
1.9k
| release_summary
stringclasses 52
values | changes_summary
stringlengths 1
758
| release_affected_domains
stringclasses 33
values | release_affected_drivers
stringclasses 51
values | domain_of_changes
stringlengths 2
571
| language_set
stringclasses 983
values | diffstat_files
int64 1
300
| diffstat_insertions
int64 0
309k
| diffstat_deletions
int64 0
168k
| commit_diff
stringlengths 92
23.4M
| category
stringclasses 108
values | commit_hash
stringlengths 34
40
| related_people
stringlengths 0
370
| domain
stringclasses 21
values | subdomain
stringclasses 241
values | leaf_module
stringlengths 0
912
|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
spi: cadence-quadspi: disable the dac for intel lgm soc
|
on intel lightning mountain(lgm) socs qspi controller do not use direct access controller(dac).
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add qspi controller support for intel lgm soc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['cadence-quadspi']
|
['c']
| 1
| 11
| 4
|
--- diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c - /* enable direct access controller */ - reg = readl(cqspi->iobase + cqspi_reg_config); - reg |= cqspi_reg_config_enb_dir_acc_ctrl; - writel(reg, cqspi->iobase + cqspi_reg_config); + /* disable direct access controller */ + if (!cqspi->use_direct_mode) { + reg = readl(cqspi->iobase + cqspi_reg_config); + reg &= ~cqspi_reg_config_enb_dir_acc_ctrl; + writel(reg, cqspi->iobase + cqspi_reg_config); + } +static const struct cqspi_driver_platdata intel_lgm_qspi = { + .quirks = cqspi_disable_dac_mode, +}; + + .data = &intel_lgm_qspi,
|
Serial Peripheral Interface (SPI)
|
ad2775dc3fc5d30dd51984ccbaa736cc7ea9caca
|
ramuthevar vadivel murugan
|
drivers
|
spi
| |
spi: cadence-quadspi: add multi-chipselect support for intel lgm soc
|
add multiple chipselect support for intel lgm socs, currently qspi-nor and qspi-nand supported.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add qspi controller support for intel lgm soc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['cadence-quadspi']
|
['c']
| 1
| 6
| 0
|
--- diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c + u32 num_chipselect; + if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) + cqspi->num_chipselect = cqspi_max_chipselect; + + master->num_chipselect = cqspi->num_chipselect; +
|
Serial Peripheral Interface (SPI)
|
b436fb7d29bfa48ff5e00cbf413609c7a6d4d81e
|
ramuthevar vadivel murugan
|
drivers
|
spi
| |
spi: move cadence-quadspi.txt to documentation/devicetree/bindings/spi
|
move the documentation/devicetree/bindings/mtd/cadence-quadspi.txt to documentation/devicetree/bindings/spi/
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add qspi controller support for intel lgm soc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['cadence-quadspi']
|
['txt']
| 1
| 0
| 0
|
--- diff --git a/documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/documentation/devicetree/bindings/spi/cadence-quadspi.txt
|
Serial Peripheral Interface (SPI)
|
eb4aadc31ef4224b926d5165048cb297f4bda34f
|
ramuthevar vadivel murugan rob herring robh kernel org
|
documentation
|
devicetree
|
bindings, spi
|
dt-bindings: spi: cadence-qspi: add support for intel lgm-qspi
|
add new vendor specific compatible string to check intel's lightning mountain(lgm) qspi features enablement in cadence-quadspi driver.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add qspi controller support for intel lgm soc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['cadence-quadspi']
|
['txt']
| 1
| 1
| 0
|
--- diff --git a/documentation/devicetree/bindings/spi/cadence-quadspi.txt b/documentation/devicetree/bindings/spi/cadence-quadspi.txt --- a/documentation/devicetree/bindings/spi/cadence-quadspi.txt +++ b/documentation/devicetree/bindings/spi/cadence-quadspi.txt + for intel lgm soc - "intel,lgm-qspi", "cdns,qspi-nor". - reg : contains two entries, each of which is a tuple consisting of a
|
Serial Peripheral Interface (SPI)
|
fcebca39938fa9f6ed03f27fc75645ad7fd489e9
|
ramuthevar vadivel murugan rob herring robh kernel org
|
documentation
|
devicetree
|
bindings, spi
|
spi: add spi_no_tx/rx support
|
transmit/receive only is a valid spi mode. for example, the mosi/tx line might be missing from an adc while for a dac the miso/rx line may be optional. this patch adds these two new modes: spi_no_tx and spi_no_rx. this way, the drivers will be able to identify if any of these two lines is missing and to adjust the transfers accordingly.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add spi_no_tx/rx support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['h', 'c']
| 3
| 47
| 5
|
--- diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c + case 0: + spi->mode |= spi_no_tx; + break; + case 0: + spi->mode |= spi_no_rx; + break; - /* check mode to prevent that dual and quad set at the same time + /* + * check mode to prevent that any two of dual, quad and no_mosi/miso + * are set at the same time - if (((spi->mode & spi_tx_dual) && (spi->mode & spi_tx_quad)) || - ((spi->mode & spi_rx_dual) && (spi->mode & spi_rx_quad))) { + if ((hweight_long(spi->mode & + (spi_tx_dual | spi_tx_quad | spi_no_tx)) > 1) || + (hweight_long(spi->mode & + (spi_rx_dual | spi_rx_quad | spi_no_rx)) > 1)) { - "setup: can not select dual and quad at the same time "); + "setup: can not select any two of dual, quad and no-rx/tx at the same time "); - bad_bits = spi->mode & ~(spi->controller->mode_bits | spi_cs_word); + bad_bits = spi->mode & ~(spi->controller->mode_bits | spi_cs_word | + spi_no_tx | spi_no_rx); + if (spi->mode & spi_no_tx) + return -einval; + if (spi->mode & spi_no_rx) + return -einval; diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h +#include <linux/bits.h> +#define spi_no_tx bit(31) /* no transmit wire */ +#define spi_no_rx bit(30) /* no receive wire */ + /* + * all bits defined above should be covered by spi_mode_kernel_mask. + * the spi_mode_kernel_mask has the spi_mode_user_mask counterpart, + * which is defined in 'include/uapi/linux/spi/spi.h'. + * the bits defined here are from bit 31 downwards, while in + * spi_mode_user_mask are from 0 upwards. + * these bits must not overlap. a static assert check should make sure of that. + * if adding extra bits, make sure to decrease the bit index below as well. + */ +#define spi_mode_kernel_mask (~(bit(30) - 1)) +/* make sure that spi_mode_kernel_mask & spi_mode_user_mask don't overlap */ +static_assert((spi_mode_kernel_mask & spi_mode_user_mask) == 0, + "spi_mode_user_mask & spi_mode_kernel_mask must not overlap"); + diff --git a/include/uapi/linux/spi/spi.h b/include/uapi/linux/spi/spi.h --- a/include/uapi/linux/spi/spi.h +++ b/include/uapi/linux/spi/spi.h +/* + * all the bits defined above should be covered by spi_mode_user_mask. + * the spi_mode_user_mask has the spi_mode_kernel_mask counterpart in + * 'include/linux/spi/spi.h'. the bits defined here are from bit 0 upwards + * while in spi_mode_kernel_mask they are from the other end downwards. + * these bits must not overlap. a static assert check should make sure of that. + * if adding extra bits, make sure to increase the bit index below as well. + */ +#define spi_mode_user_mask (_bitul(16) - 1) +
|
Serial Peripheral Interface (SPI)
|
d962608ce2188a1d46ec9d356d6fad5cd6fc0341
|
dragos bogdan
|
drivers
|
spi
|
linux, spi
|
spi: cadence-quadspi: add dtr support
|
double transfer rate (dtr) mode transfers data twice per clock cycle. add support for parsing dtr ops and set up the registers to allow it.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add dtr support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['cadence-quadspi']
|
['c']
| 1
| 242
| 39
|
--- diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c + bool dtr; +#define cqspi_reg_config_dtr_proto bit(24) +#define cqspi_reg_config_dual_opcode bit(30) +#define cqspi_reg_wr_completion_ctrl 0x38 +#define cqspi_reg_wr_disable_auto_poll bit(14) + +#define cqspi_reg_polling_status 0xb0 +#define cqspi_reg_polling_status_dummy_lsb 16 + +#define cqspi_reg_op_ext_lower 0xe0 +#define cqspi_reg_op_ext_read_lsb 24 +#define cqspi_reg_op_ext_write_lsb 16 +#define cqspi_reg_op_ext_stig_lsb 0 + -static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op) +static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr) + if (dtr) + dummy_clk /= 2; +static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata, + const struct spi_mem_op *op) +{ + f_pdata->inst_width = cqspi_inst_type_single; + f_pdata->addr_width = cqspi_inst_type_single; + f_pdata->data_width = cqspi_inst_type_single; + f_pdata->dtr = op->data.dtr && op->cmd.dtr && op->addr.dtr; + + switch (op->data.buswidth) { + case 0: + break; + case 1: + f_pdata->data_width = cqspi_inst_type_single; + break; + case 2: + f_pdata->data_width = cqspi_inst_type_dual; + break; + case 4: + f_pdata->data_width = cqspi_inst_type_quad; + break; + case 8: + f_pdata->data_width = cqspi_inst_type_octal; + break; + default: + return -einval; + } + + /* right now we only support 8-8-8 dtr mode. */ + if (f_pdata->dtr) { + switch (op->cmd.buswidth) { + case 0: + break; + case 8: + f_pdata->inst_width = cqspi_inst_type_octal; + break; + default: + return -einval; + } + + switch (op->addr.buswidth) { + case 0: + break; + case 8: + f_pdata->addr_width = cqspi_inst_type_octal; + break; + default: + return -einval; + } + + switch (op->data.buswidth) { + case 0: + break; + case 8: + f_pdata->data_width = cqspi_inst_type_octal; + break; + default: + return -einval; + } + } + + return 0; +} + +static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata, + const struct spi_mem_op *op, + unsigned int shift) +{ + struct cqspi_st *cqspi = f_pdata->cqspi; + void __iomem *reg_base = cqspi->iobase; + unsigned int reg; + u8 ext; + + if (op->cmd.nbytes != 2) + return -einval; + + /* opcode extension is the lsb. */ + ext = op->cmd.opcode & 0xff; + + reg = readl(reg_base + cqspi_reg_op_ext_lower); + reg &= ~(0xff << shift); + reg |= ext << shift; + writel(reg, reg_base + cqspi_reg_op_ext_lower); + + return 0; +} + +static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata, + const struct spi_mem_op *op, unsigned int shift, + bool enable) +{ + struct cqspi_st *cqspi = f_pdata->cqspi; + void __iomem *reg_base = cqspi->iobase; + unsigned int reg; + int ret; + + reg = readl(reg_base + cqspi_reg_config); + + /* + * we enable dual byte opcode here. the callers have to set up the + * extension opcode based on which type of operation it is. + */ + if (enable) { + reg |= cqspi_reg_config_dtr_proto; + reg |= cqspi_reg_config_dual_opcode; + + /* set up command opcode extension. */ + ret = cqspi_setup_opcode_ext(f_pdata, op, shift); + if (ret) + return ret; + } else { + reg &= ~cqspi_reg_config_dtr_proto; + reg &= ~cqspi_reg_config_dual_opcode; + } + + writel(reg, reg_base + cqspi_reg_config); + + return cqspi_wait_idle(cqspi); +} + - u8 opcode = op->cmd.opcode; + u8 opcode; + status = cqspi_set_protocol(f_pdata, op); + if (status) + return status; + + status = cqspi_enable_dtr(f_pdata, op, cqspi_reg_op_ext_stig_lsb, + f_pdata->dtr); + if (status) + return status; + + if (f_pdata->dtr) + opcode = op->cmd.opcode >> 8; + else + opcode = op->cmd.opcode; + - dummy_clk = cqspi_calc_dummy(op); + dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr); - const u8 opcode = op->cmd.opcode; + u8 opcode; + int ret; + + ret = cqspi_set_protocol(f_pdata, op); + if (ret) + return ret; + + ret = cqspi_enable_dtr(f_pdata, op, cqspi_reg_op_ext_stig_lsb, + f_pdata->dtr); + if (ret) + return ret; + reg = cqspi_calc_rdreg(f_pdata); + writel(reg, reg_base + cqspi_reg_rd_instr); + + if (f_pdata->dtr) + opcode = op->cmd.opcode >> 8; + else + opcode = op->cmd.opcode; + + int ret; + u8 opcode; - reg = op->cmd.opcode << cqspi_reg_rd_instr_opcode_lsb; + ret = cqspi_enable_dtr(f_pdata, op, cqspi_reg_op_ext_read_lsb, + f_pdata->dtr); + if (ret) + return ret; + + if (f_pdata->dtr) + opcode = op->cmd.opcode >> 8; + else + opcode = op->cmd.opcode; + + reg = opcode << cqspi_reg_rd_instr_opcode_lsb; - dummy_clk = cqspi_calc_dummy(op); + dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr); + int ret; + u8 opcode; + + ret = cqspi_enable_dtr(f_pdata, op, cqspi_reg_op_ext_write_lsb, + f_pdata->dtr); + if (ret) + return ret; + + if (f_pdata->dtr) + opcode = op->cmd.opcode >> 8; + else + opcode = op->cmd.opcode; - reg = op->cmd.opcode << cqspi_reg_wr_instr_opcode_lsb; + reg = opcode << cqspi_reg_wr_instr_opcode_lsb; + reg |= f_pdata->data_width << cqspi_reg_wr_instr_type_data_lsb; + reg |= f_pdata->addr_width << cqspi_reg_wr_instr_type_addr_lsb; + if (f_pdata->dtr) { + /* + * some flashes like the cypress semper flash expect a 4-byte + * dummy address with the read sr command in dtr mode, but this + * controller does not support sending address with the read sr + * command. so, disable write completion polling on the + * controller's side. spi-nor will take care of polling the + * status register. + */ + reg = readl(reg_base + cqspi_reg_wr_completion_ctrl); + reg |= cqspi_reg_wr_disable_auto_poll; + writel(reg, reg_base + cqspi_reg_wr_completion_ctrl); + } + -static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata, - const struct spi_mem_op *op) -{ - f_pdata->inst_width = cqspi_inst_type_single; - f_pdata->addr_width = cqspi_inst_type_single; - f_pdata->data_width = cqspi_inst_type_single; - - if (op->data.dir == spi_mem_data_in) { - switch (op->data.buswidth) { - case 1: - f_pdata->data_width = cqspi_inst_type_single; - break; - case 2: - f_pdata->data_width = cqspi_inst_type_dual; - break; - case 4: - f_pdata->data_width = cqspi_inst_type_quad; - break; - case 8: - f_pdata->data_width = cqspi_inst_type_octal; - break; - default: - return -einval; - } - } - - return 0; -} - - if (cqspi->use_direct_mode && ((to + len) <= cqspi->ahb_size)) { + /* + * some flashes like the cypress semper flash expect a dummy 4-byte + * address (all 0s) with the read status register command in dtr mode. + * but this controller does not support sending dummy address bytes to + * the flash when it is polling the write completion register in dtr + * mode. so, we can not use direct mode when in dtr mode for writing + * data. + */ + if (!f_pdata->dtr && cqspi->use_direct_mode && + ((to + len) <= cqspi->ahb_size)) { + bool all_true, all_false; + + all_true = op->cmd.dtr && op->addr.dtr && op->dummy.dtr && + op->data.dtr; + all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && + !op->data.dtr; + + /* mixed dtr modes not supported. */ + if (!(all_true || all_false)) + return false; + + /* dtr mode opcodes should be 2 bytes. */ + if (all_true && op->cmd.nbytes != 2) + return false; + - cqspi->wr_delay = 5 * div_round_up(nsec_per_sec, + cqspi->wr_delay = 50 * div_round_up(nsec_per_sec, - master->mode_bits |= spi_rx_octal; + master->mode_bits |= spi_rx_octal | spi_tx_octal; +module_author("pratyush yadav <p.yadav@ti.com>");
|
Serial Peripheral Interface (SPI)
|
f453f293979fb648d2e505c132887811acb6bde6
|
pratyush yadav
|
drivers
|
spi
| |
spi: orion: enable support for switching cs every transferred byte
|
some spi devices, require toggling the cs every transferred byte. enable such possibility in the spi-orion driver.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable support for switching cs every transferred byte
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['orion']
|
['c']
| 1
| 28
| 4
|
--- diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c --- a/drivers/spi/spi-orion.c +++ b/drivers/spi/spi-orion.c + bool cs_single_byte; + + cs_single_byte = spi->mode & spi_cs_word; + + if (cs_single_byte) + orion_spi_set_cs(spi, 0); + + if (cs_single_byte) { + orion_spi_set_cs(spi, 1); + /* satisfy some slic devices requirements */ + udelay(4); + } + if (cs_single_byte) { + orion_spi_set_cs(spi, 1); + /* satisfy some slic devices requirements */ + udelay(4); + } + + if (spi->mode & spi_cs_word) { + dev_err(&spi->dev, "spi_cs_word is only supported for 8 bit words "); + return -1; + } + - * use spi direct write mode if base address is available. otherwise - * fall back to pio mode for this transfer. + * use spi direct write mode if base address is available + * and spi_cs_word flag is not set. + * otherwise fall back to pio mode for this transfer. - if (vaddr && xfer->tx_buf && word_len == 8) { + if (vaddr && xfer->tx_buf && word_len == 8 && (spi->mode & spi_cs_word) == 0) { - master->mode_bits = spi_cpha | spi_cpol | spi_lsb_first; + master->mode_bits = spi_cpha | spi_cpol | spi_lsb_first | spi_cs_word;
|
Serial Peripheral Interface (SPI)
|
22a6d41c871225bdd269a80fe04236071f429e2b
|
marcin wojtas
|
drivers
|
spi
| |
spi: pxa2xx: add ids for the controllers found on intel lynxpoint
|
add ids for the controllers found on intel lynxpoint. in particular it's macbook air 6,2 devices.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add ids for the controllers found on intel lynxpoint
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['pxa2xx']
|
['c']
| 1
| 2
| 0
|
--- diff --git a/drivers/spi/spi-pxa2xx-pci.c b/drivers/spi/spi-pxa2xx-pci.c --- a/drivers/spi/spi-pxa2xx-pci.c +++ b/drivers/spi/spi-pxa2xx-pci.c + { pci_vdevice(intel, 0x9c65), port_lpt0 }, + { pci_vdevice(intel, 0x9c66), port_lpt1 },
|
Serial Peripheral Interface (SPI)
|
2395183738a01048584c4b49c502c44b18971597
|
andy shevchenko
|
drivers
|
spi
| |
spi: pxa2xx: add support for intel alder lake pch-p
|
add support for lpss spi on intel alder lake pch-p variant.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for intel alder lake pch-p
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['pxa2xx']
|
['c']
| 1
| 4
| 0
|
--- diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c + /* adl-p */ + { pci_vdevice(intel, 0x51aa), lpss_cnl_ssp }, + { pci_vdevice(intel, 0x51ab), lpss_cnl_ssp }, + { pci_vdevice(intel, 0x51fb), lpss_cnl_ssp },
|
Serial Peripheral Interface (SPI)
|
a402e397b938fbf7e7977bded44f3db9a659a931
|
jarkko nikula
|
drivers
|
spi
| |
spi: realtek-rtl: add support for realtek rtl838x/rtl839x spi controllers
|
this driver likely also supports earlier (rtl8196) and later (rtl93xx) socs.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for realtek rtl838x/rtl839x spi controllers
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['realtek-rtl']
|
['c', 'makefile']
| 2
| 210
| 0
|
--- diff --git a/drivers/spi/makefile b/drivers/spi/makefile --- a/drivers/spi/makefile +++ b/drivers/spi/makefile +obj-$(config_mach_realtek_rtl) += spi-realtek-rtl.o diff --git a/drivers/spi/spi-realtek-rtl.c b/drivers/spi/spi-realtek-rtl.c --- /dev/null +++ b/drivers/spi/spi-realtek-rtl.c +// spdx-license-identifier: gpl-2.0-only + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/mod_devicetable.h> +#include <linux/spi/spi.h> + +struct rtspi { + void __iomem *base; +}; + +/* spi flash configuration register */ +#define rtl_spi_sfcr 0x00 +#define rtl_spi_sfcr_rbo bit(28) +#define rtl_spi_sfcr_wbo bit(27) + +/* spi flash control and status register */ +#define rtl_spi_sfcsr 0x08 +#define rtl_spi_sfcsr_csb0 bit(31) +#define rtl_spi_sfcsr_csb1 bit(30) +#define rtl_spi_sfcsr_rdy bit(27) +#define rtl_spi_sfcsr_cs bit(24) +#define rtl_spi_sfcsr_len_mask ~(0x03 << 28) +#define rtl_spi_sfcsr_len1 (0x00 << 28) +#define rtl_spi_sfcsr_len4 (0x03 << 28) + +/* spi flash data register */ +#define rtl_spi_sfdr 0x0c + +#define reg(x) (rtspi->base + x) + + +static void rt_set_cs(struct spi_device *spi, bool active) +{ + struct rtspi *rtspi = spi_controller_get_devdata(spi->controller); + u32 value; + + /* cs0 bit is active low */ + value = readl(reg(rtl_spi_sfcsr)); + if (active) + value |= rtl_spi_sfcsr_csb0; + else + value &= ~rtl_spi_sfcsr_csb0; + writel(value, reg(rtl_spi_sfcsr)); +} + +static void set_size(struct rtspi *rtspi, int size) +{ + u32 value; + + value = readl(reg(rtl_spi_sfcsr)); + value &= rtl_spi_sfcsr_len_mask; + if (size == 4) + value |= rtl_spi_sfcsr_len4; + else if (size == 1) + value |= rtl_spi_sfcsr_len1; + writel(value, reg(rtl_spi_sfcsr)); +} + +static inline void wait_ready(struct rtspi *rtspi) +{ + while (!(readl(reg(rtl_spi_sfcsr)) & rtl_spi_sfcsr_rdy)) + cpu_relax(); +} +static void send4(struct rtspi *rtspi, const u32 *buf) +{ + wait_ready(rtspi); + set_size(rtspi, 4); + writel(*buf, reg(rtl_spi_sfdr)); +} + +static void send1(struct rtspi *rtspi, const u8 *buf) +{ + wait_ready(rtspi); + set_size(rtspi, 1); + writel(buf[0] << 24, reg(rtl_spi_sfdr)); +} + +static void rcv4(struct rtspi *rtspi, u32 *buf) +{ + wait_ready(rtspi); + set_size(rtspi, 4); + *buf = readl(reg(rtl_spi_sfdr)); +} + +static void rcv1(struct rtspi *rtspi, u8 *buf) +{ + wait_ready(rtspi); + set_size(rtspi, 1); + *buf = readl(reg(rtl_spi_sfdr)) >> 24; +} + +static int transfer_one(struct spi_controller *ctrl, struct spi_device *spi, + struct spi_transfer *xfer) +{ + struct rtspi *rtspi = spi_controller_get_devdata(ctrl); + void *rx_buf; + const void *tx_buf; + int cnt; + + tx_buf = xfer->tx_buf; + rx_buf = xfer->rx_buf; + cnt = xfer->len; + if (tx_buf) { + while (cnt >= 4) { + send4(rtspi, tx_buf); + tx_buf += 4; + cnt -= 4; + } + while (cnt) { + send1(rtspi, tx_buf); + tx_buf++; + cnt--; + } + } else if (rx_buf) { + while (cnt >= 4) { + rcv4(rtspi, rx_buf); + rx_buf += 4; + cnt -= 4; + } + while (cnt) { + rcv1(rtspi, rx_buf); + rx_buf++; + cnt--; + } + } + + spi_finalize_current_transfer(ctrl); + + return 0; +} + +static void init_hw(struct rtspi *rtspi) +{ + u32 value; + + /* turn on big-endian byte ordering */ + value = readl(reg(rtl_spi_sfcr)); + value |= rtl_spi_sfcr_rbo | rtl_spi_sfcr_wbo; + writel(value, reg(rtl_spi_sfcr)); + + value = readl(reg(rtl_spi_sfcsr)); + /* permanently disable cs1, since it's never used */ + value |= rtl_spi_sfcsr_csb1; + /* select cs0 for use */ + value &= rtl_spi_sfcsr_cs; + writel(value, reg(rtl_spi_sfcsr)); +} + +static int realtek_rtl_spi_probe(struct platform_device *pdev) +{ + struct spi_controller *ctrl; + struct rtspi *rtspi; + int err; + + ctrl = devm_spi_alloc_master(&pdev->dev, sizeof(*rtspi)); + if (!ctrl) { + dev_err(&pdev->dev, "error allocating spi controller "); + return -enomem; + } + platform_set_drvdata(pdev, ctrl); + rtspi = spi_controller_get_devdata(ctrl); + + rtspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, null); + if (is_err(rtspi->base)) { + dev_err(&pdev->dev, "could not map spi register address"); + return -enomem; + } + + init_hw(rtspi); + + ctrl->dev.of_node = pdev->dev.of_node; + ctrl->flags = spi_controller_half_duplex; + ctrl->set_cs = rt_set_cs; + ctrl->transfer_one = transfer_one; + + err = devm_spi_register_controller(&pdev->dev, ctrl); + if (err) { + dev_err(&pdev->dev, "could not register spi controller "); + return -enodev; + } + + return 0; +} + + +static const struct of_device_id realtek_rtl_spi_of_ids[] = { + { .compatible = "realtek,rtl8380-spi" }, + { .compatible = "realtek,rtl8382-spi" }, + { .compatible = "realtek,rtl8391-spi" }, + { .compatible = "realtek,rtl8392-spi" }, + { .compatible = "realtek,rtl8393-spi" }, + { /* sentinel */ } +}; +module_device_table(of, realtek_rtl_spi_of_ids); + +static struct platform_driver realtek_rtl_spi_driver = { + .probe = realtek_rtl_spi_probe, + .driver = { + .name = "realtek-rtl-spi", + .of_match_table = realtek_rtl_spi_of_ids, + }, +}; + +module_platform_driver(realtek_rtl_spi_driver); + +module_license("gpl v2"); +module_author("bert vermeulen <bert@biot.com>"); +module_description("realtek rtl spi driver");
|
Serial Peripheral Interface (SPI)
|
a8af5cc2ff1e804694629a8ef320935629dd15ba
|
bert vermeulen
|
drivers
|
spi
| |
spi: support cs timing for hw & sw mode
|
this patch supports the controller's hw cs and sw cs via use cs_gpio.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support cs timing for hw & sw mode
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['c']
| 1
| 6
| 3
|
--- diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c - if (!spi->controller->set_cs_timing) { + if (spi->cs_gpiod || gpio_is_valid(spi->cs_gpio) || + !spi->controller->set_cs_timing) { - if (!spi->controller->set_cs_timing) { + if (spi->cs_gpiod || gpio_is_valid(spi->cs_gpio) || + !spi->controller->set_cs_timing) { - if (spi->controller->set_cs_timing) { + if (spi->controller->set_cs_timing && + !(spi->cs_gpiod || gpio_is_valid(spi->cs_gpio))) {
|
Serial Peripheral Interface (SPI)
|
0486d9f91d373e7f47276f30898ee0cb12656a70
|
leilk liu
|
drivers
|
spi
| |
dt-bindings: clock: tegra: add clock id tegra210_clk_qspi_pm
|
tegra210 qspi clock output has divider div2_sel which will be enabled when using ddr interface mode.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add tegra quad spi driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['h']
| 1
| 1
| 1
|
--- diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h -/* 278 */ +#define tegra210_clk_qspi_pm 278
|
Serial Peripheral Interface (SPI)
|
88893986338beebcf5317bda80d43d4f6f7f7c7c
|
sowjanya komatineni
|
include
|
dt-bindings
|
clock
|
dt-bindings: spi: add tegra quad spi device tree binding
|
this patch adds yaml based device tree binding document for tegra quad spi driver.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add tegra quad spi driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['yaml']
| 1
| 117
| 0
|
--- diff --git a/documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml b/documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml --- /dev/null +++ b/documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml +# spdx-license-identifier: (gpl-2.0 or bsd-2-clause) +%yaml 1.2 +--- +$id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: tegra quad spi controller + +maintainers: + - thierry reding <thierry.reding@gmail.com> + - jonathan hunter <jonathanh@nvidia.com> + +allof: + - $ref: "spi-controller.yaml#" + +properties: + compatible: + enum: + - nvidia,tegra210-qspi + - nvidia,tegra186-qspi + - nvidia,tegra194-qspi + + reg: + maxitems: 1 + + interrupts: + maxitems: 1 + + clock-names: + items: + - const: qspi + - const: qspi_out + + clocks: + maxitems: 2 + + resets: + maxitems: 1 + + dmas: + maxitems: 2 + + dma-names: + items: + - const: rx + - const: tx + +patternproperties: + "@[0-9a-f]+": + type: object + + properties: + spi-rx-bus-width: + enum: [1, 2, 4] + + spi-tx-bus-width: + enum: [1, 2, 4] + + nvidia,tx-clk-tap-delay: + description: + delays the clock going out to device with this tap value. + tap value varies based on platform design trace lengths from tegra + qspi to corresponding slave device. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + + nvidia,rx-clk-tap-delay: + description: + delays the clock coming in from the device with this tap value. + tap value varies based on platform design trace lengths from tegra + qspi to corresponding slave device. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 255 + + required: + - reg + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + - resets + +unevaluatedproperties: false + +examples: + - | + #include <dt-bindings/clock/tegra210-car.h> + #include <dt-bindings/reset/tegra210-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + spi@70410000 { + compatible = "nvidia,tegra210-qspi"; + reg = <0x70410000 0x1000>; + interrupts = <gic_spi 10 irq_type_level_high>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car tegra210_clk_qspi>, + <&tegra_car tegra210_clk_qspi_pm>; + clock-names = "qspi", "qspi_out"; + resets = <&tegra_car 211>; + dmas = <&apbdma 5>, <&apbdma 5>; + dma-names = "rx", "tx"; + + flash@0 { + compatible = "spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + nvidia,tx-clk-tap-delay = <0>; + nvidia,rx-clk-tap-delay = <0>; + }; + };
|
Serial Peripheral Interface (SPI)
|
9684752e5fe3989b45f686a4e0202a683038be4a
|
sowjanya komatineni
|
documentation
|
devicetree
|
bindings, spi
|
maintainers: add tegra quad spi driver section
|
add maintainers and mailing list entries to tegra quad spi driver section.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add tegra quad spi driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['maintainers']
| 1
| 8
| 0
|
--- diff --git a/maintainers b/maintainers --- a/maintainers +++ b/maintainers +tegra quad spi driver +m: thierry reding <thierry.reding@gmail.com> +m: jonathan hunter <jonathanh@nvidia.com> +m: sowjanya komatineni <skomatineni@nvidia.com> +l: linux-tegra@vger.kernel.org +s: maintained +f: drivers/spi/spi-tegra210-quad.c +
|
Serial Peripheral Interface (SPI)
|
e5c92bb924ce4bda9c4312b8596cf62ad7b07e2e
|
sowjanya komatineni
| |||
spi: tegra210-quad: add support for tegra210 qspi controller
|
tegra soc has a quad spi controller starting from tegra210.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add tegra quad spi driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['kconfig', 'c', 'makefile']
| 3
| 1,392
| 0
|
--- diff --git a/drivers/spi/kconfig b/drivers/spi/kconfig --- a/drivers/spi/kconfig +++ b/drivers/spi/kconfig +config spi_tegra210_quad + tristate "nvidia tegra qspi controller" + depends on arch_tegra || compile_test + depends on reset_controller + help + qspi driver for nvidia tegra qspi controller interface. this + controller is different from the spi controller and is available + on tegra socs starting from tegra210. + diff --git a/drivers/spi/makefile b/drivers/spi/makefile --- a/drivers/spi/makefile +++ b/drivers/spi/makefile +obj-$(config_spi_tegra210_quad) += spi-tegra210-quad.o diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c --- /dev/null +++ b/drivers/spi/spi-tegra210-quad.c +// spdx-license-identifier: gpl-2.0-only +// +// copyright (c) 2020 nvidia corporation. + +#include <linux/clk.h> +#include <linux/completion.h> +#include <linux/delay.h> +#include <linux/dmaengine.h> +#include <linux/dma-mapping.h> +#include <linux/dmapool.h> +#include <linux/err.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/kernel.h> +#include <linux/kthread.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/reset.h> +#include <linux/spi/spi.h> + +#define qspi_command1 0x000 +#define qspi_bit_length(x) (((x) & 0x1f) << 0) +#define qspi_packed bit(5) +#define qspi_interface_width_mask (0x03 << 7) +#define qspi_interface_width(x) (((x) & 0x03) << 7) +#define qspi_interface_width_single qspi_interface_width(0) +#define qspi_interface_width_dual qspi_interface_width(1) +#define qspi_interface_width_quad qspi_interface_width(2) +#define qspi_sdr_ddr_sel bit(9) +#define qspi_tx_en bit(11) +#define qspi_rx_en bit(12) +#define qspi_cs_sw_val bit(20) +#define qspi_cs_sw_hw bit(21) +#define qspi_control_mode_0 (0 << 28) +#define qspi_control_mode_3 (3 << 28) +#define qspi_control_mode_mask (3 << 28) +#define qspi_m_s bit(30) +#define qspi_pio bit(31) + +#define qspi_command2 0x004 +#define qspi_tx_tap_delay(x) (((x) & 0x3f) << 10) +#define qspi_rx_tap_delay(x) (((x) & 0xff) << 0) + +#define qspi_cs_timing1 0x008 +#define qspi_setup_hold(setup, hold) (((setup) << 4) | (hold)) + +#define qspi_cs_timing2 0x00c +#define cycles_between_packets_0(x) (((x) & 0x1f) << 0) +#define cs_active_between_packets_0 bit(5) + +#define qspi_trans_status 0x010 +#define qspi_blk_cnt(val) (((val) >> 0) & 0xffff) +#define qspi_rdy bit(30) + +#define qspi_fifo_status 0x014 +#define qspi_rx_fifo_empty bit(0) +#define qspi_rx_fifo_full bit(1) +#define qspi_tx_fifo_empty bit(2) +#define qspi_tx_fifo_full bit(3) +#define qspi_rx_fifo_unf bit(4) +#define qspi_rx_fifo_ovf bit(5) +#define qspi_tx_fifo_unf bit(6) +#define qspi_tx_fifo_ovf bit(7) +#define qspi_err bit(8) +#define qspi_tx_fifo_flush bit(14) +#define qspi_rx_fifo_flush bit(15) +#define qspi_tx_fifo_empty_count(val) (((val) >> 16) & 0x7f) +#define qspi_rx_fifo_full_count(val) (((val) >> 23) & 0x7f) + +#define qspi_fifo_error (qspi_rx_fifo_unf | \ + qspi_rx_fifo_ovf | \ + qspi_tx_fifo_unf | \ + qspi_tx_fifo_ovf) +#define qspi_fifo_empty (qspi_rx_fifo_empty | \ + qspi_tx_fifo_empty) + +#define qspi_tx_data 0x018 +#define qspi_rx_data 0x01c + +#define qspi_dma_ctl 0x020 +#define qspi_tx_trig(n) (((n) & 0x3) << 15) +#define qspi_tx_trig_1 qspi_tx_trig(0) +#define qspi_tx_trig_4 qspi_tx_trig(1) +#define qspi_tx_trig_8 qspi_tx_trig(2) +#define qspi_tx_trig_16 qspi_tx_trig(3) + +#define qspi_rx_trig(n) (((n) & 0x3) << 19) +#define qspi_rx_trig_1 qspi_rx_trig(0) +#define qspi_rx_trig_4 qspi_rx_trig(1) +#define qspi_rx_trig_8 qspi_rx_trig(2) +#define qspi_rx_trig_16 qspi_rx_trig(3) + +#define qspi_dma_en bit(31) + +#define qspi_dma_blk 0x024 +#define qspi_dma_blk_set(x) (((x) & 0xffff) << 0) + +#define qspi_tx_fifo 0x108 +#define qspi_rx_fifo 0x188 + +#define qspi_fifo_depth 64 + +#define qspi_intr_mask 0x18c +#define qspi_intr_rx_fifo_unf_mask bit(25) +#define qspi_intr_rx_fifo_ovf_mask bit(26) +#define qspi_intr_tx_fifo_unf_mask bit(27) +#define qspi_intr_tx_fifo_ovf_mask bit(28) +#define qspi_intr_rdy_mask bit(29) +#define qspi_intr_rx_tx_fifo_err (qspi_intr_rx_fifo_unf_mask | \ + qspi_intr_rx_fifo_ovf_mask | \ + qspi_intr_tx_fifo_unf_mask | \ + qspi_intr_tx_fifo_ovf_mask) + +#define qspi_misc_reg 0x194 +#define qspi_num_dummy_cycle(x) (((x) & 0xff) << 0) + +#define data_dir_tx bit(0) +#define data_dir_rx bit(1) + +#define qspi_dma_timeout (msecs_to_jiffies(1000)) +#define default_qspi_dma_buf_len (64 * 1024) + +struct tegra_qspi_client_data { + int tx_clk_tap_delay; + int rx_clk_tap_delay; +}; + +struct tegra_qspi { + struct device *dev; + struct spi_master *master; + /* lock to protect data accessed by irq */ + spinlock_t lock; + + struct clk *clk; + struct reset_control *rst; + void __iomem *base; + phys_addr_t phys; + unsigned int irq; + + u32 cur_speed; + unsigned int cur_pos; + unsigned int words_per_32bit; + unsigned int bytes_per_word; + unsigned int curr_dma_words; + unsigned int cur_direction; + + unsigned int cur_rx_pos; + unsigned int cur_tx_pos; + + unsigned int dma_buf_size; + unsigned int max_buf_size; + bool is_curr_dma_xfer; + + struct completion rx_dma_complete; + struct completion tx_dma_complete; + + u32 tx_status; + u32 rx_status; + u32 status_reg; + bool is_packed; + bool use_dma; + + u32 command1_reg; + u32 dma_control_reg; + u32 def_command1_reg; + u32 def_command2_reg; + u32 spi_cs_timing1; + u32 spi_cs_timing2; + + struct completion xfer_completion; + struct spi_transfer *curr_xfer; + + struct dma_chan *rx_dma_chan; + u32 *rx_dma_buf; + dma_addr_t rx_dma_phys; + struct dma_async_tx_descriptor *rx_dma_desc; + + struct dma_chan *tx_dma_chan; + u32 *tx_dma_buf; + dma_addr_t tx_dma_phys; + struct dma_async_tx_descriptor *tx_dma_desc; +}; + +static inline u32 tegra_qspi_readl(struct tegra_qspi *tqspi, unsigned long offset) +{ + return readl(tqspi->base + offset); +} + +static inline void tegra_qspi_writel(struct tegra_qspi *tqspi, u32 value, unsigned long offset) +{ + writel(value, tqspi->base + offset); + + /* read back register to make sure that register writes completed */ + if (offset != qspi_tx_fifo) + readl(tqspi->base + qspi_command1); +} + +static void tegra_qspi_mask_clear_irq(struct tegra_qspi *tqspi) +{ + u32 value; + + /* write 1 to clear status register */ + value = tegra_qspi_readl(tqspi, qspi_trans_status); + tegra_qspi_writel(tqspi, value, qspi_trans_status); + + value = tegra_qspi_readl(tqspi, qspi_intr_mask); + if (!(value & qspi_intr_rdy_mask)) { + value |= (qspi_intr_rdy_mask | qspi_intr_rx_tx_fifo_err); + tegra_qspi_writel(tqspi, value, qspi_intr_mask); + } + + /* clear fifo status error if any */ + value = tegra_qspi_readl(tqspi, qspi_fifo_status); + if (value & qspi_err) + tegra_qspi_writel(tqspi, qspi_err | qspi_fifo_error, qspi_fifo_status); +} + +static unsigned int +tegra_qspi_calculate_curr_xfer_param(struct tegra_qspi *tqspi, struct spi_transfer *t) +{ + unsigned int max_word, max_len, total_fifo_words; + unsigned int remain_len = t->len - tqspi->cur_pos; + unsigned int bits_per_word = t->bits_per_word; + + tqspi->bytes_per_word = div_round_up(bits_per_word, 8); + + /* + * tegra qspi controller supports packed or unpacked mode transfers. + * packed mode is used for data transfers using 8, 16, or 32 bits per + * word with a minimum transfer of 1 word and for all other transfers + * unpacked mode will be used. + */ + + if ((bits_per_word == 8 || bits_per_word == 16 || + bits_per_word == 32) && t->len > 3) { + tqspi->is_packed = true; + tqspi->words_per_32bit = 32 / bits_per_word; + } else { + tqspi->is_packed = false; + tqspi->words_per_32bit = 1; + } + + if (tqspi->is_packed) { + max_len = min(remain_len, tqspi->max_buf_size); + tqspi->curr_dma_words = max_len / tqspi->bytes_per_word; + total_fifo_words = (max_len + 3) / 4; + } else { + max_word = (remain_len - 1) / tqspi->bytes_per_word + 1; + max_word = min(max_word, tqspi->max_buf_size / 4); + tqspi->curr_dma_words = max_word; + total_fifo_words = max_word; + } + + return total_fifo_words; +} + +static unsigned int +tegra_qspi_fill_tx_fifo_from_client_txbuf(struct tegra_qspi *tqspi, struct spi_transfer *t) +{ + unsigned int written_words, fifo_words_left, count; + unsigned int len, tx_empty_count, max_n_32bit, i; + u8 *tx_buf = (u8 *)t->tx_buf + tqspi->cur_tx_pos; + u32 fifo_status; + + fifo_status = tegra_qspi_readl(tqspi, qspi_fifo_status); + tx_empty_count = qspi_tx_fifo_empty_count(fifo_status); + + if (tqspi->is_packed) { + fifo_words_left = tx_empty_count * tqspi->words_per_32bit; + written_words = min(fifo_words_left, tqspi->curr_dma_words); + len = written_words * tqspi->bytes_per_word; + max_n_32bit = div_round_up(len, 4); + for (count = 0; count < max_n_32bit; count++) { + u32 x = 0; + + for (i = 0; (i < 4) && len; i++, len--) + x |= (u32)(*tx_buf++) << (i * 8); + tegra_qspi_writel(tqspi, x, qspi_tx_fifo); + } + + tqspi->cur_tx_pos += written_words * tqspi->bytes_per_word; + } else { + unsigned int write_bytes; + u8 bytes_per_word = tqspi->bytes_per_word; + + max_n_32bit = min(tqspi->curr_dma_words, tx_empty_count); + written_words = max_n_32bit; + len = written_words * tqspi->bytes_per_word; + if (len > t->len - tqspi->cur_pos) + len = t->len - tqspi->cur_pos; + write_bytes = len; + for (count = 0; count < max_n_32bit; count++) { + u32 x = 0; + + for (i = 0; len && (i < bytes_per_word); i++, len--) + x |= (u32)(*tx_buf++) << (i * 8); + tegra_qspi_writel(tqspi, x, qspi_tx_fifo); + } + + tqspi->cur_tx_pos += write_bytes; + } + + return written_words; +} + +static unsigned int +tegra_qspi_read_rx_fifo_to_client_rxbuf(struct tegra_qspi *tqspi, struct spi_transfer *t) +{ + u8 *rx_buf = (u8 *)t->rx_buf + tqspi->cur_rx_pos; + unsigned int len, rx_full_count, count, i; + unsigned int read_words = 0; + u32 fifo_status, x; + + fifo_status = tegra_qspi_readl(tqspi, qspi_fifo_status); + rx_full_count = qspi_rx_fifo_full_count(fifo_status); + if (tqspi->is_packed) { + len = tqspi->curr_dma_words * tqspi->bytes_per_word; + for (count = 0; count < rx_full_count; count++) { + x = tegra_qspi_readl(tqspi, qspi_rx_fifo); + + for (i = 0; len && (i < 4); i++, len--) + *rx_buf++ = (x >> i * 8) & 0xff; + } + + read_words += tqspi->curr_dma_words; + tqspi->cur_rx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word; + } else { + u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; + u8 bytes_per_word = tqspi->bytes_per_word; + unsigned int read_bytes; + + len = rx_full_count * bytes_per_word; + if (len > t->len - tqspi->cur_pos) + len = t->len - tqspi->cur_pos; + read_bytes = len; + for (count = 0; count < rx_full_count; count++) { + x = tegra_qspi_readl(tqspi, qspi_rx_fifo) & rx_mask; + + for (i = 0; len && (i < bytes_per_word); i++, len--) + *rx_buf++ = (x >> (i * 8)) & 0xff; + } + + read_words += rx_full_count; + tqspi->cur_rx_pos += read_bytes; + } + + return read_words; +} + +static void +tegra_qspi_copy_client_txbuf_to_qspi_txbuf(struct tegra_qspi *tqspi, struct spi_transfer *t) +{ + dma_sync_single_for_cpu(tqspi->dev, tqspi->tx_dma_phys, + tqspi->dma_buf_size, dma_to_device); + + /* + * in packed mode, each word in fifo may contain multiple packets + * based on bits per word. so all bytes in each fifo word are valid. + * + * in unpacked mode, each word in fifo contains single packet and + * based on bits per word any remaining bits in fifo word will be + * ignored by the hardware and are invalid bits. + */ + if (tqspi->is_packed) { + tqspi->cur_tx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word; + } else { + u8 *tx_buf = (u8 *)t->tx_buf + tqspi->cur_tx_pos; + unsigned int i, count, consume, write_bytes; + + /* + * fill tx_dma_buf to contain single packet in each word based + * on bits per word from spi core tx_buf. + */ + consume = tqspi->curr_dma_words * tqspi->bytes_per_word; + if (consume > t->len - tqspi->cur_pos) + consume = t->len - tqspi->cur_pos; + write_bytes = consume; + for (count = 0; count < tqspi->curr_dma_words; count++) { + u32 x = 0; + + for (i = 0; consume && (i < tqspi->bytes_per_word); i++, consume--) + x |= (u32)(*tx_buf++) << (i * 8); + tqspi->tx_dma_buf[count] = x; + } + + tqspi->cur_tx_pos += write_bytes; + } + + dma_sync_single_for_device(tqspi->dev, tqspi->tx_dma_phys, + tqspi->dma_buf_size, dma_to_device); +} + +static void +tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf(struct tegra_qspi *tqspi, struct spi_transfer *t) +{ + dma_sync_single_for_cpu(tqspi->dev, tqspi->rx_dma_phys, + tqspi->dma_buf_size, dma_from_device); + + if (tqspi->is_packed) { + tqspi->cur_rx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word; + } else { + unsigned char *rx_buf = t->rx_buf + tqspi->cur_rx_pos; + u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; + unsigned int i, count, consume, read_bytes; + + /* + * each fifo word contains single data packet. + * skip invalid bits in each fifo word based on bits per word + * and align bytes while filling in spi core rx_buf. + */ + consume = tqspi->curr_dma_words * tqspi->bytes_per_word; + if (consume > t->len - tqspi->cur_pos) + consume = t->len - tqspi->cur_pos; + read_bytes = consume; + for (count = 0; count < tqspi->curr_dma_words; count++) { + u32 x = tqspi->rx_dma_buf[count] & rx_mask; + + for (i = 0; consume && (i < tqspi->bytes_per_word); i++, consume--) + *rx_buf++ = (x >> (i * 8)) & 0xff; + } + + tqspi->cur_rx_pos += read_bytes; + } + + dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys, + tqspi->dma_buf_size, dma_from_device); +} + +static void tegra_qspi_dma_complete(void *args) +{ + struct completion *dma_complete = args; + + complete(dma_complete); +} + +static int tegra_qspi_start_tx_dma(struct tegra_qspi *tqspi, struct spi_transfer *t, int len) +{ + dma_addr_t tx_dma_phys; + + reinit_completion(&tqspi->tx_dma_complete); + + if (tqspi->is_packed) + tx_dma_phys = t->tx_dma; + else + tx_dma_phys = tqspi->tx_dma_phys; + + tqspi->tx_dma_desc = dmaengine_prep_slave_single(tqspi->tx_dma_chan, tx_dma_phys, + len, dma_mem_to_dev, + dma_prep_interrupt | dma_ctrl_ack); + + if (!tqspi->tx_dma_desc) { + dev_err(tqspi->dev, "unable to get tx descriptor "); + return -eio; + } + + tqspi->tx_dma_desc->callback = tegra_qspi_dma_complete; + tqspi->tx_dma_desc->callback_param = &tqspi->tx_dma_complete; + dmaengine_submit(tqspi->tx_dma_desc); + dma_async_issue_pending(tqspi->tx_dma_chan); + + return 0; +} + +static int tegra_qspi_start_rx_dma(struct tegra_qspi *tqspi, struct spi_transfer *t, int len) +{ + dma_addr_t rx_dma_phys; + + reinit_completion(&tqspi->rx_dma_complete); + + if (tqspi->is_packed) + rx_dma_phys = t->rx_dma; + else + rx_dma_phys = tqspi->rx_dma_phys; + + tqspi->rx_dma_desc = dmaengine_prep_slave_single(tqspi->rx_dma_chan, rx_dma_phys, + len, dma_dev_to_mem, + dma_prep_interrupt | dma_ctrl_ack); + + if (!tqspi->rx_dma_desc) { + dev_err(tqspi->dev, "unable to get rx descriptor "); + return -eio; + } + + tqspi->rx_dma_desc->callback = tegra_qspi_dma_complete; + tqspi->rx_dma_desc->callback_param = &tqspi->rx_dma_complete; + dmaengine_submit(tqspi->rx_dma_desc); + dma_async_issue_pending(tqspi->rx_dma_chan); + + return 0; +} + +static int tegra_qspi_flush_fifos(struct tegra_qspi *tqspi, bool atomic) +{ + void __iomem *addr = tqspi->base + qspi_fifo_status; + u32 val; + + val = tegra_qspi_readl(tqspi, qspi_fifo_status); + if ((val & qspi_fifo_empty) == qspi_fifo_empty) + return 0; + + val |= qspi_rx_fifo_flush | qspi_tx_fifo_flush; + tegra_qspi_writel(tqspi, val, qspi_fifo_status); + + if (!atomic) + return readl_relaxed_poll_timeout(addr, val, + (val & qspi_fifo_empty) == qspi_fifo_empty, + 1000, 1000000); + + return readl_relaxed_poll_timeout_atomic(addr, val, + (val & qspi_fifo_empty) == qspi_fifo_empty, + 1000, 1000000); +} + +static void tegra_qspi_unmask_irq(struct tegra_qspi *tqspi) +{ + u32 intr_mask; + + intr_mask = tegra_qspi_readl(tqspi, qspi_intr_mask); + intr_mask &= ~(qspi_intr_rdy_mask | qspi_intr_rx_tx_fifo_err); + tegra_qspi_writel(tqspi, intr_mask, qspi_intr_mask); +} + +static int tegra_qspi_dma_map_xfer(struct tegra_qspi *tqspi, struct spi_transfer *t) +{ + u8 *tx_buf = (u8 *)t->tx_buf + tqspi->cur_tx_pos; + u8 *rx_buf = (u8 *)t->rx_buf + tqspi->cur_rx_pos; + unsigned int len; + + len = div_round_up(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4; + + if (t->tx_buf) { + t->tx_dma = dma_map_single(tqspi->dev, (void *)tx_buf, len, dma_to_device); + if (dma_mapping_error(tqspi->dev, t->tx_dma)) + return -enomem; + } + + if (t->rx_buf) { + t->rx_dma = dma_map_single(tqspi->dev, (void *)rx_buf, len, dma_from_device); + if (dma_mapping_error(tqspi->dev, t->rx_dma)) { + dma_unmap_single(tqspi->dev, t->tx_dma, len, dma_to_device); + return -enomem; + } + } + + return 0; +} + +static void tegra_qspi_dma_unmap_xfer(struct tegra_qspi *tqspi, struct spi_transfer *t) +{ + unsigned int len; + + len = div_round_up(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4; + + dma_unmap_single(tqspi->dev, t->tx_dma, len, dma_to_device); + dma_unmap_single(tqspi->dev, t->rx_dma, len, dma_from_device); +} + +static int tegra_qspi_start_dma_based_transfer(struct tegra_qspi *tqspi, struct spi_transfer *t) +{ + struct dma_slave_config dma_sconfig = { 0 }; + unsigned int len; + u8 dma_burst; + int ret = 0; + u32 val; + + if (tqspi->is_packed) { + ret = tegra_qspi_dma_map_xfer(tqspi, t); + if (ret < 0) + return ret; + } + + val = qspi_dma_blk_set(tqspi->curr_dma_words - 1); + tegra_qspi_writel(tqspi, val, qspi_dma_blk); + + tegra_qspi_unmask_irq(tqspi); + + if (tqspi->is_packed) + len = div_round_up(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4; + else + len = tqspi->curr_dma_words * 4; + + /* set attention level based on length of transfer */ + val = 0; + if (len & 0xf) { + val |= qspi_tx_trig_1 | qspi_rx_trig_1; + dma_burst = 1; + } else if (((len) >> 4) & 0x1) { + val |= qspi_tx_trig_4 | qspi_rx_trig_4; + dma_burst = 4; + } else { + val |= qspi_tx_trig_8 | qspi_rx_trig_8; + dma_burst = 8; + } + + tegra_qspi_writel(tqspi, val, qspi_dma_ctl); + tqspi->dma_control_reg = val; + + dma_sconfig.device_fc = true; + if (tqspi->cur_direction & data_dir_tx) { + dma_sconfig.dst_addr = tqspi->phys + qspi_tx_fifo; + dma_sconfig.dst_addr_width = dma_slave_buswidth_4_bytes; + dma_sconfig.dst_maxburst = dma_burst; + ret = dmaengine_slave_config(tqspi->tx_dma_chan, &dma_sconfig); + if (ret < 0) { + dev_err(tqspi->dev, "failed dma slave config: %d ", ret); + return ret; + } + + tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t); + ret = tegra_qspi_start_tx_dma(tqspi, t, len); + if (ret < 0) { + dev_err(tqspi->dev, "failed to starting tx dma: %d ", ret); + return ret; + } + } + + if (tqspi->cur_direction & data_dir_rx) { + dma_sconfig.src_addr = tqspi->phys + qspi_rx_fifo; + dma_sconfig.src_addr_width = dma_slave_buswidth_4_bytes; + dma_sconfig.src_maxburst = dma_burst; + ret = dmaengine_slave_config(tqspi->rx_dma_chan, &dma_sconfig); + if (ret < 0) { + dev_err(tqspi->dev, "failed dma slave config: %d ", ret); + return ret; + } + + dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys, + tqspi->dma_buf_size, + dma_from_device); + + ret = tegra_qspi_start_rx_dma(tqspi, t, len); + if (ret < 0) { + dev_err(tqspi->dev, "failed to start rx dma: %d ", ret); + if (tqspi->cur_direction & data_dir_tx) + dmaengine_terminate_all(tqspi->tx_dma_chan); + return ret; + } + } + + tegra_qspi_writel(tqspi, tqspi->command1_reg, qspi_command1); + + tqspi->is_curr_dma_xfer = true; + tqspi->dma_control_reg = val; + val |= qspi_dma_en; + tegra_qspi_writel(tqspi, val, qspi_dma_ctl); + + return ret; +} + +static int tegra_qspi_start_cpu_based_transfer(struct tegra_qspi *qspi, struct spi_transfer *t) +{ + u32 val; + unsigned int cur_words; + + if (qspi->cur_direction & data_dir_tx) + cur_words = tegra_qspi_fill_tx_fifo_from_client_txbuf(qspi, t); + else + cur_words = qspi->curr_dma_words; + + val = qspi_dma_blk_set(cur_words - 1); + tegra_qspi_writel(qspi, val, qspi_dma_blk); + + tegra_qspi_unmask_irq(qspi); + + qspi->is_curr_dma_xfer = false; + val = qspi->command1_reg; + val |= qspi_pio; + tegra_qspi_writel(qspi, val, qspi_command1); + + return 0; +} + +static void tegra_qspi_deinit_dma(struct tegra_qspi *tqspi) +{ + if (tqspi->tx_dma_buf) { + dma_free_coherent(tqspi->dev, tqspi->dma_buf_size, + tqspi->tx_dma_buf, tqspi->tx_dma_phys); + tqspi->tx_dma_buf = null; + } + + if (tqspi->tx_dma_chan) { + dma_release_channel(tqspi->tx_dma_chan); + tqspi->tx_dma_chan = null; + } + + if (tqspi->rx_dma_buf) { + dma_free_coherent(tqspi->dev, tqspi->dma_buf_size, + tqspi->rx_dma_buf, tqspi->rx_dma_phys); + tqspi->rx_dma_buf = null; + } + + if (tqspi->rx_dma_chan) { + dma_release_channel(tqspi->rx_dma_chan); + tqspi->rx_dma_chan = null; + } +} + +static int tegra_qspi_init_dma(struct tegra_qspi *tqspi) +{ + struct dma_chan *dma_chan; + dma_addr_t dma_phys; + u32 *dma_buf; + int err; + + dma_chan = dma_request_chan(tqspi->dev, "rx"); + if (is_err(dma_chan)) { + err = ptr_err(dma_chan); + goto err_out; + } + + tqspi->rx_dma_chan = dma_chan; + + dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, gfp_kernel); + if (!dma_buf) { + err = -enomem; + goto err_out; + } + + tqspi->rx_dma_buf = dma_buf; + tqspi->rx_dma_phys = dma_phys; + + dma_chan = dma_request_chan(tqspi->dev, "tx"); + if (is_err(dma_chan)) { + err = ptr_err(dma_chan); + goto err_out; + } + + tqspi->tx_dma_chan = dma_chan; + + dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, gfp_kernel); + if (!dma_buf) { + err = -enomem; + goto err_out; + } + + tqspi->tx_dma_buf = dma_buf; + tqspi->tx_dma_phys = dma_phys; + tqspi->use_dma = true; + + return 0; + +err_out: + tegra_qspi_deinit_dma(tqspi); + + if (err != -eprobe_defer) { + dev_err(tqspi->dev, "cannot use dma: %d ", err); + dev_err(tqspi->dev, "falling back to pio "); + return 0; + } + + return err; +} + +static u32 tegra_qspi_setup_transfer_one(struct spi_device *spi, struct spi_transfer *t, + bool is_first_of_msg) +{ + struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); + struct tegra_qspi_client_data *cdata = spi->controller_data; + u32 command1, command2, speed = t->speed_hz; + u8 bits_per_word = t->bits_per_word; + u32 tx_tap = 0, rx_tap = 0; + int req_mode; + + if (speed != tqspi->cur_speed) { + clk_set_rate(tqspi->clk, speed); + tqspi->cur_speed = speed; + } + + tqspi->cur_pos = 0; + tqspi->cur_rx_pos = 0; + tqspi->cur_tx_pos = 0; + tqspi->curr_xfer = t; + + if (is_first_of_msg) { + tegra_qspi_mask_clear_irq(tqspi); + + command1 = tqspi->def_command1_reg; + command1 |= qspi_bit_length(bits_per_word - 1); + + command1 &= ~qspi_control_mode_mask; + req_mode = spi->mode & 0x3; + if (req_mode == spi_mode_3) + command1 |= qspi_control_mode_3; + else + command1 |= qspi_control_mode_0; + + if (spi->mode & spi_cs_high) + command1 |= qspi_cs_sw_val; + else + command1 &= ~qspi_cs_sw_val; + tegra_qspi_writel(tqspi, command1, qspi_command1); + + if (cdata && cdata->tx_clk_tap_delay) + tx_tap = cdata->tx_clk_tap_delay; + + if (cdata && cdata->rx_clk_tap_delay) + rx_tap = cdata->rx_clk_tap_delay; + + command2 = qspi_tx_tap_delay(tx_tap) | qspi_rx_tap_delay(rx_tap); + if (command2 != tqspi->def_command2_reg) + tegra_qspi_writel(tqspi, command2, qspi_command2); + + } else { + command1 = tqspi->command1_reg; + command1 &= ~qspi_bit_length(~0); + command1 |= qspi_bit_length(bits_per_word - 1); + } + + command1 &= ~qspi_sdr_ddr_sel; + + return command1; +} + +static int tegra_qspi_start_transfer_one(struct spi_device *spi, + struct spi_transfer *t, u32 command1) +{ + struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); + unsigned int total_fifo_words; + u8 bus_width = 0; + int ret; + + total_fifo_words = tegra_qspi_calculate_curr_xfer_param(tqspi, t); + + command1 &= ~qspi_packed; + if (tqspi->is_packed) + command1 |= qspi_packed; + tegra_qspi_writel(tqspi, command1, qspi_command1); + + tqspi->cur_direction = 0; + + command1 &= ~(qspi_tx_en | qspi_rx_en); + if (t->rx_buf) { + command1 |= qspi_rx_en; + tqspi->cur_direction |= data_dir_rx; + bus_width = t->rx_nbits; + } + + if (t->tx_buf) { + command1 |= qspi_tx_en; + tqspi->cur_direction |= data_dir_tx; + bus_width = t->tx_nbits; + } + + command1 &= ~qspi_interface_width_mask; + + if (bus_width == spi_nbits_quad) + command1 |= qspi_interface_width_quad; + else if (bus_width == spi_nbits_dual) + command1 |= qspi_interface_width_dual; + else + command1 |= qspi_interface_width_single; + + tqspi->command1_reg = command1; + + ret = tegra_qspi_flush_fifos(tqspi, false); + if (ret < 0) + return ret; + + if (tqspi->use_dma && total_fifo_words > qspi_fifo_depth) + ret = tegra_qspi_start_dma_based_transfer(tqspi, t); + else + ret = tegra_qspi_start_cpu_based_transfer(tqspi, t); + + return ret; +} + +static struct tegra_qspi_client_data *tegra_qspi_parse_cdata_dt(struct spi_device *spi) +{ + struct tegra_qspi_client_data *cdata; + struct device_node *slave_np = spi->dev.of_node; + + cdata = kzalloc(sizeof(*cdata), gfp_kernel); + if (!cdata) + return null; + + of_property_read_u32(slave_np, "nvidia,tx-clk-tap-delay", + &cdata->tx_clk_tap_delay); + of_property_read_u32(slave_np, "nvidia,rx-clk-tap-delay", + &cdata->rx_clk_tap_delay); + return cdata; +} + +static void tegra_qspi_cleanup(struct spi_device *spi) +{ + struct tegra_qspi_client_data *cdata = spi->controller_data; + + spi->controller_data = null; + kfree(cdata); +} + +static int tegra_qspi_setup(struct spi_device *spi) +{ + struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); + struct tegra_qspi_client_data *cdata = spi->controller_data; + unsigned long flags; + u32 val; + int ret; + + ret = pm_runtime_resume_and_get(tqspi->dev); + if (ret < 0) { + dev_err(tqspi->dev, "failed to get runtime pm: %d ", ret); + return ret; + } + + if (!cdata) { + cdata = tegra_qspi_parse_cdata_dt(spi); + spi->controller_data = cdata; + } + + spin_lock_irqsave(&tqspi->lock, flags); + + /* keep default cs state to inactive */ + val = tqspi->def_command1_reg; + if (spi->mode & spi_cs_high) + val &= ~qspi_cs_sw_val; + else + val |= qspi_cs_sw_val; + + tqspi->def_command1_reg = val; + tegra_qspi_writel(tqspi, tqspi->def_command1_reg, qspi_command1); + + spin_unlock_irqrestore(&tqspi->lock, flags); + + pm_runtime_put(tqspi->dev); + + return 0; +} + +static void tegra_qspi_dump_regs(struct tegra_qspi *tqspi) +{ + dev_dbg(tqspi->dev, "============ qspi register dump ============ "); + dev_dbg(tqspi->dev, "command1: 0x%08x | command2: 0x%08x ", + tegra_qspi_readl(tqspi, qspi_command1), + tegra_qspi_readl(tqspi, qspi_command2)); + dev_dbg(tqspi->dev, "dma_ctl: 0x%08x | dma_blk: 0x%08x ", + tegra_qspi_readl(tqspi, qspi_dma_ctl), + tegra_qspi_readl(tqspi, qspi_dma_blk)); + dev_dbg(tqspi->dev, "intr_mask: 0x%08x | misc: 0x%08x ", + tegra_qspi_readl(tqspi, qspi_intr_mask), + tegra_qspi_readl(tqspi, qspi_misc_reg)); + dev_dbg(tqspi->dev, "trans_stat: 0x%08x | fifo_status: 0x%08x ", + tegra_qspi_readl(tqspi, qspi_trans_status), + tegra_qspi_readl(tqspi, qspi_fifo_status)); +} + +static void tegra_qspi_handle_error(struct tegra_qspi *tqspi) +{ + dev_err(tqspi->dev, "error in transfer, fifo status 0x%08x ", tqspi->status_reg); + tegra_qspi_dump_regs(tqspi); + tegra_qspi_flush_fifos(tqspi, true); + reset_control_assert(tqspi->rst); + udelay(2); + reset_control_deassert(tqspi->rst); +} + +static void tegra_qspi_transfer_end(struct spi_device *spi) +{ + struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); + int cs_val = (spi->mode & spi_cs_high) ? 0 : 1; + + if (cs_val) + tqspi->command1_reg |= qspi_cs_sw_val; + else + tqspi->command1_reg &= ~qspi_cs_sw_val; + tegra_qspi_writel(tqspi, tqspi->command1_reg, qspi_command1); + tegra_qspi_writel(tqspi, tqspi->def_command1_reg, qspi_command1); +} + +static int tegra_qspi_transfer_one_message(struct spi_master *master, struct spi_message *msg) +{ + struct tegra_qspi *tqspi = spi_master_get_devdata(master); + struct spi_device *spi = msg->spi; + struct spi_transfer *xfer; + bool is_first_msg = true; + int ret; + + msg->status = 0; + msg->actual_length = 0; + tqspi->tx_status = 0; + tqspi->rx_status = 0; + + list_for_each_entry(xfer, &msg->transfers, transfer_list) { + u32 cmd1; + + reinit_completion(&tqspi->xfer_completion); + + cmd1 = tegra_qspi_setup_transfer_one(spi, xfer, is_first_msg); + + ret = tegra_qspi_start_transfer_one(spi, xfer, cmd1); + if (ret < 0) { + dev_err(tqspi->dev, "failed to start transfer: %d ", ret); + goto complete_xfer; + } + + is_first_msg = false; + ret = wait_for_completion_timeout(&tqspi->xfer_completion, + qspi_dma_timeout); + if (warn_on(ret == 0)) { + dev_err(tqspi->dev, "transfer timeout: %d ", ret); + if (tqspi->is_curr_dma_xfer && (tqspi->cur_direction & data_dir_tx)) + dmaengine_terminate_all(tqspi->tx_dma_chan); + if (tqspi->is_curr_dma_xfer && (tqspi->cur_direction & data_dir_rx)) + dmaengine_terminate_all(tqspi->rx_dma_chan); + tegra_qspi_handle_error(tqspi); + ret = -eio; + goto complete_xfer; + } + + if (tqspi->tx_status || tqspi->rx_status) { + tegra_qspi_handle_error(tqspi); + ret = -eio; + goto complete_xfer; + } + + msg->actual_length += xfer->len; + +complete_xfer: + if (ret < 0) { + tegra_qspi_transfer_end(spi); + spi_transfer_delay_exec(xfer); + goto exit; + } + + if (list_is_last(&xfer->transfer_list, &msg->transfers)) { + /* de-activate cs after last transfer only when cs_change is not set */ + if (!xfer->cs_change) { + tegra_qspi_transfer_end(spi); + spi_transfer_delay_exec(xfer); + } + } else if (xfer->cs_change) { + /* de-activated cs between the transfers only when cs_change is set */ + tegra_qspi_transfer_end(spi); + spi_transfer_delay_exec(xfer); + } + } + + ret = 0; +exit: + msg->status = ret; + spi_finalize_current_message(master); + return ret; +} + +static irqreturn_t handle_cpu_based_xfer(struct tegra_qspi *tqspi) +{ + struct spi_transfer *t = tqspi->curr_xfer; + unsigned long flags; + + spin_lock_irqsave(&tqspi->lock, flags); + + if (tqspi->tx_status || tqspi->rx_status) { + tegra_qspi_handle_error(tqspi); + complete(&tqspi->xfer_completion); + goto exit; + } + + if (tqspi->cur_direction & data_dir_rx) + tegra_qspi_read_rx_fifo_to_client_rxbuf(tqspi, t); + + if (tqspi->cur_direction & data_dir_tx) + tqspi->cur_pos = tqspi->cur_tx_pos; + else + tqspi->cur_pos = tqspi->cur_rx_pos; + + if (tqspi->cur_pos == t->len) { + complete(&tqspi->xfer_completion); + goto exit; + } + + tegra_qspi_calculate_curr_xfer_param(tqspi, t); + tegra_qspi_start_cpu_based_transfer(tqspi, t); +exit: + spin_unlock_irqrestore(&tqspi->lock, flags); + return irq_handled; +} + +static irqreturn_t handle_dma_based_xfer(struct tegra_qspi *tqspi) +{ + struct spi_transfer *t = tqspi->curr_xfer; + unsigned int total_fifo_words; + unsigned long flags; + long wait_status; + int err = 0; + + if (tqspi->cur_direction & data_dir_tx) { + if (tqspi->tx_status) { + dmaengine_terminate_all(tqspi->tx_dma_chan); + err += 1; + } else { + wait_status = wait_for_completion_interruptible_timeout( + &tqspi->tx_dma_complete, qspi_dma_timeout); + if (wait_status <= 0) { + dmaengine_terminate_all(tqspi->tx_dma_chan); + dev_err(tqspi->dev, "failed tx dma transfer "); + err += 1; + } + } + } + + if (tqspi->cur_direction & data_dir_rx) { + if (tqspi->rx_status) { + dmaengine_terminate_all(tqspi->rx_dma_chan); + err += 2; + } else { + wait_status = wait_for_completion_interruptible_timeout( + &tqspi->rx_dma_complete, qspi_dma_timeout); + if (wait_status <= 0) { + dmaengine_terminate_all(tqspi->rx_dma_chan); + dev_err(tqspi->dev, "failed rx dma transfer "); + err += 2; + } + } + } + + spin_lock_irqsave(&tqspi->lock, flags); + + if (err) { + tegra_qspi_dma_unmap_xfer(tqspi, t); + tegra_qspi_handle_error(tqspi); + complete(&tqspi->xfer_completion); + goto exit; + } + + if (tqspi->cur_direction & data_dir_rx) + tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf(tqspi, t); + + if (tqspi->cur_direction & data_dir_tx) + tqspi->cur_pos = tqspi->cur_tx_pos; + else + tqspi->cur_pos = tqspi->cur_rx_pos; + + if (tqspi->cur_pos == t->len) { + tegra_qspi_dma_unmap_xfer(tqspi, t); + complete(&tqspi->xfer_completion); + goto exit; + } + + tegra_qspi_dma_unmap_xfer(tqspi, t); + + /* continue transfer in current message */ + total_fifo_words = tegra_qspi_calculate_curr_xfer_param(tqspi, t); + if (total_fifo_words > qspi_fifo_depth) + err = tegra_qspi_start_dma_based_transfer(tqspi, t); + else + err = tegra_qspi_start_cpu_based_transfer(tqspi, t); + +exit: + spin_unlock_irqrestore(&tqspi->lock, flags); + return irq_handled; +} + +static irqreturn_t tegra_qspi_isr_thread(int irq, void *context_data) +{ + struct tegra_qspi *tqspi = context_data; + + tqspi->status_reg = tegra_qspi_readl(tqspi, qspi_fifo_status); + + if (tqspi->cur_direction & data_dir_tx) + tqspi->tx_status = tqspi->status_reg & (qspi_tx_fifo_unf | qspi_tx_fifo_ovf); + + if (tqspi->cur_direction & data_dir_rx) + tqspi->rx_status = tqspi->status_reg & (qspi_rx_fifo_ovf | qspi_rx_fifo_unf); + + tegra_qspi_mask_clear_irq(tqspi); + + if (!tqspi->is_curr_dma_xfer) + return handle_cpu_based_xfer(tqspi); + + return handle_dma_based_xfer(tqspi); +} + +static const struct of_device_id tegra_qspi_of_match[] = { + { .compatible = "nvidia,tegra210-qspi", }, + { .compatible = "nvidia,tegra186-qspi", }, + { .compatible = "nvidia,tegra194-qspi", }, + {} +}; + +module_device_table(of, tegra_qspi_of_match); + +static int tegra_qspi_probe(struct platform_device *pdev) +{ + struct spi_master *master; + struct tegra_qspi *tqspi; + struct resource *r; + int ret, qspi_irq; + int bus_num; + + master = devm_spi_alloc_master(&pdev->dev, sizeof(*tqspi)); + if (!master) + return -enomem; + + platform_set_drvdata(pdev, master); + tqspi = spi_master_get_devdata(master); + + master->mode_bits = spi_mode_0 | spi_mode_3 | spi_cs_high | + spi_tx_dual | spi_rx_dual | spi_tx_quad | spi_rx_quad; + master->bits_per_word_mask = spi_bpw_mask(32) | spi_bpw_mask(16) | spi_bpw_mask(8); + master->setup = tegra_qspi_setup; + master->cleanup = tegra_qspi_cleanup; + master->transfer_one_message = tegra_qspi_transfer_one_message; + master->num_chipselect = 1; + master->auto_runtime_pm = true; + + bus_num = of_alias_get_id(pdev->dev.of_node, "spi"); + if (bus_num >= 0) + master->bus_num = bus_num; + + tqspi->master = master; + tqspi->dev = &pdev->dev; + spin_lock_init(&tqspi->lock); + + r = platform_get_resource(pdev, ioresource_mem, 0); + tqspi->base = devm_ioremap_resource(&pdev->dev, r); + if (is_err(tqspi->base)) + return ptr_err(tqspi->base); + + tqspi->phys = r->start; + qspi_irq = platform_get_irq(pdev, 0); + tqspi->irq = qspi_irq; + + tqspi->clk = devm_clk_get(&pdev->dev, "qspi"); + if (is_err(tqspi->clk)) { + ret = ptr_err(tqspi->clk); + dev_err(&pdev->dev, "failed to get clock: %d ", ret); + return ret; + } + + tqspi->rst = devm_reset_control_get_exclusive(&pdev->dev, null); + if (is_err(tqspi->rst)) { + ret = ptr_err(tqspi->rst); + dev_err(&pdev->dev, "failed to get reset control: %d ", ret); + return ret; + } + + tqspi->max_buf_size = qspi_fifo_depth << 2; + tqspi->dma_buf_size = default_qspi_dma_buf_len; + + ret = tegra_qspi_init_dma(tqspi); + if (ret < 0) + return ret; + + if (tqspi->use_dma) + tqspi->max_buf_size = tqspi->dma_buf_size; + + init_completion(&tqspi->tx_dma_complete); + init_completion(&tqspi->rx_dma_complete); + init_completion(&tqspi->xfer_completion); + + pm_runtime_enable(&pdev->dev); + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "failed to get runtime pm: %d ", ret); + goto exit_pm_disable; + } + + reset_control_assert(tqspi->rst); + udelay(2); + reset_control_deassert(tqspi->rst); + + tqspi->def_command1_reg = qspi_m_s | qspi_cs_sw_hw | qspi_cs_sw_val; + tegra_qspi_writel(tqspi, tqspi->def_command1_reg, qspi_command1); + tqspi->spi_cs_timing1 = tegra_qspi_readl(tqspi, qspi_cs_timing1); + tqspi->spi_cs_timing2 = tegra_qspi_readl(tqspi, qspi_cs_timing2); + tqspi->def_command2_reg = tegra_qspi_readl(tqspi, qspi_command2); + + pm_runtime_put(&pdev->dev); + + ret = request_threaded_irq(tqspi->irq, null, + tegra_qspi_isr_thread, irqf_oneshot, + dev_name(&pdev->dev), tqspi); + if (ret < 0) { + dev_err(&pdev->dev, "failed to request irq#%u: %d ", tqspi->irq, ret); + goto exit_pm_disable; + } + + master->dev.of_node = pdev->dev.of_node; + ret = spi_register_master(master); + if (ret < 0) { + dev_err(&pdev->dev, "failed to register master: %d ", ret); + goto exit_free_irq; + } + + return 0; + +exit_free_irq: + free_irq(qspi_irq, tqspi); +exit_pm_disable: + pm_runtime_disable(&pdev->dev); + tegra_qspi_deinit_dma(tqspi); + return ret; +} + +static int tegra_qspi_remove(struct platform_device *pdev) +{ + struct spi_master *master = platform_get_drvdata(pdev); + struct tegra_qspi *tqspi = spi_master_get_devdata(master); + + spi_unregister_master(master); + free_irq(tqspi->irq, tqspi); + pm_runtime_disable(&pdev->dev); + tegra_qspi_deinit_dma(tqspi); + + return 0; +} + +static int __maybe_unused tegra_qspi_suspend(struct device *dev) +{ + struct spi_master *master = dev_get_drvdata(dev); + + return spi_master_suspend(master); +} + +static int __maybe_unused tegra_qspi_resume(struct device *dev) +{ + struct spi_master *master = dev_get_drvdata(dev); + struct tegra_qspi *tqspi = spi_master_get_devdata(master); + int ret; + + ret = pm_runtime_resume_and_get(dev); + if (ret < 0) { + dev_err(dev, "failed to get runtime pm: %d ", ret); + return ret; + } + + tegra_qspi_writel(tqspi, tqspi->command1_reg, qspi_command1); + tegra_qspi_writel(tqspi, tqspi->def_command2_reg, qspi_command2); + pm_runtime_put(dev); + + return spi_master_resume(master); +} + +static int __maybe_unused tegra_qspi_runtime_suspend(struct device *dev) +{ + struct spi_master *master = dev_get_drvdata(dev); + struct tegra_qspi *tqspi = spi_master_get_devdata(master); + + /* flush all write which are in ppsb queue by reading back */ + tegra_qspi_readl(tqspi, qspi_command1); + + clk_disable_unprepare(tqspi->clk); + + return 0; +} + +static int __maybe_unused tegra_qspi_runtime_resume(struct device *dev) +{ + struct spi_master *master = dev_get_drvdata(dev); + struct tegra_qspi *tqspi = spi_master_get_devdata(master); + int ret; + + ret = clk_prepare_enable(tqspi->clk); + if (ret < 0) + dev_err(tqspi->dev, "failed to enable clock: %d ", ret); + + return ret; +} + +static const struct dev_pm_ops tegra_qspi_pm_ops = { + set_runtime_pm_ops(tegra_qspi_runtime_suspend, tegra_qspi_runtime_resume, null) + set_system_sleep_pm_ops(tegra_qspi_suspend, tegra_qspi_resume) +}; + +static struct platform_driver tegra_qspi_driver = { + .driver = { + .name = "tegra-qspi", + .pm = &tegra_qspi_pm_ops, + .of_match_table = tegra_qspi_of_match, + }, + .probe = tegra_qspi_probe, + .remove = tegra_qspi_remove, +}; +module_platform_driver(tegra_qspi_driver); + +module_alias("platform:qspi-tegra"); +module_description("nvidia tegra qspi controller driver"); +module_author("sowjanya komatineni <skomatineni@nvidia.com>"); +module_license("gpl v2");
|
Serial Peripheral Interface (SPI)
|
921fc1838fb036f690b8ba52e6a6d3644b475cbb
|
sowjanya komatineni
|
drivers
|
spi
| |
spi: spi-mem: mark dummy transfers by setting dummy_data bit
|
this patch marks dummy transfer by setting dummy_data bit to 1.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add tegra quad spi driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['h', 'c']
| 2
| 3
| 0
|
--- diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c + xfers[xferpos].dummy_data = 1; diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h + * @dummy_data: indicates transfer is dummy bytes transfer. + unsigned dummy_data:1;
|
Serial Peripheral Interface (SPI)
|
98621ed011c57ba6e52e01a5982b221c9943b6d9
|
sowjanya komatineni
|
drivers
|
spi
|
spi
|
spi: tegra210-quad: add support for hardware dummy cycles transfer
|
tegra quad spi controller hardware supports sending dummy bytes based on programmed dummy clock cycles after the actual transfer bytes.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add tegra quad spi driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['c']
| 1
| 31
| 3
|
--- diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c +#define qspi_dummy_cycles_max 0xff + u8 dummy_cycles; + tegra_qspi_writel(tqspi, qspi_num_dummy_cycle(tqspi->dummy_cycles), qspi_misc_reg); + - struct spi_transfer *xfer; + struct spi_transfer *transfer; - list_for_each_entry(xfer, &msg->transfers, transfer_list) { + list_for_each_entry(transfer, &msg->transfers, transfer_list) { + struct spi_transfer *xfer = transfer; + u8 dummy_bytes = 0; + tqspi->dummy_cycles = 0; + /* + * tegra qspi hardware supports dummy bytes transfer after actual transfer + * bytes based on programmed dummy clock cycles in the qspi_misc register. + * so, check if the next transfer is dummy data transfer and program dummy + * clock cycles along with the current transfer and skip next transfer. + */ + if (!list_is_last(&xfer->transfer_list, &msg->transfers)) { + struct spi_transfer *next_xfer; + + next_xfer = list_next_entry(xfer, transfer_list); + if (next_xfer->dummy_data) { + u32 dummy_cycles = next_xfer->len * 8 / next_xfer->tx_nbits; + + if (dummy_cycles <= qspi_dummy_cycles_max) { + tqspi->dummy_cycles = dummy_cycles; + dummy_bytes = next_xfer->len; + transfer = next_xfer; + } + } + } + - msg->actual_length += xfer->len; + msg->actual_length += xfer->len + dummy_bytes;
|
Serial Peripheral Interface (SPI)
|
6a8a8b51703c69fa2d6adbbcbf731ce9b991c696
|
sowjanya komatineni
|
drivers
|
spi
| |
arm64: tegra: enable qspi on jetson nano
|
this patch enables qspi on jetson nano.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add tegra quad spi driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['dts', 'dtsi']
| 2
| 15
| 2
|
--- diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts + spi@70410000 { + status = "okay"; + + flash@0 { + compatible = "spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; + }; + diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi - clocks = <&tegra_car tegra210_clk_qspi>; - clock-names = "qspi"; + clocks = <&tegra_car tegra210_clk_qspi>, + <&tegra_car tegra210_clk_qspi_pm>; + clock-names = "qspi", "qspi_out";
|
Serial Peripheral Interface (SPI)
|
07910a79fc340881eb8e3ed9e47654574fa83d3f
|
sowjanya komatineni
|
arch
|
arm64
|
boot, dts, nvidia
|
arm64: tegra: add qspi nodes on tegra194
|
tegra194 has 2 qspi controllers.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add tegra quad spi driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['dtsi']
| 1
| 28
| 0
|
--- diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi + spi@3270000 { + compatible = "nvidia,tegra194-qspi"; + reg = <0x3270000 0x1000>; + interrupts = <gic_spi 35 irq_type_level_high>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp tegra194_clk_qspi0>, + <&bpmp tegra194_clk_qspi0_pm>; + clock-names = "qspi", "qspi_out"; + resets = <&bpmp tegra194_reset_qspi0>; + reset-names = "qspi"; + status = "disabled"; + }; + + spi@3300000 { + compatible = "nvidia,tegra194-qspi"; + reg = <0x3300000 0x1000>; + interrupts = <gic_spi 39 irq_type_level_high>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp tegra194_clk_qspi1>, + <&bpmp tegra194_clk_qspi1_pm>; + clock-names = "qspi", "qspi_out"; + resets = <&bpmp tegra194_reset_qspi1>; + reset-names = "qspi"; + status = "disabled"; + }; +
|
Serial Peripheral Interface (SPI)
|
96ded827a2e8da0ac74ea92d1eb5ebd9e22c2724
|
sowjanya komatineni
|
arch
|
arm64
|
boot, dts, nvidia
|
arm64: tegra: enable qspi on jetson xavier nx
|
this patch enables qspi on jetson xavier nx.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add tegra quad spi driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['dts']
| 1
| 12
| 0
|
--- diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dts --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dts + spi@3270000 { + status = "okay"; + + flash@0 { + compatible = "spi-nor"; + reg = <0>; + spi-max-frequency = <102000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + }; +
|
Serial Peripheral Interface (SPI)
|
ad338c2d69ecd45c39ff218cf219658affda9336
|
sowjanya komatineni
|
arch
|
arm64
|
boot, dts, nvidia
|
spi: remove sirf prima/atlas driver
|
the csr sirf prima2/atlas platforms are getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove sirf prima/atlas driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['txt', 'kconfig', 'c', 'makefile']
| 4
| 0
| 1,286
|
--- diff --git a/documentation/devicetree/bindings/spi/spi-sirf.txt b/documentation/devicetree/bindings/spi/spi-sirf.txt --- a/documentation/devicetree/bindings/spi/spi-sirf.txt +++ /dev/null -* csr sirfprimaii serial peripheral interface - -required properties: -- compatible : should be "sirf,prima2-spi", "sirf,prima2-usp" - or "sirf,atlas7-usp" -- reg : offset and length of the register set for the device -- interrupts : should contain spi interrupt -- resets: phandle to the reset controller asserting this device in - reset - see ../reset/reset.txt for details. -- dmas : must contain an entry for each entry in clock-names. - see ../dma/dma.txt for details. -- dma-names : must include the following entries: - - rx - - tx -- clocks : must contain an entry for each entry in clock-names. - see ../clocks/clock-bindings.txt for details. - -- #address-cells: number of cells required to define a chip select - address on the spi bus. should be set to 1. -- #size-cells: should be zero. - -optional properties: -- spi-max-frequency: specifies maximum spi clock frequency, - units - hz. definition as per - documentation/devicetree/bindings/spi/spi-bus.txt -- cs-gpios: should specify gpios used for chipselects. - -example: - -spi0: spi@b00d0000 { - compatible = "sirf,prima2-spi"; - reg = <0xb00d0000 0x10000>; - interrupts = <15>; - dmas = <&dmac1 9>, - <&dmac1 4>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clks 19>; - resets = <&rstc 26>; -}; diff --git a/drivers/spi/kconfig b/drivers/spi/kconfig --- a/drivers/spi/kconfig +++ b/drivers/spi/kconfig -config spi_sirf - tristate "csr sirfprimaii spi controller" - depends on sirf_dma - select spi_bitbang - help - spi driver for csr sirfprimaii socs - diff --git a/drivers/spi/makefile b/drivers/spi/makefile --- a/drivers/spi/makefile +++ b/drivers/spi/makefile -obj-$(config_spi_sirf) += spi-sirf.o diff --git a/drivers/spi/spi-sirf.c b/drivers/spi/spi-sirf.c --- a/drivers/spi/spi-sirf.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-or-later -/* - * spi bus driver for csr sirfprimaii - * - * copyright (c) 2011 cambridge silicon radio limited, a csr plc group company. - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/slab.h> -#include <linux/clk.h> -#include <linux/completion.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include <linux/of.h> -#include <linux/bitops.h> -#include <linux/err.h> -#include <linux/platform_device.h> -#include <linux/of_gpio.h> -#include <linux/spi/spi.h> -#include <linux/spi/spi_bitbang.h> -#include <linux/dmaengine.h> -#include <linux/dma-direction.h> -#include <linux/dma-mapping.h> -#include <linux/reset.h> - -#define driver_name "sirfsoc_spi" -/* spi ctrl register defines */ -#define sirfsoc_spi_slv_mode bit(16) -#define sirfsoc_spi_cmd_mode bit(17) -#define sirfsoc_spi_cs_io_out bit(18) -#define sirfsoc_spi_cs_io_mode bit(19) -#define sirfsoc_spi_clk_idle_stat bit(20) -#define sirfsoc_spi_cs_idle_stat bit(21) -#define sirfsoc_spi_tran_msb bit(22) -#define sirfsoc_spi_drv_pos_edge bit(23) -#define sirfsoc_spi_cs_hold_time bit(24) -#define sirfsoc_spi_clk_sample_mode bit(25) -#define sirfsoc_spi_tran_dat_format_8 (0 << 26) -#define sirfsoc_spi_tran_dat_format_12 (1 << 26) -#define sirfsoc_spi_tran_dat_format_16 (2 << 26) -#define sirfsoc_spi_tran_dat_format_32 (3 << 26) -#define sirfsoc_spi_cmd_byte_num(x) ((x & 3) << 28) -#define sirfsoc_spi_ena_auto_clr bit(30) -#define sirfsoc_spi_mul_dat_mode bit(31) - -/* interrupt enable */ -#define sirfsoc_spi_rx_done_int_en bit(0) -#define sirfsoc_spi_tx_done_int_en bit(1) -#define sirfsoc_spi_rx_oflow_int_en bit(2) -#define sirfsoc_spi_tx_uflow_int_en bit(3) -#define sirfsoc_spi_rx_io_dma_int_en bit(4) -#define sirfsoc_spi_tx_io_dma_int_en bit(5) -#define sirfsoc_spi_rxfifo_full_int_en bit(6) -#define sirfsoc_spi_txfifo_empty_int_en bit(7) -#define sirfsoc_spi_rxfifo_thd_int_en bit(8) -#define sirfsoc_spi_txfifo_thd_int_en bit(9) -#define sirfsoc_spi_frm_end_int_en bit(10) - -/* interrupt status */ -#define sirfsoc_spi_rx_done bit(0) -#define sirfsoc_spi_tx_done bit(1) -#define sirfsoc_spi_rx_oflow bit(2) -#define sirfsoc_spi_tx_uflow bit(3) -#define sirfsoc_spi_rx_io_dma bit(4) -#define sirfsoc_spi_rx_fifo_full bit(6) -#define sirfsoc_spi_txfifo_empty bit(7) -#define sirfsoc_spi_rxfifo_thd_reach bit(8) -#define sirfsoc_spi_txfifo_thd_reach bit(9) -#define sirfsoc_spi_frm_end bit(10) - -/* tx rx enable */ -#define sirfsoc_spi_rx_en bit(0) -#define sirfsoc_spi_tx_en bit(1) -#define sirfsoc_spi_cmd_tx_en bit(2) - -#define sirfsoc_spi_io_mode_sel bit(0) -#define sirfsoc_spi_rx_dma_flush bit(2) - -/* fifo ops */ -#define sirfsoc_spi_fifo_reset bit(0) -#define sirfsoc_spi_fifo_start bit(1) - -/* fifo ctrl */ -#define sirfsoc_spi_fifo_width_byte (0 << 0) -#define sirfsoc_spi_fifo_width_word (1 << 0) -#define sirfsoc_spi_fifo_width_dword (2 << 0) -/* usp related */ -#define sirfsoc_usp_sync_mode bit(0) -#define sirfsoc_usp_slv_mode bit(1) -#define sirfsoc_usp_lsb bit(4) -#define sirfsoc_usp_en bit(5) -#define sirfsoc_usp_rxd_falling_edge bit(6) -#define sirfsoc_usp_txd_falling_edge bit(7) -#define sirfsoc_usp_cs_high_valid bit(9) -#define sirfsoc_usp_sclk_idle_stat bit(11) -#define sirfsoc_usp_tfs_io_mode bit(14) -#define sirfsoc_usp_tfs_io_input bit(19) - -#define sirfsoc_usp_rxd_delay_len_mask 0xff -#define sirfsoc_usp_txd_delay_len_mask 0xff -#define sirfsoc_usp_rxd_delay_offset 0 -#define sirfsoc_usp_txd_delay_offset 8 -#define sirfsoc_usp_rxd_delay_len 1 -#define sirfsoc_usp_txd_delay_len 1 -#define sirfsoc_usp_clk_divisor_offset 21 -#define sirfsoc_usp_clk_divisor_mask 0x3ff -#define sirfsoc_usp_clk_10_11_mask 0x3 -#define sirfsoc_usp_clk_10_11_offset 30 -#define sirfsoc_usp_clk_12_15_mask 0xf -#define sirfsoc_usp_clk_12_15_offset 24 - -#define sirfsoc_usp_tx_data_offset 0 -#define sirfsoc_usp_tx_sync_offset 8 -#define sirfsoc_usp_tx_frame_offset 16 -#define sirfsoc_usp_tx_shifter_offset 24 - -#define sirfsoc_usp_tx_data_mask 0xff -#define sirfsoc_usp_tx_sync_mask 0xff -#define sirfsoc_usp_tx_frame_mask 0xff -#define sirfsoc_usp_tx_shifter_mask 0x1f - -#define sirfsoc_usp_rx_data_offset 0 -#define sirfsoc_usp_rx_frame_offset 8 -#define sirfsoc_usp_rx_shifter_offset 16 - -#define sirfsoc_usp_rx_data_mask 0xff -#define sirfsoc_usp_rx_frame_mask 0xff -#define sirfsoc_usp_rx_shifter_mask 0x1f -#define sirfsoc_usp_cs_high_value bit(1) - -#define sirfsoc_spi_fifo_sc_offset 0 -#define sirfsoc_spi_fifo_lc_offset 10 -#define sirfsoc_spi_fifo_hc_offset 20 - -#define sirfsoc_spi_fifo_full_mask(s) (1 << ((s)->fifo_full_offset)) -#define sirfsoc_spi_fifo_empty_mask(s) (1 << ((s)->fifo_full_offset + 1)) -#define sirfsoc_spi_fifo_thd_mask(s) ((s)->fifo_size - 1) -#define sirfsoc_spi_fifo_thd_offset 2 -#define sirfsoc_spi_fifo_level_chk_mask(s, val) \ - ((val) & (s)->fifo_level_chk_mask) - -enum sirf_spi_type { - sirf_real_spi, - sirf_usp_spi_p2, - sirf_usp_spi_a7, -}; - -/* - * only if the rx/tx buffer and transfer size are 4-bytes aligned, we use dma - * due to the limitation of dma controller - */ - -#define aligned(x) (!((u32)x & 0x3)) -#define is_dma_valid(x) (x && aligned(x->tx_buf) && aligned(x->rx_buf) && \ - aligned(x->len) && (x->len < 2 * page_size)) - -#define sirfsoc_max_cmd_bytes 4 -#define sirfsoc_spi_default_frq 1000000 - -struct sirf_spi_register { - /*spi and usp-spi common*/ - u32 tx_rx_en; - u32 int_en; - u32 int_st; - u32 tx_dma_io_ctrl; - u32 tx_dma_io_len; - u32 txfifo_ctrl; - u32 txfifo_level_chk; - u32 txfifo_op; - u32 txfifo_st; - u32 txfifo_data; - u32 rx_dma_io_ctrl; - u32 rx_dma_io_len; - u32 rxfifo_ctrl; - u32 rxfifo_level_chk; - u32 rxfifo_op; - u32 rxfifo_st; - u32 rxfifo_data; - /*spi self*/ - u32 spi_ctrl; - u32 spi_cmd; - u32 spi_dummy_delay_ctrl; - /*usp-spi self*/ - u32 usp_mode1; - u32 usp_mode2; - u32 usp_tx_frame_ctrl; - u32 usp_rx_frame_ctrl; - u32 usp_pin_io_data; - u32 usp_risc_dsp_mode; - u32 usp_async_param_reg; - u32 usp_irda_x_mode_div; - u32 usp_sm_cfg; - u32 usp_int_en_clr; -}; - -static const struct sirf_spi_register real_spi_register = { - .tx_rx_en = 0x8, - .int_en = 0xc, - .int_st = 0x10, - .tx_dma_io_ctrl = 0x100, - .tx_dma_io_len = 0x104, - .txfifo_ctrl = 0x108, - .txfifo_level_chk = 0x10c, - .txfifo_op = 0x110, - .txfifo_st = 0x114, - .txfifo_data = 0x118, - .rx_dma_io_ctrl = 0x120, - .rx_dma_io_len = 0x124, - .rxfifo_ctrl = 0x128, - .rxfifo_level_chk = 0x12c, - .rxfifo_op = 0x130, - .rxfifo_st = 0x134, - .rxfifo_data = 0x138, - .spi_ctrl = 0x0, - .spi_cmd = 0x4, - .spi_dummy_delay_ctrl = 0x144, -}; - -static const struct sirf_spi_register usp_spi_register = { - .tx_rx_en = 0x10, - .int_en = 0x14, - .int_st = 0x18, - .tx_dma_io_ctrl = 0x100, - .tx_dma_io_len = 0x104, - .txfifo_ctrl = 0x108, - .txfifo_level_chk = 0x10c, - .txfifo_op = 0x110, - .txfifo_st = 0x114, - .txfifo_data = 0x118, - .rx_dma_io_ctrl = 0x120, - .rx_dma_io_len = 0x124, - .rxfifo_ctrl = 0x128, - .rxfifo_level_chk = 0x12c, - .rxfifo_op = 0x130, - .rxfifo_st = 0x134, - .rxfifo_data = 0x138, - .usp_mode1 = 0x0, - .usp_mode2 = 0x4, - .usp_tx_frame_ctrl = 0x8, - .usp_rx_frame_ctrl = 0xc, - .usp_pin_io_data = 0x1c, - .usp_risc_dsp_mode = 0x20, - .usp_async_param_reg = 0x24, - .usp_irda_x_mode_div = 0x28, - .usp_sm_cfg = 0x2c, - .usp_int_en_clr = 0x140, -}; - -struct sirfsoc_spi { - struct spi_bitbang bitbang; - struct completion rx_done; - struct completion tx_done; - - void __iomem *base; - u32 ctrl_freq; /* spi controller clock speed */ - struct clk *clk; - - /* rx & tx bufs from the spi_transfer */ - const void *tx; - void *rx; - - /* place received word into rx buffer */ - void (*rx_word) (struct sirfsoc_spi *); - /* get word from tx buffer for sending */ - void (*tx_word) (struct sirfsoc_spi *); - - /* number of words left to be tranmitted/received */ - unsigned int left_tx_word; - unsigned int left_rx_word; - - /* rx & tx dma channels */ - struct dma_chan *rx_chan; - struct dma_chan *tx_chan; - dma_addr_t src_start; - dma_addr_t dst_start; - int word_width; /* in bytes */ - - /* - * if tx size is not more than 4 and rx size is null, use - * command model - */ - bool tx_by_cmd; - bool hw_cs; - enum sirf_spi_type type; - const struct sirf_spi_register *regs; - unsigned int fifo_size; - /* fifo empty offset is (fifo full offset + 1)*/ - unsigned int fifo_full_offset; - /* fifo_level_chk_mask is (fifo_size/4 - 1) */ - unsigned int fifo_level_chk_mask; - unsigned int dat_max_frm_len; -}; - -struct sirf_spi_comp_data { - const struct sirf_spi_register *regs; - enum sirf_spi_type type; - unsigned int dat_max_frm_len; - unsigned int fifo_size; - void (*hwinit)(struct sirfsoc_spi *sspi); -}; - -static void sirfsoc_usp_hwinit(struct sirfsoc_spi *sspi) -{ - /* reset usp and let usp can operate */ - writel(readl(sspi->base + sspi->regs->usp_mode1) & - ~sirfsoc_usp_en, sspi->base + sspi->regs->usp_mode1); - writel(readl(sspi->base + sspi->regs->usp_mode1) | - sirfsoc_usp_en, sspi->base + sspi->regs->usp_mode1); -} - -static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi) -{ - u32 data; - u8 *rx = sspi->rx; - - data = readl(sspi->base + sspi->regs->rxfifo_data); - - if (rx) { - *rx++ = (u8) data; - sspi->rx = rx; - } - - sspi->left_rx_word--; -} - -static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi) -{ - u32 data = 0; - const u8 *tx = sspi->tx; - - if (tx) { - data = *tx++; - sspi->tx = tx; - } - writel(data, sspi->base + sspi->regs->txfifo_data); - sspi->left_tx_word--; -} - -static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi) -{ - u32 data; - u16 *rx = sspi->rx; - - data = readl(sspi->base + sspi->regs->rxfifo_data); - - if (rx) { - *rx++ = (u16) data; - sspi->rx = rx; - } - - sspi->left_rx_word--; -} - -static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi) -{ - u32 data = 0; - const u16 *tx = sspi->tx; - - if (tx) { - data = *tx++; - sspi->tx = tx; - } - - writel(data, sspi->base + sspi->regs->txfifo_data); - sspi->left_tx_word--; -} - -static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi) -{ - u32 data; - u32 *rx = sspi->rx; - - data = readl(sspi->base + sspi->regs->rxfifo_data); - - if (rx) { - *rx++ = (u32) data; - sspi->rx = rx; - } - - sspi->left_rx_word--; - -} - -static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi) -{ - u32 data = 0; - const u32 *tx = sspi->tx; - - if (tx) { - data = *tx++; - sspi->tx = tx; - } - - writel(data, sspi->base + sspi->regs->txfifo_data); - sspi->left_tx_word--; -} - -static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id) -{ - struct sirfsoc_spi *sspi = dev_id; - u32 spi_stat; - - spi_stat = readl(sspi->base + sspi->regs->int_st); - if (sspi->tx_by_cmd && sspi->type == sirf_real_spi - && (spi_stat & sirfsoc_spi_frm_end)) { - complete(&sspi->tx_done); - writel(0x0, sspi->base + sspi->regs->int_en); - writel(readl(sspi->base + sspi->regs->int_st), - sspi->base + sspi->regs->int_st); - return irq_handled; - } - /* error conditions */ - if (spi_stat & sirfsoc_spi_rx_oflow || - spi_stat & sirfsoc_spi_tx_uflow) { - complete(&sspi->tx_done); - complete(&sspi->rx_done); - switch (sspi->type) { - case sirf_real_spi: - case sirf_usp_spi_p2: - writel(0x0, sspi->base + sspi->regs->int_en); - break; - case sirf_usp_spi_a7: - writel(~0ul, sspi->base + sspi->regs->usp_int_en_clr); - break; - } - writel(readl(sspi->base + sspi->regs->int_st), - sspi->base + sspi->regs->int_st); - return irq_handled; - } - if (spi_stat & sirfsoc_spi_txfifo_empty) - complete(&sspi->tx_done); - while (!(readl(sspi->base + sspi->regs->int_st) & - sirfsoc_spi_rx_io_dma)) - cpu_relax(); - complete(&sspi->rx_done); - switch (sspi->type) { - case sirf_real_spi: - case sirf_usp_spi_p2: - writel(0x0, sspi->base + sspi->regs->int_en); - break; - case sirf_usp_spi_a7: - writel(~0ul, sspi->base + sspi->regs->usp_int_en_clr); - break; - } - writel(readl(sspi->base + sspi->regs->int_st), - sspi->base + sspi->regs->int_st); - - return irq_handled; -} - -static void spi_sirfsoc_dma_fini_callback(void *data) -{ - struct completion *dma_complete = data; - - complete(dma_complete); -} - -static void spi_sirfsoc_cmd_transfer(struct spi_device *spi, - struct spi_transfer *t) -{ - struct sirfsoc_spi *sspi; - int timeout = t->len * 10; - u32 cmd; - - sspi = spi_master_get_devdata(spi->master); - writel(sirfsoc_spi_fifo_reset, sspi->base + sspi->regs->txfifo_op); - writel(sirfsoc_spi_fifo_start, sspi->base + sspi->regs->txfifo_op); - memcpy(&cmd, sspi->tx, t->len); - if (sspi->word_width == 1 && !(spi->mode & spi_lsb_first)) - cmd = cpu_to_be32(cmd) >> - ((sirfsoc_max_cmd_bytes - t->len) * 8); - if (sspi->word_width == 2 && t->len == 4 && - (!(spi->mode & spi_lsb_first))) - cmd = ((cmd & 0xffff) << 16) | (cmd >> 16); - writel(cmd, sspi->base + sspi->regs->spi_cmd); - writel(sirfsoc_spi_frm_end_int_en, - sspi->base + sspi->regs->int_en); - writel(sirfsoc_spi_cmd_tx_en, - sspi->base + sspi->regs->tx_rx_en); - if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) { - dev_err(&spi->dev, "cmd transfer timeout "); - return; - } - sspi->left_rx_word -= t->len; -} - -static void spi_sirfsoc_dma_transfer(struct spi_device *spi, - struct spi_transfer *t) -{ - struct sirfsoc_spi *sspi; - struct dma_async_tx_descriptor *rx_desc, *tx_desc; - int timeout = t->len * 10; - - sspi = spi_master_get_devdata(spi->master); - writel(sirfsoc_spi_fifo_reset, sspi->base + sspi->regs->rxfifo_op); - writel(sirfsoc_spi_fifo_reset, sspi->base + sspi->regs->txfifo_op); - switch (sspi->type) { - case sirf_real_spi: - writel(sirfsoc_spi_fifo_start, - sspi->base + sspi->regs->rxfifo_op); - writel(sirfsoc_spi_fifo_start, - sspi->base + sspi->regs->txfifo_op); - writel(0, sspi->base + sspi->regs->int_en); - break; - case sirf_usp_spi_p2: - writel(0x0, sspi->base + sspi->regs->rxfifo_op); - writel(0x0, sspi->base + sspi->regs->txfifo_op); - writel(0, sspi->base + sspi->regs->int_en); - break; - case sirf_usp_spi_a7: - writel(0x0, sspi->base + sspi->regs->rxfifo_op); - writel(0x0, sspi->base + sspi->regs->txfifo_op); - writel(~0ul, sspi->base + sspi->regs->usp_int_en_clr); - break; - } - writel(readl(sspi->base + sspi->regs->int_st), - sspi->base + sspi->regs->int_st); - if (sspi->left_tx_word < sspi->dat_max_frm_len) { - switch (sspi->type) { - case sirf_real_spi: - writel(readl(sspi->base + sspi->regs->spi_ctrl) | - sirfsoc_spi_ena_auto_clr | - sirfsoc_spi_mul_dat_mode, - sspi->base + sspi->regs->spi_ctrl); - writel(sspi->left_tx_word - 1, - sspi->base + sspi->regs->tx_dma_io_len); - writel(sspi->left_tx_word - 1, - sspi->base + sspi->regs->rx_dma_io_len); - break; - case sirf_usp_spi_p2: - case sirf_usp_spi_a7: - /*usp simulate spi, tx/rx_dma_io_len indicates bytes*/ - writel(sspi->left_tx_word * sspi->word_width, - sspi->base + sspi->regs->tx_dma_io_len); - writel(sspi->left_tx_word * sspi->word_width, - sspi->base + sspi->regs->rx_dma_io_len); - break; - } - } else { - if (sspi->type == sirf_real_spi) - writel(readl(sspi->base + sspi->regs->spi_ctrl), - sspi->base + sspi->regs->spi_ctrl); - writel(0, sspi->base + sspi->regs->tx_dma_io_len); - writel(0, sspi->base + sspi->regs->rx_dma_io_len); - } - sspi->dst_start = dma_map_single(&spi->dev, sspi->rx, t->len, - (t->tx_buf != t->rx_buf) ? - dma_from_device : dma_bidirectional); - rx_desc = dmaengine_prep_slave_single(sspi->rx_chan, - sspi->dst_start, t->len, dma_dev_to_mem, - dma_prep_interrupt | dma_ctrl_ack); - rx_desc->callback = spi_sirfsoc_dma_fini_callback; - rx_desc->callback_param = &sspi->rx_done; - - sspi->src_start = dma_map_single(&spi->dev, (void *)sspi->tx, t->len, - (t->tx_buf != t->rx_buf) ? - dma_to_device : dma_bidirectional); - tx_desc = dmaengine_prep_slave_single(sspi->tx_chan, - sspi->src_start, t->len, dma_mem_to_dev, - dma_prep_interrupt | dma_ctrl_ack); - tx_desc->callback = spi_sirfsoc_dma_fini_callback; - tx_desc->callback_param = &sspi->tx_done; - - dmaengine_submit(tx_desc); - dmaengine_submit(rx_desc); - dma_async_issue_pending(sspi->tx_chan); - dma_async_issue_pending(sspi->rx_chan); - writel(sirfsoc_spi_rx_en | sirfsoc_spi_tx_en, - sspi->base + sspi->regs->tx_rx_en); - if (sspi->type == sirf_usp_spi_p2 || - sspi->type == sirf_usp_spi_a7) { - writel(sirfsoc_spi_fifo_start, - sspi->base + sspi->regs->rxfifo_op); - writel(sirfsoc_spi_fifo_start, - sspi->base + sspi->regs->txfifo_op); - } - if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) { - dev_err(&spi->dev, "transfer timeout "); - dmaengine_terminate_all(sspi->rx_chan); - } else - sspi->left_rx_word = 0; - /* - * we only wait tx-done event if transferring by dma. for pio, - * we get rx data by writing tx data, so if rx is done, tx has - * done earlier - */ - if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) { - dev_err(&spi->dev, "transfer timeout "); - if (sspi->type == sirf_usp_spi_p2 || - sspi->type == sirf_usp_spi_a7) - writel(0, sspi->base + sspi->regs->tx_rx_en); - dmaengine_terminate_all(sspi->tx_chan); - } - dma_unmap_single(&spi->dev, sspi->src_start, t->len, dma_to_device); - dma_unmap_single(&spi->dev, sspi->dst_start, t->len, dma_from_device); - /* tx, rx fifo stop */ - writel(0, sspi->base + sspi->regs->rxfifo_op); - writel(0, sspi->base + sspi->regs->txfifo_op); - if (sspi->left_tx_word >= sspi->dat_max_frm_len) - writel(0, sspi->base + sspi->regs->tx_rx_en); - if (sspi->type == sirf_usp_spi_p2 || - sspi->type == sirf_usp_spi_a7) - writel(0, sspi->base + sspi->regs->tx_rx_en); -} - -static void spi_sirfsoc_pio_transfer(struct spi_device *spi, - struct spi_transfer *t) -{ - struct sirfsoc_spi *sspi; - int timeout = t->len * 10; - unsigned int data_units; - - sspi = spi_master_get_devdata(spi->master); - do { - writel(sirfsoc_spi_fifo_reset, - sspi->base + sspi->regs->rxfifo_op); - writel(sirfsoc_spi_fifo_reset, - sspi->base + sspi->regs->txfifo_op); - switch (sspi->type) { - case sirf_usp_spi_p2: - writel(0x0, sspi->base + sspi->regs->rxfifo_op); - writel(0x0, sspi->base + sspi->regs->txfifo_op); - writel(0, sspi->base + sspi->regs->int_en); - writel(readl(sspi->base + sspi->regs->int_st), - sspi->base + sspi->regs->int_st); - writel(min((sspi->left_tx_word * sspi->word_width), - sspi->fifo_size), - sspi->base + sspi->regs->tx_dma_io_len); - writel(min((sspi->left_rx_word * sspi->word_width), - sspi->fifo_size), - sspi->base + sspi->regs->rx_dma_io_len); - break; - case sirf_usp_spi_a7: - writel(0x0, sspi->base + sspi->regs->rxfifo_op); - writel(0x0, sspi->base + sspi->regs->txfifo_op); - writel(~0ul, sspi->base + sspi->regs->usp_int_en_clr); - writel(readl(sspi->base + sspi->regs->int_st), - sspi->base + sspi->regs->int_st); - writel(min((sspi->left_tx_word * sspi->word_width), - sspi->fifo_size), - sspi->base + sspi->regs->tx_dma_io_len); - writel(min((sspi->left_rx_word * sspi->word_width), - sspi->fifo_size), - sspi->base + sspi->regs->rx_dma_io_len); - break; - case sirf_real_spi: - writel(sirfsoc_spi_fifo_start, - sspi->base + sspi->regs->rxfifo_op); - writel(sirfsoc_spi_fifo_start, - sspi->base + sspi->regs->txfifo_op); - writel(0, sspi->base + sspi->regs->int_en); - writel(readl(sspi->base + sspi->regs->int_st), - sspi->base + sspi->regs->int_st); - writel(readl(sspi->base + sspi->regs->spi_ctrl) | - sirfsoc_spi_mul_dat_mode | - sirfsoc_spi_ena_auto_clr, - sspi->base + sspi->regs->spi_ctrl); - data_units = sspi->fifo_size / sspi->word_width; - writel(min(sspi->left_tx_word, data_units) - 1, - sspi->base + sspi->regs->tx_dma_io_len); - writel(min(sspi->left_rx_word, data_units) - 1, - sspi->base + sspi->regs->rx_dma_io_len); - break; - } - while (!((readl(sspi->base + sspi->regs->txfifo_st) - & sirfsoc_spi_fifo_full_mask(sspi))) && - sspi->left_tx_word) - sspi->tx_word(sspi); - writel(sirfsoc_spi_txfifo_empty_int_en | - sirfsoc_spi_tx_uflow_int_en | - sirfsoc_spi_rx_oflow_int_en | - sirfsoc_spi_rx_io_dma_int_en, - sspi->base + sspi->regs->int_en); - writel(sirfsoc_spi_rx_en | sirfsoc_spi_tx_en, - sspi->base + sspi->regs->tx_rx_en); - if (sspi->type == sirf_usp_spi_p2 || - sspi->type == sirf_usp_spi_a7) { - writel(sirfsoc_spi_fifo_start, - sspi->base + sspi->regs->rxfifo_op); - writel(sirfsoc_spi_fifo_start, - sspi->base + sspi->regs->txfifo_op); - } - if (!wait_for_completion_timeout(&sspi->tx_done, timeout) || - !wait_for_completion_timeout(&sspi->rx_done, timeout)) { - dev_err(&spi->dev, "transfer timeout "); - if (sspi->type == sirf_usp_spi_p2 || - sspi->type == sirf_usp_spi_a7) - writel(0, sspi->base + sspi->regs->tx_rx_en); - break; - } - while (!((readl(sspi->base + sspi->regs->rxfifo_st) - & sirfsoc_spi_fifo_empty_mask(sspi))) && - sspi->left_rx_word) - sspi->rx_word(sspi); - if (sspi->type == sirf_usp_spi_p2 || - sspi->type == sirf_usp_spi_a7) - writel(0, sspi->base + sspi->regs->tx_rx_en); - writel(0, sspi->base + sspi->regs->rxfifo_op); - writel(0, sspi->base + sspi->regs->txfifo_op); - } while (sspi->left_tx_word != 0 || sspi->left_rx_word != 0); -} - -static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t) -{ - struct sirfsoc_spi *sspi; - - sspi = spi_master_get_devdata(spi->master); - sspi->tx = t->tx_buf; - sspi->rx = t->rx_buf; - sspi->left_tx_word = sspi->left_rx_word = t->len / sspi->word_width; - reinit_completion(&sspi->rx_done); - reinit_completion(&sspi->tx_done); - /* - * in the transfer, if transfer data using command register with rx_buf - * null, just fill command data into command register and wait for its - * completion. - */ - if (sspi->type == sirf_real_spi && sspi->tx_by_cmd) - spi_sirfsoc_cmd_transfer(spi, t); - else if (is_dma_valid(t)) - spi_sirfsoc_dma_transfer(spi, t); - else - spi_sirfsoc_pio_transfer(spi, t); - - return t->len - sspi->left_rx_word * sspi->word_width; -} - -static void spi_sirfsoc_chipselect(struct spi_device *spi, int value) -{ - struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master); - - if (sspi->hw_cs) { - u32 regval; - - switch (sspi->type) { - case sirf_real_spi: - regval = readl(sspi->base + sspi->regs->spi_ctrl); - switch (value) { - case bitbang_cs_active: - if (spi->mode & spi_cs_high) - regval |= sirfsoc_spi_cs_io_out; - else - regval &= ~sirfsoc_spi_cs_io_out; - break; - case bitbang_cs_inactive: - if (spi->mode & spi_cs_high) - regval &= ~sirfsoc_spi_cs_io_out; - else - regval |= sirfsoc_spi_cs_io_out; - break; - } - writel(regval, sspi->base + sspi->regs->spi_ctrl); - break; - case sirf_usp_spi_p2: - case sirf_usp_spi_a7: - regval = readl(sspi->base + - sspi->regs->usp_pin_io_data); - switch (value) { - case bitbang_cs_active: - if (spi->mode & spi_cs_high) - regval |= sirfsoc_usp_cs_high_value; - else - regval &= ~(sirfsoc_usp_cs_high_value); - break; - case bitbang_cs_inactive: - if (spi->mode & spi_cs_high) - regval &= ~(sirfsoc_usp_cs_high_value); - else - regval |= sirfsoc_usp_cs_high_value; - break; - } - writel(regval, - sspi->base + sspi->regs->usp_pin_io_data); - break; - } - } else { - switch (value) { - case bitbang_cs_active: - gpio_direction_output(spi->cs_gpio, - spi->mode & spi_cs_high ? 1 : 0); - break; - case bitbang_cs_inactive: - gpio_direction_output(spi->cs_gpio, - spi->mode & spi_cs_high ? 0 : 1); - break; - } - } -} - -static int spi_sirfsoc_config_mode(struct spi_device *spi) -{ - struct sirfsoc_spi *sspi; - u32 regval, usp_mode1; - - sspi = spi_master_get_devdata(spi->master); - regval = readl(sspi->base + sspi->regs->spi_ctrl); - usp_mode1 = readl(sspi->base + sspi->regs->usp_mode1); - if (!(spi->mode & spi_cs_high)) { - regval |= sirfsoc_spi_cs_idle_stat; - usp_mode1 &= ~sirfsoc_usp_cs_high_valid; - } else { - regval &= ~sirfsoc_spi_cs_idle_stat; - usp_mode1 |= sirfsoc_usp_cs_high_valid; - } - if (!(spi->mode & spi_lsb_first)) { - regval |= sirfsoc_spi_tran_msb; - usp_mode1 &= ~sirfsoc_usp_lsb; - } else { - regval &= ~sirfsoc_spi_tran_msb; - usp_mode1 |= sirfsoc_usp_lsb; - } - if (spi->mode & spi_cpol) { - regval |= sirfsoc_spi_clk_idle_stat; - usp_mode1 |= sirfsoc_usp_sclk_idle_stat; - } else { - regval &= ~sirfsoc_spi_clk_idle_stat; - usp_mode1 &= ~sirfsoc_usp_sclk_idle_stat; - } - /* - * data should be driven at least 1/2 cycle before the fetch edge - * to make sure that data gets stable at the fetch edge. - */ - if (((spi->mode & spi_cpol) && (spi->mode & spi_cpha)) || - (!(spi->mode & spi_cpol) && !(spi->mode & spi_cpha))) { - regval &= ~sirfsoc_spi_drv_pos_edge; - usp_mode1 |= (sirfsoc_usp_txd_falling_edge | - sirfsoc_usp_rxd_falling_edge); - } else { - regval |= sirfsoc_spi_drv_pos_edge; - usp_mode1 &= ~(sirfsoc_usp_rxd_falling_edge | - sirfsoc_usp_txd_falling_edge); - } - writel((sirfsoc_spi_fifo_level_chk_mask(sspi, sspi->fifo_size - 2) << - sirfsoc_spi_fifo_sc_offset) | - (sirfsoc_spi_fifo_level_chk_mask(sspi, sspi->fifo_size / 2) << - sirfsoc_spi_fifo_lc_offset) | - (sirfsoc_spi_fifo_level_chk_mask(sspi, 2) << - sirfsoc_spi_fifo_hc_offset), - sspi->base + sspi->regs->txfifo_level_chk); - writel((sirfsoc_spi_fifo_level_chk_mask(sspi, 2) << - sirfsoc_spi_fifo_sc_offset) | - (sirfsoc_spi_fifo_level_chk_mask(sspi, sspi->fifo_size / 2) << - sirfsoc_spi_fifo_lc_offset) | - (sirfsoc_spi_fifo_level_chk_mask(sspi, sspi->fifo_size - 2) << - sirfsoc_spi_fifo_hc_offset), - sspi->base + sspi->regs->rxfifo_level_chk); - /* - * it should never set to hardware cs mode because in hardware cs mode, - * cs signal can't controlled by driver. - */ - switch (sspi->type) { - case sirf_real_spi: - regval |= sirfsoc_spi_cs_io_mode; - writel(regval, sspi->base + sspi->regs->spi_ctrl); - break; - case sirf_usp_spi_p2: - case sirf_usp_spi_a7: - usp_mode1 |= sirfsoc_usp_sync_mode; - usp_mode1 |= sirfsoc_usp_tfs_io_mode; - usp_mode1 &= ~sirfsoc_usp_tfs_io_input; - writel(usp_mode1, sspi->base + sspi->regs->usp_mode1); - break; - } - - return 0; -} - -static int -spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t) -{ - struct sirfsoc_spi *sspi; - u8 bits_per_word = 0; - int hz = 0; - u32 regval, txfifo_ctrl, rxfifo_ctrl, tx_frm_ctl, rx_frm_ctl, usp_mode2; - - sspi = spi_master_get_devdata(spi->master); - - bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word; - hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz; - - usp_mode2 = regval = (sspi->ctrl_freq / (2 * hz)) - 1; - if (regval > 0xffff || regval < 0) { - dev_err(&spi->dev, "speed %d not supported ", hz); - return -einval; - } - switch (bits_per_word) { - case 8: - regval |= sirfsoc_spi_tran_dat_format_8; - sspi->rx_word = spi_sirfsoc_rx_word_u8; - sspi->tx_word = spi_sirfsoc_tx_word_u8; - break; - case 12: - case 16: - regval |= (bits_per_word == 12) ? - sirfsoc_spi_tran_dat_format_12 : - sirfsoc_spi_tran_dat_format_16; - sspi->rx_word = spi_sirfsoc_rx_word_u16; - sspi->tx_word = spi_sirfsoc_tx_word_u16; - break; - case 32: - regval |= sirfsoc_spi_tran_dat_format_32; - sspi->rx_word = spi_sirfsoc_rx_word_u32; - sspi->tx_word = spi_sirfsoc_tx_word_u32; - break; - default: - dev_err(&spi->dev, "bpw %d not supported ", bits_per_word); - return -einval; - } - sspi->word_width = div_round_up(bits_per_word, 8); - txfifo_ctrl = (((sspi->fifo_size / 2) & - sirfsoc_spi_fifo_thd_mask(sspi)) - << sirfsoc_spi_fifo_thd_offset) | - (sspi->word_width >> 1); - rxfifo_ctrl = (((sspi->fifo_size / 2) & - sirfsoc_spi_fifo_thd_mask(sspi)) - << sirfsoc_spi_fifo_thd_offset) | - (sspi->word_width >> 1); - writel(txfifo_ctrl, sspi->base + sspi->regs->txfifo_ctrl); - writel(rxfifo_ctrl, sspi->base + sspi->regs->rxfifo_ctrl); - if (sspi->type == sirf_usp_spi_p2 || - sspi->type == sirf_usp_spi_a7) { - tx_frm_ctl = 0; - tx_frm_ctl |= ((bits_per_word - 1) & sirfsoc_usp_tx_data_mask) - << sirfsoc_usp_tx_data_offset; - tx_frm_ctl |= ((bits_per_word + 1 + sirfsoc_usp_txd_delay_len - - 1) & sirfsoc_usp_tx_sync_mask) << - sirfsoc_usp_tx_sync_offset; - tx_frm_ctl |= ((bits_per_word + 1 + sirfsoc_usp_txd_delay_len - + 2 - 1) & sirfsoc_usp_tx_frame_mask) << - sirfsoc_usp_tx_frame_offset; - tx_frm_ctl |= ((bits_per_word - 1) & - sirfsoc_usp_tx_shifter_mask) << - sirfsoc_usp_tx_shifter_offset; - rx_frm_ctl = 0; - rx_frm_ctl |= ((bits_per_word - 1) & sirfsoc_usp_rx_data_mask) - << sirfsoc_usp_rx_data_offset; - rx_frm_ctl |= ((bits_per_word + 1 + sirfsoc_usp_rxd_delay_len - + 2 - 1) & sirfsoc_usp_rx_frame_mask) << - sirfsoc_usp_rx_frame_offset; - rx_frm_ctl |= ((bits_per_word - 1) - & sirfsoc_usp_rx_shifter_mask) << - sirfsoc_usp_rx_shifter_offset; - writel(tx_frm_ctl | (((usp_mode2 >> 10) & - sirfsoc_usp_clk_10_11_mask) << - sirfsoc_usp_clk_10_11_offset), - sspi->base + sspi->regs->usp_tx_frame_ctrl); - writel(rx_frm_ctl | (((usp_mode2 >> 12) & - sirfsoc_usp_clk_12_15_mask) << - sirfsoc_usp_clk_12_15_offset), - sspi->base + sspi->regs->usp_rx_frame_ctrl); - writel(readl(sspi->base + sspi->regs->usp_mode2) | - ((usp_mode2 & sirfsoc_usp_clk_divisor_mask) << - sirfsoc_usp_clk_divisor_offset) | - (sirfsoc_usp_rxd_delay_len << - sirfsoc_usp_rxd_delay_offset) | - (sirfsoc_usp_txd_delay_len << - sirfsoc_usp_txd_delay_offset), - sspi->base + sspi->regs->usp_mode2); - } - if (sspi->type == sirf_real_spi) - writel(regval, sspi->base + sspi->regs->spi_ctrl); - spi_sirfsoc_config_mode(spi); - if (sspi->type == sirf_real_spi) { - if (t && t->tx_buf && !t->rx_buf && - (t->len <= sirfsoc_max_cmd_bytes)) { - sspi->tx_by_cmd = true; - writel(readl(sspi->base + sspi->regs->spi_ctrl) | - (sirfsoc_spi_cmd_byte_num((t->len - 1)) | - sirfsoc_spi_cmd_mode), - sspi->base + sspi->regs->spi_ctrl); - } else { - sspi->tx_by_cmd = false; - writel(readl(sspi->base + sspi->regs->spi_ctrl) & - ~sirfsoc_spi_cmd_mode, - sspi->base + sspi->regs->spi_ctrl); - } - } - if (is_dma_valid(t)) { - /* enable dma mode for rx, tx */ - writel(0, sspi->base + sspi->regs->tx_dma_io_ctrl); - writel(sirfsoc_spi_rx_dma_flush, - sspi->base + sspi->regs->rx_dma_io_ctrl); - } else { - /* enable io mode for rx, tx */ - writel(sirfsoc_spi_io_mode_sel, - sspi->base + sspi->regs->tx_dma_io_ctrl); - writel(sirfsoc_spi_io_mode_sel, - sspi->base + sspi->regs->rx_dma_io_ctrl); - } - return 0; -} - -static int spi_sirfsoc_setup(struct spi_device *spi) -{ - struct sirfsoc_spi *sspi; - int ret = 0; - - sspi = spi_master_get_devdata(spi->master); - if (spi->cs_gpio == -enoent) - sspi->hw_cs = true; - else { - sspi->hw_cs = false; - if (!spi_get_ctldata(spi)) { - void *cs = kmalloc(sizeof(int), gfp_kernel); - if (!cs) { - ret = -enomem; - goto exit; - } - ret = gpio_is_valid(spi->cs_gpio); - if (!ret) { - dev_err(&spi->dev, "no valid gpio "); - ret = -enoent; - goto exit; - } - ret = gpio_request(spi->cs_gpio, driver_name); - if (ret) { - dev_err(&spi->dev, "failed to request gpio "); - goto exit; - } - spi_set_ctldata(spi, cs); - } - } - spi_sirfsoc_config_mode(spi); - spi_sirfsoc_chipselect(spi, bitbang_cs_inactive); -exit: - return ret; -} - -static void spi_sirfsoc_cleanup(struct spi_device *spi) -{ - if (spi_get_ctldata(spi)) { - gpio_free(spi->cs_gpio); - kfree(spi_get_ctldata(spi)); - } -} - -static const struct sirf_spi_comp_data sirf_real_spi = { - .regs = &real_spi_register, - .type = sirf_real_spi, - .dat_max_frm_len = 64 * 1024, - .fifo_size = 256, -}; - -static const struct sirf_spi_comp_data sirf_usp_spi_p2 = { - .regs = &usp_spi_register, - .type = sirf_usp_spi_p2, - .dat_max_frm_len = 1024 * 1024, - .fifo_size = 128, - .hwinit = sirfsoc_usp_hwinit, -}; - -static const struct sirf_spi_comp_data sirf_usp_spi_a7 = { - .regs = &usp_spi_register, - .type = sirf_usp_spi_a7, - .dat_max_frm_len = 1024 * 1024, - .fifo_size = 512, - .hwinit = sirfsoc_usp_hwinit, -}; - -static const struct of_device_id spi_sirfsoc_of_match[] = { - { .compatible = "sirf,prima2-spi", .data = &sirf_real_spi}, - { .compatible = "sirf,prima2-usp-spi", .data = &sirf_usp_spi_p2}, - { .compatible = "sirf,atlas7-usp-spi", .data = &sirf_usp_spi_a7}, - {} -}; -module_device_table(of, spi_sirfsoc_of_match); - -static int spi_sirfsoc_probe(struct platform_device *pdev) -{ - struct sirfsoc_spi *sspi; - struct spi_master *master; - const struct sirf_spi_comp_data *spi_comp_data; - int irq; - int ret; - const struct of_device_id *match; - - ret = device_reset(&pdev->dev); - if (ret) { - dev_err(&pdev->dev, "spi reset failed! "); - return ret; - } - - master = spi_alloc_master(&pdev->dev, sizeof(*sspi)); - if (!master) { - dev_err(&pdev->dev, "unable to allocate spi master "); - return -enomem; - } - match = of_match_node(spi_sirfsoc_of_match, pdev->dev.of_node); - platform_set_drvdata(pdev, master); - sspi = spi_master_get_devdata(master); - sspi->fifo_full_offset = ilog2(sspi->fifo_size); - spi_comp_data = match->data; - sspi->regs = spi_comp_data->regs; - sspi->type = spi_comp_data->type; - sspi->fifo_level_chk_mask = (sspi->fifo_size / 4) - 1; - sspi->dat_max_frm_len = spi_comp_data->dat_max_frm_len; - sspi->fifo_size = spi_comp_data->fifo_size; - sspi->base = devm_platform_ioremap_resource(pdev, 0); - if (is_err(sspi->base)) { - ret = ptr_err(sspi->base); - goto free_master; - } - irq = platform_get_irq(pdev, 0); - if (irq < 0) { - ret = -enxio; - goto free_master; - } - ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0, - driver_name, sspi); - if (ret) - goto free_master; - - sspi->bitbang.master = master; - sspi->bitbang.chipselect = spi_sirfsoc_chipselect; - sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer; - sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer; - sspi->bitbang.master->setup = spi_sirfsoc_setup; - sspi->bitbang.master->cleanup = spi_sirfsoc_cleanup; - master->bus_num = pdev->id; - master->mode_bits = spi_cpol | spi_cpha | spi_lsb_first | spi_cs_high; - master->bits_per_word_mask = spi_bpw_mask(8) | spi_bpw_mask(12) | - spi_bpw_mask(16) | spi_bpw_mask(32); - master->max_speed_hz = sirfsoc_spi_default_frq; - master->flags = spi_master_must_rx | spi_master_must_tx; - sspi->bitbang.master->dev.of_node = pdev->dev.of_node; - - /* request dma channels */ - sspi->rx_chan = dma_request_chan(&pdev->dev, "rx"); - if (is_err(sspi->rx_chan)) { - dev_err(&pdev->dev, "can not allocate rx dma channel "); - ret = ptr_err(sspi->rx_chan); - goto free_master; - } - sspi->tx_chan = dma_request_chan(&pdev->dev, "tx"); - if (is_err(sspi->tx_chan)) { - dev_err(&pdev->dev, "can not allocate tx dma channel "); - ret = ptr_err(sspi->tx_chan); - goto free_rx_dma; - } - - sspi->clk = clk_get(&pdev->dev, null); - if (is_err(sspi->clk)) { - ret = ptr_err(sspi->clk); - goto free_tx_dma; - } - clk_prepare_enable(sspi->clk); - if (spi_comp_data->hwinit) - spi_comp_data->hwinit(sspi); - sspi->ctrl_freq = clk_get_rate(sspi->clk); - - init_completion(&sspi->rx_done); - init_completion(&sspi->tx_done); - - ret = spi_bitbang_start(&sspi->bitbang); - if (ret) - goto free_clk; - dev_info(&pdev->dev, "registered, bus number = %d ", master->bus_num); - - return 0; -free_clk: - clk_disable_unprepare(sspi->clk); - clk_put(sspi->clk); -free_tx_dma: - dma_release_channel(sspi->tx_chan); -free_rx_dma: - dma_release_channel(sspi->rx_chan); -free_master: - spi_master_put(master); - - return ret; -} - -static int spi_sirfsoc_remove(struct platform_device *pdev) -{ - struct spi_master *master; - struct sirfsoc_spi *sspi; - - master = platform_get_drvdata(pdev); - sspi = spi_master_get_devdata(master); - spi_bitbang_stop(&sspi->bitbang); - clk_disable_unprepare(sspi->clk); - clk_put(sspi->clk); - dma_release_channel(sspi->rx_chan); - dma_release_channel(sspi->tx_chan); - spi_master_put(master); - return 0; -} - -#ifdef config_pm_sleep -static int spi_sirfsoc_suspend(struct device *dev) -{ - struct spi_master *master = dev_get_drvdata(dev); - struct sirfsoc_spi *sspi = spi_master_get_devdata(master); - int ret; - - ret = spi_master_suspend(master); - if (ret) - return ret; - - clk_disable(sspi->clk); - return 0; -} - -static int spi_sirfsoc_resume(struct device *dev) -{ - struct spi_master *master = dev_get_drvdata(dev); - struct sirfsoc_spi *sspi = spi_master_get_devdata(master); - - clk_enable(sspi->clk); - writel(sirfsoc_spi_fifo_reset, sspi->base + sspi->regs->txfifo_op); - writel(sirfsoc_spi_fifo_reset, sspi->base + sspi->regs->rxfifo_op); - writel(sirfsoc_spi_fifo_start, sspi->base + sspi->regs->txfifo_op); - writel(sirfsoc_spi_fifo_start, sspi->base + sspi->regs->rxfifo_op); - return 0; -} -#endif - -static simple_dev_pm_ops(spi_sirfsoc_pm_ops, spi_sirfsoc_suspend, - spi_sirfsoc_resume); - -static struct platform_driver spi_sirfsoc_driver = { - .driver = { - .name = driver_name, - .pm = &spi_sirfsoc_pm_ops, - .of_match_table = spi_sirfsoc_of_match, - }, - .probe = spi_sirfsoc_probe, - .remove = spi_sirfsoc_remove, -}; -module_platform_driver(spi_sirfsoc_driver); -module_description("sirf soc spi master driver"); -module_author("zhiwu song <zhiwu.song@csr.com>"); -module_author("barry song <baohua.song@csr.com>"); -module_author("qipan li <qipan.li@csr.com>"); -module_license("gpl v2");
|
Serial Peripheral Interface (SPI)
|
181997b4940880b6ebc317b34dca38a17f107318
|
arnd bergmann barry song baohua kernel org
|
drivers
|
spi
|
bindings, spi
|
spi: txx9: remove driver
|
cpu support for tx49xx is getting removed, so remove support spi driver for it.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['txx9']
|
['kconfig', 'c', 'makefile']
| 3
| 0
| 484
|
--- diff --git a/drivers/spi/kconfig b/drivers/spi/kconfig --- a/drivers/spi/kconfig +++ b/drivers/spi/kconfig -config spi_txx9 - tristate "toshiba txx9 spi controller" - depends on gpiolib && (cpu_tx49xx || compile_test) - help - spi driver for toshiba txx9 mips socs - diff --git a/drivers/spi/makefile b/drivers/spi/makefile --- a/drivers/spi/makefile +++ b/drivers/spi/makefile -obj-$(config_spi_txx9) += spi-txx9.o diff --git a/drivers/spi/spi-txx9.c b/drivers/spi/spi-txx9.c --- a/drivers/spi/spi-txx9.c +++ /dev/null -/* - * txx9 spi controller driver. - * - * based on linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c - * copyright (c) 2000-2001 toshiba corporation - * - * 2003-2005 (c) montavista software, inc. this file is licensed under the - * terms of the gnu general public license version 2. this program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * support for tx4938 in 2.6 - manish lachwani (mlachwani@mvista.com) - * - * convert to generic spi framework - atsushi nemoto (anemo@mba.ocn.ne.jp) - */ -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> -#include <linux/sched.h> -#include <linux/spinlock.h> -#include <linux/workqueue.h> -#include <linux/spi/spi.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/module.h> -#include <linux/gpio/machine.h> -#include <linux/gpio/consumer.h> - - -#define spi_fifo_size 4 -#define spi_max_divider 0xff /* max. value for spcr1.ser */ -#define spi_min_divider 1 /* min. value for spcr1.ser */ - -#define txx9_spmcr 0x00 -#define txx9_spcr0 0x04 -#define txx9_spcr1 0x08 -#define txx9_spfs 0x0c -#define txx9_spsr 0x14 -#define txx9_spdr 0x18 - -/* spmcr : spi master control */ -#define txx9_spmcr_opmode 0xc0 -#define txx9_spmcr_config 0x40 -#define txx9_spmcr_active 0x80 -#define txx9_spmcr_spstp 0x02 -#define txx9_spmcr_bclr 0x01 - -/* spcr0 : spi control 0 */ -#define txx9_spcr0_txifl_mask 0xc000 -#define txx9_spcr0_rxifl_mask 0x3000 -#define txx9_spcr0_sidie 0x0800 -#define txx9_spcr0_soeie 0x0400 -#define txx9_spcr0_rbsie 0x0200 -#define txx9_spcr0_tbsie 0x0100 -#define txx9_spcr0_ifspse 0x0010 -#define txx9_spcr0_sbos 0x0004 -#define txx9_spcr0_spha 0x0002 -#define txx9_spcr0_spol 0x0001 - -/* spsr : spi status */ -#define txx9_spsr_tbsi 0x8000 -#define txx9_spsr_rbsi 0x4000 -#define txx9_spsr_tbs_mask 0x3800 -#define txx9_spsr_rbs_mask 0x0700 -#define txx9_spsr_spoe 0x0080 -#define txx9_spsr_ifsd 0x0008 -#define txx9_spsr_sidle 0x0004 -#define txx9_spsr_strdy 0x0002 -#define txx9_spsr_srrdy 0x0001 - - -struct txx9spi { - struct work_struct work; - spinlock_t lock; /* protect 'queue' */ - struct list_head queue; - wait_queue_head_t waitq; - void __iomem *membase; - int baseclk; - struct clk *clk; - struct gpio_desc *last_chipselect; - int last_chipselect_val; -}; - -static u32 txx9spi_rd(struct txx9spi *c, int reg) -{ - return __raw_readl(c->membase + reg); -} -static void txx9spi_wr(struct txx9spi *c, u32 val, int reg) -{ - __raw_writel(val, c->membase + reg); -} - -static void txx9spi_cs_func(struct spi_device *spi, struct txx9spi *c, - int on, unsigned int cs_delay) -{ - /* - * the gpio descriptor will track polarity inversion inside - * gpiolib. - */ - if (on) { - /* deselect the chip with cs_change hint in last transfer */ - if (c->last_chipselect) - gpiod_set_value(c->last_chipselect, - !c->last_chipselect_val); - c->last_chipselect = spi->cs_gpiod; - c->last_chipselect_val = on; - } else { - c->last_chipselect = null; - ndelay(cs_delay); /* cs hold time */ - } - gpiod_set_value(spi->cs_gpiod, on); - ndelay(cs_delay); /* cs setup time / cs recovery time */ -} - -static int txx9spi_setup(struct spi_device *spi) -{ - struct txx9spi *c = spi_master_get_devdata(spi->master); - - if (!spi->max_speed_hz) - return -einval; - - /* deselect chip */ - spin_lock(&c->lock); - txx9spi_cs_func(spi, c, 0, (nsec_per_sec / 2) / spi->max_speed_hz); - spin_unlock(&c->lock); - - return 0; -} - -static irqreturn_t txx9spi_interrupt(int irq, void *dev_id) -{ - struct txx9spi *c = dev_id; - - /* disable rx intr */ - txx9spi_wr(c, txx9spi_rd(c, txx9_spcr0) & ~txx9_spcr0_rbsie, - txx9_spcr0); - wake_up(&c->waitq); - return irq_handled; -} - -static void txx9spi_work_one(struct txx9spi *c, struct spi_message *m) -{ - struct spi_device *spi = m->spi; - struct spi_transfer *t; - unsigned int cs_delay; - unsigned int cs_change = 1; - int status = 0; - u32 mcr; - u32 prev_speed_hz = 0; - u8 prev_bits_per_word = 0; - - /* cs setup/hold/recovery time in nsec */ - cs_delay = 100 + (nsec_per_sec / 2) / spi->max_speed_hz; - - mcr = txx9spi_rd(c, txx9_spmcr); - if (unlikely((mcr & txx9_spmcr_opmode) == txx9_spmcr_active)) { - dev_err(&spi->dev, "bad mode. "); - status = -eio; - goto exit; - } - mcr &= ~(txx9_spmcr_opmode | txx9_spmcr_spstp | txx9_spmcr_bclr); - - /* enter config mode */ - txx9spi_wr(c, mcr | txx9_spmcr_config | txx9_spmcr_bclr, txx9_spmcr); - txx9spi_wr(c, txx9_spcr0_sbos - | ((spi->mode & spi_cpol) ? txx9_spcr0_spol : 0) - | ((spi->mode & spi_cpha) ? txx9_spcr0_spha : 0) - | 0x08, - txx9_spcr0); - - list_for_each_entry(t, &m->transfers, transfer_list) { - const void *txbuf = t->tx_buf; - void *rxbuf = t->rx_buf; - u32 data; - unsigned int len = t->len; - unsigned int wsize; - u32 speed_hz = t->speed_hz; - u8 bits_per_word = t->bits_per_word; - - wsize = bits_per_word >> 3; /* in bytes */ - - if (prev_speed_hz != speed_hz - || prev_bits_per_word != bits_per_word) { - int n = div_round_up(c->baseclk, speed_hz) - 1; - - n = clamp(n, spi_min_divider, spi_max_divider); - /* enter config mode */ - txx9spi_wr(c, mcr | txx9_spmcr_config | txx9_spmcr_bclr, - txx9_spmcr); - txx9spi_wr(c, (n << 8) | bits_per_word, txx9_spcr1); - /* enter active mode */ - txx9spi_wr(c, mcr | txx9_spmcr_active, txx9_spmcr); - - prev_speed_hz = speed_hz; - prev_bits_per_word = bits_per_word; - } - - if (cs_change) - txx9spi_cs_func(spi, c, 1, cs_delay); - cs_change = t->cs_change; - while (len) { - unsigned int count = spi_fifo_size; - int i; - u32 cr0; - - if (len < count * wsize) - count = len / wsize; - /* now tx must be idle... */ - while (!(txx9spi_rd(c, txx9_spsr) & txx9_spsr_sidle)) - cpu_relax(); - cr0 = txx9spi_rd(c, txx9_spcr0); - cr0 &= ~txx9_spcr0_rxifl_mask; - cr0 |= (count - 1) << 12; - /* enable rx intr */ - cr0 |= txx9_spcr0_rbsie; - txx9spi_wr(c, cr0, txx9_spcr0); - /* send */ - for (i = 0; i < count; i++) { - if (txbuf) { - data = (wsize == 1) - ? *(const u8 *)txbuf - : *(const u16 *)txbuf; - txx9spi_wr(c, data, txx9_spdr); - txbuf += wsize; - } else - txx9spi_wr(c, 0, txx9_spdr); - } - /* wait all rx data */ - wait_event(c->waitq, - txx9spi_rd(c, txx9_spsr) & txx9_spsr_rbsi); - /* receive */ - for (i = 0; i < count; i++) { - data = txx9spi_rd(c, txx9_spdr); - if (rxbuf) { - if (wsize == 1) - *(u8 *)rxbuf = data; - else - *(u16 *)rxbuf = data; - rxbuf += wsize; - } - } - len -= count * wsize; - } - m->actual_length += t->len; - spi_transfer_delay_exec(t); - - if (!cs_change) - continue; - if (t->transfer_list.next == &m->transfers) - break; - /* sometimes a short mid-message deselect of the chip - * may be needed to terminate a mode or command - */ - txx9spi_cs_func(spi, c, 0, cs_delay); - } - -exit: - m->status = status; - if (m->complete) - m->complete(m->context); - - /* normally deactivate chipselect ... unless no error and - * cs_change has hinted that the next message will probably - * be for this chip too. - */ - if (!(status == 0 && cs_change)) - txx9spi_cs_func(spi, c, 0, cs_delay); - - /* enter config mode */ - txx9spi_wr(c, mcr | txx9_spmcr_config | txx9_spmcr_bclr, txx9_spmcr); -} - -static void txx9spi_work(struct work_struct *work) -{ - struct txx9spi *c = container_of(work, struct txx9spi, work); - unsigned long flags; - - spin_lock_irqsave(&c->lock, flags); - while (!list_empty(&c->queue)) { - struct spi_message *m; - - m = container_of(c->queue.next, struct spi_message, queue); - list_del_init(&m->queue); - spin_unlock_irqrestore(&c->lock, flags); - - txx9spi_work_one(c, m); - - spin_lock_irqsave(&c->lock, flags); - } - spin_unlock_irqrestore(&c->lock, flags); -} - -static int txx9spi_transfer(struct spi_device *spi, struct spi_message *m) -{ - struct spi_master *master = spi->master; - struct txx9spi *c = spi_master_get_devdata(master); - struct spi_transfer *t; - unsigned long flags; - - m->actual_length = 0; - - /* check each transfer's parameters */ - list_for_each_entry(t, &m->transfers, transfer_list) { - if (!t->tx_buf && !t->rx_buf && t->len) - return -einval; - } - - spin_lock_irqsave(&c->lock, flags); - list_add_tail(&m->queue, &c->queue); - schedule_work(&c->work); - spin_unlock_irqrestore(&c->lock, flags); - - return 0; -} - -/* - * chip select uses gpio only, further the driver is using the chip select - * numer (from the device tree "reg" property, and this can only come from - * device tree since this i mips and there is no way to pass platform data) as - * the gpio number. as the platform has only one gpio controller (the txx9 gpio - * chip) it is thus using the chip select number as an offset into that chip. - * this chip has a maximum of 16 gpios 0..15 and this is what all platforms - * register. - * - * we modernized this behaviour by explicitly converting that offset to an - * offset on the gpio chip using a gpio descriptor machine table of the same - * size as the txx9 gpio chip with a 1-to-1 mapping of chip select to gpio - * offset. - * - * this is admittedly a hack, but it is countering the hack of using "reg" to - * contain a gpio offset when it should be using "cs-gpios" as the spi bindings - * state. - */ -static struct gpiod_lookup_table txx9spi_cs_gpio_table = { - .dev_id = "spi0", - .table = { - gpio_lookup_idx("txx9", 0, "cs", 0, gpio_active_low), - gpio_lookup_idx("txx9", 1, "cs", 1, gpio_active_low), - gpio_lookup_idx("txx9", 2, "cs", 2, gpio_active_low), - gpio_lookup_idx("txx9", 3, "cs", 3, gpio_active_low), - gpio_lookup_idx("txx9", 4, "cs", 4, gpio_active_low), - gpio_lookup_idx("txx9", 5, "cs", 5, gpio_active_low), - gpio_lookup_idx("txx9", 6, "cs", 6, gpio_active_low), - gpio_lookup_idx("txx9", 7, "cs", 7, gpio_active_low), - gpio_lookup_idx("txx9", 8, "cs", 8, gpio_active_low), - gpio_lookup_idx("txx9", 9, "cs", 9, gpio_active_low), - gpio_lookup_idx("txx9", 10, "cs", 10, gpio_active_low), - gpio_lookup_idx("txx9", 11, "cs", 11, gpio_active_low), - gpio_lookup_idx("txx9", 12, "cs", 12, gpio_active_low), - gpio_lookup_idx("txx9", 13, "cs", 13, gpio_active_low), - gpio_lookup_idx("txx9", 14, "cs", 14, gpio_active_low), - gpio_lookup_idx("txx9", 15, "cs", 15, gpio_active_low), - { }, - }, -}; - -static int txx9spi_probe(struct platform_device *dev) -{ - struct spi_master *master; - struct txx9spi *c; - struct resource *res; - int ret = -enodev; - u32 mcr; - int irq; - - master = spi_alloc_master(&dev->dev, sizeof(*c)); - if (!master) - return ret; - c = spi_master_get_devdata(master); - platform_set_drvdata(dev, master); - - init_work(&c->work, txx9spi_work); - spin_lock_init(&c->lock); - init_list_head(&c->queue); - init_waitqueue_head(&c->waitq); - - c->clk = devm_clk_get(&dev->dev, "spi-baseclk"); - if (is_err(c->clk)) { - ret = ptr_err(c->clk); - c->clk = null; - goto exit; - } - ret = clk_prepare_enable(c->clk); - if (ret) { - c->clk = null; - goto exit; - } - c->baseclk = clk_get_rate(c->clk); - master->min_speed_hz = div_round_up(c->baseclk, spi_max_divider + 1); - master->max_speed_hz = c->baseclk / (spi_min_divider + 1); - - res = platform_get_resource(dev, ioresource_mem, 0); - c->membase = devm_ioremap_resource(&dev->dev, res); - if (is_err(c->membase)) - goto exit_busy; - - /* enter config mode */ - mcr = txx9spi_rd(c, txx9_spmcr); - mcr &= ~(txx9_spmcr_opmode | txx9_spmcr_spstp | txx9_spmcr_bclr); - txx9spi_wr(c, mcr | txx9_spmcr_config | txx9_spmcr_bclr, txx9_spmcr); - - irq = platform_get_irq(dev, 0); - if (irq < 0) - goto exit_busy; - ret = devm_request_irq(&dev->dev, irq, txx9spi_interrupt, 0, - "spi_txx9", c); - if (ret) - goto exit; - - c->last_chipselect = null; - - dev_info(&dev->dev, "at %#llx, irq %d, %dmhz ", - (unsigned long long)res->start, irq, - (c->baseclk + 500000) / 1000000); - - gpiod_add_lookup_table(&txx9spi_cs_gpio_table); - - /* the spi->mode bits understood by this driver: */ - master->mode_bits = spi_cs_high | spi_cpol | spi_cpha; - - master->bus_num = dev->id; - master->setup = txx9spi_setup; - master->transfer = txx9spi_transfer; - master->num_chipselect = (u16)uint_max; /* any gpio numbers */ - master->bits_per_word_mask = spi_bpw_mask(8) | spi_bpw_mask(16); - master->use_gpio_descriptors = true; - - ret = devm_spi_register_master(&dev->dev, master); - if (ret) - goto exit; - return 0; -exit_busy: - ret = -ebusy; -exit: - clk_disable_unprepare(c->clk); - spi_master_put(master); - return ret; -} - -static int txx9spi_remove(struct platform_device *dev) -{ - struct spi_master *master = platform_get_drvdata(dev); - struct txx9spi *c = spi_master_get_devdata(master); - - flush_work(&c->work); - clk_disable_unprepare(c->clk); - return 0; -} - -/* work with hotplug and coldplug */ -module_alias("platform:spi_txx9"); - -static struct platform_driver txx9spi_driver = { - .probe = txx9spi_probe, - .remove = txx9spi_remove, - .driver = { - .name = "spi_txx9", - }, -}; - -static int __init txx9spi_init(void) -{ - return platform_driver_register(&txx9spi_driver); -} -subsys_initcall(txx9spi_init); - -static void __exit txx9spi_exit(void) -{ - platform_driver_unregister(&txx9spi_driver); -} -module_exit(txx9spi_exit); - -module_description("txx9 spi driver"); -module_license("gpl");
|
Serial Peripheral Interface (SPI)
|
74523a5dae0c96d6503fe72da66ee37fd23eb8f5
|
thomas bogendoerfer
|
drivers
|
spi
| |
spi: drop unused efm32 bus driver
|
support for this machine was just removed, so drop the now unused spi bus driver, too.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
drop unused efm32 bus driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['h', 'kconfig', 'c', 'makefile']
| 4
| 0
| 485
|
--- diff --git a/drivers/spi/kconfig b/drivers/spi/kconfig --- a/drivers/spi/kconfig +++ b/drivers/spi/kconfig -config spi_efm32 - tristate "efm32 spi controller" - depends on of && arm && (arch_efm32 || compile_test) - select spi_bitbang - help - driver for the spi controller found on energy micro's efm32 socs. - diff --git a/drivers/spi/makefile b/drivers/spi/makefile --- a/drivers/spi/makefile +++ b/drivers/spi/makefile -obj-$(config_spi_efm32) += spi-efm32.o diff --git a/drivers/spi/spi-efm32.c b/drivers/spi/spi-efm32.c --- a/drivers/spi/spi-efm32.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * copyright (c) 2012-2013 uwe kleine-koenig for pengutronix - */ -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/spi/spi.h> -#include <linux/spi/spi_bitbang.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/module.h> -#include <linux/platform_data/efm32-spi.h> -#include <linux/of.h> - -#define driver_name "efm32-spi" - -#define mask_val(mask, val) ((val << __ffs(mask)) & mask) - -#define reg_ctrl 0x00 -#define reg_ctrl_sync 0x0001 -#define reg_ctrl_clkpol 0x0100 -#define reg_ctrl_clkpha 0x0200 -#define reg_ctrl_msbf 0x0400 -#define reg_ctrl_txbil 0x1000 - -#define reg_frame 0x04 -#define reg_frame_databits__mask 0x000f -#define reg_frame_databits(n) ((n) - 3) - -#define reg_cmd 0x0c -#define reg_cmd_rxen 0x0001 -#define reg_cmd_rxdis 0x0002 -#define reg_cmd_txen 0x0004 -#define reg_cmd_txdis 0x0008 -#define reg_cmd_masteren 0x0010 - -#define reg_status 0x10 -#define reg_status_txens 0x0002 -#define reg_status_txc 0x0020 -#define reg_status_txbl 0x0040 -#define reg_status_rxdatav 0x0080 - -#define reg_clkdiv 0x14 - -#define reg_rxdatax 0x18 -#define reg_rxdatax_rxdata__mask 0x01ff -#define reg_rxdatax_perr 0x4000 -#define reg_rxdatax_ferr 0x8000 - -#define reg_txdata 0x34 - -#define reg_if 0x40 -#define reg_if_txbl 0x0002 -#define reg_if_rxdatav 0x0004 - -#define reg_ifs 0x44 -#define reg_ifc 0x48 -#define reg_ien 0x4c - -#define reg_route 0x54 -#define reg_route_rxpen 0x0001 -#define reg_route_txpen 0x0002 -#define reg_route_clkpen 0x0008 -#define reg_route_location__mask 0x0700 -#define reg_route_location(n) mask_val(reg_route_location__mask, (n)) - -struct efm32_spi_ddata { - struct spi_bitbang bitbang; - - spinlock_t lock; - - struct clk *clk; - void __iomem *base; - unsigned int rxirq, txirq; - struct efm32_spi_pdata pdata; - - /* irq data */ - struct completion done; - const u8 *tx_buf; - u8 *rx_buf; - unsigned tx_len, rx_len; -}; - -#define ddata_to_dev(ddata) (&(ddata->bitbang.master->dev)) -#define efm32_spi_vdbg(ddata, format, arg...) \ - dev_vdbg(ddata_to_dev(ddata), format, ##arg) - -static void efm32_spi_write32(struct efm32_spi_ddata *ddata, - u32 value, unsigned offset) -{ - writel_relaxed(value, ddata->base + offset); -} - -static u32 efm32_spi_read32(struct efm32_spi_ddata *ddata, unsigned offset) -{ - return readl_relaxed(ddata->base + offset); -} - -static int efm32_spi_setup_transfer(struct spi_device *spi, - struct spi_transfer *t) -{ - struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master); - - unsigned bpw = t->bits_per_word ?: spi->bits_per_word; - unsigned speed = t->speed_hz ?: spi->max_speed_hz; - unsigned long clkfreq = clk_get_rate(ddata->clk); - u32 clkdiv; - - efm32_spi_write32(ddata, reg_ctrl_sync | reg_ctrl_msbf | - (spi->mode & spi_cpha ? reg_ctrl_clkpha : 0) | - (spi->mode & spi_cpol ? reg_ctrl_clkpol : 0), reg_ctrl); - - efm32_spi_write32(ddata, - reg_frame_databits(bpw), reg_frame); - - if (2 * speed >= clkfreq) - clkdiv = 0; - else - clkdiv = 64 * (div_round_up(2 * clkfreq, speed) - 4); - - if (clkdiv > (1u << 21)) - return -einval; - - efm32_spi_write32(ddata, clkdiv, reg_clkdiv); - efm32_spi_write32(ddata, reg_cmd_masteren, reg_cmd); - efm32_spi_write32(ddata, reg_cmd_rxen | reg_cmd_txen, reg_cmd); - - return 0; -} - -static void efm32_spi_tx_u8(struct efm32_spi_ddata *ddata) -{ - u8 val = 0; - - if (ddata->tx_buf) { - val = *ddata->tx_buf; - ddata->tx_buf++; - } - - ddata->tx_len--; - efm32_spi_write32(ddata, val, reg_txdata); - efm32_spi_vdbg(ddata, "%s: tx 0x%x ", __func__, val); -} - -static void efm32_spi_rx_u8(struct efm32_spi_ddata *ddata) -{ - u32 rxdata = efm32_spi_read32(ddata, reg_rxdatax); - efm32_spi_vdbg(ddata, "%s: rx 0x%x ", __func__, rxdata); - - if (ddata->rx_buf) { - *ddata->rx_buf = rxdata; - ddata->rx_buf++; - } - - ddata->rx_len--; -} - -static void efm32_spi_filltx(struct efm32_spi_ddata *ddata) -{ - while (ddata->tx_len && - ddata->tx_len + 2 > ddata->rx_len && - efm32_spi_read32(ddata, reg_status) & reg_status_txbl) { - efm32_spi_tx_u8(ddata); - } -} - -static int efm32_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) -{ - struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master); - int ret = -ebusy; - - spin_lock_irq(&ddata->lock); - - if (ddata->tx_buf || ddata->rx_buf) - goto out_unlock; - - ddata->tx_buf = t->tx_buf; - ddata->rx_buf = t->rx_buf; - ddata->tx_len = ddata->rx_len = - t->len * div_round_up(t->bits_per_word, 8); - - efm32_spi_filltx(ddata); - - reinit_completion(&ddata->done); - - efm32_spi_write32(ddata, reg_if_txbl | reg_if_rxdatav, reg_ien); - - spin_unlock_irq(&ddata->lock); - - wait_for_completion(&ddata->done); - - spin_lock_irq(&ddata->lock); - - ret = t->len - max(ddata->tx_len, ddata->rx_len); - - efm32_spi_write32(ddata, 0, reg_ien); - ddata->tx_buf = ddata->rx_buf = null; - -out_unlock: - spin_unlock_irq(&ddata->lock); - - return ret; -} - -static irqreturn_t efm32_spi_rxirq(int irq, void *data) -{ - struct efm32_spi_ddata *ddata = data; - irqreturn_t ret = irq_none; - - spin_lock(&ddata->lock); - - while (ddata->rx_len > 0 && - efm32_spi_read32(ddata, reg_status) & - reg_status_rxdatav) { - efm32_spi_rx_u8(ddata); - - ret = irq_handled; - } - - if (!ddata->rx_len) { - u32 ien = efm32_spi_read32(ddata, reg_ien); - - ien &= ~reg_if_rxdatav; - - efm32_spi_write32(ddata, ien, reg_ien); - - complete(&ddata->done); - } - - spin_unlock(&ddata->lock); - - return ret; -} - -static irqreturn_t efm32_spi_txirq(int irq, void *data) -{ - struct efm32_spi_ddata *ddata = data; - - efm32_spi_vdbg(ddata, - "%s: txlen = %u, rxlen = %u, if=0x%08x, stat=0x%08x ", - __func__, ddata->tx_len, ddata->rx_len, - efm32_spi_read32(ddata, reg_if), - efm32_spi_read32(ddata, reg_status)); - - spin_lock(&ddata->lock); - - efm32_spi_filltx(ddata); - - efm32_spi_vdbg(ddata, "%s: txlen = %u, rxlen = %u ", - __func__, ddata->tx_len, ddata->rx_len); - - if (!ddata->tx_len) { - u32 ien = efm32_spi_read32(ddata, reg_ien); - - ien &= ~reg_if_txbl; - - efm32_spi_write32(ddata, ien, reg_ien); - efm32_spi_vdbg(ddata, "disable txbl "); - } - - spin_unlock(&ddata->lock); - - return irq_handled; -} - -static u32 efm32_spi_get_configured_location(struct efm32_spi_ddata *ddata) -{ - u32 reg = efm32_spi_read32(ddata, reg_route); - - return (reg & reg_route_location__mask) >> __ffs(reg_route_location__mask); -} - -static void efm32_spi_probe_dt(struct platform_device *pdev, - struct spi_master *master, struct efm32_spi_ddata *ddata) -{ - struct device_node *np = pdev->dev.of_node; - u32 location; - int ret; - - ret = of_property_read_u32(np, "energymicro,location", &location); - - if (ret) - /* fall back to wrongly namespaced property */ - ret = of_property_read_u32(np, "efm32,location", &location); - - if (ret) - /* fall back to old and (wrongly) generic property "location" */ - ret = of_property_read_u32(np, "location", &location); - - if (!ret) { - dev_dbg(&pdev->dev, "using location %u ", location); - } else { - /* default to location configured in hardware */ - location = efm32_spi_get_configured_location(ddata); - - dev_info(&pdev->dev, "fall back to location %u ", location); - } - - ddata->pdata.location = location; -} - -static int efm32_spi_probe(struct platform_device *pdev) -{ - struct efm32_spi_ddata *ddata; - struct resource *res; - int ret; - struct spi_master *master; - struct device_node *np = pdev->dev.of_node; - - if (!np) - return -einval; - - master = spi_alloc_master(&pdev->dev, sizeof(*ddata)); - if (!master) { - dev_dbg(&pdev->dev, - "failed to allocate spi master controller "); - return -enomem; - } - platform_set_drvdata(pdev, master); - - master->dev.of_node = pdev->dev.of_node; - - master->mode_bits = spi_cpol | spi_cpha | spi_cs_high; - master->bits_per_word_mask = spi_bpw_range_mask(4, 16); - master->use_gpio_descriptors = true; - - ddata = spi_master_get_devdata(master); - - ddata->bitbang.master = master; - ddata->bitbang.setup_transfer = efm32_spi_setup_transfer; - ddata->bitbang.txrx_bufs = efm32_spi_txrx_bufs; - - spin_lock_init(&ddata->lock); - init_completion(&ddata->done); - - ddata->clk = devm_clk_get(&pdev->dev, null); - if (is_err(ddata->clk)) { - ret = ptr_err(ddata->clk); - dev_err(&pdev->dev, "failed to get clock: %d ", ret); - goto err; - } - - res = platform_get_resource(pdev, ioresource_mem, 0); - if (!res) { - ret = -enodev; - dev_err(&pdev->dev, "failed to determine base address "); - goto err; - } - - if (resource_size(res) < 0x60) { - ret = -einval; - dev_err(&pdev->dev, "memory resource too small "); - goto err; - } - - ddata->base = devm_ioremap_resource(&pdev->dev, res); - if (is_err(ddata->base)) { - ret = ptr_err(ddata->base); - goto err; - } - - ret = platform_get_irq(pdev, 0); - if (ret <= 0) - goto err; - - ddata->rxirq = ret; - - ret = platform_get_irq(pdev, 1); - if (ret <= 0) - ret = ddata->rxirq + 1; - - ddata->txirq = ret; - - ret = clk_prepare_enable(ddata->clk); - if (ret < 0) { - dev_err(&pdev->dev, "failed to enable clock (%d) ", ret); - goto err; - } - - efm32_spi_probe_dt(pdev, master, ddata); - - efm32_spi_write32(ddata, 0, reg_ien); - efm32_spi_write32(ddata, reg_route_txpen | reg_route_rxpen | - reg_route_clkpen | - reg_route_location(ddata->pdata.location), reg_route); - - ret = request_irq(ddata->rxirq, efm32_spi_rxirq, - 0, driver_name " rx", ddata); - if (ret) { - dev_err(&pdev->dev, "failed to register rxirq (%d) ", ret); - goto err_disable_clk; - } - - ret = request_irq(ddata->txirq, efm32_spi_txirq, - 0, driver_name " tx", ddata); - if (ret) { - dev_err(&pdev->dev, "failed to register txirq (%d) ", ret); - goto err_free_rx_irq; - } - - ret = spi_bitbang_start(&ddata->bitbang); - if (ret) { - dev_err(&pdev->dev, "spi_bitbang_start failed (%d) ", ret); - - free_irq(ddata->txirq, ddata); -err_free_rx_irq: - free_irq(ddata->rxirq, ddata); -err_disable_clk: - clk_disable_unprepare(ddata->clk); -err: - spi_master_put(master); - } - - return ret; -} - -static int efm32_spi_remove(struct platform_device *pdev) -{ - struct spi_master *master = platform_get_drvdata(pdev); - struct efm32_spi_ddata *ddata = spi_master_get_devdata(master); - - spi_bitbang_stop(&ddata->bitbang); - - efm32_spi_write32(ddata, 0, reg_ien); - - free_irq(ddata->txirq, ddata); - free_irq(ddata->rxirq, ddata); - clk_disable_unprepare(ddata->clk); - spi_master_put(master); - - return 0; -} - -static const struct of_device_id efm32_spi_dt_ids[] = { - { - .compatible = "energymicro,efm32-spi", - }, { - /* doesn't follow the "vendor,device" scheme, don't use */ - .compatible = "efm32,spi", - }, { - /* sentinel */ - } -}; -module_device_table(of, efm32_spi_dt_ids); - -static struct platform_driver efm32_spi_driver = { - .probe = efm32_spi_probe, - .remove = efm32_spi_remove, - - .driver = { - .name = driver_name, - .of_match_table = efm32_spi_dt_ids, - }, -}; -module_platform_driver(efm32_spi_driver); - -module_author("uwe kleine-koenig <u.kleine-koenig@pengutronix.de>"); -module_description("efm32 spi driver"); -module_license("gpl v2"); -module_alias("platform:" driver_name); diff --git a/include/linux/platform_data/efm32-spi.h b/include/linux/platform_data/efm32-spi.h --- a/include/linux/platform_data/efm32-spi.h +++ /dev/null -/* spdx-license-identifier: gpl-2.0 */ -#ifndef __linux_platform_data_efm32_spi_h__ -#define __linux_platform_data_efm32_spi_h__ - -#include <linux/types.h> - -/** - * struct efm32_spi_pdata - * @location: pinmux location for the i/o pins (to be written to the route - * register) - */ -struct efm32_spi_pdata { - u8 location; -}; -#endif /* ifndef __linux_platform_data_efm32_spi_h__ */
|
Serial Peripheral Interface (SPI)
|
0ba882ae2818193487b70ad39622973538711d9a
|
uwe kleine k nig
|
drivers
|
spi
|
platform_data
|
watchdog: add watchdog driver for intel keembay soc
|
intel keembay soc requires watchdog timer support. add watchdog driver to enable this.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add watchdog driver for intel !keembay soc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['kconfig', 'c', 'makefile']
| 3
| 300
| 0
|
--- diff --git a/drivers/watchdog/kconfig b/drivers/watchdog/kconfig --- a/drivers/watchdog/kconfig +++ b/drivers/watchdog/kconfig +config keembay_watchdog + tristate "intel keem bay soc non-secure watchdog" + depends on arch_keembay || (arm64 && compile_test) + select watchdog_core + help + this option enable support for an in-secure watchdog timer driver for + intel keem bay soc. this wdt has a 32 bit timer and decrements in every + count unit. an interrupt will be triggered, when the count crosses + the thershold configured in the register. + + to compile this driver as a module, choose m here: the + module will be called keembay_wdt. + diff --git a/drivers/watchdog/makefile b/drivers/watchdog/makefile --- a/drivers/watchdog/makefile +++ b/drivers/watchdog/makefile +obj-$(config_keembay_watchdog) += keembay_wdt.o diff --git a/drivers/watchdog/keembay_wdt.c b/drivers/watchdog/keembay_wdt.c --- /dev/null +++ b/drivers/watchdog/keembay_wdt.c +// spdx-license-identifier: gpl-2.0-only +/* + * watchdog driver for intel keem bay non-secure watchdog. + * + * copyright (c) 2020 intel corporation + */ + +#include <linux/arm-smccc.h> +#include <linux/bits.h> +#include <linux/clk.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/limits.h> +#include <linux/module.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> +#include <linux/reboot.h> +#include <linux/watchdog.h> + +/* non-secure watchdog register offsets */ +#define tim_watchdog 0x0 +#define tim_watchdog_int_thres 0x4 +#define tim_wdog_en 0x8 +#define tim_safe 0xc + +#define wdt_isr_mask genmask(9, 8) +#define wdt_isr_clear 0x8200ff18 +#define wdt_unlock 0xf1d0dead +#define wdt_load_max u32_max +#define wdt_load_min 1 +#define wdt_timeout 5 + +static unsigned int timeout = wdt_timeout; +module_param(timeout, int, 0); +module_parm_desc(timeout, "watchdog timeout period in seconds (default = " + __module_string(wdt_timeout) ")"); + +static bool nowayout = watchdog_nowayout; +module_param(nowayout, bool, 0); +module_parm_desc(nowayout, "watchdog cannot be stopped once started (default = " + __module_string(watchdog_nowayout) ")"); + +struct keembay_wdt { + struct watchdog_device wdd; + struct clk *clk; + unsigned int rate; + int to_irq; + int th_irq; + void __iomem *base; +}; + +static inline u32 keembay_wdt_readl(struct keembay_wdt *wdt, u32 offset) +{ + return readl(wdt->base + offset); +} + +static inline void keembay_wdt_writel(struct keembay_wdt *wdt, u32 offset, u32 val) +{ + writel(wdt_unlock, wdt->base + tim_safe); + writel(val, wdt->base + offset); +} + +static void keembay_wdt_set_timeout_reg(struct watchdog_device *wdog) +{ + struct keembay_wdt *wdt = watchdog_get_drvdata(wdog); + + keembay_wdt_writel(wdt, tim_watchdog, wdog->timeout * wdt->rate); +} + +static void keembay_wdt_set_pretimeout_reg(struct watchdog_device *wdog) +{ + struct keembay_wdt *wdt = watchdog_get_drvdata(wdog); + u32 th_val = 0; + + if (wdog->pretimeout) + th_val = wdog->timeout - wdog->pretimeout; + + keembay_wdt_writel(wdt, tim_watchdog_int_thres, th_val * wdt->rate); +} + +static int keembay_wdt_start(struct watchdog_device *wdog) +{ + struct keembay_wdt *wdt = watchdog_get_drvdata(wdog); + + keembay_wdt_set_timeout_reg(wdog); + keembay_wdt_writel(wdt, tim_wdog_en, 1); + + return 0; +} + +static int keembay_wdt_stop(struct watchdog_device *wdog) +{ + struct keembay_wdt *wdt = watchdog_get_drvdata(wdog); + + keembay_wdt_writel(wdt, tim_wdog_en, 0); + + return 0; +} + +static int keembay_wdt_ping(struct watchdog_device *wdog) +{ + keembay_wdt_set_timeout_reg(wdog); + + return 0; +} + +static int keembay_wdt_set_timeout(struct watchdog_device *wdog, u32 t) +{ + wdog->timeout = t; + keembay_wdt_set_timeout_reg(wdog); + + return 0; +} + +static int keembay_wdt_set_pretimeout(struct watchdog_device *wdog, u32 t) +{ + if (t > wdog->timeout) + return -einval; + + wdog->pretimeout = t; + keembay_wdt_set_pretimeout_reg(wdog); + + return 0; +} + +static unsigned int keembay_wdt_get_timeleft(struct watchdog_device *wdog) +{ + struct keembay_wdt *wdt = watchdog_get_drvdata(wdog); + + return keembay_wdt_readl(wdt, tim_watchdog) / wdt->rate; +} + +/* + * smc call is used to clear the interrupt bits, because the tim_gen_config + * register is in the secure bank. + */ +static irqreturn_t keembay_wdt_to_isr(int irq, void *dev_id) +{ + struct keembay_wdt *wdt = dev_id; + struct arm_smccc_res res; + + keembay_wdt_writel(wdt, tim_watchdog, 1); + arm_smccc_smc(wdt_isr_clear, wdt_isr_mask, 0, 0, 0, 0, 0, 0, &res); + dev_crit(wdt->wdd.parent, "intel keem bay non-sec wdt timeout. "); + emergency_restart(); + + return irq_handled; +} + +static irqreturn_t keembay_wdt_th_isr(int irq, void *dev_id) +{ + struct keembay_wdt *wdt = dev_id; + struct arm_smccc_res res; + + arm_smccc_smc(wdt_isr_clear, wdt_isr_mask, 0, 0, 0, 0, 0, 0, &res); + dev_crit(wdt->wdd.parent, "intel keem bay non-sec wdt pre-timeout. "); + watchdog_notify_pretimeout(&wdt->wdd); + + return irq_handled; +} + +static const struct watchdog_info keembay_wdt_info = { + .identity = "intel keem bay watchdog timer", + .options = wdiof_settimeout | + wdiof_pretimeout | + wdiof_magicclose | + wdiof_keepaliveping, +}; + +static const struct watchdog_ops keembay_wdt_ops = { + .owner = this_module, + .start = keembay_wdt_start, + .stop = keembay_wdt_stop, + .ping = keembay_wdt_ping, + .set_timeout = keembay_wdt_set_timeout, + .set_pretimeout = keembay_wdt_set_pretimeout, + .get_timeleft = keembay_wdt_get_timeleft, +}; + +static int keembay_wdt_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct keembay_wdt *wdt; + int ret; + + wdt = devm_kzalloc(dev, sizeof(*wdt), gfp_kernel); + if (!wdt) + return -enomem; + + wdt->base = devm_platform_ioremap_resource(pdev, 0); + if (is_err(wdt->base)) + return ptr_err(wdt->base); + + /* we do not need to enable the clock as it is enabled by default */ + wdt->clk = devm_clk_get(dev, null); + if (is_err(wdt->clk)) + return dev_err_probe(dev, ptr_err(wdt->clk), "failed to get clock "); + + wdt->rate = clk_get_rate(wdt->clk); + if (!wdt->rate) + return dev_err_probe(dev, -einval, "failed to get clock rate "); + + wdt->th_irq = platform_get_irq_byname(pdev, "threshold"); + if (wdt->th_irq < 0) + return dev_err_probe(dev, wdt->th_irq, "failed to get irq for threshold "); + + ret = devm_request_irq(dev, wdt->th_irq, keembay_wdt_th_isr, 0, + "keembay-wdt", wdt); + if (ret) + return dev_err_probe(dev, ret, "failed to request irq for threshold "); + + wdt->to_irq = platform_get_irq_byname(pdev, "timeout"); + if (wdt->to_irq < 0) + return dev_err_probe(dev, wdt->to_irq, "failed to get irq for timeout "); + + ret = devm_request_irq(dev, wdt->to_irq, keembay_wdt_to_isr, 0, + "keembay-wdt", wdt); + if (ret) + return dev_err_probe(dev, ret, "failed to request irq for timeout "); + + wdt->wdd.parent = dev; + wdt->wdd.info = &keembay_wdt_info; + wdt->wdd.ops = &keembay_wdt_ops; + wdt->wdd.min_timeout = wdt_load_min; + wdt->wdd.max_timeout = wdt_load_max / wdt->rate; + wdt->wdd.timeout = wdt_timeout; + + watchdog_set_drvdata(&wdt->wdd, wdt); + watchdog_set_nowayout(&wdt->wdd, nowayout); + watchdog_init_timeout(&wdt->wdd, timeout, dev); + keembay_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout); + + ret = devm_watchdog_register_device(dev, &wdt->wdd); + if (ret) + return dev_err_probe(dev, ret, "failed to register watchdog device. "); + + platform_set_drvdata(pdev, wdt); + dev_info(dev, "initial timeout %d sec%s. ", + wdt->wdd.timeout, nowayout ? ", nowayout" : ""); + + return 0; +} + +static int __maybe_unused keembay_wdt_suspend(struct device *dev) +{ + struct keembay_wdt *wdt = dev_get_drvdata(dev); + + if (watchdog_active(&wdt->wdd)) + return keembay_wdt_stop(&wdt->wdd); + + return 0; +} + +static int __maybe_unused keembay_wdt_resume(struct device *dev) +{ + struct keembay_wdt *wdt = dev_get_drvdata(dev); + + if (watchdog_active(&wdt->wdd)) + return keembay_wdt_start(&wdt->wdd); + + return 0; +} + +static simple_dev_pm_ops(keembay_wdt_pm_ops, keembay_wdt_suspend, + keembay_wdt_resume); + +static const struct of_device_id keembay_wdt_match[] = { + { .compatible = "intel,keembay-wdt" }, + { } +}; +module_device_table(of, keembay_wdt_match); + +static struct platform_driver keembay_wdt_driver = { + .probe = keembay_wdt_probe, + .driver = { + .name = "keembay_wdt", + .of_match_table = keembay_wdt_match, + .pm = &keembay_wdt_pm_ops, + }, +}; + +module_platform_driver(keembay_wdt_driver); + +module_description("intel keem bay soc watchdog driver"); +module_author("wan ahmad zainie <wan.ahmad.zainie.wan.mohamad@intel.com"); +module_license("gpl v2");
|
Watchdog
|
fa0f8d51e90d2202be9f4f02b9a95347389a5959
|
vijayakannan ayyathurai mark gross mgross linux intel com andy shevchenko andriy shevchenko linux intel com guenter roeck linux roeck us net
|
drivers
|
watchdog
| |
watchdog: intel_scu_watchdog: remove driver for deprecated platform
|
intel moorestown and medfield are quite old intel atom based 32-bit platforms, which were in limited use in some android phones, tablets and consumer electronics more than eight years ago.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove driver for deprecated platform
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel_scu_watchdog']
|
['h', 'kconfig', 'c', 'makefile']
| 4
| 0
| 593
|
--- diff --git a/drivers/watchdog/kconfig b/drivers/watchdog/kconfig --- a/drivers/watchdog/kconfig +++ b/drivers/watchdog/kconfig -config intel_scu_watchdog - bool "intel scu watchdog for mobile platforms" - depends on x86_intel_mid - help - hardware driver for the watchdog time built into the intel scu - for intel mobile platforms. - - to compile this driver as a module, choose m here. - diff --git a/drivers/watchdog/makefile b/drivers/watchdog/makefile --- a/drivers/watchdog/makefile +++ b/drivers/watchdog/makefile -obj-$(config_intel_scu_watchdog) += intel_scu_watchdog.o diff --git a/drivers/watchdog/intel_scu_watchdog.c b/drivers/watchdog/intel_scu_watchdog.c --- a/drivers/watchdog/intel_scu_watchdog.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * intel_scu 0.2: an intel scu ioh based watchdog device - * for intel part #(s): - * - af82mp20 pch - * - * copyright (c) 2009-2010 intel corporation. all rights reserved. - */ - -#define pr_fmt(fmt) kbuild_modname ": " fmt - -#include <linux/compiler.h> -#include <linux/kernel.h> -#include <linux/moduleparam.h> -#include <linux/types.h> -#include <linux/miscdevice.h> -#include <linux/watchdog.h> -#include <linux/fs.h> -#include <linux/notifier.h> -#include <linux/reboot.h> -#include <linux/init.h> -#include <linux/jiffies.h> -#include <linux/uaccess.h> -#include <linux/slab.h> -#include <linux/io.h> -#include <linux/interrupt.h> -#include <linux/delay.h> -#include <linux/sched.h> -#include <linux/signal.h> -#include <linux/sfi.h> -#include <asm/irq.h> -#include <linux/atomic.h> -#include <asm/intel_scu_ipc.h> -#include <asm/apb_timer.h> -#include <asm/intel-mid.h> - -#include "intel_scu_watchdog.h" - -/* bounds number of times we will retry loading time count */ -/* this retry is a work around for a silicon bug. */ -#define max_retry 16 - -#define ipc_set_watchdog_timer 0xf8 - -static int timer_margin = default_soft_to_hard_margin; -module_param(timer_margin, int, 0); -module_parm_desc(timer_margin, - "watchdog timer margin" - "time between interrupt and resetting the system" - "the range is from 1 to 160" - "this is the time for all keep alives to arrive"); - -static int timer_set = default_time; -module_param(timer_set, int, 0); -module_parm_desc(timer_set, - "default watchdog timer setting" - "complete cycle time" - "the range is from 1 to 170" - "this is the time for all keep alives to arrive"); - -/* after watchdog device is closed, check force_boot. if: - * force_boot == 0, then force boot on next watchdog interrupt after close, - * force_boot == 1, then force boot immediately when device is closed. - */ -static int force_boot; -module_param(force_boot, int, 0); -module_parm_desc(force_boot, - "a value of 1 means that the driver will reboot" - "the system immediately if the /dev/watchdog device is closed" - "a value of 0 means that when /dev/watchdog device is closed" - "the watchdog timer will be refreshed for one more interval" - "of length: timer_set. at the end of this interval, the" - "watchdog timer will reset the system." - ); - -/* there is only one device in the system now; this can be made into - * an array in the future if we have more than one device */ - -static struct intel_scu_watchdog_dev watchdog_device; - -/* forces restart, if force_reboot is set */ -static void watchdog_fire(void) -{ - if (force_boot) { - pr_crit("initiating system reboot "); - emergency_restart(); - pr_crit("reboot didn't ????? "); - } - - else { - pr_crit("immediate reboot disabled "); - pr_crit("system will reset when watchdog timer times out! "); - } -} - -static int check_timer_margin(int new_margin) -{ - if ((new_margin < min_time_cycle) || - (new_margin > max_time - timer_set)) { - pr_debug("value of new_margin %d is out of the range %d to %d ", - new_margin, min_time_cycle, max_time - timer_set); - return -einval; - } - return 0; -} - -/* - * ipc operations - */ -static int watchdog_set_ipc(int soft_threshold, int threshold) -{ - u32 *ipc_wbuf; - u8 cbuf[16] = { '' }; - int ipc_ret = 0; - - ipc_wbuf = (u32 *)&cbuf; - ipc_wbuf[0] = soft_threshold; - ipc_wbuf[1] = threshold; - - ipc_ret = intel_scu_ipc_command( - ipc_set_watchdog_timer, - 0, - ipc_wbuf, - 2, - null, - 0); - - if (ipc_ret != 0) - pr_err("error setting scu watchdog timer: %x ", ipc_ret); - - return ipc_ret; -}; - -/* - * intel_scu operations - */ - -/* timer interrupt handler */ -static irqreturn_t watchdog_timer_interrupt(int irq, void *dev_id) -{ - int int_status; - int_status = ioread32(watchdog_device.timer_interrupt_status_addr); - - pr_debug("irq, int_status: %x ", int_status); - - if (int_status != 0) - return irq_none; - - /* has the timer been started? if not, then this is spurious */ - if (watchdog_device.timer_started == 0) { - pr_debug("spurious interrupt received "); - return irq_handled; - } - - /* temporarily disable the timer */ - iowrite32(0x00000002, watchdog_device.timer_control_addr); - - /* set the timer to the threshold */ - iowrite32(watchdog_device.threshold, - watchdog_device.timer_load_count_addr); - - /* allow the timer to run */ - iowrite32(0x00000003, watchdog_device.timer_control_addr); - - return irq_handled; -} - -static int intel_scu_keepalive(void) -{ - - /* read eoi register - clears interrupt */ - ioread32(watchdog_device.timer_clear_interrupt_addr); - - /* temporarily disable the timer */ - iowrite32(0x00000002, watchdog_device.timer_control_addr); - - /* set the timer to the soft_threshold */ - iowrite32(watchdog_device.soft_threshold, - watchdog_device.timer_load_count_addr); - - /* allow the timer to run */ - iowrite32(0x00000003, watchdog_device.timer_control_addr); - - return 0; -} - -static int intel_scu_stop(void) -{ - iowrite32(0, watchdog_device.timer_control_addr); - return 0; -} - -static int intel_scu_set_heartbeat(u32 t) -{ - int ipc_ret; - int retry_count; - u32 soft_value; - u32 hw_value; - - watchdog_device.timer_set = t; - watchdog_device.threshold = - timer_margin * watchdog_device.timer_tbl_ptr->freq_hz; - watchdog_device.soft_threshold = - (watchdog_device.timer_set - timer_margin) - * watchdog_device.timer_tbl_ptr->freq_hz; - - pr_debug("set_heartbeat: timer freq is %d ", - watchdog_device.timer_tbl_ptr->freq_hz); - pr_debug("set_heartbeat: timer_set is %x (hex) ", - watchdog_device.timer_set); - pr_debug("set_heartbeat: timer_margin is %x (hex) ", timer_margin); - pr_debug("set_heartbeat: threshold is %x (hex) ", - watchdog_device.threshold); - pr_debug("set_heartbeat: soft_threshold is %x (hex) ", - watchdog_device.soft_threshold); - - /* adjust thresholds by freq_adjustment factor, to make the */ - /* watchdog timing come out right. */ - watchdog_device.threshold = - watchdog_device.threshold / freq_adjustment; - watchdog_device.soft_threshold = - watchdog_device.soft_threshold / freq_adjustment; - - /* temporarily disable the timer */ - iowrite32(0x00000002, watchdog_device.timer_control_addr); - - /* send the threshold and soft_threshold via ipc to the processor */ - ipc_ret = watchdog_set_ipc(watchdog_device.soft_threshold, - watchdog_device.threshold); - - if (ipc_ret != 0) { - /* make sure the watchdog timer is stopped */ - intel_scu_stop(); - return ipc_ret; - } - - /* soft threshold set loop. early versions of silicon did */ - /* not always set this count correctly. this loop checks */ - /* the value and retries if it was not set correctly. */ - - retry_count = 0; - soft_value = watchdog_device.soft_threshold & 0xffff0000; - do { - - /* make sure timer is stopped */ - intel_scu_stop(); - - if (max_retry < retry_count++) { - /* unable to set timer value */ - pr_err("unable to set timer "); - return -enodev; - } - - /* set the timer to the soft threshold */ - iowrite32(watchdog_device.soft_threshold, - watchdog_device.timer_load_count_addr); - - /* read count value before starting timer */ - ioread32(watchdog_device.timer_load_count_addr); - - /* start the timer */ - iowrite32(0x00000003, watchdog_device.timer_control_addr); - - /* read the value the time loaded into its count reg */ - hw_value = ioread32(watchdog_device.timer_load_count_addr); - hw_value = hw_value & 0xffff0000; - - - } while (soft_value != hw_value); - - watchdog_device.timer_started = 1; - - return 0; -} - -/* - * /dev/watchdog handling - */ - -static int intel_scu_open(struct inode *inode, struct file *file) -{ - - /* set flag to indicate that watchdog device is open */ - if (test_and_set_bit(0, &watchdog_device.driver_open)) - return -ebusy; - - /* check for reopen of driver. reopens are not allowed */ - if (watchdog_device.driver_closed) - return -eperm; - - return stream_open(inode, file); -} - -static int intel_scu_release(struct inode *inode, struct file *file) -{ - /* - * this watchdog should not be closed, after the timer - * is started with the wdipc_settimeout ioctl - * if force_boot is set watchdog_fire() will cause an - * immediate reset. if force_boot is not set, the watchdog - * timer is refreshed for one more interval. at the end - * of that interval, the watchdog timer will reset the system. - */ - - if (!test_and_clear_bit(0, &watchdog_device.driver_open)) { - pr_debug("intel_scu_release, without open "); - return -enotty; - } - - if (!watchdog_device.timer_started) { - /* just close, since timer has not been started */ - pr_debug("closed, without starting timer "); - return 0; - } - - pr_crit("unexpected close of /dev/watchdog! "); - - /* since the timer was started, prevent future reopens */ - watchdog_device.driver_closed = 1; - - /* refresh the timer for one more interval */ - intel_scu_keepalive(); - - /* reboot system (if force_boot is set) */ - watchdog_fire(); - - /* we should only reach this point if force_boot is not set */ - return 0; -} - -static ssize_t intel_scu_write(struct file *file, - char const *data, - size_t len, - loff_t *ppos) -{ - - if (watchdog_device.timer_started) - /* watchdog already started, keep it alive */ - intel_scu_keepalive(); - else - /* start watchdog with timer value set by init */ - intel_scu_set_heartbeat(watchdog_device.timer_set); - - return len; -} - -static long intel_scu_ioctl(struct file *file, - unsigned int cmd, - unsigned long arg) -{ - void __user *argp = (void __user *)arg; - u32 __user *p = argp; - u32 new_margin; - - - static const struct watchdog_info ident = { - .options = wdiof_settimeout - | wdiof_keepaliveping, - .firmware_version = 0, /* @todo get from scu via - ipc_get_scu_fw_version()? */ - .identity = "intel_scu ioh watchdog" /* len < 32 */ - }; - - switch (cmd) { - case wdioc_getsupport: - return copy_to_user(argp, - &ident, - sizeof(ident)) ? -efault : 0; - case wdioc_getstatus: - case wdioc_getbootstatus: - return put_user(0, p); - case wdioc_keepalive: - intel_scu_keepalive(); - - return 0; - case wdioc_settimeout: - if (get_user(new_margin, p)) - return -efault; - - if (check_timer_margin(new_margin)) - return -einval; - - if (intel_scu_set_heartbeat(new_margin)) - return -einval; - return 0; - case wdioc_gettimeout: - return put_user(watchdog_device.soft_threshold, p); - - default: - return -enotty; - } -} - -/* - * notifier for system down - */ -static int intel_scu_notify_sys(struct notifier_block *this, - unsigned long code, - void *another_unused) -{ - if (code == sys_down || code == sys_halt) - /* turn off the watchdog timer. */ - intel_scu_stop(); - return notify_done; -} - -/* - * kernel interfaces - */ -static const struct file_operations intel_scu_fops = { - .owner = this_module, - .llseek = no_llseek, - .write = intel_scu_write, - .unlocked_ioctl = intel_scu_ioctl, - .compat_ioctl = compat_ptr_ioctl, - .open = intel_scu_open, - .release = intel_scu_release, -}; - -static int __init intel_scu_watchdog_init(void) -{ - int ret; - u32 __iomem *tmp_addr; - - /* - * we don't really need to check this as the sfi timer get will fail - * but if we do so we can exit with a clearer reason and no noise. - * - * if it isn't an intel mid device then it doesn't have this watchdog - */ - if (!intel_mid_identify_cpu()) - return -enodev; - - /* check boot parameters to verify that their initial values */ - /* are in range. */ - /* check value of timer_set boot parameter */ - if ((timer_set < min_time_cycle) || - (timer_set > max_time - min_time_cycle)) { - pr_err("value of timer_set %x (hex) is out of range from %x to %x (hex) ", - timer_set, min_time_cycle, max_time - min_time_cycle); - return -einval; - } - - /* check value of timer_margin boot parameter */ - if (check_timer_margin(timer_margin)) - return -einval; - - watchdog_device.timer_tbl_ptr = sfi_get_mtmr(sfi_mtimer_num-1); - - if (watchdog_device.timer_tbl_ptr == null) { - pr_debug("timer is not available "); - return -enodev; - } - /* make sure the timer exists */ - if (watchdog_device.timer_tbl_ptr->phys_addr == 0) { - pr_debug("timer %d does not have valid physical memory ", - sfi_mtimer_num); - return -enodev; - } - - if (watchdog_device.timer_tbl_ptr->irq == 0) { - pr_debug("timer %d invalid irq ", sfi_mtimer_num); - return -enodev; - } - - tmp_addr = ioremap(watchdog_device.timer_tbl_ptr->phys_addr, - 20); - - if (tmp_addr == null) { - pr_debug("timer unable to ioremap "); - return -enomem; - } - - watchdog_device.timer_load_count_addr = tmp_addr++; - watchdog_device.timer_current_value_addr = tmp_addr++; - watchdog_device.timer_control_addr = tmp_addr++; - watchdog_device.timer_clear_interrupt_addr = tmp_addr++; - watchdog_device.timer_interrupt_status_addr = tmp_addr++; - - /* set the default time values in device structure */ - - watchdog_device.timer_set = timer_set; - watchdog_device.threshold = - timer_margin * watchdog_device.timer_tbl_ptr->freq_hz; - watchdog_device.soft_threshold = - (watchdog_device.timer_set - timer_margin) - * watchdog_device.timer_tbl_ptr->freq_hz; - - - watchdog_device.intel_scu_notifier.notifier_call = - intel_scu_notify_sys; - - ret = register_reboot_notifier(&watchdog_device.intel_scu_notifier); - if (ret) { - pr_err("cannot register notifier %d) ", ret); - goto register_reboot_error; - } - - watchdog_device.miscdev.minor = watchdog_minor; - watchdog_device.miscdev.name = "watchdog"; - watchdog_device.miscdev.fops = &intel_scu_fops; - - ret = misc_register(&watchdog_device.miscdev); - if (ret) { - pr_err("cannot register miscdev %d err =%d ", - watchdog_minor, ret); - goto misc_register_error; - } - - ret = request_irq((unsigned int)watchdog_device.timer_tbl_ptr->irq, - watchdog_timer_interrupt, - irqf_shared, "watchdog", - &watchdog_device.timer_load_count_addr); - if (ret) { - pr_err("error requesting irq %d ", ret); - goto request_irq_error; - } - /* make sure timer is disabled before returning */ - intel_scu_stop(); - return 0; - -/* error cleanup */ - -request_irq_error: - misc_deregister(&watchdog_device.miscdev); -misc_register_error: - unregister_reboot_notifier(&watchdog_device.intel_scu_notifier); -register_reboot_error: - intel_scu_stop(); - iounmap(watchdog_device.timer_load_count_addr); - return ret; -} -late_initcall(intel_scu_watchdog_init); diff --git a/drivers/watchdog/intel_scu_watchdog.h b/drivers/watchdog/intel_scu_watchdog.h --- a/drivers/watchdog/intel_scu_watchdog.h +++ /dev/null -/* spdx-license-identifier: gpl-2.0-only */ -/* - * intel_scu 0.2: an intel scu ioh based watchdog device - * for intel part #(s): - * - af82mp20 pch - * - * copyright (c) 2009-2010 intel corporation. all rights reserved. - */ - -#ifndef __intel_scu_watchdog_h -#define __intel_scu_watchdog_h - -#define wdt_ver "0.3" - -/* minimum time between interrupts */ -#define min_time_cycle 1 - -/* time from warning to reboot is 2 seconds */ -#define default_soft_to_hard_margin 2 - -#define max_time 170 - -#define default_time 5 - -#define max_soft_to_hard_margin (max_time-min_time_cycle) - -/* ajustment to clock tick frequency to make timing come out right */ -#define freq_adjustment 8 - -struct intel_scu_watchdog_dev { - ulong driver_open; - ulong driver_closed; - u32 timer_started; - u32 timer_set; - u32 threshold; - u32 soft_threshold; - u32 __iomem *timer_load_count_addr; - u32 __iomem *timer_current_value_addr; - u32 __iomem *timer_control_addr; - u32 __iomem *timer_clear_interrupt_addr; - u32 __iomem *timer_interrupt_status_addr; - struct sfi_timer_table_entry *timer_tbl_ptr; - struct notifier_block intel_scu_notifier; - struct miscdevice miscdev; -}; - -extern int sfi_mtimer_num; - -/* extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint); */ -#endif /* __intel_scu_watchdog_h */
|
Watchdog
|
1b5b5b4eb52216af05ae4eebbe2efebed4f15a1c
|
andy shevchenko
|
drivers
|
watchdog
| |
watchdog: mt8192: add wdt support
|
add support for watchdog device found in mt8192 soc
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add wdt support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mt8192']
|
['c']
| 1
| 6
| 0
|
--- diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c +#include <dt-bindings/reset-controller/mt8192-resets.h> +static const struct mtk_wdt_data mt8192_data = { + .toprgu_sw_rst_num = mt8192_toprgu_sw_rst_num, +}; + + { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
|
Watchdog
|
adc318a3406681758b9865558952fd92a42c2d6f
|
crystal guo matthias brugger matthias bgg gmail com guenter roeck linux roeck us net
|
drivers
|
watchdog
| |
watchdog: remove coh901 driver
|
the st-ericsson u300 platform is getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove coh901 driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['txt', 'kconfig', 'c', 'makefile']
| 4
| 0
| 439
|
--- diff --git a/documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt b/documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt --- a/documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt +++ /dev/null -st-ericsson coh 901 327 watchdog timer - -required properties: -- compatible: must be "stericsson,coh901327". -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: the interrupt used for the watchdog timeout warning. - -optional properties: -- timeout-sec: contains the watchdog timeout in seconds. - -example: - -watchdog: watchdog@c0012000 { - compatible = "stericsson,coh901327"; - reg = <0xc0012000 0x1000>; - interrupts = <3>; - timeout-sec = <60>; -}; diff --git a/drivers/watchdog/kconfig b/drivers/watchdog/kconfig --- a/drivers/watchdog/kconfig +++ b/drivers/watchdog/kconfig -config coh901327_watchdog - bool "st-ericsson coh 901 327 watchdog" - depends on arch_u300 || (arm && common_clk && compile_test) - default y if mach_u300 - select watchdog_core - help - say y here to include watchdog timer support for the - watchdog embedded into the st-ericsson u300 series platforms. - this watchdog is used to reset the system and thus cannot be - compiled as a module. - diff --git a/drivers/watchdog/makefile b/drivers/watchdog/makefile --- a/drivers/watchdog/makefile +++ b/drivers/watchdog/makefile -obj-$(config_coh901327_watchdog) += coh901327_wdt.o diff --git a/drivers/watchdog/coh901327_wdt.c b/drivers/watchdog/coh901327_wdt.c --- a/drivers/watchdog/coh901327_wdt.c +++ /dev/null -// spdx-license-identifier: gpl-2.0 -/* - * coh901327_wdt.c - * - * copyright (c) 2008-2009 st-ericsson ab - * watchdog driver for the st-ericsson ab coh 901 327 ip core - * author: linus walleij <linus.walleij@stericsson.com> - */ -#include <linux/moduleparam.h> -#include <linux/mod_devicetable.h> -#include <linux/types.h> -#include <linux/watchdog.h> -#include <linux/interrupt.h> -#include <linux/pm.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/bitops.h> -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/err.h> - -#define drv_name "wdog coh 901 327" - -/* - * coh 901 327 register definitions - */ - -/* wdog_feed register 32bit (-/w) */ -#define u300_wdog_fr 0x00 -#define u300_wdog_fr_feed_restart_timer 0xfeedu -/* wdog_timeout register 32bit (r/w) */ -#define u300_wdog_tr 0x04 -#define u300_wdog_tr_timeout_mask 0x7fffu -/* wdog_disable1 register 32bit (-/w) */ -#define u300_wdog_d1r 0x08 -#define u300_wdog_d1r_disable1_disable_timer 0x2badu -/* wdog_disable2 register 32bit (r/w) */ -#define u300_wdog_d2r 0x0c -#define u300_wdog_d2r_disable2_disable_timer 0xcafeu -#define u300_wdog_d2r_disable_status_disabled 0xdabeu -#define u300_wdog_d2r_disable_status_enabled 0x0000u -/* wdog_status register 32bit (r/w) */ -#define u300_wdog_sr 0x10 -#define u300_wdog_sr_status_timed_out 0xcfe8u -#define u300_wdog_sr_status_normal 0x0000u -#define u300_wdog_sr_reset_status_reset 0xe8b4u -/* wdog_count register 32bit (r/-) */ -#define u300_wdog_cr 0x14 -#define u300_wdog_cr_valid_ind 0x8000u -#define u300_wdog_cr_valid_stable 0x0000u -#define u300_wdog_cr_count_value_mask 0x7fffu -/* wdog_jtagovr register 32bit (r/w) */ -#define u300_wdog_jor 0x18 -#define u300_wdog_jor_jtag_mode_ind 0x0002u -#define u300_wdog_jor_jtag_watchdog_enable 0x0001u -/* wdog_restart register 32bit (-/w) */ -#define u300_wdog_rr 0x1c -#define u300_wdog_rr_restart_value_resume 0xacedu -/* wdog_irq_event register 32bit (r/w) */ -#define u300_wdog_ier 0x20 -#define u300_wdog_ier_will_bark_irq_event_ind 0x0001u -#define u300_wdog_ier_will_bark_irq_ack_enable 0x0001u -/* wdog_irq_mask register 32bit (r/w) */ -#define u300_wdog_imr 0x24 -#define u300_wdog_imr_will_bark_irq_enable 0x0001u -/* wdog_irq_force register 32bit (r/w) */ -#define u300_wdog_ifr 0x28 -#define u300_wdog_ifr_will_bark_irq_force_enable 0x0001u - -/* default timeout in seconds = 1 minute */ -#define u300_wdog_default_timeout 60 - -static unsigned int margin; -static int irq; -static void __iomem *virtbase; -static struct device *parent; - -static struct clk *clk; - -/* - * enabling and disabling functions. - */ -static void coh901327_enable(u16 timeout) -{ - u16 val; - unsigned long freq; - unsigned long delay_ns; - - /* restart timer if it is disabled */ - val = readw(virtbase + u300_wdog_d2r); - if (val == u300_wdog_d2r_disable_status_disabled) - writew(u300_wdog_rr_restart_value_resume, - virtbase + u300_wdog_rr); - /* acknowledge any pending interrupt so it doesn't just fire off */ - writew(u300_wdog_ier_will_bark_irq_ack_enable, - virtbase + u300_wdog_ier); - /* - * the interrupt is cleared in the 32 khz clock domain. - * wait 3 32 khz cycles for it to take effect - */ - freq = clk_get_rate(clk); - delay_ns = div_round_up(1000000000, freq); /* freq to ns and round up */ - delay_ns = 3 * delay_ns; /* wait 3 cycles */ - ndelay(delay_ns); - /* enable the watchdog interrupt */ - writew(u300_wdog_imr_will_bark_irq_enable, virtbase + u300_wdog_imr); - /* activate the watchdog timer */ - writew(timeout, virtbase + u300_wdog_tr); - /* start the watchdog timer */ - writew(u300_wdog_fr_feed_restart_timer, virtbase + u300_wdog_fr); - /* - * extra read so that this change propagate in the watchdog. - */ - (void) readw(virtbase + u300_wdog_cr); - val = readw(virtbase + u300_wdog_d2r); - if (val != u300_wdog_d2r_disable_status_enabled) - dev_err(parent, - "%s(): watchdog not enabled! d2r value %04x ", - __func__, val); -} - -static void coh901327_disable(void) -{ - u16 val; - - /* disable the watchdog interrupt if it is active */ - writew(0x0000u, virtbase + u300_wdog_imr); - /* if the watchdog is currently enabled, attempt to disable it */ - val = readw(virtbase + u300_wdog_d2r); - if (val != u300_wdog_d2r_disable_status_disabled) { - writew(u300_wdog_d1r_disable1_disable_timer, - virtbase + u300_wdog_d1r); - writew(u300_wdog_d2r_disable2_disable_timer, - virtbase + u300_wdog_d2r); - /* write this twice (else problems occur) */ - writew(u300_wdog_d2r_disable2_disable_timer, - virtbase + u300_wdog_d2r); - } - val = readw(virtbase + u300_wdog_d2r); - if (val != u300_wdog_d2r_disable_status_disabled) - dev_err(parent, - "%s(): watchdog not disabled! d2r value %04x ", - __func__, val); -} - -static int coh901327_start(struct watchdog_device *wdt_dev) -{ - coh901327_enable(wdt_dev->timeout * 100); - return 0; -} - -static int coh901327_stop(struct watchdog_device *wdt_dev) -{ - coh901327_disable(); - return 0; -} - -static int coh901327_ping(struct watchdog_device *wdd) -{ - /* feed the watchdog */ - writew(u300_wdog_fr_feed_restart_timer, - virtbase + u300_wdog_fr); - return 0; -} - -static int coh901327_settimeout(struct watchdog_device *wdt_dev, - unsigned int time) -{ - wdt_dev->timeout = time; - /* set new timeout value */ - writew(time * 100, virtbase + u300_wdog_tr); - /* feed the dog */ - writew(u300_wdog_fr_feed_restart_timer, - virtbase + u300_wdog_fr); - return 0; -} - -static unsigned int coh901327_gettimeleft(struct watchdog_device *wdt_dev) -{ - u16 val; - - /* read repeatedly until the value is stable! */ - val = readw(virtbase + u300_wdog_cr); - while (val & u300_wdog_cr_valid_ind) - val = readw(virtbase + u300_wdog_cr); - val &= u300_wdog_cr_count_value_mask; - if (val != 0) - val /= 100; - - return val; -} - -/* - * this interrupt occurs 10 ms before the watchdog will bark. - */ -static irqreturn_t coh901327_interrupt(int irq, void *data) -{ - u16 val; - - /* - * ack irq? if this occurs we're fubar anyway, so - * just acknowledge, disable the interrupt and await the imminent end. - * if you at some point need a host of callbacks to be called - * when the system is about to watchdog-reset, add them here! - * - * note: on future versions of this ip-block, it will be possible - * to prevent a watchdog reset by feeding the watchdog at this - * point. - */ - val = readw(virtbase + u300_wdog_ier); - if (val == u300_wdog_ier_will_bark_irq_event_ind) - writew(u300_wdog_ier_will_bark_irq_ack_enable, - virtbase + u300_wdog_ier); - writew(0x0000u, virtbase + u300_wdog_imr); - dev_crit(parent, "watchdog is barking! "); - return irq_handled; -} - -static const struct watchdog_info coh901327_ident = { - .options = wdiof_cardreset | wdiof_settimeout | wdiof_keepaliveping, - .identity = drv_name, -}; - -static const struct watchdog_ops coh901327_ops = { - .owner = this_module, - .start = coh901327_start, - .stop = coh901327_stop, - .ping = coh901327_ping, - .set_timeout = coh901327_settimeout, - .get_timeleft = coh901327_gettimeleft, -}; - -static struct watchdog_device coh901327_wdt = { - .info = &coh901327_ident, - .ops = &coh901327_ops, - /* - * max timeout is 327 since the 10ms - * timeout register is max - * 0x7fff = 327670ms ~= 327s. - */ - .min_timeout = 1, - .max_timeout = 327, - .timeout = u300_wdog_default_timeout, -}; - -static int __init coh901327_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - int ret; - u16 val; - - parent = dev; - - virtbase = devm_platform_ioremap_resource(pdev, 0); - if (is_err(virtbase)) - return ptr_err(virtbase); - - clk = clk_get(dev, null); - if (is_err(clk)) { - ret = ptr_err(clk); - dev_err(dev, "could not get clock "); - return ret; - } - ret = clk_prepare_enable(clk); - if (ret) { - dev_err(dev, "could not prepare and enable clock "); - goto out_no_clk_enable; - } - - val = readw(virtbase + u300_wdog_sr); - switch (val) { - case u300_wdog_sr_status_timed_out: - dev_info(dev, "watchdog timed out since last chip reset! "); - coh901327_wdt.bootstatus |= wdiof_cardreset; - /* status will be cleared below */ - break; - case u300_wdog_sr_status_normal: - dev_info(dev, "in normal status, no timeouts have occurred. "); - break; - default: - dev_info(dev, "contains an illegal status code (%08x) ", val); - break; - } - - val = readw(virtbase + u300_wdog_d2r); - switch (val) { - case u300_wdog_d2r_disable_status_disabled: - dev_info(dev, "currently disabled. "); - break; - case u300_wdog_d2r_disable_status_enabled: - dev_info(dev, "currently enabled! (disabling it now) "); - coh901327_disable(); - break; - default: - dev_err(dev, "contains an illegal enable/disable code (%08x) ", - val); - break; - } - - /* reset the watchdog */ - writew(u300_wdog_sr_reset_status_reset, virtbase + u300_wdog_sr); - - irq = platform_get_irq(pdev, 0); - if (request_irq(irq, coh901327_interrupt, 0, - drv_name " bark", pdev)) { - ret = -eio; - goto out_no_irq; - } - - watchdog_init_timeout(&coh901327_wdt, margin, dev); - - coh901327_wdt.parent = dev; - ret = watchdog_register_device(&coh901327_wdt); - if (ret) - goto out_no_wdog; - - dev_info(dev, "initialized. (timeout=%d sec) ", - coh901327_wdt.timeout); - return 0; - -out_no_wdog: - free_irq(irq, pdev); -out_no_irq: - clk_disable_unprepare(clk); -out_no_clk_enable: - clk_put(clk); - return ret; -} - -#ifdef config_pm - -static u16 wdogenablestore; -static u16 irqmaskstore; - -static int coh901327_suspend(struct platform_device *pdev, pm_message_t state) -{ - irqmaskstore = readw(virtbase + u300_wdog_imr) & 0x0001u; - wdogenablestore = readw(virtbase + u300_wdog_d2r); - /* if watchdog is on, disable it here and now */ - if (wdogenablestore == u300_wdog_d2r_disable_status_enabled) - coh901327_disable(); - return 0; -} - -static int coh901327_resume(struct platform_device *pdev) -{ - /* restore the watchdog interrupt */ - writew(irqmaskstore, virtbase + u300_wdog_imr); - if (wdogenablestore == u300_wdog_d2r_disable_status_enabled) { - /* restart the watchdog timer */ - writew(u300_wdog_rr_restart_value_resume, - virtbase + u300_wdog_rr); - writew(u300_wdog_fr_feed_restart_timer, - virtbase + u300_wdog_fr); - } - return 0; -} -#else -#define coh901327_suspend null -#define coh901327_resume null -#endif - -/* - * mistreating the watchdog is the only way to perform a software reset of the - * system on emp platforms. so we implement this and export a symbol for it. - */ -void coh901327_watchdog_reset(void) -{ - /* enable even if on jtag too */ - writew(u300_wdog_jor_jtag_watchdog_enable, - virtbase + u300_wdog_jor); - /* - * timeout = 5s, we have to wait for the watchdog reset to - * actually take place: the watchdog will be reloaded with the - * default value immediately, so we have to reboot and get back - * into the kernel in 30s, or the device will reboot again! - * the boot loader will typically deactivate the watchdog, so we - * need time enough for the boot loader to get to the point of - * deactivating the watchdog before it is shut down by it. - * - * note: on future versions of the watchdog, this restriction is - * gone: the watchdog will be reloaded with a default value (1 min) - * instead of last value, and you can conveniently set the watchdog - * timeout to 10ms (value = 1) without any problems. - */ - coh901327_enable(500); - /* return and await doom */ -} - -static const struct of_device_id coh901327_dt_match[] = { - { .compatible = "stericsson,coh901327" }, - {}, -}; - -static struct platform_driver coh901327_driver = { - .driver = { - .name = "coh901327_wdog", - .of_match_table = coh901327_dt_match, - .suppress_bind_attrs = true, - }, - .suspend = coh901327_suspend, - .resume = coh901327_resume, -}; -builtin_platform_driver_probe(coh901327_driver, coh901327_probe); - -/* not really modular, but ... */ -module_param(margin, uint, 0); -module_parm_desc(margin, "watchdog margin in seconds (default 60s)");
|
Watchdog
|
5ecd125b4b2a55a394a459df331a0b6380c773fa
|
arnd bergmann guenter roeck linux roeck us net linus walleij linus walleij linaro org
|
drivers
|
watchdog
|
bindings, watchdog
|
watchdog: remove sirf atlas driver
|
the csr sirf prima2/atlas platforms are getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove sirf atlas driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['kconfig', 'c', 'makefile']
| 3
| 0
| 232
|
--- diff --git a/drivers/watchdog/kconfig b/drivers/watchdog/kconfig --- a/drivers/watchdog/kconfig +++ b/drivers/watchdog/kconfig -config atlas7_watchdog - tristate "csratlas7 watchdog" - depends on arch_atlas7 || compile_test - help - say y here to include watchdog timer support for the watchdog - existing on the csratlas7 series platforms. - - to compile this driver as a module, choose m here: the - module will be called atlas7_wdt. - diff --git a/drivers/watchdog/makefile b/drivers/watchdog/makefile --- a/drivers/watchdog/makefile +++ b/drivers/watchdog/makefile -obj-$(config_atlas7_watchdog) += atlas7_wdt.o diff --git a/drivers/watchdog/atlas7_wdt.c b/drivers/watchdog/atlas7_wdt.c --- a/drivers/watchdog/atlas7_wdt.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * watchdog driver for csr atlas7 - * - * copyright (c) 2015 cambridge silicon radio limited, a csr plc group company. - */ - -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/module.h> -#include <linux/moduleparam.h> -#include <linux/of.h> -#include <linux/platform_device.h> -#include <linux/watchdog.h> - -#define atlas7_timer_wdt_index 5 -#define atlas7_wdt_default_timeout 20 - -#define atlas7_wdt_cnt_ctrl (0 + 4 * atlas7_timer_wdt_index) -#define atlas7_wdt_cnt_match (0x18 + 4 * atlas7_timer_wdt_index) -#define atlas7_wdt_cnt (0x48 + 4 * atlas7_timer_wdt_index) -#define atlas7_wdt_cnt_en (bit(0) | bit(1)) -#define atlas7_wdt_en 0x64 - -static unsigned int timeout = atlas7_wdt_default_timeout; -static bool nowayout = watchdog_nowayout; - -module_param(timeout, uint, 0); -module_param(nowayout, bool, 0); - -module_parm_desc(timeout, "default watchdog timeout (in seconds)"); -module_parm_desc(nowayout, "watchdog cannot be stopped once started (default=" - __module_string(watchdog_nowayout) ")"); - -struct atlas7_wdog { - struct device *dev; - void __iomem *base; - unsigned long tick_rate; - struct clk *clk; -}; - -static unsigned int atlas7_wdt_gettimeleft(struct watchdog_device *wdd) -{ - struct atlas7_wdog *wdt = watchdog_get_drvdata(wdd); - u32 counter, match, delta; - - counter = readl(wdt->base + atlas7_wdt_cnt); - match = readl(wdt->base + atlas7_wdt_cnt_match); - delta = match - counter; - - return delta / wdt->tick_rate; -} - -static int atlas7_wdt_ping(struct watchdog_device *wdd) -{ - struct atlas7_wdog *wdt = watchdog_get_drvdata(wdd); - u32 counter, match, delta; - - counter = readl(wdt->base + atlas7_wdt_cnt); - delta = wdd->timeout * wdt->tick_rate; - match = counter + delta; - - writel(match, wdt->base + atlas7_wdt_cnt_match); - - return 0; -} - -static int atlas7_wdt_enable(struct watchdog_device *wdd) -{ - struct atlas7_wdog *wdt = watchdog_get_drvdata(wdd); - - atlas7_wdt_ping(wdd); - - writel(readl(wdt->base + atlas7_wdt_cnt_ctrl) | atlas7_wdt_cnt_en, - wdt->base + atlas7_wdt_cnt_ctrl); - writel(1, wdt->base + atlas7_wdt_en); - - return 0; -} - -static int atlas7_wdt_disable(struct watchdog_device *wdd) -{ - struct atlas7_wdog *wdt = watchdog_get_drvdata(wdd); - - writel(0, wdt->base + atlas7_wdt_en); - writel(readl(wdt->base + atlas7_wdt_cnt_ctrl) & ~atlas7_wdt_cnt_en, - wdt->base + atlas7_wdt_cnt_ctrl); - - return 0; -} - -static int atlas7_wdt_settimeout(struct watchdog_device *wdd, unsigned int to) -{ - wdd->timeout = to; - - return 0; -} - -#define options (wdiof_settimeout | wdiof_keepaliveping | wdiof_magicclose) - -static const struct watchdog_info atlas7_wdt_ident = { - .options = options, - .firmware_version = 0, - .identity = "atlas7 watchdog", -}; - -static const struct watchdog_ops atlas7_wdt_ops = { - .owner = this_module, - .start = atlas7_wdt_enable, - .stop = atlas7_wdt_disable, - .get_timeleft = atlas7_wdt_gettimeleft, - .ping = atlas7_wdt_ping, - .set_timeout = atlas7_wdt_settimeout, -}; - -static struct watchdog_device atlas7_wdd = { - .info = &atlas7_wdt_ident, - .ops = &atlas7_wdt_ops, - .timeout = atlas7_wdt_default_timeout, -}; - -static const struct of_device_id atlas7_wdt_ids[] = { - { .compatible = "sirf,atlas7-tick"}, - {} -}; - -static void atlas7_clk_disable_unprepare(void *data) -{ - clk_disable_unprepare(data); -} - -static int atlas7_wdt_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct atlas7_wdog *wdt; - struct clk *clk; - int ret; - - wdt = devm_kzalloc(dev, sizeof(*wdt), gfp_kernel); - if (!wdt) - return -enomem; - wdt->base = devm_platform_ioremap_resource(pdev, 0); - if (is_err(wdt->base)) - return ptr_err(wdt->base); - - clk = devm_clk_get(dev, null); - if (is_err(clk)) - return ptr_err(clk); - ret = clk_prepare_enable(clk); - if (ret) { - dev_err(dev, "clk enable failed "); - return ret; - } - ret = devm_add_action_or_reset(dev, atlas7_clk_disable_unprepare, clk); - if (ret) - return ret; - - /* disable watchdog hardware */ - writel(0, wdt->base + atlas7_wdt_cnt_ctrl); - - wdt->tick_rate = clk_get_rate(clk); - if (!wdt->tick_rate) - return -einval; - - wdt->clk = clk; - atlas7_wdd.min_timeout = 1; - atlas7_wdd.max_timeout = uint_max / wdt->tick_rate; - - watchdog_init_timeout(&atlas7_wdd, 0, dev); - watchdog_set_nowayout(&atlas7_wdd, nowayout); - - watchdog_set_drvdata(&atlas7_wdd, wdt); - platform_set_drvdata(pdev, &atlas7_wdd); - - watchdog_stop_on_reboot(&atlas7_wdd); - watchdog_stop_on_unregister(&atlas7_wdd); - return devm_watchdog_register_device(dev, &atlas7_wdd); -} - -static int __maybe_unused atlas7_wdt_suspend(struct device *dev) -{ - /* - * note:timer controller registers settings are saved - * and restored back by the timer-atlas7.c - */ - return 0; -} - -static int __maybe_unused atlas7_wdt_resume(struct device *dev) -{ - struct watchdog_device *wdd = dev_get_drvdata(dev); - - /* - * note: since timer controller registers settings are saved - * and restored back by the timer-atlas7.c, so we need not - * update wd settings except refreshing timeout. - */ - atlas7_wdt_ping(wdd); - - return 0; -} - -static simple_dev_pm_ops(atlas7_wdt_pm_ops, - atlas7_wdt_suspend, atlas7_wdt_resume); - -module_device_table(of, atlas7_wdt_ids); - -static struct platform_driver atlas7_wdt_driver = { - .driver = { - .name = "atlas7-wdt", - .pm = &atlas7_wdt_pm_ops, - .of_match_table = atlas7_wdt_ids, - }, - .probe = atlas7_wdt_probe, -}; -module_platform_driver(atlas7_wdt_driver); - -module_description("csratlas7 watchdog driver"); -module_author("guo zeng <guo.zeng@csr.com>"); -module_license("gpl v2"); -module_alias("platform:atlas7-wdt");
|
Watchdog
|
011eda8c67e02d9a6d2449f2bbc9448435db93ea
|
arnd bergmann barry song baohua kernel org guenter roeck linux roeck us net
|
drivers
|
watchdog
| |
watchdog: remove sirf prima driver
|
the csr sirf prima2/atlas platforms are getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove sirf prima driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['txt', 'kconfig', 'c', 'makefile']
| 4
| 0
| 245
|
--- diff --git a/documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt b/documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt --- a/documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt +++ /dev/null -sirfsoc timer and watchdog timer(wdt) controller - -required properties: -- compatible: "sirf,prima2-tick" -- reg: address range of tick timer/wdt register set -- interrupts: interrupt number to the cpu - -optional properties: -- timeout-sec : contains the watchdog timeout in seconds - -example: - -timer@b0020000 { - compatible = "sirf,prima2-tick"; - reg = <0xb0020000 0x1000>; - interrupts = <0>; - timeout-sec = <30>; -}; diff --git a/drivers/watchdog/kconfig b/drivers/watchdog/kconfig --- a/drivers/watchdog/kconfig +++ b/drivers/watchdog/kconfig -config sirfsoc_watchdog - tristate "sirfsoc watchdog" - depends on has_iomem - depends on arch_sirf || compile_test - select watchdog_core - default y - help - support for csr sirfprimaii and sirfatlasvi watchdog. when - the watchdog triggers the system will be reset. - diff --git a/drivers/watchdog/makefile b/drivers/watchdog/makefile --- a/drivers/watchdog/makefile +++ b/drivers/watchdog/makefile -obj-$(config_sirfsoc_watchdog) += sirfsoc_wdt.o diff --git a/drivers/watchdog/sirfsoc_wdt.c b/drivers/watchdog/sirfsoc_wdt.c --- a/drivers/watchdog/sirfsoc_wdt.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-or-later -/* - * watchdog driver for csr sirfprimaii and sirfatlasvi - * - * copyright (c) 2013 cambridge silicon radio limited, a csr plc group company. - */ - -#include <linux/module.h> -#include <linux/watchdog.h> -#include <linux/platform_device.h> -#include <linux/moduleparam.h> -#include <linux/of.h> -#include <linux/io.h> -#include <linux/uaccess.h> - -#define clock_freq 1000000 - -#define sirfsoc_timer_counter_lo 0x0000 -#define sirfsoc_timer_match_0 0x0008 -#define sirfsoc_timer_int_en 0x0024 -#define sirfsoc_timer_watchdog_en 0x0028 -#define sirfsoc_timer_latch 0x0030 -#define sirfsoc_timer_latched_lo 0x0034 - -#define sirfsoc_timer_wdt_index 5 - -#define sirfsoc_wdt_min_timeout 30 /* 30 secs */ -#define sirfsoc_wdt_max_timeout (10 * 60) /* 10 mins */ -#define sirfsoc_wdt_default_timeout 30 /* 30 secs */ - -static unsigned int timeout; -static bool nowayout = watchdog_nowayout; - -module_param(timeout, uint, 0); -module_param(nowayout, bool, 0); - -module_parm_desc(timeout, "default watchdog timeout (in seconds)"); -module_parm_desc(nowayout, "watchdog cannot be stopped once started (default=" - __module_string(watchdog_nowayout) ")"); - -static void __iomem *sirfsoc_wdt_base(struct watchdog_device *wdd) -{ - return (void __iomem __force *)watchdog_get_drvdata(wdd); -} - -static unsigned int sirfsoc_wdt_gettimeleft(struct watchdog_device *wdd) -{ - u32 counter, match; - void __iomem *wdt_base; - int time_left; - - wdt_base = sirfsoc_wdt_base(wdd); - counter = readl(wdt_base + sirfsoc_timer_counter_lo); - match = readl(wdt_base + - sirfsoc_timer_match_0 + (sirfsoc_timer_wdt_index << 2)); - - time_left = match - counter; - - return time_left / clock_freq; -} - -static int sirfsoc_wdt_updatetimeout(struct watchdog_device *wdd) -{ - u32 counter, timeout_ticks; - void __iomem *wdt_base; - - timeout_ticks = wdd->timeout * clock_freq; - wdt_base = sirfsoc_wdt_base(wdd); - - /* enable the latch before reading the latch_lo register */ - writel(1, wdt_base + sirfsoc_timer_latch); - - /* set the to value */ - counter = readl(wdt_base + sirfsoc_timer_latched_lo); - - counter += timeout_ticks; - - writel(counter, wdt_base + - sirfsoc_timer_match_0 + (sirfsoc_timer_wdt_index << 2)); - - return 0; -} - -static int sirfsoc_wdt_enable(struct watchdog_device *wdd) -{ - void __iomem *wdt_base = sirfsoc_wdt_base(wdd); - sirfsoc_wdt_updatetimeout(wdd); - - /* - * note: if interrupt is not enabled - * then wd-reset doesn't get generated at all. - */ - writel(readl(wdt_base + sirfsoc_timer_int_en) - | (1 << sirfsoc_timer_wdt_index), - wdt_base + sirfsoc_timer_int_en); - writel(1, wdt_base + sirfsoc_timer_watchdog_en); - - return 0; -} - -static int sirfsoc_wdt_disable(struct watchdog_device *wdd) -{ - void __iomem *wdt_base = sirfsoc_wdt_base(wdd); - - writel(0, wdt_base + sirfsoc_timer_watchdog_en); - writel(readl(wdt_base + sirfsoc_timer_int_en) - & (~(1 << sirfsoc_timer_wdt_index)), - wdt_base + sirfsoc_timer_int_en); - - return 0; -} - -static int sirfsoc_wdt_settimeout(struct watchdog_device *wdd, unsigned int to) -{ - wdd->timeout = to; - sirfsoc_wdt_updatetimeout(wdd); - - return 0; -} - -#define options (wdiof_settimeout | wdiof_keepaliveping | wdiof_magicclose) - -static const struct watchdog_info sirfsoc_wdt_ident = { - .options = options, - .firmware_version = 0, - .identity = "sirfsoc watchdog", -}; - -static const struct watchdog_ops sirfsoc_wdt_ops = { - .owner = this_module, - .start = sirfsoc_wdt_enable, - .stop = sirfsoc_wdt_disable, - .get_timeleft = sirfsoc_wdt_gettimeleft, - .ping = sirfsoc_wdt_updatetimeout, - .set_timeout = sirfsoc_wdt_settimeout, -}; - -static struct watchdog_device sirfsoc_wdd = { - .info = &sirfsoc_wdt_ident, - .ops = &sirfsoc_wdt_ops, - .timeout = sirfsoc_wdt_default_timeout, - .min_timeout = sirfsoc_wdt_min_timeout, - .max_timeout = sirfsoc_wdt_max_timeout, -}; - -static int sirfsoc_wdt_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - int ret; - void __iomem *base; - - base = devm_platform_ioremap_resource(pdev, 0); - if (is_err(base)) - return ptr_err(base); - - watchdog_set_drvdata(&sirfsoc_wdd, (__force void *)base); - - watchdog_init_timeout(&sirfsoc_wdd, timeout, dev); - watchdog_set_nowayout(&sirfsoc_wdd, nowayout); - sirfsoc_wdd.parent = dev; - - watchdog_stop_on_reboot(&sirfsoc_wdd); - watchdog_stop_on_unregister(&sirfsoc_wdd); - ret = devm_watchdog_register_device(dev, &sirfsoc_wdd); - if (ret) - return ret; - - platform_set_drvdata(pdev, &sirfsoc_wdd); - - return 0; -} - -#ifdef config_pm_sleep -static int sirfsoc_wdt_suspend(struct device *dev) -{ - return 0; -} - -static int sirfsoc_wdt_resume(struct device *dev) -{ - struct watchdog_device *wdd = dev_get_drvdata(dev); - - /* - * note: since timer controller registers settings are saved - * and restored back by the timer-prima2.c, so we need not - * update wd settings except refreshing timeout. - */ - sirfsoc_wdt_updatetimeout(wdd); - - return 0; -} -#endif - -static simple_dev_pm_ops(sirfsoc_wdt_pm_ops, - sirfsoc_wdt_suspend, sirfsoc_wdt_resume); - -static const struct of_device_id sirfsoc_wdt_of_match[] = { - { .compatible = "sirf,prima2-tick"}, - {}, -}; -module_device_table(of, sirfsoc_wdt_of_match); - -static struct platform_driver sirfsoc_wdt_driver = { - .driver = { - .name = "sirfsoc-wdt", - .pm = &sirfsoc_wdt_pm_ops, - .of_match_table = sirfsoc_wdt_of_match, - }, - .probe = sirfsoc_wdt_probe, -}; -module_platform_driver(sirfsoc_wdt_driver); - -module_description("sirf soc watchdog driver"); -module_author("xianglong du <xianglong.du@csr.com>"); -module_license("gpl v2"); -module_alias("platform:sirfsoc-wdt");
|
Watchdog
|
b4b12b48458fcec2b90ac4b3e4e017f813f22959
|
arnd bergmann barry song baohua kernel org guenter roeck linux roeck us net
|
drivers
|
watchdog
|
bindings, watchdog
|
watchdog: remove tango driver
|
the tango platform is getting removed, so the driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove tango driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['txt', 'kconfig', 'c', 'makefile']
| 4
| 0
| 239
|
--- diff --git a/documentation/devicetree/bindings/watchdog/sigma,smp8642-wdt.txt b/documentation/devicetree/bindings/watchdog/sigma,smp8642-wdt.txt --- a/documentation/devicetree/bindings/watchdog/sigma,smp8642-wdt.txt +++ /dev/null -sigma designs smp86xx/smp87xx watchdog - -required properties: -- compatible: should be "sigma,smp8642-wdt" -- reg: specifies the physical address region -- clocks: should be a phandle to the clock - -optional properties: -- timeout-sec: watchdog timeout in seconds - -example: - -watchdog@1fd00 { - compatible = "sigma,smp8642-wdt"; - reg = <0x1fd00 8>; - clocks = <&xtal_in_clk>; - timeout-sec = <30>; -}; diff --git a/drivers/watchdog/kconfig b/drivers/watchdog/kconfig --- a/drivers/watchdog/kconfig +++ b/drivers/watchdog/kconfig -config tangox_watchdog - tristate "sigma designs smp86xx/smp87xx watchdog" - select watchdog_core - depends on arch_tango || compile_test - depends on has_iomem - help - support for the watchdog in sigma designs smp86xx (tango3) - and smp87xx (tango4) family chips. - - this driver can be built as a module. the module name is tangox_wdt. - diff --git a/drivers/watchdog/makefile b/drivers/watchdog/makefile --- a/drivers/watchdog/makefile +++ b/drivers/watchdog/makefile -obj-$(config_tangox_watchdog) += tangox_wdt.o diff --git a/drivers/watchdog/tangox_wdt.c b/drivers/watchdog/tangox_wdt.c --- a/drivers/watchdog/tangox_wdt.c +++ /dev/null -// spdx-license-identifier: gpl-2.0+ -/* - * copyright (c) 2015 mans rullgard <mans@mansr.com> - * smp86xx/smp87xx watchdog driver - */ - -#include <linux/bitops.h> -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/moduleparam.h> -#include <linux/mod_devicetable.h> -#include <linux/platform_device.h> -#include <linux/watchdog.h> - -#define default_timeout 30 - -static bool nowayout = watchdog_nowayout; -module_param(nowayout, bool, 0); -module_parm_desc(nowayout, - "watchdog cannot be stopped once started (default=" - __module_string(watchdog_nowayout) ")"); - -static unsigned int timeout; -module_param(timeout, int, 0); -module_parm_desc(timeout, "watchdog timeout"); - -/* - * counter counts down from programmed value. reset asserts when - * the counter reaches 1. - */ -#define wd_counter 0 - -#define wd_config 4 -#define wd_config_xtal_in bit(0) -#define wd_config_disable bit(31) - -struct tangox_wdt_device { - struct watchdog_device wdt; - void __iomem *base; - unsigned long clk_rate; - struct clk *clk; -}; - -static int tangox_wdt_set_timeout(struct watchdog_device *wdt, - unsigned int new_timeout) -{ - wdt->timeout = new_timeout; - - return 0; -} - -static int tangox_wdt_start(struct watchdog_device *wdt) -{ - struct tangox_wdt_device *dev = watchdog_get_drvdata(wdt); - u32 ticks; - - ticks = 1 + wdt->timeout * dev->clk_rate; - writel(ticks, dev->base + wd_counter); - - return 0; -} - -static int tangox_wdt_stop(struct watchdog_device *wdt) -{ - struct tangox_wdt_device *dev = watchdog_get_drvdata(wdt); - - writel(0, dev->base + wd_counter); - - return 0; -} - -static unsigned int tangox_wdt_get_timeleft(struct watchdog_device *wdt) -{ - struct tangox_wdt_device *dev = watchdog_get_drvdata(wdt); - u32 count; - - count = readl(dev->base + wd_counter); - - if (!count) - return 0; - - return (count - 1) / dev->clk_rate; -} - -static const struct watchdog_info tangox_wdt_info = { - .options = wdiof_settimeout | wdiof_keepaliveping | wdiof_magicclose, - .identity = "tangox watchdog", -}; - -static int tangox_wdt_restart(struct watchdog_device *wdt, - unsigned long action, void *data) -{ - struct tangox_wdt_device *dev = watchdog_get_drvdata(wdt); - - writel(1, dev->base + wd_counter); - - return 0; -} - -static const struct watchdog_ops tangox_wdt_ops = { - .start = tangox_wdt_start, - .stop = tangox_wdt_stop, - .set_timeout = tangox_wdt_set_timeout, - .get_timeleft = tangox_wdt_get_timeleft, - .restart = tangox_wdt_restart, -}; - -static void tangox_clk_disable_unprepare(void *data) -{ - clk_disable_unprepare(data); -} - -static int tangox_wdt_probe(struct platform_device *pdev) -{ - struct tangox_wdt_device *dev; - u32 config; - int err; - - dev = devm_kzalloc(&pdev->dev, sizeof(*dev), gfp_kernel); - if (!dev) - return -enomem; - - dev->base = devm_platform_ioremap_resource(pdev, 0); - if (is_err(dev->base)) - return ptr_err(dev->base); - - dev->clk = devm_clk_get(&pdev->dev, null); - if (is_err(dev->clk)) - return ptr_err(dev->clk); - - err = clk_prepare_enable(dev->clk); - if (err) - return err; - err = devm_add_action_or_reset(&pdev->dev, - tangox_clk_disable_unprepare, dev->clk); - if (err) - return err; - - dev->clk_rate = clk_get_rate(dev->clk); - if (!dev->clk_rate) - return -einval; - - dev->wdt.parent = &pdev->dev; - dev->wdt.info = &tangox_wdt_info; - dev->wdt.ops = &tangox_wdt_ops; - dev->wdt.timeout = default_timeout; - dev->wdt.min_timeout = 1; - dev->wdt.max_hw_heartbeat_ms = (u32_max - 1) / dev->clk_rate; - - watchdog_init_timeout(&dev->wdt, timeout, &pdev->dev); - watchdog_set_nowayout(&dev->wdt, nowayout); - watchdog_set_drvdata(&dev->wdt, dev); - - /* - * deactivate counter if disable bit is set to avoid - * accidental reset. - */ - config = readl(dev->base + wd_config); - if (config & wd_config_disable) - writel(0, dev->base + wd_counter); - - writel(wd_config_xtal_in, dev->base + wd_config); - - /* - * mark as active and restart with configured timeout if - * already running. - */ - if (readl(dev->base + wd_counter)) { - set_bit(wdog_hw_running, &dev->wdt.status); - tangox_wdt_start(&dev->wdt); - } - - watchdog_set_restart_priority(&dev->wdt, 128); - - watchdog_stop_on_unregister(&dev->wdt); - err = devm_watchdog_register_device(&pdev->dev, &dev->wdt); - if (err) - return err; - - platform_set_drvdata(pdev, dev); - - dev_info(&pdev->dev, "smp86xx/smp87xx watchdog registered "); - - return 0; -} - -static const struct of_device_id tangox_wdt_dt_ids[] = { - { .compatible = "sigma,smp8642-wdt" }, - { .compatible = "sigma,smp8759-wdt" }, - { } -}; -module_device_table(of, tangox_wdt_dt_ids); - -static struct platform_driver tangox_wdt_driver = { - .probe = tangox_wdt_probe, - .driver = { - .name = "tangox-wdt", - .of_match_table = tangox_wdt_dt_ids, - }, -}; - -module_platform_driver(tangox_wdt_driver); - -module_author("mans rullgard <mans@mansr.com>"); -module_description("smp86xx/smp87xx watchdog driver"); -module_license("gpl");
|
Watchdog
|
c1b50b55b00daa373379bb1062afab5ce279cad1
|
arnd bergmann mans rullgard mans mansr com guenter roeck linux roeck us net
|
drivers
|
watchdog
|
bindings, watchdog
|
watchdog: remove zte zx driver
|
the zte zx platform is getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove zte zx driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['txt', 'kconfig', 'c', 'makefile']
| 4
| 0
| 322
|
--- diff --git a/documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt b/documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt --- a/documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt +++ /dev/null -zte zx2967 watchdog timer - -required properties: - -- compatible : should be one of the following. - * zte,zx296718-wdt -- reg : specifies base physical address and size of the registers. -- clocks : pairs of phandle and specifier referencing the controller's clocks. -- resets : reference to the reset controller controlling the watchdog - controller. - -optional properties: - -- timeout-sec : contains the watchdog timeout in seconds. -- zte,wdt-reset-sysctrl : directs how to reset system by the watchdog. - if we don't want to restart system when watchdog been triggered, - it's not required, vice versa. - it should include following fields. - * phandle of aon-sysctrl. - * offset of register that be written, should be 0xb0. - * configure value that be written to aon-sysctrl. - * bit mask, corresponding bits will be affected. - -example: - -wdt: watchdog@1465000 { - compatible = "zte,zx296718-wdt"; - reg = <0x1465000 0x1000>; - clocks = <&topcrm wdt_wclk>; - resets = <&toprst 35>; - zte,wdt-reset-sysctrl = <&aon_sysctrl 0xb0 1 0x115>; -}; diff --git a/drivers/watchdog/kconfig b/drivers/watchdog/kconfig --- a/drivers/watchdog/kconfig +++ b/drivers/watchdog/kconfig -config zx2967_watchdog - tristate "zte zx2967 socs watchdog support" - depends on arch_zx - select watchdog_core - help - say y here to include support for the watchdog timer - in zte zx2967 socs. - to compile this driver as a module, choose m here: the - module will be called zx2967_wdt. - diff --git a/drivers/watchdog/makefile b/drivers/watchdog/makefile --- a/drivers/watchdog/makefile +++ b/drivers/watchdog/makefile -obj-$(config_zx2967_watchdog) += zx2967_wdt.o diff --git a/drivers/watchdog/zx2967_wdt.c b/drivers/watchdog/zx2967_wdt.c --- a/drivers/watchdog/zx2967_wdt.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * watchdog driver for zte's zx2967 family - * - * copyright (c) 2017 zte ltd. - * - * author: baoyou xie <baoyou.xie@linaro.org> - */ - -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/mfd/syscon.h> -#include <linux/module.h> -#include <linux/of_address.h> -#include <linux/platform_device.h> -#include <linux/regmap.h> -#include <linux/reset.h> -#include <linux/watchdog.h> - -#define zx2967_wdt_cfg_reg 0x4 -#define zx2967_wdt_load_reg 0x8 -#define zx2967_wdt_refresh_reg 0x18 -#define zx2967_wdt_start_reg 0x1c - -#define zx2967_wdt_refresh_mask genmask(5, 0) - -#define zx2967_wdt_cfg_div(n) ((((n) & 0xff) - 1) << 8) -#define zx2967_wdt_start_en 0x1 - -/* - * hardware magic number. - * when watchdog reg is written, the lowest 16 bits are valid, but - * the highest 16 bits should be always this number. - */ -#define zx2967_wdt_writekey (0x1234 << 16) -#define zx2967_wdt_val_mask genmask(15, 0) - -#define zx2967_wdt_div_default 16 -#define zx2967_wdt_default_timeout 32 -#define zx2967_wdt_min_timeout 1 -#define zx2967_wdt_max_timeout 524 -#define zx2967_wdt_max_count 0xffff - -#define zx2967_wdt_clk_freq 0x8000 - -#define zx2967_wdt_flag_reboot_mon bit(0) - -struct zx2967_wdt { - struct watchdog_device wdt_device; - void __iomem *reg_base; - struct clk *clock; -}; - -static inline u32 zx2967_wdt_readl(struct zx2967_wdt *wdt, u16 reg) -{ - return readl_relaxed(wdt->reg_base + reg); -} - -static inline void zx2967_wdt_writel(struct zx2967_wdt *wdt, u16 reg, u32 val) -{ - writel_relaxed(val | zx2967_wdt_writekey, wdt->reg_base + reg); -} - -static void zx2967_wdt_refresh(struct zx2967_wdt *wdt) -{ - u32 val; - - val = zx2967_wdt_readl(wdt, zx2967_wdt_refresh_reg); - /* - * bit 4-5, 1 and 2: refresh config info - * bit 2-3, 1 and 2: refresh counter - * bit 0-1, 1 and 2: refresh int-value - * we shift each group value between 1 and 2 to refresh all data. - */ - val ^= zx2967_wdt_refresh_mask; - zx2967_wdt_writel(wdt, zx2967_wdt_refresh_reg, - val & zx2967_wdt_val_mask); -} - -static int -zx2967_wdt_set_timeout(struct watchdog_device *wdd, unsigned int timeout) -{ - struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd); - unsigned int divisor = zx2967_wdt_div_default; - u32 count; - - count = timeout * zx2967_wdt_clk_freq; - if (count > divisor * zx2967_wdt_max_count) - divisor = div_round_up(count, zx2967_wdt_max_count); - count = div_round_up(count, divisor); - zx2967_wdt_writel(wdt, zx2967_wdt_cfg_reg, - zx2967_wdt_cfg_div(divisor) & zx2967_wdt_val_mask); - zx2967_wdt_writel(wdt, zx2967_wdt_load_reg, - count & zx2967_wdt_val_mask); - zx2967_wdt_refresh(wdt); - wdd->timeout = (count * divisor) / zx2967_wdt_clk_freq; - - return 0; -} - -static void __zx2967_wdt_start(struct zx2967_wdt *wdt) -{ - u32 val; - - val = zx2967_wdt_readl(wdt, zx2967_wdt_start_reg); - val |= zx2967_wdt_start_en; - zx2967_wdt_writel(wdt, zx2967_wdt_start_reg, - val & zx2967_wdt_val_mask); -} - -static void __zx2967_wdt_stop(struct zx2967_wdt *wdt) -{ - u32 val; - - val = zx2967_wdt_readl(wdt, zx2967_wdt_start_reg); - val &= ~zx2967_wdt_start_en; - zx2967_wdt_writel(wdt, zx2967_wdt_start_reg, - val & zx2967_wdt_val_mask); -} - -static int zx2967_wdt_start(struct watchdog_device *wdd) -{ - struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd); - - zx2967_wdt_set_timeout(wdd, wdd->timeout); - __zx2967_wdt_start(wdt); - - return 0; -} - -static int zx2967_wdt_stop(struct watchdog_device *wdd) -{ - struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd); - - __zx2967_wdt_stop(wdt); - - return 0; -} - -static int zx2967_wdt_keepalive(struct watchdog_device *wdd) -{ - struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd); - - zx2967_wdt_refresh(wdt); - - return 0; -} - -#define zx2967_wdt_options \ - (wdiof_settimeout | wdiof_keepaliveping | wdiof_magicclose) -static const struct watchdog_info zx2967_wdt_ident = { - .options = zx2967_wdt_options, - .identity = "zx2967 watchdog", -}; - -static const struct watchdog_ops zx2967_wdt_ops = { - .owner = this_module, - .start = zx2967_wdt_start, - .stop = zx2967_wdt_stop, - .ping = zx2967_wdt_keepalive, - .set_timeout = zx2967_wdt_set_timeout, -}; - -static void zx2967_wdt_reset_sysctrl(struct device *dev) -{ - int ret; - void __iomem *regmap; - unsigned int offset, mask, config; - struct of_phandle_args out_args; - - ret = of_parse_phandle_with_fixed_args(dev->of_node, - "zte,wdt-reset-sysctrl", 3, 0, &out_args); - if (ret) - return; - - offset = out_args.args[0]; - config = out_args.args[1]; - mask = out_args.args[2]; - - regmap = syscon_node_to_regmap(out_args.np); - if (is_err(regmap)) { - of_node_put(out_args.np); - return; - } - - regmap_update_bits(regmap, offset, mask, config); - of_node_put(out_args.np); -} - -static void zx2967_clk_disable_unprepare(void *data) -{ - clk_disable_unprepare(data); -} - -static int zx2967_wdt_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct zx2967_wdt *wdt; - int ret; - struct reset_control *rstc; - - wdt = devm_kzalloc(dev, sizeof(*wdt), gfp_kernel); - if (!wdt) - return -enomem; - - platform_set_drvdata(pdev, wdt); - - wdt->wdt_device.info = &zx2967_wdt_ident; - wdt->wdt_device.ops = &zx2967_wdt_ops; - wdt->wdt_device.timeout = zx2967_wdt_default_timeout; - wdt->wdt_device.max_timeout = zx2967_wdt_max_timeout; - wdt->wdt_device.min_timeout = zx2967_wdt_min_timeout; - wdt->wdt_device.parent = dev; - - wdt->reg_base = devm_platform_ioremap_resource(pdev, 0); - if (is_err(wdt->reg_base)) - return ptr_err(wdt->reg_base); - - zx2967_wdt_reset_sysctrl(dev); - - wdt->clock = devm_clk_get(dev, null); - if (is_err(wdt->clock)) { - dev_err(dev, "failed to find watchdog clock source "); - return ptr_err(wdt->clock); - } - - ret = clk_prepare_enable(wdt->clock); - if (ret < 0) { - dev_err(dev, "failed to enable clock "); - return ret; - } - ret = devm_add_action_or_reset(dev, zx2967_clk_disable_unprepare, - wdt->clock); - if (ret) - return ret; - clk_set_rate(wdt->clock, zx2967_wdt_clk_freq); - - rstc = devm_reset_control_get_exclusive(dev, null); - if (is_err(rstc)) { - dev_err(dev, "failed to get rstc"); - return ptr_err(rstc); - } - - reset_control_assert(rstc); - reset_control_deassert(rstc); - - watchdog_set_drvdata(&wdt->wdt_device, wdt); - watchdog_init_timeout(&wdt->wdt_device, - zx2967_wdt_default_timeout, dev); - watchdog_set_nowayout(&wdt->wdt_device, watchdog_nowayout); - - ret = devm_watchdog_register_device(dev, &wdt->wdt_device); - if (ret) - return ret; - - dev_info(dev, "watchdog enabled (timeout=%d sec, nowayout=%d)", - wdt->wdt_device.timeout, watchdog_nowayout); - - return 0; -} - -static const struct of_device_id zx2967_wdt_match[] = { - { .compatible = "zte,zx296718-wdt", }, - {} -}; -module_device_table(of, zx2967_wdt_match); - -static struct platform_driver zx2967_wdt_driver = { - .probe = zx2967_wdt_probe, - .driver = { - .name = "zx2967-wdt", - .of_match_table = of_match_ptr(zx2967_wdt_match), - }, -}; -module_platform_driver(zx2967_wdt_driver); - -module_author("baoyou xie <baoyou.xie@linaro.org>"); -module_description("zte zx2967 watchdog device driver"); -module_license("gpl v2");
|
Watchdog
|
30f1ec70ddf5afd6a8d4c0e1ce9f21a4aea936be
|
arnd bergmann guenter roeck linux roeck us net
|
drivers
|
watchdog
|
bindings, watchdog
|
tty: serial: drop unused efm32 serial driver
|
support for this machine was just removed, so drop the now unused uart driver, too.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
drop unused efm32 serial driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['h', 'kconfig', 'c', 'makefile']
| 5
| 0
| 888
|
--- diff --git a/drivers/tty/serial/kconfig b/drivers/tty/serial/kconfig --- a/drivers/tty/serial/kconfig +++ b/drivers/tty/serial/kconfig -config serial_efm32_uart - tristate "efm32 uart/usart port" - depends on arm && (arch_efm32 || compile_test) - select serial_core - help - this driver support the usart and uart ports on - energy micro's efm32 socs. - -config serial_efm32_uart_console - bool "efm32 uart/usart console support" - depends on serial_efm32_uart=y - select serial_core_console - diff --git a/drivers/tty/serial/makefile b/drivers/tty/serial/makefile --- a/drivers/tty/serial/makefile +++ b/drivers/tty/serial/makefile -obj-$(config_serial_efm32_uart) += efm32-uart.o diff --git a/drivers/tty/serial/efm32-uart.c b/drivers/tty/serial/efm32-uart.c --- a/drivers/tty/serial/efm32-uart.c +++ /dev/null -// spdx-license-identifier: gpl-2.0 -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/io.h> -#include <linux/platform_device.h> -#include <linux/console.h> -#include <linux/sysrq.h> -#include <linux/serial_core.h> -#include <linux/tty_flip.h> -#include <linux/slab.h> -#include <linux/clk.h> -#include <linux/of.h> -#include <linux/of_device.h> - -#include <linux/platform_data/efm32-uart.h> - -#define driver_name "efm32-uart" -#define dev_name "ttyefm" - -#define uartn_ctrl 0x00 -#define uartn_ctrl_sync 0x0001 -#define uartn_ctrl_txbil 0x1000 - -#define uartn_frame 0x04 -#define uartn_frame_databits__mask 0x000f -#define uartn_frame_databits(n) ((n) - 3) -#define uartn_frame_parity__mask 0x0300 -#define uartn_frame_parity_none 0x0000 -#define uartn_frame_parity_even 0x0200 -#define uartn_frame_parity_odd 0x0300 -#define uartn_frame_stopbits_half 0x0000 -#define uartn_frame_stopbits_one 0x1000 -#define uartn_frame_stopbits_two 0x3000 - -#define uartn_cmd 0x0c -#define uartn_cmd_rxen 0x0001 -#define uartn_cmd_rxdis 0x0002 -#define uartn_cmd_txen 0x0004 -#define uartn_cmd_txdis 0x0008 - -#define uartn_status 0x10 -#define uartn_status_txens 0x0002 -#define uartn_status_txc 0x0020 -#define uartn_status_txbl 0x0040 -#define uartn_status_rxdatav 0x0080 - -#define uartn_clkdiv 0x14 - -#define uartn_rxdatax 0x18 -#define uartn_rxdatax_rxdata__mask 0x01ff -#define uartn_rxdatax_perr 0x4000 -#define uartn_rxdatax_ferr 0x8000 -/* - * this is a software only flag used for ignore_status_mask and - * read_status_mask! it's used for breaks that the hardware doesn't report - * explicitly. - */ -#define sw_uartn_rxdatax_berr 0x2000 - -#define uartn_txdata 0x34 - -#define uartn_if 0x40 -#define uartn_if_txc 0x0001 -#define uartn_if_txbl 0x0002 -#define uartn_if_rxdatav 0x0004 -#define uartn_if_rxof 0x0010 - -#define uartn_ifs 0x44 -#define uartn_ifc 0x48 -#define uartn_ien 0x4c - -#define uartn_route 0x54 -#define uartn_route_location__mask 0x0700 -#define uartn_route_location(n) (((n) << 8) & uartn_route_location__mask) -#define uartn_route_rxpen 0x0001 -#define uartn_route_txpen 0x0002 - -struct efm32_uart_port { - struct uart_port port; - unsigned int txirq; - struct clk *clk; - struct efm32_uart_pdata pdata; -}; -#define to_efm_port(_port) container_of(_port, struct efm32_uart_port, port) -#define efm_debug(efm_port, format, arg...) \ - dev_dbg(efm_port->port.dev, format, ##arg) - -static void efm32_uart_write32(struct efm32_uart_port *efm_port, - u32 value, unsigned offset) -{ - writel_relaxed(value, efm_port->port.membase + offset); -} - -static u32 efm32_uart_read32(struct efm32_uart_port *efm_port, - unsigned offset) -{ - return readl_relaxed(efm_port->port.membase + offset); -} - -static unsigned int efm32_uart_tx_empty(struct uart_port *port) -{ - struct efm32_uart_port *efm_port = to_efm_port(port); - u32 status = efm32_uart_read32(efm_port, uartn_status); - - if (status & uartn_status_txc) - return tiocser_temt; - else - return 0; -} - -static void efm32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) -{ - /* sorry, neither handshaking lines nor loop functionallity */ -} - -static unsigned int efm32_uart_get_mctrl(struct uart_port *port) -{ - /* sorry, no handshaking lines available */ - return tiocm_car | tiocm_cts | tiocm_dsr; -} - -static void efm32_uart_stop_tx(struct uart_port *port) -{ - struct efm32_uart_port *efm_port = to_efm_port(port); - u32 ien = efm32_uart_read32(efm_port, uartn_ien); - - efm32_uart_write32(efm_port, uartn_cmd_txdis, uartn_cmd); - ien &= ~(uartn_if_txc | uartn_if_txbl); - efm32_uart_write32(efm_port, ien, uartn_ien); -} - -static void efm32_uart_tx_chars(struct efm32_uart_port *efm_port) -{ - struct uart_port *port = &efm_port->port; - struct circ_buf *xmit = &port->state->xmit; - - while (efm32_uart_read32(efm_port, uartn_status) & - uartn_status_txbl) { - if (port->x_char) { - port->icount.tx++; - efm32_uart_write32(efm_port, port->x_char, - uartn_txdata); - port->x_char = 0; - continue; - } - if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { - port->icount.tx++; - efm32_uart_write32(efm_port, xmit->buf[xmit->tail], - uartn_txdata); - xmit->tail = (xmit->tail + 1) & (uart_xmit_size - 1); - } else - break; - } - - if (uart_circ_chars_pending(xmit) < wakeup_chars) - uart_write_wakeup(port); - - if (!port->x_char && uart_circ_empty(xmit) && - efm32_uart_read32(efm_port, uartn_status) & - uartn_status_txc) - efm32_uart_stop_tx(port); -} - -static void efm32_uart_start_tx(struct uart_port *port) -{ - struct efm32_uart_port *efm_port = to_efm_port(port); - u32 ien; - - efm32_uart_write32(efm_port, - uartn_if_txbl | uartn_if_txc, uartn_ifc); - ien = efm32_uart_read32(efm_port, uartn_ien); - efm32_uart_write32(efm_port, - ien | uartn_if_txbl | uartn_if_txc, uartn_ien); - efm32_uart_write32(efm_port, uartn_cmd_txen, uartn_cmd); - - efm32_uart_tx_chars(efm_port); -} - -static void efm32_uart_stop_rx(struct uart_port *port) -{ - struct efm32_uart_port *efm_port = to_efm_port(port); - - efm32_uart_write32(efm_port, uartn_cmd_rxdis, uartn_cmd); -} - -static void efm32_uart_break_ctl(struct uart_port *port, int ctl) -{ - /* not possible without fiddling with gpios */ -} - -static void efm32_uart_rx_chars(struct efm32_uart_port *efm_port) -{ - struct uart_port *port = &efm_port->port; - - while (efm32_uart_read32(efm_port, uartn_status) & - uartn_status_rxdatav) { - u32 rxdata = efm32_uart_read32(efm_port, uartn_rxdatax); - int flag = 0; - - /* - * this is a reserved bit and i only saw it read as 0. but to be - * sure not to be confused too much by new devices adhere to the - * warning in the reference manual that reserved bits might - * read as 1 in the future. - */ - rxdata &= ~sw_uartn_rxdatax_berr; - - port->icount.rx++; - - if ((rxdata & uartn_rxdatax_ferr) && - !(rxdata & uartn_rxdatax_rxdata__mask)) { - rxdata |= sw_uartn_rxdatax_berr; - port->icount.brk++; - if (uart_handle_break(port)) - continue; - } else if (rxdata & uartn_rxdatax_perr) - port->icount.parity++; - else if (rxdata & uartn_rxdatax_ferr) - port->icount.frame++; - - rxdata &= port->read_status_mask; - - if (rxdata & sw_uartn_rxdatax_berr) - flag = tty_break; - else if (rxdata & uartn_rxdatax_perr) - flag = tty_parity; - else if (rxdata & uartn_rxdatax_ferr) - flag = tty_frame; - else if (uart_handle_sysrq_char(port, - rxdata & uartn_rxdatax_rxdata__mask)) - continue; - - if ((rxdata & port->ignore_status_mask) == 0) - tty_insert_flip_char(&port->state->port, - rxdata & uartn_rxdatax_rxdata__mask, flag); - } -} - -static irqreturn_t efm32_uart_rxirq(int irq, void *data) -{ - struct efm32_uart_port *efm_port = data; - u32 irqflag = efm32_uart_read32(efm_port, uartn_if); - int handled = irq_none; - struct uart_port *port = &efm_port->port; - struct tty_port *tport = &port->state->port; - - spin_lock(&port->lock); - - if (irqflag & uartn_if_rxdatav) { - efm32_uart_write32(efm_port, uartn_if_rxdatav, uartn_ifc); - efm32_uart_rx_chars(efm_port); - - handled = irq_handled; - } - - if (irqflag & uartn_if_rxof) { - efm32_uart_write32(efm_port, uartn_if_rxof, uartn_ifc); - port->icount.overrun++; - tty_insert_flip_char(tport, 0, tty_overrun); - - handled = irq_handled; - } - - spin_unlock(&port->lock); - - tty_flip_buffer_push(tport); - - return handled; -} - -static irqreturn_t efm32_uart_txirq(int irq, void *data) -{ - struct efm32_uart_port *efm_port = data; - u32 irqflag = efm32_uart_read32(efm_port, uartn_if); - - /* txbl doesn't need to be cleared */ - if (irqflag & uartn_if_txc) - efm32_uart_write32(efm_port, uartn_if_txc, uartn_ifc); - - if (irqflag & (uartn_if_txc | uartn_if_txbl)) { - efm32_uart_tx_chars(efm_port); - return irq_handled; - } else - return irq_none; -} - -static int efm32_uart_startup(struct uart_port *port) -{ - struct efm32_uart_port *efm_port = to_efm_port(port); - int ret; - - ret = clk_enable(efm_port->clk); - if (ret) { - efm_debug(efm_port, "failed to enable clk "); - goto err_clk_enable; - } - port->uartclk = clk_get_rate(efm_port->clk); - - /* enable pins at configured location */ - efm32_uart_write32(efm_port, - uartn_route_location(efm_port->pdata.location) | - uartn_route_rxpen | uartn_route_txpen, - uartn_route); - - ret = request_irq(port->irq, efm32_uart_rxirq, 0, - driver_name, efm_port); - if (ret) { - efm_debug(efm_port, "failed to register rxirq "); - goto err_request_irq_rx; - } - - /* disable all irqs */ - efm32_uart_write32(efm_port, 0, uartn_ien); - - ret = request_irq(efm_port->txirq, efm32_uart_txirq, 0, - driver_name, efm_port); - if (ret) { - efm_debug(efm_port, "failed to register txirq "); - free_irq(port->irq, efm_port); -err_request_irq_rx: - - clk_disable(efm_port->clk); - } else { - efm32_uart_write32(efm_port, - uartn_if_rxdatav | uartn_if_rxof, uartn_ien); - efm32_uart_write32(efm_port, uartn_cmd_rxen, uartn_cmd); - } - -err_clk_enable: - return ret; -} - -static void efm32_uart_shutdown(struct uart_port *port) -{ - struct efm32_uart_port *efm_port = to_efm_port(port); - - efm32_uart_write32(efm_port, 0, uartn_ien); - free_irq(port->irq, efm_port); - - clk_disable(efm_port->clk); -} - -static void efm32_uart_set_termios(struct uart_port *port, - struct ktermios *new, struct ktermios *old) -{ - struct efm32_uart_port *efm_port = to_efm_port(port); - unsigned long flags; - unsigned baud; - u32 clkdiv; - u32 frame = 0; - - /* no modem control lines */ - new->c_cflag &= ~(crtscts | cmspar); - - baud = uart_get_baud_rate(port, new, old, - div_round_closest(port->uartclk, 16 * 8192), - div_round_closest(port->uartclk, 16)); - - switch (new->c_cflag & csize) { - case cs5: - frame |= uartn_frame_databits(5); - break; - case cs6: - frame |= uartn_frame_databits(6); - break; - case cs7: - frame |= uartn_frame_databits(7); - break; - case cs8: - frame |= uartn_frame_databits(8); - break; - } - - if (new->c_cflag & cstopb) - /* the receiver only verifies the first stop bit */ - frame |= uartn_frame_stopbits_two; - else - frame |= uartn_frame_stopbits_one; - - if (new->c_cflag & parenb) { - if (new->c_cflag & parodd) - frame |= uartn_frame_parity_odd; - else - frame |= uartn_frame_parity_even; - } else - frame |= uartn_frame_parity_none; - - /* - * the 6 lowest bits of clkdiv are dc, bit 6 has value 0.25. - * port->uartclk <= 14e6, so 4 * port->uartclk doesn't overflow. - */ - clkdiv = (div_round_closest(4 * port->uartclk, 16 * baud) - 4) << 6; - - spin_lock_irqsave(&port->lock, flags); - - efm32_uart_write32(efm_port, - uartn_cmd_txdis | uartn_cmd_rxdis, uartn_cmd); - - port->read_status_mask = uartn_rxdatax_rxdata__mask; - if (new->c_iflag & inpck) - port->read_status_mask |= - uartn_rxdatax_ferr | uartn_rxdatax_perr; - if (new->c_iflag & (ignbrk | brkint | parmrk)) - port->read_status_mask |= sw_uartn_rxdatax_berr; - - port->ignore_status_mask = 0; - if (new->c_iflag & ignpar) - port->ignore_status_mask |= - uartn_rxdatax_ferr | uartn_rxdatax_perr; - if (new->c_iflag & ignbrk) - port->ignore_status_mask |= sw_uartn_rxdatax_berr; - - uart_update_timeout(port, new->c_cflag, baud); - - efm32_uart_write32(efm_port, uartn_ctrl_txbil, uartn_ctrl); - efm32_uart_write32(efm_port, frame, uartn_frame); - efm32_uart_write32(efm_port, clkdiv, uartn_clkdiv); - - efm32_uart_write32(efm_port, uartn_cmd_txen | uartn_cmd_rxen, - uartn_cmd); - - spin_unlock_irqrestore(&port->lock, flags); -} - -static const char *efm32_uart_type(struct uart_port *port) -{ - return port->type == port_efmuart ? "efm32-uart" : null; -} - -static void efm32_uart_release_port(struct uart_port *port) -{ - struct efm32_uart_port *efm_port = to_efm_port(port); - - clk_unprepare(efm_port->clk); - clk_put(efm_port->clk); - iounmap(port->membase); -} - -static int efm32_uart_request_port(struct uart_port *port) -{ - struct efm32_uart_port *efm_port = to_efm_port(port); - int ret; - - port->membase = ioremap(port->mapbase, 60); - if (!efm_port->port.membase) { - ret = -enomem; - efm_debug(efm_port, "failed to remap "); - goto err_ioremap; - } - - efm_port->clk = clk_get(port->dev, null); - if (is_err(efm_port->clk)) { - ret = ptr_err(efm_port->clk); - efm_debug(efm_port, "failed to get clock "); - goto err_clk_get; - } - - ret = clk_prepare(efm_port->clk); - if (ret) { - clk_put(efm_port->clk); -err_clk_get: - - iounmap(port->membase); -err_ioremap: - return ret; - } - return 0; -} - -static void efm32_uart_config_port(struct uart_port *port, int type) -{ - if (type & uart_config_type && - !efm32_uart_request_port(port)) - port->type = port_efmuart; -} - -static int efm32_uart_verify_port(struct uart_port *port, - struct serial_struct *serinfo) -{ - int ret = 0; - - if (serinfo->type != port_unknown && serinfo->type != port_efmuart) - ret = -einval; - - return ret; -} - -static const struct uart_ops efm32_uart_pops = { - .tx_empty = efm32_uart_tx_empty, - .set_mctrl = efm32_uart_set_mctrl, - .get_mctrl = efm32_uart_get_mctrl, - .stop_tx = efm32_uart_stop_tx, - .start_tx = efm32_uart_start_tx, - .stop_rx = efm32_uart_stop_rx, - .break_ctl = efm32_uart_break_ctl, - .startup = efm32_uart_startup, - .shutdown = efm32_uart_shutdown, - .set_termios = efm32_uart_set_termios, - .type = efm32_uart_type, - .release_port = efm32_uart_release_port, - .request_port = efm32_uart_request_port, - .config_port = efm32_uart_config_port, - .verify_port = efm32_uart_verify_port, -}; - -static struct efm32_uart_port *efm32_uart_ports[5]; - -#ifdef config_serial_efm32_uart_console -static void efm32_uart_console_putchar(struct uart_port *port, int ch) -{ - struct efm32_uart_port *efm_port = to_efm_port(port); - unsigned int timeout = 0x400; - u32 status; - - while (1) { - status = efm32_uart_read32(efm_port, uartn_status); - - if (status & uartn_status_txbl) - break; - if (!timeout--) - return; - } - efm32_uart_write32(efm_port, ch, uartn_txdata); -} - -static void efm32_uart_console_write(struct console *co, const char *s, - unsigned int count) -{ - struct efm32_uart_port *efm_port = efm32_uart_ports[co->index]; - u32 status = efm32_uart_read32(efm_port, uartn_status); - unsigned int timeout = 0x400; - - if (!(status & uartn_status_txens)) - efm32_uart_write32(efm_port, uartn_cmd_txen, uartn_cmd); - - uart_console_write(&efm_port->port, s, count, - efm32_uart_console_putchar); - - /* wait for the transmitter to become empty */ - while (1) { - u32 status = efm32_uart_read32(efm_port, uartn_status); - if (status & uartn_status_txc) - break; - if (!timeout--) - break; - } - - if (!(status & uartn_status_txens)) - efm32_uart_write32(efm_port, uartn_cmd_txdis, uartn_cmd); -} - -static void efm32_uart_console_get_options(struct efm32_uart_port *efm_port, - int *baud, int *parity, int *bits) -{ - u32 ctrl = efm32_uart_read32(efm_port, uartn_ctrl); - u32 route, clkdiv, frame; - - if (ctrl & uartn_ctrl_sync) - /* not operating in async mode */ - return; - - route = efm32_uart_read32(efm_port, uartn_route); - if (!(route & uartn_route_txpen)) - /* tx pin not routed */ - return; - - clkdiv = efm32_uart_read32(efm_port, uartn_clkdiv); - - *baud = div_round_closest(4 * efm_port->port.uartclk, - 16 * (4 + (clkdiv >> 6))); - - frame = efm32_uart_read32(efm_port, uartn_frame); - switch (frame & uartn_frame_parity__mask) { - case uartn_frame_parity_odd: - *parity = 'o'; - break; - case uartn_frame_parity_even: - *parity = 'e'; - break; - default: - *parity = 'n'; - } - - *bits = (frame & uartn_frame_databits__mask) - - uartn_frame_databits(4) + 4; - - efm_debug(efm_port, "get_opts: options=%d%c%d ", - *baud, *parity, *bits); -} - -static int efm32_uart_console_setup(struct console *co, char *options) -{ - struct efm32_uart_port *efm_port; - int baud = 115200; - int bits = 8; - int parity = 'n'; - int flow = 'n'; - int ret; - - if (co->index < 0 || co->index >= array_size(efm32_uart_ports)) { - unsigned i; - for (i = 0; i < array_size(efm32_uart_ports); ++i) { - if (efm32_uart_ports[i]) { - pr_warn("efm32-console: fall back to console index %u (from %hhi) ", - i, co->index); - co->index = i; - break; - } - } - } - - efm_port = efm32_uart_ports[co->index]; - if (!efm_port) { - pr_warn("efm32-console: no port at %d ", co->index); - return -enodev; - } - - ret = clk_prepare(efm_port->clk); - if (ret) { - dev_warn(efm_port->port.dev, - "console: clk_prepare failed: %d ", ret); - return ret; - } - - efm_port->port.uartclk = clk_get_rate(efm_port->clk); - - if (options) - uart_parse_options(options, &baud, &parity, &bits, &flow); - else - efm32_uart_console_get_options(efm_port, - &baud, &parity, &bits); - - return uart_set_options(&efm_port->port, co, baud, parity, bits, flow); -} - -static struct uart_driver efm32_uart_reg; - -static struct console efm32_uart_console = { - .name = dev_name, - .write = efm32_uart_console_write, - .device = uart_console_device, - .setup = efm32_uart_console_setup, - .flags = con_printbuffer, - .index = -1, - .data = &efm32_uart_reg, -}; - -#else -#define efm32_uart_console (*(struct console *)null) -#endif /* ifdef config_serial_efm32_uart_console / else */ - -static struct uart_driver efm32_uart_reg = { - .owner = this_module, - .driver_name = driver_name, - .dev_name = dev_name, - .nr = array_size(efm32_uart_ports), - .cons = &efm32_uart_console, -}; - -static int efm32_uart_probe_dt(struct platform_device *pdev, - struct efm32_uart_port *efm_port) -{ - struct device_node *np = pdev->dev.of_node; - u32 location; - int ret; - - if (!np) - return 1; - - ret = of_property_read_u32(np, "energymicro,location", &location); - - if (ret) - /* fall back to wrongly namespaced property */ - ret = of_property_read_u32(np, "efm32,location", &location); - - if (ret) - /* fall back to old and (wrongly) generic property "location" */ - ret = of_property_read_u32(np, "location", &location); - - if (!ret) { - if (location > 5) { - dev_err(&pdev->dev, "invalid location "); - return -einval; - } - efm_debug(efm_port, "using location %u ", location); - efm_port->pdata.location = location; - } else { - efm_debug(efm_port, "fall back to location 0 "); - } - - ret = of_alias_get_id(np, "serial"); - if (ret < 0) { - dev_err(&pdev->dev, "failed to get alias id: %d ", ret); - return ret; - } else { - efm_port->port.line = ret; - return 0; - } - -} - -static int efm32_uart_probe(struct platform_device *pdev) -{ - struct efm32_uart_port *efm_port; - struct resource *res; - unsigned int line; - int ret; - - efm_port = kzalloc(sizeof(*efm_port), gfp_kernel); - if (!efm_port) { - dev_dbg(&pdev->dev, "failed to allocate private data "); - return -enomem; - } - - res = platform_get_resource(pdev, ioresource_mem, 0); - if (!res) { - ret = -enodev; - dev_dbg(&pdev->dev, "failed to determine base address "); - goto err_get_base; - } - - if (resource_size(res) < 60) { - ret = -einval; - dev_dbg(&pdev->dev, "memory resource too small "); - goto err_too_small; - } - - ret = platform_get_irq(pdev, 0); - if (ret <= 0) { - dev_dbg(&pdev->dev, "failed to get rx irq "); - goto err_get_rxirq; - } - - efm_port->port.irq = ret; - - ret = platform_get_irq(pdev, 1); - if (ret <= 0) - ret = efm_port->port.irq + 1; - - efm_port->txirq = ret; - - efm_port->port.dev = &pdev->dev; - efm_port->port.mapbase = res->start; - efm_port->port.type = port_efmuart; - efm_port->port.iotype = upio_mem32; - efm_port->port.fifosize = 2; - efm_port->port.has_sysrq = is_enabled(config_serial_efm32_uart_console); - efm_port->port.ops = &efm32_uart_pops; - efm_port->port.flags = upf_boot_autoconf; - - ret = efm32_uart_probe_dt(pdev, efm_port); - if (ret > 0) { - /* not created by device tree */ - const struct efm32_uart_pdata *pdata = dev_get_platdata(&pdev->dev); - - efm_port->port.line = pdev->id; - - if (pdata) - efm_port->pdata = *pdata; - } else if (ret < 0) - goto err_probe_dt; - - line = efm_port->port.line; - - if (line >= 0 && line < array_size(efm32_uart_ports)) - efm32_uart_ports[line] = efm_port; - - ret = uart_add_one_port(&efm32_uart_reg, &efm_port->port); - if (ret) { - dev_dbg(&pdev->dev, "failed to add port: %d ", ret); - - if (line >= 0 && line < array_size(efm32_uart_ports)) - efm32_uart_ports[line] = null; -err_probe_dt: -err_get_rxirq: -err_too_small: -err_get_base: - kfree(efm_port); - } else { - platform_set_drvdata(pdev, efm_port); - dev_dbg(&pdev->dev, "\o/ "); - } - - return ret; -} - -static int efm32_uart_remove(struct platform_device *pdev) -{ - struct efm32_uart_port *efm_port = platform_get_drvdata(pdev); - unsigned int line = efm_port->port.line; - - uart_remove_one_port(&efm32_uart_reg, &efm_port->port); - - if (line >= 0 && line < array_size(efm32_uart_ports)) - efm32_uart_ports[line] = null; - - kfree(efm_port); - - return 0; -} - -static const struct of_device_id efm32_uart_dt_ids[] = { - { - .compatible = "energymicro,efm32-uart", - }, { - /* doesn't follow the "vendor,device" scheme, don't use */ - .compatible = "efm32,uart", - }, { - /* sentinel */ - } -}; -module_device_table(of, efm32_uart_dt_ids); - -static struct platform_driver efm32_uart_driver = { - .probe = efm32_uart_probe, - .remove = efm32_uart_remove, - - .driver = { - .name = driver_name, - .of_match_table = efm32_uart_dt_ids, - }, -}; - -static int __init efm32_uart_init(void) -{ - int ret; - - ret = uart_register_driver(&efm32_uart_reg); - if (ret) - return ret; - - ret = platform_driver_register(&efm32_uart_driver); - if (ret) - uart_unregister_driver(&efm32_uart_reg); - - pr_info("efm32 uart/usart driver "); - - return ret; -} -module_init(efm32_uart_init); - -static void __exit efm32_uart_exit(void) -{ - platform_driver_unregister(&efm32_uart_driver); - uart_unregister_driver(&efm32_uart_reg); -} -module_exit(efm32_uart_exit); - -module_author("uwe kleine-koenig <u.kleine-koenig@pengutronix.de>"); -module_description("efm32 uart/usart driver"); -module_license("gpl v2"); -module_alias("platform:" driver_name); diff --git a/include/linux/platform_data/efm32-uart.h b/include/linux/platform_data/efm32-uart.h --- a/include/linux/platform_data/efm32-uart.h +++ /dev/null -/* spdx-license-identifier: gpl-2.0 */ -/* - * - * - */ -#ifndef __linux_platform_data_efm32_uart_h__ -#define __linux_platform_data_efm32_uart_h__ - -#include <linux/types.h> - -/** - * struct efm32_uart_pdata - * @location: pinmux location for the i/o pins (to be written to the route - * register) - */ -struct efm32_uart_pdata { - u8 location; -}; -#endif /* ifndef __linux_platform_data_efm32_uart_h__ */ diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h -/* energy micro efm32 soc */ -#define port_efmuart 100 -
|
Serial
|
429b29aef7f841086949c7359f9c3ccb051e7ea3
|
uwe kleine k nig
|
include
|
uapi
|
linux, platform_data, serial
|
tty: serial: cpm_uart: add udbg support for enabling xmon
|
in order to use xmon with powerpc 8xx, the serial driver must provide udbg_putc() and udpb_getc().
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add udbg support for enabling xmon
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['cpm_uart']
|
['c']
| 1
| 39
| 1
|
--- diff --git a/drivers/tty/serial/cpm_uart/cpm_uart_core.c b/drivers/tty/serial/cpm_uart/cpm_uart_core.c --- a/drivers/tty/serial/cpm_uart/cpm_uart_core.c +++ b/drivers/tty/serial/cpm_uart/cpm_uart_core.c + +static struct uart_port *udbg_port; + +static void udbg_cpm_putc(char c) +{ + if (c == ' ') + cpm_put_poll_char(udbg_port, ' '); + cpm_put_poll_char(udbg_port, c); +} + +static int udbg_cpm_getc_poll(void) +{ + int c = cpm_get_poll_char(udbg_port); + + return c == no_poll_char ? -1 : c; +} + +static int udbg_cpm_getc(void) +{ + int c; + + while ((c = udbg_cpm_getc_poll()) == -1) + cpu_relax(); + return c; +} + - udbg_putc = null; +#ifdef config_console_poll + if (!udbg_port) +#endif + udbg_putc = null; +#ifdef config_console_poll + if (!udbg_port) { + udbg_port = &pinfo->port; + udbg_putc = udbg_cpm_putc; + udbg_getc = udbg_cpm_getc; + udbg_getc_poll = udbg_cpm_getc_poll; + } +#endif +
|
Serial
|
a60526097f42eb98760d3c63c5de63fab309fe1a
|
christophe leroy
|
drivers
|
tty
|
cpm_uart, serial
|
serial: ifx6x60: remove driver for deprecated platform
|
intel moorestown and medfield are quite old intel atom based 32-bit platforms, which were in limited use in some android phones, tablets and consumer electronics more than eight years ago.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove driver for deprecated platform
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['ifx6x60']
|
['h', 'kconfig', 'c', 'makefile']
| 5
| 0
| 1,528
|
--- diff --git a/drivers/tty/serial/kconfig b/drivers/tty/serial/kconfig --- a/drivers/tty/serial/kconfig +++ b/drivers/tty/serial/kconfig -config serial_ifx6x60 - tristate "spi protocol driver for infineon 6x60 modem (experimental)" - depends on gpiolib || compile_test - depends on spi && has_dma - help - support for the ifx6x60 modem devices on intel mid platforms. - diff --git a/drivers/tty/serial/makefile b/drivers/tty/serial/makefile --- a/drivers/tty/serial/makefile +++ b/drivers/tty/serial/makefile -obj-$(config_serial_ifx6x60) += ifx6x60.o diff --git a/drivers/tty/serial/ifx6x60.c b/drivers/tty/serial/ifx6x60.c --- a/drivers/tty/serial/ifx6x60.c +++ /dev/null -// spdx-license-identifier: gpl-2.0 -/**************************************************************************** - * - * driver for the ifx 6x60 spi modem. - * - * copyright (c) 2008 option international - * copyright (c) 2008 filip aben <f.aben@option.com> - * denis joseph barrow <d.barow@option.com> - * jan dumon <j.dumon@option.com> - * - * copyright (c) 2009, 2010 intel corp - * russ gorby <russ.gorby@intel.com> - * - * driver modified by intel from option gtm501l_spi.c - * - * notes - * o the driver currently assumes a single device only. if you need to - * change this then look for saved_ifx_dev and add a device lookup - * o the driver is intended to be big-endian safe but has never been - * tested that way (no suitable hardware). there are a couple of fixme - * notes by areas that may need addressing - * o some of the gpio naming/setup assumptions may need revisiting if - * you need to use this driver for another platform. - * - *****************************************************************************/ -#include <linux/dma-mapping.h> -#include <linux/module.h> -#include <linux/termios.h> -#include <linux/tty.h> -#include <linux/device.h> -#include <linux/spi/spi.h> -#include <linux/kfifo.h> -#include <linux/tty_flip.h> -#include <linux/timer.h> -#include <linux/serial.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/rfkill.h> -#include <linux/fs.h> -#include <linux/ip.h> -#include <linux/dmapool.h> -#include <linux/gpio/consumer.h> -#include <linux/sched.h> -#include <linux/time.h> -#include <linux/wait.h> -#include <linux/pm.h> -#include <linux/pm_runtime.h> -#include <linux/spi/ifx_modem.h> -#include <linux/delay.h> -#include <linux/reboot.h> - -#include "ifx6x60.h" - -#define ifx_spi_more_mask 0x10 -#define ifx_spi_more_bit 4 /* bit position in u8 */ -#define ifx_spi_cts_bit 6 /* bit position in u8 */ -#define ifx_spi_mode spi_mode_1 -#define ifx_spi_tty_id 0 -#define ifx_spi_timeout_sec 2 -#define ifx_spi_header_0 (-1) -#define ifx_spi_header_f (-2) - -#define po_post_delay 200 - -/* forward reference */ -static void ifx_spi_handle_srdy(struct ifx_spi_device *ifx_dev); -static int ifx_modem_reboot_callback(struct notifier_block *nfb, - unsigned long event, void *data); -static int ifx_modem_power_off(struct ifx_spi_device *ifx_dev); - -/* local variables */ -static int spi_bpw = 16; /* 8, 16 or 32 bit word length */ -static struct tty_driver *tty_drv; -static struct ifx_spi_device *saved_ifx_dev; -static struct lock_class_key ifx_spi_key; - -static struct notifier_block ifx_modem_reboot_notifier_block = { - .notifier_call = ifx_modem_reboot_callback, -}; - -static int ifx_modem_power_off(struct ifx_spi_device *ifx_dev) -{ - gpiod_set_value(ifx_dev->gpio.pmu_reset, 1); - msleep(po_post_delay); - - return 0; -} - -static int ifx_modem_reboot_callback(struct notifier_block *nfb, - unsigned long event, void *data) -{ - if (saved_ifx_dev) - ifx_modem_power_off(saved_ifx_dev); - else - pr_warn("no ifx modem active; "); - - return notify_ok; -} - -/* gpio/gpe settings */ - -/** - * mrdy_set_high - set mrdy gpio - * @ifx: device we are controlling - * - */ -static inline void mrdy_set_high(struct ifx_spi_device *ifx) -{ - gpiod_set_value(ifx->gpio.mrdy, 1); -} - -/** - * mrdy_set_low - clear mrdy gpio - * @ifx: device we are controlling - * - */ -static inline void mrdy_set_low(struct ifx_spi_device *ifx) -{ - gpiod_set_value(ifx->gpio.mrdy, 0); -} - -/** - * ifx_spi_power_state_set - * @ifx_dev: our spi device - * @val: bits to set - * - * set bit in power status and signal power system if status becomes non-0 - */ -static void -ifx_spi_power_state_set(struct ifx_spi_device *ifx_dev, unsigned char val) -{ - unsigned long flags; - - spin_lock_irqsave(&ifx_dev->power_lock, flags); - - /* - * if power status is already non-0, just update, else - * tell power system - */ - if (!ifx_dev->power_status) - pm_runtime_get(&ifx_dev->spi_dev->dev); - ifx_dev->power_status |= val; - - spin_unlock_irqrestore(&ifx_dev->power_lock, flags); -} - -/** - * ifx_spi_power_state_clear - clear power bit - * @ifx_dev: our spi device - * @val: bits to clear - * - * clear bit in power status and signal power system if status becomes 0 - */ -static void -ifx_spi_power_state_clear(struct ifx_spi_device *ifx_dev, unsigned char val) -{ - unsigned long flags; - - spin_lock_irqsave(&ifx_dev->power_lock, flags); - - if (ifx_dev->power_status) { - ifx_dev->power_status &= ~val; - if (!ifx_dev->power_status) - pm_runtime_put(&ifx_dev->spi_dev->dev); - } - - spin_unlock_irqrestore(&ifx_dev->power_lock, flags); -} - -/** - * swap_buf_8 - * @buf: our buffer - * @len : number of bytes (not words) in the buffer - * @end: end of buffer - * - * swap the contents of a buffer into big endian format - */ -static inline void swap_buf_8(unsigned char *buf, int len, void *end) -{ - /* don't swap buffer if spi word width is 8 bits */ - return; -} - -/** - * swap_buf_16 - * @buf: our buffer - * @len : number of bytes (not words) in the buffer - * @end: end of buffer - * - * swap the contents of a buffer into big endian format - */ -static inline void swap_buf_16(unsigned char *buf, int len, void *end) -{ - int n; - - u16 *buf_16 = (u16 *)buf; - len = ((len + 1) >> 1); - if ((void *)&buf_16[len] > end) { - pr_err("swap_buf_16: swap exceeds boundary (%p > %p)!", - &buf_16[len], end); - return; - } - for (n = 0; n < len; n++) { - *buf_16 = cpu_to_be16(*buf_16); - buf_16++; - } -} - -/** - * swap_buf_32 - * @buf: our buffer - * @len : number of bytes (not words) in the buffer - * @end: end of buffer - * - * swap the contents of a buffer into big endian format - */ -static inline void swap_buf_32(unsigned char *buf, int len, void *end) -{ - int n; - - u32 *buf_32 = (u32 *)buf; - len = (len + 3) >> 2; - - if ((void *)&buf_32[len] > end) { - pr_err("swap_buf_32: swap exceeds boundary (%p > %p)! ", - &buf_32[len], end); - return; - } - for (n = 0; n < len; n++) { - *buf_32 = cpu_to_be32(*buf_32); - buf_32++; - } -} - -/** - * mrdy_assert - assert mrdy line - * @ifx_dev: our spi device - * - * assert mrdy and set timer to wait for srdy interrupt, if srdy is low - * now. - * - * fixme: can srdy even go high as we are running this code ? - */ -static void mrdy_assert(struct ifx_spi_device *ifx_dev) -{ - int val = gpiod_get_value(ifx_dev->gpio.srdy); - if (!val) { - if (!test_and_set_bit(ifx_spi_state_timer_pending, - &ifx_dev->flags)) { - mod_timer(&ifx_dev->spi_timer,jiffies + ifx_spi_timeout_sec*hz); - - } - } - ifx_spi_power_state_set(ifx_dev, ifx_spi_power_data_pending); - mrdy_set_high(ifx_dev); -} - -/** - * ifx_spi_timeout - spi timeout - * @t: timer in our spi device - * - * the spi has timed out: hang up the tty. users will then see a hangup - * and error events. - */ -static void ifx_spi_timeout(struct timer_list *t) -{ - struct ifx_spi_device *ifx_dev = from_timer(ifx_dev, t, spi_timer); - - dev_warn(&ifx_dev->spi_dev->dev, "*** spi timeout ***"); - tty_port_tty_hangup(&ifx_dev->tty_port, false); - mrdy_set_low(ifx_dev); - clear_bit(ifx_spi_state_timer_pending, &ifx_dev->flags); -} - -/* char/tty operations */ - -/** - * ifx_spi_tiocmget - get modem lines - * @tty: our tty device - * - * map the signal state into linux modem flags and report the value - * in linux terms - */ -static int ifx_spi_tiocmget(struct tty_struct *tty) -{ - unsigned int value; - struct ifx_spi_device *ifx_dev = tty->driver_data; - - value = - (test_bit(ifx_spi_rts, &ifx_dev->signal_state) ? tiocm_rts : 0) | - (test_bit(ifx_spi_dtr, &ifx_dev->signal_state) ? tiocm_dtr : 0) | - (test_bit(ifx_spi_cts, &ifx_dev->signal_state) ? tiocm_cts : 0) | - (test_bit(ifx_spi_dsr, &ifx_dev->signal_state) ? tiocm_dsr : 0) | - (test_bit(ifx_spi_dcd, &ifx_dev->signal_state) ? tiocm_car : 0) | - (test_bit(ifx_spi_ri, &ifx_dev->signal_state) ? tiocm_rng : 0); - return value; -} - -/** - * ifx_spi_tiocmset - set modem bits - * @tty: the tty structure - * @set: bits to set - * @clear: bits to clear - * - * the ifx6x60 only supports dtr and rts. set them accordingly - * and flag that an update to the modem is needed. - * - * fixme: do we need to kick the tranfers when we do this ? - */ -static int ifx_spi_tiocmset(struct tty_struct *tty, - unsigned int set, unsigned int clear) -{ - struct ifx_spi_device *ifx_dev = tty->driver_data; - - if (set & tiocm_rts) - set_bit(ifx_spi_rts, &ifx_dev->signal_state); - if (set & tiocm_dtr) - set_bit(ifx_spi_dtr, &ifx_dev->signal_state); - if (clear & tiocm_rts) - clear_bit(ifx_spi_rts, &ifx_dev->signal_state); - if (clear & tiocm_dtr) - clear_bit(ifx_spi_dtr, &ifx_dev->signal_state); - - set_bit(ifx_spi_update, &ifx_dev->signal_state); - return 0; -} - -/** - * ifx_spi_open - called on tty open - * @tty: our tty device - * @filp: file handle being associated with the tty - * - * open the tty interface. we let the tty_port layer do all the work - * for us. - * - * fixme: remove single device assumption and saved_ifx_dev - */ -static int ifx_spi_open(struct tty_struct *tty, struct file *filp) -{ - return tty_port_open(&saved_ifx_dev->tty_port, tty, filp); -} - -/** - * ifx_spi_close - called when our tty closes - * @tty: the tty being closed - * @filp: the file handle being closed - * - * perform the close of the tty. we use the tty_port layer to do all - * our hard work. - */ -static void ifx_spi_close(struct tty_struct *tty, struct file *filp) -{ - struct ifx_spi_device *ifx_dev = tty->driver_data; - tty_port_close(&ifx_dev->tty_port, tty, filp); - /* fixme: should we do an ifx_spi_reset here ? */ -} - -/** - * ifx_decode_spi_header - decode received header - * @buffer: the received data - * @length: decoded length - * @more: decoded more flag - * @received_cts: status of cts we received - * - * note how received_cts is handled -- if header is all f it is left - * the same as it was, if header is all 0 it is set to 0 otherwise it is - * taken from the incoming header. - * - * fixme: endianness - */ -static int ifx_spi_decode_spi_header(unsigned char *buffer, int *length, - unsigned char *more, unsigned char *received_cts) -{ - u16 h1; - u16 h2; - u16 *in_buffer = (u16 *)buffer; - - h1 = *in_buffer; - h2 = *(in_buffer+1); - - if (h1 == 0 && h2 == 0) { - *received_cts = 0; - *more = 0; - return ifx_spi_header_0; - } else if (h1 == 0xffff && h2 == 0xffff) { - *more = 0; - /* spi_slave_cts remains as it was */ - return ifx_spi_header_f; - } - - *length = h1 & 0xfff; /* upper bits of byte are flags */ - *more = (buffer[1] >> ifx_spi_more_bit) & 1; - *received_cts = (buffer[3] >> ifx_spi_cts_bit) & 1; - return 0; -} - -/** - * ifx_setup_spi_header - set header fields - * @txbuffer: pointer to start of spi buffer - * @tx_count: bytes - * @more: indicate if more to follow - * - * format up an spi header for a transfer - * - * fixme: endianness? - */ -static void ifx_spi_setup_spi_header(unsigned char *txbuffer, int tx_count, - unsigned char more) -{ - *(u16 *)(txbuffer) = tx_count; - *(u16 *)(txbuffer+2) = ifx_spi_payload_size; - txbuffer[1] |= (more << ifx_spi_more_bit) & ifx_spi_more_mask; -} - -/** - * ifx_spi_prepare_tx_buffer - prepare transmit frame - * @ifx_dev: our spi device - * - * the transmit buffr needs a header and various other bits of - * information followed by as much data as we can pull from the fifo - * and transfer. this function formats up a suitable buffer in the - * ifx_dev->tx_buffer - * - * fixme: performance - should we wake the tty when the queue is half - * empty ? - */ -static int ifx_spi_prepare_tx_buffer(struct ifx_spi_device *ifx_dev) -{ - int temp_count; - int queue_length; - int tx_count; - unsigned char *tx_buffer; - - tx_buffer = ifx_dev->tx_buffer; - - /* make room for required spi header */ - tx_buffer += ifx_spi_header_overhead; - tx_count = ifx_spi_header_overhead; - - /* clear to signal no more data if this turns out to be the - * last buffer sent in a sequence */ - ifx_dev->spi_more = 0; - - /* if modem cts is set, just send empty buffer */ - if (!ifx_dev->spi_slave_cts) { - /* see if there's tx data */ - queue_length = kfifo_len(&ifx_dev->tx_fifo); - if (queue_length != 0) { - /* data to mux -- see if there's room for it */ - temp_count = min(queue_length, ifx_spi_payload_size); - temp_count = kfifo_out_locked(&ifx_dev->tx_fifo, - tx_buffer, temp_count, - &ifx_dev->fifo_lock); - - /* update buffer pointer and data count in message */ - tx_buffer += temp_count; - tx_count += temp_count; - if (temp_count == queue_length) - /* poke port to get more data */ - tty_port_tty_wakeup(&ifx_dev->tty_port); - else /* more data in port, use next spi message */ - ifx_dev->spi_more = 1; - } - } - /* have data and info for header -- set up spi header in buffer */ - /* spi header needs payload size, not entire buffer size */ - ifx_spi_setup_spi_header(ifx_dev->tx_buffer, - tx_count-ifx_spi_header_overhead, - ifx_dev->spi_more); - /* swap actual data in the buffer */ - ifx_dev->swap_buf((ifx_dev->tx_buffer), tx_count, - &ifx_dev->tx_buffer[ifx_spi_transfer_size]); - return tx_count; -} - -/** - * ifx_spi_write - line discipline write - * @tty: our tty device - * @buf: pointer to buffer to write (kernel space) - * @count: size of buffer - * - * write the characters we have been given into the fifo. if the device - * is not active then activate it, when the srdy line is asserted back - * this will commence i/o - */ -static int ifx_spi_write(struct tty_struct *tty, const unsigned char *buf, - int count) -{ - struct ifx_spi_device *ifx_dev = tty->driver_data; - unsigned char *tmp_buf = (unsigned char *)buf; - unsigned long flags; - bool is_fifo_empty; - int tx_count; - - spin_lock_irqsave(&ifx_dev->fifo_lock, flags); - is_fifo_empty = kfifo_is_empty(&ifx_dev->tx_fifo); - tx_count = kfifo_in(&ifx_dev->tx_fifo, tmp_buf, count); - spin_unlock_irqrestore(&ifx_dev->fifo_lock, flags); - if (is_fifo_empty) - mrdy_assert(ifx_dev); - - return tx_count; -} - -/** - * ifx_spi_chars_in_buffer - line discipline helper - * @tty: our tty device - * - * report how much data we can accept before we drop bytes. as we use - * a simple fifo this is nice and easy. - */ -static int ifx_spi_write_room(struct tty_struct *tty) -{ - struct ifx_spi_device *ifx_dev = tty->driver_data; - return ifx_spi_fifo_size - kfifo_len(&ifx_dev->tx_fifo); -} - -/** - * ifx_spi_chars_in_buffer - line discipline helper - * @tty: our tty device - * - * report how many characters we have buffered. in our case this is the - * number of bytes sitting in our transmit fifo. - */ -static int ifx_spi_chars_in_buffer(struct tty_struct *tty) -{ - struct ifx_spi_device *ifx_dev = tty->driver_data; - return kfifo_len(&ifx_dev->tx_fifo); -} - -/** - * ifx_port_hangup - * @tty: our tty - * - * tty port hang up. called when tty_hangup processing is invoked either - * by loss of carrier, or by software (eg vhangup). serialized against - * activate/shutdown by the tty layer. - */ -static void ifx_spi_hangup(struct tty_struct *tty) -{ - struct ifx_spi_device *ifx_dev = tty->driver_data; - tty_port_hangup(&ifx_dev->tty_port); -} - -/** - * ifx_port_activate - * @port: our tty port - * @tty: our tty device - * - * tty port activate method - called for first open. serialized - * with hangup and shutdown by the tty layer. - */ -static int ifx_port_activate(struct tty_port *port, struct tty_struct *tty) -{ - struct ifx_spi_device *ifx_dev = - container_of(port, struct ifx_spi_device, tty_port); - - /* clear any old data; can't do this in 'close' */ - kfifo_reset(&ifx_dev->tx_fifo); - - /* clear any flag which may be set in port shutdown procedure */ - clear_bit(ifx_spi_state_io_in_progress, &ifx_dev->flags); - clear_bit(ifx_spi_state_io_ready, &ifx_dev->flags); - - /* put port data into this tty */ - tty->driver_data = ifx_dev; - - /* set flag to allows data transfer */ - set_bit(ifx_spi_state_io_available, &ifx_dev->flags); - - return 0; -} - -/** - * ifx_port_shutdown - * @port: our tty port - * - * tty port shutdown method - called for last port close. serialized - * with hangup and activate by the tty layer. - */ -static void ifx_port_shutdown(struct tty_port *port) -{ - struct ifx_spi_device *ifx_dev = - container_of(port, struct ifx_spi_device, tty_port); - - clear_bit(ifx_spi_state_io_available, &ifx_dev->flags); - mrdy_set_low(ifx_dev); - del_timer(&ifx_dev->spi_timer); - clear_bit(ifx_spi_state_timer_pending, &ifx_dev->flags); - tasklet_kill(&ifx_dev->io_work_tasklet); -} - -static const struct tty_port_operations ifx_tty_port_ops = { - .activate = ifx_port_activate, - .shutdown = ifx_port_shutdown, -}; - -static const struct tty_operations ifx_spi_serial_ops = { - .open = ifx_spi_open, - .close = ifx_spi_close, - .write = ifx_spi_write, - .hangup = ifx_spi_hangup, - .write_room = ifx_spi_write_room, - .chars_in_buffer = ifx_spi_chars_in_buffer, - .tiocmget = ifx_spi_tiocmget, - .tiocmset = ifx_spi_tiocmset, -}; - -/** - * ifx_spi_insert_fip_string - queue received data - * @ifx_dev: our spi device - * @chars: buffer we have received - * @size: number of chars reeived - * - * queue bytes to the tty assuming the tty side is currently open. if - * not the discard the data. - */ -static void ifx_spi_insert_flip_string(struct ifx_spi_device *ifx_dev, - unsigned char *chars, size_t size) -{ - tty_insert_flip_string(&ifx_dev->tty_port, chars, size); - tty_flip_buffer_push(&ifx_dev->tty_port); -} - -/** - * ifx_spi_complete - spi transfer completed - * @ctx: our spi device - * - * an spi transfer has completed. process any received data and kick off - * any further transmits we can commence. - */ -static void ifx_spi_complete(void *ctx) -{ - struct ifx_spi_device *ifx_dev = ctx; - int length; - int actual_length; - unsigned char more = 0; - unsigned char cts; - int local_write_pending = 0; - int queue_length; - int srdy; - int decode_result; - - mrdy_set_low(ifx_dev); - - if (!ifx_dev->spi_msg.status) { - /* check header validity, get comm flags */ - ifx_dev->swap_buf(ifx_dev->rx_buffer, ifx_spi_header_overhead, - &ifx_dev->rx_buffer[ifx_spi_header_overhead]); - decode_result = ifx_spi_decode_spi_header(ifx_dev->rx_buffer, - &length, &more, &cts); - if (decode_result == ifx_spi_header_0) { - dev_dbg(&ifx_dev->spi_dev->dev, - "ignore input: invalid header 0"); - ifx_dev->spi_slave_cts = 0; - goto complete_exit; - } else if (decode_result == ifx_spi_header_f) { - dev_dbg(&ifx_dev->spi_dev->dev, - "ignore input: invalid header f"); - goto complete_exit; - } - - ifx_dev->spi_slave_cts = cts; - - actual_length = min((unsigned int)length, - ifx_dev->spi_msg.actual_length); - ifx_dev->swap_buf( - (ifx_dev->rx_buffer + ifx_spi_header_overhead), - actual_length, - &ifx_dev->rx_buffer[ifx_spi_transfer_size]); - ifx_spi_insert_flip_string( - ifx_dev, - ifx_dev->rx_buffer + ifx_spi_header_overhead, - (size_t)actual_length); - } else { - more = 0; - dev_dbg(&ifx_dev->spi_dev->dev, "spi transfer error %d", - ifx_dev->spi_msg.status); - } - -complete_exit: - if (ifx_dev->write_pending) { - ifx_dev->write_pending = 0; - local_write_pending = 1; - } - - clear_bit(ifx_spi_state_io_in_progress, &(ifx_dev->flags)); - - queue_length = kfifo_len(&ifx_dev->tx_fifo); - srdy = gpiod_get_value(ifx_dev->gpio.srdy); - if (!srdy) - ifx_spi_power_state_clear(ifx_dev, ifx_spi_power_srdy); - - /* schedule output if there is more to do */ - if (test_and_clear_bit(ifx_spi_state_io_ready, &ifx_dev->flags)) - tasklet_schedule(&ifx_dev->io_work_tasklet); - else { - if (more || ifx_dev->spi_more || queue_length > 0 || - local_write_pending) { - if (ifx_dev->spi_slave_cts) { - if (more) - mrdy_assert(ifx_dev); - } else - mrdy_assert(ifx_dev); - } else { - /* - * poke line discipline driver if any for more data - * may or may not get more data to write - * for now, say not busy - */ - ifx_spi_power_state_clear(ifx_dev, - ifx_spi_power_data_pending); - tty_port_tty_wakeup(&ifx_dev->tty_port); - } - } -} - -/** - * ifx_spio_io - i/o tasklet - * @t: tasklet construct used to fetch the spi device - * - * queue data for transmission if possible and then kick off the - * transfer. - */ -static void ifx_spi_io(struct tasklet_struct *t) -{ - int retval; - struct ifx_spi_device *ifx_dev = from_tasklet(ifx_dev, t, - io_work_tasklet); - - if (!test_and_set_bit(ifx_spi_state_io_in_progress, &ifx_dev->flags) && - test_bit(ifx_spi_state_io_available, &ifx_dev->flags)) { - if (ifx_dev->gpio.unack_srdy_int_nb > 0) - ifx_dev->gpio.unack_srdy_int_nb--; - - ifx_spi_prepare_tx_buffer(ifx_dev); - - spi_message_init(&ifx_dev->spi_msg); - init_list_head(&ifx_dev->spi_msg.queue); - - ifx_dev->spi_msg.context = ifx_dev; - ifx_dev->spi_msg.complete = ifx_spi_complete; - - /* set up our spi transfer */ - /* note len is bytes, not transfers */ - ifx_dev->spi_xfer.len = ifx_spi_transfer_size; - ifx_dev->spi_xfer.cs_change = 0; - ifx_dev->spi_xfer.speed_hz = ifx_dev->spi_dev->max_speed_hz; - /* ifx_dev->spi_xfer.speed_hz = 390625; */ - ifx_dev->spi_xfer.bits_per_word = - ifx_dev->spi_dev->bits_per_word; - - ifx_dev->spi_xfer.tx_buf = ifx_dev->tx_buffer; - ifx_dev->spi_xfer.rx_buf = ifx_dev->rx_buffer; - - /* - * setup dma pointers - */ - if (ifx_dev->use_dma) { - ifx_dev->spi_msg.is_dma_mapped = 1; - ifx_dev->tx_dma = ifx_dev->tx_bus; - ifx_dev->rx_dma = ifx_dev->rx_bus; - ifx_dev->spi_xfer.tx_dma = ifx_dev->tx_dma; - ifx_dev->spi_xfer.rx_dma = ifx_dev->rx_dma; - } else { - ifx_dev->spi_msg.is_dma_mapped = 0; - ifx_dev->tx_dma = (dma_addr_t)0; - ifx_dev->rx_dma = (dma_addr_t)0; - ifx_dev->spi_xfer.tx_dma = (dma_addr_t)0; - ifx_dev->spi_xfer.rx_dma = (dma_addr_t)0; - } - - spi_message_add_tail(&ifx_dev->spi_xfer, &ifx_dev->spi_msg); - - /* assert mrdy. this may have already been done by the write - * routine. - */ - mrdy_assert(ifx_dev); - - retval = spi_async(ifx_dev->spi_dev, &ifx_dev->spi_msg); - if (retval) { - clear_bit(ifx_spi_state_io_in_progress, - &ifx_dev->flags); - tasklet_schedule(&ifx_dev->io_work_tasklet); - return; - } - } else - ifx_dev->write_pending = 1; -} - -/** - * ifx_spi_free_port - free up the tty side - * @ifx_dev: ifx device going away - * - * unregister and free up a port when the device goes away - */ -static void ifx_spi_free_port(struct ifx_spi_device *ifx_dev) -{ - if (ifx_dev->tty_dev) - tty_unregister_device(tty_drv, ifx_dev->minor); - tty_port_destroy(&ifx_dev->tty_port); - kfifo_free(&ifx_dev->tx_fifo); -} - -/** - * ifx_spi_create_port - create a new port - * @ifx_dev: our spi device - * - * allocate and initialise the tty port that goes with this interface - * and add it to the tty layer so that it can be opened. - */ -static int ifx_spi_create_port(struct ifx_spi_device *ifx_dev) -{ - int ret = 0; - struct tty_port *pport = &ifx_dev->tty_port; - - spin_lock_init(&ifx_dev->fifo_lock); - lockdep_set_class_and_subclass(&ifx_dev->fifo_lock, - &ifx_spi_key, 0); - - if (kfifo_alloc(&ifx_dev->tx_fifo, ifx_spi_fifo_size, gfp_kernel)) { - ret = -enomem; - goto error_ret; - } - - tty_port_init(pport); - pport->ops = &ifx_tty_port_ops; - ifx_dev->minor = ifx_spi_tty_id; - ifx_dev->tty_dev = tty_port_register_device(pport, tty_drv, - ifx_dev->minor, &ifx_dev->spi_dev->dev); - if (is_err(ifx_dev->tty_dev)) { - dev_dbg(&ifx_dev->spi_dev->dev, - "%s: registering tty device failed", __func__); - ret = ptr_err(ifx_dev->tty_dev); - goto error_port; - } - return 0; - -error_port: - tty_port_destroy(pport); -error_ret: - ifx_spi_free_port(ifx_dev); - return ret; -} - -/** - * ifx_spi_handle_srdy - handle srdy - * @ifx_dev: device asserting srdy - * - * check our device state and see what we need to kick off when srdy - * is asserted. this usually means killing the timer and firing off the - * i/o processing. - */ -static void ifx_spi_handle_srdy(struct ifx_spi_device *ifx_dev) -{ - if (test_bit(ifx_spi_state_timer_pending, &ifx_dev->flags)) { - del_timer(&ifx_dev->spi_timer); - clear_bit(ifx_spi_state_timer_pending, &ifx_dev->flags); - } - - ifx_spi_power_state_set(ifx_dev, ifx_spi_power_srdy); - - if (!test_bit(ifx_spi_state_io_in_progress, &ifx_dev->flags)) - tasklet_schedule(&ifx_dev->io_work_tasklet); - else - set_bit(ifx_spi_state_io_ready, &ifx_dev->flags); -} - -/** - * ifx_spi_srdy_interrupt - srdy asserted - * @irq: our irq number - * @dev: our ifx device - * - * the modem asserted srdy. handle the srdy event - */ -static irqreturn_t ifx_spi_srdy_interrupt(int irq, void *dev) -{ - struct ifx_spi_device *ifx_dev = dev; - ifx_dev->gpio.unack_srdy_int_nb++; - ifx_spi_handle_srdy(ifx_dev); - return irq_handled; -} - -/** - * ifx_spi_reset_interrupt - modem has changed reset state - * @irq: interrupt number - * @dev: our device pointer - * - * the modem has either entered or left reset state. check the gpio - * line to see which. - * - * fixme: review locking on mr_inprogress versus - * parallel unsolicited reset/solicited reset - */ -static irqreturn_t ifx_spi_reset_interrupt(int irq, void *dev) -{ - struct ifx_spi_device *ifx_dev = dev; - int val = gpiod_get_value(ifx_dev->gpio.reset_out); - int solreset = test_bit(mr_start, &ifx_dev->mdm_reset_state); - - if (val == 0) { - /* entered reset */ - set_bit(mr_inprogress, &ifx_dev->mdm_reset_state); - if (!solreset) { - /* unsolicited reset */ - tty_port_tty_hangup(&ifx_dev->tty_port, false); - } - } else { - /* exited reset */ - clear_bit(mr_inprogress, &ifx_dev->mdm_reset_state); - if (solreset) { - set_bit(mr_complete, &ifx_dev->mdm_reset_state); - wake_up(&ifx_dev->mdm_reset_wait); - } - } - return irq_handled; -} - -/** - * ifx_spi_free_device - free device - * @ifx_dev: device to free - * - * free the ifx device - */ -static void ifx_spi_free_device(struct ifx_spi_device *ifx_dev) -{ - ifx_spi_free_port(ifx_dev); - dma_free_coherent(&ifx_dev->spi_dev->dev, - ifx_spi_transfer_size, - ifx_dev->tx_buffer, - ifx_dev->tx_bus); - dma_free_coherent(&ifx_dev->spi_dev->dev, - ifx_spi_transfer_size, - ifx_dev->rx_buffer, - ifx_dev->rx_bus); -} - -/** - * ifx_spi_reset - reset modem - * @ifx_dev: modem to reset - * - * perform a reset on the modem - */ -static int ifx_spi_reset(struct ifx_spi_device *ifx_dev) -{ - int ret; - /* - * set up modem power, reset - * - * delays are required on some platforms for the modem - * to reset properly - */ - set_bit(mr_start, &ifx_dev->mdm_reset_state); - gpiod_set_value(ifx_dev->gpio.po, 0); - gpiod_set_value(ifx_dev->gpio.reset, 0); - msleep(25); - gpiod_set_value(ifx_dev->gpio.reset, 1); - msleep(1); - gpiod_set_value(ifx_dev->gpio.po, 1); - msleep(1); - gpiod_set_value(ifx_dev->gpio.po, 0); - ret = wait_event_timeout(ifx_dev->mdm_reset_wait, - test_bit(mr_complete, - &ifx_dev->mdm_reset_state), - ifx_reset_timeout); - if (!ret) - dev_warn(&ifx_dev->spi_dev->dev, "modem reset timeout: (state:%lx)", - ifx_dev->mdm_reset_state); - - ifx_dev->mdm_reset_state = 0; - return ret; -} - -/** - * ifx_spi_spi_probe - probe callback - * @spi: our possible matching spi device - * - * probe for a 6x60 modem on spi bus. perform any needed device and - * gpio setup. - * - * fixme: - * - support for multiple devices - * - split out mid specific gpio handling eventually - */ - -static int ifx_spi_spi_probe(struct spi_device *spi) -{ - int ret; - int srdy; - struct ifx_modem_platform_data *pl_data; - struct ifx_spi_device *ifx_dev; - struct device *dev = &spi->dev; - - if (saved_ifx_dev) { - dev_dbg(dev, "ignoring subsequent detection"); - return -enodev; - } - - pl_data = dev_get_platdata(dev); - if (!pl_data) { - dev_err(dev, "missing platform data!"); - return -enodev; - } - - /* initialize structure to hold our device variables */ - ifx_dev = kzalloc(sizeof(struct ifx_spi_device), gfp_kernel); - if (!ifx_dev) { - dev_err(dev, "spi device allocation failed"); - return -enomem; - } - saved_ifx_dev = ifx_dev; - ifx_dev->spi_dev = spi; - clear_bit(ifx_spi_state_io_in_progress, &ifx_dev->flags); - spin_lock_init(&ifx_dev->write_lock); - spin_lock_init(&ifx_dev->power_lock); - ifx_dev->power_status = 0; - timer_setup(&ifx_dev->spi_timer, ifx_spi_timeout, 0); - ifx_dev->modem = pl_data->modem_type; - ifx_dev->use_dma = pl_data->use_dma; - ifx_dev->max_hz = pl_data->max_hz; - /* initialize spi mode, etc */ - spi->max_speed_hz = ifx_dev->max_hz; - spi->mode = ifx_spi_mode | (spi_loop & spi->mode); - spi->bits_per_word = spi_bpw; - ret = spi_setup(spi); - if (ret) { - dev_err(dev, "spi setup wasn't successful %d", ret); - kfree(ifx_dev); - return -enodev; - } - - /* init swap_buf function according to word width configuration */ - if (spi->bits_per_word == 32) - ifx_dev->swap_buf = swap_buf_32; - else if (spi->bits_per_word == 16) - ifx_dev->swap_buf = swap_buf_16; - else - ifx_dev->swap_buf = swap_buf_8; - - /* ensure spi protocol flags are initialized to enable transfer */ - ifx_dev->spi_more = 0; - ifx_dev->spi_slave_cts = 0; - - /*initialize transfer and dma buffers */ - ifx_dev->tx_buffer = dma_alloc_coherent(ifx_dev->spi_dev->dev.parent, - ifx_spi_transfer_size, - &ifx_dev->tx_bus, - gfp_kernel); - if (!ifx_dev->tx_buffer) { - dev_err(dev, "dma-tx buffer allocation failed"); - ret = -enomem; - goto error_ret; - } - ifx_dev->rx_buffer = dma_alloc_coherent(ifx_dev->spi_dev->dev.parent, - ifx_spi_transfer_size, - &ifx_dev->rx_bus, - gfp_kernel); - if (!ifx_dev->rx_buffer) { - dev_err(dev, "dma-rx buffer allocation failed"); - ret = -enomem; - goto error_ret; - } - - /* initialize waitq for modem reset */ - init_waitqueue_head(&ifx_dev->mdm_reset_wait); - - spi_set_drvdata(spi, ifx_dev); - tasklet_setup(&ifx_dev->io_work_tasklet, ifx_spi_io); - - set_bit(ifx_spi_state_present, &ifx_dev->flags); - - /* create our tty port */ - ret = ifx_spi_create_port(ifx_dev); - if (ret != 0) { - dev_err(dev, "create default tty port failed"); - goto error_ret; - } - - ifx_dev->gpio.reset = devm_gpiod_get(dev, "reset", gpiod_out_low); - if (is_err(ifx_dev->gpio.reset)) { - dev_err(dev, "could not obtain reset gpio "); - ret = ptr_err(ifx_dev->gpio.reset); - goto error_ret; - } - gpiod_set_consumer_name(ifx_dev->gpio.reset, "ifxmodem reset"); - ifx_dev->gpio.po = devm_gpiod_get(dev, "power", gpiod_out_low); - if (is_err(ifx_dev->gpio.po)) { - dev_err(dev, "could not obtain power gpio "); - ret = ptr_err(ifx_dev->gpio.po); - goto error_ret; - } - gpiod_set_consumer_name(ifx_dev->gpio.po, "ifxmodem power"); - ifx_dev->gpio.mrdy = devm_gpiod_get(dev, "mrdy", gpiod_out_low); - if (is_err(ifx_dev->gpio.mrdy)) { - dev_err(dev, "could not obtain mrdy gpio "); - ret = ptr_err(ifx_dev->gpio.mrdy); - goto error_ret; - } - gpiod_set_consumer_name(ifx_dev->gpio.mrdy, "ifxmodem mrdy"); - ifx_dev->gpio.srdy = devm_gpiod_get(dev, "srdy", gpiod_in); - if (is_err(ifx_dev->gpio.srdy)) { - dev_err(dev, "could not obtain srdy gpio "); - ret = ptr_err(ifx_dev->gpio.srdy); - goto error_ret; - } - gpiod_set_consumer_name(ifx_dev->gpio.srdy, "ifxmodem srdy"); - ifx_dev->gpio.reset_out = devm_gpiod_get(dev, "rst_out", gpiod_in); - if (is_err(ifx_dev->gpio.reset_out)) { - dev_err(dev, "could not obtain rst_out gpio "); - ret = ptr_err(ifx_dev->gpio.reset_out); - goto error_ret; - } - gpiod_set_consumer_name(ifx_dev->gpio.reset_out, "ifxmodem reset out"); - ifx_dev->gpio.pmu_reset = devm_gpiod_get(dev, "pmu_reset", gpiod_asis); - if (is_err(ifx_dev->gpio.pmu_reset)) { - dev_err(dev, "could not obtain pmu_reset gpio "); - ret = ptr_err(ifx_dev->gpio.pmu_reset); - goto error_ret; - } - gpiod_set_consumer_name(ifx_dev->gpio.pmu_reset, "ifxmodem pmu reset"); - - ret = request_irq(gpiod_to_irq(ifx_dev->gpio.reset_out), - ifx_spi_reset_interrupt, - irqf_trigger_rising|irqf_trigger_falling, drvname, - ifx_dev); - if (ret) { - dev_err(dev, "unable to get irq %x ", - gpiod_to_irq(ifx_dev->gpio.reset_out)); - goto error_ret; - } - - ret = ifx_spi_reset(ifx_dev); - - ret = request_irq(gpiod_to_irq(ifx_dev->gpio.srdy), - ifx_spi_srdy_interrupt, irqf_trigger_rising, drvname, - ifx_dev); - if (ret) { - dev_err(dev, "unable to get irq %x", - gpiod_to_irq(ifx_dev->gpio.srdy)); - goto error_ret2; - } - - /* set pm runtime power state and register with power system */ - pm_runtime_set_active(dev); - pm_runtime_enable(dev); - - /* handle case that modem is already signaling srdy */ - /* no outgoing tty open at this point, this just satisfies the - * modem's read and should reset communication properly - */ - srdy = gpiod_get_value(ifx_dev->gpio.srdy); - - if (srdy) { - mrdy_assert(ifx_dev); - ifx_spi_handle_srdy(ifx_dev); - } else - mrdy_set_low(ifx_dev); - return 0; - -error_ret2: - free_irq(gpiod_to_irq(ifx_dev->gpio.reset_out), ifx_dev); -error_ret: - ifx_spi_free_device(ifx_dev); - saved_ifx_dev = null; - return ret; -} - -/** - * ifx_spi_spi_remove - spi device was removed - * @spi: spi device - * - * fixme: we should be shutting the device down here not in - * the module unload path. - */ - -static int ifx_spi_spi_remove(struct spi_device *spi) -{ - struct ifx_spi_device *ifx_dev = spi_get_drvdata(spi); - /* stop activity */ - tasklet_kill(&ifx_dev->io_work_tasklet); - - pm_runtime_disable(&spi->dev); - - /* free irq */ - free_irq(gpiod_to_irq(ifx_dev->gpio.reset_out), ifx_dev); - free_irq(gpiod_to_irq(ifx_dev->gpio.srdy), ifx_dev); - - /* free allocations */ - ifx_spi_free_device(ifx_dev); - - saved_ifx_dev = null; - return 0; -} - -/** - * ifx_spi_spi_shutdown - called on spi shutdown - * @spi: spi device - * - * no action needs to be taken here - */ - -static void ifx_spi_spi_shutdown(struct spi_device *spi) -{ - struct ifx_spi_device *ifx_dev = spi_get_drvdata(spi); - - ifx_modem_power_off(ifx_dev); -} - -/* - * various suspends and resumes have nothing to do - * no hardware to save state for - */ - -/** - * ifx_spi_pm_suspend - suspend modem on system suspend - * @dev: device being suspended - * - * suspend the modem. no action needed on intel mid platforms, may - * need extending for other systems. - */ -static int ifx_spi_pm_suspend(struct device *dev) -{ - return 0; -} - -/** - * ifx_spi_pm_resume - resume modem on system resume - * @dev: device being suspended - * - * allow the modem to resume. no action needed. - * - * fixme: do we need to reset anything here ? - */ -static int ifx_spi_pm_resume(struct device *dev) -{ - return 0; -} - -/** - * ifx_spi_pm_runtime_resume - suspend modem - * @dev: device being suspended - * - * allow the modem to resume. no action needed. - */ -static int ifx_spi_pm_runtime_resume(struct device *dev) -{ - return 0; -} - -/** - * ifx_spi_pm_runtime_suspend - suspend modem - * @dev: device being suspended - * - * allow the modem to suspend and thus suspend to continue up the - * device tree. - */ -static int ifx_spi_pm_runtime_suspend(struct device *dev) -{ - return 0; -} - -/** - * ifx_spi_pm_runtime_idle - check if modem idle - * @dev: our device - * - * check conditions and queue runtime suspend if idle. - */ -static int ifx_spi_pm_runtime_idle(struct device *dev) -{ - struct spi_device *spi = to_spi_device(dev); - struct ifx_spi_device *ifx_dev = spi_get_drvdata(spi); - - if (!ifx_dev->power_status) - pm_runtime_suspend(dev); - - return 0; -} - -static const struct dev_pm_ops ifx_spi_pm = { - .resume = ifx_spi_pm_resume, - .suspend = ifx_spi_pm_suspend, - .runtime_resume = ifx_spi_pm_runtime_resume, - .runtime_suspend = ifx_spi_pm_runtime_suspend, - .runtime_idle = ifx_spi_pm_runtime_idle -}; - -static const struct spi_device_id ifx_id_table[] = { - {"ifx6160", 0}, - {"ifx6260", 0}, - { } -}; -module_device_table(spi, ifx_id_table); - -/* spi operations */ -static struct spi_driver ifx_spi_driver = { - .driver = { - .name = drvname, - .pm = &ifx_spi_pm, - }, - .probe = ifx_spi_spi_probe, - .shutdown = ifx_spi_spi_shutdown, - .remove = ifx_spi_spi_remove, - .id_table = ifx_id_table -}; - -/** - * ifx_spi_exit - module exit - * - * unload the module. - */ - -static void __exit ifx_spi_exit(void) -{ - /* unregister */ - spi_unregister_driver(&ifx_spi_driver); - tty_unregister_driver(tty_drv); - put_tty_driver(tty_drv); - unregister_reboot_notifier(&ifx_modem_reboot_notifier_block); -} - -/** - * ifx_spi_init - module entry point - * - * initialise the spi and tty interfaces for the ifx spi driver - * we need to initialize upper-edge spi driver after the tty - * driver because otherwise the spi probe will race - */ - -static int __init ifx_spi_init(void) -{ - int result; - - tty_drv = alloc_tty_driver(1); - if (!tty_drv) { - pr_err("%s: alloc_tty_driver failed", drvname); - return -enomem; - } - - tty_drv->driver_name = drvname; - tty_drv->name = ttyname; - tty_drv->minor_start = ifx_spi_tty_id; - tty_drv->type = tty_driver_type_serial; - tty_drv->subtype = serial_type_normal; - tty_drv->flags = tty_driver_real_raw | tty_driver_dynamic_dev; - tty_drv->init_termios = tty_std_termios; - - tty_set_operations(tty_drv, &ifx_spi_serial_ops); - - result = tty_register_driver(tty_drv); - if (result) { - pr_err("%s: tty_register_driver failed(%d)", - drvname, result); - goto err_free_tty; - } - - result = spi_register_driver(&ifx_spi_driver); - if (result) { - pr_err("%s: spi_register_driver failed(%d)", - drvname, result); - goto err_unreg_tty; - } - - result = register_reboot_notifier(&ifx_modem_reboot_notifier_block); - if (result) { - pr_err("%s: register ifx modem reboot notifier failed(%d)", - drvname, result); - goto err_unreg_spi; - } - - return 0; -err_unreg_spi: - spi_unregister_driver(&ifx_spi_driver); -err_unreg_tty: - tty_unregister_driver(tty_drv); -err_free_tty: - put_tty_driver(tty_drv); - - return result; -} - -module_init(ifx_spi_init); -module_exit(ifx_spi_exit); - -module_author("intel"); -module_description("ifx6x60 spi driver"); -module_license("gpl"); -module_info(version, "0.1-ifx6x60"); diff --git a/drivers/tty/serial/ifx6x60.h b/drivers/tty/serial/ifx6x60.h --- a/drivers/tty/serial/ifx6x60.h +++ /dev/null -/* spdx-license-identifier: gpl-2.0 */ -/**************************************************************************** - * - * driver for the ifx spi modem. - * - * copyright (c) 2009, 2010 intel corp - * jim stanley <jim.stanley@intel.com> - * - *****************************************************************************/ -#ifndef _ifx6x60_h -#define _ifx6x60_h - -struct gpio_desc; - -#define drvname "ifx6x60" -#define ttyname "ttyifx" - -#define ifx_spi_max_minors 1 -#define ifx_spi_transfer_size 2048 -#define ifx_spi_fifo_size 4096 - -#define ifx_spi_header_overhead 4 -#define ifx_reset_timeout msecs_to_jiffies(50) - -/* device flags bitfield definitions */ -#define ifx_spi_state_present 0 -#define ifx_spi_state_io_in_progress 1 -#define ifx_spi_state_io_ready 2 -#define ifx_spi_state_timer_pending 3 -#define ifx_spi_state_io_available 4 - -/* flow control bitfields */ -#define ifx_spi_dcd 0 -#define ifx_spi_cts 1 -#define ifx_spi_dsr 2 -#define ifx_spi_ri 3 -#define ifx_spi_dtr 4 -#define ifx_spi_rts 5 -#define ifx_spi_tx_fc 6 -#define ifx_spi_rx_fc 7 -#define ifx_spi_update 8 - -#define ifx_spi_payload_size (ifx_spi_transfer_size - \ - ifx_spi_header_overhead) - -#define ifx_spi_irq_type detect_edge_rising -#define ifx_spi_gpio_target 0 -#define ifx_spi_gpio0 0x105 - -#define ifx_spi_status_timeout (2000*hz) - -/* values for bits in power status byte */ -#define ifx_spi_power_data_pending 1 -#define ifx_spi_power_srdy 2 - -struct ifx_spi_device { - /* our spi device */ - struct spi_device *spi_dev; - - /* port specific data */ - struct kfifo tx_fifo; - spinlock_t fifo_lock; - unsigned long signal_state; - - /* tty layer logic */ - struct tty_port tty_port; - struct device *tty_dev; - int minor; - - /* low level i/o work */ - struct tasklet_struct io_work_tasklet; - unsigned long flags; - dma_addr_t rx_dma; - dma_addr_t tx_dma; - - int modem; /* modem type */ - int use_dma; /* provide dma-able addrs in spi msg */ - long max_hz; /* max spi frequency */ - - spinlock_t write_lock; - int write_pending; - spinlock_t power_lock; - unsigned char power_status; - - unsigned char *rx_buffer; - unsigned char *tx_buffer; - dma_addr_t rx_bus; - dma_addr_t tx_bus; - unsigned char spi_more; - unsigned char spi_slave_cts; - - struct timer_list spi_timer; - - struct spi_message spi_msg; - struct spi_transfer spi_xfer; - - struct { - /* gpio lines */ - struct gpio_desc *srdy; /* slave-ready gpio */ - struct gpio_desc *mrdy; /* master-ready gpio */ - struct gpio_desc *reset; /* modem-reset gpio */ - struct gpio_desc *po; /* modem-on gpio */ - struct gpio_desc *reset_out; /* modem-in-reset gpio */ - struct gpio_desc *pmu_reset; /* pmu reset gpio */ - /* state/stats */ - int unack_srdy_int_nb; - } gpio; - - /* modem reset */ - unsigned long mdm_reset_state; -#define mr_start 0 -#define mr_inprogress 1 -#define mr_complete 2 - wait_queue_head_t mdm_reset_wait; - void (*swap_buf)(unsigned char *buf, int len, void *end); -}; - -#endif /* _ifx6x60_h */ diff --git a/include/linux/spi/ifx_modem.h b/include/linux/spi/ifx_modem.h --- a/include/linux/spi/ifx_modem.h +++ /dev/null -/* spdx-license-identifier: gpl-2.0 */ -#ifndef linux_ifx_modem_h -#define linux_ifx_modem_h - -struct ifx_modem_platform_data { - unsigned short tx_pwr; /* modem power threshold */ - unsigned char modem_type; /* modem type */ - unsigned long max_hz; /* max spi frequency */ - unsigned short use_dma:1; /* spi protocol driver supplies - dma-able addrs */ -}; -#define ifx_modem_6160 1 -#define ifx_modem_6260 2 - -#endif
|
Serial
|
e9103f47bf1a1bbf0ab0ea90eda3e208653a5f57
|
andy shevchenko
|
include
|
linux
|
serial, spi
|
tty: serial: owl: add support for kernel debugger
|
implement 'poll_put_char' and 'poll_get_char' callbacks in struct 'owl_uart_ops' that enables owl uart to be used for kernel debugging over serial line.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for kernel debugger
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['owl']
|
['c']
| 1
| 38
| 0
|
--- diff --git a/drivers/tty/serial/owl-uart.c b/drivers/tty/serial/owl-uart.c --- a/drivers/tty/serial/owl-uart.c +++ b/drivers/tty/serial/owl-uart.c +#include <linux/iopoll.h> +#define owl_uart_poll_usec 5 +#define owl_uart_timeout_usec 10000 + +#ifdef config_console_poll + +static int owl_uart_poll_get_char(struct uart_port *port) +{ + if (owl_uart_read(port, owl_uart_stat) & owl_uart_stat_rfem) + return no_poll_char; + + return owl_uart_read(port, owl_uart_rxdat); +} + +static void owl_uart_poll_put_char(struct uart_port *port, unsigned char ch) +{ + u32 reg; + int ret; + + /* wait while fifo is full or timeout */ + ret = readl_poll_timeout_atomic(port->membase + owl_uart_stat, reg, + !(reg & owl_uart_stat_tffu), + owl_uart_poll_usec, + owl_uart_timeout_usec); + if (ret == -etimedout) { + dev_err(port->dev, "timeout waiting while uart tx full "); + return; + } + + owl_uart_write(port, ch, owl_uart_txdat); +} + +#endif /* config_console_poll */ + +#ifdef config_console_poll + .poll_get_char = owl_uart_poll_get_char, + .poll_put_char = owl_uart_poll_put_char, +#endif
|
Serial
|
9335e23ddc33b5298b4cefdecc962736449fe596
|
cristian ciocaltea
|
drivers
|
tty
|
serial
|
serial: remove sirf prima/atlas driver
|
the csr sirf prima2/atlas platforms are getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove sirf prima/atlas driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['c', 'h', 'kconfig', 'txt', 'makefile']
| 5
| 0
| 2,007
|
--- diff --git a/documentation/devicetree/bindings/serial/sirf-uart.txt b/documentation/devicetree/bindings/serial/sirf-uart.txt --- a/documentation/devicetree/bindings/serial/sirf-uart.txt +++ /dev/null -* csr sirfprimaii/atlasvi universal synchronous asynchronous receiver/transmitter * - -required properties: -- compatible : should be "sirf,prima2-uart", "sirf, prima2-usp-uart", - "sirf,atlas7-uart" or "sirf,atlas7-usp-uart". -- reg : offset and length of the register set for the device -- interrupts : should contain uart interrupt -- fifosize : should define hardware rx/tx fifo size -- clocks : should contain uart clock number - -optional properties: -- uart-has-rtscts: we have hardware flow controller pins in hardware -- rts-gpios: rts pin for usp-based uart if uart-has-rtscts is true -- cts-gpios: cts pin for usp-based uart if uart-has-rtscts is true - -example: - -uart0: uart@b0050000 { - cell-index = <0>; - compatible = "sirf,prima2-uart"; - reg = <0xb0050000 0x1000>; - interrupts = <17>; - fifosize = <128>; - clocks = <&clks 13>; -}; - -on the board-specific dts, we can put rts-gpios and cts-gpios like - -usp@b0090000 { - compatible = "sirf,prima2-usp-uart"; - uart-has-rtscts; - rts-gpios = <&gpio 15 0>; - cts-gpios = <&gpio 46 0>; -}; diff --git a/drivers/tty/serial/kconfig b/drivers/tty/serial/kconfig --- a/drivers/tty/serial/kconfig +++ b/drivers/tty/serial/kconfig -config serial_sirfsoc - tristate "sirf soc platform serial port support" - depends on arch_sirf - select serial_core - help - support for the on-chip uart on the csr sirfprimaii series, - providing /dev/ttysirf0, 1 and 2 (note, some machines may not - provide all of these ports, depending on how the serial port - pins are configured). - -config serial_sirfsoc_console - bool "support for console on sirf soc serial port" - depends on serial_sirfsoc=y - select serial_core_console - help - even if you say y here, the currently visible virtual console - (/dev/tty0) will still be used as the system console by default, but - you can alter that using a kernel command line option such as - "console=ttysirfx". (try "man bootparam" or see the documentation of - your boot loader about how to pass options to the kernel at - boot time.) - diff --git a/drivers/tty/serial/makefile b/drivers/tty/serial/makefile --- a/drivers/tty/serial/makefile +++ b/drivers/tty/serial/makefile -obj-$(config_serial_sirfsoc) += sirfsoc_uart.o diff --git a/drivers/tty/serial/sirfsoc_uart.c b/drivers/tty/serial/sirfsoc_uart.c --- a/drivers/tty/serial/sirfsoc_uart.c +++ /dev/null -// spdx-license-identifier: gpl-2.0+ -/* - * driver for csr sirfprimaii onboard uarts. - * - * copyright (c) 2011 cambridge silicon radio limited, a csr plc group company. - */ - -#include <linux/module.h> -#include <linux/ioport.h> -#include <linux/platform_device.h> -#include <linux/init.h> -#include <linux/sysrq.h> -#include <linux/console.h> -#include <linux/tty.h> -#include <linux/tty_flip.h> -#include <linux/serial_core.h> -#include <linux/serial.h> -#include <linux/clk.h> -#include <linux/of.h> -#include <linux/slab.h> -#include <linux/io.h> -#include <linux/of_gpio.h> -#include <linux/dmaengine.h> -#include <linux/dma-direction.h> -#include <linux/dma-mapping.h> -#include <asm/irq.h> -#include <asm/mach/irq.h> - -#include "sirfsoc_uart.h" - -static unsigned int -sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count); -static unsigned int -sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count); -static struct uart_driver sirfsoc_uart_drv; - -static void sirfsoc_uart_tx_dma_complete_callback(void *param); -static const struct sirfsoc_baudrate_to_regv baudrate_to_regv[] = { - {4000000, 2359296}, - {3500000, 1310721}, - {3000000, 1572865}, - {2500000, 1245186}, - {2000000, 1572866}, - {1500000, 1245188}, - {1152000, 1638404}, - {1000000, 1572869}, - {921600, 1114120}, - {576000, 1245196}, - {500000, 1245198}, - {460800, 1572876}, - {230400, 1310750}, - {115200, 1310781}, - {57600, 1310843}, - {38400, 1114328}, - {19200, 1114545}, - {9600, 1114979}, -}; - -static struct sirfsoc_uart_port *sirf_ports[sirfsoc_uart_nr]; - -static inline struct sirfsoc_uart_port *to_sirfport(struct uart_port *port) -{ - return container_of(port, struct sirfsoc_uart_port, port); -} - -static inline unsigned int sirfsoc_uart_tx_empty(struct uart_port *port) -{ - unsigned long reg; - struct sirfsoc_uart_port *sirfport = to_sirfport(port); - struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; - struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status; - reg = rd_regl(port, ureg->sirfsoc_tx_fifo_status); - return (reg & ufifo_st->ff_empty(port)) ? tiocser_temt : 0; -} - -static unsigned int sirfsoc_uart_get_mctrl(struct uart_port *port) -{ - struct sirfsoc_uart_port *sirfport = to_sirfport(port); - struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; - if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled) - goto cts_asserted; - if (sirfport->uart_reg->uart_type == sirf_real_uart) { - if (!(rd_regl(port, ureg->sirfsoc_afc_ctrl) & - sirfuart_afc_cts_status)) - goto cts_asserted; - else - goto cts_deasserted; - } else { - if (!gpio_get_value(sirfport->cts_gpio)) - goto cts_asserted; - else - goto cts_deasserted; - } -cts_deasserted: - return tiocm_car | tiocm_dsr; -cts_asserted: - return tiocm_car | tiocm_dsr | tiocm_cts; -} - -static void sirfsoc_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) -{ - struct sirfsoc_uart_port *sirfport = to_sirfport(port); - struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; - unsigned int assert = mctrl & tiocm_rts; - unsigned int val = assert ? sirfuart_afc_ctrl_rx_thd : 0x0; - unsigned int current_val; - - if (mctrl & tiocm_loop) { - if (sirfport->uart_reg->uart_type == sirf_real_uart) - wr_regl(port, ureg->sirfsoc_line_ctrl, - rd_regl(port, ureg->sirfsoc_line_ctrl) | - sirfuart_loop_back); - else - wr_regl(port, ureg->sirfsoc_mode1, - rd_regl(port, ureg->sirfsoc_mode1) | - sirfsoc_usp_loop_back_ctrl); - } else { - if (sirfport->uart_reg->uart_type == sirf_real_uart) - wr_regl(port, ureg->sirfsoc_line_ctrl, - rd_regl(port, ureg->sirfsoc_line_ctrl) & - ~sirfuart_loop_back); - else - wr_regl(port, ureg->sirfsoc_mode1, - rd_regl(port, ureg->sirfsoc_mode1) & - ~sirfsoc_usp_loop_back_ctrl); - } - - if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled) - return; - if (sirfport->uart_reg->uart_type == sirf_real_uart) { - current_val = rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0xff; - val |= current_val; - wr_regl(port, ureg->sirfsoc_afc_ctrl, val); - } else { - if (!val) - gpio_set_value(sirfport->rts_gpio, 1); - else - gpio_set_value(sirfport->rts_gpio, 0); - } -} - -static void sirfsoc_uart_stop_tx(struct uart_port *port) -{ - struct sirfsoc_uart_port *sirfport = to_sirfport(port); - struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; - struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; - - if (sirfport->tx_dma_chan) { - if (sirfport->tx_dma_state == tx_dma_running) { - dmaengine_pause(sirfport->tx_dma_chan); - sirfport->tx_dma_state = tx_dma_pause; - } else { - if (!sirfport->is_atlas7) - wr_regl(port, ureg->sirfsoc_int_en_reg, - rd_regl(port, ureg->sirfsoc_int_en_reg) & - ~uint_en->sirfsoc_txfifo_empty_en); - else - wr_regl(port, ureg->sirfsoc_int_en_clr_reg, - uint_en->sirfsoc_txfifo_empty_en); - } - } else { - if (sirfport->uart_reg->uart_type == sirf_usp_uart) - wr_regl(port, ureg->sirfsoc_tx_rx_en, rd_regl(port, - ureg->sirfsoc_tx_rx_en) & ~sirfuart_tx_en); - if (!sirfport->is_atlas7) - wr_regl(port, ureg->sirfsoc_int_en_reg, - rd_regl(port, ureg->sirfsoc_int_en_reg) & - ~uint_en->sirfsoc_txfifo_empty_en); - else - wr_regl(port, ureg->sirfsoc_int_en_clr_reg, - uint_en->sirfsoc_txfifo_empty_en); - } -} - -static void sirfsoc_uart_tx_with_dma(struct sirfsoc_uart_port *sirfport) -{ - struct uart_port *port = &sirfport->port; - struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; - struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; - struct circ_buf *xmit = &port->state->xmit; - unsigned long tran_size; - unsigned long tran_start; - unsigned long pio_tx_size; - - tran_size = circ_cnt_to_end(xmit->head, xmit->tail, uart_xmit_size); - tran_start = (unsigned long)(xmit->buf + xmit->tail); - if (uart_circ_empty(xmit) || uart_tx_stopped(port) || - !tran_size) - return; - if (sirfport->tx_dma_state == tx_dma_pause) { - dmaengine_resume(sirfport->tx_dma_chan); - return; - } - if (sirfport->tx_dma_state == tx_dma_running) - return; - if (!sirfport->is_atlas7) - wr_regl(port, ureg->sirfsoc_int_en_reg, - rd_regl(port, ureg->sirfsoc_int_en_reg)& - ~(uint_en->sirfsoc_txfifo_empty_en)); - else - wr_regl(port, ureg->sirfsoc_int_en_clr_reg, - uint_en->sirfsoc_txfifo_empty_en); - /* - * dma requires buffer address and buffer length are both aligned with - * 4 bytes, so we use pio for - * 1. if address is not aligned with 4bytes, use pio for the first 1~3 - * bytes, and move to dma for the left part aligned with 4bytes - * 2. if buffer length is not aligned with 4bytes, use dma for aligned - * part first, move to pio for the left 1~3 bytes - */ - if (tran_size < 4 || bytes_to_align(tran_start)) { - wr_regl(port, ureg->sirfsoc_tx_fifo_op, sirfuart_fifo_stop); - wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, - rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)| - sirfuart_io_mode); - if (bytes_to_align(tran_start)) { - pio_tx_size = sirfsoc_uart_pio_tx_chars(sirfport, - bytes_to_align(tran_start)); - tran_size -= pio_tx_size; - } - if (tran_size < 4) - sirfsoc_uart_pio_tx_chars(sirfport, tran_size); - if (!sirfport->is_atlas7) - wr_regl(port, ureg->sirfsoc_int_en_reg, - rd_regl(port, ureg->sirfsoc_int_en_reg)| - uint_en->sirfsoc_txfifo_empty_en); - else - wr_regl(port, ureg->sirfsoc_int_en_reg, - uint_en->sirfsoc_txfifo_empty_en); - wr_regl(port, ureg->sirfsoc_tx_fifo_op, sirfuart_fifo_start); - } else { - /* tx transfer mode switch into dma mode */ - wr_regl(port, ureg->sirfsoc_tx_fifo_op, sirfuart_fifo_stop); - wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, - rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)& - ~sirfuart_io_mode); - wr_regl(port, ureg->sirfsoc_tx_fifo_op, sirfuart_fifo_start); - tran_size &= ~(0x3); - - sirfport->tx_dma_addr = dma_map_single(port->dev, - xmit->buf + xmit->tail, - tran_size, dma_to_device); - sirfport->tx_dma_desc = dmaengine_prep_slave_single( - sirfport->tx_dma_chan, sirfport->tx_dma_addr, - tran_size, dma_mem_to_dev, dma_prep_interrupt); - if (!sirfport->tx_dma_desc) { - dev_err(port->dev, "dma prep slave single fail "); - return; - } - sirfport->tx_dma_desc->callback = - sirfsoc_uart_tx_dma_complete_callback; - sirfport->tx_dma_desc->callback_param = (void *)sirfport; - sirfport->transfer_size = tran_size; - - dmaengine_submit(sirfport->tx_dma_desc); - dma_async_issue_pending(sirfport->tx_dma_chan); - sirfport->tx_dma_state = tx_dma_running; - } -} - -static void sirfsoc_uart_start_tx(struct uart_port *port) -{ - struct sirfsoc_uart_port *sirfport = to_sirfport(port); - struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; - struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; - if (sirfport->tx_dma_chan) - sirfsoc_uart_tx_with_dma(sirfport); - else { - if (sirfport->uart_reg->uart_type == sirf_usp_uart) - wr_regl(port, ureg->sirfsoc_tx_rx_en, rd_regl(port, - ureg->sirfsoc_tx_rx_en) | sirfuart_tx_en); - wr_regl(port, ureg->sirfsoc_tx_fifo_op, sirfuart_fifo_stop); - sirfsoc_uart_pio_tx_chars(sirfport, port->fifosize); - wr_regl(port, ureg->sirfsoc_tx_fifo_op, sirfuart_fifo_start); - if (!sirfport->is_atlas7) - wr_regl(port, ureg->sirfsoc_int_en_reg, - rd_regl(port, ureg->sirfsoc_int_en_reg)| - uint_en->sirfsoc_txfifo_empty_en); - else - wr_regl(port, ureg->sirfsoc_int_en_reg, - uint_en->sirfsoc_txfifo_empty_en); - } -} - -static void sirfsoc_uart_stop_rx(struct uart_port *port) -{ - struct sirfsoc_uart_port *sirfport = to_sirfport(port); - struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; - struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; - - wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0); - if (sirfport->rx_dma_chan) { - if (!sirfport->is_atlas7) - wr_regl(port, ureg->sirfsoc_int_en_reg, - rd_regl(port, ureg->sirfsoc_int_en_reg) & - ~(sirfuart_rx_dma_int_en(uint_en, - sirfport->uart_reg->uart_type) | - uint_en->sirfsoc_rx_done_en)); - else - wr_regl(port, ureg->sirfsoc_int_en_clr_reg, - sirfuart_rx_dma_int_en(uint_en, - sirfport->uart_reg->uart_type)| - uint_en->sirfsoc_rx_done_en); - dmaengine_terminate_all(sirfport->rx_dma_chan); - } else { - if (!sirfport->is_atlas7) - wr_regl(port, ureg->sirfsoc_int_en_reg, - rd_regl(port, ureg->sirfsoc_int_en_reg)& - ~(sirfuart_rx_io_int_en(uint_en, - sirfport->uart_reg->uart_type))); - else - wr_regl(port, ureg->sirfsoc_int_en_clr_reg, - sirfuart_rx_io_int_en(uint_en, - sirfport->uart_reg->uart_type)); - } -} - -static void sirfsoc_uart_disable_ms(struct uart_port *port) -{ - struct sirfsoc_uart_port *sirfport = to_sirfport(port); - struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; - struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; - - if (!sirfport->hw_flow_ctrl) - return; - sirfport->ms_enabled = false; - if (sirfport->uart_reg->uart_type == sirf_real_uart) { - wr_regl(port, ureg->sirfsoc_afc_ctrl, - rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0x3ff); - if (!sirfport->is_atlas7) - wr_regl(port, ureg->sirfsoc_int_en_reg, - rd_regl(port, ureg->sirfsoc_int_en_reg)& - ~uint_en->sirfsoc_cts_en); - else - wr_regl(port, ureg->sirfsoc_int_en_clr_reg, - uint_en->sirfsoc_cts_en); - } else - disable_irq(gpio_to_irq(sirfport->cts_gpio)); -} - -static irqreturn_t sirfsoc_uart_usp_cts_handler(int irq, void *dev_id) -{ - struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id; - struct uart_port *port = &sirfport->port; - spin_lock(&port->lock); - if (gpio_is_valid(sirfport->cts_gpio) && sirfport->ms_enabled) - uart_handle_cts_change(port, - !gpio_get_value(sirfport->cts_gpio)); - spin_unlock(&port->lock); - return irq_handled; -} - -static void sirfsoc_uart_enable_ms(struct uart_port *port) -{ - struct sirfsoc_uart_port *sirfport = to_sirfport(port); - struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; - struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; - - if (!sirfport->hw_flow_ctrl) - return; - sirfport->ms_enabled = true; - if (sirfport->uart_reg->uart_type == sirf_real_uart) { - wr_regl(port, ureg->sirfsoc_afc_ctrl, - rd_regl(port, ureg->sirfsoc_afc_ctrl) | - sirfuart_afc_tx_en | sirfuart_afc_rx_en | - sirfuart_afc_ctrl_rx_thd); - if (!sirfport->is_atlas7) - wr_regl(port, ureg->sirfsoc_int_en_reg, - rd_regl(port, ureg->sirfsoc_int_en_reg) - | uint_en->sirfsoc_cts_en); - else - wr_regl(port, ureg->sirfsoc_int_en_reg, - uint_en->sirfsoc_cts_en); - } else - enable_irq(gpio_to_irq(sirfport->cts_gpio)); -} - -static void sirfsoc_uart_break_ctl(struct uart_port *port, int break_state) -{ - struct sirfsoc_uart_port *sirfport = to_sirfport(port); - struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; - if (sirfport->uart_reg->uart_type == sirf_real_uart) { - unsigned long ulcon = rd_regl(port, ureg->sirfsoc_line_ctrl); - if (break_state) - ulcon |= sirfuart_set_break; - else - ulcon &= ~sirfuart_set_break; - wr_regl(port, ureg->sirfsoc_line_ctrl, ulcon); - } -} - -static unsigned int -sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count) -{ - struct sirfsoc_uart_port *sirfport = to_sirfport(port); - struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; - struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status; - unsigned int ch, rx_count = 0; - struct tty_struct *tty; - tty = tty_port_tty_get(&port->state->port); - if (!tty) - return -enodev; - while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) & - ufifo_st->ff_empty(port))) { - ch = rd_regl(port, ureg->sirfsoc_rx_fifo_data) | - sirfuart_dummy_read; - if (unlikely(uart_handle_sysrq_char(port, ch))) - continue; - uart_insert_char(port, 0, 0, ch, tty_normal); - rx_count++; - if (rx_count >= max_rx_count) - break; - } - - port->icount.rx += rx_count; - - return rx_count; -} - -static unsigned int -sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count) -{ - struct uart_port *port = &sirfport->port; - struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; - struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status; - struct circ_buf *xmit = &port->state->xmit; - unsigned int num_tx = 0; - while (!uart_circ_empty(xmit) && - !(rd_regl(port, ureg->sirfsoc_tx_fifo_status) & - ufifo_st->ff_full(port)) && - count--) { - wr_regl(port, ureg->sirfsoc_tx_fifo_data, - xmit->buf[xmit->tail]); - xmit->tail = (xmit->tail + 1) & (uart_xmit_size - 1); - port->icount.tx++; - num_tx++; - } - if (uart_circ_chars_pending(xmit) < wakeup_chars) - uart_write_wakeup(port); - return num_tx; -} - -static void sirfsoc_uart_tx_dma_complete_callback(void *param) -{ - struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)param; - struct uart_port *port = &sirfport->port; - struct circ_buf *xmit = &port->state->xmit; - unsigned long flags; - - spin_lock_irqsave(&port->lock, flags); - xmit->tail = (xmit->tail + sirfport->transfer_size) & - (uart_xmit_size - 1); - port->icount.tx += sirfport->transfer_size; - if (uart_circ_chars_pending(xmit) < wakeup_chars) - uart_write_wakeup(port); - if (sirfport->tx_dma_addr) - dma_unmap_single(port->dev, sirfport->tx_dma_addr, - sirfport->transfer_size, dma_to_device); - sirfport->tx_dma_state = tx_dma_idle; - sirfsoc_uart_tx_with_dma(sirfport); - spin_unlock_irqrestore(&port->lock, flags); -} - -static irqreturn_t sirfsoc_uart_isr(int irq, void *dev_id) -{ - unsigned long intr_status; - unsigned long cts_status; - unsigned long flag = tty_normal; - struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id; - struct uart_port *port = &sirfport->port; - struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; - struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status; - struct sirfsoc_int_status *uint_st = &sirfport->uart_reg->uart_int_st; - struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; - struct uart_state *state = port->state; - struct circ_buf *xmit = &port->state->xmit; - spin_lock(&port->lock); - intr_status = rd_regl(port, ureg->sirfsoc_int_st_reg); - wr_regl(port, ureg->sirfsoc_int_st_reg, intr_status); - intr_status &= rd_regl(port, ureg->sirfsoc_int_en_reg); - if (unlikely(intr_status & (sirfuart_err_int_stat(uint_st, - sirfport->uart_reg->uart_type)))) { - if (intr_status & uint_st->sirfsoc_rxd_brk) { - port->icount.brk++; - if (uart_handle_break(port)) - goto recv_char; - } - if (intr_status & uint_st->sirfsoc_rx_oflow) { - port->icount.overrun++; - flag = tty_overrun; - } - if (intr_status & uint_st->sirfsoc_frm_err) { - port->icount.frame++; - flag = tty_frame; - } - if (intr_status & uint_st->sirfsoc_parity_err) { - port->icount.parity++; - flag = tty_parity; - } - wr_regl(port, ureg->sirfsoc_rx_fifo_op, sirfuart_fifo_reset); - wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0); - wr_regl(port, ureg->sirfsoc_rx_fifo_op, sirfuart_fifo_start); - intr_status &= port->read_status_mask; - uart_insert_char(port, intr_status, - uint_en->sirfsoc_rx_oflow_en, 0, flag); - } -recv_char: - if ((sirfport->uart_reg->uart_type == sirf_real_uart) && - (intr_status & sirfuart_cts_int_st(uint_st)) && - !sirfport->tx_dma_state) { - cts_status = rd_regl(port, ureg->sirfsoc_afc_ctrl) & - sirfuart_afc_cts_status; - if (cts_status != 0) - cts_status = 0; - else - cts_status = 1; - uart_handle_cts_change(port, cts_status); - wake_up_interruptible(&state->port.delta_msr_wait); - } - if (!sirfport->rx_dma_chan && - (intr_status & sirfuart_rx_io_int_st(uint_st))) { - /* - * chip will trigger continuous rx_timeout interrupt - * in rxfifo empty and not trigger if rxfifo recevice - * data in limit time, original method use rx_timeout - * will trigger lots of useless interrupt in rxfifo - * empty.rxfifo received one byte will trigger rx_done - * interrupt.use rx_done to wait for data received - * into rxfifo, use rx_thd/rx_full for lots data receive - * and use rx_timeout for the last left data. - */ - if (intr_status & uint_st->sirfsoc_rx_done) { - if (!sirfport->is_atlas7) { - wr_regl(port, ureg->sirfsoc_int_en_reg, - rd_regl(port, ureg->sirfsoc_int_en_reg) - & ~(uint_en->sirfsoc_rx_done_en)); - wr_regl(port, ureg->sirfsoc_int_en_reg, - rd_regl(port, ureg->sirfsoc_int_en_reg) - | (uint_en->sirfsoc_rx_timeout_en)); - } else { - wr_regl(port, ureg->sirfsoc_int_en_clr_reg, - uint_en->sirfsoc_rx_done_en); - wr_regl(port, ureg->sirfsoc_int_en_reg, - uint_en->sirfsoc_rx_timeout_en); - } - } else { - if (intr_status & uint_st->sirfsoc_rx_timeout) { - if (!sirfport->is_atlas7) { - wr_regl(port, ureg->sirfsoc_int_en_reg, - rd_regl(port, ureg->sirfsoc_int_en_reg) - & ~(uint_en->sirfsoc_rx_timeout_en)); - wr_regl(port, ureg->sirfsoc_int_en_reg, - rd_regl(port, ureg->sirfsoc_int_en_reg) - | (uint_en->sirfsoc_rx_done_en)); - } else { - wr_regl(port, - ureg->sirfsoc_int_en_clr_reg, - uint_en->sirfsoc_rx_timeout_en); - wr_regl(port, ureg->sirfsoc_int_en_reg, - uint_en->sirfsoc_rx_done_en); - } - } - sirfsoc_uart_pio_rx_chars(port, port->fifosize); - } - } - spin_unlock(&port->lock); - tty_flip_buffer_push(&state->port); - spin_lock(&port->lock); - if (intr_status & uint_st->sirfsoc_txfifo_empty) { - if (sirfport->tx_dma_chan) - sirfsoc_uart_tx_with_dma(sirfport); - else { - if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { - spin_unlock(&port->lock); - return irq_handled; - } else { - sirfsoc_uart_pio_tx_chars(sirfport, - port->fifosize); - if ((uart_circ_empty(xmit)) && - (rd_regl(port, ureg->sirfsoc_tx_fifo_status) & - ufifo_st->ff_empty(port))) - sirfsoc_uart_stop_tx(port); - } - } - } - spin_unlock(&port->lock); - - return irq_handled; -} - -static void sirfsoc_uart_rx_dma_complete_callback(void *param) -{ -} - -/* submit rx dma task into dmaengine */ -static void sirfsoc_uart_start_next_rx_dma(struct uart_port *port) -{ - struct sirfsoc_uart_port *sirfport = to_sirfport(port); - struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; - struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; - wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, - rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) & - ~sirfuart_io_mode); - sirfport->rx_dma_items.xmit.tail = - sirfport->rx_dma_items.xmit.head = 0; - sirfport->rx_dma_items.desc = - dmaengine_prep_dma_cyclic(sirfport->rx_dma_chan, - sirfport->rx_dma_items.dma_addr, sirfsoc_rx_dma_buf_size, - sirfsoc_rx_dma_buf_size / 2, - dma_dev_to_mem, dma_prep_interrupt); - if (is_err_or_null(sirfport->rx_dma_items.desc)) { - dev_err(port->dev, "dma slave single fail "); - return; - } - sirfport->rx_dma_items.desc->callback = - sirfsoc_uart_rx_dma_complete_callback; - sirfport->rx_dma_items.desc->callback_param = sirfport; - sirfport->rx_dma_items.cookie = - dmaengine_submit(sirfport->rx_dma_items.desc); - dma_async_issue_pending(sirfport->rx_dma_chan); - if (!sirfport->is_atlas7) - wr_regl(port, ureg->sirfsoc_int_en_reg, - rd_regl(port, ureg->sirfsoc_int_en_reg) | - sirfuart_rx_dma_int_en(uint_en, - sirfport->uart_reg->uart_type)); - else - wr_regl(port, ureg->sirfsoc_int_en_reg, - sirfuart_rx_dma_int_en(uint_en, - sirfport->uart_reg->uart_type)); -} - -static unsigned int -sirfsoc_usp_calc_sample_div(unsigned long set_rate, - unsigned long ioclk_rate, unsigned long *sample_reg) -{ - unsigned long min_delta = ~0ul; - unsigned short sample_div; - unsigned long ioclk_div = 0; - unsigned long temp_delta; - - for (sample_div = sirf_usp_min_sample_div; - sample_div <= sirf_max_sample_div; sample_div++) { - temp_delta = ioclk_rate - - (ioclk_rate + (set_rate * sample_div) / 2) - / (set_rate * sample_div) * set_rate * sample_div; - - temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta; - if (temp_delta < min_delta) { - ioclk_div = (2 * ioclk_rate / - (set_rate * sample_div) + 1) / 2 - 1; - if (ioclk_div > sirf_ioclk_div_max) - continue; - min_delta = temp_delta; - *sample_reg = sample_div; - if (!temp_delta) - break; - } - } - return ioclk_div; -} - -static unsigned int -sirfsoc_uart_calc_sample_div(unsigned long baud_rate, - unsigned long ioclk_rate, unsigned long *set_baud) -{ - unsigned long min_delta = ~0ul; - unsigned short sample_div; - unsigned int regv = 0; - unsigned long ioclk_div; - unsigned long baud_tmp; - int temp_delta; - - for (sample_div = sirf_min_sample_div; - sample_div <= sirf_max_sample_div; sample_div++) { - ioclk_div = (ioclk_rate / (baud_rate * (sample_div + 1))) - 1; - if (ioclk_div > sirf_ioclk_div_max) - continue; - baud_tmp = ioclk_rate / ((ioclk_div + 1) * (sample_div + 1)); - temp_delta = baud_tmp - baud_rate; - temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta; - if (temp_delta < min_delta) { - regv = regv & (~sirf_ioclk_div_mask); - regv = regv | ioclk_div; - regv = regv & (~sirf_sample_div_mask); - regv = regv | (sample_div << sirf_sample_div_shift); - min_delta = temp_delta; - *set_baud = baud_tmp; - } - } - return regv; -} - -static void sirfsoc_uart_set_termios(struct uart_port *port, - struct ktermios *termios, - struct ktermios *old) -{ - struct sirfsoc_uart_port *sirfport = to_sirfport(port); - struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; - struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; - unsigned long config_reg = 0; - unsigned long baud_rate; - unsigned long set_baud; - unsigned long flags; - unsigned long ic; - unsigned int clk_div_reg = 0; - unsigned long txfifo_op_reg, ioclk_rate; - unsigned long rx_time_out; - int threshold_div; - u32 data_bit_len, stop_bit_len, len_val; - unsigned long sample_div_reg = 0xf; - ioclk_rate = port->uartclk; - - switch (termios->c_cflag & csize) { - default: - case cs8: - data_bit_len = 8; - config_reg |= sirfuart_data_bit_len_8; - break; - case cs7: - data_bit_len = 7; - config_reg |= sirfuart_data_bit_len_7; - break; - case cs6: - data_bit_len = 6; - config_reg |= sirfuart_data_bit_len_6; - break; - case cs5: - data_bit_len = 5; - config_reg |= sirfuart_data_bit_len_5; - break; - } - if (termios->c_cflag & cstopb) { - config_reg |= sirfuart_stop_bit_len_2; - stop_bit_len = 2; - } else - stop_bit_len = 1; - - spin_lock_irqsave(&port->lock, flags); - port->read_status_mask = uint_en->sirfsoc_rx_oflow_en; - port->ignore_status_mask = 0; - if (sirfport->uart_reg->uart_type == sirf_real_uart) { - if (termios->c_iflag & inpck) - port->read_status_mask |= uint_en->sirfsoc_frm_err_en | - uint_en->sirfsoc_parity_err_en; - } else { - if (termios->c_iflag & inpck) - port->read_status_mask |= uint_en->sirfsoc_frm_err_en; - } - if (termios->c_iflag & (ignbrk | brkint | parmrk)) - port->read_status_mask |= uint_en->sirfsoc_rxd_brk_en; - if (sirfport->uart_reg->uart_type == sirf_real_uart) { - if (termios->c_iflag & ignpar) - port->ignore_status_mask |= - uint_en->sirfsoc_frm_err_en | - uint_en->sirfsoc_parity_err_en; - if (termios->c_cflag & parenb) { - if (termios->c_cflag & cmspar) { - if (termios->c_cflag & parodd) - config_reg |= sirfuart_stick_bit_mark; - else - config_reg |= sirfuart_stick_bit_space; - } else { - if (termios->c_cflag & parodd) - config_reg |= sirfuart_stick_bit_odd; - else - config_reg |= sirfuart_stick_bit_even; - } - } - } else { - if (termios->c_iflag & ignpar) - port->ignore_status_mask |= - uint_en->sirfsoc_frm_err_en; - if (termios->c_cflag & parenb) - dev_warn(port->dev, - "usp-uart not support parity err "); - } - if (termios->c_iflag & ignbrk) { - port->ignore_status_mask |= - uint_en->sirfsoc_rxd_brk_en; - if (termios->c_iflag & ignpar) - port->ignore_status_mask |= - uint_en->sirfsoc_rx_oflow_en; - } - if ((termios->c_cflag & cread) == 0) - port->ignore_status_mask |= sirfuart_dummy_read; - /* hardware flow control settings */ - if (uart_enable_ms(port, termios->c_cflag)) { - if (!sirfport->ms_enabled) - sirfsoc_uart_enable_ms(port); - } else { - if (sirfport->ms_enabled) - sirfsoc_uart_disable_ms(port); - } - baud_rate = uart_get_baud_rate(port, termios, old, 0, 4000000); - if (ioclk_rate == 150000000) { - for (ic = 0; ic < sirf_baud_rate_support_nr; ic++) - if (baud_rate == baudrate_to_regv[ic].baud_rate) - clk_div_reg = baudrate_to_regv[ic].reg_val; - } - set_baud = baud_rate; - if (sirfport->uart_reg->uart_type == sirf_real_uart) { - if (unlikely(clk_div_reg == 0)) - clk_div_reg = sirfsoc_uart_calc_sample_div(baud_rate, - ioclk_rate, &set_baud); - wr_regl(port, ureg->sirfsoc_divisor, clk_div_reg); - } else { - clk_div_reg = sirfsoc_usp_calc_sample_div(baud_rate, - ioclk_rate, &sample_div_reg); - sample_div_reg--; - set_baud = ((ioclk_rate / (clk_div_reg+1) - 1) / - (sample_div_reg + 1)); - /* setting usp mode 2 */ - len_val = ((1 << sirfsoc_usp_mode2_rxd_delay_offset) | - (1 << sirfsoc_usp_mode2_txd_delay_offset)); - len_val |= ((clk_div_reg & sirfsoc_usp_mode2_clk_divisor_mask) - << sirfsoc_usp_mode2_clk_divisor_offset); - wr_regl(port, ureg->sirfsoc_mode2, len_val); - } - if (tty_termios_baud_rate(termios)) - tty_termios_encode_baud_rate(termios, set_baud, set_baud); - /* set receive timeout && data bits len */ - rx_time_out = sirfsoc_uart_rx_timeout(set_baud, 20000); - rx_time_out = sirfuart_recv_timeout_value(rx_time_out); - txfifo_op_reg = rd_regl(port, ureg->sirfsoc_tx_fifo_op); - wr_regl(port, ureg->sirfsoc_tx_fifo_op, - (txfifo_op_reg & ~sirfuart_fifo_start)); - if (sirfport->uart_reg->uart_type == sirf_real_uart) { - config_reg |= sirfuart_uart_recv_timeout(rx_time_out); - wr_regl(port, ureg->sirfsoc_line_ctrl, config_reg); - } else { - /*tx frame ctrl*/ - len_val = (data_bit_len - 1) << sirfsoc_usp_tx_data_len_offset; - len_val |= (data_bit_len + 1 + stop_bit_len - 1) << - sirfsoc_usp_tx_frame_len_offset; - len_val |= ((data_bit_len - 1) << - sirfsoc_usp_tx_shifter_len_offset); - len_val |= (((clk_div_reg & 0xc00) >> 10) << - sirfsoc_usp_tx_clk_divisor_offset); - wr_regl(port, ureg->sirfsoc_tx_frame_ctrl, len_val); - /*rx frame ctrl*/ - len_val = (data_bit_len - 1) << sirfsoc_usp_rx_data_len_offset; - len_val |= (data_bit_len + 1 + stop_bit_len - 1) << - sirfsoc_usp_rx_frame_len_offset; - len_val |= (data_bit_len - 1) << - sirfsoc_usp_rx_shifter_len_offset; - len_val |= (((clk_div_reg & 0xf000) >> 12) << - sirfsoc_usp_rx_clk_divisor_offset); - wr_regl(port, ureg->sirfsoc_rx_frame_ctrl, len_val); - /*async param*/ - wr_regl(port, ureg->sirfsoc_async_param_reg, - (sirfuart_usp_recv_timeout(rx_time_out)) | - (sample_div_reg & sirfsoc_usp_async_div2_mask) << - sirfsoc_usp_async_div2_offset); - } - if (sirfport->tx_dma_chan) - wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, sirfuart_dma_mode); - else - wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, sirfuart_io_mode); - if (sirfport->rx_dma_chan) - wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, - rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) & - ~sirfuart_io_mode); - else - wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, - rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) | - sirfuart_io_mode); - sirfport->rx_period_time = 20000000; - /* reset rx/tx fifo threshold level for proper baudrate */ - if (set_baud < 1000000) - threshold_div = 1; - else - threshold_div = 2; - wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl, - sirfuart_fifo_thd(port) / threshold_div); - wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl, - sirfuart_fifo_thd(port) / threshold_div); - txfifo_op_reg |= sirfuart_fifo_start; - wr_regl(port, ureg->sirfsoc_tx_fifo_op, txfifo_op_reg); - uart_update_timeout(port, termios->c_cflag, set_baud); - wr_regl(port, ureg->sirfsoc_tx_rx_en, sirfuart_tx_en | sirfuart_rx_en); - spin_unlock_irqrestore(&port->lock, flags); -} - -static void sirfsoc_uart_pm(struct uart_port *port, unsigned int state, - unsigned int oldstate) -{ - struct sirfsoc_uart_port *sirfport = to_sirfport(port); - if (!state) - clk_prepare_enable(sirfport->clk); - else - clk_disable_unprepare(sirfport->clk); -} - -static int sirfsoc_uart_startup(struct uart_port *port) -{ - struct sirfsoc_uart_port *sirfport = to_sirfport(port); - struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; - struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; - unsigned int index = port->line; - int ret; - irq_modify_status(port->irq, irq_norequest, irq_noautoen); - ret = request_irq(port->irq, - sirfsoc_uart_isr, - 0, - sirfuart_port_name, - sirfport); - if (ret != 0) { - dev_err(port->dev, "uart%d request irq line (%d) failed. ", - index, port->irq); - goto irq_err; - } - /* initial hardware settings */ - wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, - rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl) | - sirfuart_io_mode); - wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, - rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) | - sirfuart_io_mode); - wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, - rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) & - ~sirfuart_rx_dma_flush); - wr_regl(port, ureg->sirfsoc_tx_dma_io_len, 0); - wr_regl(port, ureg->sirfsoc_rx_dma_io_len, 0); - wr_regl(port, ureg->sirfsoc_tx_rx_en, sirfuart_rx_en | sirfuart_tx_en); - if (sirfport->uart_reg->uart_type == sirf_usp_uart) - wr_regl(port, ureg->sirfsoc_mode1, - sirfsoc_usp_endian_ctrl_lsbf | - sirfsoc_usp_en); - wr_regl(port, ureg->sirfsoc_tx_fifo_op, sirfuart_fifo_reset); - wr_regl(port, ureg->sirfsoc_rx_fifo_op, sirfuart_fifo_reset); - wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0); - wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl, sirfuart_fifo_thd(port)); - wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl, sirfuart_fifo_thd(port)); - if (sirfport->rx_dma_chan) - wr_regl(port, ureg->sirfsoc_rx_fifo_level_chk, - sirfuart_rx_fifo_chk_sc(port->line, 0x1) | - sirfuart_rx_fifo_chk_lc(port->line, 0x2) | - sirfuart_rx_fifo_chk_hc(port->line, 0x4)); - if (sirfport->tx_dma_chan) { - sirfport->tx_dma_state = tx_dma_idle; - wr_regl(port, ureg->sirfsoc_tx_fifo_level_chk, - sirfuart_tx_fifo_chk_sc(port->line, 0x1b) | - sirfuart_tx_fifo_chk_lc(port->line, 0xe) | - sirfuart_tx_fifo_chk_hc(port->line, 0x4)); - } - sirfport->ms_enabled = false; - if (sirfport->uart_reg->uart_type == sirf_usp_uart && - sirfport->hw_flow_ctrl) { - irq_modify_status(gpio_to_irq(sirfport->cts_gpio), - irq_norequest, irq_noautoen); - ret = request_irq(gpio_to_irq(sirfport->cts_gpio), - sirfsoc_uart_usp_cts_handler, irqf_trigger_falling | - irqf_trigger_rising, "usp_cts_irq", sirfport); - if (ret != 0) { - dev_err(port->dev, "uart-usp:request gpio irq fail "); - goto init_rx_err; - } - } - if (sirfport->uart_reg->uart_type == sirf_real_uart && - sirfport->rx_dma_chan) - wr_regl(port, ureg->sirfsoc_swh_dma_io, - sirfuart_clear_rx_addr_en); - if (sirfport->uart_reg->uart_type == sirf_usp_uart && - sirfport->rx_dma_chan) - wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, - rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) | - sirfsoc_usp_fraddr_clr_en); - if (sirfport->rx_dma_chan && !sirfport->is_hrt_enabled) { - sirfport->is_hrt_enabled = true; - sirfport->rx_period_time = 20000000; - sirfport->rx_last_pos = -1; - sirfport->pio_fetch_cnt = 0; - sirfport->rx_dma_items.xmit.tail = - sirfport->rx_dma_items.xmit.head = 0; - hrtimer_start(&sirfport->hrt, - ns_to_ktime(sirfport->rx_period_time), - hrtimer_mode_rel); - } - wr_regl(port, ureg->sirfsoc_rx_fifo_op, sirfuart_fifo_start); - if (sirfport->rx_dma_chan) - sirfsoc_uart_start_next_rx_dma(port); - else { - if (!sirfport->is_atlas7) - wr_regl(port, ureg->sirfsoc_int_en_reg, - rd_regl(port, ureg->sirfsoc_int_en_reg) | - sirfuart_rx_io_int_en(uint_en, - sirfport->uart_reg->uart_type)); - else - wr_regl(port, ureg->sirfsoc_int_en_reg, - sirfuart_rx_io_int_en(uint_en, - sirfport->uart_reg->uart_type)); - } - enable_irq(port->irq); - - return 0; -init_rx_err: - free_irq(port->irq, sirfport); -irq_err: - return ret; -} - -static void sirfsoc_uart_shutdown(struct uart_port *port) -{ - struct sirfsoc_uart_port *sirfport = to_sirfport(port); - struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; - struct circ_buf *xmit; - - xmit = &sirfport->rx_dma_items.xmit; - if (!sirfport->is_atlas7) - wr_regl(port, ureg->sirfsoc_int_en_reg, 0); - else - wr_regl(port, ureg->sirfsoc_int_en_clr_reg, ~0ul); - - free_irq(port->irq, sirfport); - if (sirfport->ms_enabled) - sirfsoc_uart_disable_ms(port); - if (sirfport->uart_reg->uart_type == sirf_usp_uart && - sirfport->hw_flow_ctrl) { - gpio_set_value(sirfport->rts_gpio, 1); - free_irq(gpio_to_irq(sirfport->cts_gpio), sirfport); - } - if (sirfport->tx_dma_chan) - sirfport->tx_dma_state = tx_dma_idle; - if (sirfport->rx_dma_chan && sirfport->is_hrt_enabled) { - while (((rd_regl(port, ureg->sirfsoc_rx_fifo_status) & - sirfuart_rx_fifo_mask) > sirfport->pio_fetch_cnt) && - !circ_cnt(xmit->head, xmit->tail, - sirfsoc_rx_dma_buf_size)) - ; - sirfport->is_hrt_enabled = false; - hrtimer_cancel(&sirfport->hrt); - } -} - -static const char *sirfsoc_uart_type(struct uart_port *port) -{ - return port->type == sirfsoc_port_type ? sirfuart_port_name : null; -} - -static int sirfsoc_uart_request_port(struct uart_port *port) -{ - struct sirfsoc_uart_port *sirfport = to_sirfport(port); - struct sirfsoc_uart_param *uart_param = &sirfport->uart_reg->uart_param; - void *ret; - ret = request_mem_region(port->mapbase, - sirfuart_map_size, uart_param->port_name); - return ret ? 0 : -ebusy; -} - -static void sirfsoc_uart_release_port(struct uart_port *port) -{ - release_mem_region(port->mapbase, sirfuart_map_size); -} - -static void sirfsoc_uart_config_port(struct uart_port *port, int flags) -{ - if (flags & uart_config_type) { - port->type = sirfsoc_port_type; - sirfsoc_uart_request_port(port); - } -} - -static const struct uart_ops sirfsoc_uart_ops = { - .tx_empty = sirfsoc_uart_tx_empty, - .get_mctrl = sirfsoc_uart_get_mctrl, - .set_mctrl = sirfsoc_uart_set_mctrl, - .stop_tx = sirfsoc_uart_stop_tx, - .start_tx = sirfsoc_uart_start_tx, - .stop_rx = sirfsoc_uart_stop_rx, - .enable_ms = sirfsoc_uart_enable_ms, - .break_ctl = sirfsoc_uart_break_ctl, - .startup = sirfsoc_uart_startup, - .shutdown = sirfsoc_uart_shutdown, - .set_termios = sirfsoc_uart_set_termios, - .pm = sirfsoc_uart_pm, - .type = sirfsoc_uart_type, - .release_port = sirfsoc_uart_release_port, - .request_port = sirfsoc_uart_request_port, - .config_port = sirfsoc_uart_config_port, -}; - -#ifdef config_serial_sirfsoc_console -static int __init -sirfsoc_uart_console_setup(struct console *co, char *options) -{ - unsigned int baud = 115200; - unsigned int bits = 8; - unsigned int parity = 'n'; - unsigned int flow = 'n'; - struct sirfsoc_uart_port *sirfport; - struct sirfsoc_register *ureg; - if (co->index < 0 || co->index >= sirfsoc_uart_nr) - co->index = 1; - sirfport = sirf_ports[co->index]; - if (!sirfport) - return -enodev; - ureg = &sirfport->uart_reg->uart_reg; - if (!sirfport->port.mapbase) - return -enodev; - - /* enable usp in mode1 register */ - if (sirfport->uart_reg->uart_type == sirf_usp_uart) - wr_regl(&sirfport->port, ureg->sirfsoc_mode1, sirfsoc_usp_en | - sirfsoc_usp_endian_ctrl_lsbf); - if (options) - uart_parse_options(options, &baud, &parity, &bits, &flow); - sirfport->port.cons = co; - - /* default console tx/rx transfer using io mode */ - sirfport->rx_dma_chan = null; - sirfport->tx_dma_chan = null; - return uart_set_options(&sirfport->port, co, baud, parity, bits, flow); -} - -static void sirfsoc_uart_console_putchar(struct uart_port *port, int ch) -{ - struct sirfsoc_uart_port *sirfport = to_sirfport(port); - struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; - struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status; - while (rd_regl(port, ureg->sirfsoc_tx_fifo_status) & - ufifo_st->ff_full(port)) - cpu_relax(); - wr_regl(port, ureg->sirfsoc_tx_fifo_data, ch); -} - -static void sirfsoc_uart_console_write(struct console *co, const char *s, - unsigned int count) -{ - struct sirfsoc_uart_port *sirfport = sirf_ports[co->index]; - - uart_console_write(&sirfport->port, s, count, - sirfsoc_uart_console_putchar); -} - -static struct console sirfsoc_uart_console = { - .name = sirfsoc_uart_name, - .device = uart_console_device, - .flags = con_printbuffer, - .index = -1, - .write = sirfsoc_uart_console_write, - .setup = sirfsoc_uart_console_setup, - .data = &sirfsoc_uart_drv, -}; - -static int __init sirfsoc_uart_console_init(void) -{ - register_console(&sirfsoc_uart_console); - return 0; -} -console_initcall(sirfsoc_uart_console_init); -#endif - -static struct uart_driver sirfsoc_uart_drv = { - .owner = this_module, - .driver_name = sirfuart_port_name, - .nr = sirfsoc_uart_nr, - .dev_name = sirfsoc_uart_name, - .major = sirfsoc_uart_major, - .minor = sirfsoc_uart_minor, -#ifdef config_serial_sirfsoc_console - .cons = &sirfsoc_uart_console, -#else - .cons = null, -#endif -}; - -static enum hrtimer_restart - sirfsoc_uart_rx_dma_hrtimer_callback(struct hrtimer *hrt) -{ - struct sirfsoc_uart_port *sirfport; - struct uart_port *port; - int count, inserted; - struct dma_tx_state tx_state; - struct tty_struct *tty; - struct sirfsoc_register *ureg; - struct circ_buf *xmit; - struct sirfsoc_fifo_status *ufifo_st; - int max_pio_cnt; - - sirfport = container_of(hrt, struct sirfsoc_uart_port, hrt); - port = &sirfport->port; - inserted = 0; - tty = port->state->port.tty; - ureg = &sirfport->uart_reg->uart_reg; - xmit = &sirfport->rx_dma_items.xmit; - ufifo_st = &sirfport->uart_reg->fifo_status; - - dmaengine_tx_status(sirfport->rx_dma_chan, - sirfport->rx_dma_items.cookie, &tx_state); - if (sirfsoc_rx_dma_buf_size - tx_state.residue != - sirfport->rx_last_pos) { - xmit->head = sirfsoc_rx_dma_buf_size - tx_state.residue; - sirfport->rx_last_pos = xmit->head; - sirfport->pio_fetch_cnt = 0; - } - count = circ_cnt_to_end(xmit->head, xmit->tail, - sirfsoc_rx_dma_buf_size); - while (count > 0) { - inserted = tty_insert_flip_string(tty->port, - (const unsigned char *)&xmit->buf[xmit->tail], count); - if (!inserted) - goto next_hrt; - port->icount.rx += inserted; - xmit->tail = (xmit->tail + inserted) & - (sirfsoc_rx_dma_buf_size - 1); - count = circ_cnt_to_end(xmit->head, xmit->tail, - sirfsoc_rx_dma_buf_size); - tty_flip_buffer_push(tty->port); - } - /* - * if rx dma buffer data have all push into tty buffer, and there is - * only little data(less than a dma transfer unit) left in rxfifo, - * fetch it out in pio mode and switch back to dma immediately - */ - if (!inserted && !count && - ((rd_regl(port, ureg->sirfsoc_rx_fifo_status) & - sirfuart_rx_fifo_mask) > sirfport->pio_fetch_cnt)) { - dmaengine_pause(sirfport->rx_dma_chan); - /* switch to pio mode */ - wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, - rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) | - sirfuart_io_mode); - /* - * uart controller swh_dma_io register have clear_rx_addr_en - * when found changing i/o to dma mode, it clears - * two low bits of read point; - * usp have similar fraddr_clr_en bit in usp_rx_dma_io_ctrl. - * fetch data out from rxfifo into dma buffer in pio mode, - * while switch back to dma mode, the data fetched will override - * by dma, as hardware have a strange behaviour: - * after switch back to dma mode, check rxfifo status it will - * be the number pio fetched, so record the fetched data count - * to avoid the repeated fetch - */ - max_pio_cnt = 3; - while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) & - ufifo_st->ff_empty(port)) && max_pio_cnt--) { - xmit->buf[xmit->head] = - rd_regl(port, ureg->sirfsoc_rx_fifo_data); - xmit->head = (xmit->head + 1) & - (sirfsoc_rx_dma_buf_size - 1); - sirfport->pio_fetch_cnt++; - } - /* switch back to dma mode */ - wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, - rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) & - ~sirfuart_io_mode); - dmaengine_resume(sirfport->rx_dma_chan); - } -next_hrt: - hrtimer_forward_now(hrt, ns_to_ktime(sirfport->rx_period_time)); - return hrtimer_restart; -} - -static const struct of_device_id sirfsoc_uart_ids[] = { - { .compatible = "sirf,prima2-uart", .data = &sirfsoc_uart,}, - { .compatible = "sirf,atlas7-uart", .data = &sirfsoc_uart}, - { .compatible = "sirf,prima2-usp-uart", .data = &sirfsoc_usp}, - { .compatible = "sirf,atlas7-usp-uart", .data = &sirfsoc_usp}, - {} -}; -module_device_table(of, sirfsoc_uart_ids); - -static int sirfsoc_uart_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct sirfsoc_uart_port *sirfport; - struct uart_port *port; - struct resource *res; - int ret; - struct dma_slave_config slv_cfg = { - .src_maxburst = 1, - }; - struct dma_slave_config tx_slv_cfg = { - .dst_maxburst = 2, - }; - const struct of_device_id *match; - - match = of_match_node(sirfsoc_uart_ids, np); - sirfport = devm_kzalloc(&pdev->dev, sizeof(*sirfport), gfp_kernel); - if (!sirfport) { - ret = -enomem; - goto err; - } - sirfport->port.line = of_alias_get_id(np, "serial"); - if (sirfport->port.line >= array_size(sirf_ports)) { - dev_err(&pdev->dev, "serial%d out of range ", - sirfport->port.line); - return -einval; - } - sirf_ports[sirfport->port.line] = sirfport; - sirfport->port.iotype = upio_mem; - sirfport->port.flags = upf_boot_autoconf; - port = &sirfport->port; - port->dev = &pdev->dev; - port->private_data = sirfport; - sirfport->uart_reg = (struct sirfsoc_uart_register *)match->data; - - sirfport->hw_flow_ctrl = - of_property_read_bool(np, "uart-has-rtscts") || - of_property_read_bool(np, "sirf,uart-has-rtscts") /* deprecated */; - if (of_device_is_compatible(np, "sirf,prima2-uart") || - of_device_is_compatible(np, "sirf,atlas7-uart")) - sirfport->uart_reg->uart_type = sirf_real_uart; - if (of_device_is_compatible(np, "sirf,prima2-usp-uart") || - of_device_is_compatible(np, "sirf,atlas7-usp-uart")) { - sirfport->uart_reg->uart_type = sirf_usp_uart; - if (!sirfport->hw_flow_ctrl) - goto usp_no_flow_control; - if (of_find_property(np, "cts-gpios", null)) - sirfport->cts_gpio = - of_get_named_gpio(np, "cts-gpios", 0); - else - sirfport->cts_gpio = -1; - if (of_find_property(np, "rts-gpios", null)) - sirfport->rts_gpio = - of_get_named_gpio(np, "rts-gpios", 0); - else - sirfport->rts_gpio = -1; - - if ((!gpio_is_valid(sirfport->cts_gpio) || - !gpio_is_valid(sirfport->rts_gpio))) { - ret = -einval; - dev_err(&pdev->dev, - "usp flow control must have cts and rts gpio"); - goto err; - } - ret = devm_gpio_request(&pdev->dev, sirfport->cts_gpio, - "usp-cts-gpio"); - if (ret) { - dev_err(&pdev->dev, "unable request cts gpio"); - goto err; - } - gpio_direction_input(sirfport->cts_gpio); - ret = devm_gpio_request(&pdev->dev, sirfport->rts_gpio, - "usp-rts-gpio"); - if (ret) { - dev_err(&pdev->dev, "unable request rts gpio"); - goto err; - } - gpio_direction_output(sirfport->rts_gpio, 1); - } -usp_no_flow_control: - if (of_device_is_compatible(np, "sirf,atlas7-uart") || - of_device_is_compatible(np, "sirf,atlas7-usp-uart")) - sirfport->is_atlas7 = true; - - if (of_property_read_u32(np, "fifosize", &port->fifosize)) { - dev_err(&pdev->dev, - "unable to find fifosize in uart node. "); - ret = -efault; - goto err; - } - - res = platform_get_resource(pdev, ioresource_mem, 0); - if (res == null) { - dev_err(&pdev->dev, "insufficient resources. "); - ret = -efault; - goto err; - } - port->mapbase = res->start; - port->membase = devm_ioremap(&pdev->dev, - res->start, resource_size(res)); - if (!port->membase) { - dev_err(&pdev->dev, "cannot remap resource. "); - ret = -enomem; - goto err; - } - res = platform_get_resource(pdev, ioresource_irq, 0); - if (res == null) { - dev_err(&pdev->dev, "insufficient resources. "); - ret = -efault; - goto err; - } - port->irq = res->start; - - sirfport->clk = devm_clk_get(&pdev->dev, null); - if (is_err(sirfport->clk)) { - ret = ptr_err(sirfport->clk); - goto err; - } - port->uartclk = clk_get_rate(sirfport->clk); - - port->ops = &sirfsoc_uart_ops; - spin_lock_init(&port->lock); - - platform_set_drvdata(pdev, sirfport); - ret = uart_add_one_port(&sirfsoc_uart_drv, port); - if (ret != 0) { - dev_err(&pdev->dev, "cannot add uart port(%d). ", pdev->id); - goto err; - } - - sirfport->rx_dma_chan = dma_request_slave_channel(port->dev, "rx"); - sirfport->rx_dma_items.xmit.buf = - dma_alloc_coherent(port->dev, sirfsoc_rx_dma_buf_size, - &sirfport->rx_dma_items.dma_addr, gfp_kernel); - if (!sirfport->rx_dma_items.xmit.buf) { - dev_err(port->dev, "uart alloc bufa failed "); - ret = -enomem; - goto alloc_coherent_err; - } - sirfport->rx_dma_items.xmit.head = - sirfport->rx_dma_items.xmit.tail = 0; - if (sirfport->rx_dma_chan) - dmaengine_slave_config(sirfport->rx_dma_chan, &slv_cfg); - sirfport->tx_dma_chan = dma_request_slave_channel(port->dev, "tx"); - if (sirfport->tx_dma_chan) - dmaengine_slave_config(sirfport->tx_dma_chan, &tx_slv_cfg); - if (sirfport->rx_dma_chan) { - hrtimer_init(&sirfport->hrt, clock_monotonic, hrtimer_mode_rel); - sirfport->hrt.function = sirfsoc_uart_rx_dma_hrtimer_callback; - sirfport->is_hrt_enabled = false; - } - - return 0; -alloc_coherent_err: - dma_free_coherent(port->dev, sirfsoc_rx_dma_buf_size, - sirfport->rx_dma_items.xmit.buf, - sirfport->rx_dma_items.dma_addr); - dma_release_channel(sirfport->rx_dma_chan); -err: - return ret; -} - -static int sirfsoc_uart_remove(struct platform_device *pdev) -{ - struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev); - struct uart_port *port = &sirfport->port; - uart_remove_one_port(&sirfsoc_uart_drv, port); - if (sirfport->rx_dma_chan) { - dmaengine_terminate_all(sirfport->rx_dma_chan); - dma_release_channel(sirfport->rx_dma_chan); - dma_free_coherent(port->dev, sirfsoc_rx_dma_buf_size, - sirfport->rx_dma_items.xmit.buf, - sirfport->rx_dma_items.dma_addr); - } - if (sirfport->tx_dma_chan) { - dmaengine_terminate_all(sirfport->tx_dma_chan); - dma_release_channel(sirfport->tx_dma_chan); - } - return 0; -} - -#ifdef config_pm_sleep -static int -sirfsoc_uart_suspend(struct device *pdev) -{ - struct sirfsoc_uart_port *sirfport = dev_get_drvdata(pdev); - struct uart_port *port = &sirfport->port; - uart_suspend_port(&sirfsoc_uart_drv, port); - return 0; -} - -static int sirfsoc_uart_resume(struct device *pdev) -{ - struct sirfsoc_uart_port *sirfport = dev_get_drvdata(pdev); - struct uart_port *port = &sirfport->port; - uart_resume_port(&sirfsoc_uart_drv, port); - return 0; -} -#endif - -static const struct dev_pm_ops sirfsoc_uart_pm_ops = { - set_system_sleep_pm_ops(sirfsoc_uart_suspend, sirfsoc_uart_resume) -}; - -static struct platform_driver sirfsoc_uart_driver = { - .probe = sirfsoc_uart_probe, - .remove = sirfsoc_uart_remove, - .driver = { - .name = sirfuart_port_name, - .of_match_table = sirfsoc_uart_ids, - .pm = &sirfsoc_uart_pm_ops, - }, -}; - -static int __init sirfsoc_uart_init(void) -{ - int ret = 0; - - ret = uart_register_driver(&sirfsoc_uart_drv); - if (ret) - goto out; - - ret = platform_driver_register(&sirfsoc_uart_driver); - if (ret) - uart_unregister_driver(&sirfsoc_uart_drv); -out: - return ret; -} -module_init(sirfsoc_uart_init); - -static void __exit sirfsoc_uart_exit(void) -{ - platform_driver_unregister(&sirfsoc_uart_driver); - uart_unregister_driver(&sirfsoc_uart_drv); -} -module_exit(sirfsoc_uart_exit); - -module_license("gpl v2"); -module_author("bin shi <bin.shi@csr.com>, rong wang<rong.wang@csr.com>"); -module_description("csr sirfprimaii uart driver"); diff --git a/drivers/tty/serial/sirfsoc_uart.h b/drivers/tty/serial/sirfsoc_uart.h --- a/drivers/tty/serial/sirfsoc_uart.h +++ /dev/null -/* spdx-license-identifier: gpl-2.0+ */ -/* - * drivers for csr sirfprimaii onboard uarts. - * - * copyright (c) 2011 cambridge silicon radio limited, a csr plc group company. - */ -#include <linux/bitops.h> -#include <linux/log2.h> -#include <linux/hrtimer.h> -struct sirfsoc_uart_param { - const char *uart_name; - const char *port_name; -}; - -struct sirfsoc_register { - /* hardware uart specific */ - u32 sirfsoc_line_ctrl; - u32 sirfsoc_divisor; - /* uart - usp common */ - u32 sirfsoc_tx_rx_en; - u32 sirfsoc_int_en_reg; - u32 sirfsoc_int_st_reg; - u32 sirfsoc_int_en_clr_reg; - u32 sirfsoc_tx_dma_io_ctrl; - u32 sirfsoc_tx_dma_io_len; - u32 sirfsoc_tx_fifo_ctrl; - u32 sirfsoc_tx_fifo_level_chk; - u32 sirfsoc_tx_fifo_op; - u32 sirfsoc_tx_fifo_status; - u32 sirfsoc_tx_fifo_data; - u32 sirfsoc_rx_dma_io_ctrl; - u32 sirfsoc_rx_dma_io_len; - u32 sirfsoc_rx_fifo_ctrl; - u32 sirfsoc_rx_fifo_level_chk; - u32 sirfsoc_rx_fifo_op; - u32 sirfsoc_rx_fifo_status; - u32 sirfsoc_rx_fifo_data; - u32 sirfsoc_afc_ctrl; - u32 sirfsoc_swh_dma_io; - /* hardware usp specific */ - u32 sirfsoc_mode1; - u32 sirfsoc_mode2; - u32 sirfsoc_tx_frame_ctrl; - u32 sirfsoc_rx_frame_ctrl; - u32 sirfsoc_async_param_reg; -}; - -typedef u32 (*fifo_full_mask)(struct uart_port *port); -typedef u32 (*fifo_empty_mask)(struct uart_port *port); - -struct sirfsoc_fifo_status { - fifo_full_mask ff_full; - fifo_empty_mask ff_empty; -}; - -struct sirfsoc_int_en { - u32 sirfsoc_rx_done_en; - u32 sirfsoc_tx_done_en; - u32 sirfsoc_rx_oflow_en; - u32 sirfsoc_tx_allout_en; - u32 sirfsoc_rx_io_dma_en; - u32 sirfsoc_tx_io_dma_en; - u32 sirfsoc_rxfifo_full_en; - u32 sirfsoc_txfifo_empty_en; - u32 sirfsoc_rxfifo_thd_en; - u32 sirfsoc_txfifo_thd_en; - u32 sirfsoc_frm_err_en; - u32 sirfsoc_rxd_brk_en; - u32 sirfsoc_rx_timeout_en; - u32 sirfsoc_parity_err_en; - u32 sirfsoc_cts_en; - u32 sirfsoc_rts_en; -}; - -struct sirfsoc_int_status { - u32 sirfsoc_rx_done; - u32 sirfsoc_tx_done; - u32 sirfsoc_rx_oflow; - u32 sirfsoc_tx_allout; - u32 sirfsoc_rx_io_dma; - u32 sirfsoc_tx_io_dma; - u32 sirfsoc_rxfifo_full; - u32 sirfsoc_txfifo_empty; - u32 sirfsoc_rxfifo_thd; - u32 sirfsoc_txfifo_thd; - u32 sirfsoc_frm_err; - u32 sirfsoc_rxd_brk; - u32 sirfsoc_rx_timeout; - u32 sirfsoc_parity_err; - u32 sirfsoc_cts; - u32 sirfsoc_rts; -}; - -enum sirfsoc_uart_type { - sirf_real_uart, - sirf_usp_uart, -}; - -struct sirfsoc_uart_register { - struct sirfsoc_register uart_reg; - struct sirfsoc_int_en uart_int_en; - struct sirfsoc_int_status uart_int_st; - struct sirfsoc_fifo_status fifo_status; - struct sirfsoc_uart_param uart_param; - enum sirfsoc_uart_type uart_type; -}; - -static u32 uart_usp_ff_full_mask(struct uart_port *port) -{ - u32 full_bit; - - full_bit = ilog2(port->fifosize); - return (1 << full_bit); -} - -static u32 uart_usp_ff_empty_mask(struct uart_port *port) -{ - u32 empty_bit; - - empty_bit = ilog2(port->fifosize) + 1; - return (1 << empty_bit); -} - -static struct sirfsoc_uart_register sirfsoc_usp = { - .uart_reg = { - .sirfsoc_mode1 = 0x0000, - .sirfsoc_mode2 = 0x0004, - .sirfsoc_tx_frame_ctrl = 0x0008, - .sirfsoc_rx_frame_ctrl = 0x000c, - .sirfsoc_tx_rx_en = 0x0010, - .sirfsoc_int_en_reg = 0x0014, - .sirfsoc_int_st_reg = 0x0018, - .sirfsoc_async_param_reg = 0x0024, - .sirfsoc_tx_dma_io_ctrl = 0x0100, - .sirfsoc_tx_dma_io_len = 0x0104, - .sirfsoc_tx_fifo_ctrl = 0x0108, - .sirfsoc_tx_fifo_level_chk = 0x010c, - .sirfsoc_tx_fifo_op = 0x0110, - .sirfsoc_tx_fifo_status = 0x0114, - .sirfsoc_tx_fifo_data = 0x0118, - .sirfsoc_rx_dma_io_ctrl = 0x0120, - .sirfsoc_rx_dma_io_len = 0x0124, - .sirfsoc_rx_fifo_ctrl = 0x0128, - .sirfsoc_rx_fifo_level_chk = 0x012c, - .sirfsoc_rx_fifo_op = 0x0130, - .sirfsoc_rx_fifo_status = 0x0134, - .sirfsoc_rx_fifo_data = 0x0138, - .sirfsoc_int_en_clr_reg = 0x140, - }, - .uart_int_en = { - .sirfsoc_rx_done_en = bit(0), - .sirfsoc_tx_done_en = bit(1), - .sirfsoc_rx_oflow_en = bit(2), - .sirfsoc_tx_allout_en = bit(3), - .sirfsoc_rx_io_dma_en = bit(4), - .sirfsoc_tx_io_dma_en = bit(5), - .sirfsoc_rxfifo_full_en = bit(6), - .sirfsoc_txfifo_empty_en = bit(7), - .sirfsoc_rxfifo_thd_en = bit(8), - .sirfsoc_txfifo_thd_en = bit(9), - .sirfsoc_frm_err_en = bit(10), - .sirfsoc_rx_timeout_en = bit(11), - .sirfsoc_rxd_brk_en = bit(15), - }, - .uart_int_st = { - .sirfsoc_rx_done = bit(0), - .sirfsoc_tx_done = bit(1), - .sirfsoc_rx_oflow = bit(2), - .sirfsoc_tx_allout = bit(3), - .sirfsoc_rx_io_dma = bit(4), - .sirfsoc_tx_io_dma = bit(5), - .sirfsoc_rxfifo_full = bit(6), - .sirfsoc_txfifo_empty = bit(7), - .sirfsoc_rxfifo_thd = bit(8), - .sirfsoc_txfifo_thd = bit(9), - .sirfsoc_frm_err = bit(10), - .sirfsoc_rx_timeout = bit(11), - .sirfsoc_rxd_brk = bit(15), - }, - .fifo_status = { - .ff_full = uart_usp_ff_full_mask, - .ff_empty = uart_usp_ff_empty_mask, - }, - .uart_param = { - .uart_name = "ttysirf", - .port_name = "sirfsoc-uart", - }, -}; - -static struct sirfsoc_uart_register sirfsoc_uart = { - .uart_reg = { - .sirfsoc_line_ctrl = 0x0040, - .sirfsoc_tx_rx_en = 0x004c, - .sirfsoc_divisor = 0x0050, - .sirfsoc_int_en_reg = 0x0054, - .sirfsoc_int_st_reg = 0x0058, - .sirfsoc_int_en_clr_reg = 0x0060, - .sirfsoc_tx_dma_io_ctrl = 0x0100, - .sirfsoc_tx_dma_io_len = 0x0104, - .sirfsoc_tx_fifo_ctrl = 0x0108, - .sirfsoc_tx_fifo_level_chk = 0x010c, - .sirfsoc_tx_fifo_op = 0x0110, - .sirfsoc_tx_fifo_status = 0x0114, - .sirfsoc_tx_fifo_data = 0x0118, - .sirfsoc_rx_dma_io_ctrl = 0x0120, - .sirfsoc_rx_dma_io_len = 0x0124, - .sirfsoc_rx_fifo_ctrl = 0x0128, - .sirfsoc_rx_fifo_level_chk = 0x012c, - .sirfsoc_rx_fifo_op = 0x0130, - .sirfsoc_rx_fifo_status = 0x0134, - .sirfsoc_rx_fifo_data = 0x0138, - .sirfsoc_afc_ctrl = 0x0140, - .sirfsoc_swh_dma_io = 0x0148, - }, - .uart_int_en = { - .sirfsoc_rx_done_en = bit(0), - .sirfsoc_tx_done_en = bit(1), - .sirfsoc_rx_oflow_en = bit(2), - .sirfsoc_tx_allout_en = bit(3), - .sirfsoc_rx_io_dma_en = bit(4), - .sirfsoc_tx_io_dma_en = bit(5), - .sirfsoc_rxfifo_full_en = bit(6), - .sirfsoc_txfifo_empty_en = bit(7), - .sirfsoc_rxfifo_thd_en = bit(8), - .sirfsoc_txfifo_thd_en = bit(9), - .sirfsoc_frm_err_en = bit(10), - .sirfsoc_rxd_brk_en = bit(11), - .sirfsoc_rx_timeout_en = bit(12), - .sirfsoc_parity_err_en = bit(13), - .sirfsoc_cts_en = bit(14), - .sirfsoc_rts_en = bit(15), - }, - .uart_int_st = { - .sirfsoc_rx_done = bit(0), - .sirfsoc_tx_done = bit(1), - .sirfsoc_rx_oflow = bit(2), - .sirfsoc_tx_allout = bit(3), - .sirfsoc_rx_io_dma = bit(4), - .sirfsoc_tx_io_dma = bit(5), - .sirfsoc_rxfifo_full = bit(6), - .sirfsoc_txfifo_empty = bit(7), - .sirfsoc_rxfifo_thd = bit(8), - .sirfsoc_txfifo_thd = bit(9), - .sirfsoc_frm_err = bit(10), - .sirfsoc_rxd_brk = bit(11), - .sirfsoc_rx_timeout = bit(12), - .sirfsoc_parity_err = bit(13), - .sirfsoc_cts = bit(14), - .sirfsoc_rts = bit(15), - }, - .fifo_status = { - .ff_full = uart_usp_ff_full_mask, - .ff_empty = uart_usp_ff_empty_mask, - }, - .uart_param = { - .uart_name = "ttysirf", - .port_name = "sirfsoc_uart", - }, -}; -/* uart io ctrl */ -#define sirfuart_data_bit_len_mask 0x3 -#define sirfuart_data_bit_len_5 bit(0) -#define sirfuart_data_bit_len_6 1 -#define sirfuart_data_bit_len_7 2 -#define sirfuart_data_bit_len_8 3 -#define sirfuart_stop_bit_len_1 0 -#define sirfuart_stop_bit_len_2 bit(2) -#define sirfuart_parity_en bit(3) -#define sirfuart_even_bit bit(4) -#define sirfuart_stick_bit_mask (7 << 3) -#define sirfuart_stick_bit_none (0 << 3) -#define sirfuart_stick_bit_even bit(3) -#define sirfuart_stick_bit_odd (3 << 3) -#define sirfuart_stick_bit_mark (5 << 3) -#define sirfuart_stick_bit_space (7 << 3) -#define sirfuart_set_break bit(6) -#define sirfuart_loop_back bit(7) -#define sirfuart_parity_mask (7 << 3) -#define sirfuart_dummy_read bit(16) -#define sirfuart_afc_ctrl_rx_thd 0x70 -#define sirfuart_afc_rx_en bit(8) -#define sirfuart_afc_tx_en bit(9) -#define sirfuart_afc_cts_ctrl bit(10) -#define sirfuart_afc_rts_ctrl bit(11) -#define sirfuart_afc_cts_status bit(12) -#define sirfuart_afc_rts_status bit(13) -/* uart fifo register */ -#define sirfuart_fifo_stop 0x0 -#define sirfuart_fifo_reset bit(0) -#define sirfuart_fifo_start bit(1) - -#define sirfuart_rx_en bit(0) -#define sirfuart_tx_en bit(1) - -#define sirfuart_io_mode bit(0) -#define sirfuart_dma_mode 0x0 -#define sirfuart_rx_dma_flush 0x4 - -#define sirfuart_clear_rx_addr_en 0x2 -/* baud rate calculation */ -#define sirf_usp_min_sample_div 0x1 -#define sirf_min_sample_div 0xf -#define sirf_max_sample_div 0x3f -#define sirf_ioclk_div_max 0xffff -#define sirf_sample_div_shift 16 -#define sirf_ioclk_div_mask 0xffff -#define sirf_sample_div_mask 0x3f0000 -#define sirf_baud_rate_support_nr 18 - -/* usp spec */ -#define sirfsoc_usp_endian_ctrl_lsbf bit(4) -#define sirfsoc_usp_en bit(5) -#define sirfsoc_usp_mode2_rxd_delay_offset 0 -#define sirfsoc_usp_mode2_txd_delay_offset 8 -#define sirfsoc_usp_mode2_clk_divisor_mask 0x3ff -#define sirfsoc_usp_mode2_clk_divisor_offset 21 -#define sirfsoc_usp_tx_data_len_offset 0 -#define sirfsoc_usp_tx_sync_len_offset 8 -#define sirfsoc_usp_tx_frame_len_offset 16 -#define sirfsoc_usp_tx_shifter_len_offset 24 -#define sirfsoc_usp_tx_clk_divisor_offset 30 -#define sirfsoc_usp_rx_data_len_offset 0 -#define sirfsoc_usp_rx_frame_len_offset 8 -#define sirfsoc_usp_rx_shifter_len_offset 16 -#define sirfsoc_usp_rx_clk_divisor_offset 24 -#define sirfsoc_usp_async_div2_mask 0x3f -#define sirfsoc_usp_async_div2_offset 16 -#define sirfsoc_usp_loop_back_ctrl bit(2) -#define sirfsoc_usp_fraddr_clr_en bit(1) -/* usp-uart common */ -#define sirfsoc_uart_rx_timeout(br, to) (((br) * (((to) + 999) / 1000)) / 1000) -#define sirfuart_recv_timeout_value(x) \ - (((x) > 0xffff) ? 0xffff : ((x) & 0xffff)) -#define sirfuart_usp_recv_timeout(x) (x & 0xffff) -#define sirfuart_uart_recv_timeout(x) ((x & 0xffff) << 16) - -#define sirfuart_fifo_thd(port) (port->fifosize >> 1) -#define sirfuart_err_int_stat(unit_st, uart_type) \ - (uint_st->sirfsoc_rx_oflow | \ - uint_st->sirfsoc_frm_err | \ - uint_st->sirfsoc_rxd_brk | \ - ((uart_type != sirf_real_uart) ? \ - 0 : uint_st->sirfsoc_parity_err)) -#define sirfuart_rx_io_int_en(uint_en, uart_type) \ - (uint_en->sirfsoc_rx_done_en |\ - uint_en->sirfsoc_rxfifo_thd_en |\ - uint_en->sirfsoc_rxfifo_full_en |\ - uint_en->sirfsoc_frm_err_en |\ - uint_en->sirfsoc_rx_oflow_en |\ - uint_en->sirfsoc_rxd_brk_en |\ - ((uart_type != sirf_real_uart) ? \ - 0 : uint_en->sirfsoc_parity_err_en)) -#define sirfuart_rx_io_int_st(uint_st) \ - (uint_st->sirfsoc_rxfifo_thd |\ - uint_st->sirfsoc_rxfifo_full|\ - uint_st->sirfsoc_rx_done |\ - uint_st->sirfsoc_rx_timeout) -#define sirfuart_cts_int_st(uint_st) (uint_st->sirfsoc_cts) -#define sirfuart_rx_dma_int_en(uint_en, uart_type) \ - (uint_en->sirfsoc_frm_err_en |\ - uint_en->sirfsoc_rx_oflow_en |\ - uint_en->sirfsoc_rxd_brk_en |\ - ((uart_type != sirf_real_uart) ? \ - 0 : uint_en->sirfsoc_parity_err_en)) -/* generic definitions */ -#define sirfsoc_uart_name "ttysirf" -#define sirfsoc_uart_major 0 -#define sirfsoc_uart_minor 0 -#define sirfuart_port_name "sirfsoc-uart" -#define sirfuart_map_size 0x200 -#define sirfsoc_uart_nr 11 -#define sirfsoc_port_type 0xa5 - -/* uart common use macro*/ -#define sirfsoc_rx_dma_buf_size (1024 * 32) -#define bytes_to_align(dma_addr) ((unsigned long)(dma_addr) & 0x3) -/* uart fifo level chk */ -#define sirfuart_tx_fifo_sc_offset 0 -#define sirfuart_tx_fifo_lc_offset 10 -#define sirfuart_tx_fifo_hc_offset 20 -#define sirfuart_tx_fifo_chk_sc(line, value) ((((line) == 1) ? (value & 0x3) :\ - (value & 0x1f)) << sirfuart_tx_fifo_sc_offset) -#define sirfuart_tx_fifo_chk_lc(line, value) ((((line) == 1) ? (value & 0x3) :\ - (value & 0x1f)) << sirfuart_tx_fifo_lc_offset) -#define sirfuart_tx_fifo_chk_hc(line, value) ((((line) == 1) ? (value & 0x3) :\ - (value & 0x1f)) << sirfuart_tx_fifo_hc_offset) - -#define sirfuart_rx_fifo_chk_sc sirfuart_tx_fifo_chk_sc -#define sirfuart_rx_fifo_chk_lc sirfuart_tx_fifo_chk_lc -#define sirfuart_rx_fifo_chk_hc sirfuart_tx_fifo_chk_hc -#define sirfuart_rx_fifo_mask 0x7f -/* indicate how many buffers used */ - -/* for fast baud rate calculation */ -struct sirfsoc_baudrate_to_regv { - unsigned int baud_rate; - unsigned int reg_val; -}; - -enum sirfsoc_tx_state { - tx_dma_idle, - tx_dma_running, - tx_dma_pause, -}; - -struct sirfsoc_rx_buffer { - struct circ_buf xmit; - dma_cookie_t cookie; - struct dma_async_tx_descriptor *desc; - dma_addr_t dma_addr; -}; - -struct sirfsoc_uart_port { - bool hw_flow_ctrl; - bool ms_enabled; - - struct uart_port port; - struct clk *clk; - /* for sirfatlas7, there are set/clr for uart_int_en */ - bool is_atlas7; - struct sirfsoc_uart_register *uart_reg; - struct dma_chan *rx_dma_chan; - struct dma_chan *tx_dma_chan; - dma_addr_t tx_dma_addr; - struct dma_async_tx_descriptor *tx_dma_desc; - unsigned long transfer_size; - enum sirfsoc_tx_state tx_dma_state; - unsigned int cts_gpio; - unsigned int rts_gpio; - - struct sirfsoc_rx_buffer rx_dma_items; - struct hrtimer hrt; - bool is_hrt_enabled; - unsigned long rx_period_time; - unsigned long rx_last_pos; - unsigned long pio_fetch_cnt; -}; - -/* register access control */ -#define portaddr(port, reg) ((port)->membase + (reg)) -#define rd_regl(port, reg) (__raw_readl(portaddr(port, reg))) -#define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg)) - -/* uart port mask */ -#define sirfuart_fifolevel_mask(port) ((port->fifosize - 1) & 0xfff) -#define sirfuart_fifofull_mask(port) (port->fifosize & 0xfff) -#define sirfuart_fifoempty_mask(port) ((port->fifosize & 0xfff) << 1)
|
Serial
|
4776a4a0a29c64b954a445ff65848bd376a50fcc
|
arnd bergmann
|
documentation
|
devicetree
|
bindings, serial
|
cpufreq: sfi-cpufreq: remove driver for deprecated firmware
|
sfi-based platforms are gone. so does this driver.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove driver for deprecated firmware
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['sfi-cpufreq']
|
['x86', 'c', 'makefile']
| 3
| 0
| 138
|
--- diff --git a/drivers/cpufreq/kconfig.x86 b/drivers/cpufreq/kconfig.x86 --- a/drivers/cpufreq/kconfig.x86 +++ b/drivers/cpufreq/kconfig.x86 -config x86_sfi_cpufreq - tristate "sfi performance-states driver" - depends on x86_intel_mid && sfi - help - this adds a cpufreq driver for some silvermont based intel atom - architectures like z34xx and z35xx which enumerate processor - performance states through sfi. - - if in doubt, say n. - diff --git a/drivers/cpufreq/makefile b/drivers/cpufreq/makefile --- a/drivers/cpufreq/makefile +++ b/drivers/cpufreq/makefile -obj-$(config_x86_sfi_cpufreq) += sfi-cpufreq.o diff --git a/drivers/cpufreq/sfi-cpufreq.c b/drivers/cpufreq/sfi-cpufreq.c --- a/drivers/cpufreq/sfi-cpufreq.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * sfi performance states driver - * - * author: vishwesh m rudramuni <vishwesh.m.rudramuni@intel.com> - * author: srinidhi kasagar <srinidhi.kasagar@intel.com> - */ - -#include <linux/cpufreq.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/sfi.h> -#include <linux/slab.h> -#include <linux/smp.h> - -#include <asm/msr.h> - -static struct cpufreq_frequency_table *freq_table; -static struct sfi_freq_table_entry *sfi_cpufreq_array; -static int num_freq_table_entries; - -static int sfi_parse_freq(struct sfi_table_header *table) -{ - struct sfi_table_simple *sb; - struct sfi_freq_table_entry *pentry; - int totallen; - - sb = (struct sfi_table_simple *)table; - num_freq_table_entries = sfi_get_num_entries(sb, - struct sfi_freq_table_entry); - if (num_freq_table_entries <= 1) { - pr_err("no p-states discovered "); - return -enodev; - } - - pentry = (struct sfi_freq_table_entry *)sb->pentry; - totallen = num_freq_table_entries * sizeof(*pentry); - - sfi_cpufreq_array = kmemdup(pentry, totallen, gfp_kernel); - if (!sfi_cpufreq_array) - return -enomem; - - return 0; -} - -static int sfi_cpufreq_target(struct cpufreq_policy *policy, unsigned int index) -{ - unsigned int next_perf_state = 0; /* index into perf table */ - u32 lo, hi; - - next_perf_state = policy->freq_table[index].driver_data; - - rdmsr_on_cpu(policy->cpu, msr_ia32_perf_ctl, &lo, &hi); - lo = (lo & ~intel_perf_ctl_mask) | - ((u32) sfi_cpufreq_array[next_perf_state].ctrl_val & - intel_perf_ctl_mask); - wrmsr_on_cpu(policy->cpu, msr_ia32_perf_ctl, lo, hi); - - return 0; -} - -static int sfi_cpufreq_cpu_init(struct cpufreq_policy *policy) -{ - policy->shared_type = cpufreq_shared_type_hw; - policy->cpuinfo.transition_latency = 100000; /* 100us */ - policy->freq_table = freq_table; - - return 0; -} - -static struct cpufreq_driver sfi_cpufreq_driver = { - .flags = cpufreq_const_loops, - .verify = cpufreq_generic_frequency_table_verify, - .target_index = sfi_cpufreq_target, - .init = sfi_cpufreq_cpu_init, - .name = "sfi-cpufreq", - .attr = cpufreq_generic_attr, -}; - -static int __init sfi_cpufreq_init(void) -{ - int ret, i; - - /* parse the freq table from sfi */ - ret = sfi_table_parse(sfi_sig_freq, null, null, sfi_parse_freq); - if (ret) - return ret; - - freq_table = kcalloc(num_freq_table_entries + 1, sizeof(*freq_table), - gfp_kernel); - if (!freq_table) { - ret = -enomem; - goto err_free_array; - } - - for (i = 0; i < num_freq_table_entries; i++) { - freq_table[i].driver_data = i; - freq_table[i].frequency = sfi_cpufreq_array[i].freq_mhz * 1000; - } - freq_table[i].frequency = cpufreq_table_end; - - ret = cpufreq_register_driver(&sfi_cpufreq_driver); - if (ret) - goto err_free_tbl; - - return ret; - -err_free_tbl: - kfree(freq_table); -err_free_array: - kfree(sfi_cpufreq_array); - return ret; -} -late_initcall(sfi_cpufreq_init); - -static void __exit sfi_cpufreq_exit(void) -{ - cpufreq_unregister_driver(&sfi_cpufreq_driver); - kfree(freq_table); - kfree(sfi_cpufreq_array); -} -module_exit(sfi_cpufreq_exit); - -module_author("vishwesh m rudramuni <vishwesh.m.rudramuni@intel.com>"); -module_description("sfi performance-states driver"); -module_license("gpl");
|
CPU Frequency scaling
|
73f70d6c200ba85f61818ed3efe7f800c78d2953
|
andy shevchenko linus walleij linus walleij linaro org viresh kumar viresh kumar linaro org
|
drivers
|
cpufreq
| |
cpufreq: qcom-hw: enable boost support
|
at least on sdm850, the 2956800 khz is detected as a boost frequency in function qcom_cpufreq_hw_read_lut(). let's enable boost support by calling cpufreq_enable_boost_support(), so that we can get the boost frequency by switching it on via 'boost' sysfs entry like below.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable boost support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['qcom-hw']
|
['c']
| 1
| 6
| 0
|
--- diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c + if (policy_has_boost_freq(policy)) { + ret = cpufreq_enable_boost_support(); + if (ret) + dev_warn(cpu_dev, "failed to enable boost: %d ", ret); + } +
|
CPU Frequency scaling
|
266991721c15f9feb5c4b839cb1bdde4a2b20030
|
shawn guo
|
drivers
|
cpufreq
| |
cpufreq: remove tango driver
|
the tango platform is getting removed, so the driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove tango driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['makefile', 'c', 'arm']
| 4
| 0
| 46
|
--- diff --git a/drivers/cpufreq/kconfig.arm b/drivers/cpufreq/kconfig.arm --- a/drivers/cpufreq/kconfig.arm +++ b/drivers/cpufreq/kconfig.arm -config arm_tango_cpufreq - bool - depends on cpufreq_dt && arch_tango - default y - diff --git a/drivers/cpufreq/makefile b/drivers/cpufreq/makefile --- a/drivers/cpufreq/makefile +++ b/drivers/cpufreq/makefile -obj-$(config_arm_tango_cpufreq) += tango-cpufreq.o diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c - { .compatible = "sigma,tango4", }, - diff --git a/drivers/cpufreq/tango-cpufreq.c b/drivers/cpufreq/tango-cpufreq.c --- a/drivers/cpufreq/tango-cpufreq.c +++ /dev/null -#include <linux/of.h> -#include <linux/cpu.h> -#include <linux/clk.h> -#include <linux/pm_opp.h> -#include <linux/platform_device.h> - -static const struct of_device_id machines[] __initconst = { - { .compatible = "sigma,tango4" }, - { /* sentinel */ } -}; - -static int __init tango_cpufreq_init(void) -{ - struct device *cpu_dev = get_cpu_device(0); - unsigned long max_freq; - struct clk *cpu_clk; - void *res; - - if (!of_match_node(machines, of_root)) - return -enodev; - - cpu_clk = clk_get(cpu_dev, null); - if (is_err(cpu_clk)) - return -enodev; - - max_freq = clk_get_rate(cpu_clk); - - dev_pm_opp_add(cpu_dev, max_freq / 1, 0); - dev_pm_opp_add(cpu_dev, max_freq / 2, 0); - dev_pm_opp_add(cpu_dev, max_freq / 3, 0); - dev_pm_opp_add(cpu_dev, max_freq / 5, 0); - dev_pm_opp_add(cpu_dev, max_freq / 9, 0); - - res = platform_device_register_data(null, "cpufreq-dt", -1, null, 0); - - return ptr_err_or_zero(res); -} -device_initcall(tango_cpufreq_init);
|
CPU Frequency scaling
|
7114ebffd330bfc5a95b9832a70b6bd857d26fd8
|
arnd bergmann
|
drivers
|
cpufreq
| |
power: reset: add poweroff driver for atc260x pmics
|
this driver provides poweroff and reboot support for a system through the atc2603c and atc2609a chip variants of the actions semi atc260x family of pmics.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add poweroff driver for atc260x pmics
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['power ', 'reset']
|
['kconfig', 'c', 'makefile']
| 3
| 270
| 1
|
--- diff --git a/drivers/power/reset/kconfig b/drivers/power/reset/kconfig --- a/drivers/power/reset/kconfig +++ b/drivers/power/reset/kconfig +config power_reset_atc260x + tristate "actions semi atc260x pmic power-off driver" + depends on mfd_atc260x + help + this driver provides power-off and restart support for a system + through actions semi atc260x series pmics. + - diff --git a/drivers/power/reset/makefile b/drivers/power/reset/makefile --- a/drivers/power/reset/makefile +++ b/drivers/power/reset/makefile +obj-$(config_power_reset_atc260x) += atc260x-poweroff.o diff --git a/drivers/power/reset/atc260x-poweroff.c b/drivers/power/reset/atc260x-poweroff.c --- /dev/null +++ b/drivers/power/reset/atc260x-poweroff.c +// spdx-license-identifier: gpl-2.0+ +/* + * poweroff & reset driver for actions semi atc260x pmics + * + * copyright (c) 2020 cristian ciocaltea <cristian.ciocaltea@gmail.com> + */ + +#include <linux/delay.h> +#include <linux/mfd/atc260x/core.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/power_supply.h> +#include <linux/reboot.h> +#include <linux/regmap.h> + +struct atc260x_pwrc { + struct device *dev; + struct regmap *regmap; + struct notifier_block restart_nb; + int (*do_poweroff)(const struct atc260x_pwrc *pwrc, bool restart); +}; + +/* global variable needed only for pm_power_off */ +static struct atc260x_pwrc *atc260x_pwrc_data; + +static int atc2603c_do_poweroff(const struct atc260x_pwrc *pwrc, bool restart) +{ + int ret, deep_sleep = 0; + uint reg_mask, reg_val; + + /* s4-deep sleep mode is not available for wall/usb power */ + if (!restart && !power_supply_is_system_supplied()) { + deep_sleep = 1; + dev_info(pwrc->dev, "enabling s4-deep sleep mode"); + } + + /* update wakeup sources */ + reg_val = atc2603c_pmu_sys_ctl0_onoff_long_wk_en | + (restart ? atc2603c_pmu_sys_ctl0_reset_wk_en + : atc2603c_pmu_sys_ctl0_onoff_short_wk_en); + + ret = regmap_update_bits(pwrc->regmap, atc2603c_pmu_sys_ctl0, + atc2603c_pmu_sys_ctl0_wk_all, reg_val); + if (ret) + dev_warn(pwrc->dev, "failed to write sys_ctl0: %d ", ret); + + /* update power mode */ + reg_mask = atc2603c_pmu_sys_ctl3_en_s2 | atc2603c_pmu_sys_ctl3_en_s3; + + ret = regmap_update_bits(pwrc->regmap, atc2603c_pmu_sys_ctl3, reg_mask, + deep_sleep ? 0 : atc2603c_pmu_sys_ctl3_en_s3); + if (ret) { + dev_err(pwrc->dev, "failed to write sys_ctl3: %d ", ret); + return ret; + } + + /* trigger poweroff / restart sequence */ + reg_mask = restart ? atc2603c_pmu_sys_ctl0_restart_en + : atc2603c_pmu_sys_ctl1_en_s1; + reg_val = restart ? atc2603c_pmu_sys_ctl0_restart_en : 0; + + ret = regmap_update_bits(pwrc->regmap, + restart ? atc2603c_pmu_sys_ctl0 : atc2603c_pmu_sys_ctl1, + reg_mask, reg_val); + if (ret) { + dev_err(pwrc->dev, "failed to write sys_ctl%d: %d ", + restart ? 0 : 1, ret); + return ret; + } + + /* wait for trigger completion */ + mdelay(200); + + return 0; +} + +static int atc2609a_do_poweroff(const struct atc260x_pwrc *pwrc, bool restart) +{ + int ret, deep_sleep = 0; + uint reg_mask, reg_val; + + /* s4-deep sleep mode is not available for wall/usb power */ + if (!restart && !power_supply_is_system_supplied()) { + deep_sleep = 1; + dev_info(pwrc->dev, "enabling s4-deep sleep mode"); + } + + /* update wakeup sources */ + reg_val = atc2609a_pmu_sys_ctl0_onoff_long_wk_en | + (restart ? atc2609a_pmu_sys_ctl0_reset_wk_en + : atc2609a_pmu_sys_ctl0_onoff_short_wk_en); + + ret = regmap_update_bits(pwrc->regmap, atc2609a_pmu_sys_ctl0, + atc2609a_pmu_sys_ctl0_wk_all, reg_val); + if (ret) + dev_warn(pwrc->dev, "failed to write sys_ctl0: %d ", ret); + + /* update power mode */ + reg_mask = atc2609a_pmu_sys_ctl3_en_s2 | atc2609a_pmu_sys_ctl3_en_s3; + + ret = regmap_update_bits(pwrc->regmap, atc2609a_pmu_sys_ctl3, reg_mask, + deep_sleep ? 0 : atc2609a_pmu_sys_ctl3_en_s3); + if (ret) { + dev_err(pwrc->dev, "failed to write sys_ctl3: %d ", ret); + return ret; + } + + /* trigger poweroff / restart sequence */ + reg_mask = restart ? atc2609a_pmu_sys_ctl0_restart_en + : atc2609a_pmu_sys_ctl1_en_s1; + reg_val = restart ? atc2609a_pmu_sys_ctl0_restart_en : 0; + + ret = regmap_update_bits(pwrc->regmap, + restart ? atc2609a_pmu_sys_ctl0 : atc2609a_pmu_sys_ctl1, + reg_mask, reg_val); + if (ret) { + dev_err(pwrc->dev, "failed to write sys_ctl%d: %d ", + restart ? 0 : 1, ret); + return ret; + } + + /* wait for trigger completion */ + mdelay(200); + + return 0; +} + +static int atc2603c_init(const struct atc260x_pwrc *pwrc) +{ + int ret; + + /* + * delay transition from s2/s3 to s1 in order to avoid + * ddr init failure in bootloader. + */ + ret = regmap_update_bits(pwrc->regmap, atc2603c_pmu_sys_ctl3, + atc2603c_pmu_sys_ctl3_s2s3tos1_timer_en, + atc2603c_pmu_sys_ctl3_s2s3tos1_timer_en); + if (ret) + dev_warn(pwrc->dev, "failed to write sys_ctl3: %d ", ret); + + /* set wakeup sources */ + ret = regmap_update_bits(pwrc->regmap, atc2603c_pmu_sys_ctl0, + atc2603c_pmu_sys_ctl0_wk_all, + atc2603c_pmu_sys_ctl0_hdsw_wk_en | + atc2603c_pmu_sys_ctl0_onoff_long_wk_en); + if (ret) + dev_warn(pwrc->dev, "failed to write sys_ctl0: %d ", ret); + + return ret; +} + +static int atc2609a_init(const struct atc260x_pwrc *pwrc) +{ + int ret; + + /* set wakeup sources */ + ret = regmap_update_bits(pwrc->regmap, atc2609a_pmu_sys_ctl0, + atc2609a_pmu_sys_ctl0_wk_all, + atc2609a_pmu_sys_ctl0_hdsw_wk_en | + atc2609a_pmu_sys_ctl0_onoff_long_wk_en); + if (ret) + dev_warn(pwrc->dev, "failed to write sys_ctl0: %d ", ret); + + return ret; +} + +static void atc260x_pwrc_pm_handler(void) +{ + atc260x_pwrc_data->do_poweroff(atc260x_pwrc_data, false); + + warn_once(1, "unable to power off system "); +} + +static int atc260x_pwrc_restart_handler(struct notifier_block *nb, + unsigned long mode, void *cmd) +{ + struct atc260x_pwrc *pwrc = container_of(nb, struct atc260x_pwrc, + restart_nb); + pwrc->do_poweroff(pwrc, true); + + return notify_done; +} + +static int atc260x_pwrc_probe(struct platform_device *pdev) +{ + struct atc260x *atc260x = dev_get_drvdata(pdev->dev.parent); + struct atc260x_pwrc *priv; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), gfp_kernel); + if (!priv) + return -enomem; + + priv->dev = &pdev->dev; + priv->regmap = atc260x->regmap; + priv->restart_nb.notifier_call = atc260x_pwrc_restart_handler; + priv->restart_nb.priority = 192; + + switch (atc260x->ic_type) { + case atc2603c: + priv->do_poweroff = atc2603c_do_poweroff; + ret = atc2603c_init(priv); + break; + case atc2609a: + priv->do_poweroff = atc2609a_do_poweroff; + ret = atc2609a_init(priv); + break; + default: + dev_err(priv->dev, + "poweroff not supported for atc260x pmic type: %u ", + atc260x->ic_type); + return -einval; + } + + if (ret) + return ret; + + platform_set_drvdata(pdev, priv); + + if (!pm_power_off) { + atc260x_pwrc_data = priv; + pm_power_off = atc260x_pwrc_pm_handler; + } else { + dev_warn(priv->dev, "poweroff callback already assigned "); + } + + ret = register_restart_handler(&priv->restart_nb); + if (ret) + dev_err(priv->dev, "failed to register restart handler: %d ", + ret); + + return ret; +} + +static int atc260x_pwrc_remove(struct platform_device *pdev) +{ + struct atc260x_pwrc *priv = platform_get_drvdata(pdev); + + if (atc260x_pwrc_data == priv) { + pm_power_off = null; + atc260x_pwrc_data = null; + } + + unregister_restart_handler(&priv->restart_nb); + + return 0; +} + +static struct platform_driver atc260x_pwrc_driver = { + .probe = atc260x_pwrc_probe, + .remove = atc260x_pwrc_remove, + .driver = { + .name = "atc260x-pwrc", + }, +}; + +module_platform_driver(atc260x_pwrc_driver); + +module_description("poweroff & reset driver for atc260x pmics"); +module_author("cristian ciocaltea <cristian.ciocaltea@gmail.com>"); +module_license("gpl");
|
Voltage, current regulators, power capping, power supply
|
3235d1305066a58ef0198d95d8a662c574f3df85
|
cristian ciocaltea
|
drivers
|
power
|
reset
|
power: reset: at91-sama5d2_shdwc: add support for sama7g5
|
add support for sama7g5 by adding proper struct reg_config structure and since sama7g5 is not currently on lpddr setups the commit also avoid the mapping of ddr controller.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for sama7g5
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['power ', 'reset', 'at91-sama5d2_shdwc']
|
['c']
| 1
| 54
| 18
|
--- diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c --- a/drivers/power/reset/at91-sama5d2_shdwc.c +++ b/drivers/power/reset/at91-sama5d2_shdwc.c +struct ddrc_reg_config { + u32 type_offset; + u32 type_mask; +}; + + struct ddrc_reg_config ddrc; + .ddrc = { + .type_offset = at91_ddrsdrc_mdr, + .type_mask = at91_ddrsdrc_md + }, + .ddrc = { + .type_offset = at91_ddrsdrc_mdr, + .type_mask = at91_ddrsdrc_md + }, +}; + +static const struct reg_config sama7g5_reg_config = { + .shdwc = { + .wkup_pin_input = 0, + .mr_rtcwk_shift = 17, + .mr_rttwk_shift = 16, + .sr_rtcwk_shift = 5, + .sr_rttwk_shift = 4, + }, + .pmc = { + .mckr = 0x28, + }, + }, + { + .compatible = "microchip,sama7g5-shdwc", + .data = &sama7g5_reg_config, + { .compatible = "microchip,sama7g5-pmc" }, - np = of_find_compatible_node(null, null, "atmel,sama5d3-ddramc"); - if (!np) { - ret = -enodev; - goto unmap; - } + if (at91_shdwc->rcfg->ddrc.type_mask) { + np = of_find_compatible_node(null, null, + "atmel,sama5d3-ddramc"); + if (!np) { + ret = -enodev; + goto unmap; + } - at91_shdwc->mpddrc_base = of_iomap(np, 0); - of_node_put(np); + at91_shdwc->mpddrc_base = of_iomap(np, 0); + of_node_put(np); - if (!at91_shdwc->mpddrc_base) { - ret = -enomem; - goto unmap; + if (!at91_shdwc->mpddrc_base) { + ret = -enomem; + goto unmap; + } + + ddr_type = readl(at91_shdwc->mpddrc_base + + at91_shdwc->rcfg->ddrc.type_offset) & + at91_shdwc->rcfg->ddrc.type_mask; + if (ddr_type != at91_ddrsdrc_md_lpddr2 && + ddr_type != at91_ddrsdrc_md_lpddr3) { + iounmap(at91_shdwc->mpddrc_base); + at91_shdwc->mpddrc_base = null; + } - ddr_type = readl(at91_shdwc->mpddrc_base + at91_ddrsdrc_mdr) & - at91_ddrsdrc_md; - if (ddr_type != at91_ddrsdrc_md_lpddr2 && - ddr_type != at91_ddrsdrc_md_lpddr3) { - iounmap(at91_shdwc->mpddrc_base); - at91_shdwc->mpddrc_base = null; - } -
|
Voltage, current regulators, power capping, power supply
|
b7e15bd0c17a37d6ab61dceb08ef683855e85635
|
claudiu beznea
|
drivers
|
power
|
reset
|
power/reset: remove zte zx driver
|
the zte zx platform is getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove zte zx driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['power ', 'reset']
|
['kconfig', 'c', 'makefile']
| 3
| 0
| 94
|
--- diff --git a/drivers/power/reset/kconfig b/drivers/power/reset/kconfig --- a/drivers/power/reset/kconfig +++ b/drivers/power/reset/kconfig -config power_reset_zx - tristate "zte socs reset driver" - depends on arch_zx || compile_test - depends on has_iomem - help - reboot support for zte socs. - diff --git a/drivers/power/reset/makefile b/drivers/power/reset/makefile --- a/drivers/power/reset/makefile +++ b/drivers/power/reset/makefile -obj-$(config_power_reset_zx) += zx-reboot.o diff --git a/drivers/power/reset/zx-reboot.c b/drivers/power/reset/zx-reboot.c --- a/drivers/power/reset/zx-reboot.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * zte zx296702 soc reset code - * - * copyright (c) 2015 linaro ltd. - * - * author: jun nie <jun.nie@linaro.org> - */ - -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/module.h> -#include <linux/notifier.h> -#include <linux/of_address.h> -#include <linux/platform_device.h> -#include <linux/reboot.h> - -static void __iomem *base; -static void __iomem *pcu_base; - -static int zx_restart_handler(struct notifier_block *this, - unsigned long mode, void *cmd) -{ - writel_relaxed(1, base + 0xb0); - writel_relaxed(1, pcu_base + 0x34); - - mdelay(50); - pr_emerg("unable to restart system "); - - return notify_done; -} - -static struct notifier_block zx_restart_nb = { - .notifier_call = zx_restart_handler, - .priority = 128, -}; - -static int zx_reboot_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - int err; - - base = of_iomap(np, 0); - if (!base) { - warn(1, "failed to map base address"); - return -enodev; - } - - np = of_find_compatible_node(null, null, "zte,zx296702-pcu"); - pcu_base = of_iomap(np, 0); - of_node_put(np); - if (!pcu_base) { - iounmap(base); - warn(1, "failed to map pcu_base address"); - return -enodev; - } - - err = register_restart_handler(&zx_restart_nb); - if (err) { - iounmap(base); - iounmap(pcu_base); - dev_err(&pdev->dev, "register restart handler failed(err=%d) ", - err); - } - - return err; -} - -static const struct of_device_id zx_reboot_of_match[] = { - { .compatible = "zte,sysctrl" }, - {} -}; -module_device_table(of, zx_reboot_of_match); - -static struct platform_driver zx_reboot_driver = { - .probe = zx_reboot_probe, - .driver = { - .name = "zx-reboot", - .of_match_table = zx_reboot_of_match, - }, -}; -module_platform_driver(zx_reboot_driver); - -module_description("zte socs reset driver"); -module_author("jun nie <jun.nie@linaro.org>"); -module_license("gpl v2");
|
Voltage, current regulators, power capping, power supply
|
9483b961ad085fbacee2f69f11411a6134c00f22
|
arnd bergmann
|
drivers
|
power
|
reset
|
power: supply: add battery gauge driver for acer iconia tab a500
|
this patch adds battery gauge driver for acer iconia tab a500 device. the battery gauge function is provided via the embedded controller, which is found on the acer a500.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add battery gauge driver for acer iconia tab a500
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['power ', 'supply']
|
['kconfig', 'c', 'makefile']
| 3
| 304
| 0
|
--- diff --git a/drivers/power/supply/kconfig b/drivers/power/supply/kconfig --- a/drivers/power/supply/kconfig +++ b/drivers/power/supply/kconfig +config battery_acer_a500 + tristate "acer iconia tab a500 battery driver" + depends on mfd_acer_a500_ec + help + say y to include support for acer iconia tab a500 battery fuel gauge. + diff --git a/drivers/power/supply/makefile b/drivers/power/supply/makefile --- a/drivers/power/supply/makefile +++ b/drivers/power/supply/makefile +obj-$(config_battery_acer_a500) += acer_a500_battery.o diff --git a/drivers/power/supply/acer_a500_battery.c b/drivers/power/supply/acer_a500_battery.c --- /dev/null +++ b/drivers/power/supply/acer_a500_battery.c +// spdx-license-identifier: gpl-2.0+ +/* + * battery driver for acer iconia tab a500. + * + * copyright 2020 grate-driver project. + * + * based on downstream driver from acer inc. + * based on nvidia gas gauge driver for sbs compliant batteries. + * + * copyright (c) 2010, nvidia corporation. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/power_supply.h> +#include <linux/regmap.h> +#include <linux/sched.h> +#include <linux/slab.h> +#include <linux/workqueue.h> + +enum { + reg_capacity, + reg_voltage, + reg_current, + reg_design_capacity, + reg_temperature, +}; + +#define ec_data(_reg, _psp) { \ + .psp = power_supply_prop_ ## _psp, \ + .reg = _reg, \ +} + +static const struct battery_register { + enum power_supply_property psp; + unsigned int reg; +} ec_data[] = { + [reg_capacity] = ec_data(0x00, capacity), + [reg_voltage] = ec_data(0x01, voltage_now), + [reg_current] = ec_data(0x03, current_now), + [reg_design_capacity] = ec_data(0x08, charge_full_design), + [reg_temperature] = ec_data(0x0a, temp), +}; + +static const enum power_supply_property a500_battery_properties[] = { + power_supply_prop_capacity, + power_supply_prop_charge_full_design, + power_supply_prop_current_now, + power_supply_prop_present, + power_supply_prop_status, + power_supply_prop_technology, + power_supply_prop_temp, + power_supply_prop_voltage_now, +}; + +struct a500_battery { + struct delayed_work poll_work; + struct power_supply *psy; + struct regmap *regmap; + unsigned int capacity; +}; + +static bool a500_battery_update_capacity(struct a500_battery *bat) +{ + unsigned int capacity; + int err; + + err = regmap_read(bat->regmap, ec_data[reg_capacity].reg, &capacity); + if (err) + return false; + + /* capacity can be >100% even if max value is 100% */ + capacity = min(capacity, 100u); + + if (bat->capacity != capacity) { + bat->capacity = capacity; + return true; + } + + return false; +} + +static int a500_battery_get_status(struct a500_battery *bat) +{ + if (bat->capacity < 100) { + if (power_supply_am_i_supplied(bat->psy)) + return power_supply_status_charging; + else + return power_supply_status_discharging; + } + + return power_supply_status_full; +} + +static void a500_battery_unit_adjustment(struct device *dev, + enum power_supply_property psp, + union power_supply_propval *val) +{ + const unsigned int base_unit_conversion = 1000; + const unsigned int temp_kelvin_to_celsius = 2731; + + switch (psp) { + case power_supply_prop_charge_full_design: + case power_supply_prop_current_now: + case power_supply_prop_voltage_now: + val->intval *= base_unit_conversion; + break; + + case power_supply_prop_temp: + val->intval -= temp_kelvin_to_celsius; + break; + + case power_supply_prop_present: + val->intval = !!val->intval; + break; + + default: + dev_dbg(dev, + "%s: no need for unit conversion %d ", __func__, psp); + } +} + +static int a500_battery_get_ec_data_index(struct device *dev, + enum power_supply_property psp) +{ + unsigned int i; + + /* + * design_capacity register always returns a non-zero value if + * battery is connected and zero if disconnected, hence we'll use + * it for judging the battery presence. + */ + if (psp == power_supply_prop_present) + psp = power_supply_prop_charge_full_design; + + for (i = 0; i < array_size(ec_data); i++) + if (psp == ec_data[i].psp) + return i; + + dev_dbg(dev, "%s: invalid property %u ", __func__, psp); + + return -einval; +} + +static int a500_battery_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct a500_battery *bat = power_supply_get_drvdata(psy); + struct device *dev = psy->dev.parent; + int ret = 0; + + switch (psp) { + case power_supply_prop_status: + val->intval = a500_battery_get_status(bat); + break; + + case power_supply_prop_technology: + val->intval = power_supply_technology_lion; + break; + + case power_supply_prop_capacity: + a500_battery_update_capacity(bat); + val->intval = bat->capacity; + break; + + case power_supply_prop_charge_full_design: + case power_supply_prop_current_now: + case power_supply_prop_voltage_now: + case power_supply_prop_present: + case power_supply_prop_temp: + ret = a500_battery_get_ec_data_index(dev, psp); + if (ret < 0) + break; + + ret = regmap_read(bat->regmap, ec_data[ret].reg, &val->intval); + break; + + default: + dev_err(dev, "%s: invalid property %u ", __func__, psp); + return -einval; + } + + if (!ret) { + /* convert units to match requirements of power supply class */ + a500_battery_unit_adjustment(dev, psp, val); + } + + dev_dbg(dev, "%s: property = %d, value = %x ", + __func__, psp, val->intval); + + /* return nodata for properties if battery not presents */ + if (ret) + return -enodata; + + return 0; +} + +static void a500_battery_poll_work(struct work_struct *work) +{ + struct a500_battery *bat; + bool capacity_changed; + + bat = container_of(work, struct a500_battery, poll_work.work); + capacity_changed = a500_battery_update_capacity(bat); + + if (capacity_changed) + power_supply_changed(bat->psy); + + /* continuously send uevent notification */ + schedule_delayed_work(&bat->poll_work, 30 * hz); +} + +static const struct power_supply_desc a500_battery_desc = { + .name = "ec-battery", + .type = power_supply_type_battery, + .properties = a500_battery_properties, + .get_property = a500_battery_get_property, + .num_properties = array_size(a500_battery_properties), + .external_power_changed = power_supply_changed, +}; + +static int a500_battery_probe(struct platform_device *pdev) +{ + struct power_supply_config psy_cfg = {}; + struct a500_battery *bat; + + bat = devm_kzalloc(&pdev->dev, sizeof(*bat), gfp_kernel); + if (!bat) + return -enomem; + + platform_set_drvdata(pdev, bat); + + psy_cfg.of_node = pdev->dev.parent->of_node; + psy_cfg.drv_data = bat; + + bat->regmap = dev_get_regmap(pdev->dev.parent, "kb930"); + if (!bat->regmap) + return -einval; + + bat->psy = devm_power_supply_register_no_ws(&pdev->dev, + &a500_battery_desc, + &psy_cfg); + if (is_err(bat->psy)) + return dev_err_probe(&pdev->dev, ptr_err(bat->psy), + "failed to register battery "); + + init_delayed_work(&bat->poll_work, a500_battery_poll_work); + schedule_delayed_work(&bat->poll_work, hz); + + return 0; +} + +static int a500_battery_remove(struct platform_device *pdev) +{ + struct a500_battery *bat = dev_get_drvdata(&pdev->dev); + + cancel_delayed_work_sync(&bat->poll_work); + + return 0; +} + +static int __maybe_unused a500_battery_suspend(struct device *dev) +{ + struct a500_battery *bat = dev_get_drvdata(dev); + + cancel_delayed_work_sync(&bat->poll_work); + + return 0; +} + +static int __maybe_unused a500_battery_resume(struct device *dev) +{ + struct a500_battery *bat = dev_get_drvdata(dev); + + schedule_delayed_work(&bat->poll_work, hz); + + return 0; +} + +static simple_dev_pm_ops(a500_battery_pm_ops, + a500_battery_suspend, a500_battery_resume); + +static struct platform_driver a500_battery_driver = { + .driver = { + .name = "acer-a500-iconia-battery", + .pm = &a500_battery_pm_ops, + }, + .probe = a500_battery_probe, + .remove = a500_battery_remove, +}; +module_platform_driver(a500_battery_driver); + +module_description("battery gauge driver for acer iconia tab a500"); +module_author("dmitry osipenko <digetx@gmail.com>"); +module_alias("platform:acer-a500-iconia-battery"); +module_license("gpl");
|
Voltage, current regulators, power capping, power supply
|
c82a2fbe6c02d5caf5a3312f6ea119da450ccee0
|
dmitry osipenko
|
drivers
|
power
|
supply
|
power/supply: add ltc4162-l-charger
|
add support for the ltc4162-l li-ion battery charger. the driver allows reading back telemetry and to set some charging options like the input current limit.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add ltc4162-l-charger
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['power ', 'supply']
|
['kconfig', 'sysfs-class-power-ltc4162l', 'c', 'makefile']
| 4
| 1,022
| 0
|
--- diff --git a/documentation/abi/testing/sysfs-class-power-ltc4162l b/documentation/abi/testing/sysfs-class-power-ltc4162l --- /dev/null +++ b/documentation/abi/testing/sysfs-class-power-ltc4162l +what: /sys/class/power_supply/ltc4162-l/charge_status +date: januari 2021 +kernelversion: 5.11 +description: + detailed charge status information as reported by the chip. + + access: read + + valid values: + ilim_reg_active + thermal_reg_active + vin_uvcl_active + iin_limit_active + constant_current + constant_voltage + charger_off + +what: /sys/class/power_supply/ltc4162-l/ibat +date: januari 2021 +kernelversion: 5.11 +description: + battery input current as measured by the charger. negative value + means that the battery is discharging. + + access: read + + valid values: signed value in microamps + +what: /sys/class/power_supply/ltc4162-l/vbat +date: januari 2021 +kernelversion: 5.11 +description: + battery voltage as measured by the charger. + + access: read + + valid values: in microvolts + +what: /sys/class/power_supply/ltc4162-l/vbat_avg +date: januari 2021 +kernelversion: 5.11 +description: + battery voltage, averaged over time, as measured by the charger. + + access: read + + valid values: in microvolts + +what: /sys/class/power_supply/ltc4162-l/force_telemetry +date: januari 2021 +kernelversion: 5.11 +description: + to save battery current, the measurement system is disabled if + the battery is the only source of power. this affects all + voltage, current and temperature measurements. + write a "1" to this to keep performing telemetry once every few + seconds, even when running on battery (as reported by the online + property, which is "1" when external power is available and "0" + when the system runs on battery). + + access: read, write + + valid values: 0 (disabled) or 1 (enabled) + +what: /sys/class/power_supply/ltc4162-l/arm_ship_mode +date: januari 2021 +kernelversion: 5.11 +description: + the charger will normally drain the battery while inactive, + typically drawing about 54 microamps. write a "1" to this + property to arm a special "ship" mode that extends shelf life + by reducing the leakage to about 2.8 microamps. the chip will + remain in this mode (and no longer respond to i2c commands) + until some external power-supply is attached raising the input + voltage above 1v. it will then automatically revert to "0". + writing a "0" to the property cancels the "ship" mode request. + the ship mode, when armed, activates once the input voltage + drops below 1v. + + access: read, write + + valid values: 0 (disable) or 1 (enable) diff --git a/drivers/power/supply/kconfig b/drivers/power/supply/kconfig --- a/drivers/power/supply/kconfig +++ b/drivers/power/supply/kconfig +config charger_ltc4162l + tristate "ltc4162-l charger" + depends on i2c + select regmap_i2c + help + say y to include support for the analog devices (linear technology) + ltc4162-l battery charger connected to i2c. + diff --git a/drivers/power/supply/makefile b/drivers/power/supply/makefile --- a/drivers/power/supply/makefile +++ b/drivers/power/supply/makefile +obj-$(config_charger_ltc4162l) += ltc4162-l-charger.o diff --git a/drivers/power/supply/ltc4162-l-charger.c b/drivers/power/supply/ltc4162-l-charger.c --- /dev/null +++ b/drivers/power/supply/ltc4162-l-charger.c +// spdx-license-identifier: gpl-2.0-or-later +/* + * driver for analog devices (linear technology) ltc4162-l charger ic. + * copyright (c) 2020, topic embedded products + */ + +#include <linux/module.h> +#include <linux/delay.h> +#include <linux/of_device.h> +#include <linux/pm_runtime.h> +#include <linux/power_supply.h> +#include <linux/i2c.h> +#include <linux/regmap.h> + +/* registers (names based on what datasheet uses) */ +#define ltc4162l_en_limit_alerts_reg 0x0d +#define ltc4162l_en_charger_state_alerts_reg 0x0e +#define ltc4162l_en_charge_status_alerts_reg 0x0f +#define ltc4162l_config_bits_reg 0x14 +#define ltc4162l_iin_limit_target 0x15 +#define ltc4162l_arm_ship_mode 0x19 +#define ltc4162l_charge_current_setting 0x1a +#define ltc4162l_vcharge_setting 0x1b +#define ltc4162l_c_over_x_threshold 0x1c +#define ltc4162l_max_cv_time 0x1d +#define ltc4162l_max_charge_time 0x1e +#define ltc4162l_charger_config_bits 0x29 +#define ltc4162l_charger_state 0x34 +#define ltc4162l_charge_status 0x35 +#define ltc4162l_limit_alerts_reg 0x36 +#define ltc4162l_charger_state_alerts_reg 0x37 +#define ltc4162l_charge_status_alerts_reg 0x38 +#define ltc4162l_system_status_reg 0x39 +#define ltc4162l_vbat 0x3a +#define ltc4162l_vin 0x3b +#define ltc4162l_vout 0x3c +#define ltc4162l_ibat 0x3d +#define ltc4162l_iin 0x3e +#define ltc4162l_die_temperature 0x3f +#define ltc4162l_thermistor_voltage 0x40 +#define ltc4162l_bsr 0x41 +#define ltc4162l_jeita_region 0x42 +#define ltc4162l_chem_cells_reg 0x43 +#define ltc4162l_icharge_dac 0x44 +#define ltc4162l_vcharge_dac 0x45 +#define ltc4162l_iin_limit_dac 0x46 +#define ltc4162l_vbat_filt 0x47 +#define ltc4162l_input_undervoltage_dac 0x4b + +/* enumeration as in datasheet. individual bits are mutually exclusive. */ +enum ltc4162l_state { + battery_detection = 2048, + charger_suspended = 256, + precharge = 128, /* trickle on low bat voltage */ + cc_cv_charge = 64, /* normal charge */ + ntc_pause = 32, + timer_term = 16, + c_over_x_term = 8, /* battery is full */ + max_charge_time_fault = 4, + bat_missing_fault = 2, + bat_short_fault = 1 +}; + +/* individual bits are mutually exclusive. only active in charging states.*/ +enum ltc4162l_charge_status { + ilim_reg_active = 32, + thermal_reg_active = 16, + vin_uvcl_active = 8, + iin_limit_active = 4, + constant_current = 2, + constant_voltage = 1, + charger_off = 0 +}; + +/* magic number to write to arm_ship_mode register */ +#define ltc4162l_arm_ship_mode_magic 21325 + +struct ltc4162l_info { + struct i2c_client *client; + struct regmap *regmap; + struct power_supply *charger; + u32 rsnsb; /* series resistor that sets charge current, microohm */ + u32 rsnsi; /* series resistor to measure input current, microohm */ + u8 cell_count; /* number of connected cells, 0 while unknown */ +}; + +static u8 ltc4162l_get_cell_count(struct ltc4162l_info *info) +{ + int ret; + unsigned int val; + + /* once read successfully */ + if (info->cell_count) + return info->cell_count; + + ret = regmap_read(info->regmap, ltc4162l_chem_cells_reg, &val); + if (ret) + return 0; + + /* lower 4 bits is the cell count, or 0 if the chip doesn't know yet */ + val &= 0x0f; + if (!val) + return 0; + + /* once determined, keep the value */ + info->cell_count = val; + + return val; +}; + +/* convert enum value to power_supply_status value */ +static int ltc4162l_state_decode(enum ltc4162l_state value) +{ + switch (value) { + case precharge: + case cc_cv_charge: + return power_supply_status_charging; + case c_over_x_term: + return power_supply_status_full; + case bat_missing_fault: + case bat_short_fault: + return power_supply_status_unknown; + default: + return power_supply_status_not_charging; + } +}; + +static int ltc4162l_get_status(struct ltc4162l_info *info, + union power_supply_propval *val) +{ + unsigned int regval; + int ret; + + ret = regmap_read(info->regmap, ltc4162l_charger_state, ®val); + if (ret) { + dev_err(&info->client->dev, "failed to read charger_state "); + return ret; + } + + val->intval = ltc4162l_state_decode(regval); + + return 0; +} + +static int ltc4162l_charge_status_decode(enum ltc4162l_charge_status value) +{ + if (!value) + return power_supply_charge_type_none; + + /* constant voltage/current and input_current limit are "fast" modes */ + if (value <= iin_limit_active) + return power_supply_charge_type_fast; + + /* anything that's not fast we'll return as trickle */ + return power_supply_charge_type_trickle; +} + +static int ltc4162l_get_charge_type(struct ltc4162l_info *info, + union power_supply_propval *val) +{ + unsigned int regval; + int ret; + + ret = regmap_read(info->regmap, ltc4162l_charge_status, ®val); + if (ret) + return ret; + + val->intval = ltc4162l_charge_status_decode(regval); + + return 0; +} + +static int ltc4162l_state_to_health(enum ltc4162l_state value) +{ + switch (value) { + case ntc_pause: + return power_supply_health_overheat; + case timer_term: + return power_supply_health_safety_timer_expire; + case max_charge_time_fault: + return power_supply_health_watchdog_timer_expire; + case bat_missing_fault: + return power_supply_health_unspec_failure; + case bat_short_fault: + return power_supply_health_dead; + default: + return power_supply_health_good; + } +} + +static int ltc4162l_get_health(struct ltc4162l_info *info, + union power_supply_propval *val) +{ + unsigned int regval; + int ret; + + ret = regmap_read(info->regmap, ltc4162l_charger_state, ®val); + if (ret) + return ret; + + val->intval = ltc4162l_state_to_health(regval); + + return 0; +} + +static int ltc4162l_get_online(struct ltc4162l_info *info, + union power_supply_propval *val) +{ + unsigned int regval; + int ret; + + ret = regmap_read(info->regmap, ltc4162l_system_status_reg, ®val); + if (ret) + return ret; + + /* bit(2) indicates if input voltage is sufficient to charge */ + val->intval = !!(regval & bit(2)); + + return 0; +} + +static int ltc4162l_get_vbat(struct ltc4162l_info *info, + unsigned int reg, + union power_supply_propval *val) +{ + unsigned int regval; + int ret; + + ret = regmap_read(info->regmap, reg, ®val); + if (ret) + return ret; + + /* cell_count 192.4v/lsb */ + regval *= 1924; + regval *= ltc4162l_get_cell_count(info); + regval /= 10; + val->intval = regval; + + return 0; +} + +static int ltc4162l_get_ibat(struct ltc4162l_info *info, + union power_supply_propval *val) +{ + unsigned int regval; + int ret; + + ret = regmap_read(info->regmap, ltc4162l_ibat, ®val); + if (ret) + return ret; + + /* signed 16-bit number, 1.466v / rsnsb amperes/lsb. */ + ret = (s16)(regval & 0xffff); + val->intval = 100 * mult_frac(ret, 14660, (int)info->rsnsb); + + return 0; +} + + +static int ltc4162l_get_input_voltage(struct ltc4162l_info *info, + union power_supply_propval *val) +{ + unsigned int regval; + int ret; + + ret = regmap_read(info->regmap, ltc4162l_vin, ®val); + if (ret) + return ret; + + /* 1.649mv/lsb */ + val->intval = regval * 1694; + + return 0; +} + +static int ltc4162l_get_input_current(struct ltc4162l_info *info, + union power_supply_propval *val) +{ + unsigned int regval; + int ret; + + ret = regmap_read(info->regmap, ltc4162l_iin, ®val); + if (ret) + return ret; + + /* signed 16-bit number, 1.466v / rsnsi amperes/lsb. */ + ret = (s16)(regval & 0xffff); + ret *= 14660; + ret /= info->rsnsi; + ret *= 100; + + val->intval = ret; + + return 0; +} + +static int ltc4162l_get_icharge(struct ltc4162l_info *info, + unsigned int reg, + union power_supply_propval *val) +{ + unsigned int regval; + int ret; + + ret = regmap_read(info->regmap, reg, ®val); + if (ret) + return ret; + + regval &= bit(6) - 1; /* only the lower 5 bits */ + + /* the charge current servo level: (icharge_dac + 1) 1mv/rsnsb */ + ++regval; + val->intval = 10000u * mult_frac(regval, 100000u, info->rsnsb); + + return 0; +} + +static int ltc4162l_set_icharge(struct ltc4162l_info *info, + unsigned int reg, + unsigned int value) +{ + value = mult_frac(value, info->rsnsb, 100000u); + value /= 10000u; + + /* round to lowest possible */ + if (value) + --value; + + if (value > 31) + return -einval; + + return regmap_write(info->regmap, reg, value); +} + + +static int ltc4162l_get_vcharge(struct ltc4162l_info *info, + unsigned int reg, + union power_supply_propval *val) +{ + unsigned int regval; + int ret; + u32 voltage; + + ret = regmap_read(info->regmap, reg, ®val); + if (ret) + return ret; + + regval &= bit(6) - 1; /* only the lower 5 bits */ + + /* + * charge voltage setting can be computed from + * cell_count (vcharge_setting 12.5mv + 3.8125v) + * where vcharge_setting ranges from 0 to 31 (4.2v max). + */ + voltage = 3812500 + (regval * 12500); + voltage *= ltc4162l_get_cell_count(info); + val->intval = voltage; + + return 0; +} + +static int ltc4162l_set_vcharge(struct ltc4162l_info *info, + unsigned int reg, + unsigned int value) +{ + u8 cell_count = ltc4162l_get_cell_count(info); + + if (!cell_count) + return -ebusy; /* not available yet, try again later */ + + value /= cell_count; + + if (value < 3812500) + return -einval; + + value -= 3812500; + value /= 12500; + + if (value > 31) + return -einval; + + return regmap_write(info->regmap, reg, value); +} + +static int ltc4162l_get_iin_limit_dac(struct ltc4162l_info *info, + union power_supply_propval *val) +{ + unsigned int regval; + int ret; + + ret = regmap_read(info->regmap, ltc4162l_iin_limit_dac, ®val); + if (ret) + return ret; + + regval &= bit(6) - 1; /* only 6 bits */ + + /* (iin_limit_dac + 1) 500v / rsnsi */ + ++regval; + regval *= 5000000u; + regval /= info->rsnsi; + val->intval = 100u * regval; + + return 0; +} + +static int ltc4162l_set_iin_limit(struct ltc4162l_info *info, + unsigned int value) +{ + unsigned int regval; + + regval = mult_frac(value, info->rsnsi, 50000u); + regval /= 10000u; + if (regval) + --regval; + if (regval > 63) + regval = 63; + + return regmap_write(info->regmap, ltc4162l_iin_limit_target, regval); +} + +static int ltc4162l_get_die_temp(struct ltc4162l_info *info, + union power_supply_propval *val) +{ + unsigned int regval; + int ret; + + ret = regmap_read(info->regmap, ltc4162l_die_temperature, ®val); + if (ret) + return ret; + + /* die_temp 0.0215c/lsb - 264.4c */ + ret = (s16)(regval & 0xffff); + ret *= 215; + ret /= 100; /* centidegrees scale */ + ret -= 26440; + val->intval = ret; + + return 0; +} + +static int ltc4162l_get_term_current(struct ltc4162l_info *info, + union power_supply_propval *val) +{ + unsigned int regval; + int ret; + + ret = regmap_read(info->regmap, ltc4162l_charger_config_bits, ®val); + if (ret) + return ret; + + /* check if c_over_x_threshold is enabled */ + if (!(regval & bit(2))) { + val->intval = 0; + return 0; + } + + ret = regmap_read(info->regmap, ltc4162l_c_over_x_threshold, ®val); + if (ret) + return ret; + + /* 1.466v / rsnsb amperes/lsb */ + regval *= 14660u; + regval /= info->rsnsb; + val->intval = 100 * regval; + + return 0; +} + +static int ltc4162l_set_term_current(struct ltc4162l_info *info, + unsigned int value) +{ + int ret; + unsigned int regval; + + if (!value) { + /* disable en_c_over_x_term when set to zero */ + return regmap_update_bits(info->regmap, + ltc4162l_charger_config_bits, + bit(2), 0); + } + + regval = mult_frac(value, info->rsnsb, 14660u); + regval /= 100u; + + ret = regmap_write(info->regmap, ltc4162l_c_over_x_threshold, regval); + if (ret) + return ret; + + /* set en_c_over_x_term after changing the threshold value */ + return regmap_update_bits(info->regmap, ltc4162l_charger_config_bits, + bit(2), bit(2)); +} + +/* custom properties */ +static const char * const ltc4162l_charge_status_name[] = { + "ilim_reg_active", /* 32 */ + "thermal_reg_active", + "vin_uvcl_active", + "iin_limit_active", + "constant_current", + "constant_voltage", + "charger_off" /* 0 */ +}; + +static ssize_t charge_status_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct power_supply *psy = to_power_supply(dev); + struct ltc4162l_info *info = power_supply_get_drvdata(psy); + const char *result = ltc4162l_charge_status_name[ + array_size(ltc4162l_charge_status_name) - 1]; + unsigned int regval; + unsigned int mask; + unsigned int index; + int ret; + + ret = regmap_read(info->regmap, ltc4162l_charge_status, ®val); + if (ret) + return ret; + + /* only one bit is set according to datasheet, let's be safe here */ + for (mask = 32, index = 0; mask != 0; mask >>= 1, ++index) { + if (regval & mask) { + result = ltc4162l_charge_status_name[index]; + break; + } + } + + return sprintf(buf, "%s ", result); +} +static device_attr_ro(charge_status); + +static ssize_t vbat_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct power_supply *psy = to_power_supply(dev); + struct ltc4162l_info *info = power_supply_get_drvdata(psy); + union power_supply_propval val; + int ret; + + ret = ltc4162l_get_vbat(info, ltc4162l_vbat, &val); + if (ret) + return ret; + + return sprintf(buf, "%d ", val.intval); +} +static device_attr_ro(vbat); + +static ssize_t vbat_avg_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct power_supply *psy = to_power_supply(dev); + struct ltc4162l_info *info = power_supply_get_drvdata(psy); + union power_supply_propval val; + int ret; + + ret = ltc4162l_get_vbat(info, ltc4162l_vbat_filt, &val); + if (ret) + return ret; + + return sprintf(buf, "%d ", val.intval); +} +static device_attr_ro(vbat_avg); + +static ssize_t ibat_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct power_supply *psy = to_power_supply(dev); + struct ltc4162l_info *info = power_supply_get_drvdata(psy); + union power_supply_propval val; + int ret; + + ret = ltc4162l_get_ibat(info, &val); + if (ret) + return ret; + + return sprintf(buf, "%d ", val.intval); +} +static device_attr_ro(ibat); + +static ssize_t force_telemetry_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct power_supply *psy = to_power_supply(dev); + struct ltc4162l_info *info = power_supply_get_drvdata(psy); + unsigned int regval; + int ret; + + ret = regmap_read(info->regmap, ltc4162l_config_bits_reg, ®val); + if (ret) + return ret; + + return sprintf(buf, "%u ", regval & bit(2) ? 1 : 0); +} + +static ssize_t force_telemetry_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct power_supply *psy = to_power_supply(dev); + struct ltc4162l_info *info = power_supply_get_drvdata(psy); + int ret; + unsigned int value; + + ret = kstrtouint(buf, 0, &value); + if (ret < 0) + return ret; + + ret = regmap_update_bits(info->regmap, ltc4162l_config_bits_reg, + bit(2), value ? bit(2) : 0); + if (ret < 0) + return ret; + + return count; +} + +static device_attr_rw(force_telemetry); + +static ssize_t arm_ship_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct power_supply *psy = to_power_supply(dev); + struct ltc4162l_info *info = power_supply_get_drvdata(psy); + unsigned int regval; + int ret; + + ret = regmap_read(info->regmap, ltc4162l_arm_ship_mode, ®val); + if (ret) + return ret; + + return sprintf(buf, "%u ", + regval == ltc4162l_arm_ship_mode_magic ? 1 : 0); +} + +static ssize_t arm_ship_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct power_supply *psy = to_power_supply(dev); + struct ltc4162l_info *info = power_supply_get_drvdata(psy); + int ret; + unsigned int value; + + ret = kstrtouint(buf, 0, &value); + if (ret < 0) + return ret; + + ret = regmap_write(info->regmap, ltc4162l_arm_ship_mode, + value ? ltc4162l_arm_ship_mode_magic : 0); + if (ret < 0) + return ret; + + return count; +} + +static device_attr_rw(arm_ship_mode); + +static struct attribute *ltc4162l_sysfs_entries[] = { + &dev_attr_charge_status.attr, + &dev_attr_ibat.attr, + &dev_attr_vbat.attr, + &dev_attr_vbat_avg.attr, + &dev_attr_force_telemetry.attr, + &dev_attr_arm_ship_mode.attr, + null, +}; + +static struct attribute_group ltc4162l_attr_group = { + .name = null, /* put in device directory */ + .attrs = ltc4162l_sysfs_entries, +}; + +static const struct attribute_group *ltc4162l_attr_groups[] = { + <c4162l_attr_group, + null, +}; + +static int ltc4162l_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct ltc4162l_info *info = power_supply_get_drvdata(psy); + + switch (psp) { + case power_supply_prop_status: + return ltc4162l_get_status(info, val); + case power_supply_prop_charge_type: + return ltc4162l_get_charge_type(info, val); + case power_supply_prop_health: + return ltc4162l_get_health(info, val); + case power_supply_prop_online: + return ltc4162l_get_online(info, val); + case power_supply_prop_voltage_now: + return ltc4162l_get_input_voltage(info, val); + case power_supply_prop_current_now: + return ltc4162l_get_input_current(info, val); + case power_supply_prop_constant_charge_current: + return ltc4162l_get_icharge(info, + ltc4162l_icharge_dac, val); + case power_supply_prop_constant_charge_current_max: + return ltc4162l_get_icharge(info, + ltc4162l_charge_current_setting, val); + case power_supply_prop_constant_charge_voltage: + return ltc4162l_get_vcharge(info, + ltc4162l_vcharge_dac, val); + case power_supply_prop_constant_charge_voltage_max: + return ltc4162l_get_vcharge(info, + ltc4162l_vcharge_setting, val); + case power_supply_prop_input_current_limit: + return ltc4162l_get_iin_limit_dac(info, val); + case power_supply_prop_temp: + return ltc4162l_get_die_temp(info, val); + case power_supply_prop_charge_term_current: + return ltc4162l_get_term_current(info, val); + default: + return -einval; + } +} + +static int ltc4162l_set_property(struct power_supply *psy, + enum power_supply_property psp, + const union power_supply_propval *val) +{ + struct ltc4162l_info *info = power_supply_get_drvdata(psy); + + switch (psp) { + case power_supply_prop_constant_charge_current_max: + return ltc4162l_set_icharge(info, + ltc4162l_charge_current_setting, val->intval); + case power_supply_prop_constant_charge_voltage_max: + return ltc4162l_set_vcharge(info, + ltc4162l_vcharge_setting, val->intval); + case power_supply_prop_input_current_limit: + return ltc4162l_set_iin_limit(info, val->intval); + case power_supply_prop_charge_term_current: + return ltc4162l_set_term_current(info, val->intval); + default: + return -einval; + } +} + +static int ltc4162l_property_is_writeable(struct power_supply *psy, + enum power_supply_property psp) +{ + switch (psp) { + case power_supply_prop_constant_charge_current_max: + case power_supply_prop_constant_charge_voltage_max: + case power_supply_prop_input_current_limit: + case power_supply_prop_charge_term_current: + return 1; + default: + return 0; + } +} + +/* charger power supply property routines */ +static enum power_supply_property ltc4162l_properties[] = { + power_supply_prop_status, + power_supply_prop_charge_type, + power_supply_prop_health, + power_supply_prop_online, + power_supply_prop_voltage_now, + power_supply_prop_current_now, + power_supply_prop_constant_charge_current, + power_supply_prop_constant_charge_current_max, + power_supply_prop_constant_charge_voltage, + power_supply_prop_constant_charge_voltage_max, + power_supply_prop_input_current_limit, + power_supply_prop_temp, + power_supply_prop_charge_term_current, +}; + +static const struct power_supply_desc ltc4162l_desc = { + .name = "ltc4162-l", + .type = power_supply_type_mains, + .properties = ltc4162l_properties, + .num_properties = array_size(ltc4162l_properties), + .get_property = ltc4162l_get_property, + .set_property = ltc4162l_set_property, + .property_is_writeable = ltc4162l_property_is_writeable, +}; + +static bool ltc4162l_is_writeable_reg(struct device *dev, unsigned int reg) +{ + /* all registers up to this one are writeable */ + if (reg <= ltc4162l_charger_config_bits) + return true; + + /* the alerts registers can be written to clear alerts */ + if (reg >= ltc4162l_limit_alerts_reg && + reg <= ltc4162l_charge_status_alerts_reg) + return true; + + return false; +} + +static bool ltc4162l_is_volatile_reg(struct device *dev, unsigned int reg) +{ + /* all registers after this one are read-only status registers */ + return reg > ltc4162l_charger_config_bits; +} + +static const struct regmap_config ltc4162l_regmap_config = { + .reg_bits = 8, + .val_bits = 16, + .val_format_endian = regmap_endian_little, + .writeable_reg = ltc4162l_is_writeable_reg, + .volatile_reg = ltc4162l_is_volatile_reg, + .max_register = ltc4162l_input_undervoltage_dac, + .cache_type = regcache_rbtree, +}; + +static void ltc4162l_clear_interrupts(struct ltc4162l_info *info) +{ + /* acknowledge interrupt to chip by clearing all events */ + regmap_write(info->regmap, ltc4162l_limit_alerts_reg, 0); + regmap_write(info->regmap, ltc4162l_charger_state_alerts_reg, 0); + regmap_write(info->regmap, ltc4162l_charge_status_alerts_reg, 0); +} + +static int ltc4162l_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct i2c_adapter *adapter = client->adapter; + struct device *dev = &client->dev; + struct ltc4162l_info *info; + struct power_supply_config ltc4162l_config = {}; + u32 value; + int ret; + + if (!i2c_check_functionality(adapter, i2c_func_smbus_word_data)) { + dev_err(dev, "no support for smbus_word_data "); + return -enodev; + } + info = devm_kzalloc(dev, sizeof(*info), gfp_kernel); + if (!info) + return -enomem; + + info->client = client; + i2c_set_clientdata(client, info); + + info->regmap = devm_regmap_init_i2c(client, <c4162l_regmap_config); + if (is_err(info->regmap)) { + dev_err(dev, "failed to initialize register map "); + return ptr_err(info->regmap); + } + + ret = device_property_read_u32(dev, "lltc,rsnsb-micro-ohms", + &info->rsnsb); + if (ret) { + dev_err(dev, "missing lltc,rsnsb-micro-ohms property "); + return ret; + } + if (!info->rsnsb) + return -einval; + + ret = device_property_read_u32(dev, "lltc,rsnsi-micro-ohms", + &info->rsnsi); + if (ret) { + dev_err(dev, "missing lltc,rsnsi-micro-ohms property "); + return ret; + } + if (!info->rsnsi) + return -einval; + + if (!device_property_read_u32(dev, "lltc,cell-count", &value)) + info->cell_count = value; + + ltc4162l_config.of_node = dev->of_node; + ltc4162l_config.drv_data = info; + ltc4162l_config.attr_grp = ltc4162l_attr_groups; + + info->charger = devm_power_supply_register(dev, <c4162l_desc, + <c4162l_config); + if (is_err(info->charger)) { + dev_err(dev, "failed to register charger "); + return ptr_err(info->charger); + } + + /* disable the threshold alerts, we're not using them */ + regmap_write(info->regmap, ltc4162l_en_limit_alerts_reg, 0); + + /* enable interrupts on all status changes */ + regmap_write(info->regmap, ltc4162l_en_charger_state_alerts_reg, + 0x1fff); + regmap_write(info->regmap, ltc4162l_en_charge_status_alerts_reg, 0x1f); + + ltc4162l_clear_interrupts(info); + + return 0; +} + +static void ltc4162l_alert(struct i2c_client *client, + enum i2c_alert_protocol type, unsigned int flag) +{ + struct ltc4162l_info *info = i2c_get_clientdata(client); + + if (type != i2c_protocol_smbus_alert) + return; + + ltc4162l_clear_interrupts(info); + power_supply_changed(info->charger); +} + +static const struct i2c_device_id ltc4162l_i2c_id_table[] = { + { "ltc4162-l", 0 }, + { }, +}; +module_device_table(i2c, ltc4162l_i2c_id_table); + +static const struct of_device_id ltc4162l_of_match[] = { + { .compatible = "lltc,ltc4162-l", }, + { }, +}; +module_device_table(of, ltc4162l_of_match); + +static struct i2c_driver ltc4162l_driver = { + .probe = ltc4162l_probe, + .alert = ltc4162l_alert, + .id_table = ltc4162l_i2c_id_table, + .driver = { + .name = "ltc4162-l-charger", + .of_match_table = of_match_ptr(ltc4162l_of_match), + }, +}; +module_i2c_driver(ltc4162l_driver); + +module_license("gpl"); +module_author("mike looijmans <mike.looijmans@topic.nl>"); +module_description("ltc4162-l charger driver");
|
Voltage, current regulators, power capping, power supply
|
cd900f181ad6b548a8feded5dd224f789f09b1c6
|
mike looijmans
|
drivers
|
power
|
supply, testing
|
power: supply: bq256xx: introduce the bq256xx charger driver
|
the bq256xx family of devices are highly integrated buck chargers for single cell batteries.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
introduce the bq256xx charger driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['power ', 'supply', 'bq256xx']
|
['kconfig', 'c', 'makefile']
| 3
| 1,757
| 0
|
--- diff --git a/drivers/power/supply/kconfig b/drivers/power/supply/kconfig --- a/drivers/power/supply/kconfig +++ b/drivers/power/supply/kconfig +config charger_bq256xx + tristate "ti bq256xx battery charger driver" + depends on i2c + depends on gpiolib || compile_test + select regmap_i2c + help + say y to enable support for the ti bq256xx battery chargers. the + bq256xx family of devices are highly-integrated, switch-mode battery + charge management and system power path management devices for single + cell li-ion and li-polymer batteries. + diff --git a/drivers/power/supply/makefile b/drivers/power/supply/makefile --- a/drivers/power/supply/makefile +++ b/drivers/power/supply/makefile +obj-$(config_charger_bq256xx) += bq256xx_charger.o diff --git a/drivers/power/supply/bq256xx_charger.c b/drivers/power/supply/bq256xx_charger.c --- /dev/null +++ b/drivers/power/supply/bq256xx_charger.c +// spdx-license-identifier: gpl-2.0 +// bq256xx battery charger driver +// copyright (c) 2020 texas instruments incorporated - http://www.ti.com/ + +#include <linux/err.h> +#include <linux/i2c.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/gpio/consumer.h> +#include <linux/power_supply.h> +#include <linux/regmap.h> +#include <linux/types.h> +#include <linux/usb/phy.h> +#include <linux/device.h> +#include <linux/moduleparam.h> +#include <linux/slab.h> +#include <linux/acpi.h> + +#define bq256xx_manufacturer "texas instruments" + +#define bq256xx_input_current_limit 0x00 +#define bq256xx_charger_control_0 0x01 +#define bq256xx_charge_current_limit 0x02 +#define bq256xx_prechg_and_term_curr_lim 0x03 +#define bq256xx_battery_voltage_limit 0x04 +#define bq256xx_charger_control_1 0x05 +#define bq256xx_charger_control_2 0x06 +#define bq256xx_charger_control_3 0x07 +#define bq256xx_charger_status_0 0x08 +#define bq256xx_charger_status_1 0x09 +#define bq256xx_charger_status_2 0x0a +#define bq256xx_part_information 0x0b +#define bq256xx_charger_control_4 0x0c + +#define bq256xx_iindpm_mask genmask(4, 0) +#define bq256xx_iindpm_step_ua 100000 +#define bq256xx_iindpm_offset_ua 100000 +#define bq256xx_iindpm_min_ua 100000 +#define bq256xx_iindpm_max_ua 3200000 +#define bq256xx_iindpm_def_ua 2400000 + +#define bq256xx_vindpm_mask genmask(3, 0) +#define bq256xx_vindpm_step_uv 100000 +#define bq256xx_vindpm_offset_uv 3900000 +#define bq256xx_vindpm_min_uv 3900000 +#define bq256xx_vindpm_max_uv 5400000 +#define bq256xx_vindpm_def_uv 4500000 + +#define bq256xx_vbatreg_mask genmask(7, 3) +#define bq2560x_vbatreg_step_uv 32000 +#define bq2560x_vbatreg_offset_uv 3856000 +#define bq2560x_vbatreg_min_uv 3856000 +#define bq2560x_vbatreg_max_uv 4624000 +#define bq2560x_vbatreg_def_uv 4208000 +#define bq25601d_vbatreg_offset_uv 3847000 +#define bq25601d_vbatreg_min_uv 3847000 +#define bq25601d_vbatreg_max_uv 4615000 +#define bq25601d_vbatreg_def_uv 4199000 +#define bq2561x_vbatreg_step_uv 10000 +#define bq25611d_vbatreg_min_uv 3494000 +#define bq25611d_vbatreg_max_uv 4510000 +#define bq25611d_vbatreg_def_uv 4190000 +#define bq25618_vbatreg_min_uv 3504000 +#define bq25618_vbatreg_max_uv 4500000 +#define bq25618_vbatreg_def_uv 4200000 +#define bq256xx_vbatreg_bit_shift 3 +#define bq2561x_vbatreg_thresh 0x8 +#define bq25611d_vbatreg_thresh_uv 4290000 +#define bq25618_vbatreg_thresh_uv 4300000 + +#define bq256xx_iterm_mask genmask(3, 0) +#define bq256xx_iterm_step_ua 60000 +#define bq256xx_iterm_offset_ua 60000 +#define bq256xx_iterm_min_ua 60000 +#define bq256xx_iterm_max_ua 780000 +#define bq256xx_iterm_def_ua 180000 +#define bq25618_iterm_step_ua 20000 +#define bq25618_iterm_offset_ua 20000 +#define bq25618_iterm_min_ua 20000 +#define bq25618_iterm_max_ua 260000 +#define bq25618_iterm_def_ua 60000 + +#define bq256xx_iprechg_mask genmask(7, 4) +#define bq256xx_iprechg_step_ua 60000 +#define bq256xx_iprechg_offset_ua 60000 +#define bq256xx_iprechg_min_ua 60000 +#define bq256xx_iprechg_max_ua 780000 +#define bq256xx_iprechg_def_ua 180000 +#define bq25618_iprechg_step_ua 20000 +#define bq25618_iprechg_offset_ua 20000 +#define bq25618_iprechg_min_ua 20000 +#define bq25618_iprechg_max_ua 260000 +#define bq25618_iprechg_def_ua 40000 +#define bq256xx_iprechg_bit_shift 4 + +#define bq256xx_ichg_mask genmask(5, 0) +#define bq256xx_ichg_step_ua 60000 +#define bq256xx_ichg_min_ua 0 +#define bq256xx_ichg_max_ua 3000000 +#define bq2560x_ichg_def_ua 2040000 +#define bq25611d_ichg_def_ua 1020000 +#define bq25618_ichg_step_ua 20000 +#define bq25618_ichg_min_ua 0 +#define bq25618_ichg_max_ua 1500000 +#define bq25618_ichg_def_ua 340000 +#define bq25618_ichg_thresh 0x3c +#define bq25618_ichg_thresh_ua 1180000 + +#define bq256xx_vbus_stat_mask genmask(7, 5) +#define bq256xx_vbus_stat_no_input 0 +#define bq256xx_vbus_stat_usb_sdp bit(5) +#define bq256xx_vbus_stat_usb_cdp bit(6) +#define bq256xx_vbus_stat_usb_dcp (bit(6) | bit(5)) +#define bq256xx_vbus_stat_usb_otg (bit(7) | bit(6) | bit(5)) + +#define bq256xx_chrg_stat_mask genmask(4, 3) +#define bq256xx_chrg_stat_not_chrging 0 +#define bq256xx_chrg_stat_prechrging bit(3) +#define bq256xx_chrg_stat_fast_chrging bit(4) +#define bq256xx_chrg_stat_chrg_term (bit(4) | bit(3)) + +#define bq256xx_pg_stat_mask bit(2) +#define bq256xx_wdt_fault_mask bit(7) +#define bq256xx_chrg_fault_mask genmask(5, 4) +#define bq256xx_chrg_fault_normal 0 +#define bq256xx_chrg_fault_input bit(4) +#define bq256xx_chrg_fault_therm bit(5) +#define bq256xx_chrg_fault_cst_expire (bit(5) | bit(4)) +#define bq256xx_bat_fault_mask bit(3) +#define bq256xx_ntc_fault_mask genmask(2, 0) +#define bq256xx_ntc_fault_warm bit(1) +#define bq256xx_ntc_fault_cool (bit(1) | bit(0)) +#define bq256xx_ntc_fault_cold (bit(2) | bit(0)) +#define bq256xx_ntc_fault_hot (bit(2) | bit(1)) + +#define bq256xx_num_wd_val 8 +#define bq256xx_watchdog_mask genmask(5, 4) +#define bq256xx_watchdog_max 1600000 +#define bq256xx_watchdog_dis 0 +#define bq256xx_wdt_bit_shift 4 + +#define bq256xx_reg_rst bit(7) + +/** + * struct bq256xx_init_data - + * @ichg: fast charge current + * @iindpm: input current limit + * @vbatreg: charge voltage + * @iterm: termination current + * @iprechg: precharge current + * @vindpm: input voltage limit + * @ichg_max: maximum fast charge current + * @vbatreg_max: maximum charge voltage + */ +struct bq256xx_init_data { + u32 ichg; + u32 iindpm; + u32 vbatreg; + u32 iterm; + u32 iprechg; + u32 vindpm; + u32 ichg_max; + u32 vbatreg_max; +}; + +/** + * struct bq256xx_state - + * @vbus_stat: vbus status according to bq256xx_charger_status_0 + * @chrg_stat: charging status according to bq256xx_charger_status_0 + * @online: pg status according to bq256xx_charger_status_0 + * + * @wdt_fault: watchdog fault according to bq256xx_charger_status_1 + * @bat_fault: battery fault according to bq256xx_charger_status_1 + * @chrg_fault: charging fault according to bq256xx_charger_status_1 + * @ntc_fault: ts fault according to bq256xx_charger_status_1 + */ +struct bq256xx_state { + u8 vbus_stat; + u8 chrg_stat; + bool online; + + u8 wdt_fault; + u8 bat_fault; + u8 chrg_fault; + u8 ntc_fault; +}; + +enum bq256xx_id { + bq25600, + bq25600d, + bq25601, + bq25601d, + bq25618, + bq25619, + bq25611d, +}; + +/** + * struct bq256xx_device - + * @client: i2c client structure + * @regmap: register map structure + * @dev: device structure + * @lock: mutex lock structure + * + * @usb2_phy: usb_phy identifier + * @usb3_phy: usb_phy identifier + * @usb_nb: notifier block + * @usb_work: usb work queue + * @usb_event: usb_event code + * + * @model_name: i2c name string + * + * @init_data: initialization data + * @chip_info: device variant information + * @state: device status and faults + * @watchdog_timer: watchdog timer value in milliseconds + */ +struct bq256xx_device { + struct i2c_client *client; + struct device *dev; + struct power_supply *charger; + struct power_supply *battery; + struct mutex lock; + struct regmap *regmap; + + struct usb_phy *usb2_phy; + struct usb_phy *usb3_phy; + struct notifier_block usb_nb; + struct work_struct usb_work; + unsigned long usb_event; + + char model_name[i2c_name_size]; + + struct bq256xx_init_data init_data; + const struct bq256xx_chip_info *chip_info; + struct bq256xx_state state; + int watchdog_timer; +}; + +/** + * struct bq256xx_chip_info - + * @model_id: device instance + * + * @bq256xx_regmap_config: regmap configuration struct + * @bq256xx_get_ichg: pointer to instance specific get_ichg function + * @bq256xx_get_iindpm: pointer to instance specific get_iindpm function + * @bq256xx_get_vbatreg: pointer to instance specific get_vbatreg function + * @bq256xx_get_iterm: pointer to instance specific get_iterm function + * @bq256xx_get_iprechg: pointer to instance specific get_iprechg function + * @bq256xx_get_vindpm: pointer to instance specific get_vindpm function + * + * @bq256xx_set_ichg: pointer to instance specific set_ichg function + * @bq256xx_set_iindpm: pointer to instance specific set_iindpm function + * @bq256xx_set_vbatreg: pointer to instance specific set_vbatreg function + * @bq256xx_set_iterm: pointer to instance specific set_iterm function + * @bq256xx_set_iprechg: pointer to instance specific set_iprechg function + * @bq256xx_set_vindpm: pointer to instance specific set_vindpm function + * + * @bq256xx_def_ichg: default ichg value in microamps + * @bq256xx_def_iindpm: default iindpm value in microamps + * @bq256xx_def_vbatreg: default vbatreg value in microvolts + * @bq256xx_def_iterm: default iterm value in microamps + * @bq256xx_def_iprechg: default iprechg value in microamps + * @bq256xx_def_vindpm: default vindpm value in microvolts + * + * @bq256xx_max_ichg: maximum charge current in microamps + * @bq256xx_max_vbatreg: maximum battery regulation voltage in microvolts + * + * @has_usb_detect: indicates whether device has bc1.2 detection + */ +struct bq256xx_chip_info { + int model_id; + + const struct regmap_config *bq256xx_regmap_config; + + int (*bq256xx_get_ichg)(struct bq256xx_device *bq); + int (*bq256xx_get_iindpm)(struct bq256xx_device *bq); + int (*bq256xx_get_vbatreg)(struct bq256xx_device *bq); + int (*bq256xx_get_iterm)(struct bq256xx_device *bq); + int (*bq256xx_get_iprechg)(struct bq256xx_device *bq); + int (*bq256xx_get_vindpm)(struct bq256xx_device *bq); + + int (*bq256xx_set_ichg)(struct bq256xx_device *bq, int ichg); + int (*bq256xx_set_iindpm)(struct bq256xx_device *bq, int iindpm); + int (*bq256xx_set_vbatreg)(struct bq256xx_device *bq, int vbatreg); + int (*bq256xx_set_iterm)(struct bq256xx_device *bq, int iterm); + int (*bq256xx_set_iprechg)(struct bq256xx_device *bq, int iprechg); + int (*bq256xx_set_vindpm)(struct bq256xx_device *bq, int vindpm); + + int bq256xx_def_ichg; + int bq256xx_def_iindpm; + int bq256xx_def_vbatreg; + int bq256xx_def_iterm; + int bq256xx_def_iprechg; + int bq256xx_def_vindpm; + + int bq256xx_max_ichg; + int bq256xx_max_vbatreg; + + bool has_usb_detect; +}; + +static int bq256xx_watchdog_time[bq256xx_num_wd_val] = { + 0, 40000, 80000, 1600000 +}; + +static const int bq25611d_vbatreg_values[] = { + 3494000, 3590000, 3686000, 3790000, 3894000, 3990000, 4090000, 4140000, + 4190000 +}; + +static const int bq25618_619_vbatreg_values[] = { + 3504000, 3600000, 3696000, 3800000, 3904000, 4000000, 4100000, 4150000, + 4200000 +}; + +static const int bq25618_619_ichg_values[] = { + 1290000, 1360000, 1430000, 1500000 +}; + +static enum power_supply_usb_type bq256xx_usb_type[] = { + power_supply_usb_type_sdp, + power_supply_usb_type_cdp, + power_supply_usb_type_dcp, + power_supply_usb_type_unknown, + power_supply_usb_type_aca, +}; + +static int bq256xx_array_parse(int array_size, int val, const int array[]) +{ + int i = 0; + + if (val < array[i]) + return i - 1; + + if (val >= array[array_size - 1]) + return array_size - 1; + + for (i = 1; i < array_size; i++) { + if (val == array[i]) + return i; + + if (val > array[i - 1] && val < array[i]) { + if (val < array[i]) + return i - 1; + else + return i; + } + } + return -einval; +} + +static int bq256xx_usb_notifier(struct notifier_block *nb, unsigned long val, + void *priv) +{ + struct bq256xx_device *bq = + container_of(nb, struct bq256xx_device, usb_nb); + + bq->usb_event = val; + queue_work(system_power_efficient_wq, &bq->usb_work); + + return notify_ok; +} + +static void bq256xx_usb_work(struct work_struct *data) +{ + struct bq256xx_device *bq = + container_of(data, struct bq256xx_device, usb_work); + + switch (bq->usb_event) { + case usb_event_id: + break; + case usb_event_none: + power_supply_changed(bq->charger); + break; + default: + dev_err(bq->dev, "error switching to charger mode. "); + break; + } +} + +static struct reg_default bq2560x_reg_defs[] = { + {bq256xx_input_current_limit, 0x17}, + {bq256xx_charger_control_0, 0x1a}, + {bq256xx_charge_current_limit, 0xa2}, + {bq256xx_prechg_and_term_curr_lim, 0x22}, + {bq256xx_battery_voltage_limit, 0x58}, + {bq256xx_charger_control_1, 0x9f}, + {bq256xx_charger_control_2, 0x66}, + {bq256xx_charger_control_3, 0x4c}, +}; + +static struct reg_default bq25611d_reg_defs[] = { + {bq256xx_input_current_limit, 0x17}, + {bq256xx_charger_control_0, 0x1a}, + {bq256xx_charge_current_limit, 0x91}, + {bq256xx_prechg_and_term_curr_lim, 0x12}, + {bq256xx_battery_voltage_limit, 0x40}, + {bq256xx_charger_control_1, 0x9e}, + {bq256xx_charger_control_2, 0xe6}, + {bq256xx_charger_control_3, 0x4c}, + {bq256xx_part_information, 0x54}, + {bq256xx_charger_control_4, 0x75}, +}; + +static struct reg_default bq25618_619_reg_defs[] = { + {bq256xx_input_current_limit, 0x17}, + {bq256xx_charger_control_0, 0x1a}, + {bq256xx_charge_current_limit, 0x91}, + {bq256xx_prechg_and_term_curr_lim, 0x12}, + {bq256xx_battery_voltage_limit, 0x40}, + {bq256xx_charger_control_1, 0x9e}, + {bq256xx_charger_control_2, 0xe6}, + {bq256xx_charger_control_3, 0x4c}, + {bq256xx_part_information, 0x2c}, + {bq256xx_charger_control_4, 0x75}, +}; + +static int bq256xx_get_state(struct bq256xx_device *bq, + struct bq256xx_state *state) +{ + unsigned int charger_status_0; + unsigned int charger_status_1; + int ret; + + ret = regmap_read(bq->regmap, bq256xx_charger_status_0, + &charger_status_0); + if (ret) + return ret; + + ret = regmap_read(bq->regmap, bq256xx_charger_status_1, + &charger_status_1); + if (ret) + return ret; + + state->vbus_stat = charger_status_0 & bq256xx_vbus_stat_mask; + state->chrg_stat = charger_status_0 & bq256xx_chrg_stat_mask; + state->online = charger_status_0 & bq256xx_pg_stat_mask; + + state->wdt_fault = charger_status_1 & bq256xx_wdt_fault_mask; + state->bat_fault = charger_status_1 & bq256xx_bat_fault_mask; + state->chrg_fault = charger_status_1 & bq256xx_chrg_fault_mask; + state->ntc_fault = charger_status_1 & bq256xx_ntc_fault_mask; + + return 0; +} + +static int bq256xx_get_ichg_curr(struct bq256xx_device *bq) +{ + unsigned int charge_current_limit; + unsigned int ichg_reg_code; + int ret; + + ret = regmap_read(bq->regmap, bq256xx_charge_current_limit, + &charge_current_limit); + if (ret) + return ret; + + ichg_reg_code = charge_current_limit & bq256xx_ichg_mask; + + return ichg_reg_code * bq256xx_ichg_step_ua; +} + +static int bq25618_619_get_ichg_curr(struct bq256xx_device *bq) +{ + unsigned int charge_current_limit; + unsigned int ichg_reg_code; + int ret; + + ret = regmap_read(bq->regmap, bq256xx_charge_current_limit, + &charge_current_limit); + if (ret) + return ret; + + ichg_reg_code = charge_current_limit & bq256xx_ichg_mask; + + if (ichg_reg_code < bq25618_ichg_thresh) + return ichg_reg_code * bq25618_ichg_step_ua; + + return bq25618_619_ichg_values[ichg_reg_code - bq25618_ichg_thresh]; +} + +static int bq256xx_set_ichg_curr(struct bq256xx_device *bq, int ichg) +{ + unsigned int ichg_reg_code; + int ichg_max = bq->init_data.ichg_max; + + ichg = clamp(ichg, bq256xx_ichg_min_ua, ichg_max); + ichg_reg_code = ichg / bq256xx_ichg_step_ua; + + return regmap_update_bits(bq->regmap, bq256xx_charge_current_limit, + bq256xx_ichg_mask, ichg_reg_code); +} + +static int bq25618_619_set_ichg_curr(struct bq256xx_device *bq, int ichg) +{ + int array_size = array_size(bq25618_619_ichg_values); + unsigned int ichg_reg_code; + int ichg_max = bq->init_data.ichg_max; + + ichg = clamp(ichg, bq25618_ichg_min_ua, ichg_max); + + if (ichg <= bq25618_ichg_thresh_ua) { + ichg_reg_code = ichg / bq25618_ichg_step_ua; + } else { + ichg_reg_code = bq256xx_array_parse(array_size, ichg, + bq25618_619_ichg_values) + bq25618_ichg_thresh; + } + + return regmap_update_bits(bq->regmap, bq256xx_charge_current_limit, + bq256xx_ichg_mask, ichg_reg_code); +} + +static int bq25618_619_get_chrg_volt(struct bq256xx_device *bq) +{ + unsigned int battery_volt_lim; + unsigned int vbatreg_reg_code; + int ret; + + ret = regmap_read(bq->regmap, bq256xx_battery_voltage_limit, + &battery_volt_lim); + + if (ret) + return ret; + + vbatreg_reg_code = (battery_volt_lim & bq256xx_vbatreg_mask) >> + bq256xx_vbatreg_bit_shift; + + if (vbatreg_reg_code > bq2561x_vbatreg_thresh) + return ((vbatreg_reg_code - bq2561x_vbatreg_thresh) * + bq2561x_vbatreg_step_uv) + + bq25618_vbatreg_thresh_uv; + + return bq25618_619_vbatreg_values[vbatreg_reg_code]; +} + +static int bq25611d_get_chrg_volt(struct bq256xx_device *bq) +{ + unsigned int battery_volt_lim; + unsigned int vbatreg_reg_code; + int ret; + + ret = regmap_read(bq->regmap, bq256xx_battery_voltage_limit, + &battery_volt_lim); + if (ret) + return ret; + + vbatreg_reg_code = (battery_volt_lim & bq256xx_vbatreg_mask) >> + bq256xx_vbatreg_bit_shift; + + if (vbatreg_reg_code > bq2561x_vbatreg_thresh) + return ((vbatreg_reg_code - bq2561x_vbatreg_thresh) * + bq2561x_vbatreg_step_uv) + + bq25611d_vbatreg_thresh_uv; + + return bq25611d_vbatreg_values[vbatreg_reg_code]; +} + +static int bq2560x_get_chrg_volt(struct bq256xx_device *bq) +{ + unsigned int battery_volt_lim; + unsigned int vbatreg_reg_code; + int ret; + + ret = regmap_read(bq->regmap, bq256xx_battery_voltage_limit, + &battery_volt_lim); + if (ret) + return ret; + + vbatreg_reg_code = (battery_volt_lim & bq256xx_vbatreg_mask) >> + bq256xx_vbatreg_bit_shift; + + return (vbatreg_reg_code * bq2560x_vbatreg_step_uv) + + bq2560x_vbatreg_offset_uv; +} + +static int bq25601d_get_chrg_volt(struct bq256xx_device *bq) +{ + unsigned int battery_volt_lim; + unsigned int vbatreg_reg_code; + int ret; + + ret = regmap_read(bq->regmap, bq256xx_battery_voltage_limit, + &battery_volt_lim); + if (ret) + return ret; + + vbatreg_reg_code = (battery_volt_lim & bq256xx_vbatreg_mask) >> + bq256xx_vbatreg_bit_shift; + + return (vbatreg_reg_code * bq2560x_vbatreg_step_uv) + + bq25601d_vbatreg_offset_uv; +} + +static int bq25618_619_set_chrg_volt(struct bq256xx_device *bq, int vbatreg) +{ + int array_size = array_size(bq25618_619_vbatreg_values); + unsigned int vbatreg_reg_code; + int vbatreg_max = bq->init_data.vbatreg_max; + + vbatreg = clamp(vbatreg, bq25618_vbatreg_min_uv, vbatreg_max); + + if (vbatreg > bq25618_vbatreg_thresh_uv) + vbatreg_reg_code = ((vbatreg - + bq25618_vbatreg_thresh_uv) / + (bq2561x_vbatreg_step_uv)) + bq2561x_vbatreg_thresh; + else { + vbatreg_reg_code = bq256xx_array_parse(array_size, vbatreg, + bq25618_619_vbatreg_values); + } + + return regmap_update_bits(bq->regmap, bq256xx_battery_voltage_limit, + bq256xx_vbatreg_mask, vbatreg_reg_code << + bq256xx_vbatreg_bit_shift); +} + +static int bq25611d_set_chrg_volt(struct bq256xx_device *bq, int vbatreg) +{ + int array_size = array_size(bq25611d_vbatreg_values); + unsigned int vbatreg_reg_code; + int vbatreg_max = bq->init_data.vbatreg_max; + + vbatreg = clamp(vbatreg, bq25611d_vbatreg_min_uv, vbatreg_max); + + if (vbatreg > bq25611d_vbatreg_thresh_uv) + vbatreg_reg_code = ((vbatreg - + bq25611d_vbatreg_thresh_uv) / + (bq2561x_vbatreg_step_uv)) + bq2561x_vbatreg_thresh; + else { + vbatreg_reg_code = bq256xx_array_parse(array_size, vbatreg, + bq25611d_vbatreg_values); + } + + return regmap_update_bits(bq->regmap, bq256xx_battery_voltage_limit, + bq256xx_vbatreg_mask, vbatreg_reg_code << + bq256xx_vbatreg_bit_shift); +} + +static int bq2560x_set_chrg_volt(struct bq256xx_device *bq, int vbatreg) +{ + unsigned int vbatreg_reg_code; + int vbatreg_max = bq->init_data.vbatreg_max; + + vbatreg = clamp(vbatreg, bq2560x_vbatreg_min_uv, vbatreg_max); + + vbatreg_reg_code = (vbatreg - bq2560x_vbatreg_offset_uv) / + bq2560x_vbatreg_step_uv; + + return regmap_update_bits(bq->regmap, bq256xx_battery_voltage_limit, + bq256xx_vbatreg_mask, vbatreg_reg_code << + bq256xx_vbatreg_bit_shift); +} + +static int bq25601d_set_chrg_volt(struct bq256xx_device *bq, int vbatreg) +{ + unsigned int vbatreg_reg_code; + int vbatreg_max = bq->init_data.vbatreg_max; + + vbatreg = clamp(vbatreg, bq25601d_vbatreg_min_uv, vbatreg_max); + + vbatreg_reg_code = (vbatreg - bq25601d_vbatreg_offset_uv) / + bq2560x_vbatreg_step_uv; + + return regmap_update_bits(bq->regmap, bq256xx_battery_voltage_limit, + bq256xx_vbatreg_mask, vbatreg_reg_code << + bq256xx_vbatreg_bit_shift); +} + +static int bq256xx_get_prechrg_curr(struct bq256xx_device *bq) +{ + unsigned int prechg_and_term_curr_lim; + unsigned int iprechg_reg_code; + int ret; + + ret = regmap_read(bq->regmap, bq256xx_prechg_and_term_curr_lim, + &prechg_and_term_curr_lim); + if (ret) + return ret; + + iprechg_reg_code = (prechg_and_term_curr_lim & bq256xx_iprechg_mask) + >> bq256xx_iprechg_bit_shift; + + return (iprechg_reg_code * bq256xx_iprechg_step_ua) + + bq256xx_iprechg_offset_ua; +} + +static int bq256xx_set_prechrg_curr(struct bq256xx_device *bq, int iprechg) +{ + unsigned int iprechg_reg_code; + + iprechg = clamp(iprechg, bq256xx_iprechg_min_ua, + bq256xx_iprechg_max_ua); + + iprechg_reg_code = ((iprechg - bq256xx_iprechg_offset_ua) / + bq256xx_iprechg_step_ua) << bq256xx_iprechg_bit_shift; + + return regmap_update_bits(bq->regmap, bq256xx_prechg_and_term_curr_lim, + bq256xx_iprechg_mask, iprechg_reg_code); +} + +static int bq25618_619_get_prechrg_curr(struct bq256xx_device *bq) +{ + unsigned int prechg_and_term_curr_lim; + unsigned int iprechg_reg_code; + int ret; + + ret = regmap_read(bq->regmap, bq256xx_prechg_and_term_curr_lim, + &prechg_and_term_curr_lim); + if (ret) + return ret; + + iprechg_reg_code = (prechg_and_term_curr_lim & bq256xx_iprechg_mask) + >> bq256xx_iprechg_bit_shift; + + return (iprechg_reg_code * bq25618_iprechg_step_ua) + + bq25618_iprechg_offset_ua; +} + +static int bq25618_619_set_prechrg_curr(struct bq256xx_device *bq, int iprechg) +{ + unsigned int iprechg_reg_code; + + iprechg = clamp(iprechg, bq25618_iprechg_min_ua, + bq25618_iprechg_max_ua); + + iprechg_reg_code = ((iprechg - bq25618_iprechg_offset_ua) / + bq25618_iprechg_step_ua) << bq256xx_iprechg_bit_shift; + + return regmap_update_bits(bq->regmap, bq256xx_prechg_and_term_curr_lim, + bq256xx_iprechg_mask, iprechg_reg_code); +} + +static int bq256xx_get_term_curr(struct bq256xx_device *bq) +{ + unsigned int prechg_and_term_curr_lim; + unsigned int iterm_reg_code; + int ret; + + ret = regmap_read(bq->regmap, bq256xx_prechg_and_term_curr_lim, + &prechg_and_term_curr_lim); + if (ret) + return ret; + + iterm_reg_code = prechg_and_term_curr_lim & bq256xx_iterm_mask; + + return (iterm_reg_code * bq256xx_iterm_step_ua) + + bq256xx_iterm_offset_ua; +} + +static int bq256xx_set_term_curr(struct bq256xx_device *bq, int iterm) +{ + unsigned int iterm_reg_code; + + iterm = clamp(iterm, bq256xx_iterm_min_ua, bq256xx_iterm_max_ua); + + iterm_reg_code = (iterm - bq256xx_iterm_offset_ua) / + bq256xx_iterm_step_ua; + + return regmap_update_bits(bq->regmap, bq256xx_prechg_and_term_curr_lim, + bq256xx_iterm_mask, iterm_reg_code); +} + +static int bq25618_619_get_term_curr(struct bq256xx_device *bq) +{ + unsigned int prechg_and_term_curr_lim; + unsigned int iterm_reg_code; + int ret; + + ret = regmap_read(bq->regmap, bq256xx_prechg_and_term_curr_lim, + &prechg_and_term_curr_lim); + if (ret) + return ret; + + iterm_reg_code = prechg_and_term_curr_lim & bq256xx_iterm_mask; + + return (iterm_reg_code * bq25618_iterm_step_ua) + + bq25618_iterm_offset_ua; +} + +static int bq25618_619_set_term_curr(struct bq256xx_device *bq, int iterm) +{ + unsigned int iterm_reg_code; + + iterm = clamp(iterm, bq25618_iterm_min_ua, bq25618_iterm_max_ua); + + iterm_reg_code = (iterm - bq25618_iterm_offset_ua) / + bq25618_iterm_step_ua; + + return regmap_update_bits(bq->regmap, bq256xx_prechg_and_term_curr_lim, + bq256xx_iterm_mask, iterm_reg_code); +} + +static int bq256xx_get_input_volt_lim(struct bq256xx_device *bq) +{ + unsigned int charger_control_2; + unsigned int vindpm_reg_code; + int ret; + + ret = regmap_read(bq->regmap, bq256xx_charger_control_2, + &charger_control_2); + if (ret) + return ret; + + vindpm_reg_code = charger_control_2 & bq256xx_vindpm_mask; + + return (vindpm_reg_code * bq256xx_vindpm_step_uv) + + bq256xx_vindpm_offset_uv; +} + +static int bq256xx_set_input_volt_lim(struct bq256xx_device *bq, int vindpm) +{ + unsigned int vindpm_reg_code; + + vindpm = clamp(vindpm, bq256xx_vindpm_min_uv, bq256xx_vindpm_max_uv); + + vindpm_reg_code = (vindpm - bq256xx_vindpm_offset_uv) / + bq256xx_vindpm_step_uv; + + return regmap_update_bits(bq->regmap, bq256xx_charger_control_2, + bq256xx_vindpm_mask, vindpm_reg_code); +} + +static int bq256xx_get_input_curr_lim(struct bq256xx_device *bq) +{ + unsigned int input_current_limit; + unsigned int iindpm_reg_code; + int ret; + + ret = regmap_read(bq->regmap, bq256xx_input_current_limit, + &input_current_limit); + if (ret) + return ret; + + iindpm_reg_code = input_current_limit & bq256xx_iindpm_mask; + + return (iindpm_reg_code * bq256xx_iindpm_step_ua) + + bq256xx_iindpm_offset_ua; +} + +static int bq256xx_set_input_curr_lim(struct bq256xx_device *bq, int iindpm) +{ + unsigned int iindpm_reg_code; + + iindpm = clamp(iindpm, bq256xx_iindpm_min_ua, bq256xx_iindpm_max_ua); + + iindpm_reg_code = (iindpm - bq256xx_iindpm_offset_ua) / + bq256xx_iindpm_step_ua; + + return regmap_update_bits(bq->regmap, bq256xx_input_current_limit, + bq256xx_iindpm_mask, iindpm_reg_code); +} + +static void bq256xx_charger_reset(void *data) +{ + struct bq256xx_device *bq = data; + + regmap_update_bits(bq->regmap, bq256xx_part_information, + bq256xx_reg_rst, bq256xx_reg_rst); + + if (!is_err_or_null(bq->usb2_phy)) + usb_unregister_notifier(bq->usb2_phy, &bq->usb_nb); + + if (!is_err_or_null(bq->usb3_phy)) + usb_unregister_notifier(bq->usb3_phy, &bq->usb_nb); +} + +static int bq256xx_set_charger_property(struct power_supply *psy, + enum power_supply_property prop, + const union power_supply_propval *val) +{ + struct bq256xx_device *bq = power_supply_get_drvdata(psy); + int ret = -einval; + + switch (prop) { + case power_supply_prop_input_current_limit: + ret = bq->chip_info->bq256xx_set_iindpm(bq, val->intval); + if (ret) + return ret; + break; + + case power_supply_prop_status: + break; + + case power_supply_prop_constant_charge_voltage: + ret = bq->chip_info->bq256xx_set_vbatreg(bq, val->intval); + if (ret) + return ret; + break; + + case power_supply_prop_constant_charge_current: + ret = bq->chip_info->bq256xx_set_ichg(bq, val->intval); + if (ret) + return ret; + break; + + case power_supply_prop_precharge_current: + ret = bq->chip_info->bq256xx_set_iprechg(bq, val->intval); + if (ret) + return ret; + break; + + case power_supply_prop_charge_term_current: + ret = bq->chip_info->bq256xx_set_iterm(bq, val->intval); + if (ret) + return ret; + break; + + case power_supply_prop_input_voltage_limit: + ret = bq->chip_info->bq256xx_set_vindpm(bq, val->intval); + if (ret) + return ret; + break; + + default: + break; + } + + return ret; +} + + +static int bq256xx_get_battery_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct bq256xx_device *bq = power_supply_get_drvdata(psy); + + switch (psp) { + case power_supply_prop_constant_charge_current_max: + val->intval = bq->init_data.ichg_max; + break; + + case power_supply_prop_constant_charge_voltage_max: + val->intval = bq->init_data.vbatreg_max; + break; + + default: + return -einval; + } + + return 0; +} + +static int bq256xx_get_charger_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct bq256xx_device *bq = power_supply_get_drvdata(psy); + struct bq256xx_state state; + int ret = 0; + + mutex_lock(&bq->lock); + ret = bq256xx_get_state(bq, &state); + mutex_unlock(&bq->lock); + if (ret) + return ret; + + switch (psp) { + case power_supply_prop_status: + if (state.vbus_stat == bq256xx_vbus_stat_no_input || + state.vbus_stat == bq256xx_vbus_stat_usb_otg) + val->intval = power_supply_status_discharging; + else if (state.chrg_stat == bq256xx_chrg_stat_not_chrging) + val->intval = power_supply_status_not_charging; + else if (state.chrg_stat == bq256xx_chrg_stat_chrg_term) + val->intval = power_supply_status_full; + else + val->intval = power_supply_status_charging; + break; + + case power_supply_prop_health: + val->intval = power_supply_health_unknown; + if (state.wdt_fault) { + val->intval = + power_supply_health_watchdog_timer_expire; + } else if (state.bat_fault) { + val->intval = power_supply_health_overvoltage; + } else { + switch (state.chrg_stat) { + case bq256xx_chrg_fault_input: + val->intval = + power_supply_health_unspec_failure; + break; + case bq256xx_chrg_fault_therm: + val->intval = power_supply_health_overheat; + break; + case bq256xx_chrg_fault_cst_expire: + val->intval = + power_supply_health_safety_timer_expire; + break; + default: + break; + } + + switch (state.ntc_fault) { + case bq256xx_ntc_fault_warm: + val->intval = power_supply_health_warm; + break; + case bq256xx_ntc_fault_cool: + val->intval = power_supply_health_cool; + break; + case bq256xx_ntc_fault_cold: + val->intval = power_supply_health_cold; + break; + case bq256xx_ntc_fault_hot: + val->intval = power_supply_health_hot; + break; + default: + val->intval = power_supply_health_good; + break; + } + } + break; + + case power_supply_prop_usb_type: + if (bq->chip_info->has_usb_detect) { + switch (state.vbus_stat) { + case bq256xx_vbus_stat_usb_sdp: + val->intval = power_supply_usb_type_sdp; + break; + case bq256xx_vbus_stat_usb_cdp: + val->intval = power_supply_usb_type_cdp; + break; + case bq256xx_vbus_stat_usb_dcp: + val->intval = power_supply_usb_type_dcp; + break; + case bq256xx_vbus_stat_usb_otg: + val->intval = power_supply_usb_type_aca; + break; + default: + val->intval = power_supply_usb_type_unknown; + break; + } + } else { + switch (state.vbus_stat) { + case bq256xx_vbus_stat_usb_sdp: + val->intval = power_supply_usb_type_sdp; + break; + case bq256xx_vbus_stat_usb_otg: + val->intval = power_supply_usb_type_aca; + break; + default: + val->intval = power_supply_usb_type_unknown; + break; + } + } + break; + + case power_supply_prop_charge_type: + switch (state.chrg_stat) { + case bq256xx_chrg_stat_not_chrging: + val->intval = power_supply_charge_type_none; + break; + case bq256xx_chrg_stat_prechrging: + val->intval = power_supply_charge_type_trickle; + break; + case bq256xx_chrg_stat_fast_chrging: + val->intval = power_supply_charge_type_fast; + break; + case bq256xx_chrg_stat_chrg_term: + val->intval = power_supply_charge_type_trickle; + break; + default: + val->intval = power_supply_charge_type_unknown; + } + break; + + case power_supply_prop_manufacturer: + val->strval = bq256xx_manufacturer; + break; + + case power_supply_prop_model_name: + val->strval = bq->model_name; + break; + + case power_supply_prop_online: + val->intval = state.online; + break; + + case power_supply_prop_input_voltage_limit: + ret = bq->chip_info->bq256xx_get_vindpm(bq); + if (ret < 0) + return ret; + val->intval = ret; + break; + + case power_supply_prop_input_current_limit: + ret = bq->chip_info->bq256xx_get_iindpm(bq); + if (ret < 0) + return ret; + val->intval = ret; + break; + + case power_supply_prop_constant_charge_voltage: + ret = bq->chip_info->bq256xx_get_vbatreg(bq); + if (ret < 0) + return ret; + val->intval = ret; + break; + + case power_supply_prop_constant_charge_current: + ret = bq->chip_info->bq256xx_get_ichg(bq); + if (ret < 0) + return ret; + val->intval = ret; + break; + + case power_supply_prop_precharge_current: + ret = bq->chip_info->bq256xx_get_iprechg(bq); + if (ret < 0) + return ret; + val->intval = ret; + break; + + case power_supply_prop_charge_term_current: + ret = bq->chip_info->bq256xx_get_iterm(bq); + if (ret < 0) + return ret; + val->intval = ret; + break; + + default: + return -einval; + } + + return ret; +} + +static bool bq256xx_state_changed(struct bq256xx_device *bq, + struct bq256xx_state *new_state) +{ + struct bq256xx_state old_state; + + mutex_lock(&bq->lock); + old_state = bq->state; + mutex_unlock(&bq->lock); + + return memcmp(&old_state, new_state, sizeof(struct bq256xx_state)) != 0; +} + +static irqreturn_t bq256xx_irq_handler_thread(int irq, void *private) +{ + struct bq256xx_device *bq = private; + struct bq256xx_state state; + int ret; + + ret = bq256xx_get_state(bq, &state); + if (ret < 0) + goto irq_out; + + if (!bq256xx_state_changed(bq, &state)) + goto irq_out; + + mutex_lock(&bq->lock); + bq->state = state; + mutex_unlock(&bq->lock); + + power_supply_changed(bq->charger); + +irq_out: + return irq_handled; +} + +static enum power_supply_property bq256xx_power_supply_props[] = { + power_supply_prop_manufacturer, + power_supply_prop_model_name, + power_supply_prop_status, + power_supply_prop_online, + power_supply_prop_health, + power_supply_prop_input_voltage_limit, + power_supply_prop_input_current_limit, + power_supply_prop_charge_type, + power_supply_prop_usb_type, + power_supply_prop_constant_charge_current, + power_supply_prop_constant_charge_voltage, + power_supply_prop_precharge_current, + power_supply_prop_charge_term_current, +}; + +static enum power_supply_property bq256xx_battery_props[] = { + power_supply_prop_constant_charge_current_max, + power_supply_prop_constant_charge_voltage_max, +}; + +static int bq256xx_property_is_writeable(struct power_supply *psy, + enum power_supply_property prop) +{ + switch (prop) { + case power_supply_prop_input_current_limit: + case power_supply_prop_constant_charge_voltage: + case power_supply_prop_constant_charge_current: + case power_supply_prop_precharge_current: + case power_supply_prop_charge_term_current: + case power_supply_prop_status: + case power_supply_prop_input_voltage_limit: + return true; + default: + return false; + } +} + +static const struct power_supply_desc bq256xx_power_supply_desc = { + .name = "bq256xx-charger", + .type = power_supply_type_usb, + .usb_types = bq256xx_usb_type, + .num_usb_types = array_size(bq256xx_usb_type), + .properties = bq256xx_power_supply_props, + .num_properties = array_size(bq256xx_power_supply_props), + .get_property = bq256xx_get_charger_property, + .set_property = bq256xx_set_charger_property, + .property_is_writeable = bq256xx_property_is_writeable, +}; + +static struct power_supply_desc bq256xx_battery_desc = { + .name = "bq256xx-battery", + .type = power_supply_type_battery, + .get_property = bq256xx_get_battery_property, + .properties = bq256xx_battery_props, + .num_properties = array_size(bq256xx_battery_props), + .property_is_writeable = bq256xx_property_is_writeable, +}; + + +static bool bq256xx_is_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case bq256xx_input_current_limit: + case bq256xx_charger_status_0...bq256xx_charger_status_2: + return true; + default: + return false; + } +} + +static const struct regmap_config bq25600_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + + .max_register = bq256xx_part_information, + .reg_defaults = bq2560x_reg_defs, + .num_reg_defaults = array_size(bq2560x_reg_defs), + .cache_type = regcache_flat, + .volatile_reg = bq256xx_is_volatile_reg, +}; + +static const struct regmap_config bq25611d_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + + .max_register = bq256xx_charger_control_4, + .reg_defaults = bq25611d_reg_defs, + .num_reg_defaults = array_size(bq25611d_reg_defs), + .cache_type = regcache_flat, + .volatile_reg = bq256xx_is_volatile_reg, +}; + +static const struct regmap_config bq25618_619_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + + .max_register = bq256xx_charger_control_4, + .reg_defaults = bq25618_619_reg_defs, + .num_reg_defaults = array_size(bq25618_619_reg_defs), + .cache_type = regcache_flat, + .volatile_reg = bq256xx_is_volatile_reg, +}; + +static const struct bq256xx_chip_info bq256xx_chip_info_tbl[] = { + [bq25600] = { + .model_id = bq25600, + .bq256xx_regmap_config = &bq25600_regmap_config, + .bq256xx_get_ichg = bq256xx_get_ichg_curr, + .bq256xx_get_iindpm = bq256xx_get_input_curr_lim, + .bq256xx_get_vbatreg = bq2560x_get_chrg_volt, + .bq256xx_get_iterm = bq256xx_get_term_curr, + .bq256xx_get_iprechg = bq256xx_get_prechrg_curr, + .bq256xx_get_vindpm = bq256xx_get_input_volt_lim, + + .bq256xx_set_ichg = bq256xx_set_ichg_curr, + .bq256xx_set_iindpm = bq256xx_set_input_curr_lim, + .bq256xx_set_vbatreg = bq2560x_set_chrg_volt, + .bq256xx_set_iterm = bq256xx_set_term_curr, + .bq256xx_set_iprechg = bq256xx_set_prechrg_curr, + .bq256xx_set_vindpm = bq256xx_set_input_volt_lim, + + .bq256xx_def_ichg = bq2560x_ichg_def_ua, + .bq256xx_def_iindpm = bq256xx_iindpm_def_ua, + .bq256xx_def_vbatreg = bq2560x_vbatreg_def_uv, + .bq256xx_def_iterm = bq256xx_iterm_def_ua, + .bq256xx_def_iprechg = bq256xx_iprechg_def_ua, + .bq256xx_def_vindpm = bq256xx_vindpm_def_uv, + + .bq256xx_max_ichg = bq256xx_ichg_max_ua, + .bq256xx_max_vbatreg = bq2560x_vbatreg_max_uv, + + .has_usb_detect = false, + }, + + [bq25600d] = { + .model_id = bq25600d, + .bq256xx_regmap_config = &bq25600_regmap_config, + .bq256xx_get_ichg = bq256xx_get_ichg_curr, + .bq256xx_get_iindpm = bq256xx_get_input_curr_lim, + .bq256xx_get_vbatreg = bq2560x_get_chrg_volt, + .bq256xx_get_iterm = bq256xx_get_term_curr, + .bq256xx_get_iprechg = bq256xx_get_prechrg_curr, + .bq256xx_get_vindpm = bq256xx_get_input_volt_lim, + + .bq256xx_set_ichg = bq256xx_set_ichg_curr, + .bq256xx_set_iindpm = bq256xx_set_input_curr_lim, + .bq256xx_set_vbatreg = bq2560x_set_chrg_volt, + .bq256xx_set_iterm = bq256xx_set_term_curr, + .bq256xx_set_iprechg = bq256xx_set_prechrg_curr, + .bq256xx_set_vindpm = bq256xx_set_input_volt_lim, + + .bq256xx_def_ichg = bq2560x_ichg_def_ua, + .bq256xx_def_iindpm = bq256xx_iindpm_def_ua, + .bq256xx_def_vbatreg = bq2560x_vbatreg_def_uv, + .bq256xx_def_iterm = bq256xx_iterm_def_ua, + .bq256xx_def_iprechg = bq256xx_iprechg_def_ua, + .bq256xx_def_vindpm = bq256xx_vindpm_def_uv, + + .bq256xx_max_ichg = bq256xx_ichg_max_ua, + .bq256xx_max_vbatreg = bq2560x_vbatreg_max_uv, + + .has_usb_detect = true, + }, + + [bq25601] = { + .model_id = bq25601, + .bq256xx_regmap_config = &bq25600_regmap_config, + .bq256xx_get_ichg = bq256xx_get_ichg_curr, + .bq256xx_get_iindpm = bq256xx_get_input_curr_lim, + .bq256xx_get_vbatreg = bq2560x_get_chrg_volt, + .bq256xx_get_iterm = bq256xx_get_term_curr, + .bq256xx_get_iprechg = bq256xx_get_prechrg_curr, + .bq256xx_get_vindpm = bq256xx_get_input_volt_lim, + + .bq256xx_set_ichg = bq256xx_set_ichg_curr, + .bq256xx_set_iindpm = bq256xx_set_input_curr_lim, + .bq256xx_set_vbatreg = bq2560x_set_chrg_volt, + .bq256xx_set_iterm = bq256xx_set_term_curr, + .bq256xx_set_iprechg = bq256xx_set_prechrg_curr, + .bq256xx_set_vindpm = bq256xx_set_input_volt_lim, + + .bq256xx_def_ichg = bq2560x_ichg_def_ua, + .bq256xx_def_iindpm = bq256xx_iindpm_def_ua, + .bq256xx_def_vbatreg = bq2560x_vbatreg_def_uv, + .bq256xx_def_iterm = bq256xx_iterm_def_ua, + .bq256xx_def_iprechg = bq256xx_iprechg_def_ua, + .bq256xx_def_vindpm = bq256xx_vindpm_def_uv, + + .bq256xx_max_ichg = bq256xx_ichg_max_ua, + .bq256xx_max_vbatreg = bq2560x_vbatreg_max_uv, + + .has_usb_detect = false, + }, + + [bq25601d] = { + .model_id = bq25601d, + .bq256xx_regmap_config = &bq25600_regmap_config, + .bq256xx_get_ichg = bq256xx_get_ichg_curr, + .bq256xx_get_iindpm = bq256xx_get_input_curr_lim, + .bq256xx_get_vbatreg = bq25601d_get_chrg_volt, + .bq256xx_get_iterm = bq256xx_get_term_curr, + .bq256xx_get_iprechg = bq256xx_get_prechrg_curr, + .bq256xx_get_vindpm = bq256xx_get_input_volt_lim, + + .bq256xx_set_ichg = bq256xx_set_ichg_curr, + .bq256xx_set_iindpm = bq256xx_set_input_curr_lim, + .bq256xx_set_vbatreg = bq25601d_set_chrg_volt, + .bq256xx_set_iterm = bq256xx_set_term_curr, + .bq256xx_set_iprechg = bq256xx_set_prechrg_curr, + .bq256xx_set_vindpm = bq256xx_set_input_volt_lim, + + .bq256xx_def_ichg = bq2560x_ichg_def_ua, + .bq256xx_def_iindpm = bq256xx_iindpm_def_ua, + .bq256xx_def_vbatreg = bq2560x_vbatreg_def_uv, + .bq256xx_def_iterm = bq256xx_iterm_def_ua, + .bq256xx_def_iprechg = bq256xx_iprechg_def_ua, + .bq256xx_def_vindpm = bq256xx_vindpm_def_uv, + + .bq256xx_max_ichg = bq256xx_ichg_max_ua, + .bq256xx_max_vbatreg = bq2560x_vbatreg_max_uv, + + .has_usb_detect = true, + }, + + [bq25611d] = { + .model_id = bq25611d, + .bq256xx_regmap_config = &bq25611d_regmap_config, + .bq256xx_get_ichg = bq256xx_get_ichg_curr, + .bq256xx_get_iindpm = bq256xx_get_input_curr_lim, + .bq256xx_get_vbatreg = bq25611d_get_chrg_volt, + .bq256xx_get_iterm = bq256xx_get_term_curr, + .bq256xx_get_iprechg = bq256xx_get_prechrg_curr, + .bq256xx_get_vindpm = bq256xx_get_input_volt_lim, + + .bq256xx_set_ichg = bq256xx_set_ichg_curr, + .bq256xx_set_iindpm = bq256xx_set_input_curr_lim, + .bq256xx_set_vbatreg = bq25611d_set_chrg_volt, + .bq256xx_set_iterm = bq256xx_set_term_curr, + .bq256xx_set_iprechg = bq256xx_set_prechrg_curr, + .bq256xx_set_vindpm = bq256xx_set_input_volt_lim, + + .bq256xx_def_ichg = bq25611d_ichg_def_ua, + .bq256xx_def_iindpm = bq256xx_iindpm_def_ua, + .bq256xx_def_vbatreg = bq25611d_vbatreg_def_uv, + .bq256xx_def_iterm = bq256xx_iterm_def_ua, + .bq256xx_def_iprechg = bq256xx_iprechg_def_ua, + .bq256xx_def_vindpm = bq256xx_vindpm_def_uv, + + .bq256xx_max_ichg = bq256xx_ichg_max_ua, + .bq256xx_max_vbatreg = bq25611d_vbatreg_max_uv, + + .has_usb_detect = true, + }, + + [bq25618] = { + .model_id = bq25618, + .bq256xx_regmap_config = &bq25618_619_regmap_config, + .bq256xx_get_ichg = bq25618_619_get_ichg_curr, + .bq256xx_get_iindpm = bq256xx_get_input_curr_lim, + .bq256xx_get_vbatreg = bq25618_619_get_chrg_volt, + .bq256xx_get_iterm = bq25618_619_get_term_curr, + .bq256xx_get_iprechg = bq25618_619_get_prechrg_curr, + .bq256xx_get_vindpm = bq256xx_get_input_volt_lim, + + .bq256xx_set_ichg = bq25618_619_set_ichg_curr, + .bq256xx_set_iindpm = bq256xx_set_input_curr_lim, + .bq256xx_set_vbatreg = bq25618_619_set_chrg_volt, + .bq256xx_set_iterm = bq25618_619_set_term_curr, + .bq256xx_set_iprechg = bq25618_619_set_prechrg_curr, + .bq256xx_set_vindpm = bq256xx_set_input_volt_lim, + + .bq256xx_def_ichg = bq25618_ichg_def_ua, + .bq256xx_def_iindpm = bq256xx_iindpm_def_ua, + .bq256xx_def_vbatreg = bq25618_vbatreg_def_uv, + .bq256xx_def_iterm = bq25618_iterm_def_ua, + .bq256xx_def_iprechg = bq25618_iprechg_def_ua, + .bq256xx_def_vindpm = bq256xx_vindpm_def_uv, + + .bq256xx_max_ichg = bq25618_ichg_max_ua, + .bq256xx_max_vbatreg = bq25618_vbatreg_max_uv, + + .has_usb_detect = false, + }, + + [bq25619] = { + .model_id = bq25619, + .bq256xx_regmap_config = &bq25618_619_regmap_config, + .bq256xx_get_ichg = bq25618_619_get_ichg_curr, + .bq256xx_get_iindpm = bq256xx_get_input_curr_lim, + .bq256xx_get_vbatreg = bq25618_619_get_chrg_volt, + .bq256xx_get_iterm = bq25618_619_get_term_curr, + .bq256xx_get_iprechg = bq25618_619_get_prechrg_curr, + .bq256xx_get_vindpm = bq256xx_get_input_volt_lim, + + .bq256xx_set_ichg = bq25618_619_set_ichg_curr, + .bq256xx_set_iindpm = bq256xx_set_input_curr_lim, + .bq256xx_set_vbatreg = bq25618_619_set_chrg_volt, + .bq256xx_set_iterm = bq25618_619_set_term_curr, + .bq256xx_set_iprechg = bq25618_619_set_prechrg_curr, + .bq256xx_set_vindpm = bq256xx_set_input_volt_lim, + + .bq256xx_def_ichg = bq25618_ichg_def_ua, + .bq256xx_def_iindpm = bq256xx_iindpm_def_ua, + .bq256xx_def_vbatreg = bq25618_vbatreg_def_uv, + .bq256xx_def_iterm = bq25618_iterm_def_ua, + .bq256xx_def_iprechg = bq25618_iprechg_def_ua, + .bq256xx_def_vindpm = bq256xx_vindpm_def_uv, + + .bq256xx_max_ichg = bq25618_ichg_max_ua, + .bq256xx_max_vbatreg = bq25618_vbatreg_max_uv, + + .has_usb_detect = false, + }, +}; + +static int bq256xx_power_supply_init(struct bq256xx_device *bq, + struct power_supply_config *psy_cfg, struct device *dev) +{ + bq->charger = devm_power_supply_register(bq->dev, + &bq256xx_power_supply_desc, + psy_cfg); + if (is_err(bq->charger)) { + dev_err(dev, "power supply register charger failed "); + return ptr_err(bq->charger); + } + + bq->battery = devm_power_supply_register(bq->dev, + &bq256xx_battery_desc, + psy_cfg); + if (is_err(bq->battery)) { + dev_err(dev, "power supply register battery failed "); + return ptr_err(bq->battery); + } + return 0; +} + +static int bq256xx_hw_init(struct bq256xx_device *bq) +{ + struct power_supply_battery_info bat_info = { }; + int wd_reg_val = bq256xx_watchdog_dis; + int ret = 0; + int i; + + for (i = 0; i < bq256xx_num_wd_val; i++) { + if (bq->watchdog_timer > bq256xx_watchdog_time[i] && + bq->watchdog_timer < bq256xx_watchdog_time[i + 1]) + wd_reg_val = i; + } + ret = regmap_update_bits(bq->regmap, bq256xx_charger_control_1, + bq256xx_watchdog_mask, wd_reg_val << + bq256xx_wdt_bit_shift); + + ret = power_supply_get_battery_info(bq->charger, &bat_info); + if (ret) { + dev_warn(bq->dev, "battery info missing, default values will be applied "); + + bat_info.constant_charge_current_max_ua = + bq->chip_info->bq256xx_def_ichg; + + bat_info.constant_charge_voltage_max_uv = + bq->chip_info->bq256xx_def_vbatreg; + + bat_info.precharge_current_ua = + bq->chip_info->bq256xx_def_iprechg; + + bat_info.charge_term_current_ua = + bq->chip_info->bq256xx_def_iterm; + + bq->init_data.ichg_max = + bq->chip_info->bq256xx_max_ichg; + + bq->init_data.vbatreg_max = + bq->chip_info->bq256xx_max_vbatreg; + } else { + bq->init_data.ichg_max = + bat_info.constant_charge_current_max_ua; + + bq->init_data.vbatreg_max = + bat_info.constant_charge_voltage_max_uv; + } + + ret = bq->chip_info->bq256xx_set_vindpm(bq, bq->init_data.vindpm); + if (ret) + return ret; + + ret = bq->chip_info->bq256xx_set_iindpm(bq, bq->init_data.iindpm); + if (ret) + return ret; + + ret = bq->chip_info->bq256xx_set_ichg(bq, + bat_info.constant_charge_current_max_ua); + if (ret) + return ret; + + ret = bq->chip_info->bq256xx_set_iprechg(bq, + bat_info.precharge_current_ua); + if (ret) + return ret; + + ret = bq->chip_info->bq256xx_set_vbatreg(bq, + bat_info.constant_charge_voltage_max_uv); + if (ret) + return ret; + + ret = bq->chip_info->bq256xx_set_iterm(bq, + bat_info.charge_term_current_ua); + if (ret) + return ret; + + power_supply_put_battery_info(bq->charger, &bat_info); + + return 0; +} + +static int bq256xx_parse_dt(struct bq256xx_device *bq, + struct power_supply_config *psy_cfg, struct device *dev) +{ + int ret = 0; + + psy_cfg->drv_data = bq; + psy_cfg->of_node = dev->of_node; + + ret = device_property_read_u32(bq->dev, "ti,watchdog-timeout-ms", + &bq->watchdog_timer); + if (ret) + bq->watchdog_timer = bq256xx_watchdog_dis; + + if (bq->watchdog_timer > bq256xx_watchdog_max || + bq->watchdog_timer < bq256xx_watchdog_dis) + return -einval; + + ret = device_property_read_u32(bq->dev, + "input-voltage-limit-microvolt", + &bq->init_data.vindpm); + if (ret) + bq->init_data.vindpm = bq->chip_info->bq256xx_def_vindpm; + + ret = device_property_read_u32(bq->dev, + "input-current-limit-microamp", + &bq->init_data.iindpm); + if (ret) + bq->init_data.iindpm = bq->chip_info->bq256xx_def_iindpm; + + return 0; +} + +static int bq256xx_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct bq256xx_device *bq; + struct power_supply_config psy_cfg = { }; + + int ret; + + bq = devm_kzalloc(dev, sizeof(*bq), gfp_kernel); + if (!bq) + return -enomem; + + bq->client = client; + bq->dev = dev; + bq->chip_info = &bq256xx_chip_info_tbl[id->driver_data]; + + mutex_init(&bq->lock); + + strncpy(bq->model_name, id->name, i2c_name_size); + + bq->regmap = devm_regmap_init_i2c(client, + bq->chip_info->bq256xx_regmap_config); + + if (is_err(bq->regmap)) { + dev_err(dev, "failed to allocate register map "); + return ptr_err(bq->regmap); + } + + i2c_set_clientdata(client, bq); + + ret = bq256xx_parse_dt(bq, &psy_cfg, dev); + if (ret) { + dev_err(dev, "failed to read device tree properties%d ", ret); + return ret; + } + + ret = devm_add_action_or_reset(dev, bq256xx_charger_reset, bq); + if (ret) + return ret; + + /* otg reporting */ + bq->usb2_phy = devm_usb_get_phy(dev, usb_phy_type_usb2); + if (!is_err_or_null(bq->usb2_phy)) { + init_work(&bq->usb_work, bq256xx_usb_work); + bq->usb_nb.notifier_call = bq256xx_usb_notifier; + usb_register_notifier(bq->usb2_phy, &bq->usb_nb); + } + + bq->usb3_phy = devm_usb_get_phy(dev, usb_phy_type_usb3); + if (!is_err_or_null(bq->usb3_phy)) { + init_work(&bq->usb_work, bq256xx_usb_work); + bq->usb_nb.notifier_call = bq256xx_usb_notifier; + usb_register_notifier(bq->usb3_phy, &bq->usb_nb); + } + + if (client->irq) { + ret = devm_request_threaded_irq(dev, client->irq, null, + bq256xx_irq_handler_thread, + irqf_trigger_falling | + irqf_oneshot, + dev_name(&client->dev), bq); + if (ret < 0) { + dev_err(dev, "get irq fail: %d ", ret); + return ret; + } + } + + ret = bq256xx_power_supply_init(bq, &psy_cfg, dev); + if (ret) { + dev_err(dev, "failed to register power supply "); + return ret; + } + + ret = bq256xx_hw_init(bq); + if (ret) { + dev_err(dev, "cannot initialize the chip. "); + return ret; + } + + return ret; +} + +static const struct i2c_device_id bq256xx_i2c_ids[] = { + { "bq25600", bq25600 }, + { "bq25600d", bq25600d }, + { "bq25601", bq25601 }, + { "bq25601d", bq25601d }, + { "bq25611d", bq25611d }, + { "bq25618", bq25618 }, + { "bq25619", bq25619 }, + {}, +}; +module_device_table(i2c, bq256xx_i2c_ids); + +static const struct of_device_id bq256xx_of_match[] = { + { .compatible = "ti,bq25600", .data = (void *)bq25600 }, + { .compatible = "ti,bq25600d", .data = (void *)bq25600d }, + { .compatible = "ti,bq25601", .data = (void *)bq25601 }, + { .compatible = "ti,bq25601d", .data = (void *)bq25601d }, + { .compatible = "ti,bq25611d", .data = (void *)bq25611d }, + { .compatible = "ti,bq25618", .data = (void *)bq25618 }, + { .compatible = "ti,bq25619", .data = (void *)bq25619 }, + { }, +}; +module_device_table(of, bq256xx_of_match); + +static const struct acpi_device_id bq256xx_acpi_match[] = { + { "bq25600", bq25600 }, + { "bq25600d", bq25600d }, + { "bq25601", bq25601 }, + { "bq25601d", bq25601d }, + { "bq25611d", bq25611d }, + { "bq25618", bq25618 }, + { "bq25619", bq25619 }, + {}, +}; +module_device_table(acpi, bq256xx_acpi_match); + +static struct i2c_driver bq256xx_driver = { + .driver = { + .name = "bq256xx-charger", + .of_match_table = bq256xx_of_match, + .acpi_match_table = bq256xx_acpi_match, + }, + .probe = bq256xx_probe, + .id_table = bq256xx_i2c_ids, +}; +module_i2c_driver(bq256xx_driver); + +module_author("ricardo rivera-matos <r-rivera-matos@ti.com>"); +module_description("bq256xx charger driver"); +module_license("gpl v2");
|
Voltage, current regulators, power capping, power supply
|
32e4978bb920d047fe5de3ea42d176f267c01f63
|
ricardo rivera matos
|
drivers
|
power
|
supply
|
power: supply: cpcap-battery: implement capacity reporting
|
calculate percentage using charge_full value provided.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
implement capacity reporting
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['power ', 'supply', 'cpcap-battery']
|
['c']
| 1
| 12
| 1
|
--- diff --git a/drivers/power/supply/cpcap-battery.c b/drivers/power/supply/cpcap-battery.c --- a/drivers/power/supply/cpcap-battery.c +++ b/drivers/power/supply/cpcap-battery.c + power_supply_prop_capacity, - struct cpcap_battery_state_data *latest, *previous; + struct cpcap_battery_state_data *latest, *previous, *empty; + case power_supply_prop_capacity: + empty = cpcap_battery_get_empty(ddata); + if (!empty->voltage || !ddata->charge_full) + return -enodata; + /* (ddata->charge_full / 200) is needed for rounding */ + val->intval = empty->counter_uah - latest->counter_uah + + ddata->charge_full / 200; + val->intval = clamp(val->intval, 0, ddata->charge_full); + val->intval = val->intval * 100 / ddata->charge_full; + break;
|
Voltage, current regulators, power capping, power supply
|
1e64926c5dd978ae444d127b1414e6682b63733f
|
arthur demchenkov
|
drivers
|
power
|
supply
|
regulator: qcom-labibb: switch voltage ops from linear_range to linear
|
the lab and ibb regulator have just one range and it is useless to use linear_range ops, as these are used to express multiple linear ranges.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
really implement qualcomm lab/ibb regulators
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['regulator ']
|
['c']
| 1
| 6
| 10
|
--- diff --git a/drivers/regulator/qcom-labibb-regulator.c b/drivers/regulator/qcom-labibb-regulator.c --- a/drivers/regulator/qcom-labibb-regulator.c +++ b/drivers/regulator/qcom-labibb-regulator.c - .list_voltage = regulator_list_voltage_linear_range, - .map_voltage = regulator_map_voltage_linear_range, + .list_voltage = regulator_list_voltage_linear, + .map_voltage = regulator_map_voltage_linear, - .linear_ranges = (struct linear_range[]) { - regulator_linear_range(4600000, 0, 15, 100000), - }, - .n_linear_ranges = 1, + .min_uv = 4600000, + .uv_step = 100000, - .linear_ranges = (struct linear_range[]) { - regulator_linear_range(1400000, 0, 63, 100000), - }, - .n_linear_ranges = 1, + .min_uv = 1400000, + .uv_step = 100000,
|
Voltage, current regulators, power capping, power supply
|
9a12eb704ea27826ece4414cb8822388ec54883c
|
angelogioacchino del regno
|
drivers
|
regulator
| |
regulator: qcom-labibb: implement current limiting
|
lab and ibb regulators can be current-limited by setting the appropriate registers, but this operation is granted only after sending an unlock code for secure access.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
really implement qualcomm lab/ibb regulators
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['regulator ']
|
['c']
| 1
| 92
| 0
|
- lab (pos): 200-1600ma, with 200ma per step (8 steps), - ibb (neg): 0-1550ma, with 50ma per step (32 steps). --- diff --git a/drivers/regulator/qcom-labibb-regulator.c b/drivers/regulator/qcom-labibb-regulator.c --- a/drivers/regulator/qcom-labibb-regulator.c +++ b/drivers/regulator/qcom-labibb-regulator.c +#define reg_labibb_current_limit 0x4b + #define lab_current_limit_mask genmask(2, 0) + #define ibb_current_limit_mask genmask(4, 0) + #define lab_current_limit_override_en bit(3) + #define labibb_current_limit_en bit(7) + +#define reg_labibb_sec_access 0xd0 + #define labibb_sec_unlock_code 0xa5 + +struct labibb_current_limits { + u32 ua_min; + u32 ua_step; + u8 ovr_val; +}; + + struct labibb_current_limits ua_limits; +static int qcom_labibb_set_current_limit(struct regulator_dev *rdev, + int min_ua, int max_ua) +{ + struct labibb_regulator *vreg = rdev_get_drvdata(rdev); + struct regulator_desc *desc = &vreg->desc; + struct labibb_current_limits *lim = &vreg->ua_limits; + u32 mask, val; + int i, ret, sel = -1; + + if (min_ua < lim->ua_min || max_ua < lim->ua_min) + return -einval; + + for (i = 0; i < desc->n_current_limits; i++) { + int ua_limit = (lim->ua_step * i) + lim->ua_min; + + if (max_ua >= ua_limit && min_ua <= ua_limit) + sel = i; + } + if (sel < 0) + return -einval; + + /* current limit setting needs secure access */ + ret = regmap_write(vreg->regmap, vreg->base + reg_labibb_sec_access, + labibb_sec_unlock_code); + if (ret) + return ret; + + mask = desc->csel_mask | lim->ovr_val; + mask |= labibb_current_limit_en; + val = (u32)sel | lim->ovr_val; + val |= labibb_current_limit_en; + + return regmap_update_bits(vreg->regmap, desc->csel_reg, mask, val); +} + +static int qcom_labibb_get_current_limit(struct regulator_dev *rdev) +{ + struct labibb_regulator *vreg = rdev_get_drvdata(rdev); + struct regulator_desc *desc = &vreg->desc; + struct labibb_current_limits *lim = &vreg->ua_limits; + unsigned int cur_step; + int ret; + + ret = regmap_read(vreg->regmap, desc->csel_reg, &cur_step); + if (ret) + return ret; + cur_step &= desc->csel_mask; + + return (cur_step * lim->ua_step) + lim->ua_min; +} + + .set_current_limit = qcom_labibb_set_current_limit, + .get_current_limit = qcom_labibb_get_current_limit, + .csel_reg = (pmi8998_lab_reg_base + reg_labibb_current_limit), + .csel_mask = lab_current_limit_mask, + .n_current_limits = 8, + .csel_reg = (pmi8998_ibb_reg_base + reg_labibb_current_limit), + .csel_mask = ibb_current_limit_mask, + .n_current_limits = 32, + switch (vreg->type) { + case qcom_lab_type: + /* lab limits: 200-1600ma */ + vreg->ua_limits.ua_min = 200000; + vreg->ua_limits.ua_step = 200000; + vreg->ua_limits.ovr_val = lab_current_limit_override_en; + break; + case qcom_ibb_type: + /* ibb limits: 0-1550ma */ + vreg->ua_limits.ua_min = 0; + vreg->ua_limits.ua_step = 50000; + vreg->ua_limits.ovr_val = 0; /* no override bit */ + break; + default: + return -einval; + } +
|
Voltage, current regulators, power capping, power supply
|
8056704ba948c1c54c7a67d78a8399a749f2d04b
|
angelogioacchino del regno
|
drivers
|
regulator
| |
regulator: qcom-labibb: implement pull-down, softstart, active discharge
|
soft start is required to avoid inrush current during lab ramp-up and ibb ramp-down, protecting connected hardware to which we supply voltage.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
really implement qualcomm lab/ibb regulators
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['regulator ']
|
['c']
| 1
| 94
| 0
|
--- diff --git a/drivers/regulator/qcom-labibb-regulator.c b/drivers/regulator/qcom-labibb-regulator.c --- a/drivers/regulator/qcom-labibb-regulator.c +++ b/drivers/regulator/qcom-labibb-regulator.c +#define reg_labibb_pd_ctl 0x47 + #define lab_pd_ctl_mask genmask(1, 0) + #define ibb_pd_ctl_mask (bit(0) | bit(7)) + #define lab_pd_ctl_strong_pull bit(0) + #define ibb_pd_ctl_half_strength bit(0) + #define ibb_pd_ctl_en bit(7) + +#define reg_ibb_pwrup_pwrdn_ctl_1 0x58 + #define ibb_ctl_1_discharge_en bit(2) + +#define reg_labibb_soft_start_ctl 0x5f + u8 dischg_sel; + u8 soft_start_sel; +static int qcom_labibb_set_soft_start(struct regulator_dev *rdev) +{ + struct labibb_regulator *vreg = rdev_get_drvdata(rdev); + u32 val = 0; + + if (vreg->type == qcom_ibb_type) + val = vreg->dischg_sel; + else + val = vreg->soft_start_sel; + + return regmap_write(rdev->regmap, rdev->desc->soft_start_reg, val); +} + +static int qcom_labibb_get_table_sel(const int *table, int sz, u32 value) +{ + int i; + + for (i = 0; i < sz; i++) + if (table[i] == value) + return i; + return -einval; +} + +/* ibb discharge resistor values in kohms */ +static const int dischg_resistor_values[] = { 300, 64, 32, 16 }; + +/* soft start time in microseconds */ +static const int soft_start_values[] = { 200, 400, 600, 800 }; + +static int qcom_labibb_of_parse_cb(struct device_node *np, + const struct regulator_desc *desc, + struct regulator_config *config) +{ + struct labibb_regulator *vreg = config->driver_data; + u32 dischg_kohms, soft_start_time; + int ret; + + ret = of_property_read_u32(np, "qcom,discharge-resistor-kohms", + &dischg_kohms); + if (ret) + dischg_kohms = 300; + + ret = qcom_labibb_get_table_sel(dischg_resistor_values, + array_size(dischg_resistor_values), + dischg_kohms); + if (ret < 0) + return ret; + vreg->dischg_sel = (u8)ret; + + ret = of_property_read_u32(np, "qcom,soft-start-us", + &soft_start_time); + if (ret) + soft_start_time = 200; + + ret = qcom_labibb_get_table_sel(soft_start_values, + array_size(soft_start_values), + soft_start_time); + if (ret < 0) + return ret; + vreg->soft_start_sel = (u8)ret; + + return 0; +} + + .set_active_discharge = regulator_set_active_discharge_regmap, + .set_pull_down = regulator_set_pull_down_regmap, + .set_soft_start = qcom_labibb_set_soft_start, + .soft_start_reg = (pmi8998_lab_reg_base + reg_labibb_soft_start_ctl), + .pull_down_reg = (pmi8998_lab_reg_base + reg_labibb_pd_ctl), + .pull_down_mask = lab_pd_ctl_mask, + .pull_down_val_on = lab_pd_ctl_strong_pull, + .of_parse_cb = qcom_labibb_of_parse_cb, + .soft_start_reg = (pmi8998_ibb_reg_base + reg_labibb_soft_start_ctl), + .active_discharge_off = 0, + .active_discharge_on = ibb_ctl_1_discharge_en, + .active_discharge_mask = ibb_ctl_1_discharge_en, + .active_discharge_reg = (pmi8998_ibb_reg_base + reg_ibb_pwrup_pwrdn_ctl_1), + .pull_down_reg = (pmi8998_ibb_reg_base + reg_labibb_pd_ctl), + .pull_down_mask = ibb_pd_ctl_mask, + .pull_down_val_on = ibb_pd_ctl_half_strength | ibb_pd_ctl_en, + .of_parse_cb = qcom_labibb_of_parse_cb,
|
Voltage, current regulators, power capping, power supply
|
3bc7cb99fb6eafae5a40bf71ded444df70a425f7
|
angelogioacchino del regno
|
drivers
|
regulator
| |
regulator: qcom-labibb: implement short-circuit and over-current irqs
|
short-circuit protection (scp) and over-current protection (ocp) are very important for regulators like lab and ibb, which are designed to provide from very small to relatively big amounts of current to the device (normally, a display).
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
really implement qualcomm lab/ibb regulators
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['regulator ']
|
['c']
| 1
| 515
| 3
|
--- diff --git a/drivers/regulator/qcom-labibb-regulator.c b/drivers/regulator/qcom-labibb-regulator.c --- a/drivers/regulator/qcom-labibb-regulator.c +++ b/drivers/regulator/qcom-labibb-regulator.c +#define pmi8998_ibb_lab_reg_offset 0x200 + #define labibb_status1_sc_bit bit(6) + #define labibb_status1_vreg_ok_bit bit(7) + +#define reg_labibb_int_set_type 0x11 +#define reg_labibb_int_polarity_high 0x12 +#define reg_labibb_int_polarity_low 0x13 +#define reg_labibb_int_latched_clr 0x14 +#define reg_labibb_int_en_set 0x15 +#define reg_labibb_int_en_clr 0x16 + #define labibb_int_vreg_ok bit(0) + #define labibb_int_vreg_type_level 0 -#define labibb_status1_vreg_ok_bit bit(7) -#define labibb_control_enable bit(7) + #define labibb_control_enable bit(7) +#define ocp_recovery_interval_ms 500 +#define sc_recovery_interval_ms 250 +#define labibb_max_ocp_count 4 +#define labibb_max_sc_count 3 +#define labibb_max_fatal_count 2 + struct delayed_work ocp_recovery_work; + struct delayed_work sc_recovery_work; + int sc_irq; + int sc_count; + int ocp_irq; + int ocp_irq_count; + int fatal_count; +static int qcom_labibb_ocp_hw_enable(struct regulator_dev *rdev) +{ + struct labibb_regulator *vreg = rdev_get_drvdata(rdev); + int ret; + + /* clear irq latch status to avoid spurious event */ + ret = regmap_update_bits(rdev->regmap, + vreg->base + reg_labibb_int_latched_clr, + labibb_int_vreg_ok, 1); + if (ret) + return ret; + + /* enable ocp hw interrupt */ + return regmap_update_bits(rdev->regmap, + vreg->base + reg_labibb_int_en_set, + labibb_int_vreg_ok, 1); +} + +static int qcom_labibb_ocp_hw_disable(struct regulator_dev *rdev) +{ + struct labibb_regulator *vreg = rdev_get_drvdata(rdev); + + return regmap_update_bits(rdev->regmap, + vreg->base + reg_labibb_int_en_clr, + labibb_int_vreg_ok, 1); +} + +/** + * qcom_labibb_check_ocp_status - check the over-current protection status + * @vreg: main driver structure + * + * this function checks the status1 register for the vreg_ok bit: if it is + * set, then there is no over-current event. + * + * returns: zero if there is no over-current, 1 if in over-current or + * negative number for error + */ +static int qcom_labibb_check_ocp_status(struct labibb_regulator *vreg) +{ + u32 cur_status; + int ret; + + ret = regmap_read(vreg->rdev->regmap, vreg->base + reg_labibb_status1, + &cur_status); + if (ret) + return ret; + + return !(cur_status & labibb_status1_vreg_ok_bit); +} + +/** + * qcom_labibb_ocp_recovery_worker - handle ocp event + * @work: ocp work structure + * + * this is the worker function to handle the over current protection + * hardware event; this will check if the hardware is still + * signaling an over-current condition and will eventually stop + * the regulator if such condition is still signaled after + * labibb_max_ocp_count times. + * + * if the driver that is consuming the regulator did not take action + * for the ocp condition, or the hardware did not stabilize, a cut + * of the lab and ibb regulators will be forced (regulators will be + * disabled). + * + * as last, if the writes to shut down the lab/ibb regulators fail + * for more than labibb_max_fatal_count, then a kernel panic will be + * triggered, as a last resort to protect the hardware from burning; + * this, however, is expected to never happen, but this is kept to + * try to further ensure that we protect the hardware at all costs. + */ +static void qcom_labibb_ocp_recovery_worker(struct work_struct *work) +{ + struct labibb_regulator *vreg; + const struct regulator_ops *ops; + int ret; + + vreg = container_of(work, struct labibb_regulator, + ocp_recovery_work.work); + ops = vreg->rdev->desc->ops; + + if (vreg->ocp_irq_count >= labibb_max_ocp_count) { + /* + * if we tried to disable the regulator multiple times but + * we kept failing, there's only one last hope to save our + * hardware from the death: raise a kernel bug, reboot and + * hope that the bootloader kindly saves us. this, though + * is done only as paranoid checking, because failing the + * regmap write to disable the vreg is almost impossible, + * since we got here after multiple regmap r/w. + */ + bug_on(vreg->fatal_count > labibb_max_fatal_count); + dev_err(&vreg->rdev->dev, "labibb: critical: disabling regulator "); + + /* disable the regulator immediately to avoid damage */ + ret = ops->disable(vreg->rdev); + if (ret) { + vreg->fatal_count++; + goto reschedule; + } + enable_irq(vreg->ocp_irq); + vreg->fatal_count = 0; + return; + } + + ret = qcom_labibb_check_ocp_status(vreg); + if (ret != 0) { + vreg->ocp_irq_count++; + goto reschedule; + } + + ret = qcom_labibb_ocp_hw_enable(vreg->rdev); + if (ret) { + /* we cannot trust it without ocp enabled. */ + dev_err(vreg->dev, "cannot enable ocp irq "); + vreg->ocp_irq_count++; + goto reschedule; + } + + enable_irq(vreg->ocp_irq); + /* everything went fine: reset the ocp count! */ + vreg->ocp_irq_count = 0; + return; + +reschedule: + mod_delayed_work(system_wq, &vreg->ocp_recovery_work, + msecs_to_jiffies(ocp_recovery_interval_ms)); +} + +/** + * qcom_labibb_ocp_isr - interrupt routine for overcurrent protection + * @irq: interrupt number + * @chip: main driver structure + * + * over current protection (ocp) will signal to the client driver + * that an over-current event has happened and then will schedule + * a recovery worker. + * + * disabling and eventually re-enabling the regulator is expected + * to be done by the driver, as some hardware may be triggering an + * over-current condition only at first initialization or it may + * be expected only for a very brief amount of time, after which + * the attached hardware may be expected to stabilize its current + * draw. + * + * returns: irq_handled for success or irq_none for failure. + */ +static irqreturn_t qcom_labibb_ocp_isr(int irq, void *chip) +{ + struct labibb_regulator *vreg = chip; + const struct regulator_ops *ops = vreg->rdev->desc->ops; + int ret; + + /* if the regulator is not enabled, this is a fake event */ + if (!ops->is_enabled(vreg->rdev)) + return 0; + + /* if we tried to recover for too many times it's not getting better */ + if (vreg->ocp_irq_count > labibb_max_ocp_count) + return irq_none; + + /* + * if we (unlikely) can't read this register, to prevent hardware + * damage at all costs, we assume that the overcurrent event was + * real; moreover, if the status register is not signaling ocp, + * it was a spurious event, so it's all ok. + */ + ret = qcom_labibb_check_ocp_status(vreg); + if (ret == 0) { + vreg->ocp_irq_count = 0; + goto end; + } + vreg->ocp_irq_count++; + + /* + * disable the interrupt temporarily, or it will fire continuously; + * we will re-enable it in the recovery worker function. + */ + disable_irq(irq); + + /* warn the user for overcurrent */ + dev_warn(vreg->dev, "over-current interrupt fired! "); + + /* disable the interrupt to avoid hogging */ + ret = qcom_labibb_ocp_hw_disable(vreg->rdev); + if (ret) + goto end; + + /* signal overcurrent event to drivers */ + regulator_notifier_call_chain(vreg->rdev, + regulator_event_over_current, null); + +end: + /* schedule the recovery work */ + schedule_delayed_work(&vreg->ocp_recovery_work, + msecs_to_jiffies(ocp_recovery_interval_ms)); + if (ret) + return irq_none; + + return irq_handled; +} + +static int qcom_labibb_set_ocp(struct regulator_dev *rdev) +{ + struct labibb_regulator *vreg = rdev_get_drvdata(rdev); + char *ocp_irq_name; + u32 irq_flags = irqf_oneshot; + int irq_trig_low, ret; + + /* if there is no ocp interrupt, there's nothing to set */ + if (vreg->ocp_irq <= 0) + return -einval; + + ocp_irq_name = devm_kasprintf(vreg->dev, gfp_kernel, "%s-over-current", + vreg->desc.name); + if (!ocp_irq_name) + return -enomem; + + /* irq polarities - lab: trigger-low, ibb: trigger-high */ + switch (vreg->type) { + case qcom_lab_type: + irq_flags |= irqf_trigger_low; + irq_trig_low = 1; + break; + case qcom_ibb_type: + irq_flags |= irqf_trigger_high; + irq_trig_low = 0; + break; + default: + return -einval; + } + + /* activate ocp hw level interrupt */ + ret = regmap_update_bits(rdev->regmap, + vreg->base + reg_labibb_int_set_type, + labibb_int_vreg_ok, + labibb_int_vreg_type_level); + if (ret) + return ret; + + /* set ocp interrupt polarity */ + ret = regmap_update_bits(rdev->regmap, + vreg->base + reg_labibb_int_polarity_high, + labibb_int_vreg_ok, !irq_trig_low); + if (ret) + return ret; + ret = regmap_update_bits(rdev->regmap, + vreg->base + reg_labibb_int_polarity_low, + labibb_int_vreg_ok, irq_trig_low); + if (ret) + return ret; + + ret = qcom_labibb_ocp_hw_enable(rdev); + if (ret) + return ret; + + return devm_request_threaded_irq(vreg->dev, vreg->ocp_irq, null, + qcom_labibb_ocp_isr, irq_flags, + ocp_irq_name, vreg); +} + +/** + * qcom_labibb_check_sc_status - check the short circuit protection status + * @vreg: main driver structure + * + * this function checks the status1 register on both lab and ibb regulators + * for the shortcircuit bit: if it is set on *any* of them, then we have + * experienced a short-circuit event. + * + * returns: zero if there is no short-circuit, 1 if in short-circuit or + * negative number for error + */ +static int qcom_labibb_check_sc_status(struct labibb_regulator *vreg) +{ + u32 ibb_status, ibb_reg, lab_status, lab_reg; + int ret; + + /* we have to work on both regulators due to pbs... */ + lab_reg = ibb_reg = vreg->base + reg_labibb_status1; + if (vreg->type == qcom_lab_type) + ibb_reg -= pmi8998_ibb_lab_reg_offset; + else + lab_reg += pmi8998_ibb_lab_reg_offset; + + ret = regmap_read(vreg->rdev->regmap, lab_reg, &lab_status); + if (ret) + return ret; + ret = regmap_read(vreg->rdev->regmap, ibb_reg, &ibb_status); + if (ret) + return ret; + + return !!(lab_status & labibb_status1_sc_bit) || + !!(ibb_status & labibb_status1_sc_bit); +} + +/** + * qcom_labibb_sc_recovery_worker - handle short circuit event + * @work: sc work structure + * + * this is the worker function to handle the short circuit protection + * hardware event; this will check if the hardware is still + * signaling a short-circuit condition and will eventually never + * re-enable the regulator if such condition is still signaled after + * labibb_max_sc_count times. + * + * if the driver that is consuming the regulator did not take action + * for the sc condition, or the hardware did not stabilize, this + * worker will stop rescheduling, leaving the regulators disabled + * as already done by the portable batch system (pbs). + * + * returns: irq_handled for success or irq_none for failure. + */ +static void qcom_labibb_sc_recovery_worker(struct work_struct *work) +{ + struct labibb_regulator *vreg; + const struct regulator_ops *ops; + u32 lab_reg, ibb_reg, lab_val, ibb_val, val; + bool pbs_cut = false; + int i, sc, ret; + + vreg = container_of(work, struct labibb_regulator, + sc_recovery_work.work); + ops = vreg->rdev->desc->ops; + + /* + * if we tried to check the regulator status multiple times but we + * kept failing, then just bail out, as the portable batch system + * (pbs) will disable the vregs for us, preventing hardware damage. + */ + if (vreg->fatal_count > labibb_max_fatal_count) + return; + + /* too many short-circuit events. throw in the towel. */ + if (vreg->sc_count > labibb_max_sc_count) + return; + + /* + * the portable batch system (pbs) automatically disables lab + * and ibb when a short-circuit event is detected, so we have to + * check and work on both of them at the same time. + */ + lab_reg = ibb_reg = vreg->base + reg_labibb_enable_ctl; + if (vreg->type == qcom_lab_type) + ibb_reg -= pmi8998_ibb_lab_reg_offset; + else + lab_reg += pmi8998_ibb_lab_reg_offset; + + sc = qcom_labibb_check_sc_status(vreg); + if (sc) + goto reschedule; + + for (i = 0; i < labibb_max_sc_count; i++) { + ret = regmap_read(vreg->regmap, lab_reg, &lab_val); + if (ret) { + vreg->fatal_count++; + goto reschedule; + } + + ret = regmap_read(vreg->regmap, ibb_reg, &ibb_val); + if (ret) { + vreg->fatal_count++; + goto reschedule; + } + val = lab_val & ibb_val; + + if (!(val & labibb_control_enable)) { + pbs_cut = true; + break; + } + usleep_range(5000, 6000); + } + if (pbs_cut) + goto reschedule; + + + /* + * if we have reached this point, we either have successfully + * recovered from the sc condition or we had a spurious sc irq, + * which means that we can re-enable the regulators, if they + * have ever been disabled by the pbs. + */ + ret = ops->enable(vreg->rdev); + if (ret) + goto reschedule; + + /* everything went fine: reset the ocp count! */ + vreg->sc_count = 0; + enable_irq(vreg->sc_irq); + return; + +reschedule: + /* + * now that we have done basic handling of the short-circuit, + * reschedule this worker in the regular system workqueue, as + * taking action is not truly urgent anymore. + */ + vreg->sc_count++; + mod_delayed_work(system_wq, &vreg->sc_recovery_work, + msecs_to_jiffies(sc_recovery_interval_ms)); +} + +/** + * qcom_labibb_sc_isr - interrupt routine for short circuit protection + * @irq: interrupt number + * @chip: main driver structure + * + * short circuit protection (scp) will signal to the client driver + * that a regulation-out event has happened and then will schedule + * a recovery worker. + * + * the lab and ibb regulators will be automatically disabled by the + * portable batch system (pbs) and they will be enabled again by + * the worker function if the hardware stops signaling the short + * circuit event. + * + * returns: irq_handled for success or irq_none for failure. + */ +static irqreturn_t qcom_labibb_sc_isr(int irq, void *chip) +{ + struct labibb_regulator *vreg = chip; + + if (vreg->sc_count > labibb_max_sc_count) + return irq_none; + + /* warn the user for short circuit */ + dev_warn(vreg->dev, "short-circuit interrupt fired! "); + + /* + * disable the interrupt temporarily, or it will fire continuously; + * we will re-enable it in the recovery worker function. + */ + disable_irq(irq); + + /* signal out of regulation event to drivers */ + regulator_notifier_call_chain(vreg->rdev, + regulator_event_regulation_out, null); + + /* schedule the short-circuit handling as high-priority work */ + mod_delayed_work(system_highpri_wq, &vreg->sc_recovery_work, + msecs_to_jiffies(sc_recovery_interval_ms)); + return irq_handled; +} + + + .set_over_current_protection = qcom_labibb_set_ocp, - + struct device_node *reg_node; + char *sc_irq_name; + int irq = 0; + sc_irq_name = devm_kasprintf(dev, gfp_kernel, + "%s-short-circuit", + reg_data->name); + if (!sc_irq_name) + return -enomem; + + reg_node = of_get_child_by_name(pdev->dev.of_node, + reg_data->name); + if (!reg_node) + return -einval; + + /* the short circuit interrupt is critical */ + irq = of_irq_get_byname(reg_node, "sc-err"); + if (irq <= 0) { + if (irq == 0) + irq = -einval; + + return dev_err_probe(vreg->dev, irq, + "short-circuit irq not found. "); + } + vreg->sc_irq = irq; + + /* overcurrent protection irq is optional */ + irq = of_irq_get_byname(reg_node, "ocp"); + vreg->ocp_irq = irq; + vreg->ocp_irq_count = 0; + of_node_put(reg_node); + + init_delayed_work(&vreg->sc_recovery_work, + qcom_labibb_sc_recovery_worker); + + if (vreg->ocp_irq > 0) + init_delayed_work(&vreg->ocp_recovery_work, + qcom_labibb_ocp_recovery_worker); + + ret = devm_request_threaded_irq(vreg->dev, vreg->sc_irq, null, + qcom_labibb_sc_isr, + irqf_oneshot | + irqf_trigger_rising, + sc_irq_name, vreg); + if (ret) + return ret;
|
Voltage, current regulators, power capping, power supply
|
390af53e04114f790d60b63802a4de9d815ade03
|
angelogioacchino del regno
|
drivers
|
regulator
| |
arm64: dts: pmi8998: add the right interrupts for lab/ibb scp and ocp
|
in commit 208921bae696 ("arm64: dts: qcom: pmi8998: add nodes for lab and ibb regulators") bindings for the lab/ibb regulators were added to the pmi8998 dt, but the original committer has never specified what the interrupts were for. lab and ibb regulators provide two interrupts, sc-err (short circuit error) and vreg-ok but, in that commit, the regulators were provided with two different types of interrupts; specifically, ibb had the sc-err interrupt, while lab had the vreg-ok one, none of which were (luckily) used, since the driver didn't actually use these at all. assuming that the original intention was to have the sc irq in both lab and ibb, as per the names appearing in documentation, fix the scp interrupt.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
really implement qualcomm lab/ibb regulators
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['regulator ']
|
['dtsi']
| 1
| 6
| 2
|
--- diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi - interrupts = <0x3 0xdc 0x2 irq_type_edge_rising>; + interrupts = <0x3 0xdc 0x2 irq_type_edge_rising>, + <0x3 0xdc 0x0 irq_type_level_high>; + interrupt-names = "sc-err", "ocp"; - interrupts = <0x3 0xde 0x0 irq_type_edge_rising>; + interrupts = <0x3 0xde 0x1 irq_type_edge_rising>, + <0x3 0xde 0x0 irq_type_level_low>; + interrupt-names = "sc-err", "ocp";
|
Voltage, current regulators, power capping, power supply
|
6243905da788cc75d920864fd087b334bb68bb7c
|
angelogioacchino del regno
|
arch
|
arm64
|
boot, dts, qcom
|
regulator: add regulator driver for atc260x pmics
|
add support for the dc-dc converters and ldo regulators found in the atc2603c and atc2609a chip variants of the actions semi atc260x family of pmics.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add regulator driver for atc260x pmics
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['regulator ']
|
['kconfig', 'c', 'makefile']
| 3
| 548
| 0
|
--- diff --git a/drivers/regulator/kconfig b/drivers/regulator/kconfig --- a/drivers/regulator/kconfig +++ b/drivers/regulator/kconfig +config regulator_atc260x + tristate "actions semi atc260x pmic regulators" + depends on mfd_atc260x + help + this driver provides support for the voltage regulators on the + atc260x pmics. this will enable support for all the software + controllable dcdc/ldo regulators. + diff --git a/drivers/regulator/makefile b/drivers/regulator/makefile --- a/drivers/regulator/makefile +++ b/drivers/regulator/makefile +obj-$(config_regulator_atc260x) += atc260x-regulator.o diff --git a/drivers/regulator/atc260x-regulator.c b/drivers/regulator/atc260x-regulator.c --- /dev/null +++ b/drivers/regulator/atc260x-regulator.c +// spdx-license-identifier: gpl-2.0+ +// +// regulator driver for atc260x pmics +// +// copyright (c) 2019 manivannan sadhasivam <manivannan.sadhasivam@linaro.org> +// copyright (c) 2020 cristian ciocaltea <cristian.ciocaltea@gmail.com> + +#include <linux/mfd/atc260x/core.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regmap.h> +#include <linux/regulator/driver.h> + +struct atc260x_regulator_data { + int voltage_time_dcdc; + int voltage_time_ldo; +}; + +static const struct linear_range atc2603c_dcdc_voltage_ranges[] = { + regulator_linear_range(1300000, 0, 13, 50000), + regulator_linear_range(1950000, 14, 15, 100000), +}; + +static const struct linear_range atc2609a_dcdc_voltage_ranges[] = { + regulator_linear_range(600000, 0, 127, 6250), + regulator_linear_range(1400000, 128, 232, 25000), +}; + +static const struct linear_range atc2609a_ldo_voltage_ranges0[] = { + regulator_linear_range(700000, 0, 15, 100000), + regulator_linear_range(2100000, 16, 28, 100000), +}; + +static const struct linear_range atc2609a_ldo_voltage_ranges1[] = { + regulator_linear_range(850000, 0, 15, 100000), + regulator_linear_range(2100000, 16, 27, 100000), +}; + +static const unsigned int atc260x_ldo_voltage_range_sel[] = { + 0x0, 0x1, +}; + +static int atc260x_dcdc_set_voltage_time_sel(struct regulator_dev *rdev, + unsigned int old_selector, + unsigned int new_selector) +{ + struct atc260x_regulator_data *data = rdev_get_drvdata(rdev); + + if (new_selector > old_selector) + return data->voltage_time_dcdc; + + return 0; +} + +static int atc260x_ldo_set_voltage_time_sel(struct regulator_dev *rdev, + unsigned int old_selector, + unsigned int new_selector) +{ + struct atc260x_regulator_data *data = rdev_get_drvdata(rdev); + + if (new_selector > old_selector) + return data->voltage_time_ldo; + + return 0; +} + +static const struct regulator_ops atc260x_dcdc_ops = { + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .list_voltage = regulator_list_voltage_linear, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_time_sel = atc260x_dcdc_set_voltage_time_sel, +}; + +static const struct regulator_ops atc260x_ldo_ops = { + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .list_voltage = regulator_list_voltage_linear, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_time_sel = atc260x_ldo_set_voltage_time_sel, +}; + +static const struct regulator_ops atc260x_ldo_bypass_ops = { + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .list_voltage = regulator_list_voltage_linear, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_time_sel = atc260x_ldo_set_voltage_time_sel, + .set_bypass = regulator_set_bypass_regmap, + .get_bypass = regulator_get_bypass_regmap, +}; + +static const struct regulator_ops atc260x_ldo_bypass_discharge_ops = { + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .list_voltage = regulator_list_voltage_linear, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_time_sel = atc260x_ldo_set_voltage_time_sel, + .set_bypass = regulator_set_bypass_regmap, + .get_bypass = regulator_get_bypass_regmap, + .set_active_discharge = regulator_set_active_discharge_regmap, +}; + +static const struct regulator_ops atc260x_dcdc_range_ops = { + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .list_voltage = regulator_list_voltage_linear_range, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_time_sel = atc260x_dcdc_set_voltage_time_sel, +}; + +static const struct regulator_ops atc260x_ldo_range_pick_ops = { + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .list_voltage = regulator_list_voltage_pickable_linear_range, + .set_voltage_sel = regulator_set_voltage_sel_pickable_regmap, + .get_voltage_sel = regulator_get_voltage_sel_pickable_regmap, + .set_voltage_time_sel = atc260x_ldo_set_voltage_time_sel, +}; + +static const struct regulator_ops atc260x_dcdc_fixed_ops = { + .list_voltage = regulator_list_voltage_linear, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_time_sel = atc260x_dcdc_set_voltage_time_sel, +}; + +static const struct regulator_ops atc260x_ldo_fixed_ops = { + .list_voltage = regulator_list_voltage_linear, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_time_sel = atc260x_ldo_set_voltage_time_sel, +}; + +static const struct regulator_ops atc260x_no_ops = { +}; + +/* + * note ldo8 is not documented in datasheet (v2.4), but supported + * in the vendor's driver implementation (xapp-le-kernel). + */ +enum atc2603c_reg_ids { + atc2603c_id_dcdc1, + atc2603c_id_dcdc2, + atc2603c_id_dcdc3, + atc2603c_id_ldo1, + atc2603c_id_ldo2, + atc2603c_id_ldo3, + atc2603c_id_ldo5, + atc2603c_id_ldo6, + atc2603c_id_ldo7, + atc2603c_id_ldo8, + atc2603c_id_ldo11, + atc2603c_id_ldo12, + atc2603c_id_switchldo1, + atc2603c_id_max, +}; + +#define atc2603c_reg_desc_dcdc(num, min, step, n_volt, vsel_h, vsel_l) { \ + .name = "dcdc"#num, \ + .supply_name = "dcdc"#num, \ + .of_match = of_match_ptr("dcdc"#num), \ + .regulators_node = of_match_ptr("regulators"), \ + .id = atc2603c_id_dcdc##num, \ + .ops = &atc260x_dcdc_ops, \ + .type = regulator_voltage, \ + .min_uv = min, \ + .uv_step = step, \ + .n_voltages = n_volt, \ + .vsel_reg = atc2603c_pmu_dc##num##_ctl0, \ + .vsel_mask = genmask(vsel_h, vsel_l), \ + .enable_reg = atc2603c_pmu_dc##num##_ctl0, \ + .enable_mask = bit(15), \ + .enable_time = 800, \ + .owner = this_module, \ +} + +#define atc2603c_reg_desc_dcdc_range(num, vsel_h, vsel_l) { \ + .name = "dcdc"#num, \ + .supply_name = "dcdc"#num, \ + .of_match = of_match_ptr("dcdc"#num), \ + .regulators_node = of_match_ptr("regulators"), \ + .id = atc2603c_id_dcdc##num, \ + .ops = &atc260x_dcdc_range_ops, \ + .type = regulator_voltage, \ + .n_voltages = 16, \ + .linear_ranges = atc2603c_dcdc_voltage_ranges, \ + .n_linear_ranges = array_size(atc2603c_dcdc_voltage_ranges), \ + .vsel_reg = atc2603c_pmu_dc##num##_ctl0, \ + .vsel_mask = genmask(vsel_h, vsel_l), \ + .enable_reg = atc2603c_pmu_dc##num##_ctl0, \ + .enable_mask = bit(15), \ + .enable_time = 800, \ + .owner = this_module, \ +} + +#define atc2603c_reg_desc_dcdc_fixed(num, min, step, n_volt, vsel_h, vsel_l) { \ + .name = "dcdc"#num, \ + .supply_name = "dcdc"#num, \ + .of_match = of_match_ptr("dcdc"#num), \ + .regulators_node = of_match_ptr("regulators"), \ + .id = atc2603c_id_dcdc##num, \ + .ops = &atc260x_dcdc_fixed_ops, \ + .type = regulator_voltage, \ + .min_uv = min, \ + .uv_step = step, \ + .n_voltages = n_volt, \ + .vsel_reg = atc2603c_pmu_dc##num##_ctl0, \ + .vsel_mask = genmask(vsel_h, vsel_l), \ + .enable_time = 800, \ + .owner = this_module, \ +} + +#define atc2603c_reg_desc_ldo(num, min, step, n_volt, vsel_h, vsel_l) { \ + .name = "ldo"#num, \ + .supply_name = "ldo"#num, \ + .of_match = of_match_ptr("ldo"#num), \ + .regulators_node = of_match_ptr("regulators"), \ + .id = atc2603c_id_ldo##num, \ + .ops = &atc260x_ldo_ops, \ + .type = regulator_voltage, \ + .min_uv = min, \ + .uv_step = step, \ + .n_voltages = n_volt, \ + .vsel_reg = atc2603c_pmu_ldo##num##_ctl, \ + .vsel_mask = genmask(vsel_h, vsel_l), \ + .enable_reg = atc2603c_pmu_ldo##num##_ctl, \ + .enable_mask = bit(0), \ + .enable_time = 2000, \ + .owner = this_module, \ +} + +#define atc2603c_reg_desc_ldo_fixed(num, min, step, n_volt, vsel_h, vsel_l) { \ + .name = "ldo"#num, \ + .supply_name = "ldo"#num, \ + .of_match = of_match_ptr("ldo"#num), \ + .regulators_node = of_match_ptr("regulators"), \ + .id = atc2603c_id_ldo##num, \ + .ops = &atc260x_ldo_fixed_ops, \ + .type = regulator_voltage, \ + .min_uv = min, \ + .uv_step = step, \ + .n_voltages = n_volt, \ + .vsel_reg = atc2603c_pmu_ldo##num##_ctl, \ + .vsel_mask = genmask(vsel_h, vsel_l), \ + .enable_time = 2000, \ + .owner = this_module, \ +} + +#define atc2603c_reg_desc_ldo_noops(num, vfixed) { \ + .name = "ldo"#num, \ + .supply_name = "ldo"#num, \ + .of_match = of_match_ptr("ldo"#num), \ + .regulators_node = of_match_ptr("regulators"), \ + .id = atc2603c_id_ldo##num, \ + .ops = &atc260x_no_ops, \ + .type = regulator_voltage, \ + .fixed_uv = vfixed, \ + .n_voltages = 1, \ + .owner = this_module, \ +} + +#define atc2603c_reg_desc_ldo_switch(num, min, step, n_volt, vsel_h, vsel_l) { \ + .name = "switchldo"#num, \ + .supply_name = "switchldo"#num, \ + .of_match = of_match_ptr("switchldo"#num), \ + .regulators_node = of_match_ptr("regulators"), \ + .id = atc2603c_id_switchldo##num, \ + .ops = &atc260x_ldo_bypass_discharge_ops, \ + .type = regulator_voltage, \ + .min_uv = min, \ + .uv_step = step, \ + .n_voltages = n_volt, \ + .vsel_reg = atc2603c_pmu_switch_ctl, \ + .vsel_mask = genmask(vsel_h, vsel_l), \ + .enable_reg = atc2603c_pmu_switch_ctl, \ + .enable_mask = bit(15), \ + .enable_is_inverted = true, \ + .enable_time = 2000, \ + .bypass_reg = atc2603c_pmu_switch_ctl, \ + .bypass_mask = bit(5), \ + .active_discharge_reg = atc2603c_pmu_switch_ctl, \ + .active_discharge_mask = bit(1), \ + .owner = this_module, \ +} + +static const struct regulator_desc atc2603c_reg[] = { + atc2603c_reg_desc_dcdc_fixed(1, 700000, 25000, 29, 11, 7), + atc2603c_reg_desc_dcdc_range(2, 12, 8), + atc2603c_reg_desc_dcdc_fixed(3, 2600000, 100000, 8, 11, 9), + atc2603c_reg_desc_ldo_fixed(1, 2600000, 100000, 8, 15, 13), + atc2603c_reg_desc_ldo_fixed(2, 2600000, 100000, 8, 15, 13), + atc2603c_reg_desc_ldo_fixed(3, 1500000, 100000, 6, 15, 13), + atc2603c_reg_desc_ldo(5, 2600000, 100000, 8, 15, 13), + atc2603c_reg_desc_ldo_fixed(6, 700000, 25000, 29, 15, 11), + atc2603c_reg_desc_ldo(7, 1500000, 100000, 6, 15, 13), + atc2603c_reg_desc_ldo(8, 2300000, 100000, 11, 15, 12), + atc2603c_reg_desc_ldo_fixed(11, 2600000, 100000, 8, 15, 13), + atc2603c_reg_desc_ldo_noops(12, 1800000), + atc2603c_reg_desc_ldo_switch(1, 3000000, 100000, 4, 4, 3), +}; + +static const struct regulator_desc atc2603c_reg_dcdc2_ver_b = + atc2603c_reg_desc_dcdc(2, 1000000, 50000, 18, 12, 8); + +enum atc2609a_reg_ids { + atc2609a_id_dcdc0, + atc2609a_id_dcdc1, + atc2609a_id_dcdc2, + atc2609a_id_dcdc3, + atc2609a_id_dcdc4, + atc2609a_id_ldo0, + atc2609a_id_ldo1, + atc2609a_id_ldo2, + atc2609a_id_ldo3, + atc2609a_id_ldo4, + atc2609a_id_ldo5, + atc2609a_id_ldo6, + atc2609a_id_ldo7, + atc2609a_id_ldo8, + atc2609a_id_ldo9, + atc2609a_id_max, +}; + +#define atc2609a_reg_desc_dcdc(num, en_bit) { \ + .name = "dcdc"#num, \ + .supply_name = "dcdc"#num, \ + .of_match = of_match_ptr("dcdc"#num), \ + .regulators_node = of_match_ptr("regulators"), \ + .id = atc2609a_id_dcdc##num, \ + .ops = &atc260x_dcdc_ops, \ + .type = regulator_voltage, \ + .min_uv = 600000, \ + .uv_step = 6250, \ + .n_voltages = 256, \ + .vsel_reg = atc2609a_pmu_dc##num##_ctl0, \ + .vsel_mask = genmask(15, 8), \ + .enable_reg = atc2609a_pmu_dc_osc, \ + .enable_mask = bit(en_bit), \ + .enable_time = 800, \ + .owner = this_module, \ +} + +#define atc2609a_reg_desc_dcdc_range(num, en_bit) { \ + .name = "dcdc"#num, \ + .supply_name = "dcdc"#num, \ + .of_match = of_match_ptr("dcdc"#num), \ + .regulators_node = of_match_ptr("regulators"), \ + .id = atc2609a_id_dcdc##num, \ + .ops = &atc260x_dcdc_range_ops, \ + .type = regulator_voltage, \ + .n_voltages = 233, \ + .linear_ranges = atc2609a_dcdc_voltage_ranges, \ + .n_linear_ranges = array_size(atc2609a_dcdc_voltage_ranges), \ + .vsel_reg = atc2609a_pmu_dc##num##_ctl0, \ + .vsel_mask = genmask(15, 8), \ + .enable_reg = atc2609a_pmu_dc_osc, \ + .enable_mask = bit(en_bit), \ + .enable_time = 800, \ + .owner = this_module, \ +} + +#define atc2609a_reg_desc_ldo(num) { \ + .name = "ldo"#num, \ + .supply_name = "ldo"#num, \ + .of_match = of_match_ptr("ldo"#num), \ + .regulators_node = of_match_ptr("regulators"), \ + .id = atc2609a_id_ldo##num, \ + .ops = &atc260x_ldo_ops, \ + .type = regulator_voltage, \ + .min_uv = 700000, \ + .uv_step = 100000, \ + .n_voltages = 16, \ + .vsel_reg = atc2609a_pmu_ldo##num##_ctl0, \ + .vsel_mask = genmask(4, 1), \ + .enable_reg = atc2609a_pmu_ldo##num##_ctl0, \ + .enable_mask = bit(0), \ + .enable_time = 2000, \ + .owner = this_module, \ +} + +#define atc2609a_reg_desc_ldo_bypass(num) { \ + .name = "ldo"#num, \ + .supply_name = "ldo"#num, \ + .of_match = of_match_ptr("ldo"#num), \ + .regulators_node = of_match_ptr("regulators"), \ + .id = atc2609a_id_ldo##num, \ + .ops = &atc260x_ldo_bypass_ops, \ + .type = regulator_voltage, \ + .min_uv = 2300000, \ + .uv_step = 100000, \ + .n_voltages = 12, \ + .vsel_reg = atc2609a_pmu_ldo##num##_ctl0, \ + .vsel_mask = genmask(5, 2), \ + .enable_reg = atc2609a_pmu_ldo##num##_ctl0, \ + .enable_mask = bit(0), \ + .enable_time = 2000, \ + .bypass_reg = atc2609a_pmu_ldo##num##_ctl0, \ + .bypass_mask = bit(1), \ + .owner = this_module, \ +} + +#define atc2609a_reg_desc_ldo_range_pick(num, n_range) { \ + .name = "ldo"#num, \ + .supply_name = "ldo"#num, \ + .of_match = of_match_ptr("ldo"#num), \ + .regulators_node = of_match_ptr("regulators"), \ + .id = atc2609a_id_ldo##num, \ + .ops = &atc260x_ldo_range_pick_ops, \ + .type = regulator_voltage, \ + .linear_ranges = atc2609a_ldo_voltage_ranges##n_range, \ + .n_linear_ranges = array_size(atc2609a_ldo_voltage_ranges##n_range), \ + .vsel_reg = atc2609a_pmu_ldo##num##_ctl0, \ + .vsel_mask = genmask(4, 1), \ + .vsel_range_reg = atc2609a_pmu_ldo##num##_ctl0, \ + .vsel_range_mask = bit(5), \ + .linear_range_selectors = atc260x_ldo_voltage_range_sel, \ + .enable_reg = atc2609a_pmu_ldo##num##_ctl0, \ + .enable_mask = bit(0), \ + .enable_time = 2000, \ + .owner = this_module, \ +} + +#define atc2609a_reg_desc_ldo_fixed(num) { \ + .name = "ldo"#num, \ + .supply_name = "ldo"#num, \ + .of_match = of_match_ptr("ldo"#num), \ + .regulators_node = of_match_ptr("regulators"), \ + .id = atc2609a_id_ldo##num, \ + .ops = &atc260x_ldo_fixed_ops, \ + .type = regulator_voltage, \ + .min_uv = 2600000, \ + .uv_step = 100000, \ + .n_voltages = 8, \ + .vsel_reg = atc2609a_pmu_ldo##num##_ctl, \ + .vsel_mask = genmask(15, 13), \ + .enable_time = 2000, \ + .owner = this_module, \ +} + +static const struct regulator_desc atc2609a_reg[] = { + atc2609a_reg_desc_dcdc(0, 4), + atc2609a_reg_desc_dcdc(1, 5), + atc2609a_reg_desc_dcdc(2, 6), + atc2609a_reg_desc_dcdc_range(3, 7), + atc2609a_reg_desc_dcdc(4, 8), + atc2609a_reg_desc_ldo_bypass(0), + atc2609a_reg_desc_ldo_bypass(1), + atc2609a_reg_desc_ldo_bypass(2), + atc2609a_reg_desc_ldo_range_pick(3, 0), + atc2609a_reg_desc_ldo_range_pick(4, 0), + atc2609a_reg_desc_ldo(5), + atc2609a_reg_desc_ldo_range_pick(6, 1), + atc2609a_reg_desc_ldo_range_pick(7, 0), + atc2609a_reg_desc_ldo_range_pick(8, 0), + atc2609a_reg_desc_ldo_fixed(9), +}; + +static int atc260x_regulator_probe(struct platform_device *pdev) +{ + struct atc260x *atc260x = dev_get_drvdata(pdev->dev.parent); + struct device *dev = atc260x->dev; + struct atc260x_regulator_data *atc260x_data; + struct regulator_config config = {}; + struct regulator_dev *atc260x_rdev; + const struct regulator_desc *regulators; + bool atc2603c_ver_b = false; + int i, nregulators; + + atc260x_data = devm_kzalloc(&pdev->dev, sizeof(*atc260x_data), gfp_kernel); + if (!atc260x_data) + return -enomem; + + atc260x_data->voltage_time_dcdc = 350; + atc260x_data->voltage_time_ldo = 800; + + switch (atc260x->ic_type) { + case atc2603c: + regulators = atc2603c_reg; + nregulators = atc2603c_id_max; + atc2603c_ver_b = atc260x->ic_ver == atc260x_b; + break; + case atc2609a: + atc260x_data->voltage_time_dcdc = 250; + regulators = atc2609a_reg; + nregulators = atc2609a_id_max; + break; + default: + dev_err(dev, "unsupported atc260x id %d ", atc260x->ic_type); + return -einval; + } + + config.dev = dev; + config.regmap = atc260x->regmap; + config.driver_data = atc260x_data; + + /* instantiate the regulators */ + for (i = 0; i < nregulators; i++) { + if (atc2603c_ver_b && regulators[i].id == atc2603c_id_dcdc2) + atc260x_rdev = devm_regulator_register(&pdev->dev, + &atc2603c_reg_dcdc2_ver_b, + &config); + else + atc260x_rdev = devm_regulator_register(&pdev->dev, + ®ulators[i], + &config); + if (is_err(atc260x_rdev)) { + dev_err(dev, "failed to register regulator: %d ", i); + return ptr_err(atc260x_rdev); + } + } + + return 0; +} + +static struct platform_driver atc260x_regulator_driver = { + .probe = atc260x_regulator_probe, + .driver = { + .name = "atc260x-regulator", + }, +}; + +module_platform_driver(atc260x_regulator_driver); + +module_description("regulator driver for atc260x pmics"); +module_author("manivannan sadhasivam <manivannan.sadhasivam@linaro.org>"); +module_author("cristian ciocaltea <cristian.ciocaltea@gmail.com>"); +module_license("gpl");
|
Voltage, current regulators, power capping, power supply
|
3b15ccac161aa61511561fa2a76cd9677563d22f
|
cristian ciocaltea
|
drivers
|
regulator
| |
regulator: regulator driver for the mediatek dvfsrc
|
driver for regulators exposed by the dvfsrc (dynamic voltage and frequency scaling resource collector) found in devices based on mt8183 and newer platforms.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
regulator driver for the mediatek dvfsrc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['regulator ']
|
['kconfig', 'c', 'makefile']
| 3
| 226
| 0
|
--- diff --git a/drivers/regulator/kconfig b/drivers/regulator/kconfig --- a/drivers/regulator/kconfig +++ b/drivers/regulator/kconfig +config regulator_mtk_dvfsrc + tristate "mediatek dvfsrc regulator driver" + depends on mtk_dvfsrc + help + say y here to control regulator by dvfsrc (dynamic voltage + and frequency scaling resource collector). + this driver supports to control regulators via the dvfsrc + of mediatek. it allows for voting on regulator state + between multiple users. + diff --git a/drivers/regulator/makefile b/drivers/regulator/makefile --- a/drivers/regulator/makefile +++ b/drivers/regulator/makefile +obj-$(config_regulator_mtk_dvfsrc) += mtk-dvfsrc-regulator.o diff --git a/drivers/regulator/mtk-dvfsrc-regulator.c b/drivers/regulator/mtk-dvfsrc-regulator.c --- /dev/null +++ b/drivers/regulator/mtk-dvfsrc-regulator.c +// spdx-license-identifier: gpl-2.0 +// +// copyright (c) 2020 mediatek inc. + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of_device.h> +#include <linux/of_platform.h> +#include <linux/regulator/driver.h> +#include <linux/regulator/of_regulator.h> +#include <linux/soc/mediatek/mtk_dvfsrc.h> + +#define dvfsrc_id_vcore 0 +#define dvfsrc_id_vscp 1 + +#define mt_dvfsrc_regular(match, _name, _volt_table) \ +[dvfsrc_id_##_name] = { \ + .desc = { \ + .name = match, \ + .of_match = of_match_ptr(match), \ + .ops = &dvfsrc_vcore_ops, \ + .type = regulator_voltage, \ + .id = dvfsrc_id_##_name, \ + .owner = this_module, \ + .n_voltages = array_size(_volt_table), \ + .volt_table = _volt_table, \ + }, \ +} + +/* + * dvfsrc regulators' information + * + * @desc: standard fields of regulator description. + * @voltage_selector: selector used for get_voltage_sel() and + * set_voltage_sel() callbacks + */ + +struct dvfsrc_regulator { + struct regulator_desc desc; +}; + +/* + * mtk dvfsrc regulators' init data + * + * @size: num of regulators + * @regulator_info: regulator info. + */ +struct dvfsrc_regulator_init_data { + u32 size; + struct dvfsrc_regulator *regulator_info; +}; + +static inline struct device *to_dvfsrc_dev(struct regulator_dev *rdev) +{ + return rdev_get_dev(rdev)->parent; +} + +static int dvfsrc_set_voltage_sel(struct regulator_dev *rdev, + unsigned int selector) +{ + struct device *dvfsrc_dev = to_dvfsrc_dev(rdev); + int id = rdev_get_id(rdev); + + if (id == dvfsrc_id_vcore) + mtk_dvfsrc_send_request(dvfsrc_dev, + mtk_dvfsrc_cmd_vcore_request, + selector); + else if (id == dvfsrc_id_vscp) + mtk_dvfsrc_send_request(dvfsrc_dev, + mtk_dvfsrc_cmd_vscp_request, + selector); + else + return -einval; + + return 0; +} + +static int dvfsrc_get_voltage_sel(struct regulator_dev *rdev) +{ + struct device *dvfsrc_dev = to_dvfsrc_dev(rdev); + int id = rdev_get_id(rdev); + int val, ret; + + if (id == dvfsrc_id_vcore) + ret = mtk_dvfsrc_query_info(dvfsrc_dev, + mtk_dvfsrc_cmd_vcore_level_query, + &val); + else if (id == dvfsrc_id_vscp) + ret = mtk_dvfsrc_query_info(dvfsrc_dev, + mtk_dvfsrc_cmd_vscp_level_query, + &val); + else + return -einval; + + if (ret != 0) + return ret; + + return val; +} + +static const struct regulator_ops dvfsrc_vcore_ops = { + .list_voltage = regulator_list_voltage_table, + .get_voltage_sel = dvfsrc_get_voltage_sel, + .set_voltage_sel = dvfsrc_set_voltage_sel, +}; + +static const unsigned int mt8183_voltages[] = { + 725000, + 800000, +}; + +static struct dvfsrc_regulator mt8183_regulators[] = { + mt_dvfsrc_regular("dvfsrc-vcore", vcore, + mt8183_voltages), +}; + +static const struct dvfsrc_regulator_init_data regulator_mt8183_data = { + .size = array_size(mt8183_regulators), + .regulator_info = &mt8183_regulators[0], +}; + +static const unsigned int mt6873_voltages[] = { + 575000, + 600000, + 650000, + 725000, +}; + +static struct dvfsrc_regulator mt6873_regulators[] = { + mt_dvfsrc_regular("dvfsrc-vcore", vcore, + mt6873_voltages), + mt_dvfsrc_regular("dvfsrc-vscp", vscp, + mt6873_voltages), +}; + +static const struct dvfsrc_regulator_init_data regulator_mt6873_data = { + .size = array_size(mt6873_regulators), + .regulator_info = &mt6873_regulators[0], +}; + +static const struct of_device_id mtk_dvfsrc_regulator_match[] = { + { + .compatible = "mediatek,mt8183-dvfsrc", + .data = ®ulator_mt8183_data, + }, { + .compatible = "mediatek,mt8192-dvfsrc", + .data = ®ulator_mt6873_data, + }, { + .compatible = "mediatek,mt6873-dvfsrc", + .data = ®ulator_mt6873_data, + }, { + /* sentinel */ + }, +}; +module_device_table(of, mtk_dvfsrc_regulator_match); + +static int dvfsrc_vcore_regulator_probe(struct platform_device *pdev) +{ + const struct of_device_id *match; + struct device *dev = &pdev->dev; + struct regulator_config config = { }; + struct regulator_dev *rdev; + const struct dvfsrc_regulator_init_data *regulator_init_data; + struct dvfsrc_regulator *mt_regulators; + int i; + + match = of_match_node(mtk_dvfsrc_regulator_match, dev->parent->of_node); + + if (!match) { + dev_err(dev, "invalid compatible string "); + return -enodev; + } + + regulator_init_data = match->data; + + mt_regulators = regulator_init_data->regulator_info; + for (i = 0; i < regulator_init_data->size; i++) { + config.dev = dev->parent; + config.driver_data = (mt_regulators + i); + rdev = devm_regulator_register(dev->parent, + &(mt_regulators + i)->desc, + &config); + if (is_err(rdev)) { + dev_err(dev, "failed to register %s ", + (mt_regulators + i)->desc.name); + return ptr_err(rdev); + } + } + + return 0; +} + +static struct platform_driver mtk_dvfsrc_regulator_driver = { + .driver = { + .name = "mtk-dvfsrc-regulator", + }, + .probe = dvfsrc_vcore_regulator_probe, +}; + +static int __init mtk_dvfsrc_regulator_init(void) +{ + return platform_driver_register(&mtk_dvfsrc_regulator_driver); +} +subsys_initcall(mtk_dvfsrc_regulator_init); + +static void __exit mtk_dvfsrc_regulator_exit(void) +{ + platform_driver_unregister(&mtk_dvfsrc_regulator_driver); +} +module_exit(mtk_dvfsrc_regulator_exit); + +module_author("arvin wang <arvin.wang@mediatek.com>"); +module_license("gpl v2");
|
Voltage, current regulators, power capping, power supply
|
a0db6b0aa670ba040f959a000ef24dd4238e016b
|
henryc chen
|
drivers
|
regulator
| |
regulator: bd9571mwv: add bd9574mwf support
|
add support for bd9574mwf which is similar chip with bd9571mwv. note that we don't support voltage rails vd{09,18,25,33} by this driver on bd9574. the vd09 voltage could be read from pmic but that is not supported by this commit.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add bd9574mwf support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['regulator ', 'bd9571mwv']
|
['c']
| 1
| 8
| 2
|
--- diff --git a/drivers/regulator/bd9571mwv-regulator.c b/drivers/regulator/bd9571mwv-regulator.c --- a/drivers/regulator/bd9571mwv-regulator.c +++ b/drivers/regulator/bd9571mwv-regulator.c - * rohm bd9571mwv-m regulator driver + * rohm bd9571mwv-m and bd9574mwf-m regulator driver +#include <linux/mfd/rohm-generic.h> + enum rohm_chip_type chip = platform_get_device_id(pdev)->driver_data; + /* bd9574mwf supports dvfs only */ + if (chip == rohm_chip_type_bd9574 && regulators[i].id != dvfs) + continue; - { "bd9571mwv-regulator", }, + { "bd9571mwv-regulator", rohm_chip_type_bd9571 }, + { "bd9574mwf-regulator", rohm_chip_type_bd9574 },
|
Voltage, current regulators, power capping, power supply
|
ceee9dc13bf991b151701e3b720487b5e1589ba4
|
yoshihiro shimoda mark brown broonie kernel org matti vaittinen matti vaittinen fi rohmeurope com
|
drivers
|
regulator
| |
regulator: mt6315: add support for mt6315 regulator
|
the mt6315 is a regulator found on boards based on mediatek mt8192 and probably other socs. it connects as a slave to soc using spmi.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for mt6315 regulator
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['regulator ', 'mt6315']
|
['h', 'kconfig', 'c', 'makefile']
| 4
| 354
| 0
|
--- diff --git a/drivers/regulator/kconfig b/drivers/regulator/kconfig --- a/drivers/regulator/kconfig +++ b/drivers/regulator/kconfig +config regulator_mt6315 + tristate "mediatek mt6315 pmic" + depends on spmi + select regmap_spmi + help + say y here to select this option to enable the power regulator of + mediatek mt6315 pmic. + this driver supports the control of different power rails of device + through regulator interface. + diff --git a/drivers/regulator/makefile b/drivers/regulator/makefile --- a/drivers/regulator/makefile +++ b/drivers/regulator/makefile +obj-$(config_regulator_mt6315) += mt6315-regulator.o diff --git a/drivers/regulator/mt6315-regulator.c b/drivers/regulator/mt6315-regulator.c --- /dev/null +++ b/drivers/regulator/mt6315-regulator.c +// spdx-license-identifier: gpl-2.0 +// +// copyright (c) 2021 mediatek inc. + +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regmap.h> +#include <linux/regulator/driver.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/mt6315-regulator.h> +#include <linux/regulator/of_regulator.h> +#include <linux/spmi.h> + +#define mt6315_buck_mode_auto 0 +#define mt6315_buck_mode_force_pwm 1 +#define mt6315_buck_mode_lp 2 + +struct mt6315_regulator_info { + struct regulator_desc desc; + u32 status_reg; + u32 lp_mode_mask; + u32 lp_mode_shift; +}; + +struct mt_regulator_init_data { + u32 modeset_mask[mt6315_vbuck_max]; +}; + +struct mt6315_chip { + struct device *dev; + struct regmap *regmap; +}; + +#define mt_buck(_name, _bid, _vsel) \ +[_bid] = { \ + .desc = { \ + .name = _name, \ + .of_match = of_match_ptr(_name), \ + .regulators_node = "regulators", \ + .ops = &mt6315_volt_range_ops, \ + .type = regulator_voltage, \ + .id = _bid, \ + .owner = this_module, \ + .n_voltages = 0xbf, \ + .linear_ranges = mt_volt_range1, \ + .n_linear_ranges = array_size(mt_volt_range1), \ + .vsel_reg = _vsel, \ + .vsel_mask = 0xff, \ + .enable_reg = mt6315_buck_top_con0, \ + .enable_mask = bit(_bid), \ + .of_map_mode = mt6315_map_mode, \ + }, \ + .status_reg = _bid##_dbg4, \ + .lp_mode_mask = bit(_bid), \ + .lp_mode_shift = _bid, \ +} + +static const struct linear_range mt_volt_range1[] = { + regulator_linear_range(0, 0, 0xbf, 6250), +}; + +static unsigned int mt6315_map_mode(u32 mode) +{ + switch (mode) { + case mt6315_buck_mode_auto: + return regulator_mode_normal; + case mt6315_buck_mode_force_pwm: + return regulator_mode_fast; + case mt6315_buck_mode_lp: + return regulator_mode_idle; + default: + return -einval; + } +} + +static unsigned int mt6315_regulator_get_mode(struct regulator_dev *rdev) +{ + struct mt_regulator_init_data *init = rdev_get_drvdata(rdev); + const struct mt6315_regulator_info *info; + int ret, regval; + u32 modeset_mask; + + info = container_of(rdev->desc, struct mt6315_regulator_info, desc); + modeset_mask = init->modeset_mask[rdev_get_id(rdev)]; + ret = regmap_read(rdev->regmap, mt6315_buck_top_4phase_ana_con42, ®val); + if (ret != 0) { + dev_notice(&rdev->dev, "failed to get mode: %d ", ret); + return ret; + } + + if ((regval & modeset_mask) == modeset_mask) + return regulator_mode_fast; + + ret = regmap_read(rdev->regmap, mt6315_buck_top_con1, ®val); + if (ret != 0) { + dev_notice(&rdev->dev, "failed to get lp mode: %d ", ret); + return ret; + } + + if (regval & info->lp_mode_mask) + return regulator_mode_idle; + else + return regulator_mode_normal; +} + +static int mt6315_regulator_set_mode(struct regulator_dev *rdev, + u32 mode) +{ + struct mt_regulator_init_data *init = rdev_get_drvdata(rdev); + const struct mt6315_regulator_info *info; + int ret, val, curr_mode; + u32 modeset_mask; + + info = container_of(rdev->desc, struct mt6315_regulator_info, desc); + modeset_mask = init->modeset_mask[rdev_get_id(rdev)]; + curr_mode = mt6315_regulator_get_mode(rdev); + switch (mode) { + case regulator_mode_fast: + ret = regmap_update_bits(rdev->regmap, + mt6315_buck_top_4phase_ana_con42, + modeset_mask, + modeset_mask); + break; + case regulator_mode_normal: + if (curr_mode == regulator_mode_fast) { + ret = regmap_update_bits(rdev->regmap, + mt6315_buck_top_4phase_ana_con42, + modeset_mask, + 0); + } else if (curr_mode == regulator_mode_idle) { + ret = regmap_update_bits(rdev->regmap, + mt6315_buck_top_con1, + info->lp_mode_mask, + 0); + usleep_range(100, 110); + } else { + ret = -einval; + } + break; + case regulator_mode_idle: + val = mt6315_buck_mode_lp >> 1; + val <<= info->lp_mode_shift; + ret = regmap_update_bits(rdev->regmap, + mt6315_buck_top_con1, + info->lp_mode_mask, + val); + break; + default: + ret = -einval; + dev_notice(&rdev->dev, "unsupported mode: %d ", mode); + break; + } + + if (ret != 0) { + dev_notice(&rdev->dev, "failed to set mode: %d ", ret); + return ret; + } + + return 0; +} + +static int mt6315_get_status(struct regulator_dev *rdev) +{ + const struct mt6315_regulator_info *info; + int ret; + u32 regval; + + info = container_of(rdev->desc, struct mt6315_regulator_info, desc); + ret = regmap_read(rdev->regmap, info->status_reg, ®val); + if (ret < 0) { + dev_notice(&rdev->dev, "failed to get enable reg: %d ", ret); + return ret; + } + + return (regval & bit(0)) ? regulator_status_on : regulator_status_off; +} + +static const struct regulator_ops mt6315_volt_range_ops = { + .list_voltage = regulator_list_voltage_linear_range, + .map_voltage = regulator_map_voltage_linear_range, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_time_sel = regulator_set_voltage_time_sel, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .get_status = mt6315_get_status, + .set_mode = mt6315_regulator_set_mode, + .get_mode = mt6315_regulator_get_mode, +}; + +static const struct mt6315_regulator_info mt6315_regulators[mt6315_vbuck_max] = { + mt_buck("vbuck1", mt6315_vbuck1, mt6315_buck_top_elr0), + mt_buck("vbuck2", mt6315_vbuck2, mt6315_buck_top_elr2), + mt_buck("vbuck3", mt6315_vbuck3, mt6315_buck_top_elr4), + mt_buck("vbuck4", mt6315_vbuck4, mt6315_buck_top_elr6), +}; + +static const struct regmap_config mt6315_regmap_config = { + .reg_bits = 16, + .val_bits = 8, + .max_register = 0x16d0, + .fast_io = true, +}; + +static const struct of_device_id mt6315_of_match[] = { + { + .compatible = "mediatek,mt6315-regulator", + }, { + /* sentinel */ + }, +}; +module_device_table(of, mt6315_of_match); + +static int mt6315_regulator_probe(struct spmi_device *pdev) +{ + struct device *dev = &pdev->dev; + struct regmap *regmap; + struct mt6315_chip *chip; + struct mt_regulator_init_data *init_data; + struct regulator_config config = {}; + struct regulator_dev *rdev; + int i; + + regmap = devm_regmap_init_spmi_ext(pdev, &mt6315_regmap_config); + if (!regmap) + return -enodev; + + chip = devm_kzalloc(dev, sizeof(struct mt6315_chip), gfp_kernel); + if (!chip) + return -enomem; + + init_data = devm_kzalloc(dev, sizeof(struct mt_regulator_init_data), gfp_kernel); + if (!init_data) + return -enomem; + + switch (pdev->usid) { + case mt6315_pp: + init_data->modeset_mask[mt6315_vbuck1] = bit(mt6315_vbuck1) | bit(mt6315_vbuck2) | + bit(mt6315_vbuck4); + break; + case mt6315_sp: + case mt6315_rp: + init_data->modeset_mask[mt6315_vbuck1] = bit(mt6315_vbuck1) | bit(mt6315_vbuck2); + break; + default: + init_data->modeset_mask[mt6315_vbuck1] = bit(mt6315_vbuck1); + break; + } + for (i = mt6315_vbuck2; i < mt6315_vbuck_max; i++) + init_data->modeset_mask[i] = bit(i); + + chip->dev = dev; + chip->regmap = regmap; + dev_set_drvdata(dev, chip); + + config.dev = dev; + config.regmap = regmap; + for (i = mt6315_vbuck1; i < mt6315_vbuck_max; i++) { + config.driver_data = init_data; + rdev = devm_regulator_register(dev, &mt6315_regulators[i].desc, &config); + if (is_err(rdev)) { + dev_notice(dev, "failed to register %s ", mt6315_regulators[i].desc.name); + continue; + } + } + + return 0; +} + +static void mt6315_regulator_shutdown(struct spmi_device *pdev) +{ + struct mt6315_chip *chip = dev_get_drvdata(&pdev->dev); + int ret = 0; + + ret |= regmap_write(chip->regmap, mt6315_top_tma_key_h, protection_key_h); + ret |= regmap_write(chip->regmap, mt6315_top_tma_key, protection_key); + ret |= regmap_update_bits(chip->regmap, mt6315_top2_elr7, 1, 1); + ret |= regmap_write(chip->regmap, mt6315_top_tma_key, 0); + ret |= regmap_write(chip->regmap, mt6315_top_tma_key_h, 0); + if (ret < 0) + dev_notice(&pdev->dev, "[%#x] failed to enable power off sequence. %d ", + pdev->usid, ret); +} + +static struct spmi_driver mt6315_regulator_driver = { + .driver = { + .name = "mt6315-regulator", + .of_match_table = mt6315_of_match, + }, + .probe = mt6315_regulator_probe, + .shutdown = mt6315_regulator_shutdown, +}; + +module_spmi_driver(mt6315_regulator_driver); + +module_author("hsin-hsiung wang <hsin-hsiung.wang@mediatek.com>"); +module_description("regulator driver for mediatek mt6315 pmic"); +module_license("gpl"); diff --git a/include/linux/regulator/mt6315-regulator.h b/include/linux/regulator/mt6315-regulator.h --- /dev/null +++ b/include/linux/regulator/mt6315-regulator.h +/* spdx-license-identifier: gpl-2.0 */ +/* + * copyright (c) 2021 mediatek inc. + */ + +#ifndef __linux_regulator_mt6315_h +#define __linux_regulator_mt6315_h + +#define mt6315_rp 3 +#define mt6315_pp 6 +#define mt6315_sp 7 + +enum { + mt6315_vbuck1 = 0, + mt6315_vbuck2, + mt6315_vbuck3, + mt6315_vbuck4, + mt6315_vbuck_max, +}; + +/* register */ +#define mt6315_top2_elr7 0x139 +#define mt6315_top_tma_key 0x39f +#define mt6315_top_tma_key_h 0x3a0 +#define mt6315_buck_top_con0 0x1440 +#define mt6315_buck_top_con1 0x1443 +#define mt6315_buck_top_elr0 0x1449 +#define mt6315_buck_top_elr2 0x144b +#define mt6315_buck_top_elr4 0x144d +#define mt6315_buck_top_elr6 0x144f +#define mt6315_vbuck1_dbg0 0x1499 +#define mt6315_vbuck1_dbg4 0x149d +#define mt6315_vbuck2_dbg0 0x1519 +#define mt6315_vbuck2_dbg4 0x151d +#define mt6315_vbuck3_dbg0 0x1599 +#define mt6315_vbuck3_dbg4 0x159d +#define mt6315_vbuck4_dbg0 0x1619 +#define mt6315_vbuck4_dbg4 0x161d +#define mt6315_buck_top_4phase_ana_con42 0x16b1 + +#define protection_key_h 0x9c +#define protection_key 0xea + +#endif /* __linux_regulator_mt6315_h */
|
Voltage, current regulators, power capping, power supply
|
7aa382cfe714f61b0c29f02c31d389c506b4e2ae
|
hsin hsiung wang
|
include
|
linux
|
regulator
|
regulator: pf8x00: add suspend support
|
this patch adds suspend/resume support so that it is possible to configure the ldos and bucks as on or off during suspend phase as well as to configure suspend specific voltages.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add suspend support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['regulator ', 'pf8x00']
|
['c']
| 1
| 70
| 5
|
--- diff --git a/drivers/regulator/pf8x00-regulator.c b/drivers/regulator/pf8x00-regulator.c --- a/drivers/regulator/pf8x00-regulator.c +++ b/drivers/regulator/pf8x00-regulator.c -struct pf8x00_regulator { +struct pf8x00_regulator_data { + unsigned int suspend_enable_reg; + unsigned int suspend_enable_mask; + unsigned int suspend_voltage_reg; + unsigned int suspend_voltage_cache; +static int pf8x00_suspend_enable(struct regulator_dev *rdev) +{ + struct pf8x00_regulator_data *regl = rdev_get_drvdata(rdev); + struct regmap *rmap = rdev_get_regmap(rdev); + + return regmap_update_bits(rmap, regl->suspend_enable_reg, + regl->suspend_enable_mask, + regl->suspend_enable_mask); +} + +static int pf8x00_suspend_disable(struct regulator_dev *rdev) +{ + struct pf8x00_regulator_data *regl = rdev_get_drvdata(rdev); + struct regmap *rmap = rdev_get_regmap(rdev); + + return regmap_update_bits(rmap, regl->suspend_enable_reg, + regl->suspend_enable_mask, 0); +} + +static int pf8x00_set_suspend_voltage(struct regulator_dev *rdev, int uv) +{ + struct pf8x00_regulator_data *regl = rdev_get_drvdata(rdev); + int ret; + + if (regl->suspend_voltage_cache == uv) + return 0; + + ret = regulator_map_voltage_iterate(rdev, uv, uv); + if (ret < 0) { + dev_err(rdev_get_dev(rdev), "failed to map %i uv ", uv); + return ret; + } + + dev_dbg(rdev_get_dev(rdev), "uv: %i, reg: 0x%x, msk: 0x%x, val: 0x%x ", + uv, regl->suspend_voltage_reg, regl->desc.vsel_mask, ret); + ret = regmap_update_bits(rdev->regmap, regl->suspend_voltage_reg, + regl->desc.vsel_mask, ret); + if (ret < 0) { + dev_err(rdev_get_dev(rdev), "failed to set %i uv ", uv); + return ret; + } + + regl->suspend_voltage_cache = uv; + + return 0; +} + + .set_suspend_enable = pf8x00_suspend_enable, + .set_suspend_disable = pf8x00_suspend_disable, + .set_suspend_voltage = pf8x00_set_suspend_voltage, + .set_suspend_enable = pf8x00_suspend_enable, + .set_suspend_disable = pf8x00_suspend_disable, + .set_suspend_voltage = pf8x00_set_suspend_voltage, + .set_suspend_enable = pf8x00_suspend_enable, + .set_suspend_disable = pf8x00_suspend_disable, + .suspend_enable_reg = (base) + ldo_config2, \ + .suspend_enable_mask = 1, \ + .suspend_voltage_reg = (base) + ldo_stby_volt, \ + .suspend_enable_reg = (base) + sw_mode1, \ + .suspend_enable_mask = 0xc, \ + .suspend_voltage_reg = (base) + sw_stby_volt, \ -static struct pf8x00_regulator pf8x00_regulators_data[pf8x00_max_regulators] = { +static struct pf8x00_regulator_data pf8x00_regs_data[pf8x00_max_regulators] = { - for (id = 0; id < array_size(pf8x00_regulators_data); id++) { - struct pf8x00_regulator *data = &pf8x00_regulators_data[id]; + for (id = 0; id < array_size(pf8x00_regs_data); id++) { + struct pf8x00_regulator_data *data = &pf8x00_regs_data[id]; - config.driver_data = chip; + config.driver_data = data;
|
Voltage, current regulators, power capping, power supply
|
7fefe72b0f8c0d7e63af9810c4dcc88757eddcd5
|
christoph fritz
|
drivers
|
regulator
| |
regulator: qcom-rpmh-regulator: add pm8009-1 chip revision
|
pm8009 has special revision (p=1), which is to be used for sm8250 platform. the major difference is the s2 regulator which supplies 0.95 v instead of 2.848v. declare regulators data to be used for this chip revision. the datasheet calls the chip just pm8009-1, so use the same name.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add pm8009-1 chip revision
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['regulator ', 'qcom-rpmh-regulator']
|
['c']
| 1
| 26
| 0
|
--- diff --git a/drivers/regulator/qcom-rpmh-regulator.c b/drivers/regulator/qcom-rpmh-regulator.c --- a/drivers/regulator/qcom-rpmh-regulator.c +++ b/drivers/regulator/qcom-rpmh-regulator.c +static const struct rpmh_vreg_hw_data pmic5_hfsmps515_1 = { + .regulator_type = vrm, + .ops = &rpmh_regulator_vrm_ops, + .voltage_range = regulator_linear_range(900000, 0, 4, 16000), + .n_voltages = 5, + .pmic_mode_map = pmic_mode_map_pmic5_smps, + .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode, +}; + +static const struct rpmh_vreg_init_data pm8009_1_vreg_data[] = { + rpmh_vreg("smps1", "smp%s1", &pmic5_hfsmps510, "vdd-s1"), + rpmh_vreg("smps2", "smp%s2", &pmic5_hfsmps515_1, "vdd-s2"), + rpmh_vreg("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1"), + rpmh_vreg("ldo2", "ldo%s2", &pmic5_nldo, "vdd-l2"), + rpmh_vreg("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3"), + rpmh_vreg("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l4"), + rpmh_vreg("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l5-l6"), + rpmh_vreg("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l5-l6"), + rpmh_vreg("ldo7", "ldo%s6", &pmic5_pldo_lv, "vdd-l7"), + {}, +}; + + { + .compatible = "qcom,pm8009-1-rpmh-regulators", + .data = pm8009_1_vreg_data, + },
|
Voltage, current regulators, power capping, power supply
|
951384cabc5dfb09251d440dbc26058eba86f97e
|
dmitry baryshkov vinod koul vkoul kernel org
|
drivers
|
regulator
| |
regulator: rt4831: adds support for richtek rt4831 dsv regulator
|
adds support for richtek rt4831 dsv regulator
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
adds support for richtek rt4831 dsv regulator
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['regulator ', 'rt4831']
|
['kconfig', 'c', 'makefile']
| 3
| 209
| 0
|
--- diff --git a/drivers/regulator/kconfig b/drivers/regulator/kconfig --- a/drivers/regulator/kconfig +++ b/drivers/regulator/kconfig +config regulator_rt4831 + tristate "richtek rt4831 dsv regulators" + depends on mfd_rt4831 + help + this adds support for voltage regulators in richtek rt4831. + there are three regulators (vlcm/dsvp/dsvn). + vlcm is a virtual voltage input for dsvp/dsvn inside ic. + and dsvp/dsvn is the real vout range from 4v to 6.5v. + it's common used to provide the power for the display panel. + diff --git a/drivers/regulator/makefile b/drivers/regulator/makefile --- a/drivers/regulator/makefile +++ b/drivers/regulator/makefile +obj-$(config_regulator_rt4831) += rt4831-regulator.o diff --git a/drivers/regulator/rt4831-regulator.c b/drivers/regulator/rt4831-regulator.c --- /dev/null +++ b/drivers/regulator/rt4831-regulator.c +// spdx-license-identifier: gpl-2.0-only + +#include <linux/bitops.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/regulator/consumer.h> +#include <linux/regulator/driver.h> + +enum { + dsv_out_vlcm = 0, + dsv_out_vpos, + dsv_out_vneg, + dsv_out_max +}; + +#define rt4831_reg_dsven 0x09 +#define rt4831_reg_vlcm 0x0c +#define rt4831_reg_vpos 0x0d +#define rt4831_reg_vneg 0x0e +#define rt4831_reg_flags 0x0f + +#define rt4831_volt_mask genmask(5, 0) +#define rt4831_dsvmode_shift 5 +#define rt4831_dsvmode_mask genmask(7, 5) +#define rt4831_posaden_mask bit(4) +#define rt4831_negaden_mask bit(3) +#define rt4831_posen_mask bit(2) +#define rt4831_negen_mask bit(1) + +#define rt4831_otp_mask bit(6) +#define rt4831_lcmovp_mask bit(5) +#define rt4831_vposscp_mask bit(3) +#define rt4831_vnegscp_mask bit(2) + +#define dsv_mode_normal (0x4 << rt4831_dsvmode_shift) +#define dsv_mode_bypass (0x6 << rt4831_dsvmode_shift) +#define step_uv 50000 +#define vlcm_min_uv 4000000 +#define vlcm_max_uv 7150000 +#define vlcm_n_voltages ((vlcm_max_uv - vlcm_min_uv) / step_uv + 1) +#define vpn_min_uv 4000000 +#define vpn_max_uv 6500000 +#define vpn_n_voltages ((vpn_max_uv - vpn_min_uv) / step_uv + 1) + +static int rt4831_get_error_flags(struct regulator_dev *rdev, unsigned int *flags) +{ + struct regmap *regmap = rdev_get_regmap(rdev); + int rid = rdev_get_id(rdev); + unsigned int val, events = 0; + int ret; + + ret = regmap_read(regmap, rt4831_reg_flags, &val); + if (ret) + return ret; + + if (val & rt4831_otp_mask) + events |= regulator_error_over_temp; + + if (rid == dsv_out_vlcm && (val & rt4831_lcmovp_mask)) + events |= regulator_error_over_current; + + if (rid == dsv_out_vpos && (val & rt4831_vposscp_mask)) + events |= regulator_error_over_current; + + if (rid == dsv_out_vneg && (val & rt4831_vnegscp_mask)) + events |= regulator_error_over_current; + + *flags = events; + return 0; +} + +static const struct regulator_ops rt4831_dsvlcm_ops = { + .list_voltage = regulator_list_voltage_linear, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_bypass = regulator_set_bypass_regmap, + .get_bypass = regulator_get_bypass_regmap, + .get_error_flags = rt4831_get_error_flags, +}; + +static const struct regulator_ops rt4831_dsvpn_ops = { + .list_voltage = regulator_list_voltage_linear, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .set_active_discharge = regulator_set_active_discharge_regmap, + .get_error_flags = rt4831_get_error_flags, +}; + +static const struct regulator_desc rt4831_regulator_descs[] = { + { + .name = "dsvlcm", + .ops = &rt4831_dsvlcm_ops, + .of_match = of_match_ptr("dsvlcm"), + .regulators_node = of_match_ptr("regulators"), + .type = regulator_voltage, + .id = dsv_out_vlcm, + .n_voltages = vlcm_n_voltages, + .min_uv = vlcm_min_uv, + .uv_step = step_uv, + .vsel_reg = rt4831_reg_vlcm, + .vsel_mask = rt4831_volt_mask, + .bypass_reg = rt4831_reg_dsven, + .bypass_val_on = dsv_mode_bypass, + .bypass_val_off = dsv_mode_normal, + }, + { + .name = "dsvp", + .ops = &rt4831_dsvpn_ops, + .of_match = of_match_ptr("dsvp"), + .regulators_node = of_match_ptr("regulators"), + .type = regulator_voltage, + .id = dsv_out_vpos, + .n_voltages = vpn_n_voltages, + .min_uv = vpn_min_uv, + .uv_step = step_uv, + .vsel_reg = rt4831_reg_vpos, + .vsel_mask = rt4831_volt_mask, + .enable_reg = rt4831_reg_dsven, + .enable_mask = rt4831_posen_mask, + .active_discharge_reg = rt4831_reg_dsven, + .active_discharge_mask = rt4831_posaden_mask, + }, + { + .name = "dsvn", + .ops = &rt4831_dsvpn_ops, + .of_match = of_match_ptr("dsvn"), + .regulators_node = of_match_ptr("regulators"), + .type = regulator_voltage, + .id = dsv_out_vneg, + .n_voltages = vpn_n_voltages, + .min_uv = vpn_min_uv, + .uv_step = step_uv, + .vsel_reg = rt4831_reg_vneg, + .vsel_mask = rt4831_volt_mask, + .enable_reg = rt4831_reg_dsven, + .enable_mask = rt4831_negen_mask, + .active_discharge_reg = rt4831_reg_dsven, + .active_discharge_mask = rt4831_negaden_mask, + } +}; + +static int rt4831_regulator_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + struct regulator_dev *rdev; + struct regulator_config config = {}; + int i, ret; + + regmap = dev_get_regmap(pdev->dev.parent, null); + if (is_err(regmap)) { + dev_err(&pdev->dev, "failed to init regmap "); + return ptr_err(regmap); + } + + /* configure dsv mode to normal by default */ + ret = regmap_update_bits(regmap, rt4831_reg_dsven, rt4831_dsvmode_mask, dsv_mode_normal); + if (ret) { + dev_err(&pdev->dev, "failed to configure dsv mode to normal "); + return ret; + } + + config.dev = pdev->dev.parent; + config.regmap = regmap; + + for (i = 0; i < dsv_out_max; i++) { + rdev = devm_regulator_register(&pdev->dev, rt4831_regulator_descs + i, &config); + if (is_err(rdev)) { + dev_err(&pdev->dev, "failed to register %d regulator ", i); + return ptr_err(rdev); + } + } + + return 0; +} + +static const struct platform_device_id rt4831_regulator_match[] = { + { "rt4831-regulator", 0 }, + {} +}; +module_device_table(platform, rt4831_regulator_match); + +static struct platform_driver rt4831_regulator_driver = { + .driver = { + .name = "rt4831-regulator", + }, + .id_table = rt4831_regulator_match, + .probe = rt4831_regulator_probe, +}; +module_platform_driver(rt4831_regulator_driver); + +module_author("chiyuan huang <cy_huang@richtek.com>"); +module_license("gpl v2");
|
Voltage, current regulators, power capping, power supply
|
9351ab8b0cb61ffbef30343d28d1855e329c98fb
|
chiyuan huang
|
drivers
|
regulator
| |
regulator: remove ab3100 driver
|
the st-ericsson u300 platform is getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove ab3100 driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['regulator ']
|
['kconfig', 'c', 'makefile']
| 3
| 0
| 734
|
--- diff --git a/drivers/regulator/kconfig b/drivers/regulator/kconfig --- a/drivers/regulator/kconfig +++ b/drivers/regulator/kconfig -config regulator_ab3100 - tristate "st-ericsson ab3100 regulator functions" - depends on ab3100_core - default y if ab3100_core - help - these regulators correspond to functionality in the - ab3100 analog baseband dealing with power regulators - for the system. - diff --git a/drivers/regulator/makefile b/drivers/regulator/makefile --- a/drivers/regulator/makefile +++ b/drivers/regulator/makefile -obj-$(config_regulator_ab3100) += ab3100.o diff --git a/drivers/regulator/ab3100.c b/drivers/regulator/ab3100.c --- a/drivers/regulator/ab3100.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * drivers/regulator/ab3100.c - * - * copyright (c) 2008-2009 st-ericsson ab - * low-level control of the ab3100 ic low dropout (ldo) - * regulators, external regulator and buck converter - * author: mattias wallin <mattias.wallin@stericsson.com> - * author: linus walleij <linus.walleij@stericsson.com> - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/err.h> -#include <linux/platform_device.h> -#include <linux/regulator/driver.h> -#include <linux/mfd/ab3100.h> -#include <linux/mfd/abx500.h> -#include <linux/of.h> -#include <linux/regulator/of_regulator.h> - -/* ldo registers and some handy masking definitions for ab3100 */ -#define ab3100_ldo_a 0x40 -#define ab3100_ldo_c 0x41 -#define ab3100_ldo_d 0x42 -#define ab3100_ldo_e 0x43 -#define ab3100_ldo_e_sleep 0x44 -#define ab3100_ldo_f 0x45 -#define ab3100_ldo_g 0x46 -#define ab3100_ldo_h 0x47 -#define ab3100_ldo_h_sleep_mode 0 -#define ab3100_ldo_h_sleep_en 2 -#define ab3100_ldo_on 4 -#define ab3100_ldo_h_vsel_ac 5 -#define ab3100_ldo_k 0x48 -#define ab3100_ldo_ext 0x49 -#define ab3100_buck 0x4a -#define ab3100_buck_sleep 0x4b -#define ab3100_reg_on_mask 0x10 - -/** - * struct ab3100_regulator - * a struct passed around the individual regulator functions - * @platform_device: platform device holding this regulator - * @dev: handle to the device - * @plfdata: ab3100 platform data passed in at probe time - * @regreg: regulator register number in the ab3100 - */ -struct ab3100_regulator { - struct device *dev; - struct ab3100_platform_data *plfdata; - u8 regreg; -}; - -/* the order in which registers are initialized */ -static const u8 ab3100_reg_init_order[ab3100_num_regulators+2] = { - ab3100_ldo_a, - ab3100_ldo_c, - ab3100_ldo_e, - ab3100_ldo_e_sleep, - ab3100_ldo_f, - ab3100_ldo_g, - ab3100_ldo_h, - ab3100_ldo_k, - ab3100_ldo_ext, - ab3100_buck, - ab3100_buck_sleep, - ab3100_ldo_d, -}; - -/* preset (hardware defined) voltages for these regulators */ -#define ldo_a_voltage 2750000 -#define ldo_c_voltage 2650000 -#define ldo_d_voltage 2650000 - -static const unsigned int ldo_e_buck_typ_voltages[] = { - 1800000, - 1400000, - 1300000, - 1200000, - 1100000, - 1050000, - 900000, -}; - -static const unsigned int ldo_f_typ_voltages[] = { - 1800000, - 1400000, - 1300000, - 1200000, - 1100000, - 1050000, - 2500000, - 2650000, -}; - -static const unsigned int ldo_g_typ_voltages[] = { - 2850000, - 2750000, - 1800000, - 1500000, -}; - -static const unsigned int ldo_h_typ_voltages[] = { - 2750000, - 1800000, - 1500000, - 1200000, -}; - -static const unsigned int ldo_k_typ_voltages[] = { - 2750000, - 1800000, -}; - - -/* the regulator devices */ -static struct ab3100_regulator -ab3100_regulators[ab3100_num_regulators] = { - { - .regreg = ab3100_ldo_a, - }, - { - .regreg = ab3100_ldo_c, - }, - { - .regreg = ab3100_ldo_d, - }, - { - .regreg = ab3100_ldo_e, - }, - { - .regreg = ab3100_ldo_f, - }, - { - .regreg = ab3100_ldo_g, - }, - { - .regreg = ab3100_ldo_h, - }, - { - .regreg = ab3100_ldo_k, - }, - { - .regreg = ab3100_ldo_ext, - /* no voltages for the external regulator */ - }, - { - .regreg = ab3100_buck, - }, -}; - -/* - * general functions for enable, disable and is_enabled used for - * ldo: a,c,e,f,g,h,k,ext and buck - */ -static int ab3100_enable_regulator(struct regulator_dev *reg) -{ - struct ab3100_regulator *abreg = rdev_get_drvdata(reg); - int err; - u8 regval; - - err = abx500_get_register_interruptible(abreg->dev, 0, abreg->regreg, - ®val); - if (err) { - dev_warn(®->dev, "failed to get regid %d value ", - abreg->regreg); - return err; - } - - /* the regulator is already on, no reason to go further */ - if (regval & ab3100_reg_on_mask) - return 0; - - regval |= ab3100_reg_on_mask; - - err = abx500_set_register_interruptible(abreg->dev, 0, abreg->regreg, - regval); - if (err) { - dev_warn(®->dev, "failed to set regid %d value ", - abreg->regreg); - return err; - } - - return 0; -} - -static int ab3100_disable_regulator(struct regulator_dev *reg) -{ - struct ab3100_regulator *abreg = rdev_get_drvdata(reg); - int err; - u8 regval; - - /* - * ldo d is a special regulator. when it is disabled, the entire - * system is shut down. so this is handled specially. - */ - pr_info("called ab3100_disable_regulator "); - if (abreg->regreg == ab3100_ldo_d) { - dev_info(®->dev, "disabling ldo d - shut down system "); - /* setting ldo d to 0x00 cuts the power to the soc */ - return abx500_set_register_interruptible(abreg->dev, 0, - ab3100_ldo_d, 0x00u); - } - - /* - * all other regulators are handled here - */ - err = abx500_get_register_interruptible(abreg->dev, 0, abreg->regreg, - ®val); - if (err) { - dev_err(®->dev, "unable to get register 0x%x ", - abreg->regreg); - return err; - } - regval &= ~ab3100_reg_on_mask; - return abx500_set_register_interruptible(abreg->dev, 0, abreg->regreg, - regval); -} - -static int ab3100_is_enabled_regulator(struct regulator_dev *reg) -{ - struct ab3100_regulator *abreg = rdev_get_drvdata(reg); - u8 regval; - int err; - - err = abx500_get_register_interruptible(abreg->dev, 0, abreg->regreg, - ®val); - if (err) { - dev_err(®->dev, "unable to get register 0x%x ", - abreg->regreg); - return err; - } - - return regval & ab3100_reg_on_mask; -} - -static int ab3100_get_voltage_regulator(struct regulator_dev *reg) -{ - struct ab3100_regulator *abreg = rdev_get_drvdata(reg); - u8 regval; - int err; - - /* - * for variable types, read out setting and index into - * supplied voltage list. - */ - err = abx500_get_register_interruptible(abreg->dev, 0, - abreg->regreg, ®val); - if (err) { - dev_warn(®->dev, - "failed to get regulator value in register %02x ", - abreg->regreg); - return err; - } - - /* the 3 highest bits index voltages */ - regval &= 0xe0; - regval >>= 5; - - if (regval >= reg->desc->n_voltages) { - dev_err(®->dev, - "regulator register %02x contains an illegal voltage setting ", - abreg->regreg); - return -einval; - } - - return reg->desc->volt_table[regval]; -} - -static int ab3100_set_voltage_regulator_sel(struct regulator_dev *reg, - unsigned selector) -{ - struct ab3100_regulator *abreg = rdev_get_drvdata(reg); - u8 regval; - int err; - - err = abx500_get_register_interruptible(abreg->dev, 0, - abreg->regreg, ®val); - if (err) { - dev_warn(®->dev, - "failed to get regulator register %02x ", - abreg->regreg); - return err; - } - - /* the highest three bits control the variable regulators */ - regval &= ~0xe0; - regval |= (selector << 5); - - err = abx500_set_register_interruptible(abreg->dev, 0, - abreg->regreg, regval); - if (err) - dev_warn(®->dev, "failed to set regulator register %02x ", - abreg->regreg); - - return err; -} - -static int ab3100_set_suspend_voltage_regulator(struct regulator_dev *reg, - int uv) -{ - struct ab3100_regulator *abreg = rdev_get_drvdata(reg); - u8 regval; - int err; - int bestindex; - u8 targetreg; - - if (abreg->regreg == ab3100_ldo_e) - targetreg = ab3100_ldo_e_sleep; - else if (abreg->regreg == ab3100_buck) - targetreg = ab3100_buck_sleep; - else - return -einval; - - /* ldo e and buck have special suspend voltages you can set */ - bestindex = regulator_map_voltage_iterate(reg, uv, uv); - - err = abx500_get_register_interruptible(abreg->dev, 0, - targetreg, ®val); - if (err) { - dev_warn(®->dev, - "failed to get regulator register %02x ", - targetreg); - return err; - } - - /* the highest three bits control the variable regulators */ - regval &= ~0xe0; - regval |= (bestindex << 5); - - err = abx500_set_register_interruptible(abreg->dev, 0, - targetreg, regval); - if (err) - dev_warn(®->dev, "failed to set regulator register %02x ", - abreg->regreg); - - return err; -} - -/* - * the external regulator can just define a fixed voltage. - */ -static int ab3100_get_voltage_regulator_external(struct regulator_dev *reg) -{ - struct ab3100_regulator *abreg = rdev_get_drvdata(reg); - - if (abreg->plfdata) - return abreg->plfdata->external_voltage; - else - /* todo: encode external voltage into device tree */ - return 0; -} - -static const struct regulator_ops regulator_ops_fixed = { - .enable = ab3100_enable_regulator, - .disable = ab3100_disable_regulator, - .is_enabled = ab3100_is_enabled_regulator, -}; - -static const struct regulator_ops regulator_ops_variable = { - .enable = ab3100_enable_regulator, - .disable = ab3100_disable_regulator, - .is_enabled = ab3100_is_enabled_regulator, - .get_voltage = ab3100_get_voltage_regulator, - .set_voltage_sel = ab3100_set_voltage_regulator_sel, - .list_voltage = regulator_list_voltage_table, -}; - -static const struct regulator_ops regulator_ops_variable_sleepable = { - .enable = ab3100_enable_regulator, - .disable = ab3100_disable_regulator, - .is_enabled = ab3100_is_enabled_regulator, - .get_voltage = ab3100_get_voltage_regulator, - .set_voltage_sel = ab3100_set_voltage_regulator_sel, - .set_suspend_voltage = ab3100_set_suspend_voltage_regulator, - .list_voltage = regulator_list_voltage_table, -}; - -/* - * ldo ext is an external regulator so it is really - * not possible to set any voltage locally here, ab3100 - * is an on/off switch plain an simple. the external - * voltage is defined in the board set-up if any. - */ -static const struct regulator_ops regulator_ops_external = { - .enable = ab3100_enable_regulator, - .disable = ab3100_disable_regulator, - .is_enabled = ab3100_is_enabled_regulator, - .get_voltage = ab3100_get_voltage_regulator_external, -}; - -static const struct regulator_desc -ab3100_regulator_desc[ab3100_num_regulators] = { - { - .name = "ldo_a", - .id = ab3100_ldo_a, - .ops = ®ulator_ops_fixed, - .n_voltages = 1, - .type = regulator_voltage, - .owner = this_module, - .fixed_uv = ldo_a_voltage, - .enable_time = 200, - }, - { - .name = "ldo_c", - .id = ab3100_ldo_c, - .ops = ®ulator_ops_fixed, - .n_voltages = 1, - .type = regulator_voltage, - .owner = this_module, - .fixed_uv = ldo_c_voltage, - .enable_time = 200, - }, - { - .name = "ldo_d", - .id = ab3100_ldo_d, - .ops = ®ulator_ops_fixed, - .n_voltages = 1, - .type = regulator_voltage, - .owner = this_module, - .fixed_uv = ldo_d_voltage, - .enable_time = 200, - }, - { - .name = "ldo_e", - .id = ab3100_ldo_e, - .ops = ®ulator_ops_variable_sleepable, - .n_voltages = array_size(ldo_e_buck_typ_voltages), - .volt_table = ldo_e_buck_typ_voltages, - .type = regulator_voltage, - .owner = this_module, - .enable_time = 200, - }, - { - .name = "ldo_f", - .id = ab3100_ldo_f, - .ops = ®ulator_ops_variable, - .n_voltages = array_size(ldo_f_typ_voltages), - .volt_table = ldo_f_typ_voltages, - .type = regulator_voltage, - .owner = this_module, - .enable_time = 600, - }, - { - .name = "ldo_g", - .id = ab3100_ldo_g, - .ops = ®ulator_ops_variable, - .n_voltages = array_size(ldo_g_typ_voltages), - .volt_table = ldo_g_typ_voltages, - .type = regulator_voltage, - .owner = this_module, - .enable_time = 400, - }, - { - .name = "ldo_h", - .id = ab3100_ldo_h, - .ops = ®ulator_ops_variable, - .n_voltages = array_size(ldo_h_typ_voltages), - .volt_table = ldo_h_typ_voltages, - .type = regulator_voltage, - .owner = this_module, - .enable_time = 200, - }, - { - .name = "ldo_k", - .id = ab3100_ldo_k, - .ops = ®ulator_ops_variable, - .n_voltages = array_size(ldo_k_typ_voltages), - .volt_table = ldo_k_typ_voltages, - .type = regulator_voltage, - .owner = this_module, - .enable_time = 200, - }, - { - .name = "ldo_ext", - .id = ab3100_ldo_ext, - .ops = ®ulator_ops_external, - .type = regulator_voltage, - .owner = this_module, - }, - { - .name = "buck", - .id = ab3100_buck, - .ops = ®ulator_ops_variable_sleepable, - .n_voltages = array_size(ldo_e_buck_typ_voltages), - .volt_table = ldo_e_buck_typ_voltages, - .type = regulator_voltage, - .owner = this_module, - .enable_time = 1000, - }, -}; - -static int ab3100_regulator_register(struct platform_device *pdev, - struct ab3100_platform_data *plfdata, - struct regulator_init_data *init_data, - struct device_node *np, - unsigned long id) -{ - const struct regulator_desc *desc; - struct ab3100_regulator *reg; - struct regulator_dev *rdev; - struct regulator_config config = { }; - int err, i; - - for (i = 0; i < ab3100_num_regulators; i++) { - desc = &ab3100_regulator_desc[i]; - if (desc->id == id) - break; - } - if (desc->id != id) - return -enodev; - - /* same index used for this array */ - reg = &ab3100_regulators[i]; - - /* - * initialize per-regulator struct. - * inherit platform data, this comes down from the - * i2c boarddata, from the machine. so if you want to - * see what it looks like for a certain machine, go - * into the machine i2c setup. - */ - reg->dev = &pdev->dev; - if (plfdata) { - reg->plfdata = plfdata; - config.init_data = &plfdata->reg_constraints[i]; - } else if (np) { - config.of_node = np; - config.init_data = init_data; - } - config.dev = &pdev->dev; - config.driver_data = reg; - - rdev = devm_regulator_register(&pdev->dev, desc, &config); - if (is_err(rdev)) { - err = ptr_err(rdev); - dev_err(&pdev->dev, - "%s: failed to register regulator %s err %d ", - __func__, desc->name, - err); - return err; - } - - return 0; -} - -static struct of_regulator_match ab3100_regulator_matches[] = { - { .name = "ab3100_ldo_a", .driver_data = (void *) ab3100_ldo_a, }, - { .name = "ab3100_ldo_c", .driver_data = (void *) ab3100_ldo_c, }, - { .name = "ab3100_ldo_d", .driver_data = (void *) ab3100_ldo_d, }, - { .name = "ab3100_ldo_e", .driver_data = (void *) ab3100_ldo_e, }, - { .name = "ab3100_ldo_f", .driver_data = (void *) ab3100_ldo_f }, - { .name = "ab3100_ldo_g", .driver_data = (void *) ab3100_ldo_g }, - { .name = "ab3100_ldo_h", .driver_data = (void *) ab3100_ldo_h }, - { .name = "ab3100_ldo_k", .driver_data = (void *) ab3100_ldo_k }, - { .name = "ab3100_ext", .driver_data = (void *) ab3100_ldo_ext }, - { .name = "ab3100_buck", .driver_data = (void *) ab3100_buck }, -}; - -/* - * initial settings of ab3100 registers. - * common for below ldo regulator settings are that - * bit 7-5 controls voltage. bit 4 turns regulator on(1) or off(0). - * bit 3-2 controls sleep enable and bit 1-0 controls sleep mode. - */ -/* ldo_a 0x16: 2.75v, on, sleep_a, sleep off gnd */ -#define ldo_a_setting 0x16 -/* ldo_c 0x10: 2.65v, on, sleep_a or b, sleep full power */ -#define ldo_c_setting 0x10 -/* ldo_d 0x10: 2.65v, on, sleep mode not used */ -#define ldo_d_setting 0x10 -/* ldo_e 0x10: 1.8v, on, sleep_a or b, sleep full power */ -#define ldo_e_setting 0x10 -/* ldo_e sleep 0x00: 1.8v, not used, sleep_a or b, not used */ -#define ldo_e_sleep_setting 0x00 -/* ldo_f 0xd0: 2.5v, on, sleep_a or b, sleep full power */ -#define ldo_f_setting 0xd0 -/* ldo_g 0x00: 2.85v, off, sleep_a or b, sleep full power */ -#define ldo_g_setting 0x00 -/* ldo_h 0x18: 2.75v, on, sleep_b, sleep full power */ -#define ldo_h_setting 0x18 -/* ldo_k 0x00: 2.75v, off, sleep_a or b, sleep full power */ -#define ldo_k_setting 0x00 -/* ldo_ext 0x00: voltage not set, off, not used, not used */ -#define ldo_ext_setting 0x00 -/* buck 0x7d: 1.2v, on, sleep_a and b, sleep low power */ -#define buck_setting 0x7d -/* buck sleep 0xac: 1.05v, not used, sleep_a and b, not used */ -#define buck_sleep_setting 0xac - -static const u8 ab3100_reg_initvals[] = { - ldo_a_setting, - ldo_c_setting, - ldo_e_setting, - ldo_e_sleep_setting, - ldo_f_setting, - ldo_g_setting, - ldo_h_setting, - ldo_k_setting, - ldo_ext_setting, - buck_setting, - buck_sleep_setting, - ldo_d_setting, -}; - -static int -ab3100_regulator_of_probe(struct platform_device *pdev, struct device_node *np) -{ - int err, i; - - /* - * set up the regulator registers, as was previously done with - * platform data. - */ - /* set up regulators */ - for (i = 0; i < array_size(ab3100_reg_init_order); i++) { - err = abx500_set_register_interruptible(&pdev->dev, 0, - ab3100_reg_init_order[i], - ab3100_reg_initvals[i]); - if (err) { - dev_err(&pdev->dev, "regulator initialization failed with error %d ", - err); - return err; - } - } - - for (i = 0; i < array_size(ab3100_regulator_matches); i++) { - err = ab3100_regulator_register( - pdev, null, ab3100_regulator_matches[i].init_data, - ab3100_regulator_matches[i].of_node, - (unsigned long)ab3100_regulator_matches[i].driver_data); - if (err) - return err; - } - - return 0; -} - - -static int ab3100_regulators_probe(struct platform_device *pdev) -{ - struct ab3100_platform_data *plfdata = dev_get_platdata(&pdev->dev); - struct device_node *np = pdev->dev.of_node; - int err = 0; - u8 data; - int i; - - /* check chip state */ - err = abx500_get_register_interruptible(&pdev->dev, 0, - ab3100_ldo_d, &data); - if (err) { - dev_err(&pdev->dev, "could not read initial status of ldo_d "); - return err; - } - if (data & 0x10) - dev_notice(&pdev->dev, - "chip is already in active mode (warm start) "); - else - dev_notice(&pdev->dev, - "chip is in inactive mode (cold start) "); - - if (np) { - err = of_regulator_match(&pdev->dev, np, - ab3100_regulator_matches, - array_size(ab3100_regulator_matches)); - if (err < 0) { - dev_err(&pdev->dev, - "error parsing regulator init data: %d ", err); - return err; - } - return ab3100_regulator_of_probe(pdev, np); - } - - /* set up regulators */ - for (i = 0; i < array_size(ab3100_reg_init_order); i++) { - err = abx500_set_register_interruptible(&pdev->dev, 0, - ab3100_reg_init_order[i], - plfdata->reg_initvals[i]); - if (err) { - dev_err(&pdev->dev, "regulator initialization failed with error %d ", - err); - return err; - } - } - - /* register the regulators */ - for (i = 0; i < ab3100_num_regulators; i++) { - const struct regulator_desc *desc = &ab3100_regulator_desc[i]; - - err = ab3100_regulator_register(pdev, plfdata, null, null, - desc->id); - if (err) - return err; - } - - return 0; -} - -static struct platform_driver ab3100_regulators_driver = { - .driver = { - .name = "ab3100-regulators", - }, - .probe = ab3100_regulators_probe, -}; - -static __init int ab3100_regulators_init(void) -{ - return platform_driver_register(&ab3100_regulators_driver); -} - -static __exit void ab3100_regulators_exit(void) -{ - platform_driver_unregister(&ab3100_regulators_driver); -} - -subsys_initcall(ab3100_regulators_init); -module_exit(ab3100_regulators_exit); - -module_author("mattias wallin <mattias.wallin@stericsson.com>"); -module_description("ab3100 regulator driver"); -module_license("gpl"); -module_alias("platform:ab3100-regulators");
|
Voltage, current regulators, power capping, power supply
|
d93d6f52bd9e3aa6f37b7ea5657e4bee50a4b0a4
|
arnd bergmann linus walleij linus walleij linaro org
|
drivers
|
regulator
| |
thermal/drivers/tango: remove tango driver
|
the tango platform is getting removed, so the driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove tango driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['thermal: ']
|
['txt', 'kconfig', 'c', 'makefile']
| 4
| 0
| 153
|
--- diff --git a/documentation/devicetree/bindings/thermal/tango-thermal.txt b/documentation/devicetree/bindings/thermal/tango-thermal.txt --- a/documentation/devicetree/bindings/thermal/tango-thermal.txt +++ /dev/null -* tango thermal - -the smp8758 soc includes 3 instances of this temperature sensor -(in the cpu, video decoder, and pcie controller). - -required properties: -- #thermal-sensor-cells: should be 0 (see documentation/devicetree/bindings/thermal/thermal-sensor.yaml) -- compatible: "sigma,smp8758-thermal" -- reg: address range of the thermal registers - -example: - - cpu_temp: thermal@920100 { - #thermal-sensor-cells = <0>; - compatible = "sigma,smp8758-thermal"; - reg = <0x920100 12>; - }; diff --git a/drivers/thermal/kconfig b/drivers/thermal/kconfig --- a/drivers/thermal/kconfig +++ b/drivers/thermal/kconfig -config tango_thermal - tristate "tango thermal management" - depends on arch_tango || compile_test - help - enable the tango thermal driver, which supports the primitive - temperature sensor embedded in tango chips since the smp8758. - this sensor only generates a 1-bit signal to indicate whether - the die temperature exceeds a programmable threshold. - diff --git a/drivers/thermal/makefile b/drivers/thermal/makefile --- a/drivers/thermal/makefile +++ b/drivers/thermal/makefile -obj-$(config_tango_thermal) += tango_thermal.o diff --git a/drivers/thermal/tango_thermal.c b/drivers/thermal/tango_thermal.c --- a/drivers/thermal/tango_thermal.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -#include <linux/io.h> -#include <linux/delay.h> -#include <linux/module.h> -#include <linux/thermal.h> -#include <linux/platform_device.h> - -/* - * according to a data sheet draft, "this temperature sensor uses a bandgap - * type of circuit to compare a voltage which has a negative temperature - * coefficient with a voltage that is proportional to absolute temperature. - * a resistor bank allows 41 different temperature thresholds to be selected - * and the logic output will then indicate whether the actual die temperature - * lies above or below the selected threshold." - */ - -#define tempsi_cmd 0 -#define tempsi_res 4 -#define tempsi_cfg 8 - -#define cmd_off 0 -#define cmd_on 1 -#define cmd_read 2 - -#define idx_min 15 -#define idx_max 40 - -struct tango_thermal_priv { - void __iomem *base; - int thresh_idx; -}; - -static bool temp_above_thresh(void __iomem *base, int thresh_idx) -{ - writel(cmd_read | thresh_idx << 8, base + tempsi_cmd); - usleep_range(10, 20); - writel(cmd_read | thresh_idx << 8, base + tempsi_cmd); - - return readl(base + tempsi_res); -} - -static int tango_get_temp(void *arg, int *res) -{ - struct tango_thermal_priv *priv = arg; - int idx = priv->thresh_idx; - - if (temp_above_thresh(priv->base, idx)) { - /* search upward by incrementing thresh_idx */ - while (idx < idx_max && temp_above_thresh(priv->base, ++idx)) - cpu_relax(); - idx = idx - 1; /* always return lower bound */ - } else { - /* search downward by decrementing thresh_idx */ - while (idx > idx_min && !temp_above_thresh(priv->base, --idx)) - cpu_relax(); - } - - *res = (idx * 9 / 2 - 38) * 1000; /* millidegrees celsius */ - priv->thresh_idx = idx; - - return 0; -} - -static const struct thermal_zone_of_device_ops ops = { - .get_temp = tango_get_temp, -}; - -static void tango_thermal_init(struct tango_thermal_priv *priv) -{ - writel(0, priv->base + tempsi_cfg); - writel(cmd_on, priv->base + tempsi_cmd); -} - -static int tango_thermal_probe(struct platform_device *pdev) -{ - struct resource *res; - struct tango_thermal_priv *priv; - struct thermal_zone_device *tzdev; - - priv = devm_kzalloc(&pdev->dev, sizeof(*priv), gfp_kernel); - if (!priv) - return -enomem; - - res = platform_get_resource(pdev, ioresource_mem, 0); - priv->base = devm_ioremap_resource(&pdev->dev, res); - if (is_err(priv->base)) - return ptr_err(priv->base); - - platform_set_drvdata(pdev, priv); - priv->thresh_idx = idx_min; - tango_thermal_init(priv); - - tzdev = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, priv, &ops); - return ptr_err_or_zero(tzdev); -} - -static int __maybe_unused tango_thermal_resume(struct device *dev) -{ - tango_thermal_init(dev_get_drvdata(dev)); - return 0; -} - -static simple_dev_pm_ops(tango_thermal_pm, null, tango_thermal_resume); - -static const struct of_device_id tango_sensor_ids[] = { - { - .compatible = "sigma,smp8758-thermal", - }, - { /* sentinel */ } -}; -module_device_table(of, tango_sensor_ids); - -static struct platform_driver tango_thermal_driver = { - .probe = tango_thermal_probe, - .driver = { - .name = "tango-thermal", - .of_match_table = tango_sensor_ids, - .pm = &tango_thermal_pm, - }, -}; - -module_platform_driver(tango_thermal_driver); - -module_license("gpl"); -module_author("sigma designs"); -module_description("tango temperature sensor");
|
Voltage, current regulators, power capping, power supply
|
8fefe3ce6b7d11a551d98557d5dfc5eba6477409
|
arnd bergmann mans rullgard mans mansr com
|
drivers
|
thermal
|
bindings, thermal
|
thermal/drivers/zx: remove zx driver
|
the zte zx platform is getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove zx driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['thermal: ']
|
['txt', 'kconfig', 'c', 'makefile']
| 4
| 0
| 381
|
--- diff --git a/documentation/devicetree/bindings/thermal/zx2967-thermal.txt b/documentation/devicetree/bindings/thermal/zx2967-thermal.txt --- a/documentation/devicetree/bindings/thermal/zx2967-thermal.txt +++ /dev/null -* zte zx2967 family thermal - -required properties: -- compatible: should be one of the following. - * zte,zx296718-thermal -- reg: physical base address of the controller and length of memory mapped - region. -- clocks : pairs of phandle and specifier referencing the controller's clocks. -- clock-names: "topcrm" for the topcrm clock. - "apb" for the apb clock. -- #thermal-sensor-cells: must be 0. - -please note: slope coefficient defined in thermal-zones section need to be -multiplied by 1000. - -example for tempsensor: - - tempsensor: tempsensor@148a000 { - compatible = "zte,zx296718-thermal"; - reg = <0x0148a000 0x20>; - clocks = <&topcrm tempsensor_gate>, <&audiocrm audio_ts_pclk>; - clock-names = "topcrm", "apb"; - #thermal-sensor-cells = <0>; - }; - -example for cooling device: - - cooling_dev: cooling_dev { - cluster0_cooling_dev: cluster0-cooling-dev { - #cooling-cells = <2>; - cpumask = <0xf>; - capacitance = <1500>; - }; - - cluster1_cooling_dev: cluster1-cooling-dev { - #cooling-cells = <2>; - cpumask = <0x30>; - capacitance = <2000>; - }; - }; - -example for thermal zones: - - thermal-zones { - zx296718_thermal: zx296718_thermal { - polling-delay-passive = <500>; - polling-delay = <1000>; - sustainable-power = <6500>; - - thermal-sensors = <&tempsensor 0>; - /* - * slope need to be multiplied by 1000. - */ - coefficients = <1951 (-922)>; - - trips { - trip0: switch_on_temperature { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip1: desired_temperature { - temperature = <100000>; - hysteresis = <2000>; - type = "passive"; - }; - - crit: critical_temperature { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&trip0>; - cooling-device = <&gpu 2 5>; - }; - - map1 { - trip = <&trip0>; - cooling-device = <&cluster0_cooling_dev 1 2>; - }; - - map2 { - trip = <&trip1>; - cooling-device = <&cluster0_cooling_dev 1 2>; - }; - - map3 { - trip = <&crit>; - cooling-device = <&cluster0_cooling_dev 1 2>; - }; - - map4 { - trip = <&trip0>; - cooling-device = <&cluster1_cooling_dev 1 2>; - contribution = <9000>; - }; - - map5 { - trip = <&trip1>; - cooling-device = <&cluster1_cooling_dev 1 2>; - contribution = <4096>; - }; - - map6 { - trip = <&crit>; - cooling-device = <&cluster1_cooling_dev 1 2>; - contribution = <4096>; - }; - }; - }; - }; diff --git a/drivers/thermal/kconfig b/drivers/thermal/kconfig --- a/drivers/thermal/kconfig +++ b/drivers/thermal/kconfig -config zx2967_thermal - tristate "thermal sensors on zx2967 soc" - depends on arch_zx || compile_test - help - enable the zx2967 thermal sensors driver, which supports - the primitive temperature sensor embedded in zx2967 socs. - this sensor generates the real time die temperature. - diff --git a/drivers/thermal/makefile b/drivers/thermal/makefile --- a/drivers/thermal/makefile +++ b/drivers/thermal/makefile -obj-$(config_zx2967_thermal) += zx2967_thermal.o diff --git a/drivers/thermal/zx2967_thermal.c b/drivers/thermal/zx2967_thermal.c --- a/drivers/thermal/zx2967_thermal.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * zte's zx2967 family thermal sensor driver - * - * copyright (c) 2017 zte ltd. - * - * author: baoyou xie <baoyou.xie@linaro.org> - */ - -#include <linux/clk.h> -#include <linux/device.h> -#include <linux/err.h> -#include <linux/iopoll.h> -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/thermal.h> - -/* power mode: 0->low 1->high */ -#define zx2967_thermal_power_mode 0 -#define zx2967_power_mode_low 0 -#define zx2967_power_mode_high 1 - -/* dcf control register */ -#define zx2967_thermal_dcf 0x4 -#define zx2967_dcf_en bit(1) -#define zx2967_dcf_freeze bit(0) - -/* selection register */ -#define zx2967_thermal_sel 0x8 - -/* control register */ -#define zx2967_thermal_ctrl 0x10 - -#define zx2967_thermal_ready bit(12) -#define zx2967_thermal_temp_mask genmask(11, 0) -#define zx2967_thermal_id_mask 0x18 -#define zx2967_thermal_id 0x10 - -#define zx2967_get_temp_timeout_us (100 * 1024) - -/** - * struct zx2967_thermal_priv - zx2967 thermal sensor private structure - * @tzd: struct thermal_zone_device where the sensor is registered - * @lock: prevents read sensor in parallel - * @clk_topcrm: topcrm clk structure - * @clk_apb: apb clk structure - * @regs: pointer to base address of the thermal sensor - * @dev: struct device pointer - */ - -struct zx2967_thermal_priv { - struct thermal_zone_device *tzd; - struct mutex lock; - struct clk *clk_topcrm; - struct clk *clk_apb; - void __iomem *regs; - struct device *dev; -}; - -static int zx2967_thermal_get_temp(void *data, int *temp) -{ - void __iomem *regs; - struct zx2967_thermal_priv *priv = data; - u32 val; - int ret; - - if (!priv->tzd) - return -eagain; - - regs = priv->regs; - mutex_lock(&priv->lock); - writel_relaxed(zx2967_power_mode_low, - regs + zx2967_thermal_power_mode); - writel_relaxed(zx2967_dcf_en, regs + zx2967_thermal_dcf); - - val = readl_relaxed(regs + zx2967_thermal_sel); - val &= ~zx2967_thermal_id_mask; - val |= zx2967_thermal_id; - writel_relaxed(val, regs + zx2967_thermal_sel); - - /* - * must wait for a while, surely it's a bit odd. - * otherwise temperature value we got has a few deviation, even if - * the thermal_ready bit is set. - */ - usleep_range(100, 300); - ret = readx_poll_timeout(readl, regs + zx2967_thermal_ctrl, - val, val & zx2967_thermal_ready, 300, - zx2967_get_temp_timeout_us); - if (ret) { - dev_err(priv->dev, "thermal sensor data timeout "); - goto unlock; - } - - writel_relaxed(zx2967_dcf_freeze | zx2967_dcf_en, - regs + zx2967_thermal_dcf); - val = readl_relaxed(regs + zx2967_thermal_ctrl) - & zx2967_thermal_temp_mask; - writel_relaxed(zx2967_power_mode_high, - regs + zx2967_thermal_power_mode); - - /* - * calculate temperature - * in dts, slope is multiplied by 1000. - */ - *temp = div_round_closest(((s32)val + priv->tzd->tzp->offset) * 1000, - priv->tzd->tzp->slope); - -unlock: - mutex_unlock(&priv->lock); - return ret; -} - -static const struct thermal_zone_of_device_ops zx2967_of_thermal_ops = { - .get_temp = zx2967_thermal_get_temp, -}; - -static int zx2967_thermal_probe(struct platform_device *pdev) -{ - struct zx2967_thermal_priv *priv; - struct resource *res; - int ret; - - priv = devm_kzalloc(&pdev->dev, sizeof(*priv), gfp_kernel); - if (!priv) - return -enomem; - - res = platform_get_resource(pdev, ioresource_mem, 0); - priv->regs = devm_ioremap_resource(&pdev->dev, res); - if (is_err(priv->regs)) - return ptr_err(priv->regs); - - priv->clk_topcrm = devm_clk_get(&pdev->dev, "topcrm"); - if (is_err(priv->clk_topcrm)) { - ret = ptr_err(priv->clk_topcrm); - dev_err(&pdev->dev, "failed to get topcrm clock: %d ", ret); - return ret; - } - - ret = clk_prepare_enable(priv->clk_topcrm); - if (ret) { - dev_err(&pdev->dev, "failed to enable topcrm clock: %d ", - ret); - return ret; - } - - priv->clk_apb = devm_clk_get(&pdev->dev, "apb"); - if (is_err(priv->clk_apb)) { - ret = ptr_err(priv->clk_apb); - dev_err(&pdev->dev, "failed to get apb clock: %d ", ret); - goto disable_clk_topcrm; - } - - ret = clk_prepare_enable(priv->clk_apb); - if (ret) { - dev_err(&pdev->dev, "failed to enable apb clock: %d ", - ret); - goto disable_clk_topcrm; - } - - mutex_init(&priv->lock); - priv->tzd = thermal_zone_of_sensor_register(&pdev->dev, - 0, priv, &zx2967_of_thermal_ops); - - if (is_err(priv->tzd)) { - ret = ptr_err(priv->tzd); - dev_err(&pdev->dev, "failed to register sensor: %d ", ret); - goto disable_clk_all; - } - - if (priv->tzd->tzp->slope == 0) { - thermal_zone_of_sensor_unregister(&pdev->dev, priv->tzd); - dev_err(&pdev->dev, "coefficients of sensor is invalid "); - ret = -einval; - goto disable_clk_all; - } - - priv->dev = &pdev->dev; - platform_set_drvdata(pdev, priv); - - return 0; - -disable_clk_all: - clk_disable_unprepare(priv->clk_apb); -disable_clk_topcrm: - clk_disable_unprepare(priv->clk_topcrm); - return ret; -} - -static int zx2967_thermal_exit(struct platform_device *pdev) -{ - struct zx2967_thermal_priv *priv = platform_get_drvdata(pdev); - - thermal_zone_of_sensor_unregister(&pdev->dev, priv->tzd); - clk_disable_unprepare(priv->clk_topcrm); - clk_disable_unprepare(priv->clk_apb); - - return 0; -} - -static const struct of_device_id zx2967_thermal_id_table[] = { - { .compatible = "zte,zx296718-thermal" }, - {} -}; -module_device_table(of, zx2967_thermal_id_table); - -#ifdef config_pm_sleep -static int zx2967_thermal_suspend(struct device *dev) -{ - struct zx2967_thermal_priv *priv = dev_get_drvdata(dev); - - if (priv && priv->clk_topcrm) - clk_disable_unprepare(priv->clk_topcrm); - - if (priv && priv->clk_apb) - clk_disable_unprepare(priv->clk_apb); - - return 0; -} - -static int zx2967_thermal_resume(struct device *dev) -{ - struct zx2967_thermal_priv *priv = dev_get_drvdata(dev); - int error; - - error = clk_prepare_enable(priv->clk_topcrm); - if (error) - return error; - - error = clk_prepare_enable(priv->clk_apb); - if (error) { - clk_disable_unprepare(priv->clk_topcrm); - return error; - } - - return 0; -} -#endif - -static simple_dev_pm_ops(zx2967_thermal_pm_ops, - zx2967_thermal_suspend, zx2967_thermal_resume); - -static struct platform_driver zx2967_thermal_driver = { - .probe = zx2967_thermal_probe, - .remove = zx2967_thermal_exit, - .driver = { - .name = "zx2967_thermal", - .of_match_table = zx2967_thermal_id_table, - .pm = &zx2967_thermal_pm_ops, - }, -}; -module_platform_driver(zx2967_thermal_driver); - -module_author("baoyou xie <baoyou.xie@linaro.org>"); -module_description("zte zx2967 thermal driver"); -module_license("gpl v2");
|
Voltage, current regulators, power capping, power supply
|
73da3f0cca94555d08d62b60ec9b8b9582bc1313
|
arnd bergmann
|
drivers
|
thermal
|
bindings, thermal
|
thermal: qcom: add support for adc-tm5 pmic thermal monitor
|
add support for thermal monitoring part of pmic5. this part is closely coupled with adc, using it's channels directly. adc-tm support generating interrupts on adc value crossing low or high voltage bounds, which is used to support thermal trip points.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for adc-tm5 pmic thermal monitor
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['thermal: ', 'qcom']
|
['kconfig', 'h', 'c', 'makefile']
| 5
| 688
| 0
|
--- diff --git a/drivers/iio/adc/qcom-vadc-common.c b/drivers/iio/adc/qcom-vadc-common.c --- a/drivers/iio/adc/qcom-vadc-common.c +++ b/drivers/iio/adc/qcom-vadc-common.c +static s32 qcom_vadc_map_temp_voltage(const struct vadc_map_pt *pts, + u32 tablesize, int input) +{ + u32 i = 0; + + /* + * table must be sorted, find the interval of 'y' which contains value + * 'input' and map it to proper 'x' value + */ + while (i < tablesize && pts[i].y < input) + i++; + + if (i == 0) + return pts[0].x; + if (i == tablesize) + return pts[tablesize - 1].x; + + /* interpolate linearly */ + return fixp_linear_interpolate(pts[i - 1].y, pts[i - 1].x, + pts[i].y, pts[i].x, input); +} + +/* convert voltage to adc code, using 1.875v reference */ +static u16 qcom_vadc_scale_voltage_code(s32 voltage, + const struct vadc_prescale_ratio *prescale, + const u32 full_scale_code_volt, + unsigned int factor) +{ + s64 volt = voltage; + s64 adc_vdd_ref_mv = 1875; /* reference voltage */ + + volt *= prescale->num * factor * full_scale_code_volt; + volt = div64_s64(volt, (s64)prescale->den * adc_vdd_ref_mv * 1000); + + return volt; +} + +u16 qcom_adc_tm5_temp_volt_scale(unsigned int prescale_ratio, + u32 full_scale_code_volt, int temp) +{ + const struct vadc_prescale_ratio *prescale = &adc5_prescale_ratios[prescale_ratio]; + s32 voltage; + + voltage = qcom_vadc_map_temp_voltage(adcmap_100k_104ef_104fb_1875_vref, + array_size(adcmap_100k_104ef_104fb_1875_vref), + temp); + return qcom_vadc_scale_voltage_code(voltage, prescale, full_scale_code_volt, 1000); +} +export_symbol(qcom_adc_tm5_temp_volt_scale); + diff --git a/drivers/thermal/qcom/kconfig b/drivers/thermal/qcom/kconfig --- a/drivers/thermal/qcom/kconfig +++ b/drivers/thermal/qcom/kconfig +config qcom_spmi_adc_tm5 + tristate "qualcomm spmi pmic thermal monitor adc5" + depends on of && spmi && iio + select regmap_spmi + select qcom_vadc_common + help + this enables the thermal driver for the adc thermal monitoring + device. it shows up as a thermal zone with multiple trip points. + thermal client sets threshold temperature for both warm and cool and + gets updated when a threshold is reached. + diff --git a/drivers/thermal/qcom/makefile b/drivers/thermal/qcom/makefile --- a/drivers/thermal/qcom/makefile +++ b/drivers/thermal/qcom/makefile +obj-$(config_qcom_spmi_adc_tm5) += qcom-spmi-adc-tm5.o diff --git a/drivers/thermal/qcom/qcom-spmi-adc-tm5.c b/drivers/thermal/qcom/qcom-spmi-adc-tm5.c --- /dev/null +++ b/drivers/thermal/qcom/qcom-spmi-adc-tm5.c +// spdx-license-identifier: gpl-2.0-only +/* + * copyright (c) 2020 linaro limited + * + * based on original driver: + * copyright (c) 2012-2020, the linux foundation. all rights reserved. + */ +#include <linux/bitfield.h> +#include <linux/iio/adc/qcom-vadc-common.h> +#include <linux/iio/consumer.h> +#include <linux/interrupt.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/thermal.h> + +/* + * thermal monitoring block consists of 8 (adc_tm5_num_channels) channels. each + * channel is programmed to use one of adc channels for voltage comparison. + * voltages are programmed using adc codes, so we have to convert temp to + * voltage and then to adc code value. + * + * configuration of tm channels must match configuration of corresponding adc + * channels. + */ + +#define adc5_max_channel 0xc0 +#define adc_tm5_num_channels 8 + +#define adc_tm5_status_low 0x0a + +#define adc_tm5_status_high 0x0b + +#define adc_tm5_num_btm 0x0f + +#define adc_tm5_adc_dig_param 0x42 + +#define adc_tm5_fast_avg_ctl (adc_tm5_adc_dig_param + 1) +#define adc_tm5_fast_avg_en bit(7) + +#define adc_tm5_meas_interval_ctl (adc_tm5_adc_dig_param + 2) +#define adc_tm5_timer1 3 /* 3.9ms */ + +#define adc_tm5_meas_interval_ctl2 (adc_tm5_adc_dig_param + 3) +#define adc_tm5_meas_interval_ctl2_mask 0xf0 +#define adc_tm5_timer2 10 /* 1 second */ +#define adc_tm5_meas_interval_ctl3_mask 0xf +#define adc_tm5_timer3 4 /* 4 second */ + +#define adc_tm_en_ctl1 0x46 +#define adc_tm_en bit(7) +#define adc_tm_conv_req 0x47 +#define adc_tm_conv_req_en bit(7) + +#define adc_tm5_m_chan_base 0x60 + +#define adc_tm5_m_adc_ch_sel_ctl(n) (adc_tm5_m_chan_base + ((n) * 8) + 0) +#define adc_tm5_m_low_thr0(n) (adc_tm5_m_chan_base + ((n) * 8) + 1) +#define adc_tm5_m_low_thr1(n) (adc_tm5_m_chan_base + ((n) * 8) + 2) +#define adc_tm5_m_high_thr0(n) (adc_tm5_m_chan_base + ((n) * 8) + 3) +#define adc_tm5_m_high_thr1(n) (adc_tm5_m_chan_base + ((n) * 8) + 4) +#define adc_tm5_m_meas_interval_ctl(n) (adc_tm5_m_chan_base + ((n) * 8) + 5) +#define adc_tm5_m_ctl(n) (adc_tm5_m_chan_base + ((n) * 8) + 6) +#define adc_tm5_m_ctl_hw_settle_delay_mask 0xf +#define adc_tm5_m_ctl_cal_sel_mask 0x30 +#define adc_tm5_m_ctl_cal_val 0x40 +#define adc_tm5_m_en(n) (adc_tm5_m_chan_base + ((n) * 8) + 7) +#define adc_tm5_m_meas_en bit(7) +#define adc_tm5_m_high_thr_int_en bit(1) +#define adc_tm5_m_low_thr_int_en bit(0) + +enum adc5_timer_select { + adc5_timer_sel_1 = 0, + adc5_timer_sel_2, + adc5_timer_sel_3, + adc5_timer_sel_none, +}; + +struct adc_tm5_data { + const u32 full_scale_code_volt; + unsigned int *decimation; + unsigned int *hw_settle; +}; + +enum adc_tm5_cal_method { + adc_tm5_no_cal = 0, + adc_tm5_ratiometric_cal, + adc_tm5_absolute_cal +}; + +struct adc_tm5_chip; + +/** + * struct adc_tm5_channel - adc thermal monitoring channel data. + * @channel: channel number. + * @adc_channel: corresponding adc channel number. + * @cal_method: calibration method. + * @prescale: channel scaling performed on the input signal. + * @hw_settle_time: the time between amux being configured and the + * start of conversion. + * @iio: iio channel instance used by this channel. + * @chip: adc tm chip instance. + * @tzd: thermal zone device used by this channel. + */ +struct adc_tm5_channel { + unsigned int channel; + unsigned int adc_channel; + enum adc_tm5_cal_method cal_method; + unsigned int prescale; + unsigned int hw_settle_time; + struct iio_channel *iio; + struct adc_tm5_chip *chip; + struct thermal_zone_device *tzd; +}; + +/** + * struct adc_tm5_chip - adc thermal monitoring properties + * @regmap: spmi adc5 thermal monitoring peripheral register map field. + * @dev: spmi adc5 device. + * @data: software configuration data. + * @channels: array of adc tm channel data. + * @nchannels: amount of channels defined/allocated + * @decimation: sampling rate supported for the channel. + * @avg_samples: ability to provide single result from the adc + * that is an average of multiple measurements. + * @base: base address of tm registers. + */ +struct adc_tm5_chip { + struct regmap *regmap; + struct device *dev; + const struct adc_tm5_data *data; + struct adc_tm5_channel *channels; + unsigned int nchannels; + unsigned int decimation; + unsigned int avg_samples; + u16 base; +}; + +static const struct adc_tm5_data adc_tm5_data_pmic = { + .full_scale_code_volt = 0x70e4, + .decimation = (unsigned int []) { 250, 420, 840 }, + .hw_settle = (unsigned int []) { 15, 100, 200, 300, 400, 500, 600, 700, + 1000, 2000, 4000, 8000, 16000, 32000, + 64000, 128000 }, +}; + +static int adc_tm5_read(struct adc_tm5_chip *adc_tm, u16 offset, u8 *data, int len) +{ + return regmap_bulk_read(adc_tm->regmap, adc_tm->base + offset, data, len); +} + +static int adc_tm5_write(struct adc_tm5_chip *adc_tm, u16 offset, u8 *data, int len) +{ + return regmap_bulk_write(adc_tm->regmap, adc_tm->base + offset, data, len); +} + +static int adc_tm5_reg_update(struct adc_tm5_chip *adc_tm, u16 offset, u8 mask, u8 val) +{ + return regmap_write_bits(adc_tm->regmap, adc_tm->base + offset, mask, val); +} + +static irqreturn_t adc_tm5_isr(int irq, void *data) +{ + struct adc_tm5_chip *chip = data; + u8 status_low, status_high, ctl; + int ret, i; + + ret = adc_tm5_read(chip, adc_tm5_status_low, &status_low, sizeof(status_low)); + if (unlikely(ret)) { + dev_err(chip->dev, "read status low failed: %d ", ret); + return irq_handled; + } + + ret = adc_tm5_read(chip, adc_tm5_status_high, &status_high, sizeof(status_high)); + if (unlikely(ret)) { + dev_err(chip->dev, "read status high failed: %d ", ret); + return irq_handled; + } + + for (i = 0; i < chip->nchannels; i++) { + bool upper_set = false, lower_set = false; + unsigned int ch = chip->channels[i].channel; + + /* no tzd, we warned at the boot time */ + if (!chip->channels[i].tzd) + continue; + + ret = adc_tm5_read(chip, adc_tm5_m_en(ch), &ctl, sizeof(ctl)); + if (unlikely(ret)) { + dev_err(chip->dev, "ctl read failed: %d, channel %d ", ret, i); + continue; + } + + if (!(ctl & adc_tm5_m_meas_en)) + continue; + + lower_set = (status_low & bit(ch)) && + (ctl & adc_tm5_m_low_thr_int_en); + + upper_set = (status_high & bit(ch)) && + (ctl & adc_tm5_m_high_thr_int_en); + + if (upper_set || lower_set) + thermal_zone_device_update(chip->channels[i].tzd, + thermal_event_unspecified); + } + + return irq_handled; +} + +static int adc_tm5_get_temp(void *data, int *temp) +{ + struct adc_tm5_channel *channel = data; + int ret; + + if (!channel || !channel->iio) + return -einval; + + ret = iio_read_channel_processed(channel->iio, temp); + if (ret < 0) + return ret; + + if (ret != iio_val_int) + return -einval; + + return 0; +} + +static int adc_tm5_disable_channel(struct adc_tm5_channel *channel) +{ + struct adc_tm5_chip *chip = channel->chip; + unsigned int reg = adc_tm5_m_en(channel->channel); + + return adc_tm5_reg_update(chip, reg, + adc_tm5_m_meas_en | + adc_tm5_m_high_thr_int_en | + adc_tm5_m_low_thr_int_en, + 0); +} + +static int adc_tm5_enable(struct adc_tm5_chip *chip) +{ + int ret; + u8 data; + + data = adc_tm_en; + ret = adc_tm5_write(chip, adc_tm_en_ctl1, &data, sizeof(data)); + if (ret < 0) { + dev_err(chip->dev, "adc-tm enable failed "); + return ret; + } + + data = adc_tm_conv_req_en; + ret = adc_tm5_write(chip, adc_tm_conv_req, &data, sizeof(data)); + if (ret < 0) { + dev_err(chip->dev, "adc-tm request conversion failed "); + return ret; + } + + return 0; +} + +static int adc_tm5_configure(struct adc_tm5_channel *channel, int low, int high) +{ + struct adc_tm5_chip *chip = channel->chip; + u8 buf[8]; + u16 reg = adc_tm5_m_adc_ch_sel_ctl(channel->channel); + int ret; + + ret = adc_tm5_read(chip, reg, buf, sizeof(buf)); + if (ret) { + dev_err(chip->dev, "channel %d params read failed: %d ", channel->channel, ret); + return ret; + } + + buf[0] = channel->adc_channel; + + /* high temperature corresponds to low voltage threshold */ + if (high != int_max) { + u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale, + chip->data->full_scale_code_volt, high); + + buf[1] = adc_code & 0xff; + buf[2] = adc_code >> 8; + buf[7] |= adc_tm5_m_low_thr_int_en; + } else { + buf[7] &= ~adc_tm5_m_low_thr_int_en; + } + + /* low temperature corresponds to high voltage threshold */ + if (low != -int_max) { + u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale, + chip->data->full_scale_code_volt, low); + + buf[3] = adc_code & 0xff; + buf[4] = adc_code >> 8; + buf[7] |= adc_tm5_m_high_thr_int_en; + } else { + buf[7] &= ~adc_tm5_m_high_thr_int_en; + } + + buf[5] = adc5_timer_sel_2; + + /* set calibration select, hw_settle delay */ + buf[6] &= ~adc_tm5_m_ctl_hw_settle_delay_mask; + buf[6] |= field_prep(adc_tm5_m_ctl_hw_settle_delay_mask, channel->hw_settle_time); + buf[6] &= ~adc_tm5_m_ctl_cal_sel_mask; + buf[6] |= field_prep(adc_tm5_m_ctl_cal_sel_mask, channel->cal_method); + + buf[7] |= adc_tm5_m_meas_en; + + ret = adc_tm5_write(chip, reg, buf, sizeof(buf)); + if (ret) { + dev_err(chip->dev, "channel %d params write failed: %d ", channel->channel, ret); + return ret; + } + + return adc_tm5_enable(chip); +} + +static int adc_tm5_set_trips(void *data, int low, int high) +{ + struct adc_tm5_channel *channel = data; + struct adc_tm5_chip *chip; + int ret; + + if (!channel) + return -einval; + + chip = channel->chip; + dev_dbg(chip->dev, "%d:low(mdegc):%d, high(mdegc):%d ", + channel->channel, low, high); + + if (high == int_max && low <= -int_max) + ret = adc_tm5_disable_channel(channel); + else + ret = adc_tm5_configure(channel, low, high); + + return ret; +} + +static struct thermal_zone_of_device_ops adc_tm5_ops = { + .get_temp = adc_tm5_get_temp, + .set_trips = adc_tm5_set_trips, +}; + +static int adc_tm5_register_tzd(struct adc_tm5_chip *adc_tm) +{ + unsigned int i; + struct thermal_zone_device *tzd; + + for (i = 0; i < adc_tm->nchannels; i++) { + adc_tm->channels[i].chip = adc_tm; + + tzd = devm_thermal_zone_of_sensor_register(adc_tm->dev, + adc_tm->channels[i].channel, + &adc_tm->channels[i], + &adc_tm5_ops); + if (is_err(tzd)) { + dev_err(adc_tm->dev, "error registering tz zone for channel %d: %ld ", + adc_tm->channels[i].channel, ptr_err(tzd)); + return ptr_err(tzd); + } + adc_tm->channels[i].tzd = tzd; + } + + return 0; +} + +static int adc_tm5_init(struct adc_tm5_chip *chip) +{ + u8 buf[4], channels_available; + int ret; + unsigned int i; + + for (i = 0; i < chip->nchannels; i++) { + if (chip->channels[i].channel >= channels_available) { + dev_err(chip->dev, "invalid channel %d ", chip->channels[i].channel); + return -einval; + } + } + + ret = adc_tm5_read(chip, adc_tm5_num_btm, + &channels_available, sizeof(channels_available)); + if (ret) { + dev_err(chip->dev, "read failed for btm channels "); + return ret; + } + + buf[0] = chip->decimation; + buf[1] = chip->avg_samples | adc_tm5_fast_avg_en; + buf[2] = adc_tm5_timer1; + buf[3] = field_prep(adc_tm5_meas_interval_ctl2_mask, adc_tm5_timer2) | + field_prep(adc_tm5_meas_interval_ctl3_mask, adc_tm5_timer3); + + ret = adc_tm5_write(chip, adc_tm5_adc_dig_param, buf, sizeof(buf)); + if (ret) { + dev_err(chip->dev, "block write failed: %d ", ret); + return ret; + } + + return ret; +} + +static int adc_tm5_get_dt_channel_data(struct adc_tm5_chip *adc_tm, + struct adc_tm5_channel *channel, + struct device_node *node) +{ + const char *name = node->name; + u32 chan, value, varr[2]; + int ret; + struct device *dev = adc_tm->dev; + struct of_phandle_args args; + + ret = of_property_read_u32(node, "reg", &chan); + if (ret) { + dev_err(dev, "%s: invalid channel number %d ", name, ret); + return ret; + } + + if (chan >= adc_tm5_num_channels) { + dev_err(dev, "%s: channel number too big: %d ", name, chan); + return -einval; + } + + channel->channel = chan; + + /* + * we are tied to pmic's adc controller, which always use single + * argument for channel number. so don't bother parsing + * #io-channel-cells, just enforce cell_count = 1. + */ + ret = of_parse_phandle_with_fixed_args(node, "io-channels", 1, 0, &args); + if (ret < 0) { + dev_err(dev, "%s: error parsing adc channel number %d: %d ", name, chan, ret); + return ret; + } + of_node_put(args.np); + + if (args.args_count != 1 || args.args[0] >= adc5_max_channel) { + dev_err(dev, "%s: invalid adc channel number %d ", name, chan); + return ret; + } + channel->adc_channel = args.args[0]; + + channel->iio = devm_of_iio_channel_get_by_name(adc_tm->dev, node, null); + if (is_err(channel->iio)) { + ret = ptr_err(channel->iio); + if (ret != -eprobe_defer) + dev_err(dev, "%s: error getting channel: %d ", name, ret); + return ret; + } + + ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2); + if (!ret) { + ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]); + if (ret < 0) { + dev_err(dev, "%s: invalid pre-scaling <%d %d> ", + name, varr[0], varr[1]); + return ret; + } + channel->prescale = ret; + } else { + /* 1:1 prescale is index 0 */ + channel->prescale = 0; + } + + ret = of_property_read_u32(node, "qcom,hw-settle-time-us", &value); + if (!ret) { + ret = qcom_adc5_hw_settle_time_from_dt(value, adc_tm->data->hw_settle); + if (ret < 0) { + dev_err(dev, "%s invalid hw-settle-time-us %d us ", + name, value); + return ret; + } + channel->hw_settle_time = ret; + } else { + channel->hw_settle_time = vadc_def_hw_settle_time; + } + + if (of_property_read_bool(node, "qcom,ratiometric")) + channel->cal_method = adc_tm5_ratiometric_cal; + else + channel->cal_method = adc_tm5_absolute_cal; + + return 0; +} + +static int adc_tm5_get_dt_data(struct adc_tm5_chip *adc_tm, struct device_node *node) +{ + struct adc_tm5_channel *channels; + struct device_node *child; + u32 value; + int ret; + struct device *dev = adc_tm->dev; + + adc_tm->nchannels = of_get_available_child_count(node); + if (!adc_tm->nchannels) + return -einval; + + adc_tm->channels = devm_kcalloc(dev, adc_tm->nchannels, + sizeof(*adc_tm->channels), gfp_kernel); + if (!adc_tm->channels) + return -enomem; + + channels = adc_tm->channels; + + adc_tm->data = of_device_get_match_data(dev); + if (!adc_tm->data) + adc_tm->data = &adc_tm5_data_pmic; + + ret = of_property_read_u32(node, "qcom,decimation", &value); + if (!ret) { + ret = qcom_adc5_decimation_from_dt(value, adc_tm->data->decimation); + if (ret < 0) { + dev_err(dev, "invalid decimation %d ", value); + return ret; + } + adc_tm->decimation = ret; + } else { + adc_tm->decimation = adc5_decimation_default; + } + + ret = of_property_read_u32(node, "qcom,avg-samples", &value); + if (!ret) { + ret = qcom_adc5_avg_samples_from_dt(value); + if (ret < 0) { + dev_err(dev, "invalid avg-samples %d ", value); + return ret; + } + adc_tm->avg_samples = ret; + } else { + adc_tm->avg_samples = vadc_def_avg_samples; + } + + for_each_available_child_of_node(node, child) { + ret = adc_tm5_get_dt_channel_data(adc_tm, channels, child); + if (ret) { + of_node_put(child); + return ret; + } + + channels++; + } + + return 0; +} + +static int adc_tm5_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct device *dev = &pdev->dev; + struct adc_tm5_chip *adc_tm; + struct regmap *regmap; + int ret, irq; + u32 reg; + + regmap = dev_get_regmap(dev->parent, null); + if (!regmap) + return -enodev; + + ret = of_property_read_u32(node, "reg", ®); + if (ret) + return ret; + + adc_tm = devm_kzalloc(&pdev->dev, sizeof(*adc_tm), gfp_kernel); + if (!adc_tm) + return -enomem; + + adc_tm->regmap = regmap; + adc_tm->dev = dev; + adc_tm->base = reg; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "get_irq failed: %d ", irq); + return irq; + } + + ret = adc_tm5_get_dt_data(adc_tm, node); + if (ret) { + dev_err(dev, "get dt data failed: %d ", ret); + return ret; + } + + ret = adc_tm5_init(adc_tm); + if (ret) { + dev_err(dev, "adc-tm init failed "); + return ret; + } + + ret = adc_tm5_register_tzd(adc_tm); + if (ret) { + dev_err(dev, "tzd register failed "); + return ret; + } + + return devm_request_threaded_irq(dev, irq, null, adc_tm5_isr, + irqf_oneshot, "pm-adc-tm5", adc_tm); +} + +static const struct of_device_id adc_tm5_match_table[] = { + { + .compatible = "qcom,spmi-adc-tm5", + .data = &adc_tm5_data_pmic, + }, + { } +}; +module_device_table(of, adc_tm5_match_table); + +static struct platform_driver adc_tm5_driver = { + .driver = { + .name = "qcom-spmi-adc-tm5", + .of_match_table = adc_tm5_match_table, + }, + .probe = adc_tm5_probe, +}; +module_platform_driver(adc_tm5_driver); + +module_description("spmi pmic thermal monitor adc driver"); +module_license("gpl v2"); diff --git a/include/linux/iio/adc/qcom-vadc-common.h b/include/linux/iio/adc/qcom-vadc-common.h --- a/include/linux/iio/adc/qcom-vadc-common.h +++ b/include/linux/iio/adc/qcom-vadc-common.h +u16 qcom_adc_tm5_temp_volt_scale(unsigned int prescale_ratio, + u32 full_scale_code_volt, int temp); +
|
Voltage, current regulators, power capping, power supply
|
ca66dca5eda6bd16b7b27fed2a034f2396df5627
|
dmitry baryshkov
|
include
|
linux
|
adc, iio, qcom
|
rtc: pcf8563: add nxp pca8565 compatible
|
the nxp pca8565 is software compatible with the nxp pcf8563, add dt and acpi compatible entries.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add nxp pca8565 compatible
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['pcf8563']
|
['txt', 'c']
| 2
| 4
| 1
|
--- diff --git a/documentation/devicetree/bindings/rtc/pcf8563.txt b/documentation/devicetree/bindings/rtc/pcf8563.txt --- a/documentation/devicetree/bindings/rtc/pcf8563.txt +++ b/documentation/devicetree/bindings/rtc/pcf8563.txt - compatible: should contain "nxp,pcf8563", - "microcrystal,rv8564" + "microcrystal,rv8564" or + "nxp,pca8565" - reg: i2c address for chip. diff --git a/drivers/rtc/rtc-pcf8563.c b/drivers/rtc/rtc-pcf8563.c --- a/drivers/rtc/rtc-pcf8563.c +++ b/drivers/rtc/rtc-pcf8563.c + { "pca8565", 0 }, + { .compatible = "nxp,pca8565" },
|
Real Time Clock (RTC)
|
198be9898b9e62bea65f39b04d35f56d76c8bede
|
marek vasut
|
drivers
|
rtc
|
bindings, rtc
|
rtc: remove sirfsoc driver
|
the csr sirf prima2/atlas platforms are getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove sirfsoc driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['c', 'h', 'kconfig', 'txt', 'makefile']
| 5
| 0
| 488
|
--- diff --git a/documentation/devicetree/bindings/rtc/sirf,prima2-sysrtc.txt b/documentation/devicetree/bindings/rtc/sirf,prima2-sysrtc.txt --- a/documentation/devicetree/bindings/rtc/sirf,prima2-sysrtc.txt +++ /dev/null -sirfsoc real time clock - -required properties: -- compatible: must be "sirf,prima2-sysrtc" -- reg: address range of rtc register set. -- interrupts: rtc alarm interrupts. - -example: - rtc@2000 { - compatible = "sirf,prima2-sysrtc"; - reg = <0x2000 0x1000>; - interrupts = <52 53 54>; - }; diff --git a/drivers/rtc/kconfig b/drivers/rtc/kconfig --- a/drivers/rtc/kconfig +++ b/drivers/rtc/kconfig -config rtc_drv_sirfsoc - tristate "sirfsoc rtc" - depends on arch_sirf - help - say "yes" here to support the real time clock on sirf soc chips. - this driver can also be built as a module called rtc-sirfsoc. - diff --git a/drivers/rtc/makefile b/drivers/rtc/makefile --- a/drivers/rtc/makefile +++ b/drivers/rtc/makefile -obj-$(config_rtc_drv_sirfsoc) += rtc-sirfsoc.o diff --git a/drivers/rtc/rtc-sirfsoc.c b/drivers/rtc/rtc-sirfsoc.c --- a/drivers/rtc/rtc-sirfsoc.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-or-later -/* - * sirfsoc real time clock interface for linux - * - * copyright (c) 2013 cambridge silicon radio limited, a csr plc group company. - */ - -#include <linux/module.h> -#include <linux/err.h> -#include <linux/rtc.h> -#include <linux/platform_device.h> -#include <linux/slab.h> -#include <linux/io.h> -#include <linux/of.h> -#include <linux/regmap.h> -#include <linux/rtc/sirfsoc_rtciobrg.h> - - -#define rtc_cn 0x00 -#define rtc_alarm0 0x04 -#define rtc_alarm1 0x18 -#define rtc_status 0x08 -#define rtc_sw_value 0x40 -#define sirfsoc_rtc_al1e (1<<6) -#define sirfsoc_rtc_al1 (1<<4) -#define sirfsoc_rtc_hze (1<<3) -#define sirfsoc_rtc_al0e (1<<2) -#define sirfsoc_rtc_hz (1<<1) -#define sirfsoc_rtc_al0 (1<<0) -#define rtc_div 0x0c -#define rtc_deep_ctrl 0x14 -#define rtc_clock_switch 0x1c -#define sirfsoc_rtc_clk 0x03 /* others are reserved */ - -/* refer to rtc div switch */ -#define rtc_hz 16 - -/* this macro is also defined in arch/arm/plat-sirfsoc/cpu.c */ -#define rtc_shift 4 - -#define intr_sysrtc_cn 0x48 - -struct sirfsoc_rtc_drv { - struct rtc_device *rtc; - u32 rtc_base; - u32 irq; - unsigned irq_wake; - /* overflow for every 8 years extra time */ - u32 overflow_rtc; - spinlock_t lock; - struct regmap *regmap; -#ifdef config_pm - u32 saved_counter; - u32 saved_overflow_rtc; -#endif -}; - -static u32 sirfsoc_rtc_readl(struct sirfsoc_rtc_drv *rtcdrv, u32 offset) -{ - u32 val; - - regmap_read(rtcdrv->regmap, rtcdrv->rtc_base + offset, &val); - return val; -} - -static void sirfsoc_rtc_writel(struct sirfsoc_rtc_drv *rtcdrv, - u32 offset, u32 val) -{ - regmap_write(rtcdrv->regmap, rtcdrv->rtc_base + offset, val); -} - -static int sirfsoc_rtc_read_alarm(struct device *dev, - struct rtc_wkalrm *alrm) -{ - unsigned long rtc_alarm, rtc_count; - struct sirfsoc_rtc_drv *rtcdrv; - - rtcdrv = dev_get_drvdata(dev); - - spin_lock_irq(&rtcdrv->lock); - - rtc_count = sirfsoc_rtc_readl(rtcdrv, rtc_cn); - - rtc_alarm = sirfsoc_rtc_readl(rtcdrv, rtc_alarm0); - memset(alrm, 0, sizeof(struct rtc_wkalrm)); - - /* - * assume alarm interval not beyond one round counter overflow_rtc: - * 0->0xffffffff - */ - /* if alarm is in next overflow cycle */ - if (rtc_count > rtc_alarm) - rtc_time64_to_tm((rtcdrv->overflow_rtc + 1) - << (bits_per_long - rtc_shift) - | rtc_alarm >> rtc_shift, &alrm->time); - else - rtc_time64_to_tm(rtcdrv->overflow_rtc - << (bits_per_long - rtc_shift) - | rtc_alarm >> rtc_shift, &alrm->time); - if (sirfsoc_rtc_readl(rtcdrv, rtc_status) & sirfsoc_rtc_al0e) - alrm->enabled = 1; - - spin_unlock_irq(&rtcdrv->lock); - - return 0; -} - -static int sirfsoc_rtc_set_alarm(struct device *dev, - struct rtc_wkalrm *alrm) -{ - unsigned long rtc_status_reg, rtc_alarm; - struct sirfsoc_rtc_drv *rtcdrv; - rtcdrv = dev_get_drvdata(dev); - - if (alrm->enabled) { - rtc_alarm = rtc_tm_to_time64(&alrm->time); - - spin_lock_irq(&rtcdrv->lock); - - rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, rtc_status); - if (rtc_status_reg & sirfsoc_rtc_al0e) { - /* - * an ongoing alarm in progress - ingore it and not - * to return ebusy - */ - dev_info(dev, "an old alarm was set, will be replaced by a new one "); - } - - sirfsoc_rtc_writel(rtcdrv, rtc_alarm0, rtc_alarm << rtc_shift); - rtc_status_reg &= ~0x07; /* mask out the lower status bits */ - /* - * this bit rtc_al sets it as a wake-up source for sleep mode - * writing 1 into this bit will clear it - */ - rtc_status_reg |= sirfsoc_rtc_al0; - /* enable the rtc alarm interrupt */ - rtc_status_reg |= sirfsoc_rtc_al0e; - sirfsoc_rtc_writel(rtcdrv, rtc_status, rtc_status_reg); - - spin_unlock_irq(&rtcdrv->lock); - } else { - /* - * if this function was called with enabled=0 - * then it could mean that the application is - * trying to cancel an ongoing alarm - */ - spin_lock_irq(&rtcdrv->lock); - - rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, rtc_status); - if (rtc_status_reg & sirfsoc_rtc_al0e) { - /* clear the rtc status register's alarm bit */ - rtc_status_reg &= ~0x07; - /* write 1 into sirfsoc_rtc_al0 to force a clear */ - rtc_status_reg |= (sirfsoc_rtc_al0); - /* clear the alarm enable bit */ - rtc_status_reg &= ~(sirfsoc_rtc_al0e); - - sirfsoc_rtc_writel(rtcdrv, rtc_status, - rtc_status_reg); - } - - spin_unlock_irq(&rtcdrv->lock); - } - - return 0; -} - -static int sirfsoc_rtc_read_time(struct device *dev, - struct rtc_time *tm) -{ - unsigned long tmp_rtc = 0; - struct sirfsoc_rtc_drv *rtcdrv; - rtcdrv = dev_get_drvdata(dev); - /* - * this patch is taken from wince - need to validate this for - * correctness. to work around sirfsoc rtc counter double sync logic - * fail, read several times to make sure get stable value. - */ - do { - tmp_rtc = sirfsoc_rtc_readl(rtcdrv, rtc_cn); - cpu_relax(); - } while (tmp_rtc != sirfsoc_rtc_readl(rtcdrv, rtc_cn)); - - rtc_time64_to_tm(rtcdrv->overflow_rtc << (bits_per_long - rtc_shift) - | tmp_rtc >> rtc_shift, tm); - return 0; -} - -static int sirfsoc_rtc_set_time(struct device *dev, - struct rtc_time *tm) -{ - unsigned long rtc_time; - struct sirfsoc_rtc_drv *rtcdrv; - rtcdrv = dev_get_drvdata(dev); - - rtc_time = rtc_tm_to_time64(tm); - - rtcdrv->overflow_rtc = rtc_time >> (bits_per_long - rtc_shift); - - sirfsoc_rtc_writel(rtcdrv, rtc_sw_value, rtcdrv->overflow_rtc); - sirfsoc_rtc_writel(rtcdrv, rtc_cn, rtc_time << rtc_shift); - - return 0; -} - -static int sirfsoc_rtc_alarm_irq_enable(struct device *dev, - unsigned int enabled) -{ - unsigned long rtc_status_reg = 0x0; - struct sirfsoc_rtc_drv *rtcdrv; - - rtcdrv = dev_get_drvdata(dev); - - spin_lock_irq(&rtcdrv->lock); - - rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, rtc_status); - if (enabled) - rtc_status_reg |= sirfsoc_rtc_al0e; - else - rtc_status_reg &= ~sirfsoc_rtc_al0e; - - sirfsoc_rtc_writel(rtcdrv, rtc_status, rtc_status_reg); - - spin_unlock_irq(&rtcdrv->lock); - - return 0; - -} - -static const struct rtc_class_ops sirfsoc_rtc_ops = { - .read_time = sirfsoc_rtc_read_time, - .set_time = sirfsoc_rtc_set_time, - .read_alarm = sirfsoc_rtc_read_alarm, - .set_alarm = sirfsoc_rtc_set_alarm, - .alarm_irq_enable = sirfsoc_rtc_alarm_irq_enable -}; - -static irqreturn_t sirfsoc_rtc_irq_handler(int irq, void *pdata) -{ - struct sirfsoc_rtc_drv *rtcdrv = pdata; - unsigned long rtc_status_reg = 0x0; - unsigned long events = 0x0; - - spin_lock(&rtcdrv->lock); - - rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, rtc_status); - /* this bit will be set only if an alarm was active - * and it expired now - * so this is being used as an assert - */ - if (rtc_status_reg & sirfsoc_rtc_al0) { - /* - * clear the rtc status register's alarm bit - * mask out the lower status bits - */ - rtc_status_reg &= ~0x07; - /* write 1 into sirfsoc_rtc_al0 to ack the alarm interrupt */ - rtc_status_reg |= (sirfsoc_rtc_al0); - /* clear the alarm enable bit */ - rtc_status_reg &= ~(sirfsoc_rtc_al0e); - } - - sirfsoc_rtc_writel(rtcdrv, rtc_status, rtc_status_reg); - - spin_unlock(&rtcdrv->lock); - - /* this should wake up any apps polling/waiting on the read - * after setting the alarm - */ - events |= rtc_irqf | rtc_af; - rtc_update_irq(rtcdrv->rtc, 1, events); - - return irq_handled; -} - -static const struct of_device_id sirfsoc_rtc_of_match[] = { - { .compatible = "sirf,prima2-sysrtc"}, - {}, -}; - -static const struct regmap_config sysrtc_regmap_config = { - .reg_bits = 32, - .val_bits = 32, - .fast_io = true, -}; - -module_device_table(of, sirfsoc_rtc_of_match); - -static int sirfsoc_rtc_probe(struct platform_device *pdev) -{ - int err; - unsigned long rtc_div; - struct sirfsoc_rtc_drv *rtcdrv; - struct device_node *np = pdev->dev.of_node; - - rtcdrv = devm_kzalloc(&pdev->dev, - sizeof(struct sirfsoc_rtc_drv), gfp_kernel); - if (rtcdrv == null) - return -enomem; - - spin_lock_init(&rtcdrv->lock); - - err = of_property_read_u32(np, "reg", &rtcdrv->rtc_base); - if (err) { - dev_err(&pdev->dev, "unable to find base address of rtc node in dtb "); - return err; - } - - platform_set_drvdata(pdev, rtcdrv); - - /* register rtc alarm as a wakeup source */ - device_init_wakeup(&pdev->dev, 1); - - rtcdrv->regmap = devm_regmap_init_iobg(&pdev->dev, - &sysrtc_regmap_config); - if (is_err(rtcdrv->regmap)) { - err = ptr_err(rtcdrv->regmap); - dev_err(&pdev->dev, "failed to allocate register map: %d ", - err); - return err; - } - - /* - * set sys_rtc counter in rtc_hz hz units - * we are using 32k rtc crystal (32768 / rtc_hz / 2) -1 - * if 16hz, therefore rtc_div = 1023; - */ - rtc_div = ((32768 / rtc_hz) / 2) - 1; - sirfsoc_rtc_writel(rtcdrv, rtc_div, rtc_div); - - /* 0x3 -> rtc_clk */ - sirfsoc_rtc_writel(rtcdrv, rtc_clock_switch, sirfsoc_rtc_clk); - - /* reset sys rtc alarm0 */ - sirfsoc_rtc_writel(rtcdrv, rtc_alarm0, 0x0); - - /* reset sys rtc alarm1 */ - sirfsoc_rtc_writel(rtcdrv, rtc_alarm1, 0x0); - - /* restore rtc overflow from register after command reboot */ - rtcdrv->overflow_rtc = - sirfsoc_rtc_readl(rtcdrv, rtc_sw_value); - - rtcdrv->rtc = devm_rtc_allocate_device(&pdev->dev); - if (is_err(rtcdrv->rtc)) - return ptr_err(rtcdrv->rtc); - - rtcdrv->rtc->ops = &sirfsoc_rtc_ops; - rtcdrv->rtc->range_max = (1ull << 60) - 1; - - rtcdrv->irq = platform_get_irq(pdev, 0); - err = devm_request_irq(&pdev->dev, rtcdrv->irq, sirfsoc_rtc_irq_handler, - irqf_shared, pdev->name, rtcdrv); - if (err) { - dev_err(&pdev->dev, "unable to register for the sirf soc rtc irq "); - return err; - } - - return devm_rtc_register_device(rtcdrv->rtc); -} - -#ifdef config_pm_sleep -static int sirfsoc_rtc_suspend(struct device *dev) -{ - struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev); - rtcdrv->overflow_rtc = - sirfsoc_rtc_readl(rtcdrv, rtc_sw_value); - - rtcdrv->saved_counter = - sirfsoc_rtc_readl(rtcdrv, rtc_cn); - rtcdrv->saved_overflow_rtc = rtcdrv->overflow_rtc; - if (device_may_wakeup(dev) && !enable_irq_wake(rtcdrv->irq)) - rtcdrv->irq_wake = 1; - - return 0; -} - -static int sirfsoc_rtc_resume(struct device *dev) -{ - u32 tmp; - struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev); - - /* - * if resume from snapshot and the rtc power is lost, - * restroe the rtc settings - */ - if (sirfsoc_rtc_clk != sirfsoc_rtc_readl(rtcdrv, rtc_clock_switch)) { - u32 rtc_div; - /* 0x3 -> rtc_clk */ - sirfsoc_rtc_writel(rtcdrv, rtc_clock_switch, sirfsoc_rtc_clk); - /* - * set sys_rtc counter in rtc_hz hz units - * we are using 32k rtc crystal (32768 / rtc_hz / 2) -1 - * if 16hz, therefore rtc_div = 1023; - */ - rtc_div = ((32768 / rtc_hz) / 2) - 1; - - sirfsoc_rtc_writel(rtcdrv, rtc_div, rtc_div); - - /* reset sys rtc alarm0 */ - sirfsoc_rtc_writel(rtcdrv, rtc_alarm0, 0x0); - - /* reset sys rtc alarm1 */ - sirfsoc_rtc_writel(rtcdrv, rtc_alarm1, 0x0); - } - rtcdrv->overflow_rtc = rtcdrv->saved_overflow_rtc; - - /* - * if current counter is small than previous, - * it means overflow in sleep - */ - tmp = sirfsoc_rtc_readl(rtcdrv, rtc_cn); - if (tmp <= rtcdrv->saved_counter) - rtcdrv->overflow_rtc++; - /* - *pwrc value be changed when suspend, restore overflow - * in memory to register - */ - sirfsoc_rtc_writel(rtcdrv, rtc_sw_value, rtcdrv->overflow_rtc); - - if (device_may_wakeup(dev) && rtcdrv->irq_wake) { - disable_irq_wake(rtcdrv->irq); - rtcdrv->irq_wake = 0; - } - - return 0; -} -#endif - -static simple_dev_pm_ops(sirfsoc_rtc_pm_ops, - sirfsoc_rtc_suspend, sirfsoc_rtc_resume); - -static struct platform_driver sirfsoc_rtc_driver = { - .driver = { - .name = "sirfsoc-rtc", - .pm = &sirfsoc_rtc_pm_ops, - .of_match_table = sirfsoc_rtc_of_match, - }, - .probe = sirfsoc_rtc_probe, -}; -module_platform_driver(sirfsoc_rtc_driver); - -module_description("sirf soc rtc driver"); -module_author("xianglong du <xianglong.du@csr.com>"); -module_license("gpl v2"); -module_alias("platform:sirfsoc-rtc"); diff --git a/include/linux/rtc/sirfsoc_rtciobrg.h b/include/linux/rtc/sirfsoc_rtciobrg.h --- a/include/linux/rtc/sirfsoc_rtciobrg.h +++ /dev/null -/* spdx-license-identifier: gpl-2.0-or-later */ -/* - * rtc i/o bridge interfaces for csr sirfprimaii - * arm access the registers of sysrtc, gpsrtc and pwrc through this module - * - * copyright (c) 2011 cambridge silicon radio limited, a csr plc group company. - */ -#ifndef _sirfsoc_rtc_iobrg_h_ -#define _sirfsoc_rtc_iobrg_h_ - -struct regmap_config; - -extern void sirfsoc_rtc_iobrg_besyncing(void); - -extern u32 sirfsoc_rtc_iobrg_readl(u32 addr); - -extern void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr); -struct regmap *devm_regmap_init_iobg(struct device *dev, - const struct regmap_config *config); - -#endif
|
Real Time Clock (RTC)
|
9d0735519f99948c5b5c22426b682ced7f7af9be
|
arnd bergmann barry song baohua kernel org
|
drivers
|
rtc
|
bindings, rtc
|
rtc: remove ste ab3100 driver
|
the st-ericsson u300 platform is getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove ste ab3100 driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['kconfig', 'c', 'makefile']
| 3
| 0
| 263
|
--- diff --git a/drivers/rtc/kconfig b/drivers/rtc/kconfig --- a/drivers/rtc/kconfig +++ b/drivers/rtc/kconfig -config rtc_drv_ab3100 - tristate "st-ericsson ab3100 rtc" - depends on ab3100_core - default y if ab3100_core - help - select this to enable the st-ericsson ab3100 mixed signal ic rtc - support. this chip contains a battery- and capacitor-backed rtc. - diff --git a/drivers/rtc/makefile b/drivers/rtc/makefile --- a/drivers/rtc/makefile +++ b/drivers/rtc/makefile -obj-$(config_rtc_drv_ab3100) += rtc-ab3100.o diff --git a/drivers/rtc/rtc-ab3100.c b/drivers/rtc/rtc-ab3100.c --- a/drivers/rtc/rtc-ab3100.c +++ /dev/null -// spdx-license-identifier: gpl-2.0 -/* - * copyright (c) 2007-2009 st-ericsson ab - * rtc clock driver for the ab3100 analog baseband chip - * author: linus walleij <linus.walleij@stericsson.com> - */ -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/rtc.h> -#include <linux/mfd/abx500.h> - -/* clock rate in hz */ -#define ab3100_rtc_clock_rate 32768 - -/* - * the ab3100 rtc registers. these are the same for - * ab3000 and ab3100. - * control register: - * bit 0: rtc monitor cleared=0, active=1, if you set it - * to 1 it remains active until rtc power is lost. - * bit 1: 32 khz oscillator, 0 = on, 1 = bypass - * bit 2: alarm on, 0 = off, 1 = on - * bit 3: 32 khz buffer disabling, 0 = enabled, 1 = disabled - */ -#define ab3100_rtc 0x53 -/* default setting, buffer disabled, alarm on */ -#define rtc_setting 0x30 -/* alarm when al0-al3 == ti0-ti3 */ -#define ab3100_al0 0x56 -#define ab3100_al1 0x57 -#define ab3100_al2 0x58 -#define ab3100_al3 0x59 -/* this 48-bit register that counts up at 32768 hz */ -#define ab3100_ti0 0x5a -#define ab3100_ti1 0x5b -#define ab3100_ti2 0x5c -#define ab3100_ti3 0x5d -#define ab3100_ti4 0x5e -#define ab3100_ti5 0x5f - -/* - * rtc clock functions and device struct declaration - */ -static int ab3100_rtc_set_time(struct device *dev, struct rtc_time *tm) -{ - u8 regs[] = {ab3100_ti0, ab3100_ti1, ab3100_ti2, - ab3100_ti3, ab3100_ti4, ab3100_ti5}; - unsigned char buf[6]; - u64 hw_counter = rtc_tm_to_time64(tm) * ab3100_rtc_clock_rate * 2; - int err = 0; - int i; - - buf[0] = (hw_counter) & 0xff; - buf[1] = (hw_counter >> 8) & 0xff; - buf[2] = (hw_counter >> 16) & 0xff; - buf[3] = (hw_counter >> 24) & 0xff; - buf[4] = (hw_counter >> 32) & 0xff; - buf[5] = (hw_counter >> 40) & 0xff; - - for (i = 0; i < 6; i++) { - err = abx500_set_register_interruptible(dev, 0, - regs[i], buf[i]); - if (err) - return err; - } - - /* set the flag to mark that the clock is now set */ - return abx500_mask_and_set_register_interruptible(dev, 0, - ab3100_rtc, - 0x01, 0x01); - -} - -static int ab3100_rtc_read_time(struct device *dev, struct rtc_time *tm) -{ - time64_t time; - u8 rtcval; - int err; - - err = abx500_get_register_interruptible(dev, 0, - ab3100_rtc, &rtcval); - if (err) - return err; - - if (!(rtcval & 0x01)) { - dev_info(dev, "clock not set (lost power)"); - return -einval; - } else { - u64 hw_counter; - u8 buf[6]; - - /* read out time registers */ - err = abx500_get_register_page_interruptible(dev, 0, - ab3100_ti0, - buf, 6); - if (err != 0) - return err; - - hw_counter = ((u64) buf[5] << 40) | ((u64) buf[4] << 32) | - ((u64) buf[3] << 24) | ((u64) buf[2] << 16) | - ((u64) buf[1] << 8) | (u64) buf[0]; - time = hw_counter / (u64) (ab3100_rtc_clock_rate * 2); - } - - rtc_time64_to_tm(time, tm); - - return 0; -} - -static int ab3100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) -{ - time64_t time; - u64 hw_counter; - u8 buf[6]; - u8 rtcval; - int err; - - /* figure out if alarm is enabled or not */ - err = abx500_get_register_interruptible(dev, 0, - ab3100_rtc, &rtcval); - if (err) - return err; - if (rtcval & 0x04) - alarm->enabled = 1; - else - alarm->enabled = 0; - /* no idea how this could be represented */ - alarm->pending = 0; - /* read out alarm registers, only 4 bytes */ - err = abx500_get_register_page_interruptible(dev, 0, - ab3100_al0, buf, 4); - if (err) - return err; - hw_counter = ((u64) buf[3] << 40) | ((u64) buf[2] << 32) | - ((u64) buf[1] << 24) | ((u64) buf[0] << 16); - time = hw_counter / (u64) (ab3100_rtc_clock_rate * 2); - - rtc_time64_to_tm(time, &alarm->time); - - return rtc_valid_tm(&alarm->time); -} - -static int ab3100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) -{ - u8 regs[] = {ab3100_al0, ab3100_al1, ab3100_al2, ab3100_al3}; - unsigned char buf[4]; - time64_t secs; - u64 hw_counter; - int err; - int i; - - secs = rtc_tm_to_time64(&alarm->time); - hw_counter = secs * ab3100_rtc_clock_rate * 2; - buf[0] = (hw_counter >> 16) & 0xff; - buf[1] = (hw_counter >> 24) & 0xff; - buf[2] = (hw_counter >> 32) & 0xff; - buf[3] = (hw_counter >> 40) & 0xff; - - /* set the alarm */ - for (i = 0; i < 4; i++) { - err = abx500_set_register_interruptible(dev, 0, - regs[i], buf[i]); - if (err) - return err; - } - /* then enable the alarm */ - return abx500_mask_and_set_register_interruptible(dev, 0, - ab3100_rtc, (1 << 2), - alarm->enabled << 2); -} - -static int ab3100_rtc_irq_enable(struct device *dev, unsigned int enabled) -{ - /* - * it's not possible to enable/disable the alarm irq for this rtc. - * it does not actually trigger any irq: instead its only function is - * to power up the system, if it wasn't on. this will manifest as - * a "power up cause" in the ab3100 power driver (battery charging etc) - * and need to be handled there instead. - */ - if (enabled) - return abx500_mask_and_set_register_interruptible(dev, 0, - ab3100_rtc, (1 << 2), - 1 << 2); - else - return abx500_mask_and_set_register_interruptible(dev, 0, - ab3100_rtc, (1 << 2), - 0); -} - -static const struct rtc_class_ops ab3100_rtc_ops = { - .read_time = ab3100_rtc_read_time, - .set_time = ab3100_rtc_set_time, - .read_alarm = ab3100_rtc_read_alarm, - .set_alarm = ab3100_rtc_set_alarm, - .alarm_irq_enable = ab3100_rtc_irq_enable, -}; - -static int __init ab3100_rtc_probe(struct platform_device *pdev) -{ - int err; - u8 regval; - struct rtc_device *rtc; - - /* the first rtc register needs special treatment */ - err = abx500_get_register_interruptible(&pdev->dev, 0, - ab3100_rtc, ®val); - if (err) { - dev_err(&pdev->dev, "unable to read rtc register "); - return -enodev; - } - - if ((regval & 0xfe) != rtc_setting) { - dev_warn(&pdev->dev, "not default value in rtc reg 0x%x ", - regval); - } - - if ((regval & 1) == 0) { - /* - * set bit to detect power loss. - * this bit remains until rtc power is lost. - */ - regval = 1 | rtc_setting; - err = abx500_set_register_interruptible(&pdev->dev, 0, - ab3100_rtc, regval); - /* ignore any error on this write */ - } - - rtc = devm_rtc_allocate_device(&pdev->dev); - if (is_err(rtc)) - return ptr_err(rtc); - - rtc->ops = &ab3100_rtc_ops; - /* 48bit counter at (ab3100_rtc_clock_rate * 2) */ - rtc->range_max = u32_max; - - platform_set_drvdata(pdev, rtc); - - return devm_rtc_register_device(rtc); -} - -static struct platform_driver ab3100_rtc_driver = { - .driver = { - .name = "ab3100-rtc", - }, -}; - -module_platform_driver_probe(ab3100_rtc_driver, ab3100_rtc_probe); - -module_author("linus walleij <linus.walleij@stericsson.com>"); -module_description("ab3100 rtc driver"); -module_license("gpl");
|
Real Time Clock (RTC)
|
2f58f5eea8c60052100ff325688f2d987bde572b
|
arnd bergmann linus walleij linus walleij linaro org
|
drivers
|
rtc
| |
rtc: remove ste coh901 driver
|
the st-ericsson u300 platform is getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove ste coh901 driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['txt', 'kconfig', 'c', 'makefile']
| 4
| 0
| 319
|
--- diff --git a/documentation/devicetree/bindings/rtc/stericsson,coh901331.txt b/documentation/devicetree/bindings/rtc/stericsson,coh901331.txt --- a/documentation/devicetree/bindings/rtc/stericsson,coh901331.txt +++ /dev/null -st-ericsson coh 901 331 real time clock - -required properties: -- compatible: must be "stericsson,coh901331" -- reg: address range of rtc register set. -- interrupts: rtc alarm interrupt. -- clocks: phandle to the rtc clock source - -example: - rtc: rtc@c0017000 { - compatible = "stericsson,coh901331"; - reg = <0xc0017000 0x1000>; - interrupt-parent = <&vicb>; - interrupts = <10>; - clocks = <&rtc_clk>; - }; diff --git a/drivers/rtc/kconfig b/drivers/rtc/kconfig --- a/drivers/rtc/kconfig +++ b/drivers/rtc/kconfig -config rtc_drv_coh901331 - tristate "st-ericsson coh 901 331 rtc" - depends on arch_u300 || compile_test - help - if you say y here you will get access to st-ericsson - coh 901 331 rtc clock found in some st-ericsson mobile - platforms. - - this driver can also be built as a module. if so, the module - will be called "rtc-coh901331". - - diff --git a/drivers/rtc/makefile b/drivers/rtc/makefile --- a/drivers/rtc/makefile +++ b/drivers/rtc/makefile -obj-$(config_rtc_drv_coh901331) += rtc-coh901331.o diff --git a/drivers/rtc/rtc-coh901331.c b/drivers/rtc/rtc-coh901331.c --- a/drivers/rtc/rtc-coh901331.c +++ /dev/null -// spdx-license-identifier: gpl-2.0 -/* - * copyright (c) 2007-2009 st-ericsson ab - * real time clock interface for st-ericsson ab coh 901 331 rtc. - * author: linus walleij <linus.walleij@stericsson.com> - * based on rtc-pl031.c by deepak saxena <dsaxena@plexity.net> - * copyright 2006 (c) montavista software, inc. - */ -#include <linux/init.h> -#include <linux/module.h> -#include <linux/mod_devicetable.h> -#include <linux/rtc.h> -#include <linux/clk.h> -#include <linux/interrupt.h> -#include <linux/pm.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/slab.h> - -/* - * registers in the coh 901 331 - */ -/* alarm value 32bit (r/w) */ -#define coh901331_alarm 0x00u -/* used to set current time 32bit (r/w) */ -#define coh901331_set_time 0x04u -/* indication if current time is valid 32bit (r/-) */ -#define coh901331_valid 0x08u -/* read the current time 32bit (r/-) */ -#define coh901331_cur_time 0x0cu -/* event register for the "alarm" interrupt */ -#define coh901331_irq_event 0x10u -/* mask register for the "alarm" interrupt */ -#define coh901331_irq_mask 0x14u -/* force register for the "alarm" interrupt */ -#define coh901331_irq_force 0x18u - -/* - * reference to rtc block clock - * notice that the frequent clk_enable()/clk_disable() on this - * clock is mainly to be able to turn on/off other clocks in the - * hierarchy as needed, the rtc clock is always on anyway. - */ -struct coh901331_port { - struct rtc_device *rtc; - struct clk *clk; - void __iomem *virtbase; - int irq; -#ifdef config_pm_sleep - u32 irqmaskstore; -#endif -}; - -static irqreturn_t coh901331_interrupt(int irq, void *data) -{ - struct coh901331_port *rtap = data; - - clk_enable(rtap->clk); - /* ack irq */ - writel(1, rtap->virtbase + coh901331_irq_event); - /* - * disable the interrupt. this is necessary because - * the rtc lives on a lower-clocked line and will - * not release the irq line until after a few (slower) - * clock cycles. the interrupt will be re-enabled when - * a new alarm is set anyway. - */ - writel(0, rtap->virtbase + coh901331_irq_mask); - clk_disable(rtap->clk); - - /* set alarm flag */ - rtc_update_irq(rtap->rtc, 1, rtc_af); - - return irq_handled; -} - -static int coh901331_read_time(struct device *dev, struct rtc_time *tm) -{ - struct coh901331_port *rtap = dev_get_drvdata(dev); - - clk_enable(rtap->clk); - /* check if the time is valid */ - if (!readl(rtap->virtbase + coh901331_valid)) { - clk_disable(rtap->clk); - return -einval; - } - - rtc_time64_to_tm(readl(rtap->virtbase + coh901331_cur_time), tm); - clk_disable(rtap->clk); - return 0; -} - -static int coh901331_set_time(struct device *dev, struct rtc_time *tm) -{ - struct coh901331_port *rtap = dev_get_drvdata(dev); - - clk_enable(rtap->clk); - writel(rtc_tm_to_time64(tm), rtap->virtbase + coh901331_set_time); - clk_disable(rtap->clk); - - return 0; -} - -static int coh901331_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) -{ - struct coh901331_port *rtap = dev_get_drvdata(dev); - - clk_enable(rtap->clk); - rtc_time64_to_tm(readl(rtap->virtbase + coh901331_alarm), &alarm->time); - alarm->pending = readl(rtap->virtbase + coh901331_irq_event) & 1u; - alarm->enabled = readl(rtap->virtbase + coh901331_irq_mask) & 1u; - clk_disable(rtap->clk); - - return 0; -} - -static int coh901331_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) -{ - struct coh901331_port *rtap = dev_get_drvdata(dev); - unsigned long time = rtc_tm_to_time64(&alarm->time); - - clk_enable(rtap->clk); - writel(time, rtap->virtbase + coh901331_alarm); - writel(alarm->enabled, rtap->virtbase + coh901331_irq_mask); - clk_disable(rtap->clk); - - return 0; -} - -static int coh901331_alarm_irq_enable(struct device *dev, unsigned int enabled) -{ - struct coh901331_port *rtap = dev_get_drvdata(dev); - - clk_enable(rtap->clk); - if (enabled) - writel(1, rtap->virtbase + coh901331_irq_mask); - else - writel(0, rtap->virtbase + coh901331_irq_mask); - clk_disable(rtap->clk); - - return 0; -} - -static const struct rtc_class_ops coh901331_ops = { - .read_time = coh901331_read_time, - .set_time = coh901331_set_time, - .read_alarm = coh901331_read_alarm, - .set_alarm = coh901331_set_alarm, - .alarm_irq_enable = coh901331_alarm_irq_enable, -}; - -static int __exit coh901331_remove(struct platform_device *pdev) -{ - struct coh901331_port *rtap = platform_get_drvdata(pdev); - - if (rtap) - clk_unprepare(rtap->clk); - - return 0; -} - - -static int __init coh901331_probe(struct platform_device *pdev) -{ - int ret; - struct coh901331_port *rtap; - - rtap = devm_kzalloc(&pdev->dev, - sizeof(struct coh901331_port), gfp_kernel); - if (!rtap) - return -enomem; - - rtap->virtbase = devm_platform_ioremap_resource(pdev, 0); - if (is_err(rtap->virtbase)) - return ptr_err(rtap->virtbase); - - rtap->irq = platform_get_irq(pdev, 0); - if (devm_request_irq(&pdev->dev, rtap->irq, coh901331_interrupt, 0, - "rtc coh 901 331 alarm", rtap)) - return -eio; - - rtap->clk = devm_clk_get(&pdev->dev, null); - if (is_err(rtap->clk)) { - ret = ptr_err(rtap->clk); - dev_err(&pdev->dev, "could not get clock "); - return ret; - } - - rtap->rtc = devm_rtc_allocate_device(&pdev->dev); - if (is_err(rtap->rtc)) - return ptr_err(rtap->rtc); - - rtap->rtc->ops = &coh901331_ops; - rtap->rtc->range_max = u32_max; - - /* we enable/disable the clock only to assure it works */ - ret = clk_prepare_enable(rtap->clk); - if (ret) { - dev_err(&pdev->dev, "could not enable clock "); - return ret; - } - clk_disable(rtap->clk); - - platform_set_drvdata(pdev, rtap); - - ret = devm_rtc_register_device(rtap->rtc); - if (ret) - goto out_no_rtc; - - return 0; - - out_no_rtc: - clk_unprepare(rtap->clk); - return ret; -} - -#ifdef config_pm_sleep -static int coh901331_suspend(struct device *dev) -{ - struct coh901331_port *rtap = dev_get_drvdata(dev); - - /* - * if this rtc alarm will be used for waking the system up, - * don't disable it of course. else we just disable the alarm - * and await suspension. - */ - if (device_may_wakeup(dev)) { - enable_irq_wake(rtap->irq); - } else { - clk_enable(rtap->clk); - rtap->irqmaskstore = readl(rtap->virtbase + coh901331_irq_mask); - writel(0, rtap->virtbase + coh901331_irq_mask); - clk_disable(rtap->clk); - } - clk_unprepare(rtap->clk); - return 0; -} - -static int coh901331_resume(struct device *dev) -{ - int ret; - struct coh901331_port *rtap = dev_get_drvdata(dev); - - ret = clk_prepare(rtap->clk); - if (ret) - return ret; - - if (device_may_wakeup(dev)) { - disable_irq_wake(rtap->irq); - } else { - clk_enable(rtap->clk); - writel(rtap->irqmaskstore, rtap->virtbase + coh901331_irq_mask); - clk_disable(rtap->clk); - } - return 0; -} -#endif - -static simple_dev_pm_ops(coh901331_pm_ops, coh901331_suspend, coh901331_resume); - -static void coh901331_shutdown(struct platform_device *pdev) -{ - struct coh901331_port *rtap = platform_get_drvdata(pdev); - - clk_enable(rtap->clk); - writel(0, rtap->virtbase + coh901331_irq_mask); - clk_disable_unprepare(rtap->clk); -} - -static const struct of_device_id coh901331_dt_match[] = { - { .compatible = "stericsson,coh901331" }, - {}, -}; -module_device_table(of, coh901331_dt_match); - -static struct platform_driver coh901331_driver = { - .driver = { - .name = "rtc-coh901331", - .pm = &coh901331_pm_ops, - .of_match_table = coh901331_dt_match, - }, - .remove = __exit_p(coh901331_remove), - .shutdown = coh901331_shutdown, -}; - -module_platform_driver_probe(coh901331_driver, coh901331_probe); - -module_author("linus walleij <linus.walleij@stericsson.com>"); -module_description("st-ericsson ab coh 901 331 rtc driver"); -module_license("gpl");
|
Real Time Clock (RTC)
|
dd2d3b40039d0278f25a21aa3e50955a01a92a62
|
arnd bergmann linus walleij linus walleij linaro org
|
drivers
|
rtc
|
bindings, rtc
|
rtc: mrst: remove driver for deprecated platform
|
intel moorestown and medfield are quite old intel atom based 32-bit platforms, which were in limited use in some android phones, tablets and consumer electronics more than eight years ago.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove driver for deprecated platform
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mrst']
|
['kconfig', 'c', 'makefile']
| 3
| 0
| 534
|
--- diff --git a/drivers/rtc/kconfig b/drivers/rtc/kconfig --- a/drivers/rtc/kconfig +++ b/drivers/rtc/kconfig -config rtc_drv_vrtc - tristate "virtual rtc for intel mid platforms" - depends on x86_intel_mid - default y if x86_intel_mid - - help - say "yes" here to get direct support for the real time clock - found on moorestown platforms. the vrtc is a emulated rtc that - derives its clock source from a real rtc in the pmic. the mc146818 - style programming interface is mostly conserved, but any - updates are done via ipc calls to the system controller fw. - diff --git a/drivers/rtc/makefile b/drivers/rtc/makefile --- a/drivers/rtc/makefile +++ b/drivers/rtc/makefile -obj-$(config_rtc_drv_vrtc) += rtc-mrst.o diff --git a/drivers/rtc/rtc-mrst.c b/drivers/rtc/rtc-mrst.c --- a/drivers/rtc/rtc-mrst.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * rtc-mrst.c: driver for moorestown virtual rtc - * - * (c) copyright 2009 intel corporation - * author: jacob pan (jacob.jun.pan@intel.com) - * feng tang (feng.tang@intel.com) - * - * note: - * vrtc is emulated by system controller firmware, the real hw - * rtc is located in the pmic device. scu fw shadows pmic rtc - * in a memory mapped io space that is visible to the host ia - * processor. - * - * this driver is based upon drivers/rtc/rtc-cmos.c - */ - -/* - * note: - * * vrtc only supports binary mode and 24h mode - * * vrtc only support pie and aie, no uie, and its pie only happens - * at 23:59:59pm everyday, no support for adjustable frequency - * * alarm function is also limited to hr/min/sec. - */ - -#include <linux/mod_devicetable.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <linux/spinlock.h> -#include <linux/kernel.h> -#include <linux/mc146818rtc.h> -#include <linux/module.h> -#include <linux/init.h> -#include <linux/sfi.h> - -#include <asm/intel_scu_ipc.h> -#include <asm/intel-mid.h> -#include <asm/intel_mid_vrtc.h> - -struct mrst_rtc { - struct rtc_device *rtc; - struct device *dev; - int irq; - - u8 enabled_wake; - u8 suspend_ctrl; -}; - -static const char driver_name[] = "rtc_mrst"; - -#define rtc_irqmask (rtc_pf | rtc_af) - -static inline int is_intr(u8 rtc_intr) -{ - if (!(rtc_intr & rtc_irqf)) - return 0; - return rtc_intr & rtc_irqmask; -} - -static inline unsigned char vrtc_is_updating(void) -{ - unsigned char uip; - unsigned long flags; - - spin_lock_irqsave(&rtc_lock, flags); - uip = (vrtc_cmos_read(rtc_freq_select) & rtc_uip); - spin_unlock_irqrestore(&rtc_lock, flags); - return uip; -} - -/* - * rtc_time's year contains the increment over 1900, but vrtc's year - * register can't be programmed to value larger than 0x64, so vrtc - * driver chose to use 1972 (1970 is unix time start point) as the base, - * and does the translation at read/write time. - * - * why not just use 1970 as the offset? it's because using 1972 will - * make it consistent in leap year setting for both vrtc and low-level - * physical rtc devices. then why not use 1960 as the offset? if we use - * 1960, for a device's first use, its year register is 0 and the system - * year will be parsed as 1960 which is not a valid unix time and will - * cause many applications to fail mysteriously. - */ -static int mrst_read_time(struct device *dev, struct rtc_time *time) -{ - unsigned long flags; - - if (vrtc_is_updating()) - msleep(20); - - spin_lock_irqsave(&rtc_lock, flags); - time->tm_sec = vrtc_cmos_read(rtc_seconds); - time->tm_min = vrtc_cmos_read(rtc_minutes); - time->tm_hour = vrtc_cmos_read(rtc_hours); - time->tm_mday = vrtc_cmos_read(rtc_day_of_month); - time->tm_mon = vrtc_cmos_read(rtc_month); - time->tm_year = vrtc_cmos_read(rtc_year); - spin_unlock_irqrestore(&rtc_lock, flags); - - /* adjust for the 1972/1900 */ - time->tm_year += 72; - time->tm_mon--; - return 0; -} - -static int mrst_set_time(struct device *dev, struct rtc_time *time) -{ - int ret; - unsigned long flags; - unsigned char mon, day, hrs, min, sec; - unsigned int yrs; - - yrs = time->tm_year; - mon = time->tm_mon + 1; /* tm_mon starts at zero */ - day = time->tm_mday; - hrs = time->tm_hour; - min = time->tm_min; - sec = time->tm_sec; - - if (yrs < 72 || yrs > 172) - return -einval; - yrs -= 72; - - spin_lock_irqsave(&rtc_lock, flags); - - vrtc_cmos_write(yrs, rtc_year); - vrtc_cmos_write(mon, rtc_month); - vrtc_cmos_write(day, rtc_day_of_month); - vrtc_cmos_write(hrs, rtc_hours); - vrtc_cmos_write(min, rtc_minutes); - vrtc_cmos_write(sec, rtc_seconds); - - spin_unlock_irqrestore(&rtc_lock, flags); - - ret = intel_scu_ipc_simple_command(ipcmsg_vrtc, ipc_cmd_vrtc_settime); - return ret; -} - -static int mrst_read_alarm(struct device *dev, struct rtc_wkalrm *t) -{ - struct mrst_rtc *mrst = dev_get_drvdata(dev); - unsigned char rtc_control; - - if (mrst->irq <= 0) - return -eio; - - /* vrtc only supports binary mode */ - spin_lock_irq(&rtc_lock); - t->time.tm_sec = vrtc_cmos_read(rtc_seconds_alarm); - t->time.tm_min = vrtc_cmos_read(rtc_minutes_alarm); - t->time.tm_hour = vrtc_cmos_read(rtc_hours_alarm); - - rtc_control = vrtc_cmos_read(rtc_control); - spin_unlock_irq(&rtc_lock); - - t->enabled = !!(rtc_control & rtc_aie); - t->pending = 0; - - return 0; -} - -static void mrst_checkintr(struct mrst_rtc *mrst, unsigned char rtc_control) -{ - unsigned char rtc_intr; - - /* - * note after changing rtc_xie bits we always read intr_flags; - * allegedly some older rtcs need that to handle irqs properly - */ - rtc_intr = vrtc_cmos_read(rtc_intr_flags); - rtc_intr &= (rtc_control & rtc_irqmask) | rtc_irqf; - if (is_intr(rtc_intr)) - rtc_update_irq(mrst->rtc, 1, rtc_intr); -} - -static void mrst_irq_enable(struct mrst_rtc *mrst, unsigned char mask) -{ - unsigned char rtc_control; - - /* - * flush any pending irq status, notably for update irqs, - * before we enable new irqs - */ - rtc_control = vrtc_cmos_read(rtc_control); - mrst_checkintr(mrst, rtc_control); - - rtc_control |= mask; - vrtc_cmos_write(rtc_control, rtc_control); - - mrst_checkintr(mrst, rtc_control); -} - -static void mrst_irq_disable(struct mrst_rtc *mrst, unsigned char mask) -{ - unsigned char rtc_control; - - rtc_control = vrtc_cmos_read(rtc_control); - rtc_control &= ~mask; - vrtc_cmos_write(rtc_control, rtc_control); - mrst_checkintr(mrst, rtc_control); -} - -static int mrst_set_alarm(struct device *dev, struct rtc_wkalrm *t) -{ - struct mrst_rtc *mrst = dev_get_drvdata(dev); - unsigned char hrs, min, sec; - int ret = 0; - - if (!mrst->irq) - return -eio; - - hrs = t->time.tm_hour; - min = t->time.tm_min; - sec = t->time.tm_sec; - - spin_lock_irq(&rtc_lock); - /* next rtc irq must not be from previous alarm setting */ - mrst_irq_disable(mrst, rtc_aie); - - /* update alarm */ - vrtc_cmos_write(hrs, rtc_hours_alarm); - vrtc_cmos_write(min, rtc_minutes_alarm); - vrtc_cmos_write(sec, rtc_seconds_alarm); - - spin_unlock_irq(&rtc_lock); - - ret = intel_scu_ipc_simple_command(ipcmsg_vrtc, ipc_cmd_vrtc_setalarm); - if (ret) - return ret; - - spin_lock_irq(&rtc_lock); - if (t->enabled) - mrst_irq_enable(mrst, rtc_aie); - - spin_unlock_irq(&rtc_lock); - - return 0; -} - -/* currently, the vrtc doesn't support uie on/off */ -static int mrst_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) -{ - struct mrst_rtc *mrst = dev_get_drvdata(dev); - unsigned long flags; - - spin_lock_irqsave(&rtc_lock, flags); - if (enabled) - mrst_irq_enable(mrst, rtc_aie); - else - mrst_irq_disable(mrst, rtc_aie); - spin_unlock_irqrestore(&rtc_lock, flags); - return 0; -} - - -#if is_enabled(config_rtc_intf_proc) - -static int mrst_procfs(struct device *dev, struct seq_file *seq) -{ - unsigned char rtc_control; - - spin_lock_irq(&rtc_lock); - rtc_control = vrtc_cmos_read(rtc_control); - spin_unlock_irq(&rtc_lock); - - seq_printf(seq, - "periodic_irq : %s " - "alarm : %s " - "bcd : no " - "periodic_freq : daily (not adjustable) ", - (rtc_control & rtc_pie) ? "on" : "off", - (rtc_control & rtc_aie) ? "on" : "off"); - - return 0; -} - -#else -#define mrst_procfs null -#endif - -static const struct rtc_class_ops mrst_rtc_ops = { - .read_time = mrst_read_time, - .set_time = mrst_set_time, - .read_alarm = mrst_read_alarm, - .set_alarm = mrst_set_alarm, - .proc = mrst_procfs, - .alarm_irq_enable = mrst_rtc_alarm_irq_enable, -}; - -static struct mrst_rtc mrst_rtc; - -/* - * when vrtc irq is captured by scu fw, fw will clear the aie bit in - * reg b, so no need for this driver to clear it - */ -static irqreturn_t mrst_rtc_irq(int irq, void *p) -{ - u8 irqstat; - - spin_lock(&rtc_lock); - /* this read will clear all irq flags inside reg c */ - irqstat = vrtc_cmos_read(rtc_intr_flags); - spin_unlock(&rtc_lock); - - irqstat &= rtc_irqmask | rtc_irqf; - if (is_intr(irqstat)) { - rtc_update_irq(p, 1, irqstat); - return irq_handled; - } - return irq_none; -} - -static int vrtc_mrst_do_probe(struct device *dev, struct resource *iomem, - int rtc_irq) -{ - int retval = 0; - unsigned char rtc_control; - - /* there can be only one ... */ - if (mrst_rtc.dev) - return -ebusy; - - if (!iomem) - return -enodev; - - iomem = devm_request_mem_region(dev, iomem->start, resource_size(iomem), - driver_name); - if (!iomem) { - dev_dbg(dev, "i/o mem already in use. "); - return -ebusy; - } - - mrst_rtc.irq = rtc_irq; - mrst_rtc.dev = dev; - dev_set_drvdata(dev, &mrst_rtc); - - mrst_rtc.rtc = devm_rtc_allocate_device(dev); - if (is_err(mrst_rtc.rtc)) - return ptr_err(mrst_rtc.rtc); - - mrst_rtc.rtc->ops = &mrst_rtc_ops; - - rename_region(iomem, dev_name(&mrst_rtc.rtc->dev)); - - spin_lock_irq(&rtc_lock); - mrst_irq_disable(&mrst_rtc, rtc_pie | rtc_aie); - rtc_control = vrtc_cmos_read(rtc_control); - spin_unlock_irq(&rtc_lock); - - if (!(rtc_control & rtc_24h) || (rtc_control & (rtc_dm_binary))) - dev_dbg(dev, "todo: support more than 24-hr bcd mode "); - - if (rtc_irq) { - retval = devm_request_irq(dev, rtc_irq, mrst_rtc_irq, - 0, dev_name(&mrst_rtc.rtc->dev), - mrst_rtc.rtc); - if (retval < 0) { - dev_dbg(dev, "irq %d is already in use, err %d ", - rtc_irq, retval); - goto cleanup0; - } - } - - retval = devm_rtc_register_device(mrst_rtc.rtc); - if (retval) - goto cleanup0; - - dev_dbg(dev, "initialised "); - return 0; - -cleanup0: - mrst_rtc.dev = null; - dev_err(dev, "rtc-mrst: unable to initialise "); - return retval; -} - -static void rtc_mrst_do_shutdown(void) -{ - spin_lock_irq(&rtc_lock); - mrst_irq_disable(&mrst_rtc, rtc_irqmask); - spin_unlock_irq(&rtc_lock); -} - -static void rtc_mrst_do_remove(struct device *dev) -{ - struct mrst_rtc *mrst = dev_get_drvdata(dev); - - rtc_mrst_do_shutdown(); - - mrst->rtc = null; - mrst->dev = null; -} - -#ifdef config_pm_sleep -static int mrst_suspend(struct device *dev) -{ - struct mrst_rtc *mrst = dev_get_drvdata(dev); - unsigned char tmp; - - /* only the alarm might be a wakeup event source */ - spin_lock_irq(&rtc_lock); - mrst->suspend_ctrl = tmp = vrtc_cmos_read(rtc_control); - if (tmp & (rtc_pie | rtc_aie)) { - unsigned char mask; - - if (device_may_wakeup(dev)) - mask = rtc_irqmask & ~rtc_aie; - else - mask = rtc_irqmask; - tmp &= ~mask; - vrtc_cmos_write(tmp, rtc_control); - - mrst_checkintr(mrst, tmp); - } - spin_unlock_irq(&rtc_lock); - - if (tmp & rtc_aie) { - mrst->enabled_wake = 1; - enable_irq_wake(mrst->irq); - } - - dev_dbg(&mrst_rtc.rtc->dev, "suspend%s, ctrl %02x ", - (tmp & rtc_aie) ? ", alarm may wake" : "", - tmp); - - return 0; -} - -/* - * we want rtc alarms to wake us from the deep power saving state - */ -static inline int mrst_poweroff(struct device *dev) -{ - return mrst_suspend(dev); -} - -static int mrst_resume(struct device *dev) -{ - struct mrst_rtc *mrst = dev_get_drvdata(dev); - unsigned char tmp = mrst->suspend_ctrl; - - /* re-enable any irqs previously active */ - if (tmp & rtc_irqmask) { - unsigned char mask; - - if (mrst->enabled_wake) { - disable_irq_wake(mrst->irq); - mrst->enabled_wake = 0; - } - - spin_lock_irq(&rtc_lock); - do { - vrtc_cmos_write(tmp, rtc_control); - - mask = vrtc_cmos_read(rtc_intr_flags); - mask &= (tmp & rtc_irqmask) | rtc_irqf; - if (!is_intr(mask)) - break; - - rtc_update_irq(mrst->rtc, 1, mask); - tmp &= ~rtc_aie; - } while (mask & rtc_aie); - spin_unlock_irq(&rtc_lock); - } - - dev_dbg(&mrst_rtc.rtc->dev, "resume, ctrl %02x ", tmp); - - return 0; -} - -static simple_dev_pm_ops(mrst_pm_ops, mrst_suspend, mrst_resume); -#define mrst_pm_ops (&mrst_pm_ops) - -#else -#define mrst_pm_ops null - -static inline int mrst_poweroff(struct device *dev) -{ - return -enosys; -} - -#endif - -static int vrtc_mrst_platform_probe(struct platform_device *pdev) -{ - return vrtc_mrst_do_probe(&pdev->dev, - platform_get_resource(pdev, ioresource_mem, 0), - platform_get_irq(pdev, 0)); -} - -static int vrtc_mrst_platform_remove(struct platform_device *pdev) -{ - rtc_mrst_do_remove(&pdev->dev); - return 0; -} - -static void vrtc_mrst_platform_shutdown(struct platform_device *pdev) -{ - if (system_state == system_power_off && !mrst_poweroff(&pdev->dev)) - return; - - rtc_mrst_do_shutdown(); -} - -module_alias("platform:vrtc_mrst"); - -static struct platform_driver vrtc_mrst_platform_driver = { - .probe = vrtc_mrst_platform_probe, - .remove = vrtc_mrst_platform_remove, - .shutdown = vrtc_mrst_platform_shutdown, - .driver = { - .name = driver_name, - .pm = mrst_pm_ops, - } -}; - -module_platform_driver(vrtc_mrst_platform_driver); - -module_author("jacob pan; feng tang"); -module_description("driver for moorestown virtual rtc"); -module_license("gpl");
|
Real Time Clock (RTC)
|
c5158358dffc8c7962f412c2c89fcce4e5fff96f
|
andy shevchenko
|
drivers
|
rtc
| |
rtc: tx4939: remove driver
|
cpu support for tx49xx is getting removed, so remove rtc driver for it.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['tx4939']
|
['kconfig', 'c', 'makefile']
| 3
| 0
| 311
|
--- diff --git a/drivers/rtc/kconfig b/drivers/rtc/kconfig --- a/drivers/rtc/kconfig +++ b/drivers/rtc/kconfig -config rtc_drv_tx4939 - tristate "tx4939 soc" - depends on soc_tx4939 || compile_test - help - driver for the internal rtc (realtime clock) module found on - toshiba tx4939 soc. - diff --git a/drivers/rtc/makefile b/drivers/rtc/makefile --- a/drivers/rtc/makefile +++ b/drivers/rtc/makefile -obj-$(config_rtc_drv_tx4939) += rtc-tx4939.o diff --git a/drivers/rtc/rtc-tx4939.c b/drivers/rtc/rtc-tx4939.c --- a/drivers/rtc/rtc-tx4939.c +++ /dev/null -// spdx-license-identifier: gpl-2.0 -/* - * tx4939 internal rtc driver - * based on rbtx49xx patch from celf patch archive. - * - * (c) copyright toshiba corporation 2005-2007 - */ -#include <linux/rtc.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <linux/module.h> -#include <linux/io.h> -#include <linux/gfp.h> - -#define tx4939_rtcctl_alme 0x00000080 -#define tx4939_rtcctl_almd 0x00000040 -#define tx4939_rtcctl_busy 0x00000020 - -#define tx4939_rtcctl_command 0x00000007 -#define tx4939_rtcctl_command_nop 0x00000000 -#define tx4939_rtcctl_command_gettime 0x00000001 -#define tx4939_rtcctl_command_settime 0x00000002 -#define tx4939_rtcctl_command_getalarm 0x00000003 -#define tx4939_rtcctl_command_setalarm 0x00000004 - -#define tx4939_rtctbc_pm 0x00000080 -#define tx4939_rtctbc_comp 0x0000007f - -#define tx4939_rtc_reg_ramsize 0x00000100 -#define tx4939_rtc_reg_rwbsize 0x00000006 - -struct tx4939_rtc_reg { - __u32 ctl; - __u32 adr; - __u32 dat; - __u32 tbc; -}; - -struct tx4939rtc_plat_data { - struct rtc_device *rtc; - struct tx4939_rtc_reg __iomem *rtcreg; - spinlock_t lock; -}; - -static int tx4939_rtc_cmd(struct tx4939_rtc_reg __iomem *rtcreg, int cmd) -{ - int i = 0; - - __raw_writel(cmd, &rtcreg->ctl); - /* this might take 30us (next 32.768khz clock) */ - while (__raw_readl(&rtcreg->ctl) & tx4939_rtcctl_busy) { - /* timeout on approx. 100us (@ gbus200mhz) */ - if (i++ > 200 * 100) - return -ebusy; - cpu_relax(); - } - return 0; -} - -static int tx4939_rtc_set_time(struct device *dev, struct rtc_time *tm) -{ - struct tx4939rtc_plat_data *pdata = dev_get_drvdata(dev); - struct tx4939_rtc_reg __iomem *rtcreg = pdata->rtcreg; - unsigned long secs = rtc_tm_to_time64(tm); - int i, ret; - unsigned char buf[6]; - - buf[0] = 0; - buf[1] = 0; - buf[2] = secs; - buf[3] = secs >> 8; - buf[4] = secs >> 16; - buf[5] = secs >> 24; - spin_lock_irq(&pdata->lock); - __raw_writel(0, &rtcreg->adr); - for (i = 0; i < 6; i++) - __raw_writel(buf[i], &rtcreg->dat); - ret = tx4939_rtc_cmd(rtcreg, - tx4939_rtcctl_command_settime | - (__raw_readl(&rtcreg->ctl) & tx4939_rtcctl_alme)); - spin_unlock_irq(&pdata->lock); - return ret; -} - -static int tx4939_rtc_read_time(struct device *dev, struct rtc_time *tm) -{ - struct tx4939rtc_plat_data *pdata = dev_get_drvdata(dev); - struct tx4939_rtc_reg __iomem *rtcreg = pdata->rtcreg; - int i, ret; - unsigned long sec; - unsigned char buf[6]; - - spin_lock_irq(&pdata->lock); - ret = tx4939_rtc_cmd(rtcreg, - tx4939_rtcctl_command_gettime | - (__raw_readl(&rtcreg->ctl) & tx4939_rtcctl_alme)); - if (ret) { - spin_unlock_irq(&pdata->lock); - return ret; - } - __raw_writel(2, &rtcreg->adr); - for (i = 2; i < 6; i++) - buf[i] = __raw_readl(&rtcreg->dat); - spin_unlock_irq(&pdata->lock); - sec = ((unsigned long)buf[5] << 24) | (buf[4] << 16) | - (buf[3] << 8) | buf[2]; - rtc_time64_to_tm(sec, tm); - return 0; -} - -static int tx4939_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) -{ - struct tx4939rtc_plat_data *pdata = dev_get_drvdata(dev); - struct tx4939_rtc_reg __iomem *rtcreg = pdata->rtcreg; - int i, ret; - unsigned long sec; - unsigned char buf[6]; - - sec = rtc_tm_to_time64(&alrm->time); - buf[0] = 0; - buf[1] = 0; - buf[2] = sec; - buf[3] = sec >> 8; - buf[4] = sec >> 16; - buf[5] = sec >> 24; - spin_lock_irq(&pdata->lock); - __raw_writel(0, &rtcreg->adr); - for (i = 0; i < 6; i++) - __raw_writel(buf[i], &rtcreg->dat); - ret = tx4939_rtc_cmd(rtcreg, tx4939_rtcctl_command_setalarm | - (alrm->enabled ? tx4939_rtcctl_alme : 0)); - spin_unlock_irq(&pdata->lock); - return ret; -} - -static int tx4939_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) -{ - struct tx4939rtc_plat_data *pdata = dev_get_drvdata(dev); - struct tx4939_rtc_reg __iomem *rtcreg = pdata->rtcreg; - int i, ret; - unsigned long sec; - unsigned char buf[6]; - u32 ctl; - - spin_lock_irq(&pdata->lock); - ret = tx4939_rtc_cmd(rtcreg, - tx4939_rtcctl_command_getalarm | - (__raw_readl(&rtcreg->ctl) & tx4939_rtcctl_alme)); - if (ret) { - spin_unlock_irq(&pdata->lock); - return ret; - } - __raw_writel(2, &rtcreg->adr); - for (i = 2; i < 6; i++) - buf[i] = __raw_readl(&rtcreg->dat); - ctl = __raw_readl(&rtcreg->ctl); - alrm->enabled = (ctl & tx4939_rtcctl_alme) ? 1 : 0; - alrm->pending = (ctl & tx4939_rtcctl_almd) ? 1 : 0; - spin_unlock_irq(&pdata->lock); - sec = ((unsigned long)buf[5] << 24) | (buf[4] << 16) | - (buf[3] << 8) | buf[2]; - rtc_time64_to_tm(sec, &alrm->time); - return rtc_valid_tm(&alrm->time); -} - -static int tx4939_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) -{ - struct tx4939rtc_plat_data *pdata = dev_get_drvdata(dev); - - spin_lock_irq(&pdata->lock); - tx4939_rtc_cmd(pdata->rtcreg, - tx4939_rtcctl_command_nop | - (enabled ? tx4939_rtcctl_alme : 0)); - spin_unlock_irq(&pdata->lock); - return 0; -} - -static irqreturn_t tx4939_rtc_interrupt(int irq, void *dev_id) -{ - struct tx4939rtc_plat_data *pdata = dev_get_drvdata(dev_id); - struct tx4939_rtc_reg __iomem *rtcreg = pdata->rtcreg; - unsigned long events = rtc_irqf; - - spin_lock(&pdata->lock); - if (__raw_readl(&rtcreg->ctl) & tx4939_rtcctl_almd) { - events |= rtc_af; - tx4939_rtc_cmd(rtcreg, tx4939_rtcctl_command_nop); - } - spin_unlock(&pdata->lock); - rtc_update_irq(pdata->rtc, 1, events); - - return irq_handled; -} - -static const struct rtc_class_ops tx4939_rtc_ops = { - .read_time = tx4939_rtc_read_time, - .read_alarm = tx4939_rtc_read_alarm, - .set_alarm = tx4939_rtc_set_alarm, - .set_time = tx4939_rtc_set_time, - .alarm_irq_enable = tx4939_rtc_alarm_irq_enable, -}; - -static int tx4939_nvram_read(void *priv, unsigned int pos, void *val, - size_t bytes) -{ - struct tx4939rtc_plat_data *pdata = priv; - struct tx4939_rtc_reg __iomem *rtcreg = pdata->rtcreg; - u8 *buf = val; - - spin_lock_irq(&pdata->lock); - for (; bytes; bytes--) { - __raw_writel(pos++, &rtcreg->adr); - *buf++ = __raw_readl(&rtcreg->dat); - } - spin_unlock_irq(&pdata->lock); - return 0; -} - -static int tx4939_nvram_write(void *priv, unsigned int pos, void *val, - size_t bytes) -{ - struct tx4939rtc_plat_data *pdata = priv; - struct tx4939_rtc_reg __iomem *rtcreg = pdata->rtcreg; - u8 *buf = val; - - spin_lock_irq(&pdata->lock); - for (; bytes; bytes--) { - __raw_writel(pos++, &rtcreg->adr); - __raw_writel(*buf++, &rtcreg->dat); - } - spin_unlock_irq(&pdata->lock); - return 0; -} - -static int __init tx4939_rtc_probe(struct platform_device *pdev) -{ - struct rtc_device *rtc; - struct tx4939rtc_plat_data *pdata; - int irq, ret; - struct nvmem_config nvmem_cfg = { - .name = "tx4939_nvram", - .size = tx4939_rtc_reg_ramsize, - .reg_read = tx4939_nvram_read, - .reg_write = tx4939_nvram_write, - }; - - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return -enodev; - pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), gfp_kernel); - if (!pdata) - return -enomem; - platform_set_drvdata(pdev, pdata); - - pdata->rtcreg = devm_platform_ioremap_resource(pdev, 0); - if (is_err(pdata->rtcreg)) - return ptr_err(pdata->rtcreg); - - spin_lock_init(&pdata->lock); - tx4939_rtc_cmd(pdata->rtcreg, tx4939_rtcctl_command_nop); - if (devm_request_irq(&pdev->dev, irq, tx4939_rtc_interrupt, - 0, pdev->name, &pdev->dev) < 0) - return -ebusy; - rtc = devm_rtc_allocate_device(&pdev->dev); - if (is_err(rtc)) - return ptr_err(rtc); - - rtc->ops = &tx4939_rtc_ops; - rtc->range_max = u32_max; - - pdata->rtc = rtc; - - nvmem_cfg.priv = pdata; - ret = devm_rtc_nvmem_register(rtc, &nvmem_cfg); - if (ret) - return ret; - - return devm_rtc_register_device(rtc); -} - -static int __exit tx4939_rtc_remove(struct platform_device *pdev) -{ - struct tx4939rtc_plat_data *pdata = platform_get_drvdata(pdev); - - spin_lock_irq(&pdata->lock); - tx4939_rtc_cmd(pdata->rtcreg, tx4939_rtcctl_command_nop); - spin_unlock_irq(&pdata->lock); - return 0; -} - -static struct platform_driver tx4939_rtc_driver = { - .remove = __exit_p(tx4939_rtc_remove), - .driver = { - .name = "tx4939rtc", - }, -}; - -module_platform_driver_probe(tx4939_rtc_driver, tx4939_rtc_probe); - -module_author("atsushi nemoto <anemo@mba.ocn.ne.jp>"); -module_description("tx4939 internal rtc driver"); -module_license("gpl v2"); -module_alias("platform:tx4939rtc");
|
Real Time Clock (RTC)
|
446667df283002fdda0530523347ffd1cf053373
|
thomas bogendoerfer
|
drivers
|
rtc
| |
pinctrl: add risc-v canaan kendryte k210 fpioa driver
|
add the pinctrl-k210.c pinctrl driver for the canaan kendryte k210 field programmable io array (fpioa) to allow configuring the soc pin functions. the k210 has 48 programmable pins which can take any of 256 possible functions.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add risc-v canaan kendryte k210 fpioa driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['c', 'socs', 'kconfig', 'maintainers', 'makefile']
| 5
| 1,007
| 0
|
--- diff --git a/maintainers b/maintainers --- a/maintainers +++ b/maintainers +canaan/kendryte k210 soc fpioa driver +m: damien le moal <damien.lemoal@wdc.com> +l: linux-riscv@lists.infradead.org +l: linux-gpio@vger.kernel.org (pinctrl driver) +f: documentation/devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml +f: drivers/pinctrl/pinctrl-k210.c + diff --git a/arch/riscv/kconfig.socs b/arch/riscv/kconfig.socs --- a/arch/riscv/kconfig.socs +++ b/arch/riscv/kconfig.socs + select pinctrl diff --git a/drivers/pinctrl/kconfig b/drivers/pinctrl/kconfig --- a/drivers/pinctrl/kconfig +++ b/drivers/pinctrl/kconfig +config pinctrl_k210 + bool "pinctrl driver for the canaan kendryte k210 soc" + depends on riscv && soc_canaan && of + select generic_pinmux_functions + select generic_pinconf + select gpiolib + select of_gpio + select regmap_mmio + default soc_canaan + help + add support for the canaan kendryte k210 risc-v soc field + programmable io array (fpioa) controller. + diff --git a/drivers/pinctrl/makefile b/drivers/pinctrl/makefile --- a/drivers/pinctrl/makefile +++ b/drivers/pinctrl/makefile +obj-$(config_pinctrl_k210) += pinctrl-k210.o diff --git a/drivers/pinctrl/pinctrl-k210.c b/drivers/pinctrl/pinctrl-k210.c --- /dev/null +++ b/drivers/pinctrl/pinctrl-k210.c +// spdx-license-identifier: gpl-2.0-or-later +/* + * copyright (c) 2020 sean anderson <seanga2@gmail.com> + * copyright (c) 2020 western digital corporation or its affiliates. + */ +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/clk.h> +#include <linux/mfd/syscon.h> +#include <linux/platform_device.h> +#include <linux/bitfield.h> +#include <linux/regmap.h> +#include <linux/slab.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/io.h> + +#include <dt-bindings/pinctrl/k210-fpioa.h> + +#include "core.h" +#include "pinconf.h" +#include "pinctrl-utils.h" + +/* + * the k210 only implements 8 drive levels, even though + * there is register space for 16 + */ +#define k210_pc_drive_mask genmask(11, 8) +#define k210_pc_drive_shift 8 +#define k210_pc_drive_0 (0 << k210_pc_drive_shift) +#define k210_pc_drive_1 (1 << k210_pc_drive_shift) +#define k210_pc_drive_2 (2 << k210_pc_drive_shift) +#define k210_pc_drive_3 (3 << k210_pc_drive_shift) +#define k210_pc_drive_4 (4 << k210_pc_drive_shift) +#define k210_pc_drive_5 (5 << k210_pc_drive_shift) +#define k210_pc_drive_6 (6 << k210_pc_drive_shift) +#define k210_pc_drive_7 (7 << k210_pc_drive_shift) +#define k210_pc_drive_max 7 +#define k210_pc_mode_mask genmask(23, 12) + +/* + * output enabled == pc_oe & (pc_oe_inv ^ function_oe) + * where function_oe is a physical signal from the function. + */ +#define k210_pc_oe bit(12) /* output enable */ +#define k210_pc_oe_inv bit(13) /* invert output enable */ +#define k210_pc_do_oe bit(14) /* set data out to output enable sig */ +#define k210_pc_do_inv bit(15) /* invert final data output */ +#define k210_pc_pu bit(16) /* pull up */ +#define k210_pc_pd bit(17) /* pull down */ +/* strong pull up not implemented on k210 */ +#define k210_pc_sl bit(19) /* reduce slew rate */ +/* same semantics as oe above */ +#define k210_pc_ie bit(20) /* input enable */ +#define k210_pc_ie_inv bit(21) /* invert input enable */ +#define k210_pc_di_inv bit(22) /* invert data input */ +#define k210_pc_st bit(23) /* schmitt trigger */ +#define k210_pc_di bit(31) /* raw data input */ + +#define k210_pc_bias_mask (k210_pc_pu & k210_pc_pd) + +#define k210_pc_mode_in (k210_pc_ie | k210_pc_st) +#define k210_pc_mode_out (k210_pc_drive_7 | k210_pc_oe) +#define k210_pc_mode_i2c (k210_pc_mode_in | k210_pc_sl | \ + k210_pc_oe | k210_pc_pu) +#define k210_pc_mode_sccb (k210_pc_mode_i2c | \ + k210_pc_oe_inv | k210_pc_ie_inv) +#define k210_pc_mode_spi (k210_pc_mode_in | k210_pc_ie_inv | \ + k210_pc_mode_out | k210_pc_oe_inv) +#define k210_pc_mode_gpio (k210_pc_mode_in | k210_pc_mode_out) + +#define k210_pg_func genmask(7, 0) +#define k210_pg_do bit(8) +#define k210_pg_pin genmask(22, 16) + +/* + * struct k210_fpioa: kendryte k210 fpioa memory mapped registers + * @pins: 48 32-bits io pin registers + * @tie_en: 256 (one per function) input tie enable bits + * @tie_val: 256 (one per function) input tie value bits + */ +struct k210_fpioa { + u32 pins[48]; + u32 tie_en[8]; + u32 tie_val[8]; +}; + +struct k210_fpioa_data { + + struct device *dev; + struct pinctrl_dev *pctl; + + struct k210_fpioa __iomem *fpioa; + struct regmap *sysctl_map; + u32 power_offset; + struct clk *clk; + struct clk *pclk; +}; + +#define k210_pin_name(i) ("io_" #i) +#define k210_pin(i) [(i)] = pinctrl_pin((i), k210_pin_name(i)) + +static const struct pinctrl_pin_desc k210_pins[] = { + k210_pin(0), k210_pin(1), k210_pin(2), + k210_pin(3), k210_pin(4), k210_pin(5), + k210_pin(6), k210_pin(7), k210_pin(8), + k210_pin(9), k210_pin(10), k210_pin(11), + k210_pin(12), k210_pin(13), k210_pin(14), + k210_pin(15), k210_pin(16), k210_pin(17), + k210_pin(18), k210_pin(19), k210_pin(20), + k210_pin(21), k210_pin(22), k210_pin(23), + k210_pin(24), k210_pin(25), k210_pin(26), + k210_pin(27), k210_pin(28), k210_pin(29), + k210_pin(30), k210_pin(31), k210_pin(32), + k210_pin(33), k210_pin(34), k210_pin(35), + k210_pin(36), k210_pin(37), k210_pin(38), + k210_pin(39), k210_pin(40), k210_pin(41), + k210_pin(42), k210_pin(43), k210_pin(44), + k210_pin(45), k210_pin(46), k210_pin(47) +}; + +#define k210_npins array_size(k210_pins) + +/* + * pin groups: each of the 48 programmable pins is a group. + * to this are added 8 power domain groups, which for the purposes of + * the pin subsystem, contain no pins. the power domain groups only exist + * to set the power level. the id should never be used (since there are + * no pins 48-55). + */ +static const char *const k210_group_names[] = { + /* the first 48 groups are for pins, one each */ + k210_pin_name(0), k210_pin_name(1), k210_pin_name(2), + k210_pin_name(3), k210_pin_name(4), k210_pin_name(5), + k210_pin_name(6), k210_pin_name(7), k210_pin_name(8), + k210_pin_name(9), k210_pin_name(10), k210_pin_name(11), + k210_pin_name(12), k210_pin_name(13), k210_pin_name(14), + k210_pin_name(15), k210_pin_name(16), k210_pin_name(17), + k210_pin_name(18), k210_pin_name(19), k210_pin_name(20), + k210_pin_name(21), k210_pin_name(22), k210_pin_name(23), + k210_pin_name(24), k210_pin_name(25), k210_pin_name(26), + k210_pin_name(27), k210_pin_name(28), k210_pin_name(29), + k210_pin_name(30), k210_pin_name(31), k210_pin_name(32), + k210_pin_name(33), k210_pin_name(34), k210_pin_name(35), + k210_pin_name(36), k210_pin_name(37), k210_pin_name(38), + k210_pin_name(39), k210_pin_name(40), k210_pin_name(41), + k210_pin_name(42), k210_pin_name(43), k210_pin_name(44), + k210_pin_name(45), k210_pin_name(46), k210_pin_name(47), + [48] = "a0", [49] = "a1", [50] = "a2", + [51] = "b3", [52] = "b4", [53] = "b5", + [54] = "c6", [55] = "c7" +}; + +#define k210_ngroups array_size(k210_group_names) + +enum k210_pinctrl_mode_id { + k210_pc_default_disabled, + k210_pc_default_in, + k210_pc_default_in_tie, + k210_pc_default_out, + k210_pc_default_i2c, + k210_pc_default_sccb, + k210_pc_default_spi, + k210_pc_default_gpio, + k210_pc_default_int13, +}; + +#define k210_pc_default(mode) \ + [k210_pc_default_##mode] = k210_pc_mode_##mode + +static const u32 k210_pinconf_mode_id_to_mode[] = { + [k210_pc_default_disabled] = 0, + k210_pc_default(in), + [k210_pc_default_in_tie] = k210_pc_mode_in, + k210_pc_default(out), + k210_pc_default(i2c), + k210_pc_default(sccb), + k210_pc_default(spi), + k210_pc_default(gpio), + [k210_pc_default_int13] = k210_pc_mode_in | k210_pc_pu, +}; + +#undef default + +/* + * pin functions configuration information. + */ +struct k210_pcf_info { + char name[15]; + u8 mode_id; +}; + +#define k210_func(id, mode) \ + [k210_pcf_##id] = { \ + .name = #id, \ + .mode_id = k210_pc_default_##mode \ + } + +static const struct k210_pcf_info k210_pcf_infos[] = { + k210_func(jtag_tclk, in), + k210_func(jtag_tdi, in), + k210_func(jtag_tms, in), + k210_func(jtag_tdo, out), + k210_func(spi0_d0, spi), + k210_func(spi0_d1, spi), + k210_func(spi0_d2, spi), + k210_func(spi0_d3, spi), + k210_func(spi0_d4, spi), + k210_func(spi0_d5, spi), + k210_func(spi0_d6, spi), + k210_func(spi0_d7, spi), + k210_func(spi0_ss0, out), + k210_func(spi0_ss1, out), + k210_func(spi0_ss2, out), + k210_func(spi0_ss3, out), + k210_func(spi0_arb, in_tie), + k210_func(spi0_sclk, out), + k210_func(uarths_rx, in), + k210_func(uarths_tx, out), + k210_func(resv6, in), + k210_func(resv7, in), + k210_func(clk_spi1, out), + k210_func(clk_i2c1, out), + k210_func(gpiohs0, gpio), + k210_func(gpiohs1, gpio), + k210_func(gpiohs2, gpio), + k210_func(gpiohs3, gpio), + k210_func(gpiohs4, gpio), + k210_func(gpiohs5, gpio), + k210_func(gpiohs6, gpio), + k210_func(gpiohs7, gpio), + k210_func(gpiohs8, gpio), + k210_func(gpiohs9, gpio), + k210_func(gpiohs10, gpio), + k210_func(gpiohs11, gpio), + k210_func(gpiohs12, gpio), + k210_func(gpiohs13, gpio), + k210_func(gpiohs14, gpio), + k210_func(gpiohs15, gpio), + k210_func(gpiohs16, gpio), + k210_func(gpiohs17, gpio), + k210_func(gpiohs18, gpio), + k210_func(gpiohs19, gpio), + k210_func(gpiohs20, gpio), + k210_func(gpiohs21, gpio), + k210_func(gpiohs22, gpio), + k210_func(gpiohs23, gpio), + k210_func(gpiohs24, gpio), + k210_func(gpiohs25, gpio), + k210_func(gpiohs26, gpio), + k210_func(gpiohs27, gpio), + k210_func(gpiohs28, gpio), + k210_func(gpiohs29, gpio), + k210_func(gpiohs30, gpio), + k210_func(gpiohs31, gpio), + k210_func(gpio0, gpio), + k210_func(gpio1, gpio), + k210_func(gpio2, gpio), + k210_func(gpio3, gpio), + k210_func(gpio4, gpio), + k210_func(gpio5, gpio), + k210_func(gpio6, gpio), + k210_func(gpio7, gpio), + k210_func(uart1_rx, in), + k210_func(uart1_tx, out), + k210_func(uart2_rx, in), + k210_func(uart2_tx, out), + k210_func(uart3_rx, in), + k210_func(uart3_tx, out), + k210_func(spi1_d0, spi), + k210_func(spi1_d1, spi), + k210_func(spi1_d2, spi), + k210_func(spi1_d3, spi), + k210_func(spi1_d4, spi), + k210_func(spi1_d5, spi), + k210_func(spi1_d6, spi), + k210_func(spi1_d7, spi), + k210_func(spi1_ss0, out), + k210_func(spi1_ss1, out), + k210_func(spi1_ss2, out), + k210_func(spi1_ss3, out), + k210_func(spi1_arb, in_tie), + k210_func(spi1_sclk, out), + k210_func(spi2_d0, spi), + k210_func(spi2_ss, in), + k210_func(spi2_sclk, in), + k210_func(i2s0_mclk, out), + k210_func(i2s0_sclk, out), + k210_func(i2s0_ws, out), + k210_func(i2s0_in_d0, in), + k210_func(i2s0_in_d1, in), + k210_func(i2s0_in_d2, in), + k210_func(i2s0_in_d3, in), + k210_func(i2s0_out_d0, out), + k210_func(i2s0_out_d1, out), + k210_func(i2s0_out_d2, out), + k210_func(i2s0_out_d3, out), + k210_func(i2s1_mclk, out), + k210_func(i2s1_sclk, out), + k210_func(i2s1_ws, out), + k210_func(i2s1_in_d0, in), + k210_func(i2s1_in_d1, in), + k210_func(i2s1_in_d2, in), + k210_func(i2s1_in_d3, in), + k210_func(i2s1_out_d0, out), + k210_func(i2s1_out_d1, out), + k210_func(i2s1_out_d2, out), + k210_func(i2s1_out_d3, out), + k210_func(i2s2_mclk, out), + k210_func(i2s2_sclk, out), + k210_func(i2s2_ws, out), + k210_func(i2s2_in_d0, in), + k210_func(i2s2_in_d1, in), + k210_func(i2s2_in_d2, in), + k210_func(i2s2_in_d3, in), + k210_func(i2s2_out_d0, out), + k210_func(i2s2_out_d1, out), + k210_func(i2s2_out_d2, out), + k210_func(i2s2_out_d3, out), + k210_func(resv0, disabled), + k210_func(resv1, disabled), + k210_func(resv2, disabled), + k210_func(resv3, disabled), + k210_func(resv4, disabled), + k210_func(resv5, disabled), + k210_func(i2c0_sclk, i2c), + k210_func(i2c0_sda, i2c), + k210_func(i2c1_sclk, i2c), + k210_func(i2c1_sda, i2c), + k210_func(i2c2_sclk, i2c), + k210_func(i2c2_sda, i2c), + k210_func(dvp_xclk, out), + k210_func(dvp_rst, out), + k210_func(dvp_pwdn, out), + k210_func(dvp_vsync, in), + k210_func(dvp_hsync, in), + k210_func(dvp_pclk, in), + k210_func(dvp_d0, in), + k210_func(dvp_d1, in), + k210_func(dvp_d2, in), + k210_func(dvp_d3, in), + k210_func(dvp_d4, in), + k210_func(dvp_d5, in), + k210_func(dvp_d6, in), + k210_func(dvp_d7, in), + k210_func(sccb_sclk, sccb), + k210_func(sccb_sda, sccb), + k210_func(uart1_cts, in), + k210_func(uart1_dsr, in), + k210_func(uart1_dcd, in), + k210_func(uart1_ri, in), + k210_func(uart1_sir_in, in), + k210_func(uart1_dtr, out), + k210_func(uart1_rts, out), + k210_func(uart1_out2, out), + k210_func(uart1_out1, out), + k210_func(uart1_sir_out, out), + k210_func(uart1_baud, out), + k210_func(uart1_re, out), + k210_func(uart1_de, out), + k210_func(uart1_rs485_en, out), + k210_func(uart2_cts, in), + k210_func(uart2_dsr, in), + k210_func(uart2_dcd, in), + k210_func(uart2_ri, in), + k210_func(uart2_sir_in, in), + k210_func(uart2_dtr, out), + k210_func(uart2_rts, out), + k210_func(uart2_out2, out), + k210_func(uart2_out1, out), + k210_func(uart2_sir_out, out), + k210_func(uart2_baud, out), + k210_func(uart2_re, out), + k210_func(uart2_de, out), + k210_func(uart2_rs485_en, out), + k210_func(uart3_cts, in), + k210_func(uart3_dsr, in), + k210_func(uart3_dcd, in), + k210_func(uart3_ri, in), + k210_func(uart3_sir_in, in), + k210_func(uart3_dtr, out), + k210_func(uart3_rts, out), + k210_func(uart3_out2, out), + k210_func(uart3_out1, out), + k210_func(uart3_sir_out, out), + k210_func(uart3_baud, out), + k210_func(uart3_re, out), + k210_func(uart3_de, out), + k210_func(uart3_rs485_en, out), + k210_func(timer0_toggle1, out), + k210_func(timer0_toggle2, out), + k210_func(timer0_toggle3, out), + k210_func(timer0_toggle4, out), + k210_func(timer1_toggle1, out), + k210_func(timer1_toggle2, out), + k210_func(timer1_toggle3, out), + k210_func(timer1_toggle4, out), + k210_func(timer2_toggle1, out), + k210_func(timer2_toggle2, out), + k210_func(timer2_toggle3, out), + k210_func(timer2_toggle4, out), + k210_func(clk_spi2, out), + k210_func(clk_i2c2, out), + k210_func(internal0, out), + k210_func(internal1, out), + k210_func(internal2, out), + k210_func(internal3, out), + k210_func(internal4, out), + k210_func(internal5, out), + k210_func(internal6, out), + k210_func(internal7, out), + k210_func(internal8, out), + k210_func(internal9, in), + k210_func(internal10, in), + k210_func(internal11, in), + k210_func(internal12, in), + k210_func(internal13, int13), + k210_func(internal14, i2c), + k210_func(internal15, in), + k210_func(internal16, in), + k210_func(internal17, in), + k210_func(constant, disabled), + k210_func(internal18, in), + k210_func(debug0, out), + k210_func(debug1, out), + k210_func(debug2, out), + k210_func(debug3, out), + k210_func(debug4, out), + k210_func(debug5, out), + k210_func(debug6, out), + k210_func(debug7, out), + k210_func(debug8, out), + k210_func(debug9, out), + k210_func(debug10, out), + k210_func(debug11, out), + k210_func(debug12, out), + k210_func(debug13, out), + k210_func(debug14, out), + k210_func(debug15, out), + k210_func(debug16, out), + k210_func(debug17, out), + k210_func(debug18, out), + k210_func(debug19, out), + k210_func(debug20, out), + k210_func(debug21, out), + k210_func(debug22, out), + k210_func(debug23, out), + k210_func(debug24, out), + k210_func(debug25, out), + k210_func(debug26, out), + k210_func(debug27, out), + k210_func(debug28, out), + k210_func(debug29, out), + k210_func(debug30, out), + k210_func(debug31, out), +}; + +#define pin_config_output_invert (pin_config_end + 1) +#define pin_config_input_invert (pin_config_end + 2) + +static const struct pinconf_generic_params k210_pinconf_custom_params[] = { + { "output-polarity-invert", pin_config_output_invert, 1 }, + { "input-polarity-invert", pin_config_input_invert, 1 }, +}; + +/* + * max drive strength in ua. + */ +static const int k210_pinconf_drive_strength[] = { + [0] = 11200, + [1] = 16800, + [2] = 22300, + [3] = 27800, + [4] = 33300, + [5] = 38700, + [6] = 44100, + [7] = 49500, +}; + +static int k210_pinconf_get_drive(unsigned int max_strength_ua) +{ + int i; + + for (i = k210_pc_drive_max; i; i--) { + if (k210_pinconf_drive_strength[i] <= max_strength_ua) + return i; + } + + return -einval; +} + +static void k210_pinmux_set_pin_function(struct pinctrl_dev *pctldev, + u32 pin, u32 func) +{ + struct k210_fpioa_data *pdata = pinctrl_dev_get_drvdata(pctldev); + const struct k210_pcf_info *info = &k210_pcf_infos[func]; + u32 mode = k210_pinconf_mode_id_to_mode[info->mode_id]; + u32 val = func | mode; + + dev_dbg(pdata->dev, "set pin %u function %s (%u) -> 0x%08x ", + pin, info->name, func, val); + + writel(val, &pdata->fpioa->pins[pin]); +} + +static int k210_pinconf_set_param(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned int param, unsigned int arg) +{ + struct k210_fpioa_data *pdata = pinctrl_dev_get_drvdata(pctldev); + u32 val = readl(&pdata->fpioa->pins[pin]); + int drive; + + dev_dbg(pdata->dev, "set pin %u param %u, arg 0x%x ", + pin, param, arg); + + switch (param) { + case pin_config_bias_disable: + val &= ~k210_pc_bias_mask; + break; + case pin_config_bias_pull_down: + if (!arg) + return -einval; + val |= k210_pc_pd; + break; + case pin_config_bias_pull_up: + if (!arg) + return -einval; + val |= k210_pc_pd; + break; + case pin_config_drive_strength: + arg *= 1000; + fallthrough; + case pin_config_drive_strength_ua: + drive = k210_pinconf_get_drive(arg); + if (drive < 0) + return drive; + val &= ~k210_pc_drive_mask; + val |= field_prep(k210_pc_drive_mask, drive); + break; + case pin_config_input_enable: + if (arg) + val |= k210_pc_ie; + else + val &= ~k210_pc_ie; + break; + case pin_config_input_schmitt_enable: + if (arg) + val |= k210_pc_st; + else + val &= ~k210_pc_st; + break; + case pin_config_output: + k210_pinmux_set_pin_function(pctldev, pin, k210_pcf_constant); + val = readl(&pdata->fpioa->pins[pin]); + val |= k210_pc_mode_out; + if (!arg) + val |= k210_pc_do_inv; + break; + case pin_config_output_enable: + if (arg) + val |= k210_pc_oe; + else + val &= ~k210_pc_oe; + break; + case pin_config_slew_rate: + if (arg) + val |= k210_pc_sl; + else + val &= ~k210_pc_sl; + break; + case pin_config_output_invert: + if (arg) + val |= k210_pc_do_inv; + else + val &= ~k210_pc_do_inv; + break; + case pin_config_input_invert: + if (arg) + val |= k210_pc_di_inv; + else + val &= ~k210_pc_di_inv; + break; + default: + return -einval; + } + + writel(val, &pdata->fpioa->pins[pin]); + + return 0; +} + +static int k210_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + unsigned int param, arg; + int i, ret; + + if (warn_on(pin >= k210_npins)) + return -einval; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + ret = k210_pinconf_set_param(pctldev, pin, param, arg); + if (ret) + return ret; + } + + return 0; +} + +static void k210_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin) +{ + struct k210_fpioa_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + seq_printf(s, "%#x", readl(&pdata->fpioa->pins[pin])); +} + +static int k210_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int selector, unsigned long *configs, + unsigned int num_configs) +{ + struct k210_fpioa_data *pdata = pinctrl_dev_get_drvdata(pctldev); + unsigned int param, arg; + u32 bit; + int i; + + /* pins should be configured with pinmux, not groups*/ + if (selector < k210_npins) + return -einval; + + /* otherwise it's a power domain */ + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + if (param != pin_config_power_source) + return -einval; + + arg = pinconf_to_config_argument(configs[i]); + bit = bit(selector - k210_npins); + regmap_update_bits(pdata->sysctl_map, + pdata->power_offset, + bit, arg ? bit : 0); + } + + return 0; +} + +static void k210_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned int selector) +{ + struct k210_fpioa_data *pdata = pinctrl_dev_get_drvdata(pctldev); + int ret; + u32 val; + + if (selector < k210_npins) + return k210_pinconf_dbg_show(pctldev, s, selector); + + ret = regmap_read(pdata->sysctl_map, pdata->power_offset, &val); + if (ret) { + dev_err(pdata->dev, "failed to read power reg "); + return; + } + + seq_printf(s, "%s: %s v", k210_group_names[selector], + val & bit(selector - k210_npins) ? "1.8" : "3.3"); +} + +static const struct pinconf_ops k210_pinconf_ops = { + .is_generic = true, + .pin_config_set = k210_pinconf_set, + .pin_config_group_set = k210_pinconf_group_set, + .pin_config_dbg_show = k210_pinconf_dbg_show, + .pin_config_group_dbg_show = k210_pinconf_group_dbg_show, +}; + +static int k210_pinmux_get_function_count(struct pinctrl_dev *pctldev) +{ + return array_size(k210_pcf_infos); +} + +static const char *k210_pinmux_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return k210_pcf_infos[selector].name; +} + +static int k210_pinmux_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + /* any function can be mapped to any pin */ + *groups = k210_group_names; + *num_groups = k210_npins; + + return 0; +} + +static int k210_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, + unsigned int group) +{ + /* can't mux power domains */ + if (group >= k210_npins) + return -einval; + + k210_pinmux_set_pin_function(pctldev, group, function); + + return 0; +} + +static const struct pinmux_ops k210_pinmux_ops = { + .get_functions_count = k210_pinmux_get_function_count, + .get_function_name = k210_pinmux_get_function_name, + .get_function_groups = k210_pinmux_get_function_groups, + .set_mux = k210_pinmux_set_mux, + .strict = true, +}; + +static int k210_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + return k210_ngroups; +} + +static const char *k210_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int group) +{ + return k210_group_names[group]; +} + +static int k210_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int group, + const unsigned int **pins, + unsigned int *npins) +{ + if (group >= k210_npins) { + *pins = null; + *npins = 0; + return 0; + } + + *pins = &k210_pins[group].number; + *npins = 1; + + return 0; +} + +static void k210_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int offset) +{ + seq_printf(s, "%s", dev_name(pctldev->dev)); +} + +static int k210_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *reserved_maps, + unsigned int *num_maps) +{ + struct property *prop; + const __be32 *p; + int ret, pinmux_groups; + u32 pinmux_group; + unsigned long *configs = null; + unsigned int num_configs = 0; + unsigned int reserve = 0; + + ret = of_property_count_strings(np, "groups"); + if (!ret) + return pinconf_generic_dt_subnode_to_map(pctldev, np, map, + reserved_maps, num_maps, + pin_map_type_configs_group); + + pinmux_groups = of_property_count_u32_elems(np, "pinmux"); + if (pinmux_groups <= 0) { + /* ignore this node */ + return 0; + } + + ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, + &num_configs); + if (ret < 0) { + dev_err(pctldev->dev, "%pof: could not parse node property ", + np); + return ret; + } + + reserve = pinmux_groups * (1 + num_configs); + ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, + reserve); + if (ret < 0) + goto exit; + + of_property_for_each_u32(np, "pinmux", prop, p, pinmux_group) { + const char *group_name, *func_name; + u32 pin = field_get(k210_pg_pin, pinmux_group); + u32 func = field_get(k210_pg_func, pinmux_group); + + if (pin >= k210_npins) { + ret = -einval; + goto exit; + } + + group_name = k210_group_names[pin]; + func_name = k210_pcf_infos[func].name; + + dev_dbg(pctldev->dev, "pinmux %s: pin %u func %s ", + np->name, pin, func_name); + + ret = pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, + num_maps, group_name, + func_name); + if (ret < 0) { + dev_err(pctldev->dev, "%pof add mux map failed %d ", + np, ret); + goto exit; + } + + if (num_configs) { + ret = pinctrl_utils_add_map_configs(pctldev, map, + reserved_maps, num_maps, group_name, + configs, num_configs, + pin_map_type_configs_pin); + if (ret < 0) { + dev_err(pctldev->dev, + "%pof add configs map failed %d ", + np, ret); + goto exit; + } + } + } + + ret = 0; + +exit: + kfree(configs); + return ret; +} + +static int k210_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + unsigned int reserved_maps; + struct device_node *np; + int ret; + + reserved_maps = 0; + *map = null; + *num_maps = 0; + + ret = k210_pinctrl_dt_subnode_to_map(pctldev, np_config, map, + &reserved_maps, num_maps); + if (ret < 0) + goto err; + + for_each_available_child_of_node(np_config, np) { + ret = k210_pinctrl_dt_subnode_to_map(pctldev, np, map, + &reserved_maps, num_maps); + if (ret < 0) + goto err; + } + return 0; + +err: + pinctrl_utils_free_map(pctldev, *map, *num_maps); + return ret; +} + + +static const struct pinctrl_ops k210_pinctrl_ops = { + .get_groups_count = k210_pinctrl_get_groups_count, + .get_group_name = k210_pinctrl_get_group_name, + .get_group_pins = k210_pinctrl_get_group_pins, + .pin_dbg_show = k210_pinctrl_pin_dbg_show, + .dt_node_to_map = k210_pinctrl_dt_node_to_map, + .dt_free_map = pinconf_generic_dt_free_map, +}; + +static struct pinctrl_desc k210_pinctrl_desc = { + .name = "k210-pinctrl", + .pins = k210_pins, + .npins = k210_npins, + .pctlops = &k210_pinctrl_ops, + .pmxops = &k210_pinmux_ops, + .confops = &k210_pinconf_ops, + .custom_params = k210_pinconf_custom_params, + .num_custom_params = array_size(k210_pinconf_custom_params), +}; + +static void k210_fpioa_init_ties(struct k210_fpioa_data *pdata) +{ + struct k210_fpioa __iomem *fpioa = pdata->fpioa; + u32 val; + int i, j; + + dev_dbg(pdata->dev, "init pin ties "); + + /* init pin functions input ties */ + for (i = 0; i < array_size(fpioa->tie_en); i++) { + val = 0; + for (j = 0; j < 32; j++) { + if (k210_pcf_infos[i * 32 + j].mode_id == + k210_pc_default_in_tie) { + dev_dbg(pdata->dev, + "tie_en function %d (%s) ", + i * 32 + j, + k210_pcf_infos[i * 32 + j].name); + val |= bit(j); + } + } + + /* set value before enable */ + writel(val, &fpioa->tie_val[i]); + writel(val, &fpioa->tie_en[i]); + } +} + +static int k210_fpioa_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct k210_fpioa_data *pdata; + int ret; + + dev_info(dev, "k210 fpioa pin controller "); + + pdata = devm_kzalloc(dev, sizeof(*pdata), gfp_kernel); + if (!pdata) + return -enomem; + + pdata->dev = dev; + platform_set_drvdata(pdev, pdata); + + pdata->fpioa = devm_platform_ioremap_resource(pdev, 0); + if (is_err(pdata->fpioa)) + return ptr_err(pdata->fpioa); + + pdata->clk = devm_clk_get(dev, "ref"); + if (is_err(pdata->clk)) + return ptr_err(pdata->clk); + + ret = clk_prepare_enable(pdata->clk); + if (ret) + return ret; + + pdata->pclk = devm_clk_get_optional(dev, "pclk"); + if (!is_err(pdata->pclk)) + clk_prepare_enable(pdata->pclk); + + pdata->sysctl_map = + syscon_regmap_lookup_by_phandle_args(np, + "canaan,k210-sysctl-power", + 1, &pdata->power_offset); + if (is_err(pdata->sysctl_map)) + return ptr_err(pdata->sysctl_map); + + k210_fpioa_init_ties(pdata); + + pdata->pctl = pinctrl_register(&k210_pinctrl_desc, dev, (void *)pdata); + if (is_err(pdata->pctl)) + return ptr_err(pdata->pctl); + + return 0; +} + +static const struct of_device_id k210_fpioa_dt_ids[] = { + { .compatible = "canaan,k210-fpioa" }, + { /* sentinel */ }, +}; + +static struct platform_driver k210_fpioa_driver = { + .probe = k210_fpioa_probe, + .driver = { + .name = "k210-fpioa", + .of_match_table = k210_fpioa_dt_ids, + }, +}; +builtin_platform_driver(k210_fpioa_driver);
|
Pin Controllers (pinctrl)
|
d4c34d09ab03e1e631fe195ddf35365a1273be9c
|
damien le moal
|
arch
|
riscv
| |
pinctrl: at91-pio4: add support for slew-rate
|
sama7g5 supports slew rate configuration. adapt the driver for this. for output switching frequencies lower than 50mhz the slew rate needs to be enabled. since most of the pins on sama7g5 fall into this category enabled the slew rate by default.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for slew-rate
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['at91-pio4']
|
['c']
| 1
| 27
| 0
|
--- diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c +#define atmel_pio_sr_mask bit(11) + * @slew_rate_support: slew rate support + unsigned int slew_rate_support; + * @slew_rate_support: slew rate support + unsigned int slew_rate_support; + case pin_config_slew_rate: + if (!atmel_pioctrl->slew_rate_support) + return -eopnotsupp; + if (!(res & atmel_pio_sr_mask)) + return -einval; + arg = 1; + break; + /* keep slew rate enabled by default. */ + if (atmel_pioctrl->slew_rate_support) + conf |= atmel_pio_sr_mask; + + case pin_config_slew_rate: + if (!atmel_pioctrl->slew_rate_support) + break; + /* and remove it if explicitly requested. */ + if (arg == 0) + conf &= ~atmel_pio_sr_mask; + break; + if (atmel_pioctrl->slew_rate_support && (conf & atmel_pio_sr_mask)) + seq_printf(s, "%s ", "slew-rate"); + .slew_rate_support = 1, + atmel_pioctrl->slew_rate_support = atmel_pioctrl_data->slew_rate_support;
|
Pin Controllers (pinctrl)
|
c709135e576b593d2ea4aef84b8fcd924a816a2d
|
claudiu beznea ludovic desroches ludovic desroches microchip com
|
drivers
|
pinctrl
| |
pinctrl: ingenic: improve jz4760 support
|
- add otg function and otg-vbus group.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
improve jz4760 support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['ingenic']
|
['c']
| 1
| 28
| 10
|
- add otg function and otg-vbus group. - add lcd-8bit, lcd-16bit, lcd-18bit, lcd-generic and lcd-special --- diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c +static int jz4760_lcd_8bit_pins[] = { + 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x4c, + 0x4d, 0x52, 0x53, +}; +static int jz4760_lcd_16bit_pins[] = { + 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59, +}; +static int jz4760_lcd_18bit_pins[] = { + 0x5a, 0x5b, +}; - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, - 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, - 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, - 0x58, 0x59, 0x5a, 0x5b, + 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55, +static int jz4760_lcd_special_pins[] = { 0x40, 0x41, 0x4a, 0x54 }; +static int jz4760_lcd_generic_pins[] = { 0x49, }; +static int jz4760_otg_pins[] = { 0x8a, }; + ingenic_pin_group("lcd-8bit", jz4760_lcd_8bit, 0), + ingenic_pin_group("lcd-16bit", jz4760_lcd_16bit, 0), + ingenic_pin_group("lcd-18bit", jz4760_lcd_18bit, 0), - { "lcd-no-pins", }, + ingenic_pin_group("lcd-generic", jz4760_lcd_generic, 0), + ingenic_pin_group("lcd-special", jz4760_lcd_special, 1), + ingenic_pin_group("otg-vbus", jz4760_otg, 0), -static const char *jz4760_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", }; +static const char *jz4760_lcd_groups[] = { + "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", + "lcd-special", "lcd-generic", +}; +static const char *jz4760_otg_groups[] = { "otg-vbus", }; + { "otg", jz4760_otg_groups, array_size(jz4760_otg_groups), }, -static int jz4770_otg_pins[] = { 0x8a, }; - ingenic_pin_group("otg-vbus", jz4770_otg, 0), + ingenic_pin_group("otg-vbus", jz4760_otg, 0), -static const char *jz4770_otg_groups[] = { "otg-vbus", }; - { "otg", jz4770_otg_groups, array_size(jz4770_otg_groups), }, + { "otg", jz4760_otg_groups, array_size(jz4760_otg_groups), },
|
Pin Controllers (pinctrl)
|
dd1ccfd6766911cade8cb50b41e192770d7ef91c
|
paul cercueil
|
drivers
|
pinctrl
| |
pinctrl: qcom: add sm8350 pinctrl driver
|
this adds pincontrol driver for tlmm block found in sm8350 soc
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add sm8350 pinctrl driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['qcom']
|
['kconfig', 'c', 'makefile']
| 3
| 1,659
| 0
|
--- diff --git a/drivers/pinctrl/qcom/kconfig b/drivers/pinctrl/qcom/kconfig --- a/drivers/pinctrl/qcom/kconfig +++ b/drivers/pinctrl/qcom/kconfig +config pinctrl_sm8350 + tristate "qualcomm technologies inc sm8350 pin controller driver" + depends on gpiolib && of + select pinctrl_msm + help + this is the pinctrl, pinmux, pinconf and gpiolib driver for the + qualcomm technologies inc tlmm block found on the qualcomm + technologies inc sm8350 platform. + diff --git a/drivers/pinctrl/qcom/makefile b/drivers/pinctrl/qcom/makefile --- a/drivers/pinctrl/qcom/makefile +++ b/drivers/pinctrl/qcom/makefile +obj-$(config_pinctrl_sm8350) += pinctrl-sm8350.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm8350.c b/drivers/pinctrl/qcom/pinctrl-sm8350.c --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8350.c +// spdx-license-identifier: gpl-2.0-only +/* + * copyright (c) 2019-2020, the linux foundation. all rights reserved. + * copyright (c) 2020-2021, linaro limited + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-msm.h" + +#define function(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = array_size(fname##_groups), \ + } + +#define reg_size 0x1000 + +#define pingroup(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned int)array_size(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = reg_size * id, \ + .io_reg = reg_size * id + 0x4, \ + .intr_cfg_reg = reg_size * id + 0x8, \ + .intr_status_reg = reg_size * id + 0xc, \ + .intr_target_reg = reg_size * id + 0x8, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define sdc_pingroup(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)array_size(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define ufs_reset(pg_name, offset) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)array_size(pg_name##_pins), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sm8350_pins[] = { + pinctrl_pin(0, "gpio_0"), + pinctrl_pin(1, "gpio_1"), + pinctrl_pin(2, "gpio_2"), + pinctrl_pin(3, "gpio_3"), + pinctrl_pin(4, "gpio_4"), + pinctrl_pin(5, "gpio_5"), + pinctrl_pin(6, "gpio_6"), + pinctrl_pin(7, "gpio_7"), + pinctrl_pin(8, "gpio_8"), + pinctrl_pin(9, "gpio_9"), + pinctrl_pin(10, "gpio_10"), + pinctrl_pin(11, "gpio_11"), + pinctrl_pin(12, "gpio_12"), + pinctrl_pin(13, "gpio_13"), + pinctrl_pin(14, "gpio_14"), + pinctrl_pin(15, "gpio_15"), + pinctrl_pin(16, "gpio_16"), + pinctrl_pin(17, "gpio_17"), + pinctrl_pin(18, "gpio_18"), + pinctrl_pin(19, "gpio_19"), + pinctrl_pin(20, "gpio_20"), + pinctrl_pin(21, "gpio_21"), + pinctrl_pin(22, "gpio_22"), + pinctrl_pin(23, "gpio_23"), + pinctrl_pin(24, "gpio_24"), + pinctrl_pin(25, "gpio_25"), + pinctrl_pin(26, "gpio_26"), + pinctrl_pin(27, "gpio_27"), + pinctrl_pin(28, "gpio_28"), + pinctrl_pin(29, "gpio_29"), + pinctrl_pin(30, "gpio_30"), + pinctrl_pin(31, "gpio_31"), + pinctrl_pin(32, "gpio_32"), + pinctrl_pin(33, "gpio_33"), + pinctrl_pin(34, "gpio_34"), + pinctrl_pin(35, "gpio_35"), + pinctrl_pin(36, "gpio_36"), + pinctrl_pin(37, "gpio_37"), + pinctrl_pin(38, "gpio_38"), + pinctrl_pin(39, "gpio_39"), + pinctrl_pin(40, "gpio_40"), + pinctrl_pin(41, "gpio_41"), + pinctrl_pin(42, "gpio_42"), + pinctrl_pin(43, "gpio_43"), + pinctrl_pin(44, "gpio_44"), + pinctrl_pin(45, "gpio_45"), + pinctrl_pin(46, "gpio_46"), + pinctrl_pin(47, "gpio_47"), + pinctrl_pin(48, "gpio_48"), + pinctrl_pin(49, "gpio_49"), + pinctrl_pin(50, "gpio_50"), + pinctrl_pin(51, "gpio_51"), + pinctrl_pin(52, "gpio_52"), + pinctrl_pin(53, "gpio_53"), + pinctrl_pin(54, "gpio_54"), + pinctrl_pin(55, "gpio_55"), + pinctrl_pin(56, "gpio_56"), + pinctrl_pin(57, "gpio_57"), + pinctrl_pin(58, "gpio_58"), + pinctrl_pin(59, "gpio_59"), + pinctrl_pin(60, "gpio_60"), + pinctrl_pin(61, "gpio_61"), + pinctrl_pin(62, "gpio_62"), + pinctrl_pin(63, "gpio_63"), + pinctrl_pin(64, "gpio_64"), + pinctrl_pin(65, "gpio_65"), + pinctrl_pin(66, "gpio_66"), + pinctrl_pin(67, "gpio_67"), + pinctrl_pin(68, "gpio_68"), + pinctrl_pin(69, "gpio_69"), + pinctrl_pin(70, "gpio_70"), + pinctrl_pin(71, "gpio_71"), + pinctrl_pin(72, "gpio_72"), + pinctrl_pin(73, "gpio_73"), + pinctrl_pin(74, "gpio_74"), + pinctrl_pin(75, "gpio_75"), + pinctrl_pin(76, "gpio_76"), + pinctrl_pin(77, "gpio_77"), + pinctrl_pin(78, "gpio_78"), + pinctrl_pin(79, "gpio_79"), + pinctrl_pin(80, "gpio_80"), + pinctrl_pin(81, "gpio_81"), + pinctrl_pin(82, "gpio_82"), + pinctrl_pin(83, "gpio_83"), + pinctrl_pin(84, "gpio_84"), + pinctrl_pin(85, "gpio_85"), + pinctrl_pin(86, "gpio_86"), + pinctrl_pin(87, "gpio_87"), + pinctrl_pin(88, "gpio_88"), + pinctrl_pin(89, "gpio_89"), + pinctrl_pin(90, "gpio_90"), + pinctrl_pin(91, "gpio_91"), + pinctrl_pin(92, "gpio_92"), + pinctrl_pin(93, "gpio_93"), + pinctrl_pin(94, "gpio_94"), + pinctrl_pin(95, "gpio_95"), + pinctrl_pin(96, "gpio_96"), + pinctrl_pin(97, "gpio_97"), + pinctrl_pin(98, "gpio_98"), + pinctrl_pin(99, "gpio_99"), + pinctrl_pin(100, "gpio_100"), + pinctrl_pin(101, "gpio_101"), + pinctrl_pin(102, "gpio_102"), + pinctrl_pin(103, "gpio_103"), + pinctrl_pin(104, "gpio_104"), + pinctrl_pin(105, "gpio_105"), + pinctrl_pin(106, "gpio_106"), + pinctrl_pin(107, "gpio_107"), + pinctrl_pin(108, "gpio_108"), + pinctrl_pin(109, "gpio_109"), + pinctrl_pin(110, "gpio_110"), + pinctrl_pin(111, "gpio_111"), + pinctrl_pin(112, "gpio_112"), + pinctrl_pin(113, "gpio_113"), + pinctrl_pin(114, "gpio_114"), + pinctrl_pin(115, "gpio_115"), + pinctrl_pin(116, "gpio_116"), + pinctrl_pin(117, "gpio_117"), + pinctrl_pin(118, "gpio_118"), + pinctrl_pin(119, "gpio_119"), + pinctrl_pin(120, "gpio_120"), + pinctrl_pin(121, "gpio_121"), + pinctrl_pin(122, "gpio_122"), + pinctrl_pin(123, "gpio_123"), + pinctrl_pin(124, "gpio_124"), + pinctrl_pin(125, "gpio_125"), + pinctrl_pin(126, "gpio_126"), + pinctrl_pin(127, "gpio_127"), + pinctrl_pin(128, "gpio_128"), + pinctrl_pin(129, "gpio_129"), + pinctrl_pin(130, "gpio_130"), + pinctrl_pin(131, "gpio_131"), + pinctrl_pin(132, "gpio_132"), + pinctrl_pin(133, "gpio_133"), + pinctrl_pin(134, "gpio_134"), + pinctrl_pin(135, "gpio_135"), + pinctrl_pin(136, "gpio_136"), + pinctrl_pin(137, "gpio_137"), + pinctrl_pin(138, "gpio_138"), + pinctrl_pin(139, "gpio_139"), + pinctrl_pin(140, "gpio_140"), + pinctrl_pin(141, "gpio_141"), + pinctrl_pin(142, "gpio_142"), + pinctrl_pin(143, "gpio_143"), + pinctrl_pin(144, "gpio_144"), + pinctrl_pin(145, "gpio_145"), + pinctrl_pin(146, "gpio_146"), + pinctrl_pin(147, "gpio_147"), + pinctrl_pin(148, "gpio_148"), + pinctrl_pin(149, "gpio_149"), + pinctrl_pin(150, "gpio_150"), + pinctrl_pin(151, "gpio_151"), + pinctrl_pin(152, "gpio_152"), + pinctrl_pin(153, "gpio_153"), + pinctrl_pin(154, "gpio_154"), + pinctrl_pin(155, "gpio_155"), + pinctrl_pin(156, "gpio_156"), + pinctrl_pin(157, "gpio_157"), + pinctrl_pin(158, "gpio_158"), + pinctrl_pin(159, "gpio_159"), + pinctrl_pin(160, "gpio_160"), + pinctrl_pin(161, "gpio_161"), + pinctrl_pin(162, "gpio_162"), + pinctrl_pin(163, "gpio_163"), + pinctrl_pin(164, "gpio_164"), + pinctrl_pin(165, "gpio_165"), + pinctrl_pin(166, "gpio_166"), + pinctrl_pin(167, "gpio_167"), + pinctrl_pin(168, "gpio_168"), + pinctrl_pin(169, "gpio_169"), + pinctrl_pin(170, "gpio_170"), + pinctrl_pin(171, "gpio_171"), + pinctrl_pin(172, "gpio_172"), + pinctrl_pin(173, "gpio_173"), + pinctrl_pin(174, "gpio_174"), + pinctrl_pin(175, "gpio_175"), + pinctrl_pin(176, "gpio_176"), + pinctrl_pin(177, "gpio_177"), + pinctrl_pin(178, "gpio_178"), + pinctrl_pin(179, "gpio_179"), + pinctrl_pin(180, "gpio_180"), + pinctrl_pin(181, "gpio_181"), + pinctrl_pin(182, "gpio_182"), + pinctrl_pin(183, "gpio_183"), + pinctrl_pin(184, "gpio_184"), + pinctrl_pin(185, "gpio_185"), + pinctrl_pin(186, "gpio_186"), + pinctrl_pin(187, "gpio_187"), + pinctrl_pin(188, "gpio_188"), + pinctrl_pin(189, "gpio_189"), + pinctrl_pin(190, "gpio_190"), + pinctrl_pin(191, "gpio_191"), + pinctrl_pin(192, "gpio_192"), + pinctrl_pin(193, "gpio_193"), + pinctrl_pin(194, "gpio_194"), + pinctrl_pin(195, "gpio_195"), + pinctrl_pin(196, "gpio_196"), + pinctrl_pin(197, "gpio_197"), + pinctrl_pin(198, "gpio_198"), + pinctrl_pin(199, "gpio_199"), + pinctrl_pin(200, "gpio_200"), + pinctrl_pin(201, "gpio_201"), + pinctrl_pin(202, "gpio_202"), + pinctrl_pin(203, "ufs_reset"), + pinctrl_pin(204, "sdc2_clk"), + pinctrl_pin(205, "sdc2_cmd"), + pinctrl_pin(206, "sdc2_data"), +}; + +#define declare_msm_gpio_pins(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +declare_msm_gpio_pins(0); +declare_msm_gpio_pins(1); +declare_msm_gpio_pins(2); +declare_msm_gpio_pins(3); +declare_msm_gpio_pins(4); +declare_msm_gpio_pins(5); +declare_msm_gpio_pins(6); +declare_msm_gpio_pins(7); +declare_msm_gpio_pins(8); +declare_msm_gpio_pins(9); +declare_msm_gpio_pins(10); +declare_msm_gpio_pins(11); +declare_msm_gpio_pins(12); +declare_msm_gpio_pins(13); +declare_msm_gpio_pins(14); +declare_msm_gpio_pins(15); +declare_msm_gpio_pins(16); +declare_msm_gpio_pins(17); +declare_msm_gpio_pins(18); +declare_msm_gpio_pins(19); +declare_msm_gpio_pins(20); +declare_msm_gpio_pins(21); +declare_msm_gpio_pins(22); +declare_msm_gpio_pins(23); +declare_msm_gpio_pins(24); +declare_msm_gpio_pins(25); +declare_msm_gpio_pins(26); +declare_msm_gpio_pins(27); +declare_msm_gpio_pins(28); +declare_msm_gpio_pins(29); +declare_msm_gpio_pins(30); +declare_msm_gpio_pins(31); +declare_msm_gpio_pins(32); +declare_msm_gpio_pins(33); +declare_msm_gpio_pins(34); +declare_msm_gpio_pins(35); +declare_msm_gpio_pins(36); +declare_msm_gpio_pins(37); +declare_msm_gpio_pins(38); +declare_msm_gpio_pins(39); +declare_msm_gpio_pins(40); +declare_msm_gpio_pins(41); +declare_msm_gpio_pins(42); +declare_msm_gpio_pins(43); +declare_msm_gpio_pins(44); +declare_msm_gpio_pins(45); +declare_msm_gpio_pins(46); +declare_msm_gpio_pins(47); +declare_msm_gpio_pins(48); +declare_msm_gpio_pins(49); +declare_msm_gpio_pins(50); +declare_msm_gpio_pins(51); +declare_msm_gpio_pins(52); +declare_msm_gpio_pins(53); +declare_msm_gpio_pins(54); +declare_msm_gpio_pins(55); +declare_msm_gpio_pins(56); +declare_msm_gpio_pins(57); +declare_msm_gpio_pins(58); +declare_msm_gpio_pins(59); +declare_msm_gpio_pins(60); +declare_msm_gpio_pins(61); +declare_msm_gpio_pins(62); +declare_msm_gpio_pins(63); +declare_msm_gpio_pins(64); +declare_msm_gpio_pins(65); +declare_msm_gpio_pins(66); +declare_msm_gpio_pins(67); +declare_msm_gpio_pins(68); +declare_msm_gpio_pins(69); +declare_msm_gpio_pins(70); +declare_msm_gpio_pins(71); +declare_msm_gpio_pins(72); +declare_msm_gpio_pins(73); +declare_msm_gpio_pins(74); +declare_msm_gpio_pins(75); +declare_msm_gpio_pins(76); +declare_msm_gpio_pins(77); +declare_msm_gpio_pins(78); +declare_msm_gpio_pins(79); +declare_msm_gpio_pins(80); +declare_msm_gpio_pins(81); +declare_msm_gpio_pins(82); +declare_msm_gpio_pins(83); +declare_msm_gpio_pins(84); +declare_msm_gpio_pins(85); +declare_msm_gpio_pins(86); +declare_msm_gpio_pins(87); +declare_msm_gpio_pins(88); +declare_msm_gpio_pins(89); +declare_msm_gpio_pins(90); +declare_msm_gpio_pins(91); +declare_msm_gpio_pins(92); +declare_msm_gpio_pins(93); +declare_msm_gpio_pins(94); +declare_msm_gpio_pins(95); +declare_msm_gpio_pins(96); +declare_msm_gpio_pins(97); +declare_msm_gpio_pins(98); +declare_msm_gpio_pins(99); +declare_msm_gpio_pins(100); +declare_msm_gpio_pins(101); +declare_msm_gpio_pins(102); +declare_msm_gpio_pins(103); +declare_msm_gpio_pins(104); +declare_msm_gpio_pins(105); +declare_msm_gpio_pins(106); +declare_msm_gpio_pins(107); +declare_msm_gpio_pins(108); +declare_msm_gpio_pins(109); +declare_msm_gpio_pins(110); +declare_msm_gpio_pins(111); +declare_msm_gpio_pins(112); +declare_msm_gpio_pins(113); +declare_msm_gpio_pins(114); +declare_msm_gpio_pins(115); +declare_msm_gpio_pins(116); +declare_msm_gpio_pins(117); +declare_msm_gpio_pins(118); +declare_msm_gpio_pins(119); +declare_msm_gpio_pins(120); +declare_msm_gpio_pins(121); +declare_msm_gpio_pins(122); +declare_msm_gpio_pins(123); +declare_msm_gpio_pins(124); +declare_msm_gpio_pins(125); +declare_msm_gpio_pins(126); +declare_msm_gpio_pins(127); +declare_msm_gpio_pins(128); +declare_msm_gpio_pins(129); +declare_msm_gpio_pins(130); +declare_msm_gpio_pins(131); +declare_msm_gpio_pins(132); +declare_msm_gpio_pins(133); +declare_msm_gpio_pins(134); +declare_msm_gpio_pins(135); +declare_msm_gpio_pins(136); +declare_msm_gpio_pins(137); +declare_msm_gpio_pins(138); +declare_msm_gpio_pins(139); +declare_msm_gpio_pins(140); +declare_msm_gpio_pins(141); +declare_msm_gpio_pins(142); +declare_msm_gpio_pins(143); +declare_msm_gpio_pins(144); +declare_msm_gpio_pins(145); +declare_msm_gpio_pins(146); +declare_msm_gpio_pins(147); +declare_msm_gpio_pins(148); +declare_msm_gpio_pins(149); +declare_msm_gpio_pins(150); +declare_msm_gpio_pins(151); +declare_msm_gpio_pins(152); +declare_msm_gpio_pins(153); +declare_msm_gpio_pins(154); +declare_msm_gpio_pins(155); +declare_msm_gpio_pins(156); +declare_msm_gpio_pins(157); +declare_msm_gpio_pins(158); +declare_msm_gpio_pins(159); +declare_msm_gpio_pins(160); +declare_msm_gpio_pins(161); +declare_msm_gpio_pins(162); +declare_msm_gpio_pins(163); +declare_msm_gpio_pins(164); +declare_msm_gpio_pins(165); +declare_msm_gpio_pins(166); +declare_msm_gpio_pins(167); +declare_msm_gpio_pins(168); +declare_msm_gpio_pins(169); +declare_msm_gpio_pins(170); +declare_msm_gpio_pins(171); +declare_msm_gpio_pins(172); +declare_msm_gpio_pins(173); +declare_msm_gpio_pins(174); +declare_msm_gpio_pins(175); +declare_msm_gpio_pins(176); +declare_msm_gpio_pins(177); +declare_msm_gpio_pins(178); +declare_msm_gpio_pins(179); +declare_msm_gpio_pins(180); +declare_msm_gpio_pins(181); +declare_msm_gpio_pins(182); +declare_msm_gpio_pins(183); +declare_msm_gpio_pins(184); +declare_msm_gpio_pins(185); +declare_msm_gpio_pins(186); +declare_msm_gpio_pins(187); +declare_msm_gpio_pins(188); +declare_msm_gpio_pins(189); +declare_msm_gpio_pins(190); +declare_msm_gpio_pins(191); +declare_msm_gpio_pins(192); +declare_msm_gpio_pins(193); +declare_msm_gpio_pins(194); +declare_msm_gpio_pins(195); +declare_msm_gpio_pins(196); +declare_msm_gpio_pins(197); +declare_msm_gpio_pins(198); +declare_msm_gpio_pins(199); +declare_msm_gpio_pins(200); +declare_msm_gpio_pins(201); +declare_msm_gpio_pins(202); + +static const unsigned int ufs_reset_pins[] = { 203 }; +static const unsigned int sdc2_clk_pins[] = { 204 }; +static const unsigned int sdc2_cmd_pins[] = { 205 }; +static const unsigned int sdc2_data_pins[] = { 206 }; + +enum sm8350_functions { + msm_mux_atest_char, + msm_mux_atest_usb, + msm_mux_audio_ref, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer, + msm_mux_cmu_rng, + msm_mux_coex_uart1, + msm_mux_coex_uart2, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_dp_hot, + msm_mux_dp_lcd, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gpio, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_lpass_slimbus, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mi2s0_data0, + msm_mux_mi2s0_data1, + msm_mux_mi2s0_sck, + msm_mux_mi2s0_ws, + msm_mux_mi2s1_data0, + msm_mux_mi2s1_data1, + msm_mux_mi2s1_sck, + msm_mux_mi2s1_ws, + msm_mux_mi2s2_data0, + msm_mux_mi2s2_data1, + msm_mux_mi2s2_sck, + msm_mux_mi2s2_ws, + msm_mux_mss_grfc0, + msm_mux_mss_grfc1, + msm_mux_mss_grfc10, + msm_mux_mss_grfc11, + msm_mux_mss_grfc12, + msm_mux_mss_grfc2, + msm_mux_mss_grfc3, + msm_mux_mss_grfc4, + msm_mux_mss_grfc5, + msm_mux_mss_grfc6, + msm_mux_mss_grfc7, + msm_mux_mss_grfc8, + msm_mux_mss_grfc9, + msm_mux_nav_gpio, + msm_mux_pa_indicator, + msm_mux_pcie0_clkreqn, + msm_mux_pcie1_clkreqn, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_clk, + msm_mux_pri_mi2s, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qlink0_enable, + msm_mux_qlink0_request, + msm_mux_qlink0_wmss, + msm_mux_qlink1_enable, + msm_mux_qlink1_request, + msm_mux_qlink1_wmss, + msm_mux_qlink2_enable, + msm_mux_qlink2_request, + msm_mux_qlink2_wmss, + msm_mux_qspi0, + msm_mux_qspi1, + msm_mux_qspi2, + msm_mux_qspi3, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup16, + msm_mux_qup17, + msm_mux_qup18, + msm_mux_qup19, + msm_mux_qup2, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_qup6, + msm_mux_qup7, + msm_mux_qup8, + msm_mux_qup9, + msm_mux_qup_l4, + msm_mux_qup_l5, + msm_mux_qup_l6, + msm_mux_sd_write, + msm_mux_sdc40, + msm_mux_sdc41, + msm_mux_sdc42, + msm_mux_sdc43, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sec_mi2s, + msm_mux_tb_trig, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_uim0_clk, + msm_mux_uim0_data, + msm_mux_uim0_present, + msm_mux_uim0_reset, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_usb2phy_ac, + msm_mux_usb_phy, + msm_mux_vfr_0, + msm_mux_vfr_1, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", + "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", + "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", + "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", + "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", + "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", + "gpio201", "gpio202", +}; + +static const char * const atest_char_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio115", "gpio117", +}; + +static const char * const atest_usb_groups[] = { + "gpio55", "gpio80", "gpio81", "gpio151", "gpio152", + "gpio153", "gpio154", "gpio158", "gpio159", "gpio161", +}; + +static const char * const audio_ref_groups[] = { + "gpio124", +}; + +static const char * const cam_mclk_groups[] = { + "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", +}; + +static const char * const cci_async_groups[] = { + "gpio106", "gpio118", "gpio119", +}; + +static const char * const cci_i2c_groups[] = { + "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", + "gpio113", "gpio114", +}; + +static const char * const cci_timer_groups[] = { + "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", +}; + +static const char * const cmu_rng_groups[] = { + "gpio174", "gpio175", "gpio176", "gpio177", +}; + +static const char * const coex_uart1_groups[] = { + "gpio151", "gpio152", +}; + +static const char * const coex_uart2_groups[] = { + "gpio153", "gpio154", +}; + +static const char * const cri_trng_groups[] = { + "gpio186", +}; + +static const char * const cri_trng0_groups[] = { + "gpio183", +}; + +static const char * const cri_trng1_groups[] = { + "gpio184", +}; + +static const char * const dbg_out_groups[] = { + "gpio14", +}; + +static const char * const ddr_bist_groups[] = { + "gpio36", "gpio37", "gpio40", "gpio41", +}; + +static const char * const ddr_pxi0_groups[] = { + "gpio51", "gpio52", +}; + +static const char * const ddr_pxi1_groups[] = { + "gpio48", "gpio49", +}; + +static const char * const ddr_pxi2_groups[] = { + "gpio45", "gpio47", +}; + +static const char * const ddr_pxi3_groups[] = { + "gpio43", "gpio44", +}; + +static const char * const dp_hot_groups[] = { + "gpio87", +}; + +static const char * const dp_lcd_groups[] = { + "gpio83", +}; + +static const char * const gcc_gp1_groups[] = { + "gpio115", "gpio129", +}; + +static const char * const gcc_gp2_groups[] = { + "gpio116", "gpio130", +}; + +static const char * const gcc_gp3_groups[] = { + "gpio117", "gpio131", +}; + +static const char * const ibi_i3c_groups[] = { + "gpio36", "gpio37", "gpio56", "gpio57", "gpio60", "gpio61", +}; + +static const char * const jitter_bist_groups[] = { + "gpio80", +}; + +static const char * const lpass_slimbus_groups[] = { + "gpio129", "gpio130", +}; + +static const char * const mdp_vsync_groups[] = { + "gpio15", "gpio26", "gpio82", "gpio83", "gpio84", +}; + +static const char * const mdp_vsync0_groups[] = { + "gpio86", +}; + +static const char * const mdp_vsync1_groups[] = { + "gpio86", +}; + +static const char * const mdp_vsync2_groups[] = { + "gpio87", +}; + +static const char * const mdp_vsync3_groups[] = { + "gpio87", +}; + +static const char * const mi2s0_data0_groups[] = { + "gpio126", +}; + +static const char * const mi2s0_data1_groups[] = { + "gpio127", +}; + +static const char * const mi2s0_sck_groups[] = { + "gpio125", +}; + +static const char * const mi2s0_ws_groups[] = { + "gpio128", +}; + +static const char * const mi2s1_data0_groups[] = { + "gpio130", +}; + +static const char * const mi2s1_data1_groups[] = { + "gpio131", +}; + +static const char * const mi2s1_sck_groups[] = { + "gpio129", +}; + +static const char * const mi2s1_ws_groups[] = { + "gpio132", +}; + +static const char * const mi2s2_data0_groups[] = { + "gpio121", +}; + +static const char * const mi2s2_data1_groups[] = { + "gpio124", +}; + +static const char * const mi2s2_sck_groups[] = { + "gpio120", +}; + +static const char * const mi2s2_ws_groups[] = { + "gpio122", +}; + +static const char * const mss_grfc0_groups[] = { + "gpio141", "gpio158", +}; + +static const char * const mss_grfc1_groups[] = { + "gpio142", +}; + +static const char * const mss_grfc10_groups[] = { + "gpio153", +}; + +static const char * const mss_grfc11_groups[] = { + "gpio154", +}; + +static const char * const mss_grfc12_groups[] = { + "gpio157", +}; + +static const char * const mss_grfc2_groups[] = { + "gpio143", +}; + +static const char * const mss_grfc3_groups[] = { + "gpio144", +}; + +static const char * const mss_grfc4_groups[] = { + "gpio145", +}; + +static const char * const mss_grfc5_groups[] = { + "gpio146", +}; + +static const char * const mss_grfc6_groups[] = { + "gpio147", +}; + +static const char * const mss_grfc7_groups[] = { + "gpio148", +}; + +static const char * const mss_grfc8_groups[] = { + "gpio149", +}; + +static const char * const mss_grfc9_groups[] = { + "gpio150", +}; + +static const char * const nav_gpio_groups[] = { + "gpio155", "gpio156", "gpio157", +}; + +static const char * const pa_indicator_groups[] = { + "gpio157", +}; + +static const char * const pcie0_clkreqn_groups[] = { + "gpio95", +}; + +static const char * const pcie1_clkreqn_groups[] = { + "gpio98", +}; + +static const char * const phase_flag_groups[] = { + "gpio12", "gpio13", "gpio16", "gpio17", "gpio28", "gpio29", "gpio30", + "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio72", "gpio73", + "gpio74", "gpio75", "gpio76", "gpio77", "gpio78", "gpio79", "gpio103", + "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", + "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", +}; + +static const char * const pll_bist_groups[] = { + "gpio81", +}; + +static const char * const pll_clk_groups[] = { + "gpio81", +}; + +static const char * const pri_mi2s_groups[] = { + "gpio123", +}; + +static const char * const prng_rosc_groups[] = { + "gpio185", +}; + +static const char * const qdss_cti_groups[] = { + "gpio14", "gpio27", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", "gpio92", +}; + +static const char * const qdss_gpio_groups[] = { + "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", + "gpio116", "gpio117", "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", "gpio195", "gpio196", + "gpio197", "gpio198", "gpio199", "gpio200", +}; + +static const char * const qlink0_enable_groups[] = { + "gpio160", +}; + +static const char * const qlink0_request_groups[] = { + "gpio159", +}; + +static const char * const qlink0_wmss_groups[] = { + "gpio161", +}; + +static const char * const qlink1_enable_groups[] = { + "gpio163", +}; + +static const char * const qlink1_request_groups[] = { + "gpio162", +}; + +static const char * const qlink1_wmss_groups[] = { + "gpio164", +}; + +static const char * const qlink2_enable_groups[] = { + "gpio166", +}; + +static const char * const qlink2_request_groups[] = { + "gpio165", +}; + +static const char * const qlink2_wmss_groups[] = { + "gpio167", +}; + +static const char * const qspi0_groups[] = { + "gpio44", +}; + +static const char * const qspi1_groups[] = { + "gpio45", +}; + +static const char * const qspi2_groups[] = { + "gpio48", +}; + +static const char * const qspi3_groups[] = { + "gpio49", +}; + +static const char * const qspi_clk_groups[] = { + "gpio50", +}; + +static const char * const qspi_cs_groups[] = { + "gpio47", "gpio51", +}; + +static const char * const qup0_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char * const qup1_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const qup10_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char * const qup11_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", +}; + +static const char * const qup12_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", +}; + +static const char * const qup13_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char * const qup14_groups[] = { + "gpio56", "gpio57", "gpio58", "gpio59", +}; + +static const char * const qup15_groups[] = { + "gpio60", "gpio61", "gpio62", "gpio63", +}; + +static const char * const qup16_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", +}; + +static const char * const qup17_groups[] = { + "gpio72", "gpio73", "gpio74", "gpio75", +}; + +static const char * const qup18_groups[] = { + "gpio68", "gpio69", "gpio70", "gpio71", +}; + +static const char * const qup19_groups[] = { + "gpio76", "gpio77", "gpio78", "gpio79", +}; + +static const char * const qup2_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; + +static const char * const qup3_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char * const qup4_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char * const qup5_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; + +static const char * const qup6_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; + +static const char * const qup7_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; + +static const char * const qup8_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char * const qup9_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", +}; + +static const char * const qup_l4_groups[] = { + "gpio2", "gpio6", "gpio58", "gpio63", +}; + +static const char * const qup_l5_groups[] = { + "gpio3", "gpio7", "gpio59", "gpio66", +}; + +static const char * const qup_l6_groups[] = { + "gpio10", "gpio42", "gpio62", "gpio67", +}; + +static const char * const sd_write_groups[] = { + "gpio93", +}; + +static const char * const sdc40_groups[] = { + "gpio44", +}; + +static const char * const sdc41_groups[] = { + "gpio45", +}; + +static const char * const sdc42_groups[] = { + "gpio48", +}; + +static const char * const sdc43_groups[] = { + "gpio49", +}; + +static const char * const sdc4_clk_groups[] = { + "gpio50", +}; + +static const char * const sdc4_cmd_groups[] = { + "gpio51", +}; + +static const char * const sec_mi2s_groups[] = { + "gpio124", +}; + +static const char * const tb_trig_groups[] = { + "gpio64", "gpio136", +}; + +static const char * const tgu_ch0_groups[] = { + "gpio99", +}; + +static const char * const tgu_ch1_groups[] = { + "gpio100", +}; + +static const char * const tgu_ch2_groups[] = { + "gpio101", +}; + +static const char * const tgu_ch3_groups[] = { + "gpio102", +}; + +static const char * const tsense_pwm1_groups[] = { + "gpio88", +}; + +static const char * const tsense_pwm2_groups[] = { + "gpio88", +}; + +static const char * const uim0_clk_groups[] = { + "gpio138", +}; + +static const char * const uim0_data_groups[] = { + "gpio137", +}; + +static const char * const uim0_present_groups[] = { + "gpio140", +}; + +static const char * const uim0_reset_groups[] = { + "gpio139", +}; + +static const char * const uim1_clk_groups[] = { + "gpio134", +}; + +static const char * const uim1_data_groups[] = { + "gpio133", +}; + +static const char * const uim1_present_groups[] = { + "gpio136", +}; + +static const char * const uim1_reset_groups[] = { + "gpio135", +}; + +static const char * const usb2phy_ac_groups[] = { + "gpio39", "gpio80", +}; + +static const char * const usb_phy_groups[] = { + "gpio81", +}; + +static const char * const vfr_0_groups[] = { + "gpio84", +}; + +static const char * const vfr_1_groups[] = { + "gpio90", +}; + +static const char * const vsense_trigger_groups[] = { + "gpio78", +}; + +static const struct msm_function sm8350_functions[] = { + function(atest_char), + function(atest_usb), + function(audio_ref), + function(cam_mclk), + function(cci_async), + function(cci_i2c), + function(cci_timer), + function(cmu_rng), + function(coex_uart1), + function(coex_uart2), + function(cri_trng), + function(cri_trng0), + function(cri_trng1), + function(dbg_out), + function(ddr_bist), + function(ddr_pxi0), + function(ddr_pxi1), + function(ddr_pxi2), + function(ddr_pxi3), + function(dp_hot), + function(dp_lcd), + function(gcc_gp1), + function(gcc_gp2), + function(gcc_gp3), + function(gpio), + function(ibi_i3c), + function(jitter_bist), + function(lpass_slimbus), + function(mdp_vsync), + function(mdp_vsync0), + function(mdp_vsync1), + function(mdp_vsync2), + function(mdp_vsync3), + function(mi2s0_data0), + function(mi2s0_data1), + function(mi2s0_sck), + function(mi2s0_ws), + function(mi2s1_data0), + function(mi2s1_data1), + function(mi2s1_sck), + function(mi2s1_ws), + function(mi2s2_data0), + function(mi2s2_data1), + function(mi2s2_sck), + function(mi2s2_ws), + function(mss_grfc0), + function(mss_grfc1), + function(mss_grfc10), + function(mss_grfc11), + function(mss_grfc12), + function(mss_grfc2), + function(mss_grfc3), + function(mss_grfc4), + function(mss_grfc5), + function(mss_grfc6), + function(mss_grfc7), + function(mss_grfc8), + function(mss_grfc9), + function(nav_gpio), + function(pa_indicator), + function(pcie0_clkreqn), + function(pcie1_clkreqn), + function(phase_flag), + function(pll_bist), + function(pll_clk), + function(pri_mi2s), + function(prng_rosc), + function(qdss_cti), + function(qdss_gpio), + function(qlink0_enable), + function(qlink0_request), + function(qlink0_wmss), + function(qlink1_enable), + function(qlink1_request), + function(qlink1_wmss), + function(qlink2_enable), + function(qlink2_request), + function(qlink2_wmss), + function(qspi0), + function(qspi1), + function(qspi2), + function(qspi3), + function(qspi_clk), + function(qspi_cs), + function(qup0), + function(qup1), + function(qup10), + function(qup11), + function(qup12), + function(qup13), + function(qup14), + function(qup15), + function(qup16), + function(qup17), + function(qup18), + function(qup19), + function(qup2), + function(qup3), + function(qup4), + function(qup5), + function(qup6), + function(qup7), + function(qup8), + function(qup9), + function(qup_l4), + function(qup_l5), + function(qup_l6), + function(sd_write), + function(sdc40), + function(sdc41), + function(sdc42), + function(sdc43), + function(sdc4_clk), + function(sdc4_cmd), + function(sec_mi2s), + function(tb_trig), + function(tgu_ch0), + function(tgu_ch1), + function(tgu_ch2), + function(tgu_ch3), + function(tsense_pwm1), + function(tsense_pwm2), + function(uim0_clk), + function(uim0_data), + function(uim0_present), + function(uim0_reset), + function(uim1_clk), + function(uim1_data), + function(uim1_present), + function(uim1_reset), + function(usb2phy_ac), + function(usb_phy), + function(vfr_0), + function(vfr_1), + function(vsense_trigger), +}; + +/* every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sm8350_groups[] = { + [0] = pingroup(0, qup13, _, _, _, _, _, _, _, _), + [1] = pingroup(1, qup13, _, _, _, _, _, _, _, _), + [2] = pingroup(2, qup13, qup_l4, _, _, _, _, _, _, _), + [3] = pingroup(3, qup13, qup_l5, _, _, _, _, _, _, _), + [4] = pingroup(4, qup0, _, _, _, _, _, _, _, _), + [5] = pingroup(5, qup0, _, _, _, _, _, _, _, _), + [6] = pingroup(6, qup0, qup_l4, _, _, _, _, _, _, _), + [7] = pingroup(7, qup0, qup_l5, _, _, _, _, _, _, _), + [8] = pingroup(8, qup1, _, _, _, _, _, _, _, _), + [9] = pingroup(9, qup1, _, _, _, _, _, _, _, _), + [10] = pingroup(10, qup1, qup_l6, _, _, _, _, _, _, _), + [11] = pingroup(11, qup1, _, _, _, _, _, _, _, _), + [12] = pingroup(12, qup2, phase_flag, _, _, _, _, _, _, _), + [13] = pingroup(13, qup2, phase_flag, _, _, _, _, _, _, _), + [14] = pingroup(14, qup2, qdss_cti, dbg_out, _, _, _, _, _, _), + [15] = pingroup(15, qup2, mdp_vsync, _, _, _, _, _, _, _), + [16] = pingroup(16, qup3, phase_flag, _, _, _, _, _, _, _), + [17] = pingroup(17, qup3, phase_flag, _, _, _, _, _, _, _), + [18] = pingroup(18, qup3, _, _, _, _, _, _, _, _), + [19] = pingroup(19, qup3, _, _, _, _, _, _, _, _), + [20] = pingroup(20, qup4, _, _, _, _, _, _, _, _), + [21] = pingroup(21, qup4, _, _, _, _, _, _, _, _), + [22] = pingroup(22, qup4, _, _, _, _, _, _, _, _), + [23] = pingroup(23, qup4, _, _, _, _, _, _, _, _), + [24] = pingroup(24, qup5, _, _, _, _, _, _, _, _), + [25] = pingroup(25, qup5, _, _, _, _, _, _, _, _), + [26] = pingroup(26, qup5, mdp_vsync, _, _, _, _, _, _, _), + [27] = pingroup(27, qup5, qdss_cti, _, _, _, _, _, _, _), + [28] = pingroup(28, qup6, phase_flag, _, _, _, _, _, _, _), + [29] = pingroup(29, qup6, phase_flag, _, _, _, _, _, _, _), + [30] = pingroup(30, qup6, phase_flag, _, _, _, _, _, _, _), + [31] = pingroup(31, qup6, phase_flag, _, _, _, _, _, _, _), + [32] = pingroup(32, qup7, phase_flag, _, _, _, _, _, _, _), + [33] = pingroup(33, qup7, phase_flag, _, _, _, _, _, _, _), + [34] = pingroup(34, qup7, phase_flag, _, _, _, _, _, _, _), + [35] = pingroup(35, qup7, phase_flag, _, _, _, _, _, _, _), + [36] = pingroup(36, qup8, ibi_i3c, ddr_bist, _, _, _, _, _, _), + [37] = pingroup(37, qup8, ibi_i3c, ddr_bist, _, _, _, _, _, _), + [38] = pingroup(38, qup8, _, _, _, _, _, _, _, _), + [39] = pingroup(39, qup8, usb2phy_ac, _, _, _, _, _, _, _), + [40] = pingroup(40, qup9, ddr_bist, _, _, _, _, _, _, _), + [41] = pingroup(41, qup9, ddr_bist, _, _, _, _, _, _, _), + [42] = pingroup(42, qup9, qup_l6, _, _, _, _, _, _, _), + [43] = pingroup(43, qup9, ddr_pxi3, _, _, _, _, _, _, _), + [44] = pingroup(44, qup10, qspi0, sdc40, ddr_pxi3, _, _, _, _, _), + [45] = pingroup(45, qup10, qspi1, sdc41, ddr_pxi2, _, _, _, _, _), + [46] = pingroup(46, qup10, _, _, _, _, _, _, _, _), + [47] = pingroup(47, qup10, qspi_cs, ddr_pxi2, _, _, _, _, _, _), + [48] = pingroup(48, qup11, qspi2, sdc42, ddr_pxi1, _, _, _, _, _), + [49] = pingroup(49, qup11, qspi3, sdc43, ddr_pxi1, _, _, _, _, _), + [50] = pingroup(50, qup11, qspi_clk, sdc4_clk, _, _, _, _, _, _), + [51] = pingroup(51, qup11, qspi_cs, sdc4_cmd, ddr_pxi0, _, _, _, _, _), + [52] = pingroup(52, qup12, ddr_pxi0, _, _, _, _, _, _, _), + [53] = pingroup(53, qup12, _, _, _, _, _, _, _, _), + [54] = pingroup(54, qup12, _, _, _, _, _, _, _, _), + [55] = pingroup(55, qup12, atest_usb, _, _, _, _, _, _, _), + [56] = pingroup(56, qup14, ibi_i3c, _, _, _, _, _, _, _), + [57] = pingroup(57, qup14, ibi_i3c, _, _, _, _, _, _, _), + [58] = pingroup(58, qup14, qup_l4, _, _, _, _, _, _, _), + [59] = pingroup(59, qup14, qup_l5, _, _, _, _, _, _, _), + [60] = pingroup(60, qup15, ibi_i3c, _, _, _, _, _, _, _), + [61] = pingroup(61, qup15, ibi_i3c, _, _, _, _, _, _, _), + [62] = pingroup(62, qup15, qup_l6, _, _, _, _, _, _, _), + [63] = pingroup(63, qup15, qup_l4, _, _, _, _, _, _, _), + [64] = pingroup(64, qup16, tb_trig, _, _, _, _, _, _, _), + [65] = pingroup(65, qup16, _, _, _, _, _, _, _, _), + [66] = pingroup(66, qup16, qup_l5, _, _, _, _, _, _, _), + [67] = pingroup(67, qup16, qup_l6, _, _, _, _, _, _, _), + [68] = pingroup(68, qup18, _, _, _, _, _, _, _, _), + [69] = pingroup(69, qup18, _, _, _, _, _, _, _, _), + [70] = pingroup(70, qup18, _, _, _, _, _, _, _, _), + [71] = pingroup(71, qup18, _, _, _, _, _, _, _, _), + [72] = pingroup(72, qup17, phase_flag, _, _, _, _, _, _, _), + [73] = pingroup(73, qup17, phase_flag, _, _, _, _, _, _, _), + [74] = pingroup(74, qup17, phase_flag, _, _, _, _, _, _, _), + [75] = pingroup(75, qup17, phase_flag, _, _, _, _, _, _, _), + [76] = pingroup(76, qup19, phase_flag, _, _, _, _, _, _, _), + [77] = pingroup(77, qup19, phase_flag, _, _, _, _, _, _, _), + [78] = pingroup(78, qup19, phase_flag, _, vsense_trigger, _, _, _, _, _), + [79] = pingroup(79, qup19, phase_flag, _, _, _, _, _, _, _), + [80] = pingroup(80, usb2phy_ac, jitter_bist, atest_usb, _, _, _, _, _, _), + [81] = pingroup(81, usb_phy, pll_bist, pll_clk, atest_usb, _, _, _, _, _), + [82] = pingroup(82, mdp_vsync, _, _, _, _, _, _, _, _), + [83] = pingroup(83, mdp_vsync, dp_lcd, _, _, _, _, _, _, _), + [84] = pingroup(84, mdp_vsync, vfr_0, _, _, _, _, _, _, _), + [85] = pingroup(85, atest_char, _, _, _, _, _, _, _, _), + [86] = pingroup(86, mdp_vsync0, mdp_vsync1, atest_char, _, _, _, _, _, _), + [87] = pingroup(87, dp_hot, mdp_vsync2, mdp_vsync3, qdss_cti, atest_char, _, _, _, _), + [88] = pingroup(88, qdss_cti, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _), + [89] = pingroup(89, qdss_cti, _, _, _, _, _, _, _, _), + [90] = pingroup(90, vfr_1, qdss_cti, _, _, _, _, _, _, _), + [91] = pingroup(91, qdss_cti, _, _, _, _, _, _, _, _), + [92] = pingroup(92, qdss_cti, _, _, _, _, _, _, _, _), + [93] = pingroup(93, sd_write, _, _, _, _, _, _, _, _), + [94] = pingroup(94, _, _, _, _, _, _, _, _, _), + [95] = pingroup(95, pcie0_clkreqn, _, _, _, _, _, _, _, _), + [96] = pingroup(96, _, _, _, _, _, _, _, _, _), + [97] = pingroup(97, _, _, _, _, _, _, _, _, _), + [98] = pingroup(98, pcie1_clkreqn, _, _, _, _, _, _, _, _), + [99] = pingroup(99, tgu_ch0, _, _, _, _, _, _, _, _), + [100] = pingroup(100, cam_mclk, tgu_ch1, qdss_gpio, _, _, _, _, _, _), + [101] = pingroup(101, cam_mclk, tgu_ch2, qdss_gpio, _, _, _, _, _, _), + [102] = pingroup(102, cam_mclk, tgu_ch3, qdss_gpio, _, _, _, _, _, _), + [103] = pingroup(103, cam_mclk, phase_flag, _, qdss_gpio, _, _, _, _, _), + [104] = pingroup(104, cam_mclk, phase_flag, _, qdss_gpio, _, _, _, _, _), + [105] = pingroup(105, cam_mclk, phase_flag, _, qdss_gpio, _, _, _, _, _), + [106] = pingroup(106, cci_async, phase_flag, _, qdss_gpio, _, _, _, _, _), + [107] = pingroup(107, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [108] = pingroup(108, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [109] = pingroup(109, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [110] = pingroup(110, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [111] = pingroup(111, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [112] = pingroup(112, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [113] = pingroup(113, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [114] = pingroup(114, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [115] = pingroup(115, cci_timer, gcc_gp1, qdss_gpio, atest_char, _, _, _, _, _), + [116] = pingroup(116, cci_timer, gcc_gp2, qdss_gpio, _, _, _, _, _, _), + [117] = pingroup(117, cci_timer, gcc_gp3, qdss_gpio, atest_char, _, _, _, _, _), + [118] = pingroup(118, cci_timer, cci_async, _, _, _, _, _, _, _), + [119] = pingroup(119, cci_timer, cci_async, _, _, _, _, _, _, _), + [120] = pingroup(120, mi2s2_sck, _, _, _, _, _, _, _, _), + [121] = pingroup(121, mi2s2_data0, _, _, _, _, _, _, _, _), + [122] = pingroup(122, mi2s2_ws, _, _, _, _, _, _, _, _), + [123] = pingroup(123, pri_mi2s, _, _, _, _, _, _, _, _), + [124] = pingroup(124, sec_mi2s, audio_ref, mi2s2_data1, _, _, _, _, _, _), + [125] = pingroup(125, mi2s0_sck, _, _, _, _, _, _, _, _), + [126] = pingroup(126, mi2s0_data0, _, _, _, _, _, _, _, _), + [127] = pingroup(127, mi2s0_data1, _, _, _, _, _, _, _, _), + [128] = pingroup(128, mi2s0_ws, _, _, _, _, _, _, _, _), + [129] = pingroup(129, lpass_slimbus, mi2s1_sck, gcc_gp1, _, _, _, _, _, _), + [130] = pingroup(130, lpass_slimbus, mi2s1_data0, gcc_gp2, _, _, _, _, _, _), + [131] = pingroup(131, mi2s1_data1, gcc_gp3, _, _, _, _, _, _, _), + [132] = pingroup(132, mi2s1_ws, _, _, _, _, _, _, _, _), + [133] = pingroup(133, uim1_data, _, _, _, _, _, _, _, _), + [134] = pingroup(134, uim1_clk, _, _, _, _, _, _, _, _), + [135] = pingroup(135, uim1_reset, _, _, _, _, _, _, _, _), + [136] = pingroup(136, uim1_present, tb_trig, _, _, _, _, _, _, _), + [137] = pingroup(137, uim0_data, _, _, _, _, _, _, _, _), + [138] = pingroup(138, uim0_clk, _, _, _, _, _, _, _, _), + [139] = pingroup(139, uim0_reset, _, _, _, _, _, _, _, _), + [140] = pingroup(140, uim0_present, _, _, _, _, _, _, _, _), + [141] = pingroup(141, _, mss_grfc0, _, _, _, _, _, _, _), + [142] = pingroup(142, _, mss_grfc1, _, _, _, _, _, _, _), + [143] = pingroup(143, _, mss_grfc2, _, _, _, _, _, _, _), + [144] = pingroup(144, _, mss_grfc3, _, _, _, _, _, _, _), + [145] = pingroup(145, _, mss_grfc4, _, _, _, _, _, _, _), + [146] = pingroup(146, _, mss_grfc5, _, _, _, _, _, _, _), + [147] = pingroup(147, _, mss_grfc6, _, _, _, _, _, _, _), + [148] = pingroup(148, _, mss_grfc7, _, _, _, _, _, _, _), + [149] = pingroup(149, _, mss_grfc8, _, _, _, _, _, _, _), + [150] = pingroup(150, _, mss_grfc9, _, _, _, _, _, _, _), + [151] = pingroup(151, coex_uart1, atest_usb, _, _, _, _, _, _, _), + [152] = pingroup(152, coex_uart1, atest_usb, _, _, _, _, _, _, _), + [153] = pingroup(153, coex_uart2, mss_grfc10, atest_usb, _, _, _, _, _, _), + [154] = pingroup(154, coex_uart2, mss_grfc11, atest_usb, _, _, _, _, _, _), + [155] = pingroup(155, nav_gpio, _, _, _, _, _, _, _, _), + [156] = pingroup(156, nav_gpio, _, _, _, _, _, _, _, _), + [157] = pingroup(157, mss_grfc12, pa_indicator, nav_gpio, _, _, _, _, _, _), + [158] = pingroup(158, mss_grfc0, atest_usb, _, _, _, _, _, _, _), + [159] = pingroup(159, qlink0_request, atest_usb, _, _, _, _, _, _, _), + [160] = pingroup(160, qlink0_enable, _, _, _, _, _, _, _, _), + [161] = pingroup(161, qlink0_wmss, atest_usb, _, _, _, _, _, _, _), + [162] = pingroup(162, qlink1_request, _, _, _, _, _, _, _, _), + [163] = pingroup(163, qlink1_enable, _, _, _, _, _, _, _, _), + [164] = pingroup(164, qlink1_wmss, _, _, _, _, _, _, _, _), + [165] = pingroup(165, qlink2_request, _, _, _, _, _, _, _, _), + [166] = pingroup(166, qlink2_enable, _, _, _, _, _, _, _, _), + [167] = pingroup(167, qlink2_wmss, _, _, _, _, _, _, _, _), + [168] = pingroup(168, _, _, _, _, _, _, _, _, _), + [169] = pingroup(169, _, _, _, _, _, _, _, _, _), + [170] = pingroup(170, _, _, _, _, _, _, _, _, _), + [171] = pingroup(171, _, _, _, _, _, _, _, _, _), + [172] = pingroup(172, _, _, _, _, _, _, _, _, _), + [173] = pingroup(173, _, _, _, _, _, _, _, _, _), + [174] = pingroup(174, cmu_rng, _, _, _, _, _, _, _, _), + [175] = pingroup(175, cmu_rng, _, _, _, _, _, _, _, _), + [176] = pingroup(176, cmu_rng, _, _, _, _, _, _, _, _), + [177] = pingroup(177, cmu_rng, _, _, _, _, _, _, _, _), + [178] = pingroup(178, _, _, _, _, _, _, _, _, _), + [179] = pingroup(179, _, _, _, _, _, _, _, _, _), + [180] = pingroup(180, _, _, _, _, _, _, _, _, _), + [181] = pingroup(181, _, _, _, _, _, _, _, _, _), + [182] = pingroup(182, _, _, _, _, _, _, _, _, _), + [183] = pingroup(183, cri_trng0, qdss_gpio, _, _, _, _, _, _, _), + [184] = pingroup(184, cri_trng1, qdss_gpio, _, _, _, _, _, _, _), + [185] = pingroup(185, prng_rosc, qdss_gpio, _, _, _, _, _, _, _), + [186] = pingroup(186, cri_trng, qdss_gpio, _, _, _, _, _, _, _), + [187] = pingroup(187, qdss_gpio, _, _, _, _, _, _, _, _), + [188] = pingroup(188, qdss_gpio, _, _, _, _, _, _, _, _), + [189] = pingroup(189, qdss_gpio, _, _, _, _, _, _, _, _), + [190] = pingroup(190, qdss_gpio, _, _, _, _, _, _, _, _), + [191] = pingroup(191, qdss_gpio, _, _, _, _, _, _, _, _), + [192] = pingroup(192, qdss_gpio, _, _, _, _, _, _, _, _), + [193] = pingroup(193, qdss_gpio, _, _, _, _, _, _, _, _), + [194] = pingroup(194, qdss_gpio, _, _, _, _, _, _, _, _), + [195] = pingroup(195, qdss_gpio, _, _, _, _, _, _, _, _), + [196] = pingroup(196, qdss_gpio, _, _, _, _, _, _, _, _), + [197] = pingroup(197, qdss_gpio, _, _, _, _, _, _, _, _), + [198] = pingroup(198, qdss_gpio, _, _, _, _, _, _, _, _), + [199] = pingroup(199, qdss_gpio, _, _, _, _, _, _, _, _), + [200] = pingroup(200, qdss_gpio, _, _, _, _, _, _, _, _), + [201] = pingroup(201, _, _, _, _, _, _, _, _, _), + [202] = pingroup(202, _, _, _, _, _, _, _, _, _), + [203] = ufs_reset(ufs_reset, 0x1d8000), + [204] = sdc_pingroup(sdc2_clk, 0x1cf000, 14, 6), + [205] = sdc_pingroup(sdc2_cmd, 0x1cf000, 11, 3), + [206] = sdc_pingroup(sdc2_data, 0x1cf000, 9, 0), +}; + +static const struct msm_pinctrl_soc_data sm8350_tlmm = { + .pins = sm8350_pins, + .npins = array_size(sm8350_pins), + .functions = sm8350_functions, + .nfunctions = array_size(sm8350_functions), + .groups = sm8350_groups, + .ngroups = array_size(sm8350_groups), + .ngpios = 204, +}; + +static int sm8350_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sm8350_tlmm); +} + +static const struct of_device_id sm8350_tlmm_of_match[] = { + { .compatible = "qcom,sm8350-tlmm", }, + { }, +}; + +static struct platform_driver sm8350_tlmm_driver = { + .driver = { + .name = "sm8350-tlmm", + .of_match_table = sm8350_tlmm_of_match, + }, + .probe = sm8350_tlmm_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sm8350_tlmm_init(void) +{ + return platform_driver_register(&sm8350_tlmm_driver); +} +arch_initcall(sm8350_tlmm_init); + +static void __exit sm8350_tlmm_exit(void) +{ + platform_driver_unregister(&sm8350_tlmm_driver); +} +module_exit(sm8350_tlmm_exit); + +module_description("qti sm8350 tlmm driver"); +module_license("gpl v2"); +module_device_table(of, sm8350_tlmm_of_match);
|
Pin Controllers (pinctrl)
|
d5d348a3271f4b4d877ed246d0566ad1b9ec7f5b
|
vinod koul
|
drivers
|
pinctrl
|
qcom
|
pinctrl: qcom: add sc8180x tlmm driver
|
add pinctrl driver for the sc8180x tlmm block.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add sc8180x tlmm driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['qcom']
|
['kconfig', 'c', 'makefile']
| 3
| 1,634
| 0
|
--- diff --git a/drivers/pinctrl/qcom/kconfig b/drivers/pinctrl/qcom/kconfig --- a/drivers/pinctrl/qcom/kconfig +++ b/drivers/pinctrl/qcom/kconfig +config pinctrl_sc8180x + tristate "qualcomm technologies inc sc8180x pin controller driver" + depends on gpiolib && of + select pinctrl_msm + help + this is the pinctrl, pinmux, pinconf and gpiolib driver for the + qualcomm technologies inc tlmm block found on the qualcomm + technologies inc sc8180x platform. + diff --git a/drivers/pinctrl/qcom/makefile b/drivers/pinctrl/qcom/makefile --- a/drivers/pinctrl/qcom/makefile +++ b/drivers/pinctrl/qcom/makefile +obj-$(config_pinctrl_sc8180x) += pinctrl-sc8180x.o diff --git a/drivers/pinctrl/qcom/pinctrl-sc8180x.c b/drivers/pinctrl/qcom/pinctrl-sc8180x.c --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sc8180x.c +// spdx-license-identifier: gpl-2.0 +/* + * copyright (c) 2018-2019, the linux foundation. all rights reserved. + * copyright (c) 2020-2021, linaro ltd. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-msm.h" + +static const char * const sc8180x_tiles[] = { + "south", + "east", + "west" +}; + +enum { + south, + east, + west +}; + +#define function(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = array_size(fname##_groups), \ + } + +#define reg_size 0x1000 +#define pingroup_offset(id, _tile, offset, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned int)array_size(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = reg_size * id + offset, \ + .io_reg = reg_size * id + 0x4 + offset, \ + .intr_cfg_reg = reg_size * id + 0x8 + offset, \ + .intr_status_reg = reg_size * id + 0xc + offset,\ + .intr_target_reg = reg_size * id + 0x8 + offset,\ + .tile = _tile, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define pingroup(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + pingroup_offset(id, _tile, 0x0, f1, f2, f3, f4, f5, f6, f7, f8, f9) + +#define sdc_qdsd_pingroup(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)array_size(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = east, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define ufs_reset(pg_name) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)array_size(pg_name##_pins), \ + .ctl_reg = 0xb6000, \ + .io_reg = 0xb6004, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = south, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc sc8180x_pins[] = { + pinctrl_pin(0, "gpio_0"), + pinctrl_pin(1, "gpio_1"), + pinctrl_pin(2, "gpio_2"), + pinctrl_pin(3, "gpio_3"), + pinctrl_pin(4, "gpio_4"), + pinctrl_pin(5, "gpio_5"), + pinctrl_pin(6, "gpio_6"), + pinctrl_pin(7, "gpio_7"), + pinctrl_pin(8, "gpio_8"), + pinctrl_pin(9, "gpio_9"), + pinctrl_pin(10, "gpio_10"), + pinctrl_pin(11, "gpio_11"), + pinctrl_pin(12, "gpio_12"), + pinctrl_pin(13, "gpio_13"), + pinctrl_pin(14, "gpio_14"), + pinctrl_pin(15, "gpio_15"), + pinctrl_pin(16, "gpio_16"), + pinctrl_pin(17, "gpio_17"), + pinctrl_pin(18, "gpio_18"), + pinctrl_pin(19, "gpio_19"), + pinctrl_pin(20, "gpio_20"), + pinctrl_pin(21, "gpio_21"), + pinctrl_pin(22, "gpio_22"), + pinctrl_pin(23, "gpio_23"), + pinctrl_pin(24, "gpio_24"), + pinctrl_pin(25, "gpio_25"), + pinctrl_pin(26, "gpio_26"), + pinctrl_pin(27, "gpio_27"), + pinctrl_pin(28, "gpio_28"), + pinctrl_pin(29, "gpio_29"), + pinctrl_pin(30, "gpio_30"), + pinctrl_pin(31, "gpio_31"), + pinctrl_pin(32, "gpio_32"), + pinctrl_pin(33, "gpio_33"), + pinctrl_pin(34, "gpio_34"), + pinctrl_pin(35, "gpio_35"), + pinctrl_pin(36, "gpio_36"), + pinctrl_pin(37, "gpio_37"), + pinctrl_pin(38, "gpio_38"), + pinctrl_pin(39, "gpio_39"), + pinctrl_pin(40, "gpio_40"), + pinctrl_pin(41, "gpio_41"), + pinctrl_pin(42, "gpio_42"), + pinctrl_pin(43, "gpio_43"), + pinctrl_pin(44, "gpio_44"), + pinctrl_pin(45, "gpio_45"), + pinctrl_pin(46, "gpio_46"), + pinctrl_pin(47, "gpio_47"), + pinctrl_pin(48, "gpio_48"), + pinctrl_pin(49, "gpio_49"), + pinctrl_pin(50, "gpio_50"), + pinctrl_pin(51, "gpio_51"), + pinctrl_pin(52, "gpio_52"), + pinctrl_pin(53, "gpio_53"), + pinctrl_pin(54, "gpio_54"), + pinctrl_pin(55, "gpio_55"), + pinctrl_pin(56, "gpio_56"), + pinctrl_pin(57, "gpio_57"), + pinctrl_pin(58, "gpio_58"), + pinctrl_pin(59, "gpio_59"), + pinctrl_pin(60, "gpio_60"), + pinctrl_pin(61, "gpio_61"), + pinctrl_pin(62, "gpio_62"), + pinctrl_pin(63, "gpio_63"), + pinctrl_pin(64, "gpio_64"), + pinctrl_pin(65, "gpio_65"), + pinctrl_pin(66, "gpio_66"), + pinctrl_pin(67, "gpio_67"), + pinctrl_pin(68, "gpio_68"), + pinctrl_pin(69, "gpio_69"), + pinctrl_pin(70, "gpio_70"), + pinctrl_pin(71, "gpio_71"), + pinctrl_pin(72, "gpio_72"), + pinctrl_pin(73, "gpio_73"), + pinctrl_pin(74, "gpio_74"), + pinctrl_pin(75, "gpio_75"), + pinctrl_pin(76, "gpio_76"), + pinctrl_pin(77, "gpio_77"), + pinctrl_pin(78, "gpio_78"), + pinctrl_pin(79, "gpio_79"), + pinctrl_pin(80, "gpio_80"), + pinctrl_pin(81, "gpio_81"), + pinctrl_pin(82, "gpio_82"), + pinctrl_pin(83, "gpio_83"), + pinctrl_pin(84, "gpio_84"), + pinctrl_pin(85, "gpio_85"), + pinctrl_pin(86, "gpio_86"), + pinctrl_pin(87, "gpio_87"), + pinctrl_pin(88, "gpio_88"), + pinctrl_pin(89, "gpio_89"), + pinctrl_pin(90, "gpio_90"), + pinctrl_pin(91, "gpio_91"), + pinctrl_pin(92, "gpio_92"), + pinctrl_pin(93, "gpio_93"), + pinctrl_pin(94, "gpio_94"), + pinctrl_pin(95, "gpio_95"), + pinctrl_pin(96, "gpio_96"), + pinctrl_pin(97, "gpio_97"), + pinctrl_pin(98, "gpio_98"), + pinctrl_pin(99, "gpio_99"), + pinctrl_pin(100, "gpio_100"), + pinctrl_pin(101, "gpio_101"), + pinctrl_pin(102, "gpio_102"), + pinctrl_pin(103, "gpio_103"), + pinctrl_pin(104, "gpio_104"), + pinctrl_pin(105, "gpio_105"), + pinctrl_pin(106, "gpio_106"), + pinctrl_pin(107, "gpio_107"), + pinctrl_pin(108, "gpio_108"), + pinctrl_pin(109, "gpio_109"), + pinctrl_pin(110, "gpio_110"), + pinctrl_pin(111, "gpio_111"), + pinctrl_pin(112, "gpio_112"), + pinctrl_pin(113, "gpio_113"), + pinctrl_pin(114, "gpio_114"), + pinctrl_pin(115, "gpio_115"), + pinctrl_pin(116, "gpio_116"), + pinctrl_pin(117, "gpio_117"), + pinctrl_pin(118, "gpio_118"), + pinctrl_pin(119, "gpio_119"), + pinctrl_pin(120, "gpio_120"), + pinctrl_pin(121, "gpio_121"), + pinctrl_pin(122, "gpio_122"), + pinctrl_pin(123, "gpio_123"), + pinctrl_pin(124, "gpio_124"), + pinctrl_pin(125, "gpio_125"), + pinctrl_pin(126, "gpio_126"), + pinctrl_pin(127, "gpio_127"), + pinctrl_pin(128, "gpio_128"), + pinctrl_pin(129, "gpio_129"), + pinctrl_pin(130, "gpio_130"), + pinctrl_pin(131, "gpio_131"), + pinctrl_pin(132, "gpio_132"), + pinctrl_pin(133, "gpio_133"), + pinctrl_pin(134, "gpio_134"), + pinctrl_pin(135, "gpio_135"), + pinctrl_pin(136, "gpio_136"), + pinctrl_pin(137, "gpio_137"), + pinctrl_pin(138, "gpio_138"), + pinctrl_pin(139, "gpio_139"), + pinctrl_pin(140, "gpio_140"), + pinctrl_pin(141, "gpio_141"), + pinctrl_pin(142, "gpio_142"), + pinctrl_pin(143, "gpio_143"), + pinctrl_pin(144, "gpio_144"), + pinctrl_pin(145, "gpio_145"), + pinctrl_pin(146, "gpio_146"), + pinctrl_pin(147, "gpio_147"), + pinctrl_pin(148, "gpio_148"), + pinctrl_pin(149, "gpio_149"), + pinctrl_pin(150, "gpio_150"), + pinctrl_pin(151, "gpio_151"), + pinctrl_pin(152, "gpio_152"), + pinctrl_pin(153, "gpio_153"), + pinctrl_pin(154, "gpio_154"), + pinctrl_pin(155, "gpio_155"), + pinctrl_pin(156, "gpio_156"), + pinctrl_pin(157, "gpio_157"), + pinctrl_pin(158, "gpio_158"), + pinctrl_pin(159, "gpio_159"), + pinctrl_pin(160, "gpio_160"), + pinctrl_pin(161, "gpio_161"), + pinctrl_pin(162, "gpio_162"), + pinctrl_pin(163, "gpio_163"), + pinctrl_pin(164, "gpio_164"), + pinctrl_pin(165, "gpio_165"), + pinctrl_pin(166, "gpio_166"), + pinctrl_pin(167, "gpio_167"), + pinctrl_pin(168, "gpio_168"), + pinctrl_pin(169, "gpio_169"), + pinctrl_pin(170, "gpio_170"), + pinctrl_pin(171, "gpio_171"), + pinctrl_pin(172, "gpio_172"), + pinctrl_pin(173, "gpio_173"), + pinctrl_pin(174, "gpio_174"), + pinctrl_pin(175, "gpio_175"), + pinctrl_pin(176, "gpio_176"), + pinctrl_pin(177, "gpio_177"), + pinctrl_pin(178, "gpio_178"), + pinctrl_pin(179, "gpio_179"), + pinctrl_pin(180, "gpio_180"), + pinctrl_pin(181, "gpio_181"), + pinctrl_pin(182, "gpio_182"), + pinctrl_pin(183, "gpio_183"), + pinctrl_pin(184, "gpio_184"), + pinctrl_pin(185, "gpio_185"), + pinctrl_pin(186, "gpio_186"), + pinctrl_pin(187, "gpio_187"), + pinctrl_pin(188, "gpio_188"), + pinctrl_pin(189, "gpio_189"), + pinctrl_pin(190, "ufs_reset"), + pinctrl_pin(191, "sdc2_clk"), + pinctrl_pin(192, "sdc2_cmd"), + pinctrl_pin(193, "sdc2_data"), +}; + +#define declare_msm_gpio_pins(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +declare_msm_gpio_pins(0); +declare_msm_gpio_pins(1); +declare_msm_gpio_pins(2); +declare_msm_gpio_pins(3); +declare_msm_gpio_pins(4); +declare_msm_gpio_pins(5); +declare_msm_gpio_pins(6); +declare_msm_gpio_pins(7); +declare_msm_gpio_pins(8); +declare_msm_gpio_pins(9); +declare_msm_gpio_pins(10); +declare_msm_gpio_pins(11); +declare_msm_gpio_pins(12); +declare_msm_gpio_pins(13); +declare_msm_gpio_pins(14); +declare_msm_gpio_pins(15); +declare_msm_gpio_pins(16); +declare_msm_gpio_pins(17); +declare_msm_gpio_pins(18); +declare_msm_gpio_pins(19); +declare_msm_gpio_pins(20); +declare_msm_gpio_pins(21); +declare_msm_gpio_pins(22); +declare_msm_gpio_pins(23); +declare_msm_gpio_pins(24); +declare_msm_gpio_pins(25); +declare_msm_gpio_pins(26); +declare_msm_gpio_pins(27); +declare_msm_gpio_pins(28); +declare_msm_gpio_pins(29); +declare_msm_gpio_pins(30); +declare_msm_gpio_pins(31); +declare_msm_gpio_pins(32); +declare_msm_gpio_pins(33); +declare_msm_gpio_pins(34); +declare_msm_gpio_pins(35); +declare_msm_gpio_pins(36); +declare_msm_gpio_pins(37); +declare_msm_gpio_pins(38); +declare_msm_gpio_pins(39); +declare_msm_gpio_pins(40); +declare_msm_gpio_pins(41); +declare_msm_gpio_pins(42); +declare_msm_gpio_pins(43); +declare_msm_gpio_pins(44); +declare_msm_gpio_pins(45); +declare_msm_gpio_pins(46); +declare_msm_gpio_pins(47); +declare_msm_gpio_pins(48); +declare_msm_gpio_pins(49); +declare_msm_gpio_pins(50); +declare_msm_gpio_pins(51); +declare_msm_gpio_pins(52); +declare_msm_gpio_pins(53); +declare_msm_gpio_pins(54); +declare_msm_gpio_pins(55); +declare_msm_gpio_pins(56); +declare_msm_gpio_pins(57); +declare_msm_gpio_pins(58); +declare_msm_gpio_pins(59); +declare_msm_gpio_pins(60); +declare_msm_gpio_pins(61); +declare_msm_gpio_pins(62); +declare_msm_gpio_pins(63); +declare_msm_gpio_pins(64); +declare_msm_gpio_pins(65); +declare_msm_gpio_pins(66); +declare_msm_gpio_pins(67); +declare_msm_gpio_pins(68); +declare_msm_gpio_pins(69); +declare_msm_gpio_pins(70); +declare_msm_gpio_pins(71); +declare_msm_gpio_pins(72); +declare_msm_gpio_pins(73); +declare_msm_gpio_pins(74); +declare_msm_gpio_pins(75); +declare_msm_gpio_pins(76); +declare_msm_gpio_pins(77); +declare_msm_gpio_pins(78); +declare_msm_gpio_pins(79); +declare_msm_gpio_pins(80); +declare_msm_gpio_pins(81); +declare_msm_gpio_pins(82); +declare_msm_gpio_pins(83); +declare_msm_gpio_pins(84); +declare_msm_gpio_pins(85); +declare_msm_gpio_pins(86); +declare_msm_gpio_pins(87); +declare_msm_gpio_pins(88); +declare_msm_gpio_pins(89); +declare_msm_gpio_pins(90); +declare_msm_gpio_pins(91); +declare_msm_gpio_pins(92); +declare_msm_gpio_pins(93); +declare_msm_gpio_pins(94); +declare_msm_gpio_pins(95); +declare_msm_gpio_pins(96); +declare_msm_gpio_pins(97); +declare_msm_gpio_pins(98); +declare_msm_gpio_pins(99); +declare_msm_gpio_pins(100); +declare_msm_gpio_pins(101); +declare_msm_gpio_pins(102); +declare_msm_gpio_pins(103); +declare_msm_gpio_pins(104); +declare_msm_gpio_pins(105); +declare_msm_gpio_pins(106); +declare_msm_gpio_pins(107); +declare_msm_gpio_pins(108); +declare_msm_gpio_pins(109); +declare_msm_gpio_pins(110); +declare_msm_gpio_pins(111); +declare_msm_gpio_pins(112); +declare_msm_gpio_pins(113); +declare_msm_gpio_pins(114); +declare_msm_gpio_pins(115); +declare_msm_gpio_pins(116); +declare_msm_gpio_pins(117); +declare_msm_gpio_pins(118); +declare_msm_gpio_pins(119); +declare_msm_gpio_pins(120); +declare_msm_gpio_pins(121); +declare_msm_gpio_pins(122); +declare_msm_gpio_pins(123); +declare_msm_gpio_pins(124); +declare_msm_gpio_pins(125); +declare_msm_gpio_pins(126); +declare_msm_gpio_pins(127); +declare_msm_gpio_pins(128); +declare_msm_gpio_pins(129); +declare_msm_gpio_pins(130); +declare_msm_gpio_pins(131); +declare_msm_gpio_pins(132); +declare_msm_gpio_pins(133); +declare_msm_gpio_pins(134); +declare_msm_gpio_pins(135); +declare_msm_gpio_pins(136); +declare_msm_gpio_pins(137); +declare_msm_gpio_pins(138); +declare_msm_gpio_pins(139); +declare_msm_gpio_pins(140); +declare_msm_gpio_pins(141); +declare_msm_gpio_pins(142); +declare_msm_gpio_pins(143); +declare_msm_gpio_pins(144); +declare_msm_gpio_pins(145); +declare_msm_gpio_pins(146); +declare_msm_gpio_pins(147); +declare_msm_gpio_pins(148); +declare_msm_gpio_pins(149); +declare_msm_gpio_pins(150); +declare_msm_gpio_pins(151); +declare_msm_gpio_pins(152); +declare_msm_gpio_pins(153); +declare_msm_gpio_pins(154); +declare_msm_gpio_pins(155); +declare_msm_gpio_pins(156); +declare_msm_gpio_pins(157); +declare_msm_gpio_pins(158); +declare_msm_gpio_pins(159); +declare_msm_gpio_pins(160); +declare_msm_gpio_pins(161); +declare_msm_gpio_pins(162); +declare_msm_gpio_pins(163); +declare_msm_gpio_pins(164); +declare_msm_gpio_pins(165); +declare_msm_gpio_pins(166); +declare_msm_gpio_pins(167); +declare_msm_gpio_pins(168); +declare_msm_gpio_pins(169); +declare_msm_gpio_pins(170); +declare_msm_gpio_pins(171); +declare_msm_gpio_pins(172); +declare_msm_gpio_pins(173); +declare_msm_gpio_pins(174); +declare_msm_gpio_pins(175); +declare_msm_gpio_pins(176); +declare_msm_gpio_pins(177); +declare_msm_gpio_pins(178); +declare_msm_gpio_pins(179); +declare_msm_gpio_pins(180); +declare_msm_gpio_pins(181); +declare_msm_gpio_pins(182); +declare_msm_gpio_pins(183); +declare_msm_gpio_pins(184); +declare_msm_gpio_pins(185); +declare_msm_gpio_pins(186); +declare_msm_gpio_pins(187); +declare_msm_gpio_pins(188); +declare_msm_gpio_pins(189); + +static const unsigned int sdc2_clk_pins[] = { 190 }; +static const unsigned int sdc2_cmd_pins[] = { 191 }; +static const unsigned int sdc2_data_pins[] = { 192 }; +static const unsigned int ufs_reset_pins[] = { 193 }; + +enum sc8180x_functions { + msm_mux_adsp_ext, + msm_mux_agera_pll, + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_tsens, + msm_mux_atest_tsens2, + msm_mux_atest_usb0, + msm_mux_atest_usb1, + msm_mux_atest_usb2, + msm_mux_atest_usb3, + msm_mux_atest_usb4, + msm_mux_audio_ref, + msm_mux_btfm_slimbus, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cci_timer5, + msm_mux_cci_timer6, + msm_mux_cci_timer7, + msm_mux_cci_timer8, + msm_mux_cci_timer9, + msm_mux_cri_trng, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi, + msm_mux_debug_hot, + msm_mux_dp_hot, + msm_mux_edp_hot, + msm_mux_edp_lcd, + msm_mux_emac_phy, + msm_mux_emac_pps, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gcc_gp4, + msm_mux_gcc_gp5, + msm_mux_gpio, + msm_mux_gps, + msm_mux_grfc, + msm_mux_hs1_mi2s, + msm_mux_hs2_mi2s, + msm_mux_hs3_mi2s, + msm_mux_jitter_bist, + msm_mux_lpass_slimbus, + msm_mux_m_voc, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mdp_vsync4, + msm_mux_mdp_vsync5, + msm_mux_mss_lte, + msm_mux_nav_pps, + msm_mux_pa_indicator, + msm_mux_pci_e0, + msm_mux_pci_e1, + msm_mux_pci_e2, + msm_mux_pci_e3, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_bypassnl, + msm_mux_pll_reset, + msm_mux_pri_mi2s, + msm_mux_pri_mi2s_ws, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qlink, + msm_mux_qspi0, + msm_mux_qspi0_clk, + msm_mux_qspi0_cs, + msm_mux_qspi1, + msm_mux_qspi1_clk, + msm_mux_qspi1_cs, + msm_mux_qua_mi2s, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup2, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_qup6, + msm_mux_qup7, + msm_mux_qup8, + msm_mux_qup9, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup16, + msm_mux_qup17, + msm_mux_qup18, + msm_mux_qup19, + msm_mux_qup_l4, + msm_mux_qup_l5, + msm_mux_qup_l6, + msm_mux_rgmii, + msm_mux_sd_write, + msm_mux_sdc4, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sec_mi2s, + msm_mux_sp_cmu, + msm_mux_spkr_i2s, + msm_mux_ter_mi2s, + msm_mux_tgu, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsif1, + msm_mux_tsif2, + msm_mux_uim1, + msm_mux_uim2, + msm_mux_uim_batt, + msm_mux_usb0_phy, + msm_mux_usb1_phy, + msm_mux_usb2phy_ac, + msm_mux_vfr_1, + msm_mux_vsense_trigger, + msm_mux_wlan1_adc, + msm_mux_wlan2_adc, + msm_mux_wmss_reset, + msm_mux__, +}; + +static const char * const adsp_ext_groups[] = { + "gpio115", +}; + +static const char * const agera_pll_groups[] = { + "gpio37", +}; + +static const char * const aoss_cti_groups[] = { + "gpio113", +}; + +static const char * const atest_char_groups[] = { + "gpio133", "gpio134", "gpio135", "gpio140", "gpio142", +}; + +static const char * const atest_tsens2_groups[] = { + "gpio62", +}; + +static const char * const atest_tsens_groups[] = { + "gpio93", +}; + +static const char * const atest_usb0_groups[] = { + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", +}; + +static const char * const atest_usb1_groups[] = { + "gpio60", "gpio62", "gpio63", "gpio64", "gpio65", +}; + +static const char * const atest_usb2_groups[] = { + "gpio34", "gpio95", "gpio102", "gpio121", "gpio122", +}; + +static const char * const atest_usb3_groups[] = { + "gpio68", "gpio71", "gpio72", "gpio73", "gpio74", +}; + +static const char * const atest_usb4_groups[] = { + "gpio75", "gpio76", "gpio77", "gpio78", "gpio88", +}; + +static const char * const audio_ref_groups[] = { + "gpio148", +}; + +static const char * const btfm_slimbus_groups[] = { + "gpio153", "gpio154", +}; + +static const char * const cam_mclk_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", "gpio25", "gpio179", "gpio180", + "gpio181", +}; + +static const char * const cci_async_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio176", "gpio185", "gpio186", +}; + +static const char * const cci_i2c_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio17", "gpio18", "gpio19", + "gpio20", "gpio31", "gpio32", "gpio33", "gpio34", "gpio39", "gpio40", + "gpio41", "gpio42", +}; + +static const char * const cci_timer0_groups[] = { + "gpio21", +}; + +static const char * const cci_timer1_groups[] = { + "gpio22", +}; + +static const char * const cci_timer2_groups[] = { + "gpio23", +}; + +static const char * const cci_timer3_groups[] = { + "gpio24", +}; + +static const char * const cci_timer4_groups[] = { + "gpio178", +}; + +static const char * const cci_timer5_groups[] = { + "gpio182", +}; + +static const char * const cci_timer6_groups[] = { + "gpio183", +}; + +static const char * const cci_timer7_groups[] = { + "gpio184", +}; + +static const char * const cci_timer8_groups[] = { + "gpio185", +}; + +static const char * const cci_timer9_groups[] = { + "gpio186", +}; + +static const char * const cri_trng_groups[] = { + "gpio159", + "gpio160", + "gpio161", +}; + +static const char * const dbg_out_groups[] = { + "gpio34", +}; + +static const char * const ddr_bist_groups[] = { + "gpio98", "gpio99", "gpio145", "gpio146", +}; + +static const char * const ddr_pxi_groups[] = { + "gpio60", "gpio62", "gpio63", "gpio64", "gpio65", "gpio68", "gpio71", + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", "gpio78", + "gpio88", "gpio90", +}; + +static const char * const debug_hot_groups[] = { + "gpio7", +}; + +static const char * const dp_hot_groups[] = { + "gpio189", +}; + +static const char * const edp_hot_groups[] = { + "gpio10", +}; + +static const char * const edp_lcd_groups[] = { + "gpio11", +}; + +static const char * const emac_phy_groups[] = { + "gpio124", +}; + +static const char * const emac_pps_groups[] = { + "gpio81", +}; + +static const char * const gcc_gp1_groups[] = { + "gpio131", "gpio136", +}; + +static const char * const gcc_gp2_groups[] = { + "gpio21", "gpio137", +}; + +static const char * const gcc_gp3_groups[] = { + "gpio22", "gpio138", +}; + +static const char * const gcc_gp4_groups[] = { + "gpio139", "gpio182", +}; + +static const char * const gcc_gp5_groups[] = { + "gpio140", "gpio183", +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", + "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", + "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", + "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", + "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", + "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", + "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", + "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", + "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", + "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", + "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", + "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", + "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", + "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", + "gpio128", "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", + "gpio134", "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", + "gpio140", "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", + "gpio146", "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", + "gpio152", "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", + "gpio158", "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", + "gpio164", "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", + "gpio170", "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", + "gpio176", "gpio177", "gpio177", "gpio178", "gpio179", "gpio180", + "gpio181", "gpio182", "gpio183", "gpio184", "gpio185", "gpio186", + "gpio186", "gpio187", "gpio187", "gpio188", "gpio188", "gpio189", +}; + +static const char * const gps_groups[] = { + "gpio60", "gpio76", "gpio77", "gpio81", "gpio82", +}; + +static const char * const grfc_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio71", "gpio72", + "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", "gpio78", "gpio79", + "gpio80", "gpio81", "gpio82", +}; + +static const char * const hs1_mi2s_groups[] = { + "gpio155", "gpio156", "gpio157", "gpio158", "gpio159", +}; + +static const char * const hs2_mi2s_groups[] = { + "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", +}; + +static const char * const hs3_mi2s_groups[] = { + "gpio125", "gpio165", "gpio166", "gpio167", "gpio168", +}; + +static const char * const jitter_bist_groups[] = { + "gpio129", +}; + +static const char * const lpass_slimbus_groups[] = { + "gpio149", "gpio150", "gpio151", "gpio152", +}; + +static const char * const m_voc_groups[] = { + "gpio10", +}; + +static const char * const mdp_vsync0_groups[] = { + "gpio89", +}; + +static const char * const mdp_vsync1_groups[] = { + "gpio89", +}; + +static const char * const mdp_vsync2_groups[] = { + "gpio89", +}; + +static const char * const mdp_vsync3_groups[] = { + "gpio89", +}; + +static const char * const mdp_vsync4_groups[] = { + "gpio89", +}; + +static const char * const mdp_vsync5_groups[] = { + "gpio89", +}; + +static const char * const mdp_vsync_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio60", "gpio82", +}; + +static const char * const mss_lte_groups[] = { + "gpio69", "gpio70", +}; + +static const char * const nav_pps_groups[] = { + "gpio60", "gpio60", "gpio76", "gpio76", "gpio77", "gpio77", "gpio81", + "gpio81", "gpio82", "gpio82", +}; + +static const char * const pa_indicator_groups[] = { + "gpio68", +}; + +static const char * const pci_e0_groups[] = { + "gpio35", "gpio36", +}; + +static const char * const pci_e1_groups[] = { + "gpio102", "gpio103", +}; + +static const char * const pci_e2_groups[] = { + "gpio175", "gpio176", +}; + +static const char * const pci_e3_groups[] = { + "gpio178", "gpio179", +}; + +static const char * const phase_flag_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio33", "gpio53", "gpio54", + "gpio102", "gpio120", "gpio121", "gpio122", "gpio123", "gpio125", + "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", "gpio155", + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", + "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167", + "gpio168", +}; + +static const char * const pll_bist_groups[] = { + "gpio130", +}; + +static const char * const pll_bypassnl_groups[] = { + "gpio100", +}; + +static const char * const pll_reset_groups[] = { + "gpio101", +}; + +static const char * const pri_mi2s_groups[] = { + "gpio143", "gpio144", "gpio146", "gpio147", +}; + +static const char * const pri_mi2s_ws_groups[] = { + "gpio145", +}; + +static const char * const prng_rosc_groups[] = { + "gpio163", +}; + +static const char * const qdss_cti_groups[] = { + "gpio49", "gpio50", "gpio81", "gpio82", "gpio89", "gpio90", "gpio141", + "gpio142", +}; + +static const char * const qdss_gpio_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", + "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", + "gpio27", "gpio28", "gpio29", "gpio30", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio92", "gpio114", "gpio115", "gpio116", "gpio117", + "gpio118", "gpio119", "gpio120", "gpio121", "gpio130", "gpio132", + "gpio133", "gpio134", "gpio135", +}; + +static const char * const qlink_groups[] = { + "gpio61", "gpio62", +}; + +static const char * const qspi0_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio93", +}; + +static const char * const qspi0_clk_groups[] = { + "gpio92", +}; + +static const char * const qspi0_cs_groups[] = { + "gpio88", "gpio94", +}; + +static const char * const qspi1_groups[] = { + "gpio56", "gpio57", "gpio161", "gpio162", +}; + +static const char * const qspi1_clk_groups[] = { + "gpio163", +}; + +static const char * const qspi1_cs_groups[] = { + "gpio55", "gpio164", +}; + +static const char * const qua_mi2s_groups[] = { + "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", "gpio141", + "gpio142", +}; + +static const char * const qup0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char * const qup10_groups[] = { + "gpio9", "gpio10", "gpio11", "gpio12", +}; + +static const char * const qup11_groups[] = { + "gpio92", "gpio93", "gpio94", "gpio95", +}; + +static const char * const qup12_groups[] = { + "gpio83", "gpio84", "gpio85", "gpio86", +}; + +static const char * const qup13_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46", +}; + +static const char * const qup14_groups[] = { + "gpio47", "gpio48", "gpio49", "gpio50", +}; + +static const char * const qup15_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", +}; + +static const char * const qup16_groups[] = { + "gpio83", "gpio84", "gpio85", "gpio86", +}; + +static const char * const qup17_groups[] = { + "gpio55", "gpio56", "gpio57", "gpio58", +}; + +static const char * const qup18_groups[] = { + "gpio23", "gpio24", "gpio25", "gpio26", +}; + +static const char * const qup19_groups[] = { + "gpio181", "gpio182", "gpio183", "gpio184", +}; + +static const char * const qup1_groups[] = { + "gpio114", "gpio115", "gpio116", "gpio117", +}; + +static const char * const qup2_groups[] = { + "gpio126", "gpio127", "gpio128", "gpio129", +}; + +static const char * const qup3_groups[] = { + "gpio144", "gpio145", "gpio146", "gpio147", +}; + +static const char * const qup4_groups[] = { + "gpio51", "gpio52", "gpio53", "gpio54", +}; + +static const char * const qup5_groups[] = { + "gpio119", "gpio120", "gpio121", "gpio122", +}; + +static const char * const qup6_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char * const qup7_groups[] = { + "gpio98", "gpio99", "gpio100", "gpio101", +}; + +static const char * const qup8_groups[] = { + "gpio88", "gpio89", "gpio90", "gpio91", +}; + +static const char * const qup9_groups[] = { + "gpio39", "gpio40", "gpio41", "gpio42", +}; + +static const char * const qup_l4_groups[] = { + "gpio35", "gpio59", "gpio60", "gpio95", +}; + +static const char * const qup_l5_groups[] = { + "gpio7", "gpio33", "gpio36", "gpio96", +}; + +static const char * const qup_l6_groups[] = { + "gpio6", "gpio34", "gpio37", "gpio97", +}; + +static const char * const rgmii_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio59", "gpio114", "gpio115", + "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", + "gpio122", +}; + +static const char * const sd_write_groups[] = { + "gpio97", +}; + +static const char * const sdc4_groups[] = { + "gpio91", "gpio93", "gpio94", "gpio95", +}; + +static const char * const sdc4_clk_groups[] = { + "gpio92", +}; + +static const char * const sdc4_cmd_groups[] = { + "gpio90", +}; + +static const char * const sec_mi2s_groups[] = { + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", +}; + +static const char * const sp_cmu_groups[] = { + "gpio162", +}; + +static const char * const spkr_i2s_groups[] = { + "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", +}; + +static const char * const ter_mi2s_groups[] = { + "gpio131", "gpio132", "gpio133", "gpio134", "gpio135", +}; + +static const char * const tgu_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio88", "gpio74", "gpio77", "gpio76", + "gpio75", +}; + +static const char * const tsense_pwm1_groups[] = { + "gpio150", +}; + +static const char * const tsense_pwm2_groups[] = { + "gpio150", +}; + +static const char * const tsif1_groups[] = { + "gpio88", "gpio89", "gpio90", "gpio91", "gpio97", +}; + +static const char * const tsif2_groups[] = { + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", +}; + +static const char * const uim1_groups[] = { + "gpio109", "gpio110", "gpio111", "gpio112", +}; + +static const char * const uim2_groups[] = { + "gpio105", "gpio106", "gpio107", "gpio108", +}; + +static const char * const uim_batt_groups[] = { + "gpio113", +}; + +static const char * const usb0_phy_groups[] = { + "gpio38", +}; + +static const char * const usb1_phy_groups[] = { + "gpio58", +}; + +static const char * const usb2phy_ac_groups[] = { + "gpio47", "gpio48", "gpio113", "gpio123", +}; + +static const char * const vfr_1_groups[] = { + "gpio91", +}; + +static const char * const vsense_trigger_groups[] = { + "gpio62", +}; + +static const char * const wlan1_adc_groups[] = { + "gpio64", "gpio63", +}; + +static const char * const wlan2_adc_groups[] = { + "gpio68", "gpio65", +}; + +static const char * const wmss_reset_groups[] = { + "gpio63", +}; + +static const struct msm_function sc8180x_functions[] = { + function(adsp_ext), + function(agera_pll), + function(aoss_cti), + function(atest_char), + function(atest_tsens), + function(atest_tsens2), + function(atest_usb0), + function(atest_usb1), + function(atest_usb2), + function(atest_usb3), + function(atest_usb4), + function(audio_ref), + function(btfm_slimbus), + function(cam_mclk), + function(cci_async), + function(cci_i2c), + function(cci_timer0), + function(cci_timer1), + function(cci_timer2), + function(cci_timer3), + function(cci_timer4), + function(cci_timer5), + function(cci_timer6), + function(cci_timer7), + function(cci_timer8), + function(cci_timer9), + function(cri_trng), + function(dbg_out), + function(ddr_bist), + function(ddr_pxi), + function(debug_hot), + function(dp_hot), + function(edp_hot), + function(edp_lcd), + function(emac_phy), + function(emac_pps), + function(gcc_gp1), + function(gcc_gp2), + function(gcc_gp3), + function(gcc_gp4), + function(gcc_gp5), + function(gpio), + function(gps), + function(grfc), + function(hs1_mi2s), + function(hs2_mi2s), + function(hs3_mi2s), + function(jitter_bist), + function(lpass_slimbus), + function(m_voc), + function(mdp_vsync), + function(mdp_vsync0), + function(mdp_vsync1), + function(mdp_vsync2), + function(mdp_vsync3), + function(mdp_vsync4), + function(mdp_vsync5), + function(mss_lte), + function(nav_pps), + function(pa_indicator), + function(pci_e0), + function(pci_e1), + function(pci_e2), + function(pci_e3), + function(phase_flag), + function(pll_bist), + function(pll_bypassnl), + function(pll_reset), + function(pri_mi2s), + function(pri_mi2s_ws), + function(prng_rosc), + function(qdss_cti), + function(qdss_gpio), + function(qlink), + function(qspi0), + function(qspi0_clk), + function(qspi0_cs), + function(qspi1), + function(qspi1_clk), + function(qspi1_cs), + function(qua_mi2s), + function(qup0), + function(qup1), + function(qup2), + function(qup3), + function(qup4), + function(qup5), + function(qup6), + function(qup7), + function(qup8), + function(qup9), + function(qup10), + function(qup11), + function(qup12), + function(qup13), + function(qup14), + function(qup15), + function(qup16), + function(qup17), + function(qup18), + function(qup19), + function(qup_l4), + function(qup_l5), + function(qup_l6), + function(rgmii), + function(sd_write), + function(sdc4), + function(sdc4_clk), + function(sdc4_cmd), + function(sec_mi2s), + function(sp_cmu), + function(spkr_i2s), + function(ter_mi2s), + function(tgu), + function(tsense_pwm1), + function(tsense_pwm2), + function(tsif1), + function(tsif2), + function(uim1), + function(uim2), + function(uim_batt), + function(usb0_phy), + function(usb1_phy), + function(usb2phy_ac), + function(vfr_1), + function(vsense_trigger), + function(wlan1_adc), + function(wlan2_adc), + function(wmss_reset), +}; + +/* every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sc8180x_groups[] = { + [0] = pingroup(0, west, qup0, cci_i2c, _, _, _, _, _, _, _), + [1] = pingroup(1, west, qup0, cci_i2c, _, _, _, _, _, _, _), + [2] = pingroup(2, west, qup0, cci_i2c, _, _, _, _, _, _, _), + [3] = pingroup(3, west, qup0, cci_i2c, _, _, _, _, _, _, _), + [4] = pingroup(4, west, qup6, rgmii, _, phase_flag, _, _, _, _, _), + [5] = pingroup(5, west, qup6, rgmii, _, phase_flag, _, _, _, _, _), + [6] = pingroup(6, west, qup6, rgmii, qup_l6, _, phase_flag, _, _, _, _), + [7] = pingroup(7, west, qup6, debug_hot, rgmii, qup_l5, _, phase_flag, _, _, _), + [8] = pingroup(8, east, mdp_vsync, _, _, _, _, _, _, _, _), + [9] = pingroup(9, east, mdp_vsync, qup10, _, _, _, _, _, _, _), + [10] = pingroup(10, east, edp_hot, m_voc, mdp_vsync, qup10, _, _, _, _, _), + [11] = pingroup(11, east, edp_lcd, qup10, _, _, _, _, _, _, _), + [12] = pingroup(12, east, qup10, _, _, _, _, _, _, _, _), + [13] = pingroup(13, east, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [14] = pingroup(14, east, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [15] = pingroup(15, east, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [16] = pingroup(16, east, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [17] = pingroup(17, east, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [18] = pingroup(18, east, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [19] = pingroup(19, east, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [20] = pingroup(20, east, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [21] = pingroup(21, east, cci_timer0, gcc_gp2, qdss_gpio, _, _, _, _, _, _), + [22] = pingroup(22, east, cci_timer1, gcc_gp3, qdss_gpio, _, _, _, _, _, _), + [23] = pingroup(23, east, cci_timer2, qup18, qdss_gpio, _, _, _, _, _, _), + [24] = pingroup(24, east, cci_timer3, cci_async, qup18, qdss_gpio, _, _, _, _, _), + [25] = pingroup(25, east, cam_mclk, cci_async, qup18, qdss_gpio, _, _, _, _, _), + [26] = pingroup(26, east, cci_async, qup18, qdss_gpio, _, _, _, _, _, _), + [27] = pingroup(27, east, qup15, _, qdss_gpio, _, _, _, _, _, _), + [28] = pingroup(28, east, qup15, qdss_gpio, _, _, _, _, _, _, _), + [29] = pingroup(29, east, qup15, qdss_gpio, _, _, _, _, _, _, _), + [30] = pingroup(30, east, qup15, qdss_gpio, _, _, _, _, _, _, _), + [31] = pingroup(31, east, cci_i2c, _, _, _, _, _, _, _, _), + [32] = pingroup(32, east, cci_i2c, _, _, _, _, _, _, _, _), + [33] = pingroup(33, east, cci_i2c, qup_l5, _, phase_flag, _, _, _, _, _), + [34] = pingroup(34, east, cci_i2c, qup_l6, dbg_out, atest_usb2, _, _, _, _, _), + [35] = pingroup(35, south, pci_e0, qup_l4, _, _, _, _, _, _, _), + [36] = pingroup(36, south, pci_e0, qup_l5, _, _, _, _, _, _, _), + [37] = pingroup(37, south, qup_l6, agera_pll, _, _, _, _, _, _, _), + [38] = pingroup(38, south, usb0_phy, _, _, _, _, _, _, _, _), + [39] = pingroup(39, east, qup9, cci_i2c, qdss_gpio, _, _, _, _, _, _), + [40] = pingroup(40, east, qup9, cci_i2c, qdss_gpio, _, _, _, _, _, _), + [41] = pingroup(41, east, qup9, cci_i2c, qdss_gpio, _, _, _, _, _, _), + [42] = pingroup(42, east, qup9, cci_i2c, qdss_gpio, _, _, _, _, _, _), + [43] = pingroup(43, east, qup13, _, _, _, _, _, _, _, _), + [44] = pingroup(44, east, qup13, _, _, _, _, _, _, _, _), + [45] = pingroup(45, east, qup13, _, _, _, _, _, _, _, _), + [46] = pingroup(46, east, qup13, _, _, _, _, _, _, _, _), + [47] = pingroup(47, east, qup14, usb2phy_ac, _, _, _, _, _, _, _), + [48] = pingroup(48, east, qup14, usb2phy_ac, _, _, _, _, _, _, _), + [49] = pingroup(49, east, qup14, qdss_cti, _, _, _, _, _, _, _), + [50] = pingroup(50, east, qup14, qdss_cti, _, _, _, _, _, _, _), + [51] = pingroup(51, west, qup4, _, _, _, _, _, _, _, _), + [52] = pingroup(52, west, qup4, _, _, _, _, _, _, _, _), + [53] = pingroup(53, west, qup4, _, phase_flag, _, _, _, _, _, _), + [54] = pingroup(54, west, qup4, _, _, phase_flag, _, _, _, _, _), + [55] = pingroup(55, west, qup17, qspi1_cs, _, _, _, _, _, _, _), + [56] = pingroup(56, west, qup17, qspi1, _, _, _, _, _, _, _), + [57] = pingroup(57, west, qup17, qspi1, _, _, _, _, _, _, _), + [58] = pingroup(58, west, usb1_phy, qup17, _, _, _, _, _, _, _), + [59] = pingroup(59, west, rgmii, qup_l4, _, _, _, _, _, _, _), + [60] = pingroup(60, east, gps, nav_pps, nav_pps, qup_l4, mdp_vsync, atest_usb1, ddr_pxi, _, _), + [61] = pingroup(61, east, qlink, _, _, _, _, _, _, _, _), + [62] = pingroup(62, east, qlink, atest_tsens2, atest_usb1, ddr_pxi, vsense_trigger, _, _, _, _), + [63] = pingroup(63, east, wmss_reset, _, atest_usb1, ddr_pxi, wlan1_adc, _, _, _, _), + [64] = pingroup(64, east, grfc, _, atest_usb1, ddr_pxi, wlan1_adc, _, _, _, _), + [65] = pingroup(65, east, grfc, atest_usb1, ddr_pxi, wlan2_adc, _, _, _, _, _), + [66] = pingroup(66, east, grfc, _, _, _, _, _, _, _, _), + [67] = pingroup(67, east, grfc, _, _, _, _, _, _, _, _), + [68] = pingroup(68, east, grfc, pa_indicator, atest_usb3, ddr_pxi, wlan2_adc, _, _, _, _), + [69] = pingroup(69, east, mss_lte, _, _, _, _, _, _, _, _), + [70] = pingroup(70, east, mss_lte, _, _, _, _, _, _, _, _), + [71] = pingroup(71, east, _, grfc, atest_usb3, ddr_pxi, _, _, _, _, _), + [72] = pingroup(72, east, _, grfc, atest_usb3, ddr_pxi, _, _, _, _, _), + [73] = pingroup(73, east, _, grfc, atest_usb3, ddr_pxi, _, _, _, _, _), + [74] = pingroup(74, east, _, grfc, tgu, atest_usb3, ddr_pxi, _, _, _, _), + [75] = pingroup(75, east, _, grfc, tgu, atest_usb4, ddr_pxi, _, _, _, _), + [76] = pingroup(76, east, _, grfc, gps, nav_pps, nav_pps, tgu, atest_usb4, ddr_pxi, _), + [77] = pingroup(77, east, _, grfc, gps, nav_pps, nav_pps, tgu, atest_usb4, ddr_pxi, _), + [78] = pingroup(78, east, _, grfc, _, atest_usb4, ddr_pxi, _, _, _, _), + [79] = pingroup(79, east, _, grfc, _, _, _, _, _, _, _), + [80] = pingroup(80, east, _, grfc, _, _, _, _, _, _, _), + [81] = pingroup(81, east, _, grfc, gps, nav_pps, nav_pps, qdss_cti, _, emac_pps, _), + [82] = pingroup(82, east, _, grfc, gps, nav_pps, nav_pps, mdp_vsync, qdss_cti, _, _), + [83] = pingroup(83, east, qup12, qup16, _, _, _, _, _, _, _), + [84] = pingroup(84, east, qup12, qup16, _, _, _, _, _, _, _), + [85] = pingroup(85, east, qup12, qup16, _, _, _, _, _, _, _), + [86] = pingroup(86, east, qup12, qup16, _, _, _, _, _, _, _), + [87] = pingroup(87, south, _, _, _, _, _, _, _, _, _), + [88] = pingroup(88, east, tsif1, qup8, qspi0_cs, tgu, atest_usb4, ddr_pxi, _, _, _), + [89] = pingroup(89, east, tsif1, qup8, qspi0, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5), + [90] = pingroup(90, east, tsif1, qup8, qspi0, sdc4_cmd, tgu, qdss_cti, atest_usb0, ddr_pxi, _), + [91] = pingroup(91, east, tsif1, qup8, qspi0, sdc4, vfr_1, tgu, atest_usb0, _, _), + [92] = pingroup(92, east, tsif2, qup11, qspi0_clk, sdc4_clk, qdss_gpio, atest_usb0, _, _, _), + [93] = pingroup(93, east, tsif2, qup11, qspi0, sdc4, atest_tsens, atest_usb0, _, _, _), + [94] = pingroup(94, east, tsif2, qup11, qspi0_cs, sdc4, _, atest_usb0, _, _, _), + [95] = pingroup(95, east, tsif2, qup11, sdc4, qup_l4, atest_usb2, _, _, _, _), + [96] = pingroup(96, west, tsif2, qup_l5, _, _, _, _, _, _, _), + [97] = pingroup(97, west, sd_write, tsif1, qup_l6, _, _, _, _, _, _), + [98] = pingroup(98, west, qup7, ddr_bist, _, _, _, _, _, _, _), + [99] = pingroup(99, west, qup7, ddr_bist, _, _, _, _, _, _, _), + [100] = pingroup(100, west, qup7, pll_bypassnl, _, _, _, _, _, _, _), + [101] = pingroup(101, west, qup7, pll_reset, _, _, _, _, _, _, _), + [102] = pingroup(102, south, pci_e1, _, phase_flag, atest_usb2, _, _, _, _, _), + [103] = pingroup(103, south, pci_e1, _, _, _, _, _, _, _, _), + [104] = pingroup(104, south, _, _, _, _, _, _, _, _, _), + [105] = pingroup(105, west, uim2, _, _, _, _, _, _, _, _), + [106] = pingroup(106, west, uim2, _, _, _, _, _, _, _, _), + [107] = pingroup(107, west, uim2, _, _, _, _, _, _, _, _), + [108] = pingroup(108, west, uim2, _, _, _, _, _, _, _, _), + [109] = pingroup(109, west, uim1, _, _, _, _, _, _, _, _), + [110] = pingroup(110, west, uim1, _, _, _, _, _, _, _, _), + [111] = pingroup(111, west, uim1, _, _, _, _, _, _, _, _), + [112] = pingroup(112, west, uim1, _, _, _, _, _, _, _, _), + [113] = pingroup(113, west, uim_batt, usb2phy_ac, aoss_cti, _, _, _, _, _, _), + [114] = pingroup(114, west, qup1, rgmii, _, qdss_gpio, _, _, _, _, _), + [115] = pingroup(115, west, qup1, rgmii, adsp_ext, _, qdss_gpio, _, _, _, _), + [116] = pingroup(116, west, qup1, rgmii, _, qdss_gpio, _, _, _, _, _), + [117] = pingroup(117, west, qup1, rgmii, _, qdss_gpio, _, _, _, _, _), + [118] = pingroup(118, west, rgmii, _, qdss_gpio, _, _, _, _, _, _), + [119] = pingroup(119, west, qup5, rgmii, _, qdss_gpio, _, _, _, _, _), + [120] = pingroup(120, west, qup5, rgmii, _, phase_flag, qdss_gpio, _, _, _, _), + [121] = pingroup(121, west, qup5, rgmii, _, phase_flag, qdss_gpio, atest_usb2, _, _, _), + [122] = pingroup(122, west, qup5, rgmii, _, phase_flag, atest_usb2, _, _, _, _), + [123] = pingroup(123, south, usb2phy_ac, _, phase_flag, _, _, _, _, _, _), + [124] = pingroup(124, south, emac_phy, _, _, _, _, _, _, _, _), + [125] = pingroup(125, west, hs3_mi2s, _, phase_flag, _, _, _, _, _, _), + [126] = pingroup(126, west, sec_mi2s, qup2, _, _, _, _, _, _, _), + [127] = pingroup(127, west, sec_mi2s, qup2, _, _, _, _, _, _, _), + [128] = pingroup(128, west, sec_mi2s, qup2, _, _, _, _, _, _, _), + [129] = pingroup(129, west, sec_mi2s, qup2, jitter_bist, _, _, _, _, _, _), + [130] = pingroup(130, west, sec_mi2s, pll_bist, _, qdss_gpio, _, _, _, _, _), + [131] = pingroup(131, west, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _), + [132] = pingroup(132, west, ter_mi2s, _, qdss_gpio, _, _, _, _, _, _), + [133] = pingroup(133, west, ter_mi2s, _, qdss_gpio, atest_char, _, _, _, _, _), + [134] = pingroup(134, west, ter_mi2s, _, qdss_gpio, atest_char, _, _, _, _, _), + [135] = pingroup(135, west, ter_mi2s, _, qdss_gpio, atest_char, _, _, _, _, _), + [136] = pingroup(136, west, qua_mi2s, gcc_gp1, _, _, _, _, _, _, _), + [137] = pingroup(137, west, qua_mi2s, gcc_gp2, _, _, _, _, _, _, _), + [138] = pingroup(138, west, qua_mi2s, gcc_gp3, _, _, _, _, _, _, _), + [139] = pingroup(139, west, qua_mi2s, gcc_gp4, _, _, _, _, _, _, _), + [140] = pingroup(140, west, qua_mi2s, gcc_gp5, _, atest_char, _, _, _, _, _), + [141] = pingroup(141, west, qua_mi2s, qdss_cti, _, _, _, _, _, _, _), + [142] = pingroup(142, west, qua_mi2s, _, _, qdss_cti, atest_char, _, _, _, _), + [143] = pingroup(143, west, pri_mi2s, _, _, _, _, _, _, _, _), + [144] = pingroup(144, west, pri_mi2s, qup3, _, _, _, _, _, _, _), + [145] = pingroup(145, west, pri_mi2s_ws, qup3, ddr_bist, _, _, _, _, _, _), + [146] = pingroup(146, west, pri_mi2s, qup3, ddr_bist, _, _, _, _, _, _), + [147] = pingroup(147, west, pri_mi2s, qup3, _, _, _, _, _, _, _), + [148] = pingroup(148, west, spkr_i2s, audio_ref, _, phase_flag, _, _, _, _, _), + [149] = pingroup(149, west, lpass_slimbus, spkr_i2s, _, phase_flag, _, _, _, _, _), + [150] = pingroup(150, west, lpass_slimbus, spkr_i2s, _, phase_flag, tsense_pwm1, tsense_pwm2, _, _, _), + [151] = pingroup(151, west, lpass_slimbus, spkr_i2s, _, phase_flag, _, _, _, _, _), + [152] = pingroup(152, west, lpass_slimbus, spkr_i2s, _, phase_flag, _, _, _, _, _), + [153] = pingroup(153, west, btfm_slimbus, _, _, _, _, _, _, _, _), + [154] = pingroup(154, west, btfm_slimbus, _, _, _, _, _, _, _, _), + [155] = pingroup(155, west, hs1_mi2s, _, phase_flag, _, _, _, _, _, _), + [156] = pingroup(156, west, hs1_mi2s, _, phase_flag, _, _, _, _, _, _), + [157] = pingroup(157, west, hs1_mi2s, _, phase_flag, _, _, _, _, _, _), + [158] = pingroup(158, west, hs1_mi2s, _, phase_flag, _, _, _, _, _, _), + [159] = pingroup(159, west, hs1_mi2s, cri_trng, _, phase_flag, _, _, _, _, _), + [160] = pingroup(160, west, hs2_mi2s, cri_trng, _, phase_flag, _, _, _, _, _), + [161] = pingroup(161, west, hs2_mi2s, qspi1, cri_trng, _, phase_flag, _, _, _, _), + [162] = pingroup(162, west, hs2_mi2s, qspi1, sp_cmu, _, phase_flag, _, _, _, _), + [163] = pingroup(163, west, hs2_mi2s, qspi1_clk, prng_rosc, _, phase_flag, _, _, _, _), + [164] = pingroup(164, west, hs2_mi2s, qspi1_cs, _, phase_flag, _, _, _, _, _), + [165] = pingroup(165, west, hs3_mi2s, _, phase_flag, _, _, _, _, _, _), + [166] = pingroup(166, west, hs3_mi2s, _, phase_flag, _, _, _, _, _, _), + [167] = pingroup(167, west, hs3_mi2s, _, phase_flag, _, _, _, _, _, _), + [168] = pingroup(168, west, hs3_mi2s, _, phase_flag, _, _, _, _, _, _), + [169] = pingroup(169, south, _, _, _, _, _, _, _, _, _), + [170] = pingroup(170, south, _, _, _, _, _, _, _, _, _), + [171] = pingroup(171, south, _, _, _, _, _, _, _, _, _), + [172] = pingroup(172, south, _, _, _, _, _, _, _, _, _), + [173] = pingroup(173, south, _, _, _, _, _, _, _, _, _), + [174] = pingroup(174, south, _, _, _, _, _, _, _, _, _), + [175] = pingroup(175, south, pci_e2, _, _, _, _, _, _, _, _), + [176] = pingroup(176, south, pci_e2, cci_async, _, _, _, _, _, _, _), + [177] = pingroup_offset(177, south, 0x1e000, _, _, _, _, _, _, _, _, _), + [178] = pingroup_offset(178, south, 0x1e000, pci_e3, cci_timer4, _, _, _, _, _, _, _), + [179] = pingroup_offset(179, south, 0x1e000, pci_e3, cam_mclk, _, _, _, _, _, _, _), + [180] = pingroup_offset(180, south, 0x1e000, cam_mclk, _, _, _, _, _, _, _, _), + [181] = pingroup_offset(181, south, 0x1e000, qup19, cam_mclk, _, _, _, _, _, _, _), + [182] = pingroup_offset(182, south, 0x1e000, qup19, cci_timer5, gcc_gp4, _, _, _, _, _, _), + [183] = pingroup_offset(183, south, 0x1e000, qup19, cci_timer6, gcc_gp5, _, _, _, _, _, _), + [184] = pingroup_offset(184, south, 0x1e000, qup19, cci_timer7, _, _, _, _, _, _, _), + [185] = pingroup_offset(185, south, 0x1e000, cci_timer8, cci_async, _, _, _, _, _, _, _), + [186] = pingroup_offset(186, south, 0x1e000, cci_timer9, cci_async, _, _, _, _, _, _, _), + [187] = pingroup_offset(187, south, 0x1e000, _, _, _, _, _, _, _, _, _), + [188] = pingroup_offset(188, south, 0x1e000, _, _, _, _, _, _, _, _, _), + [189] = pingroup_offset(189, south, 0x1e000, dp_hot, _, _, _, _, _, _, _, _), + [190] = ufs_reset(ufs_reset), + [191] = sdc_qdsd_pingroup(sdc2_clk, 0x4b2000, 14, 6), + [192] = sdc_qdsd_pingroup(sdc2_cmd, 0x4b2000, 11, 3), + [193] = sdc_qdsd_pingroup(sdc2_data, 0x4b2000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sc8180x_pdc_map[] = { + { 3, 31 }, { 5, 32 }, { 8, 33 }, { 9, 34 }, { 10, 100 }, { 12, 104 }, + { 24, 37 }, { 26, 38 }, { 27, 41 }, { 28, 42 }, { 30, 39 }, { 36, 43 }, + { 37, 43 }, { 38, 45 }, { 39, 118 }, { 39, 125 }, { 41, 47 }, + { 42, 48 }, { 46, 50 }, { 47, 49 }, { 48, 51 }, { 49, 53 }, { 50, 52 }, + { 51, 116 }, { 51, 123 }, { 53, 54 }, { 54, 55 }, { 55, 56 }, + { 56, 57 }, { 58, 58 }, { 60, 60 }, { 68, 62 }, { 70, 63 }, { 76, 86 }, + { 77, 36 }, { 81, 64 }, { 83, 65 }, { 86, 67 }, { 87, 84 }, { 88, 117 }, + { 88, 124 }, { 90, 69 }, { 91, 70 }, { 93, 75 }, { 95, 72 }, { 97, 74 }, + { 101, 76 }, { 103, 77 }, { 104, 78 }, { 114, 82 }, { 117, 85 }, + { 118, 101 }, { 119, 87 }, { 120, 88 }, { 121, 89 }, { 122, 90 }, + { 123, 91 }, { 124, 92 }, { 125, 93 }, { 129, 94 }, { 132, 105 }, + { 133, 35 }, { 134, 36 }, { 136, 97 }, { 142, 103 }, { 144, 115 }, + { 144, 122 }, { 147, 106 }, { 150, 107 }, { 152, 108 }, { 153, 109 }, + { 177, 111 }, { 180, 112 }, { 184, 113 }, { 189, 114 } +}; + +static struct msm_pinctrl_soc_data sc8180x_pinctrl = { + .tiles = sc8180x_tiles, + .ntiles = array_size(sc8180x_tiles), + .pins = sc8180x_pins, + .npins = array_size(sc8180x_pins), + .functions = sc8180x_functions, + .nfunctions = array_size(sc8180x_functions), + .groups = sc8180x_groups, + .ngroups = array_size(sc8180x_groups), + .ngpios = 191, + .wakeirq_map = sc8180x_pdc_map, + .nwakeirq_map = array_size(sc8180x_pdc_map), +}; + +static int sc8180x_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sc8180x_pinctrl); +} + +static const struct of_device_id sc8180x_pinctrl_of_match[] = { + { .compatible = "qcom,sc8180x-tlmm", }, + { }, +}; +module_device_table(of, sc8180x_pinctrl_of_match); + +static struct platform_driver sc8180x_pinctrl_driver = { + .driver = { + .name = "sc8180x-pinctrl", + .of_match_table = sc8180x_pinctrl_of_match, + }, + .probe = sc8180x_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sc8180x_pinctrl_init(void) +{ + return platform_driver_register(&sc8180x_pinctrl_driver); +} +arch_initcall(sc8180x_pinctrl_init); + +static void __exit sc8180x_pinctrl_exit(void) +{ + platform_driver_unregister(&sc8180x_pinctrl_driver); +} +module_exit(sc8180x_pinctrl_exit); + +module_description("qti sc8180x pinctrl driver"); +module_license("gpl v2");
|
Pin Controllers (pinctrl)
|
97423113ec4bbfe92c13ff4794d33391ab70ec96
|
bjorn andersson
|
drivers
|
pinctrl
|
qcom
|
pinctrl: renesas: initial r8a779a0 (v3u) pfc support
|
this patch adds initial pinctrl support for the r8a779a0 (v3u) soc, including bias, drive strength and voltage control.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
initial r8a779a0 (v3u) pfc support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['renesas']
|
['h', 'kconfig', 'c', 'makefile']
| 5
| 2,529
| 0
|
--- diff --git a/drivers/pinctrl/renesas/kconfig b/drivers/pinctrl/renesas/kconfig --- a/drivers/pinctrl/renesas/kconfig +++ b/drivers/pinctrl/renesas/kconfig + select pinctrl_pfc_r8a779a0 if arch_r8a779a0 +config pinctrl_pfc_r8a779a0 + bool "pin control support for r-car v3u" if compile_test + select pinctrl_sh_pfc + diff --git a/drivers/pinctrl/renesas/makefile b/drivers/pinctrl/renesas/makefile --- a/drivers/pinctrl/renesas/makefile +++ b/drivers/pinctrl/renesas/makefile +obj-$(config_pinctrl_pfc_r8a779a0) += pfc-r8a779a0.o diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c --- a/drivers/pinctrl/renesas/core.c +++ b/drivers/pinctrl/renesas/core.c +#ifdef config_pinctrl_pfc_r8a779a0 + { + .compatible = "renesas,pfc-r8a779a0", + .data = &r8a779a0_pinmux_info, + }, +#endif diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c --- /dev/null +++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c +// spdx-license-identifier: gpl-2.0 +/* + * r8a779a0 processor support - pfc hardware block. + * + * copyright (c) 2020 renesas electronics corp. + * + * this file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c + */ + +#include <linux/errno.h> +#include <linux/io.h> +#include <linux/kernel.h> + +#include "core.h" +#include "sh_pfc.h" + +#define cfg_flags (sh_pfc_pin_cfg_drive_strength | sh_pfc_pin_cfg_pull_up_down) + +#define cpu_all_gp(fn, sfx) \ + port_gp_cfg_15(0, fn, sfx, cfg_flags), \ + port_gp_cfg_1(0, 15, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(0, 16, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(0, 17, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(0, 18, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(0, 19, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(0, 20, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(0, 21, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(0, 22, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(0, 23, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(0, 24, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(0, 25, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(0, 26, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(0, 27, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_31(1, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_2(2, fn, sfx, cfg_flags), \ + port_gp_cfg_1(2, 2, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(2, 3, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(2, 4, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(2, 5, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(2, 6, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(2, 7, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(2, 8, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(2, 9, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(2, 10, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(2, 11, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(2, 12, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(2, 13, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(2, 14, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(2, 15, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_18_33), \ + port_gp_cfg_1(2, 16, fn, sfx, cfg_flags), \ + port_gp_cfg_1(2, 17, fn, sfx, cfg_flags), \ + port_gp_cfg_1(2, 18, fn, sfx, cfg_flags), \ + port_gp_cfg_1(2, 19, fn, sfx, cfg_flags), \ + port_gp_cfg_1(2, 20, fn, sfx, cfg_flags), \ + port_gp_cfg_1(2, 21, fn, sfx, cfg_flags), \ + port_gp_cfg_1(2, 22, fn, sfx, cfg_flags), \ + port_gp_cfg_1(2, 23, fn, sfx, cfg_flags), \ + port_gp_cfg_1(2, 24, fn, sfx, cfg_flags), \ + port_gp_cfg_17(3, fn, sfx, cfg_flags), \ + port_gp_cfg_18(4, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_25_33),\ + port_gp_cfg_1(4, 18, fn, sfx, cfg_flags), \ + port_gp_cfg_1(4, 19, fn, sfx, cfg_flags), \ + port_gp_cfg_1(4, 20, fn, sfx, cfg_flags), \ + port_gp_cfg_1(4, 21, fn, sfx, cfg_flags), \ + port_gp_cfg_1(4, 22, fn, sfx, cfg_flags), \ + port_gp_cfg_1(4, 23, fn, sfx, cfg_flags), \ + port_gp_cfg_1(4, 24, fn, sfx, cfg_flags), \ + port_gp_cfg_1(4, 25, fn, sfx, cfg_flags), \ + port_gp_cfg_1(4, 26, fn, sfx, cfg_flags), \ + port_gp_cfg_18(5, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_25_33),\ + port_gp_cfg_1(5, 18, fn, sfx, cfg_flags), \ + port_gp_cfg_1(5, 19, fn, sfx, cfg_flags), \ + port_gp_cfg_1(5, 20, fn, sfx, cfg_flags), \ + port_gp_cfg_18(6, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_25_33),\ + port_gp_cfg_1(6, 18, fn, sfx, cfg_flags), \ + port_gp_cfg_1(6, 19, fn, sfx, cfg_flags), \ + port_gp_cfg_1(6, 20, fn, sfx, cfg_flags), \ + port_gp_cfg_18(7, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_25_33),\ + port_gp_cfg_1(7, 18, fn, sfx, cfg_flags), \ + port_gp_cfg_1(7, 19, fn, sfx, cfg_flags), \ + port_gp_cfg_1(7, 20, fn, sfx, cfg_flags), \ + port_gp_cfg_18(8, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_25_33),\ + port_gp_cfg_1(8, 18, fn, sfx, cfg_flags), \ + port_gp_cfg_1(8, 19, fn, sfx, cfg_flags), \ + port_gp_cfg_1(8, 20, fn, sfx, cfg_flags), \ + port_gp_cfg_18(9, fn, sfx, cfg_flags | sh_pfc_pin_cfg_io_voltage_25_33),\ + port_gp_cfg_1(9, 18, fn, sfx, cfg_flags), \ + port_gp_cfg_1(9, 19, fn, sfx, cfg_flags), \ + port_gp_cfg_1(9, 20, fn, sfx, cfg_flags) + +#define cpu_all_nogp(fn) \ + pin_nogp_cfg(presetout_n, "presetout#", fn, sh_pfc_pin_cfg_pull_up_down), \ + pin_nogp_cfg(extalr, "extalr", fn, sh_pfc_pin_cfg_pull_up_down), \ + pin_nogp_cfg(dcutrst_n_lpdrst_n, "dcutrst#_lpdrst#", fn, sh_pfc_pin_cfg_pull_up_down), \ + pin_nogp_cfg(dcutck_lpdclk, "dcutck_lpdclk", fn, sh_pfc_pin_cfg_pull_up_down), \ + pin_nogp_cfg(dcutms, "dcutms", fn, sh_pfc_pin_cfg_pull_up_down), \ + pin_nogp_cfg(dcutdi_lpdi, "dcutdi_lpdi", fn, sh_pfc_pin_cfg_pull_up_down) + +/* + * f_() : just information + * fm() : macro for fn_xxx / xxx_mark + */ + +/* gpsr0 */ +#define gpsr0_27 fm(mmc_d7) +#define gpsr0_26 fm(mmc_d6) +#define gpsr0_25 fm(mmc_d5) +#define gpsr0_24 fm(mmc_d4) +#define gpsr0_23 fm(mmc_sd_clk) +#define gpsr0_22 fm(mmc_sd_d3) +#define gpsr0_21 fm(mmc_sd_d2) +#define gpsr0_20 fm(mmc_sd_d1) +#define gpsr0_19 fm(mmc_sd_d0) +#define gpsr0_18 fm(mmc_sd_cmd) +#define gpsr0_17 fm(mmc_ds) +#define gpsr0_16 fm(sd_cd) +#define gpsr0_15 fm(sd_wp) +#define gpsr0_14 fm(rpc_int_n) +#define gpsr0_13 fm(rpc_wp_n) +#define gpsr0_12 fm(rpc_reset_n) +#define gpsr0_11 fm(qspi1_ssl) +#define gpsr0_10 fm(qspi1_io3) +#define gpsr0_9 fm(qspi1_io2) +#define gpsr0_8 fm(qspi1_miso_io1) +#define gpsr0_7 fm(qspi1_mosi_io0) +#define gpsr0_6 fm(qspi1_spclk) +#define gpsr0_5 fm(qspi0_ssl) +#define gpsr0_4 fm(qspi0_io3) +#define gpsr0_3 fm(qspi0_io2) +#define gpsr0_2 fm(qspi0_miso_io1) +#define gpsr0_1 fm(qspi0_mosi_io0) +#define gpsr0_0 fm(qspi0_spclk) + +/* gpsr1 */ +#define gpsr1_30 f_(gp1_30, ip3sr1_27_24) +#define gpsr1_29 f_(gp1_29, ip3sr1_23_20) +#define gpsr1_28 f_(gp1_28, ip3sr1_19_16) +#define gpsr1_27 f_(irq3, ip3sr1_15_12) +#define gpsr1_26 f_(irq2, ip3sr1_11_8) +#define gpsr1_25 f_(irq1, ip3sr1_7_4) +#define gpsr1_24 f_(irq0, ip3sr1_3_0) +#define gpsr1_23 f_(msiof2_ss2, ip2sr1_31_28) +#define gpsr1_22 f_(msiof2_ss1, ip2sr1_27_24) +#define gpsr1_21 f_(msiof2_sync, ip2sr1_23_20) +#define gpsr1_20 f_(msiof2_sck, ip2sr1_19_16) +#define gpsr1_19 f_(msiof2_txd, ip2sr1_15_12) +#define gpsr1_18 f_(msiof2_rxd, ip2sr1_11_8) +#define gpsr1_17 f_(msiof1_ss2, ip2sr1_7_4) +#define gpsr1_16 f_(msiof1_ss1, ip2sr1_3_0) +#define gpsr1_15 f_(msiof1_sync, ip1sr1_31_28) +#define gpsr1_14 f_(msiof1_sck, ip1sr1_27_24) +#define gpsr1_13 f_(msiof1_txd, ip1sr1_23_20) +#define gpsr1_12 f_(msiof1_rxd, ip1sr1_19_16) +#define gpsr1_11 f_(msiof0_ss2, ip1sr1_15_12) +#define gpsr1_10 f_(msiof0_ss1, ip1sr1_11_8) +#define gpsr1_9 f_(msiof0_sync, ip1sr1_7_4) +#define gpsr1_8 f_(msiof0_sck, ip1sr1_3_0) +#define gpsr1_7 f_(msiof0_txd, ip0sr1_31_28) +#define gpsr1_6 f_(msiof0_rxd, ip0sr1_27_24) +#define gpsr1_5 f_(htx0, ip0sr1_23_20) +#define gpsr1_4 f_(hcts0_n, ip0sr1_19_16) +#define gpsr1_3 f_(hrts0_n, ip0sr1_15_12) +#define gpsr1_2 f_(hsck0, ip0sr1_11_8) +#define gpsr1_1 f_(hrx0, ip0sr1_7_4) +#define gpsr1_0 f_(scif_clk, ip0sr1_3_0) + +/* gpsr2 */ +#define gpsr2_24 fm(tclk2_a) +#define gpsr2_23 f_(tclk1_a, ip2sr2_31_28) +#define gpsr2_22 f_(tpu0to1, ip2sr2_27_24) +#define gpsr2_21 f_(tpu0to0, ip2sr2_23_20) +#define gpsr2_20 f_(clk_extfxr, ip2sr2_19_16) +#define gpsr2_19 f_(rxdb_extfxr, ip2sr2_15_12) +#define gpsr2_18 f_(fxr_txdb, ip2sr2_11_8) +#define gpsr2_17 f_(rxda_extfxr_a, ip2sr2_7_4) +#define gpsr2_16 f_(fxr_txda_a, ip2sr2_3_0) +#define gpsr2_15 f_(gp2_15, ip1sr2_31_28) +#define gpsr2_14 f_(gp2_14, ip1sr2_27_24) +#define gpsr2_13 f_(gp2_13, ip1sr2_23_20) +#define gpsr2_12 f_(gp2_12, ip1sr2_19_16) +#define gpsr2_11 f_(gp2_11, ip1sr2_15_12) +#define gpsr2_10 f_(gp2_10, ip1sr2_11_8) +#define gpsr2_9 f_(gp2_09, ip1sr2_7_4) +#define gpsr2_8 f_(gp2_08, ip1sr2_3_0) +#define gpsr2_7 f_(gp2_07, ip0sr2_31_28) +#define gpsr2_6 f_(gp2_06, ip0sr2_27_24) +#define gpsr2_5 f_(gp2_05, ip0sr2_23_20) +#define gpsr2_4 f_(gp2_04, ip0sr2_19_16) +#define gpsr2_3 f_(gp2_03, ip0sr2_15_12) +#define gpsr2_2 f_(gp2_02, ip0sr2_11_8) +#define gpsr2_1 f_(ipc_clkout, ip0sr2_7_4) +#define gpsr2_0 f_(ipc_clkin, ip0sr2_3_0) + +/* gpsr3 */ +#define gpsr3_16 fm(canfd7_rx) +#define gpsr3_15 fm(canfd7_tx) +#define gpsr3_14 fm(canfd6_rx) +#define gpsr3_13 f_(canfd6_tx, ip1sr3_23_20) +#define gpsr3_12 f_(canfd5_rx, ip1sr3_19_16) +#define gpsr3_11 f_(canfd5_tx, ip1sr3_15_12) +#define gpsr3_10 f_(canfd4_rx, ip1sr3_11_8) +#define gpsr3_9 f_(canfd4_tx, ip1sr3_7_4) +#define gpsr3_8 f_(canfd3_rx, ip1sr3_3_0) +#define gpsr3_7 f_(canfd3_tx, ip0sr3_31_28) +#define gpsr3_6 f_(canfd2_rx, ip0sr3_27_24) +#define gpsr3_5 f_(canfd2_tx, ip0sr3_23_20) +#define gpsr3_4 fm(canfd1_rx) +#define gpsr3_3 fm(canfd1_tx) +#define gpsr3_2 f_(canfd0_rx, ip0sr3_11_8) +#define gpsr3_1 f_(canfd0_tx, ip0sr3_7_4) +#define gpsr3_0 fm(can_clk) + +/* gpsr4 */ +#define gpsr4_26 fm(avs1) +#define gpsr4_25 fm(avs0) +#define gpsr4_24 fm(pcie3_clkreq_n) +#define gpsr4_23 fm(pcie2_clkreq_n) +#define gpsr4_22 fm(pcie1_clkreq_n) +#define gpsr4_21 fm(pcie0_clkreq_n) +#define gpsr4_20 f_(avb0_avtp_pps, ip2sr4_19_16) +#define gpsr4_19 f_(avb0_avtp_capture, ip2sr4_15_12) +#define gpsr4_18 f_(avb0_avtp_match, ip2sr4_11_8) +#define gpsr4_17 f_(avb0_link, ip2sr4_7_4) +#define gpsr4_16 fm(avb0_phy_int) +#define gpsr4_15 f_(avb0_magic, ip1sr4_31_28) +#define gpsr4_14 f_(avb0_mdc, ip1sr4_27_24) +#define gpsr4_13 f_(avb0_mdio, ip1sr4_23_20) +#define gpsr4_12 f_(avb0_txcrefclk, ip1sr4_19_16) +#define gpsr4_11 f_(avb0_td3, ip1sr4_15_12) +#define gpsr4_10 f_(avb0_td2, ip1sr4_11_8) +#define gpsr4_9 f_(avb0_td1, ip1sr4_7_4) +#define gpsr4_8 f_(avb0_td0, ip1sr4_3_0) +#define gpsr4_7 f_(avb0_txc, ip0sr4_31_28) +#define gpsr4_6 f_(avb0_tx_ctl, ip0sr4_27_24) +#define gpsr4_5 f_(avb0_rd3, ip0sr4_23_20) +#define gpsr4_4 f_(avb0_rd2, ip0sr4_19_16) +#define gpsr4_3 f_(avb0_rd1, ip0sr4_15_12) +#define gpsr4_2 f_(avb0_rd0, ip0sr4_11_8) +#define gpsr4_1 f_(avb0_rxc, ip0sr4_7_4) +#define gpsr4_0 f_(avb0_rx_ctl, ip0sr4_3_0) + +/* gpsr5 */ +#define gpsr5_20 f_(avb1_avtp_pps, ip2sr5_19_16) +#define gpsr5_19 f_(avb1_avtp_capture, ip2sr5_15_12) +#define gpsr5_18 f_(avb1_avtp_match, ip2sr5_11_8) +#define gpsr5_17 f_(avb1_link, ip2sr5_7_4) +#define gpsr5_16 fm(avb1_phy_int) +#define gpsr5_15 f_(avb1_magic, ip1sr5_31_28) +#define gpsr5_14 f_(avb1_mdc, ip1sr5_27_24) +#define gpsr5_13 f_(avb1_mdio, ip1sr5_23_20) +#define gpsr5_12 f_(avb1_txcrefclk, ip1sr5_19_16) +#define gpsr5_11 f_(avb1_td3, ip1sr5_15_12) +#define gpsr5_10 f_(avb1_td2, ip1sr5_11_8) +#define gpsr5_9 f_(avb1_td1, ip1sr5_7_4) +#define gpsr5_8 f_(avb1_td0, ip1sr5_3_0) +#define gpsr5_7 f_(avb1_txc, ip0sr5_31_28) +#define gpsr5_6 f_(avb1_tx_ctl, ip0sr5_27_24) +#define gpsr5_5 f_(avb1_rd3, ip0sr5_23_20) +#define gpsr5_4 f_(avb1_rd2, ip0sr5_19_16) +#define gpsr5_3 f_(avb1_rd1, ip0sr5_15_12) +#define gpsr5_2 f_(avb1_rd0, ip0sr5_11_8) +#define gpsr5_1 f_(avb1_rxc, ip0sr5_7_4) +#define gpsr5_0 f_(avb1_rx_ctl, ip0sr5_3_0) + +/* gpsr6 */ +#define gpsr6_20 fm(avb2_avtp_pps) +#define gpsr6_19 fm(avb2_avtp_capture) +#define gpsr6_18 fm(avb2_avtp_match) +#define gpsr6_17 fm(avb2_link) +#define gpsr6_16 fm(avb2_phy_int) +#define gpsr6_15 fm(avb2_magic) +#define gpsr6_14 fm(avb2_mdc) +#define gpsr6_13 fm(avb2_mdio) +#define gpsr6_12 fm(avb2_txcrefclk) +#define gpsr6_11 fm(avb2_td3) +#define gpsr6_10 fm(avb2_td2) +#define gpsr6_9 fm(avb2_td1) +#define gpsr6_8 fm(avb2_td0) +#define gpsr6_7 fm(avb2_txc) +#define gpsr6_6 fm(avb2_tx_ctl) +#define gpsr6_5 fm(avb2_rd3) +#define gpsr6_4 fm(avb2_rd2) +#define gpsr6_3 fm(avb2_rd1) +#define gpsr6_2 fm(avb2_rd0) +#define gpsr6_1 fm(avb2_rxc) +#define gpsr6_0 fm(avb2_rx_ctl) + +/* gpsr7 */ +#define gpsr7_20 fm(avb3_avtp_pps) +#define gpsr7_19 fm(avb3_avtp_capture) +#define gpsr7_18 fm(avb3_avtp_match) +#define gpsr7_17 fm(avb3_link) +#define gpsr7_16 fm(avb3_phy_int) +#define gpsr7_15 fm(avb3_magic) +#define gpsr7_14 fm(avb3_mdc) +#define gpsr7_13 fm(avb3_mdio) +#define gpsr7_12 fm(avb3_txcrefclk) +#define gpsr7_11 fm(avb3_td3) +#define gpsr7_10 fm(avb3_td2) +#define gpsr7_9 fm(avb3_td1) +#define gpsr7_8 fm(avb3_td0) +#define gpsr7_7 fm(avb3_txc) +#define gpsr7_6 fm(avb3_tx_ctl) +#define gpsr7_5 fm(avb3_rd3) +#define gpsr7_4 fm(avb3_rd2) +#define gpsr7_3 fm(avb3_rd1) +#define gpsr7_2 fm(avb3_rd0) +#define gpsr7_1 fm(avb3_rxc) +#define gpsr7_0 fm(avb3_rx_ctl) + +/* gpsr8 */ +#define gpsr8_20 fm(avb4_avtp_pps) +#define gpsr8_19 fm(avb4_avtp_capture) +#define gpsr8_18 fm(avb4_avtp_match) +#define gpsr8_17 fm(avb4_link) +#define gpsr8_16 fm(avb4_phy_int) +#define gpsr8_15 fm(avb4_magic) +#define gpsr8_14 fm(avb4_mdc) +#define gpsr8_13 fm(avb4_mdio) +#define gpsr8_12 fm(avb4_txcrefclk) +#define gpsr8_11 fm(avb4_td3) +#define gpsr8_10 fm(avb4_td2) +#define gpsr8_9 fm(avb4_td1) +#define gpsr8_8 fm(avb4_td0) +#define gpsr8_7 fm(avb4_txc) +#define gpsr8_6 fm(avb4_tx_ctl) +#define gpsr8_5 fm(avb4_rd3) +#define gpsr8_4 fm(avb4_rd2) +#define gpsr8_3 fm(avb4_rd1) +#define gpsr8_2 fm(avb4_rd0) +#define gpsr8_1 fm(avb4_rxc) +#define gpsr8_0 fm(avb4_rx_ctl) + +/* gpsr9 */ +#define gpsr9_20 fm(avb5_avtp_pps) +#define gpsr9_19 fm(avb5_avtp_capture) +#define gpsr9_18 fm(avb5_avtp_match) +#define gpsr9_17 fm(avb5_link) +#define gpsr9_16 fm(avb5_phy_int) +#define gpsr9_15 fm(avb5_magic) +#define gpsr9_14 fm(avb5_mdc) +#define gpsr9_13 fm(avb5_mdio) +#define gpsr9_12 fm(avb5_txcrefclk) +#define gpsr9_11 fm(avb5_td3) +#define gpsr9_10 fm(avb5_td2) +#define gpsr9_9 fm(avb5_td1) +#define gpsr9_8 fm(avb5_td0) +#define gpsr9_7 fm(avb5_txc) +#define gpsr9_6 fm(avb5_tx_ctl) +#define gpsr9_5 fm(avb5_rd3) +#define gpsr9_4 fm(avb5_rd2) +#define gpsr9_3 fm(avb5_rd1) +#define gpsr9_2 fm(avb5_rd0) +#define gpsr9_1 fm(avb5_rxc) +#define gpsr9_0 fm(avb5_rx_ctl) + +/* ip0sr1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - f */ +#define ip0sr1_3_0 fm(scif_clk) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) fm(a0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr1_7_4 fm(hrx0) fm(rx0) f_(0, 0) f_(0, 0) f_(0, 0) fm(a1) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr1_11_8 fm(hsck0) fm(sck0) f_(0, 0) f_(0, 0) f_(0, 0) fm(a2) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr1_15_12 fm(hrts0_n) fm(rts0_n) f_(0, 0) f_(0, 0) f_(0, 0) fm(a3) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr1_19_16 fm(hcts0_n) fm(cts0_n) f_(0, 0) f_(0, 0) f_(0, 0) fm(a4) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr1_23_20 fm(htx0) fm(tx0) f_(0, 0) f_(0, 0) f_(0, 0) fm(a5) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr1_27_24 fm(msiof0_rxd) f_(0, 0) f_(0, 0) f_(0, 0) fm(du_dr2) fm(a6) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr1_31_28 fm(msiof0_txd) f_(0, 0) f_(0, 0) f_(0, 0) fm(du_dr3) fm(a7) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +/* ip1sr1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - f */ +#define ip1sr1_3_0 fm(msiof0_sck) f_(0, 0) f_(0, 0) f_(0, 0) fm(du_dr4) fm(a8) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr1_7_4 fm(msiof0_sync) f_(0, 0) f_(0, 0) f_(0, 0) fm(du_dr5) fm(a9) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr1_11_8 fm(msiof0_ss1) f_(0, 0) f_(0, 0) f_(0, 0) fm(du_dr6) fm(a10) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr1_15_12 fm(msiof0_ss2) f_(0, 0) f_(0, 0) f_(0, 0) fm(du_dr7) fm(a11) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr1_19_16 fm(msiof1_rxd) f_(0, 0) f_(0, 0) f_(0, 0) fm(du_dg2) fm(a12) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr1_23_20 fm(msiof1_txd) fm(hrx3) fm(sck3) f_(0, 0) fm(du_dg3) fm(a13) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr1_27_24 fm(msiof1_sck) fm(hsck3) fm(cts3_n) f_(0, 0) fm(du_dg4) fm(a14) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr1_31_28 fm(msiof1_sync) fm(hrts3_n) fm(rts3_n) f_(0, 0) fm(du_dg5) fm(a15) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +/* ip2sr1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - f */ +#define ip2sr1_3_0 fm(msiof1_ss1) fm(hcts3_n) fm(rx3) f_(0, 0) fm(du_dg6) fm(a16) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr1_7_4 fm(msiof1_ss2) fm(htx3) fm(tx3) f_(0, 0) fm(du_dg7) fm(a17) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr1_11_8 fm(msiof2_rxd) fm(hsck1) fm(sck1) f_(0, 0) fm(du_db2) fm(a18) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr1_15_12 fm(msiof2_txd) fm(hcts1_n) fm(cts1_n) f_(0, 0) fm(du_db3) fm(a19) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr1_19_16 fm(msiof2_sck) fm(hrts1_n) fm(rts1_n) f_(0, 0) fm(du_db4) fm(a20) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr1_23_20 fm(msiof2_sync) fm(hrx1) fm(rx1_a) f_(0, 0) fm(du_db5) fm(a21) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr1_27_24 fm(msiof2_ss1) fm(htx1) fm(tx1_a) f_(0, 0) fm(du_db6) fm(a22) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr1_31_28 fm(msiof2_ss2) fm(tclk1_b) f_(0, 0) f_(0, 0) fm(du_db7) fm(a23) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) + +/* ip3sr1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - f */ +#define ip3sr1_3_0 fm(irq0) f_(0, 0) f_(0, 0) f_(0, 0) fm(du_dotclkout) fm(a24) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip3sr1_7_4 fm(irq1) f_(0, 0) f_(0, 0) f_(0, 0) fm(du_hsync) fm(a25) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip3sr1_11_8 fm(irq2) f_(0, 0) f_(0, 0) f_(0, 0) fm(du_vsync) fm(cs1_n_a26) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip3sr1_15_12 fm(irq3) f_(0, 0) f_(0, 0) f_(0, 0) fm(du_oddf_disp_cde) fm(cs0_n) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip3sr1_19_16 fm(gp1_28) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) fm(d0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip3sr1_23_20 fm(gp1_29) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) fm(d1) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip3sr1_27_24 fm(gp1_30) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) fm(d2) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip3sr1_31_28 f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) + +/* ip0sr2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - f */ +#define ip0sr2_3_0 fm(ipc_clkin) fm(ipc_clken_in) f_(0, 0) f_(0, 0) fm(du_dotclkin) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr2_7_4 fm(ipc_clkout) fm(ipc_clken_out) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr2_11_8 fm(gp2_02) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) fm(d3) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr2_15_12 fm(gp2_03) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) fm(d4) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr2_19_16 fm(gp2_04) f_(0, 0) fm(msiof4_rxd) f_(0, 0) f_(0, 0) fm(d5) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr2_23_20 fm(gp2_05) fm(hsck2) fm(msiof4_txd) fm(sck4) f_(0, 0) fm(d6) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr2_27_24 fm(gp2_06) fm(hcts2_n) fm(msiof4_sck) fm(cts4_n) f_(0, 0) fm(d7) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr2_31_28 fm(gp2_07) fm(hrts2_n) fm(msiof4_sync) fm(rts4_n) f_(0, 0) fm(d8) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +/* ip1sr2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - f */ +#define ip1sr2_3_0 fm(gp2_08) fm(hrx2) fm(msiof4_ss1) fm(rx4) f_(0, 0) fm(d9) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr2_7_4 fm(gp2_09) fm(htx2) fm(msiof4_ss2) fm(tx4) f_(0, 0) fm(d10) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr2_11_8 fm(gp2_10) fm(tclk2_b) fm(msiof5_rxd) f_(0, 0) f_(0, 0) fm(d11) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr2_15_12 fm(gp2_11) fm(tclk3) fm(msiof5_txd) f_(0, 0) f_(0, 0) fm(d12) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr2_19_16 fm(gp2_12) fm(tclk4) fm(msiof5_sck) f_(0, 0) f_(0, 0) fm(d13) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr2_23_20 fm(gp2_13) f_(0, 0) fm(msiof5_sync) f_(0, 0) f_(0, 0) fm(d14) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr2_27_24 fm(gp2_14) fm(irq4) fm(msiof5_ss1) f_(0, 0) f_(0, 0) fm(d15) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr2_31_28 fm(gp2_15) fm(irq5) fm(msiof5_ss2) fm(cpg_cpckout) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +/* ip2sr2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - f */ +#define ip2sr2_3_0 fm(fxr_txda_a) fm(msiof3_ss1) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr2_7_4 fm(rxda_extfxr_a) fm(msiof3_ss2) f_(0, 0) f_(0, 0) f_(0, 0) fm(bs_n) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr2_11_8 fm(fxr_txdb) fm(msiof3_rxd) f_(0, 0) f_(0, 0) f_(0, 0) fm(rd_n) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr2_15_12 fm(rxdb_extfxr) fm(msiof3_txd) f_(0, 0) f_(0, 0) f_(0, 0) fm(we0_n) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr2_19_16 fm(clk_extfxr) fm(msiof3_sck) f_(0, 0) f_(0, 0) f_(0, 0) fm(we1_n) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr2_23_20 fm(tpu0to0) fm(msiof3_sync) f_(0, 0) f_(0, 0) f_(0, 0) fm(rd_wr_n) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr2_27_24 fm(tpu0to1) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) fm(clkout) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr2_31_28 fm(tclk1_a) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) fm(ex_wait0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) + +/* ip0sr3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - f */ +#define ip0sr3_3_0 f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr3_7_4 fm(canfd0_tx) fm(fxr_txda_b) fm(tx1_b) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr3_11_8 fm(canfd0_rx) fm(rxda_extfxr_b) fm(rx1_b) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr3_15_12 f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr3_19_16 f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr3_23_20 fm(canfd2_tx) fm(tpu0to2) fm(pwm0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr3_27_24 fm(canfd2_rx) fm(tpu0to3) fm(pwm1) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr3_31_28 fm(canfd3_tx) f_(0, 0) fm(pwm2) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +/* ip1sr3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - f */ +#define ip1sr3_3_0 fm(canfd3_rx) f_(0, 0) fm(pwm3) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr3_7_4 fm(canfd4_tx) f_(0, 0) fm(pwm4) fm(fxr_clkout1) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr3_11_8 fm(canfd4_rx) f_(0, 0) f_(0, 0) fm(fxr_clkout2) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr3_15_12 fm(canfd5_tx) f_(0, 0) f_(0, 0) fm(fxr_txena_n) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr3_19_16 fm(canfd5_rx) f_(0, 0) f_(0, 0) fm(fxr_txenb_n) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr3_23_20 fm(canfd6_tx) f_(0, 0) f_(0, 0) fm(stpwt_extfxr) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr3_27_24 f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr3_31_28 f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) + +/* ip0sr4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - f */ +#define ip0sr4_3_0 fm(avb0_rx_ctl) fm(avb0_mii_rx_dv) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr4_7_4 fm(avb0_rxc) fm(avb0_mii_rxc) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr4_11_8 fm(avb0_rd0) fm(avb0_mii_rd0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr4_15_12 fm(avb0_rd1) fm(avb0_mii_rd1) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr4_19_16 fm(avb0_rd2) fm(avb0_mii_rd2) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr4_23_20 fm(avb0_rd3) fm(avb0_mii_rd3) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr4_27_24 fm(avb0_tx_ctl) fm(avb0_mii_tx_en) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr4_31_28 fm(avb0_txc) fm(avb0_mii_txc) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +/* ip1sr4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - f */ +#define ip1sr4_3_0 fm(avb0_td0) fm(avb0_mii_td0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr4_7_4 fm(avb0_td1) fm(avb0_mii_td1) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr4_11_8 fm(avb0_td2) fm(avb0_mii_td2) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr4_15_12 fm(avb0_td3) fm(avb0_mii_td3) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr4_19_16 fm(avb0_txcrefclk) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr4_23_20 fm(avb0_mdio) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr4_27_24 fm(avb0_mdc) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr4_31_28 fm(avb0_magic) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +/* ip2sr4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - f */ +#define ip2sr4_3_0 f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr4_7_4 fm(avb0_link) fm(avb0_mii_tx_er) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr4_11_8 fm(avb0_avtp_match) fm(avb0_mii_rx_er) fm(cc5_oscout) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr4_15_12 fm(avb0_avtp_capture) fm(avb0_mii_crs) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr4_19_16 fm(avb0_avtp_pps) fm(avb0_mii_col) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr4_23_20 f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr4_27_24 f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr4_31_28 f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) + +/* ip0sr5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - f */ +#define ip0sr5_3_0 fm(avb1_rx_ctl) fm(avb1_mii_rx_dv) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr5_7_4 fm(avb1_rxc) fm(avb1_mii_rxc) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr5_11_8 fm(avb1_rd0) fm(avb1_mii_rd0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr5_15_12 fm(avb1_rd1) fm(avb1_mii_rd1) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr5_19_16 fm(avb1_rd2) fm(avb1_mii_rd2) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr5_23_20 fm(avb1_rd3) fm(avb1_mii_rd3) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr5_27_24 fm(avb1_tx_ctl) fm(avb1_mii_tx_en) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip0sr5_31_28 fm(avb1_txc) fm(avb1_mii_txc) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +/* ip1sr5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - f */ +#define ip1sr5_3_0 fm(avb1_td0) fm(avb1_mii_td0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr5_7_4 fm(avb1_td1) fm(avb1_mii_td1) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr5_11_8 fm(avb1_td2) fm(avb1_mii_td2) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr5_15_12 fm(avb1_td3) fm(avb1_mii_td3) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr5_19_16 fm(avb1_txcrefclk) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr5_23_20 fm(avb1_mdio) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr5_27_24 fm(avb1_mdc) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip1sr5_31_28 fm(avb1_magic) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +/* ip2sr5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - f */ +#define ip2sr5_3_0 f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr5_7_4 fm(avb1_link) fm(avb1_mii_tx_er) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr5_11_8 fm(avb1_avtp_match) fm(avb1_mii_rx_er) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr5_15_12 fm(avb1_avtp_capture) fm(avb1_mii_crs) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr5_19_16 fm(avb1_avtp_pps) fm(avb1_mii_col) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr5_23_20 f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr5_27_24 f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) +#define ip2sr5_31_28 f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) f_(0, 0) + +#define pinmux_gpsr \ + \ + gpsr1_30 \ + gpsr1_29 \ + gpsr1_28 \ +gpsr0_27 gpsr1_27 \ +gpsr0_26 gpsr1_26 gpsr4_26 \ +gpsr0_25 gpsr1_25 gpsr4_25 \ +gpsr0_24 gpsr1_24 gpsr2_24 gpsr4_24 \ +gpsr0_23 gpsr1_23 gpsr2_23 gpsr4_23 \ +gpsr0_22 gpsr1_22 gpsr2_22 gpsr4_22 \ +gpsr0_21 gpsr1_21 gpsr2_21 gpsr4_21 \ +gpsr0_20 gpsr1_20 gpsr2_20 gpsr4_20 gpsr5_20 gpsr6_20 gpsr7_20 gpsr8_20 gpsr9_20 \ +gpsr0_19 gpsr1_19 gpsr2_19 gpsr4_19 gpsr5_19 gpsr6_19 gpsr7_19 gpsr8_19 gpsr9_19 \ +gpsr0_18 gpsr1_18 gpsr2_18 gpsr4_18 gpsr5_18 gpsr6_18 gpsr7_18 gpsr8_18 gpsr9_18 \ +gpsr0_17 gpsr1_17 gpsr2_17 gpsr4_17 gpsr5_17 gpsr6_17 gpsr7_17 gpsr8_17 gpsr9_17 \ +gpsr0_16 gpsr1_16 gpsr2_16 gpsr3_16 gpsr4_16 gpsr5_16 gpsr6_16 gpsr7_16 gpsr8_16 gpsr9_16 \ +gpsr0_15 gpsr1_15 gpsr2_15 gpsr3_15 gpsr4_15 gpsr5_15 gpsr6_15 gpsr7_15 gpsr8_15 gpsr9_15 \ +gpsr0_14 gpsr1_14 gpsr2_14 gpsr3_14 gpsr4_14 gpsr5_14 gpsr6_14 gpsr7_14 gpsr8_14 gpsr9_14 \ +gpsr0_13 gpsr1_13 gpsr2_13 gpsr3_13 gpsr4_13 gpsr5_13 gpsr6_13 gpsr7_13 gpsr8_13 gpsr9_13 \ +gpsr0_12 gpsr1_12 gpsr2_12 gpsr3_12 gpsr4_12 gpsr5_12 gpsr6_12 gpsr7_12 gpsr8_12 gpsr9_12 \ +gpsr0_11 gpsr1_11 gpsr2_11 gpsr3_11 gpsr4_11 gpsr5_11 gpsr6_11 gpsr7_11 gpsr8_11 gpsr9_11 \ +gpsr0_10 gpsr1_10 gpsr2_10 gpsr3_10 gpsr4_10 gpsr5_10 gpsr6_10 gpsr7_10 gpsr8_10 gpsr9_10 \ +gpsr0_9 gpsr1_9 gpsr2_9 gpsr3_9 gpsr4_9 gpsr5_9 gpsr6_9 gpsr7_9 gpsr8_9 gpsr9_9 \ +gpsr0_8 gpsr1_8 gpsr2_8 gpsr3_8 gpsr4_8 gpsr5_8 gpsr6_8 gpsr7_8 gpsr8_8 gpsr9_8 \ +gpsr0_7 gpsr1_7 gpsr2_7 gpsr3_7 gpsr4_7 gpsr5_7 gpsr6_7 gpsr7_7 gpsr8_7 gpsr9_7 \ +gpsr0_6 gpsr1_6 gpsr2_6 gpsr3_6 gpsr4_6 gpsr5_6 gpsr6_6 gpsr7_6 gpsr8_6 gpsr9_6 \ +gpsr0_5 gpsr1_5 gpsr2_5 gpsr3_5 gpsr4_5 gpsr5_5 gpsr6_5 gpsr7_5 gpsr8_5 gpsr9_5 \ +gpsr0_4 gpsr1_4 gpsr2_4 gpsr3_4 gpsr4_4 gpsr5_4 gpsr6_4 gpsr7_4 gpsr8_4 gpsr9_4 \ +gpsr0_3 gpsr1_3 gpsr2_3 gpsr3_3 gpsr4_3 gpsr5_3 gpsr6_3 gpsr7_3 gpsr8_3 gpsr9_3 \ +gpsr0_2 gpsr1_2 gpsr2_2 gpsr3_2 gpsr4_2 gpsr5_2 gpsr6_2 gpsr7_2 gpsr8_2 gpsr9_2 \ +gpsr0_1 gpsr1_1 gpsr2_1 gpsr3_1 gpsr4_1 gpsr5_1 gpsr6_1 gpsr7_1 gpsr8_1 gpsr9_1 \ +gpsr0_0 gpsr1_0 gpsr2_0 gpsr3_0 gpsr4_0 gpsr5_0 gpsr6_0 gpsr7_0 gpsr8_0 gpsr9_0 + +#define pinmux_ipsr \ +\ +fm(ip0sr1_3_0) ip0sr1_3_0 fm(ip1sr1_3_0) ip1sr1_3_0 fm(ip2sr1_3_0) ip2sr1_3_0 fm(ip3sr1_3_0) ip3sr1_3_0 \ +fm(ip0sr1_7_4) ip0sr1_7_4 fm(ip1sr1_7_4) ip1sr1_7_4 fm(ip2sr1_7_4) ip2sr1_7_4 fm(ip3sr1_7_4) ip3sr1_7_4 \ +fm(ip0sr1_11_8) ip0sr1_11_8 fm(ip1sr1_11_8) ip1sr1_11_8 fm(ip2sr1_11_8) ip2sr1_11_8 fm(ip3sr1_11_8) ip3sr1_11_8 \ +fm(ip0sr1_15_12) ip0sr1_15_12 fm(ip1sr1_15_12) ip1sr1_15_12 fm(ip2sr1_15_12) ip2sr1_15_12 fm(ip3sr1_15_12) ip3sr1_15_12 \ +fm(ip0sr1_19_16) ip0sr1_19_16 fm(ip1sr1_19_16) ip1sr1_19_16 fm(ip2sr1_19_16) ip2sr1_19_16 fm(ip3sr1_19_16) ip3sr1_19_16 \ +fm(ip0sr1_23_20) ip0sr1_23_20 fm(ip1sr1_23_20) ip1sr1_23_20 fm(ip2sr1_23_20) ip2sr1_23_20 fm(ip3sr1_23_20) ip3sr1_23_20 \ +fm(ip0sr1_27_24) ip0sr1_27_24 fm(ip1sr1_27_24) ip1sr1_27_24 fm(ip2sr1_27_24) ip2sr1_27_24 fm(ip3sr1_27_24) ip3sr1_27_24 \ +fm(ip0sr1_31_28) ip0sr1_31_28 fm(ip1sr1_31_28) ip1sr1_31_28 fm(ip2sr1_31_28) ip2sr1_31_28 fm(ip3sr1_31_28) ip3sr1_31_28 \ +\ +fm(ip0sr2_3_0) ip0sr2_3_0 fm(ip1sr2_3_0) ip1sr2_3_0 fm(ip2sr2_3_0) ip2sr2_3_0 \ +fm(ip0sr2_7_4) ip0sr2_7_4 fm(ip1sr2_7_4) ip1sr2_7_4 fm(ip2sr2_7_4) ip2sr2_7_4 \ +fm(ip0sr2_11_8) ip0sr2_11_8 fm(ip1sr2_11_8) ip1sr2_11_8 fm(ip2sr2_11_8) ip2sr2_11_8 \ +fm(ip0sr2_15_12) ip0sr2_15_12 fm(ip1sr2_15_12) ip1sr2_15_12 fm(ip2sr2_15_12) ip2sr2_15_12 \ +fm(ip0sr2_19_16) ip0sr2_19_16 fm(ip1sr2_19_16) ip1sr2_19_16 fm(ip2sr2_19_16) ip2sr2_19_16 \ +fm(ip0sr2_23_20) ip0sr2_23_20 fm(ip1sr2_23_20) ip1sr2_23_20 fm(ip2sr2_23_20) ip2sr2_23_20 \ +fm(ip0sr2_27_24) ip0sr2_27_24 fm(ip1sr2_27_24) ip1sr2_27_24 fm(ip2sr2_27_24) ip2sr2_27_24 \ +fm(ip0sr2_31_28) ip0sr2_31_28 fm(ip1sr2_31_28) ip1sr2_31_28 fm(ip2sr2_31_28) ip2sr2_31_28 \ +\ +fm(ip0sr3_3_0) ip0sr3_3_0 fm(ip1sr3_3_0) ip1sr3_3_0 \ +fm(ip0sr3_7_4) ip0sr3_7_4 fm(ip1sr3_7_4) ip1sr3_7_4 \ +fm(ip0sr3_11_8) ip0sr3_11_8 fm(ip1sr3_11_8) ip1sr3_11_8 \ +fm(ip0sr3_15_12) ip0sr3_15_12 fm(ip1sr3_15_12) ip1sr3_15_12 \ +fm(ip0sr3_19_16) ip0sr3_19_16 fm(ip1sr3_19_16) ip1sr3_19_16 \ +fm(ip0sr3_23_20) ip0sr3_23_20 fm(ip1sr3_23_20) ip1sr3_23_20 \ +fm(ip0sr3_27_24) ip0sr3_27_24 fm(ip1sr3_27_24) ip1sr3_27_24 \ +fm(ip0sr3_31_28) ip0sr3_31_28 fm(ip1sr3_31_28) ip1sr3_31_28 \ +\ +fm(ip0sr4_3_0) ip0sr4_3_0 fm(ip1sr4_3_0) ip1sr4_3_0 fm(ip2sr4_3_0) ip2sr4_3_0 \ +fm(ip0sr4_7_4) ip0sr4_7_4 fm(ip1sr4_7_4) ip1sr4_7_4 fm(ip2sr4_7_4) ip2sr4_7_4 \ +fm(ip0sr4_11_8) ip0sr4_11_8 fm(ip1sr4_11_8) ip1sr4_11_8 fm(ip2sr4_11_8) ip2sr4_11_8 \ +fm(ip0sr4_15_12) ip0sr4_15_12 fm(ip1sr4_15_12) ip1sr4_15_12 fm(ip2sr4_15_12) ip2sr4_15_12 \ +fm(ip0sr4_19_16) ip0sr4_19_16 fm(ip1sr4_19_16) ip1sr4_19_16 fm(ip2sr4_19_16) ip2sr4_19_16 \ +fm(ip0sr4_23_20) ip0sr4_23_20 fm(ip1sr4_23_20) ip1sr4_23_20 fm(ip2sr4_23_20) ip2sr4_23_20 \ +fm(ip0sr4_27_24) ip0sr4_27_24 fm(ip1sr4_27_24) ip1sr4_27_24 fm(ip2sr4_27_24) ip2sr4_27_24 \ +fm(ip0sr4_31_28) ip0sr4_31_28 fm(ip1sr4_31_28) ip1sr4_31_28 fm(ip2sr4_31_28) ip2sr4_31_28 \ +\ +fm(ip0sr5_3_0) ip0sr5_3_0 fm(ip1sr5_3_0) ip1sr5_3_0 fm(ip2sr5_3_0) ip2sr5_3_0 \ +fm(ip0sr5_7_4) ip0sr5_7_4 fm(ip1sr5_7_4) ip1sr5_7_4 fm(ip2sr5_7_4) ip2sr5_7_4 \ +fm(ip0sr5_11_8) ip0sr5_11_8 fm(ip1sr5_11_8) ip1sr5_11_8 fm(ip2sr5_11_8) ip2sr5_11_8 \ +fm(ip0sr5_15_12) ip0sr5_15_12 fm(ip1sr5_15_12) ip1sr5_15_12 fm(ip2sr5_15_12) ip2sr5_15_12 \ +fm(ip0sr5_19_16) ip0sr5_19_16 fm(ip1sr5_19_16) ip1sr5_19_16 fm(ip2sr5_19_16) ip2sr5_19_16 \ +fm(ip0sr5_23_20) ip0sr5_23_20 fm(ip1sr5_23_20) ip1sr5_23_20 fm(ip2sr5_23_20) ip2sr5_23_20 \ +fm(ip0sr5_27_24) ip0sr5_27_24 fm(ip1sr5_27_24) ip1sr5_27_24 fm(ip2sr5_27_24) ip2sr5_27_24 \ +fm(ip0sr5_31_28) ip0sr5_31_28 fm(ip1sr5_31_28) ip1sr5_31_28 fm(ip2sr5_31_28) ip2sr5_31_28 + +/* mod_sel2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ +#define mod_sel2_14_15 fm(sel_i2c6_0) f_(0, 0) f_(0, 0) fm(sel_i2c6_3) +#define mod_sel2_12_13 fm(sel_i2c5_0) f_(0, 0) f_(0, 0) fm(sel_i2c5_3) +#define mod_sel2_10_11 fm(sel_i2c4_0) f_(0, 0) f_(0, 0) fm(sel_i2c4_3) +#define mod_sel2_8_9 fm(sel_i2c3_0) f_(0, 0) f_(0, 0) fm(sel_i2c3_3) +#define mod_sel2_6_7 fm(sel_i2c2_0) f_(0, 0) f_(0, 0) fm(sel_i2c2_3) +#define mod_sel2_4_5 fm(sel_i2c1_0) f_(0, 0) f_(0, 0) fm(sel_i2c1_3) +#define mod_sel2_2_3 fm(sel_i2c0_0) f_(0, 0) f_(0, 0) fm(sel_i2c0_3) + +#define pinmux_mod_sels \ +\ +mod_sel2_14_15 \ +mod_sel2_12_13 \ +mod_sel2_10_11 \ +mod_sel2_8_9 \ +mod_sel2_6_7 \ +mod_sel2_4_5 \ +mod_sel2_2_3 + +#define pinmux_phys \ + fm(scl0) fm(sda0) fm(scl1) fm(sda1) fm(scl2) fm(sda2) fm(scl3) fm(sda3) \ + fm(scl4) fm(sda4) fm(scl5) fm(sda5) fm(scl6) fm(sda6) + +enum { + pinmux_reserved = 0, + + pinmux_data_begin, + gp_all(data), + pinmux_data_end, + +#define f_(x, y) +#define fm(x) fn_##x, + pinmux_function_begin, + gp_all(fn), + pinmux_gpsr + pinmux_ipsr + pinmux_mod_sels + pinmux_function_end, +#undef f_ +#undef fm + +#define f_(x, y) +#define fm(x) x##_mark, + pinmux_mark_begin, + pinmux_gpsr + pinmux_ipsr + pinmux_mod_sels + pinmux_phys + pinmux_mark_end, +#undef f_ +#undef fm +}; + +static const u16 pinmux_data[] = { + pinmux_data_gp_all(), + + pinmux_single(mmc_d7), + pinmux_single(mmc_d6), + pinmux_single(mmc_d5), + pinmux_single(mmc_d4), + pinmux_single(mmc_sd_clk), + pinmux_single(mmc_sd_d3), + pinmux_single(mmc_sd_d2), + pinmux_single(mmc_sd_d1), + pinmux_single(mmc_sd_d0), + pinmux_single(mmc_sd_cmd), + pinmux_single(mmc_ds), + + pinmux_single(sd_cd), + pinmux_single(sd_wp), + + pinmux_single(rpc_int_n), + pinmux_single(rpc_wp_n), + pinmux_single(rpc_reset_n), + + pinmux_single(qspi1_ssl), + pinmux_single(qspi1_io3), + pinmux_single(qspi1_io2), + pinmux_single(qspi1_miso_io1), + pinmux_single(qspi1_mosi_io0), + pinmux_single(qspi1_spclk), + pinmux_single(qspi0_ssl), + pinmux_single(qspi0_io3), + pinmux_single(qspi0_io2), + pinmux_single(qspi0_miso_io1), + pinmux_single(qspi0_mosi_io0), + pinmux_single(qspi0_spclk), + + pinmux_single(tclk2_a), + + pinmux_single(canfd7_rx), + pinmux_single(canfd7_tx), + pinmux_single(canfd6_rx), + pinmux_single(canfd1_rx), + pinmux_single(canfd1_tx), + pinmux_single(can_clk), + + pinmux_single(avs1), + pinmux_single(avs0), + + pinmux_single(pcie3_clkreq_n), + pinmux_single(pcie2_clkreq_n), + pinmux_single(pcie1_clkreq_n), + pinmux_single(pcie0_clkreq_n), + + pinmux_single(avb0_phy_int), + pinmux_single(avb0_magic), + pinmux_single(avb0_mdc), + pinmux_single(avb0_mdio), + pinmux_single(avb0_txcrefclk), + + pinmux_single(avb1_phy_int), + pinmux_single(avb1_magic), + pinmux_single(avb1_mdc), + pinmux_single(avb1_mdio), + pinmux_single(avb1_txcrefclk), + + pinmux_single(avb2_avtp_pps), + pinmux_single(avb2_avtp_capture), + pinmux_single(avb2_avtp_match), + pinmux_single(avb2_link), + pinmux_single(avb2_phy_int), + pinmux_single(avb2_magic), + pinmux_single(avb2_mdc), + pinmux_single(avb2_mdio), + pinmux_single(avb2_txcrefclk), + pinmux_single(avb2_td3), + pinmux_single(avb2_td2), + pinmux_single(avb2_td1), + pinmux_single(avb2_td0), + pinmux_single(avb2_txc), + pinmux_single(avb2_tx_ctl), + pinmux_single(avb2_rd3), + pinmux_single(avb2_rd2), + pinmux_single(avb2_rd1), + pinmux_single(avb2_rd0), + pinmux_single(avb2_rxc), + pinmux_single(avb2_rx_ctl), + + pinmux_single(avb3_avtp_pps), + pinmux_single(avb3_avtp_capture), + pinmux_single(avb3_avtp_match), + pinmux_single(avb3_link), + pinmux_single(avb3_phy_int), + pinmux_single(avb3_magic), + pinmux_single(avb3_mdc), + pinmux_single(avb3_mdio), + pinmux_single(avb3_txcrefclk), + pinmux_single(avb3_td3), + pinmux_single(avb3_td2), + pinmux_single(avb3_td1), + pinmux_single(avb3_td0), + pinmux_single(avb3_txc), + pinmux_single(avb3_tx_ctl), + pinmux_single(avb3_rd3), + pinmux_single(avb3_rd2), + pinmux_single(avb3_rd1), + pinmux_single(avb3_rd0), + pinmux_single(avb3_rxc), + pinmux_single(avb3_rx_ctl), + + pinmux_single(avb4_avtp_pps), + pinmux_single(avb4_avtp_capture), + pinmux_single(avb4_avtp_match), + pinmux_single(avb4_link), + pinmux_single(avb4_phy_int), + pinmux_single(avb4_magic), + pinmux_single(avb4_mdc), + pinmux_single(avb4_mdio), + pinmux_single(avb4_txcrefclk), + pinmux_single(avb4_td3), + pinmux_single(avb4_td2), + pinmux_single(avb4_td1), + pinmux_single(avb4_td0), + pinmux_single(avb4_txc), + pinmux_single(avb4_tx_ctl), + pinmux_single(avb4_rd3), + pinmux_single(avb4_rd2), + pinmux_single(avb4_rd1), + pinmux_single(avb4_rd0), + pinmux_single(avb4_rxc), + pinmux_single(avb4_rx_ctl), + + pinmux_single(avb5_avtp_pps), + pinmux_single(avb5_avtp_capture), + pinmux_single(avb5_avtp_match), + pinmux_single(avb5_link), + pinmux_single(avb5_phy_int), + pinmux_single(avb5_magic), + pinmux_single(avb5_mdc), + pinmux_single(avb5_mdio), + pinmux_single(avb5_txcrefclk), + pinmux_single(avb5_td3), + pinmux_single(avb5_td2), + pinmux_single(avb5_td1), + pinmux_single(avb5_td0), + pinmux_single(avb5_txc), + pinmux_single(avb5_tx_ctl), + pinmux_single(avb5_rd3), + pinmux_single(avb5_rd2), + pinmux_single(avb5_rd1), + pinmux_single(avb5_rd0), + pinmux_single(avb5_rxc), + pinmux_single(avb5_rx_ctl), + + /* ip0sr1 */ + pinmux_ipsr_gpsr(ip0sr1_3_0, scif_clk), + pinmux_ipsr_gpsr(ip0sr1_3_0, a0), + + pinmux_ipsr_gpsr(ip0sr1_7_4, hrx0), + pinmux_ipsr_gpsr(ip0sr1_7_4, rx0), + pinmux_ipsr_gpsr(ip0sr1_7_4, a1), + + pinmux_ipsr_gpsr(ip0sr1_11_8, hsck0), + pinmux_ipsr_gpsr(ip0sr1_11_8, sck0), + pinmux_ipsr_gpsr(ip0sr1_11_8, a2), + + pinmux_ipsr_gpsr(ip0sr1_15_12, hrts0_n), + pinmux_ipsr_gpsr(ip0sr1_15_12, rts0_n), + pinmux_ipsr_gpsr(ip0sr1_15_12, a3), + + pinmux_ipsr_gpsr(ip0sr1_19_16, hcts0_n), + pinmux_ipsr_gpsr(ip0sr1_19_16, cts0_n), + pinmux_ipsr_gpsr(ip0sr1_19_16, a4), + + pinmux_ipsr_gpsr(ip0sr1_23_20, htx0), + pinmux_ipsr_gpsr(ip0sr1_23_20, tx0), + pinmux_ipsr_gpsr(ip0sr1_23_20, a5), + + pinmux_ipsr_gpsr(ip0sr1_27_24, msiof0_rxd), + pinmux_ipsr_gpsr(ip0sr1_27_24, du_dr2), + pinmux_ipsr_gpsr(ip0sr1_27_24, a6), + + pinmux_ipsr_gpsr(ip0sr1_31_28, msiof0_txd), + pinmux_ipsr_gpsr(ip0sr1_31_28, du_dr3), + pinmux_ipsr_gpsr(ip0sr1_31_28, a7), + + /* ip1sr1 */ + pinmux_ipsr_gpsr(ip1sr1_3_0, msiof0_sck), + pinmux_ipsr_gpsr(ip1sr1_3_0, du_dr4), + pinmux_ipsr_gpsr(ip1sr1_3_0, a8), + + pinmux_ipsr_gpsr(ip1sr1_7_4, msiof0_sync), + pinmux_ipsr_gpsr(ip1sr1_7_4, du_dr5), + pinmux_ipsr_gpsr(ip1sr1_7_4, a9), + + pinmux_ipsr_gpsr(ip1sr1_11_8, msiof0_ss1), + pinmux_ipsr_gpsr(ip1sr1_11_8, du_dr6), + pinmux_ipsr_gpsr(ip1sr1_11_8, a10), + + pinmux_ipsr_gpsr(ip1sr1_15_12, msiof0_ss2), + pinmux_ipsr_gpsr(ip1sr1_15_12, du_dr7), + pinmux_ipsr_gpsr(ip1sr1_15_12, a11), + + pinmux_ipsr_gpsr(ip1sr1_19_16, msiof1_rxd), + pinmux_ipsr_gpsr(ip1sr1_19_16, du_dg2), + pinmux_ipsr_gpsr(ip1sr1_19_16, a12), + + pinmux_ipsr_gpsr(ip1sr1_23_20, msiof1_txd), + pinmux_ipsr_gpsr(ip1sr1_23_20, hrx3), + pinmux_ipsr_gpsr(ip1sr1_23_20, sck3), + pinmux_ipsr_gpsr(ip1sr1_23_20, du_dg3), + pinmux_ipsr_gpsr(ip1sr1_23_20, a13), + + pinmux_ipsr_gpsr(ip1sr1_27_24, msiof1_sck), + pinmux_ipsr_gpsr(ip1sr1_27_24, hsck3), + pinmux_ipsr_gpsr(ip1sr1_27_24, cts3_n), + pinmux_ipsr_gpsr(ip1sr1_27_24, du_dg4), + pinmux_ipsr_gpsr(ip1sr1_27_24, a14), + + pinmux_ipsr_gpsr(ip1sr1_31_28, msiof1_sync), + pinmux_ipsr_gpsr(ip1sr1_31_28, hrts3_n), + pinmux_ipsr_gpsr(ip1sr1_31_28, rts3_n), + pinmux_ipsr_gpsr(ip1sr1_31_28, du_dg5), + pinmux_ipsr_gpsr(ip1sr1_31_28, a15), + + /* ip2sr1 */ + pinmux_ipsr_gpsr(ip2sr1_3_0, msiof1_ss1), + pinmux_ipsr_gpsr(ip2sr1_3_0, hcts3_n), + pinmux_ipsr_gpsr(ip2sr1_3_0, rx3), + pinmux_ipsr_gpsr(ip2sr1_3_0, du_dg6), + pinmux_ipsr_gpsr(ip2sr1_3_0, a16), + + pinmux_ipsr_gpsr(ip2sr1_7_4, msiof1_ss2), + pinmux_ipsr_gpsr(ip2sr1_7_4, htx3), + pinmux_ipsr_gpsr(ip2sr1_7_4, tx3), + pinmux_ipsr_gpsr(ip2sr1_7_4, du_dg7), + pinmux_ipsr_gpsr(ip2sr1_7_4, a17), + + pinmux_ipsr_gpsr(ip2sr1_11_8, msiof2_rxd), + pinmux_ipsr_gpsr(ip2sr1_11_8, hsck1), + pinmux_ipsr_gpsr(ip2sr1_11_8, sck1), + pinmux_ipsr_gpsr(ip2sr1_11_8, du_db2), + pinmux_ipsr_gpsr(ip2sr1_11_8, a18), + + pinmux_ipsr_gpsr(ip2sr1_15_12, msiof2_txd), + pinmux_ipsr_gpsr(ip2sr1_15_12, hcts1_n), + pinmux_ipsr_gpsr(ip2sr1_15_12, cts1_n), + pinmux_ipsr_gpsr(ip2sr1_15_12, du_db3), + pinmux_ipsr_gpsr(ip2sr1_15_12, a19), + + pinmux_ipsr_gpsr(ip2sr1_19_16, msiof2_sck), + pinmux_ipsr_gpsr(ip2sr1_19_16, hrts1_n), + pinmux_ipsr_gpsr(ip2sr1_19_16, rts1_n), + pinmux_ipsr_gpsr(ip2sr1_19_16, du_db4), + pinmux_ipsr_gpsr(ip2sr1_19_16, a20), + + pinmux_ipsr_gpsr(ip2sr1_23_20, msiof2_sync), + pinmux_ipsr_gpsr(ip2sr1_23_20, hrx1), + pinmux_ipsr_gpsr(ip2sr1_23_20, rx1_a), + pinmux_ipsr_gpsr(ip2sr1_23_20, du_db5), + pinmux_ipsr_gpsr(ip2sr1_23_20, a21), + + pinmux_ipsr_gpsr(ip2sr1_27_24, msiof2_ss1), + pinmux_ipsr_gpsr(ip2sr1_27_24, htx1), + pinmux_ipsr_gpsr(ip2sr1_27_24, tx1_a), + pinmux_ipsr_gpsr(ip2sr1_27_24, du_db6), + pinmux_ipsr_gpsr(ip2sr1_27_24, a22), + + pinmux_ipsr_gpsr(ip2sr1_31_28, msiof2_ss2), + pinmux_ipsr_gpsr(ip2sr1_31_28, tclk1_b), + pinmux_ipsr_gpsr(ip2sr1_31_28, du_db7), + pinmux_ipsr_gpsr(ip2sr1_31_28, a23), + + /* ip3sr1 */ + pinmux_ipsr_gpsr(ip3sr1_3_0, irq0), + pinmux_ipsr_gpsr(ip3sr1_3_0, du_dotclkout), + pinmux_ipsr_gpsr(ip3sr1_3_0, a24), + + pinmux_ipsr_gpsr(ip3sr1_7_4, irq1), + pinmux_ipsr_gpsr(ip3sr1_7_4, du_hsync), + pinmux_ipsr_gpsr(ip3sr1_7_4, a25), + + pinmux_ipsr_gpsr(ip3sr1_11_8, irq2), + pinmux_ipsr_gpsr(ip3sr1_11_8, du_vsync), + pinmux_ipsr_gpsr(ip3sr1_11_8, cs1_n_a26), + + pinmux_ipsr_gpsr(ip3sr1_15_12, irq3), + pinmux_ipsr_gpsr(ip3sr1_15_12, du_oddf_disp_cde), + pinmux_ipsr_gpsr(ip3sr1_15_12, cs0_n), + + pinmux_ipsr_gpsr(ip3sr1_19_16, gp1_28), + pinmux_ipsr_gpsr(ip3sr1_19_16, d0), + + pinmux_ipsr_gpsr(ip3sr1_23_20, gp1_29), + pinmux_ipsr_gpsr(ip3sr1_23_20, d1), + + pinmux_ipsr_gpsr(ip3sr1_27_24, gp1_30), + pinmux_ipsr_gpsr(ip3sr1_27_24, d2), + + /* ip0sr2 */ + pinmux_ipsr_gpsr(ip0sr2_3_0, ipc_clkin), + pinmux_ipsr_gpsr(ip0sr2_3_0, ipc_clken_in), + pinmux_ipsr_gpsr(ip0sr2_3_0, du_dotclkin), + + pinmux_ipsr_gpsr(ip0sr2_7_4, ipc_clkout), + pinmux_ipsr_gpsr(ip0sr2_7_4, ipc_clken_out), + + /* gp2_02 = scl0 */ + pinmux_ipsr_msel(ip0sr2_11_8, gp2_02, sel_i2c0_0), + pinmux_ipsr_msel(ip0sr2_11_8, d3, sel_i2c0_0), + pinmux_ipsr_phys(ip0sr2_11_8, scl0, sel_i2c0_3), + + /* gp2_03 = sda0 */ + pinmux_ipsr_msel(ip0sr2_15_12, gp2_03, sel_i2c0_0), + pinmux_ipsr_msel(ip0sr2_15_12, d4, sel_i2c0_0), + pinmux_ipsr_phys(ip0sr2_15_12, sda0, sel_i2c0_3), + + /* gp2_04 = scl1 */ + pinmux_ipsr_msel(ip0sr2_19_16, gp2_04, sel_i2c1_0), + pinmux_ipsr_msel(ip0sr2_19_16, msiof4_rxd, sel_i2c1_0), + pinmux_ipsr_msel(ip0sr2_19_16, d5, sel_i2c1_0), + pinmux_ipsr_phys(ip0sr2_19_16, scl1, sel_i2c1_3), + + /* gp2_05 = sda1 */ + pinmux_ipsr_msel(ip0sr2_23_20, gp2_05, sel_i2c1_0), + pinmux_ipsr_msel(ip0sr2_23_20, hsck2, sel_i2c1_0), + pinmux_ipsr_msel(ip0sr2_23_20, msiof4_txd, sel_i2c1_0), + pinmux_ipsr_msel(ip0sr2_23_20, sck4, sel_i2c1_0), + pinmux_ipsr_msel(ip0sr2_23_20, d6, sel_i2c1_0), + pinmux_ipsr_phys(ip0sr2_23_20, sda1, sel_i2c1_3), + + /* gp2_06 = scl2 */ + pinmux_ipsr_msel(ip0sr2_27_24, gp2_06, sel_i2c2_0), + pinmux_ipsr_msel(ip0sr2_27_24, hcts2_n, sel_i2c2_0), + pinmux_ipsr_msel(ip0sr2_27_24, msiof4_sck, sel_i2c2_0), + pinmux_ipsr_msel(ip0sr2_27_24, cts4_n, sel_i2c2_0), + pinmux_ipsr_msel(ip0sr2_27_24, d7, sel_i2c2_0), + pinmux_ipsr_phys(ip0sr2_27_24, scl2, sel_i2c2_3), + + /* gp2_07 = sda2 */ + pinmux_ipsr_msel(ip0sr2_31_28, gp2_07, sel_i2c2_0), + pinmux_ipsr_msel(ip0sr2_31_28, hrts2_n, sel_i2c2_0), + pinmux_ipsr_msel(ip0sr2_31_28, msiof4_sync, sel_i2c2_0), + pinmux_ipsr_msel(ip0sr2_31_28, rts4_n, sel_i2c2_0), + pinmux_ipsr_msel(ip0sr2_31_28, d8, sel_i2c2_0), + pinmux_ipsr_phys(ip0sr2_31_28, sda2, sel_i2c2_3), + + /* gp2_08 = scl3 */ + pinmux_ipsr_msel(ip1sr2_3_0, gp2_08, sel_i2c3_0), + pinmux_ipsr_msel(ip1sr2_3_0, hrx2, sel_i2c3_0), + pinmux_ipsr_msel(ip1sr2_3_0, msiof4_ss1, sel_i2c3_0), + pinmux_ipsr_msel(ip1sr2_3_0, rx4, sel_i2c3_0), + pinmux_ipsr_msel(ip1sr2_3_0, d9, sel_i2c3_0), + pinmux_ipsr_phys(ip1sr2_3_0, scl3, sel_i2c3_3), + + /* gp2_09 = sda3 */ + pinmux_ipsr_msel(ip1sr2_7_4, gp2_09, sel_i2c3_0), + pinmux_ipsr_msel(ip1sr2_7_4, htx2, sel_i2c3_0), + pinmux_ipsr_msel(ip1sr2_7_4, msiof4_ss2, sel_i2c3_0), + pinmux_ipsr_msel(ip1sr2_7_4, tx4, sel_i2c3_0), + pinmux_ipsr_msel(ip1sr2_7_4, d10, sel_i2c3_0), + pinmux_ipsr_phys(ip1sr2_7_4, sda3, sel_i2c3_3), + + /* gp2_10 = scl4 */ + pinmux_ipsr_msel(ip1sr2_11_8, gp2_10, sel_i2c4_0), + pinmux_ipsr_msel(ip1sr2_11_8, tclk2_b, sel_i2c4_0), + pinmux_ipsr_msel(ip1sr2_11_8, msiof5_rxd, sel_i2c4_0), + pinmux_ipsr_msel(ip1sr2_11_8, d11, sel_i2c4_0), + pinmux_ipsr_phys(ip1sr2_11_8, scl4, sel_i2c4_3), + + /* gp2_11 = sda4 */ + pinmux_ipsr_msel(ip1sr2_15_12, gp2_11, sel_i2c4_0), + pinmux_ipsr_msel(ip1sr2_15_12, tclk3, sel_i2c4_0), + pinmux_ipsr_msel(ip1sr2_15_12, msiof5_txd, sel_i2c4_0), + pinmux_ipsr_msel(ip1sr2_15_12, d12, sel_i2c4_0), + pinmux_ipsr_phys(ip1sr2_15_12, sda4, sel_i2c4_3), + + /* gp2_12 = scl5 */ + pinmux_ipsr_msel(ip1sr2_19_16, gp2_12, sel_i2c5_0), + pinmux_ipsr_msel(ip1sr2_19_16, tclk4, sel_i2c5_0), + pinmux_ipsr_msel(ip1sr2_19_16, msiof5_sck, sel_i2c5_0), + pinmux_ipsr_msel(ip1sr2_19_16, d13, sel_i2c5_0), + pinmux_ipsr_phys(ip1sr2_19_16, scl5, sel_i2c5_3), + + /* gp2_13 = sda5 */ + pinmux_ipsr_msel(ip1sr2_23_20, gp2_13, sel_i2c5_0), + pinmux_ipsr_msel(ip1sr2_23_20, msiof5_sync, sel_i2c5_0), + pinmux_ipsr_msel(ip1sr2_23_20, d14, sel_i2c5_0), + pinmux_ipsr_phys(ip1sr2_23_20, sda5, sel_i2c5_3), + + /* gp2_14 = scl6 */ + pinmux_ipsr_msel(ip1sr2_27_24, gp2_14, sel_i2c6_0), + pinmux_ipsr_msel(ip1sr2_27_24, irq4, sel_i2c6_0), + pinmux_ipsr_msel(ip1sr2_27_24, msiof5_ss1, sel_i2c6_0), + pinmux_ipsr_msel(ip1sr2_27_24, d15, sel_i2c6_0), + pinmux_ipsr_phys(ip1sr2_27_24, scl6, sel_i2c6_3), + + /* gp2_15 = sda6 */ + pinmux_ipsr_msel(ip1sr2_31_28, gp2_15, sel_i2c6_0), + pinmux_ipsr_msel(ip1sr2_31_28, irq5, sel_i2c6_0), + pinmux_ipsr_msel(ip1sr2_31_28, msiof5_ss2, sel_i2c6_0), + pinmux_ipsr_msel(ip1sr2_31_28, cpg_cpckout, sel_i2c6_0), + pinmux_ipsr_phys(ip1sr2_31_28, sda6, sel_i2c6_3), + + /* ip2sr2 */ + pinmux_ipsr_gpsr(ip2sr2_3_0, fxr_txda_a), + pinmux_ipsr_gpsr(ip2sr2_3_0, msiof3_ss1), + + pinmux_ipsr_gpsr(ip2sr2_7_4, rxda_extfxr_a), + pinmux_ipsr_gpsr(ip2sr2_7_4, msiof3_ss2), + pinmux_ipsr_gpsr(ip2sr2_7_4, bs_n), + + pinmux_ipsr_gpsr(ip2sr2_11_8, fxr_txdb), + pinmux_ipsr_gpsr(ip2sr2_11_8, msiof3_rxd), + pinmux_ipsr_gpsr(ip2sr2_11_8, rd_n), + + pinmux_ipsr_gpsr(ip2sr2_15_12, rxdb_extfxr), + pinmux_ipsr_gpsr(ip2sr2_15_12, msiof3_txd), + pinmux_ipsr_gpsr(ip2sr2_15_12, we0_n), + + pinmux_ipsr_gpsr(ip2sr2_19_16, clk_extfxr), + pinmux_ipsr_gpsr(ip2sr2_19_16, msiof3_sck), + pinmux_ipsr_gpsr(ip2sr2_19_16, we1_n), + + pinmux_ipsr_gpsr(ip2sr2_23_20, tpu0to0), + pinmux_ipsr_gpsr(ip2sr2_23_20, msiof3_sync), + pinmux_ipsr_gpsr(ip2sr2_23_20, rd_wr_n), + + pinmux_ipsr_gpsr(ip2sr2_27_24, tpu0to1), + pinmux_ipsr_gpsr(ip2sr2_27_24, clkout), + + pinmux_ipsr_gpsr(ip2sr2_31_28, tclk1_a), + pinmux_ipsr_gpsr(ip2sr2_31_28, ex_wait0), + + /* ip0sr3 */ + pinmux_ipsr_gpsr(ip0sr3_7_4, canfd0_tx), + pinmux_ipsr_gpsr(ip0sr3_7_4, fxr_txda_b), + pinmux_ipsr_gpsr(ip0sr3_7_4, tx1_b), + + pinmux_ipsr_gpsr(ip0sr3_11_8, canfd0_rx), + pinmux_ipsr_gpsr(ip0sr3_11_8, rxda_extfxr_b), + pinmux_ipsr_gpsr(ip0sr3_11_8, rx1_b), + + pinmux_ipsr_gpsr(ip0sr3_23_20, canfd2_tx), + pinmux_ipsr_gpsr(ip0sr3_23_20, tpu0to2), + pinmux_ipsr_gpsr(ip0sr3_23_20, pwm0), + + pinmux_ipsr_gpsr(ip0sr3_27_24, canfd2_rx), + pinmux_ipsr_gpsr(ip0sr3_27_24, tpu0to3), + pinmux_ipsr_gpsr(ip0sr3_27_24, pwm1), + + pinmux_ipsr_gpsr(ip0sr3_31_28, canfd3_tx), + pinmux_ipsr_gpsr(ip0sr3_31_28, pwm2), + + /* ip1sr3 */ + pinmux_ipsr_gpsr(ip1sr3_3_0, canfd3_rx), + pinmux_ipsr_gpsr(ip1sr3_3_0, pwm3), + + pinmux_ipsr_gpsr(ip1sr3_7_4, canfd4_tx), + pinmux_ipsr_gpsr(ip1sr3_7_4, pwm4), + pinmux_ipsr_gpsr(ip1sr3_7_4, fxr_clkout1), + + pinmux_ipsr_gpsr(ip1sr3_11_8, canfd4_rx), + pinmux_ipsr_gpsr(ip1sr3_11_8, fxr_clkout2), + + pinmux_ipsr_gpsr(ip1sr3_15_12, canfd5_tx), + pinmux_ipsr_gpsr(ip1sr3_15_12, fxr_txena_n), + + pinmux_ipsr_gpsr(ip1sr3_19_16, canfd5_rx), + pinmux_ipsr_gpsr(ip1sr3_19_16, fxr_txenb_n), + + pinmux_ipsr_gpsr(ip1sr3_23_20, canfd6_tx), + pinmux_ipsr_gpsr(ip1sr3_23_20, stpwt_extfxr), + + /* ip0sr4 */ + pinmux_ipsr_gpsr(ip0sr4_3_0, avb0_rx_ctl), + pinmux_ipsr_gpsr(ip0sr4_3_0, avb0_mii_rx_dv), + + pinmux_ipsr_gpsr(ip0sr4_7_4, avb0_rxc), + pinmux_ipsr_gpsr(ip0sr4_7_4, avb0_mii_rxc), + + pinmux_ipsr_gpsr(ip0sr4_11_8, avb0_rd0), + pinmux_ipsr_gpsr(ip0sr4_11_8, avb0_mii_rd0), + + pinmux_ipsr_gpsr(ip0sr4_15_12, avb0_rd1), + pinmux_ipsr_gpsr(ip0sr4_15_12, avb0_mii_rd1), + + pinmux_ipsr_gpsr(ip0sr4_19_16, avb0_rd2), + pinmux_ipsr_gpsr(ip0sr4_19_16, avb0_mii_rd2), + + pinmux_ipsr_gpsr(ip0sr4_23_20, avb0_rd3), + pinmux_ipsr_gpsr(ip0sr4_23_20, avb0_mii_rd3), + + pinmux_ipsr_gpsr(ip0sr4_27_24, avb0_tx_ctl), + pinmux_ipsr_gpsr(ip0sr4_27_24, avb0_mii_tx_en), + + pinmux_ipsr_gpsr(ip0sr4_31_28, avb0_txc), + pinmux_ipsr_gpsr(ip0sr4_31_28, avb0_mii_txc), + + /* ip1sr4 */ + pinmux_ipsr_gpsr(ip1sr4_3_0, avb0_td0), + pinmux_ipsr_gpsr(ip1sr4_3_0, avb0_mii_td0), + + pinmux_ipsr_gpsr(ip1sr4_7_4, avb0_td1), + pinmux_ipsr_gpsr(ip1sr4_7_4, avb0_mii_td1), + + pinmux_ipsr_gpsr(ip1sr4_11_8, avb0_td2), + pinmux_ipsr_gpsr(ip1sr4_11_8, avb0_mii_td2), + + pinmux_ipsr_gpsr(ip1sr4_15_12, avb0_td3), + pinmux_ipsr_gpsr(ip1sr4_15_12, avb0_mii_td3), + + pinmux_ipsr_gpsr(ip1sr4_19_16, avb0_txcrefclk), + + pinmux_ipsr_gpsr(ip1sr4_23_20, avb0_mdio), + + pinmux_ipsr_gpsr(ip1sr4_27_24, avb0_mdc), + + pinmux_ipsr_gpsr(ip1sr4_31_28, avb0_magic), + + /* ip2sr4 */ + pinmux_ipsr_gpsr(ip2sr4_7_4, avb0_link), + pinmux_ipsr_gpsr(ip2sr4_7_4, avb0_mii_tx_er), + + pinmux_ipsr_gpsr(ip2sr4_11_8, avb0_avtp_match), + pinmux_ipsr_gpsr(ip2sr4_11_8, avb0_mii_rx_er), + pinmux_ipsr_gpsr(ip2sr4_11_8, cc5_oscout), + + pinmux_ipsr_gpsr(ip2sr4_15_12, avb0_avtp_capture), + pinmux_ipsr_gpsr(ip2sr4_15_12, avb0_mii_crs), + + pinmux_ipsr_gpsr(ip2sr4_19_16, avb0_avtp_pps), + pinmux_ipsr_gpsr(ip2sr4_19_16, avb0_mii_col), + + /* ip0sr5 */ + pinmux_ipsr_gpsr(ip0sr5_3_0, avb1_rx_ctl), + pinmux_ipsr_gpsr(ip0sr5_3_0, avb1_mii_rx_dv), + + pinmux_ipsr_gpsr(ip0sr5_7_4, avb1_rxc), + pinmux_ipsr_gpsr(ip0sr5_7_4, avb1_mii_rxc), + + pinmux_ipsr_gpsr(ip0sr5_11_8, avb1_rd0), + pinmux_ipsr_gpsr(ip0sr5_11_8, avb1_mii_rd0), + + pinmux_ipsr_gpsr(ip0sr5_15_12, avb1_rd1), + pinmux_ipsr_gpsr(ip0sr5_15_12, avb1_mii_rd1), + + pinmux_ipsr_gpsr(ip0sr5_19_16, avb1_rd2), + pinmux_ipsr_gpsr(ip0sr5_19_16, avb1_mii_rd2), + + pinmux_ipsr_gpsr(ip0sr5_23_20, avb1_rd3), + pinmux_ipsr_gpsr(ip0sr5_23_20, avb1_mii_rd3), + + pinmux_ipsr_gpsr(ip0sr5_27_24, avb1_tx_ctl), + pinmux_ipsr_gpsr(ip0sr5_27_24, avb1_mii_tx_en), + + pinmux_ipsr_gpsr(ip0sr5_31_28, avb1_txc), + pinmux_ipsr_gpsr(ip0sr5_31_28, avb1_mii_txc), + + /* ip1sr5 */ + pinmux_ipsr_gpsr(ip1sr5_3_0, avb1_td0), + pinmux_ipsr_gpsr(ip1sr5_3_0, avb1_mii_td0), + + pinmux_ipsr_gpsr(ip1sr5_7_4, avb1_td1), + pinmux_ipsr_gpsr(ip1sr5_7_4, avb1_mii_td1), + + pinmux_ipsr_gpsr(ip1sr5_11_8, avb1_td2), + pinmux_ipsr_gpsr(ip1sr5_11_8, avb1_mii_td2), + + pinmux_ipsr_gpsr(ip1sr5_15_12, avb1_td3), + pinmux_ipsr_gpsr(ip1sr5_15_12, avb1_mii_td3), + + pinmux_ipsr_gpsr(ip1sr5_19_16, avb1_txcrefclk), + + pinmux_ipsr_gpsr(ip1sr5_23_20, avb1_mdio), + + pinmux_ipsr_gpsr(ip1sr5_27_24, avb1_mdc), + + pinmux_ipsr_gpsr(ip1sr5_31_28, avb1_magic), + + /* ip2sr5 */ + pinmux_ipsr_gpsr(ip2sr5_7_4, avb1_link), + pinmux_ipsr_gpsr(ip2sr5_7_4, avb1_mii_tx_er), + + pinmux_ipsr_gpsr(ip2sr5_11_8, avb1_avtp_match), + pinmux_ipsr_gpsr(ip2sr5_11_8, avb1_mii_rx_er), + + pinmux_ipsr_gpsr(ip2sr5_15_12, avb1_avtp_capture), + pinmux_ipsr_gpsr(ip2sr5_15_12, avb1_mii_crs), + + pinmux_ipsr_gpsr(ip2sr5_19_16, avb1_avtp_pps), + pinmux_ipsr_gpsr(ip2sr5_19_16, avb1_mii_col), +}; + +/* + * pins not associated with a gpio port. + */ +enum { + gp_assign_last(), + nogp_all(), +}; + +static const struct sh_pfc_pin pinmux_pins[] = { + pinmux_gpio_gp_all(), +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { +}; + +static const struct sh_pfc_function pinmux_functions[] = { +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { +#define f_(x, y) fn_##y +#define fm(x) fn_##x + { pinmux_cfg_reg("gpsr0", 0xe6058040, 32, 1, group( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + gp_0_27_fn, gpsr0_27, + gp_0_26_fn, gpsr0_26, + gp_0_25_fn, gpsr0_25, + gp_0_24_fn, gpsr0_24, + gp_0_23_fn, gpsr0_23, + gp_0_22_fn, gpsr0_22, + gp_0_21_fn, gpsr0_21, + gp_0_20_fn, gpsr0_20, + gp_0_19_fn, gpsr0_19, + gp_0_18_fn, gpsr0_18, + gp_0_17_fn, gpsr0_17, + gp_0_16_fn, gpsr0_16, + gp_0_15_fn, gpsr0_15, + gp_0_14_fn, gpsr0_14, + gp_0_13_fn, gpsr0_13, + gp_0_12_fn, gpsr0_12, + gp_0_11_fn, gpsr0_11, + gp_0_10_fn, gpsr0_10, + gp_0_9_fn, gpsr0_9, + gp_0_8_fn, gpsr0_8, + gp_0_7_fn, gpsr0_7, + gp_0_6_fn, gpsr0_6, + gp_0_5_fn, gpsr0_5, + gp_0_4_fn, gpsr0_4, + gp_0_3_fn, gpsr0_3, + gp_0_2_fn, gpsr0_2, + gp_0_1_fn, gpsr0_1, + gp_0_0_fn, gpsr0_0, )) + }, + { pinmux_cfg_reg("gpsr1", 0xe6050040, 32, 1, group( + 0, 0, + gp_1_30_fn, gpsr1_30, + gp_1_29_fn, gpsr1_29, + gp_1_28_fn, gpsr1_28, + gp_1_27_fn, gpsr1_27, + gp_1_26_fn, gpsr1_26, + gp_1_25_fn, gpsr1_25, + gp_1_24_fn, gpsr1_24, + gp_1_23_fn, gpsr1_23, + gp_1_22_fn, gpsr1_22, + gp_1_21_fn, gpsr1_21, + gp_1_20_fn, gpsr1_20, + gp_1_19_fn, gpsr1_19, + gp_1_18_fn, gpsr1_18, + gp_1_17_fn, gpsr1_17, + gp_1_16_fn, gpsr1_16, + gp_1_15_fn, gpsr1_15, + gp_1_14_fn, gpsr1_14, + gp_1_13_fn, gpsr1_13, + gp_1_12_fn, gpsr1_12, + gp_1_11_fn, gpsr1_11, + gp_1_10_fn, gpsr1_10, + gp_1_9_fn, gpsr1_9, + gp_1_8_fn, gpsr1_8, + gp_1_7_fn, gpsr1_7, + gp_1_6_fn, gpsr1_6, + gp_1_5_fn, gpsr1_5, + gp_1_4_fn, gpsr1_4, + gp_1_3_fn, gpsr1_3, + gp_1_2_fn, gpsr1_2, + gp_1_1_fn, gpsr1_1, + gp_1_0_fn, gpsr1_0, )) + }, + { pinmux_cfg_reg("gpsr2", 0xe6050840, 32, 1, group( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + gp_2_24_fn, gpsr2_24, + gp_2_23_fn, gpsr2_23, + gp_2_22_fn, gpsr2_22, + gp_2_21_fn, gpsr2_21, + gp_2_20_fn, gpsr2_20, + gp_2_19_fn, gpsr2_19, + gp_2_18_fn, gpsr2_18, + gp_2_17_fn, gpsr2_17, + gp_2_16_fn, gpsr2_16, + gp_2_15_fn, gpsr2_15, + gp_2_14_fn, gpsr2_14, + gp_2_13_fn, gpsr2_13, + gp_2_12_fn, gpsr2_12, + gp_2_11_fn, gpsr2_11, + gp_2_10_fn, gpsr2_10, + gp_2_9_fn, gpsr2_9, + gp_2_8_fn, gpsr2_8, + gp_2_7_fn, gpsr2_7, + gp_2_6_fn, gpsr2_6, + gp_2_5_fn, gpsr2_5, + gp_2_4_fn, gpsr2_4, + gp_2_3_fn, gpsr2_3, + gp_2_2_fn, gpsr2_2, + gp_2_1_fn, gpsr2_1, + gp_2_0_fn, gpsr2_0, )) + }, + { pinmux_cfg_reg("gpsr3", 0xe6058840, 32, 1, group( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + gp_3_16_fn, gpsr3_16, + gp_3_15_fn, gpsr3_15, + gp_3_14_fn, gpsr3_14, + gp_3_13_fn, gpsr3_13, + gp_3_12_fn, gpsr3_12, + gp_3_11_fn, gpsr3_11, + gp_3_10_fn, gpsr3_10, + gp_3_9_fn, gpsr3_9, + gp_3_8_fn, gpsr3_8, + gp_3_7_fn, gpsr3_7, + gp_3_6_fn, gpsr3_6, + gp_3_5_fn, gpsr3_5, + gp_3_4_fn, gpsr3_4, + gp_3_3_fn, gpsr3_3, + gp_3_2_fn, gpsr3_2, + gp_3_1_fn, gpsr3_1, + gp_3_0_fn, gpsr3_0, )) + }, + { pinmux_cfg_reg("gpsr4", 0xe6060040, 32, 1, group( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + gp_4_26_fn, gpsr4_26, + gp_4_25_fn, gpsr4_25, + gp_4_24_fn, gpsr4_24, + gp_4_23_fn, gpsr4_23, + gp_4_22_fn, gpsr4_22, + gp_4_21_fn, gpsr4_21, + gp_4_20_fn, gpsr4_20, + gp_4_19_fn, gpsr4_19, + gp_4_18_fn, gpsr4_18, + gp_4_17_fn, gpsr4_17, + gp_4_16_fn, gpsr4_16, + gp_4_15_fn, gpsr4_15, + gp_4_14_fn, gpsr4_14, + gp_4_13_fn, gpsr4_13, + gp_4_12_fn, gpsr4_12, + gp_4_11_fn, gpsr4_11, + gp_4_10_fn, gpsr4_10, + gp_4_9_fn, gpsr4_9, + gp_4_8_fn, gpsr4_8, + gp_4_7_fn, gpsr4_7, + gp_4_6_fn, gpsr4_6, + gp_4_5_fn, gpsr4_5, + gp_4_4_fn, gpsr4_4, + gp_4_3_fn, gpsr4_3, + gp_4_2_fn, gpsr4_2, + gp_4_1_fn, gpsr4_1, + gp_4_0_fn, gpsr4_0, )) + }, + { pinmux_cfg_reg("gpsr5", 0xe6060840, 32, 1, group( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + gp_5_20_fn, gpsr5_20, + gp_5_19_fn, gpsr5_19, + gp_5_18_fn, gpsr5_18, + gp_5_17_fn, gpsr5_17, + gp_5_16_fn, gpsr5_16, + gp_5_15_fn, gpsr5_15, + gp_5_14_fn, gpsr5_14, + gp_5_13_fn, gpsr5_13, + gp_5_12_fn, gpsr5_12, + gp_5_11_fn, gpsr5_11, + gp_5_10_fn, gpsr5_10, + gp_5_9_fn, gpsr5_9, + gp_5_8_fn, gpsr5_8, + gp_5_7_fn, gpsr5_7, + gp_5_6_fn, gpsr5_6, + gp_5_5_fn, gpsr5_5, + gp_5_4_fn, gpsr5_4, + gp_5_3_fn, gpsr5_3, + gp_5_2_fn, gpsr5_2, + gp_5_1_fn, gpsr5_1, + gp_5_0_fn, gpsr5_0, )) + }, + { pinmux_cfg_reg("gpsr6", 0xe6068040, 32, 1, group( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + gp_6_20_fn, gpsr6_20, + gp_6_19_fn, gpsr6_19, + gp_6_18_fn, gpsr6_18, + gp_6_17_fn, gpsr6_17, + gp_6_16_fn, gpsr6_16, + gp_6_15_fn, gpsr6_15, + gp_6_14_fn, gpsr6_14, + gp_6_13_fn, gpsr6_13, + gp_6_12_fn, gpsr6_12, + gp_6_11_fn, gpsr6_11, + gp_6_10_fn, gpsr6_10, + gp_6_9_fn, gpsr6_9, + gp_6_8_fn, gpsr6_8, + gp_6_7_fn, gpsr6_7, + gp_6_6_fn, gpsr6_6, + gp_6_5_fn, gpsr6_5, + gp_6_4_fn, gpsr6_4, + gp_6_3_fn, gpsr6_3, + gp_6_2_fn, gpsr6_2, + gp_6_1_fn, gpsr6_1, + gp_6_0_fn, gpsr6_0, )) + }, + { pinmux_cfg_reg("gpsr7", 0xe6068840, 32, 1, group( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + gp_7_20_fn, gpsr7_20, + gp_7_19_fn, gpsr7_19, + gp_7_18_fn, gpsr7_18, + gp_7_17_fn, gpsr7_17, + gp_7_16_fn, gpsr7_16, + gp_7_15_fn, gpsr7_15, + gp_7_14_fn, gpsr7_14, + gp_7_13_fn, gpsr7_13, + gp_7_12_fn, gpsr7_12, + gp_7_11_fn, gpsr7_11, + gp_7_10_fn, gpsr7_10, + gp_7_9_fn, gpsr7_9, + gp_7_8_fn, gpsr7_8, + gp_7_7_fn, gpsr7_7, + gp_7_6_fn, gpsr7_6, + gp_7_5_fn, gpsr7_5, + gp_7_4_fn, gpsr7_4, + gp_7_3_fn, gpsr7_3, + gp_7_2_fn, gpsr7_2, + gp_7_1_fn, gpsr7_1, + gp_7_0_fn, gpsr7_0, )) + }, + { pinmux_cfg_reg("gpsr8", 0xe6069040, 32, 1, group( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + gp_8_20_fn, gpsr8_20, + gp_8_19_fn, gpsr8_19, + gp_8_18_fn, gpsr8_18, + gp_8_17_fn, gpsr8_17, + gp_8_16_fn, gpsr8_16, + gp_8_15_fn, gpsr8_15, + gp_8_14_fn, gpsr8_14, + gp_8_13_fn, gpsr8_13, + gp_8_12_fn, gpsr8_12, + gp_8_11_fn, gpsr8_11, + gp_8_10_fn, gpsr8_10, + gp_8_9_fn, gpsr8_9, + gp_8_8_fn, gpsr8_8, + gp_8_7_fn, gpsr8_7, + gp_8_6_fn, gpsr8_6, + gp_8_5_fn, gpsr8_5, + gp_8_4_fn, gpsr8_4, + gp_8_3_fn, gpsr8_3, + gp_8_2_fn, gpsr8_2, + gp_8_1_fn, gpsr8_1, + gp_8_0_fn, gpsr8_0, )) + }, + { pinmux_cfg_reg("gpsr9", 0xe6069840, 32, 1, group( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + gp_9_20_fn, gpsr9_20, + gp_9_19_fn, gpsr9_19, + gp_9_18_fn, gpsr9_18, + gp_9_17_fn, gpsr9_17, + gp_9_16_fn, gpsr9_16, + gp_9_15_fn, gpsr9_15, + gp_9_14_fn, gpsr9_14, + gp_9_13_fn, gpsr9_13, + gp_9_12_fn, gpsr9_12, + gp_9_11_fn, gpsr9_11, + gp_9_10_fn, gpsr9_10, + gp_9_9_fn, gpsr9_9, + gp_9_8_fn, gpsr9_8, + gp_9_7_fn, gpsr9_7, + gp_9_6_fn, gpsr9_6, + gp_9_5_fn, gpsr9_5, + gp_9_4_fn, gpsr9_4, + gp_9_3_fn, gpsr9_3, + gp_9_2_fn, gpsr9_2, + gp_9_1_fn, gpsr9_1, + gp_9_0_fn, gpsr9_0, )) + }, +#undef f_ +#undef fm + +#define f_(x, y) x, +#define fm(x) fn_##x, + { pinmux_cfg_reg("ip0sr1", 0xe6050060, 32, 4, group( + ip0sr1_31_28 + ip0sr1_27_24 + ip0sr1_23_20 + ip0sr1_19_16 + ip0sr1_15_12 + ip0sr1_11_8 + ip0sr1_7_4 + ip0sr1_3_0)) + }, + { pinmux_cfg_reg("ip1sr1", 0xe6050064, 32, 4, group( + ip1sr1_31_28 + ip1sr1_27_24 + ip1sr1_23_20 + ip1sr1_19_16 + ip1sr1_15_12 + ip1sr1_11_8 + ip1sr1_7_4 + ip1sr1_3_0)) + }, + { pinmux_cfg_reg("ip2sr1", 0xe6050068, 32, 4, group( + ip2sr1_31_28 + ip2sr1_27_24 + ip2sr1_23_20 + ip2sr1_19_16 + ip2sr1_15_12 + ip2sr1_11_8 + ip2sr1_7_4 + ip2sr1_3_0)) + }, + { pinmux_cfg_reg("ip3sr1", 0xe605006c, 32, 4, group( + ip3sr1_31_28 + ip3sr1_27_24 + ip3sr1_23_20 + ip3sr1_19_16 + ip3sr1_15_12 + ip3sr1_11_8 + ip3sr1_7_4 + ip3sr1_3_0)) + }, + { pinmux_cfg_reg("ip0sr2", 0xe6050860, 32, 4, group( + ip0sr2_31_28 + ip0sr2_27_24 + ip0sr2_23_20 + ip0sr2_19_16 + ip0sr2_15_12 + ip0sr2_11_8 + ip0sr2_7_4 + ip0sr2_3_0)) + }, + { pinmux_cfg_reg("ip1sr2", 0xe6050864, 32, 4, group( + ip1sr2_31_28 + ip1sr2_27_24 + ip1sr2_23_20 + ip1sr2_19_16 + ip1sr2_15_12 + ip1sr2_11_8 + ip1sr2_7_4 + ip1sr2_3_0)) + }, + { pinmux_cfg_reg("ip2sr2", 0xe6050868, 32, 4, group( + ip2sr2_31_28 + ip2sr2_27_24 + ip2sr2_23_20 + ip2sr2_19_16 + ip2sr2_15_12 + ip2sr2_11_8 + ip2sr2_7_4 + ip2sr2_3_0)) + }, + { pinmux_cfg_reg("ip0sr3", 0xe6058860, 32, 4, group( + ip0sr3_31_28 + ip0sr3_27_24 + ip0sr3_23_20 + ip0sr3_19_16 + ip0sr3_15_12 + ip0sr3_11_8 + ip0sr3_7_4 + ip0sr3_3_0)) + }, + { pinmux_cfg_reg("ip1sr3", 0xe6058864, 32, 4, group( + ip1sr3_31_28 + ip1sr3_27_24 + ip1sr3_23_20 + ip1sr3_19_16 + ip1sr3_15_12 + ip1sr3_11_8 + ip1sr3_7_4 + ip1sr3_3_0)) + }, + { pinmux_cfg_reg("ip0sr4", 0xe6060060, 32, 4, group( + ip0sr4_31_28 + ip0sr4_27_24 + ip0sr4_23_20 + ip0sr4_19_16 + ip0sr4_15_12 + ip0sr4_11_8 + ip0sr4_7_4 + ip0sr4_3_0)) + }, + { pinmux_cfg_reg("ip1sr4", 0xe6060064, 32, 4, group( + ip1sr4_31_28 + ip1sr4_27_24 + ip1sr4_23_20 + ip1sr4_19_16 + ip1sr4_15_12 + ip1sr4_11_8 + ip1sr4_7_4 + ip1sr4_3_0)) + }, + { pinmux_cfg_reg("ip2sr4", 0xe6060068, 32, 4, group( + ip2sr4_31_28 + ip2sr4_27_24 + ip2sr4_23_20 + ip2sr4_19_16 + ip2sr4_15_12 + ip2sr4_11_8 + ip2sr4_7_4 + ip2sr4_3_0)) + }, + { pinmux_cfg_reg("ip0sr5", 0xe6060860, 32, 4, group( + ip0sr5_31_28 + ip0sr5_27_24 + ip0sr5_23_20 + ip0sr5_19_16 + ip0sr5_15_12 + ip0sr5_11_8 + ip0sr5_7_4 + ip0sr5_3_0)) + }, + { pinmux_cfg_reg("ip1sr5", 0xe6060864, 32, 4, group( + ip1sr5_31_28 + ip1sr5_27_24 + ip1sr5_23_20 + ip1sr5_19_16 + ip1sr5_15_12 + ip1sr5_11_8 + ip1sr5_7_4 + ip1sr5_3_0)) + }, + { pinmux_cfg_reg("ip2sr5", 0xe6060868, 32, 4, group( + ip2sr5_31_28 + ip2sr5_27_24 + ip2sr5_23_20 + ip2sr5_19_16 + ip2sr5_15_12 + ip2sr5_11_8 + ip2sr5_7_4 + ip2sr5_3_0)) + }, +#undef f_ +#undef fm + +#define f_(x, y) x, +#define fm(x) fn_##x, + { pinmux_cfg_reg_var("mod_sel2", 0xe6050900, 32, + group(4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 1, 1), + group( + /* reserved 31, 30, 29, 28 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* reserved 27, 26, 25, 24 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* reserved 23, 22, 21, 20 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* reserved 19, 18, 17, 16 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + mod_sel2_14_15 + mod_sel2_12_13 + mod_sel2_10_11 + mod_sel2_8_9 + mod_sel2_6_7 + mod_sel2_4_5 + mod_sel2_2_3 + 0, 0, + 0, 0, )) + }, + { }, +}; + +static const struct pinmux_drive_reg pinmux_drive_regs[] = { + { pinmux_drive_reg("drv0ctrl0", 0xe6058080) { + { rcar_gp_pin(0, 7), 28, 2 }, /* qspi1_mosi_io0 */ + { rcar_gp_pin(0, 6), 24, 2 }, /* qspi1_spclk */ + { rcar_gp_pin(0, 5), 20, 2 }, /* qspi0_ssl */ + { rcar_gp_pin(0, 4), 16, 2 }, /* qspi0_io3 */ + { rcar_gp_pin(0, 3), 12, 2 }, /* qspi0_io2 */ + { rcar_gp_pin(0, 2), 8, 2 }, /* qspi0_miso_io1 */ + { rcar_gp_pin(0, 1), 4, 2 }, /* qspi0_mosi_io0 */ + { rcar_gp_pin(0, 0), 0, 2 }, /* qspi0_spclk */ + } }, + { pinmux_drive_reg("drv1ctrl0", 0xe6058084) { + { rcar_gp_pin(0, 15), 28, 3 }, /* sd_wp */ + { rcar_gp_pin(0, 14), 24, 2 }, /* rpc_int_n */ + { rcar_gp_pin(0, 13), 20, 2 }, /* rpc_wp_n */ + { rcar_gp_pin(0, 12), 16, 2 }, /* rpc_reset_n */ + { rcar_gp_pin(0, 11), 12, 2 }, /* qspi1_ssl */ + { rcar_gp_pin(0, 10), 8, 2 }, /* qspi1_io3 */ + { rcar_gp_pin(0, 9), 4, 2 }, /* qspi1_io2 */ + { rcar_gp_pin(0, 8), 0, 2 }, /* qspi1_miso_io1 */ + } }, + { pinmux_drive_reg("drv2ctrl0", 0xe6058088) { + { rcar_gp_pin(0, 23), 28, 3 }, /* mmc_sd_clk */ + { rcar_gp_pin(0, 22), 24, 3 }, /* mmc_sd_d3 */ + { rcar_gp_pin(0, 21), 20, 3 }, /* mmc_sd_d2 */ + { rcar_gp_pin(0, 20), 16, 3 }, /* mmc_sd_d1 */ + { rcar_gp_pin(0, 19), 12, 3 }, /* mmc_sd_d0 */ + { rcar_gp_pin(0, 18), 8, 3 }, /* mmc_sd_cmd */ + { rcar_gp_pin(0, 17), 4, 3 }, /* mmc_ds */ + { rcar_gp_pin(0, 16), 0, 3 }, /* sd_cd */ + } }, + { pinmux_drive_reg("drv3ctrl0", 0xe605808c) { + { rcar_gp_pin(0, 27), 12, 3 }, /* mmc_d7 */ + { rcar_gp_pin(0, 26), 8, 3 }, /* mmc_d6 */ + { rcar_gp_pin(0, 25), 4, 3 }, /* mmc_d5 */ + { rcar_gp_pin(0, 24), 0, 3 }, /* mmc_d4 */ + } }, + { pinmux_drive_reg("drv0ctrl1", 0xe6050080) { + { rcar_gp_pin(1, 7), 28, 3 }, /* msiof0_txd */ + { rcar_gp_pin(1, 6), 24, 3 }, /* msiof0_rxd */ + { rcar_gp_pin(1, 5), 20, 3 }, /* htx0 */ + { rcar_gp_pin(1, 4), 16, 3 }, /* hcts0_n */ + { rcar_gp_pin(1, 3), 12, 3 }, /* hrts0_n */ + { rcar_gp_pin(1, 2), 8, 3 }, /* hsck0 */ + { rcar_gp_pin(1, 1), 4, 3 }, /* hrx0 */ + { rcar_gp_pin(1, 0), 0, 3 }, /* scif_clk */ + } }, + { pinmux_drive_reg("drv1ctrl1", 0xe6050084) { + { rcar_gp_pin(1, 15), 28, 3 }, /* msiof1_sync */ + { rcar_gp_pin(1, 14), 24, 3 }, /* msiof1_sck */ + { rcar_gp_pin(1, 13), 20, 3 }, /* msiof1_txd */ + { rcar_gp_pin(1, 12), 16, 3 }, /* msiof1_rxd */ + { rcar_gp_pin(1, 11), 12, 3 }, /* msiof0_ss2 */ + { rcar_gp_pin(1, 10), 8, 3 }, /* msiof0_ss1 */ + { rcar_gp_pin(1, 9), 4, 3 }, /* msiof0_sync */ + { rcar_gp_pin(1, 8), 0, 3 }, /* msiof0_sck */ + } }, + { pinmux_drive_reg("drv2ctrl1", 0xe6050088) { + { rcar_gp_pin(1, 23), 28, 3 }, /* msiof2_ss2 */ + { rcar_gp_pin(1, 22), 24, 3 }, /* msiof2_ss1 */ + { rcar_gp_pin(1, 21), 20, 3 }, /* msiof2_sync */ + { rcar_gp_pin(1, 20), 16, 3 }, /* msiof2_sck */ + { rcar_gp_pin(1, 19), 12, 3 }, /* msiof2_txd */ + { rcar_gp_pin(1, 18), 8, 3 }, /* msiof2_rxd */ + { rcar_gp_pin(1, 17), 4, 3 }, /* msiof1_ss2 */ + { rcar_gp_pin(1, 16), 0, 3 }, /* msiof1_ss1 */ + } }, + { pinmux_drive_reg("drv3ctrl1", 0xe605008c) { + { rcar_gp_pin(1, 30), 24, 3 }, /* gp1_30 */ + { rcar_gp_pin(1, 29), 20, 3 }, /* gp1_29 */ + { rcar_gp_pin(1, 28), 16, 3 }, /* gp1_28 */ + { rcar_gp_pin(1, 27), 12, 3 }, /* irq3 */ + { rcar_gp_pin(1, 26), 8, 3 }, /* irq2 */ + { rcar_gp_pin(1, 25), 4, 3 }, /* irq1 */ + { rcar_gp_pin(1, 24), 0, 3 }, /* irq0 */ + } }, + { pinmux_drive_reg("drv0ctrl2", 0xe6050880) { + { rcar_gp_pin(2, 7), 28, 3 }, /* gp2_07 */ + { rcar_gp_pin(2, 6), 24, 3 }, /* gp2_06 */ + { rcar_gp_pin(2, 5), 20, 3 }, /* gp2_05 */ + { rcar_gp_pin(2, 4), 16, 3 }, /* gp2_04 */ + { rcar_gp_pin(2, 3), 12, 3 }, /* gp2_03 */ + { rcar_gp_pin(2, 2), 8, 3 }, /* gp2_02 */ + { rcar_gp_pin(2, 1), 4, 2 }, /* ipc_clkout */ + { rcar_gp_pin(2, 0), 0, 2 }, /* ipc_clkin */ + } }, + { pinmux_drive_reg("drv1ctrl2", 0xe6050884) { + { rcar_gp_pin(2, 15), 28, 3 }, /* gp2_15 */ + { rcar_gp_pin(2, 14), 24, 3 }, /* gp2_14 */ + { rcar_gp_pin(2, 13), 20, 3 }, /* gp2_13 */ + { rcar_gp_pin(2, 12), 16, 3 }, /* gp2_12 */ + { rcar_gp_pin(2, 11), 12, 3 }, /* gp2_11 */ + { rcar_gp_pin(2, 10), 8, 3 }, /* gp2_10 */ + { rcar_gp_pin(2, 9), 4, 3 }, /* gp2_9 */ + { rcar_gp_pin(2, 8), 0, 3 }, /* gp2_8 */ + } }, + { pinmux_drive_reg("drv2ctrl2", 0xe6050888) { + { rcar_gp_pin(2, 23), 28, 3 }, /* tclk1_a */ + { rcar_gp_pin(2, 22), 24, 3 }, /* tpu0to1 */ + { rcar_gp_pin(2, 21), 20, 3 }, /* tpu0to0 */ + { rcar_gp_pin(2, 20), 16, 3 }, /* clk_extfxr */ + { rcar_gp_pin(2, 19), 12, 3 }, /* rxdb_extfxr */ + { rcar_gp_pin(2, 18), 8, 3 }, /* fxr_txdb */ + { rcar_gp_pin(2, 17), 4, 3 }, /* rxda_extfxr_a */ + { rcar_gp_pin(2, 16), 0, 3 }, /* fxr_txda_a */ + } }, + { pinmux_drive_reg("drv3ctrl2", 0xe605088c) { + { rcar_gp_pin(2, 24), 0, 3 }, /* tclk2_a */ + } }, + { pinmux_drive_reg("drv0ctrl3", 0xe6058880) { + { rcar_gp_pin(3, 7), 28, 3 }, /* canfd3_tx */ + { rcar_gp_pin(3, 6), 24, 3 }, /* canfd2_rx */ + { rcar_gp_pin(3, 5), 20, 3 }, /* canfd2_tx */ + { rcar_gp_pin(3, 4), 16, 3 }, /* canfd1_rx */ + { rcar_gp_pin(3, 3), 12, 3 }, /* canfd1_tx */ + { rcar_gp_pin(3, 2), 8, 3 }, /* canfd0_rx */ + { rcar_gp_pin(3, 1), 4, 2 }, /* canfd0_tx */ + { rcar_gp_pin(3, 0), 0, 2 }, /* can_clk */ + } }, + { pinmux_drive_reg("drv1ctrl3", 0xe6058884) { + { rcar_gp_pin(3, 15), 28, 3 }, /* canfd7_tx */ + { rcar_gp_pin(3, 14), 24, 3 }, /* canfd6_rx */ + { rcar_gp_pin(3, 13), 20, 3 }, /* canfd6_tx */ + { rcar_gp_pin(3, 12), 16, 3 }, /* canfd5_rx */ + { rcar_gp_pin(3, 11), 12, 3 }, /* canfd5_tx */ + { rcar_gp_pin(3, 10), 8, 3 }, /* canfd4_rx */ + { rcar_gp_pin(3, 9), 4, 3 }, /* canfd4_tx*/ + { rcar_gp_pin(3, 8), 0, 3 }, /* canfd3_rx */ + } }, + { pinmux_drive_reg("drv2ctrl3", 0xe6058888) { + { rcar_gp_pin(3, 16), 0, 3 }, /* canfd7_rx */ + } }, + { pinmux_drive_reg("drv0ctrl4", 0xe6060080) { + { rcar_gp_pin(4, 7), 28, 3 }, /* avb0_txc */ + { rcar_gp_pin(4, 6), 24, 3 }, /* avb0_tx_ctl */ + { rcar_gp_pin(4, 5), 20, 3 }, /* avb0_rd3 */ + { rcar_gp_pin(4, 4), 16, 3 }, /* avb0_rd2 */ + { rcar_gp_pin(4, 3), 12, 3 }, /* avb0_rd1 */ + { rcar_gp_pin(4, 2), 8, 3 }, /* avb0_rd0 */ + { rcar_gp_pin(4, 1), 4, 3 }, /* avb0_rxc */ + { rcar_gp_pin(4, 0), 0, 3 }, /* avb0_rx_ctl */ + } }, + { pinmux_drive_reg("drv1ctrl4", 0xe6060084) { + { rcar_gp_pin(4, 15), 28, 3 }, /* avb0_magic */ + { rcar_gp_pin(4, 14), 24, 3 }, /* avb0_mdc */ + { rcar_gp_pin(4, 13), 20, 3 }, /* avb0_mdio */ + { rcar_gp_pin(4, 12), 16, 3 }, /* avb0_txcrefclk */ + { rcar_gp_pin(4, 11), 12, 3 }, /* avb0_td3 */ + { rcar_gp_pin(4, 10), 8, 3 }, /* avb0_td2 */ + { rcar_gp_pin(4, 9), 4, 3 }, /* avb0_td1*/ + { rcar_gp_pin(4, 8), 0, 3 }, /* avb0_td0 */ + } }, + { pinmux_drive_reg("drv2ctrl4", 0xe6060088) { + { rcar_gp_pin(4, 23), 28, 3 }, /* pcie2_clkreq_n */ + { rcar_gp_pin(4, 22), 24, 3 }, /* pcie1_clkreq_n */ + { rcar_gp_pin(4, 21), 20, 3 }, /* pcie0_clkreq_n */ + { rcar_gp_pin(4, 20), 16, 3 }, /* avb0_avtp_pps */ + { rcar_gp_pin(4, 19), 12, 3 }, /* avb0_avtp_capture */ + { rcar_gp_pin(4, 18), 8, 3 }, /* avb0_avtp_match */ + { rcar_gp_pin(4, 17), 4, 3 }, /* avb0_link */ + { rcar_gp_pin(4, 16), 0, 3 }, /* avb0_phy_int */ + } }, + { pinmux_drive_reg("drv3ctrl4", 0xe606008c) { + { rcar_gp_pin(4, 26), 8, 3 }, /* avs1 */ + { rcar_gp_pin(4, 25), 4, 3 }, /* avs0 */ + { rcar_gp_pin(4, 24), 0, 3 }, /* pcie3_clkreq_n */ + } }, + { pinmux_drive_reg("drv0ctrl5", 0xe6060880) { + { rcar_gp_pin(5, 7), 28, 3 }, /* avb1_txc */ + { rcar_gp_pin(5, 6), 24, 3 }, /* avb1_tx_ctl */ + { rcar_gp_pin(5, 5), 20, 3 }, /* avb1_rd3 */ + { rcar_gp_pin(5, 4), 16, 3 }, /* avb1_rd2 */ + { rcar_gp_pin(5, 3), 12, 3 }, /* avb1_rd1 */ + { rcar_gp_pin(5, 2), 8, 3 }, /* avb1_rd0 */ + { rcar_gp_pin(5, 1), 4, 3 }, /* avb1_rxc */ + { rcar_gp_pin(5, 0), 0, 3 }, /* avb1_rx_ctl */ + } }, + { pinmux_drive_reg("drv1ctrl5", 0xe6060884) { + { rcar_gp_pin(5, 15), 28, 3 }, /* avb1_magic */ + { rcar_gp_pin(5, 14), 24, 3 }, /* avb1_mdc */ + { rcar_gp_pin(5, 13), 20, 3 }, /* avb1_mdio */ + { rcar_gp_pin(5, 12), 16, 3 }, /* avb1_txcrefclk */ + { rcar_gp_pin(5, 11), 12, 3 }, /* avb1_td3 */ + { rcar_gp_pin(5, 10), 8, 3 }, /* avb1_td2 */ + { rcar_gp_pin(5, 9), 4, 3 }, /* avb1_td1*/ + { rcar_gp_pin(5, 8), 0, 3 }, /* avb1_td0 */ + } }, + { pinmux_drive_reg("drv2ctrl5", 0xe6060888) { + { rcar_gp_pin(5, 20), 16, 3 }, /* avb1_avtp_pps */ + { rcar_gp_pin(5, 19), 12, 3 }, /* avb1_avtp_capture */ + { rcar_gp_pin(5, 18), 8, 3 }, /* avb1_avtp_match */ + { rcar_gp_pin(5, 17), 4, 3 }, /* avb1_link */ + { rcar_gp_pin(5, 16), 0, 3 }, /* avb1_phy_int */ + } }, + { pinmux_drive_reg("drv0ctrl6", 0xe6068080) { + { rcar_gp_pin(6, 7), 28, 3 }, /* avb2_txc */ + { rcar_gp_pin(6, 6), 24, 3 }, /* avb2_tx_ctl */ + { rcar_gp_pin(6, 5), 20, 3 }, /* avb2_rd3 */ + { rcar_gp_pin(6, 4), 16, 3 }, /* avb2_rd2 */ + { rcar_gp_pin(6, 3), 12, 3 }, /* avb2_rd1 */ + { rcar_gp_pin(6, 2), 8, 3 }, /* avb2_rd0 */ + { rcar_gp_pin(6, 1), 4, 3 }, /* avb2_rxc */ + { rcar_gp_pin(6, 0), 0, 3 }, /* avb2_rx_ctl */ + } }, + { pinmux_drive_reg("drv1ctrl6", 0xe6068084) { + { rcar_gp_pin(6, 15), 28, 3 }, /* avb2_magic */ + { rcar_gp_pin(6, 14), 24, 3 }, /* avb2_mdc */ + { rcar_gp_pin(6, 13), 20, 3 }, /* avb2_mdio */ + { rcar_gp_pin(6, 12), 16, 3 }, /* avb2_txcrefclk */ + { rcar_gp_pin(6, 11), 12, 3 }, /* avb2_td3 */ + { rcar_gp_pin(6, 10), 8, 3 }, /* avb2_td2 */ + { rcar_gp_pin(6, 9), 4, 3 }, /* avb2_td1*/ + { rcar_gp_pin(6, 8), 0, 3 }, /* avb2_td0 */ + } }, + { pinmux_drive_reg("drv2ctrl6", 0xe6068088) { + { rcar_gp_pin(6, 20), 16, 3 }, /* avb2_avtp_pps */ + { rcar_gp_pin(6, 19), 12, 3 }, /* avb2_avtp_capture */ + { rcar_gp_pin(6, 18), 8, 3 }, /* avb2_avtp_match */ + { rcar_gp_pin(6, 17), 4, 3 }, /* avb2_link */ + { rcar_gp_pin(6, 16), 0, 3 }, /* avb2_phy_int */ + } }, + { pinmux_drive_reg("drv0ctrl7", 0xe6068880) { + { rcar_gp_pin(7, 7), 28, 3 }, /* avb3_txc */ + { rcar_gp_pin(7, 6), 24, 3 }, /* avb3_tx_ctl */ + { rcar_gp_pin(7, 5), 20, 3 }, /* avb3_rd3 */ + { rcar_gp_pin(7, 4), 16, 3 }, /* avb3_rd2 */ + { rcar_gp_pin(7, 3), 12, 3 }, /* avb3_rd1 */ + { rcar_gp_pin(7, 2), 8, 3 }, /* avb3_rd0 */ + { rcar_gp_pin(7, 1), 4, 3 }, /* avb3_rxc */ + { rcar_gp_pin(7, 0), 0, 3 }, /* avb3_rx_ctl */ + } }, + { pinmux_drive_reg("drv1ctrl7", 0xe6068884) { + { rcar_gp_pin(7, 15), 28, 3 }, /* avb3_magic */ + { rcar_gp_pin(7, 14), 24, 3 }, /* avb3_mdc */ + { rcar_gp_pin(7, 13), 20, 3 }, /* avb3_mdio */ + { rcar_gp_pin(7, 12), 16, 3 }, /* avb3_txcrefclk */ + { rcar_gp_pin(7, 11), 12, 3 }, /* avb3_td3 */ + { rcar_gp_pin(7, 10), 8, 3 }, /* avb3_td2 */ + { rcar_gp_pin(7, 9), 4, 3 }, /* avb3_td1*/ + { rcar_gp_pin(7, 8), 0, 3 }, /* avb3_td0 */ + } }, + { pinmux_drive_reg("drv2ctrl7", 0xe6068888) { + { rcar_gp_pin(7, 20), 16, 3 }, /* avb3_avtp_pps */ + { rcar_gp_pin(7, 19), 12, 3 }, /* avb3_avtp_capture */ + { rcar_gp_pin(7, 18), 8, 3 }, /* avb3_avtp_match */ + { rcar_gp_pin(7, 17), 4, 3 }, /* avb3_link */ + { rcar_gp_pin(7, 16), 0, 3 }, /* avb3_phy_int */ + } }, + { pinmux_drive_reg("drv0ctrl8", 0xe6069080) { + { rcar_gp_pin(8, 7), 28, 3 }, /* avb4_txc */ + { rcar_gp_pin(8, 6), 24, 3 }, /* avb4_tx_ctl */ + { rcar_gp_pin(8, 5), 20, 3 }, /* avb4_rd3 */ + { rcar_gp_pin(8, 4), 16, 3 }, /* avb4_rd2 */ + { rcar_gp_pin(8, 3), 12, 3 }, /* avb4_rd1 */ + { rcar_gp_pin(8, 2), 8, 3 }, /* avb4_rd0 */ + { rcar_gp_pin(8, 1), 4, 3 }, /* avb4_rxc */ + { rcar_gp_pin(8, 0), 0, 3 }, /* avb4_rx_ctl */ + } }, + { pinmux_drive_reg("drv1ctrl8", 0xe6069084) { + { rcar_gp_pin(8, 15), 28, 3 }, /* avb4_magic */ + { rcar_gp_pin(8, 14), 24, 3 }, /* avb4_mdc */ + { rcar_gp_pin(8, 13), 20, 3 }, /* avb4_mdio */ + { rcar_gp_pin(8, 12), 16, 3 }, /* avb4_txcrefclk */ + { rcar_gp_pin(8, 11), 12, 3 }, /* avb4_td3 */ + { rcar_gp_pin(8, 10), 8, 3 }, /* avb4_td2 */ + { rcar_gp_pin(8, 9), 4, 3 }, /* avb4_td1*/ + { rcar_gp_pin(8, 8), 0, 3 }, /* avb4_td0 */ + } }, + { pinmux_drive_reg("drv2ctrl8", 0xe6069088) { + { rcar_gp_pin(8, 20), 16, 3 }, /* avb4_avtp_pps */ + { rcar_gp_pin(8, 19), 12, 3 }, /* avb4_avtp_capture */ + { rcar_gp_pin(8, 18), 8, 3 }, /* avb4_avtp_match */ + { rcar_gp_pin(8, 17), 4, 3 }, /* avb4_link */ + { rcar_gp_pin(8, 16), 0, 3 }, /* avb4_phy_int */ + } }, + { pinmux_drive_reg("drv0ctrl9", 0xe6069880) { + { rcar_gp_pin(9, 7), 28, 3 }, /* avb5_txc */ + { rcar_gp_pin(9, 6), 24, 3 }, /* avb5_tx_ctl */ + { rcar_gp_pin(9, 5), 20, 3 }, /* avb5_rd3 */ + { rcar_gp_pin(9, 4), 16, 3 }, /* avb5_rd2 */ + { rcar_gp_pin(9, 3), 12, 3 }, /* avb5_rd1 */ + { rcar_gp_pin(9, 2), 8, 3 }, /* avb5_rd0 */ + { rcar_gp_pin(9, 1), 4, 3 }, /* avb5_rxc */ + { rcar_gp_pin(9, 0), 0, 3 }, /* avb5_rx_ctl */ + } }, + { pinmux_drive_reg("drv1ctrl9", 0xe6069884) { + { rcar_gp_pin(9, 15), 28, 3 }, /* avb5_magic */ + { rcar_gp_pin(9, 14), 24, 3 }, /* avb5_mdc */ + { rcar_gp_pin(9, 13), 20, 3 }, /* avb5_mdio */ + { rcar_gp_pin(9, 12), 16, 3 }, /* avb5_txcrefclk */ + { rcar_gp_pin(9, 11), 12, 3 }, /* avb5_td3 */ + { rcar_gp_pin(9, 10), 8, 3 }, /* avb5_td2 */ + { rcar_gp_pin(9, 9), 4, 3 }, /* avb5_td1*/ + { rcar_gp_pin(9, 8), 0, 3 }, /* avb5_td0 */ + } }, + { pinmux_drive_reg("drv2ctrl9", 0xe6069888) { + { rcar_gp_pin(9, 20), 16, 3 }, /* avb5_avtp_pps */ + { rcar_gp_pin(9, 19), 12, 3 }, /* avb5_avtp_capture */ + { rcar_gp_pin(9, 18), 8, 3 }, /* avb5_avtp_match */ + { rcar_gp_pin(9, 17), 4, 3 }, /* avb5_link */ + { rcar_gp_pin(9, 16), 0, 3 }, /* avb5_phy_int */ + } }, + { }, +}; + +enum ioctrl_regs { + poc0, + poc1, + poc2, + poc4, + poc5, + poc6, + poc7, + poc8, + poc9, + td1sel0, +}; + +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { + [poc0] = { 0xe60580a0, }, + [poc1] = { 0xe60500a0, }, + [poc2] = { 0xe60508a0, }, + [poc4] = { 0xe60600a0, }, + [poc5] = { 0xe60608a0, }, + [poc6] = { 0xe60680a0, }, + [poc7] = { 0xe60688a0, }, + [poc8] = { 0xe60690a0, }, + [poc9] = { 0xe60698a0, }, + [td1sel0] = { 0xe6058124, }, + { /* sentinel */ }, +}; + +static int r8a779a0_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, + u32 *pocctrl) +{ + int bit = pin & 0x1f; + + *pocctrl = pinmux_ioctrl_regs[poc0].reg; + if (pin >= rcar_gp_pin(0, 15) && pin <= rcar_gp_pin(0, 27)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[poc1].reg; + if (pin >= rcar_gp_pin(1, 0) && pin <= rcar_gp_pin(1, 30)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[poc2].reg; + if (pin >= rcar_gp_pin(2, 2) && pin <= rcar_gp_pin(2, 15)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[poc4].reg; + if (pin >= rcar_gp_pin(4, 0) && pin <= rcar_gp_pin(4, 17)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[poc5].reg; + if (pin >= rcar_gp_pin(5, 0) && pin <= rcar_gp_pin(5, 17)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[poc6].reg; + if (pin >= rcar_gp_pin(6, 0) && pin <= rcar_gp_pin(6, 17)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[poc7].reg; + if (pin >= rcar_gp_pin(7, 0) && pin <= rcar_gp_pin(7, 17)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[poc8].reg; + if (pin >= rcar_gp_pin(8, 0) && pin <= rcar_gp_pin(8, 17)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[poc9].reg; + if (pin >= rcar_gp_pin(9, 0) && pin <= rcar_gp_pin(9, 17)) + return bit; + + return -einval; +} + +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { pinmux_bias_reg("puen0", 0xe60580c0, "pud0", 0xe60580e0) { + [ 0] = rcar_gp_pin(0, 0), /* qspi0_spclk */ + [ 1] = rcar_gp_pin(0, 1), /* qspi0_mosi_io0 */ + [ 2] = rcar_gp_pin(0, 2), /* qspi0_miso_io1 */ + [ 3] = rcar_gp_pin(0, 3), /* qspi0_io2 */ + [ 4] = rcar_gp_pin(0, 4), /* qspi0_io3 */ + [ 5] = rcar_gp_pin(0, 5), /* qspi0_ssl */ + [ 6] = rcar_gp_pin(0, 6), /* qspi1_spclk */ + [ 7] = rcar_gp_pin(0, 7), /* qspi1_mosi_io0 */ + [ 8] = rcar_gp_pin(0, 8), /* qspi1_miso_io1 */ + [ 9] = rcar_gp_pin(0, 9), /* qspi1_io2 */ + [10] = rcar_gp_pin(0, 10), /* qspi1_io3 */ + [11] = rcar_gp_pin(0, 11), /* qspi1_ssl */ + [12] = rcar_gp_pin(0, 12), /* rpc_reset_n */ + [13] = rcar_gp_pin(0, 13), /* rpc_wp_n */ + [14] = rcar_gp_pin(0, 14), /* rpc_int_n */ + [15] = rcar_gp_pin(0, 15), /* sd_wp */ + [16] = rcar_gp_pin(0, 16), /* sd_cd */ + [17] = rcar_gp_pin(0, 17), /* mmc_ds */ + [18] = rcar_gp_pin(0, 18), /* mmc_sd_cmd */ + [19] = rcar_gp_pin(0, 19), /* mmc_sd_d0 */ + [20] = rcar_gp_pin(0, 20), /* mmc_sd_d1 */ + [21] = rcar_gp_pin(0, 21), /* mmc_sd_d2 */ + [22] = rcar_gp_pin(0, 22), /* mmc_sd_d3 */ + [23] = rcar_gp_pin(0, 23), /* mmc_sd_clk */ + [24] = rcar_gp_pin(0, 24), /* mmc_d4 */ + [25] = rcar_gp_pin(0, 25), /* mmc_d5 */ + [26] = rcar_gp_pin(0, 26), /* mmc_d6 */ + [27] = rcar_gp_pin(0, 27), /* mmc_d7 */ + [28] = sh_pfc_pin_none, + [29] = sh_pfc_pin_none, + [30] = sh_pfc_pin_none, + [31] = sh_pfc_pin_none, + } }, + { pinmux_bias_reg("puen1", 0xe60500c0, "pud1", 0xe60500e0) { + [ 0] = rcar_gp_pin(1, 0), /* scif_clk */ + [ 1] = rcar_gp_pin(1, 1), /* hrx0 */ + [ 2] = rcar_gp_pin(1, 2), /* hsck0 */ + [ 3] = rcar_gp_pin(1, 3), /* hrts0_n */ + [ 4] = rcar_gp_pin(1, 4), /* hcts0_n */ + [ 5] = rcar_gp_pin(1, 5), /* htx0 */ + [ 6] = rcar_gp_pin(1, 6), /* msiof0_rxd */ + [ 7] = rcar_gp_pin(1, 7), /* msiof0_txd */ + [ 8] = rcar_gp_pin(1, 8), /* msiof0_sck */ + [ 9] = rcar_gp_pin(1, 9), /* msiof0_sync */ + [10] = rcar_gp_pin(1, 10), /* msiof0_ss1 */ + [11] = rcar_gp_pin(1, 11), /* msiof0_ss2 */ + [12] = rcar_gp_pin(1, 12), /* msiof1_rxd */ + [13] = rcar_gp_pin(1, 13), /* msiof1_txd */ + [14] = rcar_gp_pin(1, 14), /* msiof1_sck */ + [15] = rcar_gp_pin(1, 15), /* msiof1_sync */ + [16] = rcar_gp_pin(1, 16), /* msiof1_ss1 */ + [17] = rcar_gp_pin(1, 17), /* msiof1_ss2 */ + [18] = rcar_gp_pin(1, 18), /* msiof2_rxd */ + [19] = rcar_gp_pin(1, 19), /* msiof2_txd */ + [20] = rcar_gp_pin(1, 20), /* msiof2_sck */ + [21] = rcar_gp_pin(1, 21), /* msiof2_sync */ + [22] = rcar_gp_pin(1, 22), /* msiof2_ss1 */ + [23] = rcar_gp_pin(1, 23), /* msiof2_ss2 */ + [24] = rcar_gp_pin(1, 24), /* irq0 */ + [25] = rcar_gp_pin(1, 25), /* irq1 */ + [26] = rcar_gp_pin(1, 26), /* irq2 */ + [27] = rcar_gp_pin(1, 27), /* irq3 */ + [28] = rcar_gp_pin(1, 28), /* gp1_28 */ + [29] = rcar_gp_pin(1, 29), /* gp1_29 */ + [30] = rcar_gp_pin(1, 30), /* gp1_30 */ + [31] = sh_pfc_pin_none, + } }, + { pinmux_bias_reg("puen2", 0xe60508c0, "pud2", 0xe60508e0) { + [ 0] = rcar_gp_pin(2, 0), /* ipc_clkin */ + [ 1] = rcar_gp_pin(2, 1), /* ipc_clkout */ + [ 2] = rcar_gp_pin(2, 2), /* gp2_02 */ + [ 3] = rcar_gp_pin(2, 3), /* gp2_03 */ + [ 4] = rcar_gp_pin(2, 4), /* gp2_04 */ + [ 5] = rcar_gp_pin(2, 5), /* gp2_05 */ + [ 6] = rcar_gp_pin(2, 6), /* gp2_06 */ + [ 7] = rcar_gp_pin(2, 7), /* gp2_07 */ + [ 8] = rcar_gp_pin(2, 8), /* gp2_08 */ + [ 9] = rcar_gp_pin(2, 9), /* gp2_09 */ + [10] = rcar_gp_pin(2, 10), /* gp2_10 */ + [11] = rcar_gp_pin(2, 11), /* gp2_11 */ + [12] = rcar_gp_pin(2, 12), /* gp2_12 */ + [13] = rcar_gp_pin(2, 13), /* gp2_13 */ + [14] = rcar_gp_pin(2, 14), /* gp2_14 */ + [15] = rcar_gp_pin(2, 15), /* gp2_15 */ + [16] = rcar_gp_pin(2, 16), /* fxr_txda_a */ + [17] = rcar_gp_pin(2, 17), /* rxda_extfxr_a */ + [18] = rcar_gp_pin(2, 18), /* fxr_txdb */ + [19] = rcar_gp_pin(2, 19), /* rxdb_extfxr */ + [20] = rcar_gp_pin(2, 20), /* clk_extfxr */ + [21] = rcar_gp_pin(2, 21), /* tpu0to0 */ + [22] = rcar_gp_pin(2, 22), /* tpu0to1 */ + [23] = rcar_gp_pin(2, 23), /* tclk1_a */ + [24] = rcar_gp_pin(2, 24), /* tclk2_a */ + [25] = sh_pfc_pin_none, + [26] = sh_pfc_pin_none, + [27] = sh_pfc_pin_none, + [28] = sh_pfc_pin_none, + [29] = sh_pfc_pin_none, + [30] = sh_pfc_pin_none, + [31] = sh_pfc_pin_none, + } }, + { pinmux_bias_reg("puen3", 0xe60588c0, "pud3", 0xe60588e0) { + [ 0] = rcar_gp_pin(3, 0), /* can_clk */ + [ 1] = rcar_gp_pin(3, 1), /* canfd0_tx */ + [ 2] = rcar_gp_pin(3, 2), /* canfd0_rx */ + [ 3] = rcar_gp_pin(3, 3), /* canfd1_tx */ + [ 4] = rcar_gp_pin(3, 4), /* canfd1_rx */ + [ 5] = rcar_gp_pin(3, 5), /* canfd2_tx */ + [ 6] = rcar_gp_pin(3, 6), /* canfd2_rx */ + [ 7] = rcar_gp_pin(3, 7), /* canfd3_tx */ + [ 8] = rcar_gp_pin(3, 8), /* canfd3_rx */ + [ 9] = rcar_gp_pin(3, 9), /* canfd4_tx */ + [10] = rcar_gp_pin(3, 10), /* canfd4_rx */ + [11] = rcar_gp_pin(3, 11), /* canfd5_tx */ + [12] = rcar_gp_pin(3, 12), /* canfd5_rx */ + [13] = rcar_gp_pin(3, 13), /* canfd6_tx */ + [14] = rcar_gp_pin(3, 14), /* canfd6_rx */ + [15] = rcar_gp_pin(3, 15), /* canfd7_tx */ + [16] = rcar_gp_pin(3, 16), /* canfd7_rx */ + [17] = sh_pfc_pin_none, + [18] = sh_pfc_pin_none, + [19] = sh_pfc_pin_none, + [20] = sh_pfc_pin_none, + [21] = sh_pfc_pin_none, + [22] = sh_pfc_pin_none, + [23] = sh_pfc_pin_none, + [24] = sh_pfc_pin_none, + [25] = sh_pfc_pin_none, + [26] = sh_pfc_pin_none, + [27] = sh_pfc_pin_none, + [28] = sh_pfc_pin_none, + [29] = sh_pfc_pin_none, + [30] = sh_pfc_pin_none, + [31] = sh_pfc_pin_none, + } }, + { pinmux_bias_reg("puen4", 0xe60600c0, "pud4", 0xe60600e0) { + [ 0] = rcar_gp_pin(4, 0), /* avb0_rx_ctl */ + [ 1] = rcar_gp_pin(4, 1), /* avb0_rxc */ + [ 2] = rcar_gp_pin(4, 2), /* avb0_rd0 */ + [ 3] = rcar_gp_pin(4, 3), /* avb0_rd1 */ + [ 4] = rcar_gp_pin(4, 4), /* avb0_rd2 */ + [ 5] = rcar_gp_pin(4, 5), /* avb0_rd3 */ + [ 6] = rcar_gp_pin(4, 6), /* avb0_tx_ctl */ + [ 7] = rcar_gp_pin(4, 7), /* avb0_txc */ + [ 8] = rcar_gp_pin(4, 8), /* avb0_td0 */ + [ 9] = rcar_gp_pin(4, 9), /* avb0_td1 */ + [10] = rcar_gp_pin(4, 10), /* avb0_td2 */ + [11] = rcar_gp_pin(4, 11), /* avb0_td3 */ + [12] = rcar_gp_pin(4, 12), /* avb0_txrefclk */ + [13] = rcar_gp_pin(4, 13), /* avb0_mdio */ + [14] = rcar_gp_pin(4, 14), /* avb0_mdc */ + [15] = rcar_gp_pin(4, 15), /* avb0_magic */ + [16] = rcar_gp_pin(4, 16), /* avb0_phy_int */ + [17] = rcar_gp_pin(4, 17), /* avb0_link */ + [18] = rcar_gp_pin(4, 18), /* avb0_avtp_match */ + [19] = rcar_gp_pin(4, 19), /* avb0_avtp_capture */ + [20] = rcar_gp_pin(4, 20), /* avb0_avtp_pps */ + [21] = rcar_gp_pin(4, 21), /* pcie0_clkreq_n */ + [22] = rcar_gp_pin(4, 22), /* pcie1_clkreq_n */ + [23] = rcar_gp_pin(4, 23), /* pcie2_clkreq_n */ + [24] = rcar_gp_pin(4, 24), /* pcie3_clkreq_n */ + [25] = rcar_gp_pin(4, 25), /* avs0 */ + [26] = rcar_gp_pin(4, 26), /* avs1 */ + [27] = sh_pfc_pin_none, + [28] = sh_pfc_pin_none, + [29] = sh_pfc_pin_none, + [30] = sh_pfc_pin_none, + [31] = sh_pfc_pin_none, + } }, + { pinmux_bias_reg("puen5", 0xe60608c0, "pud5", 0xe60608e0) { + [ 0] = rcar_gp_pin(5, 0), /* avb1_rx_ctl */ + [ 1] = rcar_gp_pin(5, 1), /* avb1_rxc */ + [ 2] = rcar_gp_pin(5, 2), /* avb1_rd0 */ + [ 3] = rcar_gp_pin(5, 3), /* avb1_rd1 */ + [ 4] = rcar_gp_pin(5, 4), /* avb1_rd2 */ + [ 5] = rcar_gp_pin(5, 5), /* avb1_rd3 */ + [ 6] = rcar_gp_pin(5, 6), /* avb1_tx_ctl */ + [ 7] = rcar_gp_pin(5, 7), /* avb1_txc */ + [ 8] = rcar_gp_pin(5, 8), /* avb1_td0 */ + [ 9] = rcar_gp_pin(5, 9), /* avb1_td1 */ + [10] = rcar_gp_pin(5, 10), /* avb1_td2 */ + [11] = rcar_gp_pin(5, 11), /* avb1_td3 */ + [12] = rcar_gp_pin(5, 12), /* avb1_txcrefclk */ + [13] = rcar_gp_pin(5, 13), /* avb1_mdio */ + [14] = rcar_gp_pin(5, 14), /* avb1_mdc */ + [15] = rcar_gp_pin(5, 15), /* avb1_magic */ + [16] = rcar_gp_pin(5, 16), /* avb1_phy_int */ + [17] = rcar_gp_pin(5, 17), /* avb1_link */ + [18] = rcar_gp_pin(5, 18), /* avb1_avtp_match */ + [19] = rcar_gp_pin(5, 19), /* avb1_avtp_capture */ + [20] = rcar_gp_pin(5, 20), /* avb1_avtp_pps */ + [21] = sh_pfc_pin_none, + [22] = sh_pfc_pin_none, + [23] = sh_pfc_pin_none, + [24] = sh_pfc_pin_none, + [25] = sh_pfc_pin_none, + [26] = sh_pfc_pin_none, + [27] = sh_pfc_pin_none, + [28] = sh_pfc_pin_none, + [29] = sh_pfc_pin_none, + [30] = sh_pfc_pin_none, + [31] = sh_pfc_pin_none, + } }, + { pinmux_bias_reg("puen6", 0xe60680c0, "pud6", 0xe60680e0) { + [ 0] = rcar_gp_pin(6, 0), /* avb2_rx_ctl */ + [ 1] = rcar_gp_pin(6, 1), /* avb2_rxc */ + [ 2] = rcar_gp_pin(6, 2), /* avb2_rd0 */ + [ 3] = rcar_gp_pin(6, 3), /* avb2_rd1 */ + [ 4] = rcar_gp_pin(6, 4), /* avb2_rd2 */ + [ 5] = rcar_gp_pin(6, 5), /* avb2_rd3 */ + [ 6] = rcar_gp_pin(6, 6), /* avb2_tx_ctl */ + [ 7] = rcar_gp_pin(6, 7), /* avb2_txc */ + [ 8] = rcar_gp_pin(6, 8), /* avb2_td0 */ + [ 9] = rcar_gp_pin(6, 9), /* avb2_td1 */ + [10] = rcar_gp_pin(6, 10), /* avb2_td2 */ + [11] = rcar_gp_pin(6, 11), /* avb2_td3 */ + [12] = rcar_gp_pin(6, 12), /* avb2_txcrefclk */ + [13] = rcar_gp_pin(6, 13), /* avb2_mdio */ + [14] = rcar_gp_pin(6, 14), /* avb2_mdc*/ + [15] = rcar_gp_pin(6, 15), /* avb2_magic */ + [16] = rcar_gp_pin(6, 16), /* avb2_phy_int */ + [17] = rcar_gp_pin(6, 17), /* avb2_link */ + [18] = rcar_gp_pin(6, 18), /* avb2_avtp_match */ + [19] = rcar_gp_pin(6, 19), /* avb2_avtp_capture */ + [20] = rcar_gp_pin(6, 20), /* avb2_avtp_pps */ + [21] = sh_pfc_pin_none, + [22] = sh_pfc_pin_none, + [23] = sh_pfc_pin_none, + [24] = sh_pfc_pin_none, + [25] = sh_pfc_pin_none, + [26] = sh_pfc_pin_none, + [27] = sh_pfc_pin_none, + [28] = sh_pfc_pin_none, + [29] = sh_pfc_pin_none, + [30] = sh_pfc_pin_none, + [31] = sh_pfc_pin_none, + } }, + { pinmux_bias_reg("puen7", 0xe60688c0, "pud7", 0xe60688e0) { + [ 0] = rcar_gp_pin(7, 0), /* avb3_rx_ctl */ + [ 1] = rcar_gp_pin(7, 1), /* avb3_rxc */ + [ 2] = rcar_gp_pin(7, 2), /* avb3_rd0 */ + [ 3] = rcar_gp_pin(7, 3), /* avb3_rd1 */ + [ 4] = rcar_gp_pin(7, 4), /* avb3_rd2 */ + [ 5] = rcar_gp_pin(7, 5), /* avb3_rd3 */ + [ 6] = rcar_gp_pin(7, 6), /* avb3_tx_ctl */ + [ 7] = rcar_gp_pin(7, 7), /* avb3_txc */ + [ 8] = rcar_gp_pin(7, 8), /* avb3_td0 */ + [ 9] = rcar_gp_pin(7, 9), /* avb3_td1 */ + [10] = rcar_gp_pin(7, 10), /* avb3_td2 */ + [11] = rcar_gp_pin(7, 11), /* avb3_td3 */ + [12] = rcar_gp_pin(7, 12), /* avb3_txcrefclk */ + [13] = rcar_gp_pin(7, 13), /* avb3_mdio */ + [14] = rcar_gp_pin(7, 14), /* avb3_mdc */ + [15] = rcar_gp_pin(7, 15), /* avb3_magic */ + [16] = rcar_gp_pin(7, 16), /* avb3_phy_int */ + [17] = rcar_gp_pin(7, 17), /* avb3_link */ + [18] = rcar_gp_pin(7, 18), /* avb3_avtp_match */ + [19] = rcar_gp_pin(7, 19), /* avb3_avtp_capture */ + [20] = rcar_gp_pin(7, 20), /* avb3_avtp_pps */ + [21] = sh_pfc_pin_none, + [22] = sh_pfc_pin_none, + [23] = sh_pfc_pin_none, + [24] = sh_pfc_pin_none, + [25] = sh_pfc_pin_none, + [26] = sh_pfc_pin_none, + [27] = sh_pfc_pin_none, + [28] = sh_pfc_pin_none, + [29] = sh_pfc_pin_none, + [30] = sh_pfc_pin_none, + [31] = sh_pfc_pin_none, + } }, + { pinmux_bias_reg("puen8", 0xe60690c0, "pud8", 0xe60690e0) { + [ 0] = rcar_gp_pin(8, 0), /* avb4_rx_ctl */ + [ 1] = rcar_gp_pin(8, 1), /* avb4_rxc */ + [ 2] = rcar_gp_pin(8, 2), /* avb4_rd0 */ + [ 3] = rcar_gp_pin(8, 3), /* avb4_rd1 */ + [ 4] = rcar_gp_pin(8, 4), /* avb4_rd2 */ + [ 5] = rcar_gp_pin(8, 5), /* avb4_rd3 */ + [ 6] = rcar_gp_pin(8, 6), /* avb4_tx_ctl */ + [ 7] = rcar_gp_pin(8, 7), /* avb4_txc */ + [ 8] = rcar_gp_pin(8, 8), /* avb4_td0 */ + [ 9] = rcar_gp_pin(8, 9), /* avb4_td1 */ + [10] = rcar_gp_pin(8, 10), /* avb4_td2 */ + [11] = rcar_gp_pin(8, 11), /* avb4_td3 */ + [12] = rcar_gp_pin(8, 12), /* avb4_txcrefclk */ + [13] = rcar_gp_pin(8, 13), /* avb4_mdio */ + [14] = rcar_gp_pin(8, 14), /* avb4_mdc */ + [15] = rcar_gp_pin(8, 15), /* avb4_magic */ + [16] = rcar_gp_pin(8, 16), /* avb4_phy_int */ + [17] = rcar_gp_pin(8, 17), /* avb4_link */ + [18] = rcar_gp_pin(8, 18), /* avb4_avtp_match */ + [19] = rcar_gp_pin(8, 19), /* avb4_avtp_capture */ + [20] = rcar_gp_pin(8, 20), /* avb4_avtp_pps */ + [21] = sh_pfc_pin_none, + [22] = sh_pfc_pin_none, + [23] = sh_pfc_pin_none, + [24] = sh_pfc_pin_none, + [25] = sh_pfc_pin_none, + [26] = sh_pfc_pin_none, + [27] = sh_pfc_pin_none, + [28] = sh_pfc_pin_none, + [29] = sh_pfc_pin_none, + [30] = sh_pfc_pin_none, + [31] = sh_pfc_pin_none, + } }, + { pinmux_bias_reg("puen9", 0xe60698c0, "pud9", 0xe60698e0) { + [ 0] = rcar_gp_pin(9, 0), /* avb5_rx_ctl */ + [ 1] = rcar_gp_pin(9, 1), /* avb5_rxc */ + [ 2] = rcar_gp_pin(9, 2), /* avb5_rd0 */ + [ 3] = rcar_gp_pin(9, 3), /* avb5_rd1 */ + [ 4] = rcar_gp_pin(9, 4), /* avb5_rd2 */ + [ 5] = rcar_gp_pin(9, 5), /* avb5_rd3 */ + [ 6] = rcar_gp_pin(9, 6), /* avb5_tx_ctl */ + [ 7] = rcar_gp_pin(9, 7), /* avb5_txc */ + [ 8] = rcar_gp_pin(9, 8), /* avb5_td0 */ + [ 9] = rcar_gp_pin(9, 9), /* avb5_td1 */ + [10] = rcar_gp_pin(9, 10), /* avb5_td2 */ + [11] = rcar_gp_pin(9, 11), /* avb5_td3 */ + [12] = rcar_gp_pin(9, 12), /* avb5_txcrefclk */ + [13] = rcar_gp_pin(9, 13), /* avb5_mdio */ + [14] = rcar_gp_pin(9, 14), /* avb5_mdc */ + [15] = rcar_gp_pin(9, 15), /* avb5_magic */ + [16] = rcar_gp_pin(9, 16), /* avb5_phy_int */ + [17] = rcar_gp_pin(9, 17), /* avb5_link */ + [18] = rcar_gp_pin(9, 18), /* avb5_avtp_match */ + [19] = rcar_gp_pin(9, 19), /* avb5_avtp_capture */ + [20] = rcar_gp_pin(9, 20), /* avb5_avtp_pps */ + [21] = sh_pfc_pin_none, + [22] = sh_pfc_pin_none, + [23] = sh_pfc_pin_none, + [24] = sh_pfc_pin_none, + [25] = sh_pfc_pin_none, + [26] = sh_pfc_pin_none, + [27] = sh_pfc_pin_none, + [28] = sh_pfc_pin_none, + [29] = sh_pfc_pin_none, + [30] = sh_pfc_pin_none, + [31] = sh_pfc_pin_none, + } }, + { /* sentinel */ }, +}; + +static const struct sh_pfc_soc_operations pinmux_ops = { + .pin_to_pocctrl = r8a779a0_pin_to_pocctrl, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, +}; + +const struct sh_pfc_soc_info r8a779a0_pinmux_info = { + .name = "r8a779a0_pfc", + .ops = &pinmux_ops, + .unlock_reg = 0x1ff, /* pmmrn mask */ + + .function = { pinmux_function_begin, pinmux_function_end }, + + .pins = pinmux_pins, + .nr_pins = array_size(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = array_size(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = array_size(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + .drive_regs = pinmux_drive_regs, + .bias_regs = pinmux_bias_regs, + .ioctrl_regs = pinmux_ioctrl_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = array_size(pinmux_data), +}; diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h +extern const struct sh_pfc_soc_info r8a779a0_pinmux_info;
|
Pin Controllers (pinctrl)
|
741a7370fc3b8b549ac69886be161a99109b78b6
|
ulrich hecht
|
drivers
|
pinctrl
|
renesas
|
pinctrl: sunxi: add support for the allwinner h616 pin controller
|
port a is used for an internal connection to some analogue circuitry which looks like an ac200 ip (as in the h6), though this is not mentioned in the manual.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for the allwinner h616 pin controller
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['sunxi']
|
['kconfig', 'c', 'makefile']
| 3
| 554
| 0
|
--- diff --git a/drivers/pinctrl/sunxi/kconfig b/drivers/pinctrl/sunxi/kconfig --- a/drivers/pinctrl/sunxi/kconfig +++ b/drivers/pinctrl/sunxi/kconfig +config pinctrl_sun50i_h616 + bool "support for the allwinner h616 pio" + default arm64 && arch_sunxi + select pinctrl_sunxi + diff --git a/drivers/pinctrl/sunxi/makefile b/drivers/pinctrl/sunxi/makefile --- a/drivers/pinctrl/sunxi/makefile +++ b/drivers/pinctrl/sunxi/makefile +obj-$(config_pinctrl_sun50i_h616) += pinctrl-sun50i-h616.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c +// spdx-license-identifier: gpl-2.0 +/* + * allwinner h616 soc pinctrl driver. + * + * copyright (c) 2020 arm ltd. + * based on the h6 pinctrl driver + * copyright (c) 2017 icenowy zheng <icenowy@aosc.io> + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin h616_pins[] = { + /* internal connection to the ac200 part */ + sunxi_pin(sunxi_pinctrl_pin(a, 0), + sunxi_function(0x2, "emac1")), /* erxd1 */ + sunxi_pin(sunxi_pinctrl_pin(a, 1), + sunxi_function(0x2, "emac1")), /* erxd0 */ + sunxi_pin(sunxi_pinctrl_pin(a, 2), + sunxi_function(0x2, "emac1")), /* ecrs_dv */ + sunxi_pin(sunxi_pinctrl_pin(a, 3), + sunxi_function(0x2, "emac1")), /* erxerr */ + sunxi_pin(sunxi_pinctrl_pin(a, 4), + sunxi_function(0x2, "emac1")), /* etxd1 */ + sunxi_pin(sunxi_pinctrl_pin(a, 5), + sunxi_function(0x2, "emac1")), /* etxd0 */ + sunxi_pin(sunxi_pinctrl_pin(a, 6), + sunxi_function(0x2, "emac1")), /* etxck */ + sunxi_pin(sunxi_pinctrl_pin(a, 7), + sunxi_function(0x2, "emac1")), /* etxen */ + sunxi_pin(sunxi_pinctrl_pin(a, 8), + sunxi_function(0x2, "emac1")), /* emdc */ + sunxi_pin(sunxi_pinctrl_pin(a, 9), + sunxi_function(0x2, "emac1")), /* emdio */ + sunxi_pin(sunxi_pinctrl_pin(a, 10), + sunxi_function(0x2, "i2c3")), /* sck */ + sunxi_pin(sunxi_pinctrl_pin(a, 11), + sunxi_function(0x2, "i2c3")), /* sda */ + sunxi_pin(sunxi_pinctrl_pin(a, 12), + sunxi_function(0x2, "pwm5")), + /* hole */ + sunxi_pin(sunxi_pinctrl_pin(c, 0), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "nand0"), /* we */ + sunxi_function(0x3, "mmc2"), /* ds */ + sunxi_function(0x4, "spi0"), /* clk */ + sunxi_function_irq_bank(0x6, 1, 0)), /* pc_eint0 */ + sunxi_pin(sunxi_pinctrl_pin(c, 1), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "nand0"), /* ale */ + sunxi_function(0x3, "mmc2"), /* rst */ + sunxi_function_irq_bank(0x6, 1, 1)), /* pc_eint1 */ + sunxi_pin(sunxi_pinctrl_pin(c, 2), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "nand0"), /* cle */ + sunxi_function(0x4, "spi0"), /* mosi */ + sunxi_function_irq_bank(0x6, 1, 2)), /* pc_eint2 */ + sunxi_pin(sunxi_pinctrl_pin(c, 3), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "nand0"), /* ce1 */ + sunxi_function(0x4, "spi0"), /* cs0 */ + sunxi_function_irq_bank(0x6, 1, 3)), /* pc_eint3 */ + sunxi_pin(sunxi_pinctrl_pin(c, 4), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "nand0"), /* ce0 */ + sunxi_function(0x4, "spi0"), /* miso */ + sunxi_function_irq_bank(0x6, 1, 4)), /* pc_eint4 */ + sunxi_pin(sunxi_pinctrl_pin(c, 5), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "nand0"), /* re */ + sunxi_function(0x3, "mmc2"), /* clk */ + sunxi_function_irq_bank(0x6, 1, 5)), /* pc_eint5 */ + sunxi_pin(sunxi_pinctrl_pin(c, 6), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "nand0"), /* rb0 */ + sunxi_function(0x3, "mmc2"), /* cmd */ + sunxi_function_irq_bank(0x6, 1, 6)), /* pc_eint6 */ + sunxi_pin(sunxi_pinctrl_pin(c, 7), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "nand0"), /* rb1 */ + sunxi_function(0x4, "spi0"), /* cs1 */ + sunxi_function_irq_bank(0x6, 1, 7)), /* pc_eint7 */ + sunxi_pin(sunxi_pinctrl_pin(c, 8), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "nand0"), /* dq7 */ + sunxi_function(0x3, "mmc2"), /* d3 */ + sunxi_function_irq_bank(0x6, 1, 8)), /* pc_eint8 */ + sunxi_pin(sunxi_pinctrl_pin(c, 9), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "nand0"), /* dq6 */ + sunxi_function(0x3, "mmc2"), /* d4 */ + sunxi_function_irq_bank(0x6, 1, 9)), /* pc_eint9 */ + sunxi_pin(sunxi_pinctrl_pin(c, 10), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "nand0"), /* dq5 */ + sunxi_function(0x3, "mmc2"), /* d0 */ + sunxi_function_irq_bank(0x6, 1, 10)), /* pc_eint10 */ + sunxi_pin(sunxi_pinctrl_pin(c, 11), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "nand0"), /* dq4 */ + sunxi_function(0x3, "mmc2"), /* d5 */ + sunxi_function_irq_bank(0x6, 1, 11)), /* pc_eint11 */ + sunxi_pin(sunxi_pinctrl_pin(c, 12), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "nand0"), /* dqs */ + sunxi_function_irq_bank(0x6, 1, 12)), /* pc_eint12 */ + sunxi_pin(sunxi_pinctrl_pin(c, 13), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "nand0"), /* dq3 */ + sunxi_function(0x3, "mmc2"), /* d1 */ + sunxi_function_irq_bank(0x6, 1, 13)), /* pc_eint13 */ + sunxi_pin(sunxi_pinctrl_pin(c, 14), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "nand0"), /* dq2 */ + sunxi_function(0x3, "mmc2"), /* d6 */ + sunxi_function_irq_bank(0x6, 1, 14)), /* pc_eint14 */ + sunxi_pin(sunxi_pinctrl_pin(c, 15), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "nand0"), /* dq1 */ + sunxi_function(0x3, "mmc2"), /* d2 */ + sunxi_function(0x4, "spi0"), /* wp */ + sunxi_function_irq_bank(0x6, 1, 15)), /* pc_eint15 */ + sunxi_pin(sunxi_pinctrl_pin(c, 16), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "nand0"), /* dq0 */ + sunxi_function(0x3, "mmc2"), /* d7 */ + sunxi_function(0x4, "spi0"), /* hold */ + sunxi_function_irq_bank(0x6, 1, 16)), /* pc_eint16 */ + /* hole */ + sunxi_pin(sunxi_pinctrl_pin(f, 0), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "mmc0"), /* d1 */ + sunxi_function(0x3, "jtag"), /* ms */ + sunxi_function_irq_bank(0x6, 4, 0)), /* pf_eint0 */ + sunxi_pin(sunxi_pinctrl_pin(f, 1), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "mmc0"), /* d0 */ + sunxi_function(0x3, "jtag"), /* di */ + sunxi_function_irq_bank(0x6, 4, 1)), /* pf_eint1 */ + sunxi_pin(sunxi_pinctrl_pin(f, 2), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "mmc0"), /* clk */ + sunxi_function(0x3, "uart0"), /* tx */ + sunxi_function_irq_bank(0x6, 4, 2)), /* pf_eint2 */ + sunxi_pin(sunxi_pinctrl_pin(f, 3), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "mmc0"), /* cmd */ + sunxi_function(0x3, "jtag"), /* do */ + sunxi_function_irq_bank(0x6, 4, 3)), /* pf_eint3 */ + sunxi_pin(sunxi_pinctrl_pin(f, 4), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "mmc0"), /* d3 */ + sunxi_function(0x3, "uart0"), /* rx */ + sunxi_function_irq_bank(0x6, 4, 4)), /* pf_eint4 */ + sunxi_pin(sunxi_pinctrl_pin(f, 5), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "mmc0"), /* d2 */ + sunxi_function(0x3, "jtag"), /* ck */ + sunxi_function_irq_bank(0x6, 4, 5)), /* pf_eint5 */ + sunxi_pin(sunxi_pinctrl_pin(f, 6), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function_irq_bank(0x6, 4, 6)), /* pf_eint6 */ + /* hole */ + sunxi_pin(sunxi_pinctrl_pin(g, 0), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "mmc1"), /* clk */ + sunxi_function_irq_bank(0x6, 5, 0)), /* pg_eint0 */ + sunxi_pin(sunxi_pinctrl_pin(g, 1), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "mmc1"), /* cmd */ + sunxi_function_irq_bank(0x6, 5, 1)), /* pg_eint1 */ + sunxi_pin(sunxi_pinctrl_pin(g, 2), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "mmc1"), /* d0 */ + sunxi_function_irq_bank(0x6, 5, 2)), /* pg_eint2 */ + sunxi_pin(sunxi_pinctrl_pin(g, 3), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "mmc1"), /* d1 */ + sunxi_function_irq_bank(0x6, 5, 3)), /* pg_eint3 */ + sunxi_pin(sunxi_pinctrl_pin(g, 4), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "mmc1"), /* d2 */ + sunxi_function_irq_bank(0x6, 5, 4)), /* pg_eint4 */ + sunxi_pin(sunxi_pinctrl_pin(g, 5), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "mmc1"), /* d3 */ + sunxi_function_irq_bank(0x6, 5, 5)), /* pg_eint5 */ + sunxi_pin(sunxi_pinctrl_pin(g, 6), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "uart1"), /* tx */ + sunxi_function(0x4, "jtag"), /* ms */ + sunxi_function_irq_bank(0x6, 5, 6)), /* pg_eint6 */ + sunxi_pin(sunxi_pinctrl_pin(g, 7), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "uart1"), /* rx */ + sunxi_function(0x4, "jtag"), /* ck */ + sunxi_function_irq_bank(0x6, 5, 7)), /* pg_eint7 */ + sunxi_pin(sunxi_pinctrl_pin(g, 8), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "uart1"), /* rts */ + sunxi_function(0x3, "clock"), /* pll_lock_debug */ + sunxi_function(0x4, "jtag"), /* do */ + sunxi_function_irq_bank(0x6, 5, 8)), /* pg_eint8 */ + sunxi_pin(sunxi_pinctrl_pin(g, 9), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "uart1"), /* cts */ + sunxi_function_irq_bank(0x6, 5, 9)), /* pg_eint9 */ + sunxi_pin(sunxi_pinctrl_pin(g, 10), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "i2s2"), /* mclk */ + sunxi_function(0x3, "clock"), /* x32kfout */ + sunxi_function_irq_bank(0x6, 5, 10)), /* pg_eint10 */ + sunxi_pin(sunxi_pinctrl_pin(g, 11), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "i2s2"), /* bclk */ + sunxi_function_irq_bank(0x6, 5, 11)), /* pg_eint11 */ + sunxi_pin(sunxi_pinctrl_pin(g, 12), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "i2s2"), /* sync */ + sunxi_function_irq_bank(0x6, 5, 12)), /* pg_eint12 */ + sunxi_pin(sunxi_pinctrl_pin(g, 13), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "i2s2"), /* dout */ + sunxi_function_irq_bank(0x6, 5, 13)), /* pg_eint13 */ + sunxi_pin(sunxi_pinctrl_pin(g, 14), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "i2s2"), /* din */ + sunxi_function_irq_bank(0x6, 5, 14)), /* pg_eint14 */ + sunxi_pin(sunxi_pinctrl_pin(g, 15), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "uart2"), /* tx */ + sunxi_function(0x5, "i2c4"), /* sck */ + sunxi_function_irq_bank(0x6, 5, 15)), /* pg_eint15 */ + sunxi_pin(sunxi_pinctrl_pin(g, 16), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "uart2"), /* rx */ + sunxi_function(0x5, "i2c4"), /* sda */ + sunxi_function_irq_bank(0x6, 5, 16)), /* pg_eint16 */ + sunxi_pin(sunxi_pinctrl_pin(g, 17), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "uart2"), /* rts */ + sunxi_function(0x5, "i2c3"), /* sck */ + sunxi_function_irq_bank(0x6, 5, 17)), /* pg_eint17 */ + sunxi_pin(sunxi_pinctrl_pin(g, 18), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "uart2"), /* cts */ + sunxi_function(0x5, "i2c3"), /* sda */ + sunxi_function_irq_bank(0x6, 5, 18)), /* pg_eint18 */ + sunxi_pin(sunxi_pinctrl_pin(g, 19), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x4, "pwm1"), + sunxi_function_irq_bank(0x6, 5, 19)), /* pg_eint19 */ + /* hole */ + sunxi_pin(sunxi_pinctrl_pin(h, 0), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "uart0"), /* tx */ + sunxi_function(0x4, "pwm3"), + sunxi_function(0x5, "i2c1"), /* sck */ + sunxi_function_irq_bank(0x6, 6, 0)), /* ph_eint0 */ + sunxi_pin(sunxi_pinctrl_pin(h, 1), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "uart0"), /* rx */ + sunxi_function(0x4, "pwm4"), + sunxi_function(0x5, "i2c1"), /* sda */ + sunxi_function_irq_bank(0x6, 6, 1)), /* ph_eint1 */ + sunxi_pin(sunxi_pinctrl_pin(h, 2), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "uart5"), /* tx */ + sunxi_function(0x3, "spdif"), /* mclk */ + sunxi_function(0x4, "pwm2"), + sunxi_function(0x5, "i2c2"), /* sck */ + sunxi_function_irq_bank(0x6, 6, 2)), /* ph_eint2 */ + sunxi_pin(sunxi_pinctrl_pin(h, 3), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "uart5"), /* rx */ + sunxi_function(0x4, "pwm1"), + sunxi_function(0x5, "i2c2"), /* sda */ + sunxi_function_irq_bank(0x6, 6, 3)), /* ph_eint3 */ + sunxi_pin(sunxi_pinctrl_pin(h, 4), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x3, "spdif"), /* out */ + sunxi_function(0x5, "i2c3"), /* sck */ + sunxi_function_irq_bank(0x6, 6, 4)), /* ph_eint4 */ + sunxi_pin(sunxi_pinctrl_pin(h, 5), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "uart2"), /* tx */ + sunxi_function(0x3, "i2s3"), /* mclk */ + sunxi_function(0x4, "spi1"), /* cs0 */ + sunxi_function(0x5, "i2c3"), /* sda */ + sunxi_function_irq_bank(0x6, 6, 5)), /* ph_eint5 */ + sunxi_pin(sunxi_pinctrl_pin(h, 6), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "uart2"), /* rx */ + sunxi_function(0x3, "i2s3"), /* bclk */ + sunxi_function(0x4, "spi1"), /* clk */ + sunxi_function(0x5, "i2c4"), /* sck */ + sunxi_function_irq_bank(0x6, 6, 6)), /* ph_eint6 */ + sunxi_pin(sunxi_pinctrl_pin(h, 7), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "uart2"), /* rts */ + sunxi_function(0x3, "i2s3"), /* sync */ + sunxi_function(0x4, "spi1"), /* mosi */ + sunxi_function(0x5, "i2c4"), /* sda */ + sunxi_function_irq_bank(0x6, 6, 7)), /* ph_eint7 */ + sunxi_pin(sunxi_pinctrl_pin(h, 8), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "uart2"), /* cts */ + sunxi_function(0x3, "i2s3"), /* do0 */ + sunxi_function(0x4, "spi1"), /* miso */ + sunxi_function(0x5, "i2s3"), /* di1 */ + sunxi_function_irq_bank(0x6, 6, 8)), /* ph_eint8 */ + sunxi_pin(sunxi_pinctrl_pin(h, 9), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x3, "i2s3"), /* di0 */ + sunxi_function(0x4, "spi1"), /* cs1 */ + sunxi_function(0x3, "i2s3"), /* do1 */ + sunxi_function_irq_bank(0x6, 6, 9)), /* ph_eint9 */ + sunxi_pin(sunxi_pinctrl_pin(h, 10), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x3, "ir_rx"), + sunxi_function_irq_bank(0x6, 6, 10)), /* ph_eint10 */ + /* hole */ + sunxi_pin(sunxi_pinctrl_pin(i, 0), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "emac0"), /* erxd3 */ + sunxi_function(0x3, "dmic"), /* clk */ + sunxi_function(0x4, "i2s0"), /* mclk */ + sunxi_function(0x5, "hdmi"), /* hscl */ + sunxi_function_irq_bank(0x6, 7, 0)), /* pi_eint0 */ + sunxi_pin(sunxi_pinctrl_pin(i, 1), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "emac0"), /* erxd2 */ + sunxi_function(0x3, "dmic"), /* data0 */ + sunxi_function(0x4, "i2s0"), /* bclk */ + sunxi_function(0x5, "hdmi"), /* hsda */ + sunxi_function_irq_bank(0x6, 7, 1)), /* pi_eint1 */ + sunxi_pin(sunxi_pinctrl_pin(i, 2), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "emac0"), /* erxd1 */ + sunxi_function(0x3, "dmic"), /* data1 */ + sunxi_function(0x4, "i2s0"), /* sync */ + sunxi_function(0x5, "hdmi"), /* hcec */ + sunxi_function_irq_bank(0x6, 7, 2)), /* pi_eint2 */ + sunxi_pin(sunxi_pinctrl_pin(i, 3), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "emac0"), /* erxd0 */ + sunxi_function(0x3, "dmic"), /* data2 */ + sunxi_function(0x4, "i2s0_dout0"), /* do0 */ + sunxi_function(0x5, "i2s0_din1"), /* di1 */ + sunxi_function_irq_bank(0x6, 7, 3)), /* pi_eint3 */ + sunxi_pin(sunxi_pinctrl_pin(i, 4), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "emac0"), /* erxck */ + sunxi_function(0x3, "dmic"), /* data3 */ + sunxi_function(0x4, "i2s0_din0"), /* di0 */ + sunxi_function(0x5, "i2s0_dout1"), /* do1 */ + sunxi_function_irq_bank(0x6, 7, 4)), /* pi_eint4 */ + sunxi_pin(sunxi_pinctrl_pin(i, 5), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "emac0"), /* erxctl */ + sunxi_function(0x3, "uart2"), /* tx */ + sunxi_function(0x4, "ts0"), /* clk */ + sunxi_function(0x5, "i2c0"), /* sck */ + sunxi_function_irq_bank(0x6, 7, 5)), /* pi_eint5 */ + sunxi_pin(sunxi_pinctrl_pin(i, 6), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "emac0"), /* enull */ + sunxi_function(0x3, "uart2"), /* rx */ + sunxi_function(0x4, "ts0"), /* err */ + sunxi_function(0x5, "i2c0"), /* sda */ + sunxi_function_irq_bank(0x6, 7, 6)), /* pi_eint6 */ + sunxi_pin(sunxi_pinctrl_pin(i, 7), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "emac0"), /* etxd3 */ + sunxi_function(0x3, "uart2"), /* rts */ + sunxi_function(0x4, "ts0"), /* sync */ + sunxi_function(0x5, "i2c1"), /* sck */ + sunxi_function_irq_bank(0x6, 7, 7)), /* pi_eint7 */ + sunxi_pin(sunxi_pinctrl_pin(i, 8), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "emac0"), /* etxd2 */ + sunxi_function(0x3, "uart2"), /* cts */ + sunxi_function(0x4, "ts0"), /* dvld */ + sunxi_function(0x5, "i2c1"), /* sda */ + sunxi_function_irq_bank(0x6, 7, 8)), /* pi_eint8 */ + sunxi_pin(sunxi_pinctrl_pin(i, 9), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "emac0"), /* etxd1 */ + sunxi_function(0x3, "uart3"), /* tx */ + sunxi_function(0x4, "ts0"), /* d0 */ + sunxi_function(0x5, "i2c2"), /* sck */ + sunxi_function_irq_bank(0x6, 7, 9)), /* pi_eint9 */ + sunxi_pin(sunxi_pinctrl_pin(i, 10), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "emac0"), /* etxd0 */ + sunxi_function(0x3, "uart3"), /* rx */ + sunxi_function(0x4, "ts0"), /* d1 */ + sunxi_function(0x5, "i2c2"), /* sda */ + sunxi_function_irq_bank(0x6, 7, 10)), /* pi_eint10 */ + sunxi_pin(sunxi_pinctrl_pin(i, 11), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "emac0"), /* etxck */ + sunxi_function(0x3, "uart3"), /* rts */ + sunxi_function(0x4, "ts0"), /* d2 */ + sunxi_function(0x5, "pwm1"), + sunxi_function_irq_bank(0x6, 7, 11)), /* pi_eint11 */ + sunxi_pin(sunxi_pinctrl_pin(i, 12), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "emac0"), /* etxctl */ + sunxi_function(0x3, "uart3"), /* cts */ + sunxi_function(0x4, "ts0"), /* d3 */ + sunxi_function(0x5, "pwm2"), + sunxi_function_irq_bank(0x6, 7, 12)), /* pi_eint12 */ + sunxi_pin(sunxi_pinctrl_pin(i, 13), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "emac0"), /* eclkin */ + sunxi_function(0x3, "uart4"), /* tx */ + sunxi_function(0x4, "ts0"), /* d4 */ + sunxi_function(0x5, "pwm3"), + sunxi_function_irq_bank(0x6, 7, 13)), /* pi_eint13 */ + sunxi_pin(sunxi_pinctrl_pin(i, 14), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "emac0"), /* mdc */ + sunxi_function(0x3, "uart4"), /* rx */ + sunxi_function(0x4, "ts0"), /* d5 */ + sunxi_function(0x5, "pwm4"), + sunxi_function_irq_bank(0x6, 7, 14)), /* pi_eint14 */ + sunxi_pin(sunxi_pinctrl_pin(i, 15), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "emac0"), /* mdio */ + sunxi_function(0x3, "uart4"), /* rts */ + sunxi_function(0x4, "ts0"), /* d6 */ + sunxi_function(0x5, "clock"), /* clk_fanout0 */ + sunxi_function_irq_bank(0x6, 7, 15)), /* pi_eint15 */ + sunxi_pin(sunxi_pinctrl_pin(i, 16), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "emac0"), /* ephy_clk */ + sunxi_function(0x3, "uart4"), /* cts */ + sunxi_function(0x4, "ts0"), /* d7 */ + sunxi_function(0x5, "clock"), /* clk_fanout1 */ + sunxi_function_irq_bank(0x6, 7, 16)), /* pi_eint16 */ +}; +static const unsigned int h616_irq_bank_map[] = { 0, 2, 3, 4, 5, 6, 7, 8 }; + +static const struct sunxi_pinctrl_desc h616_pinctrl_data = { + .pins = h616_pins, + .npins = array_size(h616_pins), + .irq_banks = array_size(h616_irq_bank_map), + .irq_bank_map = h616_irq_bank_map, + .irq_read_needs_mux = true, + .io_bias_cfg_variant = bias_voltage_pio_pow_mode_sel, +}; + +static int h616_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, &h616_pinctrl_data); +} + +static const struct of_device_id h616_pinctrl_match[] = { + { .compatible = "allwinner,sun50i-h616-pinctrl", }, + {} +}; + +static struct platform_driver h616_pinctrl_driver = { + .probe = h616_pinctrl_probe, + .driver = { + .name = "sun50i-h616-pinctrl", + .of_match_table = h616_pinctrl_match, + }, +}; +builtin_platform_driver(h616_pinctrl_driver);
|
Pin Controllers (pinctrl)
|
25adc29407fb3a064921af664f2e5134846312b9
|
andre przywara maxime ripard mripard kernel org
|
drivers
|
pinctrl
|
sunxi
|
pinctrl: sunxi: add support for the allwinner h616-r pin controller
|
there are only two pins left now, used to connect to the pmic via i2c.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for the allwinner h616-r pin controller
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['sunxi']
|
['kconfig', 'c', 'makefile']
| 3
| 62
| 0
|
--- diff --git a/drivers/pinctrl/sunxi/kconfig b/drivers/pinctrl/sunxi/kconfig --- a/drivers/pinctrl/sunxi/kconfig +++ b/drivers/pinctrl/sunxi/kconfig +config pinctrl_sun50i_h616_r + bool "support for the allwinner h616 r-pio" + default arm64 && arch_sunxi + select pinctrl_sunxi + diff --git a/drivers/pinctrl/sunxi/makefile b/drivers/pinctrl/sunxi/makefile --- a/drivers/pinctrl/sunxi/makefile +++ b/drivers/pinctrl/sunxi/makefile +obj-$(config_pinctrl_sun50i_h616_r) += pinctrl-sun50i-h616-r.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c +// spdx-license-identifier: gpl-2.0 +/* + * allwinner h616 r_pio pin controller driver + * + * copyright (c) 2020 arm ltd. + * based on former work, which is: + * copyright (c) 2017 icenowy zheng <icenowy@aosc.io> + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/reset.h> + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun50i_h616_r_pins[] = { + sunxi_pin(sunxi_pinctrl_pin(l, 0), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "s_rsb"), /* sck */ + sunxi_function(0x3, "s_i2c")), /* sck */ + sunxi_pin(sunxi_pinctrl_pin(l, 1), + sunxi_function(0x0, "gpio_in"), + sunxi_function(0x1, "gpio_out"), + sunxi_function(0x2, "s_rsb"), /* sda */ + sunxi_function(0x3, "s_i2c")), /* sda */ +}; + +static const struct sunxi_pinctrl_desc sun50i_h616_r_pinctrl_data = { + .pins = sun50i_h616_r_pins, + .npins = array_size(sun50i_h616_r_pins), + .pin_base = pl_base, +}; + +static int sun50i_h616_r_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun50i_h616_r_pinctrl_data); +} + +static const struct of_device_id sun50i_h616_r_pinctrl_match[] = { + { .compatible = "allwinner,sun50i-h616-r-pinctrl", }, + {} +}; + +static struct platform_driver sun50i_h616_r_pinctrl_driver = { + .probe = sun50i_h616_r_pinctrl_probe, + .driver = { + .name = "sun50i-h616-r-pinctrl", + .of_match_table = sun50i_h616_r_pinctrl_match, + }, +}; +builtin_platform_driver(sun50i_h616_r_pinctrl_driver);
|
Pin Controllers (pinctrl)
|
561c1cf17c465c6661b6fd3832df921458833e40
|
andre przywara maxime ripard mripard kernel org jernej skrabec jernej skrabec siol net
|
drivers
|
pinctrl
|
sunxi
|
pinctrl: tigerlake: add alder lake-p acpi id
|
intel alder lake-p pch has the same gpio hardware than tiger lake-lp pch but the acpi id is different. add this new acpi id to the list of supported devices.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add alder lake-p acpi id
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['tigerlake']
|
['c']
| 1
| 1
| 0
|
--- diff --git a/drivers/pinctrl/intel/pinctrl-tigerlake.c b/drivers/pinctrl/intel/pinctrl-tigerlake.c --- a/drivers/pinctrl/intel/pinctrl-tigerlake.c +++ b/drivers/pinctrl/intel/pinctrl-tigerlake.c + { "intc1055", (kernel_ulong_t)&tgllp_soc_data },
|
Pin Controllers (pinctrl)
|
0e793a4e283487378e9a5b7db37bc1781bc72fd7
|
andy shevchenko mika westerberg mika westerberg linux intel com
|
drivers
|
pinctrl
|
intel
|
pinctrl: remove coh901 driver
|
the st-ericsson u300 platform is getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove coh901 driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['c', 'h', 'kconfig', 'txt', 'makefile']
| 5
| 0
| 798
|
--- diff --git a/documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt b/documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt --- a/documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt +++ /dev/null -st-ericsson coh 901 571/3 gpio controller - -required properties: -- compatible: compatible property value should be "stericsson,gpio-coh901" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: the 0...n interrupts assigned to the different gpio ports/banks. diff --git a/drivers/pinctrl/kconfig b/drivers/pinctrl/kconfig --- a/drivers/pinctrl/kconfig +++ b/drivers/pinctrl/kconfig -config pinctrl_coh901 - bool "st-ericsson u300 coh 901 335/571 gpio" - depends on gpiolib && arch_u300 && pinctrl_u300 - select gpiolib_irqchip - help - say yes here to support gpio interface on st-ericsson u300. - the names of the two ip block variants supported are - coh 901 335 and coh 901 571/3. they contain 3, 5 or 7 - ports of 8 gpio pins each. - diff --git a/drivers/pinctrl/makefile b/drivers/pinctrl/makefile --- a/drivers/pinctrl/makefile +++ b/drivers/pinctrl/makefile -obj-$(config_pinctrl_coh901) += pinctrl-coh901.o diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c --- a/drivers/pinctrl/pinctrl-coh901.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * u300 gpio module. - * - * copyright (c) 2007-2012 st-ericsson ab - * coh 901 571/3 - used in db3210 (u365 2.0) and db3350 (u335 1.0) - * author: linus walleij <linus.walleij@linaro.org> - * author: jonas aaberg <jonas.aberg@stericsson.com> - */ -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <linux/io.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/platform_device.h> -#include <linux/gpio/driver.h> -#include <linux/slab.h> -#include <linux/pinctrl/consumer.h> -#include <linux/pinctrl/pinconf-generic.h> -#include "pinctrl-coh901.h" - -#define u300_gpio_port_stride (0x30) -/* - * control register 32bit (r/w) - * bit 15-9 (mask 0x0000fe00) contains the number of cores. 8*cores - * gives the number of gpio pins. - * bit 8-2 (mask 0x000001fc) contains the core version id. - */ -#define u300_gpio_cr (0x00) -#define u300_gpio_cr_sync_sel_enable (0x00000002ul) -#define u300_gpio_cr_block_clkrq_enable (0x00000001ul) -#define u300_gpio_pxpdir (0x04) -#define u300_gpio_pxpdor (0x08) -#define u300_gpio_pxpcr (0x0c) -#define u300_gpio_pxpcr_all_pins_mode_mask (0x0000fffful) -#define u300_gpio_pxpcr_pin_mode_mask (0x00000003ul) -#define u300_gpio_pxpcr_pin_mode_shift (0x00000002ul) -#define u300_gpio_pxpcr_pin_mode_input (0x00000000ul) -#define u300_gpio_pxpcr_pin_mode_output_push_pull (0x00000001ul) -#define u300_gpio_pxpcr_pin_mode_output_open_drain (0x00000002ul) -#define u300_gpio_pxpcr_pin_mode_output_open_source (0x00000003ul) -#define u300_gpio_pxper (0x10) -#define u300_gpio_pxper_all_pull_up_disable_mask (0x000000fful) -#define u300_gpio_pxper_pull_up_disable (0x00000001ul) -#define u300_gpio_pxiev (0x14) -#define u300_gpio_pxien (0x18) -#define u300_gpio_pxifr (0x1c) -#define u300_gpio_pxicr (0x20) -#define u300_gpio_pxicr_all_irq_config_mask (0x000000fful) -#define u300_gpio_pxicr_irq_config_mask (0x00000001ul) -#define u300_gpio_pxicr_irq_config_falling_edge (0x00000000ul) -#define u300_gpio_pxicr_irq_config_rising_edge (0x00000001ul) - -/* 8 bits per port, no version has more than 7 ports */ -#define u300_gpio_num_ports 7 -#define u300_gpio_pins_per_port 8 -#define u300_gpio_max (u300_gpio_pins_per_port * u300_gpio_num_ports) - -struct u300_gpio_port { - struct u300_gpio *gpio; - char name[8]; - int irq; - int number; - u8 toggle_edge_mode; -}; - -struct u300_gpio { - struct gpio_chip chip; - struct u300_gpio_port ports[u300_gpio_num_ports]; - struct clk *clk; - void __iomem *base; - struct device *dev; - u32 stride; - /* register offsets */ - u32 pcr; - u32 dor; - u32 dir; - u32 per; - u32 icr; - u32 ien; - u32 iev; -}; - -/* - * macro to expand to read a specific register found in the "gpio" - * struct. it requires the struct u300_gpio *gpio variable to exist in - * its context. it calculates the port offset from the given pin - * offset, muliplies by the port stride and adds the register offset - * so it provides a pointer to the desired register. - */ -#define u300_pin_reg(pin, reg) \ - (gpio->base + (pin >> 3) * gpio->stride + gpio->reg) - -/* - * provides a bitmask for a specific gpio pin inside an 8-bit gpio - * register. - */ -#define u300_pin_bit(pin) \ - (1 << (pin & 0x07)) - -struct u300_gpio_confdata { - u16 bias_mode; - bool output; - int outval; -}; - -#define u300_floating_input { \ - .bias_mode = pin_config_bias_high_impedance, \ - .output = false, \ -} - -#define u300_pull_up_input { \ - .bias_mode = pin_config_bias_pull_up, \ - .output = false, \ -} - -#define u300_output_low { \ - .output = true, \ - .outval = 0, \ -} - -#define u300_output_high { \ - .output = true, \ - .outval = 1, \ -} - -/* initial configuration */ -static const struct u300_gpio_confdata __initconst -bs335_gpio_config[u300_gpio_num_ports][u300_gpio_pins_per_port] = { - /* port 0, pins 0-7 */ - { - u300_floating_input, - u300_output_high, - u300_floating_input, - u300_output_low, - u300_output_low, - u300_output_low, - u300_output_low, - u300_output_low, - }, - /* port 1, pins 0-7 */ - { - u300_output_low, - u300_output_low, - u300_output_low, - u300_pull_up_input, - u300_floating_input, - u300_output_high, - u300_output_low, - u300_output_low, - }, - /* port 2, pins 0-7 */ - { - u300_floating_input, - u300_floating_input, - u300_floating_input, - u300_floating_input, - u300_output_low, - u300_pull_up_input, - u300_output_low, - u300_pull_up_input, - }, - /* port 3, pins 0-7 */ - { - u300_pull_up_input, - u300_output_low, - u300_floating_input, - u300_floating_input, - u300_floating_input, - u300_floating_input, - u300_floating_input, - u300_floating_input, - }, - /* port 4, pins 0-7 */ - { - u300_floating_input, - u300_floating_input, - u300_floating_input, - u300_floating_input, - u300_floating_input, - u300_floating_input, - u300_floating_input, - u300_floating_input, - }, - /* port 5, pins 0-7 */ - { - u300_floating_input, - u300_floating_input, - u300_floating_input, - u300_floating_input, - u300_floating_input, - u300_floating_input, - u300_floating_input, - u300_floating_input, - }, - /* port 6, pind 0-7 */ - { - u300_floating_input, - u300_floating_input, - u300_floating_input, - u300_floating_input, - u300_floating_input, - u300_floating_input, - u300_floating_input, - u300_floating_input, - } -}; - -static int u300_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - struct u300_gpio *gpio = gpiochip_get_data(chip); - - return !!(readl(u300_pin_reg(offset, dir)) & u300_pin_bit(offset)); -} - -static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value) -{ - struct u300_gpio *gpio = gpiochip_get_data(chip); - unsigned long flags; - u32 val; - - local_irq_save(flags); - - val = readl(u300_pin_reg(offset, dor)); - if (value) - writel(val | u300_pin_bit(offset), u300_pin_reg(offset, dor)); - else - writel(val & ~u300_pin_bit(offset), u300_pin_reg(offset, dor)); - - local_irq_restore(flags); -} - -static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -{ - struct u300_gpio *gpio = gpiochip_get_data(chip); - unsigned long flags; - u32 val; - - local_irq_save(flags); - val = readl(u300_pin_reg(offset, pcr)); - /* mask out this pin, note 2 bits per setting */ - val &= ~(u300_gpio_pxpcr_pin_mode_mask << ((offset & 0x07) << 1)); - writel(val, u300_pin_reg(offset, pcr)); - local_irq_restore(flags); - return 0; -} - -static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset, - int value) -{ - struct u300_gpio *gpio = gpiochip_get_data(chip); - unsigned long flags; - u32 oldmode; - u32 val; - - local_irq_save(flags); - val = readl(u300_pin_reg(offset, pcr)); - /* - * drive mode must be set by the special mode set function, set - * push/pull mode by default if no mode has been selected. - */ - oldmode = val & (u300_gpio_pxpcr_pin_mode_mask << - ((offset & 0x07) << 1)); - /* mode = 0 means input, else some mode is already set */ - if (oldmode == 0) { - val &= ~(u300_gpio_pxpcr_pin_mode_mask << - ((offset & 0x07) << 1)); - val |= (u300_gpio_pxpcr_pin_mode_output_push_pull - << ((offset & 0x07) << 1)); - writel(val, u300_pin_reg(offset, pcr)); - } - u300_gpio_set(chip, offset, value); - local_irq_restore(flags); - return 0; -} - -/* returning -einval means "supported but not available" */ -int u300_gpio_config_get(struct gpio_chip *chip, - unsigned offset, - unsigned long *config) -{ - struct u300_gpio *gpio = gpiochip_get_data(chip); - enum pin_config_param param = (enum pin_config_param) *config; - bool biasmode; - u32 drmode; - - /* one bit per pin, clamp to bool range */ - biasmode = !!(readl(u300_pin_reg(offset, per)) & u300_pin_bit(offset)); - - /* mask out the two bits for this pin and shift to bits 0,1 */ - drmode = readl(u300_pin_reg(offset, pcr)); - drmode &= (u300_gpio_pxpcr_pin_mode_mask << ((offset & 0x07) << 1)); - drmode >>= ((offset & 0x07) << 1); - - switch (param) { - case pin_config_bias_high_impedance: - *config = 0; - if (biasmode) - return 0; - else - return -einval; - break; - case pin_config_bias_pull_up: - *config = 0; - if (!biasmode) - return 0; - else - return -einval; - break; - case pin_config_drive_push_pull: - *config = 0; - if (drmode == u300_gpio_pxpcr_pin_mode_output_push_pull) - return 0; - else - return -einval; - break; - case pin_config_drive_open_drain: - *config = 0; - if (drmode == u300_gpio_pxpcr_pin_mode_output_open_drain) - return 0; - else - return -einval; - break; - case pin_config_drive_open_source: - *config = 0; - if (drmode == u300_gpio_pxpcr_pin_mode_output_open_source) - return 0; - else - return -einval; - break; - default: - break; - } - return -enotsupp; -} - -int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset, - enum pin_config_param param) -{ - struct u300_gpio *gpio = gpiochip_get_data(chip); - unsigned long flags; - u32 val; - - local_irq_save(flags); - switch (param) { - case pin_config_bias_disable: - case pin_config_bias_high_impedance: - val = readl(u300_pin_reg(offset, per)); - writel(val | u300_pin_bit(offset), u300_pin_reg(offset, per)); - break; - case pin_config_bias_pull_up: - val = readl(u300_pin_reg(offset, per)); - writel(val & ~u300_pin_bit(offset), u300_pin_reg(offset, per)); - break; - case pin_config_drive_push_pull: - val = readl(u300_pin_reg(offset, pcr)); - val &= ~(u300_gpio_pxpcr_pin_mode_mask - << ((offset & 0x07) << 1)); - val |= (u300_gpio_pxpcr_pin_mode_output_push_pull - << ((offset & 0x07) << 1)); - writel(val, u300_pin_reg(offset, pcr)); - break; - case pin_config_drive_open_drain: - val = readl(u300_pin_reg(offset, pcr)); - val &= ~(u300_gpio_pxpcr_pin_mode_mask - << ((offset & 0x07) << 1)); - val |= (u300_gpio_pxpcr_pin_mode_output_open_drain - << ((offset & 0x07) << 1)); - writel(val, u300_pin_reg(offset, pcr)); - break; - case pin_config_drive_open_source: - val = readl(u300_pin_reg(offset, pcr)); - val &= ~(u300_gpio_pxpcr_pin_mode_mask - << ((offset & 0x07) << 1)); - val |= (u300_gpio_pxpcr_pin_mode_output_open_source - << ((offset & 0x07) << 1)); - writel(val, u300_pin_reg(offset, pcr)); - break; - default: - local_irq_restore(flags); - dev_err(gpio->dev, "illegal configuration requested "); - return -einval; - } - local_irq_restore(flags); - return 0; -} - -static const struct gpio_chip u300_gpio_chip = { - .label = "u300-gpio-chip", - .owner = this_module, - .request = gpiochip_generic_request, - .free = gpiochip_generic_free, - .get = u300_gpio_get, - .set = u300_gpio_set, - .direction_input = u300_gpio_direction_input, - .direction_output = u300_gpio_direction_output, -}; - -static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset) -{ - u32 val; - - val = readl(u300_pin_reg(offset, icr)); - /* set mode depending on state */ - if (u300_gpio_get(&gpio->chip, offset)) { - /* high now, let's trigger on falling edge next then */ - writel(val & ~u300_pin_bit(offset), u300_pin_reg(offset, icr)); - dev_dbg(gpio->dev, "next irq on falling edge on pin %d ", - offset); - } else { - /* low now, let's trigger on rising edge next then */ - writel(val | u300_pin_bit(offset), u300_pin_reg(offset, icr)); - dev_dbg(gpio->dev, "next irq on rising edge on pin %d ", - offset); - } -} - -static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger) -{ - struct gpio_chip *chip = irq_data_get_irq_chip_data(d); - struct u300_gpio *gpio = gpiochip_get_data(chip); - struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3]; - int offset = d->hwirq; - u32 val; - - if ((trigger & irqf_trigger_rising) && - (trigger & irqf_trigger_falling)) { - /* - * the gpio block can only trigger on falling or rising edges, - * not both. so we need to toggle the mode whenever the pin - * goes from one state to the other with a special state flag - */ - dev_dbg(gpio->dev, - "trigger on both rising and falling edge on pin %d ", - offset); - port->toggle_edge_mode |= u300_pin_bit(offset); - u300_toggle_trigger(gpio, offset); - } else if (trigger & irqf_trigger_rising) { - dev_dbg(gpio->dev, "trigger on rising edge on pin %d ", - offset); - val = readl(u300_pin_reg(offset, icr)); - writel(val | u300_pin_bit(offset), u300_pin_reg(offset, icr)); - port->toggle_edge_mode &= ~u300_pin_bit(offset); - } else if (trigger & irqf_trigger_falling) { - dev_dbg(gpio->dev, "trigger on falling edge on pin %d ", - offset); - val = readl(u300_pin_reg(offset, icr)); - writel(val & ~u300_pin_bit(offset), u300_pin_reg(offset, icr)); - port->toggle_edge_mode &= ~u300_pin_bit(offset); - } - - return 0; -} - -static void u300_gpio_irq_enable(struct irq_data *d) -{ - struct gpio_chip *chip = irq_data_get_irq_chip_data(d); - struct u300_gpio *gpio = gpiochip_get_data(chip); - struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3]; - int offset = d->hwirq; - u32 val; - unsigned long flags; - - dev_dbg(gpio->dev, "enable irq for hwirq %lu on port %s, offset %d ", - d->hwirq, port->name, offset); - local_irq_save(flags); - val = readl(u300_pin_reg(offset, ien)); - writel(val | u300_pin_bit(offset), u300_pin_reg(offset, ien)); - local_irq_restore(flags); -} - -static void u300_gpio_irq_disable(struct irq_data *d) -{ - struct gpio_chip *chip = irq_data_get_irq_chip_data(d); - struct u300_gpio *gpio = gpiochip_get_data(chip); - int offset = d->hwirq; - u32 val; - unsigned long flags; - - local_irq_save(flags); - val = readl(u300_pin_reg(offset, ien)); - writel(val & ~u300_pin_bit(offset), u300_pin_reg(offset, ien)); - local_irq_restore(flags); -} - -static struct irq_chip u300_gpio_irqchip = { - .name = "u300-gpio-irqchip", - .irq_enable = u300_gpio_irq_enable, - .irq_disable = u300_gpio_irq_disable, - .irq_set_type = u300_gpio_irq_type, -}; - -static void u300_gpio_irq_handler(struct irq_desc *desc) -{ - unsigned int irq = irq_desc_get_irq(desc); - struct irq_chip *parent_chip = irq_desc_get_chip(desc); - struct gpio_chip *chip = irq_desc_get_handler_data(desc); - struct u300_gpio *gpio = gpiochip_get_data(chip); - struct u300_gpio_port *port = &gpio->ports[irq - chip->base]; - int pinoffset = port->number << 3; /* get the right stride */ - unsigned long val; - - chained_irq_enter(parent_chip, desc); - - /* read event register */ - val = readl(u300_pin_reg(pinoffset, iev)); - /* mask relevant bits */ - val &= 0xffu; /* 8 bits per port */ - /* ack irq (clear event) */ - writel(val, u300_pin_reg(pinoffset, iev)); - - /* call irq handler */ - if (val != 0) { - int irqoffset; - - for_each_set_bit(irqoffset, &val, u300_gpio_pins_per_port) { - int offset = pinoffset + irqoffset; - int pin_irq = irq_find_mapping(chip->irq.domain, offset); - - dev_dbg(gpio->dev, "gpio irq %d on pin %d ", - pin_irq, offset); - generic_handle_irq(pin_irq); - /* - * triggering irq on both rising and falling edge - * needs mockery - */ - if (port->toggle_edge_mode & u300_pin_bit(offset)) - u300_toggle_trigger(gpio, offset); - } - } - - chained_irq_exit(parent_chip, desc); -} - -static void __init u300_gpio_init_pin(struct u300_gpio *gpio, - int offset, - const struct u300_gpio_confdata *conf) -{ - /* set mode: input or output */ - if (conf->output) { - u300_gpio_direction_output(&gpio->chip, offset, conf->outval); - - /* deactivate bias mode for output */ - u300_gpio_config_set(&gpio->chip, offset, - pin_config_bias_high_impedance); - - /* set drive mode for output */ - u300_gpio_config_set(&gpio->chip, offset, - pin_config_drive_push_pull); - - dev_dbg(gpio->dev, "set up pin %d as output, value: %d ", - offset, conf->outval); - } else { - u300_gpio_direction_input(&gpio->chip, offset); - - /* always set output low on input pins */ - u300_gpio_set(&gpio->chip, offset, 0); - - /* set bias mode for input */ - u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode); - - dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x ", - offset, conf->bias_mode); - } -} - -static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio) -{ - int i, j; - - /* write default config and values to all pins */ - for (i = 0; i < u300_gpio_num_ports; i++) { - for (j = 0; j < 8; j++) { - const struct u300_gpio_confdata *conf; - int offset = (i*8) + j; - - conf = &bs335_gpio_config[i][j]; - u300_gpio_init_pin(gpio, offset, conf); - } - } -} - -/* - * here we map a gpio in the local gpio_chip pin space to a pin in - * the local pinctrl pin space. the pin controller used is - * pinctrl-u300. - */ -struct coh901_pinpair { - unsigned int offset; - unsigned int pin_base; -}; - -#define coh901_pinrange(a, b) { .offset = a, .pin_base = b } - -static struct coh901_pinpair coh901_pintable[] = { - coh901_pinrange(10, 426), - coh901_pinrange(11, 180), - coh901_pinrange(12, 165), /* ms/mmc card insertion */ - coh901_pinrange(13, 179), - coh901_pinrange(14, 178), - coh901_pinrange(16, 194), - coh901_pinrange(17, 193), - coh901_pinrange(18, 192), - coh901_pinrange(19, 191), - coh901_pinrange(20, 186), - coh901_pinrange(21, 185), - coh901_pinrange(22, 184), - coh901_pinrange(23, 183), - coh901_pinrange(24, 182), - coh901_pinrange(25, 181), -}; - -static int __init u300_gpio_probe(struct platform_device *pdev) -{ - struct u300_gpio *gpio; - struct gpio_irq_chip *girq; - int err = 0; - int portno; - u32 val; - u32 ifr; - int i; - - gpio = devm_kzalloc(&pdev->dev, sizeof(struct u300_gpio), gfp_kernel); - if (gpio == null) - return -enomem; - - gpio->chip = u300_gpio_chip; - gpio->chip.ngpio = u300_gpio_num_ports * u300_gpio_pins_per_port; - gpio->chip.parent = &pdev->dev; - gpio->chip.base = 0; - gpio->dev = &pdev->dev; - - gpio->base = devm_platform_ioremap_resource(pdev, 0); - if (is_err(gpio->base)) - return ptr_err(gpio->base); - - gpio->clk = devm_clk_get(gpio->dev, null); - if (is_err(gpio->clk)) { - err = ptr_err(gpio->clk); - dev_err(gpio->dev, "could not get gpio clock "); - return err; - } - - err = clk_prepare_enable(gpio->clk); - if (err) { - dev_err(gpio->dev, "could not enable gpio clock "); - return err; - } - - dev_info(gpio->dev, - "initializing gpio controller coh 901 571/3 "); - gpio->stride = u300_gpio_port_stride; - gpio->pcr = u300_gpio_pxpcr; - gpio->dor = u300_gpio_pxpdor; - gpio->dir = u300_gpio_pxpdir; - gpio->per = u300_gpio_pxper; - gpio->icr = u300_gpio_pxicr; - gpio->ien = u300_gpio_pxien; - gpio->iev = u300_gpio_pxiev; - ifr = u300_gpio_pxifr; - - val = readl(gpio->base + u300_gpio_cr); - dev_info(gpio->dev, "coh901571/3 block version: %d, " \ - "number of cores: %d totalling %d pins ", - ((val & 0x000001fc) >> 2), - ((val & 0x0000fe00) >> 9), - ((val & 0x0000fe00) >> 9) * 8); - writel(u300_gpio_cr_block_clkrq_enable, - gpio->base + u300_gpio_cr); - u300_gpio_init_coh901571(gpio); - - girq = &gpio->chip.irq; - girq->chip = &u300_gpio_irqchip; - girq->parent_handler = u300_gpio_irq_handler; - girq->num_parents = u300_gpio_num_ports; - girq->parents = devm_kcalloc(gpio->dev, u300_gpio_num_ports, - sizeof(*girq->parents), - gfp_kernel); - if (!girq->parents) { - err = -enomem; - goto err_dis_clk; - } - for (portno = 0 ; portno < u300_gpio_num_ports; portno++) { - struct u300_gpio_port *port = &gpio->ports[portno]; - - snprintf(port->name, 8, "gpio%d", portno); - port->number = portno; - port->gpio = gpio; - - port->irq = platform_get_irq(pdev, portno); - girq->parents[portno] = port->irq; - - /* turns off irq force (test register) for this port */ - writel(0x0, gpio->base + portno * gpio->stride + ifr); - } - girq->default_type = irq_type_edge_falling; - girq->handler = handle_simple_irq; -#ifdef config_of_gpio - gpio->chip.of_node = pdev->dev.of_node; -#endif - err = gpiochip_add_data(&gpio->chip, gpio); - if (err) { - dev_err(gpio->dev, "unable to add gpiochip: %d ", err); - goto err_dis_clk; - } - - /* - * add pinctrl pin ranges, the pin controller must be registered - * at this point - */ - for (i = 0; i < array_size(coh901_pintable); i++) { - struct coh901_pinpair *p = &coh901_pintable[i]; - - err = gpiochip_add_pin_range(&gpio->chip, "pinctrl-u300", - p->offset, p->pin_base, 1); - if (err) - goto err_no_range; - } - - platform_set_drvdata(pdev, gpio); - - return 0; - -err_no_range: - gpiochip_remove(&gpio->chip); -err_dis_clk: - clk_disable_unprepare(gpio->clk); - dev_err(&pdev->dev, "module error:%d ", err); - return err; -} - -static int __exit u300_gpio_remove(struct platform_device *pdev) -{ - struct u300_gpio *gpio = platform_get_drvdata(pdev); - - /* turn off the gpio block */ - writel(0x00000000u, gpio->base + u300_gpio_cr); - - gpiochip_remove(&gpio->chip); - clk_disable_unprepare(gpio->clk); - return 0; -} - -static const struct of_device_id u300_gpio_match[] = { - { .compatible = "stericsson,gpio-coh901" }, - {}, -}; - -static struct platform_driver u300_gpio_driver = { - .driver = { - .name = "u300-gpio", - .of_match_table = u300_gpio_match, - }, - .remove = __exit_p(u300_gpio_remove), -}; - -static int __init u300_gpio_init(void) -{ - return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe); -} - -static void __exit u300_gpio_exit(void) -{ - platform_driver_unregister(&u300_gpio_driver); -} - -arch_initcall(u300_gpio_init); -module_exit(u300_gpio_exit); - -module_author("linus walleij <linus.walleij@stericsson.com>"); -module_description("st-ericsson ab coh 901 335/coh 901 571/3 gpio driver"); -module_license("gpl"); diff --git a/drivers/pinctrl/pinctrl-coh901.h b/drivers/pinctrl/pinctrl-coh901.h --- a/drivers/pinctrl/pinctrl-coh901.h +++ /dev/null -/* spdx-license-identifier: gpl-2.0 */ -int u300_gpio_config_get(struct gpio_chip *chip, - unsigned offset, - unsigned long *config); -int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset, - enum pin_config_param param);
|
Pin Controllers (pinctrl)
|
5817364a90c944cbe72c657e53495d41868013f4
|
arnd bergmann
|
documentation
|
devicetree
|
bindings, gpio
|
pinctrl: remove sirf atlas/prima drivers
|
the csr sirf prima2/atlas platforms are getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove sirf atlas/prima drivers
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['c', 'h', 'kconfig', 'txt', 'makefile']
| 10
| 0
| 9,610
|
--- diff --git a/documentation/devicetree/bindings/gpio/gpio-atlas7.txt b/documentation/devicetree/bindings/gpio/gpio-atlas7.txt --- a/documentation/devicetree/bindings/gpio/gpio-atlas7.txt +++ /dev/null -csr sirfatlas7 gpio controller bindings - -required properties: -- compatible : "sirf,atlas7-gpio" -- reg : address range of the pinctrl registers -- interrupts : interrupts used by every gpio group -- gpio-banks : how many gpio banks on this controller -- gpio-controller : indicates this device is a gpio controller -- interrupt-controller : marks the device node as an interrupt controller - -the gpio controller also acts as an interrupt controller. it uses the default -two cells specifier as described in documentation/devicetree/bindings/ -interrupt-controller/interrupts.txt. - -example: - - gpio_0: gpio_mediam@17040000 { - compatible = "sirf,atlas7-gpio"; - reg = <0x17040000 0x1000>; - interrupts = <0 13 0>, <0 14 0>; - - #gpio-cells = <2>; - #interrupt-cells = <2>; - - gpio-controller; - interrupt-controller; - - gpio-banks = <2>; - gpio-ranges = <&pinctrl 0 0 0>, - <&pinctrl 32 0 0>; - gpio-ranges-group-names = "lvds_gpio_grp", - "uart_nand_gpio_grp"; - }; - - leds { - compatible = "gpio-leds"; - - led1 { - gpios = <&gpio_1 15 0>; - ... - }; - - led2 { - gpios = <&gpio_2 34 0>; - ... - }; - }; - -please refer to gpio.txt in this directory for details of the common -gpio properties used by devices. diff --git a/documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt b/documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt --- a/documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt +++ /dev/null -csr sirfatlas7 pinmux controller - -required properties: -- compatible : "sirf,atlas7-ioc" -- reg : address range of the pinctrl registers - -for example, pinctrl might have properties like the following: - pinctrl: ioc@18880000 { - compatible = "sirf,atlas7-ioc"; - reg = <0x18880000 0x1000>; - - a_ac97_pmx: ac97@0 { - ac97 { - groups = "audio_ac97_grp"; - function = "audio_ac97"; - }; - }; - - ... - - sd2_pmx: sd2@0 { - sd2 { - groups = "sd2_grp0"; - function = "sd2"; - }; - }; - - ... - - - sample0_cfg: sample0@0 { - sample0 { - pins = "ldd_0", "ldd_1"; - bias-pull-up; - }; - }; - - sample1_cfg: sample1@0 { - sample1 { - pins = "ldd_2", "ldd_3"; - input-schmitt-enable; - }; - }; - - sample2_cfg: sample2@0 { - sample2 { - groups = "uart4_nopause_grp"; - bias-pull-down; - }; - }; - - sample3_cfg: sample3@0 { - sample3 { - pins = "ldd_4", "ldd_5"; - drive-strength = <2>; - }; - }; - }; - -please refer to pinctrl-bindings.txt in this directory for details of the common -pinctrl bindings used by client devices. - -sirfatlas7's pinmux nodes act as a container for an arbitrary number of subnodes. -each of these subnodes represents some desired configuration for a group of pins. - -required subnode-properties: -- groups : an array of strings. each string contains the name of a group. -- function: a string containing the name of the function to mux to the - group. - - valid values for group and function names can be found from looking at the - group and function arrays in driver files: - drivers/pinctrl/pinctrl-sirf.c - -for example, pinctrl might have subnodes like the following: - sd0_pmx: sd0@0 { - sd0 { - groups = "sd0_grp"; - function = "sd0"; - }; - }; - - sd1_pmx0: sd1@0 { - sd1 { - groups = "sd1_grp0"; - function = "sd1_m0"; - }; - }; - - sd1_pmx1: sd1@1 { - sd1 { - groups = "sd1_grp1"; - function = "sd1_m1"; - }; - }; - -for a specific board, if it wants to use sd1, -it can add the following to its board-specific .dts file. -sd1: sd@12340000 { - pinctrl-names = "default"; - pinctrl-0 = <&sd1_pmx0>; -} - -or - -sd1: sd@12340000 { - pinctrl-names = "default"; - pinctrl-0 = <&sd1_pmx1>; -} diff --git a/drivers/pinctrl/kconfig b/drivers/pinctrl/kconfig --- a/drivers/pinctrl/kconfig +++ b/drivers/pinctrl/kconfig -config pinctrl_sirf - bool "csr sirfprimaii pin controller driver" - depends on arch_sirf - select pinmux - select pinconf - select generic_pinconf - select gpiolib_irqchip - diff --git a/drivers/pinctrl/makefile b/drivers/pinctrl/makefile --- a/drivers/pinctrl/makefile +++ b/drivers/pinctrl/makefile -obj-$(config_pinctrl_sirf) += sirf/ diff --git a/drivers/pinctrl/sirf/makefile b/drivers/pinctrl/sirf/makefile --- a/drivers/pinctrl/sirf/makefile +++ /dev/null -# spdx-license-identifier: gpl-2.0-only -# csr sirfsoc pinmux support - -obj-y += pinctrl-sirf.o -obj-y += pinctrl-prima2.o -obj-y += pinctrl-atlas6.o -obj-y += pinctrl-atlas7.o diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c --- a/drivers/pinctrl/sirf/pinctrl-atlas6.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-or-later -/* - * pinctrl pads, groups, functions for csr sirfatlasvi - * - * copyright (c) 2011 - 2014 cambridge silicon radio limited, a csr plc group - * company. - */ - -#include <linux/pinctrl/pinctrl.h> -#include <linux/bitops.h> - -#include "pinctrl-sirf.h" - -/* - * pad list for the pinmux subsystem - * refer to atlasvi_io_table_v0.93.xls - */ -static const struct pinctrl_pin_desc sirfsoc_pads[] = { - pinctrl_pin(0, "gpio0-0"), - pinctrl_pin(1, "gpio0-1"), - pinctrl_pin(2, "gpio0-2"), - pinctrl_pin(3, "gpio0-3"), - pinctrl_pin(4, "pwm0"), - pinctrl_pin(5, "pwm1"), - pinctrl_pin(6, "pwm2"), - pinctrl_pin(7, "pwm3"), - pinctrl_pin(8, "warm_rst_b"), - pinctrl_pin(9, "odo_0"), - pinctrl_pin(10, "odo_1"), - pinctrl_pin(11, "dr_dir"), - pinctrl_pin(12, "rts_0"), - pinctrl_pin(13, "scl_1"), - pinctrl_pin(14, "ntrst"), - pinctrl_pin(15, "sda_1"), - pinctrl_pin(16, "x_ldd[16]"), - pinctrl_pin(17, "x_ldd[17]"), - pinctrl_pin(18, "x_ldd[18]"), - pinctrl_pin(19, "x_ldd[19]"), - pinctrl_pin(20, "x_ldd[20]"), - pinctrl_pin(21, "x_ldd[21]"), - pinctrl_pin(22, "x_ldd[22]"), - pinctrl_pin(23, "x_ldd[23]"), - pinctrl_pin(24, "gps_sgn"), - pinctrl_pin(25, "gps_mag"), - pinctrl_pin(26, "gps_clk"), - pinctrl_pin(27, "sd_cd_b_2"), - pinctrl_pin(28, "sd_vcc_on_2"), - pinctrl_pin(29, "sd_wp_b_2"), - pinctrl_pin(30, "sd_clk_3"), - pinctrl_pin(31, "sd_cmd_3"), - - pinctrl_pin(32, "x_sd_dat_3[0]"), - pinctrl_pin(33, "x_sd_dat_3[1]"), - pinctrl_pin(34, "x_sd_dat_3[2]"), - pinctrl_pin(35, "x_sd_dat_3[3]"), - pinctrl_pin(36, "usb_clk"), - pinctrl_pin(37, "usb_dir"), - pinctrl_pin(38, "usb_nxt"), - pinctrl_pin(39, "usb_stp"), - pinctrl_pin(40, "usb_dat[7]"), - pinctrl_pin(41, "usb_dat[6]"), - pinctrl_pin(42, "x_cko_1"), - pinctrl_pin(43, "spi_clk_1"), - pinctrl_pin(44, "spi_dout_1"), - pinctrl_pin(45, "spi_din_1"), - pinctrl_pin(46, "spi_en_1"), - pinctrl_pin(47, "x_txd_1"), - pinctrl_pin(48, "x_txd_2"), - pinctrl_pin(49, "x_rxd_1"), - pinctrl_pin(50, "x_rxd_2"), - pinctrl_pin(51, "x_usclk_0"), - pinctrl_pin(52, "x_utxd_0"), - pinctrl_pin(53, "x_urxd_0"), - pinctrl_pin(54, "x_utfs_0"), - pinctrl_pin(55, "x_urfs_0"), - pinctrl_pin(56, "usb_dat5"), - pinctrl_pin(57, "usb_dat4"), - pinctrl_pin(58, "usb_dat3"), - pinctrl_pin(59, "usb_dat2"), - pinctrl_pin(60, "usb_dat1"), - pinctrl_pin(61, "usb_dat0"), - pinctrl_pin(62, "x_ldd[14]"), - pinctrl_pin(63, "x_ldd[15]"), - - pinctrl_pin(64, "x_gps_gpio"), - pinctrl_pin(65, "x_ldd[13]"), - pinctrl_pin(66, "x_df_we_b"), - pinctrl_pin(67, "x_df_re_b"), - pinctrl_pin(68, "x_txd_0"), - pinctrl_pin(69, "x_rxd_0"), - pinctrl_pin(70, "x_l_lck"), - pinctrl_pin(71, "x_l_fck"), - pinctrl_pin(72, "x_l_de"), - pinctrl_pin(73, "x_ldd[0]"), - pinctrl_pin(74, "x_ldd[1]"), - pinctrl_pin(75, "x_ldd[2]"), - pinctrl_pin(76, "x_ldd[3]"), - pinctrl_pin(77, "x_ldd[4]"), - pinctrl_pin(78, "x_cko_0"), - pinctrl_pin(79, "x_ldd[5]"), - pinctrl_pin(80, "x_ldd[6]"), - pinctrl_pin(81, "x_ldd[7]"), - pinctrl_pin(82, "x_ldd[8]"), - pinctrl_pin(83, "x_ldd[9]"), - pinctrl_pin(84, "x_ldd[10]"), - pinctrl_pin(85, "x_ldd[11]"), - pinctrl_pin(86, "x_ldd[12]"), - pinctrl_pin(87, "x_vip_vsync"), - pinctrl_pin(88, "x_vip_hsync"), - pinctrl_pin(89, "x_vip_pxclk"), - pinctrl_pin(90, "x_sda_0"), - pinctrl_pin(91, "x_scl_0"), - pinctrl_pin(92, "x_df_ry_by"), - pinctrl_pin(93, "x_df_cs_b[1]"), - pinctrl_pin(94, "x_df_cs_b[0]"), - pinctrl_pin(95, "x_l_pclk"), - - pinctrl_pin(96, "x_df_dqs"), - pinctrl_pin(97, "x_df_wp_b"), - pinctrl_pin(98, "ac97_sync"), - pinctrl_pin(99, "ac97_bit_clk "), - pinctrl_pin(100, "ac97_dout"), - pinctrl_pin(101, "ac97_din"), - pinctrl_pin(102, "x_rtc_io"), - - pinctrl_pin(103, "x_usb1_dp"), - pinctrl_pin(104, "x_usb1_dn"), -}; - -static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { - { - .group = 1, - .mask = bit(30) | bit(31), - }, { - .group = 2, - .mask = bit(1) | bit(6) | bit(7) | bit(8) | bit(9) | - bit(10) | bit(11) | bit(12) | bit(13) | bit(15) | - bit(16) | bit(17) | bit(18) | bit(19) | - bit(20) | bit(21) | bit(22) | bit(31), - }, -}; - -static const struct sirfsoc_padmux lcd_16bits_padmux = { - .muxmask_counts = array_size(lcd_16bits_sirfsoc_muxmask), - .muxmask = lcd_16bits_sirfsoc_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(4), - .funcval = 0, -}; - -static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75, - 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 }; - -static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = { - { - .group = 2, - .mask = bit(1) | bit(6) | bit(7) | bit(8) | bit(9) | - bit(10) | bit(11) | bit(12) | bit(13) | bit(15) | - bit(16) | bit(17) | bit(18) | bit(19) | - bit(20) | bit(21) | bit(22) | bit(31), - }, { - .group = 1, - .mask = bit(30) | bit(31), - }, { - .group = 0, - .mask = bit(16) | bit(17), - }, -}; - -static const struct sirfsoc_padmux lcd_18bits_padmux = { - .muxmask_counts = array_size(lcd_18bits_muxmask), - .muxmask = lcd_18bits_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(4) | bit(15), - .funcval = 0, -}; - -static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73, - 74, 75, 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 }; - -static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = { - { - .group = 2, - .mask = bit(1) | bit(6) | bit(7) | bit(8) | bit(9) | - bit(10) | bit(11) | bit(12) | bit(13) | bit(15) | - bit(16) | bit(17) | bit(18) | bit(19) | - bit(20) | bit(21) | bit(22) | bit(31), - }, { - .group = 1, - .mask = bit(30) | bit(31), - }, { - .group = 0, - .mask = bit(16) | bit(17) | bit(18) | bit(19) | bit(20) | - bit(21) | bit(22) | bit(23), - }, -}; - -static const struct sirfsoc_padmux lcd_24bits_padmux = { - .muxmask_counts = array_size(lcd_24bits_muxmask), - .muxmask = lcd_24bits_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(4) | bit(15), - .funcval = 0, -}; - -static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62, - 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 84, - 85, 86, 95}; - -static const struct sirfsoc_muxmask lcdrom_muxmask[] = { - { - .group = 2, - .mask = bit(1) | bit(6) | bit(7) | bit(8) | bit(9) | bit(10) | - bit(11) | bit(12) | bit(13) | bit(15) | bit(16) | - bit(17) | bit(18) | bit(19) | - bit(20) | bit(21) | bit(22) | bit(31), - }, { - .group = 1, - .mask = bit(30) | bit(31), - }, { - .group = 0, - .mask = bit(8), - }, -}; - -static const struct sirfsoc_padmux lcdrom_padmux = { - .muxmask_counts = array_size(lcdrom_muxmask), - .muxmask = lcdrom_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(4), - .funcval = bit(4), -}; - -static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75, - 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95}; - -static const struct sirfsoc_muxmask uart0_muxmask[] = { - { - .group = 0, - .mask = bit(12), - }, { - .group = 1, - .mask = bit(23), - }, { - .group = 2, - .mask = bit(4) | bit(5), - }, -}; - -static const struct sirfsoc_padmux uart0_padmux = { - .muxmask_counts = array_size(uart0_muxmask), - .muxmask = uart0_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(9), - .funcval = bit(9), -}; - -static const unsigned uart0_pins[] = { 12, 55, 68, 69 }; - -static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = { - { - .group = 2, - .mask = bit(4) | bit(5), - }, -}; - -static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = { - .muxmask_counts = array_size(uart0_nostreamctrl_muxmask), - .muxmask = uart0_nostreamctrl_muxmask, -}; - -static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 }; - -static const struct sirfsoc_muxmask uart1_muxmask[] = { - { - .group = 1, - .mask = bit(15) | bit(17), - }, -}; - -static const struct sirfsoc_padmux uart1_padmux = { - .muxmask_counts = array_size(uart1_muxmask), - .muxmask = uart1_muxmask, -}; - -static const unsigned uart1_pins[] = { 47, 49 }; - -static const struct sirfsoc_muxmask uart2_muxmask[] = { - { - .group = 0, - .mask = bit(10) | bit(14), - }, { - .group = 1, - .mask = bit(16) | bit(18), - }, -}; - -static const struct sirfsoc_padmux uart2_padmux = { - .muxmask_counts = array_size(uart2_muxmask), - .muxmask = uart2_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(10), - .funcval = bit(10), -}; - -static const unsigned uart2_pins[] = { 10, 14, 48, 50 }; - -static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = { - { - .group = 1, - .mask = bit(16) | bit(18), - }, -}; - -static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = { - .muxmask_counts = array_size(uart2_nostreamctrl_muxmask), - .muxmask = uart2_nostreamctrl_muxmask, -}; - -static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 }; - -static const struct sirfsoc_muxmask sdmmc3_muxmask[] = { - { - .group = 0, - .mask = bit(30) | bit(31), - }, { - .group = 1, - .mask = bit(0) | bit(1) | bit(2) | bit(3), - }, -}; - -static const struct sirfsoc_padmux sdmmc3_padmux = { - .muxmask_counts = array_size(sdmmc3_muxmask), - .muxmask = sdmmc3_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(7), - .funcval = 0, -}; - -static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 }; - -static const struct sirfsoc_muxmask spi0_muxmask[] = { - { - .group = 0, - .mask = bit(30), - }, { - .group = 1, - .mask = bit(0) | bit(2) | bit(3), - }, -}; - -static const struct sirfsoc_padmux spi0_padmux = { - .muxmask_counts = array_size(spi0_muxmask), - .muxmask = spi0_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(7), - .funcval = bit(7), -}; - -static const unsigned spi0_pins[] = { 30, 32, 34, 35 }; - -static const struct sirfsoc_muxmask cko1_muxmask[] = { - { - .group = 1, - .mask = bit(10), - }, -}; - -static const struct sirfsoc_padmux cko1_padmux = { - .muxmask_counts = array_size(cko1_muxmask), - .muxmask = cko1_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(3), - .funcval = 0, -}; - -static const unsigned cko1_pins[] = { 42 }; - -static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = { - { - .group = 1, - .mask = bit(10), - }, -}; - -static const struct sirfsoc_padmux i2s_mclk_padmux = { - .muxmask_counts = array_size(i2s_mclk_muxmask), - .muxmask = i2s_mclk_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(3), - .funcval = bit(3), -}; - -static const unsigned i2s_mclk_pins[] = { 42 }; - -static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = { - { - .group = 1, - .mask = bit(19), - }, -}; - -static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = { - .muxmask_counts = array_size(i2s_ext_clk_input_muxmask), - .muxmask = i2s_ext_clk_input_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(2), - .funcval = bit(2), -}; - -static const unsigned i2s_ext_clk_input_pins[] = { 51 }; - -static const struct sirfsoc_muxmask i2s_muxmask[] = { - { - .group = 3, - .mask = bit(2) | bit(3) | bit(4) | bit(5), - }, -}; - -static const struct sirfsoc_padmux i2s_padmux = { - .muxmask_counts = array_size(i2s_muxmask), - .muxmask = i2s_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, -}; - -static const unsigned i2s_pins[] = { 98, 99, 100, 101 }; - -static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = { - { - .group = 3, - .mask = bit(2) | bit(3) | bit(4), - }, -}; - -static const struct sirfsoc_padmux i2s_no_din_padmux = { - .muxmask_counts = array_size(i2s_no_din_muxmask), - .muxmask = i2s_no_din_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, -}; - -static const unsigned i2s_no_din_pins[] = { 98, 99, 100 }; - -static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = { - { - .group = 3, - .mask = bit(2) | bit(3) | bit(4) | bit(5), - }, -}; - -static const struct sirfsoc_padmux i2s_6chn_padmux = { - .muxmask_counts = array_size(i2s_6chn_muxmask), - .muxmask = i2s_6chn_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(1) | bit(9), - .funcval = bit(1) | bit(9), -}; - -static const unsigned i2s_6chn_pins[] = { 52, 55, 98, 99, 100, 101 }; - -static const struct sirfsoc_muxmask ac97_muxmask[] = { - { - .group = 3, - .mask = bit(2) | bit(3) | bit(4) | bit(5), - }, -}; - -static const struct sirfsoc_padmux ac97_padmux = { - .muxmask_counts = array_size(ac97_muxmask), - .muxmask = ac97_muxmask, -}; - -static const unsigned ac97_pins[] = { 98, 99, 100, 101 }; - -static const struct sirfsoc_muxmask spi1_muxmask[] = { - { - .group = 1, - .mask = bit(11) | bit(12) | bit(13) | bit(14), - }, -}; - -static const struct sirfsoc_padmux spi1_padmux = { - .muxmask_counts = array_size(spi1_muxmask), - .muxmask = spi1_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(16), - .funcval = 0, -}; - -static const unsigned spi1_pins[] = { 43, 44, 45, 46 }; - -static const struct sirfsoc_muxmask sdmmc1_muxmask[] = { - { - .group = 2, - .mask = bit(2) | bit(3), - }, -}; - -static const struct sirfsoc_padmux sdmmc1_padmux = { - .muxmask_counts = array_size(sdmmc1_muxmask), - .muxmask = sdmmc1_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(5), - .funcval = bit(5), -}; - -static const unsigned sdmmc1_pins[] = { 66, 67 }; - -static const struct sirfsoc_muxmask gps_muxmask[] = { - { - .group = 0, - .mask = bit(24) | bit(25) | bit(26), - }, -}; - -static const struct sirfsoc_padmux gps_padmux = { - .muxmask_counts = array_size(gps_muxmask), - .muxmask = gps_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(13), - .funcval = 0, -}; - -static const unsigned gps_pins[] = { 24, 25, 26 }; - -static const struct sirfsoc_muxmask sdmmc5_muxmask[] = { - { - .group = 0, - .mask = bit(24) | bit(25) | bit(26), - }, -}; - -static const struct sirfsoc_padmux sdmmc5_padmux = { - .muxmask_counts = array_size(sdmmc5_muxmask), - .muxmask = sdmmc5_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(13), - .funcval = bit(13), -}; - -static const unsigned sdmmc5_pins[] = { 24, 25, 26 }; - -static const struct sirfsoc_muxmask usp0_muxmask[] = { - { - .group = 1, - .mask = bit(19) | bit(20) | bit(21) | bit(22) | bit(23), - }, -}; - -static const struct sirfsoc_padmux usp0_padmux = { - .muxmask_counts = array_size(usp0_muxmask), - .muxmask = usp0_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(1) | bit(2) | bit(9), - .funcval = 0, -}; - -static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 }; - -static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = { - { - .group = 1, - .mask = bit(19) | bit(20) | bit(21) | bit(22), - }, -}; - -static const struct sirfsoc_padmux usp0_only_utfs_padmux = { - .muxmask_counts = array_size(usp0_only_utfs_muxmask), - .muxmask = usp0_only_utfs_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(1) | bit(2) | bit(6), - .funcval = 0, -}; - -static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 }; - -static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = { - { - .group = 1, - .mask = bit(19) | bit(20) | bit(21) | bit(23), - }, -}; - -static const struct sirfsoc_padmux usp0_only_urfs_padmux = { - .muxmask_counts = array_size(usp0_only_urfs_muxmask), - .muxmask = usp0_only_urfs_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(1) | bit(2) | bit(9), - .funcval = 0, -}; - -static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 }; - -static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = { - { - .group = 1, - .mask = bit(20) | bit(21), - }, -}; - -static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = { - .muxmask_counts = array_size(usp0_uart_nostreamctrl_muxmask), - .muxmask = usp0_uart_nostreamctrl_muxmask, -}; - -static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 }; -static const struct sirfsoc_muxmask usp1_muxmask[] = { - { - .group = 0, - .mask = bit(15), - }, { - .group = 1, - .mask = bit(11) | bit(12) | bit(13) | bit(14), - }, -}; - -static const struct sirfsoc_padmux usp1_padmux = { - .muxmask_counts = array_size(usp1_muxmask), - .muxmask = usp1_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(16), - .funcval = bit(16), -}; - -static const unsigned usp1_pins[] = { 15, 43, 44, 45, 46 }; - -static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = { - { - .group = 1, - .mask = bit(12) | bit(13), - }, -}; - -static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = { - .muxmask_counts = array_size(usp1_uart_nostreamctrl_muxmask), - .muxmask = usp1_uart_nostreamctrl_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(16), - .funcval = bit(16), -}; - -static const unsigned usp1_uart_nostreamctrl_pins[] = { 44, 45 }; - -static const struct sirfsoc_muxmask nand_muxmask[] = { - { - .group = 2, - .mask = bit(2) | bit(3) | bit(28) | bit(29) | bit(30), - }, { - .group = 3, - .mask = bit(0) | bit(1), - }, -}; - -static const struct sirfsoc_padmux nand_padmux = { - .muxmask_counts = array_size(nand_muxmask), - .muxmask = nand_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(5) | bit(19), - .funcval = 0, -}; - -static const unsigned nand_pins[] = { 66, 67, 92, 93, 94, 96, 97 }; - -static const struct sirfsoc_muxmask sdmmc0_muxmask[] = { - { - .group = 3, - .mask = bit(1), - }, -}; - -static const struct sirfsoc_padmux sdmmc0_padmux = { - .muxmask_counts = array_size(sdmmc0_muxmask), - .muxmask = sdmmc0_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(5) | bit(19), - .funcval = bit(19), -}; - -static const unsigned sdmmc0_pins[] = { 97 }; - -static const struct sirfsoc_muxmask sdmmc2_muxmask[] = { - { - .group = 0, - .mask = bit(27) | bit(28) | bit(29), - }, -}; - -static const struct sirfsoc_padmux sdmmc2_padmux = { - .muxmask_counts = array_size(sdmmc2_muxmask), - .muxmask = sdmmc2_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(11), - .funcval = 0, -}; - -static const unsigned sdmmc2_pins[] = { 27, 28, 29 }; - -static const struct sirfsoc_muxmask sdmmc2_nowp_muxmask[] = { - { - .group = 0, - .mask = bit(27) | bit(28), - }, -}; - -static const struct sirfsoc_padmux sdmmc2_nowp_padmux = { - .muxmask_counts = array_size(sdmmc2_nowp_muxmask), - .muxmask = sdmmc2_nowp_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(11), - .funcval = 0, -}; - -static const unsigned sdmmc2_nowp_pins[] = { 27, 28 }; - -static const struct sirfsoc_muxmask cko0_muxmask[] = { - { - .group = 2, - .mask = bit(14), - }, -}; - -static const struct sirfsoc_padmux cko0_padmux = { - .muxmask_counts = array_size(cko0_muxmask), - .muxmask = cko0_muxmask, -}; - -static const unsigned cko0_pins[] = { 78 }; - -static const struct sirfsoc_muxmask vip_muxmask[] = { - { - .group = 1, - .mask = bit(4) | bit(5) | bit(6) | bit(8) | bit(9) - | bit(24) | bit(25) | bit(26) | bit(27) | bit(28) | - bit(29), - }, -}; - -static const struct sirfsoc_padmux vip_padmux = { - .muxmask_counts = array_size(vip_muxmask), - .muxmask = vip_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(18), - .funcval = bit(18), -}; - -static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59, - 60, 61 }; - -static const struct sirfsoc_muxmask vip_noupli_muxmask[] = { - { - .group = 0, - .mask = bit(16) | bit(17) | bit(18) | bit(19) | bit(20) - | bit(21) | bit(22) | bit(23), - }, { - .group = 2, - .mask = bit(23) | bit(24) | bit(25), - }, -}; - -static const struct sirfsoc_padmux vip_noupli_padmux = { - .muxmask_counts = array_size(vip_noupli_muxmask), - .muxmask = vip_noupli_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(15), - .funcval = bit(15), -}; - -static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, - 87, 88, 89 }; - -static const struct sirfsoc_muxmask i2c0_muxmask[] = { - { - .group = 2, - .mask = bit(26) | bit(27), - }, -}; - -static const struct sirfsoc_padmux i2c0_padmux = { - .muxmask_counts = array_size(i2c0_muxmask), - .muxmask = i2c0_muxmask, -}; - -static const unsigned i2c0_pins[] = { 90, 91 }; - -static const struct sirfsoc_muxmask i2c1_muxmask[] = { - { - .group = 0, - .mask = bit(13) | bit(15), - }, -}; - -static const struct sirfsoc_padmux i2c1_padmux = { - .muxmask_counts = array_size(i2c1_muxmask), - .muxmask = i2c1_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(16), - .funcval = 0, -}; - -static const unsigned i2c1_pins[] = { 13, 15 }; - -static const struct sirfsoc_muxmask pwm0_muxmask[] = { - { - .group = 0, - .mask = bit(4), - }, -}; - -static const struct sirfsoc_padmux pwm0_padmux = { - .muxmask_counts = array_size(pwm0_muxmask), - .muxmask = pwm0_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(12), - .funcval = 0, -}; - -static const unsigned pwm0_pins[] = { 4 }; - -static const struct sirfsoc_muxmask pwm1_muxmask[] = { - { - .group = 0, - .mask = bit(5), - }, -}; - -static const struct sirfsoc_padmux pwm1_padmux = { - .muxmask_counts = array_size(pwm1_muxmask), - .muxmask = pwm1_muxmask, -}; - -static const unsigned pwm1_pins[] = { 5 }; - -static const struct sirfsoc_muxmask pwm2_muxmask[] = { - { - .group = 0, - .mask = bit(6), - }, -}; - -static const struct sirfsoc_padmux pwm2_padmux = { - .muxmask_counts = array_size(pwm2_muxmask), - .muxmask = pwm2_muxmask, -}; - -static const unsigned pwm2_pins[] = { 6 }; - -static const struct sirfsoc_muxmask pwm3_muxmask[] = { - { - .group = 0, - .mask = bit(7), - }, -}; - -static const struct sirfsoc_padmux pwm3_padmux = { - .muxmask_counts = array_size(pwm3_muxmask), - .muxmask = pwm3_muxmask, -}; - -static const unsigned pwm3_pins[] = { 7 }; - -static const struct sirfsoc_muxmask pwm4_muxmask[] = { - { - .group = 2, - .mask = bit(14), - }, -}; - -static const struct sirfsoc_padmux pwm4_padmux = { - .muxmask_counts = array_size(pwm4_muxmask), - .muxmask = pwm4_muxmask, -}; - -static const unsigned pwm4_pins[] = { 78 }; - -static const struct sirfsoc_muxmask warm_rst_muxmask[] = { - { - .group = 0, - .mask = bit(8), - }, -}; - -static const struct sirfsoc_padmux warm_rst_padmux = { - .muxmask_counts = array_size(warm_rst_muxmask), - .muxmask = warm_rst_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(4), - .funcval = 0, -}; - -static const unsigned warm_rst_pins[] = { 8 }; - -static const struct sirfsoc_muxmask usb0_upli_drvbus_muxmask[] = { - { - .group = 1, - .mask = bit(4) | bit(5) | bit(6) | bit(7) | bit(8) - | bit(9) | bit(24) | bit(25) | bit(26) | - bit(27) | bit(28) | bit(29), - }, -}; -static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = { - .muxmask_counts = array_size(usb0_upli_drvbus_muxmask), - .muxmask = usb0_upli_drvbus_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(18), - .funcval = 0, -}; - -static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40, - 41, 56, 57, 58, 59, 60, 61 }; - -static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = { - { - .group = 0, - .mask = bit(28), - }, -}; - -static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = { - .muxmask_counts = array_size(usb1_utmi_drvbus_muxmask), - .muxmask = usb1_utmi_drvbus_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(11), - .funcval = bit(11), /* refer to pad_utmi_drvvbus1_enable */ -}; - -static const unsigned usb1_utmi_drvbus_pins[] = { 28 }; - -static const struct sirfsoc_padmux usb1_dp_dn_padmux = { - .muxmask_counts = 0, - .ctrlreg = sirfsoc_rsc_usb_uart_share, - .funcmask = bit(2), - .funcval = bit(2), -}; - -static const unsigned usb1_dp_dn_pins[] = { 103, 104 }; - -static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = { - .muxmask_counts = 0, - .ctrlreg = sirfsoc_rsc_usb_uart_share, - .funcmask = bit(2), - .funcval = 0, -}; - -static const unsigned uart1_route_io_usb1_pins[] = { 103, 104 }; - -static const struct sirfsoc_muxmask pulse_count_muxmask[] = { - { - .group = 0, - .mask = bit(9) | bit(10) | bit(11), - }, -}; - -static const struct sirfsoc_padmux pulse_count_padmux = { - .muxmask_counts = array_size(pulse_count_muxmask), - .muxmask = pulse_count_muxmask, -}; - -static const unsigned pulse_count_pins[] = { 9, 10, 11 }; - -static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { - sirfsoc_pin_group("lcd_16bitsgrp", lcd_16bits_pins), - sirfsoc_pin_group("lcd_18bitsgrp", lcd_18bits_pins), - sirfsoc_pin_group("lcd_24bitsgrp", lcd_24bits_pins), - sirfsoc_pin_group("lcdrom_grp", lcdrom_pins), - sirfsoc_pin_group("uart0grp", uart0_pins), - sirfsoc_pin_group("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins), - sirfsoc_pin_group("uart1grp", uart1_pins), - sirfsoc_pin_group("uart2grp", uart2_pins), - sirfsoc_pin_group("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins), - sirfsoc_pin_group("usp0grp", usp0_pins), - sirfsoc_pin_group("usp0_uart_nostreamctrl_grp", - usp0_uart_nostreamctrl_pins), - sirfsoc_pin_group("usp0_only_utfs_grp", usp0_only_utfs_pins), - sirfsoc_pin_group("usp0_only_urfs_grp", usp0_only_urfs_pins), - sirfsoc_pin_group("usp1grp", usp1_pins), - sirfsoc_pin_group("usp1_uart_nostreamctrl_grp", - usp1_uart_nostreamctrl_pins), - sirfsoc_pin_group("i2c0grp", i2c0_pins), - sirfsoc_pin_group("i2c1grp", i2c1_pins), - sirfsoc_pin_group("pwm0grp", pwm0_pins), - sirfsoc_pin_group("pwm1grp", pwm1_pins), - sirfsoc_pin_group("pwm2grp", pwm2_pins), - sirfsoc_pin_group("pwm3grp", pwm3_pins), - sirfsoc_pin_group("pwm4grp", pwm4_pins), - sirfsoc_pin_group("vipgrp", vip_pins), - sirfsoc_pin_group("vip_noupligrp", vip_noupli_pins), - sirfsoc_pin_group("warm_rstgrp", warm_rst_pins), - sirfsoc_pin_group("cko0grp", cko0_pins), - sirfsoc_pin_group("cko1grp", cko1_pins), - sirfsoc_pin_group("sdmmc0grp", sdmmc0_pins), - sirfsoc_pin_group("sdmmc1grp", sdmmc1_pins), - sirfsoc_pin_group("sdmmc2grp", sdmmc2_pins), - sirfsoc_pin_group("sdmmc2_nowpgrp", sdmmc2_nowp_pins), - sirfsoc_pin_group("sdmmc3grp", sdmmc3_pins), - sirfsoc_pin_group("sdmmc5grp", sdmmc5_pins), - sirfsoc_pin_group("usb0_upli_drvbusgrp", usb0_upli_drvbus_pins), - sirfsoc_pin_group("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins), - sirfsoc_pin_group("usb1_dp_dngrp", usb1_dp_dn_pins), - sirfsoc_pin_group("uart1_route_io_usb1grp", uart1_route_io_usb1_pins), - sirfsoc_pin_group("pulse_countgrp", pulse_count_pins), - sirfsoc_pin_group("i2smclkgrp", i2s_mclk_pins), - sirfsoc_pin_group("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins), - sirfsoc_pin_group("i2sgrp", i2s_pins), - sirfsoc_pin_group("i2s_no_dingrp", i2s_no_din_pins), - sirfsoc_pin_group("i2s_6chngrp", i2s_6chn_pins), - sirfsoc_pin_group("ac97grp", ac97_pins), - sirfsoc_pin_group("nandgrp", nand_pins), - sirfsoc_pin_group("spi0grp", spi0_pins), - sirfsoc_pin_group("spi1grp", spi1_pins), - sirfsoc_pin_group("gpsgrp", gps_pins), -}; - -static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" }; -static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" }; -static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" }; -static const char * const lcdromgrp[] = { "lcdromgrp" }; -static const char * const uart0grp[] = { "uart0grp" }; -static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" }; -static const char * const uart1grp[] = { "uart1grp" }; -static const char * const uart2grp[] = { "uart2grp" }; -static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" }; -static const char * const usp0_uart_nostreamctrl_grp[] = { - "usp0_uart_nostreamctrl_grp" }; -static const char * const usp0grp[] = { "usp0grp" }; -static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" }; -static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" }; - -static const char * const usp1grp[] = { "usp1grp" }; -static const char * const usp1_uart_nostreamctrl_grp[] = { - "usp1_uart_nostreamctrl_grp" }; -static const char * const i2c0grp[] = { "i2c0grp" }; -static const char * const i2c1grp[] = { "i2c1grp" }; -static const char * const pwm0grp[] = { "pwm0grp" }; -static const char * const pwm1grp[] = { "pwm1grp" }; -static const char * const pwm2grp[] = { "pwm2grp" }; -static const char * const pwm3grp[] = { "pwm3grp" }; -static const char * const pwm4grp[] = { "pwm4grp" }; -static const char * const vipgrp[] = { "vipgrp" }; -static const char * const vip_noupligrp[] = { "vip_noupligrp" }; -static const char * const warm_rstgrp[] = { "warm_rstgrp" }; -static const char * const cko0grp[] = { "cko0grp" }; -static const char * const cko1grp[] = { "cko1grp" }; -static const char * const sdmmc0grp[] = { "sdmmc0grp" }; -static const char * const sdmmc1grp[] = { "sdmmc1grp" }; -static const char * const sdmmc2grp[] = { "sdmmc2grp" }; -static const char * const sdmmc3grp[] = { "sdmmc3grp" }; -static const char * const sdmmc5grp[] = { "sdmmc5grp" }; -static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" }; -static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" }; -static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" }; -static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" }; -static const char * const - uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" }; -static const char * const pulse_countgrp[] = { "pulse_countgrp" }; -static const char * const i2smclkgrp[] = { "i2smclkgrp" }; -static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" }; -static const char * const i2sgrp[] = { "i2sgrp" }; -static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" }; -static const char * const i2s_6chngrp[] = { "i2s_6chngrp" }; -static const char * const ac97grp[] = { "ac97grp" }; -static const char * const nandgrp[] = { "nandgrp" }; -static const char * const spi0grp[] = { "spi0grp" }; -static const char * const spi1grp[] = { "spi1grp" }; -static const char * const gpsgrp[] = { "gpsgrp" }; - -static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { - sirfsoc_pmx_function("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux), - sirfsoc_pmx_function("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux), - sirfsoc_pmx_function("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux), - sirfsoc_pmx_function("lcdrom", lcdromgrp, lcdrom_padmux), - sirfsoc_pmx_function("uart0", uart0grp, uart0_padmux), - sirfsoc_pmx_function("uart0_nostreamctrl", uart0_nostreamctrlgrp, - uart0_nostreamctrl_padmux), - sirfsoc_pmx_function("uart1", uart1grp, uart1_padmux), - sirfsoc_pmx_function("uart2", uart2grp, uart2_padmux), - sirfsoc_pmx_function("uart2_nostreamctrl", - uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux), - sirfsoc_pmx_function("usp0", usp0grp, usp0_padmux), - sirfsoc_pmx_function("usp0_uart_nostreamctrl", - usp0_uart_nostreamctrl_grp, - usp0_uart_nostreamctrl_padmux), - sirfsoc_pmx_function("usp0_only_utfs", usp0_only_utfs_grp, - usp0_only_utfs_padmux), - sirfsoc_pmx_function("usp0_only_urfs", usp0_only_urfs_grp, - usp0_only_urfs_padmux), - sirfsoc_pmx_function("usp1", usp1grp, usp1_padmux), - sirfsoc_pmx_function("usp1_uart_nostreamctrl", - usp1_uart_nostreamctrl_grp, - usp1_uart_nostreamctrl_padmux), - sirfsoc_pmx_function("i2c0", i2c0grp, i2c0_padmux), - sirfsoc_pmx_function("i2c1", i2c1grp, i2c1_padmux), - sirfsoc_pmx_function("pwm0", pwm0grp, pwm0_padmux), - sirfsoc_pmx_function("pwm1", pwm1grp, pwm1_padmux), - sirfsoc_pmx_function("pwm2", pwm2grp, pwm2_padmux), - sirfsoc_pmx_function("pwm3", pwm3grp, pwm3_padmux), - sirfsoc_pmx_function("pwm4", pwm4grp, pwm4_padmux), - sirfsoc_pmx_function("vip", vipgrp, vip_padmux), - sirfsoc_pmx_function("vip_noupli", vip_noupligrp, vip_noupli_padmux), - sirfsoc_pmx_function("warm_rst", warm_rstgrp, warm_rst_padmux), - sirfsoc_pmx_function("cko0", cko0grp, cko0_padmux), - sirfsoc_pmx_function("cko1", cko1grp, cko1_padmux), - sirfsoc_pmx_function("sdmmc0", sdmmc0grp, sdmmc0_padmux), - sirfsoc_pmx_function("sdmmc1", sdmmc1grp, sdmmc1_padmux), - sirfsoc_pmx_function("sdmmc2", sdmmc2grp, sdmmc2_padmux), - sirfsoc_pmx_function("sdmmc3", sdmmc3grp, sdmmc3_padmux), - sirfsoc_pmx_function("sdmmc5", sdmmc5grp, sdmmc5_padmux), - sirfsoc_pmx_function("sdmmc2_nowp", - sdmmc2_nowpgrp, sdmmc2_nowp_padmux), - sirfsoc_pmx_function("usb0_upli_drvbus", - usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux), - sirfsoc_pmx_function("usb1_utmi_drvbus", - usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), - sirfsoc_pmx_function("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux), - sirfsoc_pmx_function("uart1_route_io_usb1", - uart1_route_io_usb1grp, uart1_route_io_usb1_padmux), - sirfsoc_pmx_function("pulse_count", pulse_countgrp, pulse_count_padmux), - sirfsoc_pmx_function("i2s_mclk", i2smclkgrp, i2s_mclk_padmux), - sirfsoc_pmx_function("i2s_ext_clk_input", i2s_ext_clk_inputgrp, - i2s_ext_clk_input_padmux), - sirfsoc_pmx_function("i2s", i2sgrp, i2s_padmux), - sirfsoc_pmx_function("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux), - sirfsoc_pmx_function("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux), - sirfsoc_pmx_function("ac97", ac97grp, ac97_padmux), - sirfsoc_pmx_function("nand", nandgrp, nand_padmux), - sirfsoc_pmx_function("spi0", spi0grp, spi0_padmux), - sirfsoc_pmx_function("spi1", spi1grp, spi1_padmux), - sirfsoc_pmx_function("gps", gpsgrp, gps_padmux), -}; - -struct sirfsoc_pinctrl_data atlas6_pinctrl_data = { - (struct pinctrl_pin_desc *)sirfsoc_pads, - array_size(sirfsoc_pads), - (struct sirfsoc_pin_group *)sirfsoc_pin_groups, - array_size(sirfsoc_pin_groups), - (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions, - array_size(sirfsoc_pmx_functions), -}; - diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c --- a/drivers/pinctrl/sirf/pinctrl-atlas7.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-or-later -/* - * pinctrl pads, groups, functions for csr sirfatlasvii - * - * copyright (c) 2011 - 2014 cambridge silicon radio limited, a csr plc group - * company. - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/bitops.h> -#include <linux/irq.h> -#include <linux/slab.h> -#include <linux/clk.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> -#include <linux/of_platform.h> -#include <linux/of_irq.h> -#include <linux/pinctrl/machine.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/consumer.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/gpio/driver.h> - -/* definition of pad&mux properties */ -#define n 0 - -/* the bank contains input-disable regisgers */ -#define bank_ds 0 - -/* clear register offset */ -#define clr_reg(r) ((r) + 0x04) - -/* definition of multiple function select register */ -#define func_clear_mask 0x7 -#define func_gpio 0 -#define func_analogue 0x8 -#define ana_clear_mask 0x1 - -/* the atlas7's pad type list */ -enum altas7_pad_type { - pad_t_4we_pd = 0, /* zio_pad3v_4we_pd */ - pad_t_4we_pu, /* zio_pad3v_4we_pd */ - pad_t_16st, /* zio_pad3v_sdclk_pd */ - pad_t_m31_0204_pd, /* prdw0204sdgz_m311311_pd */ - pad_t_m31_0204_pu, /* prdw0204sdgz_m311311_pu */ - pad_t_m31_0610_pd, /* pruw0610sdgz_m311311_pd */ - pad_t_m31_0610_pu, /* pruw0610sdgz_m311311_pu */ - pad_t_ad, /* prdwuwhw08scdg_hz */ -}; - -/* raw value of driver-strength bits */ -#define ds3 bit(3) -#define ds2 bit(2) -#define ds1 bit(1) -#define ds0 bit(0) -#define dsz 0 - -/* drive-strength intermediate values */ -#define ds_null -1 -#define ds_1bit_im_val ds0 -#define ds_1bit_mask 0x1 -#define ds_2bit_im_val (ds1 | ds0) -#define ds_2bit_mask 0x3 -#define ds_4bit_im_val (ds3 | ds2 | ds1 | ds0) -#define ds_4bit_mask 0xf - -/* the drive-strength of 4we pad ds1 0 co */ -#define ds_4we_3 (ds1 | ds0) /* 1 1 3 */ -#define ds_4we_2 (ds1) /* 1 0 2 */ -#define ds_4we_1 (ds0) /* 0 1 1 */ -#define ds_4we_0 (dsz) /* 0 0 0 */ - -/* the drive-strength of 16st pad ds3 2 1 0 co */ -#define ds_16st_15 (ds3 | ds2 | ds1 | ds0) /* 1 1 1 1 15 */ -#define ds_16st_14 (ds3 | ds2 | ds0) /* 1 1 0 1 13 */ -#define ds_16st_13 (ds3 | ds2 | ds1) /* 1 1 1 0 14 */ -#define ds_16st_12 (ds2 | ds1 | ds0) /* 0 1 1 1 7 */ -#define ds_16st_11 (ds2 | ds0) /* 0 1 0 1 5 */ -#define ds_16st_10 (ds3 | ds1 | ds0) /* 1 0 1 1 11 */ -#define ds_16st_9 (ds3 | ds0) /* 1 0 0 1 9 */ -#define ds_16st_8 (ds1 | ds0) /* 0 0 1 1 3 */ -#define ds_16st_7 (ds2 | ds1) /* 0 1 1 0 6 */ -#define ds_16st_6 (ds3 | ds2) /* 1 1 0 0 12 */ -#define ds_16st_5 (ds2) /* 0 1 0 0 4 */ -#define ds_16st_4 (ds3 | ds1) /* 1 0 1 0 10 */ -#define ds_16st_3 (ds1) /* 0 0 1 0 2 */ -#define ds_16st_2 (ds0) /* 0 0 0 1 1 */ -#define ds_16st_1 (dsz) /* 0 0 0 0 0 */ -#define ds_16st_0 (ds3) /* 1 0 0 0 8 */ - -/* the drive-strength of m31 pad ds0 co */ -#define ds_m31_0 (dsz) /* 0 0 */ -#define ds_m31_1 (ds0) /* 1 1 */ - -/* raw values of pull option bits */ -#define pun bit(1) -#define pd bit(0) -#define pe bit(0) -#define pz 0 - -/* definition of pull types */ -#define pull_up 0 -#define high_hysteresis 1 -#define high_z 2 -#define pull_down 3 -#define pull_disable 4 -#define pull_enable 5 -#define pull_unknown -1 - -/* pull options for 4we pad pun pd co */ -#define p4we_pull_mask 0x3 -#define p4we_pull_down (pun | pd) /* 1 1 3 */ -#define p4we_high_z (pun) /* 1 0 2 */ -#define p4we_high_hysteresis (pd) /* 0 1 1 */ -#define p4we_pull_up (pz) /* 0 0 0 */ - -/* pull options for 16st pad pun pd co */ -#define p16st_pull_mask 0x3 -#define p16st_pull_down (pun | pd) /* 1 1 3 */ -#define p16st_high_z (pun) /* 1 0 2 */ -#define p16st_pull_up (pz) /* 0 0 0 */ - -/* pull options for m31 pad pe */ -#define pm31_pull_mask 0x1 -#define pm31_pull_enabled (pe) /* 1 */ -#define pm31_pull_disabled (pz) /* 0 */ - -/* pull options for a/d pad pun pd co */ -#define pangd_pull_mask 0x3 -#define pangd_pull_down (pun | pd) /* 1 1 3 */ -#define pangd_high_z (pun) /* 1 0 2 */ -#define pangd_pull_up (pz) /* 0 0 0 */ - -/* definition of input disable */ -#define di_mask 0x1 -#define di_disable 0x1 -#define di_enable 0x0 - -/* definition of input disable value */ -#define div_mask 0x1 -#define div_disable 0x1 -#define div_enable 0x0 - -/* number of function input disable registers */ -#define num_of_in_disable_reg 0x2 - -/* offset of function input disable registers */ -#define in_disable_0_reg_set 0x0a00 -#define in_disable_0_reg_clr 0x0a04 -#define in_disable_1_reg_set 0x0a08 -#define in_disable_1_reg_clr 0x0a0c -#define in_disable_val_0_reg_set 0x0a80 -#define in_disable_val_0_reg_clr 0x0a84 -#define in_disable_val_1_reg_set 0x0a88 -#define in_disable_val_1_reg_clr 0x0a8c - -/* offset of the sdio9sel*/ -#define sys2pci_sdio9sel 0x14 - -struct dt_params { - const char *property; - int value; -}; - -/** - * struct atlas7_pad_conf - atlas7 pad configuration - * @id: the id of this pad. - * @type: the type of this pad. - * @mux_reg: the mux register offset. - * this register contains the mux. - * @pupd_reg: the pull-up/down register offset. - * @drvstr_reg: the drive-strength register offset. - * @ad_ctrl_reg: the analogue/digital control register. - * - * @mux_bit: the start bit of mux register. - * @pupd_bit: the start bit of pull-up/down register. - * @drvstr_bit: the start bit of drive-strength register. - * @ad_ctrl_bit: the start bit of analogue/digital register. - */ -struct atlas7_pad_config { - const u32 id; - u32 type; - u32 mux_reg; - u32 pupd_reg; - u32 drvstr_reg; - u32 ad_ctrl_reg; - /* bits in register */ - u8 mux_bit; - u8 pupd_bit; - u8 drvstr_bit; - u8 ad_ctrl_bit; -}; - -#define padconf(pad, t, mr, pr, dsr, adr, mb, pb, dsb, adb) \ - { \ - .id = pad, \ - .type = t, \ - .mux_reg = mr, \ - .pupd_reg = pr, \ - .drvstr_reg = dsr, \ - .ad_ctrl_reg = adr, \ - .mux_bit = mb, \ - .pupd_bit = pb, \ - .drvstr_bit = dsb, \ - .ad_ctrl_bit = adb, \ - } - -/* - * struct atlas7_pad_status - atlas7 pad status - */ -struct atlas7_pad_status { - u8 func; - u8 pull; - u8 dstr; - u8 reserved; -}; - -/** - * struct atlas7_pad_mux - atlas7 mux - * @bank: the bank of this pad's registers on. - * @pin : the id of this pad. - * @func: the mux func on this pad. - * @dinput_reg: the input-disable register offset. - * @dinput_bit: the start bit of input-disable register. - * @dinput_val_reg: the input-disable-value register offset. - * this register is used to set the value of this pad - * if this pad was disabled. - * @dinput_val_bit: the start bit of input-disable value register. - */ -struct atlas7_pad_mux { - u32 bank; - u32 pin; - u32 func; - u32 dinput_reg; - u32 dinput_bit; - u32 dinput_val_reg; - u32 dinput_val_bit; -}; - -#define mux(b, pad, f, dr, db, dvr, dvb) \ - { \ - .bank = b, \ - .pin = pad, \ - .func = f, \ - .dinput_reg = dr, \ - .dinput_bit = db, \ - .dinput_val_reg = dvr, \ - .dinput_val_bit = dvb, \ - } - -struct atlas7_grp_mux { - unsigned int group; - unsigned int pad_mux_count; - const struct atlas7_pad_mux *pad_mux_list; -}; - - /** - * struct sirfsoc_pin_group - describes a sirfprimaii pin group - * @name: the name of this specific pin group - * @pins: an array of discrete physical pins used in this group, taken - * from the driver-local pin enumeration space - * @num_pins: the number of pins in this group array, i.e. the number of - * elements in .pins so we can iterate over that array - */ -struct atlas7_pin_group { - const char *name; - const unsigned int *pins; - const unsigned num_pins; -}; - -#define group(n, p) \ - { \ - .name = n, \ - .pins = p, \ - .num_pins = array_size(p), \ - } - -struct atlas7_pmx_func { - const char *name; - const char * const *groups; - const unsigned num_groups; - const struct atlas7_grp_mux *grpmux; -}; - -#define function(n, g, m) \ - { \ - .name = n, \ - .groups = g, \ - .num_groups = array_size(g), \ - .grpmux = m, \ - } - -struct atlas7_pinctrl_data { - struct pinctrl_pin_desc *pads; - int pads_cnt; - struct atlas7_pin_group *grps; - int grps_cnt; - struct atlas7_pmx_func *funcs; - int funcs_cnt; - struct atlas7_pad_config *confs; - int confs_cnt; -}; - -/* platform info of atlas7 pinctrl */ -#define atlas7_pinctrl_reg_banks 2 -#define atlas7_pinctrl_bank_0_pins 18 -#define atlas7_pinctrl_bank_1_pins 141 -#define atlas7_pinctrl_total_pins \ - (atlas7_pinctrl_bank_0_pins + atlas7_pinctrl_bank_1_pins) - -/** - * atlas7 gpio chip - */ - -#define ngpio_of_bank 32 -#define gpio_to_bank(gpio) ((gpio) / ngpio_of_bank) - -/* registers of gpio controllers */ -#define atlas7_gpio_base(g, b) ((g)->reg + 0x100 * (b)) -#define atlas7_gpio_ctrl(b, i) ((b)->base + 4 * (i)) -#define atlas7_gpio_int_status(b) ((b)->base + 0x8c) - -/* definition bits of gpio control registers */ -#define atlas7_gpio_ctl_intr_low_mask bit(0) -#define atlas7_gpio_ctl_intr_high_mask bit(1) -#define atlas7_gpio_ctl_intr_type_mask bit(2) -#define atlas7_gpio_ctl_intr_en_mask bit(3) -#define atlas7_gpio_ctl_intr_status_mask bit(4) -#define atlas7_gpio_ctl_out_en_mask bit(5) -#define atlas7_gpio_ctl_dataout_mask bit(6) -#define atlas7_gpio_ctl_datain_mask bit(7) - -struct atlas7_gpio_bank { - int id; - int irq; - void __iomem *base; - unsigned int gpio_offset; - unsigned int ngpio; - const unsigned int *gpio_pins; - u32 sleep_data[ngpio_of_bank]; -}; - -struct atlas7_gpio_chip { - const char *name; - void __iomem *reg; - struct clk *clk; - int nbank; - raw_spinlock_t lock; - struct gpio_chip chip; - struct atlas7_gpio_bank banks[]; -}; - -struct atlas7_pmx { - struct device *dev; - struct pinctrl_dev *pctl; - struct pinctrl_desc pctl_desc; - struct atlas7_pinctrl_data *pctl_data; - void __iomem *regs[atlas7_pinctrl_reg_banks]; - void __iomem *sys2pci_base; - u32 status_ds[num_of_in_disable_reg]; - u32 status_dsv[num_of_in_disable_reg]; - struct atlas7_pad_status sleep_data[atlas7_pinctrl_total_pins]; -}; - -/* - * pad list for the pinmux subsystem - * refer to a7da io summary - cs-314158-dd-4e.xls - */ - -/* pads in ioc rtc & top */ -static const struct pinctrl_pin_desc atlas7_ioc_pads[] = { - /* rtc pads */ - pinctrl_pin(0, "rtc_gpio_0"), - pinctrl_pin(1, "rtc_gpio_1"), - pinctrl_pin(2, "rtc_gpio_2"), - pinctrl_pin(3, "rtc_gpio_3"), - pinctrl_pin(4, "low_bat_ind_b"), - pinctrl_pin(5, "on_key_b"), - pinctrl_pin(6, "ext_on"), - pinctrl_pin(7, "mem_on"), - pinctrl_pin(8, "core_on"), - pinctrl_pin(9, "io_on"), - pinctrl_pin(10, "can0_tx"), - pinctrl_pin(11, "can0_rx"), - pinctrl_pin(12, "spi0_clk"), - pinctrl_pin(13, "spi0_cs_b"), - pinctrl_pin(14, "spi0_io_0"), - pinctrl_pin(15, "spi0_io_1"), - pinctrl_pin(16, "spi0_io_2"), - pinctrl_pin(17, "spi0_io_3"), - - /* top pads */ - pinctrl_pin(18, "spi1_en"), - pinctrl_pin(19, "spi1_clk"), - pinctrl_pin(20, "spi1_din"), - pinctrl_pin(21, "spi1_dout"), - pinctrl_pin(22, "trg_spi_clk"), - pinctrl_pin(23, "trg_spi_di"), - pinctrl_pin(24, "trg_spi_do"), - pinctrl_pin(25, "trg_spi_cs_b"), - pinctrl_pin(26, "trg_acq_d1"), - pinctrl_pin(27, "trg_irq_b"), - pinctrl_pin(28, "trg_acq_d0"), - pinctrl_pin(29, "trg_acq_clk"), - pinctrl_pin(30, "trg_shutdown_b_out"), - pinctrl_pin(31, "sdio2_clk"), - pinctrl_pin(32, "sdio2_cmd"), - pinctrl_pin(33, "sdio2_dat_0"), - pinctrl_pin(34, "sdio2_dat_1"), - pinctrl_pin(35, "sdio2_dat_2"), - pinctrl_pin(36, "sdio2_dat_3"), - pinctrl_pin(37, "df_ad_7"), - pinctrl_pin(38, "df_ad_6"), - pinctrl_pin(39, "df_ad_5"), - pinctrl_pin(40, "df_ad_4"), - pinctrl_pin(41, "df_ad_3"), - pinctrl_pin(42, "df_ad_2"), - pinctrl_pin(43, "df_ad_1"), - pinctrl_pin(44, "df_ad_0"), - pinctrl_pin(45, "df_dqs"), - pinctrl_pin(46, "df_cle"), - pinctrl_pin(47, "df_ale"), - pinctrl_pin(48, "df_we_b"), - pinctrl_pin(49, "df_re_b"), - pinctrl_pin(50, "df_ry_by"), - pinctrl_pin(51, "df_cs_b_1"), - pinctrl_pin(52, "df_cs_b_0"), - pinctrl_pin(53, "l_pclk"), - pinctrl_pin(54, "l_lck"), - pinctrl_pin(55, "l_fck"), - pinctrl_pin(56, "l_de"), - pinctrl_pin(57, "ldd_0"), - pinctrl_pin(58, "ldd_1"), - pinctrl_pin(59, "ldd_2"), - pinctrl_pin(60, "ldd_3"), - pinctrl_pin(61, "ldd_4"), - pinctrl_pin(62, "ldd_5"), - pinctrl_pin(63, "ldd_6"), - pinctrl_pin(64, "ldd_7"), - pinctrl_pin(65, "ldd_8"), - pinctrl_pin(66, "ldd_9"), - pinctrl_pin(67, "ldd_10"), - pinctrl_pin(68, "ldd_11"), - pinctrl_pin(69, "ldd_12"), - pinctrl_pin(70, "ldd_13"), - pinctrl_pin(71, "ldd_14"), - pinctrl_pin(72, "ldd_15"), - pinctrl_pin(73, "lcd_gpio_20"), - pinctrl_pin(74, "vip_0"), - pinctrl_pin(75, "vip_1"), - pinctrl_pin(76, "vip_2"), - pinctrl_pin(77, "vip_3"), - pinctrl_pin(78, "vip_4"), - pinctrl_pin(79, "vip_5"), - pinctrl_pin(80, "vip_6"), - pinctrl_pin(81, "vip_7"), - pinctrl_pin(82, "vip_pxclk"), - pinctrl_pin(83, "vip_hsync"), - pinctrl_pin(84, "vip_vsync"), - pinctrl_pin(85, "sdio3_clk"), - pinctrl_pin(86, "sdio3_cmd"), - pinctrl_pin(87, "sdio3_dat_0"), - pinctrl_pin(88, "sdio3_dat_1"), - pinctrl_pin(89, "sdio3_dat_2"), - pinctrl_pin(90, "sdio3_dat_3"), - pinctrl_pin(91, "sdio5_clk"), - pinctrl_pin(92, "sdio5_cmd"), - pinctrl_pin(93, "sdio5_dat_0"), - pinctrl_pin(94, "sdio5_dat_1"), - pinctrl_pin(95, "sdio5_dat_2"), - pinctrl_pin(96, "sdio5_dat_3"), - pinctrl_pin(97, "rgmii_txd_0"), - pinctrl_pin(98, "rgmii_txd_1"), - pinctrl_pin(99, "rgmii_txd_2"), - pinctrl_pin(100, "rgmii_txd_3"), - pinctrl_pin(101, "rgmii_txclk"), - pinctrl_pin(102, "rgmii_tx_ctl"), - pinctrl_pin(103, "rgmii_rxd_0"), - pinctrl_pin(104, "rgmii_rxd_1"), - pinctrl_pin(105, "rgmii_rxd_2"), - pinctrl_pin(106, "rgmii_rxd_3"), - pinctrl_pin(107, "rgmii_rx_clk"), - pinctrl_pin(108, "rgmii_rxc_ctl"), - pinctrl_pin(109, "rgmii_mdio"), - pinctrl_pin(110, "rgmii_mdc"), - pinctrl_pin(111, "rgmii_intr_n"), - pinctrl_pin(112, "i2s_mclk"), - pinctrl_pin(113, "i2s_bclk"), - pinctrl_pin(114, "i2s_ws"), - pinctrl_pin(115, "i2s_dout0"), - pinctrl_pin(116, "i2s_dout1"), - pinctrl_pin(117, "i2s_dout2"), - pinctrl_pin(118, "i2s_din"), - pinctrl_pin(119, "gpio_0"), - pinctrl_pin(120, "gpio_1"), - pinctrl_pin(121, "gpio_2"), - pinctrl_pin(122, "gpio_3"), - pinctrl_pin(123, "gpio_4"), - pinctrl_pin(124, "gpio_5"), - pinctrl_pin(125, "gpio_6"), - pinctrl_pin(126, "gpio_7"), - pinctrl_pin(127, "sda_0"), - pinctrl_pin(128, "scl_0"), - pinctrl_pin(129, "coex_pio_0"), - pinctrl_pin(130, "coex_pio_1"), - pinctrl_pin(131, "coex_pio_2"), - pinctrl_pin(132, "coex_pio_3"), - pinctrl_pin(133, "uart0_tx"), - pinctrl_pin(134, "uart0_rx"), - pinctrl_pin(135, "uart1_tx"), - pinctrl_pin(136, "uart1_rx"), - pinctrl_pin(137, "uart3_tx"), - pinctrl_pin(138, "uart3_rx"), - pinctrl_pin(139, "uart4_tx"), - pinctrl_pin(140, "uart4_rx"), - pinctrl_pin(141, "usp0_clk"), - pinctrl_pin(142, "usp0_tx"), - pinctrl_pin(143, "usp0_rx"), - pinctrl_pin(144, "usp0_fs"), - pinctrl_pin(145, "usp1_clk"), - pinctrl_pin(146, "usp1_tx"), - pinctrl_pin(147, "usp1_rx"), - pinctrl_pin(148, "usp1_fs"), - pinctrl_pin(149, "lvds_tx0d4p"), - pinctrl_pin(150, "lvds_tx0d4n"), - pinctrl_pin(151, "lvds_tx0d3p"), - pinctrl_pin(152, "lvds_tx0d3n"), - pinctrl_pin(153, "lvds_tx0d2p"), - pinctrl_pin(154, "lvds_tx0d2n"), - pinctrl_pin(155, "lvds_tx0d1p"), - pinctrl_pin(156, "lvds_tx0d1n"), - pinctrl_pin(157, "lvds_tx0d0p"), - pinctrl_pin(158, "lvds_tx0d0n"), - pinctrl_pin(159, "jtag_tdo"), - pinctrl_pin(160, "jtag_tms"), - pinctrl_pin(161, "jtag_tck"), - pinctrl_pin(162, "jtag_tdi"), - pinctrl_pin(163, "jtag_trstn"), -}; - -static struct atlas7_pad_config atlas7_ioc_pad_confs[] = { - /* the configuration of ioc_rtc pads */ - padconf(0, 3, 0x0, 0x100, 0x200, -1, 0, 0, 0, 0), - padconf(1, 3, 0x0, 0x100, 0x200, -1, 4, 2, 2, 0), - padconf(2, 3, 0x0, 0x100, 0x200, -1, 8, 4, 4, 0), - padconf(3, 5, 0x0, 0x100, 0x200, -1, 12, 6, 6, 0), - padconf(4, 4, 0x0, 0x100, 0x200, -1, 16, 8, 8, 0), - padconf(5, 4, 0x0, 0x100, 0x200, -1, 20, 10, 10, 0), - padconf(6, 3, 0x0, 0x100, 0x200, -1, 24, 12, 12, 0), - padconf(7, 3, 0x0, 0x100, 0x200, -1, 28, 14, 14, 0), - padconf(8, 3, 0x8, 0x100, 0x200, -1, 0, 16, 16, 0), - padconf(9, 3, 0x8, 0x100, 0x200, -1, 4, 18, 18, 0), - padconf(10, 4, 0x8, 0x100, 0x200, -1, 8, 20, 20, 0), - padconf(11, 4, 0x8, 0x100, 0x200, -1, 12, 22, 22, 0), - padconf(12, 5, 0x8, 0x100, 0x200, -1, 16, 24, 24, 0), - padconf(13, 6, 0x8, 0x100, 0x200, -1, 20, 26, 26, 0), - padconf(14, 5, 0x8, 0x100, 0x200, -1, 24, 28, 28, 0), - padconf(15, 5, 0x8, 0x100, 0x200, -1, 28, 30, 30, 0), - padconf(16, 5, 0x10, 0x108, 0x208, -1, 0, 0, 0, 0), - padconf(17, 5, 0x10, 0x108, 0x208, -1, 4, 2, 2, 0), - /* the configuration of ioc_top pads */ - padconf(18, 5, 0x80, 0x180, 0x300, -1, 0, 0, 0, 0), - padconf(19, 5, 0x80, 0x180, 0x300, -1, 4, 2, 2, 0), - padconf(20, 5, 0x80, 0x180, 0x300, -1, 8, 4, 4, 0), - padconf(21, 5, 0x80, 0x180, 0x300, -1, 12, 6, 6, 0), - padconf(22, 5, 0x88, 0x188, 0x308, -1, 0, 0, 0, 0), - padconf(23, 5, 0x88, 0x188, 0x308, -1, 4, 2, 2, 0), - padconf(24, 5, 0x88, 0x188, 0x308, -1, 8, 4, 4, 0), - padconf(25, 6, 0x88, 0x188, 0x308, -1, 12, 6, 6, 0), - padconf(26, 5, 0x88, 0x188, 0x308, -1, 16, 8, 8, 0), - padconf(27, 6, 0x88, 0x188, 0x308, -1, 20, 10, 10, 0), - padconf(28, 5, 0x88, 0x188, 0x308, -1, 24, 12, 12, 0), - padconf(29, 5, 0x88, 0x188, 0x308, -1, 28, 14, 14, 0), - padconf(30, 5, 0x90, 0x188, 0x308, -1, 0, 16, 16, 0), - padconf(31, 2, 0x98, 0x190, 0x310, -1, 0, 0, 0, 0), - padconf(32, 1, 0x98, 0x190, 0x310, -1, 4, 2, 4, 0), - padconf(33, 1, 0x98, 0x190, 0x310, -1, 8, 4, 6, 0), - padconf(34, 1, 0x98, 0x190, 0x310, -1, 12, 6, 8, 0), - padconf(35, 1, 0x98, 0x190, 0x310, -1, 16, 8, 10, 0), - padconf(36, 1, 0x98, 0x190, 0x310, -1, 20, 10, 12, 0), - padconf(37, 1, 0xa0, 0x198, 0x318, -1, 0, 0, 0, 0), - padconf(38, 1, 0xa0, 0x198, 0x318, -1, 4, 2, 2, 0), - padconf(39, 1, 0xa0, 0x198, 0x318, -1, 8, 4, 4, 0), - padconf(40, 1, 0xa0, 0x198, 0x318, -1, 12, 6, 6, 0), - padconf(41, 1, 0xa0, 0x198, 0x318, -1, 16, 8, 8, 0), - padconf(42, 1, 0xa0, 0x198, 0x318, -1, 20, 10, 10, 0), - padconf(43, 1, 0xa0, 0x198, 0x318, -1, 24, 12, 12, 0), - padconf(44, 1, 0xa0, 0x198, 0x318, -1, 28, 14, 14, 0), - padconf(45, 0, 0xa8, 0x198, 0x318, -1, 0, 16, 16, 0), - padconf(46, 0, 0xa8, 0x198, 0x318, -1, 4, 18, 18, 0), - padconf(47, 1, 0xa8, 0x198, 0x318, -1, 8, 20, 20, 0), - padconf(48, 1, 0xa8, 0x198, 0x318, -1, 12, 22, 22, 0), - padconf(49, 1, 0xa8, 0x198, 0x318, -1, 16, 24, 24, 0), - padconf(50, 1, 0xa8, 0x198, 0x318, -1, 20, 26, 26, 0), - padconf(51, 1, 0xa8, 0x198, 0x318, -1, 24, 28, 28, 0), - padconf(52, 1, 0xa8, 0x198, 0x318, -1, 28, 30, 30, 0), - padconf(53, 0, 0xb0, 0x1a0, 0x320, -1, 0, 0, 0, 0), - padconf(54, 0, 0xb0, 0x1a0, 0x320, -1, 4, 2, 2, 0), - padconf(55, 0, 0xb0, 0x1a0, 0x320, -1, 8, 4, 4, 0), - padconf(56, 0, 0xb0, 0x1a0, 0x320, -1, 12, 6, 6, 0), - padconf(57, 0, 0xb0, 0x1a0, 0x320, -1, 16, 8, 8, 0), - padconf(58, 0, 0xb0, 0x1a0, 0x320, -1, 20, 10, 10, 0), - padconf(59, 0, 0xb0, 0x1a0, 0x320, -1, 24, 12, 12, 0), - padconf(60, 0, 0xb0, 0x1a0, 0x320, -1, 28, 14, 14, 0), - padconf(61, 0, 0xb8, 0x1a0, 0x320, -1, 0, 16, 16, 0), - padconf(62, 0, 0xb8, 0x1a0, 0x320, -1, 4, 18, 18, 0), - padconf(63, 0, 0xb8, 0x1a0, 0x320, -1, 8, 20, 20, 0), - padconf(64, 0, 0xb8, 0x1a0, 0x320, -1, 12, 22, 22, 0), - padconf(65, 0, 0xb8, 0x1a0, 0x320, -1, 16, 24, 24, 0), - padconf(66, 0, 0xb8, 0x1a0, 0x320, -1, 20, 26, 26, 0), - padconf(67, 0, 0xb8, 0x1a0, 0x320, -1, 24, 28, 28, 0), - padconf(68, 0, 0xb8, 0x1a0, 0x320, -1, 28, 30, 30, 0), - padconf(69, 0, 0xc0, 0x1a8, 0x328, -1, 0, 0, 0, 0), - padconf(70, 0, 0xc0, 0x1a8, 0x328, -1, 4, 2, 2, 0), - padconf(71, 0, 0xc0, 0x1a8, 0x328, -1, 8, 4, 4, 0), - padconf(72, 0, 0xc0, 0x1a8, 0x328, -1, 12, 6, 6, 0), - padconf(73, 0, 0xc0, 0x1a8, 0x328, -1, 16, 8, 8, 0), - padconf(74, 0, 0xc8, 0x1b0, 0x330, -1, 0, 0, 0, 0), - padconf(75, 0, 0xc8, 0x1b0, 0x330, -1, 4, 2, 2, 0), - padconf(76, 0, 0xc8, 0x1b0, 0x330, -1, 8, 4, 4, 0), - padconf(77, 0, 0xc8, 0x1b0, 0x330, -1, 12, 6, 6, 0), - padconf(78, 0, 0xc8, 0x1b0, 0x330, -1, 16, 8, 8, 0), - padconf(79, 0, 0xc8, 0x1b0, 0x330, -1, 20, 10, 10, 0), - padconf(80, 0, 0xc8, 0x1b0, 0x330, -1, 24, 12, 12, 0), - padconf(81, 0, 0xc8, 0x1b0, 0x330, -1, 28, 14, 14, 0), - padconf(82, 0, 0xd0, 0x1b0, 0x330, -1, 0, 16, 16, 0), - padconf(83, 0, 0xd0, 0x1b0, 0x330, -1, 4, 18, 18, 0), - padconf(84, 0, 0xd0, 0x1b0, 0x330, -1, 8, 20, 20, 0), - padconf(85, 2, 0xd8, 0x1b8, 0x338, -1, 0, 0, 0, 0), - padconf(86, 1, 0xd8, 0x1b8, 0x338, -1, 4, 4, 4, 0), - padconf(87, 1, 0xd8, 0x1b8, 0x338, -1, 8, 6, 6, 0), - padconf(88, 1, 0xd8, 0x1b8, 0x338, -1, 12, 8, 8, 0), - padconf(89, 1, 0xd8, 0x1b8, 0x338, -1, 16, 10, 10, 0), - padconf(90, 1, 0xd8, 0x1b8, 0x338, -1, 20, 12, 12, 0), - padconf(91, 2, 0xe0, 0x1c0, 0x340, -1, 0, 0, 0, 0), - padconf(92, 1, 0xe0, 0x1c0, 0x340, -1, 4, 4, 4, 0), - padconf(93, 1, 0xe0, 0x1c0, 0x340, -1, 8, 6, 6, 0), - padconf(94, 1, 0xe0, 0x1c0, 0x340, -1, 12, 8, 8, 0), - padconf(95, 1, 0xe0, 0x1c0, 0x340, -1, 16, 10, 10, 0), - padconf(96, 1, 0xe0, 0x1c0, 0x340, -1, 20, 12, 12, 0), - padconf(97, 0, 0xe8, 0x1c8, 0x348, -1, 0, 0, 0, 0), - padconf(98, 0, 0xe8, 0x1c8, 0x348, -1, 4, 2, 2, 0), - padconf(99, 0, 0xe8, 0x1c8, 0x348, -1, 8, 4, 4, 0), - padconf(100, 0, 0xe8, 0x1c8, 0x348, -1, 12, 6, 6, 0), - padconf(101, 2, 0xe8, 0x1c8, 0x348, -1, 16, 8, 8, 0), - padconf(102, 0, 0xe8, 0x1c8, 0x348, -1, 20, 12, 12, 0), - padconf(103, 0, 0xe8, 0x1c8, 0x348, -1, 24, 14, 14, 0), - padconf(104, 0, 0xe8, 0x1c8, 0x348, -1, 28, 16, 16, 0), - padconf(105, 0, 0xf0, 0x1c8, 0x348, -1, 0, 18, 18, 0), - padconf(106, 0, 0xf0, 0x1c8, 0x348, -1, 4, 20, 20, 0), - padconf(107, 0, 0xf0, 0x1c8, 0x348, -1, 8, 22, 22, 0), - padconf(108, 0, 0xf0, 0x1c8, 0x348, -1, 12, 24, 24, 0), - padconf(109, 1, 0xf0, 0x1c8, 0x348, -1, 16, 26, 26, 0), - padconf(110, 0, 0xf0, 0x1c8, 0x348, -1, 20, 28, 28, 0), - padconf(111, 1, 0xf0, 0x1c8, 0x348, -1, 24, 30, 30, 0), - padconf(112, 5, 0xf8, 0x200, 0x350, -1, 0, 0, 0, 0), - padconf(113, 5, 0xf8, 0x200, 0x350, -1, 4, 2, 2, 0), - padconf(114, 5, 0xf8, 0x200, 0x350, -1, 8, 4, 4, 0), - padconf(115, 5, 0xf8, 0x200, 0x350, -1, 12, 6, 6, 0), - padconf(116, 5, 0xf8, 0x200, 0x350, -1, 16, 8, 8, 0), - padconf(117, 5, 0xf8, 0x200, 0x350, -1, 20, 10, 10, 0), - padconf(118, 5, 0xf8, 0x200, 0x350, -1, 24, 12, 12, 0), - padconf(119, 5, 0x100, 0x250, 0x358, -1, 0, 0, 0, 0), - padconf(120, 5, 0x100, 0x250, 0x358, -1, 4, 2, 2, 0), - padconf(121, 5, 0x100, 0x250, 0x358, -1, 8, 4, 4, 0), - padconf(122, 5, 0x100, 0x250, 0x358, -1, 12, 6, 6, 0), - padconf(123, 6, 0x100, 0x250, 0x358, -1, 16, 8, 8, 0), - padconf(124, 6, 0x100, 0x250, 0x358, -1, 20, 10, 10, 0), - padconf(125, 6, 0x100, 0x250, 0x358, -1, 24, 12, 12, 0), - padconf(126, 6, 0x100, 0x250, 0x358, -1, 28, 14, 14, 0), - padconf(127, 6, 0x108, 0x250, 0x358, -1, 16, 24, 24, 0), - padconf(128, 6, 0x108, 0x250, 0x358, -1, 20, 26, 26, 0), - padconf(129, 0, 0x110, 0x258, 0x360, -1, 0, 0, 0, 0), - padconf(130, 0, 0x110, 0x258, 0x360, -1, 4, 2, 2, 0), - padconf(131, 0, 0x110, 0x258, 0x360, -1, 8, 4, 4, 0), - padconf(132, 0, 0x110, 0x258, 0x360, -1, 12, 6, 6, 0), - padconf(133, 6, 0x118, 0x260, 0x368, -1, 0, 0, 0, 0), - padconf(134, 6, 0x118, 0x260, 0x368, -1, 4, 2, 2, 0), - padconf(135, 6, 0x118, 0x260, 0x368, -1, 16, 8, 8, 0), - padconf(136, 6, 0x118, 0x260, 0x368, -1, 20, 10, 10, 0), - padconf(137, 6, 0x118, 0x260, 0x368, -1, 24, 12, 12, 0), - padconf(138, 6, 0x118, 0x260, 0x368, -1, 28, 14, 14, 0), - padconf(139, 6, 0x120, 0x260, 0x368, -1, 0, 16, 16, 0), - padconf(140, 6, 0x120, 0x260, 0x368, -1, 4, 18, 18, 0), - padconf(141, 5, 0x128, 0x268, 0x378, -1, 0, 0, 0, 0), - padconf(142, 5, 0x128, 0x268, 0x378, -1, 4, 2, 2, 0), - padconf(143, 5, 0x128, 0x268, 0x378, -1, 8, 4, 4, 0), - padconf(144, 5, 0x128, 0x268, 0x378, -1, 12, 6, 6, 0), - padconf(145, 5, 0x128, 0x268, 0x378, -1, 16, 8, 8, 0), - padconf(146, 5, 0x128, 0x268, 0x378, -1, 20, 10, 10, 0), - padconf(147, 5, 0x128, 0x268, 0x378, -1, 24, 12, 12, 0), - padconf(148, 5, 0x128, 0x268, 0x378, -1, 28, 14, 14, 0), - padconf(149, 7, 0x130, 0x270, -1, 0x480, 0, 0, 0, 0), - padconf(150, 7, 0x130, 0x270, -1, 0x480, 4, 2, 0, 1), - padconf(151, 7, 0x130, 0x270, -1, 0x480, 8, 4, 0, 2), - padconf(152, 7, 0x130, 0x270, -1, 0x480, 12, 6, 0, 3), - padconf(153, 7, 0x130, 0x270, -1, 0x480, 16, 8, 0, 4), - padconf(154, 7, 0x130, 0x270, -1, 0x480, 20, 10, 0, 5), - padconf(155, 7, 0x130, 0x270, -1, 0x480, 24, 12, 0, 6), - padconf(156, 7, 0x130, 0x270, -1, 0x480, 28, 14, 0, 7), - padconf(157, 7, 0x138, 0x278, -1, 0x480, 0, 0, 0, 8), - padconf(158, 7, 0x138, 0x278, -1, 0x480, 4, 2, 0, 9), - padconf(159, 5, 0x140, 0x280, 0x380, -1, 0, 0, 0, 0), - padconf(160, 6, 0x140, 0x280, 0x380, -1, 4, 2, 2, 0), - padconf(161, 5, 0x140, 0x280, 0x380, -1, 8, 4, 4, 0), - padconf(162, 6, 0x140, 0x280, 0x380, -1, 12, 6, 6, 0), - padconf(163, 6, 0x140, 0x280, 0x380, -1, 16, 8, 8, 0), -}; - -/* pin list of each pin group */ -static const unsigned int gnss_gpio_pins[] = { 119, 120, 121, 122, 123, 124, - 125, 126, 127, 128, 22, 23, 24, 25, 26, 27, 28, 29, 30, }; -static const unsigned int lcd_vip_gpio_pins[] = { 74, 75, 76, 77, 78, 79, 80, - 81, 82, 83, 84, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, - 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, }; -static const unsigned int sdio_i2s_gpio_pins[] = { 31, 32, 33, 34, 35, 36, - 85, 86, 87, 88, 89, 90, 129, 130, 131, 132, 91, 92, 93, 94, - 95, 96, 112, 113, 114, 115, 116, 117, 118, }; -static const unsigned int sp_rgmii_gpio_pins[] = { 97, 98, 99, 100, 101, 102, - 103, 104, 105, 106, 107, 108, 109, 110, 111, 18, 19, 20, 21, - 141, 142, 143, 144, 145, 146, 147, 148, }; -static const unsigned int lvds_gpio_pins[] = { 157, 158, 155, 156, 153, 154, - 151, 152, 149, 150, }; -static const unsigned int jtag_uart_nand_gpio_pins[] = { 44, 43, 42, 41, 40, - 39, 38, 37, 46, 47, 48, 49, 50, 52, 51, 45, 133, 134, 135, - 136, 137, 138, 139, 140, 159, 160, 161, 162, 163, }; -static const unsigned int rtc_gpio_pins[] = { 0, 1, 2, 3, 4, 10, 11, 12, 13, - 14, 15, 16, 17, 9, }; -static const unsigned int audio_ac97_pins[] = { 113, 118, 115, 114, }; -static const unsigned int audio_digmic_pins0[] = { 51, }; -static const unsigned int audio_digmic_pins1[] = { 122, }; -static const unsigned int audio_digmic_pins2[] = { 161, }; -static const unsigned int audio_func_dbg_pins[] = { 141, 144, 44, 43, 42, 41, - 40, 39, 38, 37, 74, 75, 76, 77, 78, 79, 81, 113, 114, 118, - 115, 49, 50, 142, 143, 80, }; -static const unsigned int audio_i2s_pins[] = { 118, 115, 116, 117, 112, 113, - 114, }; -static const unsigned int audio_i2s_2ch_pins[] = { 118, 115, 112, 113, 114, }; -static const unsigned int audio_i2s_extclk_pins[] = { 112, }; -static const unsigned int audio_spdif_out_pins0[] = { 112, }; -static const unsigned int audio_spdif_out_pins1[] = { 116, }; -static const unsigned int audio_spdif_out_pins2[] = { 142, }; -static const unsigned int audio_uart0_basic_pins[] = { 143, 142, 141, 144, }; -static const unsigned int audio_uart0_urfs_pins0[] = { 117, }; -static const unsigned int audio_uart0_urfs_pins1[] = { 139, }; -static const unsigned int audio_uart0_urfs_pins2[] = { 163, }; -static const unsigned int audio_uart0_urfs_pins3[] = { 162, }; -static const unsigned int audio_uart1_basic_pins[] = { 147, 146, 145, 148, }; -static const unsigned int audio_uart1_urfs_pins0[] = { 117, }; -static const unsigned int audio_uart1_urfs_pins1[] = { 140, }; -static const unsigned int audio_uart1_urfs_pins2[] = { 163, }; -static const unsigned int audio_uart2_urfs_pins0[] = { 139, }; -static const unsigned int audio_uart2_urfs_pins1[] = { 163, }; -static const unsigned int audio_uart2_urfs_pins2[] = { 96, }; -static const unsigned int audio_uart2_urxd_pins0[] = { 20, }; -static const unsigned int audio_uart2_urxd_pins1[] = { 109, }; -static const unsigned int audio_uart2_urxd_pins2[] = { 93, }; -static const unsigned int audio_uart2_usclk_pins0[] = { 19, }; -static const unsigned int audio_uart2_usclk_pins1[] = { 101, }; -static const unsigned int audio_uart2_usclk_pins2[] = { 91, }; -static const unsigned int audio_uart2_utfs_pins0[] = { 18, }; -static const unsigned int audio_uart2_utfs_pins1[] = { 111, }; -static const unsigned int audio_uart2_utfs_pins2[] = { 94, }; -static const unsigned int audio_uart2_utxd_pins0[] = { 21, }; -static const unsigned int audio_uart2_utxd_pins1[] = { 110, }; -static const unsigned int audio_uart2_utxd_pins2[] = { 92, }; -static const unsigned int c_can_trnsvr_en_pins0[] = { 2, }; -static const unsigned int c_can_trnsvr_en_pins1[] = { 0, }; -static const unsigned int c_can_trnsvr_intr_pins[] = { 1, }; -static const unsigned int c_can_trnsvr_stb_n_pins[] = { 3, }; -static const unsigned int c0_can_rxd_trnsv0_pins[] = { 11, }; -static const unsigned int c0_can_rxd_trnsv1_pins[] = { 2, }; -static const unsigned int c0_can_txd_trnsv0_pins[] = { 10, }; -static const unsigned int c0_can_txd_trnsv1_pins[] = { 3, }; -static const unsigned int c1_can_rxd_pins0[] = { 138, }; -static const unsigned int c1_can_rxd_pins1[] = { 147, }; -static const unsigned int c1_can_rxd_pins2[] = { 2, }; -static const unsigned int c1_can_rxd_pins3[] = { 162, }; -static const unsigned int c1_can_txd_pins0[] = { 137, }; -static const unsigned int c1_can_txd_pins1[] = { 146, }; -static const unsigned int c1_can_txd_pins2[] = { 3, }; -static const unsigned int c1_can_txd_pins3[] = { 161, }; -static const unsigned int ca_audio_lpc_pins[] = { 62, 63, 64, 65, 66, 67, 68, - 69, 70, 71, }; -static const unsigned int ca_bt_lpc_pins[] = { 85, 86, 87, 88, 89, 90, }; -static const unsigned int ca_coex_pins[] = { 129, 130, 131, 132, }; -static const unsigned int ca_curator_lpc_pins[] = { 57, 58, 59, 60, }; -static const unsigned int ca_pcm_debug_pins[] = { 91, 93, 94, 92, }; -static const unsigned int ca_pio_pins[] = { 121, 122, 125, 126, 38, 37, 47, - 49, 50, 54, 55, 56, }; -static const unsigned int ca_sdio_debug_pins[] = { 40, 39, 44, 43, 42, 41, }; -static const unsigned int ca_spi_pins[] = { 82, 79, 80, 81, }; -static const unsigned int ca_trb_pins[] = { 91, 93, 94, 95, 96, 78, 74, 75, - 76, 77, }; -static const unsigned int ca_uart_debug_pins[] = { 136, 135, 134, 133, }; -static const unsigned int clkc_pins0[] = { 30, 47, }; -static const unsigned int clkc_pins1[] = { 78, 54, }; -static const unsigned int gn_gnss_i2c_pins[] = { 128, 127, }; -static const unsigned int gn_gnss_uart_nopause_pins[] = { 134, 133, }; -static const unsigned int gn_gnss_uart_pins[] = { 134, 133, 136, 135, }; -static const unsigned int gn_trg_spi_pins0[] = { 22, 25, 23, 24, }; -static const unsigned int gn_trg_spi_pins1[] = { 82, 79, 80, 81, }; -static const unsigned int cvbs_dbg_pins[] = { 54, 53, 82, 74, 75, 76, 77, 78, - 79, 80, 81, 83, 84, 73, 55, 56, }; -static const unsigned int cvbs_dbg_test_pins0[] = { 57, }; -static const unsigned int cvbs_dbg_test_pins1[] = { 58, }; -static const unsigned int cvbs_dbg_test_pins2[] = { 59, }; -static const unsigned int cvbs_dbg_test_pins3[] = { 60, }; -static const unsigned int cvbs_dbg_test_pins4[] = { 61, }; -static const unsigned int cvbs_dbg_test_pins5[] = { 62, }; -static const unsigned int cvbs_dbg_test_pins6[] = { 63, }; -static const unsigned int cvbs_dbg_test_pins7[] = { 64, }; -static const unsigned int cvbs_dbg_test_pins8[] = { 65, }; -static const unsigned int cvbs_dbg_test_pins9[] = { 66, }; -static const unsigned int cvbs_dbg_test_pins10[] = { 67, }; -static const unsigned int cvbs_dbg_test_pins11[] = { 68, }; -static const unsigned int cvbs_dbg_test_pins12[] = { 69, }; -static const unsigned int cvbs_dbg_test_pins13[] = { 70, }; -static const unsigned int cvbs_dbg_test_pins14[] = { 71, }; -static const unsigned int cvbs_dbg_test_pins15[] = { 72, }; -static const unsigned int gn_gnss_power_pins[] = { 123, 124, 121, 122, 125, - 120, }; -static const unsigned int gn_gnss_sw_status_pins[] = { 57, 58, 59, 60, 61, - 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 55, 56, 54, }; -static const unsigned int gn_gnss_eclk_pins[] = { 113, }; -static const unsigned int gn_gnss_irq1_pins0[] = { 112, }; -static const unsigned int gn_gnss_irq2_pins0[] = { 118, }; -static const unsigned int gn_gnss_tm_pins[] = { 115, }; -static const unsigned int gn_gnss_tsync_pins[] = { 114, }; -static const unsigned int gn_io_gnsssys_sw_cfg_pins[] = { 44, 43, 42, 41, 40, - 39, 38, 37, 49, 50, 91, 92, 93, 94, 95, 96, }; -static const unsigned int gn_trg_pins0[] = { 29, 28, 26, 27, }; -static const unsigned int gn_trg_pins1[] = { 77, 76, 74, 75, }; -static const unsigned int gn_trg_shutdown_pins0[] = { 30, }; -static const unsigned int gn_trg_shutdown_pins1[] = { 83, }; -static const unsigned int gn_trg_shutdown_pins2[] = { 117, }; -static const unsigned int gn_trg_shutdown_pins3[] = { 123, }; -static const unsigned int i2c0_pins[] = { 128, 127, }; -static const unsigned int i2c1_pins[] = { 126, 125, }; -static const unsigned int i2s0_pins[] = { 91, 93, 94, 92, }; -static const unsigned int i2s1_basic_pins[] = { 95, 96, }; -static const unsigned int i2s1_rxd0_pins0[] = { 61, }; -static const unsigned int i2s1_rxd0_pins1[] = { 131, }; -static const unsigned int i2s1_rxd0_pins2[] = { 129, }; -static const unsigned int i2s1_rxd0_pins3[] = { 117, }; -static const unsigned int i2s1_rxd0_pins4[] = { 83, }; -static const unsigned int i2s1_rxd1_pins0[] = { 72, }; -static const unsigned int i2s1_rxd1_pins1[] = { 132, }; -static const unsigned int i2s1_rxd1_pins2[] = { 130, }; -static const unsigned int i2s1_rxd1_pins3[] = { 118, }; -static const unsigned int i2s1_rxd1_pins4[] = { 84, }; -static const unsigned int jtag_jt_dbg_nsrst_pins[] = { 125, }; -static const unsigned int jtag_ntrst_pins0[] = { 4, }; -static const unsigned int jtag_ntrst_pins1[] = { 163, }; -static const unsigned int jtag_swdiotms_pins0[] = { 2, }; -static const unsigned int jtag_swdiotms_pins1[] = { 160, }; -static const unsigned int jtag_tck_pins0[] = { 0, }; -static const unsigned int jtag_tck_pins1[] = { 161, }; -static const unsigned int jtag_tdi_pins0[] = { 1, }; -static const unsigned int jtag_tdi_pins1[] = { 162, }; -static const unsigned int jtag_tdo_pins0[] = { 3, }; -static const unsigned int jtag_tdo_pins1[] = { 159, }; -static const unsigned int ks_kas_spi_pins0[] = { 141, 144, 143, 142, }; -static const unsigned int ld_ldd_pins[] = { 57, 58, 59, 60, 61, 62, 63, 64, - 65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79, 80, - 81, 56, 53, }; -static const unsigned int ld_ldd_16bit_pins[] = { 57, 58, 59, 60, 61, 62, 63, - 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, }; -static const unsigned int ld_ldd_fck_pins[] = { 55, }; -static const unsigned int ld_ldd_lck_pins[] = { 54, }; -static const unsigned int lr_lcdrom_pins[] = { 73, 54, 57, 58, 59, 60, 61, - 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, 55, }; -static const unsigned int lvds_analog_pins[] = { 149, 150, 151, 152, 153, 154, - 155, 156, 157, 158, }; -static const unsigned int nd_df_basic_pins[] = { 44, 43, 42, 41, 40, 39, 38, - 37, 47, 46, 52, 45, 49, 50, 48, }; -static const unsigned int nd_df_wp_pins[] = { 124, }; -static const unsigned int nd_df_cs_pins[] = { 51, }; -static const unsigned int ps_pins[] = { 120, 119, 121, }; -static const unsigned int ps_no_dir_pins[] = { 119, }; -static const unsigned int pwc_core_on_pins[] = { 8, }; -static const unsigned int pwc_ext_on_pins[] = { 6, }; -static const unsigned int pwc_gpio3_clk_pins[] = { 3, }; -static const unsigned int pwc_io_on_pins[] = { 9, }; -static const unsigned int pwc_lowbatt_b_pins0[] = { 4, }; -static const unsigned int pwc_mem_on_pins[] = { 7, }; -static const unsigned int pwc_on_key_b_pins0[] = { 5, }; -static const unsigned int pwc_wakeup_src0_pins[] = { 0, }; -static const unsigned int pwc_wakeup_src1_pins[] = { 1, }; -static const unsigned int pwc_wakeup_src2_pins[] = { 2, }; -static const unsigned int pwc_wakeup_src3_pins[] = { 3, }; -static const unsigned int pw_cko0_pins0[] = { 123, }; -static const unsigned int pw_cko0_pins1[] = { 101, }; -static const unsigned int pw_cko0_pins2[] = { 82, }; -static const unsigned int pw_cko0_pins3[] = { 162, }; -static const unsigned int pw_cko1_pins0[] = { 124, }; -static const unsigned int pw_cko1_pins1[] = { 110, }; -static const unsigned int pw_cko1_pins2[] = { 163, }; -static const unsigned int pw_i2s01_clk_pins0[] = { 125, }; -static const unsigned int pw_i2s01_clk_pins1[] = { 117, }; -static const unsigned int pw_i2s01_clk_pins2[] = { 132, }; -static const unsigned int pw_pwm0_pins0[] = { 119, }; -static const unsigned int pw_pwm0_pins1[] = { 159, }; -static const unsigned int pw_pwm1_pins0[] = { 120, }; -static const unsigned int pw_pwm1_pins1[] = { 160, }; -static const unsigned int pw_pwm1_pins2[] = { 131, }; -static const unsigned int pw_pwm2_pins0[] = { 121, }; -static const unsigned int pw_pwm2_pins1[] = { 98, }; -static const unsigned int pw_pwm2_pins2[] = { 161, }; -static const unsigned int pw_pwm3_pins0[] = { 122, }; -static const unsigned int pw_pwm3_pins1[] = { 73, }; -static const unsigned int pw_pwm_cpu_vol_pins0[] = { 121, }; -static const unsigned int pw_pwm_cpu_vol_pins1[] = { 98, }; -static const unsigned int pw_pwm_cpu_vol_pins2[] = { 161, }; -static const unsigned int pw_backlight_pins0[] = { 122, }; -static const unsigned int pw_backlight_pins1[] = { 73, }; -static const unsigned int rg_eth_mac_pins[] = { 108, 103, 104, 105, 106, 107, - 102, 97, 98, 99, 100, 101, }; -static const unsigned int rg_gmac_phy_intr_n_pins[] = { 111, }; -static const unsigned int rg_rgmii_mac_pins[] = { 109, 110, }; -static const unsigned int rg_rgmii_phy_ref_clk_pins0[] = { 111, }; -static const unsigned int rg_rgmii_phy_ref_clk_pins1[] = { 53, }; -static const unsigned int sd0_pins[] = { 46, 47, 44, 43, 42, 41, 40, 39, 38, - 37, }; -static const unsigned int sd0_4bit_pins[] = { 46, 47, 44, 43, 42, 41, }; -static const unsigned int sd1_pins[] = { 48, 49, 44, 43, 42, 41, 40, 39, 38, - 37, }; -static const unsigned int sd1_4bit_pins0[] = { 48, 49, 44, 43, 42, 41, }; -static const unsigned int sd1_4bit_pins1[] = { 48, 49, 40, 39, 38, 37, }; -static const unsigned int sd2_basic_pins[] = { 31, 32, 33, 34, 35, 36, }; -static const unsigned int sd2_cdb_pins0[] = { 124, }; -static const unsigned int sd2_cdb_pins1[] = { 161, }; -static const unsigned int sd2_wpb_pins0[] = { 123, }; -static const unsigned int sd2_wpb_pins1[] = { 163, }; -static const unsigned int sd3_9_pins[] = { 85, 86, 87, 88, 89, 90, }; -static const unsigned int sd5_pins[] = { 91, 92, 93, 94, 95, 96, }; -static const unsigned int sd6_pins0[] = { 79, 78, 74, 75, 76, 77, }; -static const unsigned int sd6_pins1[] = { 101, 99, 100, 110, 109, 111, }; -static const unsigned int sp0_ext_ldo_on_pins[] = { 4, }; -static const unsigned int sp0_qspi_pins[] = { 12, 13, 14, 15, 16, 17, }; -static const unsigned int sp1_spi_pins[] = { 19, 20, 21, 18, }; -static const unsigned int tpiu_trace_pins[] = { 53, 56, 57, 58, 59, 60, 61, - 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, }; -static const unsigned int uart0_pins[] = { 121, 120, 134, 133, }; -static const unsigned int uart0_nopause_pins[] = { 134, 133, }; -static const unsigned int uart1_pins[] = { 136, 135, }; -static const unsigned int uart2_cts_pins0[] = { 132, }; -static const unsigned int uart2_cts_pins1[] = { 162, }; -static const unsigned int uart2_rts_pins0[] = { 131, }; -static const unsigned int uart2_rts_pins1[] = { 161, }; -static const unsigned int uart2_rxd_pins0[] = { 11, }; -static const unsigned int uart2_rxd_pins1[] = { 160, }; -static const unsigned int uart2_rxd_pins2[] = { 130, }; -static const unsigned int uart2_txd_pins0[] = { 10, }; -static const unsigned int uart2_txd_pins1[] = { 159, }; -static const unsigned int uart2_txd_pins2[] = { 129, }; -static const unsigned int uart3_cts_pins0[] = { 125, }; -static const unsigned int uart3_cts_pins1[] = { 111, }; -static const unsigned int uart3_cts_pins2[] = { 140, }; -static const unsigned int uart3_rts_pins0[] = { 126, }; -static const unsigned int uart3_rts_pins1[] = { 109, }; -static const unsigned int uart3_rts_pins2[] = { 139, }; -static const unsigned int uart3_rxd_pins0[] = { 138, }; -static const unsigned int uart3_rxd_pins1[] = { 84, }; -static const unsigned int uart3_rxd_pins2[] = { 162, }; -static const unsigned int uart3_txd_pins0[] = { 137, }; -static const unsigned int uart3_txd_pins1[] = { 83, }; -static const unsigned int uart3_txd_pins2[] = { 161, }; -static const unsigned int uart4_basic_pins[] = { 140, 139, }; -static const unsigned int uart4_cts_pins0[] = { 122, }; -static const unsigned int uart4_cts_pins1[] = { 100, }; -static const unsigned int uart4_cts_pins2[] = { 117, }; -static const unsigned int uart4_rts_pins0[] = { 123, }; -static const unsigned int uart4_rts_pins1[] = { 99, }; -static const unsigned int uart4_rts_pins2[] = { 116, }; -static const unsigned int usb0_drvvbus_pins0[] = { 51, }; -static const unsigned int usb0_drvvbus_pins1[] = { 162, }; -static const unsigned int usb1_drvvbus_pins0[] = { 134, }; -static const unsigned int usb1_drvvbus_pins1[] = { 163, }; -static const unsigned int visbus_dout_pins[] = { 57, 58, 59, 60, 61, 62, 63, - 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 54, 55, 56, 85, 86, - 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, }; -static const unsigned int vi_vip1_pins[] = { 74, 75, 76, 77, 78, 79, 80, 81, - 82, 83, 84, 103, 104, 105, 106, 107, 102, 97, 98, }; -static const unsigned int vi_vip1_ext_pins[] = { 74, 75, 76, 77, 78, 79, 80, - 81, 82, 83, 84, 108, 103, 104, 105, 106, 107, 102, 97, 98, - 99, 100, }; -static const unsigned int vi_vip1_low8bit_pins[] = { 74, 75, 76, 77, 78, 79, - 80, 81, 82, 83, 84, }; -static const unsigned int vi_vip1_high8bit_pins[] = { 82, 83, 84, 103, 104, - 105, 106, 107, 102, 97, 98, }; - -/* definition of pin group table */ -static struct atlas7_pin_group altas7_pin_groups[] = { - group("gnss_gpio_grp", gnss_gpio_pins), - group("lcd_vip_gpio_grp", lcd_vip_gpio_pins), - group("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins), - group("sp_rgmii_gpio_grp", sp_rgmii_gpio_pins), - group("lvds_gpio_grp", lvds_gpio_pins), - group("jtag_uart_nand_gpio_grp", jtag_uart_nand_gpio_pins), - group("rtc_gpio_grp", rtc_gpio_pins), - group("audio_ac97_grp", audio_ac97_pins), - group("audio_digmic_grp0", audio_digmic_pins0), - group("audio_digmic_grp1", audio_digmic_pins1), - group("audio_digmic_grp2", audio_digmic_pins2), - group("audio_func_dbg_grp", audio_func_dbg_pins), - group("audio_i2s_grp", audio_i2s_pins), - group("audio_i2s_2ch_grp", audio_i2s_2ch_pins), - group("audio_i2s_extclk_grp", audio_i2s_extclk_pins), - group("audio_spdif_out_grp0", audio_spdif_out_pins0), - group("audio_spdif_out_grp1", audio_spdif_out_pins1), - group("audio_spdif_out_grp2", audio_spdif_out_pins2), - group("audio_uart0_basic_grp", audio_uart0_basic_pins), - group("audio_uart0_urfs_grp0", audio_uart0_urfs_pins0), - group("audio_uart0_urfs_grp1", audio_uart0_urfs_pins1), - group("audio_uart0_urfs_grp2", audio_uart0_urfs_pins2), - group("audio_uart0_urfs_grp3", audio_uart0_urfs_pins3), - group("audio_uart1_basic_grp", audio_uart1_basic_pins), - group("audio_uart1_urfs_grp0", audio_uart1_urfs_pins0), - group("audio_uart1_urfs_grp1", audio_uart1_urfs_pins1), - group("audio_uart1_urfs_grp2", audio_uart1_urfs_pins2), - group("audio_uart2_urfs_grp0", audio_uart2_urfs_pins0), - group("audio_uart2_urfs_grp1", audio_uart2_urfs_pins1), - group("audio_uart2_urfs_grp2", audio_uart2_urfs_pins2), - group("audio_uart2_urxd_grp0", audio_uart2_urxd_pins0), - group("audio_uart2_urxd_grp1", audio_uart2_urxd_pins1), - group("audio_uart2_urxd_grp2", audio_uart2_urxd_pins2), - group("audio_uart2_usclk_grp0", audio_uart2_usclk_pins0), - group("audio_uart2_usclk_grp1", audio_uart2_usclk_pins1), - group("audio_uart2_usclk_grp2", audio_uart2_usclk_pins2), - group("audio_uart2_utfs_grp0", audio_uart2_utfs_pins0), - group("audio_uart2_utfs_grp1", audio_uart2_utfs_pins1), - group("audio_uart2_utfs_grp2", audio_uart2_utfs_pins2), - group("audio_uart2_utxd_grp0", audio_uart2_utxd_pins0), - group("audio_uart2_utxd_grp1", audio_uart2_utxd_pins1), - group("audio_uart2_utxd_grp2", audio_uart2_utxd_pins2), - group("c_can_trnsvr_en_grp0", c_can_trnsvr_en_pins0), - group("c_can_trnsvr_en_grp1", c_can_trnsvr_en_pins1), - group("c_can_trnsvr_intr_grp", c_can_trnsvr_intr_pins), - group("c_can_trnsvr_stb_n_grp", c_can_trnsvr_stb_n_pins), - group("c0_can_rxd_trnsv0_grp", c0_can_rxd_trnsv0_pins), - group("c0_can_rxd_trnsv1_grp", c0_can_rxd_trnsv1_pins), - group("c0_can_txd_trnsv0_grp", c0_can_txd_trnsv0_pins), - group("c0_can_txd_trnsv1_grp", c0_can_txd_trnsv1_pins), - group("c1_can_rxd_grp0", c1_can_rxd_pins0), - group("c1_can_rxd_grp1", c1_can_rxd_pins1), - group("c1_can_rxd_grp2", c1_can_rxd_pins2), - group("c1_can_rxd_grp3", c1_can_rxd_pins3), - group("c1_can_txd_grp0", c1_can_txd_pins0), - group("c1_can_txd_grp1", c1_can_txd_pins1), - group("c1_can_txd_grp2", c1_can_txd_pins2), - group("c1_can_txd_grp3", c1_can_txd_pins3), - group("ca_audio_lpc_grp", ca_audio_lpc_pins), - group("ca_bt_lpc_grp", ca_bt_lpc_pins), - group("ca_coex_grp", ca_coex_pins), - group("ca_curator_lpc_grp", ca_curator_lpc_pins), - group("ca_pcm_debug_grp", ca_pcm_debug_pins), - group("ca_pio_grp", ca_pio_pins), - group("ca_sdio_debug_grp", ca_sdio_debug_pins), - group("ca_spi_grp", ca_spi_pins), - group("ca_trb_grp", ca_trb_pins), - group("ca_uart_debug_grp", ca_uart_debug_pins), - group("clkc_grp0", clkc_pins0), - group("clkc_grp1", clkc_pins1), - group("gn_gnss_i2c_grp", gn_gnss_i2c_pins), - group("gn_gnss_uart_nopause_grp", gn_gnss_uart_nopause_pins), - group("gn_gnss_uart_grp", gn_gnss_uart_pins), - group("gn_trg_spi_grp0", gn_trg_spi_pins0), - group("gn_trg_spi_grp1", gn_trg_spi_pins1), - group("cvbs_dbg_grp", cvbs_dbg_pins), - group("cvbs_dbg_test_grp0", cvbs_dbg_test_pins0), - group("cvbs_dbg_test_grp1", cvbs_dbg_test_pins1), - group("cvbs_dbg_test_grp2", cvbs_dbg_test_pins2), - group("cvbs_dbg_test_grp3", cvbs_dbg_test_pins3), - group("cvbs_dbg_test_grp4", cvbs_dbg_test_pins4), - group("cvbs_dbg_test_grp5", cvbs_dbg_test_pins5), - group("cvbs_dbg_test_grp6", cvbs_dbg_test_pins6), - group("cvbs_dbg_test_grp7", cvbs_dbg_test_pins7), - group("cvbs_dbg_test_grp8", cvbs_dbg_test_pins8), - group("cvbs_dbg_test_grp9", cvbs_dbg_test_pins9), - group("cvbs_dbg_test_grp10", cvbs_dbg_test_pins10), - group("cvbs_dbg_test_grp11", cvbs_dbg_test_pins11), - group("cvbs_dbg_test_grp12", cvbs_dbg_test_pins12), - group("cvbs_dbg_test_grp13", cvbs_dbg_test_pins13), - group("cvbs_dbg_test_grp14", cvbs_dbg_test_pins14), - group("cvbs_dbg_test_grp15", cvbs_dbg_test_pins15), - group("gn_gnss_power_grp", gn_gnss_power_pins), - group("gn_gnss_sw_status_grp", gn_gnss_sw_status_pins), - group("gn_gnss_eclk_grp", gn_gnss_eclk_pins), - group("gn_gnss_irq1_grp0", gn_gnss_irq1_pins0), - group("gn_gnss_irq2_grp0", gn_gnss_irq2_pins0), - group("gn_gnss_tm_grp", gn_gnss_tm_pins), - group("gn_gnss_tsync_grp", gn_gnss_tsync_pins), - group("gn_io_gnsssys_sw_cfg_grp", gn_io_gnsssys_sw_cfg_pins), - group("gn_trg_grp0", gn_trg_pins0), - group("gn_trg_grp1", gn_trg_pins1), - group("gn_trg_shutdown_grp0", gn_trg_shutdown_pins0), - group("gn_trg_shutdown_grp1", gn_trg_shutdown_pins1), - group("gn_trg_shutdown_grp2", gn_trg_shutdown_pins2), - group("gn_trg_shutdown_grp3", gn_trg_shutdown_pins3), - group("i2c0_grp", i2c0_pins), - group("i2c1_grp", i2c1_pins), - group("i2s0_grp", i2s0_pins), - group("i2s1_basic_grp", i2s1_basic_pins), - group("i2s1_rxd0_grp0", i2s1_rxd0_pins0), - group("i2s1_rxd0_grp1", i2s1_rxd0_pins1), - group("i2s1_rxd0_grp2", i2s1_rxd0_pins2), - group("i2s1_rxd0_grp3", i2s1_rxd0_pins3), - group("i2s1_rxd0_grp4", i2s1_rxd0_pins4), - group("i2s1_rxd1_grp0", i2s1_rxd1_pins0), - group("i2s1_rxd1_grp1", i2s1_rxd1_pins1), - group("i2s1_rxd1_grp2", i2s1_rxd1_pins2), - group("i2s1_rxd1_grp3", i2s1_rxd1_pins3), - group("i2s1_rxd1_grp4", i2s1_rxd1_pins4), - group("jtag_jt_dbg_nsrst_grp", jtag_jt_dbg_nsrst_pins), - group("jtag_ntrst_grp0", jtag_ntrst_pins0), - group("jtag_ntrst_grp1", jtag_ntrst_pins1), - group("jtag_swdiotms_grp0", jtag_swdiotms_pins0), - group("jtag_swdiotms_grp1", jtag_swdiotms_pins1), - group("jtag_tck_grp0", jtag_tck_pins0), - group("jtag_tck_grp1", jtag_tck_pins1), - group("jtag_tdi_grp0", jtag_tdi_pins0), - group("jtag_tdi_grp1", jtag_tdi_pins1), - group("jtag_tdo_grp0", jtag_tdo_pins0), - group("jtag_tdo_grp1", jtag_tdo_pins1), - group("ks_kas_spi_grp0", ks_kas_spi_pins0), - group("ld_ldd_grp", ld_ldd_pins), - group("ld_ldd_16bit_grp", ld_ldd_16bit_pins), - group("ld_ldd_fck_grp", ld_ldd_fck_pins), - group("ld_ldd_lck_grp", ld_ldd_lck_pins), - group("lr_lcdrom_grp", lr_lcdrom_pins), - group("lvds_analog_grp", lvds_analog_pins), - group("nd_df_basic_grp", nd_df_basic_pins), - group("nd_df_wp_grp", nd_df_wp_pins), - group("nd_df_cs_grp", nd_df_cs_pins), - group("ps_grp", ps_pins), - group("ps_no_dir_grp", ps_no_dir_pins), - group("pwc_core_on_grp", pwc_core_on_pins), - group("pwc_ext_on_grp", pwc_ext_on_pins), - group("pwc_gpio3_clk_grp", pwc_gpio3_clk_pins), - group("pwc_io_on_grp", pwc_io_on_pins), - group("pwc_lowbatt_b_grp0", pwc_lowbatt_b_pins0), - group("pwc_mem_on_grp", pwc_mem_on_pins), - group("pwc_on_key_b_grp0", pwc_on_key_b_pins0), - group("pwc_wakeup_src0_grp", pwc_wakeup_src0_pins), - group("pwc_wakeup_src1_grp", pwc_wakeup_src1_pins), - group("pwc_wakeup_src2_grp", pwc_wakeup_src2_pins), - group("pwc_wakeup_src3_grp", pwc_wakeup_src3_pins), - group("pw_cko0_grp0", pw_cko0_pins0), - group("pw_cko0_grp1", pw_cko0_pins1), - group("pw_cko0_grp2", pw_cko0_pins2), - group("pw_cko0_grp3", pw_cko0_pins3), - group("pw_cko1_grp0", pw_cko1_pins0), - group("pw_cko1_grp1", pw_cko1_pins1), - group("pw_cko1_grp2", pw_cko1_pins2), - group("pw_i2s01_clk_grp0", pw_i2s01_clk_pins0), - group("pw_i2s01_clk_grp1", pw_i2s01_clk_pins1), - group("pw_i2s01_clk_grp2", pw_i2s01_clk_pins2), - group("pw_pwm0_grp0", pw_pwm0_pins0), - group("pw_pwm0_grp1", pw_pwm0_pins1), - group("pw_pwm1_grp0", pw_pwm1_pins0), - group("pw_pwm1_grp1", pw_pwm1_pins1), - group("pw_pwm1_grp2", pw_pwm1_pins2), - group("pw_pwm2_grp0", pw_pwm2_pins0), - group("pw_pwm2_grp1", pw_pwm2_pins1), - group("pw_pwm2_grp2", pw_pwm2_pins2), - group("pw_pwm3_grp0", pw_pwm3_pins0), - group("pw_pwm3_grp1", pw_pwm3_pins1), - group("pw_pwm_cpu_vol_grp0", pw_pwm_cpu_vol_pins0), - group("pw_pwm_cpu_vol_grp1", pw_pwm_cpu_vol_pins1), - group("pw_pwm_cpu_vol_grp2", pw_pwm_cpu_vol_pins2), - group("pw_backlight_grp0", pw_backlight_pins0), - group("pw_backlight_grp1", pw_backlight_pins1), - group("rg_eth_mac_grp", rg_eth_mac_pins), - group("rg_gmac_phy_intr_n_grp", rg_gmac_phy_intr_n_pins), - group("rg_rgmii_mac_grp", rg_rgmii_mac_pins), - group("rg_rgmii_phy_ref_clk_grp0", rg_rgmii_phy_ref_clk_pins0), - group("rg_rgmii_phy_ref_clk_grp1", rg_rgmii_phy_ref_clk_pins1), - group("sd0_grp", sd0_pins), - group("sd0_4bit_grp", sd0_4bit_pins), - group("sd1_grp", sd1_pins), - group("sd1_4bit_grp0", sd1_4bit_pins0), - group("sd1_4bit_grp1", sd1_4bit_pins1), - group("sd2_basic_grp", sd2_basic_pins), - group("sd2_cdb_grp0", sd2_cdb_pins0), - group("sd2_cdb_grp1", sd2_cdb_pins1), - group("sd2_wpb_grp0", sd2_wpb_pins0), - group("sd2_wpb_grp1", sd2_wpb_pins1), - group("sd3_9_grp", sd3_9_pins), - group("sd5_grp", sd5_pins), - group("sd6_grp0", sd6_pins0), - group("sd6_grp1", sd6_pins1), - group("sp0_ext_ldo_on_grp", sp0_ext_ldo_on_pins), - group("sp0_qspi_grp", sp0_qspi_pins), - group("sp1_spi_grp", sp1_spi_pins), - group("tpiu_trace_grp", tpiu_trace_pins), - group("uart0_grp", uart0_pins), - group("uart0_nopause_grp", uart0_nopause_pins), - group("uart1_grp", uart1_pins), - group("uart2_cts_grp0", uart2_cts_pins0), - group("uart2_cts_grp1", uart2_cts_pins1), - group("uart2_rts_grp0", uart2_rts_pins0), - group("uart2_rts_grp1", uart2_rts_pins1), - group("uart2_rxd_grp0", uart2_rxd_pins0), - group("uart2_rxd_grp1", uart2_rxd_pins1), - group("uart2_rxd_grp2", uart2_rxd_pins2), - group("uart2_txd_grp0", uart2_txd_pins0), - group("uart2_txd_grp1", uart2_txd_pins1), - group("uart2_txd_grp2", uart2_txd_pins2), - group("uart3_cts_grp0", uart3_cts_pins0), - group("uart3_cts_grp1", uart3_cts_pins1), - group("uart3_cts_grp2", uart3_cts_pins2), - group("uart3_rts_grp0", uart3_rts_pins0), - group("uart3_rts_grp1", uart3_rts_pins1), - group("uart3_rts_grp2", uart3_rts_pins2), - group("uart3_rxd_grp0", uart3_rxd_pins0), - group("uart3_rxd_grp1", uart3_rxd_pins1), - group("uart3_rxd_grp2", uart3_rxd_pins2), - group("uart3_txd_grp0", uart3_txd_pins0), - group("uart3_txd_grp1", uart3_txd_pins1), - group("uart3_txd_grp2", uart3_txd_pins2), - group("uart4_basic_grp", uart4_basic_pins), - group("uart4_cts_grp0", uart4_cts_pins0), - group("uart4_cts_grp1", uart4_cts_pins1), - group("uart4_cts_grp2", uart4_cts_pins2), - group("uart4_rts_grp0", uart4_rts_pins0), - group("uart4_rts_grp1", uart4_rts_pins1), - group("uart4_rts_grp2", uart4_rts_pins2), - group("usb0_drvvbus_grp0", usb0_drvvbus_pins0), - group("usb0_drvvbus_grp1", usb0_drvvbus_pins1), - group("usb1_drvvbus_grp0", usb1_drvvbus_pins0), - group("usb1_drvvbus_grp1", usb1_drvvbus_pins1), - group("visbus_dout_grp", visbus_dout_pins), - group("vi_vip1_grp", vi_vip1_pins), - group("vi_vip1_ext_grp", vi_vip1_ext_pins), - group("vi_vip1_low8bit_grp", vi_vip1_low8bit_pins), - group("vi_vip1_high8bit_grp", vi_vip1_high8bit_pins), -}; - -/* how many groups that a function can use */ -static const char * const gnss_gpio_grp[] = { "gnss_gpio_grp", }; -static const char * const lcd_vip_gpio_grp[] = { "lcd_vip_gpio_grp", }; -static const char * const sdio_i2s_gpio_grp[] = { "sdio_i2s_gpio_grp", }; -static const char * const sp_rgmii_gpio_grp[] = { "sp_rgmii_gpio_grp", }; -static const char * const lvds_gpio_grp[] = { "lvds_gpio_grp", }; -static const char * const jtag_uart_nand_gpio_grp[] = { - "jtag_uart_nand_gpio_grp", }; -static const char * const rtc_gpio_grp[] = { "rtc_gpio_grp", }; -static const char * const audio_ac97_grp[] = { "audio_ac97_grp", }; -static const char * const audio_digmic_grp0[] = { "audio_digmic_grp0", }; -static const char * const audio_digmic_grp1[] = { "audio_digmic_grp1", }; -static const char * const audio_digmic_grp2[] = { "audio_digmic_grp2", }; -static const char * const audio_func_dbg_grp[] = { "audio_func_dbg_grp", }; -static const char * const audio_i2s_grp[] = { "audio_i2s_grp", }; -static const char * const audio_i2s_2ch_grp[] = { "audio_i2s_2ch_grp", }; -static const char * const audio_i2s_extclk_grp[] = { "audio_i2s_extclk_grp", }; -static const char * const audio_spdif_out_grp0[] = { "audio_spdif_out_grp0", }; -static const char * const audio_spdif_out_grp1[] = { "audio_spdif_out_grp1", }; -static const char * const audio_spdif_out_grp2[] = { "audio_spdif_out_grp2", }; -static const char * const audio_uart0_basic_grp[] = { - "audio_uart0_basic_grp", }; -static const char * const audio_uart0_urfs_grp0[] = { - "audio_uart0_urfs_grp0", }; -static const char * const audio_uart0_urfs_grp1[] = { - "audio_uart0_urfs_grp1", }; -static const char * const audio_uart0_urfs_grp2[] = { - "audio_uart0_urfs_grp2", }; -static const char * const audio_uart0_urfs_grp3[] = { - "audio_uart0_urfs_grp3", }; -static const char * const audio_uart1_basic_grp[] = { - "audio_uart1_basic_grp", }; -static const char * const audio_uart1_urfs_grp0[] = { - "audio_uart1_urfs_grp0", }; -static const char * const audio_uart1_urfs_grp1[] = { - "audio_uart1_urfs_grp1", }; -static const char * const audio_uart1_urfs_grp2[] = { - "audio_uart1_urfs_grp2", }; -static const char * const audio_uart2_urfs_grp0[] = { - "audio_uart2_urfs_grp0", }; -static const char * const audio_uart2_urfs_grp1[] = { - "audio_uart2_urfs_grp1", }; -static const char * const audio_uart2_urfs_grp2[] = { - "audio_uart2_urfs_grp2", }; -static const char * const audio_uart2_urxd_grp0[] = { - "audio_uart2_urxd_grp0", }; -static const char * const audio_uart2_urxd_grp1[] = { - "audio_uart2_urxd_grp1", }; -static const char * const audio_uart2_urxd_grp2[] = { - "audio_uart2_urxd_grp2", }; -static const char * const audio_uart2_usclk_grp0[] = { - "audio_uart2_usclk_grp0", }; -static const char * const audio_uart2_usclk_grp1[] = { - "audio_uart2_usclk_grp1", }; -static const char * const audio_uart2_usclk_grp2[] = { - "audio_uart2_usclk_grp2", }; -static const char * const audio_uart2_utfs_grp0[] = { - "audio_uart2_utfs_grp0", }; -static const char * const audio_uart2_utfs_grp1[] = { - "audio_uart2_utfs_grp1", }; -static const char * const audio_uart2_utfs_grp2[] = { - "audio_uart2_utfs_grp2", }; -static const char * const audio_uart2_utxd_grp0[] = { - "audio_uart2_utxd_grp0", }; -static const char * const audio_uart2_utxd_grp1[] = { - "audio_uart2_utxd_grp1", }; -static const char * const audio_uart2_utxd_grp2[] = { - "audio_uart2_utxd_grp2", }; -static const char * const c_can_trnsvr_en_grp0[] = { "c_can_trnsvr_en_grp0", }; -static const char * const c_can_trnsvr_en_grp1[] = { "c_can_trnsvr_en_grp1", }; -static const char * const c_can_trnsvr_intr_grp[] = { - "c_can_trnsvr_intr_grp", }; -static const char * const c_can_trnsvr_stb_n_grp[] = { - "c_can_trnsvr_stb_n_grp", }; -static const char * const c0_can_rxd_trnsv0_grp[] = { - "c0_can_rxd_trnsv0_grp", }; -static const char * const c0_can_rxd_trnsv1_grp[] = { - "c0_can_rxd_trnsv1_grp", }; -static const char * const c0_can_txd_trnsv0_grp[] = { - "c0_can_txd_trnsv0_grp", }; -static const char * const c0_can_txd_trnsv1_grp[] = { - "c0_can_txd_trnsv1_grp", }; -static const char * const c1_can_rxd_grp0[] = { "c1_can_rxd_grp0", }; -static const char * const c1_can_rxd_grp1[] = { "c1_can_rxd_grp1", }; -static const char * const c1_can_rxd_grp2[] = { "c1_can_rxd_grp2", }; -static const char * const c1_can_rxd_grp3[] = { "c1_can_rxd_grp3", }; -static const char * const c1_can_txd_grp0[] = { "c1_can_txd_grp0", }; -static const char * const c1_can_txd_grp1[] = { "c1_can_txd_grp1", }; -static const char * const c1_can_txd_grp2[] = { "c1_can_txd_grp2", }; -static const char * const c1_can_txd_grp3[] = { "c1_can_txd_grp3", }; -static const char * const ca_audio_lpc_grp[] = { "ca_audio_lpc_grp", }; -static const char * const ca_bt_lpc_grp[] = { "ca_bt_lpc_grp", }; -static const char * const ca_coex_grp[] = { "ca_coex_grp", }; -static const char * const ca_curator_lpc_grp[] = { "ca_curator_lpc_grp", }; -static const char * const ca_pcm_debug_grp[] = { "ca_pcm_debug_grp", }; -static const char * const ca_pio_grp[] = { "ca_pio_grp", }; -static const char * const ca_sdio_debug_grp[] = { "ca_sdio_debug_grp", }; -static const char * const ca_spi_grp[] = { "ca_spi_grp", }; -static const char * const ca_trb_grp[] = { "ca_trb_grp", }; -static const char * const ca_uart_debug_grp[] = { "ca_uart_debug_grp", }; -static const char * const clkc_grp0[] = { "clkc_grp0", }; -static const char * const clkc_grp1[] = { "clkc_grp1", }; -static const char * const gn_gnss_i2c_grp[] = { "gn_gnss_i2c_grp", }; -static const char * const gn_gnss_uart_nopause_grp[] = { - "gn_gnss_uart_nopause_grp", }; -static const char * const gn_gnss_uart_grp[] = { "gn_gnss_uart_grp", }; -static const char * const gn_trg_spi_grp0[] = { "gn_trg_spi_grp0", }; -static const char * const gn_trg_spi_grp1[] = { "gn_trg_spi_grp1", }; -static const char * const cvbs_dbg_grp[] = { "cvbs_dbg_grp", }; -static const char * const cvbs_dbg_test_grp0[] = { "cvbs_dbg_test_grp0", }; -static const char * const cvbs_dbg_test_grp1[] = { "cvbs_dbg_test_grp1", }; -static const char * const cvbs_dbg_test_grp2[] = { "cvbs_dbg_test_grp2", }; -static const char * const cvbs_dbg_test_grp3[] = { "cvbs_dbg_test_grp3", }; -static const char * const cvbs_dbg_test_grp4[] = { "cvbs_dbg_test_grp4", }; -static const char * const cvbs_dbg_test_grp5[] = { "cvbs_dbg_test_grp5", }; -static const char * const cvbs_dbg_test_grp6[] = { "cvbs_dbg_test_grp6", }; -static const char * const cvbs_dbg_test_grp7[] = { "cvbs_dbg_test_grp7", }; -static const char * const cvbs_dbg_test_grp8[] = { "cvbs_dbg_test_grp8", }; -static const char * const cvbs_dbg_test_grp9[] = { "cvbs_dbg_test_grp9", }; -static const char * const cvbs_dbg_test_grp10[] = { "cvbs_dbg_test_grp10", }; -static const char * const cvbs_dbg_test_grp11[] = { "cvbs_dbg_test_grp11", }; -static const char * const cvbs_dbg_test_grp12[] = { "cvbs_dbg_test_grp12", }; -static const char * const cvbs_dbg_test_grp13[] = { "cvbs_dbg_test_grp13", }; -static const char * const cvbs_dbg_test_grp14[] = { "cvbs_dbg_test_grp14", }; -static const char * const cvbs_dbg_test_grp15[] = { "cvbs_dbg_test_grp15", }; -static const char * const gn_gnss_power_grp[] = { "gn_gnss_power_grp", }; -static const char * const gn_gnss_sw_status_grp[] = { - "gn_gnss_sw_status_grp", }; -static const char * const gn_gnss_eclk_grp[] = { "gn_gnss_eclk_grp", }; -static const char * const gn_gnss_irq1_grp0[] = { "gn_gnss_irq1_grp0", }; -static const char * const gn_gnss_irq2_grp0[] = { "gn_gnss_irq2_grp0", }; -static const char * const gn_gnss_tm_grp[] = { "gn_gnss_tm_grp", }; -static const char * const gn_gnss_tsync_grp[] = { "gn_gnss_tsync_grp", }; -static const char * const gn_io_gnsssys_sw_cfg_grp[] = { - "gn_io_gnsssys_sw_cfg_grp", }; -static const char * const gn_trg_grp0[] = { "gn_trg_grp0", }; -static const char * const gn_trg_grp1[] = { "gn_trg_grp1", }; -static const char * const gn_trg_shutdown_grp0[] = { "gn_trg_shutdown_grp0", }; -static const char * const gn_trg_shutdown_grp1[] = { "gn_trg_shutdown_grp1", }; -static const char * const gn_trg_shutdown_grp2[] = { "gn_trg_shutdown_grp2", }; -static const char * const gn_trg_shutdown_grp3[] = { "gn_trg_shutdown_grp3", }; -static const char * const i2c0_grp[] = { "i2c0_grp", }; -static const char * const i2c1_grp[] = { "i2c1_grp", }; -static const char * const i2s0_grp[] = { "i2s0_grp", }; -static const char * const i2s1_basic_grp[] = { "i2s1_basic_grp", }; -static const char * const i2s1_rxd0_grp0[] = { "i2s1_rxd0_grp0", }; -static const char * const i2s1_rxd0_grp1[] = { "i2s1_rxd0_grp1", }; -static const char * const i2s1_rxd0_grp2[] = { "i2s1_rxd0_grp2", }; -static const char * const i2s1_rxd0_grp3[] = { "i2s1_rxd0_grp3", }; -static const char * const i2s1_rxd0_grp4[] = { "i2s1_rxd0_grp4", }; -static const char * const i2s1_rxd1_grp0[] = { "i2s1_rxd1_grp0", }; -static const char * const i2s1_rxd1_grp1[] = { "i2s1_rxd1_grp1", }; -static const char * const i2s1_rxd1_grp2[] = { "i2s1_rxd1_grp2", }; -static const char * const i2s1_rxd1_grp3[] = { "i2s1_rxd1_grp3", }; -static const char * const i2s1_rxd1_grp4[] = { "i2s1_rxd1_grp4", }; -static const char * const jtag_jt_dbg_nsrst_grp[] = { - "jtag_jt_dbg_nsrst_grp", }; -static const char * const jtag_ntrst_grp0[] = { "jtag_ntrst_grp0", }; -static const char * const jtag_ntrst_grp1[] = { "jtag_ntrst_grp1", }; -static const char * const jtag_swdiotms_grp0[] = { "jtag_swdiotms_grp0", }; -static const char * const jtag_swdiotms_grp1[] = { "jtag_swdiotms_grp1", }; -static const char * const jtag_tck_grp0[] = { "jtag_tck_grp0", }; -static const char * const jtag_tck_grp1[] = { "jtag_tck_grp1", }; -static const char * const jtag_tdi_grp0[] = { "jtag_tdi_grp0", }; -static const char * const jtag_tdi_grp1[] = { "jtag_tdi_grp1", }; -static const char * const jtag_tdo_grp0[] = { "jtag_tdo_grp0", }; -static const char * const jtag_tdo_grp1[] = { "jtag_tdo_grp1", }; -static const char * const ks_kas_spi_grp0[] = { "ks_kas_spi_grp0", }; -static const char * const ld_ldd_grp[] = { "ld_ldd_grp", }; -static const char * const ld_ldd_16bit_grp[] = { "ld_ldd_16bit_grp", }; -static const char * const ld_ldd_fck_grp[] = { "ld_ldd_fck_grp", }; -static const char * const ld_ldd_lck_grp[] = { "ld_ldd_lck_grp", }; -static const char * const lr_lcdrom_grp[] = { "lr_lcdrom_grp", }; -static const char * const lvds_analog_grp[] = { "lvds_analog_grp", }; -static const char * const nd_df_basic_grp[] = { "nd_df_basic_grp", }; -static const char * const nd_df_wp_grp[] = { "nd_df_wp_grp", }; -static const char * const nd_df_cs_grp[] = { "nd_df_cs_grp", }; -static const char * const ps_grp[] = { "ps_grp", }; -static const char * const ps_no_dir_grp[] = { "ps_no_dir_grp", }; -static const char * const pwc_core_on_grp[] = { "pwc_core_on_grp", }; -static const char * const pwc_ext_on_grp[] = { "pwc_ext_on_grp", }; -static const char * const pwc_gpio3_clk_grp[] = { "pwc_gpio3_clk_grp", }; -static const char * const pwc_io_on_grp[] = { "pwc_io_on_grp", }; -static const char * const pwc_lowbatt_b_grp0[] = { "pwc_lowbatt_b_grp0", }; -static const char * const pwc_mem_on_grp[] = { "pwc_mem_on_grp", }; -static const char * const pwc_on_key_b_grp0[] = { "pwc_on_key_b_grp0", }; -static const char * const pwc_wakeup_src0_grp[] = { "pwc_wakeup_src0_grp", }; -static const char * const pwc_wakeup_src1_grp[] = { "pwc_wakeup_src1_grp", }; -static const char * const pwc_wakeup_src2_grp[] = { "pwc_wakeup_src2_grp", }; -static const char * const pwc_wakeup_src3_grp[] = { "pwc_wakeup_src3_grp", }; -static const char * const pw_cko0_grp0[] = { "pw_cko0_grp0", }; -static const char * const pw_cko0_grp1[] = { "pw_cko0_grp1", }; -static const char * const pw_cko0_grp2[] = { "pw_cko0_grp2", }; -static const char * const pw_cko0_grp3[] = { "pw_cko0_grp3", }; -static const char * const pw_cko1_grp0[] = { "pw_cko1_grp0", }; -static const char * const pw_cko1_grp1[] = { "pw_cko1_grp1", }; -static const char * const pw_cko1_grp2[] = { "pw_cko1_grp2", }; -static const char * const pw_i2s01_clk_grp0[] = { "pw_i2s01_clk_grp0", }; -static const char * const pw_i2s01_clk_grp1[] = { "pw_i2s01_clk_grp1", }; -static const char * const pw_i2s01_clk_grp2[] = { "pw_i2s01_clk_grp2", }; -static const char * const pw_pwm0_grp0[] = { "pw_pwm0_grp0", }; -static const char * const pw_pwm0_grp1[] = { "pw_pwm0_grp1", }; -static const char * const pw_pwm1_grp0[] = { "pw_pwm1_grp0", }; -static const char * const pw_pwm1_grp1[] = { "pw_pwm1_grp1", }; -static const char * const pw_pwm1_grp2[] = { "pw_pwm1_grp2", }; -static const char * const pw_pwm2_grp0[] = { "pw_pwm2_grp0", }; -static const char * const pw_pwm2_grp1[] = { "pw_pwm2_grp1", }; -static const char * const pw_pwm2_grp2[] = { "pw_pwm2_grp2", }; -static const char * const pw_pwm3_grp0[] = { "pw_pwm3_grp0", }; -static const char * const pw_pwm3_grp1[] = { "pw_pwm3_grp1", }; -static const char * const pw_pwm_cpu_vol_grp0[] = { "pw_pwm_cpu_vol_grp0", }; -static const char * const pw_pwm_cpu_vol_grp1[] = { "pw_pwm_cpu_vol_grp1", }; -static const char * const pw_pwm_cpu_vol_grp2[] = { "pw_pwm_cpu_vol_grp2", }; -static const char * const pw_backlight_grp0[] = { "pw_backlight_grp0", }; -static const char * const pw_backlight_grp1[] = { "pw_backlight_grp1", }; -static const char * const rg_eth_mac_grp[] = { "rg_eth_mac_grp", }; -static const char * const rg_gmac_phy_intr_n_grp[] = { - "rg_gmac_phy_intr_n_grp", }; -static const char * const rg_rgmii_mac_grp[] = { "rg_rgmii_mac_grp", }; -static const char * const rg_rgmii_phy_ref_clk_grp0[] = { - "rg_rgmii_phy_ref_clk_grp0", }; -static const char * const rg_rgmii_phy_ref_clk_grp1[] = { - "rg_rgmii_phy_ref_clk_grp1", }; -static const char * const sd0_grp[] = { "sd0_grp", }; -static const char * const sd0_4bit_grp[] = { "sd0_4bit_grp", }; -static const char * const sd1_grp[] = { "sd1_grp", }; -static const char * const sd1_4bit_grp0[] = { "sd1_4bit_grp0", }; -static const char * const sd1_4bit_grp1[] = { "sd1_4bit_grp1", }; -static const char * const sd2_basic_grp[] = { "sd2_basic_grp", }; -static const char * const sd2_cdb_grp0[] = { "sd2_cdb_grp0", }; -static const char * const sd2_cdb_grp1[] = { "sd2_cdb_grp1", }; -static const char * const sd2_wpb_grp0[] = { "sd2_wpb_grp0", }; -static const char * const sd2_wpb_grp1[] = { "sd2_wpb_grp1", }; -static const char * const sd3_9_grp[] = { "sd3_9_grp", }; -static const char * const sd5_grp[] = { "sd5_grp", }; -static const char * const sd6_grp0[] = { "sd6_grp0", }; -static const char * const sd6_grp1[] = { "sd6_grp1", }; -static const char * const sp0_ext_ldo_on_grp[] = { "sp0_ext_ldo_on_grp", }; -static const char * const sp0_qspi_grp[] = { "sp0_qspi_grp", }; -static const char * const sp1_spi_grp[] = { "sp1_spi_grp", }; -static const char * const tpiu_trace_grp[] = { "tpiu_trace_grp", }; -static const char * const uart0_grp[] = { "uart0_grp", }; -static const char * const uart0_nopause_grp[] = { "uart0_nopause_grp", }; -static const char * const uart1_grp[] = { "uart1_grp", }; -static const char * const uart2_cts_grp0[] = { "uart2_cts_grp0", }; -static const char * const uart2_cts_grp1[] = { "uart2_cts_grp1", }; -static const char * const uart2_rts_grp0[] = { "uart2_rts_grp0", }; -static const char * const uart2_rts_grp1[] = { "uart2_rts_grp1", }; -static const char * const uart2_rxd_grp0[] = { "uart2_rxd_grp0", }; -static const char * const uart2_rxd_grp1[] = { "uart2_rxd_grp1", }; -static const char * const uart2_rxd_grp2[] = { "uart2_rxd_grp2", }; -static const char * const uart2_txd_grp0[] = { "uart2_txd_grp0", }; -static const char * const uart2_txd_grp1[] = { "uart2_txd_grp1", }; -static const char * const uart2_txd_grp2[] = { "uart2_txd_grp2", }; -static const char * const uart3_cts_grp0[] = { "uart3_cts_grp0", }; -static const char * const uart3_cts_grp1[] = { "uart3_cts_grp1", }; -static const char * const uart3_cts_grp2[] = { "uart3_cts_grp2", }; -static const char * const uart3_rts_grp0[] = { "uart3_rts_grp0", }; -static const char * const uart3_rts_grp1[] = { "uart3_rts_grp1", }; -static const char * const uart3_rts_grp2[] = { "uart3_rts_grp2", }; -static const char * const uart3_rxd_grp0[] = { "uart3_rxd_grp0", }; -static const char * const uart3_rxd_grp1[] = { "uart3_rxd_grp1", }; -static const char * const uart3_rxd_grp2[] = { "uart3_rxd_grp2", }; -static const char * const uart3_txd_grp0[] = { "uart3_txd_grp0", }; -static const char * const uart3_txd_grp1[] = { "uart3_txd_grp1", }; -static const char * const uart3_txd_grp2[] = { "uart3_txd_grp2", }; -static const char * const uart4_basic_grp[] = { "uart4_basic_grp", }; -static const char * const uart4_cts_grp0[] = { "uart4_cts_grp0", }; -static const char * const uart4_cts_grp1[] = { "uart4_cts_grp1", }; -static const char * const uart4_cts_grp2[] = { "uart4_cts_grp2", }; -static const char * const uart4_rts_grp0[] = { "uart4_rts_grp0", }; -static const char * const uart4_rts_grp1[] = { "uart4_rts_grp1", }; -static const char * const uart4_rts_grp2[] = { "uart4_rts_grp2", }; -static const char * const usb0_drvvbus_grp0[] = { "usb0_drvvbus_grp0", }; -static const char * const usb0_drvvbus_grp1[] = { "usb0_drvvbus_grp1", }; -static const char * const usb1_drvvbus_grp0[] = { "usb1_drvvbus_grp0", }; -static const char * const usb1_drvvbus_grp1[] = { "usb1_drvvbus_grp1", }; -static const char * const visbus_dout_grp[] = { "visbus_dout_grp", }; -static const char * const vi_vip1_grp[] = { "vi_vip1_grp", }; -static const char * const vi_vip1_ext_grp[] = { "vi_vip1_ext_grp", }; -static const char * const vi_vip1_low8bit_grp[] = { "vi_vip1_low8bit_grp", }; -static const char * const vi_vip1_high8bit_grp[] = { "vi_vip1_high8bit_grp", }; - -static struct atlas7_pad_mux gnss_gpio_grp_pad_mux[] = { - mux(1, 119, 0, n, n, n, n), - mux(1, 120, 0, n, n, n, n), - mux(1, 121, 0, n, n, n, n), - mux(1, 122, 0, n, n, n, n), - mux(1, 123, 0, n, n, n, n), - mux(1, 124, 0, n, n, n, n), - mux(1, 125, 0, n, n, n, n), - mux(1, 126, 0, n, n, n, n), - mux(1, 127, 0, n, n, n, n), - mux(1, 128, 0, n, n, n, n), - mux(1, 22, 0, n, n, n, n), - mux(1, 23, 0, n, n, n, n), - mux(1, 24, 0, n, n, n, n), - mux(1, 25, 0, n, n, n, n), - mux(1, 26, 0, n, n, n, n), - mux(1, 27, 0, n, n, n, n), - mux(1, 28, 0, n, n, n, n), - mux(1, 29, 0, n, n, n, n), - mux(1, 30, 0, n, n, n, n), -}; - -static struct atlas7_grp_mux gnss_gpio_grp_mux = { - .pad_mux_count = array_size(gnss_gpio_grp_pad_mux), - .pad_mux_list = gnss_gpio_grp_pad_mux, -}; - -static struct atlas7_pad_mux lcd_vip_gpio_grp_pad_mux[] = { - mux(1, 74, 0, n, n, n, n), - mux(1, 75, 0, n, n, n, n), - mux(1, 76, 0, n, n, n, n), - mux(1, 77, 0, n, n, n, n), - mux(1, 78, 0, n, n, n, n), - mux(1, 79, 0, n, n, n, n), - mux(1, 80, 0, n, n, n, n), - mux(1, 81, 0, n, n, n, n), - mux(1, 82, 0, n, n, n, n), - mux(1, 83, 0, n, n, n, n), - mux(1, 84, 0, n, n, n, n), - mux(1, 53, 0, n, n, n, n), - mux(1, 54, 0, n, n, n, n), - mux(1, 55, 0, n, n, n, n), - mux(1, 56, 0, n, n, n, n), - mux(1, 57, 0, n, n, n, n), - mux(1, 58, 0, n, n, n, n), - mux(1, 59, 0, n, n, n, n), - mux(1, 60, 0, n, n, n, n), - mux(1, 61, 0, n, n, n, n), - mux(1, 62, 0, n, n, n, n), - mux(1, 63, 0, n, n, n, n), - mux(1, 64, 0, n, n, n, n), - mux(1, 65, 0, n, n, n, n), - mux(1, 66, 0, n, n, n, n), - mux(1, 67, 0, n, n, n, n), - mux(1, 68, 0, n, n, n, n), - mux(1, 69, 0, n, n, n, n), - mux(1, 70, 0, n, n, n, n), - mux(1, 71, 0, n, n, n, n), - mux(1, 72, 0, n, n, n, n), - mux(1, 73, 0, n, n, n, n), -}; - -static struct atlas7_grp_mux lcd_vip_gpio_grp_mux = { - .pad_mux_count = array_size(lcd_vip_gpio_grp_pad_mux), - .pad_mux_list = lcd_vip_gpio_grp_pad_mux, -}; - -static struct atlas7_pad_mux sdio_i2s_gpio_grp_pad_mux[] = { - mux(1, 31, 0, n, n, n, n), - mux(1, 32, 0, n, n, n, n), - mux(1, 33, 0, n, n, n, n), - mux(1, 34, 0, n, n, n, n), - mux(1, 35, 0, n, n, n, n), - mux(1, 36, 0, n, n, n, n), - mux(1, 85, 0, n, n, n, n), - mux(1, 86, 0, n, n, n, n), - mux(1, 87, 0, n, n, n, n), - mux(1, 88, 0, n, n, n, n), - mux(1, 89, 0, n, n, n, n), - mux(1, 90, 0, n, n, n, n), - mux(1, 129, 0, n, n, n, n), - mux(1, 130, 0, n, n, n, n), - mux(1, 131, 0, n, n, n, n), - mux(1, 132, 0, n, n, n, n), - mux(1, 91, 0, n, n, n, n), - mux(1, 92, 0, n, n, n, n), - mux(1, 93, 0, n, n, n, n), - mux(1, 94, 0, n, n, n, n), - mux(1, 95, 0, n, n, n, n), - mux(1, 96, 0, n, n, n, n), - mux(1, 112, 0, n, n, n, n), - mux(1, 113, 0, n, n, n, n), - mux(1, 114, 0, n, n, n, n), - mux(1, 115, 0, n, n, n, n), - mux(1, 116, 0, n, n, n, n), - mux(1, 117, 0, n, n, n, n), - mux(1, 118, 0, n, n, n, n), -}; - -static struct atlas7_grp_mux sdio_i2s_gpio_grp_mux = { - .pad_mux_count = array_size(sdio_i2s_gpio_grp_pad_mux), - .pad_mux_list = sdio_i2s_gpio_grp_pad_mux, -}; - -static struct atlas7_pad_mux sp_rgmii_gpio_grp_pad_mux[] = { - mux(1, 97, 0, n, n, n, n), - mux(1, 98, 0, n, n, n, n), - mux(1, 99, 0, n, n, n, n), - mux(1, 100, 0, n, n, n, n), - mux(1, 101, 0, n, n, n, n), - mux(1, 102, 0, n, n, n, n), - mux(1, 103, 0, n, n, n, n), - mux(1, 104, 0, n, n, n, n), - mux(1, 105, 0, n, n, n, n), - mux(1, 106, 0, n, n, n, n), - mux(1, 107, 0, n, n, n, n), - mux(1, 108, 0, n, n, n, n), - mux(1, 109, 0, n, n, n, n), - mux(1, 110, 0, n, n, n, n), - mux(1, 111, 0, n, n, n, n), - mux(1, 18, 0, n, n, n, n), - mux(1, 19, 0, n, n, n, n), - mux(1, 20, 0, n, n, n, n), - mux(1, 21, 0, n, n, n, n), - mux(1, 141, 0, n, n, n, n), - mux(1, 142, 0, n, n, n, n), - mux(1, 143, 0, n, n, n, n), - mux(1, 144, 0, n, n, n, n), - mux(1, 145, 0, n, n, n, n), - mux(1, 146, 0, n, n, n, n), - mux(1, 147, 0, n, n, n, n), - mux(1, 148, 0, n, n, n, n), -}; - -static struct atlas7_grp_mux sp_rgmii_gpio_grp_mux = { - .pad_mux_count = array_size(sp_rgmii_gpio_grp_pad_mux), - .pad_mux_list = sp_rgmii_gpio_grp_pad_mux, -}; - -static struct atlas7_pad_mux lvds_gpio_grp_pad_mux[] = { - mux(1, 157, 0, n, n, n, n), - mux(1, 158, 0, n, n, n, n), - mux(1, 155, 0, n, n, n, n), - mux(1, 156, 0, n, n, n, n), - mux(1, 153, 0, n, n, n, n), - mux(1, 154, 0, n, n, n, n), - mux(1, 151, 0, n, n, n, n), - mux(1, 152, 0, n, n, n, n), - mux(1, 149, 0, n, n, n, n), - mux(1, 150, 0, n, n, n, n), -}; - -static struct atlas7_grp_mux lvds_gpio_grp_mux = { - .pad_mux_count = array_size(lvds_gpio_grp_pad_mux), - .pad_mux_list = lvds_gpio_grp_pad_mux, -}; - -static struct atlas7_pad_mux jtag_uart_nand_gpio_grp_pad_mux[] = { - mux(1, 44, 0, n, n, n, n), - mux(1, 43, 0, n, n, n, n), - mux(1, 42, 0, n, n, n, n), - mux(1, 41, 0, n, n, n, n), - mux(1, 40, 0, n, n, n, n), - mux(1, 39, 0, n, n, n, n), - mux(1, 38, 0, n, n, n, n), - mux(1, 37, 0, n, n, n, n), - mux(1, 46, 0, n, n, n, n), - mux(1, 47, 0, n, n, n, n), - mux(1, 48, 0, n, n, n, n), - mux(1, 49, 0, n, n, n, n), - mux(1, 50, 0, n, n, n, n), - mux(1, 52, 0, n, n, n, n), - mux(1, 51, 0, n, n, n, n), - mux(1, 45, 0, n, n, n, n), - mux(1, 133, 0, n, n, n, n), - mux(1, 134, 0, n, n, n, n), - mux(1, 135, 0, n, n, n, n), - mux(1, 136, 0, n, n, n, n), - mux(1, 137, 0, n, n, n, n), - mux(1, 138, 0, n, n, n, n), - mux(1, 139, 0, n, n, n, n), - mux(1, 140, 0, n, n, n, n), - mux(1, 159, 0, n, n, n, n), - mux(1, 160, 0, n, n, n, n), - mux(1, 161, 0, n, n, n, n), - mux(1, 162, 0, n, n, n, n), - mux(1, 163, 0, n, n, n, n), -}; - -static struct atlas7_grp_mux jtag_uart_nand_gpio_grp_mux = { - .pad_mux_count = array_size(jtag_uart_nand_gpio_grp_pad_mux), - .pad_mux_list = jtag_uart_nand_gpio_grp_pad_mux, -}; - -static struct atlas7_pad_mux rtc_gpio_grp_pad_mux[] = { - mux(0, 0, 0, n, n, n, n), - mux(0, 1, 0, n, n, n, n), - mux(0, 2, 0, n, n, n, n), - mux(0, 3, 0, n, n, n, n), - mux(0, 4, 0, n, n, n, n), - mux(0, 10, 0, n, n, n, n), - mux(0, 11, 0, n, n, n, n), - mux(0, 12, 0, n, n, n, n), - mux(0, 13, 0, n, n, n, n), - mux(0, 14, 0, n, n, n, n), - mux(0, 15, 0, n, n, n, n), - mux(0, 16, 0, n, n, n, n), - mux(0, 17, 0, n, n, n, n), - mux(0, 9, 0, n, n, n, n), -}; - -static struct atlas7_grp_mux rtc_gpio_grp_mux = { - .pad_mux_count = array_size(rtc_gpio_grp_pad_mux), - .pad_mux_list = rtc_gpio_grp_pad_mux, -}; - -static struct atlas7_pad_mux audio_ac97_grp_pad_mux[] = { - mux(1, 113, 2, n, n, n, n), - mux(1, 118, 2, n, n, n, n), - mux(1, 115, 2, n, n, n, n), - mux(1, 114, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux audio_ac97_grp_mux = { - .pad_mux_count = array_size(audio_ac97_grp_pad_mux), - .pad_mux_list = audio_ac97_grp_pad_mux, -}; - -static struct atlas7_pad_mux audio_digmic_grp0_pad_mux[] = { - mux(1, 51, 3, 0xa10, 20, 0xa90, 20), -}; - -static struct atlas7_grp_mux audio_digmic_grp0_mux = { - .pad_mux_count = array_size(audio_digmic_grp0_pad_mux), - .pad_mux_list = audio_digmic_grp0_pad_mux, -}; - -static struct atlas7_pad_mux audio_digmic_grp1_pad_mux[] = { - mux(1, 122, 5, 0xa10, 20, 0xa90, 20), -}; - -static struct atlas7_grp_mux audio_digmic_grp1_mux = { - .pad_mux_count = array_size(audio_digmic_grp1_pad_mux), - .pad_mux_list = audio_digmic_grp1_pad_mux, -}; - -static struct atlas7_pad_mux audio_digmic_grp2_pad_mux[] = { - mux(1, 161, 7, 0xa10, 20, 0xa90, 20), -}; - -static struct atlas7_grp_mux audio_digmic_grp2_mux = { - .pad_mux_count = array_size(audio_digmic_grp2_pad_mux), - .pad_mux_list = audio_digmic_grp2_pad_mux, -}; - -static struct atlas7_pad_mux audio_func_dbg_grp_pad_mux[] = { - mux(1, 141, 4, n, n, n, n), - mux(1, 144, 4, n, n, n, n), - mux(1, 44, 6, n, n, n, n), - mux(1, 43, 6, n, n, n, n), - mux(1, 42, 6, n, n, n, n), - mux(1, 41, 6, n, n, n, n), - mux(1, 40, 6, n, n, n, n), - mux(1, 39, 6, n, n, n, n), - mux(1, 38, 6, n, n, n, n), - mux(1, 37, 6, n, n, n, n), - mux(1, 74, 6, n, n, n, n), - mux(1, 75, 6, n, n, n, n), - mux(1, 76, 6, n, n, n, n), - mux(1, 77, 6, n, n, n, n), - mux(1, 78, 6, n, n, n, n), - mux(1, 79, 6, n, n, n, n), - mux(1, 81, 6, n, n, n, n), - mux(1, 113, 6, n, n, n, n), - mux(1, 114, 6, n, n, n, n), - mux(1, 118, 6, n, n, n, n), - mux(1, 115, 6, n, n, n, n), - mux(1, 49, 6, n, n, n, n), - mux(1, 50, 6, n, n, n, n), - mux(1, 142, 4, n, n, n, n), - mux(1, 143, 4, n, n, n, n), - mux(1, 80, 6, n, n, n, n), -}; - -static struct atlas7_grp_mux audio_func_dbg_grp_mux = { - .pad_mux_count = array_size(audio_func_dbg_grp_pad_mux), - .pad_mux_list = audio_func_dbg_grp_pad_mux, -}; - -static struct atlas7_pad_mux audio_i2s_grp_pad_mux[] = { - mux(1, 118, 1, n, n, n, n), - mux(1, 115, 1, n, n, n, n), - mux(1, 116, 1, n, n, n, n), - mux(1, 117, 1, n, n, n, n), - mux(1, 112, 1, n, n, n, n), - mux(1, 113, 1, n, n, n, n), - mux(1, 114, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux audio_i2s_grp_mux = { - .pad_mux_count = array_size(audio_i2s_grp_pad_mux), - .pad_mux_list = audio_i2s_grp_pad_mux, -}; - -static struct atlas7_pad_mux audio_i2s_2ch_grp_pad_mux[] = { - mux(1, 118, 1, n, n, n, n), - mux(1, 115, 1, n, n, n, n), - mux(1, 112, 1, n, n, n, n), - mux(1, 113, 1, n, n, n, n), - mux(1, 114, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux audio_i2s_2ch_grp_mux = { - .pad_mux_count = array_size(audio_i2s_2ch_grp_pad_mux), - .pad_mux_list = audio_i2s_2ch_grp_pad_mux, -}; - -static struct atlas7_pad_mux audio_i2s_extclk_grp_pad_mux[] = { - mux(1, 112, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux audio_i2s_extclk_grp_mux = { - .pad_mux_count = array_size(audio_i2s_extclk_grp_pad_mux), - .pad_mux_list = audio_i2s_extclk_grp_pad_mux, -}; - -static struct atlas7_pad_mux audio_spdif_out_grp0_pad_mux[] = { - mux(1, 112, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux audio_spdif_out_grp0_mux = { - .pad_mux_count = array_size(audio_spdif_out_grp0_pad_mux), - .pad_mux_list = audio_spdif_out_grp0_pad_mux, -}; - -static struct atlas7_pad_mux audio_spdif_out_grp1_pad_mux[] = { - mux(1, 116, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux audio_spdif_out_grp1_mux = { - .pad_mux_count = array_size(audio_spdif_out_grp1_pad_mux), - .pad_mux_list = audio_spdif_out_grp1_pad_mux, -}; - -static struct atlas7_pad_mux audio_spdif_out_grp2_pad_mux[] = { - mux(1, 142, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux audio_spdif_out_grp2_mux = { - .pad_mux_count = array_size(audio_spdif_out_grp2_pad_mux), - .pad_mux_list = audio_spdif_out_grp2_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart0_basic_grp_pad_mux[] = { - mux(1, 143, 1, n, n, n, n), - mux(1, 142, 1, n, n, n, n), - mux(1, 141, 1, n, n, n, n), - mux(1, 144, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux audio_uart0_basic_grp_mux = { - .pad_mux_count = array_size(audio_uart0_basic_grp_pad_mux), - .pad_mux_list = audio_uart0_basic_grp_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart0_urfs_grp0_pad_mux[] = { - mux(1, 117, 5, 0xa10, 28, 0xa90, 28), -}; - -static struct atlas7_grp_mux audio_uart0_urfs_grp0_mux = { - .pad_mux_count = array_size(audio_uart0_urfs_grp0_pad_mux), - .pad_mux_list = audio_uart0_urfs_grp0_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart0_urfs_grp1_pad_mux[] = { - mux(1, 139, 3, 0xa10, 28, 0xa90, 28), -}; - -static struct atlas7_grp_mux audio_uart0_urfs_grp1_mux = { - .pad_mux_count = array_size(audio_uart0_urfs_grp1_pad_mux), - .pad_mux_list = audio_uart0_urfs_grp1_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart0_urfs_grp2_pad_mux[] = { - mux(1, 163, 3, 0xa10, 28, 0xa90, 28), -}; - -static struct atlas7_grp_mux audio_uart0_urfs_grp2_mux = { - .pad_mux_count = array_size(audio_uart0_urfs_grp2_pad_mux), - .pad_mux_list = audio_uart0_urfs_grp2_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart0_urfs_grp3_pad_mux[] = { - mux(1, 162, 6, 0xa10, 28, 0xa90, 28), -}; - -static struct atlas7_grp_mux audio_uart0_urfs_grp3_mux = { - .pad_mux_count = array_size(audio_uart0_urfs_grp3_pad_mux), - .pad_mux_list = audio_uart0_urfs_grp3_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart1_basic_grp_pad_mux[] = { - mux(1, 147, 1, 0xa10, 24, 0xa90, 24), - mux(1, 146, 1, 0xa10, 25, 0xa90, 25), - mux(1, 145, 1, 0xa10, 23, 0xa90, 23), - mux(1, 148, 1, 0xa10, 22, 0xa90, 22), -}; - -static struct atlas7_grp_mux audio_uart1_basic_grp_mux = { - .pad_mux_count = array_size(audio_uart1_basic_grp_pad_mux), - .pad_mux_list = audio_uart1_basic_grp_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart1_urfs_grp0_pad_mux[] = { - mux(1, 117, 6, 0xa10, 29, 0xa90, 29), -}; - -static struct atlas7_grp_mux audio_uart1_urfs_grp0_mux = { - .pad_mux_count = array_size(audio_uart1_urfs_grp0_pad_mux), - .pad_mux_list = audio_uart1_urfs_grp0_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart1_urfs_grp1_pad_mux[] = { - mux(1, 140, 3, 0xa10, 29, 0xa90, 29), -}; - -static struct atlas7_grp_mux audio_uart1_urfs_grp1_mux = { - .pad_mux_count = array_size(audio_uart1_urfs_grp1_pad_mux), - .pad_mux_list = audio_uart1_urfs_grp1_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart1_urfs_grp2_pad_mux[] = { - mux(1, 163, 4, 0xa10, 29, 0xa90, 29), -}; - -static struct atlas7_grp_mux audio_uart1_urfs_grp2_mux = { - .pad_mux_count = array_size(audio_uart1_urfs_grp2_pad_mux), - .pad_mux_list = audio_uart1_urfs_grp2_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart2_urfs_grp0_pad_mux[] = { - mux(1, 139, 4, 0xa10, 30, 0xa90, 30), -}; - -static struct atlas7_grp_mux audio_uart2_urfs_grp0_mux = { - .pad_mux_count = array_size(audio_uart2_urfs_grp0_pad_mux), - .pad_mux_list = audio_uart2_urfs_grp0_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart2_urfs_grp1_pad_mux[] = { - mux(1, 163, 6, 0xa10, 30, 0xa90, 30), -}; - -static struct atlas7_grp_mux audio_uart2_urfs_grp1_mux = { - .pad_mux_count = array_size(audio_uart2_urfs_grp1_pad_mux), - .pad_mux_list = audio_uart2_urfs_grp1_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart2_urfs_grp2_pad_mux[] = { - mux(1, 96, 3, 0xa10, 30, 0xa90, 30), -}; - -static struct atlas7_grp_mux audio_uart2_urfs_grp2_mux = { - .pad_mux_count = array_size(audio_uart2_urfs_grp2_pad_mux), - .pad_mux_list = audio_uart2_urfs_grp2_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart2_urxd_grp0_pad_mux[] = { - mux(1, 20, 2, 0xa00, 24, 0xa80, 24), -}; - -static struct atlas7_grp_mux audio_uart2_urxd_grp0_mux = { - .pad_mux_count = array_size(audio_uart2_urxd_grp0_pad_mux), - .pad_mux_list = audio_uart2_urxd_grp0_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart2_urxd_grp1_pad_mux[] = { - mux(1, 109, 2, 0xa00, 24, 0xa80, 24), -}; - -static struct atlas7_grp_mux audio_uart2_urxd_grp1_mux = { - .pad_mux_count = array_size(audio_uart2_urxd_grp1_pad_mux), - .pad_mux_list = audio_uart2_urxd_grp1_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart2_urxd_grp2_pad_mux[] = { - mux(1, 93, 3, 0xa00, 24, 0xa80, 24), -}; - -static struct atlas7_grp_mux audio_uart2_urxd_grp2_mux = { - .pad_mux_count = array_size(audio_uart2_urxd_grp2_pad_mux), - .pad_mux_list = audio_uart2_urxd_grp2_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart2_usclk_grp0_pad_mux[] = { - mux(1, 19, 2, 0xa00, 23, 0xa80, 23), -}; - -static struct atlas7_grp_mux audio_uart2_usclk_grp0_mux = { - .pad_mux_count = array_size(audio_uart2_usclk_grp0_pad_mux), - .pad_mux_list = audio_uart2_usclk_grp0_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart2_usclk_grp1_pad_mux[] = { - mux(1, 101, 2, 0xa00, 23, 0xa80, 23), -}; - -static struct atlas7_grp_mux audio_uart2_usclk_grp1_mux = { - .pad_mux_count = array_size(audio_uart2_usclk_grp1_pad_mux), - .pad_mux_list = audio_uart2_usclk_grp1_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart2_usclk_grp2_pad_mux[] = { - mux(1, 91, 3, 0xa00, 23, 0xa80, 23), -}; - -static struct atlas7_grp_mux audio_uart2_usclk_grp2_mux = { - .pad_mux_count = array_size(audio_uart2_usclk_grp2_pad_mux), - .pad_mux_list = audio_uart2_usclk_grp2_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart2_utfs_grp0_pad_mux[] = { - mux(1, 18, 2, 0xa00, 22, 0xa80, 22), -}; - -static struct atlas7_grp_mux audio_uart2_utfs_grp0_mux = { - .pad_mux_count = array_size(audio_uart2_utfs_grp0_pad_mux), - .pad_mux_list = audio_uart2_utfs_grp0_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart2_utfs_grp1_pad_mux[] = { - mux(1, 111, 2, 0xa00, 22, 0xa80, 22), -}; - -static struct atlas7_grp_mux audio_uart2_utfs_grp1_mux = { - .pad_mux_count = array_size(audio_uart2_utfs_grp1_pad_mux), - .pad_mux_list = audio_uart2_utfs_grp1_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart2_utfs_grp2_pad_mux[] = { - mux(1, 94, 3, 0xa00, 22, 0xa80, 22), -}; - -static struct atlas7_grp_mux audio_uart2_utfs_grp2_mux = { - .pad_mux_count = array_size(audio_uart2_utfs_grp2_pad_mux), - .pad_mux_list = audio_uart2_utfs_grp2_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart2_utxd_grp0_pad_mux[] = { - mux(1, 21, 2, 0xa00, 25, 0xa80, 25), -}; - -static struct atlas7_grp_mux audio_uart2_utxd_grp0_mux = { - .pad_mux_count = array_size(audio_uart2_utxd_grp0_pad_mux), - .pad_mux_list = audio_uart2_utxd_grp0_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart2_utxd_grp1_pad_mux[] = { - mux(1, 110, 2, 0xa00, 25, 0xa80, 25), -}; - -static struct atlas7_grp_mux audio_uart2_utxd_grp1_mux = { - .pad_mux_count = array_size(audio_uart2_utxd_grp1_pad_mux), - .pad_mux_list = audio_uart2_utxd_grp1_pad_mux, -}; - -static struct atlas7_pad_mux audio_uart2_utxd_grp2_pad_mux[] = { - mux(1, 92, 3, 0xa00, 25, 0xa80, 25), -}; - -static struct atlas7_grp_mux audio_uart2_utxd_grp2_mux = { - .pad_mux_count = array_size(audio_uart2_utxd_grp2_pad_mux), - .pad_mux_list = audio_uart2_utxd_grp2_pad_mux, -}; - -static struct atlas7_pad_mux c_can_trnsvr_en_grp0_pad_mux[] = { - mux(0, 2, 6, n, n, n, n), -}; - -static struct atlas7_grp_mux c_can_trnsvr_en_grp0_mux = { - .pad_mux_count = array_size(c_can_trnsvr_en_grp0_pad_mux), - .pad_mux_list = c_can_trnsvr_en_grp0_pad_mux, -}; - -static struct atlas7_pad_mux c_can_trnsvr_en_grp1_pad_mux[] = { - mux(0, 0, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux c_can_trnsvr_en_grp1_mux = { - .pad_mux_count = array_size(c_can_trnsvr_en_grp1_pad_mux), - .pad_mux_list = c_can_trnsvr_en_grp1_pad_mux, -}; - -static struct atlas7_pad_mux c_can_trnsvr_intr_grp_pad_mux[] = { - mux(0, 1, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux c_can_trnsvr_intr_grp_mux = { - .pad_mux_count = array_size(c_can_trnsvr_intr_grp_pad_mux), - .pad_mux_list = c_can_trnsvr_intr_grp_pad_mux, -}; - -static struct atlas7_pad_mux c_can_trnsvr_stb_n_grp_pad_mux[] = { - mux(0, 3, 6, n, n, n, n), -}; - -static struct atlas7_grp_mux c_can_trnsvr_stb_n_grp_mux = { - .pad_mux_count = array_size(c_can_trnsvr_stb_n_grp_pad_mux), - .pad_mux_list = c_can_trnsvr_stb_n_grp_pad_mux, -}; - -static struct atlas7_pad_mux c0_can_rxd_trnsv0_grp_pad_mux[] = { - mux(0, 11, 1, 0xa08, 9, 0xa88, 9), -}; - -static struct atlas7_grp_mux c0_can_rxd_trnsv0_grp_mux = { - .pad_mux_count = array_size(c0_can_rxd_trnsv0_grp_pad_mux), - .pad_mux_list = c0_can_rxd_trnsv0_grp_pad_mux, -}; - -static struct atlas7_pad_mux c0_can_rxd_trnsv1_grp_pad_mux[] = { - mux(0, 2, 5, 0xa10, 9, 0xa90, 9), -}; - -static struct atlas7_grp_mux c0_can_rxd_trnsv1_grp_mux = { - .pad_mux_count = array_size(c0_can_rxd_trnsv1_grp_pad_mux), - .pad_mux_list = c0_can_rxd_trnsv1_grp_pad_mux, -}; - -static struct atlas7_pad_mux c0_can_txd_trnsv0_grp_pad_mux[] = { - mux(0, 10, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux c0_can_txd_trnsv0_grp_mux = { - .pad_mux_count = array_size(c0_can_txd_trnsv0_grp_pad_mux), - .pad_mux_list = c0_can_txd_trnsv0_grp_pad_mux, -}; - -static struct atlas7_pad_mux c0_can_txd_trnsv1_grp_pad_mux[] = { - mux(0, 3, 5, n, n, n, n), -}; - -static struct atlas7_grp_mux c0_can_txd_trnsv1_grp_mux = { - .pad_mux_count = array_size(c0_can_txd_trnsv1_grp_pad_mux), - .pad_mux_list = c0_can_txd_trnsv1_grp_pad_mux, -}; - -static struct atlas7_pad_mux c1_can_rxd_grp0_pad_mux[] = { - mux(1, 138, 2, 0xa00, 4, 0xa80, 4), -}; - -static struct atlas7_grp_mux c1_can_rxd_grp0_mux = { - .pad_mux_count = array_size(c1_can_rxd_grp0_pad_mux), - .pad_mux_list = c1_can_rxd_grp0_pad_mux, -}; - -static struct atlas7_pad_mux c1_can_rxd_grp1_pad_mux[] = { - mux(1, 147, 2, 0xa00, 4, 0xa80, 4), -}; - -static struct atlas7_grp_mux c1_can_rxd_grp1_mux = { - .pad_mux_count = array_size(c1_can_rxd_grp1_pad_mux), - .pad_mux_list = c1_can_rxd_grp1_pad_mux, -}; - -static struct atlas7_pad_mux c1_can_rxd_grp2_pad_mux[] = { - mux(0, 2, 2, 0xa00, 4, 0xa80, 4), -}; - -static struct atlas7_grp_mux c1_can_rxd_grp2_mux = { - .pad_mux_count = array_size(c1_can_rxd_grp2_pad_mux), - .pad_mux_list = c1_can_rxd_grp2_pad_mux, -}; - -static struct atlas7_pad_mux c1_can_rxd_grp3_pad_mux[] = { - mux(1, 162, 4, 0xa00, 4, 0xa80, 4), -}; - -static struct atlas7_grp_mux c1_can_rxd_grp3_mux = { - .pad_mux_count = array_size(c1_can_rxd_grp3_pad_mux), - .pad_mux_list = c1_can_rxd_grp3_pad_mux, -}; - -static struct atlas7_pad_mux c1_can_txd_grp0_pad_mux[] = { - mux(1, 137, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux c1_can_txd_grp0_mux = { - .pad_mux_count = array_size(c1_can_txd_grp0_pad_mux), - .pad_mux_list = c1_can_txd_grp0_pad_mux, -}; - -static struct atlas7_pad_mux c1_can_txd_grp1_pad_mux[] = { - mux(1, 146, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux c1_can_txd_grp1_mux = { - .pad_mux_count = array_size(c1_can_txd_grp1_pad_mux), - .pad_mux_list = c1_can_txd_grp1_pad_mux, -}; - -static struct atlas7_pad_mux c1_can_txd_grp2_pad_mux[] = { - mux(0, 3, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux c1_can_txd_grp2_mux = { - .pad_mux_count = array_size(c1_can_txd_grp2_pad_mux), - .pad_mux_list = c1_can_txd_grp2_pad_mux, -}; - -static struct atlas7_pad_mux c1_can_txd_grp3_pad_mux[] = { - mux(1, 161, 4, n, n, n, n), -}; - -static struct atlas7_grp_mux c1_can_txd_grp3_mux = { - .pad_mux_count = array_size(c1_can_txd_grp3_pad_mux), - .pad_mux_list = c1_can_txd_grp3_pad_mux, -}; - -static struct atlas7_pad_mux ca_audio_lpc_grp_pad_mux[] = { - mux(1, 62, 4, n, n, n, n), - mux(1, 63, 4, n, n, n, n), - mux(1, 64, 4, n, n, n, n), - mux(1, 65, 4, n, n, n, n), - mux(1, 66, 4, n, n, n, n), - mux(1, 67, 4, n, n, n, n), - mux(1, 68, 4, n, n, n, n), - mux(1, 69, 4, n, n, n, n), - mux(1, 70, 4, n, n, n, n), - mux(1, 71, 4, n, n, n, n), -}; - -static struct atlas7_grp_mux ca_audio_lpc_grp_mux = { - .pad_mux_count = array_size(ca_audio_lpc_grp_pad_mux), - .pad_mux_list = ca_audio_lpc_grp_pad_mux, -}; - -static struct atlas7_pad_mux ca_bt_lpc_grp_pad_mux[] = { - mux(1, 85, 5, n, n, n, n), - mux(1, 86, 5, n, n, n, n), - mux(1, 87, 5, n, n, n, n), - mux(1, 88, 5, n, n, n, n), - mux(1, 89, 5, n, n, n, n), - mux(1, 90, 5, n, n, n, n), -}; - -static struct atlas7_grp_mux ca_bt_lpc_grp_mux = { - .pad_mux_count = array_size(ca_bt_lpc_grp_pad_mux), - .pad_mux_list = ca_bt_lpc_grp_pad_mux, -}; - -static struct atlas7_pad_mux ca_coex_grp_pad_mux[] = { - mux(1, 129, 1, n, n, n, n), - mux(1, 130, 1, n, n, n, n), - mux(1, 131, 1, n, n, n, n), - mux(1, 132, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux ca_coex_grp_mux = { - .pad_mux_count = array_size(ca_coex_grp_pad_mux), - .pad_mux_list = ca_coex_grp_pad_mux, -}; - -static struct atlas7_pad_mux ca_curator_lpc_grp_pad_mux[] = { - mux(1, 57, 4, n, n, n, n), - mux(1, 58, 4, n, n, n, n), - mux(1, 59, 4, n, n, n, n), - mux(1, 60, 4, n, n, n, n), -}; - -static struct atlas7_grp_mux ca_curator_lpc_grp_mux = { - .pad_mux_count = array_size(ca_curator_lpc_grp_pad_mux), - .pad_mux_list = ca_curator_lpc_grp_pad_mux, -}; - -static struct atlas7_pad_mux ca_pcm_debug_grp_pad_mux[] = { - mux(1, 91, 5, n, n, n, n), - mux(1, 93, 5, n, n, n, n), - mux(1, 94, 5, n, n, n, n), - mux(1, 92, 5, n, n, n, n), -}; - -static struct atlas7_grp_mux ca_pcm_debug_grp_mux = { - .pad_mux_count = array_size(ca_pcm_debug_grp_pad_mux), - .pad_mux_list = ca_pcm_debug_grp_pad_mux, -}; - -static struct atlas7_pad_mux ca_pio_grp_pad_mux[] = { - mux(1, 121, 2, n, n, n, n), - mux(1, 122, 2, n, n, n, n), - mux(1, 125, 6, n, n, n, n), - mux(1, 126, 6, n, n, n, n), - mux(1, 38, 5, n, n, n, n), - mux(1, 37, 5, n, n, n, n), - mux(1, 47, 5, n, n, n, n), - mux(1, 49, 5, n, n, n, n), - mux(1, 50, 5, n, n, n, n), - mux(1, 54, 4, n, n, n, n), - mux(1, 55, 4, n, n, n, n), - mux(1, 56, 4, n, n, n, n), -}; - -static struct atlas7_grp_mux ca_pio_grp_mux = { - .pad_mux_count = array_size(ca_pio_grp_pad_mux), - .pad_mux_list = ca_pio_grp_pad_mux, -}; - -static struct atlas7_pad_mux ca_sdio_debug_grp_pad_mux[] = { - mux(1, 40, 5, n, n, n, n), - mux(1, 39, 5, n, n, n, n), - mux(1, 44, 5, n, n, n, n), - mux(1, 43, 5, n, n, n, n), - mux(1, 42, 5, n, n, n, n), - mux(1, 41, 5, n, n, n, n), -}; - -static struct atlas7_grp_mux ca_sdio_debug_grp_mux = { - .pad_mux_count = array_size(ca_sdio_debug_grp_pad_mux), - .pad_mux_list = ca_sdio_debug_grp_pad_mux, -}; - -static struct atlas7_pad_mux ca_spi_grp_pad_mux[] = { - mux(1, 82, 5, n, n, n, n), - mux(1, 79, 5, 0xa08, 6, 0xa88, 6), - mux(1, 80, 5, n, n, n, n), - mux(1, 81, 5, n, n, n, n), -}; - -static struct atlas7_grp_mux ca_spi_grp_mux = { - .pad_mux_count = array_size(ca_spi_grp_pad_mux), - .pad_mux_list = ca_spi_grp_pad_mux, -}; - -static struct atlas7_pad_mux ca_trb_grp_pad_mux[] = { - mux(1, 91, 4, n, n, n, n), - mux(1, 93, 4, n, n, n, n), - mux(1, 94, 4, n, n, n, n), - mux(1, 95, 4, n, n, n, n), - mux(1, 96, 4, n, n, n, n), - mux(1, 78, 5, n, n, n, n), - mux(1, 74, 5, n, n, n, n), - mux(1, 75, 5, n, n, n, n), - mux(1, 76, 5, n, n, n, n), - mux(1, 77, 5, n, n, n, n), -}; - -static struct atlas7_grp_mux ca_trb_grp_mux = { - .pad_mux_count = array_size(ca_trb_grp_pad_mux), - .pad_mux_list = ca_trb_grp_pad_mux, -}; - -static struct atlas7_pad_mux ca_uart_debug_grp_pad_mux[] = { - mux(1, 136, 3, n, n, n, n), - mux(1, 135, 3, n, n, n, n), - mux(1, 134, 3, n, n, n, n), - mux(1, 133, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux ca_uart_debug_grp_mux = { - .pad_mux_count = array_size(ca_uart_debug_grp_pad_mux), - .pad_mux_list = ca_uart_debug_grp_pad_mux, -}; - -static struct atlas7_pad_mux clkc_grp0_pad_mux[] = { - mux(1, 30, 2, 0xa08, 14, 0xa88, 14), - mux(1, 47, 6, n, n, n, n), -}; - -static struct atlas7_grp_mux clkc_grp0_mux = { - .pad_mux_count = array_size(clkc_grp0_pad_mux), - .pad_mux_list = clkc_grp0_pad_mux, -}; - -static struct atlas7_pad_mux clkc_grp1_pad_mux[] = { - mux(1, 78, 3, 0xa08, 14, 0xa88, 14), - mux(1, 54, 5, n, n, n, n), -}; - -static struct atlas7_grp_mux clkc_grp1_mux = { - .pad_mux_count = array_size(clkc_grp1_pad_mux), - .pad_mux_list = clkc_grp1_pad_mux, -}; - -static struct atlas7_pad_mux gn_gnss_i2c_grp_pad_mux[] = { - mux(1, 128, 2, n, n, n, n), - mux(1, 127, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux gn_gnss_i2c_grp_mux = { - .pad_mux_count = array_size(gn_gnss_i2c_grp_pad_mux), - .pad_mux_list = gn_gnss_i2c_grp_pad_mux, -}; - -static struct atlas7_pad_mux gn_gnss_uart_nopause_grp_pad_mux[] = { - mux(1, 134, 4, n, n, n, n), - mux(1, 133, 4, n, n, n, n), -}; - -static struct atlas7_grp_mux gn_gnss_uart_nopause_grp_mux = { - .pad_mux_count = array_size(gn_gnss_uart_nopause_grp_pad_mux), - .pad_mux_list = gn_gnss_uart_nopause_grp_pad_mux, -}; - -static struct atlas7_pad_mux gn_gnss_uart_grp_pad_mux[] = { - mux(1, 134, 4, n, n, n, n), - mux(1, 133, 4, n, n, n, n), - mux(1, 136, 4, n, n, n, n), - mux(1, 135, 4, n, n, n, n), -}; - -static struct atlas7_grp_mux gn_gnss_uart_grp_mux = { - .pad_mux_count = array_size(gn_gnss_uart_grp_pad_mux), - .pad_mux_list = gn_gnss_uart_grp_pad_mux, -}; - -static struct atlas7_pad_mux gn_trg_spi_grp0_pad_mux[] = { - mux(1, 22, 1, n, n, n, n), - mux(1, 25, 1, n, n, n, n), - mux(1, 23, 1, 0xa00, 10, 0xa80, 10), - mux(1, 24, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux gn_trg_spi_grp0_mux = { - .pad_mux_count = array_size(gn_trg_spi_grp0_pad_mux), - .pad_mux_list = gn_trg_spi_grp0_pad_mux, -}; - -static struct atlas7_pad_mux gn_trg_spi_grp1_pad_mux[] = { - mux(1, 82, 3, n, n, n, n), - mux(1, 79, 3, n, n, n, n), - mux(1, 80, 3, 0xa00, 10, 0xa80, 10), - mux(1, 81, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux gn_trg_spi_grp1_mux = { - .pad_mux_count = array_size(gn_trg_spi_grp1_pad_mux), - .pad_mux_list = gn_trg_spi_grp1_pad_mux, -}; - -static struct atlas7_pad_mux cvbs_dbg_grp_pad_mux[] = { - mux(1, 54, 3, n, n, n, n), - mux(1, 53, 3, n, n, n, n), - mux(1, 82, 7, n, n, n, n), - mux(1, 74, 7, n, n, n, n), - mux(1, 75, 7, n, n, n, n), - mux(1, 76, 7, n, n, n, n), - mux(1, 77, 7, n, n, n, n), - mux(1, 78, 7, n, n, n, n), - mux(1, 79, 7, n, n, n, n), - mux(1, 80, 7, n, n, n, n), - mux(1, 81, 7, n, n, n, n), - mux(1, 83, 7, n, n, n, n), - mux(1, 84, 7, n, n, n, n), - mux(1, 73, 3, n, n, n, n), - mux(1, 55, 3, n, n, n, n), - mux(1, 56, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux cvbs_dbg_grp_mux = { - .pad_mux_count = array_size(cvbs_dbg_grp_pad_mux), - .pad_mux_list = cvbs_dbg_grp_pad_mux, -}; - -static struct atlas7_pad_mux cvbs_dbg_test_grp0_pad_mux[] = { - mux(1, 57, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux cvbs_dbg_test_grp0_mux = { - .pad_mux_count = array_size(cvbs_dbg_test_grp0_pad_mux), - .pad_mux_list = cvbs_dbg_test_grp0_pad_mux, -}; - -static struct atlas7_pad_mux cvbs_dbg_test_grp1_pad_mux[] = { - mux(1, 58, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux cvbs_dbg_test_grp1_mux = { - .pad_mux_count = array_size(cvbs_dbg_test_grp1_pad_mux), - .pad_mux_list = cvbs_dbg_test_grp1_pad_mux, -}; - -static struct atlas7_pad_mux cvbs_dbg_test_grp2_pad_mux[] = { - mux(1, 59, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux cvbs_dbg_test_grp2_mux = { - .pad_mux_count = array_size(cvbs_dbg_test_grp2_pad_mux), - .pad_mux_list = cvbs_dbg_test_grp2_pad_mux, -}; - -static struct atlas7_pad_mux cvbs_dbg_test_grp3_pad_mux[] = { - mux(1, 60, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux cvbs_dbg_test_grp3_mux = { - .pad_mux_count = array_size(cvbs_dbg_test_grp3_pad_mux), - .pad_mux_list = cvbs_dbg_test_grp3_pad_mux, -}; - -static struct atlas7_pad_mux cvbs_dbg_test_grp4_pad_mux[] = { - mux(1, 61, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux cvbs_dbg_test_grp4_mux = { - .pad_mux_count = array_size(cvbs_dbg_test_grp4_pad_mux), - .pad_mux_list = cvbs_dbg_test_grp4_pad_mux, -}; - -static struct atlas7_pad_mux cvbs_dbg_test_grp5_pad_mux[] = { - mux(1, 62, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux cvbs_dbg_test_grp5_mux = { - .pad_mux_count = array_size(cvbs_dbg_test_grp5_pad_mux), - .pad_mux_list = cvbs_dbg_test_grp5_pad_mux, -}; - -static struct atlas7_pad_mux cvbs_dbg_test_grp6_pad_mux[] = { - mux(1, 63, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux cvbs_dbg_test_grp6_mux = { - .pad_mux_count = array_size(cvbs_dbg_test_grp6_pad_mux), - .pad_mux_list = cvbs_dbg_test_grp6_pad_mux, -}; - -static struct atlas7_pad_mux cvbs_dbg_test_grp7_pad_mux[] = { - mux(1, 64, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux cvbs_dbg_test_grp7_mux = { - .pad_mux_count = array_size(cvbs_dbg_test_grp7_pad_mux), - .pad_mux_list = cvbs_dbg_test_grp7_pad_mux, -}; - -static struct atlas7_pad_mux cvbs_dbg_test_grp8_pad_mux[] = { - mux(1, 65, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux cvbs_dbg_test_grp8_mux = { - .pad_mux_count = array_size(cvbs_dbg_test_grp8_pad_mux), - .pad_mux_list = cvbs_dbg_test_grp8_pad_mux, -}; - -static struct atlas7_pad_mux cvbs_dbg_test_grp9_pad_mux[] = { - mux(1, 66, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux cvbs_dbg_test_grp9_mux = { - .pad_mux_count = array_size(cvbs_dbg_test_grp9_pad_mux), - .pad_mux_list = cvbs_dbg_test_grp9_pad_mux, -}; - -static struct atlas7_pad_mux cvbs_dbg_test_grp10_pad_mux[] = { - mux(1, 67, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux cvbs_dbg_test_grp10_mux = { - .pad_mux_count = array_size(cvbs_dbg_test_grp10_pad_mux), - .pad_mux_list = cvbs_dbg_test_grp10_pad_mux, -}; - -static struct atlas7_pad_mux cvbs_dbg_test_grp11_pad_mux[] = { - mux(1, 68, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux cvbs_dbg_test_grp11_mux = { - .pad_mux_count = array_size(cvbs_dbg_test_grp11_pad_mux), - .pad_mux_list = cvbs_dbg_test_grp11_pad_mux, -}; - -static struct atlas7_pad_mux cvbs_dbg_test_grp12_pad_mux[] = { - mux(1, 69, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux cvbs_dbg_test_grp12_mux = { - .pad_mux_count = array_size(cvbs_dbg_test_grp12_pad_mux), - .pad_mux_list = cvbs_dbg_test_grp12_pad_mux, -}; - -static struct atlas7_pad_mux cvbs_dbg_test_grp13_pad_mux[] = { - mux(1, 70, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux cvbs_dbg_test_grp13_mux = { - .pad_mux_count = array_size(cvbs_dbg_test_grp13_pad_mux), - .pad_mux_list = cvbs_dbg_test_grp13_pad_mux, -}; - -static struct atlas7_pad_mux cvbs_dbg_test_grp14_pad_mux[] = { - mux(1, 71, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux cvbs_dbg_test_grp14_mux = { - .pad_mux_count = array_size(cvbs_dbg_test_grp14_pad_mux), - .pad_mux_list = cvbs_dbg_test_grp14_pad_mux, -}; - -static struct atlas7_pad_mux cvbs_dbg_test_grp15_pad_mux[] = { - mux(1, 72, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux cvbs_dbg_test_grp15_mux = { - .pad_mux_count = array_size(cvbs_dbg_test_grp15_pad_mux), - .pad_mux_list = cvbs_dbg_test_grp15_pad_mux, -}; - -static struct atlas7_pad_mux gn_gnss_power_grp_pad_mux[] = { - mux(1, 123, 7, n, n, n, n), - mux(1, 124, 7, n, n, n, n), - mux(1, 121, 7, n, n, n, n), - mux(1, 122, 7, n, n, n, n), - mux(1, 125, 7, n, n, n, n), - mux(1, 120, 7, n, n, n, n), -}; - -static struct atlas7_grp_mux gn_gnss_power_grp_mux = { - .pad_mux_count = array_size(gn_gnss_power_grp_pad_mux), - .pad_mux_list = gn_gnss_power_grp_pad_mux, -}; - -static struct atlas7_pad_mux gn_gnss_sw_status_grp_pad_mux[] = { - mux(1, 57, 7, n, n, n, n), - mux(1, 58, 7, n, n, n, n), - mux(1, 59, 7, n, n, n, n), - mux(1, 60, 7, n, n, n, n), - mux(1, 61, 7, n, n, n, n), - mux(1, 62, 7, n, n, n, n), - mux(1, 63, 7, n, n, n, n), - mux(1, 64, 7, n, n, n, n), - mux(1, 65, 7, n, n, n, n), - mux(1, 66, 7, n, n, n, n), - mux(1, 67, 7, n, n, n, n), - mux(1, 68, 7, n, n, n, n), - mux(1, 69, 7, n, n, n, n), - mux(1, 70, 7, n, n, n, n), - mux(1, 71, 7, n, n, n, n), - mux(1, 72, 7, n, n, n, n), - mux(1, 53, 7, n, n, n, n), - mux(1, 55, 7, n, n, n, n), - mux(1, 56, 7, 0xa08, 12, 0xa88, 12), - mux(1, 54, 7, n, n, n, n), -}; - -static struct atlas7_grp_mux gn_gnss_sw_status_grp_mux = { - .pad_mux_count = array_size(gn_gnss_sw_status_grp_pad_mux), - .pad_mux_list = gn_gnss_sw_status_grp_pad_mux, -}; - -static struct atlas7_pad_mux gn_gnss_eclk_grp_pad_mux[] = { - mux(1, 113, 4, n, n, n, n), -}; - -static struct atlas7_grp_mux gn_gnss_eclk_grp_mux = { - .pad_mux_count = array_size(gn_gnss_eclk_grp_pad_mux), - .pad_mux_list = gn_gnss_eclk_grp_pad_mux, -}; - -static struct atlas7_pad_mux gn_gnss_irq1_grp0_pad_mux[] = { - mux(1, 112, 4, 0xa08, 10, 0xa88, 10), -}; - -static struct atlas7_grp_mux gn_gnss_irq1_grp0_mux = { - .pad_mux_count = array_size(gn_gnss_irq1_grp0_pad_mux), - .pad_mux_list = gn_gnss_irq1_grp0_pad_mux, -}; - -static struct atlas7_pad_mux gn_gnss_irq2_grp0_pad_mux[] = { - mux(1, 118, 4, 0xa08, 11, 0xa88, 11), -}; - -static struct atlas7_grp_mux gn_gnss_irq2_grp0_mux = { - .pad_mux_count = array_size(gn_gnss_irq2_grp0_pad_mux), - .pad_mux_list = gn_gnss_irq2_grp0_pad_mux, -}; - -static struct atlas7_pad_mux gn_gnss_tm_grp_pad_mux[] = { - mux(1, 115, 4, n, n, n, n), -}; - -static struct atlas7_grp_mux gn_gnss_tm_grp_mux = { - .pad_mux_count = array_size(gn_gnss_tm_grp_pad_mux), - .pad_mux_list = gn_gnss_tm_grp_pad_mux, -}; - -static struct atlas7_pad_mux gn_gnss_tsync_grp_pad_mux[] = { - mux(1, 114, 4, n, n, n, n), -}; - -static struct atlas7_grp_mux gn_gnss_tsync_grp_mux = { - .pad_mux_count = array_size(gn_gnss_tsync_grp_pad_mux), - .pad_mux_list = gn_gnss_tsync_grp_pad_mux, -}; - -static struct atlas7_pad_mux gn_io_gnsssys_sw_cfg_grp_pad_mux[] = { - mux(1, 44, 7, n, n, n, n), - mux(1, 43, 7, n, n, n, n), - mux(1, 42, 7, n, n, n, n), - mux(1, 41, 7, n, n, n, n), - mux(1, 40, 7, n, n, n, n), - mux(1, 39, 7, n, n, n, n), - mux(1, 38, 7, n, n, n, n), - mux(1, 37, 7, n, n, n, n), - mux(1, 49, 7, n, n, n, n), - mux(1, 50, 7, n, n, n, n), - mux(1, 91, 7, n, n, n, n), - mux(1, 92, 7, n, n, n, n), - mux(1, 93, 7, n, n, n, n), - mux(1, 94, 7, n, n, n, n), - mux(1, 95, 7, n, n, n, n), - mux(1, 96, 7, n, n, n, n), -}; - -static struct atlas7_grp_mux gn_io_gnsssys_sw_cfg_grp_mux = { - .pad_mux_count = array_size(gn_io_gnsssys_sw_cfg_grp_pad_mux), - .pad_mux_list = gn_io_gnsssys_sw_cfg_grp_pad_mux, -}; - -static struct atlas7_pad_mux gn_trg_grp0_pad_mux[] = { - mux(1, 29, 1, 0xa00, 6, 0xa80, 6), - mux(1, 28, 1, 0xa00, 7, 0xa80, 7), - mux(1, 26, 1, 0xa00, 8, 0xa80, 8), - mux(1, 27, 1, 0xa00, 9, 0xa80, 9), -}; - -static struct atlas7_grp_mux gn_trg_grp0_mux = { - .pad_mux_count = array_size(gn_trg_grp0_pad_mux), - .pad_mux_list = gn_trg_grp0_pad_mux, -}; - -static struct atlas7_pad_mux gn_trg_grp1_pad_mux[] = { - mux(1, 77, 3, 0xa00, 6, 0xa80, 6), - mux(1, 76, 3, 0xa00, 7, 0xa80, 7), - mux(1, 74, 3, 0xa00, 8, 0xa80, 8), - mux(1, 75, 3, 0xa00, 9, 0xa80, 9), -}; - -static struct atlas7_grp_mux gn_trg_grp1_mux = { - .pad_mux_count = array_size(gn_trg_grp1_pad_mux), - .pad_mux_list = gn_trg_grp1_pad_mux, -}; - -static struct atlas7_pad_mux gn_trg_shutdown_grp0_pad_mux[] = { - mux(1, 30, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux gn_trg_shutdown_grp0_mux = { - .pad_mux_count = array_size(gn_trg_shutdown_grp0_pad_mux), - .pad_mux_list = gn_trg_shutdown_grp0_pad_mux, -}; - -static struct atlas7_pad_mux gn_trg_shutdown_grp1_pad_mux[] = { - mux(1, 83, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux gn_trg_shutdown_grp1_mux = { - .pad_mux_count = array_size(gn_trg_shutdown_grp1_pad_mux), - .pad_mux_list = gn_trg_shutdown_grp1_pad_mux, -}; - -static struct atlas7_pad_mux gn_trg_shutdown_grp2_pad_mux[] = { - mux(1, 117, 4, n, n, n, n), -}; - -static struct atlas7_grp_mux gn_trg_shutdown_grp2_mux = { - .pad_mux_count = array_size(gn_trg_shutdown_grp2_pad_mux), - .pad_mux_list = gn_trg_shutdown_grp2_pad_mux, -}; - -static struct atlas7_pad_mux gn_trg_shutdown_grp3_pad_mux[] = { - mux(1, 123, 5, n, n, n, n), -}; - -static struct atlas7_grp_mux gn_trg_shutdown_grp3_mux = { - .pad_mux_count = array_size(gn_trg_shutdown_grp3_pad_mux), - .pad_mux_list = gn_trg_shutdown_grp3_pad_mux, -}; - -static struct atlas7_pad_mux i2c0_grp_pad_mux[] = { - mux(1, 128, 1, n, n, n, n), - mux(1, 127, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux i2c0_grp_mux = { - .pad_mux_count = array_size(i2c0_grp_pad_mux), - .pad_mux_list = i2c0_grp_pad_mux, -}; - -static struct atlas7_pad_mux i2c1_grp_pad_mux[] = { - mux(1, 126, 4, n, n, n, n), - mux(1, 125, 4, n, n, n, n), -}; - -static struct atlas7_grp_mux i2c1_grp_mux = { - .pad_mux_count = array_size(i2c1_grp_pad_mux), - .pad_mux_list = i2c1_grp_pad_mux, -}; - -static struct atlas7_pad_mux i2s0_grp_pad_mux[] = { - mux(1, 91, 2, 0xa10, 12, 0xa90, 12), - mux(1, 93, 2, 0xa10, 13, 0xa90, 13), - mux(1, 94, 2, 0xa10, 14, 0xa90, 14), - mux(1, 92, 2, 0xa10, 15, 0xa90, 15), -}; - -static struct atlas7_grp_mux i2s0_grp_mux = { - .pad_mux_count = array_size(i2s0_grp_pad_mux), - .pad_mux_list = i2s0_grp_pad_mux, -}; - -static struct atlas7_pad_mux i2s1_basic_grp_pad_mux[] = { - mux(1, 95, 2, 0xa10, 16, 0xa90, 16), - mux(1, 96, 2, 0xa10, 19, 0xa90, 19), -}; - -static struct atlas7_grp_mux i2s1_basic_grp_mux = { - .pad_mux_count = array_size(i2s1_basic_grp_pad_mux), - .pad_mux_list = i2s1_basic_grp_pad_mux, -}; - -static struct atlas7_pad_mux i2s1_rxd0_grp0_pad_mux[] = { - mux(1, 61, 4, 0xa10, 17, 0xa90, 17), -}; - -static struct atlas7_grp_mux i2s1_rxd0_grp0_mux = { - .pad_mux_count = array_size(i2s1_rxd0_grp0_pad_mux), - .pad_mux_list = i2s1_rxd0_grp0_pad_mux, -}; - -static struct atlas7_pad_mux i2s1_rxd0_grp1_pad_mux[] = { - mux(1, 131, 4, 0xa10, 17, 0xa90, 17), -}; - -static struct atlas7_grp_mux i2s1_rxd0_grp1_mux = { - .pad_mux_count = array_size(i2s1_rxd0_grp1_pad_mux), - .pad_mux_list = i2s1_rxd0_grp1_pad_mux, -}; - -static struct atlas7_pad_mux i2s1_rxd0_grp2_pad_mux[] = { - mux(1, 129, 2, 0xa10, 17, 0xa90, 17), -}; - -static struct atlas7_grp_mux i2s1_rxd0_grp2_mux = { - .pad_mux_count = array_size(i2s1_rxd0_grp2_pad_mux), - .pad_mux_list = i2s1_rxd0_grp2_pad_mux, -}; - -static struct atlas7_pad_mux i2s1_rxd0_grp3_pad_mux[] = { - mux(1, 117, 7, 0xa10, 17, 0xa90, 17), -}; - -static struct atlas7_grp_mux i2s1_rxd0_grp3_mux = { - .pad_mux_count = array_size(i2s1_rxd0_grp3_pad_mux), - .pad_mux_list = i2s1_rxd0_grp3_pad_mux, -}; - -static struct atlas7_pad_mux i2s1_rxd0_grp4_pad_mux[] = { - mux(1, 83, 4, 0xa10, 17, 0xa90, 17), -}; - -static struct atlas7_grp_mux i2s1_rxd0_grp4_mux = { - .pad_mux_count = array_size(i2s1_rxd0_grp4_pad_mux), - .pad_mux_list = i2s1_rxd0_grp4_pad_mux, -}; - -static struct atlas7_pad_mux i2s1_rxd1_grp0_pad_mux[] = { - mux(1, 72, 4, 0xa10, 18, 0xa90, 18), -}; - -static struct atlas7_grp_mux i2s1_rxd1_grp0_mux = { - .pad_mux_count = array_size(i2s1_rxd1_grp0_pad_mux), - .pad_mux_list = i2s1_rxd1_grp0_pad_mux, -}; - -static struct atlas7_pad_mux i2s1_rxd1_grp1_pad_mux[] = { - mux(1, 132, 4, 0xa10, 18, 0xa90, 18), -}; - -static struct atlas7_grp_mux i2s1_rxd1_grp1_mux = { - .pad_mux_count = array_size(i2s1_rxd1_grp1_pad_mux), - .pad_mux_list = i2s1_rxd1_grp1_pad_mux, -}; - -static struct atlas7_pad_mux i2s1_rxd1_grp2_pad_mux[] = { - mux(1, 130, 2, 0xa10, 18, 0xa90, 18), -}; - -static struct atlas7_grp_mux i2s1_rxd1_grp2_mux = { - .pad_mux_count = array_size(i2s1_rxd1_grp2_pad_mux), - .pad_mux_list = i2s1_rxd1_grp2_pad_mux, -}; - -static struct atlas7_pad_mux i2s1_rxd1_grp3_pad_mux[] = { - mux(1, 118, 7, 0xa10, 18, 0xa90, 18), -}; - -static struct atlas7_grp_mux i2s1_rxd1_grp3_mux = { - .pad_mux_count = array_size(i2s1_rxd1_grp3_pad_mux), - .pad_mux_list = i2s1_rxd1_grp3_pad_mux, -}; - -static struct atlas7_pad_mux i2s1_rxd1_grp4_pad_mux[] = { - mux(1, 84, 4, 0xa10, 18, 0xa90, 18), -}; - -static struct atlas7_grp_mux i2s1_rxd1_grp4_mux = { - .pad_mux_count = array_size(i2s1_rxd1_grp4_pad_mux), - .pad_mux_list = i2s1_rxd1_grp4_pad_mux, -}; - -static struct atlas7_pad_mux jtag_jt_dbg_nsrst_grp_pad_mux[] = { - mux(1, 125, 5, 0xa08, 2, 0xa88, 2), -}; - -static struct atlas7_grp_mux jtag_jt_dbg_nsrst_grp_mux = { - .pad_mux_count = array_size(jtag_jt_dbg_nsrst_grp_pad_mux), - .pad_mux_list = jtag_jt_dbg_nsrst_grp_pad_mux, -}; - -static struct atlas7_pad_mux jtag_ntrst_grp0_pad_mux[] = { - mux(0, 4, 3, 0xa08, 3, 0xa88, 3), -}; - -static struct atlas7_grp_mux jtag_ntrst_grp0_mux = { - .pad_mux_count = array_size(jtag_ntrst_grp0_pad_mux), - .pad_mux_list = jtag_ntrst_grp0_pad_mux, -}; - -static struct atlas7_pad_mux jtag_ntrst_grp1_pad_mux[] = { - mux(1, 163, 1, 0xa08, 3, 0xa88, 3), -}; - -static struct atlas7_grp_mux jtag_ntrst_grp1_mux = { - .pad_mux_count = array_size(jtag_ntrst_grp1_pad_mux), - .pad_mux_list = jtag_ntrst_grp1_pad_mux, -}; - -static struct atlas7_pad_mux jtag_swdiotms_grp0_pad_mux[] = { - mux(0, 2, 3, 0xa10, 10, 0xa90, 10), -}; - -static struct atlas7_grp_mux jtag_swdiotms_grp0_mux = { - .pad_mux_count = array_size(jtag_swdiotms_grp0_pad_mux), - .pad_mux_list = jtag_swdiotms_grp0_pad_mux, -}; - -static struct atlas7_pad_mux jtag_swdiotms_grp1_pad_mux[] = { - mux(1, 160, 1, 0xa10, 10, 0xa90, 10), -}; - -static struct atlas7_grp_mux jtag_swdiotms_grp1_mux = { - .pad_mux_count = array_size(jtag_swdiotms_grp1_pad_mux), - .pad_mux_list = jtag_swdiotms_grp1_pad_mux, -}; - -static struct atlas7_pad_mux jtag_tck_grp0_pad_mux[] = { - mux(0, 0, 3, 0xa10, 11, 0xa90, 11), -}; - -static struct atlas7_grp_mux jtag_tck_grp0_mux = { - .pad_mux_count = array_size(jtag_tck_grp0_pad_mux), - .pad_mux_list = jtag_tck_grp0_pad_mux, -}; - -static struct atlas7_pad_mux jtag_tck_grp1_pad_mux[] = { - mux(1, 161, 1, 0xa10, 11, 0xa90, 11), -}; - -static struct atlas7_grp_mux jtag_tck_grp1_mux = { - .pad_mux_count = array_size(jtag_tck_grp1_pad_mux), - .pad_mux_list = jtag_tck_grp1_pad_mux, -}; - -static struct atlas7_pad_mux jtag_tdi_grp0_pad_mux[] = { - mux(0, 1, 3, 0xa10, 31, 0xa90, 31), -}; - -static struct atlas7_grp_mux jtag_tdi_grp0_mux = { - .pad_mux_count = array_size(jtag_tdi_grp0_pad_mux), - .pad_mux_list = jtag_tdi_grp0_pad_mux, -}; - -static struct atlas7_pad_mux jtag_tdi_grp1_pad_mux[] = { - mux(1, 162, 1, 0xa10, 31, 0xa90, 31), -}; - -static struct atlas7_grp_mux jtag_tdi_grp1_mux = { - .pad_mux_count = array_size(jtag_tdi_grp1_pad_mux), - .pad_mux_list = jtag_tdi_grp1_pad_mux, -}; - -static struct atlas7_pad_mux jtag_tdo_grp0_pad_mux[] = { - mux(0, 3, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux jtag_tdo_grp0_mux = { - .pad_mux_count = array_size(jtag_tdo_grp0_pad_mux), - .pad_mux_list = jtag_tdo_grp0_pad_mux, -}; - -static struct atlas7_pad_mux jtag_tdo_grp1_pad_mux[] = { - mux(1, 159, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux jtag_tdo_grp1_mux = { - .pad_mux_count = array_size(jtag_tdo_grp1_pad_mux), - .pad_mux_list = jtag_tdo_grp1_pad_mux, -}; - -static struct atlas7_pad_mux ks_kas_spi_grp0_pad_mux[] = { - mux(1, 141, 2, n, n, n, n), - mux(1, 144, 2, 0xa08, 8, 0xa88, 8), - mux(1, 143, 2, n, n, n, n), - mux(1, 142, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux ks_kas_spi_grp0_mux = { - .pad_mux_count = array_size(ks_kas_spi_grp0_pad_mux), - .pad_mux_list = ks_kas_spi_grp0_pad_mux, -}; - -static struct atlas7_pad_mux ld_ldd_grp_pad_mux[] = { - mux(1, 57, 1, n, n, n, n), - mux(1, 58, 1, n, n, n, n), - mux(1, 59, 1, n, n, n, n), - mux(1, 60, 1, n, n, n, n), - mux(1, 61, 1, n, n, n, n), - mux(1, 62, 1, n, n, n, n), - mux(1, 63, 1, n, n, n, n), - mux(1, 64, 1, n, n, n, n), - mux(1, 65, 1, n, n, n, n), - mux(1, 66, 1, n, n, n, n), - mux(1, 67, 1, n, n, n, n), - mux(1, 68, 1, n, n, n, n), - mux(1, 69, 1, n, n, n, n), - mux(1, 70, 1, n, n, n, n), - mux(1, 71, 1, n, n, n, n), - mux(1, 72, 1, n, n, n, n), - mux(1, 74, 2, n, n, n, n), - mux(1, 75, 2, n, n, n, n), - mux(1, 76, 2, n, n, n, n), - mux(1, 77, 2, n, n, n, n), - mux(1, 78, 2, n, n, n, n), - mux(1, 79, 2, n, n, n, n), - mux(1, 80, 2, n, n, n, n), - mux(1, 81, 2, n, n, n, n), - mux(1, 56, 1, n, n, n, n), - mux(1, 53, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux ld_ldd_grp_mux = { - .pad_mux_count = array_size(ld_ldd_grp_pad_mux), - .pad_mux_list = ld_ldd_grp_pad_mux, -}; - -static struct atlas7_pad_mux ld_ldd_16bit_grp_pad_mux[] = { - mux(1, 57, 1, n, n, n, n), - mux(1, 58, 1, n, n, n, n), - mux(1, 59, 1, n, n, n, n), - mux(1, 60, 1, n, n, n, n), - mux(1, 61, 1, n, n, n, n), - mux(1, 62, 1, n, n, n, n), - mux(1, 63, 1, n, n, n, n), - mux(1, 64, 1, n, n, n, n), - mux(1, 65, 1, n, n, n, n), - mux(1, 66, 1, n, n, n, n), - mux(1, 67, 1, n, n, n, n), - mux(1, 68, 1, n, n, n, n), - mux(1, 69, 1, n, n, n, n), - mux(1, 70, 1, n, n, n, n), - mux(1, 71, 1, n, n, n, n), - mux(1, 72, 1, n, n, n, n), - mux(1, 56, 1, n, n, n, n), - mux(1, 53, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux ld_ldd_16bit_grp_mux = { - .pad_mux_count = array_size(ld_ldd_16bit_grp_pad_mux), - .pad_mux_list = ld_ldd_16bit_grp_pad_mux, -}; - -static struct atlas7_pad_mux ld_ldd_fck_grp_pad_mux[] = { - mux(1, 55, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux ld_ldd_fck_grp_mux = { - .pad_mux_count = array_size(ld_ldd_fck_grp_pad_mux), - .pad_mux_list = ld_ldd_fck_grp_pad_mux, -}; - -static struct atlas7_pad_mux ld_ldd_lck_grp_pad_mux[] = { - mux(1, 54, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux ld_ldd_lck_grp_mux = { - .pad_mux_count = array_size(ld_ldd_lck_grp_pad_mux), - .pad_mux_list = ld_ldd_lck_grp_pad_mux, -}; - -static struct atlas7_pad_mux lr_lcdrom_grp_pad_mux[] = { - mux(1, 73, 2, n, n, n, n), - mux(1, 54, 2, n, n, n, n), - mux(1, 57, 2, n, n, n, n), - mux(1, 58, 2, n, n, n, n), - mux(1, 59, 2, n, n, n, n), - mux(1, 60, 2, n, n, n, n), - mux(1, 61, 2, n, n, n, n), - mux(1, 62, 2, n, n, n, n), - mux(1, 63, 2, n, n, n, n), - mux(1, 64, 2, n, n, n, n), - mux(1, 65, 2, n, n, n, n), - mux(1, 66, 2, n, n, n, n), - mux(1, 67, 2, n, n, n, n), - mux(1, 68, 2, n, n, n, n), - mux(1, 69, 2, n, n, n, n), - mux(1, 70, 2, n, n, n, n), - mux(1, 71, 2, n, n, n, n), - mux(1, 72, 2, n, n, n, n), - mux(1, 56, 2, n, n, n, n), - mux(1, 53, 2, n, n, n, n), - mux(1, 55, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux lr_lcdrom_grp_mux = { - .pad_mux_count = array_size(lr_lcdrom_grp_pad_mux), - .pad_mux_list = lr_lcdrom_grp_pad_mux, -}; - -static struct atlas7_pad_mux lvds_analog_grp_pad_mux[] = { - mux(1, 149, 8, n, n, n, n), - mux(1, 150, 8, n, n, n, n), - mux(1, 151, 8, n, n, n, n), - mux(1, 152, 8, n, n, n, n), - mux(1, 153, 8, n, n, n, n), - mux(1, 154, 8, n, n, n, n), - mux(1, 155, 8, n, n, n, n), - mux(1, 156, 8, n, n, n, n), - mux(1, 157, 8, n, n, n, n), - mux(1, 158, 8, n, n, n, n), -}; - -static struct atlas7_grp_mux lvds_analog_grp_mux = { - .pad_mux_count = array_size(lvds_analog_grp_pad_mux), - .pad_mux_list = lvds_analog_grp_pad_mux, -}; - -static struct atlas7_pad_mux nd_df_basic_grp_pad_mux[] = { - mux(1, 44, 1, n, n, n, n), - mux(1, 43, 1, n, n, n, n), - mux(1, 42, 1, n, n, n, n), - mux(1, 41, 1, n, n, n, n), - mux(1, 40, 1, n, n, n, n), - mux(1, 39, 1, n, n, n, n), - mux(1, 38, 1, n, n, n, n), - mux(1, 37, 1, n, n, n, n), - mux(1, 47, 1, n, n, n, n), - mux(1, 46, 1, n, n, n, n), - mux(1, 52, 1, n, n, n, n), - mux(1, 45, 1, n, n, n, n), - mux(1, 49, 1, n, n, n, n), - mux(1, 50, 1, n, n, n, n), - mux(1, 48, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux nd_df_basic_grp_mux = { - .pad_mux_count = array_size(nd_df_basic_grp_pad_mux), - .pad_mux_list = nd_df_basic_grp_pad_mux, -}; - -static struct atlas7_pad_mux nd_df_wp_grp_pad_mux[] = { - mux(1, 124, 4, n, n, n, n), -}; - -static struct atlas7_grp_mux nd_df_wp_grp_mux = { - .pad_mux_count = array_size(nd_df_wp_grp_pad_mux), - .pad_mux_list = nd_df_wp_grp_pad_mux, -}; - -static struct atlas7_pad_mux nd_df_cs_grp_pad_mux[] = { - mux(1, 51, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux nd_df_cs_grp_mux = { - .pad_mux_count = array_size(nd_df_cs_grp_pad_mux), - .pad_mux_list = nd_df_cs_grp_pad_mux, -}; - -static struct atlas7_pad_mux ps_grp_pad_mux[] = { - mux(1, 120, 2, n, n, n, n), - mux(1, 119, 2, n, n, n, n), - mux(1, 121, 5, n, n, n, n), -}; - -static struct atlas7_grp_mux ps_grp_mux = { - .pad_mux_count = array_size(ps_grp_pad_mux), - .pad_mux_list = ps_grp_pad_mux, -}; - -static struct atlas7_pad_mux ps_no_dir_grp_pad_mux[] = { - mux(1, 119, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux ps_no_dir_grp_mux = { - .pad_mux_count = array_size(ps_no_dir_grp_pad_mux), - .pad_mux_list = ps_no_dir_grp_pad_mux, -}; - -static struct atlas7_pad_mux pwc_core_on_grp_pad_mux[] = { - mux(0, 8, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux pwc_core_on_grp_mux = { - .pad_mux_count = array_size(pwc_core_on_grp_pad_mux), - .pad_mux_list = pwc_core_on_grp_pad_mux, -}; - -static struct atlas7_pad_mux pwc_ext_on_grp_pad_mux[] = { - mux(0, 6, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux pwc_ext_on_grp_mux = { - .pad_mux_count = array_size(pwc_ext_on_grp_pad_mux), - .pad_mux_list = pwc_ext_on_grp_pad_mux, -}; - -static struct atlas7_pad_mux pwc_gpio3_clk_grp_pad_mux[] = { - mux(0, 3, 4, n, n, n, n), -}; - -static struct atlas7_grp_mux pwc_gpio3_clk_grp_mux = { - .pad_mux_count = array_size(pwc_gpio3_clk_grp_pad_mux), - .pad_mux_list = pwc_gpio3_clk_grp_pad_mux, -}; - -static struct atlas7_pad_mux pwc_io_on_grp_pad_mux[] = { - mux(0, 9, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux pwc_io_on_grp_mux = { - .pad_mux_count = array_size(pwc_io_on_grp_pad_mux), - .pad_mux_list = pwc_io_on_grp_pad_mux, -}; - -static struct atlas7_pad_mux pwc_lowbatt_b_grp0_pad_mux[] = { - mux(0, 4, 1, 0xa08, 4, 0xa88, 4), -}; - -static struct atlas7_grp_mux pwc_lowbatt_b_grp0_mux = { - .pad_mux_count = array_size(pwc_lowbatt_b_grp0_pad_mux), - .pad_mux_list = pwc_lowbatt_b_grp0_pad_mux, -}; - -static struct atlas7_pad_mux pwc_mem_on_grp_pad_mux[] = { - mux(0, 7, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux pwc_mem_on_grp_mux = { - .pad_mux_count = array_size(pwc_mem_on_grp_pad_mux), - .pad_mux_list = pwc_mem_on_grp_pad_mux, -}; - -static struct atlas7_pad_mux pwc_on_key_b_grp0_pad_mux[] = { - mux(0, 5, 1, 0xa08, 5, 0xa88, 5), -}; - -static struct atlas7_grp_mux pwc_on_key_b_grp0_mux = { - .pad_mux_count = array_size(pwc_on_key_b_grp0_pad_mux), - .pad_mux_list = pwc_on_key_b_grp0_pad_mux, -}; - -static struct atlas7_pad_mux pwc_wakeup_src0_grp_pad_mux[] = { - mux(0, 0, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux pwc_wakeup_src0_grp_mux = { - .pad_mux_count = array_size(pwc_wakeup_src0_grp_pad_mux), - .pad_mux_list = pwc_wakeup_src0_grp_pad_mux, -}; - -static struct atlas7_pad_mux pwc_wakeup_src1_grp_pad_mux[] = { - mux(0, 1, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux pwc_wakeup_src1_grp_mux = { - .pad_mux_count = array_size(pwc_wakeup_src1_grp_pad_mux), - .pad_mux_list = pwc_wakeup_src1_grp_pad_mux, -}; - -static struct atlas7_pad_mux pwc_wakeup_src2_grp_pad_mux[] = { - mux(0, 2, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux pwc_wakeup_src2_grp_mux = { - .pad_mux_count = array_size(pwc_wakeup_src2_grp_pad_mux), - .pad_mux_list = pwc_wakeup_src2_grp_pad_mux, -}; - -static struct atlas7_pad_mux pwc_wakeup_src3_grp_pad_mux[] = { - mux(0, 3, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux pwc_wakeup_src3_grp_mux = { - .pad_mux_count = array_size(pwc_wakeup_src3_grp_pad_mux), - .pad_mux_list = pwc_wakeup_src3_grp_pad_mux, -}; - -static struct atlas7_pad_mux pw_cko0_grp0_pad_mux[] = { - mux(1, 123, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_cko0_grp0_mux = { - .pad_mux_count = array_size(pw_cko0_grp0_pad_mux), - .pad_mux_list = pw_cko0_grp0_pad_mux, -}; - -static struct atlas7_pad_mux pw_cko0_grp1_pad_mux[] = { - mux(1, 101, 4, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_cko0_grp1_mux = { - .pad_mux_count = array_size(pw_cko0_grp1_pad_mux), - .pad_mux_list = pw_cko0_grp1_pad_mux, -}; - -static struct atlas7_pad_mux pw_cko0_grp2_pad_mux[] = { - mux(1, 82, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_cko0_grp2_mux = { - .pad_mux_count = array_size(pw_cko0_grp2_pad_mux), - .pad_mux_list = pw_cko0_grp2_pad_mux, -}; - -static struct atlas7_pad_mux pw_cko0_grp3_pad_mux[] = { - mux(1, 162, 5, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_cko0_grp3_mux = { - .pad_mux_count = array_size(pw_cko0_grp3_pad_mux), - .pad_mux_list = pw_cko0_grp3_pad_mux, -}; - -static struct atlas7_pad_mux pw_cko1_grp0_pad_mux[] = { - mux(1, 124, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_cko1_grp0_mux = { - .pad_mux_count = array_size(pw_cko1_grp0_pad_mux), - .pad_mux_list = pw_cko1_grp0_pad_mux, -}; - -static struct atlas7_pad_mux pw_cko1_grp1_pad_mux[] = { - mux(1, 110, 4, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_cko1_grp1_mux = { - .pad_mux_count = array_size(pw_cko1_grp1_pad_mux), - .pad_mux_list = pw_cko1_grp1_pad_mux, -}; - -static struct atlas7_pad_mux pw_cko1_grp2_pad_mux[] = { - mux(1, 163, 5, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_cko1_grp2_mux = { - .pad_mux_count = array_size(pw_cko1_grp2_pad_mux), - .pad_mux_list = pw_cko1_grp2_pad_mux, -}; - -static struct atlas7_pad_mux pw_i2s01_clk_grp0_pad_mux[] = { - mux(1, 125, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_i2s01_clk_grp0_mux = { - .pad_mux_count = array_size(pw_i2s01_clk_grp0_pad_mux), - .pad_mux_list = pw_i2s01_clk_grp0_pad_mux, -}; - -static struct atlas7_pad_mux pw_i2s01_clk_grp1_pad_mux[] = { - mux(1, 117, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_i2s01_clk_grp1_mux = { - .pad_mux_count = array_size(pw_i2s01_clk_grp1_pad_mux), - .pad_mux_list = pw_i2s01_clk_grp1_pad_mux, -}; - -static struct atlas7_pad_mux pw_i2s01_clk_grp2_pad_mux[] = { - mux(1, 132, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_i2s01_clk_grp2_mux = { - .pad_mux_count = array_size(pw_i2s01_clk_grp2_pad_mux), - .pad_mux_list = pw_i2s01_clk_grp2_pad_mux, -}; - -static struct atlas7_pad_mux pw_pwm0_grp0_pad_mux[] = { - mux(1, 119, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_pwm0_grp0_mux = { - .pad_mux_count = array_size(pw_pwm0_grp0_pad_mux), - .pad_mux_list = pw_pwm0_grp0_pad_mux, -}; - -static struct atlas7_pad_mux pw_pwm0_grp1_pad_mux[] = { - mux(1, 159, 5, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_pwm0_grp1_mux = { - .pad_mux_count = array_size(pw_pwm0_grp1_pad_mux), - .pad_mux_list = pw_pwm0_grp1_pad_mux, -}; - -static struct atlas7_pad_mux pw_pwm1_grp0_pad_mux[] = { - mux(1, 120, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_pwm1_grp0_mux = { - .pad_mux_count = array_size(pw_pwm1_grp0_pad_mux), - .pad_mux_list = pw_pwm1_grp0_pad_mux, -}; - -static struct atlas7_pad_mux pw_pwm1_grp1_pad_mux[] = { - mux(1, 160, 5, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_pwm1_grp1_mux = { - .pad_mux_count = array_size(pw_pwm1_grp1_pad_mux), - .pad_mux_list = pw_pwm1_grp1_pad_mux, -}; - -static struct atlas7_pad_mux pw_pwm1_grp2_pad_mux[] = { - mux(1, 131, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_pwm1_grp2_mux = { - .pad_mux_count = array_size(pw_pwm1_grp2_pad_mux), - .pad_mux_list = pw_pwm1_grp2_pad_mux, -}; - -static struct atlas7_pad_mux pw_pwm2_grp0_pad_mux[] = { - mux(1, 121, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_pwm2_grp0_mux = { - .pad_mux_count = array_size(pw_pwm2_grp0_pad_mux), - .pad_mux_list = pw_pwm2_grp0_pad_mux, -}; - -static struct atlas7_pad_mux pw_pwm2_grp1_pad_mux[] = { - mux(1, 98, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_pwm2_grp1_mux = { - .pad_mux_count = array_size(pw_pwm2_grp1_pad_mux), - .pad_mux_list = pw_pwm2_grp1_pad_mux, -}; - -static struct atlas7_pad_mux pw_pwm2_grp2_pad_mux[] = { - mux(1, 161, 5, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_pwm2_grp2_mux = { - .pad_mux_count = array_size(pw_pwm2_grp2_pad_mux), - .pad_mux_list = pw_pwm2_grp2_pad_mux, -}; - -static struct atlas7_pad_mux pw_pwm3_grp0_pad_mux[] = { - mux(1, 122, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_pwm3_grp0_mux = { - .pad_mux_count = array_size(pw_pwm3_grp0_pad_mux), - .pad_mux_list = pw_pwm3_grp0_pad_mux, -}; - -static struct atlas7_pad_mux pw_pwm3_grp1_pad_mux[] = { - mux(1, 73, 4, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_pwm3_grp1_mux = { - .pad_mux_count = array_size(pw_pwm3_grp1_pad_mux), - .pad_mux_list = pw_pwm3_grp1_pad_mux, -}; - -static struct atlas7_pad_mux pw_pwm_cpu_vol_grp0_pad_mux[] = { - mux(1, 121, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_pwm_cpu_vol_grp0_mux = { - .pad_mux_count = array_size(pw_pwm_cpu_vol_grp0_pad_mux), - .pad_mux_list = pw_pwm_cpu_vol_grp0_pad_mux, -}; - -static struct atlas7_pad_mux pw_pwm_cpu_vol_grp1_pad_mux[] = { - mux(1, 98, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_pwm_cpu_vol_grp1_mux = { - .pad_mux_count = array_size(pw_pwm_cpu_vol_grp1_pad_mux), - .pad_mux_list = pw_pwm_cpu_vol_grp1_pad_mux, -}; - -static struct atlas7_pad_mux pw_pwm_cpu_vol_grp2_pad_mux[] = { - mux(1, 161, 5, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_pwm_cpu_vol_grp2_mux = { - .pad_mux_count = array_size(pw_pwm_cpu_vol_grp2_pad_mux), - .pad_mux_list = pw_pwm_cpu_vol_grp2_pad_mux, -}; - -static struct atlas7_pad_mux pw_backlight_grp0_pad_mux[] = { - mux(1, 122, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_backlight_grp0_mux = { - .pad_mux_count = array_size(pw_backlight_grp0_pad_mux), - .pad_mux_list = pw_backlight_grp0_pad_mux, -}; - -static struct atlas7_pad_mux pw_backlight_grp1_pad_mux[] = { - mux(1, 73, 4, n, n, n, n), -}; - -static struct atlas7_grp_mux pw_backlight_grp1_mux = { - .pad_mux_count = array_size(pw_backlight_grp1_pad_mux), - .pad_mux_list = pw_backlight_grp1_pad_mux, -}; - -static struct atlas7_pad_mux rg_eth_mac_grp_pad_mux[] = { - mux(1, 108, 1, n, n, n, n), - mux(1, 103, 1, n, n, n, n), - mux(1, 104, 1, n, n, n, n), - mux(1, 105, 1, n, n, n, n), - mux(1, 106, 1, n, n, n, n), - mux(1, 107, 1, n, n, n, n), - mux(1, 102, 1, n, n, n, n), - mux(1, 97, 1, n, n, n, n), - mux(1, 98, 1, n, n, n, n), - mux(1, 99, 1, n, n, n, n), - mux(1, 100, 1, n, n, n, n), - mux(1, 101, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux rg_eth_mac_grp_mux = { - .pad_mux_count = array_size(rg_eth_mac_grp_pad_mux), - .pad_mux_list = rg_eth_mac_grp_pad_mux, -}; - -static struct atlas7_pad_mux rg_gmac_phy_intr_n_grp_pad_mux[] = { - mux(1, 111, 1, 0xa08, 13, 0xa88, 13), -}; - -static struct atlas7_grp_mux rg_gmac_phy_intr_n_grp_mux = { - .pad_mux_count = array_size(rg_gmac_phy_intr_n_grp_pad_mux), - .pad_mux_list = rg_gmac_phy_intr_n_grp_pad_mux, -}; - -static struct atlas7_pad_mux rg_rgmii_mac_grp_pad_mux[] = { - mux(1, 109, 1, n, n, n, n), - mux(1, 110, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux rg_rgmii_mac_grp_mux = { - .pad_mux_count = array_size(rg_rgmii_mac_grp_pad_mux), - .pad_mux_list = rg_rgmii_mac_grp_pad_mux, -}; - -static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp0_pad_mux[] = { - mux(1, 111, 5, n, n, n, n), -}; - -static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp0_mux = { - .pad_mux_count = array_size(rg_rgmii_phy_ref_clk_grp0_pad_mux), - .pad_mux_list = rg_rgmii_phy_ref_clk_grp0_pad_mux, -}; - -static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp1_pad_mux[] = { - mux(1, 53, 4, n, n, n, n), -}; - -static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp1_mux = { - .pad_mux_count = array_size(rg_rgmii_phy_ref_clk_grp1_pad_mux), - .pad_mux_list = rg_rgmii_phy_ref_clk_grp1_pad_mux, -}; - -static struct atlas7_pad_mux sd0_grp_pad_mux[] = { - mux(1, 46, 2, n, n, n, n), - mux(1, 47, 2, n, n, n, n), - mux(1, 44, 2, n, n, n, n), - mux(1, 43, 2, n, n, n, n), - mux(1, 42, 2, n, n, n, n), - mux(1, 41, 2, n, n, n, n), - mux(1, 40, 2, n, n, n, n), - mux(1, 39, 2, n, n, n, n), - mux(1, 38, 2, n, n, n, n), - mux(1, 37, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux sd0_grp_mux = { - .pad_mux_count = array_size(sd0_grp_pad_mux), - .pad_mux_list = sd0_grp_pad_mux, -}; - -static struct atlas7_pad_mux sd0_4bit_grp_pad_mux[] = { - mux(1, 46, 2, n, n, n, n), - mux(1, 47, 2, n, n, n, n), - mux(1, 44, 2, n, n, n, n), - mux(1, 43, 2, n, n, n, n), - mux(1, 42, 2, n, n, n, n), - mux(1, 41, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux sd0_4bit_grp_mux = { - .pad_mux_count = array_size(sd0_4bit_grp_pad_mux), - .pad_mux_list = sd0_4bit_grp_pad_mux, -}; - -static struct atlas7_pad_mux sd1_grp_pad_mux[] = { - mux(1, 48, 3, n, n, n, n), - mux(1, 49, 3, n, n, n, n), - mux(1, 44, 3, 0xa00, 0, 0xa80, 0), - mux(1, 43, 3, 0xa00, 1, 0xa80, 1), - mux(1, 42, 3, 0xa00, 2, 0xa80, 2), - mux(1, 41, 3, 0xa00, 3, 0xa80, 3), - mux(1, 40, 3, n, n, n, n), - mux(1, 39, 3, n, n, n, n), - mux(1, 38, 3, n, n, n, n), - mux(1, 37, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux sd1_grp_mux = { - .pad_mux_count = array_size(sd1_grp_pad_mux), - .pad_mux_list = sd1_grp_pad_mux, -}; - -static struct atlas7_pad_mux sd1_4bit_grp0_pad_mux[] = { - mux(1, 48, 3, n, n, n, n), - mux(1, 49, 3, n, n, n, n), - mux(1, 44, 3, 0xa00, 0, 0xa80, 0), - mux(1, 43, 3, 0xa00, 1, 0xa80, 1), - mux(1, 42, 3, 0xa00, 2, 0xa80, 2), - mux(1, 41, 3, 0xa00, 3, 0xa80, 3), -}; - -static struct atlas7_grp_mux sd1_4bit_grp0_mux = { - .pad_mux_count = array_size(sd1_4bit_grp0_pad_mux), - .pad_mux_list = sd1_4bit_grp0_pad_mux, -}; - -static struct atlas7_pad_mux sd1_4bit_grp1_pad_mux[] = { - mux(1, 48, 3, n, n, n, n), - mux(1, 49, 3, n, n, n, n), - mux(1, 40, 4, 0xa00, 0, 0xa80, 0), - mux(1, 39, 4, 0xa00, 1, 0xa80, 1), - mux(1, 38, 4, 0xa00, 2, 0xa80, 2), - mux(1, 37, 4, 0xa00, 3, 0xa80, 3), -}; - -static struct atlas7_grp_mux sd1_4bit_grp1_mux = { - .pad_mux_count = array_size(sd1_4bit_grp1_pad_mux), - .pad_mux_list = sd1_4bit_grp1_pad_mux, -}; - -static struct atlas7_pad_mux sd2_basic_grp_pad_mux[] = { - mux(1, 31, 1, n, n, n, n), - mux(1, 32, 1, n, n, n, n), - mux(1, 33, 1, n, n, n, n), - mux(1, 34, 1, n, n, n, n), - mux(1, 35, 1, n, n, n, n), - mux(1, 36, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux sd2_basic_grp_mux = { - .pad_mux_count = array_size(sd2_basic_grp_pad_mux), - .pad_mux_list = sd2_basic_grp_pad_mux, -}; - -static struct atlas7_pad_mux sd2_cdb_grp0_pad_mux[] = { - mux(1, 124, 2, 0xa08, 7, 0xa88, 7), -}; - -static struct atlas7_grp_mux sd2_cdb_grp0_mux = { - .pad_mux_count = array_size(sd2_cdb_grp0_pad_mux), - .pad_mux_list = sd2_cdb_grp0_pad_mux, -}; - -static struct atlas7_pad_mux sd2_cdb_grp1_pad_mux[] = { - mux(1, 161, 6, 0xa08, 7, 0xa88, 7), -}; - -static struct atlas7_grp_mux sd2_cdb_grp1_mux = { - .pad_mux_count = array_size(sd2_cdb_grp1_pad_mux), - .pad_mux_list = sd2_cdb_grp1_pad_mux, -}; - -static struct atlas7_pad_mux sd2_wpb_grp0_pad_mux[] = { - mux(1, 123, 2, 0xa10, 6, 0xa90, 6), -}; - -static struct atlas7_grp_mux sd2_wpb_grp0_mux = { - .pad_mux_count = array_size(sd2_wpb_grp0_pad_mux), - .pad_mux_list = sd2_wpb_grp0_pad_mux, -}; - -static struct atlas7_pad_mux sd2_wpb_grp1_pad_mux[] = { - mux(1, 163, 7, 0xa10, 6, 0xa90, 6), -}; - -static struct atlas7_grp_mux sd2_wpb_grp1_mux = { - .pad_mux_count = array_size(sd2_wpb_grp1_pad_mux), - .pad_mux_list = sd2_wpb_grp1_pad_mux, -}; - -static struct atlas7_pad_mux sd3_9_grp_pad_mux[] = { - mux(1, 85, 1, n, n, n, n), - mux(1, 86, 1, n, n, n, n), - mux(1, 87, 1, n, n, n, n), - mux(1, 88, 1, n, n, n, n), - mux(1, 89, 1, n, n, n, n), - mux(1, 90, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux sd3_9_grp_mux = { - .pad_mux_count = array_size(sd3_9_grp_pad_mux), - .pad_mux_list = sd3_9_grp_pad_mux, -}; - -static struct atlas7_pad_mux sd5_grp_pad_mux[] = { - mux(1, 91, 1, n, n, n, n), - mux(1, 92, 1, n, n, n, n), - mux(1, 93, 1, n, n, n, n), - mux(1, 94, 1, n, n, n, n), - mux(1, 95, 1, n, n, n, n), - mux(1, 96, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux sd5_grp_mux = { - .pad_mux_count = array_size(sd5_grp_pad_mux), - .pad_mux_list = sd5_grp_pad_mux, -}; - -static struct atlas7_pad_mux sd6_grp0_pad_mux[] = { - mux(1, 79, 4, 0xa00, 27, 0xa80, 27), - mux(1, 78, 4, 0xa00, 26, 0xa80, 26), - mux(1, 74, 4, 0xa00, 28, 0xa80, 28), - mux(1, 75, 4, 0xa00, 29, 0xa80, 29), - mux(1, 76, 4, 0xa00, 30, 0xa80, 30), - mux(1, 77, 4, 0xa00, 31, 0xa80, 31), -}; - -static struct atlas7_grp_mux sd6_grp0_mux = { - .pad_mux_count = array_size(sd6_grp0_pad_mux), - .pad_mux_list = sd6_grp0_pad_mux, -}; - -static struct atlas7_pad_mux sd6_grp1_pad_mux[] = { - mux(1, 101, 3, 0xa00, 27, 0xa80, 27), - mux(1, 99, 3, 0xa00, 26, 0xa80, 26), - mux(1, 100, 3, 0xa00, 28, 0xa80, 28), - mux(1, 110, 3, 0xa00, 29, 0xa80, 29), - mux(1, 109, 3, 0xa00, 30, 0xa80, 30), - mux(1, 111, 3, 0xa00, 31, 0xa80, 31), -}; - -static struct atlas7_grp_mux sd6_grp1_mux = { - .pad_mux_count = array_size(sd6_grp1_pad_mux), - .pad_mux_list = sd6_grp1_pad_mux, -}; - -static struct atlas7_pad_mux sp0_ext_ldo_on_grp_pad_mux[] = { - mux(0, 4, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux sp0_ext_ldo_on_grp_mux = { - .pad_mux_count = array_size(sp0_ext_ldo_on_grp_pad_mux), - .pad_mux_list = sp0_ext_ldo_on_grp_pad_mux, -}; - -static struct atlas7_pad_mux sp0_qspi_grp_pad_mux[] = { - mux(0, 12, 1, n, n, n, n), - mux(0, 13, 1, n, n, n, n), - mux(0, 14, 1, n, n, n, n), - mux(0, 15, 1, n, n, n, n), - mux(0, 16, 1, n, n, n, n), - mux(0, 17, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux sp0_qspi_grp_mux = { - .pad_mux_count = array_size(sp0_qspi_grp_pad_mux), - .pad_mux_list = sp0_qspi_grp_pad_mux, -}; - -static struct atlas7_pad_mux sp1_spi_grp_pad_mux[] = { - mux(1, 19, 1, n, n, n, n), - mux(1, 20, 1, n, n, n, n), - mux(1, 21, 1, n, n, n, n), - mux(1, 18, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux sp1_spi_grp_mux = { - .pad_mux_count = array_size(sp1_spi_grp_pad_mux), - .pad_mux_list = sp1_spi_grp_pad_mux, -}; - -static struct atlas7_pad_mux tpiu_trace_grp_pad_mux[] = { - mux(1, 53, 5, n, n, n, n), - mux(1, 56, 5, n, n, n, n), - mux(1, 57, 5, n, n, n, n), - mux(1, 58, 5, n, n, n, n), - mux(1, 59, 5, n, n, n, n), - mux(1, 60, 5, n, n, n, n), - mux(1, 61, 5, n, n, n, n), - mux(1, 62, 5, n, n, n, n), - mux(1, 63, 5, n, n, n, n), - mux(1, 64, 5, n, n, n, n), - mux(1, 65, 5, n, n, n, n), - mux(1, 66, 5, n, n, n, n), - mux(1, 67, 5, n, n, n, n), - mux(1, 68, 5, n, n, n, n), - mux(1, 69, 5, n, n, n, n), - mux(1, 70, 5, n, n, n, n), - mux(1, 71, 5, n, n, n, n), - mux(1, 72, 5, n, n, n, n), -}; - -static struct atlas7_grp_mux tpiu_trace_grp_mux = { - .pad_mux_count = array_size(tpiu_trace_grp_pad_mux), - .pad_mux_list = tpiu_trace_grp_pad_mux, -}; - -static struct atlas7_pad_mux uart0_grp_pad_mux[] = { - mux(1, 121, 4, n, n, n, n), - mux(1, 120, 4, n, n, n, n), - mux(1, 134, 1, n, n, n, n), - mux(1, 133, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux uart0_grp_mux = { - .pad_mux_count = array_size(uart0_grp_pad_mux), - .pad_mux_list = uart0_grp_pad_mux, -}; - -static struct atlas7_pad_mux uart0_nopause_grp_pad_mux[] = { - mux(1, 134, 1, n, n, n, n), - mux(1, 133, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux uart0_nopause_grp_mux = { - .pad_mux_count = array_size(uart0_nopause_grp_pad_mux), - .pad_mux_list = uart0_nopause_grp_pad_mux, -}; - -static struct atlas7_pad_mux uart1_grp_pad_mux[] = { - mux(1, 136, 1, n, n, n, n), - mux(1, 135, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux uart1_grp_mux = { - .pad_mux_count = array_size(uart1_grp_pad_mux), - .pad_mux_list = uart1_grp_pad_mux, -}; - -static struct atlas7_pad_mux uart2_cts_grp0_pad_mux[] = { - mux(1, 132, 3, 0xa10, 2, 0xa90, 2), -}; - -static struct atlas7_grp_mux uart2_cts_grp0_mux = { - .pad_mux_count = array_size(uart2_cts_grp0_pad_mux), - .pad_mux_list = uart2_cts_grp0_pad_mux, -}; - -static struct atlas7_pad_mux uart2_cts_grp1_pad_mux[] = { - mux(1, 162, 2, 0xa10, 2, 0xa90, 2), -}; - -static struct atlas7_grp_mux uart2_cts_grp1_mux = { - .pad_mux_count = array_size(uart2_cts_grp1_pad_mux), - .pad_mux_list = uart2_cts_grp1_pad_mux, -}; - -static struct atlas7_pad_mux uart2_rts_grp0_pad_mux[] = { - mux(1, 131, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux uart2_rts_grp0_mux = { - .pad_mux_count = array_size(uart2_rts_grp0_pad_mux), - .pad_mux_list = uart2_rts_grp0_pad_mux, -}; - -static struct atlas7_pad_mux uart2_rts_grp1_pad_mux[] = { - mux(1, 161, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux uart2_rts_grp1_mux = { - .pad_mux_count = array_size(uart2_rts_grp1_pad_mux), - .pad_mux_list = uart2_rts_grp1_pad_mux, -}; - -static struct atlas7_pad_mux uart2_rxd_grp0_pad_mux[] = { - mux(0, 11, 2, 0xa10, 5, 0xa90, 5), -}; - -static struct atlas7_grp_mux uart2_rxd_grp0_mux = { - .pad_mux_count = array_size(uart2_rxd_grp0_pad_mux), - .pad_mux_list = uart2_rxd_grp0_pad_mux, -}; - -static struct atlas7_pad_mux uart2_rxd_grp1_pad_mux[] = { - mux(1, 160, 2, 0xa10, 5, 0xa90, 5), -}; - -static struct atlas7_grp_mux uart2_rxd_grp1_mux = { - .pad_mux_count = array_size(uart2_rxd_grp1_pad_mux), - .pad_mux_list = uart2_rxd_grp1_pad_mux, -}; - -static struct atlas7_pad_mux uart2_rxd_grp2_pad_mux[] = { - mux(1, 130, 3, 0xa10, 5, 0xa90, 5), -}; - -static struct atlas7_grp_mux uart2_rxd_grp2_mux = { - .pad_mux_count = array_size(uart2_rxd_grp2_pad_mux), - .pad_mux_list = uart2_rxd_grp2_pad_mux, -}; - -static struct atlas7_pad_mux uart2_txd_grp0_pad_mux[] = { - mux(0, 10, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux uart2_txd_grp0_mux = { - .pad_mux_count = array_size(uart2_txd_grp0_pad_mux), - .pad_mux_list = uart2_txd_grp0_pad_mux, -}; - -static struct atlas7_pad_mux uart2_txd_grp1_pad_mux[] = { - mux(1, 159, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux uart2_txd_grp1_mux = { - .pad_mux_count = array_size(uart2_txd_grp1_pad_mux), - .pad_mux_list = uart2_txd_grp1_pad_mux, -}; - -static struct atlas7_pad_mux uart2_txd_grp2_pad_mux[] = { - mux(1, 129, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux uart2_txd_grp2_mux = { - .pad_mux_count = array_size(uart2_txd_grp2_pad_mux), - .pad_mux_list = uart2_txd_grp2_pad_mux, -}; - -static struct atlas7_pad_mux uart3_cts_grp0_pad_mux[] = { - mux(1, 125, 2, 0xa08, 0, 0xa88, 0), -}; - -static struct atlas7_grp_mux uart3_cts_grp0_mux = { - .pad_mux_count = array_size(uart3_cts_grp0_pad_mux), - .pad_mux_list = uart3_cts_grp0_pad_mux, -}; - -static struct atlas7_pad_mux uart3_cts_grp1_pad_mux[] = { - mux(1, 111, 4, 0xa08, 0, 0xa88, 0), -}; - -static struct atlas7_grp_mux uart3_cts_grp1_mux = { - .pad_mux_count = array_size(uart3_cts_grp1_pad_mux), - .pad_mux_list = uart3_cts_grp1_pad_mux, -}; - -static struct atlas7_pad_mux uart3_cts_grp2_pad_mux[] = { - mux(1, 140, 2, 0xa08, 0, 0xa88, 0), -}; - -static struct atlas7_grp_mux uart3_cts_grp2_mux = { - .pad_mux_count = array_size(uart3_cts_grp2_pad_mux), - .pad_mux_list = uart3_cts_grp2_pad_mux, -}; - -static struct atlas7_pad_mux uart3_rts_grp0_pad_mux[] = { - mux(1, 126, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux uart3_rts_grp0_mux = { - .pad_mux_count = array_size(uart3_rts_grp0_pad_mux), - .pad_mux_list = uart3_rts_grp0_pad_mux, -}; - -static struct atlas7_pad_mux uart3_rts_grp1_pad_mux[] = { - mux(1, 109, 4, n, n, n, n), -}; - -static struct atlas7_grp_mux uart3_rts_grp1_mux = { - .pad_mux_count = array_size(uart3_rts_grp1_pad_mux), - .pad_mux_list = uart3_rts_grp1_pad_mux, -}; - -static struct atlas7_pad_mux uart3_rts_grp2_pad_mux[] = { - mux(1, 139, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux uart3_rts_grp2_mux = { - .pad_mux_count = array_size(uart3_rts_grp2_pad_mux), - .pad_mux_list = uart3_rts_grp2_pad_mux, -}; - -static struct atlas7_pad_mux uart3_rxd_grp0_pad_mux[] = { - mux(1, 138, 1, 0xa00, 5, 0xa80, 5), -}; - -static struct atlas7_grp_mux uart3_rxd_grp0_mux = { - .pad_mux_count = array_size(uart3_rxd_grp0_pad_mux), - .pad_mux_list = uart3_rxd_grp0_pad_mux, -}; - -static struct atlas7_pad_mux uart3_rxd_grp1_pad_mux[] = { - mux(1, 84, 2, 0xa00, 5, 0xa80, 5), -}; - -static struct atlas7_grp_mux uart3_rxd_grp1_mux = { - .pad_mux_count = array_size(uart3_rxd_grp1_pad_mux), - .pad_mux_list = uart3_rxd_grp1_pad_mux, -}; - -static struct atlas7_pad_mux uart3_rxd_grp2_pad_mux[] = { - mux(1, 162, 3, 0xa00, 5, 0xa80, 5), -}; - -static struct atlas7_grp_mux uart3_rxd_grp2_mux = { - .pad_mux_count = array_size(uart3_rxd_grp2_pad_mux), - .pad_mux_list = uart3_rxd_grp2_pad_mux, -}; - -static struct atlas7_pad_mux uart3_txd_grp0_pad_mux[] = { - mux(1, 137, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux uart3_txd_grp0_mux = { - .pad_mux_count = array_size(uart3_txd_grp0_pad_mux), - .pad_mux_list = uart3_txd_grp0_pad_mux, -}; - -static struct atlas7_pad_mux uart3_txd_grp1_pad_mux[] = { - mux(1, 83, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux uart3_txd_grp1_mux = { - .pad_mux_count = array_size(uart3_txd_grp1_pad_mux), - .pad_mux_list = uart3_txd_grp1_pad_mux, -}; - -static struct atlas7_pad_mux uart3_txd_grp2_pad_mux[] = { - mux(1, 161, 3, n, n, n, n), -}; - -static struct atlas7_grp_mux uart3_txd_grp2_mux = { - .pad_mux_count = array_size(uart3_txd_grp2_pad_mux), - .pad_mux_list = uart3_txd_grp2_pad_mux, -}; - -static struct atlas7_pad_mux uart4_basic_grp_pad_mux[] = { - mux(1, 140, 1, n, n, n, n), - mux(1, 139, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux uart4_basic_grp_mux = { - .pad_mux_count = array_size(uart4_basic_grp_pad_mux), - .pad_mux_list = uart4_basic_grp_pad_mux, -}; - -static struct atlas7_pad_mux uart4_cts_grp0_pad_mux[] = { - mux(1, 122, 4, 0xa08, 1, 0xa88, 1), -}; - -static struct atlas7_grp_mux uart4_cts_grp0_mux = { - .pad_mux_count = array_size(uart4_cts_grp0_pad_mux), - .pad_mux_list = uart4_cts_grp0_pad_mux, -}; - -static struct atlas7_pad_mux uart4_cts_grp1_pad_mux[] = { - mux(1, 100, 4, 0xa08, 1, 0xa88, 1), -}; - -static struct atlas7_grp_mux uart4_cts_grp1_mux = { - .pad_mux_count = array_size(uart4_cts_grp1_pad_mux), - .pad_mux_list = uart4_cts_grp1_pad_mux, -}; - -static struct atlas7_pad_mux uart4_cts_grp2_pad_mux[] = { - mux(1, 117, 2, 0xa08, 1, 0xa88, 1), -}; - -static struct atlas7_grp_mux uart4_cts_grp2_mux = { - .pad_mux_count = array_size(uart4_cts_grp2_pad_mux), - .pad_mux_list = uart4_cts_grp2_pad_mux, -}; - -static struct atlas7_pad_mux uart4_rts_grp0_pad_mux[] = { - mux(1, 123, 4, n, n, n, n), -}; - -static struct atlas7_grp_mux uart4_rts_grp0_mux = { - .pad_mux_count = array_size(uart4_rts_grp0_pad_mux), - .pad_mux_list = uart4_rts_grp0_pad_mux, -}; - -static struct atlas7_pad_mux uart4_rts_grp1_pad_mux[] = { - mux(1, 99, 4, n, n, n, n), -}; - -static struct atlas7_grp_mux uart4_rts_grp1_mux = { - .pad_mux_count = array_size(uart4_rts_grp1_pad_mux), - .pad_mux_list = uart4_rts_grp1_pad_mux, -}; - -static struct atlas7_pad_mux uart4_rts_grp2_pad_mux[] = { - mux(1, 116, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux uart4_rts_grp2_mux = { - .pad_mux_count = array_size(uart4_rts_grp2_pad_mux), - .pad_mux_list = uart4_rts_grp2_pad_mux, -}; - -static struct atlas7_pad_mux usb0_drvvbus_grp0_pad_mux[] = { - mux(1, 51, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux usb0_drvvbus_grp0_mux = { - .pad_mux_count = array_size(usb0_drvvbus_grp0_pad_mux), - .pad_mux_list = usb0_drvvbus_grp0_pad_mux, -}; - -static struct atlas7_pad_mux usb0_drvvbus_grp1_pad_mux[] = { - mux(1, 162, 7, n, n, n, n), -}; - -static struct atlas7_grp_mux usb0_drvvbus_grp1_mux = { - .pad_mux_count = array_size(usb0_drvvbus_grp1_pad_mux), - .pad_mux_list = usb0_drvvbus_grp1_pad_mux, -}; - -static struct atlas7_pad_mux usb1_drvvbus_grp0_pad_mux[] = { - mux(1, 134, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux usb1_drvvbus_grp0_mux = { - .pad_mux_count = array_size(usb1_drvvbus_grp0_pad_mux), - .pad_mux_list = usb1_drvvbus_grp0_pad_mux, -}; - -static struct atlas7_pad_mux usb1_drvvbus_grp1_pad_mux[] = { - mux(1, 163, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux usb1_drvvbus_grp1_mux = { - .pad_mux_count = array_size(usb1_drvvbus_grp1_pad_mux), - .pad_mux_list = usb1_drvvbus_grp1_pad_mux, -}; - -static struct atlas7_pad_mux visbus_dout_grp_pad_mux[] = { - mux(1, 57, 6, n, n, n, n), - mux(1, 58, 6, n, n, n, n), - mux(1, 59, 6, n, n, n, n), - mux(1, 60, 6, n, n, n, n), - mux(1, 61, 6, n, n, n, n), - mux(1, 62, 6, n, n, n, n), - mux(1, 63, 6, n, n, n, n), - mux(1, 64, 6, n, n, n, n), - mux(1, 65, 6, n, n, n, n), - mux(1, 66, 6, n, n, n, n), - mux(1, 67, 6, n, n, n, n), - mux(1, 68, 6, n, n, n, n), - mux(1, 69, 6, n, n, n, n), - mux(1, 70, 6, n, n, n, n), - mux(1, 71, 6, n, n, n, n), - mux(1, 72, 6, n, n, n, n), - mux(1, 53, 6, n, n, n, n), - mux(1, 54, 6, n, n, n, n), - mux(1, 55, 6, n, n, n, n), - mux(1, 56, 6, n, n, n, n), - mux(1, 85, 6, n, n, n, n), - mux(1, 86, 6, n, n, n, n), - mux(1, 87, 6, n, n, n, n), - mux(1, 88, 6, n, n, n, n), - mux(1, 89, 6, n, n, n, n), - mux(1, 90, 6, n, n, n, n), - mux(1, 91, 6, n, n, n, n), - mux(1, 92, 6, n, n, n, n), - mux(1, 93, 6, n, n, n, n), - mux(1, 94, 6, n, n, n, n), - mux(1, 95, 6, n, n, n, n), - mux(1, 96, 6, n, n, n, n), -}; - -static struct atlas7_grp_mux visbus_dout_grp_mux = { - .pad_mux_count = array_size(visbus_dout_grp_pad_mux), - .pad_mux_list = visbus_dout_grp_pad_mux, -}; - -static struct atlas7_pad_mux vi_vip1_grp_pad_mux[] = { - mux(1, 74, 1, n, n, n, n), - mux(1, 75, 1, n, n, n, n), - mux(1, 76, 1, n, n, n, n), - mux(1, 77, 1, n, n, n, n), - mux(1, 78, 1, n, n, n, n), - mux(1, 79, 1, n, n, n, n), - mux(1, 80, 1, n, n, n, n), - mux(1, 81, 1, n, n, n, n), - mux(1, 82, 1, n, n, n, n), - mux(1, 83, 1, n, n, n, n), - mux(1, 84, 1, n, n, n, n), - mux(1, 103, 2, n, n, n, n), - mux(1, 104, 2, n, n, n, n), - mux(1, 105, 2, n, n, n, n), - mux(1, 106, 2, n, n, n, n), - mux(1, 107, 2, n, n, n, n), - mux(1, 102, 2, n, n, n, n), - mux(1, 97, 2, n, n, n, n), - mux(1, 98, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux vi_vip1_grp_mux = { - .pad_mux_count = array_size(vi_vip1_grp_pad_mux), - .pad_mux_list = vi_vip1_grp_pad_mux, -}; - -static struct atlas7_pad_mux vi_vip1_ext_grp_pad_mux[] = { - mux(1, 74, 1, n, n, n, n), - mux(1, 75, 1, n, n, n, n), - mux(1, 76, 1, n, n, n, n), - mux(1, 77, 1, n, n, n, n), - mux(1, 78, 1, n, n, n, n), - mux(1, 79, 1, n, n, n, n), - mux(1, 80, 1, n, n, n, n), - mux(1, 81, 1, n, n, n, n), - mux(1, 82, 1, n, n, n, n), - mux(1, 83, 1, n, n, n, n), - mux(1, 84, 1, n, n, n, n), - mux(1, 108, 2, n, n, n, n), - mux(1, 103, 2, n, n, n, n), - mux(1, 104, 2, n, n, n, n), - mux(1, 105, 2, n, n, n, n), - mux(1, 106, 2, n, n, n, n), - mux(1, 107, 2, n, n, n, n), - mux(1, 102, 2, n, n, n, n), - mux(1, 97, 2, n, n, n, n), - mux(1, 98, 2, n, n, n, n), - mux(1, 99, 2, n, n, n, n), - mux(1, 100, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux vi_vip1_ext_grp_mux = { - .pad_mux_count = array_size(vi_vip1_ext_grp_pad_mux), - .pad_mux_list = vi_vip1_ext_grp_pad_mux, -}; - -static struct atlas7_pad_mux vi_vip1_low8bit_grp_pad_mux[] = { - mux(1, 74, 1, n, n, n, n), - mux(1, 75, 1, n, n, n, n), - mux(1, 76, 1, n, n, n, n), - mux(1, 77, 1, n, n, n, n), - mux(1, 78, 1, n, n, n, n), - mux(1, 79, 1, n, n, n, n), - mux(1, 80, 1, n, n, n, n), - mux(1, 81, 1, n, n, n, n), - mux(1, 82, 1, n, n, n, n), - mux(1, 83, 1, n, n, n, n), - mux(1, 84, 1, n, n, n, n), -}; - -static struct atlas7_grp_mux vi_vip1_low8bit_grp_mux = { - .pad_mux_count = array_size(vi_vip1_low8bit_grp_pad_mux), - .pad_mux_list = vi_vip1_low8bit_grp_pad_mux, -}; - -static struct atlas7_pad_mux vi_vip1_high8bit_grp_pad_mux[] = { - mux(1, 82, 1, n, n, n, n), - mux(1, 83, 1, n, n, n, n), - mux(1, 84, 1, n, n, n, n), - mux(1, 103, 2, n, n, n, n), - mux(1, 104, 2, n, n, n, n), - mux(1, 105, 2, n, n, n, n), - mux(1, 106, 2, n, n, n, n), - mux(1, 107, 2, n, n, n, n), - mux(1, 102, 2, n, n, n, n), - mux(1, 97, 2, n, n, n, n), - mux(1, 98, 2, n, n, n, n), -}; - -static struct atlas7_grp_mux vi_vip1_high8bit_grp_mux = { - .pad_mux_count = array_size(vi_vip1_high8bit_grp_pad_mux), - .pad_mux_list = vi_vip1_high8bit_grp_pad_mux, -}; - -static struct atlas7_pmx_func atlas7_pmx_functions[] = { - function("gnss_gpio", gnss_gpio_grp, &gnss_gpio_grp_mux), - function("lcd_vip_gpio", lcd_vip_gpio_grp, &lcd_vip_gpio_grp_mux), - function("sdio_i2s_gpio", sdio_i2s_gpio_grp, &sdio_i2s_gpio_grp_mux), - function("sp_rgmii_gpio", sp_rgmii_gpio_grp, &sp_rgmii_gpio_grp_mux), - function("lvds_gpio", lvds_gpio_grp, &lvds_gpio_grp_mux), - function("jtag_uart_nand_gpio", - jtag_uart_nand_gpio_grp, - &jtag_uart_nand_gpio_grp_mux), - function("rtc_gpio", rtc_gpio_grp, &rtc_gpio_grp_mux), - function("audio_ac97", audio_ac97_grp, &audio_ac97_grp_mux), - function("audio_digmic_m0", - audio_digmic_grp0, - &audio_digmic_grp0_mux), - function("audio_digmic_m1", - audio_digmic_grp1, - &audio_digmic_grp1_mux), - function("audio_digmic_m2", - audio_digmic_grp2, - &audio_digmic_grp2_mux), - function("audio_func_dbg", - audio_func_dbg_grp, - &audio_func_dbg_grp_mux), - function("audio_i2s", audio_i2s_grp, &audio_i2s_grp_mux), - function("audio_i2s_2ch", audio_i2s_2ch_grp, &audio_i2s_2ch_grp_mux), - function("audio_i2s_extclk", - audio_i2s_extclk_grp, - &audio_i2s_extclk_grp_mux), - function("audio_spdif_out_m0", - audio_spdif_out_grp0, - &audio_spdif_out_grp0_mux), - function("audio_spdif_out_m1", - audio_spdif_out_grp1, - &audio_spdif_out_grp1_mux), - function("audio_spdif_out_m2", - audio_spdif_out_grp2, - &audio_spdif_out_grp2_mux), - function("audio_uart0_basic", - audio_uart0_basic_grp, - &audio_uart0_basic_grp_mux), - function("audio_uart0_urfs_m0", - audio_uart0_urfs_grp0, - &audio_uart0_urfs_grp0_mux), - function("audio_uart0_urfs_m1", - audio_uart0_urfs_grp1, - &audio_uart0_urfs_grp1_mux), - function("audio_uart0_urfs_m2", - audio_uart0_urfs_grp2, - &audio_uart0_urfs_grp2_mux), - function("audio_uart0_urfs_m3", - audio_uart0_urfs_grp3, - &audio_uart0_urfs_grp3_mux), - function("audio_uart1_basic", - audio_uart1_basic_grp, - &audio_uart1_basic_grp_mux), - function("audio_uart1_urfs_m0", - audio_uart1_urfs_grp0, - &audio_uart1_urfs_grp0_mux), - function("audio_uart1_urfs_m1", - audio_uart1_urfs_grp1, - &audio_uart1_urfs_grp1_mux), - function("audio_uart1_urfs_m2", - audio_uart1_urfs_grp2, - &audio_uart1_urfs_grp2_mux), - function("audio_uart2_urfs_m0", - audio_uart2_urfs_grp0, - &audio_uart2_urfs_grp0_mux), - function("audio_uart2_urfs_m1", - audio_uart2_urfs_grp1, - &audio_uart2_urfs_grp1_mux), - function("audio_uart2_urfs_m2", - audio_uart2_urfs_grp2, - &audio_uart2_urfs_grp2_mux), - function("audio_uart2_urxd_m0", - audio_uart2_urxd_grp0, - &audio_uart2_urxd_grp0_mux), - function("audio_uart2_urxd_m1", - audio_uart2_urxd_grp1, - &audio_uart2_urxd_grp1_mux), - function("audio_uart2_urxd_m2", - audio_uart2_urxd_grp2, - &audio_uart2_urxd_grp2_mux), - function("audio_uart2_usclk_m0", - audio_uart2_usclk_grp0, - &audio_uart2_usclk_grp0_mux), - function("audio_uart2_usclk_m1", - audio_uart2_usclk_grp1, - &audio_uart2_usclk_grp1_mux), - function("audio_uart2_usclk_m2", - audio_uart2_usclk_grp2, - &audio_uart2_usclk_grp2_mux), - function("audio_uart2_utfs_m0", - audio_uart2_utfs_grp0, - &audio_uart2_utfs_grp0_mux), - function("audio_uart2_utfs_m1", - audio_uart2_utfs_grp1, - &audio_uart2_utfs_grp1_mux), - function("audio_uart2_utfs_m2", - audio_uart2_utfs_grp2, - &audio_uart2_utfs_grp2_mux), - function("audio_uart2_utxd_m0", - audio_uart2_utxd_grp0, - &audio_uart2_utxd_grp0_mux), - function("audio_uart2_utxd_m1", - audio_uart2_utxd_grp1, - &audio_uart2_utxd_grp1_mux), - function("audio_uart2_utxd_m2", - audio_uart2_utxd_grp2, - &audio_uart2_utxd_grp2_mux), - function("c_can_trnsvr_en_m0", - c_can_trnsvr_en_grp0, - &c_can_trnsvr_en_grp0_mux), - function("c_can_trnsvr_en_m1", - c_can_trnsvr_en_grp1, - &c_can_trnsvr_en_grp1_mux), - function("c_can_trnsvr_intr", - c_can_trnsvr_intr_grp, - &c_can_trnsvr_intr_grp_mux), - function("c_can_trnsvr_stb_n", - c_can_trnsvr_stb_n_grp, - &c_can_trnsvr_stb_n_grp_mux), - function("c0_can_rxd_trnsv0", - c0_can_rxd_trnsv0_grp, - &c0_can_rxd_trnsv0_grp_mux), - function("c0_can_rxd_trnsv1", - c0_can_rxd_trnsv1_grp, - &c0_can_rxd_trnsv1_grp_mux), - function("c0_can_txd_trnsv0", - c0_can_txd_trnsv0_grp, - &c0_can_txd_trnsv0_grp_mux), - function("c0_can_txd_trnsv1", - c0_can_txd_trnsv1_grp, - &c0_can_txd_trnsv1_grp_mux), - function("c1_can_rxd_m0", c1_can_rxd_grp0, &c1_can_rxd_grp0_mux), - function("c1_can_rxd_m1", c1_can_rxd_grp1, &c1_can_rxd_grp1_mux), - function("c1_can_rxd_m2", c1_can_rxd_grp2, &c1_can_rxd_grp2_mux), - function("c1_can_rxd_m3", c1_can_rxd_grp3, &c1_can_rxd_grp3_mux), - function("c1_can_txd_m0", c1_can_txd_grp0, &c1_can_txd_grp0_mux), - function("c1_can_txd_m1", c1_can_txd_grp1, &c1_can_txd_grp1_mux), - function("c1_can_txd_m2", c1_can_txd_grp2, &c1_can_txd_grp2_mux), - function("c1_can_txd_m3", c1_can_txd_grp3, &c1_can_txd_grp3_mux), - function("ca_audio_lpc", ca_audio_lpc_grp, &ca_audio_lpc_grp_mux), - function("ca_bt_lpc", ca_bt_lpc_grp, &ca_bt_lpc_grp_mux), - function("ca_coex", ca_coex_grp, &ca_coex_grp_mux), - function("ca_curator_lpc", - ca_curator_lpc_grp, - &ca_curator_lpc_grp_mux), - function("ca_pcm_debug", ca_pcm_debug_grp, &ca_pcm_debug_grp_mux), - function("ca_pio", ca_pio_grp, &ca_pio_grp_mux), - function("ca_sdio_debug", ca_sdio_debug_grp, &ca_sdio_debug_grp_mux), - function("ca_spi", ca_spi_grp, &ca_spi_grp_mux), - function("ca_trb", ca_trb_grp, &ca_trb_grp_mux), - function("ca_uart_debug", ca_uart_debug_grp, &ca_uart_debug_grp_mux), - function("clkc_m0", clkc_grp0, &clkc_grp0_mux), - function("clkc_m1", clkc_grp1, &clkc_grp1_mux), - function("gn_gnss_i2c", gn_gnss_i2c_grp, &gn_gnss_i2c_grp_mux), - function("gn_gnss_uart_nopause", - gn_gnss_uart_nopause_grp, - &gn_gnss_uart_nopause_grp_mux), - function("gn_gnss_uart", gn_gnss_uart_grp, &gn_gnss_uart_grp_mux), - function("gn_trg_spi_m0", gn_trg_spi_grp0, &gn_trg_spi_grp0_mux), - function("gn_trg_spi_m1", gn_trg_spi_grp1, &gn_trg_spi_grp1_mux), - function("cvbs_dbg", cvbs_dbg_grp, &cvbs_dbg_grp_mux), - function("cvbs_dbg_test_m0", - cvbs_dbg_test_grp0, - &cvbs_dbg_test_grp0_mux), - function("cvbs_dbg_test_m1", - cvbs_dbg_test_grp1, - &cvbs_dbg_test_grp1_mux), - function("cvbs_dbg_test_m2", - cvbs_dbg_test_grp2, - &cvbs_dbg_test_grp2_mux), - function("cvbs_dbg_test_m3", - cvbs_dbg_test_grp3, - &cvbs_dbg_test_grp3_mux), - function("cvbs_dbg_test_m4", - cvbs_dbg_test_grp4, - &cvbs_dbg_test_grp4_mux), - function("cvbs_dbg_test_m5", - cvbs_dbg_test_grp5, - &cvbs_dbg_test_grp5_mux), - function("cvbs_dbg_test_m6", - cvbs_dbg_test_grp6, - &cvbs_dbg_test_grp6_mux), - function("cvbs_dbg_test_m7", - cvbs_dbg_test_grp7, - &cvbs_dbg_test_grp7_mux), - function("cvbs_dbg_test_m8", - cvbs_dbg_test_grp8, - &cvbs_dbg_test_grp8_mux), - function("cvbs_dbg_test_m9", - cvbs_dbg_test_grp9, - &cvbs_dbg_test_grp9_mux), - function("cvbs_dbg_test_m10", - cvbs_dbg_test_grp10, - &cvbs_dbg_test_grp10_mux), - function("cvbs_dbg_test_m11", - cvbs_dbg_test_grp11, - &cvbs_dbg_test_grp11_mux), - function("cvbs_dbg_test_m12", - cvbs_dbg_test_grp12, - &cvbs_dbg_test_grp12_mux), - function("cvbs_dbg_test_m13", - cvbs_dbg_test_grp13, - &cvbs_dbg_test_grp13_mux), - function("cvbs_dbg_test_m14", - cvbs_dbg_test_grp14, - &cvbs_dbg_test_grp14_mux), - function("cvbs_dbg_test_m15", - cvbs_dbg_test_grp15, - &cvbs_dbg_test_grp15_mux), - function("gn_gnss_power", gn_gnss_power_grp, &gn_gnss_power_grp_mux), - function("gn_gnss_sw_status", - gn_gnss_sw_status_grp, - &gn_gnss_sw_status_grp_mux), - function("gn_gnss_eclk", gn_gnss_eclk_grp, &gn_gnss_eclk_grp_mux), - function("gn_gnss_irq1_m0", - gn_gnss_irq1_grp0, - &gn_gnss_irq1_grp0_mux), - function("gn_gnss_irq2_m0", - gn_gnss_irq2_grp0, - &gn_gnss_irq2_grp0_mux), - function("gn_gnss_tm", gn_gnss_tm_grp, &gn_gnss_tm_grp_mux), - function("gn_gnss_tsync", gn_gnss_tsync_grp, &gn_gnss_tsync_grp_mux), - function("gn_io_gnsssys_sw_cfg", - gn_io_gnsssys_sw_cfg_grp, - &gn_io_gnsssys_sw_cfg_grp_mux), - function("gn_trg_m0", gn_trg_grp0, &gn_trg_grp0_mux), - function("gn_trg_m1", gn_trg_grp1, &gn_trg_grp1_mux), - function("gn_trg_shutdown_m0", - gn_trg_shutdown_grp0, - &gn_trg_shutdown_grp0_mux), - function("gn_trg_shutdown_m1", - gn_trg_shutdown_grp1, - &gn_trg_shutdown_grp1_mux), - function("gn_trg_shutdown_m2", - gn_trg_shutdown_grp2, - &gn_trg_shutdown_grp2_mux), - function("gn_trg_shutdown_m3", - gn_trg_shutdown_grp3, - &gn_trg_shutdown_grp3_mux), - function("i2c0", i2c0_grp, &i2c0_grp_mux), - function("i2c1", i2c1_grp, &i2c1_grp_mux), - function("i2s0", i2s0_grp, &i2s0_grp_mux), - function("i2s1_basic", i2s1_basic_grp, &i2s1_basic_grp_mux), - function("i2s1_rxd0_m0", i2s1_rxd0_grp0, &i2s1_rxd0_grp0_mux), - function("i2s1_rxd0_m1", i2s1_rxd0_grp1, &i2s1_rxd0_grp1_mux), - function("i2s1_rxd0_m2", i2s1_rxd0_grp2, &i2s1_rxd0_grp2_mux), - function("i2s1_rxd0_m3", i2s1_rxd0_grp3, &i2s1_rxd0_grp3_mux), - function("i2s1_rxd0_m4", i2s1_rxd0_grp4, &i2s1_rxd0_grp4_mux), - function("i2s1_rxd1_m0", i2s1_rxd1_grp0, &i2s1_rxd1_grp0_mux), - function("i2s1_rxd1_m1", i2s1_rxd1_grp1, &i2s1_rxd1_grp1_mux), - function("i2s1_rxd1_m2", i2s1_rxd1_grp2, &i2s1_rxd1_grp2_mux), - function("i2s1_rxd1_m3", i2s1_rxd1_grp3, &i2s1_rxd1_grp3_mux), - function("i2s1_rxd1_m4", i2s1_rxd1_grp4, &i2s1_rxd1_grp4_mux), - function("jtag_jt_dbg_nsrst", - jtag_jt_dbg_nsrst_grp, - &jtag_jt_dbg_nsrst_grp_mux), - function("jtag_ntrst_m0", jtag_ntrst_grp0, &jtag_ntrst_grp0_mux), - function("jtag_ntrst_m1", jtag_ntrst_grp1, &jtag_ntrst_grp1_mux), - function("jtag_swdiotms_m0", - jtag_swdiotms_grp0, - &jtag_swdiotms_grp0_mux), - function("jtag_swdiotms_m1", - jtag_swdiotms_grp1, - &jtag_swdiotms_grp1_mux), - function("jtag_tck_m0", jtag_tck_grp0, &jtag_tck_grp0_mux), - function("jtag_tck_m1", jtag_tck_grp1, &jtag_tck_grp1_mux), - function("jtag_tdi_m0", jtag_tdi_grp0, &jtag_tdi_grp0_mux), - function("jtag_tdi_m1", jtag_tdi_grp1, &jtag_tdi_grp1_mux), - function("jtag_tdo_m0", jtag_tdo_grp0, &jtag_tdo_grp0_mux), - function("jtag_tdo_m1", jtag_tdo_grp1, &jtag_tdo_grp1_mux), - function("ks_kas_spi_m0", ks_kas_spi_grp0, &ks_kas_spi_grp0_mux), - function("ld_ldd", ld_ldd_grp, &ld_ldd_grp_mux), - function("ld_ldd_16bit", ld_ldd_16bit_grp, &ld_ldd_16bit_grp_mux), - function("ld_ldd_fck", ld_ldd_fck_grp, &ld_ldd_fck_grp_mux), - function("ld_ldd_lck", ld_ldd_lck_grp, &ld_ldd_lck_grp_mux), - function("lr_lcdrom", lr_lcdrom_grp, &lr_lcdrom_grp_mux), - function("lvds_analog", lvds_analog_grp, &lvds_analog_grp_mux), - function("nd_df_basic", nd_df_basic_grp, &nd_df_basic_grp_mux), - function("nd_df_wp", nd_df_wp_grp, &nd_df_wp_grp_mux), - function("nd_df_cs", nd_df_cs_grp, &nd_df_cs_grp_mux), - function("ps", ps_grp, &ps_grp_mux), - function("ps_no_dir", ps_no_dir_grp, &ps_no_dir_grp_mux), - function("pwc_core_on", pwc_core_on_grp, &pwc_core_on_grp_mux), - function("pwc_ext_on", pwc_ext_on_grp, &pwc_ext_on_grp_mux), - function("pwc_gpio3_clk", pwc_gpio3_clk_grp, &pwc_gpio3_clk_grp_mux), - function("pwc_io_on", pwc_io_on_grp, &pwc_io_on_grp_mux), - function("pwc_lowbatt_b_m0", - pwc_lowbatt_b_grp0, - &pwc_lowbatt_b_grp0_mux), - function("pwc_mem_on", pwc_mem_on_grp, &pwc_mem_on_grp_mux), - function("pwc_on_key_b_m0", - pwc_on_key_b_grp0, - &pwc_on_key_b_grp0_mux), - function("pwc_wakeup_src0", - pwc_wakeup_src0_grp, - &pwc_wakeup_src0_grp_mux), - function("pwc_wakeup_src1", - pwc_wakeup_src1_grp, - &pwc_wakeup_src1_grp_mux), - function("pwc_wakeup_src2", - pwc_wakeup_src2_grp, - &pwc_wakeup_src2_grp_mux), - function("pwc_wakeup_src3", - pwc_wakeup_src3_grp, - &pwc_wakeup_src3_grp_mux), - function("pw_cko0_m0", pw_cko0_grp0, &pw_cko0_grp0_mux), - function("pw_cko0_m1", pw_cko0_grp1, &pw_cko0_grp1_mux), - function("pw_cko0_m2", pw_cko0_grp2, &pw_cko0_grp2_mux), - function("pw_cko0_m3", pw_cko0_grp3, &pw_cko0_grp3_mux), - function("pw_cko1_m0", pw_cko1_grp0, &pw_cko1_grp0_mux), - function("pw_cko1_m1", pw_cko1_grp1, &pw_cko1_grp1_mux), - function("pw_cko1_m2", pw_cko1_grp2, &pw_cko1_grp2_mux), - function("pw_i2s01_clk_m0", - pw_i2s01_clk_grp0, - &pw_i2s01_clk_grp0_mux), - function("pw_i2s01_clk_m1", - pw_i2s01_clk_grp1, - &pw_i2s01_clk_grp1_mux), - function("pw_i2s01_clk_m2", - pw_i2s01_clk_grp2, - &pw_i2s01_clk_grp2_mux), - function("pw_pwm0_m0", pw_pwm0_grp0, &pw_pwm0_grp0_mux), - function("pw_pwm0_m1", pw_pwm0_grp1, &pw_pwm0_grp1_mux), - function("pw_pwm1_m0", pw_pwm1_grp0, &pw_pwm1_grp0_mux), - function("pw_pwm1_m1", pw_pwm1_grp1, &pw_pwm1_grp1_mux), - function("pw_pwm1_m2", pw_pwm1_grp2, &pw_pwm1_grp2_mux), - function("pw_pwm2_m0", pw_pwm2_grp0, &pw_pwm2_grp0_mux), - function("pw_pwm2_m1", pw_pwm2_grp1, &pw_pwm2_grp1_mux), - function("pw_pwm2_m2", pw_pwm2_grp2, &pw_pwm2_grp2_mux), - function("pw_pwm3_m0", pw_pwm3_grp0, &pw_pwm3_grp0_mux), - function("pw_pwm3_m1", pw_pwm3_grp1, &pw_pwm3_grp1_mux), - function("pw_pwm_cpu_vol_m0", - pw_pwm_cpu_vol_grp0, - &pw_pwm_cpu_vol_grp0_mux), - function("pw_pwm_cpu_vol_m1", - pw_pwm_cpu_vol_grp1, - &pw_pwm_cpu_vol_grp1_mux), - function("pw_pwm_cpu_vol_m2", - pw_pwm_cpu_vol_grp2, - &pw_pwm_cpu_vol_grp2_mux), - function("pw_backlight_m0", - pw_backlight_grp0, - &pw_backlight_grp0_mux), - function("pw_backlight_m1", - pw_backlight_grp1, - &pw_backlight_grp1_mux), - function("rg_eth_mac", rg_eth_mac_grp, &rg_eth_mac_grp_mux), - function("rg_gmac_phy_intr_n", - rg_gmac_phy_intr_n_grp, - &rg_gmac_phy_intr_n_grp_mux), - function("rg_rgmii_mac", rg_rgmii_mac_grp, &rg_rgmii_mac_grp_mux), - function("rg_rgmii_phy_ref_clk_m0", - rg_rgmii_phy_ref_clk_grp0, - &rg_rgmii_phy_ref_clk_grp0_mux), - function("rg_rgmii_phy_ref_clk_m1", - rg_rgmii_phy_ref_clk_grp1, - &rg_rgmii_phy_ref_clk_grp1_mux), - function("sd0", sd0_grp, &sd0_grp_mux), - function("sd0_4bit", sd0_4bit_grp, &sd0_4bit_grp_mux), - function("sd1", sd1_grp, &sd1_grp_mux), - function("sd1_4bit_m0", sd1_4bit_grp0, &sd1_4bit_grp0_mux), - function("sd1_4bit_m1", sd1_4bit_grp1, &sd1_4bit_grp1_mux), - function("sd2_basic", sd2_basic_grp, &sd2_basic_grp_mux), - function("sd2_cdb_m0", sd2_cdb_grp0, &sd2_cdb_grp0_mux), - function("sd2_cdb_m1", sd2_cdb_grp1, &sd2_cdb_grp1_mux), - function("sd2_wpb_m0", sd2_wpb_grp0, &sd2_wpb_grp0_mux), - function("sd2_wpb_m1", sd2_wpb_grp1, &sd2_wpb_grp1_mux), - function("sd3", sd3_9_grp, &sd3_9_grp_mux), - function("sd5", sd5_grp, &sd5_grp_mux), - function("sd6_m0", sd6_grp0, &sd6_grp0_mux), - function("sd6_m1", sd6_grp1, &sd6_grp1_mux), - function("sd9", sd3_9_grp, &sd3_9_grp_mux), - function("sp0_ext_ldo_on", - sp0_ext_ldo_on_grp, - &sp0_ext_ldo_on_grp_mux), - function("sp0_qspi", sp0_qspi_grp, &sp0_qspi_grp_mux), - function("sp1_spi", sp1_spi_grp, &sp1_spi_grp_mux), - function("tpiu_trace", tpiu_trace_grp, &tpiu_trace_grp_mux), - function("uart0", uart0_grp, &uart0_grp_mux), - function("uart0_nopause", uart0_nopause_grp, &uart0_nopause_grp_mux), - function("uart1", uart1_grp, &uart1_grp_mux), - function("uart2_cts_m0", uart2_cts_grp0, &uart2_cts_grp0_mux), - function("uart2_cts_m1", uart2_cts_grp1, &uart2_cts_grp1_mux), - function("uart2_rts_m0", uart2_rts_grp0, &uart2_rts_grp0_mux), - function("uart2_rts_m1", uart2_rts_grp1, &uart2_rts_grp1_mux), - function("uart2_rxd_m0", uart2_rxd_grp0, &uart2_rxd_grp0_mux), - function("uart2_rxd_m1", uart2_rxd_grp1, &uart2_rxd_grp1_mux), - function("uart2_rxd_m2", uart2_rxd_grp2, &uart2_rxd_grp2_mux), - function("uart2_txd_m0", uart2_txd_grp0, &uart2_txd_grp0_mux), - function("uart2_txd_m1", uart2_txd_grp1, &uart2_txd_grp1_mux), - function("uart2_txd_m2", uart2_txd_grp2, &uart2_txd_grp2_mux), - function("uart3_cts_m0", uart3_cts_grp0, &uart3_cts_grp0_mux), - function("uart3_cts_m1", uart3_cts_grp1, &uart3_cts_grp1_mux), - function("uart3_cts_m2", uart3_cts_grp2, &uart3_cts_grp2_mux), - function("uart3_rts_m0", uart3_rts_grp0, &uart3_rts_grp0_mux), - function("uart3_rts_m1", uart3_rts_grp1, &uart3_rts_grp1_mux), - function("uart3_rts_m2", uart3_rts_grp2, &uart3_rts_grp2_mux), - function("uart3_rxd_m0", uart3_rxd_grp0, &uart3_rxd_grp0_mux), - function("uart3_rxd_m1", uart3_rxd_grp1, &uart3_rxd_grp1_mux), - function("uart3_rxd_m2", uart3_rxd_grp2, &uart3_rxd_grp2_mux), - function("uart3_txd_m0", uart3_txd_grp0, &uart3_txd_grp0_mux), - function("uart3_txd_m1", uart3_txd_grp1, &uart3_txd_grp1_mux), - function("uart3_txd_m2", uart3_txd_grp2, &uart3_txd_grp2_mux), - function("uart4_basic", uart4_basic_grp, &uart4_basic_grp_mux), - function("uart4_cts_m0", uart4_cts_grp0, &uart4_cts_grp0_mux), - function("uart4_cts_m1", uart4_cts_grp1, &uart4_cts_grp1_mux), - function("uart4_cts_m2", uart4_cts_grp2, &uart4_cts_grp2_mux), - function("uart4_rts_m0", uart4_rts_grp0, &uart4_rts_grp0_mux), - function("uart4_rts_m1", uart4_rts_grp1, &uart4_rts_grp1_mux), - function("uart4_rts_m2", uart4_rts_grp2, &uart4_rts_grp2_mux), - function("usb0_drvvbus_m0", - usb0_drvvbus_grp0, - &usb0_drvvbus_grp0_mux), - function("usb0_drvvbus_m1", - usb0_drvvbus_grp1, - &usb0_drvvbus_grp1_mux), - function("usb1_drvvbus_m0", - usb1_drvvbus_grp0, - &usb1_drvvbus_grp0_mux), - function("usb1_drvvbus_m1", - usb1_drvvbus_grp1, - &usb1_drvvbus_grp1_mux), - function("visbus_dout", visbus_dout_grp, &visbus_dout_grp_mux), - function("vi_vip1", vi_vip1_grp, &vi_vip1_grp_mux), - function("vi_vip1_ext", vi_vip1_ext_grp, &vi_vip1_ext_grp_mux), - function("vi_vip1_low8bit", - vi_vip1_low8bit_grp, - &vi_vip1_low8bit_grp_mux), - function("vi_vip1_high8bit", - vi_vip1_high8bit_grp, - &vi_vip1_high8bit_grp_mux), -}; - -static struct atlas7_pinctrl_data atlas7_ioc_data = { - .pads = (struct pinctrl_pin_desc *)atlas7_ioc_pads, - .pads_cnt = array_size(atlas7_ioc_pads), - .grps = (struct atlas7_pin_group *)altas7_pin_groups, - .grps_cnt = array_size(altas7_pin_groups), - .funcs = (struct atlas7_pmx_func *)atlas7_pmx_functions, - .funcs_cnt = array_size(atlas7_pmx_functions), - .confs = (struct atlas7_pad_config *)atlas7_ioc_pad_confs, - .confs_cnt = array_size(atlas7_ioc_pad_confs), -}; - -/* simple map data structure */ -struct map_data { - u8 idx; - u8 data; -}; - -/** - * struct atlas7_pull_info - atlas7 pad pull info - * @pad_type: the type of this pad. - * @mask: the mas value of this pin's pull bits. - * @v2s: the map of pull register value to pull status. - * @s2v: the map of pull status to pull register value. - */ -struct atlas7_pull_info { - u8 pad_type; - u8 mask; - const struct map_data *v2s; - const struct map_data *s2v; -}; - -/* pull register value map to status */ -static const struct map_data p4we_pull_v2s[] = { - { p4we_pull_up, pull_up }, - { p4we_high_hysteresis, high_hysteresis }, - { p4we_high_z, high_z }, - { p4we_pull_down, pull_down }, -}; - -static const struct map_data p16st_pull_v2s[] = { - { p16st_pull_up, pull_up }, - { pd, pull_unknown }, - { p16st_high_z, high_z }, - { p16st_pull_down, pull_down }, -}; - -static const struct map_data pm31_pull_v2s[] = { - { pm31_pull_disabled, pull_down }, - { pm31_pull_enabled, pull_up }, -}; - -static const struct map_data pangd_pull_v2s[] = { - { pangd_pull_up, pull_up }, - { pd, pull_unknown }, - { pangd_high_z, high_z }, - { pangd_pull_down, pull_down }, -}; - -/* pull status map to register value */ -static const struct map_data p4we_pull_s2v[] = { - { pull_up, p4we_pull_up }, - { high_hysteresis, p4we_high_hysteresis }, - { high_z, p4we_high_z }, - { pull_down, p4we_pull_down }, - { pull_disable, -1 }, - { pull_enable, -1 }, -}; - -static const struct map_data p16st_pull_s2v[] = { - { pull_up, p16st_pull_up }, - { high_hysteresis, -1 }, - { high_z, p16st_high_z }, - { pull_down, p16st_pull_down }, - { pull_disable, -1 }, - { pull_enable, -1 }, -}; - -static const struct map_data pm31_pull_s2v[] = { - { pull_up, pm31_pull_enabled }, - { high_hysteresis, -1 }, - { high_z, -1 }, - { pull_down, pm31_pull_disabled }, - { pull_disable, -1 }, - { pull_enable, -1 }, -}; - -static const struct map_data pangd_pull_s2v[] = { - { pull_up, pangd_pull_up }, - { high_hysteresis, -1 }, - { high_z, pangd_high_z }, - { pull_down, pangd_pull_down }, - { pull_disable, -1 }, - { pull_enable, -1 }, -}; - -static const struct atlas7_pull_info atlas7_pull_map[] = { - { pad_t_4we_pd, p4we_pull_mask, p4we_pull_v2s, p4we_pull_s2v }, - { pad_t_4we_pu, p4we_pull_mask, p4we_pull_v2s, p4we_pull_s2v }, - { pad_t_16st, p16st_pull_mask, p16st_pull_v2s, p16st_pull_s2v }, - { pad_t_m31_0204_pd, pm31_pull_mask, pm31_pull_v2s, pm31_pull_s2v }, - { pad_t_m31_0204_pu, pm31_pull_mask, pm31_pull_v2s, pm31_pull_s2v }, - { pad_t_m31_0610_pd, pm31_pull_mask, pm31_pull_v2s, pm31_pull_s2v }, - { pad_t_m31_0610_pu, pm31_pull_mask, pm31_pull_v2s, pm31_pull_s2v }, - { pad_t_ad, pangd_pull_mask, pangd_pull_v2s, pangd_pull_s2v }, -}; - -/** - * struct atlas7_ds_ma_info - atlas7 pad drivestrength & currents info - * @ma: the drive strength in current value . - * @ds_16st: the correspond raw value of 16st pad. - * @ds_4we: the correspond raw value of 4we pad. - * @ds_0204m31: the correspond raw value of 0204m31 pad. - * @ds_0610m31: the correspond raw value of 0610m31 pad. - */ -struct atlas7_ds_ma_info { - u32 ma; - u32 ds_16st; - u32 ds_4we; - u32 ds_0204m31; - u32 ds_0610m31; -}; - -static const struct atlas7_ds_ma_info atlas7_ma2ds_map[] = { - { 2, ds_16st_0, ds_4we_0, ds_m31_0, ds_null }, - { 4, ds_16st_1, ds_null, ds_m31_1, ds_null }, - { 6, ds_16st_2, ds_null, ds_null, ds_m31_0 }, - { 8, ds_16st_3, ds_4we_1, ds_null, ds_null }, - { 10, ds_16st_4, ds_null, ds_null, ds_m31_1 }, - { 12, ds_16st_5, ds_null, ds_null, ds_null }, - { 14, ds_16st_6, ds_null, ds_null, ds_null }, - { 16, ds_16st_7, ds_4we_2, ds_null, ds_null }, - { 18, ds_16st_8, ds_null, ds_null, ds_null }, - { 20, ds_16st_9, ds_null, ds_null, ds_null }, - { 22, ds_16st_10, ds_null, ds_null, ds_null }, - { 24, ds_16st_11, ds_null, ds_null, ds_null }, - { 26, ds_16st_12, ds_null, ds_null, ds_null }, - { 28, ds_16st_13, ds_4we_3, ds_null, ds_null }, - { 30, ds_16st_14, ds_null, ds_null, ds_null }, - { 32, ds_16st_15, ds_null, ds_null, ds_null }, -}; - -/** - * struct atlas7_ds_info - atlas7 pad drivestrength info - * @type: the type of this pad. - * @mask: the mask value of this pin's pull bits. - * @imval: the immediate value of drives trength register. - * @reserved: reserved space - */ -struct atlas7_ds_info { - u8 type; - u8 mask; - u8 imval; - u8 reserved; -}; - -static const struct atlas7_ds_info atlas7_ds_map[] = { - { pad_t_4we_pd, ds_2bit_mask, ds_2bit_im_val }, - { pad_t_4we_pu, ds_2bit_mask, ds_2bit_im_val }, - { pad_t_16st, ds_4bit_mask, ds_4bit_im_val }, - { pad_t_m31_0204_pd, ds_1bit_mask, ds_1bit_im_val }, - { pad_t_m31_0204_pu, ds_1bit_mask, ds_1bit_im_val }, - { pad_t_m31_0610_pd, ds_1bit_mask, ds_1bit_im_val }, - { pad_t_m31_0610_pu, ds_1bit_mask, ds_1bit_im_val }, - { pad_t_ad, ds_null, ds_null }, -}; - -static inline u32 atlas7_pin_to_bank(u32 pin) -{ - return (pin >= atlas7_pinctrl_bank_0_pins) ? 1 : 0; -} - -static int atlas7_pmx_get_funcs_count(struct pinctrl_dev *pctldev) -{ - struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - - return pmx->pctl_data->funcs_cnt; -} - -static const char *atlas7_pmx_get_func_name(struct pinctrl_dev *pctldev, - u32 selector) -{ - struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - - return pmx->pctl_data->funcs[selector].name; -} - -static int atlas7_pmx_get_func_groups(struct pinctrl_dev *pctldev, - u32 selector, const char * const **groups, - u32 * const num_groups) -{ - struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - - *groups = pmx->pctl_data->funcs[selector].groups; - *num_groups = pmx->pctl_data->funcs[selector].num_groups; - - return 0; -} - -static void __atlas7_pmx_pin_input_disable_set(struct atlas7_pmx *pmx, - const struct atlas7_pad_mux *mux) -{ - /* set input disable to avoid input glitches - * - * all input-disable control registers are located on iocrtc. - * so the regs bank is always 0. - * - */ - if (mux->dinput_reg && mux->dinput_val_reg) { - writel(di_mask << mux->dinput_bit, - pmx->regs[bank_ds] + clr_reg(mux->dinput_reg)); - writel(di_disable << mux->dinput_bit, - pmx->regs[bank_ds] + mux->dinput_reg); - - - writel(div_mask << mux->dinput_val_bit, - pmx->regs[bank_ds] + clr_reg(mux->dinput_val_reg)); - writel(div_disable << mux->dinput_val_bit, - pmx->regs[bank_ds] + mux->dinput_val_reg); - } -} - -static void __atlas7_pmx_pin_input_disable_clr(struct atlas7_pmx *pmx, - const struct atlas7_pad_mux *mux) -{ - /* clear input disable to avoid input glitches */ - if (mux->dinput_reg && mux->dinput_val_reg) { - writel(di_mask << mux->dinput_bit, - pmx->regs[bank_ds] + clr_reg(mux->dinput_reg)); - writel(di_enable << mux->dinput_bit, - pmx->regs[bank_ds] + mux->dinput_reg); - - writel(div_mask << mux->dinput_val_bit, - pmx->regs[bank_ds] + clr_reg(mux->dinput_val_reg)); - writel(div_enable << mux->dinput_val_bit, - pmx->regs[bank_ds] + mux->dinput_val_reg); - } -} - -static int __atlas7_pmx_pin_ad_sel(struct atlas7_pmx *pmx, - struct atlas7_pad_config *conf, - u32 bank, u32 ad_sel) -{ - unsigned long regv; - - /* write to clear register to clear a/d selector */ - writel(ana_clear_mask << conf->ad_ctrl_bit, - pmx->regs[bank] + clr_reg(conf->ad_ctrl_reg)); - - /* set target pad a/d selector */ - regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg); - regv &= ~(ana_clear_mask << conf->ad_ctrl_bit); - writel(regv | (ad_sel << conf->ad_ctrl_bit), - pmx->regs[bank] + conf->ad_ctrl_reg); - - regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg); - pr_debug("bank:%d reg:0x%04x val:0x%08lx ", - bank, conf->ad_ctrl_reg, regv); - return 0; -} - -static int __atlas7_pmx_pin_analog_enable(struct atlas7_pmx *pmx, - struct atlas7_pad_config *conf, u32 bank) -{ - /* only pad_t_ad pins can change between analogue&digital */ - if (conf->type != pad_t_ad) - return -einval; - - return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 0); -} - -static int __atlas7_pmx_pin_digital_enable(struct atlas7_pmx *pmx, - struct atlas7_pad_config *conf, u32 bank) -{ - /* other type pads are always digital */ - if (conf->type != pad_t_ad) - return 0; - - return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 1); -} - -static int __atlas7_pmx_pin_enable(struct atlas7_pmx *pmx, - u32 pin, u32 func) -{ - struct atlas7_pad_config *conf; - u32 bank; - int ret; - unsigned long regv; - - pr_debug("pmx dump ### pin#%d func:%d #### start >>> ", - pin, func); - - /* get this pad's descriptor from pinctrl */ - conf = &pmx->pctl_data->confs[pin]; - bank = atlas7_pin_to_bank(pin); - - /* just enable the analog function of this pad */ - if (func_analogue == func) { - ret = __atlas7_pmx_pin_analog_enable(pmx, conf, bank); - if (ret) - dev_err(pmx->dev, - "convert pad#%d to analog failed, ret=%d ", - pin, ret); - return ret; - } - - /* set pads from analog to digital */ - ret = __atlas7_pmx_pin_digital_enable(pmx, conf, bank); - if (ret) { - dev_err(pmx->dev, - "convert pad#%d to digital failed, ret=%d ", - pin, ret); - return ret; - } - - /* write to clear register to clear current function */ - writel(func_clear_mask << conf->mux_bit, - pmx->regs[bank] + clr_reg(conf->mux_reg)); - - /* set target pad mux function */ - regv = readl(pmx->regs[bank] + conf->mux_reg); - regv &= ~(func_clear_mask << conf->mux_bit); - writel(regv | (func << conf->mux_bit), - pmx->regs[bank] + conf->mux_reg); - - regv = readl(pmx->regs[bank] + conf->mux_reg); - pr_debug("bank:%d reg:0x%04x val:0x%08lx ", - bank, conf->mux_reg, regv); - - return 0; -} - -static int atlas7_pmx_set_mux(struct pinctrl_dev *pctldev, - u32 func_selector, u32 group_selector) -{ - int idx, ret; - struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - struct atlas7_pmx_func *pmx_func; - struct atlas7_pin_group *pin_grp; - const struct atlas7_grp_mux *grp_mux; - const struct atlas7_pad_mux *mux; - - pmx_func = &pmx->pctl_data->funcs[func_selector]; - pin_grp = &pmx->pctl_data->grps[group_selector]; - - pr_debug("pmx dump ### function:[%s] group:[%s] #### start >>> ", - pmx_func->name, pin_grp->name); - - /* the sd3 and sd9 pin select by sys2pci_sdio9sel register */ - if (pin_grp->pins == (unsigned int *)&sd3_9_pins) { - if (!strcmp(pmx_func->name, "sd9")) - writel(1, pmx->sys2pci_base + sys2pci_sdio9sel); - else - writel(0, pmx->sys2pci_base + sys2pci_sdio9sel); - } - - grp_mux = pmx_func->grpmux; - - for (idx = 0; idx < grp_mux->pad_mux_count; idx++) { - mux = &grp_mux->pad_mux_list[idx]; - __atlas7_pmx_pin_input_disable_set(pmx, mux); - ret = __atlas7_pmx_pin_enable(pmx, mux->pin, mux->func); - if (ret) { - dev_err(pmx->dev, - "func:%s grp:%s pin#%d.%d failed, ret=%d ", - pmx_func->name, pin_grp->name, - mux->pin, mux->func, ret); - bug_on(1); - } - __atlas7_pmx_pin_input_disable_clr(pmx, mux); - } - pr_debug("pmx dump ### function:[%s] group:[%s] #### end <<< ", - pmx_func->name, pin_grp->name); - - return 0; -} - -static u32 convert_current_to_drive_strength(u32 type, u32 ma) -{ - int idx; - - for (idx = 0; idx < array_size(atlas7_ma2ds_map); idx++) { - if (atlas7_ma2ds_map[idx].ma != ma) - continue; - - if (type == pad_t_4we_pd || type == pad_t_4we_pu) - return atlas7_ma2ds_map[idx].ds_4we; - else if (type == pad_t_16st) - return atlas7_ma2ds_map[idx].ds_16st; - else if (type == pad_t_m31_0204_pd || type == pad_t_m31_0204_pu) - return atlas7_ma2ds_map[idx].ds_0204m31; - else if (type == pad_t_m31_0610_pd || type == pad_t_m31_0610_pu) - return atlas7_ma2ds_map[idx].ds_0610m31; - } - - return ds_null; -} - -static int altas7_pinctrl_set_pull_sel(struct pinctrl_dev *pctldev, - u32 pin, u32 sel) -{ - struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin]; - const struct atlas7_pull_info *pull_info; - u32 bank; - unsigned long regv; - void __iomem *pull_sel_reg; - - bank = atlas7_pin_to_bank(pin); - pull_info = &atlas7_pull_map[conf->type]; - pull_sel_reg = pmx->regs[bank] + conf->pupd_reg; - - /* retrieve correspond register value from table by sel */ - regv = pull_info->s2v[sel].data & pull_info->mask; - - /* clear & set new value to pull register */ - writel(pull_info->mask << conf->pupd_bit, clr_reg(pull_sel_reg)); - writel(regv << conf->pupd_bit, pull_sel_reg); - - pr_debug("pin_cfg ### set pin#%d pull selector:%d == ok #### ", - pin, sel); - return 0; -} - -static int __altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev, - u32 pin, u32 sel) -{ - struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin]; - const struct atlas7_ds_info *ds_info; - u32 bank; - void __iomem *ds_sel_reg; - - ds_info = &atlas7_ds_map[conf->type]; - if (sel & (~(ds_info->mask))) - goto unsupport; - - bank = atlas7_pin_to_bank(pin); - ds_sel_reg = pmx->regs[bank] + conf->drvstr_reg; - - writel(ds_info->imval << conf->drvstr_bit, clr_reg(ds_sel_reg)); - writel(sel << conf->drvstr_bit, ds_sel_reg); - - return 0; - -unsupport: - pr_err("pad#%d type[%d] doesn't support ds code[%d]! ", - pin, conf->type, sel); - return -enotsupp; -} - -static int altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev, - u32 pin, u32 ma) -{ - struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin]; - u32 type = conf->type; - u32 sel; - int ret; - - sel = convert_current_to_drive_strength(conf->type, ma); - if (ds_null == sel) { - pr_err("pad#%d type[%d] doesn't support ds current[%d]! ", - pin, type, ma); - return -enotsupp; - } - - ret = __altas7_pinctrl_set_drive_strength_sel(pctldev, - pin, sel); - pr_debug("pin_cfg ### set pin#%d ds:%d ma:%d == %s #### ", - pin, sel, ma, ret?"failed":"ok"); - return ret; -} - -static int atlas7_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, u32 pin) -{ - struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - u32 idx; - - dev_dbg(pmx->dev, - "atlas7_pmx_gpio_request_enable: pin=%d ", pin); - for (idx = 0; idx < range->npins; idx++) { - if (pin == range->pins[idx]) - break; - } - - if (idx >= range->npins) { - dev_err(pmx->dev, - "the pin#%d could not be requested as gpio!! ", - pin); - return -eperm; - } - - __atlas7_pmx_pin_enable(pmx, pin, func_gpio); - - return 0; -} - -static const struct pinmux_ops atlas7_pinmux_ops = { - .get_functions_count = atlas7_pmx_get_funcs_count, - .get_function_name = atlas7_pmx_get_func_name, - .get_function_groups = atlas7_pmx_get_func_groups, - .set_mux = atlas7_pmx_set_mux, - .gpio_request_enable = atlas7_pmx_gpio_request_enable, -}; - -static int atlas7_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - - return pmx->pctl_data->grps_cnt; -} - -static const char *atlas7_pinctrl_get_group_name(struct pinctrl_dev *pctldev, - u32 group) -{ - struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - - return pmx->pctl_data->grps[group].name; -} - -static int atlas7_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, - u32 group, const u32 **pins, u32 *num_pins) -{ - struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - - *num_pins = pmx->pctl_data->grps[group].num_pins; - *pins = pmx->pctl_data->grps[group].pins; - - return 0; -} - -static int atlas7_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, - u32 *num_maps) -{ - return pinconf_generic_dt_node_to_map(pctldev, np_config, map, - num_maps, pin_map_type_invalid); -} - -static void atlas7_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, u32 num_maps) -{ - kfree(map); -} - -static const struct pinctrl_ops atlas7_pinctrl_ops = { - .get_groups_count = atlas7_pinctrl_get_groups_count, - .get_group_name = atlas7_pinctrl_get_group_name, - .get_group_pins = atlas7_pinctrl_get_group_pins, - .dt_node_to_map = atlas7_pinctrl_dt_node_to_map, - .dt_free_map = atlas7_pinctrl_dt_free_map, -}; - -static int atlas7_pin_config_set(struct pinctrl_dev *pctldev, - unsigned pin, unsigned long *configs, - unsigned num_configs) -{ - u16 param; - u32 arg; - int idx, err; - - for (idx = 0; idx < num_configs; idx++) { - param = pinconf_to_config_param(configs[idx]); - arg = pinconf_to_config_argument(configs[idx]); - - pr_debug("pmx cfg###### atlas7 pin#%d [%s] config param:%d arg:%d >>>>> ", - pin, atlas7_ioc_pads[pin].name, param, arg); - switch (param) { - case pin_config_bias_pull_up: - err = altas7_pinctrl_set_pull_sel(pctldev, - pin, pull_up); - if (err) - return err; - break; - - case pin_config_bias_pull_down: - err = altas7_pinctrl_set_pull_sel(pctldev, - pin, pull_down); - if (err) - return err; - break; - - case pin_config_input_schmitt_enable: - err = altas7_pinctrl_set_pull_sel(pctldev, - pin, high_hysteresis); - if (err) - return err; - break; - case pin_config_bias_high_impedance: - err = altas7_pinctrl_set_pull_sel(pctldev, - pin, high_z); - if (err) - return err; - break; - - case pin_config_drive_strength: - err = altas7_pinctrl_set_drive_strength_sel(pctldev, - pin, arg); - if (err) - return err; - break; - default: - return -enotsupp; - } - pr_debug("pmx cfg###### atlas7 pin#%d [%s] config param:%d arg:%d <<<< ", - pin, atlas7_ioc_pads[pin].name, param, arg); - } - - return 0; -} - -static int atlas7_pin_config_group_set(struct pinctrl_dev *pctldev, - unsigned group, unsigned long *configs, - unsigned num_configs) -{ - const unsigned *pins; - unsigned npins; - int i, ret; - - ret = atlas7_pinctrl_get_group_pins(pctldev, group, &pins, &npins); - if (ret) - return ret; - for (i = 0; i < npins; i++) { - if (atlas7_pin_config_set(pctldev, pins[i], - configs, num_configs)) - return -enotsupp; - } - return 0; -} - -static const struct pinconf_ops atlas7_pinconf_ops = { - .pin_config_set = atlas7_pin_config_set, - .pin_config_group_set = atlas7_pin_config_group_set, - .is_generic = true, -}; - -static int atlas7_pinmux_probe(struct platform_device *pdev) -{ - int ret, idx; - struct atlas7_pmx *pmx; - struct device_node *np = pdev->dev.of_node; - u32 banks = atlas7_pinctrl_reg_banks; - struct device_node *sys2pci_np; - struct resource res; - - /* create state holders etc for this driver */ - pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), gfp_kernel); - if (!pmx) - return -enomem; - - /* the sd3 and sd9 shared all pins, and the function select by - * sys2pci_sdio9sel register - */ - sys2pci_np = of_find_node_by_name(null, "sys2pci"); - if (!sys2pci_np) - return -einval; - - ret = of_address_to_resource(sys2pci_np, 0, &res); - of_node_put(sys2pci_np); - if (ret) - return ret; - - pmx->sys2pci_base = devm_ioremap_resource(&pdev->dev, &res); - if (is_err(pmx->sys2pci_base)) - return -enomem; - - pmx->dev = &pdev->dev; - - pmx->pctl_data = &atlas7_ioc_data; - pmx->pctl_desc.name = "pinctrl-atlas7"; - pmx->pctl_desc.pins = pmx->pctl_data->pads; - pmx->pctl_desc.npins = pmx->pctl_data->pads_cnt; - pmx->pctl_desc.pctlops = &atlas7_pinctrl_ops; - pmx->pctl_desc.pmxops = &atlas7_pinmux_ops; - pmx->pctl_desc.confops = &atlas7_pinconf_ops; - - for (idx = 0; idx < banks; idx++) { - pmx->regs[idx] = of_iomap(np, idx); - if (!pmx->regs[idx]) { - dev_err(&pdev->dev, - "can't map ioc bank#%d registers ", idx); - ret = -enomem; - goto unmap_io; - } - } - - /* now register the pin controller and all pins it handles */ - pmx->pctl = pinctrl_register(&pmx->pctl_desc, &pdev->dev, pmx); - if (is_err(pmx->pctl)) { - dev_err(&pdev->dev, "could not register atlas7 pinmux driver "); - ret = ptr_err(pmx->pctl); - goto unmap_io; - } - - platform_set_drvdata(pdev, pmx); - - dev_info(&pdev->dev, "initialized atlas7 pinmux driver "); - - return 0; - -unmap_io: - for (idx = 0; idx < banks; idx++) { - if (!pmx->regs[idx]) - break; - iounmap(pmx->regs[idx]); - } - - return ret; -} - -#ifdef config_pm_sleep -static int atlas7_pinmux_suspend_noirq(struct device *dev) -{ - struct atlas7_pmx *pmx = dev_get_drvdata(dev); - struct atlas7_pad_status *status; - struct atlas7_pad_config *conf; - const struct atlas7_ds_info *ds_info; - const struct atlas7_pull_info *pull_info; - int idx; - u32 bank; - unsigned long regv; - - for (idx = 0; idx < pmx->pctl_desc.npins; idx++) { - /* get this pad's descriptor from pinctrl */ - conf = &pmx->pctl_data->confs[idx]; - bank = atlas7_pin_to_bank(idx); - status = &pmx->sleep_data[idx]; - - /* save function selector */ - regv = readl(pmx->regs[bank] + conf->mux_reg); - status->func = (regv >> conf->mux_bit) & func_clear_mask; - - /* check if pad is in analogue selector */ - if (conf->ad_ctrl_reg == -1) - goto save_ds_sel; - - regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg); - if (!(regv & (conf->ad_ctrl_bit << ana_clear_mask))) - status->func = func_analogue; - -save_ds_sel: - if (conf->drvstr_reg == -1) - goto save_pull_sel; - - /* save drive strength selector */ - ds_info = &atlas7_ds_map[conf->type]; - regv = readl(pmx->regs[bank] + conf->drvstr_reg); - status->dstr = (regv >> conf->drvstr_bit) & ds_info->mask; - -save_pull_sel: - /* save pull selector */ - pull_info = &atlas7_pull_map[conf->type]; - regv = readl(pmx->regs[bank] + conf->pupd_reg); - regv = (regv >> conf->pupd_bit) & pull_info->mask; - status->pull = pull_info->v2s[regv].data; - } - - /* - * save disable input selector, this selector is not for pin, - * but for mux function. - */ - for (idx = 0; idx < num_of_in_disable_reg; idx++) { - pmx->status_ds[idx] = readl(pmx->regs[bank_ds] + - in_disable_0_reg_set + 0x8 * idx); - pmx->status_dsv[idx] = readl(pmx->regs[bank_ds] + - in_disable_val_0_reg_set + 0x8 * idx); - } - - return 0; -} - -static int atlas7_pinmux_resume_noirq(struct device *dev) -{ - struct atlas7_pmx *pmx = dev_get_drvdata(dev); - struct atlas7_pad_status *status; - int idx; - - for (idx = 0; idx < pmx->pctl_desc.npins; idx++) { - /* get this pad's descriptor from pinctrl */ - status = &pmx->sleep_data[idx]; - - /* restore function selector */ - __atlas7_pmx_pin_enable(pmx, idx, (u32)status->func & 0xff); - - if (func_analogue == status->func) - goto restore_pull_sel; - - /* restore drive strength selector */ - __altas7_pinctrl_set_drive_strength_sel(pmx->pctl, idx, - (u32)status->dstr & 0xff); - -restore_pull_sel: - /* restore pull selector */ - altas7_pinctrl_set_pull_sel(pmx->pctl, idx, - (u32)status->pull & 0xff); - } - - /* - * restore disable input selector, this selector is not for pin, - * but for mux function - */ - for (idx = 0; idx < num_of_in_disable_reg; idx++) { - writel(~0, pmx->regs[bank_ds] + - in_disable_0_reg_clr + 0x8 * idx); - writel(pmx->status_ds[idx], pmx->regs[bank_ds] + - in_disable_0_reg_set + 0x8 * idx); - writel(~0, pmx->regs[bank_ds] + - in_disable_val_0_reg_clr + 0x8 * idx); - writel(pmx->status_dsv[idx], pmx->regs[bank_ds] + - in_disable_val_0_reg_set + 0x8 * idx); - } - - return 0; -} - -static const struct dev_pm_ops atlas7_pinmux_pm_ops = { - .suspend_noirq = atlas7_pinmux_suspend_noirq, - .resume_noirq = atlas7_pinmux_resume_noirq, - .freeze_noirq = atlas7_pinmux_suspend_noirq, - .restore_noirq = atlas7_pinmux_resume_noirq, -}; -#endif - -static const struct of_device_id atlas7_pinmux_ids[] = { - { .compatible = "sirf,atlas7-ioc",}, - {}, -}; - -static struct platform_driver atlas7_pinmux_driver = { - .driver = { - .name = "atlas7-ioc", - .of_match_table = atlas7_pinmux_ids, -#ifdef config_pm_sleep - .pm = &atlas7_pinmux_pm_ops, -#endif - }, - .probe = atlas7_pinmux_probe, -}; - -static int __init atlas7_pinmux_init(void) -{ - return platform_driver_register(&atlas7_pinmux_driver); -} -arch_initcall(atlas7_pinmux_init); - - -/* - * the following is gpio code - */ -static inline struct -atlas7_gpio_bank *atlas7_gpio_to_bank(struct atlas7_gpio_chip *a7gc, u32 gpio) -{ - return &a7gc->banks[gpio_to_bank(gpio)]; -} - -static int __atlas7_gpio_to_pin(struct atlas7_gpio_chip *a7gc, u32 gpio) -{ - struct atlas7_gpio_bank *bank; - u32 ofs; - - bank = atlas7_gpio_to_bank(a7gc, gpio); - ofs = gpio - bank->gpio_offset; - if (ofs >= bank->ngpio) - return -enodev; - - return bank->gpio_pins[ofs]; -} - -static void atlas7_gpio_irq_ack(struct irq_data *d) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc); - struct atlas7_gpio_bank *bank; - void __iomem *ctrl_reg; - u32 val, pin_in_bank; - unsigned long flags; - - bank = atlas7_gpio_to_bank(a7gc, d->hwirq); - pin_in_bank = d->hwirq - bank->gpio_offset; - ctrl_reg = atlas7_gpio_ctrl(bank, pin_in_bank); - - raw_spin_lock_irqsave(&a7gc->lock, flags); - - val = readl(ctrl_reg); - /* clear interrupt status */ - writel(val, ctrl_reg); - - raw_spin_unlock_irqrestore(&a7gc->lock, flags); -} - -static void __atlas7_gpio_irq_mask(struct atlas7_gpio_chip *a7gc, int idx) -{ - struct atlas7_gpio_bank *bank; - void __iomem *ctrl_reg; - u32 val, pin_in_bank; - - bank = atlas7_gpio_to_bank(a7gc, idx); - pin_in_bank = idx - bank->gpio_offset; - ctrl_reg = atlas7_gpio_ctrl(bank, pin_in_bank); - - val = readl(ctrl_reg); - val &= ~(atlas7_gpio_ctl_intr_en_mask | - atlas7_gpio_ctl_intr_status_mask); - writel(val, ctrl_reg); -} - -static void atlas7_gpio_irq_mask(struct irq_data *d) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc); - unsigned long flags; - - raw_spin_lock_irqsave(&a7gc->lock, flags); - - __atlas7_gpio_irq_mask(a7gc, d->hwirq); - - raw_spin_unlock_irqrestore(&a7gc->lock, flags); -} - -static void atlas7_gpio_irq_unmask(struct irq_data *d) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc); - struct atlas7_gpio_bank *bank; - void __iomem *ctrl_reg; - u32 val, pin_in_bank; - unsigned long flags; - - bank = atlas7_gpio_to_bank(a7gc, d->hwirq); - pin_in_bank = d->hwirq - bank->gpio_offset; - ctrl_reg = atlas7_gpio_ctrl(bank, pin_in_bank); - - raw_spin_lock_irqsave(&a7gc->lock, flags); - - val = readl(ctrl_reg); - val &= ~atlas7_gpio_ctl_intr_status_mask; - val |= atlas7_gpio_ctl_intr_en_mask; - writel(val, ctrl_reg); - - raw_spin_unlock_irqrestore(&a7gc->lock, flags); -} - -static int atlas7_gpio_irq_type(struct irq_data *d, - unsigned int type) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc); - struct atlas7_gpio_bank *bank; - void __iomem *ctrl_reg; - u32 val, pin_in_bank; - unsigned long flags; - - bank = atlas7_gpio_to_bank(a7gc, d->hwirq); - pin_in_bank = d->hwirq - bank->gpio_offset; - ctrl_reg = atlas7_gpio_ctrl(bank, pin_in_bank); - - raw_spin_lock_irqsave(&a7gc->lock, flags); - - val = readl(ctrl_reg); - val &= ~(atlas7_gpio_ctl_intr_status_mask | - atlas7_gpio_ctl_intr_en_mask); - - switch (type) { - case irq_type_none: - break; - - case irq_type_edge_rising: - val |= atlas7_gpio_ctl_intr_high_mask | - atlas7_gpio_ctl_intr_type_mask; - val &= ~atlas7_gpio_ctl_intr_low_mask; - break; - - case irq_type_edge_falling: - val &= ~atlas7_gpio_ctl_intr_high_mask; - val |= atlas7_gpio_ctl_intr_low_mask | - atlas7_gpio_ctl_intr_type_mask; - break; - - case irq_type_edge_both: - val |= atlas7_gpio_ctl_intr_high_mask | - atlas7_gpio_ctl_intr_low_mask | - atlas7_gpio_ctl_intr_type_mask; - break; - - case irq_type_level_low: - val &= ~(atlas7_gpio_ctl_intr_high_mask | - atlas7_gpio_ctl_intr_type_mask); - val |= atlas7_gpio_ctl_intr_low_mask; - break; - - case irq_type_level_high: - val |= atlas7_gpio_ctl_intr_high_mask; - val &= ~(atlas7_gpio_ctl_intr_low_mask | - atlas7_gpio_ctl_intr_type_mask); - break; - } - - writel(val, ctrl_reg); - - raw_spin_unlock_irqrestore(&a7gc->lock, flags); - - return 0; -} - -static struct irq_chip atlas7_gpio_irq_chip = { - .name = "atlas7-gpio-irq", - .irq_ack = atlas7_gpio_irq_ack, - .irq_mask = atlas7_gpio_irq_mask, - .irq_unmask = atlas7_gpio_irq_unmask, - .irq_set_type = atlas7_gpio_irq_type, -}; - -static void atlas7_gpio_handle_irq(struct irq_desc *desc) -{ - struct gpio_chip *gc = irq_desc_get_handler_data(desc); - struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc); - struct atlas7_gpio_bank *bank = null; - u32 status, ctrl; - int pin_in_bank = 0, idx; - struct irq_chip *chip = irq_desc_get_chip(desc); - unsigned int irq = irq_desc_get_irq(desc); - - for (idx = 0; idx < a7gc->nbank; idx++) { - bank = &a7gc->banks[idx]; - if (bank->irq == irq) - break; - } - bug_on(idx == a7gc->nbank); - - chained_irq_enter(chip, desc); - - status = readl(atlas7_gpio_int_status(bank)); - if (!status) { - pr_warn("%s: gpio [%s] status %#x no interrupt is flagged ", - __func__, gc->label, status); - handle_bad_irq(desc); - return; - } - - while (status) { - ctrl = readl(atlas7_gpio_ctrl(bank, pin_in_bank)); - - /* - * here we must check whether the corresponding gpio's - * interrupt has been enabled, otherwise just skip it - */ - if ((status & 0x1) && (ctrl & atlas7_gpio_ctl_intr_en_mask)) { - pr_debug("%s: chip[%s] gpio:%d happens ", - __func__, gc->label, - bank->gpio_offset + pin_in_bank); - generic_handle_irq( - irq_find_mapping(gc->irq.domain, - bank->gpio_offset + pin_in_bank)); - } - - if (++pin_in_bank >= bank->ngpio) - break; - - status = status >> 1; - } - - chained_irq_exit(chip, desc); -} - -static void __atlas7_gpio_set_input(struct atlas7_gpio_chip *a7gc, - unsigned int gpio) -{ - struct atlas7_gpio_bank *bank; - void __iomem *ctrl_reg; - u32 val, pin_in_bank; - - bank = atlas7_gpio_to_bank(a7gc, gpio); - pin_in_bank = gpio - bank->gpio_offset; - ctrl_reg = atlas7_gpio_ctrl(bank, pin_in_bank); - - val = readl(ctrl_reg); - val &= ~atlas7_gpio_ctl_out_en_mask; - writel(val, ctrl_reg); -} - -static int atlas7_gpio_request(struct gpio_chip *chip, - unsigned int gpio) -{ - struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip); - int ret; - unsigned long flags; - - ret = __atlas7_gpio_to_pin(a7gc, gpio); - if (ret < 0) - return ret; - - if (pinctrl_gpio_request(chip->base + gpio)) - return -enodev; - - raw_spin_lock_irqsave(&a7gc->lock, flags); - - /* - * default status: - * set direction as input and mask irq - */ - __atlas7_gpio_set_input(a7gc, gpio); - __atlas7_gpio_irq_mask(a7gc, gpio); - - raw_spin_unlock_irqrestore(&a7gc->lock, flags); - - return 0; -} - -static void atlas7_gpio_free(struct gpio_chip *chip, - unsigned int gpio) -{ - struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip); - unsigned long flags; - - raw_spin_lock_irqsave(&a7gc->lock, flags); - - __atlas7_gpio_irq_mask(a7gc, gpio); - __atlas7_gpio_set_input(a7gc, gpio); - - raw_spin_unlock_irqrestore(&a7gc->lock, flags); - - pinctrl_gpio_free(chip->base + gpio); -} - -static int atlas7_gpio_direction_input(struct gpio_chip *chip, - unsigned int gpio) -{ - struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip); - unsigned long flags; - - raw_spin_lock_irqsave(&a7gc->lock, flags); - - __atlas7_gpio_set_input(a7gc, gpio); - - raw_spin_unlock_irqrestore(&a7gc->lock, flags); - - return 0; -} - -static void __atlas7_gpio_set_output(struct atlas7_gpio_chip *a7gc, - unsigned int gpio, int value) -{ - struct atlas7_gpio_bank *bank; - void __iomem *ctrl_reg; - u32 out_ctrl, pin_in_bank; - - bank = atlas7_gpio_to_bank(a7gc, gpio); - pin_in_bank = gpio - bank->gpio_offset; - ctrl_reg = atlas7_gpio_ctrl(bank, pin_in_bank); - - out_ctrl = readl(ctrl_reg); - if (value) - out_ctrl |= atlas7_gpio_ctl_dataout_mask; - else - out_ctrl &= ~atlas7_gpio_ctl_dataout_mask; - - out_ctrl &= ~atlas7_gpio_ctl_intr_en_mask; - out_ctrl |= atlas7_gpio_ctl_out_en_mask; - writel(out_ctrl, ctrl_reg); -} - -static int atlas7_gpio_direction_output(struct gpio_chip *chip, - unsigned int gpio, int value) -{ - struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip); - unsigned long flags; - - raw_spin_lock_irqsave(&a7gc->lock, flags); - - __atlas7_gpio_set_output(a7gc, gpio, value); - - raw_spin_unlock_irqrestore(&a7gc->lock, flags); - - return 0; -} - -static int atlas7_gpio_get_value(struct gpio_chip *chip, - unsigned int gpio) -{ - struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip); - struct atlas7_gpio_bank *bank; - u32 val, pin_in_bank; - unsigned long flags; - - bank = atlas7_gpio_to_bank(a7gc, gpio); - pin_in_bank = gpio - bank->gpio_offset; - - raw_spin_lock_irqsave(&a7gc->lock, flags); - - val = readl(atlas7_gpio_ctrl(bank, pin_in_bank)); - - raw_spin_unlock_irqrestore(&a7gc->lock, flags); - - return !!(val & atlas7_gpio_ctl_datain_mask); -} - -static void atlas7_gpio_set_value(struct gpio_chip *chip, - unsigned int gpio, int value) -{ - struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip); - struct atlas7_gpio_bank *bank; - void __iomem *ctrl_reg; - u32 ctrl, pin_in_bank; - unsigned long flags; - - bank = atlas7_gpio_to_bank(a7gc, gpio); - pin_in_bank = gpio - bank->gpio_offset; - ctrl_reg = atlas7_gpio_ctrl(bank, pin_in_bank); - - raw_spin_lock_irqsave(&a7gc->lock, flags); - - ctrl = readl(ctrl_reg); - if (value) - ctrl |= atlas7_gpio_ctl_dataout_mask; - else - ctrl &= ~atlas7_gpio_ctl_dataout_mask; - writel(ctrl, ctrl_reg); - - raw_spin_unlock_irqrestore(&a7gc->lock, flags); -} - -static const struct of_device_id atlas7_gpio_ids[] = { - { .compatible = "sirf,atlas7-gpio", }, - {}, -}; - -static int atlas7_gpio_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct atlas7_gpio_chip *a7gc; - struct gpio_chip *chip; - u32 nbank; - int ret, idx; - struct gpio_irq_chip *girq; - - ret = of_property_read_u32(np, "gpio-banks", &nbank); - if (ret) { - dev_err(&pdev->dev, - "could not find gpio bank info,ret=%d! ", - ret); - return ret; - } - - /* retrieve gpio descriptor data */ - a7gc = devm_kzalloc(&pdev->dev, struct_size(a7gc, banks, nbank), - gfp_kernel); - if (!a7gc) - return -enomem; - - /* get gpio clk */ - a7gc->clk = of_clk_get(np, 0); - if (!is_err(a7gc->clk)) { - ret = clk_prepare_enable(a7gc->clk); - if (ret) { - dev_err(&pdev->dev, - "could not enable clock! "); - return ret; - } - } - - /* get gpio registers */ - a7gc->reg = of_iomap(np, 0); - if (!a7gc->reg) { - dev_err(&pdev->dev, "could not map gpio registers! "); - return -enomem; - } - - a7gc->nbank = nbank; - raw_spin_lock_init(&a7gc->lock); - - /* setup gpio chip */ - chip = &a7gc->chip; - chip->request = atlas7_gpio_request; - chip->free = atlas7_gpio_free; - chip->direction_input = atlas7_gpio_direction_input; - chip->get = atlas7_gpio_get_value; - chip->direction_output = atlas7_gpio_direction_output; - chip->set = atlas7_gpio_set_value; - chip->base = -1; - /* each chip can support 32 pins at one bank */ - chip->ngpio = ngpio_of_bank * nbank; - chip->label = kstrdup(np->name, gfp_kernel); - chip->of_node = np; - chip->of_gpio_n_cells = 2; - chip->parent = &pdev->dev; - - girq = &chip->irq; - girq->chip = &atlas7_gpio_irq_chip; - girq->parent_handler = atlas7_gpio_handle_irq; - girq->num_parents = nbank; - girq->parents = devm_kcalloc(&pdev->dev, nbank, - sizeof(*girq->parents), - gfp_kernel); - if (!girq->parents) - return -enomem; - for (idx = 0; idx < nbank; idx++) { - struct atlas7_gpio_bank *bank; - - bank = &a7gc->banks[idx]; - /* set ctrl registers' base of this bank */ - bank->base = atlas7_gpio_base(a7gc, idx); - bank->gpio_offset = idx * ngpio_of_bank; - - /* get interrupt number from dts */ - ret = of_irq_get(np, idx); - if (ret <= 0) { - dev_err(&pdev->dev, - "unable to find irq number. ret=%d ", ret); - if (!ret) - ret = -enxio; - goto failed; - } - bank->irq = ret; - girq->parents[idx] = ret; - } - girq->default_type = irq_type_none; - girq->handler = handle_level_irq; - - /* add gpio chip to system */ - ret = gpiochip_add_data(chip, a7gc); - if (ret) { - dev_err(&pdev->dev, - "%pof: error in probe function with status %d ", - np, ret); - goto failed; - } - - platform_set_drvdata(pdev, a7gc); - dev_info(&pdev->dev, "add to system. "); - return 0; -failed: - return ret; -} - -#ifdef config_pm_sleep -static int atlas7_gpio_suspend_noirq(struct device *dev) -{ - struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev); - struct atlas7_gpio_bank *bank; - void __iomem *ctrl_reg; - u32 idx, pin; - - for (idx = 0; idx < a7gc->nbank; idx++) { - bank = &a7gc->banks[idx]; - for (pin = 0; pin < bank->ngpio; pin++) { - ctrl_reg = atlas7_gpio_ctrl(bank, pin); - bank->sleep_data[pin] = readl(ctrl_reg); - } - } - - return 0; -} - -static int atlas7_gpio_resume_noirq(struct device *dev) -{ - struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev); - struct atlas7_gpio_bank *bank; - void __iomem *ctrl_reg; - u32 idx, pin; - - for (idx = 0; idx < a7gc->nbank; idx++) { - bank = &a7gc->banks[idx]; - for (pin = 0; pin < bank->ngpio; pin++) { - ctrl_reg = atlas7_gpio_ctrl(bank, pin); - writel(bank->sleep_data[pin], ctrl_reg); - } - } - - return 0; -} - -static const struct dev_pm_ops atlas7_gpio_pm_ops = { - .suspend_noirq = atlas7_gpio_suspend_noirq, - .resume_noirq = atlas7_gpio_resume_noirq, - .freeze_noirq = atlas7_gpio_suspend_noirq, - .restore_noirq = atlas7_gpio_resume_noirq, -}; -#endif - -static struct platform_driver atlas7_gpio_driver = { - .driver = { - .name = "atlas7-gpio", - .of_match_table = atlas7_gpio_ids, -#ifdef config_pm_sleep - .pm = &atlas7_gpio_pm_ops, -#endif - }, - .probe = atlas7_gpio_probe, -}; - -static int __init atlas7_gpio_init(void) -{ - return platform_driver_register(&atlas7_gpio_driver); -} -subsys_initcall(atlas7_gpio_init); diff --git a/drivers/pinctrl/sirf/pinctrl-prima2.c b/drivers/pinctrl/sirf/pinctrl-prima2.c --- a/drivers/pinctrl/sirf/pinctrl-prima2.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-or-later -/* - * pinctrl pads, groups, functions for csr sirfprimaii - * - * copyright (c) 2011 - 2014 cambridge silicon radio limited, a csr plc group - * company. - */ - -#include <linux/pinctrl/pinctrl.h> -#include <linux/bitops.h> - -#include "pinctrl-sirf.h" - -/* - * pad list for the pinmux subsystem - * refer to cs-131858-dc-6a.xls - */ -static const struct pinctrl_pin_desc sirfsoc_pads[] = { - pinctrl_pin(0, "gpio0-0"), - pinctrl_pin(1, "gpio0-1"), - pinctrl_pin(2, "gpio0-2"), - pinctrl_pin(3, "gpio0-3"), - pinctrl_pin(4, "pwm0"), - pinctrl_pin(5, "pwm1"), - pinctrl_pin(6, "pwm2"), - pinctrl_pin(7, "pwm3"), - pinctrl_pin(8, "warm_rst_b"), - pinctrl_pin(9, "odo_0"), - pinctrl_pin(10, "odo_1"), - pinctrl_pin(11, "dr_dir"), - pinctrl_pin(12, "viprom_fa"), - pinctrl_pin(13, "scl_1"), - pinctrl_pin(14, "ntrst"), - pinctrl_pin(15, "sda_1"), - pinctrl_pin(16, "x_ldd[16]"), - pinctrl_pin(17, "x_ldd[17]"), - pinctrl_pin(18, "x_ldd[18]"), - pinctrl_pin(19, "x_ldd[19]"), - pinctrl_pin(20, "x_ldd[20]"), - pinctrl_pin(21, "x_ldd[21]"), - pinctrl_pin(22, "x_ldd[22]"), - pinctrl_pin(23, "x_ldd[23], lcdrom_frdy"), - pinctrl_pin(24, "gps_sgn"), - pinctrl_pin(25, "gps_mag"), - pinctrl_pin(26, "gps_clk"), - pinctrl_pin(27, "sd_cd_b_1"), - pinctrl_pin(28, "sd_vcc_on_1"), - pinctrl_pin(29, "sd_wp_b_1"), - pinctrl_pin(30, "sd_clk_3"), - pinctrl_pin(31, "sd_cmd_3"), - - pinctrl_pin(32, "x_sd_dat_3[0]"), - pinctrl_pin(33, "x_sd_dat_3[1]"), - pinctrl_pin(34, "x_sd_dat_3[2]"), - pinctrl_pin(35, "x_sd_dat_3[3]"), - pinctrl_pin(36, "x_sd_clk_4"), - pinctrl_pin(37, "x_sd_cmd_4"), - pinctrl_pin(38, "x_sd_dat_4[0]"), - pinctrl_pin(39, "x_sd_dat_4[1]"), - pinctrl_pin(40, "x_sd_dat_4[2]"), - pinctrl_pin(41, "x_sd_dat_4[3]"), - pinctrl_pin(42, "x_cko_1"), - pinctrl_pin(43, "x_ac97_bit_clk"), - pinctrl_pin(44, "x_ac97_dout"), - pinctrl_pin(45, "x_ac97_din"), - pinctrl_pin(46, "x_ac97_sync"), - pinctrl_pin(47, "x_txd_1"), - pinctrl_pin(48, "x_txd_2"), - pinctrl_pin(49, "x_rxd_1"), - pinctrl_pin(50, "x_rxd_2"), - pinctrl_pin(51, "x_usclk_0"), - pinctrl_pin(52, "x_utxd_0"), - pinctrl_pin(53, "x_urxd_0"), - pinctrl_pin(54, "x_utfs_0"), - pinctrl_pin(55, "x_urfs_0"), - pinctrl_pin(56, "x_usclk_1"), - pinctrl_pin(57, "x_utxd_1"), - pinctrl_pin(58, "x_urxd_1"), - pinctrl_pin(59, "x_utfs_1"), - pinctrl_pin(60, "x_urfs_1"), - pinctrl_pin(61, "x_usclk_2"), - pinctrl_pin(62, "x_utxd_2"), - pinctrl_pin(63, "x_urxd_2"), - - pinctrl_pin(64, "x_utfs_2"), - pinctrl_pin(65, "x_urfs_2"), - pinctrl_pin(66, "x_df_we_b"), - pinctrl_pin(67, "x_df_re_b"), - pinctrl_pin(68, "x_txd_0"), - pinctrl_pin(69, "x_rxd_0"), - pinctrl_pin(78, "x_cko_0"), - pinctrl_pin(79, "x_vip_pxd[7]"), - pinctrl_pin(80, "x_vip_pxd[6]"), - pinctrl_pin(81, "x_vip_pxd[5]"), - pinctrl_pin(82, "x_vip_pxd[4]"), - pinctrl_pin(83, "x_vip_pxd[3]"), - pinctrl_pin(84, "x_vip_pxd[2]"), - pinctrl_pin(85, "x_vip_pxd[1]"), - pinctrl_pin(86, "x_vip_pxd[0]"), - pinctrl_pin(87, "x_vip_vsync"), - pinctrl_pin(88, "x_vip_hsync"), - pinctrl_pin(89, "x_vip_pxclk"), - pinctrl_pin(90, "x_sda_0"), - pinctrl_pin(91, "x_scl_0"), - pinctrl_pin(92, "x_df_ry_by"), - pinctrl_pin(93, "x_df_cs_b[1]"), - pinctrl_pin(94, "x_df_cs_b[0]"), - pinctrl_pin(95, "x_l_pclk"), - - pinctrl_pin(96, "x_l_lck"), - pinctrl_pin(97, "x_l_fck"), - pinctrl_pin(98, "x_l_de"), - pinctrl_pin(99, "x_ldd[0]"), - pinctrl_pin(100, "x_ldd[1]"), - pinctrl_pin(101, "x_ldd[2]"), - pinctrl_pin(102, "x_ldd[3]"), - pinctrl_pin(103, "x_ldd[4]"), - pinctrl_pin(104, "x_ldd[5]"), - pinctrl_pin(105, "x_ldd[6]"), - pinctrl_pin(106, "x_ldd[7]"), - pinctrl_pin(107, "x_ldd[8]"), - pinctrl_pin(108, "x_ldd[9]"), - pinctrl_pin(109, "x_ldd[10]"), - pinctrl_pin(110, "x_ldd[11]"), - pinctrl_pin(111, "x_ldd[12]"), - pinctrl_pin(112, "x_ldd[13]"), - pinctrl_pin(113, "x_ldd[14]"), - pinctrl_pin(114, "x_ldd[15]"), - - pinctrl_pin(115, "x_usb1_dp"), - pinctrl_pin(116, "x_usb1_dn"), -}; - -static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { - { - .group = 3, - .mask = bit(0) | bit(1) | bit(2) | bit(3) | bit(4) | bit(5) | - bit(6) | bit(7) | bit(8) | bit(9) | bit(10) | bit(11) | - bit(12) | bit(13) | bit(14) | bit(15) | bit(16) | - bit(17) | bit(18), - }, { - .group = 2, - .mask = bit(31), - }, -}; - -static const struct sirfsoc_padmux lcd_16bits_padmux = { - .muxmask_counts = array_size(lcd_16bits_sirfsoc_muxmask), - .muxmask = lcd_16bits_sirfsoc_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(4), - .funcval = 0, -}; - -static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102, - 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; - -static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = { - { - .group = 3, - .mask = bit(0) | bit(1) | bit(2) | bit(3) | bit(4) | bit(5) | - bit(6) | bit(7) | bit(8) | bit(9) | bit(10) | bit(11) | - bit(12) | bit(13) | bit(14) | bit(15) | bit(16) | - bit(17) | bit(18), - }, { - .group = 2, - .mask = bit(31), - }, { - .group = 0, - .mask = bit(16) | bit(17), - }, -}; - -static const struct sirfsoc_padmux lcd_18bits_padmux = { - .muxmask_counts = array_size(lcd_18bits_muxmask), - .muxmask = lcd_18bits_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(4), - .funcval = 0, -}; - -static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100, - 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114}; - -static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = { - { - .group = 3, - .mask = bit(0) | bit(1) | bit(2) | bit(3) | bit(4) | bit(5) | - bit(6) | bit(7) | bit(8) | bit(9) | bit(10) | bit(11) | - bit(12) | bit(13) | bit(14) | bit(15) | bit(16) | - bit(17) | bit(18), - }, { - .group = 2, - .mask = bit(31), - }, { - .group = 0, - .mask = bit(16) | bit(17) | bit(18) | bit(19) | bit(20) | - bit(21) | bit(22) | bit(23), - }, -}; - -static const struct sirfsoc_padmux lcd_24bits_padmux = { - .muxmask_counts = array_size(lcd_24bits_muxmask), - .muxmask = lcd_24bits_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(4), - .funcval = 0, -}; - -static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, - 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, - 110, 111, 112, 113, 114 }; - -static const struct sirfsoc_muxmask lcdrom_muxmask[] = { - { - .group = 3, - .mask = bit(0) | bit(1) | bit(2) | bit(3) | bit(4) | bit(5) | - bit(6) | bit(7) | bit(8) | bit(9) | bit(10) | bit(11) | - bit(12) | bit(13) | bit(14) | bit(15) | bit(16) | - bit(17) | bit(18), - }, { - .group = 2, - .mask = bit(31), - }, { - .group = 0, - .mask = bit(23), - }, -}; - -static const struct sirfsoc_padmux lcdrom_padmux = { - .muxmask_counts = array_size(lcdrom_muxmask), - .muxmask = lcdrom_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(4), - .funcval = bit(4), -}; - -static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102, - 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; - -static const struct sirfsoc_muxmask uart0_muxmask[] = { - { - .group = 2, - .mask = bit(4) | bit(5), - }, { - .group = 1, - .mask = bit(23) | bit(28), - }, -}; - -static const struct sirfsoc_padmux uart0_padmux = { - .muxmask_counts = array_size(uart0_muxmask), - .muxmask = uart0_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(9), - .funcval = bit(9), -}; - -static const unsigned uart0_pins[] = { 55, 60, 68, 69 }; - -static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = { - { - .group = 2, - .mask = bit(4) | bit(5), - }, -}; - -static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = { - .muxmask_counts = array_size(uart0_nostreamctrl_muxmask), - .muxmask = uart0_nostreamctrl_muxmask, -}; - -static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 }; - -static const struct sirfsoc_muxmask uart1_muxmask[] = { - { - .group = 1, - .mask = bit(15) | bit(17), - }, -}; - -static const struct sirfsoc_padmux uart1_padmux = { - .muxmask_counts = array_size(uart1_muxmask), - .muxmask = uart1_muxmask, -}; - -static const unsigned uart1_pins[] = { 47, 49 }; - -static const struct sirfsoc_muxmask uart2_muxmask[] = { - { - .group = 1, - .mask = bit(16) | bit(18) | bit(24) | bit(27), - }, -}; - -static const struct sirfsoc_padmux uart2_padmux = { - .muxmask_counts = array_size(uart2_muxmask), - .muxmask = uart2_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(10), - .funcval = bit(10), -}; - -static const unsigned uart2_pins[] = { 48, 50, 56, 59 }; - -static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = { - { - .group = 1, - .mask = bit(16) | bit(18), - }, -}; - -static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = { - .muxmask_counts = array_size(uart2_nostreamctrl_muxmask), - .muxmask = uart2_nostreamctrl_muxmask, -}; - -static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 }; - -static const struct sirfsoc_muxmask sdmmc3_muxmask[] = { - { - .group = 0, - .mask = bit(30) | bit(31), - }, { - .group = 1, - .mask = bit(0) | bit(1) | bit(2) | bit(3), - }, -}; - -static const struct sirfsoc_padmux sdmmc3_padmux = { - .muxmask_counts = array_size(sdmmc3_muxmask), - .muxmask = sdmmc3_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(7), - .funcval = 0, -}; - -static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 }; - -static const struct sirfsoc_muxmask spi0_muxmask[] = { - { - .group = 1, - .mask = bit(0) | bit(1) | bit(2) | bit(3), - }, -}; - -static const struct sirfsoc_padmux spi0_padmux = { - .muxmask_counts = array_size(spi0_muxmask), - .muxmask = spi0_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(7), - .funcval = bit(7), -}; - -static const unsigned spi0_pins[] = { 32, 33, 34, 35 }; - -static const struct sirfsoc_muxmask sdmmc4_muxmask[] = { - { - .group = 1, - .mask = bit(4) | bit(5) | bit(6) | bit(7) | bit(8) | bit(9), - }, -}; - -static const struct sirfsoc_padmux sdmmc4_padmux = { - .muxmask_counts = array_size(sdmmc4_muxmask), - .muxmask = sdmmc4_muxmask, -}; - -static const unsigned sdmmc4_pins[] = { 36, 37, 38, 39, 40, 41 }; - -static const struct sirfsoc_muxmask cko1_muxmask[] = { - { - .group = 1, - .mask = bit(10), - }, -}; - -static const struct sirfsoc_padmux cko1_padmux = { - .muxmask_counts = array_size(cko1_muxmask), - .muxmask = cko1_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(3), - .funcval = 0, -}; - -static const unsigned cko1_pins[] = { 42 }; - -static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = { - { - .group = 1, - .mask = bit(10), - }, -}; - -static const struct sirfsoc_padmux i2s_mclk_padmux = { - .muxmask_counts = array_size(i2s_mclk_muxmask), - .muxmask = i2s_mclk_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(3), - .funcval = bit(3), -}; - -static const unsigned i2s_mclk_pins[] = { 42 }; - -static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = { - { - .group = 1, - .mask = bit(19), - }, -}; - -static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = { - .muxmask_counts = array_size(i2s_ext_clk_input_muxmask), - .muxmask = i2s_ext_clk_input_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(2), - .funcval = bit(2), -}; - -static const unsigned i2s_ext_clk_input_pins[] = { 51 }; - -static const struct sirfsoc_muxmask i2s_muxmask[] = { - { - .group = 1, - .mask = bit(11) | bit(12) | bit(13) | bit(14), - }, -}; - -static const struct sirfsoc_padmux i2s_padmux = { - .muxmask_counts = array_size(i2s_muxmask), - .muxmask = i2s_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, -}; - -static const unsigned i2s_pins[] = { 43, 44, 45, 46 }; - -static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = { - { - .group = 1, - .mask = bit(11) | bit(12) | bit(14), - }, -}; - -static const struct sirfsoc_padmux i2s_no_din_padmux = { - .muxmask_counts = array_size(i2s_no_din_muxmask), - .muxmask = i2s_no_din_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, -}; - -static const unsigned i2s_no_din_pins[] = { 43, 44, 46 }; - -static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = { - { - .group = 1, - .mask = bit(11) | bit(12) | bit(13) | bit(14) - | bit(23) | bit(28), - }, -}; - -static const struct sirfsoc_padmux i2s_6chn_padmux = { - .muxmask_counts = array_size(i2s_6chn_muxmask), - .muxmask = i2s_6chn_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(1) | bit(9), - .funcval = bit(1) | bit(9), -}; - -static const unsigned i2s_6chn_pins[] = { 43, 44, 45, 46, 55, 60 }; - -static const struct sirfsoc_muxmask ac97_muxmask[] = { - { - .group = 1, - .mask = bit(11) | bit(12) | bit(13) | bit(14), - }, -}; - -static const struct sirfsoc_padmux ac97_padmux = { - .muxmask_counts = array_size(ac97_muxmask), - .muxmask = ac97_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(8), - .funcval = 0, -}; - -static const unsigned ac97_pins[] = { 43, 44, 45, 46 }; - -static const struct sirfsoc_muxmask spi1_muxmask[] = { - { - .group = 1, - .mask = bit(11) | bit(12) | bit(13) | bit(14), - }, -}; - -static const struct sirfsoc_padmux spi1_padmux = { - .muxmask_counts = array_size(spi1_muxmask), - .muxmask = spi1_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(8), - .funcval = bit(8), -}; - -static const unsigned spi1_pins[] = { 43, 44, 45, 46 }; - -static const struct sirfsoc_muxmask sdmmc1_muxmask[] = { - { - .group = 0, - .mask = bit(27) | bit(28) | bit(29), - }, -}; - -static const struct sirfsoc_padmux sdmmc1_padmux = { - .muxmask_counts = array_size(sdmmc1_muxmask), - .muxmask = sdmmc1_muxmask, -}; - -static const unsigned sdmmc1_pins[] = { 27, 28, 29 }; - -static const struct sirfsoc_muxmask gps_muxmask[] = { - { - .group = 0, - .mask = bit(24) | bit(25) | bit(26), - }, -}; - -static const struct sirfsoc_padmux gps_padmux = { - .muxmask_counts = array_size(gps_muxmask), - .muxmask = gps_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(12) | bit(13) | bit(14), - .funcval = bit(12), -}; - -static const unsigned gps_pins[] = { 24, 25, 26 }; - -static const struct sirfsoc_muxmask sdmmc5_muxmask[] = { - { - .group = 0, - .mask = bit(24) | bit(25) | bit(26), - }, -}; - -static const struct sirfsoc_padmux sdmmc5_padmux = { - .muxmask_counts = array_size(sdmmc5_muxmask), - .muxmask = sdmmc5_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(13) | bit(14), - .funcval = bit(13) | bit(14), -}; - -static const unsigned sdmmc5_pins[] = { 24, 25, 26 }; - -static const struct sirfsoc_muxmask usp0_muxmask[] = { - { - .group = 1, - .mask = bit(19) | bit(20) | bit(21) | bit(22) | bit(23), - }, -}; - -static const struct sirfsoc_padmux usp0_padmux = { - .muxmask_counts = array_size(usp0_muxmask), - .muxmask = usp0_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(1) | bit(2) | bit(6) | bit(9), - .funcval = 0, -}; - -static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 }; - -static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = { - { - .group = 1, - .mask = bit(19) | bit(20) | bit(21) | bit(22), - }, -}; - -static const struct sirfsoc_padmux usp0_only_utfs_padmux = { - .muxmask_counts = array_size(usp0_only_utfs_muxmask), - .muxmask = usp0_only_utfs_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(1) | bit(2) | bit(6), - .funcval = 0, -}; - -static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 }; - -static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = { - { - .group = 1, - .mask = bit(19) | bit(20) | bit(21) | bit(23), - }, -}; - -static const struct sirfsoc_padmux usp0_only_urfs_padmux = { - .muxmask_counts = array_size(usp0_only_urfs_muxmask), - .muxmask = usp0_only_urfs_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(1) | bit(2) | bit(9), - .funcval = 0, -}; - -static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 }; - -static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = { - { - .group = 1, - .mask = bit(20) | bit(21), - }, -}; - -static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = { - .muxmask_counts = array_size(usp0_uart_nostreamctrl_muxmask), - .muxmask = usp0_uart_nostreamctrl_muxmask, -}; - -static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 }; - -static const struct sirfsoc_muxmask usp1_muxmask[] = { - { - .group = 1, - .mask = bit(24) | bit(25) | bit(26) | bit(27) | bit(28), - }, -}; - -static const struct sirfsoc_padmux usp1_padmux = { - .muxmask_counts = array_size(usp1_muxmask), - .muxmask = usp1_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(1) | bit(9) | bit(10) | bit(11), - .funcval = 0, -}; - -static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 }; - -static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = { - { - .group = 1, - .mask = bit(25) | bit(26), - }, -}; - -static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = { - .muxmask_counts = array_size(usp1_uart_nostreamctrl_muxmask), - .muxmask = usp1_uart_nostreamctrl_muxmask, -}; - -static const unsigned usp1_uart_nostreamctrl_pins[] = { 57, 58 }; - -static const struct sirfsoc_muxmask usp2_muxmask[] = { - { - .group = 1, - .mask = bit(29) | bit(30) | bit(31), - }, { - .group = 2, - .mask = bit(0) | bit(1), - }, -}; - -static const struct sirfsoc_padmux usp2_padmux = { - .muxmask_counts = array_size(usp2_muxmask), - .muxmask = usp2_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(13) | bit(14), - .funcval = 0, -}; - -static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 }; - -static const struct sirfsoc_muxmask usp2_uart_nostreamctrl_muxmask[] = { - { - .group = 1, - .mask = bit(30) | bit(31), - }, -}; - -static const struct sirfsoc_padmux usp2_uart_nostreamctrl_padmux = { - .muxmask_counts = array_size(usp2_uart_nostreamctrl_muxmask), - .muxmask = usp2_uart_nostreamctrl_muxmask, -}; - -static const unsigned usp2_uart_nostreamctrl_pins[] = { 62, 63 }; - -static const struct sirfsoc_muxmask nand_muxmask[] = { - { - .group = 2, - .mask = bit(2) | bit(3) | bit(28) | bit(29) | bit(30), - }, -}; - -static const struct sirfsoc_padmux nand_padmux = { - .muxmask_counts = array_size(nand_muxmask), - .muxmask = nand_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(5), - .funcval = 0, -}; - -static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 }; - -static const struct sirfsoc_padmux sdmmc0_padmux = { - .muxmask_counts = 0, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(5), - .funcval = 0, -}; - -static const unsigned sdmmc0_pins[] = { }; - -static const struct sirfsoc_muxmask sdmmc2_muxmask[] = { - { - .group = 2, - .mask = bit(2) | bit(3), - }, -}; - -static const struct sirfsoc_padmux sdmmc2_padmux = { - .muxmask_counts = array_size(sdmmc2_muxmask), - .muxmask = sdmmc2_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(5), - .funcval = bit(5), -}; - -static const unsigned sdmmc2_pins[] = { 66, 67 }; - -static const struct sirfsoc_muxmask cko0_muxmask[] = { - { - .group = 2, - .mask = bit(14), - }, -}; - -static const struct sirfsoc_padmux cko0_padmux = { - .muxmask_counts = array_size(cko0_muxmask), - .muxmask = cko0_muxmask, -}; - -static const unsigned cko0_pins[] = { 78 }; - -static const struct sirfsoc_muxmask vip_muxmask[] = { - { - .group = 2, - .mask = bit(15) | bit(16) | bit(17) | bit(18) | bit(19) - | bit(20) | bit(21) | bit(22) | bit(23) | bit(24) | - bit(25), - }, -}; - -static const struct sirfsoc_padmux vip_padmux = { - .muxmask_counts = array_size(vip_muxmask), - .muxmask = vip_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(0), - .funcval = 0, -}; - -static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87, - 88, 89 }; - -static const struct sirfsoc_muxmask i2c0_muxmask[] = { - { - .group = 2, - .mask = bit(26) | bit(27), - }, -}; - -static const struct sirfsoc_padmux i2c0_padmux = { - .muxmask_counts = array_size(i2c0_muxmask), - .muxmask = i2c0_muxmask, -}; - -static const unsigned i2c0_pins[] = { 90, 91 }; - -static const struct sirfsoc_muxmask i2c1_muxmask[] = { - { - .group = 0, - .mask = bit(13) | bit(15), - }, -}; - -static const struct sirfsoc_padmux i2c1_padmux = { - .muxmask_counts = array_size(i2c1_muxmask), - .muxmask = i2c1_muxmask, -}; - -static const unsigned i2c1_pins[] = { 13, 15 }; - -static const struct sirfsoc_muxmask viprom_muxmask[] = { - { - .group = 2, - .mask = bit(15) | bit(16) | bit(17) | bit(18) | bit(19) - | bit(20) | bit(21) | bit(22) | bit(23) | bit(24) | - bit(25), - }, { - .group = 0, - .mask = bit(12), - }, -}; - -static const struct sirfsoc_padmux viprom_padmux = { - .muxmask_counts = array_size(viprom_muxmask), - .muxmask = viprom_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(0), - .funcval = bit(0), -}; - -static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86, - 87, 88, 89 }; - -static const struct sirfsoc_muxmask pwm0_muxmask[] = { - { - .group = 0, - .mask = bit(4), - }, -}; - -static const struct sirfsoc_padmux pwm0_padmux = { - .muxmask_counts = array_size(pwm0_muxmask), - .muxmask = pwm0_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(12), - .funcval = 0, -}; - -static const unsigned pwm0_pins[] = { 4 }; - -static const struct sirfsoc_muxmask pwm1_muxmask[] = { - { - .group = 0, - .mask = bit(5), - }, -}; - -static const struct sirfsoc_padmux pwm1_padmux = { - .muxmask_counts = array_size(pwm1_muxmask), - .muxmask = pwm1_muxmask, -}; - -static const unsigned pwm1_pins[] = { 5 }; - -static const struct sirfsoc_muxmask pwm2_muxmask[] = { - { - .group = 0, - .mask = bit(6), - }, -}; - -static const struct sirfsoc_padmux pwm2_padmux = { - .muxmask_counts = array_size(pwm2_muxmask), - .muxmask = pwm2_muxmask, -}; - -static const unsigned pwm2_pins[] = { 6 }; - -static const struct sirfsoc_muxmask pwm3_muxmask[] = { - { - .group = 0, - .mask = bit(7), - }, -}; - -static const struct sirfsoc_padmux pwm3_padmux = { - .muxmask_counts = array_size(pwm3_muxmask), - .muxmask = pwm3_muxmask, -}; - -static const unsigned pwm3_pins[] = { 7 }; - -static const struct sirfsoc_muxmask warm_rst_muxmask[] = { - { - .group = 0, - .mask = bit(8), - }, -}; - -static const struct sirfsoc_padmux warm_rst_padmux = { - .muxmask_counts = array_size(warm_rst_muxmask), - .muxmask = warm_rst_muxmask, -}; - -static const unsigned warm_rst_pins[] = { 8 }; - -static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = { - { - .group = 1, - .mask = bit(22), - }, -}; -static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = { - .muxmask_counts = array_size(usb0_utmi_drvbus_muxmask), - .muxmask = usb0_utmi_drvbus_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(6), - .funcval = bit(6), /* refer to pad_utmi_drvvbus0_enable */ -}; - -static const unsigned usb0_utmi_drvbus_pins[] = { 54 }; - -static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = { - { - .group = 1, - .mask = bit(27), - }, -}; - -static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = { - .muxmask_counts = array_size(usb1_utmi_drvbus_muxmask), - .muxmask = usb1_utmi_drvbus_muxmask, - .ctrlreg = sirfsoc_rsc_pin_mux, - .funcmask = bit(11), - .funcval = bit(11), /* refer to pad_utmi_drvvbus1_enable */ -}; - -static const unsigned usb1_utmi_drvbus_pins[] = { 59 }; - -static const struct sirfsoc_padmux usb1_dp_dn_padmux = { - .muxmask_counts = 0, - .ctrlreg = sirfsoc_rsc_usb_uart_share, - .funcmask = bit(2), - .funcval = bit(2), -}; - -static const unsigned usb1_dp_dn_pins[] = { 115, 116 }; - -static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = { - .muxmask_counts = 0, - .ctrlreg = sirfsoc_rsc_usb_uart_share, - .funcmask = bit(2), - .funcval = 0, -}; - -static const unsigned uart1_route_io_usb1_pins[] = { 115, 116 }; - -static const struct sirfsoc_muxmask pulse_count_muxmask[] = { - { - .group = 0, - .mask = bit(9) | bit(10) | bit(11), - }, -}; - -static const struct sirfsoc_padmux pulse_count_padmux = { - .muxmask_counts = array_size(pulse_count_muxmask), - .muxmask = pulse_count_muxmask, -}; - -static const unsigned pulse_count_pins[] = { 9, 10, 11 }; - -static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { - sirfsoc_pin_group("lcd_16bitsgrp", lcd_16bits_pins), - sirfsoc_pin_group("lcd_18bitsgrp", lcd_18bits_pins), - sirfsoc_pin_group("lcd_24bitsgrp", lcd_24bits_pins), - sirfsoc_pin_group("lcdrom_grp", lcdrom_pins), - sirfsoc_pin_group("uart0grp", uart0_pins), - sirfsoc_pin_group("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins), - sirfsoc_pin_group("uart1grp", uart1_pins), - sirfsoc_pin_group("uart2grp", uart2_pins), - sirfsoc_pin_group("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins), - sirfsoc_pin_group("usp0grp", usp0_pins), - sirfsoc_pin_group("usp0_uart_nostreamctrl_grp", - usp0_uart_nostreamctrl_pins), - sirfsoc_pin_group("usp0_only_utfs_grp", usp0_only_utfs_pins), - sirfsoc_pin_group("usp0_only_urfs_grp", usp0_only_urfs_pins), - sirfsoc_pin_group("usp1grp", usp1_pins), - sirfsoc_pin_group("usp1_uart_nostreamctrl_grp", - usp1_uart_nostreamctrl_pins), - sirfsoc_pin_group("usp2grp", usp2_pins), - sirfsoc_pin_group("usp2_uart_nostreamctrl_grp", - usp2_uart_nostreamctrl_pins), - sirfsoc_pin_group("i2c0grp", i2c0_pins), - sirfsoc_pin_group("i2c1grp", i2c1_pins), - sirfsoc_pin_group("pwm0grp", pwm0_pins), - sirfsoc_pin_group("pwm1grp", pwm1_pins), - sirfsoc_pin_group("pwm2grp", pwm2_pins), - sirfsoc_pin_group("pwm3grp", pwm3_pins), - sirfsoc_pin_group("vipgrp", vip_pins), - sirfsoc_pin_group("vipromgrp", viprom_pins), - sirfsoc_pin_group("warm_rstgrp", warm_rst_pins), - sirfsoc_pin_group("cko0grp", cko0_pins), - sirfsoc_pin_group("cko1grp", cko1_pins), - sirfsoc_pin_group("sdmmc0grp", sdmmc0_pins), - sirfsoc_pin_group("sdmmc1grp", sdmmc1_pins), - sirfsoc_pin_group("sdmmc2grp", sdmmc2_pins), - sirfsoc_pin_group("sdmmc3grp", sdmmc3_pins), - sirfsoc_pin_group("sdmmc4grp", sdmmc4_pins), - sirfsoc_pin_group("sdmmc5grp", sdmmc5_pins), - sirfsoc_pin_group("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins), - sirfsoc_pin_group("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins), - sirfsoc_pin_group("usb1_dp_dngrp", usb1_dp_dn_pins), - sirfsoc_pin_group("uart1_route_io_usb1grp", uart1_route_io_usb1_pins), - sirfsoc_pin_group("pulse_countgrp", pulse_count_pins), - sirfsoc_pin_group("i2smclkgrp", i2s_mclk_pins), - sirfsoc_pin_group("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins), - sirfsoc_pin_group("i2sgrp", i2s_pins), - sirfsoc_pin_group("i2s_no_dingrp", i2s_no_din_pins), - sirfsoc_pin_group("i2s_6chngrp", i2s_6chn_pins), - sirfsoc_pin_group("ac97grp", ac97_pins), - sirfsoc_pin_group("nandgrp", nand_pins), - sirfsoc_pin_group("spi0grp", spi0_pins), - sirfsoc_pin_group("spi1grp", spi1_pins), - sirfsoc_pin_group("gpsgrp", gps_pins), -}; - -static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" }; -static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" }; -static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" }; -static const char * const lcdromgrp[] = { "lcdromgrp" }; -static const char * const uart0grp[] = { "uart0grp" }; -static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" }; -static const char * const uart1grp[] = { "uart1grp" }; -static const char * const uart2grp[] = { "uart2grp" }; -static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" }; -static const char * const usp0grp[] = { "usp0grp" }; -static const char * const usp0_uart_nostreamctrl_grp[] = { - "usp0_uart_nostreamctrl_grp" -}; -static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" }; -static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" }; -static const char * const usp1grp[] = { "usp1grp" }; -static const char * const usp1_uart_nostreamctrl_grp[] = { - "usp1_uart_nostreamctrl_grp" -}; -static const char * const usp2grp[] = { "usp2grp" }; -static const char * const usp2_uart_nostreamctrl_grp[] = { - "usp2_uart_nostreamctrl_grp" -}; -static const char * const i2c0grp[] = { "i2c0grp" }; -static const char * const i2c1grp[] = { "i2c1grp" }; -static const char * const pwm0grp[] = { "pwm0grp" }; -static const char * const pwm1grp[] = { "pwm1grp" }; -static const char * const pwm2grp[] = { "pwm2grp" }; -static const char * const pwm3grp[] = { "pwm3grp" }; -static const char * const vipgrp[] = { "vipgrp" }; -static const char * const vipromgrp[] = { "vipromgrp" }; -static const char * const warm_rstgrp[] = { "warm_rstgrp" }; -static const char * const cko0grp[] = { "cko0grp" }; -static const char * const cko1grp[] = { "cko1grp" }; -static const char * const sdmmc0grp[] = { "sdmmc0grp" }; -static const char * const sdmmc1grp[] = { "sdmmc1grp" }; -static const char * const sdmmc2grp[] = { "sdmmc2grp" }; -static const char * const sdmmc3grp[] = { "sdmmc3grp" }; -static const char * const sdmmc4grp[] = { "sdmmc4grp" }; -static const char * const sdmmc5grp[] = { "sdmmc5grp" }; -static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" }; -static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" }; -static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" }; -static const char * const - uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" }; -static const char * const pulse_countgrp[] = { "pulse_countgrp" }; -static const char * const i2smclkgrp[] = { "i2smclkgrp" }; -static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" }; -static const char * const i2sgrp[] = { "i2sgrp" }; -static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" }; -static const char * const i2s_6chngrp[] = { "i2s_6chngrp" }; -static const char * const ac97grp[] = { "ac97grp" }; -static const char * const nandgrp[] = { "nandgrp" }; -static const char * const spi0grp[] = { "spi0grp" }; -static const char * const spi1grp[] = { "spi1grp" }; -static const char * const gpsgrp[] = { "gpsgrp" }; - -static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { - sirfsoc_pmx_function("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux), - sirfsoc_pmx_function("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux), - sirfsoc_pmx_function("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux), - sirfsoc_pmx_function("lcdrom", lcdromgrp, lcdrom_padmux), - sirfsoc_pmx_function("uart0", uart0grp, uart0_padmux), - sirfsoc_pmx_function("uart0_nostreamctrl", - uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux), - sirfsoc_pmx_function("uart1", uart1grp, uart1_padmux), - sirfsoc_pmx_function("uart2", uart2grp, uart2_padmux), - sirfsoc_pmx_function("uart2_nostreamctrl", - uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux), - sirfsoc_pmx_function("usp0", usp0grp, usp0_padmux), - sirfsoc_pmx_function("usp0_uart_nostreamctrl", - usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux), - sirfsoc_pmx_function("usp0_only_utfs", - usp0_only_utfs_grp, usp0_only_utfs_padmux), - sirfsoc_pmx_function("usp0_only_urfs", - usp0_only_urfs_grp, usp0_only_urfs_padmux), - sirfsoc_pmx_function("usp1", usp1grp, usp1_padmux), - sirfsoc_pmx_function("usp1_uart_nostreamctrl", - usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux), - sirfsoc_pmx_function("usp2", usp2grp, usp2_padmux), - sirfsoc_pmx_function("usp2_uart_nostreamctrl", - usp2_uart_nostreamctrl_grp, usp2_uart_nostreamctrl_padmux), - sirfsoc_pmx_function("i2c0", i2c0grp, i2c0_padmux), - sirfsoc_pmx_function("i2c1", i2c1grp, i2c1_padmux), - sirfsoc_pmx_function("pwm0", pwm0grp, pwm0_padmux), - sirfsoc_pmx_function("pwm1", pwm1grp, pwm1_padmux), - sirfsoc_pmx_function("pwm2", pwm2grp, pwm2_padmux), - sirfsoc_pmx_function("pwm3", pwm3grp, pwm3_padmux), - sirfsoc_pmx_function("vip", vipgrp, vip_padmux), - sirfsoc_pmx_function("viprom", vipromgrp, viprom_padmux), - sirfsoc_pmx_function("warm_rst", warm_rstgrp, warm_rst_padmux), - sirfsoc_pmx_function("cko0", cko0grp, cko0_padmux), - sirfsoc_pmx_function("cko1", cko1grp, cko1_padmux), - sirfsoc_pmx_function("sdmmc0", sdmmc0grp, sdmmc0_padmux), - sirfsoc_pmx_function("sdmmc1", sdmmc1grp, sdmmc1_padmux), - sirfsoc_pmx_function("sdmmc2", sdmmc2grp, sdmmc2_padmux), - sirfsoc_pmx_function("sdmmc3", sdmmc3grp, sdmmc3_padmux), - sirfsoc_pmx_function("sdmmc4", sdmmc4grp, sdmmc4_padmux), - sirfsoc_pmx_function("sdmmc5", sdmmc5grp, sdmmc5_padmux), - sirfsoc_pmx_function("usb0_utmi_drvbus", - usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux), - sirfsoc_pmx_function("usb1_utmi_drvbus", - usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), - sirfsoc_pmx_function("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux), - sirfsoc_pmx_function("uart1_route_io_usb1", - uart1_route_io_usb1grp, uart1_route_io_usb1_padmux), - sirfsoc_pmx_function("pulse_count", pulse_countgrp, pulse_count_padmux), - sirfsoc_pmx_function("i2s_mclk", i2smclkgrp, i2s_mclk_padmux), - sirfsoc_pmx_function("i2s_ext_clk_input", i2s_ext_clk_inputgrp, - i2s_ext_clk_input_padmux), - sirfsoc_pmx_function("i2s", i2sgrp, i2s_padmux), - sirfsoc_pmx_function("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux), - sirfsoc_pmx_function("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux), - sirfsoc_pmx_function("ac97", ac97grp, ac97_padmux), - sirfsoc_pmx_function("nand", nandgrp, nand_padmux), - sirfsoc_pmx_function("spi0", spi0grp, spi0_padmux), - sirfsoc_pmx_function("spi1", spi1grp, spi1_padmux), - sirfsoc_pmx_function("gps", gpsgrp, gps_padmux), -}; - -struct sirfsoc_pinctrl_data prima2_pinctrl_data = { - (struct pinctrl_pin_desc *)sirfsoc_pads, - array_size(sirfsoc_pads), - (struct sirfsoc_pin_group *)sirfsoc_pin_groups, - array_size(sirfsoc_pin_groups), - (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions, - array_size(sirfsoc_pmx_functions), -}; - diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-or-later -/* - * pinmux driver for csr sirfprimaii - * - * authors: - * rongjun ying <rongjun.ying@csr.com> - * yuping luo <yuping.luo@csr.com> - * barry song <baohua.song@csr.com> - * - * copyright (c) 2011 - 2014 cambridge silicon radio limited, a csr plc group - * company. - */ - -#include <linux/init.h> -#include <linux/irq.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/slab.h> -#include <linux/err.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/consumer.h> -#include <linux/pinctrl/machine.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> -#include <linux/of_platform.h> -#include <linux/bitops.h> -#include <linux/gpio/driver.h> -#include <linux/of_gpio.h> - -#include "pinctrl-sirf.h" - -#define driver_name "pinmux-sirf" - -struct sirfsoc_gpio_bank { - int id; - int parent_irq; - spinlock_t lock; -}; - -struct sirfsoc_gpio_chip { - struct of_mm_gpio_chip chip; - struct sirfsoc_gpio_bank sgpio_bank[sirfsoc_gpio_no_of_banks]; - spinlock_t lock; -}; - -static struct sirfsoc_pin_group *sirfsoc_pin_groups; -static int sirfsoc_pingrp_cnt; - -static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev) -{ - return sirfsoc_pingrp_cnt; -} - -static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - return sirfsoc_pin_groups[selector].name; -} - -static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, - unsigned selector, - const unsigned **pins, - unsigned *num_pins) -{ - *pins = sirfsoc_pin_groups[selector].pins; - *num_pins = sirfsoc_pin_groups[selector].num_pins; - return 0; -} - -static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned offset) -{ - seq_printf(s, " " driver_name); -} - -static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, unsigned *num_maps) -{ - struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev); - struct device_node *np; - struct property *prop; - const char *function, *group; - int ret, index = 0, count = 0; - - /* calculate number of maps required */ - for_each_child_of_node(np_config, np) { - ret = of_property_read_string(np, "sirf,function", &function); - if (ret < 0) { - of_node_put(np); - return ret; - } - - ret = of_property_count_strings(np, "sirf,pins"); - if (ret < 0) { - of_node_put(np); - return ret; - } - - count += ret; - } - - if (!count) { - dev_err(spmx->dev, "no child nodes passed via dt "); - return -enodev; - } - - *map = kcalloc(count, sizeof(**map), gfp_kernel); - if (!*map) - return -enomem; - - for_each_child_of_node(np_config, np) { - of_property_read_string(np, "sirf,function", &function); - of_property_for_each_string(np, "sirf,pins", prop, group) { - (*map)[index].type = pin_map_type_mux_group; - (*map)[index].data.mux.group = group; - (*map)[index].data.mux.function = function; - index++; - } - } - - *num_maps = count; - - return 0; -} - -static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - kfree(map); -} - -static const struct pinctrl_ops sirfsoc_pctrl_ops = { - .get_groups_count = sirfsoc_get_groups_count, - .get_group_name = sirfsoc_get_group_name, - .get_group_pins = sirfsoc_get_group_pins, - .pin_dbg_show = sirfsoc_pin_dbg_show, - .dt_node_to_map = sirfsoc_dt_node_to_map, - .dt_free_map = sirfsoc_dt_free_map, -}; - -static struct sirfsoc_pmx_func *sirfsoc_pmx_functions; -static int sirfsoc_pmxfunc_cnt; - -static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, - unsigned selector, bool enable) -{ - int i; - const struct sirfsoc_padmux *mux = - sirfsoc_pmx_functions[selector].padmux; - const struct sirfsoc_muxmask *mask = mux->muxmask; - - for (i = 0; i < mux->muxmask_counts; i++) { - u32 muxval; - muxval = readl(spmx->gpio_virtbase + - sirfsoc_gpio_pad_en(mask[i].group)); - if (enable) - muxval = muxval & ~mask[i].mask; - else - muxval = muxval | mask[i].mask; - writel(muxval, spmx->gpio_virtbase + - sirfsoc_gpio_pad_en(mask[i].group)); - } - - if (mux->funcmask && enable) { - u32 func_en_val; - - func_en_val = - readl(spmx->rsc_virtbase + mux->ctrlreg); - func_en_val = - (func_en_val & ~mux->funcmask) | (mux->funcval); - writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg); - } -} - -static int sirfsoc_pinmux_set_mux(struct pinctrl_dev *pmxdev, - unsigned selector, - unsigned group) -{ - struct sirfsoc_pmx *spmx; - - spmx = pinctrl_dev_get_drvdata(pmxdev); - sirfsoc_pinmux_endisable(spmx, selector, true); - - return 0; -} - -static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev) -{ - return sirfsoc_pmxfunc_cnt; -} - -static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - return sirfsoc_pmx_functions[selector].name; -} - -static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, - unsigned selector, - const char * const **groups, - unsigned * const num_groups) -{ - *groups = sirfsoc_pmx_functions[selector].groups; - *num_groups = sirfsoc_pmx_functions[selector].num_groups; - return 0; -} - -static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, - struct pinctrl_gpio_range *range, unsigned offset) -{ - struct sirfsoc_pmx *spmx; - - int group = range->id; - - u32 muxval; - - spmx = pinctrl_dev_get_drvdata(pmxdev); - - muxval = readl(spmx->gpio_virtbase + - sirfsoc_gpio_pad_en(group)); - muxval = muxval | (1 << (offset - range->pin_base)); - writel(muxval, spmx->gpio_virtbase + - sirfsoc_gpio_pad_en(group)); - - return 0; -} - -static const struct pinmux_ops sirfsoc_pinmux_ops = { - .set_mux = sirfsoc_pinmux_set_mux, - .get_functions_count = sirfsoc_pinmux_get_funcs_count, - .get_function_name = sirfsoc_pinmux_get_func_name, - .get_function_groups = sirfsoc_pinmux_get_groups, - .gpio_request_enable = sirfsoc_pinmux_request_gpio, -}; - -static struct pinctrl_desc sirfsoc_pinmux_desc = { - .name = driver_name, - .pctlops = &sirfsoc_pctrl_ops, - .pmxops = &sirfsoc_pinmux_ops, - .owner = this_module, -}; - -static void __iomem *sirfsoc_rsc_of_iomap(void) -{ - const struct of_device_id rsc_ids[] = { - { .compatible = "sirf,prima2-rsc" }, - {} - }; - struct device_node *np; - - np = of_find_matching_node(null, rsc_ids); - if (!np) - panic("unable to find compatible rsc node in dtb "); - - return of_iomap(np, 0); -} - -static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc, - const struct of_phandle_args *gpiospec, - u32 *flags) -{ - if (gpiospec->args[0] > sirfsoc_gpio_no_of_banks * sirfsoc_gpio_bank_size) - return -einval; - - if (flags) - *flags = gpiospec->args[1]; - - return gpiospec->args[0]; -} - -static const struct of_device_id pinmux_ids[] = { - { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, }, - { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, }, - {} -}; - -static int sirfsoc_pinmux_probe(struct platform_device *pdev) -{ - int ret; - struct sirfsoc_pmx *spmx; - struct device_node *np = pdev->dev.of_node; - const struct sirfsoc_pinctrl_data *pdata; - - /* create state holders etc for this driver */ - spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), gfp_kernel); - if (!spmx) - return -enomem; - - spmx->dev = &pdev->dev; - - platform_set_drvdata(pdev, spmx); - - spmx->gpio_virtbase = of_iomap(np, 0); - if (!spmx->gpio_virtbase) { - dev_err(&pdev->dev, "can't map gpio registers "); - return -enomem; - } - - spmx->rsc_virtbase = sirfsoc_rsc_of_iomap(); - if (!spmx->rsc_virtbase) { - ret = -enomem; - dev_err(&pdev->dev, "can't map rsc registers "); - goto out_no_rsc_remap; - } - - pdata = of_match_node(pinmux_ids, np)->data; - sirfsoc_pin_groups = pdata->grps; - sirfsoc_pingrp_cnt = pdata->grps_cnt; - sirfsoc_pmx_functions = pdata->funcs; - sirfsoc_pmxfunc_cnt = pdata->funcs_cnt; - sirfsoc_pinmux_desc.pins = pdata->pads; - sirfsoc_pinmux_desc.npins = pdata->pads_cnt; - - - /* now register the pin controller and all pins it handles */ - spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx); - if (is_err(spmx->pmx)) { - dev_err(&pdev->dev, "could not register sirfsoc pinmux driver "); - ret = ptr_err(spmx->pmx); - goto out_no_pmx; - } - - dev_info(&pdev->dev, "initialized sirfsoc pinmux driver "); - - return 0; - -out_no_pmx: - iounmap(spmx->rsc_virtbase); -out_no_rsc_remap: - iounmap(spmx->gpio_virtbase); - return ret; -} - -#ifdef config_pm_sleep -static int sirfsoc_pinmux_suspend_noirq(struct device *dev) -{ - int i, j; - struct sirfsoc_pmx *spmx = dev_get_drvdata(dev); - - for (i = 0; i < sirfsoc_gpio_no_of_banks; i++) { - for (j = 0; j < sirfsoc_gpio_bank_size; j++) { - spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase + - sirfsoc_gpio_ctrl(i, j)); - } - spmx->ints_regs[i] = readl(spmx->gpio_virtbase + - sirfsoc_gpio_int_status(i)); - spmx->paden_regs[i] = readl(spmx->gpio_virtbase + - sirfsoc_gpio_pad_en(i)); - } - spmx->dspen_regs = readl(spmx->gpio_virtbase + sirfsoc_gpio_dsp_en0); - - for (i = 0; i < 3; i++) - spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i); - - return 0; -} - -static int sirfsoc_pinmux_resume_noirq(struct device *dev) -{ - int i, j; - struct sirfsoc_pmx *spmx = dev_get_drvdata(dev); - - for (i = 0; i < sirfsoc_gpio_no_of_banks; i++) { - for (j = 0; j < sirfsoc_gpio_bank_size; j++) { - writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase + - sirfsoc_gpio_ctrl(i, j)); - } - writel(spmx->ints_regs[i], spmx->gpio_virtbase + - sirfsoc_gpio_int_status(i)); - writel(spmx->paden_regs[i], spmx->gpio_virtbase + - sirfsoc_gpio_pad_en(i)); - } - writel(spmx->dspen_regs, spmx->gpio_virtbase + sirfsoc_gpio_dsp_en0); - - for (i = 0; i < 3; i++) - writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i); - - return 0; -} - -static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = { - .suspend_noirq = sirfsoc_pinmux_suspend_noirq, - .resume_noirq = sirfsoc_pinmux_resume_noirq, - .freeze_noirq = sirfsoc_pinmux_suspend_noirq, - .restore_noirq = sirfsoc_pinmux_resume_noirq, -}; -#endif - -static struct platform_driver sirfsoc_pinmux_driver = { - .driver = { - .name = driver_name, - .of_match_table = pinmux_ids, -#ifdef config_pm_sleep - .pm = &sirfsoc_pinmux_pm_ops, -#endif - }, - .probe = sirfsoc_pinmux_probe, -}; - -static int __init sirfsoc_pinmux_init(void) -{ - return platform_driver_register(&sirfsoc_pinmux_driver); -} -arch_initcall(sirfsoc_pinmux_init); - -static inline struct sirfsoc_gpio_bank * -sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset) -{ - return &sgpio->sgpio_bank[offset / sirfsoc_gpio_bank_size]; -} - -static inline int sirfsoc_gpio_to_bankoff(unsigned int offset) -{ - return offset % sirfsoc_gpio_bank_size; -} - -static void sirfsoc_gpio_irq_ack(struct irq_data *d) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc); - struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); - int idx = sirfsoc_gpio_to_bankoff(d->hwirq); - u32 val, offset; - unsigned long flags; - - offset = sirfsoc_gpio_ctrl(bank->id, idx); - - spin_lock_irqsave(&sgpio->lock, flags); - - val = readl(sgpio->chip.regs + offset); - - writel(val, sgpio->chip.regs + offset); - - spin_unlock_irqrestore(&sgpio->lock, flags); -} - -static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio, - struct sirfsoc_gpio_bank *bank, - int idx) -{ - u32 val, offset; - unsigned long flags; - - offset = sirfsoc_gpio_ctrl(bank->id, idx); - - spin_lock_irqsave(&sgpio->lock, flags); - - val = readl(sgpio->chip.regs + offset); - val &= ~sirfsoc_gpio_ctl_intr_en_mask; - val &= ~sirfsoc_gpio_ctl_intr_sts_mask; - writel(val, sgpio->chip.regs + offset); - - spin_unlock_irqrestore(&sgpio->lock, flags); -} - -static void sirfsoc_gpio_irq_mask(struct irq_data *d) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc); - struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); - - __sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % sirfsoc_gpio_bank_size); -} - -static void sirfsoc_gpio_irq_unmask(struct irq_data *d) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc); - struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); - int idx = sirfsoc_gpio_to_bankoff(d->hwirq); - u32 val, offset; - unsigned long flags; - - offset = sirfsoc_gpio_ctrl(bank->id, idx); - - spin_lock_irqsave(&sgpio->lock, flags); - - val = readl(sgpio->chip.regs + offset); - val &= ~sirfsoc_gpio_ctl_intr_sts_mask; - val |= sirfsoc_gpio_ctl_intr_en_mask; - writel(val, sgpio->chip.regs + offset); - - spin_unlock_irqrestore(&sgpio->lock, flags); -} - -static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc); - struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); - int idx = sirfsoc_gpio_to_bankoff(d->hwirq); - u32 val, offset; - unsigned long flags; - - offset = sirfsoc_gpio_ctrl(bank->id, idx); - - spin_lock_irqsave(&sgpio->lock, flags); - - val = readl(sgpio->chip.regs + offset); - val &= ~(sirfsoc_gpio_ctl_intr_sts_mask | sirfsoc_gpio_ctl_out_en_mask); - - switch (type) { - case irq_type_none: - break; - case irq_type_edge_rising: - val |= sirfsoc_gpio_ctl_intr_high_mask | - sirfsoc_gpio_ctl_intr_type_mask; - val &= ~sirfsoc_gpio_ctl_intr_low_mask; - break; - case irq_type_edge_falling: - val &= ~sirfsoc_gpio_ctl_intr_high_mask; - val |= sirfsoc_gpio_ctl_intr_low_mask | - sirfsoc_gpio_ctl_intr_type_mask; - break; - case irq_type_edge_both: - val |= sirfsoc_gpio_ctl_intr_high_mask | - sirfsoc_gpio_ctl_intr_low_mask | - sirfsoc_gpio_ctl_intr_type_mask; - break; - case irq_type_level_low: - val &= ~(sirfsoc_gpio_ctl_intr_high_mask | - sirfsoc_gpio_ctl_intr_type_mask); - val |= sirfsoc_gpio_ctl_intr_low_mask; - break; - case irq_type_level_high: - val |= sirfsoc_gpio_ctl_intr_high_mask; - val &= ~(sirfsoc_gpio_ctl_intr_low_mask | - sirfsoc_gpio_ctl_intr_type_mask); - break; - } - - writel(val, sgpio->chip.regs + offset); - - spin_unlock_irqrestore(&sgpio->lock, flags); - - return 0; -} - -static struct irq_chip sirfsoc_irq_chip = { - .name = "sirf-gpio-irq", - .irq_ack = sirfsoc_gpio_irq_ack, - .irq_mask = sirfsoc_gpio_irq_mask, - .irq_unmask = sirfsoc_gpio_irq_unmask, - .irq_set_type = sirfsoc_gpio_irq_type, -}; - -static void sirfsoc_gpio_handle_irq(struct irq_desc *desc) -{ - unsigned int irq = irq_desc_get_irq(desc); - struct gpio_chip *gc = irq_desc_get_handler_data(desc); - struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc); - struct sirfsoc_gpio_bank *bank; - u32 status, ctrl; - int idx = 0; - struct irq_chip *chip = irq_desc_get_chip(desc); - int i; - - for (i = 0; i < sirfsoc_gpio_no_of_banks; i++) { - bank = &sgpio->sgpio_bank[i]; - if (bank->parent_irq == irq) - break; - } - bug_on(i == sirfsoc_gpio_no_of_banks); - - chained_irq_enter(chip, desc); - - status = readl(sgpio->chip.regs + sirfsoc_gpio_int_status(bank->id)); - if (!status) { - printk(kern_warning - "%s: gpio id %d status %#x no interrupt is flagged ", - __func__, bank->id, status); - handle_bad_irq(desc); - return; - } - - while (status) { - ctrl = readl(sgpio->chip.regs + sirfsoc_gpio_ctrl(bank->id, idx)); - - /* - * here we must check whether the corresponding gpio's interrupt - * has been enabled, otherwise just skip it - */ - if ((status & 0x1) && (ctrl & sirfsoc_gpio_ctl_intr_en_mask)) { - pr_debug("%s: gpio id %d idx %d happens ", - __func__, bank->id, idx); - generic_handle_irq(irq_find_mapping(gc->irq.domain, idx + - bank->id * sirfsoc_gpio_bank_size)); - } - - idx++; - status = status >> 1; - } - - chained_irq_exit(chip, desc); -} - -static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_chip *sgpio, - unsigned ctrl_offset) -{ - u32 val; - - val = readl(sgpio->chip.regs + ctrl_offset); - val &= ~sirfsoc_gpio_ctl_out_en_mask; - writel(val, sgpio->chip.regs + ctrl_offset); -} - -static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset) -{ - struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip); - struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); - unsigned long flags; - - if (pinctrl_gpio_request(chip->base + offset)) - return -enodev; - - spin_lock_irqsave(&bank->lock, flags); - - /* - * default status: - * set direction as input and mask irq - */ - sirfsoc_gpio_set_input(sgpio, sirfsoc_gpio_ctrl(bank->id, offset)); - __sirfsoc_gpio_irq_mask(sgpio, bank, offset); - - spin_unlock_irqrestore(&bank->lock, flags); - - return 0; -} - -static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset) -{ - struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip); - struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); - unsigned long flags; - - spin_lock_irqsave(&bank->lock, flags); - - __sirfsoc_gpio_irq_mask(sgpio, bank, offset); - sirfsoc_gpio_set_input(sgpio, sirfsoc_gpio_ctrl(bank->id, offset)); - - spin_unlock_irqrestore(&bank->lock, flags); - - pinctrl_gpio_free(chip->base + offset); -} - -static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) -{ - struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip); - struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio); - int idx = sirfsoc_gpio_to_bankoff(gpio); - unsigned long flags; - unsigned offset; - - offset = sirfsoc_gpio_ctrl(bank->id, idx); - - spin_lock_irqsave(&bank->lock, flags); - - sirfsoc_gpio_set_input(sgpio, offset); - - spin_unlock_irqrestore(&bank->lock, flags); - - return 0; -} - -static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio, - struct sirfsoc_gpio_bank *bank, - unsigned offset, - int value) -{ - u32 out_ctrl; - unsigned long flags; - - spin_lock_irqsave(&bank->lock, flags); - - out_ctrl = readl(sgpio->chip.regs + offset); - if (value) - out_ctrl |= sirfsoc_gpio_ctl_dataout_mask; - else - out_ctrl &= ~sirfsoc_gpio_ctl_dataout_mask; - - out_ctrl &= ~sirfsoc_gpio_ctl_intr_en_mask; - out_ctrl |= sirfsoc_gpio_ctl_out_en_mask; - writel(out_ctrl, sgpio->chip.regs + offset); - - spin_unlock_irqrestore(&bank->lock, flags); -} - -static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, - unsigned gpio, int value) -{ - struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip); - struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio); - int idx = sirfsoc_gpio_to_bankoff(gpio); - u32 offset; - unsigned long flags; - - offset = sirfsoc_gpio_ctrl(bank->id, idx); - - spin_lock_irqsave(&sgpio->lock, flags); - - sirfsoc_gpio_set_output(sgpio, bank, offset, value); - - spin_unlock_irqrestore(&sgpio->lock, flags); - - return 0; -} - -static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset) -{ - struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip); - struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); - u32 val; - unsigned long flags; - - spin_lock_irqsave(&bank->lock, flags); - - val = readl(sgpio->chip.regs + sirfsoc_gpio_ctrl(bank->id, offset)); - - spin_unlock_irqrestore(&bank->lock, flags); - - return !!(val & sirfsoc_gpio_ctl_datain_mask); -} - -static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset, - int value) -{ - struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip); - struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); - u32 ctrl; - unsigned long flags; - - spin_lock_irqsave(&bank->lock, flags); - - ctrl = readl(sgpio->chip.regs + sirfsoc_gpio_ctrl(bank->id, offset)); - if (value) - ctrl |= sirfsoc_gpio_ctl_dataout_mask; - else - ctrl &= ~sirfsoc_gpio_ctl_dataout_mask; - writel(ctrl, sgpio->chip.regs + sirfsoc_gpio_ctrl(bank->id, offset)); - - spin_unlock_irqrestore(&bank->lock, flags); -} - -static void sirfsoc_gpio_set_pullup(struct sirfsoc_gpio_chip *sgpio, - const u32 *pullups) -{ - int i, n; - const unsigned long *p = (const unsigned long *)pullups; - - for (i = 0; i < sirfsoc_gpio_no_of_banks; i++) { - for_each_set_bit(n, p + i, bits_per_long) { - u32 offset = sirfsoc_gpio_ctrl(i, n); - u32 val = readl(sgpio->chip.regs + offset); - val |= sirfsoc_gpio_ctl_pull_mask; - val |= sirfsoc_gpio_ctl_pull_high; - writel(val, sgpio->chip.regs + offset); - } - } -} - -static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip *sgpio, - const u32 *pulldowns) -{ - int i, n; - const unsigned long *p = (const unsigned long *)pulldowns; - - for (i = 0; i < sirfsoc_gpio_no_of_banks; i++) { - for_each_set_bit(n, p + i, bits_per_long) { - u32 offset = sirfsoc_gpio_ctrl(i, n); - u32 val = readl(sgpio->chip.regs + offset); - val |= sirfsoc_gpio_ctl_pull_mask; - val &= ~sirfsoc_gpio_ctl_pull_high; - writel(val, sgpio->chip.regs + offset); - } - } -} - -static int sirfsoc_gpio_probe(struct device_node *np) -{ - int i, err = 0; - struct sirfsoc_gpio_chip *sgpio; - struct sirfsoc_gpio_bank *bank; - void __iomem *regs; - struct platform_device *pdev; - struct gpio_irq_chip *girq; - - u32 pullups[sirfsoc_gpio_no_of_banks], pulldowns[sirfsoc_gpio_no_of_banks]; - - pdev = of_find_device_by_node(np); - if (!pdev) - return -enodev; - - sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), gfp_kernel); - if (!sgpio) { - err = -enomem; - goto out_put_device; - } - spin_lock_init(&sgpio->lock); - - regs = of_iomap(np, 0); - if (!regs) { - err = -enomem; - goto out_put_device; - } - - sgpio->chip.gc.request = sirfsoc_gpio_request; - sgpio->chip.gc.free = sirfsoc_gpio_free; - sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input; - sgpio->chip.gc.get = sirfsoc_gpio_get_value; - sgpio->chip.gc.direction_output = sirfsoc_gpio_direction_output; - sgpio->chip.gc.set = sirfsoc_gpio_set_value; - sgpio->chip.gc.base = 0; - sgpio->chip.gc.ngpio = sirfsoc_gpio_bank_size * sirfsoc_gpio_no_of_banks; - sgpio->chip.gc.label = kasprintf(gfp_kernel, "%pof", np); - sgpio->chip.gc.of_node = np; - sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate; - sgpio->chip.gc.of_gpio_n_cells = 2; - sgpio->chip.gc.parent = &pdev->dev; - sgpio->chip.regs = regs; - - girq = &sgpio->chip.gc.irq; - girq->chip = &sirfsoc_irq_chip; - girq->parent_handler = sirfsoc_gpio_handle_irq; - girq->num_parents = sirfsoc_gpio_no_of_banks; - girq->parents = devm_kcalloc(&pdev->dev, sirfsoc_gpio_no_of_banks, - sizeof(*girq->parents), - gfp_kernel); - if (!girq->parents) { - err = -enomem; - goto out_put_device; - } - for (i = 0; i < sirfsoc_gpio_no_of_banks; i++) { - bank = &sgpio->sgpio_bank[i]; - spin_lock_init(&bank->lock); - bank->parent_irq = platform_get_irq(pdev, i); - if (bank->parent_irq < 0) { - err = bank->parent_irq; - goto out; - } - girq->parents[i] = bank->parent_irq; - } - girq->default_type = irq_type_none; - girq->handler = handle_level_irq; - - err = gpiochip_add_data(&sgpio->chip.gc, sgpio); - if (err) { - dev_err(&pdev->dev, "%pof: error in probe function with status %d ", - np, err); - goto out; - } - - err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev), - 0, 0, sirfsoc_gpio_bank_size * sirfsoc_gpio_no_of_banks); - if (err) { - dev_err(&pdev->dev, - "could not add gpiochip pin range "); - goto out_no_range; - } - - if (!of_property_read_u32_array(np, "sirf,pullups", pullups, - sirfsoc_gpio_no_of_banks)) - sirfsoc_gpio_set_pullup(sgpio, pullups); - - if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns, - sirfsoc_gpio_no_of_banks)) - sirfsoc_gpio_set_pulldown(sgpio, pulldowns); - - return 0; - -out_no_range: - gpiochip_remove(&sgpio->chip.gc); -out: - iounmap(regs); -out_put_device: - put_device(&pdev->dev); - return err; -} - -static int __init sirfsoc_gpio_init(void) -{ - - struct device_node *np; - - np = of_find_matching_node(null, pinmux_ids); - - if (!np) - return -enodev; - - return sirfsoc_gpio_probe(np); -} -subsys_initcall(sirfsoc_gpio_init); diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.h b/drivers/pinctrl/sirf/pinctrl-sirf.h --- a/drivers/pinctrl/sirf/pinctrl-sirf.h +++ /dev/null -/* spdx-license-identifier: gpl-2.0-or-later */ -/* - * pinmux driver shared headfile for csr sirfsoc - * - * copyright (c) 2011 cambridge silicon radio limited, a csr plc group company. - */ - -#ifndef __pinmux_sirf_h__ -#define __pinmux_sirf_h__ - -#define sirfsoc_num_pads 622 -#define sirfsoc_rsc_usb_uart_share 0 -#define sirfsoc_rsc_pin_mux 0x4 - -#define sirfsoc_gpio_pad_en(g) ((g)*0x100 + 0x84) -#define sirfsoc_gpio_pad_en_clr(g) ((g)*0x100 + 0x90) -#define sirfsoc_gpio_ctrl(g, i) ((g)*0x100 + (i)*4) -#define sirfsoc_gpio_dsp_en0 (0x80) -#define sirfsoc_gpio_int_status(g) ((g)*0x100 + 0x8c) - -#define sirfsoc_gpio_ctl_intr_low_mask 0x1 -#define sirfsoc_gpio_ctl_intr_high_mask 0x2 -#define sirfsoc_gpio_ctl_intr_type_mask 0x4 -#define sirfsoc_gpio_ctl_intr_en_mask 0x8 -#define sirfsoc_gpio_ctl_intr_sts_mask 0x10 -#define sirfsoc_gpio_ctl_out_en_mask 0x20 -#define sirfsoc_gpio_ctl_dataout_mask 0x40 -#define sirfsoc_gpio_ctl_datain_mask 0x80 -#define sirfsoc_gpio_ctl_pull_mask 0x100 -#define sirfsoc_gpio_ctl_pull_high 0x200 -#define sirfsoc_gpio_ctl_dsp_int 0x400 - -#define sirfsoc_gpio_no_of_banks 5 -#define sirfsoc_gpio_bank_size 32 -#define sirfsoc_gpio_num(bank, index) (((bank)*(32)) + (index)) - -/** - * @dev: a pointer back to containing device - * @virtbase: the offset to the controller in virtual memory - */ -struct sirfsoc_pmx { - struct device *dev; - struct pinctrl_dev *pmx; - void __iomem *gpio_virtbase; - void __iomem *rsc_virtbase; - u32 gpio_regs[sirfsoc_gpio_no_of_banks][sirfsoc_gpio_bank_size]; - u32 ints_regs[sirfsoc_gpio_no_of_banks]; - u32 paden_regs[sirfsoc_gpio_no_of_banks]; - u32 dspen_regs; - u32 rsc_regs[3]; -}; - -/* sirfsoc_gpio_pad_en set */ -struct sirfsoc_muxmask { - unsigned long group; - unsigned long mask; -}; - -struct sirfsoc_padmux { - unsigned long muxmask_counts; - const struct sirfsoc_muxmask *muxmask; - /* rsc_pin_mux set */ - unsigned long ctrlreg; - unsigned long funcmask; - unsigned long funcval; -}; - - /** - * struct sirfsoc_pin_group - describes a sirfprimaii pin group - * @name: the name of this specific pin group - * @pins: an array of discrete physical pins used in this group, taken - * from the driver-local pin enumeration space - * @num_pins: the number of pins in this group array, i.e. the number of - * elements in .pins so we can iterate over that array - */ -struct sirfsoc_pin_group { - const char *name; - const unsigned int *pins; - const unsigned num_pins; -}; - -#define sirfsoc_pin_group(n, p) \ - { \ - .name = n, \ - .pins = p, \ - .num_pins = array_size(p), \ - } - -struct sirfsoc_pmx_func { - const char *name; - const char * const *groups; - const unsigned num_groups; - const struct sirfsoc_padmux *padmux; -}; - -#define sirfsoc_pmx_function(n, g, m) \ - { \ - .name = n, \ - .groups = g, \ - .num_groups = array_size(g), \ - .padmux = &m, \ - } - -struct sirfsoc_pinctrl_data { - struct pinctrl_pin_desc *pads; - int pads_cnt; - struct sirfsoc_pin_group *grps; - int grps_cnt; - struct sirfsoc_pmx_func *funcs; - int funcs_cnt; -}; - -extern struct sirfsoc_pinctrl_data prima2_pinctrl_data; -extern struct sirfsoc_pinctrl_data atlas6_pinctrl_data; - -#endif
|
Pin Controllers (pinctrl)
|
c41e02c384f50dd514b904dc2fbf1627e11a6313
|
arnd bergmann barry song baohua kernel org
|
drivers
|
pinctrl
|
bindings, gpio, pinctrl, sirf
|
pinctrl: remove ste u300 driver
|
the st-ericsson u300 platform is getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove ste u300 driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['kconfig', 'c', 'makefile']
| 3
| 0
| 1,118
|
--- diff --git a/drivers/pinctrl/kconfig b/drivers/pinctrl/kconfig --- a/drivers/pinctrl/kconfig +++ b/drivers/pinctrl/kconfig -config pinctrl_u300 - bool "u300 pin controller driver" - depends on arch_u300 - select pinmux - select generic_pinconf - diff --git a/drivers/pinctrl/makefile b/drivers/pinctrl/makefile --- a/drivers/pinctrl/makefile +++ b/drivers/pinctrl/makefile -obj-$(config_pinctrl_u300) += pinctrl-u300.o diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c --- a/drivers/pinctrl/pinctrl-u300.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * driver for the u300 pin controller - * - * based on the original u300 padmux functions - * copyright (c) 2009-2011 st-ericsson ab - * author: martin persson <martin.persson@stericsson.com> - * author: linus walleij <linus.walleij@linaro.org> - * - * the db3350 design and control registers are oriented around pads rather than - * pins, so we enumerate the pads we can mux rather than actual pins. the pads - * are connected to different pins in different packaging types, so it would - * be confusing. - */ -#include <linux/init.h> -#include <linux/module.h> -#include <linux/mod_devicetable.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/slab.h> -#include <linux/err.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinconf-generic.h> -#include "pinctrl-coh901.h" - -/* - * register definitions for the u300 padmux control registers in the - * system controller - */ - -/* pad mux control register 1 (low) 16bit (r/w) */ -#define u300_syscon_pmc1lr 0x007c -#define u300_syscon_pmc1lr_mask 0xffff -#define u300_syscon_pmc1lr_cdi_mask 0xc000 -#define u300_syscon_pmc1lr_cdi_cdi 0x0000 -#define u300_syscon_pmc1lr_cdi_emif 0x4000 -/* for bs335 */ -#define u300_syscon_pmc1lr_cdi_cdi2 0x8000 -#define u300_syscon_pmc1lr_cdi_wcdma_app_gpio 0xc000 -/* for bs365 */ -#define u300_syscon_pmc1lr_cdi_gpio 0x8000 -#define u300_syscon_pmc1lr_cdi_wcdma 0xc000 -/* common defs */ -#define u300_syscon_pmc1lr_pdi_mask 0x3000 -#define u300_syscon_pmc1lr_pdi_pdi 0x0000 -#define u300_syscon_pmc1lr_pdi_egg 0x1000 -#define u300_syscon_pmc1lr_pdi_wcdma 0x3000 -#define u300_syscon_pmc1lr_mmcsd_mask 0x0c00 -#define u300_syscon_pmc1lr_mmcsd_mmcsd 0x0000 -#define u300_syscon_pmc1lr_mmcsd_mspro 0x0400 -#define u300_syscon_pmc1lr_mmcsd_dsp 0x0800 -#define u300_syscon_pmc1lr_mmcsd_wcdma 0x0c00 -#define u300_syscon_pmc1lr_etm_mask 0x0300 -#define u300_syscon_pmc1lr_etm_acc 0x0000 -#define u300_syscon_pmc1lr_etm_app 0x0100 -#define u300_syscon_pmc1lr_emif_1_cs2_mask 0x00c0 -#define u300_syscon_pmc1lr_emif_1_cs2_static 0x0000 -#define u300_syscon_pmc1lr_emif_1_cs2_nfif 0x0040 -#define u300_syscon_pmc1lr_emif_1_cs2_sdram 0x0080 -#define u300_syscon_pmc1lr_emif_1_cs2_static_2gb 0x00c0 -#define u300_syscon_pmc1lr_emif_1_cs1_mask 0x0030 -#define u300_syscon_pmc1lr_emif_1_cs1_static 0x0000 -#define u300_syscon_pmc1lr_emif_1_cs1_nfif 0x0010 -#define u300_syscon_pmc1lr_emif_1_cs1_sdram 0x0020 -#define u300_syscon_pmc1lr_emif_1_cs1_semi 0x0030 -#define u300_syscon_pmc1lr_emif_1_cs0_mask 0x000c -#define u300_syscon_pmc1lr_emif_1_cs0_static 0x0000 -#define u300_syscon_pmc1lr_emif_1_cs0_nfif 0x0004 -#define u300_syscon_pmc1lr_emif_1_cs0_sdram 0x0008 -#define u300_syscon_pmc1lr_emif_1_cs0_semi 0x000c -#define u300_syscon_pmc1lr_emif_1_mask 0x0003 -#define u300_syscon_pmc1lr_emif_1_static 0x0000 -#define u300_syscon_pmc1lr_emif_1_sdram0 0x0001 -#define u300_syscon_pmc1lr_emif_1_sdram1 0x0002 -#define u300_syscon_pmc1lr_emif_1 0x0003 -/* pad mux control register 2 (high) 16bit (r/w) */ -#define u300_syscon_pmc1hr 0x007e -#define u300_syscon_pmc1hr_mask 0xffff -#define u300_syscon_pmc1hr_misc_2_mask 0xc000 -#define u300_syscon_pmc1hr_misc_2_app_gpio 0x0000 -#define u300_syscon_pmc1hr_misc_2_mspro 0x4000 -#define u300_syscon_pmc1hr_misc_2_dsp 0x8000 -#define u300_syscon_pmc1hr_misc_2_aaif 0xc000 -#define u300_syscon_pmc1hr_app_gpio_2_mask 0x3000 -#define u300_syscon_pmc1hr_app_gpio_2_app_gpio 0x0000 -#define u300_syscon_pmc1hr_app_gpio_2_nfif 0x1000 -#define u300_syscon_pmc1hr_app_gpio_2_dsp 0x2000 -#define u300_syscon_pmc1hr_app_gpio_2_aaif 0x3000 -#define u300_syscon_pmc1hr_app_gpio_1_mask 0x0c00 -#define u300_syscon_pmc1hr_app_gpio_1_app_gpio 0x0000 -#define u300_syscon_pmc1hr_app_gpio_1_mmc 0x0400 -#define u300_syscon_pmc1hr_app_gpio_1_dsp 0x0800 -#define u300_syscon_pmc1hr_app_gpio_1_aaif 0x0c00 -#define u300_syscon_pmc1hr_app_spi_cs_2_mask 0x0300 -#define u300_syscon_pmc1hr_app_spi_cs_2_app_gpio 0x0000 -#define u300_syscon_pmc1hr_app_spi_cs_2_spi 0x0100 -#define u300_syscon_pmc1hr_app_spi_cs_2_aaif 0x0300 -#define u300_syscon_pmc1hr_app_spi_cs_1_mask 0x00c0 -#define u300_syscon_pmc1hr_app_spi_cs_1_app_gpio 0x0000 -#define u300_syscon_pmc1hr_app_spi_cs_1_spi 0x0040 -#define u300_syscon_pmc1hr_app_spi_cs_1_aaif 0x00c0 -#define u300_syscon_pmc1hr_app_spi_2_mask 0x0030 -#define u300_syscon_pmc1hr_app_spi_2_app_gpio 0x0000 -#define u300_syscon_pmc1hr_app_spi_2_spi 0x0010 -#define u300_syscon_pmc1hr_app_spi_2_dsp 0x0020 -#define u300_syscon_pmc1hr_app_spi_2_aaif 0x0030 -#define u300_syscon_pmc1hr_app_uart0_2_mask 0x000c -#define u300_syscon_pmc1hr_app_uart0_2_app_gpio 0x0000 -#define u300_syscon_pmc1hr_app_uart0_2_uart0 0x0004 -#define u300_syscon_pmc1hr_app_uart0_2_nfif_cs 0x0008 -#define u300_syscon_pmc1hr_app_uart0_2_aaif 0x000c -#define u300_syscon_pmc1hr_app_uart0_1_mask 0x0003 -#define u300_syscon_pmc1hr_app_uart0_1_app_gpio 0x0000 -#define u300_syscon_pmc1hr_app_uart0_1_uart0 0x0001 -#define u300_syscon_pmc1hr_app_uart0_1_aaif 0x0003 -/* padmux 2 control */ -#define u300_syscon_pmc2r 0x100 -#define u300_syscon_pmc2r_app_misc_0_mask 0x00c0 -#define u300_syscon_pmc2r_app_misc_0_app_gpio 0x0000 -#define u300_syscon_pmc2r_app_misc_0_emif_sdram 0x0040 -#define u300_syscon_pmc2r_app_misc_0_mmc 0x0080 -#define u300_syscon_pmc2r_app_misc_0_cdi2 0x00c0 -#define u300_syscon_pmc2r_app_misc_1_mask 0x0300 -#define u300_syscon_pmc2r_app_misc_1_app_gpio 0x0000 -#define u300_syscon_pmc2r_app_misc_1_emif_sdram 0x0100 -#define u300_syscon_pmc2r_app_misc_1_mmc 0x0200 -#define u300_syscon_pmc2r_app_misc_1_cdi2 0x0300 -#define u300_syscon_pmc2r_app_misc_2_mask 0x0c00 -#define u300_syscon_pmc2r_app_misc_2_app_gpio 0x0000 -#define u300_syscon_pmc2r_app_misc_2_emif_sdram 0x0400 -#define u300_syscon_pmc2r_app_misc_2_mmc 0x0800 -#define u300_syscon_pmc2r_app_misc_2_cdi2 0x0c00 -#define u300_syscon_pmc2r_app_misc_3_mask 0x3000 -#define u300_syscon_pmc2r_app_misc_3_app_gpio 0x0000 -#define u300_syscon_pmc2r_app_misc_3_emif_sdram 0x1000 -#define u300_syscon_pmc2r_app_misc_3_mmc 0x2000 -#define u300_syscon_pmc2r_app_misc_3_cdi2 0x3000 -#define u300_syscon_pmc2r_app_misc_4_mask 0xc000 -#define u300_syscon_pmc2r_app_misc_4_app_gpio 0x0000 -#define u300_syscon_pmc2r_app_misc_4_emif_sdram 0x4000 -#define u300_syscon_pmc2r_app_misc_4_mmc 0x8000 -#define u300_syscon_pmc2r_app_misc_4_acc_gpio 0xc000 -/* todo: more syscon registers missing */ -#define u300_syscon_pmc3r 0x10c -#define u300_syscon_pmc3r_app_misc_11_mask 0xc000 -#define u300_syscon_pmc3r_app_misc_11_spi 0x4000 -#define u300_syscon_pmc3r_app_misc_10_mask 0x3000 -#define u300_syscon_pmc3r_app_misc_10_spi 0x1000 -/* todo: missing other configs */ -#define u300_syscon_pmc4r 0x168 -#define u300_syscon_pmc4r_app_misc_12_mask 0x0003 -#define u300_syscon_pmc4r_app_misc_12_app_gpio 0x0000 -#define u300_syscon_pmc4r_app_misc_13_mask 0x000c -#define u300_syscon_pmc4r_app_misc_13_cdi 0x0000 -#define u300_syscon_pmc4r_app_misc_13_smia 0x0004 -#define u300_syscon_pmc4r_app_misc_13_smia2 0x0008 -#define u300_syscon_pmc4r_app_misc_13_app_gpio 0x000c -#define u300_syscon_pmc4r_app_misc_14_mask 0x0030 -#define u300_syscon_pmc4r_app_misc_14_cdi 0x0000 -#define u300_syscon_pmc4r_app_misc_14_smia 0x0010 -#define u300_syscon_pmc4r_app_misc_14_cdi2 0x0020 -#define u300_syscon_pmc4r_app_misc_14_app_gpio 0x0030 -#define u300_syscon_pmc4r_app_misc_16_mask 0x0300 -#define u300_syscon_pmc4r_app_misc_16_app_gpio_13 0x0000 -#define u300_syscon_pmc4r_app_misc_16_app_uart1_cts 0x0100 -#define u300_syscon_pmc4r_app_misc_16_emif_1_static_cs5_n 0x0200 - -#define driver_name "pinctrl-u300" - -/* - * the db3350 has 467 pads, i have enumerated the pads clockwise around the - * edges of the silicon, finger by finger. ltcorner upper left is pad 0. - * data taken from the padring chart, arranged like this: - * - * 0 ..... 104 - * 466 105 - * . . - * . . - * 358 224 - * 357 .... 225 - */ -#define u300_num_pads 467 - -/* pad names for the pinmux subsystem */ -static const struct pinctrl_pin_desc u300_pads[] = { - /* pads along the top edge of the chip */ - pinctrl_pin(0, "p pad vdd 28"), - pinctrl_pin(1, "p pad gnd 28"), - pinctrl_pin(2, "po sim rst n"), - pinctrl_pin(3, "vssio 25"), - pinctrl_pin(4, "vssa adda esdsub"), - pinctrl_pin(5, "pwr vsscommon"), - pinctrl_pin(6, "pi adc i1 pos"), - pinctrl_pin(7, "pi adc i1 neg"), - pinctrl_pin(8, "pwr vssad0"), - pinctrl_pin(9, "pwr vccad0"), - pinctrl_pin(10, "pi adc q1 neg"), - pinctrl_pin(11, "pi adc q1 pos"), - pinctrl_pin(12, "pwr vddad"), - pinctrl_pin(13, "pwr gndad"), - pinctrl_pin(14, "pi adc i2 pos"), - pinctrl_pin(15, "pi adc i2 neg"), - pinctrl_pin(16, "pwr vssad1"), - pinctrl_pin(17, "pwr vccad1"), - pinctrl_pin(18, "pi adc q2 neg"), - pinctrl_pin(19, "pi adc q2 pos"), - pinctrl_pin(20, "vssa adda esdsub"), - pinctrl_pin(21, "pwr vccgpad"), - pinctrl_pin(22, "pi tx pow"), - pinctrl_pin(23, "pwr vssgpad"), - pinctrl_pin(24, "po dac i pos"), - pinctrl_pin(25, "po dac i neg"), - pinctrl_pin(26, "po dac q pos"), - pinctrl_pin(27, "po dac q neg"), - pinctrl_pin(28, "pwr vssda"), - pinctrl_pin(29, "pwr vccda"), - pinctrl_pin(30, "vssa adda esdsub"), - pinctrl_pin(31, "p pad vddio 11"), - pinctrl_pin(32, "pi pll 26 filtvdd"), - pinctrl_pin(33, "pi pll 26 vcont"), - pinctrl_pin(34, "pwr agndpll2v5 32 13"), - pinctrl_pin(35, "pwr avddpll2v5 32 13"), - pinctrl_pin(36, "vdda pll esd"), - pinctrl_pin(37, "vssa pll esd"), - pinctrl_pin(38, "vss pll"), - pinctrl_pin(39, "vddc pll"), - pinctrl_pin(40, "pwr agndpll2v5 26 60"), - pinctrl_pin(41, "pwr avddpll2v5 26 60"), - pinctrl_pin(42, "pwr avddpll2v5 26 208"), - pinctrl_pin(43, "pwr agndpll2v5 26 208"), - pinctrl_pin(44, "pwr avddpll2v5 13 208"), - pinctrl_pin(45, "pwr agndpll2v5 13 208"), - pinctrl_pin(46, "p pad vssio 11"), - pinctrl_pin(47, "p pad vssio 12"), - pinctrl_pin(48, "pi pow rst n"), - pinctrl_pin(49, "vddc io"), - pinctrl_pin(50, "p pad vddio 16"), - pinctrl_pin(51, "po rf wcdma en 4"), - pinctrl_pin(52, "po rf wcdma en 3"), - pinctrl_pin(53, "po rf wcdma en 2"), - pinctrl_pin(54, "po rf wcdma en 1"), - pinctrl_pin(55, "po rf wcdma en 0"), - pinctrl_pin(56, "po gsm pa enable"), - pinctrl_pin(57, "po rf data strb"), - pinctrl_pin(58, "po rf data2"), - pinctrl_pin(59, "pio rf data1"), - pinctrl_pin(60, "pio rf data0"), - pinctrl_pin(61, "p pad vdd 11"), - pinctrl_pin(62, "p pad gnd 11"), - pinctrl_pin(63, "p pad vssio 16"), - pinctrl_pin(64, "p pad vddio 18"), - pinctrl_pin(65, "po rf ctrl strb2"), - pinctrl_pin(66, "po rf ctrl strb1"), - pinctrl_pin(67, "po rf ctrl strb0"), - pinctrl_pin(68, "pio rf ctrl data"), - pinctrl_pin(69, "po rf ctrl clk"), - pinctrl_pin(70, "po tx adc strb"), - pinctrl_pin(71, "po ant sw 2"), - pinctrl_pin(72, "po ant sw 3"), - pinctrl_pin(73, "po ant sw 0"), - pinctrl_pin(74, "po ant sw 1"), - pinctrl_pin(75, "po m clkrq"), - pinctrl_pin(76, "pi m clk"), - pinctrl_pin(77, "pi rtc clk"), - pinctrl_pin(78, "p pad vdd 8"), - pinctrl_pin(79, "p pad gnd 8"), - pinctrl_pin(80, "p pad vssio 13"), - pinctrl_pin(81, "p pad vddio 13"), - pinctrl_pin(82, "po sys 1 clk"), - pinctrl_pin(83, "po sys 2 clk"), - pinctrl_pin(84, "po sys 0 clk"), - pinctrl_pin(85, "pi sys 0 clkrq"), - pinctrl_pin(86, "po pwr mngt ctrl 1"), - pinctrl_pin(87, "po pwr mngt ctrl 0"), - pinctrl_pin(88, "po resout2 rst n"), - pinctrl_pin(89, "po resout1 rst n"), - pinctrl_pin(90, "po resout0 rst n"), - pinctrl_pin(91, "pi service n"), - pinctrl_pin(92, "p pad vdd 29"), - pinctrl_pin(93, "p pad gnd 29"), - pinctrl_pin(94, "p pad vssio 8"), - pinctrl_pin(95, "p pad vddio 8"), - pinctrl_pin(96, "pi ext irq1 n"), - pinctrl_pin(97, "pi ext irq0 n"), - pinctrl_pin(98, "pio dc on"), - pinctrl_pin(99, "pio acc app i2c data"), - pinctrl_pin(100, "pio acc app i2c clk"), - pinctrl_pin(101, "p pad vdd 12"), - pinctrl_pin(102, "p pad gnd 12"), - pinctrl_pin(103, "p pad vssio 14"), - pinctrl_pin(104, "p pad vddio 14"), - /* pads along the right edge of the chip */ - pinctrl_pin(105, "pio app i2c1 data"), - pinctrl_pin(106, "pio app i2c1 clk"), - pinctrl_pin(107, "po key out0"), - pinctrl_pin(108, "po key out1"), - pinctrl_pin(109, "po key out2"), - pinctrl_pin(110, "po key out3"), - pinctrl_pin(111, "po key out4"), - pinctrl_pin(112, "pi key in0"), - pinctrl_pin(113, "pi key in1"), - pinctrl_pin(114, "pi key in2"), - pinctrl_pin(115, "p pad vddio 15"), - pinctrl_pin(116, "p pad vssio 15"), - pinctrl_pin(117, "p pad gnd 13"), - pinctrl_pin(118, "p pad vdd 13"), - pinctrl_pin(119, "pi key in3"), - pinctrl_pin(120, "pi key in4"), - pinctrl_pin(121, "pi key in5"), - pinctrl_pin(122, "pio app pcm i2s1 data b"), - pinctrl_pin(123, "pio app pcm i2s1 data a"), - pinctrl_pin(124, "pio app pcm i2s1 ws"), - pinctrl_pin(125, "pio app pcm i2s1 clk"), - pinctrl_pin(126, "pio app pcm i2s0 data b"), - pinctrl_pin(127, "pio app pcm i2s0 data a"), - pinctrl_pin(128, "pio app pcm i2s0 ws"), - pinctrl_pin(129, "pio app pcm i2s0 clk"), - pinctrl_pin(130, "p pad vdd 17"), - pinctrl_pin(131, "p pad gnd 17"), - pinctrl_pin(132, "p pad vssio 19"), - pinctrl_pin(133, "p pad vddio 19"), - pinctrl_pin(134, "uart0 rts"), - pinctrl_pin(135, "uart0 cts"), - pinctrl_pin(136, "uart0 tx"), - pinctrl_pin(137, "uart0 rx"), - pinctrl_pin(138, "pio acc spi do"), - pinctrl_pin(139, "pio acc spi di"), - pinctrl_pin(140, "pio acc spi cs0 n"), - pinctrl_pin(141, "pio acc spi cs1 n"), - pinctrl_pin(142, "pio acc spi cs2 n"), - pinctrl_pin(143, "pio acc spi clk"), - pinctrl_pin(144, "po pdi ext rst n"), - pinctrl_pin(145, "p pad vddio 22"), - pinctrl_pin(146, "p pad vssio 22"), - pinctrl_pin(147, "p pad gnd 18"), - pinctrl_pin(148, "p pad vdd 18"), - pinctrl_pin(149, "pio pdi c0"), - pinctrl_pin(150, "pio pdi c1"), - pinctrl_pin(151, "pio pdi c2"), - pinctrl_pin(152, "pio pdi c3"), - pinctrl_pin(153, "pio pdi c4"), - pinctrl_pin(154, "pio pdi c5"), - pinctrl_pin(155, "pio pdi d0"), - pinctrl_pin(156, "pio pdi d1"), - pinctrl_pin(157, "pio pdi d2"), - pinctrl_pin(158, "pio pdi d3"), - pinctrl_pin(159, "p pad vddio 21"), - pinctrl_pin(160, "p pad vssio 21"), - pinctrl_pin(161, "pio pdi d4"), - pinctrl_pin(162, "pio pdi d5"), - pinctrl_pin(163, "pio pdi d6"), - pinctrl_pin(164, "pio pdi d7"), - pinctrl_pin(165, "pio ms ins"), - pinctrl_pin(166, "mmc data dir ls"), - pinctrl_pin(167, "mmc data 3"), - pinctrl_pin(168, "mmc data 2"), - pinctrl_pin(169, "mmc data 1"), - pinctrl_pin(170, "mmc data 0"), - pinctrl_pin(171, "mmc cmd dir ls"), - pinctrl_pin(172, "p pad vdd 27"), - pinctrl_pin(173, "p pad gnd 27"), - pinctrl_pin(174, "p pad vssio 20"), - pinctrl_pin(175, "p pad vddio 20"), - pinctrl_pin(176, "mmc cmd"), - pinctrl_pin(177, "mmc clk"), - pinctrl_pin(178, "pio app gpio 14"), - pinctrl_pin(179, "pio app gpio 13"), - pinctrl_pin(180, "pio app gpio 11"), - pinctrl_pin(181, "pio app gpio 25"), - pinctrl_pin(182, "pio app gpio 24"), - pinctrl_pin(183, "pio app gpio 23"), - pinctrl_pin(184, "pio app gpio 22"), - pinctrl_pin(185, "pio app gpio 21"), - pinctrl_pin(186, "pio app gpio 20"), - pinctrl_pin(187, "p pad vdd 19"), - pinctrl_pin(188, "p pad gnd 19"), - pinctrl_pin(189, "p pad vssio 23"), - pinctrl_pin(190, "p pad vddio 23"), - pinctrl_pin(191, "pio app gpio 19"), - pinctrl_pin(192, "pio app gpio 18"), - pinctrl_pin(193, "pio app gpio 17"), - pinctrl_pin(194, "pio app gpio 16"), - pinctrl_pin(195, "pi ci d1"), - pinctrl_pin(196, "pi ci d0"), - pinctrl_pin(197, "pi ci hsync"), - pinctrl_pin(198, "pi ci vsync"), - pinctrl_pin(199, "pi ci ext clk"), - pinctrl_pin(200, "po ci ext rst n"), - pinctrl_pin(201, "p pad vssio 43"), - pinctrl_pin(202, "p pad vddio 43"), - pinctrl_pin(203, "pi ci d6"), - pinctrl_pin(204, "pi ci d7"), - pinctrl_pin(205, "pi ci d2"), - pinctrl_pin(206, "pi ci d3"), - pinctrl_pin(207, "pi ci d4"), - pinctrl_pin(208, "pi ci d5"), - pinctrl_pin(209, "pi ci d8"), - pinctrl_pin(210, "pi ci d9"), - pinctrl_pin(211, "p pad vdd 20"), - pinctrl_pin(212, "p pad gnd 20"), - pinctrl_pin(213, "p pad vssio 24"), - pinctrl_pin(214, "p pad vddio 24"), - pinctrl_pin(215, "p pad vddio 26"), - pinctrl_pin(216, "po emif 1 a26"), - pinctrl_pin(217, "po emif 1 a25"), - pinctrl_pin(218, "p pad vssio 26"), - pinctrl_pin(219, "po emif 1 a24"), - pinctrl_pin(220, "po emif 1 a23"), - /* pads along the bottom edge of the chip */ - pinctrl_pin(221, "po emif 1 a22"), - pinctrl_pin(222, "po emif 1 a21"), - pinctrl_pin(223, "p pad vdd 21"), - pinctrl_pin(224, "p pad gnd 21"), - pinctrl_pin(225, "p pad vssio 27"), - pinctrl_pin(226, "p pad vddio 27"), - pinctrl_pin(227, "po emif 1 a20"), - pinctrl_pin(228, "po emif 1 a19"), - pinctrl_pin(229, "po emif 1 a18"), - pinctrl_pin(230, "po emif 1 a17"), - pinctrl_pin(231, "p pad vddio 28"), - pinctrl_pin(232, "p pad vssio 28"), - pinctrl_pin(233, "po emif 1 a16"), - pinctrl_pin(234, "pio emif 1 d15"), - pinctrl_pin(235, "po emif 1 a15"), - pinctrl_pin(236, "pio emif 1 d14"), - pinctrl_pin(237, "p pad vdd 22"), - pinctrl_pin(238, "p pad gnd 22"), - pinctrl_pin(239, "p pad vssio 29"), - pinctrl_pin(240, "p pad vddio 29"), - pinctrl_pin(241, "po emif 1 a14"), - pinctrl_pin(242, "pio emif 1 d13"), - pinctrl_pin(243, "po emif 1 a13"), - pinctrl_pin(244, "pio emif 1 d12"), - pinctrl_pin(245, "p pad vssio 30"), - pinctrl_pin(246, "p pad vddio 30"), - pinctrl_pin(247, "po emif 1 a12"), - pinctrl_pin(248, "pio emif 1 d11"), - pinctrl_pin(249, "po emif 1 a11"), - pinctrl_pin(250, "pio emif 1 d10"), - pinctrl_pin(251, "p pad vssio 31"), - pinctrl_pin(252, "p pad vddio 31"), - pinctrl_pin(253, "po emif 1 a10"), - pinctrl_pin(254, "pio emif 1 d09"), - pinctrl_pin(255, "po emif 1 a09"), - pinctrl_pin(256, "p pad vddio 32"), - pinctrl_pin(257, "p pad vssio 32"), - pinctrl_pin(258, "p pad gnd 24"), - pinctrl_pin(259, "p pad vdd 24"), - pinctrl_pin(260, "pio emif 1 d08"), - pinctrl_pin(261, "po emif 1 a08"), - pinctrl_pin(262, "pio emif 1 d07"), - pinctrl_pin(263, "po emif 1 a07"), - pinctrl_pin(264, "p pad vddio 33"), - pinctrl_pin(265, "p pad vssio 33"), - pinctrl_pin(266, "pio emif 1 d06"), - pinctrl_pin(267, "po emif 1 a06"), - pinctrl_pin(268, "pio emif 1 d05"), - pinctrl_pin(269, "po emif 1 a05"), - pinctrl_pin(270, "p pad vddio 34"), - pinctrl_pin(271, "p pad vssio 34"), - pinctrl_pin(272, "pio emif 1 d04"), - pinctrl_pin(273, "po emif 1 a04"), - pinctrl_pin(274, "pio emif 1 d03"), - pinctrl_pin(275, "po emif 1 a03"), - pinctrl_pin(276, "p pad vddio 35"), - pinctrl_pin(277, "p pad vssio 35"), - pinctrl_pin(278, "p pad gnd 23"), - pinctrl_pin(279, "p pad vdd 23"), - pinctrl_pin(280, "pio emif 1 d02"), - pinctrl_pin(281, "po emif 1 a02"), - pinctrl_pin(282, "pio emif 1 d01"), - pinctrl_pin(283, "po emif 1 a01"), - pinctrl_pin(284, "p pad vddio 36"), - pinctrl_pin(285, "p pad vssio 36"), - pinctrl_pin(286, "pio emif 1 d00"), - pinctrl_pin(287, "po emif 1 be1 n"), - pinctrl_pin(288, "po emif 1 be0 n"), - pinctrl_pin(289, "po emif 1 adv n"), - pinctrl_pin(290, "p pad vddio 37"), - pinctrl_pin(291, "p pad vssio 37"), - pinctrl_pin(292, "po emif 1 sd cke0"), - pinctrl_pin(293, "po emif 1 oe n"), - pinctrl_pin(294, "po emif 1 we n"), - pinctrl_pin(295, "p pad vddio 38"), - pinctrl_pin(296, "p pad vssio 38"), - pinctrl_pin(297, "po emif 1 clk"), - pinctrl_pin(298, "pio emif 1 sd clk"), - pinctrl_pin(299, "p pad vssio 45 (not bonded)"), - pinctrl_pin(300, "p pad vddio 42"), - pinctrl_pin(301, "p pad vssio 42"), - pinctrl_pin(302, "p pad gnd 31"), - pinctrl_pin(303, "p pad vdd 31"), - pinctrl_pin(304, "pi emif 1 ret clk"), - pinctrl_pin(305, "pi emif 1 wait n"), - pinctrl_pin(306, "pi emif 1 nfif ready"), - pinctrl_pin(307, "po emif 1 sd cke1"), - pinctrl_pin(308, "po emif 1 cs3 n"), - pinctrl_pin(309, "p pad vdd 25"), - pinctrl_pin(310, "p pad gnd 25"), - pinctrl_pin(311, "p pad vssio 39"), - pinctrl_pin(312, "p pad vddio 39"), - pinctrl_pin(313, "po emif 1 cs2 n"), - pinctrl_pin(314, "po emif 1 cs1 n"), - pinctrl_pin(315, "po emif 1 cs0 n"), - pinctrl_pin(316, "po etm trace pkt0"), - pinctrl_pin(317, "po etm trace pkt1"), - pinctrl_pin(318, "po etm trace pkt2"), - pinctrl_pin(319, "p pad vdd 30"), - pinctrl_pin(320, "p pad gnd 30"), - pinctrl_pin(321, "p pad vssio 44"), - pinctrl_pin(322, "p pad vddio 44"), - pinctrl_pin(323, "po etm trace pkt3"), - pinctrl_pin(324, "po etm trace pkt4"), - pinctrl_pin(325, "po etm trace pkt5"), - pinctrl_pin(326, "po etm trace pkt6"), - pinctrl_pin(327, "po etm trace pkt7"), - pinctrl_pin(328, "po etm pipe stat0"), - pinctrl_pin(329, "p pad vdd 26"), - pinctrl_pin(330, "p pad gnd 26"), - pinctrl_pin(331, "p pad vssio 40"), - pinctrl_pin(332, "p pad vddio 40"), - pinctrl_pin(333, "po etm pipe stat1"), - pinctrl_pin(334, "po etm pipe stat2"), - pinctrl_pin(335, "po etm trace clk"), - pinctrl_pin(336, "po etm trace sync"), - pinctrl_pin(337, "pio acc gpio 33"), - pinctrl_pin(338, "pio acc gpio 32"), - pinctrl_pin(339, "pio acc gpio 30"), - pinctrl_pin(340, "pio acc gpio 29"), - pinctrl_pin(341, "p pad vddio 17"), - pinctrl_pin(342, "p pad vssio 17"), - pinctrl_pin(343, "p pad gnd 15"), - pinctrl_pin(344, "p pad vdd 15"), - pinctrl_pin(345, "pio acc gpio 28"), - pinctrl_pin(346, "pio acc gpio 27"), - pinctrl_pin(347, "pio acc gpio 16"), - pinctrl_pin(348, "pi tap tms"), - pinctrl_pin(349, "pi tap tdi"), - pinctrl_pin(350, "po tap tdo"), - pinctrl_pin(351, "pi tap rst n"), - /* pads along the left edge of the chip */ - pinctrl_pin(352, "pi emu mode 0"), - pinctrl_pin(353, "po tap ret clk"), - pinctrl_pin(354, "pi tap clk"), - pinctrl_pin(355, "po emif 0 sd cs n"), - pinctrl_pin(356, "po emif 0 sd cas n"), - pinctrl_pin(357, "po emif 0 sd we n"), - pinctrl_pin(358, "p pad vddio 1"), - pinctrl_pin(359, "p pad vssio 1"), - pinctrl_pin(360, "p pad gnd 1"), - pinctrl_pin(361, "p pad vdd 1"), - pinctrl_pin(362, "po emif 0 sd cke"), - pinctrl_pin(363, "po emif 0 sd dqml"), - pinctrl_pin(364, "po emif 0 sd dqmu"), - pinctrl_pin(365, "po emif 0 sd ras n"), - pinctrl_pin(366, "pio emif 0 d15"), - pinctrl_pin(367, "po emif 0 a15"), - pinctrl_pin(368, "pio emif 0 d14"), - pinctrl_pin(369, "po emif 0 a14"), - pinctrl_pin(370, "pio emif 0 d13"), - pinctrl_pin(371, "po emif 0 a13"), - pinctrl_pin(372, "p pad vddio 2"), - pinctrl_pin(373, "p pad vssio 2"), - pinctrl_pin(374, "p pad gnd 2"), - pinctrl_pin(375, "p pad vdd 2"), - pinctrl_pin(376, "pio emif 0 d12"), - pinctrl_pin(377, "po emif 0 a12"), - pinctrl_pin(378, "pio emif 0 d11"), - pinctrl_pin(379, "po emif 0 a11"), - pinctrl_pin(380, "pio emif 0 d10"), - pinctrl_pin(381, "po emif 0 a10"), - pinctrl_pin(382, "pio emif 0 d09"), - pinctrl_pin(383, "po emif 0 a09"), - pinctrl_pin(384, "pio emif 0 d08"), - pinctrl_pin(385, "po emif 0 a08"), - pinctrl_pin(386, "pio emif 0 d07"), - pinctrl_pin(387, "po emif 0 a07"), - pinctrl_pin(388, "p pad vddio 3"), - pinctrl_pin(389, "p pad vssio 3"), - pinctrl_pin(390, "p pad gnd 3"), - pinctrl_pin(391, "p pad vdd 3"), - pinctrl_pin(392, "po efuse rdout1"), - pinctrl_pin(393, "pio emif 0 d06"), - pinctrl_pin(394, "po emif 0 a06"), - pinctrl_pin(395, "pio emif 0 d05"), - pinctrl_pin(396, "po emif 0 a05"), - pinctrl_pin(397, "pio emif 0 d04"), - pinctrl_pin(398, "po emif 0 a04"), - pinctrl_pin(399, "a pads/a vddco1v82v5 gnd 80u sf lin vddco af"), - pinctrl_pin(400, "pwr vddco af"), - pinctrl_pin(401, "pwr efuse hv1"), - pinctrl_pin(402, "p pad vssio 4"), - pinctrl_pin(403, "p pad vddio 4"), - pinctrl_pin(404, "p pad gnd 4"), - pinctrl_pin(405, "p pad vdd 4"), - pinctrl_pin(406, "pio emif 0 d03"), - pinctrl_pin(407, "po emif 0 a03"), - pinctrl_pin(408, "pwr efuse hv2"), - pinctrl_pin(409, "pwr efuse hv3"), - pinctrl_pin(410, "pio emif 0 d02"), - pinctrl_pin(411, "po emif 0 a02"), - pinctrl_pin(412, "pio emif 0 d01"), - pinctrl_pin(413, "p pad vddio 5"), - pinctrl_pin(414, "p pad vssio 5"), - pinctrl_pin(415, "p pad gnd 5"), - pinctrl_pin(416, "p pad vdd 5"), - pinctrl_pin(417, "po emif 0 a01"), - pinctrl_pin(418, "pio emif 0 d00"), - pinctrl_pin(419, "if 0 sd clk"), - pinctrl_pin(420, "app spi clk"), - pinctrl_pin(421, "app spi do"), - pinctrl_pin(422, "app spi di"), - pinctrl_pin(423, "app spi cs0"), - pinctrl_pin(424, "app spi cs1"), - pinctrl_pin(425, "app spi cs2"), - pinctrl_pin(426, "pio app gpio 10"), - pinctrl_pin(427, "p pad vddio 41"), - pinctrl_pin(428, "p pad vssio 41"), - pinctrl_pin(429, "p pad gnd 6"), - pinctrl_pin(430, "p pad vdd 6"), - pinctrl_pin(431, "pio acc sdio0 cmd"), - pinctrl_pin(432, "pio acc sdio0 ck"), - pinctrl_pin(433, "pio acc sdio0 d3"), - pinctrl_pin(434, "pio acc sdio0 d2"), - pinctrl_pin(435, "pio acc sdio0 d1"), - pinctrl_pin(436, "pio acc sdio0 d0"), - pinctrl_pin(437, "pio usb pu"), - pinctrl_pin(438, "pio usb sp"), - pinctrl_pin(439, "pio usb dat vp"), - pinctrl_pin(440, "pio usb se0 vm"), - pinctrl_pin(441, "pio usb oe"), - pinctrl_pin(442, "pio usb susp"), - pinctrl_pin(443, "p pad vssio 6"), - pinctrl_pin(444, "p pad vddio 6"), - pinctrl_pin(445, "pio usb puen"), - pinctrl_pin(446, "pio acc uart0 rx"), - pinctrl_pin(447, "pio acc uart0 tx"), - pinctrl_pin(448, "pio acc uart0 cts"), - pinctrl_pin(449, "pio acc uart0 rts"), - pinctrl_pin(450, "pio acc uart3 rx"), - pinctrl_pin(451, "pio acc uart3 tx"), - pinctrl_pin(452, "pio acc uart3 cts"), - pinctrl_pin(453, "pio acc uart3 rts"), - pinctrl_pin(454, "pio acc irda tx"), - pinctrl_pin(455, "p pad vddio 7"), - pinctrl_pin(456, "p pad vssio 7"), - pinctrl_pin(457, "p pad gnd 7"), - pinctrl_pin(458, "p pad vdd 7"), - pinctrl_pin(459, "pio acc irda rx"), - pinctrl_pin(460, "pio acc pcm i2s clk"), - pinctrl_pin(461, "pio acc pcm i2s ws"), - pinctrl_pin(462, "pio acc pcm i2s data a"), - pinctrl_pin(463, "pio acc pcm i2s data b"), - pinctrl_pin(464, "po sim clk"), - pinctrl_pin(465, "pio acc irda sd"), - pinctrl_pin(466, "pio sim data"), -}; - -/** - * @dev: a pointer back to containing device - * @virtbase: the offset to the controller in virtual memory - */ -struct u300_pmx { - struct device *dev; - struct pinctrl_dev *pctl; - void __iomem *virtbase; -}; - -/** - * u300_pmx_registers - the array of registers read/written for each pinmux - * shunt setting - */ -static const u32 u300_pmx_registers[] = { - u300_syscon_pmc1lr, - u300_syscon_pmc1hr, - u300_syscon_pmc2r, - u300_syscon_pmc3r, - u300_syscon_pmc4r, -}; - -/** - * struct u300_pin_group - describes a u300 pin group - * @name: the name of this specific pin group - * @pins: an array of discrete physical pins used in this group, taken - * from the driver-local pin enumeration space - * @num_pins: the number of pins in this group array, i.e. the number of - * elements in .pins so we can iterate over that array - */ -struct u300_pin_group { - const char *name; - const unsigned int *pins; - const unsigned num_pins; -}; - -/** - * struct pmx_onmask - mask bits to enable/disable padmux - * @mask: mask bits to disable - * @val: mask bits to enable - * - * onmask lazy dog: - * onmask = { - * {"pmc1lr" mask, "pmc1lr" value}, - * {"pmc1hr" mask, "pmc1hr" value}, - * {"pmc2r" mask, "pmc2r" value}, - * {"pmc3r" mask, "pmc3r" value}, - * {"pmc4r" mask, "pmc4r" value} - * } - */ -struct u300_pmx_mask { - u16 mask; - u16 bits; -}; - -/* the chip power pins are vdd, gnd, vddio and vssio */ -static const unsigned power_pins[] = { 0, 1, 3, 31, 46, 47, 49, 50, 61, 62, 63, - 64, 78, 79, 80, 81, 92, 93, 94, 95, 101, 102, 103, 104, 115, 116, 117, - 118, 130, 131, 132, 133, 145, 146, 147, 148, 159, 160, 172, 173, 174, - 175, 187, 188, 189, 190, 201, 202, 211, 212, 213, 214, 215, 218, 223, - 224, 225, 226, 231, 232, 237, 238, 239, 240, 245, 246, 251, 252, 256, - 257, 258, 259, 264, 265, 270, 271, 276, 277, 278, 279, 284, 285, 290, - 291, 295, 296, 299, 300, 301, 302, 303, 309, 310, 311, 312, 319, 320, - 321, 322, 329, 330, 331, 332, 341, 342, 343, 344, 358, 359, 360, 361, - 372, 373, 374, 375, 388, 389, 390, 391, 402, 403, 404, 405, 413, 414, - 415, 416, 427, 428, 429, 430, 443, 444, 455, 456, 457, 458 }; -static const unsigned emif0_pins[] = { 355, 356, 357, 362, 363, 364, 365, 366, - 367, 368, 369, 370, 371, 376, 377, 378, 379, 380, 381, 382, 383, 384, - 385, 386, 387, 393, 394, 395, 396, 397, 398, 406, 407, 410, 411, 412, - 417, 418 }; -static const unsigned emif1_pins[] = { 216, 217, 219, 220, 221, 222, 227, 228, - 229, 230, 233, 234, 235, 236, 241, 242, 243, 244, 247, 248, 249, 250, - 253, 254, 255, 260, 261, 262, 263, 266, 267, 268, 269, 272, 273, 274, - 275, 280, 281, 282, 283, 286, 287, 288, 289, 292, 293, 294, 297, 298, - 304, 305, 306, 307, 308, 313, 314, 315 }; -static const unsigned uart0_pins[] = { 134, 135, 136, 137 }; -static const unsigned mmc0_pins[] = { 166, 167, 168, 169, 170, 171, 176, 177 }; -static const unsigned spi0_pins[] = { 420, 421, 422, 423, 424, 425 }; - -static const struct u300_pmx_mask emif0_mask[] = { - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}, -}; - -static const struct u300_pmx_mask emif1_mask[] = { - /* - * this connects the sdram to cs2 and a nand flash to - * cs0 on the emif. - */ - { - u300_syscon_pmc1lr_emif_1_cs2_mask | - u300_syscon_pmc1lr_emif_1_cs1_mask | - u300_syscon_pmc1lr_emif_1_cs0_mask | - u300_syscon_pmc1lr_emif_1_mask, - u300_syscon_pmc1lr_emif_1_cs2_sdram | - u300_syscon_pmc1lr_emif_1_cs1_static | - u300_syscon_pmc1lr_emif_1_cs0_nfif | - u300_syscon_pmc1lr_emif_1_sdram0 - }, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}, -}; - -static const struct u300_pmx_mask uart0_mask[] = { - {0, 0}, - { - u300_syscon_pmc1hr_app_uart0_1_mask | - u300_syscon_pmc1hr_app_uart0_2_mask, - u300_syscon_pmc1hr_app_uart0_1_uart0 | - u300_syscon_pmc1hr_app_uart0_2_uart0 - }, - {0, 0}, - {0, 0}, - {0, 0}, -}; - -static const struct u300_pmx_mask mmc0_mask[] = { - { u300_syscon_pmc1lr_mmcsd_mask, u300_syscon_pmc1lr_mmcsd_mmcsd}, - {0, 0}, - {0, 0}, - {0, 0}, - { u300_syscon_pmc4r_app_misc_12_mask, - u300_syscon_pmc4r_app_misc_12_app_gpio } -}; - -static const struct u300_pmx_mask spi0_mask[] = { - {0, 0}, - { - u300_syscon_pmc1hr_app_spi_2_mask | - u300_syscon_pmc1hr_app_spi_cs_1_mask | - u300_syscon_pmc1hr_app_spi_cs_2_mask, - u300_syscon_pmc1hr_app_spi_2_spi | - u300_syscon_pmc1hr_app_spi_cs_1_spi | - u300_syscon_pmc1hr_app_spi_cs_2_spi - }, - {0, 0}, - {0, 0}, - {0, 0} -}; - -static const struct u300_pin_group u300_pin_groups[] = { - { - .name = "powergrp", - .pins = power_pins, - .num_pins = array_size(power_pins), - }, - { - .name = "emif0grp", - .pins = emif0_pins, - .num_pins = array_size(emif0_pins), - }, - { - .name = "emif1grp", - .pins = emif1_pins, - .num_pins = array_size(emif1_pins), - }, - { - .name = "uart0grp", - .pins = uart0_pins, - .num_pins = array_size(uart0_pins), - }, - { - .name = "mmc0grp", - .pins = mmc0_pins, - .num_pins = array_size(mmc0_pins), - }, - { - .name = "spi0grp", - .pins = spi0_pins, - .num_pins = array_size(spi0_pins), - }, -}; - -static int u300_get_groups_count(struct pinctrl_dev *pctldev) -{ - return array_size(u300_pin_groups); -} - -static const char *u300_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - return u300_pin_groups[selector].name; -} - -static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, - const unsigned **pins, - unsigned *num_pins) -{ - *pins = u300_pin_groups[selector].pins; - *num_pins = u300_pin_groups[selector].num_pins; - return 0; -} - -static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, - unsigned offset) -{ - seq_printf(s, " " driver_name); -} - -static const struct pinctrl_ops u300_pctrl_ops = { - .get_groups_count = u300_get_groups_count, - .get_group_name = u300_get_group_name, - .get_group_pins = u300_get_group_pins, - .pin_dbg_show = u300_pin_dbg_show, -}; - -/* - * here we define the available functions and their corresponding pin groups - */ - -/** - * struct u300_pmx_func - describes u300 pinmux functions - * @name: the name of this specific function - * @groups: corresponding pin groups - * @onmask: bits to set to enable this when doing pin muxing - */ -struct u300_pmx_func { - const char *name; - const char * const *groups; - const unsigned num_groups; - const struct u300_pmx_mask *mask; -}; - -static const char * const powergrps[] = { "powergrp" }; -static const char * const emif0grps[] = { "emif0grp" }; -static const char * const emif1grps[] = { "emif1grp" }; -static const char * const uart0grps[] = { "uart0grp" }; -static const char * const mmc0grps[] = { "mmc0grp" }; -static const char * const spi0grps[] = { "spi0grp" }; - -static const struct u300_pmx_func u300_pmx_functions[] = { - { - .name = "power", - .groups = powergrps, - .num_groups = array_size(powergrps), - /* mask is n/a */ - }, - { - .name = "emif0", - .groups = emif0grps, - .num_groups = array_size(emif0grps), - .mask = emif0_mask, - }, - { - .name = "emif1", - .groups = emif1grps, - .num_groups = array_size(emif1grps), - .mask = emif1_mask, - }, - { - .name = "uart0", - .groups = uart0grps, - .num_groups = array_size(uart0grps), - .mask = uart0_mask, - }, - { - .name = "mmc0", - .groups = mmc0grps, - .num_groups = array_size(mmc0grps), - .mask = mmc0_mask, - }, - { - .name = "spi0", - .groups = spi0grps, - .num_groups = array_size(spi0grps), - .mask = spi0_mask, - }, -}; - -static void u300_pmx_endisable(struct u300_pmx *upmx, unsigned selector, - bool enable) -{ - u16 regval, val, mask; - int i; - const struct u300_pmx_mask *upmx_mask; - - upmx_mask = u300_pmx_functions[selector].mask; - for (i = 0; i < array_size(u300_pmx_registers); i++) { - if (enable) - val = upmx_mask->bits; - else - val = 0; - - mask = upmx_mask->mask; - if (mask != 0) { - regval = readw(upmx->virtbase + u300_pmx_registers[i]); - regval &= ~mask; - regval |= val; - writew(regval, upmx->virtbase + u300_pmx_registers[i]); - } - upmx_mask++; - } -} - -static int u300_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) -{ - struct u300_pmx *upmx; - - /* there is nothing to do with the power pins */ - if (selector == 0) - return 0; - - upmx = pinctrl_dev_get_drvdata(pctldev); - u300_pmx_endisable(upmx, selector, true); - - return 0; -} - -static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev) -{ - return array_size(u300_pmx_functions); -} - -static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - return u300_pmx_functions[selector].name; -} - -static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, - const char * const **groups, - unsigned * const num_groups) -{ - *groups = u300_pmx_functions[selector].groups; - *num_groups = u300_pmx_functions[selector].num_groups; - return 0; -} - -static const struct pinmux_ops u300_pmx_ops = { - .get_functions_count = u300_pmx_get_funcs_count, - .get_function_name = u300_pmx_get_func_name, - .get_function_groups = u300_pmx_get_groups, - .set_mux = u300_pmx_set_mux, -}; - -static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long *config) -{ - struct pinctrl_gpio_range *range = - pinctrl_find_gpio_range_from_pin(pctldev, pin); - - /* we get config for those pins we can get it for and that's it */ - if (!range) - return -enotsupp; - - return u300_gpio_config_get(range->gc, - (pin - range->pin_base + range->base), - config); -} - -static int u300_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long *configs, unsigned num_configs) -{ - struct pinctrl_gpio_range *range = - pinctrl_find_gpio_range_from_pin(pctldev, pin); - int ret, i; - - if (!range) - return -einval; - - for (i = 0; i < num_configs; i++) { - /* note: none of these configurations take any argument */ - ret = u300_gpio_config_set(range->gc, - (pin - range->pin_base + range->base), - pinconf_to_config_param(configs[i])); - if (ret) - return ret; - } /* for each config */ - - return 0; -} - -static const struct pinconf_ops u300_pconf_ops = { - .is_generic = true, - .pin_config_get = u300_pin_config_get, - .pin_config_set = u300_pin_config_set, -}; - -static struct pinctrl_desc u300_pmx_desc = { - .name = driver_name, - .pins = u300_pads, - .npins = array_size(u300_pads), - .pctlops = &u300_pctrl_ops, - .pmxops = &u300_pmx_ops, - .confops = &u300_pconf_ops, - .owner = this_module, -}; - -static int u300_pmx_probe(struct platform_device *pdev) -{ - struct u300_pmx *upmx; - - /* create state holders etc for this driver */ - upmx = devm_kzalloc(&pdev->dev, sizeof(*upmx), gfp_kernel); - if (!upmx) - return -enomem; - - upmx->dev = &pdev->dev; - - upmx->virtbase = devm_platform_ioremap_resource(pdev, 0); - if (is_err(upmx->virtbase)) - return ptr_err(upmx->virtbase); - - upmx->pctl = devm_pinctrl_register(&pdev->dev, &u300_pmx_desc, upmx); - if (is_err(upmx->pctl)) { - dev_err(&pdev->dev, "could not register u300 pinmux driver "); - return ptr_err(upmx->pctl); - } - - platform_set_drvdata(pdev, upmx); - - dev_info(&pdev->dev, "initialized u300 pin control driver "); - - return 0; -} - -static const struct of_device_id u300_pinctrl_match[] = { - { .compatible = "stericsson,pinctrl-u300" }, - {}, -}; - - -static struct platform_driver u300_pmx_driver = { - .driver = { - .name = driver_name, - .of_match_table = u300_pinctrl_match, - }, - .probe = u300_pmx_probe, -}; - -static int __init u300_pmx_init(void) -{ - return platform_driver_register(&u300_pmx_driver); -} -arch_initcall(u300_pmx_init); - -static void __exit u300_pmx_exit(void) -{ - platform_driver_unregister(&u300_pmx_driver); -} -module_exit(u300_pmx_exit); - -module_author("linus walleij <linus.walleij@linaro.org>"); -module_description("u300 pin control driver"); -module_license("gpl v2");
|
Pin Controllers (pinctrl)
|
4ef82b305239aca1ebf0ddd44b790eb9ddca5ba4
|
arnd bergmann
|
drivers
|
pinctrl
| |
pinctrl: remove zte zx driver
|
the zte zx platform is getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove zte zx driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['c', 'h', 'kconfig', 'txt', 'makefile']
| 8
| 0
| 1,674
|
--- diff --git a/documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt b/documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt --- a/documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt +++ /dev/null -* zte zx pin controller - -the pin controller on zte zx platforms is kinda of hybrid. it consists of -a main controller and an auxiliary one. for example, on zx296718 soc, the -main controller is top_pmm and the auxiliary one is aon_iocfg. both -controllers work together to control pin multiplexing and configuration in -the way illustrated as below. - - - gmii_rxd3 ---+ - | - dvi1_hs ---+----------------------------- gmii_rxd3 (top pin) - | - bgpio16 ---+ ^ - | pinconf - ^ | - | pinmux | - | | - - top_pmm (main) aon_iocfg (aux) - - | | | - | pinmux | | - | pinmux v | - v | pinconf - key_row2 ---+ v - port1_lcd_te ---+ | - | agpio10 ---+------ key_row2 (aon pin) - i2s0_dout3 ---+ | - |-----------------------+ - pwm_out3 ---+ - | - vga_vs1 ---+ - - -for most of pins like gmii_rxd3 in the figure, the pinmux function is -controlled by top_pmm block only, and this type of pins are meant by term -'top pins'. for pins like key_row2, the pinmux is controlled by both -top_pmm and aon_iocfg blocks, as the available multiplexing functions for -the pin spread in both controllers. this type of pins are called 'aon pins'. -though pinmux implementation is quite different, pinconf is same for both -types of pins. both are controlled by auxiliary controller, i.e. aon_iocfg -on zx296718. - -required properties: -- compatible: should be "zte,zx296718-pmm". -- reg: the register physical address and length. -- zte,auxiliary-controller: phandle to the auxiliary pin controller which - implements pinmux for aon pins and pinconf for all pins. - -the following pin configuration are supported. please refer to -pinctrl-bindings.txt in this directory for more details of the common -pinctrl bindings used by client devices. - -- bias-pull-up -- bias-pull-down -- drive-strength -- input-enable -- slew-rate - -examples: - -iocfg: pin-controller@119000 { - compatible = "zte,zx296718-iocfg"; - reg = <0x119000 0x1000>; -}; - -pmm: pin-controller@1462000 { - compatible = "zte,zx296718-pmm"; - reg = <0x1462000 0x1000>; - zte,auxiliary-controller = <&iocfg>; -}; - -&pmm { - vga_pins: vga { - pins = "key_col1", "key_col2", "key_row1", "key_row2"; - function = "vga"; - }; -}; - -&vga { - pinctrl-names = "default"; - pinctrl-0 = <&vga_pins>; -}; diff --git a/drivers/pinctrl/kconfig b/drivers/pinctrl/kconfig --- a/drivers/pinctrl/kconfig +++ b/drivers/pinctrl/kconfig -source "drivers/pinctrl/zte/kconfig" diff --git a/drivers/pinctrl/makefile b/drivers/pinctrl/makefile --- a/drivers/pinctrl/makefile +++ b/drivers/pinctrl/makefile -obj-$(config_pinctrl_zx) += zte/ diff --git a/drivers/pinctrl/zte/kconfig b/drivers/pinctrl/zte/kconfig --- a/drivers/pinctrl/zte/kconfig +++ /dev/null -# spdx-license-identifier: gpl-2.0-only -config pinctrl_zx - bool - select pinmux - select generic_pinconf - select generic_pinctrl_groups - select generic_pinmux_functions - -config pinctrl_zx296718 - bool "zte zx296718 pinctrl driver" - depends on of && arch_zx - select pinctrl_zx - help - say y here to enable the zx296718 pinctrl driver diff --git a/drivers/pinctrl/zte/makefile b/drivers/pinctrl/zte/makefile --- a/drivers/pinctrl/zte/makefile +++ /dev/null -# spdx-license-identifier: gpl-2.0-only -obj-$(config_pinctrl_zx) += pinctrl-zx.o -obj-$(config_pinctrl_zx296718) += pinctrl-zx296718.o diff --git a/drivers/pinctrl/zte/pinctrl-zx.c b/drivers/pinctrl/zte/pinctrl-zx.c --- a/drivers/pinctrl/zte/pinctrl-zx.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * copyright (c) 2017 sanechips technology co., ltd. - * copyright 2017 linaro ltd. - */ - -#include <linux/io.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/pinctrl/pinmux.h> -#include <linux/platform_device.h> -#include <linux/slab.h> - -#include "../core.h" -#include "../pinctrl-utils.h" -#include "../pinmux.h" -#include "pinctrl-zx.h" - -#define zx_pull_down bit(0) -#define zx_pull_up bit(1) -#define zx_input_enable bit(3) -#define zx_ds_shift 4 -#define zx_ds_mask (0x7 << zx_ds_shift) -#define zx_ds_value(x) (((x) << zx_ds_shift) & zx_ds_mask) -#define zx_slew bit(8) - -struct zx_pinctrl { - struct pinctrl_dev *pctldev; - struct device *dev; - void __iomem *base; - void __iomem *aux_base; - spinlock_t lock; - struct zx_pinctrl_soc_info *info; -}; - -static int zx_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, u32 *num_maps) -{ - return pinconf_generic_dt_node_to_map(pctldev, np_config, map, - num_maps, pin_map_type_invalid); -} - -static const struct pinctrl_ops zx_pinctrl_ops = { - .dt_node_to_map = zx_dt_node_to_map, - .dt_free_map = pinctrl_utils_free_map, - .get_groups_count = pinctrl_generic_get_group_count, - .get_group_name = pinctrl_generic_get_group_name, - .get_group_pins = pinctrl_generic_get_group_pins, -}; - -#define nonaon_mval 2 - -static int zx_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, - unsigned int group_selector) -{ - struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev); - struct zx_pinctrl_soc_info *info = zpctl->info; - const struct pinctrl_pin_desc *pindesc = info->pins + group_selector; - struct zx_pin_data *data = pindesc->drv_data; - struct zx_mux_desc *mux; - u32 mask, offset, bitpos; - struct function_desc *func; - unsigned long flags; - u32 val, mval; - - /* skip reserved pin */ - if (!data) - return -einval; - - mux = data->muxes; - mask = (1 << data->width) - 1; - offset = data->offset; - bitpos = data->bitpos; - - func = pinmux_generic_get_function(pctldev, func_selector); - if (!func) - return -einval; - - while (mux->name) { - if (strcmp(mux->name, func->name) == 0) - break; - mux++; - } - - /* found mux value to be written */ - mval = mux->muxval; - - spin_lock_irqsave(&zpctl->lock, flags); - - if (data->aon_pin) { - /* - * it's an aon pin, whose mux register offset and bit position - * can be calculated from pin number. each register covers 16 - * pins, and each pin occupies 2 bits. - */ - u16 aoffset = pindesc->number / 16 * 4; - u16 abitpos = (pindesc->number % 16) * 2; - - if (mval & aon_mux_flag) { - /* - * this is a mux value that needs to be written into - * aon pinmux register. write it and then we're done. - */ - val = readl(zpctl->aux_base + aoffset); - val &= ~(0x3 << abitpos); - val |= (mval & 0x3) << abitpos; - writel(val, zpctl->aux_base + aoffset); - } else { - /* - * it's a mux value that needs to be written into top - * pinmux register. - */ - val = readl(zpctl->base + offset); - val &= ~(mask << bitpos); - val |= (mval & mask) << bitpos; - writel(val, zpctl->base + offset); - - /* - * in this case, the aon pinmux register needs to be - * set up to select non-aon function. - */ - val = readl(zpctl->aux_base + aoffset); - val &= ~(0x3 << abitpos); - val |= nonaon_mval << abitpos; - writel(val, zpctl->aux_base + aoffset); - } - - } else { - /* - * this is a top pin, and we only need to set up top pinmux - * register and then we're done with it. - */ - val = readl(zpctl->base + offset); - val &= ~(mask << bitpos); - val |= (mval & mask) << bitpos; - writel(val, zpctl->base + offset); - } - - spin_unlock_irqrestore(&zpctl->lock, flags); - - return 0; -} - -static const struct pinmux_ops zx_pinmux_ops = { - .get_functions_count = pinmux_generic_get_function_count, - .get_function_name = pinmux_generic_get_function_name, - .get_function_groups = pinmux_generic_get_function_groups, - .set_mux = zx_set_mux, -}; - -static int zx_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long *config) -{ - struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev); - struct zx_pinctrl_soc_info *info = zpctl->info; - const struct pinctrl_pin_desc *pindesc = info->pins + pin; - struct zx_pin_data *data = pindesc->drv_data; - enum pin_config_param param = pinconf_to_config_param(*config); - u32 val; - - /* skip reserved pin */ - if (!data) - return -einval; - - val = readl(zpctl->aux_base + data->coffset); - val = val >> data->cbitpos; - - switch (param) { - case pin_config_bias_pull_down: - val &= zx_pull_down; - val = !!val; - if (val == 0) - return -einval; - break; - case pin_config_bias_pull_up: - val &= zx_pull_up; - val = !!val; - if (val == 0) - return -einval; - break; - case pin_config_input_enable: - val &= zx_input_enable; - val = !!val; - if (val == 0) - return -einval; - break; - case pin_config_drive_strength: - val &= zx_ds_mask; - val = val >> zx_ds_shift; - break; - case pin_config_slew_rate: - val &= zx_slew; - val = !!val; - break; - default: - return -enotsupp; - } - - *config = pinconf_to_config_packed(param, val); - - return 0; -} - -static int zx_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long *configs, unsigned int num_configs) -{ - struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev); - struct zx_pinctrl_soc_info *info = zpctl->info; - const struct pinctrl_pin_desc *pindesc = info->pins + pin; - struct zx_pin_data *data = pindesc->drv_data; - enum pin_config_param param; - u32 val, arg; - int i; - - /* skip reserved pin */ - if (!data) - return -einval; - - val = readl(zpctl->aux_base + data->coffset); - - for (i = 0; i < num_configs; i++) { - param = pinconf_to_config_param(configs[i]); - arg = pinconf_to_config_argument(configs[i]); - - switch (param) { - case pin_config_bias_pull_down: - val |= zx_pull_down << data->cbitpos; - break; - case pin_config_bias_pull_up: - val |= zx_pull_up << data->cbitpos; - break; - case pin_config_input_enable: - val |= zx_input_enable << data->cbitpos; - break; - case pin_config_drive_strength: - val &= ~(zx_ds_mask << data->cbitpos); - val |= zx_ds_value(arg) << data->cbitpos; - break; - case pin_config_slew_rate: - if (arg) - val |= zx_slew << data->cbitpos; - else - val &= ~zx_slew << data->cbitpos; - break; - default: - return -enotsupp; - } - } - - writel(val, zpctl->aux_base + data->coffset); - return 0; -} - -static const struct pinconf_ops zx_pinconf_ops = { - .pin_config_set = zx_pin_config_set, - .pin_config_get = zx_pin_config_get, - .is_generic = true, -}; - -static int zx_pinctrl_build_state(struct platform_device *pdev) -{ - struct zx_pinctrl *zpctl = platform_get_drvdata(pdev); - struct zx_pinctrl_soc_info *info = zpctl->info; - struct pinctrl_dev *pctldev = zpctl->pctldev; - struct function_desc *functions; - int nfunctions; - struct group_desc *groups; - int ngroups; - int i; - - /* every single pin composes a group */ - ngroups = info->npins; - groups = devm_kcalloc(&pdev->dev, ngroups, sizeof(*groups), - gfp_kernel); - if (!groups) - return -enomem; - - for (i = 0; i < ngroups; i++) { - const struct pinctrl_pin_desc *pindesc = info->pins + i; - struct group_desc *group = groups + i; - - group->name = pindesc->name; - group->pins = (int *) &pindesc->number; - group->num_pins = 1; - radix_tree_insert(&pctldev->pin_group_tree, i, group); - } - - pctldev->num_groups = ngroups; - - /* build function list from pin mux functions */ - functions = kcalloc(info->npins, sizeof(*functions), gfp_kernel); - if (!functions) - return -enomem; - - nfunctions = 0; - for (i = 0; i < info->npins; i++) { - const struct pinctrl_pin_desc *pindesc = info->pins + i; - struct zx_pin_data *data = pindesc->drv_data; - struct zx_mux_desc *mux; - - /* reserved pins do not have a drv_data at all */ - if (!data) - continue; - - /* loop over all muxes for the pin */ - mux = data->muxes; - while (mux->name) { - struct function_desc *func = functions; - - /* search function list for given mux */ - while (func->name) { - if (strcmp(mux->name, func->name) == 0) { - /* function exists */ - func->num_group_names++; - break; - } - func++; - } - - if (!func->name) { - /* new function */ - func->name = mux->name; - func->num_group_names = 1; - radix_tree_insert(&pctldev->pin_function_tree, - nfunctions++, func); - } - - mux++; - } - } - - pctldev->num_functions = nfunctions; - functions = krealloc(functions, nfunctions * sizeof(*functions), - gfp_kernel); - - /* find pin groups for every single function */ - for (i = 0; i < info->npins; i++) { - const struct pinctrl_pin_desc *pindesc = info->pins + i; - struct zx_pin_data *data = pindesc->drv_data; - struct zx_mux_desc *mux; - - if (!data) - continue; - - mux = data->muxes; - while (mux->name) { - struct function_desc *func; - const char **group; - int j; - - /* find function for given mux */ - for (j = 0; j < nfunctions; j++) - if (strcmp(functions[j].name, mux->name) == 0) - break; - - func = functions + j; - if (!func->group_names) { - func->group_names = devm_kcalloc(&pdev->dev, - func->num_group_names, - sizeof(*func->group_names), - gfp_kernel); - if (!func->group_names) { - kfree(functions); - return -enomem; - } - } - - group = func->group_names; - while (*group) - group++; - *group = pindesc->name; - - mux++; - } - } - - return 0; -} - -int zx_pinctrl_init(struct platform_device *pdev, - struct zx_pinctrl_soc_info *info) -{ - struct pinctrl_desc *pctldesc; - struct zx_pinctrl *zpctl; - struct device_node *np; - int ret; - - zpctl = devm_kzalloc(&pdev->dev, sizeof(*zpctl), gfp_kernel); - if (!zpctl) - return -enomem; - - spin_lock_init(&zpctl->lock); - - zpctl->base = devm_platform_ioremap_resource(pdev, 0); - if (is_err(zpctl->base)) - return ptr_err(zpctl->base); - - np = of_parse_phandle(pdev->dev.of_node, "zte,auxiliary-controller", 0); - if (!np) { - dev_err(&pdev->dev, "failed to find auxiliary controller "); - return -enodev; - } - - zpctl->aux_base = of_iomap(np, 0); - of_node_put(np); - if (!zpctl->aux_base) - return -enomem; - - zpctl->dev = &pdev->dev; - zpctl->info = info; - - pctldesc = devm_kzalloc(&pdev->dev, sizeof(*pctldesc), gfp_kernel); - if (!pctldesc) - return -enomem; - - pctldesc->name = dev_name(&pdev->dev); - pctldesc->owner = this_module; - pctldesc->pins = info->pins; - pctldesc->npins = info->npins; - pctldesc->pctlops = &zx_pinctrl_ops; - pctldesc->pmxops = &zx_pinmux_ops; - pctldesc->confops = &zx_pinconf_ops; - - zpctl->pctldev = devm_pinctrl_register(&pdev->dev, pctldesc, zpctl); - if (is_err(zpctl->pctldev)) { - ret = ptr_err(zpctl->pctldev); - dev_err(&pdev->dev, "failed to register pinctrl: %d ", ret); - return ret; - } - - platform_set_drvdata(pdev, zpctl); - - ret = zx_pinctrl_build_state(pdev); - if (ret) { - dev_err(&pdev->dev, "failed to build state: %d ", ret); - return ret; - } - - dev_info(&pdev->dev, "initialized pinctrl driver "); - return 0; -} diff --git a/drivers/pinctrl/zte/pinctrl-zx.h b/drivers/pinctrl/zte/pinctrl-zx.h --- a/drivers/pinctrl/zte/pinctrl-zx.h +++ /dev/null -/* spdx-license-identifier: gpl-2.0-only */ -/* - * copyright (c) 2017 sanechips technology co., ltd. - * copyright 2017 linaro ltd. - */ - -#ifndef __pinctrl_zx_h -#define __pinctrl_zx_h - -/** - * struct zx_mux_desc - hardware mux descriptor - * @name: mux function name - * @muxval: mux register bit value - */ -struct zx_mux_desc { - const char *name; - u8 muxval; -}; - -/** - * struct zx_pin_data - hardware per-pin data - * @aon_pin: whether it's an aon pin - * @offset: register offset within top pinmux controller - * @bitpos: bit position within top pinmux register - * @width: bit width within top pinmux register - * @coffset: pinconf register offset within aon controller - * @cbitpos: pinconf bit position within aon register - * @muxes: available mux function names and corresponding register values - * - * unlike top pinmux and aon pinconf registers which are arranged pretty - * arbitrarily, aon pinmux register bits are well organized per pin id, and - * each pin occupies two bits, so that we can calculate the aon register offset - * and bit position from pin id. thus, we only need to define top pinmux and - * aon pinconf register data for the pin. - */ -struct zx_pin_data { - bool aon_pin; - u16 offset; - u16 bitpos; - u16 width; - u16 coffset; - u16 cbitpos; - struct zx_mux_desc *muxes; -}; - -struct zx_pinctrl_soc_info { - const struct pinctrl_pin_desc *pins; - unsigned int npins; -}; - -#define top_pin(pin, off, bp, wd, coff, cbp, ...) { \ - .number = pin, \ - .name = #pin, \ - .drv_data = &(struct zx_pin_data) { \ - .aon_pin = false, \ - .offset = off, \ - .bitpos = bp, \ - .width = wd, \ - .coffset = coff, \ - .cbitpos = cbp, \ - .muxes = (struct zx_mux_desc[]) { \ - __va_args__, { } }, \ - }, \ -} - -#define aon_pin(pin, off, bp, wd, coff, cbp, ...) { \ - .number = pin, \ - .name = #pin, \ - .drv_data = &(struct zx_pin_data) { \ - .aon_pin = true, \ - .offset = off, \ - .bitpos = bp, \ - .width = wd, \ - .coffset = coff, \ - .cbitpos = cbp, \ - .muxes = (struct zx_mux_desc[]) { \ - __va_args__, { } }, \ - }, \ -} - -#define zx_reserved(pin) pinctrl_pin(pin, #pin) - -#define top_mux(_val, _name) { \ - .name = _name, \ - .muxval = _val, \ -} - -/* - * when the flag is set, it's a mux configuration for an aon pin that sits in - * aon register. otherwise, it's one for aon pin but sitting in top register. - */ -#define aon_mux_flag bit(7) - -#define aon_mux(_val, _name) { \ - .name = _name, \ - .muxval = _val | aon_mux_flag, \ -} - -int zx_pinctrl_init(struct platform_device *pdev, - struct zx_pinctrl_soc_info *info); - -#endif /* __pinctrl_zx_h */ diff --git a/drivers/pinctrl/zte/pinctrl-zx296718.c b/drivers/pinctrl/zte/pinctrl-zx296718.c --- a/drivers/pinctrl/zte/pinctrl-zx296718.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * copyright (c) 2017 sanechips technology co., ltd. - * copyright 2017 linaro ltd. - */ - -#include <linux/module.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/platform_device.h> - -#include "pinctrl-zx.h" - -#define top_reg0 0x00 -#define top_reg1 0x04 -#define top_reg2 0x08 -#define top_reg3 0x0c -#define top_reg4 0x10 -#define top_reg5 0x14 -#define top_reg6 0x18 -#define top_reg7 0x1c -#define top_reg8 0x20 - -/* - * the pin numbering starts from aon pins with reserved ones included, - * so that register data like offset and bit position for aon pins can - * be calculated from pin number. - */ -enum zx296718_pin { - /* aon_pmm_reg_0 */ - i2c3_scl = 0, - i2c3_sda = 1, - aon_reserved0 = 2, - aon_reserved1 = 3, - sec_en = 4, - uart0_rxd = 5, - uart0_txd = 6, - ir_in = 7, - spi0_clk = 8, - spi0_cs = 9, - spi0_txd = 10, - spi0_rxd = 11, - key_col0 = 12, - key_col1 = 13, - key_col2 = 14, - key_row0 = 15, - - /* aon_pmm_reg_1 */ - key_row1 = 16, - key_row2 = 17, - hdmi_scl = 18, - hdmi_sda = 19, - jtag_tck = 20, - jtag_trstn = 21, - jtag_tms = 22, - jtag_tdi = 23, - jtag_tdo = 24, - i2c0_scl = 25, - i2c0_sda = 26, - i2c1_scl = 27, - i2c1_sda = 28, - aon_reserved2 = 29, - aon_reserved3 = 30, - aon_reserved4 = 31, - - /* aon_pmm_reg_2 */ - spi1_clk = 32, - spi1_cs = 33, - spi1_txd = 34, - spi1_rxd = 35, - aon_reserved5 = 36, - aon_reserved6 = 37, - audio_det = 38, - spdif_out = 39, - hdmi_cec = 40, - hdmi_hpd = 41, - gmac_25m_out = 42, - boot_sel0 = 43, - boot_sel1 = 44, - boot_sel2 = 45, - deep_sleep_out_n = 46, - aon_reserved7 = 47, - - /* top_pmm_reg_0 */ - gmii_gtx_clk = 48, - gmii_tx_clk = 49, - gmii_txd0 = 50, - gmii_txd1 = 51, - gmii_txd2 = 52, - gmii_txd3 = 53, - gmii_txd4 = 54, - gmii_txd5 = 55, - gmii_txd6 = 56, - gmii_txd7 = 57, - gmii_tx_er = 58, - gmii_tx_en = 59, - gmii_rx_clk = 60, - gmii_rxd0 = 61, - gmii_rxd1 = 62, - gmii_rxd2 = 63, - - /* top_pmm_reg_1 */ - gmii_rxd3 = 64, - gmii_rxd4 = 65, - gmii_rxd5 = 66, - gmii_rxd6 = 67, - gmii_rxd7 = 68, - gmii_rx_er = 69, - gmii_rx_dv = 70, - gmii_col = 71, - gmii_crs = 72, - gmii_mdc = 73, - gmii_mdio = 74, - sdio1_clk = 75, - sdio1_cmd = 76, - sdio1_data0 = 77, - sdio1_data1 = 78, - sdio1_data2 = 79, - - /* top_pmm_reg_2 */ - sdio1_data3 = 80, - sdio1_cd = 81, - sdio1_wp = 82, - usim1_cd = 83, - usim1_clk = 84, - usim1_rst = 85, - - /* top_pmm_reg_3 */ - usim1_data = 86, - sdio0_clk = 87, - sdio0_cmd = 88, - sdio0_data0 = 89, - sdio0_data1 = 90, - sdio0_data2 = 91, - sdio0_data3 = 92, - sdio0_cd = 93, - sdio0_wp = 94, - - /* top_pmm_reg_4 */ - tsi0_data0 = 95, - spinor_clk = 96, - tsi2_data = 97, - tsi2_clk = 98, - tsi2_sync = 99, - tsi2_valid = 100, - spinor_cs = 101, - spinor_dq0 = 102, - spinor_dq1 = 103, - spinor_dq2 = 104, - spinor_dq3 = 105, - vga_hs = 106, - vga_vs = 107, - tsi3_data = 108, - - /* top_pmm_reg_5 */ - tsi3_clk = 109, - tsi3_sync = 110, - tsi3_valid = 111, - i2s1_ws = 112, - i2s1_bclk = 113, - i2s1_mclk = 114, - i2s1_din0 = 115, - i2s1_dout0 = 116, - spi3_clk = 117, - spi3_cs = 118, - spi3_txd = 119, - nand_ldo_ms18_sel = 120, - - /* top_pmm_reg_6 */ - spi3_rxd = 121, - i2s0_mclk = 122, - i2s0_bclk = 123, - i2s0_ws = 124, - i2s0_din0 = 125, - i2s0_dout0 = 126, - i2c5_scl = 127, - i2c5_sda = 128, - spi2_clk = 129, - spi2_cs = 130, - spi2_txd = 131, - - /* top_pmm_reg_7 */ - spi2_rxd = 132, - nand_wp_n = 133, - nand_page_size0 = 134, - nand_page_size1 = 135, - nand_addr_cycle = 136, - nand_rb0 = 137, - nand_rb1 = 138, - nand_rb2 = 139, - nand_rb3 = 140, - - /* top_pmm_reg_8 */ - gmac_125m_in = 141, - gmac_50m_out = 142, - spinor_ssclk_loopback = 143, - spinor_sdio1clk_loopback = 144, -}; - -static const struct pinctrl_pin_desc zx296718_pins[] = { - /* aon_pmm_reg_0 */ - aon_pin(i2c3_scl, top_reg2, 18, 2, 0x48, 0, - aon_mux(0x0, "anmi"), /* anmi */ - aon_mux(0x1, "agpio"), /* agpio29 */ - aon_mux(0x2, "nonaon"), /* pin0 */ - aon_mux(0x3, "ext_int"), /* int4 */ - top_mux(0x0, "i2c3"), /* scl */ - top_mux(0x1, "spi2"), /* txd */ - top_mux(0x2, "i2s1")), /* din0 */ - aon_pin(i2c3_sda, top_reg2, 20, 2, 0x48, 9, - aon_mux(0x0, "wd"), /* rst_b */ - aon_mux(0x1, "agpio"), /* agpio30 */ - aon_mux(0x2, "nonaon"), /* pin1 */ - aon_mux(0x3, "ext_int"), /* int5 */ - top_mux(0x0, "i2c3"), /* sda */ - top_mux(0x1, "spi2"), /* rxd */ - top_mux(0x2, "i2s0")), /* mclk */ - zx_reserved(aon_reserved0), - zx_reserved(aon_reserved1), - aon_pin(sec_en, top_reg3, 5, 1, 0x50, 0, - aon_mux(0x0, "sec"), /* en */ - aon_mux(0x1, "agpio"), /* agpio28 */ - aon_mux(0x2, "nonaon"), /* pin3 */ - aon_mux(0x3, "ext_int"), /* int7 */ - top_mux(0x0, "i2c2"), /* sda */ - top_mux(0x1, "spi2")), /* cs */ - aon_pin(uart0_rxd, 0, 0, 0, 0x50, 9, - aon_mux(0x0, "uart0"), /* rxd */ - aon_mux(0x1, "agpio"), /* agpio20 */ - aon_mux(0x2, "nonaon")), /* pin34 */ - aon_pin(uart0_txd, 0, 0, 0, 0x50, 18, - aon_mux(0x0, "uart0"), /* txd */ - aon_mux(0x1, "agpio"), /* agpio21 */ - aon_mux(0x2, "nonaon")), /* pin32 */ - aon_pin(ir_in, 0, 0, 0, 0x64, 0, - aon_mux(0x0, "ir"), /* in */ - aon_mux(0x1, "agpio"), /* agpio0 */ - aon_mux(0x2, "nonaon")), /* pin27 */ - aon_pin(spi0_clk, top_reg3, 16, 1, 0x64, 9, - aon_mux(0x0, "ext_int"), /* int0 */ - aon_mux(0x1, "agpio"), /* agpio23 */ - aon_mux(0x2, "nonaon"), /* pin5 */ - aon_mux(0x3, "pcu"), /* test6 */ - top_mux(0x0, "spi0"), /* clk */ - top_mux(0x1, "isp")), /* flash_trig */ - aon_pin(spi0_cs, top_reg3, 17, 1, 0x64, 18, - aon_mux(0x0, "ext_int"), /* int1 */ - aon_mux(0x1, "agpio"), /* agpio24 */ - aon_mux(0x2, "nonaon"), /* pin6 */ - aon_mux(0x3, "pcu"), /* test0 */ - top_mux(0x0, "spi0"), /* cs */ - top_mux(0x1, "isp")), /* prelight_trig */ - aon_pin(spi0_txd, top_reg3, 18, 1, 0x68, 0, - aon_mux(0x0, "ext_int"), /* int2 */ - aon_mux(0x1, "agpio"), /* agpio25 */ - aon_mux(0x2, "nonaon"), /* pin7 */ - aon_mux(0x3, "pcu"), /* test1 */ - top_mux(0x0, "spi0"), /* txd */ - top_mux(0x1, "isp")), /* shutter_trig */ - aon_pin(spi0_rxd, top_reg3, 19, 1, 0x68, 9, - aon_mux(0x0, "ext_int"), /* int3 */ - aon_mux(0x1, "agpio"), /* agpio26 */ - aon_mux(0x2, "nonaon"), /* pin8 */ - aon_mux(0x3, "pcu"), /* test2 */ - top_mux(0x0, "spi0"), /* rxd */ - top_mux(0x1, "isp")), /* shutter_open */ - aon_pin(key_col0, top_reg3, 20, 1, 0x68, 18, - aon_mux(0x0, "key"), /* col0 */ - aon_mux(0x1, "agpio"), /* agpio5 */ - aon_mux(0x2, "nonaon"), /* pin9 */ - aon_mux(0x3, "pcu"), /* test3 */ - top_mux(0x0, "uart3"), /* rxd */ - top_mux(0x1, "i2s0")), /* din1 */ - aon_pin(key_col1, top_reg3, 21, 2, 0x6c, 0, - aon_mux(0x0, "key"), /* col1 */ - aon_mux(0x1, "agpio"), /* agpio6 */ - aon_mux(0x2, "nonaon"), /* pin10 */ - top_mux(0x0, "uart3"), /* txd */ - top_mux(0x1, "i2s0"), /* din2 */ - top_mux(0x2, "vga")), /* scl */ - aon_pin(key_col2, top_reg3, 23, 2, 0x6c, 9, - aon_mux(0x0, "key"), /* col2 */ - aon_mux(0x1, "agpio"), /* agpio7 */ - aon_mux(0x2, "nonaon"), /* pin11 */ - top_mux(0x0, "pwm"), /* out1 */ - top_mux(0x1, "i2s0"), /* din3 */ - top_mux(0x2, "vga")), /* sda */ - aon_pin(key_row0, 0, 0, 0, 0x6c, 18, - aon_mux(0x0, "key"), /* row0 */ - aon_mux(0x1, "agpio"), /* agpio8 */ - aon_mux(0x2, "nonaon"), /* pin33 */ - aon_mux(0x3, "wd")), /* rst_b */ - - /* aon_pmm_reg_1 */ - aon_pin(key_row1, top_reg3, 25, 2, 0x70, 0, - aon_mux(0x0, "key"), /* row1 */ - aon_mux(0x1, "agpio"), /* agpio9 */ - aon_mux(0x2, "nonaon"), /* pin12 */ - top_mux(0x0, "lcd"), /* port0 lcd_te */ - top_mux(0x1, "i2s0"), /* dout2 */ - top_mux(0x2, "pwm"), /* out2 */ - top_mux(0x3, "vga")), /* hs1 */ - aon_pin(key_row2, top_reg3, 27, 2, 0x70, 9, - aon_mux(0x0, "key"), /* row2 */ - aon_mux(0x1, "agpio"), /* agpio10 */ - aon_mux(0x2, "nonaon"), /* pin13 */ - top_mux(0x0, "lcd"), /* port1 lcd_te */ - top_mux(0x1, "i2s0"), /* dout3 */ - top_mux(0x2, "pwm"), /* out3 */ - top_mux(0x3, "vga")), /* vs1 */ - aon_pin(hdmi_scl, top_reg3, 29, 1, 0x70, 18, - aon_mux(0x0, "pcu"), /* test7 */ - aon_mux(0x1, "agpio"), /* agpio3 */ - aon_mux(0x2, "nonaon"), /* pin14 */ - top_mux(0x0, "hdmi"), /* scl */ - top_mux(0x1, "uart3")), /* rxd */ - aon_pin(hdmi_sda, top_reg3, 30, 1, 0x74, 0, - aon_mux(0x0, "pcu"), /* test8 */ - aon_mux(0x1, "agpio"), /* agpio4 */ - aon_mux(0x2, "nonaon"), /* pin15 */ - top_mux(0x0, "hdmi"), /* sda */ - top_mux(0x1, "uart3")), /* txd */ - aon_pin(jtag_tck, top_reg7, 3, 1, 0x78, 18, - aon_mux(0x0, "jtag"), /* tck */ - aon_mux(0x1, "agpio"), /* agpio11 */ - aon_mux(0x2, "nonaon"), /* pin22 */ - aon_mux(0x3, "ext_int"), /* int4 */ - top_mux(0x0, "spi4"), /* clk */ - top_mux(0x1, "uart1")), /* rxd */ - aon_pin(jtag_trstn, top_reg7, 4, 1, 0xac, 0, - aon_mux(0x0, "jtag"), /* trstn */ - aon_mux(0x1, "agpio"), /* agpio12 */ - aon_mux(0x2, "nonaon"), /* pin23 */ - aon_mux(0x3, "ext_int"), /* int5 */ - top_mux(0x0, "spi4"), /* cs */ - top_mux(0x1, "uart1")), /* txd */ - aon_pin(jtag_tms, top_reg7, 5, 1, 0xac, 9, - aon_mux(0x0, "jtag"), /* tms */ - aon_mux(0x1, "agpio"), /* agpio13 */ - aon_mux(0x2, "nonaon"), /* pin24 */ - aon_mux(0x3, "ext_int"), /* int6 */ - top_mux(0x0, "spi4"), /* txd */ - top_mux(0x1, "uart2")), /* rxd */ - aon_pin(jtag_tdi, top_reg7, 6, 1, 0xac, 18, - aon_mux(0x0, "jtag"), /* tdi */ - aon_mux(0x1, "agpio"), /* agpio14 */ - aon_mux(0x2, "nonaon"), /* pin25 */ - aon_mux(0x3, "ext_int"), /* int7 */ - top_mux(0x0, "spi4"), /* rxd */ - top_mux(0x1, "uart2")), /* txd */ - aon_pin(jtag_tdo, 0, 0, 0, 0xb0, 0, - aon_mux(0x0, "jtag"), /* tdo */ - aon_mux(0x1, "agpio"), /* agpio15 */ - aon_mux(0x2, "nonaon")), /* pin26 */ - aon_pin(i2c0_scl, 0, 0, 0, 0xb0, 9, - aon_mux(0x0, "i2c0"), /* scl */ - aon_mux(0x1, "agpio"), /* agpio16 */ - aon_mux(0x2, "nonaon")), /* pin28 */ - aon_pin(i2c0_sda, 0, 0, 0, 0xb0, 18, - aon_mux(0x0, "i2c0"), /* sda */ - aon_mux(0x1, "agpio"), /* agpio17 */ - aon_mux(0x2, "nonaon")), /* pin29 */ - aon_pin(i2c1_scl, top_reg8, 4, 1, 0xb4, 0, - aon_mux(0x0, "i2c1"), /* scl */ - aon_mux(0x1, "agpio"), /* agpio18 */ - aon_mux(0x2, "nonaon"), /* pin30 */ - top_mux(0x0, "lcd")), /* port0 lcd_te */ - aon_pin(i2c1_sda, top_reg8, 5, 1, 0xb4, 9, - aon_mux(0x0, "i2c1"), /* sda */ - aon_mux(0x1, "agpio"), /* agpio19 */ - aon_mux(0x2, "nonaon"), /* pin31 */ - top_mux(0x0, "lcd")), /* port1 lcd_te */ - zx_reserved(aon_reserved2), - zx_reserved(aon_reserved3), - zx_reserved(aon_reserved4), - - /* aon_pmm_reg_2 */ - aon_pin(spi1_clk, top_reg2, 6, 3, 0x40, 9, - aon_mux(0x0, "ext_int"), /* int0 */ - aon_mux(0x1, "pcu"), /* test12 */ - aon_mux(0x2, "nonaon"), /* pin39 */ - top_mux(0x0, "spi1"), /* clk */ - top_mux(0x1, "pcm"), /* clk */ - top_mux(0x2, "bgpio"), /* gpio35 */ - top_mux(0x3, "i2c4"), /* scl */ - top_mux(0x4, "i2s1"), /* mclk */ - top_mux(0x5, "isp")), /* flash_trig */ - aon_pin(spi1_cs, top_reg2, 9, 3, 0x40, 18, - aon_mux(0x0, "ext_int"), /* int1 */ - aon_mux(0x1, "pcu"), /* test13 */ - aon_mux(0x2, "nonaon"), /* pin40 */ - top_mux(0x0, "spi1"), /* cs */ - top_mux(0x1, "pcm"), /* fs */ - top_mux(0x2, "bgpio"), /* gpio36 */ - top_mux(0x3, "i2c4"), /* sda */ - top_mux(0x4, "i2s1"), /* bclk */ - top_mux(0x5, "isp")), /* prelight_trig */ - aon_pin(spi1_txd, top_reg2, 12, 3, 0x44, 0, - aon_mux(0x0, "ext_int"), /* int2 */ - aon_mux(0x1, "pcu"), /* test14 */ - aon_mux(0x2, "nonaon"), /* pin41 */ - top_mux(0x0, "spi1"), /* txd */ - top_mux(0x1, "pcm"), /* txd */ - top_mux(0x2, "bgpio"), /* gpio37 */ - top_mux(0x3, "uart5"), /* rxd */ - top_mux(0x4, "i2s1"), /* ws */ - top_mux(0x5, "isp")), /* shutter_trig */ - aon_pin(spi1_rxd, top_reg2, 15, 3, 0x44, 9, - aon_mux(0x0, "ext_int"), /* int3 */ - aon_mux(0x1, "pcu"), /* test15 */ - aon_mux(0x2, "nonaon"), /* pin42 */ - top_mux(0x0, "spi1"), /* rxd */ - top_mux(0x1, "pcm"), /* rxd */ - top_mux(0x2, "bgpio"), /* gpio38 */ - top_mux(0x3, "uart5"), /* txd */ - top_mux(0x4, "i2s1"), /* dout0 */ - top_mux(0x5, "isp")), /* shutter_open */ - zx_reserved(aon_reserved5), - zx_reserved(aon_reserved6), - aon_pin(audio_det, top_reg3, 3, 2, 0x48, 18, - aon_mux(0x0, "pcu"), /* test4 */ - aon_mux(0x1, "agpio"), /* agpio27 */ - aon_mux(0x2, "nonaon"), /* pin2 */ - aon_mux(0x3, "ext_int"), /* int16 */ - top_mux(0x0, "audio"), /* detect */ - top_mux(0x1, "i2c2"), /* scl */ - top_mux(0x2, "spi2")), /* clk */ - aon_pin(spdif_out, top_reg3, 14, 2, 0x78, 9, - aon_mux(0x0, "pcu"), /* test5 */ - aon_mux(0x1, "agpio"), /* agpio22 */ - aon_mux(0x2, "nonaon"), /* pin4 */ - top_mux(0x0, "spdif"), /* out */ - top_mux(0x1, "pwm"), /* out0 */ - top_mux(0x2, "isp")), /* fl_trig */ - aon_pin(hdmi_cec, 0, 0, 0, 0x74, 9, - aon_mux(0x0, "pcu"), /* test9 */ - aon_mux(0x1, "agpio"), /* agpio1 */ - aon_mux(0x2, "nonaon")), /* pin16 */ - aon_pin(hdmi_hpd, 0, 0, 0, 0x74, 18, - aon_mux(0x0, "pcu"), /* test10 */ - aon_mux(0x1, "agpio"), /* agpio2 */ - aon_mux(0x2, "nonaon")), /* pin17 */ - aon_pin(gmac_25m_out, 0, 0, 0, 0x78, 0, - aon_mux(0x0, "pcu"), /* test11 */ - aon_mux(0x1, "agpio"), /* agpio31 */ - aon_mux(0x2, "nonaon")), /* pin43 */ - aon_pin(boot_sel0, 0, 0, 0, 0xc0, 9, - aon_mux(0x0, "boot"), /* sel0 */ - aon_mux(0x1, "agpio"), /* agpio18 */ - aon_mux(0x2, "nonaon")), /* pin18 */ - aon_pin(boot_sel1, 0, 0, 0, 0xc0, 18, - aon_mux(0x0, "boot"), /* sel1 */ - aon_mux(0x1, "agpio"), /* agpio19 */ - aon_mux(0x2, "nonaon")), /* pin19 */ - aon_pin(boot_sel2, 0, 0, 0, 0xc4, 0, - aon_mux(0x0, "boot"), /* sel2 */ - aon_mux(0x1, "agpio"), /* agpio20 */ - aon_mux(0x2, "nonaon")), /* pin20 */ - aon_pin(deep_sleep_out_n, 0, 0, 0, 0xc4, 9, - aon_mux(0x0, "deepslp"), /* deep sleep out_n */ - aon_mux(0x1, "agpio"), /* agpio21 */ - aon_mux(0x2, "nonaon")), /* pin21 */ - zx_reserved(aon_reserved7), - - /* top_pmm_reg_0 */ - top_pin(gmii_gtx_clk, top_reg0, 0, 2, 0x10, 0, - top_mux(0x0, "gmii"), /* gtx_clk */ - top_mux(0x1, "dvi0"), /* clk */ - top_mux(0x2, "bgpio")), /* gpio0 */ - top_pin(gmii_tx_clk, top_reg0, 2, 2, 0x10, 9, - top_mux(0x0, "gmii"), /* tx_clk */ - top_mux(0x1, "dvi0"), /* vs */ - top_mux(0x2, "bgpio")), /* gpio1 */ - top_pin(gmii_txd0, top_reg0, 4, 2, 0x10, 18, - top_mux(0x0, "gmii"), /* txd0 */ - top_mux(0x1, "dvi0"), /* hs */ - top_mux(0x2, "bgpio")), /* gpio2 */ - top_pin(gmii_txd1, top_reg0, 6, 2, 0x14, 0, - top_mux(0x0, "gmii"), /* txd1 */ - top_mux(0x1, "dvi0"), /* d0 */ - top_mux(0x2, "bgpio")), /* gpio3 */ - top_pin(gmii_txd2, top_reg0, 8, 2, 0x14, 9, - top_mux(0x0, "gmii"), /* txd2 */ - top_mux(0x1, "dvi0"), /* d1 */ - top_mux(0x2, "bgpio")), /* gpio4 */ - top_pin(gmii_txd3, top_reg0, 10, 2, 0x14, 18, - top_mux(0x0, "gmii"), /* txd3 */ - top_mux(0x1, "dvi0"), /* d2 */ - top_mux(0x2, "bgpio")), /* gpio5 */ - top_pin(gmii_txd4, top_reg0, 12, 2, 0x18, 0, - top_mux(0x0, "gmii"), /* txd4 */ - top_mux(0x1, "dvi0"), /* d3 */ - top_mux(0x2, "bgpio")), /* gpio6 */ - top_pin(gmii_txd5, top_reg0, 14, 2, 0x18, 9, - top_mux(0x0, "gmii"), /* txd5 */ - top_mux(0x1, "dvi0"), /* d4 */ - top_mux(0x2, "bgpio")), /* gpio7 */ - top_pin(gmii_txd6, top_reg0, 16, 2, 0x18, 18, - top_mux(0x0, "gmii"), /* txd6 */ - top_mux(0x1, "dvi0"), /* d5 */ - top_mux(0x2, "bgpio")), /* gpio8 */ - top_pin(gmii_txd7, top_reg0, 18, 2, 0x1c, 0, - top_mux(0x0, "gmii"), /* txd7 */ - top_mux(0x1, "dvi0"), /* d6 */ - top_mux(0x2, "bgpio")), /* gpio9 */ - top_pin(gmii_tx_er, top_reg0, 20, 2, 0x1c, 9, - top_mux(0x0, "gmii"), /* tx_er */ - top_mux(0x1, "dvi0"), /* d7 */ - top_mux(0x2, "bgpio")), /* gpio10 */ - top_pin(gmii_tx_en, top_reg0, 22, 2, 0x1c, 18, - top_mux(0x0, "gmii"), /* tx_en */ - top_mux(0x1, "dvi0"), /* d8 */ - top_mux(0x3, "bgpio")), /* gpio11 */ - top_pin(gmii_rx_clk, top_reg0, 24, 2, 0x20, 0, - top_mux(0x0, "gmii"), /* rx_clk */ - top_mux(0x1, "dvi0"), /* d9 */ - top_mux(0x3, "bgpio")), /* gpio12 */ - top_pin(gmii_rxd0, top_reg0, 26, 2, 0x20, 9, - top_mux(0x0, "gmii"), /* rxd0 */ - top_mux(0x1, "dvi0"), /* d10 */ - top_mux(0x3, "bgpio")), /* gpio13 */ - top_pin(gmii_rxd1, top_reg0, 28, 2, 0x20, 18, - top_mux(0x0, "gmii"), /* rxd1 */ - top_mux(0x1, "dvi0"), /* d11 */ - top_mux(0x2, "bgpio")), /* gpio14 */ - top_pin(gmii_rxd2, top_reg0, 30, 2, 0x24, 0, - top_mux(0x0, "gmii"), /* rxd2 */ - top_mux(0x1, "dvi1"), /* clk */ - top_mux(0x2, "bgpio")), /* gpio15 */ - - /* top_pmm_reg_1 */ - top_pin(gmii_rxd3, top_reg1, 0, 2, 0x24, 9, - top_mux(0x0, "gmii"), /* rxd3 */ - top_mux(0x1, "dvi1"), /* hs */ - top_mux(0x2, "bgpio")), /* gpio16 */ - top_pin(gmii_rxd4, top_reg1, 2, 2, 0x24, 18, - top_mux(0x0, "gmii"), /* rxd4 */ - top_mux(0x1, "dvi1"), /* vs */ - top_mux(0x2, "bgpio")), /* gpio17 */ - top_pin(gmii_rxd5, top_reg1, 4, 2, 0x28, 0, - top_mux(0x0, "gmii"), /* rxd5 */ - top_mux(0x1, "dvi1"), /* d0 */ - top_mux(0x2, "bgpio"), /* gpio18 */ - top_mux(0x3, "tsi0")), /* dat0 */ - top_pin(gmii_rxd6, top_reg1, 6, 2, 0x28, 9, - top_mux(0x0, "gmii"), /* rxd6 */ - top_mux(0x1, "dvi1"), /* d1 */ - top_mux(0x2, "bgpio"), /* gpio19 */ - top_mux(0x3, "tsi0")), /* clk */ - top_pin(gmii_rxd7, top_reg1, 8, 2, 0x28, 18, - top_mux(0x0, "gmii"), /* rxd7 */ - top_mux(0x1, "dvi1"), /* d2 */ - top_mux(0x2, "bgpio"), /* gpio20 */ - top_mux(0x3, "tsi0")), /* sync */ - top_pin(gmii_rx_er, top_reg1, 10, 2, 0x2c, 0, - top_mux(0x0, "gmii"), /* rx_er */ - top_mux(0x1, "dvi1"), /* d3 */ - top_mux(0x2, "bgpio"), /* gpio21 */ - top_mux(0x3, "tsi0")), /* valid */ - top_pin(gmii_rx_dv, top_reg1, 12, 2, 0x2c, 9, - top_mux(0x0, "gmii"), /* rx_dv */ - top_mux(0x1, "dvi1"), /* d4 */ - top_mux(0x2, "bgpio"), /* gpio22 */ - top_mux(0x3, "tsi1")), /* dat0 */ - top_pin(gmii_col, top_reg1, 14, 2, 0x2c, 18, - top_mux(0x0, "gmii"), /* col */ - top_mux(0x1, "dvi1"), /* d5 */ - top_mux(0x2, "bgpio"), /* gpio23 */ - top_mux(0x3, "tsi1")), /* clk */ - top_pin(gmii_crs, top_reg1, 16, 2, 0x30, 0, - top_mux(0x0, "gmii"), /* crs */ - top_mux(0x1, "dvi1"), /* d6 */ - top_mux(0x2, "bgpio"), /* gpio24 */ - top_mux(0x3, "tsi1")), /* sync */ - top_pin(gmii_mdc, top_reg1, 18, 2, 0x30, 9, - top_mux(0x0, "gmii"), /* mdc */ - top_mux(0x1, "dvi1"), /* d7 */ - top_mux(0x2, "bgpio"), /* gpio25 */ - top_mux(0x3, "tsi1")), /* valid */ - top_pin(gmii_mdio, top_reg1, 20, 1, 0x30, 18, - top_mux(0x0, "gmii"), /* mdio */ - top_mux(0x2, "bgpio")), /* gpio26 */ - top_pin(sdio1_clk, top_reg1, 21, 2, 0x34, 18, - top_mux(0x0, "sdio1"), /* clk */ - top_mux(0x1, "usim0"), /* clk */ - top_mux(0x2, "bgpio"), /* gpio27 */ - top_mux(0x3, "spinor")), /* clk */ - top_pin(sdio1_cmd, top_reg1, 23, 2, 0x38, 0, - top_mux(0x0, "sdio1"), /* cmd */ - top_mux(0x1, "usim0"), /* cd */ - top_mux(0x2, "bgpio"), /* gpio28 */ - top_mux(0x3, "spinor")), /* cs */ - top_pin(sdio1_data0, top_reg1, 25, 2, 0x38, 9, - top_mux(0x0, "sdio1"), /* dat0 */ - top_mux(0x1, "usim0"), /* rst */ - top_mux(0x2, "bgpio"), /* gpio29 */ - top_mux(0x3, "spinor")), /* dq0 */ - top_pin(sdio1_data1, top_reg1, 27, 2, 0x38, 18, - top_mux(0x0, "sdio1"), /* dat1 */ - top_mux(0x1, "usim0"), /* data */ - top_mux(0x2, "bgpio"), /* gpio30 */ - top_mux(0x3, "spinor")), /* dq1 */ - top_pin(sdio1_data2, top_reg1, 29, 2, 0x3c, 0, - top_mux(0x0, "sdio1"), /* dat2 */ - top_mux(0x1, "bgpio"), /* gpio31 */ - top_mux(0x2, "spinor")), /* dq2 */ - - /* top_pmm_reg_2 */ - top_pin(sdio1_data3, top_reg2, 0, 2, 0x3c, 9, - top_mux(0x0, "sdio1"), /* dat3 */ - top_mux(0x1, "bgpio"), /* gpio32 */ - top_mux(0x2, "spinor")), /* dq3 */ - top_pin(sdio1_cd, top_reg2, 2, 2, 0x3c, 18, - top_mux(0x0, "sdio1"), /* cd */ - top_mux(0x1, "bgpio"), /* gpio33 */ - top_mux(0x2, "isp")), /* fl_trig */ - top_pin(sdio1_wp, top_reg2, 4, 2, 0x40, 0, - top_mux(0x0, "sdio1"), /* wp */ - top_mux(0x1, "bgpio"), /* gpio34 */ - top_mux(0x2, "isp")), /* ref_clk */ - top_pin(usim1_cd, top_reg2, 22, 3, 0x44, 18, - top_mux(0x0, "usim1"), /* cd */ - top_mux(0x1, "uart4"), /* rxd */ - top_mux(0x2, "bgpio"), /* gpio39 */ - top_mux(0x3, "spi3"), /* clk */ - top_mux(0x4, "i2s0"), /* bclk */ - top_mux(0x5, "b_dvi0")), /* d8 */ - top_pin(usim1_clk, top_reg2, 25, 3, 0x4c, 18, - top_mux(0x0, "usim1"), /* clk */ - top_mux(0x1, "uart4"), /* txd */ - top_mux(0x2, "bgpio"), /* gpio40 */ - top_mux(0x3, "spi3"), /* cs */ - top_mux(0x4, "i2s0"), /* ws */ - top_mux(0x5, "b_dvi0")), /* d9 */ - top_pin(usim1_rst, top_reg2, 28, 3, 0x4c, 0, - top_mux(0x0, "usim1"), /* rst */ - top_mux(0x1, "uart4"), /* cts */ - top_mux(0x2, "bgpio"), /* gpio41 */ - top_mux(0x3, "spi3"), /* txd */ - top_mux(0x4, "i2s0"), /* dout0 */ - top_mux(0x5, "b_dvi0")), /* d10 */ - - /* top_pmm_reg_3 */ - top_pin(usim1_data, top_reg3, 0, 3, 0x4c, 9, - top_mux(0x0, "usim1"), /* dat */ - top_mux(0x1, "uart4"), /* rst */ - top_mux(0x2, "bgpio"), /* gpio42 */ - top_mux(0x3, "spi3"), /* rxd */ - top_mux(0x4, "i2s0"), /* din0 */ - top_mux(0x5, "b_dvi0")), /* d11 */ - top_pin(sdio0_clk, top_reg3, 6, 1, 0x58, 0, - top_mux(0x0, "sdio0"), /* clk */ - top_mux(0x1, "gpio")), /* gpio43 */ - top_pin(sdio0_cmd, top_reg3, 7, 1, 0x58, 9, - top_mux(0x0, "sdio0"), /* cmd */ - top_mux(0x1, "gpio")), /* gpio44 */ - top_pin(sdio0_data0, top_reg3, 8, 1, 0x58, 18, - top_mux(0x0, "sdio0"), /* dat0 */ - top_mux(0x1, "gpio")), /* gpio45 */ - top_pin(sdio0_data1, top_reg3, 9, 1, 0x5c, 0, - top_mux(0x0, "sdio0"), /* dat1 */ - top_mux(0x1, "gpio")), /* gpio46 */ - top_pin(sdio0_data2, top_reg3, 10, 1, 0x5c, 9, - top_mux(0x0, "sdio0"), /* dat2 */ - top_mux(0x1, "gpio")), /* gpio47 */ - top_pin(sdio0_data3, top_reg3, 11, 1, 0x5c, 18, - top_mux(0x0, "sdio0"), /* dat3 */ - top_mux(0x1, "gpio")), /* gpio48 */ - top_pin(sdio0_cd, top_reg3, 12, 1, 0x60, 0, - top_mux(0x0, "sdio0"), /* cd */ - top_mux(0x1, "gpio")), /* gpio49 */ - top_pin(sdio0_wp, top_reg3, 13, 1, 0x60, 9, - top_mux(0x0, "sdio0"), /* wp */ - top_mux(0x1, "gpio")), /* gpio50 */ - - /* top_pmm_reg_4 */ - top_pin(tsi0_data0, top_reg4, 0, 2, 0x60, 18, - top_mux(0x0, "tsi0"), /* dat0 */ - top_mux(0x1, "lcd"), /* clk */ - top_mux(0x2, "bgpio")), /* gpio51 */ - top_pin(spinor_clk, top_reg4, 2, 2, 0xa8, 18, - top_mux(0x0, "spinor"), /* clk */ - top_mux(0x1, "tsi0"), /* dat1 */ - top_mux(0x2, "lcd"), /* dat0 */ - top_mux(0x3, "bgpio")), /* gpio52 */ - top_pin(tsi2_data, top_reg4, 4, 2, 0x7c, 0, - top_mux(0x0, "tsi2"), /* dat */ - top_mux(0x1, "tsi0"), /* dat2 */ - top_mux(0x2, "lcd"), /* dat1 */ - top_mux(0x3, "bgpio")), /* gpio53 */ - top_pin(tsi2_clk, top_reg4, 6, 2, 0x7c, 9, - top_mux(0x0, "tsi2"), /* clk */ - top_mux(0x1, "tsi0"), /* dat3 */ - top_mux(0x2, "lcd"), /* dat2 */ - top_mux(0x3, "bgpio")), /* gpio54 */ - top_pin(tsi2_sync, top_reg4, 8, 2, 0x7c, 18, - top_mux(0x0, "tsi2"), /* sync */ - top_mux(0x1, "tsi0"), /* dat4 */ - top_mux(0x2, "lcd"), /* dat3 */ - top_mux(0x3, "bgpio")), /* gpio55 */ - top_pin(tsi2_valid, top_reg4, 10, 2, 0x80, 0, - top_mux(0x0, "tsi2"), /* valid */ - top_mux(0x1, "tsi0"), /* dat5 */ - top_mux(0x2, "lcd"), /* dat4 */ - top_mux(0x3, "bgpio")), /* gpio56 */ - top_pin(spinor_cs, top_reg4, 12, 2, 0x80, 9, - top_mux(0x0, "spinor"), /* cs */ - top_mux(0x1, "tsi0"), /* dat6 */ - top_mux(0x2, "lcd"), /* dat5 */ - top_mux(0x3, "bgpio")), /* gpio57 */ - top_pin(spinor_dq0, top_reg4, 14, 2, 0x80, 18, - top_mux(0x0, "spinor"), /* dq0 */ - top_mux(0x1, "tsi0"), /* dat7 */ - top_mux(0x2, "lcd"), /* dat6 */ - top_mux(0x3, "bgpio")), /* gpio58 */ - top_pin(spinor_dq1, top_reg4, 16, 2, 0x84, 0, - top_mux(0x0, "spinor"), /* dq1 */ - top_mux(0x1, "tsi0"), /* clk */ - top_mux(0x2, "lcd"), /* dat7 */ - top_mux(0x3, "bgpio")), /* gpio59 */ - top_pin(spinor_dq2, top_reg4, 18, 2, 0x84, 9, - top_mux(0x0, "spinor"), /* dq2 */ - top_mux(0x1, "tsi0"), /* sync */ - top_mux(0x2, "lcd"), /* dat8 */ - top_mux(0x3, "bgpio")), /* gpio60 */ - top_pin(spinor_dq3, top_reg4, 20, 2, 0x84, 18, - top_mux(0x0, "spinor"), /* dq3 */ - top_mux(0x1, "tsi0"), /* valid */ - top_mux(0x2, "lcd"), /* dat9 */ - top_mux(0x3, "bgpio")), /* gpio61 */ - top_pin(vga_hs, top_reg4, 22, 3, 0x88, 0, - top_mux(0x0, "vga"), /* hs */ - top_mux(0x1, "tsi1"), /* dat0 */ - top_mux(0x2, "lcd"), /* dat10 */ - top_mux(0x3, "bgpio"), /* gpio62 */ - top_mux(0x4, "i2s1"), /* din1 */ - top_mux(0x5, "b_dvi0")), /* clk */ - top_pin(vga_vs, top_reg4, 25, 3, 0x88, 9, - top_mux(0x0, "vga"), /* vs0 */ - top_mux(0x1, "tsi1"), /* dat1 */ - top_mux(0x2, "lcd"), /* dat11 */ - top_mux(0x3, "bgpio"), /* gpio63 */ - top_mux(0x4, "i2s1"), /* din2 */ - top_mux(0x5, "b_dvi0")), /* vs */ - top_pin(tsi3_data, top_reg4, 28, 3, 0x88, 18, - top_mux(0x0, "tsi3"), /* dat */ - top_mux(0x1, "tsi1"), /* dat2 */ - top_mux(0x2, "lcd"), /* dat12 */ - top_mux(0x3, "bgpio"), /* gpio64 */ - top_mux(0x4, "i2s1"), /* din3 */ - top_mux(0x5, "b_dvi0")), /* hs */ - - /* top_pmm_reg_5 */ - top_pin(tsi3_clk, top_reg5, 0, 3, 0x8c, 0, - top_mux(0x0, "tsi3"), /* clk */ - top_mux(0x1, "tsi1"), /* dat3 */ - top_mux(0x2, "lcd"), /* dat13 */ - top_mux(0x3, "bgpio"), /* gpio65 */ - top_mux(0x4, "i2s1"), /* dout1 */ - top_mux(0x5, "b_dvi0")), /* d0 */ - top_pin(tsi3_sync, top_reg5, 3, 3, 0x8c, 9, - top_mux(0x0, "tsi3"), /* sync */ - top_mux(0x1, "tsi1"), /* dat4 */ - top_mux(0x2, "lcd"), /* dat14 */ - top_mux(0x3, "bgpio"), /* gpio66 */ - top_mux(0x4, "i2s1"), /* dout2 */ - top_mux(0x5, "b_dvi0")), /* d1 */ - top_pin(tsi3_valid, top_reg5, 6, 3, 0x8c, 18, - top_mux(0x0, "tsi3"), /* valid */ - top_mux(0x1, "tsi1"), /* dat5 */ - top_mux(0x2, "lcd"), /* dat15 */ - top_mux(0x3, "bgpio"), /* gpio67 */ - top_mux(0x4, "i2s1"), /* dout3 */ - top_mux(0x5, "b_dvi0")), /* d2 */ - top_pin(i2s1_ws, top_reg5, 9, 3, 0x90, 0, - top_mux(0x0, "i2s1"), /* ws */ - top_mux(0x1, "tsi1"), /* dat6 */ - top_mux(0x2, "lcd"), /* dat16 */ - top_mux(0x3, "bgpio"), /* gpio68 */ - top_mux(0x4, "vga"), /* scl */ - top_mux(0x5, "b_dvi0")), /* d3 */ - top_pin(i2s1_bclk, top_reg5, 12, 3, 0x90, 9, - top_mux(0x0, "i2s1"), /* bclk */ - top_mux(0x1, "tsi1"), /* dat7 */ - top_mux(0x2, "lcd"), /* dat17 */ - top_mux(0x3, "bgpio"), /* gpio69 */ - top_mux(0x4, "vga"), /* sda */ - top_mux(0x5, "b_dvi0")), /* d4 */ - top_pin(i2s1_mclk, top_reg5, 15, 2, 0x90, 18, - top_mux(0x0, "i2s1"), /* mclk */ - top_mux(0x1, "tsi1"), /* clk */ - top_mux(0x2, "lcd"), /* dat18 */ - top_mux(0x3, "bgpio")), /* gpio70 */ - top_pin(i2s1_din0, top_reg5, 17, 2, 0x94, 0, - top_mux(0x0, "i2s1"), /* din0 */ - top_mux(0x1, "tsi1"), /* sync */ - top_mux(0x2, "lcd"), /* dat19 */ - top_mux(0x3, "bgpio")), /* gpio71 */ - top_pin(i2s1_dout0, top_reg5, 19, 2, 0x94, 9, - top_mux(0x0, "i2s1"), /* dout0 */ - top_mux(0x1, "tsi1"), /* valid */ - top_mux(0x2, "lcd"), /* dat20 */ - top_mux(0x3, "bgpio")), /* gpio72 */ - top_pin(spi3_clk, top_reg5, 21, 3, 0x94, 18, - top_mux(0x0, "spi3"), /* clk */ - top_mux(0x1, "tso1"), /* clk */ - top_mux(0x2, "lcd"), /* dat21 */ - top_mux(0x3, "bgpio"), /* gpio73 */ - top_mux(0x4, "uart5"), /* rxd */ - top_mux(0x5, "pcm"), /* fs */ - top_mux(0x6, "i2s0"), /* din1 */ - top_mux(0x7, "b_dvi0")), /* d5 */ - top_pin(spi3_cs, top_reg5, 24, 3, 0x98, 0, - top_mux(0x0, "spi3"), /* cs */ - top_mux(0x1, "tso1"), /* dat0 */ - top_mux(0x2, "lcd"), /* dat22 */ - top_mux(0x3, "bgpio"), /* gpio74 */ - top_mux(0x4, "uart5"), /* txd */ - top_mux(0x5, "pcm"), /* clk */ - top_mux(0x6, "i2s0"), /* din2 */ - top_mux(0x7, "b_dvi0")), /* d6 */ - top_pin(spi3_txd, top_reg5, 27, 3, 0x98, 9, - top_mux(0x0, "spi3"), /* txd */ - top_mux(0x1, "tso1"), /* dat1 */ - top_mux(0x2, "lcd"), /* dat23 */ - top_mux(0x3, "bgpio"), /* gpio75 */ - top_mux(0x4, "uart5"), /* cts */ - top_mux(0x5, "pcm"), /* txd */ - top_mux(0x6, "i2s0"), /* din3 */ - top_mux(0x7, "b_dvi0")), /* d7 */ - top_pin(nand_ldo_ms18_sel, top_reg5, 30, 1, 0xe4, 0, - top_mux(0x0, "nand"), /* ldo_ms18_sel */ - top_mux(0x1, "bgpio")), /* gpio99 */ - - /* top_pmm_reg_6 */ - top_pin(spi3_rxd, top_reg6, 0, 3, 0x98, 18, - top_mux(0x0, "spi3"), /* rxd */ - top_mux(0x1, "tso1"), /* dat2 */ - top_mux(0x2, "lcd"), /* stvu_vsync */ - top_mux(0x3, "bgpio"), /* gpio76 */ - top_mux(0x4, "uart5"), /* rts */ - top_mux(0x5, "pcm"), /* rxd */ - top_mux(0x6, "i2s0"), /* dout1 */ - top_mux(0x7, "b_dvi1")), /* clk */ - top_pin(i2s0_mclk, top_reg6, 3, 3, 0x9c, 0, - top_mux(0x0, "i2s0"), /* mclk */ - top_mux(0x1, "tso1"), /* dat3 */ - top_mux(0x2, "lcd"), /* stvd */ - top_mux(0x3, "bgpio"), /* gpio77 */ - top_mux(0x4, "usim0"), /* cd */ - top_mux(0x5, "b_dvi1")), /* vs */ - top_pin(i2s0_bclk, top_reg6, 6, 3, 0x9c, 9, - top_mux(0x0, "i2s0"), /* bclk */ - top_mux(0x1, "tso1"), /* dat4 */ - top_mux(0x2, "lcd"), /* sthl_hsync */ - top_mux(0x3, "bgpio"), /* gpio78 */ - top_mux(0x4, "usim0"), /* clk */ - top_mux(0x5, "b_dvi1")), /* hs */ - top_pin(i2s0_ws, top_reg6, 9, 3, 0x9c, 18, - top_mux(0x0, "i2s0"), /* ws */ - top_mux(0x1, "tso1"), /* dat5 */ - top_mux(0x2, "lcd"), /* sthr */ - top_mux(0x3, "bgpio"), /* gpio79 */ - top_mux(0x4, "usim0"), /* rst */ - top_mux(0x5, "b_dvi1")), /* d0 */ - top_pin(i2s0_din0, top_reg6, 12, 3, 0xa0, 0, - top_mux(0x0, "i2s0"), /* din0 */ - top_mux(0x1, "tso1"), /* dat6 */ - top_mux(0x2, "lcd"), /* oev_dataen */ - top_mux(0x3, "bgpio"), /* gpio80 */ - top_mux(0x4, "usim0"), /* dat */ - top_mux(0x5, "b_dvi1")), /* d1 */ - top_pin(i2s0_dout0, top_reg6, 15, 2, 0xa0, 9, - top_mux(0x0, "i2s0"), /* dout0 */ - top_mux(0x1, "tso1"), /* dat7 */ - top_mux(0x2, "lcd"), /* ckv */ - top_mux(0x3, "bgpio")), /* gpio81 */ - top_pin(i2c5_scl, top_reg6, 17, 3, 0xa0, 18, - top_mux(0x0, "i2c5"), /* scl */ - top_mux(0x1, "tso1"), /* sync */ - top_mux(0x2, "lcd"), /* ld */ - top_mux(0x3, "bgpio"), /* gpio82 */ - top_mux(0x4, "pwm"), /* out2 */ - top_mux(0x5, "i2s0"), /* dout2 */ - top_mux(0x6, "b_dvi1")), /* d2 */ - top_pin(i2c5_sda, top_reg6, 20, 3, 0xa4, 0, - top_mux(0x0, "i2c5"), /* sda */ - top_mux(0x1, "tso1"), /* vld */ - top_mux(0x2, "lcd"), /* pol */ - top_mux(0x3, "bgpio"), /* gpio83 */ - top_mux(0x4, "pwm"), /* out3 */ - top_mux(0x5, "i2s0"), /* dout3 */ - top_mux(0x6, "b_dvi1")), /* d3 */ - top_pin(spi2_clk, top_reg6, 23, 3, 0xa4, 9, - top_mux(0x0, "spi2"), /* clk */ - top_mux(0x1, "tso0"), /* clk */ - top_mux(0x2, "lcd"), /* degsl */ - top_mux(0x3, "bgpio"), /* gpio84 */ - top_mux(0x4, "i2c4"), /* scl */ - top_mux(0x5, "b_dvi1")), /* d4 */ - top_pin(spi2_cs, top_reg6, 26, 3, 0xa4, 18, - top_mux(0x0, "spi2"), /* cs */ - top_mux(0x1, "tso0"), /* data */ - top_mux(0x2, "lcd"), /* rev */ - top_mux(0x3, "bgpio"), /* gpio85 */ - top_mux(0x4, "i2c4"), /* sda */ - top_mux(0x5, "b_dvi1")), /* d5 */ - top_pin(spi2_txd, top_reg6, 29, 3, 0xa8, 0, - top_mux(0x0, "spi2"), /* txd */ - top_mux(0x1, "tso0"), /* sync */ - top_mux(0x2, "lcd"), /* u_d */ - top_mux(0x3, "bgpio"), /* gpio86 */ - top_mux(0x4, "i2c4"), /* scl */ - top_mux(0x5, "b_dvi1")), /* d6 */ - - /* top_pmm_reg_7 */ - top_pin(spi2_rxd, top_reg7, 0, 3, 0xa8, 9, - top_mux(0x0, "spi2"), /* rxd */ - top_mux(0x1, "tso0"), /* vld */ - top_mux(0x2, "lcd"), /* r_l */ - top_mux(0x3, "bgpio"), /* gpio87 */ - top_mux(0x4, "i2c3"), /* sda */ - top_mux(0x5, "b_dvi1")), /* d7 */ - top_pin(nand_wp_n, top_reg7, 7, 3, 0x54, 9, - top_mux(0x0, "nand"), /* wp */ - top_mux(0x1, "pwm"), /* out2 */ - top_mux(0x2, "spi2"), /* clk */ - top_mux(0x3, "bgpio"), /* gpio88 */ - top_mux(0x4, "tsi0"), /* dat0 */ - top_mux(0x5, "i2s1")), /* din1 */ - top_pin(nand_page_size0, top_reg7, 10, 3, 0xb8, 0, - top_mux(0x0, "nand"), /* boot_pagesize0 */ - top_mux(0x1, "pwm"), /* out3 */ - top_mux(0x2, "spi2"), /* cs */ - top_mux(0x3, "bgpio"), /* gpio89 */ - top_mux(0x4, "tsi0"), /* clk */ - top_mux(0x5, "i2s1")), /* din2 */ - top_pin(nand_page_size1, top_reg7, 13, 3, 0xb8, 9, - top_mux(0x0, "nand"), /* boot_pagesize1 */ - top_mux(0x1, "i2c4"), /* scl */ - top_mux(0x2, "spi2"), /* txd */ - top_mux(0x3, "bgpio"), /* gpio90 */ - top_mux(0x4, "tsi0"), /* sync */ - top_mux(0x5, "i2s1")), /* din3 */ - top_pin(nand_addr_cycle, top_reg7, 16, 3, 0xb8, 18, - top_mux(0x0, "nand"), /* boot_addr_cycles */ - top_mux(0x1, "i2c4"), /* sda */ - top_mux(0x2, "spi2"), /* rxd */ - top_mux(0x3, "bgpio"), /* gpio91 */ - top_mux(0x4, "tsi0"), /* valid */ - top_mux(0x5, "i2s1")), /* dout1 */ - top_pin(nand_rb0, top_reg7, 19, 3, 0xbc, 0, - top_mux(0x0, "nand"), /* rdy_busy0 */ - top_mux(0x1, "i2c2"), /* scl */ - top_mux(0x2, "usim0"), /* cd */ - top_mux(0x3, "bgpio"), /* gpio92 */ - top_mux(0x4, "tsi1")), /* data0 */ - top_pin(nand_rb1, top_reg7, 22, 3, 0xbc, 9, - top_mux(0x0, "nand"), /* rdy_busy1 */ - top_mux(0x1, "i2c2"), /* sda */ - top_mux(0x2, "usim0"), /* clk */ - top_mux(0x3, "bgpio"), /* gpio93 */ - top_mux(0x4, "tsi1")), /* clk */ - top_pin(nand_rb2, top_reg7, 25, 3, 0xbc, 18, - top_mux(0x0, "nand"), /* rdy_busy2 */ - top_mux(0x1, "uart5"), /* rxd */ - top_mux(0x2, "usim0"), /* rst */ - top_mux(0x3, "bgpio"), /* gpio94 */ - top_mux(0x4, "tsi1"), /* sync */ - top_mux(0x4, "i2s1")), /* dout2 */ - top_pin(nand_rb3, top_reg7, 28, 3, 0x54, 18, - top_mux(0x0, "nand"), /* rdy_busy3 */ - top_mux(0x1, "uart5"), /* txd */ - top_mux(0x2, "usim0"), /* dat */ - top_mux(0x3, "bgpio"), /* gpio95 */ - top_mux(0x4, "tsi1"), /* valid */ - top_mux(0x4, "i2s1")), /* dout3 */ - - /* top_pmm_reg_8 */ - top_pin(gmac_125m_in, top_reg8, 0, 2, 0x34, 0, - top_mux(0x0, "gmii"), /* 125m_in */ - top_mux(0x1, "usb2"), /* 0_drvvbus */ - top_mux(0x2, "isp"), /* ref_clk */ - top_mux(0x3, "bgpio")), /* gpio96 */ - top_pin(gmac_50m_out, top_reg8, 2, 2, 0x34, 9, - top_mux(0x0, "gmii"), /* 50m_out */ - top_mux(0x1, "usb2"), /* 1_drvvbus */ - top_mux(0x2, "bgpio"), /* gpio97 */ - top_mux(0x3, "usb2")), /* 0_drvvbus */ - top_pin(spinor_ssclk_loopback, top_reg8, 6, 1, 0xc8, 9, - top_mux(0x0, "spinor")), /* sdio1_clk_i */ - top_pin(spinor_sdio1clk_loopback, top_reg8, 7, 1, 0xc8, 18, - top_mux(0x0, "spinor")), /* ssclk_i */ -}; - -static struct zx_pinctrl_soc_info zx296718_pinctrl_info = { - .pins = zx296718_pins, - .npins = array_size(zx296718_pins), -}; - -static int zx296718_pinctrl_probe(struct platform_device *pdev) -{ - return zx_pinctrl_init(pdev, &zx296718_pinctrl_info); -} - -static const struct of_device_id zx296718_pinctrl_match[] = { - { .compatible = "zte,zx296718-pmm", }, - {} -}; -module_device_table(of, zx296718_pinctrl_match); - -static struct platform_driver zx296718_pinctrl_driver = { - .probe = zx296718_pinctrl_probe, - .driver = { - .name = "zx296718-pinctrl", - .of_match_table = zx296718_pinctrl_match, - }, -}; -builtin_platform_driver(zx296718_pinctrl_driver); - -module_description("zte zx296718 pinctrl driver"); -module_license("gpl");
|
Pin Controllers (pinctrl)
|
484c58d6601c2868e9763e105443ef57d562ee3b
|
arnd bergmann
|
drivers
|
pinctrl
|
bindings, pinctrl, zte
|
mmc: core: add basic support for inline encryption
|
in preparation for adding cqhci crypto engine (inline encryption) support, add the code required to make mmc_core and mmc_block aware of inline encryption. specifically:
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
emmc inline encryption support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['h', 'kconfig', 'c', 'makefile']
| 10
| 124
| 0
|
- add a capability flag mmc_cap2_crypto to struct mmc_host. drivers - embed a blk_keyslot_manager in struct mmc_host. drivers will - make mmc_block copy the crypto keyslot and crypto data unit number - if the mmc host is reset, reprogram all the keyslots to ensure that --- diff --git a/drivers/mmc/core/kconfig b/drivers/mmc/core/kconfig --- a/drivers/mmc/core/kconfig +++ b/drivers/mmc/core/kconfig +config mmc_crypto + bool "mmc crypto engine support" + depends on blk_inline_encryption + help + enable crypto engine support in mmc. + enabling this makes it possible for the kernel to use the crypto + capabilities of the mmc device (if present) to perform crypto + operations on data being transferred to/from the device. diff --git a/drivers/mmc/core/makefile b/drivers/mmc/core/makefile --- a/drivers/mmc/core/makefile +++ b/drivers/mmc/core/makefile +mmc_core-$(config_mmc_crypto) += crypto.o diff --git a/drivers/mmc/core/block.c b/drivers/mmc/core/block.c --- a/drivers/mmc/core/block.c +++ b/drivers/mmc/core/block.c +#include "crypto.h" + mmc_crypto_prepare_req(mqrq); + diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c +#include "crypto.h" + + mmc_crypto_set_initial_state(host); diff --git a/drivers/mmc/core/crypto.c b/drivers/mmc/core/crypto.c --- /dev/null +++ b/drivers/mmc/core/crypto.c +// spdx-license-identifier: gpl-2.0-only +/* + * mmc crypto engine (inline encryption) support + * + * copyright 2020 google llc + */ + +#include <linux/blk-crypto.h> +#include <linux/mmc/host.h> + +#include "core.h" +#include "crypto.h" +#include "queue.h" + +void mmc_crypto_set_initial_state(struct mmc_host *host) +{ + /* reset might clear all keys, so reprogram all the keys. */ + if (host->caps2 & mmc_cap2_crypto) + blk_ksm_reprogram_all_keys(&host->ksm); +} + +void mmc_crypto_setup_queue(struct request_queue *q, struct mmc_host *host) +{ + if (host->caps2 & mmc_cap2_crypto) + blk_ksm_register(&host->ksm, q); +} +export_symbol_gpl(mmc_crypto_setup_queue); + +void mmc_crypto_prepare_req(struct mmc_queue_req *mqrq) +{ + struct request *req = mmc_queue_req_to_req(mqrq); + struct mmc_request *mrq = &mqrq->brq.mrq; + + if (!req->crypt_keyslot) + return; + + mrq->crypto_enabled = true; + mrq->crypto_key_slot = blk_ksm_get_slot_idx(req->crypt_keyslot); + + /* + * for now we assume that all mmc drivers set max_dun_bytes_supported=4, + * which is the limit for cqhci crypto. so all duns should be 32-bit. + */ + warn_on_once(req->crypt_ctx->bc_dun[0] > u32_max); + + mrq->data_unit_num = req->crypt_ctx->bc_dun[0]; +} +export_symbol_gpl(mmc_crypto_prepare_req); diff --git a/drivers/mmc/core/crypto.h b/drivers/mmc/core/crypto.h --- /dev/null +++ b/drivers/mmc/core/crypto.h +/* spdx-license-identifier: gpl-2.0-only */ +/* + * mmc crypto engine (inline encryption) support + * + * copyright 2020 google llc + */ + +#ifndef _mmc_core_crypto_h +#define _mmc_core_crypto_h + +struct mmc_host; +struct mmc_queue_req; +struct request_queue; + +#ifdef config_mmc_crypto + +void mmc_crypto_set_initial_state(struct mmc_host *host); + +void mmc_crypto_setup_queue(struct request_queue *q, struct mmc_host *host); + +void mmc_crypto_prepare_req(struct mmc_queue_req *mqrq); + +#else /* config_mmc_crypto */ + +static inline void mmc_crypto_set_initial_state(struct mmc_host *host) +{ +} + +static inline void mmc_crypto_setup_queue(struct request_queue *q, + struct mmc_host *host) +{ +} + +static inline void mmc_crypto_prepare_req(struct mmc_queue_req *mqrq) +{ +} + +#endif /* !config_mmc_crypto */ + +#endif /* _mmc_core_crypto_h */ diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c --- a/drivers/mmc/core/host.c +++ b/drivers/mmc/core/host.c +#include "crypto.h" diff --git a/drivers/mmc/core/queue.c b/drivers/mmc/core/queue.c --- a/drivers/mmc/core/queue.c +++ b/drivers/mmc/core/queue.c +#include "crypto.h" + + mmc_crypto_setup_queue(mq->queue, host); diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h --- a/include/linux/mmc/core.h +++ b/include/linux/mmc/core.h + +#ifdef config_mmc_crypto + bool crypto_enabled; + int crypto_key_slot; + u32 data_unit_num; +#endif diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h +#include <linux/keyslot-manager.h> +#ifdef config_mmc_crypto +#define mmc_cap2_crypto (1 << 27) /* host supports inline encryption */ +#else +#define mmc_cap2_crypto 0 +#endif + /* inline encryption support */ +#ifdef config_mmc_crypto + struct blk_keyslot_manager ksm; +#endif +
|
Multi Media Card (MMC)
|
93f1c150cb0d043e1e8985db7824b4e2e1ac653f
|
eric biggers
|
include
|
linux
|
core, mmc
|
mmc: cqhci: rename cqhci.c to cqhci-core.c
|
rename cqhci.c to cqhci-core.c so that another source file can be added to the cqhci module without having to rename the module.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
emmc inline encryption support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['c', 'makefile']
| 2
| 1
| 0
|
--- diff --git a/drivers/mmc/host/makefile b/drivers/mmc/host/makefile --- a/drivers/mmc/host/makefile +++ b/drivers/mmc/host/makefile +cqhci-y += cqhci-core.o diff --git a/drivers/mmc/host/cqhci.c b/drivers/mmc/host/cqhci-core.c
|
Multi Media Card (MMC)
|
0653300224a696719953a19efe13e1c6e9b8cceb
|
eric biggers adrian hunter adrian hunter intel com
|
drivers
|
mmc
|
host
|
mmc: cqhci: initialize upper 64 bits of 128-bit task descriptors
|
move the task descriptor initialization into cqhci_prep_task_desc(). in addition, make it explicitly initialize all 128 bits of the task descriptor if the host controller is using 128-bit task descriptors, rather than relying on the implicit zeroing from dmam_alloc_coherent().
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
emmc inline encryption support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['c']
| 1
| 20
| 10
|
--- diff --git a/drivers/mmc/host/cqhci-core.c b/drivers/mmc/host/cqhci-core.c --- a/drivers/mmc/host/cqhci-core.c +++ b/drivers/mmc/host/cqhci-core.c - u64 *data, bool intr) + struct cqhci_host *cq_host, int tag) + __le64 *task_desc = (__le64 __force *)get_desc(cq_host, tag); + u64 desc0; - *data = cqhci_valid(1) | + desc0 = cqhci_valid(1) | - cqhci_int(intr) | + cqhci_int(1) | - pr_debug("%s: cqhci: tag %d task descriptor 0x%016llx ", - mmc_hostname(mrq->host), mrq->tag, (unsigned long long)*data); + task_desc[0] = cpu_to_le64(desc0); + + if (cq_host->caps & cqhci_task_desc_sz_128) { + u64 desc1 = 0; + + task_desc[1] = cpu_to_le64(desc1); + + pr_debug("%s: cqhci: tag %d task descriptor 0x%016llx%016llx ", + mmc_hostname(mrq->host), mrq->tag, desc1, desc0); + } else { + pr_debug("%s: cqhci: tag %d task descriptor 0x%016llx ", + mmc_hostname(mrq->host), mrq->tag, desc0); + } - u64 data = 0; - u64 *task_desc = null; - task_desc = (__le64 __force *)get_desc(cq_host, tag); - cqhci_prep_task_desc(mrq, &data, 1); - *task_desc = cpu_to_le64(data); + cqhci_prep_task_desc(mrq, cq_host, tag); +
|
Multi Media Card (MMC)
|
ee49d0321f02596a046173be16fddcdfb8ceb7c1
|
eric biggers
|
drivers
|
mmc
|
host
|
mmc: cqhci: add support for inline encryption
|
add support for emmc inline encryption using the blk-crypto framework (documentation/block/inline-encryption.rst).
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
emmc inline encryption support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['h', 'c', 'makefile']
| 5
| 404
| 3
|
--- diff --git a/drivers/mmc/host/makefile b/drivers/mmc/host/makefile --- a/drivers/mmc/host/makefile +++ b/drivers/mmc/host/makefile +cqhci-$(config_mmc_crypto) += cqhci-crypto.o diff --git a/drivers/mmc/host/cqhci-core.c b/drivers/mmc/host/cqhci-core.c --- a/drivers/mmc/host/cqhci-core.c +++ b/drivers/mmc/host/cqhci-core.c +#include "cqhci-crypto.h" + if (mmc->caps2 & mmc_cap2_crypto) + cqcfg |= cqhci_crypto_general_enable; + - u64 desc1 = 0; + u64 desc1 = cqhci_crypto_prep_task_desc(mrq); + u32 tdpe; + /* + * handle icce ("invalid crypto configuration error"). this should + * never happen, since the block layer ensures that all crypto-enabled + * i/o requests have a valid keyslot before they reach the driver. + * + * note that gce ("general crypto error") is different; it already got + * handled above by checking terri. + */ + if (status & cqhci_is_icce) { + tdpe = cqhci_readl(cq_host, cqhci_tdpe); + warn_once(1, + "%s: cqhci: invalid crypto configuration error. irq status: 0x%08x tdpe: 0x%08x ", + mmc_hostname(mmc), status, tdpe); + while (tdpe != 0) { + tag = __ffs(tdpe); + tdpe &= ~(1 << tag); + slot = &cq_host->slot[tag]; + if (!slot->mrq) + continue; + slot->flags = cqhci_error_flags(data_error, cmd_error); + cqhci_recovery_needed(mmc, slot->mrq, true); + } + } + - if ((status & cqhci_is_red) || cmd_error || data_error) + if ((status & (cqhci_is_red | cqhci_is_gce | cqhci_is_icce)) || + cmd_error || data_error) + err = cqhci_crypto_init(cq_host); + if (err) { + pr_err("%s: cqhci crypto initialization failed ", + mmc_hostname(mmc)); + goto out_err; + } + diff --git a/drivers/mmc/host/cqhci-crypto.c b/drivers/mmc/host/cqhci-crypto.c --- /dev/null +++ b/drivers/mmc/host/cqhci-crypto.c +// spdx-license-identifier: gpl-2.0-only +/* + * cqhci crypto engine (inline encryption) support + * + * copyright 2020 google llc + */ + +#include <linux/blk-crypto.h> +#include <linux/keyslot-manager.h> +#include <linux/mmc/host.h> + +#include "cqhci-crypto.h" + +/* map from blk-crypto modes to cqhci crypto algorithm ids and key sizes */ +static const struct cqhci_crypto_alg_entry { + enum cqhci_crypto_alg alg; + enum cqhci_crypto_key_size key_size; +} cqhci_crypto_algs[blk_encryption_mode_max] = { + [blk_encryption_mode_aes_256_xts] = { + .alg = cqhci_crypto_alg_aes_xts, + .key_size = cqhci_crypto_key_size_256, + }, +}; + +static inline struct cqhci_host * +cqhci_host_from_ksm(struct blk_keyslot_manager *ksm) +{ + struct mmc_host *mmc = container_of(ksm, struct mmc_host, ksm); + + return mmc->cqe_private; +} + +static void cqhci_crypto_program_key(struct cqhci_host *cq_host, + const union cqhci_crypto_cfg_entry *cfg, + int slot) +{ + u32 slot_offset = cq_host->crypto_cfg_register + slot * sizeof(*cfg); + int i; + + /* clear cfge */ + cqhci_writel(cq_host, 0, slot_offset + 16 * sizeof(cfg->reg_val[0])); + + /* write the key */ + for (i = 0; i < 16; i++) { + cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[i]), + slot_offset + i * sizeof(cfg->reg_val[0])); + } + /* write dword 17 */ + cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[17]), + slot_offset + 17 * sizeof(cfg->reg_val[0])); + /* write dword 16, which includes the new value of cfge */ + cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[16]), + slot_offset + 16 * sizeof(cfg->reg_val[0])); +} + +static int cqhci_crypto_keyslot_program(struct blk_keyslot_manager *ksm, + const struct blk_crypto_key *key, + unsigned int slot) + +{ + struct cqhci_host *cq_host = cqhci_host_from_ksm(ksm); + const union cqhci_crypto_cap_entry *ccap_array = + cq_host->crypto_cap_array; + const struct cqhci_crypto_alg_entry *alg = + &cqhci_crypto_algs[key->crypto_cfg.crypto_mode]; + u8 data_unit_mask = key->crypto_cfg.data_unit_size / 512; + int i; + int cap_idx = -1; + union cqhci_crypto_cfg_entry cfg = {}; + + build_bug_on(cqhci_crypto_key_size_invalid != 0); + for (i = 0; i < cq_host->crypto_capabilities.num_crypto_cap; i++) { + if (ccap_array[i].algorithm_id == alg->alg && + ccap_array[i].key_size == alg->key_size && + (ccap_array[i].sdus_mask & data_unit_mask)) { + cap_idx = i; + break; + } + } + if (warn_on(cap_idx < 0)) + return -eopnotsupp; + + cfg.data_unit_size = data_unit_mask; + cfg.crypto_cap_idx = cap_idx; + cfg.config_enable = cqhci_crypto_configuration_enable; + + if (ccap_array[cap_idx].algorithm_id == cqhci_crypto_alg_aes_xts) { + /* in xts mode, the blk_crypto_key's size is already doubled */ + memcpy(cfg.crypto_key, key->raw, key->size/2); + memcpy(cfg.crypto_key + cqhci_crypto_key_max_size/2, + key->raw + key->size/2, key->size/2); + } else { + memcpy(cfg.crypto_key, key->raw, key->size); + } + + cqhci_crypto_program_key(cq_host, &cfg, slot); + + memzero_explicit(&cfg, sizeof(cfg)); + return 0; +} + +static void cqhci_crypto_clear_keyslot(struct cqhci_host *cq_host, int slot) +{ + /* + * clear the crypto cfg on the device. clearing cfge + * might not be sufficient, so just clear the entire cfg. + */ + union cqhci_crypto_cfg_entry cfg = {}; + + cqhci_crypto_program_key(cq_host, &cfg, slot); +} + +static int cqhci_crypto_keyslot_evict(struct blk_keyslot_manager *ksm, + const struct blk_crypto_key *key, + unsigned int slot) +{ + struct cqhci_host *cq_host = cqhci_host_from_ksm(ksm); + + cqhci_crypto_clear_keyslot(cq_host, slot); + return 0; +} + +/* + * the keyslot management operations for cqhci crypto. + * + * note that the block layer ensures that these are never called while the host + * controller is runtime-suspended. however, the cqe won't necessarily be + * "enabled" when these are called, i.e. cqhci_enable might not be set in the + * cqhci_cfg register. but the hardware allows that. + */ +static const struct blk_ksm_ll_ops cqhci_ksm_ops = { + .keyslot_program = cqhci_crypto_keyslot_program, + .keyslot_evict = cqhci_crypto_keyslot_evict, +}; + +static enum blk_crypto_mode_num +cqhci_find_blk_crypto_mode(union cqhci_crypto_cap_entry cap) +{ + int i; + + for (i = 0; i < array_size(cqhci_crypto_algs); i++) { + build_bug_on(cqhci_crypto_key_size_invalid != 0); + if (cqhci_crypto_algs[i].alg == cap.algorithm_id && + cqhci_crypto_algs[i].key_size == cap.key_size) + return i; + } + return blk_encryption_mode_invalid; +} + +/** + * cqhci_crypto_init - initialize cqhci crypto support + * @cq_host: a cqhci host + * + * if the driver previously set mmc_cap2_crypto and the cqe declares + * cqhci_cap_cs, initialize the crypto support. this involves reading the + * crypto capability registers, initializing the keyslot manager, clearing all + * keyslots, and enabling 128-bit task descriptors. + * + * return: 0 if crypto was initialized or isn't supported; whether + * mmc_cap2_crypto remains set indicates which one of those cases it is. + * also can return a negative errno value on unexpected error. + */ +int cqhci_crypto_init(struct cqhci_host *cq_host) +{ + struct mmc_host *mmc = cq_host->mmc; + struct device *dev = mmc_dev(mmc); + struct blk_keyslot_manager *ksm = &mmc->ksm; + unsigned int num_keyslots; + unsigned int cap_idx; + enum blk_crypto_mode_num blk_mode_num; + unsigned int slot; + int err = 0; + + if (!(mmc->caps2 & mmc_cap2_crypto) || + !(cqhci_readl(cq_host, cqhci_cap) & cqhci_cap_cs)) + goto out; + + cq_host->crypto_capabilities.reg_val = + cpu_to_le32(cqhci_readl(cq_host, cqhci_ccap)); + + cq_host->crypto_cfg_register = + (u32)cq_host->crypto_capabilities.config_array_ptr * 0x100; + + cq_host->crypto_cap_array = + devm_kcalloc(dev, cq_host->crypto_capabilities.num_crypto_cap, + sizeof(cq_host->crypto_cap_array[0]), gfp_kernel); + if (!cq_host->crypto_cap_array) { + err = -enomem; + goto out; + } + + /* + * ccap.cfgc is off by one, so the actual number of crypto + * configurations (a.k.a. keyslots) is ccap.cfgc + 1. + */ + num_keyslots = cq_host->crypto_capabilities.config_count + 1; + + err = devm_blk_ksm_init(dev, ksm, num_keyslots); + if (err) + goto out; + + ksm->ksm_ll_ops = cqhci_ksm_ops; + ksm->dev = dev; + + /* unfortunately, cqhci crypto only supports 32 dun bits. */ + ksm->max_dun_bytes_supported = 4; + + /* + * cache all the crypto capabilities and advertise the supported crypto + * modes and data unit sizes to the block layer. + */ + for (cap_idx = 0; cap_idx < cq_host->crypto_capabilities.num_crypto_cap; + cap_idx++) { + cq_host->crypto_cap_array[cap_idx].reg_val = + cpu_to_le32(cqhci_readl(cq_host, + cqhci_cryptocap + + cap_idx * sizeof(__le32))); + blk_mode_num = cqhci_find_blk_crypto_mode( + cq_host->crypto_cap_array[cap_idx]); + if (blk_mode_num == blk_encryption_mode_invalid) + continue; + ksm->crypto_modes_supported[blk_mode_num] |= + cq_host->crypto_cap_array[cap_idx].sdus_mask * 512; + } + + /* clear all the keyslots so that we start in a known state. */ + for (slot = 0; slot < num_keyslots; slot++) + cqhci_crypto_clear_keyslot(cq_host, slot); + + /* cqhci crypto requires the use of 128-bit task descriptors. */ + cq_host->caps |= cqhci_task_desc_sz_128; + + return 0; + +out: + mmc->caps2 &= ~mmc_cap2_crypto; + return err; +} diff --git a/drivers/mmc/host/cqhci-crypto.h b/drivers/mmc/host/cqhci-crypto.h --- /dev/null +++ b/drivers/mmc/host/cqhci-crypto.h +/* spdx-license-identifier: gpl-2.0-only */ +/* + * cqhci crypto engine (inline encryption) support + * + * copyright 2020 google llc + */ + +#ifndef linux_mmc_cqhci_crypto_h +#define linux_mmc_cqhci_crypto_h + +#include <linux/mmc/host.h> + +#include "cqhci.h" + +#ifdef config_mmc_crypto + +int cqhci_crypto_init(struct cqhci_host *host); + +/* + * returns the crypto bits that should be set in bits 64-127 of the + * task descriptor. + */ +static inline u64 cqhci_crypto_prep_task_desc(struct mmc_request *mrq) +{ + if (!mrq->crypto_enabled) + return 0; + + return cqhci_crypto_enable_bit | + cqhci_crypto_keyslot(mrq->crypto_key_slot) | + mrq->data_unit_num; +} + +#else /* config_mmc_crypto */ + +static inline int cqhci_crypto_init(struct cqhci_host *host) +{ + return 0; +} + +static inline u64 cqhci_crypto_prep_task_desc(struct mmc_request *mrq) +{ + return 0; +} + +#endif /* !config_mmc_crypto */ + +#endif /* linux_mmc_cqhci_crypto_h */ diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h --- a/drivers/mmc/host/cqhci.h +++ b/drivers/mmc/host/cqhci.h +#define cqhci_cap_cs 0x10000000 /* crypto support */ + +#define cqhci_crypto_general_enable 0x00000002 +#define cqhci_is_gce bit(4) /* general crypto error */ +#define cqhci_is_icce bit(5) /* invalid crypto config error */ -#define cqhci_is_mask (cqhci_is_tcc | cqhci_is_red) +#define cqhci_is_mask (cqhci_is_tcc | cqhci_is_red | \ + cqhci_is_gce | cqhci_is_icce) +/* task descriptor processing error */ +#define cqhci_tdpe 0x3c + +/* crypto capabilities */ +#define cqhci_ccap 0x100 +#define cqhci_cryptocap 0x104 + +/* crypto task descriptor fields (for bits 64-127 of task descriptor) */ +#define cqhci_crypto_enable_bit (1ull << 47) +#define cqhci_crypto_keyslot(x) ((u64)(x) << 32) + +/* ccap - crypto capability 100h */ +union cqhci_crypto_capabilities { + __le32 reg_val; + struct { + u8 num_crypto_cap; + u8 config_count; + u8 reserved; + u8 config_array_ptr; + }; +}; + +enum cqhci_crypto_key_size { + cqhci_crypto_key_size_invalid = 0, + cqhci_crypto_key_size_128 = 1, + cqhci_crypto_key_size_192 = 2, + cqhci_crypto_key_size_256 = 3, + cqhci_crypto_key_size_512 = 4, +}; + +enum cqhci_crypto_alg { + cqhci_crypto_alg_aes_xts = 0, + cqhci_crypto_alg_bitlocker_aes_cbc = 1, + cqhci_crypto_alg_aes_ecb = 2, + cqhci_crypto_alg_essiv_aes_cbc = 3, +}; + +/* x-cryptocap - crypto capability x */ +union cqhci_crypto_cap_entry { + __le32 reg_val; + struct { + u8 algorithm_id; + u8 sdus_mask; /* supported data unit size mask */ + u8 key_size; + u8 reserved; + }; +}; + +#define cqhci_crypto_configuration_enable (1 << 7) +#define cqhci_crypto_key_max_size 64 +/* x-cryptocfg - crypto configuration x */ +union cqhci_crypto_cfg_entry { + __le32 reg_val[32]; + struct { + u8 crypto_key[cqhci_crypto_key_max_size]; + u8 data_unit_size; + u8 crypto_cap_idx; + u8 reserved_1; + u8 config_enable; + u8 reserved_multi_host; + u8 reserved_2; + u8 vsb[2]; + u8 reserved_3[56]; + }; +}; + + +#ifdef config_mmc_crypto + union cqhci_crypto_capabilities crypto_capabilities; + union cqhci_crypto_cap_entry *crypto_cap_array; + u32 crypto_cfg_register; +#endif
|
Multi Media Card (MMC)
|
1e80709bdbfc1e1f3cac0ba8ed9a58f5789bcf51
|
eric biggers
|
drivers
|
mmc
|
host
|
mmc: cqhci: add cqhci_host_ops::program_key
|
on snapdragon socs, the linux kernel isn't permitted to directly access the standard cqhci crypto configuration registers. instead, programming and evicting keys must be done through vendor-specific smc calls.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
emmc inline encryption support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['h', 'c']
| 2
| 17
| 9
|
--- diff --git a/drivers/mmc/host/cqhci-crypto.c b/drivers/mmc/host/cqhci-crypto.c --- a/drivers/mmc/host/cqhci-crypto.c +++ b/drivers/mmc/host/cqhci-crypto.c -static void cqhci_crypto_program_key(struct cqhci_host *cq_host, - const union cqhci_crypto_cfg_entry *cfg, - int slot) +static int cqhci_crypto_program_key(struct cqhci_host *cq_host, + const union cqhci_crypto_cfg_entry *cfg, + int slot) + if (cq_host->ops->program_key) + return cq_host->ops->program_key(cq_host, cfg, slot); + + return 0; + int err; - cqhci_crypto_program_key(cq_host, &cfg, slot); + err = cqhci_crypto_program_key(cq_host, &cfg, slot); - return 0; + return err; -static void cqhci_crypto_clear_keyslot(struct cqhci_host *cq_host, int slot) +static int cqhci_crypto_clear_keyslot(struct cqhci_host *cq_host, int slot) - cqhci_crypto_program_key(cq_host, &cfg, slot); + return cqhci_crypto_program_key(cq_host, &cfg, slot); - cqhci_crypto_clear_keyslot(cq_host, slot); - return 0; + return cqhci_crypto_clear_keyslot(cq_host, slot); diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h --- a/drivers/mmc/host/cqhci.h +++ b/drivers/mmc/host/cqhci.h +#ifdef config_mmc_crypto + int (*program_key)(struct cqhci_host *cq_host, + const union cqhci_crypto_cfg_entry *cfg, int slot); +#endif
|
Multi Media Card (MMC)
|
0a0c866f377ebea6ed5b65942cf1269651c21072
|
eric biggers
|
drivers
|
mmc
|
host
|
firmware: qcom_scm: update comment for ice-related functions
|
the scm calls qcom_scm_es_invalidate_ice_key and qcom_scm_es_config_set_ice_key are also needed for emmc inline encryption support, not just for ufs. update the comments accordingly.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
emmc inline encryption support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['c']
| 1
| 11
| 5
|
--- diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c - * the ufshci standard defines a standard way to do this, but it doesn't work on - * these socs; only this scm call does. + * the ufshci and emmc standards define a standard way to do this, but it + * doesn't work on these socs; only this scm call does. + * + * it is assumed that the soc has only one ice instance being used, as this scm + * call doesn't specify which ice instance the keyslot belongs to. - * can then be used to encrypt/decrypt ufs i/o requests inline. + * can then be used to encrypt/decrypt ufs or emmc i/o requests inline. + * + * the ufshci and emmc standards define a standard way to do this, but it + * doesn't work on these socs; only this scm call does. - * the ufshci standard defines a standard way to do this, but it doesn't work on - * these socs; only this scm call does. + * it is assumed that the soc has only one ice instance being used, as this scm + * call doesn't specify which ice instance the keyslot belongs to.
|
Multi Media Card (MMC)
|
433611ea8df3666845ecd3480c22667f065ea7af
|
eric biggers bjorn andersson bjorn andersson linaro org satya tangirala satyat google com
|
drivers
|
firmware
| |
dt-bindings: mmc: sdhci-msm: add ice registers and clock
|
document the bindings for the registers and clock for the mmc instance of the inline crypto engine (ice) on snapdragon socs. these bindings are needed in order for sdhci-msm to support inline encryption.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
emmc inline encryption support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['txt']
| 1
| 3
| 0
|
--- diff --git a/documentation/devicetree/bindings/mmc/sdhci-msm.txt b/documentation/devicetree/bindings/mmc/sdhci-msm.txt --- a/documentation/devicetree/bindings/mmc/sdhci-msm.txt +++ b/documentation/devicetree/bindings/mmc/sdhci-msm.txt - sd core register map (required for controllers earlier than msm-v5) - cqe register map (optional, cqe support is present on sdhc instance meant + - inline crypto engine register map (optional) - reg-names: when cqe register map is supplied, below reg-names are required - "hc" for host controller register map - "core" for sd core register map - "cqhci" for cqe register map + - "ice" for inline crypto engine register map (optional) - interrupts: should contain an interrupt-specifiers for the interrupts: - host controller interrupt (required) - pinctrl-names: should contain only one value - "default". + "ice" - clock for inline crypto engine (optional) - qcom,ddr-config: certain chipsets and platforms require particular settings
|
Multi Media Card (MMC)
|
5cc046eb134f680f3ab6e2bb4ff43b94683336eb
|
eric biggers rob herring robh kernel org satya tangirala satyat google com
|
documentation
|
devicetree
|
bindings, mmc
|
mmc: sdhci-msm: add inline crypto engine support
|
add support for qualcomm inline crypto engine (ice) to sdhci-msm.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
emmc inline encryption support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['kconfig', 'c']
| 2
| 273
| 4
|
--- diff --git a/drivers/mmc/host/kconfig b/drivers/mmc/host/kconfig --- a/drivers/mmc/host/kconfig +++ b/drivers/mmc/host/kconfig + select qcom_scm if mmc_crypto && arch_qcom diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c +#include <linux/qcom_scm.h> + void __iomem *ice_mem; /* msm ice mapped address (if available) */ - struct clk_bulk_data bulk_clks[4]; /* core, iface, cal, sleep clocks */ + /* core, iface, cal, sleep, and ice clocks */ + struct clk_bulk_data bulk_clks[5]; +/*****************************************************************************\ + * * + * inline crypto engine (ice) support * + * * +\*****************************************************************************/ + +#ifdef config_mmc_crypto + +#define aes_256_xts_key_size 64 + +/* qcom ice registers */ + +#define qcom_ice_reg_version 0x0008 + +#define qcom_ice_reg_fuse_setting 0x0010 +#define qcom_ice_fuse_setting_mask 0x1 +#define qcom_ice_force_hw_key0_setting_mask 0x2 +#define qcom_ice_force_hw_key1_setting_mask 0x4 + +#define qcom_ice_reg_bist_status 0x0070 +#define qcom_ice_bist_status_mask 0xf0000000 + +#define qcom_ice_reg_advanced_control 0x1000 + +#define sdhci_msm_ice_writel(host, val, reg) \ + writel((val), (host)->ice_mem + (reg)) +#define sdhci_msm_ice_readl(host, reg) \ + readl((host)->ice_mem + (reg)) + +static bool sdhci_msm_ice_supported(struct sdhci_msm_host *msm_host) +{ + struct device *dev = mmc_dev(msm_host->mmc); + u32 regval = sdhci_msm_ice_readl(msm_host, qcom_ice_reg_version); + int major = regval >> 24; + int minor = (regval >> 16) & 0xff; + int step = regval & 0xffff; + + /* for now this driver only supports ice version 3. */ + if (major != 3) { + dev_warn(dev, "unsupported ice version: v%d.%d.%d ", + major, minor, step); + return false; + } + + dev_info(dev, "found qc inline crypto engine (ice) v%d.%d.%d ", + major, minor, step); + + /* if fuses are blown, ice might not work in the standard way. */ + regval = sdhci_msm_ice_readl(msm_host, qcom_ice_reg_fuse_setting); + if (regval & (qcom_ice_fuse_setting_mask | + qcom_ice_force_hw_key0_setting_mask | + qcom_ice_force_hw_key1_setting_mask)) { + dev_warn(dev, "fuses are blown; ice is unusable! "); + return false; + } + return true; +} + +static inline struct clk *sdhci_msm_ice_get_clk(struct device *dev) +{ + return devm_clk_get(dev, "ice"); +} + +static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, + struct cqhci_host *cq_host) +{ + struct mmc_host *mmc = msm_host->mmc; + struct device *dev = mmc_dev(mmc); + struct resource *res; + int err; + + if (!(cqhci_readl(cq_host, cqhci_cap) & cqhci_cap_cs)) + return 0; + + res = platform_get_resource_byname(msm_host->pdev, ioresource_mem, + "ice"); + if (!res) { + dev_warn(dev, "ice registers not found "); + goto disable; + } + + if (!qcom_scm_ice_available()) { + dev_warn(dev, "ice scm interface not found "); + goto disable; + } + + msm_host->ice_mem = devm_ioremap_resource(dev, res); + if (is_err(msm_host->ice_mem)) { + err = ptr_err(msm_host->ice_mem); + dev_err(dev, "failed to map ice registers; err=%d ", err); + return err; + } + + if (!sdhci_msm_ice_supported(msm_host)) + goto disable; + + mmc->caps2 |= mmc_cap2_crypto; + return 0; + +disable: + dev_warn(dev, "disabling inline encryption support "); + return 0; +} + +static void sdhci_msm_ice_low_power_mode_enable(struct sdhci_msm_host *msm_host) +{ + u32 regval; + + regval = sdhci_msm_ice_readl(msm_host, qcom_ice_reg_advanced_control); + /* + * enable low power mode sequence + * [0]-0, [1]-0, [2]-0, [3]-e, [4]-0, [5]-0, [6]-0, [7]-0 + */ + regval |= 0x7000; + sdhci_msm_ice_writel(msm_host, regval, qcom_ice_reg_advanced_control); +} + +static void sdhci_msm_ice_optimization_enable(struct sdhci_msm_host *msm_host) +{ + u32 regval; + + /* ice optimizations enable sequence */ + regval = sdhci_msm_ice_readl(msm_host, qcom_ice_reg_advanced_control); + regval |= 0xd807100; + /* ice hpg requires delay before writing */ + udelay(5); + sdhci_msm_ice_writel(msm_host, regval, qcom_ice_reg_advanced_control); + udelay(5); +} + +/* + * wait until the ice bist (built-in self-test) has completed. + * + * this may be necessary before ice can be used. + * + * note that we don't really care whether the bist passed or failed; we really + * just want to make sure that it isn't still running. this is because (a) the + * bist is a fips compliance thing that never fails in practice, (b) ice is + * documented to reject crypto requests if the bist fails, so we needn't do it + * in software too, and (c) properly testing storage encryption requires testing + * the full storage stack anyway, and not relying on hardware-level self-tests. + */ +static int sdhci_msm_ice_wait_bist_status(struct sdhci_msm_host *msm_host) +{ + u32 regval; + int err; + + err = readl_poll_timeout(msm_host->ice_mem + qcom_ice_reg_bist_status, + regval, !(regval & qcom_ice_bist_status_mask), + 50, 5000); + if (err) + dev_err(mmc_dev(msm_host->mmc), + "timed out waiting for ice self-test to complete "); + return err; +} + +static void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host) +{ + if (!(msm_host->mmc->caps2 & mmc_cap2_crypto)) + return; + sdhci_msm_ice_low_power_mode_enable(msm_host); + sdhci_msm_ice_optimization_enable(msm_host); + sdhci_msm_ice_wait_bist_status(msm_host); +} + +static int __maybe_unused sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host) +{ + if (!(msm_host->mmc->caps2 & mmc_cap2_crypto)) + return 0; + return sdhci_msm_ice_wait_bist_status(msm_host); +} + +/* + * program a key into a qc ice keyslot, or evict a keyslot. qc ice requires + * vendor-specific scm calls for this; it doesn't support the standard way. + */ +static int sdhci_msm_program_key(struct cqhci_host *cq_host, + const union cqhci_crypto_cfg_entry *cfg, + int slot) +{ + struct device *dev = mmc_dev(cq_host->mmc); + union cqhci_crypto_cap_entry cap; + union { + u8 bytes[aes_256_xts_key_size]; + u32 words[aes_256_xts_key_size / sizeof(u32)]; + } key; + int i; + int err; + + if (!(cfg->config_enable & cqhci_crypto_configuration_enable)) + return qcom_scm_ice_invalidate_key(slot); + + /* only aes-256-xts has been tested so far. */ + cap = cq_host->crypto_cap_array[cfg->crypto_cap_idx]; + if (cap.algorithm_id != cqhci_crypto_alg_aes_xts || + cap.key_size != cqhci_crypto_key_size_256) { + dev_err_ratelimited(dev, + "unhandled crypto capability; algorithm_id=%d, key_size=%d ", + cap.algorithm_id, cap.key_size); + return -einval; + } + + memcpy(key.bytes, cfg->crypto_key, aes_256_xts_key_size); + + /* + * the scm call byte-swaps the 32-bit words of the key. so we have to + * do the same, in order for the final key be correct. + */ + for (i = 0; i < array_size(key.words); i++) + __cpu_to_be32s(&key.words[i]); + + err = qcom_scm_ice_set_key(slot, key.bytes, aes_256_xts_key_size, + qcom_scm_ice_cipher_aes_256_xts, + cfg->data_unit_size); + memzero_explicit(&key, sizeof(key)); + return err; +} +#else /* config_mmc_crypto */ +static inline struct clk *sdhci_msm_ice_get_clk(struct device *dev) +{ + return null; +} + +static inline int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, + struct cqhci_host *cq_host) +{ + return 0; +} + +static inline void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host) +{ +} + +static inline int __maybe_unused +sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host) +{ + return 0; +} +#endif /* !config_mmc_crypto */ + +static void sdhci_msm_cqe_enable(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); + + sdhci_cqe_enable(mmc); + sdhci_msm_ice_enable(msm_host); +} + - .enable = sdhci_cqe_enable, + .enable = sdhci_msm_cqe_enable, +#ifdef config_mmc_crypto + .program_key = sdhci_msm_program_key, +#endif + ret = sdhci_msm_ice_init(msm_host, cq_host); + if (ret) + goto cleanup; + + clk = sdhci_msm_ice_get_clk(&pdev->dev); + if (is_err(clk)) + clk = null; + msm_host->bulk_clks[4].clk = clk; + - if (msm_host->restore_dll_config && msm_host->clk_rate) + if (msm_host->restore_dll_config && msm_host->clk_rate) { + if (ret) + return ret; + } - return ret; + return sdhci_msm_ice_resume(msm_host);
|
Multi Media Card (MMC)
|
c93767cf64ebf41c65d8834af27df63f2f0f7ec5
|
eric biggers
|
drivers
|
mmc
|
host
|
mmc: mmci: add support for probing bus voltage level translator
|
add support for testing whether bus voltage level translator is present and operational. this is useful on systems where the bus voltage level translator is optional, as the translator can be auto-detected by the driver and the feedback clock functionality can be disabled if it is not present.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for probing bus voltage level translator
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mmci']
|
['c']
| 1
| 65
| 5
|
--- diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c +#include <linux/gpio/consumer.h> +static void mmci_probe_level_translator(struct mmc_host *mmc) +{ + struct device *dev = mmc_dev(mmc); + struct mmci_host *host = mmc_priv(mmc); + struct gpio_desc *cmd_gpio; + struct gpio_desc *ck_gpio; + struct gpio_desc *ckin_gpio; + int clk_hi, clk_lo; + + /* + * assume the level translator is present if st,use-ckin is set. + * this is to cater for dts which do not implement this test. + */ + host->clk_reg_add |= mci_stm32_clk_selckin; + + cmd_gpio = gpiod_get(dev, "st,cmd", gpiod_out_high); + if (is_err(cmd_gpio)) + goto exit_cmd; + + ck_gpio = gpiod_get(dev, "st,ck", gpiod_out_high); + if (is_err(ck_gpio)) + goto exit_ck; + + ckin_gpio = gpiod_get(dev, "st,ckin", gpiod_in); + if (is_err(ckin_gpio)) + goto exit_ckin; + + /* all gpios are valid, test whether level translator works */ + + /* sample ckin */ + clk_hi = !!gpiod_get_value(ckin_gpio); + + /* set ck low */ + gpiod_set_value(ck_gpio, 0); + + /* sample ckin */ + clk_lo = !!gpiod_get_value(ckin_gpio); + + /* tristate all */ + gpiod_direction_input(cmd_gpio); + gpiod_direction_input(ck_gpio); + + /* level translator is present if ck signal is propagated to ckin */ + if (!clk_hi || clk_lo) { + host->clk_reg_add &= ~mci_stm32_clk_selckin; + dev_warn(dev, + "level translator inoperable, ck signal not detected on ckin, disabling. "); + } + + gpiod_put(ckin_gpio); + +exit_ckin: + gpiod_put(ck_gpio); +exit_ck: + gpiod_put(cmd_gpio); +exit_cmd: + pinctrl_select_default_state(dev); +} + - host->clk_reg_add |= mci_stm32_clk_selckin; + mmci_probe_level_translator(mmc); - ret = mmci_of_parse(np, mmc); - if (ret) - goto host_free; - + ret = mmci_of_parse(np, mmc); + if (ret) + goto host_free; +
|
Multi Media Card (MMC)
|
6351cac92a8c598115d74a700f1720861d57ef20
|
marek vasut
|
drivers
|
mmc
|
host
|
mmc: sdhci-of-aspeed: add ast2600 bus clock support
|
the ast2600 can achieve hs200 speeds with a change to the bus clock divisor behaviour. the divisor can also be more accurate with respect to the requested clock rate, but keep the one-hot behaviour for backwards compatibility with the ast2400 and ast2500.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add ast2600 bus clock support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['sdhci-of-aspeed']
|
['c']
| 1
| 33
| 4
|
--- diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c --- a/drivers/mmc/host/sdhci-of-aspeed.c +++ b/drivers/mmc/host/sdhci-of-aspeed.c + unsigned int clk_div_start; + struct aspeed_sdhci *sdhci; + sdhci = sdhci_pltfm_priv(pltfm_host); + - for (div = 2; div < 256; div *= 2) { + /* + * regarding the ast2600: + * + * if (emmc12c[7:6], emmc12c[15:8] == 0) then + * period of sdclk = period of sdmclk. + * + * if (emmc12c[7:6], emmc12c[15:8] != 0) then + * period of sdclk = period of sdmclk * 2 * (emmc12c[7:6], emmc[15:8]) + * + * if you keep emmc12c[7:6] = 0 and emmc12c[15:8] as one-hot, + * 0x1/0x2/0x4/etc, you will find it is compatible to ast2400 or ast2500 + * + * keep the one-hot behaviour for backwards compatibility except for + * supporting the value 0 in (emmc12c[7:6], emmc12c[15:8]), and capture + * the 0-value capability in clk_div_start. + */ + for (div = sdhci->pdata->clk_div_start; div < 256; div *= 2) { + if (!aspeed_pdata) { + dev_err(&pdev->dev, "missing platform configuration data "); + return -einval; + } - if (dev->pdata && slot < dev->pdata->nr_phase_descs) { + if (slot < dev->pdata->nr_phase_descs) { +static const struct aspeed_sdhci_pdata ast2400_sdhci_pdata = { + .clk_div_start = 2, +}; + + .clk_div_start = 1, - { .compatible = "aspeed,ast2400-sdhci", }, - { .compatible = "aspeed,ast2500-sdhci", }, + { .compatible = "aspeed,ast2400-sdhci", .data = &ast2400_sdhci_pdata, }, + { .compatible = "aspeed,ast2500-sdhci", .data = &ast2400_sdhci_pdata, },
|
Multi Media Card (MMC)
|
0c53dc321a507c78fdd15a682f42175a131b1763
|
andrew jeffery
|
drivers
|
mmc
|
host
|
mmc: sdhci_am654: add support for ti's am64 soc
|
add support for the controller present on the am64x soc.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for ti's am64 soc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['sdhci_am654']
|
['c']
| 1
| 28
| 0
|
--- diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c +static const struct sdhci_pltfm_data sdhci_am64_8bit_pdata = { + .ops = &sdhci_j721e_8bit_ops, + .quirks2 = sdhci_quirk2_preset_value_broken, +}; + +static const struct sdhci_am654_driver_data sdhci_am64_8bit_drvdata = { + .pdata = &sdhci_am64_8bit_pdata, + .flags = dll_present | dll_calib, +}; + +static const struct sdhci_pltfm_data sdhci_am64_4bit_pdata = { + .ops = &sdhci_j721e_4bit_ops, + .quirks2 = sdhci_quirk2_preset_value_broken, +}; + +static const struct sdhci_am654_driver_data sdhci_am64_4bit_drvdata = { + .pdata = &sdhci_am64_4bit_pdata, + .flags = iomux_present, +}; + + { + .compatible = "ti,am64-sdhci-8bit", + .data = &sdhci_am64_8bit_drvdata, + }, + { + .compatible = "ti,am64-sdhci-4bit", + .data = &sdhci_am64_4bit_drvdata, + },
|
Multi Media Card (MMC)
|
754b7f2f7d2acda729619c6cfed9bc8124ca17cb
|
faiz abbas
|
drivers
|
mmc
|
host
|
mmc: sunxi: add support for a100 mmc controller
|
this patch adds support for a100 mmc controller, which use word address for internal dma.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for a100 mmc controller
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['sunxi']
|
['c']
| 1
| 25
| 3
|
--- diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c --- a/drivers/mmc/host/sunxi-mmc.c +++ b/drivers/mmc/host/sunxi-mmc.c + u32 idma_des_shift; - mmc_writel(host, reg_dlba, host->sg_dma); + mmc_writel(host, reg_dlba, host->sg_dma >> host->cfg->idma_des_shift); - cpu_to_le32(sg_dma_address(&data->sg[i])); - pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc); + cpu_to_le32(sg_dma_address(&data->sg[i]) >> + host->cfg->idma_des_shift); + pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc >> + host->cfg->idma_des_shift); +static const struct sunxi_mmc_cfg sun50i_a100_cfg = { + .idma_des_size_bits = 16, + .idma_des_shift = 2, + .clk_delays = null, + .can_calibrate = true, + .mask_data0 = true, + .needs_new_timings = true, +}; + +static const struct sunxi_mmc_cfg sun50i_a100_emmc_cfg = { + .idma_des_size_bits = 13, + .idma_des_shift = 2, + .clk_delays = null, + .can_calibrate = true, + .needs_new_timings = true, +}; + + { .compatible = "allwinner,sun50i-a100-mmc", .data = &sun50i_a100_cfg }, + { .compatible = "allwinner,sun50i-a100-emmc", .data = &sun50i_a100_emmc_cfg },
|
Multi Media Card (MMC)
|
3536b82e5853ec302c1803896c126725afb6d57c
|
yangtao li
|
drivers
|
mmc
|
host
|
mmc: remove dw_mmc-zx driver
|
the zte zx platform is getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove dw_mmc-zx driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['c', 'h', 'kconfig', 'txt', 'makefile']
| 5
| 0
| 307
|
--- diff --git a/documentation/devicetree/bindings/mmc/zx-dw-mshc.txt b/documentation/devicetree/bindings/mmc/zx-dw-mshc.txt --- a/documentation/devicetree/bindings/mmc/zx-dw-mshc.txt +++ /dev/null -* zte specific extensions to the synopsys designware mobile storage - host controller - -the synopsys designware mobile storage host controller is used to interface -a soc with storage medium such as emmc or sd/mmc cards. this file documents -differences between the core synopsys dw mshc controller properties described -by synopsys-dw-mshc.txt and the properties used by the zte specific -extensions to the synopsys designware mobile storage host controller. - -required properties: - -* compatible: should be - - "zte,zx296718-dw-mshc": for zx socs - -example: - - mmc1: mmc@1110000 { - compatible = "zte,zx296718-dw-mshc"; - reg = <0x01110000 0x1000>; - interrupts = <gic_spi 15 irq_type_level_high>; - fifo-depth = <32>; - data-addr = <0x200>; - fifo-watermark-aligned; - bus-width = <4>; - clock-frequency = <50000000>; - clocks = <&topcrm sd0_ahb>, <&topcrm sd0_wclk>; - clock-names = "biu", "ciu"; - max-frequency = <50000000>; - cap-sdio-irq; - cap-sd-highspeed; - }; diff --git a/drivers/mmc/host/kconfig b/drivers/mmc/host/kconfig --- a/drivers/mmc/host/kconfig +++ b/drivers/mmc/host/kconfig -config mmc_dw_zx - tristate "zte specific extensions for synopsys dw memory card interface" - depends on mmc_dw && arch_zx - select mmc_dw_pltfm - help - this selects support for zte soc specific extensions to the - synopsys designware memory card interface driver. select this option - for platforms based on zx296718 soc's. - diff --git a/drivers/mmc/host/makefile b/drivers/mmc/host/makefile --- a/drivers/mmc/host/makefile +++ b/drivers/mmc/host/makefile -obj-$(config_mmc_dw_zx) += dw_mmc-zx.o diff --git a/drivers/mmc/host/dw_mmc-zx.c b/drivers/mmc/host/dw_mmc-zx.c --- a/drivers/mmc/host/dw_mmc-zx.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-or-later -/* - * zx specific extensions for synopsys dw multimedia card interface driver - * - * copyright (c) 2016, linaro ltd. - * copyright (c) 2016, zte corp. - */ - -#include <linux/clk.h> -#include <linux/mfd/syscon.h> -#include <linux/mmc/host.h> -#include <linux/mmc/mmc.h> -#include <linux/module.h> -#include <linux/of.h> -#include <linux/platform_device.h> -#include <linux/pm_runtime.h> -#include <linux/regmap.h> -#include <linux/slab.h> - -#include "dw_mmc.h" -#include "dw_mmc-pltfm.h" -#include "dw_mmc-zx.h" - -struct dw_mci_zx_priv_data { - struct regmap *sysc_base; -}; - -enum delay_type { - delay_type_read, /* read dqs delay */ - delay_type_clk, /* clk sample delay */ -}; - -static int dw_mci_zx_emmc_set_delay(struct dw_mci *host, unsigned int delay, - enum delay_type dflag) -{ - struct dw_mci_zx_priv_data *priv = host->priv; - struct regmap *sysc_base = priv->sysc_base; - unsigned int clksel; - unsigned int loop = 1000; - int ret; - - if (!sysc_base) - return -einval; - - ret = regmap_update_bits(sysc_base, lb_aon_emmc_cfg_reg0, - para_half_clk_mode | para_dll_bypass_mode | - para_phase_det_sel_mask | - para_dll_lock_num_mask | - dll_reg_set | para_dll_start_mask, - para_dll_start(4) | para_dll_lock_num(4)); - if (ret) - return ret; - - ret = regmap_read(sysc_base, lb_aon_emmc_cfg_reg1, &clksel); - if (ret) - return ret; - - if (dflag == delay_type_clk) { - clksel &= ~clk_samp_delay_mask; - clksel |= clk_samp_delay(delay); - } else { - clksel &= ~read_dqs_delay_mask; - clksel |= read_dqs_delay(delay); - } - - regmap_write(sysc_base, lb_aon_emmc_cfg_reg1, clksel); - regmap_update_bits(sysc_base, lb_aon_emmc_cfg_reg0, - para_dll_start_mask | para_dll_lock_num_mask | - dll_reg_set, - para_dll_start(4) | para_dll_lock_num(4) | - dll_reg_set); - - do { - ret = regmap_read(sysc_base, lb_aon_emmc_cfg_reg2, &clksel); - if (ret) - return ret; - - } while (--loop && !(clksel & zx_dll_locked)); - - if (!loop) { - dev_err(host->dev, "error: %s dll lock fail ", __func__); - return -eio; - } - - return 0; -} - -static int dw_mci_zx_emmc_execute_tuning(struct dw_mci_slot *slot, u32 opcode) -{ - struct dw_mci *host = slot->host; - struct mmc_host *mmc = slot->mmc; - int ret, len = 0, start = 0, end = 0, delay, best = 0; - - for (delay = 1; delay < 128; delay++) { - ret = dw_mci_zx_emmc_set_delay(host, delay, delay_type_clk); - if (!ret && mmc_send_tuning(mmc, opcode, null)) { - if (start >= 0) { - end = delay - 1; - /* check and update longest good range */ - if ((end - start) > len) { - best = (start + end) >> 1; - len = end - start; - } - } - start = -1; - end = 0; - continue; - } - if (start < 0) - start = delay; - } - - if (start >= 0) { - end = delay - 1; - if ((end - start) > len) { - best = (start + end) >> 1; - len = end - start; - } - } - if (best < 0) - return -eio; - - dev_info(host->dev, "%s best range: start %d end %d ", __func__, - start, end); - return dw_mci_zx_emmc_set_delay(host, best, delay_type_clk); -} - -static int dw_mci_zx_prepare_hs400_tuning(struct dw_mci *host, - struct mmc_ios *ios) -{ - int ret; - - /* config phase shift as 90 degree */ - ret = dw_mci_zx_emmc_set_delay(host, 32, delay_type_read); - if (ret < 0) - return -eio; - - return 0; -} - -static int dw_mci_zx_execute_tuning(struct dw_mci_slot *slot, u32 opcode) -{ - struct dw_mci *host = slot->host; - - if (host->verid == 0x290a) /* only for emmc */ - return dw_mci_zx_emmc_execute_tuning(slot, opcode); - /* todo: add 0x210a dedicated tuning for sd/sdio */ - - return 0; -} - -static int dw_mci_zx_parse_dt(struct dw_mci *host) -{ - struct device_node *np = host->dev->of_node; - struct device_node *node; - struct dw_mci_zx_priv_data *priv; - struct regmap *sysc_base; - - /* syscon is needed only by emmc */ - node = of_parse_phandle(np, "zte,aon-syscon", 0); - if (node) { - sysc_base = syscon_node_to_regmap(node); - of_node_put(node); - - if (is_err(sysc_base)) - return dev_err_probe(host->dev, ptr_err(sysc_base), - "can't get syscon "); - } else { - return 0; - } - - priv = devm_kzalloc(host->dev, sizeof(*priv), gfp_kernel); - if (!priv) - return -enomem; - priv->sysc_base = sysc_base; - host->priv = priv; - - return 0; -} - -static unsigned long zx_dwmmc_caps[3] = { - mmc_cap_cmd23, - mmc_cap_cmd23, - mmc_cap_cmd23, -}; - -static const struct dw_mci_drv_data zx_drv_data = { - .caps = zx_dwmmc_caps, - .num_caps = array_size(zx_dwmmc_caps), - .execute_tuning = dw_mci_zx_execute_tuning, - .prepare_hs400_tuning = dw_mci_zx_prepare_hs400_tuning, - .parse_dt = dw_mci_zx_parse_dt, -}; - -static const struct of_device_id dw_mci_zx_match[] = { - { .compatible = "zte,zx296718-dw-mshc", .data = &zx_drv_data}, - {}, -}; -module_device_table(of, dw_mci_zx_match); - -static int dw_mci_zx_probe(struct platform_device *pdev) -{ - const struct dw_mci_drv_data *drv_data; - const struct of_device_id *match; - - match = of_match_node(dw_mci_zx_match, pdev->dev.of_node); - drv_data = match->data; - - return dw_mci_pltfm_register(pdev, drv_data); -} - -static const struct dev_pm_ops dw_mci_zx_dev_pm_ops = { - set_system_sleep_pm_ops(pm_runtime_force_suspend, - pm_runtime_force_resume) - set_runtime_pm_ops(dw_mci_runtime_suspend, - dw_mci_runtime_resume, - null) -}; - -static struct platform_driver dw_mci_zx_pltfm_driver = { - .probe = dw_mci_zx_probe, - .remove = dw_mci_pltfm_remove, - .driver = { - .name = "dwmmc_zx", - .probe_type = probe_prefer_asynchronous, - .of_match_table = dw_mci_zx_match, - .pm = &dw_mci_zx_dev_pm_ops, - }, -}; - -module_platform_driver(dw_mci_zx_pltfm_driver); - -module_description("zte emmc/sd driver"); -module_license("gpl v2"); diff --git a/drivers/mmc/host/dw_mmc-zx.h b/drivers/mmc/host/dw_mmc-zx.h --- a/drivers/mmc/host/dw_mmc-zx.h +++ /dev/null -/* spdx-license-identifier: gpl-2.0 */ -#ifndef _dw_mmc_zx_h_ -#define _dw_mmc_zx_h_ - -/* zx296718 soc specific dll register offset. */ -#define lb_aon_emmc_cfg_reg0 0x1b0 -#define lb_aon_emmc_cfg_reg1 0x1b4 -#define lb_aon_emmc_cfg_reg2 0x1b8 - -/* lb_aon_emmc_cfg_reg0 register defines */ -#define para_dll_start(x) ((x) & 0xff) -#define para_dll_start_mask 0xff -#define dll_reg_set bit(8) -#define para_dll_lock_num(x) (((x) & 7) << 16) -#define para_dll_lock_num_mask (7 << 16) -#define para_phase_det_sel(x) (((x) & 7) << 20) -#define para_phase_det_sel_mask (7 << 20) -#define para_dll_bypass_mode bit(23) -#define para_half_clk_mode bit(24) - -/* lb_aon_emmc_cfg_reg1 register defines */ -#define read_dqs_delay(x) ((x) & 0x7f) -#define read_dqs_delay_mask (0x7f) -#define read_dqs_bypass_mode bit(7) -#define clk_samp_delay(x) (((x) & 0x7f) << 8) -#define clk_samp_delay_mask (0x7f << 8) -#define clk_samp_bypass_mode bit(15) - -/* lb_aon_emmc_cfg_reg2 register defines */ -#define zx_dll_locked bit(2) - -#endif /* _dw_mmc_zx_h_ */
|
Multi Media Card (MMC)
|
e55f2cf512591dc0051a32e14b8866668d02706a
|
arnd bergmann
|
documentation
|
devicetree
|
bindings, host, mmc
|
mmc: remove sirf prima/atlas driver
|
the csr sirf prima2/atlas platforms are getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove sirf prima/atlas driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['txt', 'kconfig', 'c', 'makefile']
| 4
| 0
| 266
|
--- diff --git a/documentation/devicetree/bindings/mmc/sdhci-sirf.txt b/documentation/devicetree/bindings/mmc/sdhci-sirf.txt --- a/documentation/devicetree/bindings/mmc/sdhci-sirf.txt +++ /dev/null -* sirfprimii/marco/atlas6 sdhci controller - -this file documents differences between the core properties in mmc.txt -and the properties used by the sdhci-sirf driver. - -required properties: -- compatible: sirf,prima2-sdhc - -optional properties: -- cd-gpios: card detect gpio, with zero flags. - -example: - - sd0: sdhci@56000000 { - compatible = "sirf,prima2-sdhc"; - reg = <0xcd000000 0x100000>; - cd-gpios = <&gpio 6 0>; - }; diff --git a/drivers/mmc/host/kconfig b/drivers/mmc/host/kconfig --- a/drivers/mmc/host/kconfig +++ b/drivers/mmc/host/kconfig -config mmc_sdhci_sirf - tristate "sdhci support on csr sirfprimaii and sirfmarco socs" - depends on arch_sirf || compile_test - depends on mmc_sdhci_pltfm - select mmc_sdhci_io_accessors - help - this selects the sdhci support for sirf system-on-chip devices. - - if you have a controller with this interface, say y or m here. - - if unsure, say n. - diff --git a/drivers/mmc/host/makefile b/drivers/mmc/host/makefile --- a/drivers/mmc/host/makefile +++ b/drivers/mmc/host/makefile -obj-$(config_mmc_sdhci_sirf) += sdhci-sirf.o diff --git a/drivers/mmc/host/sdhci-sirf.c b/drivers/mmc/host/sdhci-sirf.c --- a/drivers/mmc/host/sdhci-sirf.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-or-later -/* - * sdhci support for sirf primaii and marco socs - * - * copyright (c) 2011 cambridge silicon radio limited, a csr plc group company. - */ - -#include <linux/delay.h> -#include <linux/device.h> -#include <linux/mmc/host.h> -#include <linux/module.h> -#include <linux/of.h> -#include <linux/mmc/slot-gpio.h> -#include "sdhci-pltfm.h" - -#define sdhci_clk_delay_setting 0x4c -#define sdhci_sirf_8bitbus bit(3) -#define sirf_tuning_count 16384 - -static void sdhci_sirf_set_bus_width(struct sdhci_host *host, int width) -{ - u8 ctrl; - - ctrl = sdhci_readb(host, sdhci_host_control); - ctrl &= ~(sdhci_ctrl_4bitbus | sdhci_sirf_8bitbus); - - /* - * csr atlas7 and prima2 sd host version is not 3.0 - * 8bit-width enable bit of csr sd hosts is 3, - * while stardard hosts use bit 5 - */ - if (width == mmc_bus_width_8) - ctrl |= sdhci_sirf_8bitbus; - else if (width == mmc_bus_width_4) - ctrl |= sdhci_ctrl_4bitbus; - - sdhci_writeb(host, ctrl, sdhci_host_control); -} - -static u32 sdhci_sirf_readl_le(struct sdhci_host *host, int reg) -{ - u32 val = readl(host->ioaddr + reg); - - if (unlikely((reg == sdhci_capabilities_1) && - (host->mmc->caps & mmc_cap_uhs_sdr50))) { - /* fake cap_1 register */ - val = sdhci_support_ddr50 | - sdhci_support_sdr50 | sdhci_use_sdr50_tuning; - } - - if (unlikely(reg == sdhci_slot_int_status)) { - u32 prss = val; - /* fake chips as v3.0 host conreoller */ - prss &= ~(0xff << 16); - val = prss | (sdhci_spec_300 << 16); - } - return val; -} - -static u16 sdhci_sirf_readw_le(struct sdhci_host *host, int reg) -{ - u16 ret = 0; - - ret = readw(host->ioaddr + reg); - - if (unlikely(reg == sdhci_host_version)) { - ret = readw(host->ioaddr + sdhci_host_version); - ret |= sdhci_spec_300; - } - - return ret; -} - -static int sdhci_sirf_execute_tuning(struct sdhci_host *host, u32 opcode) -{ - int tuning_seq_cnt = 3; - int phase; - u8 tuned_phase_cnt = 0; - int rc = 0, longest_range = 0; - int start = -1, end = 0, tuning_value = -1, range = 0; - u16 clock_setting; - struct mmc_host *mmc = host->mmc; - - clock_setting = sdhci_readw(host, sdhci_clk_delay_setting); - clock_setting &= ~0x3fff; - -retry: - phase = 0; - tuned_phase_cnt = 0; - do { - sdhci_writel(host, - clock_setting | phase, - sdhci_clk_delay_setting); - - if (!mmc_send_tuning(mmc, opcode, null)) { - /* tuning is successful at this tuning point */ - tuned_phase_cnt++; - dev_dbg(mmc_dev(mmc), "%s: found good phase = %d ", - mmc_hostname(mmc), phase); - if (start == -1) - start = phase; - end = phase; - range++; - if (phase == (sirf_tuning_count - 1) - && range > longest_range) - tuning_value = (start + end) / 2; - } else { - dev_dbg(mmc_dev(mmc), "%s: found bad phase = %d ", - mmc_hostname(mmc), phase); - if (range > longest_range) { - tuning_value = (start + end) / 2; - longest_range = range; - } - start = -1; - end = range = 0; - } - } while (++phase < sirf_tuning_count); - - if (tuned_phase_cnt && tuning_value > 0) { - /* - * finally set the selected phase in delay - * line hw block. - */ - phase = tuning_value; - sdhci_writel(host, - clock_setting | phase, - sdhci_clk_delay_setting); - - dev_dbg(mmc_dev(mmc), "%s: setting the tuning phase to %d ", - mmc_hostname(mmc), phase); - } else { - if (--tuning_seq_cnt) - goto retry; - /* tuning failed */ - dev_dbg(mmc_dev(mmc), "%s: no tuning point found ", - mmc_hostname(mmc)); - rc = -eio; - } - - return rc; -} - -static const struct sdhci_ops sdhci_sirf_ops = { - .read_l = sdhci_sirf_readl_le, - .read_w = sdhci_sirf_readw_le, - .platform_execute_tuning = sdhci_sirf_execute_tuning, - .set_clock = sdhci_set_clock, - .get_max_clock = sdhci_pltfm_clk_get_max_clock, - .set_bus_width = sdhci_sirf_set_bus_width, - .reset = sdhci_reset, - .set_uhs_signaling = sdhci_set_uhs_signaling, -}; - -static const struct sdhci_pltfm_data sdhci_sirf_pdata = { - .ops = &sdhci_sirf_ops, - .quirks = sdhci_quirk_broken_timeout_val | - sdhci_quirk_data_timeout_uses_sdclk | - sdhci_quirk_cap_clock_base_broken | - sdhci_quirk_reset_cmd_data_on_ios, - .quirks2 = sdhci_quirk2_preset_value_broken, -}; - -static int sdhci_sirf_probe(struct platform_device *pdev) -{ - struct sdhci_host *host; - struct sdhci_pltfm_host *pltfm_host; - struct clk *clk; - int ret; - - clk = devm_clk_get(&pdev->dev, null); - if (is_err(clk)) { - dev_err(&pdev->dev, "unable to get clock"); - return ptr_err(clk); - } - - host = sdhci_pltfm_init(pdev, &sdhci_sirf_pdata, 0); - if (is_err(host)) - return ptr_err(host); - - pltfm_host = sdhci_priv(host); - pltfm_host->clk = clk; - - sdhci_get_of_property(pdev); - - ret = clk_prepare_enable(pltfm_host->clk); - if (ret) - goto err_clk_prepare; - - ret = sdhci_add_host(host); - if (ret) - goto err_sdhci_add; - - /* - * we must request the irq after sdhci_add_host(), as the tasklet only - * gets setup in sdhci_add_host() and we oops. - */ - ret = mmc_gpiod_request_cd(host->mmc, "cd", 0, false, 0); - if (ret == -eprobe_defer) - goto err_request_cd; - if (!ret) - mmc_gpiod_request_cd_irq(host->mmc); - - return 0; - -err_request_cd: - sdhci_remove_host(host, 0); -err_sdhci_add: - clk_disable_unprepare(pltfm_host->clk); -err_clk_prepare: - sdhci_pltfm_free(pdev); - return ret; -} - -static const struct of_device_id sdhci_sirf_of_match[] = { - { .compatible = "sirf,prima2-sdhc" }, - { } -}; -module_device_table(of, sdhci_sirf_of_match); - -static struct platform_driver sdhci_sirf_driver = { - .driver = { - .name = "sdhci-sirf", - .probe_type = probe_prefer_asynchronous, - .of_match_table = sdhci_sirf_of_match, - .pm = &sdhci_pltfm_pmops, - }, - .probe = sdhci_sirf_probe, - .remove = sdhci_pltfm_unregister, -}; - -module_platform_driver(sdhci_sirf_driver); - -module_description("sdhci driver for sirfprimaii/sirfmarco"); -module_author("barry song <21cnbao@gmail.com>"); -module_license("gpl v2");
|
Multi Media Card (MMC)
|
c7b9f01fd12a46333c917f416b0df6ee39e7c774
|
arnd bergmann barry song baohua kernel org
|
documentation
|
devicetree
|
bindings, host, mmc
|
mtd: parsers: add qcom smem parser
|
nand based qualcomm platforms have the partition table populated in the shared memory (smem). hence, add a parser for parsing the partitions from it.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add qcom smem parser
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['parsers']
|
['kconfig', 'c', 'makefile']
| 3
| 179
| 0
|
--- diff --git a/drivers/mtd/parsers/kconfig b/drivers/mtd/parsers/kconfig --- a/drivers/mtd/parsers/kconfig +++ b/drivers/mtd/parsers/kconfig + +config mtd_qcomsmem_parts + tristate "qualcomm smem nand flash partition parser" + depends on mtd_nand_qcom || compile_test + depends on qcom_smem + help + this provides support for parsing partitions from shared memory (smem) + for nand flash on qualcomm platforms. diff --git a/drivers/mtd/parsers/makefile b/drivers/mtd/parsers/makefile --- a/drivers/mtd/parsers/makefile +++ b/drivers/mtd/parsers/makefile +obj-$(config_mtd_qcomsmem_parts) += qcomsmempart.o diff --git a/drivers/mtd/parsers/qcomsmempart.c b/drivers/mtd/parsers/qcomsmempart.c --- /dev/null +++ b/drivers/mtd/parsers/qcomsmempart.c +// spdx-license-identifier: gpl-2.0-only +/* + * qualcomm smem nand flash partition parser + * + * copyright (c) 2020, linaro ltd. + */ + +#include <linux/ctype.h> +#include <linux/module.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/slab.h> +#include <linux/soc/qcom/smem.h> + +#define smem_aarm_partition_table 9 +#define smem_apps 0 + +#define smem_flash_part_magic1 0x55ee73aa +#define smem_flash_part_magic2 0xe35ebddb +#define smem_flash_ptable_v3 3 +#define smem_flash_ptable_v4 4 +#define smem_flash_ptable_max_parts_v3 16 +#define smem_flash_ptable_max_parts_v4 48 +#define smem_flash_ptable_hdr_len (4 * sizeof(u32)) +#define smem_flash_ptable_name_size 16 + +/** + * struct smem_flash_pentry - smem flash partition entry + * @name: name of the partition + * @offset: offset in blocks + * @length: length of the partition in blocks + * @attr: flags for this partition + */ +struct smem_flash_pentry { + char name[smem_flash_ptable_name_size]; + __le32 offset; + __le32 length; + u8 attr; +} __packed __aligned(4); + +/** + * struct smem_flash_ptable - smem flash partition table + * @magic1: partition table magic 1 + * @magic2: partition table magic 2 + * @version: partition table version + * @numparts: number of partitions in this ptable + * @pentry: flash partition entries belonging to this ptable + */ +struct smem_flash_ptable { + __le32 magic1; + __le32 magic2; + __le32 version; + __le32 numparts; + struct smem_flash_pentry pentry[smem_flash_ptable_max_parts_v4]; +} __packed __aligned(4); + +static int parse_qcomsmem_part(struct mtd_info *mtd, + const struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + struct smem_flash_pentry *pentry; + struct smem_flash_ptable *ptable; + size_t len = smem_flash_ptable_hdr_len; + struct mtd_partition *parts; + int ret, i, numparts; + char *name, *c; + + pr_debug("parsing partition table info from smem "); + ptable = qcom_smem_get(smem_apps, smem_aarm_partition_table, &len); + if (is_err(ptable)) { + pr_err("error reading partition table header "); + return ptr_err(ptable); + } + + /* verify ptable magic */ + if (le32_to_cpu(ptable->magic1) != smem_flash_part_magic1 || + le32_to_cpu(ptable->magic2) != smem_flash_part_magic2) { + pr_err("partition table magic verification failed "); + return -einval; + } + + /* ensure that # of partitions is less than the max we have allocated */ + numparts = le32_to_cpu(ptable->numparts); + if (numparts > smem_flash_ptable_max_parts_v4) { + pr_err("partition numbers exceed the max limit "); + return -einval; + } + + /* find out length of partition data based on table version */ + if (le32_to_cpu(ptable->version) <= smem_flash_ptable_v3) { + len = smem_flash_ptable_hdr_len + smem_flash_ptable_max_parts_v3 * + sizeof(struct smem_flash_pentry); + } else if (le32_to_cpu(ptable->version) == smem_flash_ptable_v4) { + len = smem_flash_ptable_hdr_len + smem_flash_ptable_max_parts_v4 * + sizeof(struct smem_flash_pentry); + } else { + pr_err("unknown ptable version (%d)", le32_to_cpu(ptable->version)); + return -einval; + } + + /* + * now that the partition table header has been parsed, verified + * and the length of the partition table calculated, read the + * complete partition table + */ + ptable = qcom_smem_get(smem_apps, smem_aarm_partition_table, &len); + if (is_err_or_null(ptable)) { + pr_err("error reading partition table "); + return ptr_err(ptable); + } + + parts = kcalloc(numparts, sizeof(*parts), gfp_kernel); + if (!parts) + return -enomem; + + for (i = 0; i < numparts; i++) { + pentry = &ptable->pentry[i]; + if (pentry->name[0] == '') + continue; + + name = kstrdup(pentry->name, gfp_kernel); + if (!name) { + ret = -enomem; + goto out_free_parts; + } + + /* convert name to lower case */ + for (c = name; *c != ''; c++) + *c = tolower(*c); + + parts[i].name = name; + parts[i].offset = le32_to_cpu(pentry->offset) * mtd->erasesize; + parts[i].mask_flags = pentry->attr; + parts[i].size = le32_to_cpu(pentry->length) * mtd->erasesize; + pr_debug("%d: %s offs=0x%08x size=0x%08x attr:0x%08x ", + i, pentry->name, le32_to_cpu(pentry->offset), + le32_to_cpu(pentry->length), pentry->attr); + } + + pr_debug("smem partition table found: ver: %d len: %d ", + le32_to_cpu(ptable->version), numparts); + *pparts = parts; + + return numparts; + +out_free_parts: + while (--i >= 0) + kfree(parts[i].name); + kfree(parts); + *pparts = null; + + return ret; +} + +static const struct of_device_id qcomsmem_of_match_table[] = { + { .compatible = "qcom,smem-part" }, + {}, +}; +module_device_table(of, qcomsmem_of_match_table); + +static struct mtd_part_parser mtd_parser_qcomsmem = { + .parse_fn = parse_qcomsmem_part, + .name = "qcomsmem", + .of_match_table = qcomsmem_of_match_table, +}; +module_mtd_part_parser(mtd_parser_qcomsmem); + +module_license("gpl v2"); +module_author("manivannan sadhasivam <manivannan.sadhasivam@linaro.org>"); +module_description("qualcomm smem nand flash partition parser");
|
Memory Technology Devices (MTD)
|
803eb124e1a64e42888542c3444bfe6dac412c7f
|
manivannan sadhasivam
|
drivers
|
mtd
|
parsers
|
mtd: rawnand: qcom: add support for qcom smem parser
|
add support for using qualcomm smem based flash partition parser in qualcomm nand controller.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for qcom smem parser
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['rawnand', 'qcom']
|
['c']
| 1
| 3
| 1
|
--- diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c +static const char * const probes[] = { "qcomsmem", null }; + - ret = mtd_device_register(mtd, null, 0); + ret = mtd_device_parse_register(mtd, probes, null, null, 0);
|
Memory Technology Devices (MTD)
|
82bfd11f1b0364cfd75069d1464f92cc2a985660
|
manivannan sadhasivam
|
drivers
|
mtd
|
nand, raw
|
mtd: spi-nor: add global block unlock command
|
the global block unlock command has different names depending on the manufacturer, but always the same command value: 0x98. macronix's mx25u12835f names it gang block unlock, winbond's w25q128fv names it global block unlock and microchip's sst26vf064b names it global block protection unlock.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add global block unlock command
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['spi-nor']
|
['h', 'c']
| 3
| 39
| 0
|
--- diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c +/** + * spi_nor_global_block_unlock() - unlock global block protection. + * @nor: pointer to 'struct spi_nor'. + * + * return: 0 on success, -errno otherwise. + */ +int spi_nor_global_block_unlock(struct spi_nor *nor) +{ + int ret; + + ret = spi_nor_write_enable(nor); + if (ret) + return ret; + + if (nor->spimem) { + struct spi_mem_op op = + spi_mem_op(spi_mem_op_cmd(spinor_op_gbulk, 0), + spi_mem_op_no_addr, + spi_mem_op_no_dummy, + spi_mem_op_no_data); + + spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); + + ret = spi_mem_exec_op(nor->spimem, &op); + } else { + ret = spi_nor_controller_ops_write_reg(nor, spinor_op_gbulk, + null, 0); + } + + if (ret) { + dev_dbg(nor->dev, "error %d on global block unlock ", ret); + return ret; + } + + return spi_nor_wait_till_ready(nor); +} + diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h +int spi_nor_global_block_unlock(struct spi_nor *nor); diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h +#define spinor_op_gbulk 0x98 /* global block unlock */
|
Memory Technology Devices (MTD)
|
a7a5acba0e06b8f9923faa1a726f0ac1380b719a
|
tudor ambarus
|
drivers
|
mtd
|
mtd, spi-nor
|
mtd: spi-nor: intel-spi: add support for intel alder lake-p spi serial flash
|
intel alder lake-p has the same spi serial flash controller as alder lake-s. add alder lake-p pci id to the driver list of supported devices.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for intel alder lake-p spi serial flash
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['spi-nor', 'intel-spi']
|
['c']
| 1
| 1
| 0
|
--- diff --git a/drivers/mtd/spi-nor/controllers/intel-spi-pci.c b/drivers/mtd/spi-nor/controllers/intel-spi-pci.c --- a/drivers/mtd/spi-nor/controllers/intel-spi-pci.c +++ b/drivers/mtd/spi-nor/controllers/intel-spi-pci.c + { pci_vdevice(intel, 0x51a4), (unsigned long)&cnl_info },
|
Memory Technology Devices (MTD)
|
d5802468c358cd421c09355467be36a41ea5b5d6
|
mika westerberg
|
drivers
|
mtd
|
controllers, spi-nor
|
mtd: spi-nor: sst: add support for global unlock on sst26vf
|
even if sst26vf shares the spinor_op_gbulk opcode with macronix (ex. mx25u12835f) and winbound (ex. w25q128fv), it has its own individual block protection scheme, which is also capable to read-lock individual parameter blocks. thus the sst26vf's individual block protection scheme will reside in the sst.c manufacturer driver.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for global unlock on sst26vf
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['spi-nor', 'sst']
|
['h', 'c']
| 3
| 52
| 3
|
--- diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c -static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr) +int spi_nor_read_cr(struct spi_nor *nor, u8 *cr) diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h +int spi_nor_read_cr(struct spi_nor *nor, u8 *cr); diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c --- a/drivers/mtd/spi-nor/sst.c +++ b/drivers/mtd/spi-nor/sst.c +#define sst26vf_cr_bpnv bit(3) + +static int sst26vf_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) +{ + return -eopnotsupp; +} + +static int sst26vf_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) +{ + int ret; + + /* we only support unlocking the entire flash array. */ + if (ofs != 0 || len != nor->params->size) + return -einval; + + ret = spi_nor_read_cr(nor, nor->bouncebuf); + if (ret) + return ret; + + if (!(nor->bouncebuf[0] & sst26vf_cr_bpnv)) { + dev_dbg(nor->dev, "any block has been permanently locked "); + return -einval; + } + + return spi_nor_global_block_unlock(nor); +} + +static int sst26vf_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) +{ + return -eopnotsupp; +} + +static const struct spi_nor_locking_ops sst26vf_locking_ops = { + .lock = sst26vf_lock, + .unlock = sst26vf_unlock, + .is_locked = sst26vf_is_locked, +}; + +static void sst26vf_default_init(struct spi_nor *nor) +{ + nor->params->locking_ops = &sst26vf_locking_ops; +} + +static const struct spi_nor_fixups sst26vf_fixups = { + .default_init = sst26vf_default_init, +}; + - sect_4k | spi_nor_dual_read | - spi_nor_quad_read) }, + sect_4k | spi_nor_dual_read | spi_nor_quad_read | + spi_nor_has_lock | spi_nor_swp_is_volatile) + .fixups = &sst26vf_fixups },
|
Memory Technology Devices (MTD)
|
75386810d3a61f4bb9e180774291454f7235b8b3
|
tudor ambarus
|
drivers
|
mtd
|
spi-nor
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.