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mtd: rawnand: tango: remove the driver
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the tango platform is getting removed [1], so the driver is no longer needed.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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remove the driver
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
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['rawnand', 'tango']
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['kconfig', 'c', 'makefile']
| 3
| 0
| 735
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--- diff --git a/drivers/mtd/nand/raw/kconfig b/drivers/mtd/nand/raw/kconfig --- a/drivers/mtd/nand/raw/kconfig +++ b/drivers/mtd/nand/raw/kconfig -config mtd_nand_tango - tristate "tango nand controller" - depends on arch_tango || compile_test - depends on has_iomem - help - enables the nand flash controller on tango chips. - diff --git a/drivers/mtd/nand/raw/makefile b/drivers/mtd/nand/raw/makefile --- a/drivers/mtd/nand/raw/makefile +++ b/drivers/mtd/nand/raw/makefile -obj-$(config_mtd_nand_tango) += tango_nand.o diff --git a/drivers/mtd/nand/raw/tango_nand.c b/drivers/mtd/nand/raw/tango_nand.c --- a/drivers/mtd/nand/raw/tango_nand.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * copyright (c) 2016 sigma designs - */ - -#include <linux/io.h> -#include <linux/of.h> -#include <linux/clk.h> -#include <linux/iopoll.h> -#include <linux/module.h> -#include <linux/mtd/rawnand.h> -#include <linux/dmaengine.h> -#include <linux/dma-mapping.h> -#include <linux/platform_device.h> - -/* offsets relative to chip->base */ -#define pbus_cmd 0 -#define pbus_addr 4 -#define pbus_data 8 - -/* offsets relative to reg_base */ -#define nfc_status 0x00 -#define nfc_flash_cmd 0x04 -#define nfc_device_cfg 0x08 -#define nfc_timing1 0x0c -#define nfc_timing2 0x10 -#define nfc_xfer_cfg 0x14 -#define nfc_pkt_0_cfg 0x18 -#define nfc_pkt_n_cfg 0x1c -#define nfc_bb_cfg 0x20 -#define nfc_addr_page 0x24 -#define nfc_addr_offset 0x28 -#define nfc_xfer_status 0x2c - -/* nfc_status values */ -#define cmd_ready bit(31) - -/* nfc_flash_cmd values */ -#define nfc_read 1 -#define nfc_write 2 - -/* nfc_xfer_status values */ -#define page_is_empty bit(16) - -/* offsets relative to mem_base */ -#define metadata 0x000 -#define error_report 0x1c0 - -/* - * error reports are split in two bytes: - * byte 0 for the first packet in the page (pkt_0) - * byte 1 for other packets in the page (pkt_n, for n > 0) - * err_count_pkt_n is the max error count over all but the first packet. - */ -#define err_count_pkt_0(v) (((v) >> 0) & 0x3f) -#define err_count_pkt_n(v) (((v) >> 8) & 0x3f) -#define decode_fail_pkt_0(v) (((v) & bit(7)) == 0) -#define decode_fail_pkt_n(v) (((v) & bit(15)) == 0) - -/* offsets relative to pbus_base */ -#define pbus_cs_ctrl 0x83c -#define pbus_pad_mode 0x8f0 - -/* pbus_cs_ctrl values */ -#define pbus_iordy bit(31) - -/* - * pbus_pad_mode values - * in raw mode, the driver communicates directly with the nand chips. - * in nfc mode, the nand flash controller manages the communication. - * we use nfc mode for read and write; raw mode for everything else. - */ -#define mode_raw 0 -#define mode_nfc bit(31) - -#define metadata_size 4 -#define bbm_size 6 -#define field_order 15 - -#define max_cs 4 - -struct tango_nfc { - struct nand_controller hw; - void __iomem *reg_base; - void __iomem *mem_base; - void __iomem *pbus_base; - struct tango_chip *chips[max_cs]; - struct dma_chan *chan; - int freq_khz; -}; - -#define to_tango_nfc(ptr) container_of(ptr, struct tango_nfc, hw) - -struct tango_chip { - struct nand_chip nand_chip; - void __iomem *base; - u32 timing1; - u32 timing2; - u32 xfer_cfg; - u32 pkt_0_cfg; - u32 pkt_n_cfg; - u32 bb_cfg; -}; - -#define to_tango_chip(ptr) container_of(ptr, struct tango_chip, nand_chip) - -#define xfer_cfg(cs, page_count, steps, metadata_size) \ - ((cs) << 24 | (page_count) << 16 | (steps) << 8 | (metadata_size)) - -#define pkt_cfg(size, strength) ((size) << 16 | (strength)) - -#define bb_cfg(bb_offset, bb_size) ((bb_offset) << 16 | (bb_size)) - -#define timing(t0, t1, t2, t3) ((t0) << 24 | (t1) << 16 | (t2) << 8 | (t3)) - -static void tango_select_target(struct nand_chip *chip, unsigned int cs) -{ - struct tango_nfc *nfc = to_tango_nfc(chip->controller); - struct tango_chip *tchip = to_tango_chip(chip); - - writel_relaxed(tchip->timing1, nfc->reg_base + nfc_timing1); - writel_relaxed(tchip->timing2, nfc->reg_base + nfc_timing2); - writel_relaxed(tchip->xfer_cfg, nfc->reg_base + nfc_xfer_cfg); - writel_relaxed(tchip->pkt_0_cfg, nfc->reg_base + nfc_pkt_0_cfg); - writel_relaxed(tchip->pkt_n_cfg, nfc->reg_base + nfc_pkt_n_cfg); - writel_relaxed(tchip->bb_cfg, nfc->reg_base + nfc_bb_cfg); -} - -static int tango_waitrdy(struct nand_chip *chip, unsigned int timeout_ms) -{ - struct tango_nfc *nfc = to_tango_nfc(chip->controller); - u32 status; - - return readl_relaxed_poll_timeout(nfc->pbus_base + pbus_cs_ctrl, - status, status & pbus_iordy, 20, - timeout_ms); -} - -static int tango_exec_instr(struct nand_chip *chip, - const struct nand_op_instr *instr) -{ - struct tango_chip *tchip = to_tango_chip(chip); - unsigned int i; - - switch (instr->type) { - case nand_op_cmd_instr: - writeb_relaxed(instr->ctx.cmd.opcode, tchip->base + pbus_cmd); - return 0; - case nand_op_addr_instr: - for (i = 0; i < instr->ctx.addr.naddrs; i++) - writeb_relaxed(instr->ctx.addr.addrs[i], - tchip->base + pbus_addr); - return 0; - case nand_op_data_in_instr: - ioread8_rep(tchip->base + pbus_data, instr->ctx.data.buf.in, - instr->ctx.data.len); - return 0; - case nand_op_data_out_instr: - iowrite8_rep(tchip->base + pbus_data, instr->ctx.data.buf.out, - instr->ctx.data.len); - return 0; - case nand_op_waitrdy_instr: - return tango_waitrdy(chip, - instr->ctx.waitrdy.timeout_ms); - default: - break; - } - - return -einval; -} - -static int tango_exec_op(struct nand_chip *chip, - const struct nand_operation *op, - bool check_only) -{ - unsigned int i; - int ret = 0; - - if (check_only) - return 0; - - tango_select_target(chip, op->cs); - for (i = 0; i < op->ninstrs; i++) { - ret = tango_exec_instr(chip, &op->instrs[i]); - if (ret) - break; - } - - return ret; -} - -/* - * the controller does not check for bitflips in erased pages, - * therefore software must check instead. - */ -static int check_erased_page(struct nand_chip *chip, u8 *buf) -{ - struct mtd_info *mtd = nand_to_mtd(chip); - u8 *meta = chip->oob_poi + bbm_size; - u8 *ecc = chip->oob_poi + bbm_size + metadata_size; - const int ecc_size = chip->ecc.bytes; - const int pkt_size = chip->ecc.size; - int i, res, meta_len, bitflips = 0; - - for (i = 0; i < chip->ecc.steps; ++i) { - meta_len = i ? 0 : metadata_size; - res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size, - meta, meta_len, - chip->ecc.strength); - if (res < 0) - mtd->ecc_stats.failed++; - else - mtd->ecc_stats.corrected += res; - - bitflips = max(res, bitflips); - buf += pkt_size; - ecc += ecc_size; - } - - return bitflips; -} - -static int decode_error_report(struct nand_chip *chip) -{ - u32 status, res; - struct mtd_info *mtd = nand_to_mtd(chip); - struct tango_nfc *nfc = to_tango_nfc(chip->controller); - - status = readl_relaxed(nfc->reg_base + nfc_xfer_status); - if (status & page_is_empty) - return 0; - - res = readl_relaxed(nfc->mem_base + error_report); - - if (decode_fail_pkt_0(res) || decode_fail_pkt_n(res)) - return -ebadmsg; - - /* err_count_pkt_n is max, not sum, but that's all we have */ - mtd->ecc_stats.corrected += - err_count_pkt_0(res) + err_count_pkt_n(res); - - return max(err_count_pkt_0(res), err_count_pkt_n(res)); -} - -static void tango_dma_callback(void *arg) -{ - complete(arg); -} - -static int do_dma(struct tango_nfc *nfc, enum dma_data_direction dir, int cmd, - const void *buf, int len, int page) -{ - void __iomem *addr = nfc->reg_base + nfc_status; - struct dma_chan *chan = nfc->chan; - struct dma_async_tx_descriptor *desc; - enum dma_transfer_direction tdir; - struct scatterlist sg; - struct completion tx_done; - int err = -eio; - u32 res, val; - - sg_init_one(&sg, buf, len); - if (dma_map_sg(chan->device->dev, &sg, 1, dir) != 1) - return -eio; - - tdir = dir == dma_to_device ? dma_mem_to_dev : dma_dev_to_mem; - desc = dmaengine_prep_slave_sg(chan, &sg, 1, tdir, dma_prep_interrupt); - if (!desc) - goto dma_unmap; - - desc->callback = tango_dma_callback; - desc->callback_param = &tx_done; - init_completion(&tx_done); - - writel_relaxed(mode_nfc, nfc->pbus_base + pbus_pad_mode); - - writel_relaxed(page, nfc->reg_base + nfc_addr_page); - writel_relaxed(0, nfc->reg_base + nfc_addr_offset); - writel_relaxed(cmd, nfc->reg_base + nfc_flash_cmd); - - dmaengine_submit(desc); - dma_async_issue_pending(chan); - - res = wait_for_completion_timeout(&tx_done, hz); - if (res > 0) - err = readl_poll_timeout(addr, val, val & cmd_ready, 0, 1000); - - writel_relaxed(mode_raw, nfc->pbus_base + pbus_pad_mode); - -dma_unmap: - dma_unmap_sg(chan->device->dev, &sg, 1, dir); - - return err; -} - -static int tango_read_page(struct nand_chip *chip, u8 *buf, - int oob_required, int page) -{ - struct mtd_info *mtd = nand_to_mtd(chip); - struct tango_nfc *nfc = to_tango_nfc(chip->controller); - int err, res, len = mtd->writesize; - - tango_select_target(chip, chip->cur_cs); - if (oob_required) - chip->ecc.read_oob(chip, page); - - err = do_dma(nfc, dma_from_device, nfc_read, buf, len, page); - if (err) - return err; - - res = decode_error_report(chip); - if (res < 0) { - chip->ecc.read_oob_raw(chip, page); - res = check_erased_page(chip, buf); - } - - return res; -} - -static int tango_write_page(struct nand_chip *chip, const u8 *buf, - int oob_required, int page) -{ - struct mtd_info *mtd = nand_to_mtd(chip); - struct tango_nfc *nfc = to_tango_nfc(chip->controller); - const struct nand_sdr_timings *timings; - int err, len = mtd->writesize; - u8 status; - - /* calling tango_write_oob() would send pageprog twice */ - if (oob_required) - return -enotsupp; - - tango_select_target(chip, chip->cur_cs); - writel_relaxed(0xffffffff, nfc->mem_base + metadata); - err = do_dma(nfc, dma_to_device, nfc_write, buf, len, page); - if (err) - return err; - - timings = nand_get_sdr_timings(nand_get_interface_config(chip)); - err = tango_waitrdy(chip, psec_to_msec(timings->tr_max)); - if (err) - return err; - - err = nand_status_op(chip, &status); - if (err) - return err; - - return (status & nand_status_fail) ? -eio : 0; -} - -static void aux_read(struct nand_chip *chip, u8 **buf, int len, int *pos) -{ - *pos += len; - - if (!*buf) { - /* skip over "len" bytes */ - nand_change_read_column_op(chip, *pos, null, 0, false); - } else { - struct tango_chip *tchip = to_tango_chip(chip); - - ioread8_rep(tchip->base + pbus_data, *buf, len); - *buf += len; - } -} - -static void aux_write(struct nand_chip *chip, const u8 **buf, int len, int *pos) -{ - *pos += len; - - if (!*buf) { - /* skip over "len" bytes */ - nand_change_write_column_op(chip, *pos, null, 0, false); - } else { - struct tango_chip *tchip = to_tango_chip(chip); - - iowrite8_rep(tchip->base + pbus_data, *buf, len); - *buf += len; - } -} - -/* - * physical page layout (not drawn to scale) - * - * nb: bad block marker area splits pkt_n in two (n1, n2). - * - * +---+-----------------+-------+-----+-----------+-----+----+-------+ - * | m | pkt_0 | ecc_0 | ... | n1 | bbm | n2 | ecc_n | - * +---+-----------------+-------+-----+-----------+-----+----+-------+ - * - * logical page layout: - * - * +-----+---+-------+-----+-------+ - * oob = | bbm | m | ecc_0 | ... | ecc_n | - * +-----+---+-------+-----+-------+ - * - * +-----------------+-----+-----------------+ - * buf = | pkt_0 | ... | pkt_n | - * +-----------------+-----+-----------------+ - */ -static void raw_read(struct nand_chip *chip, u8 *buf, u8 *oob) -{ - struct mtd_info *mtd = nand_to_mtd(chip); - u8 *oob_orig = oob; - const int page_size = mtd->writesize; - const int ecc_size = chip->ecc.bytes; - const int pkt_size = chip->ecc.size; - int pos = 0; /* position within physical page */ - int rem = page_size; /* bytes remaining until bbm area */ - - if (oob) - oob += bbm_size; - - aux_read(chip, &oob, metadata_size, &pos); - - while (rem > pkt_size) { - aux_read(chip, &buf, pkt_size, &pos); - aux_read(chip, &oob, ecc_size, &pos); - rem = page_size - pos; - } - - aux_read(chip, &buf, rem, &pos); - aux_read(chip, &oob_orig, bbm_size, &pos); - aux_read(chip, &buf, pkt_size - rem, &pos); - aux_read(chip, &oob, ecc_size, &pos); -} - -static void raw_write(struct nand_chip *chip, const u8 *buf, const u8 *oob) -{ - struct mtd_info *mtd = nand_to_mtd(chip); - const u8 *oob_orig = oob; - const int page_size = mtd->writesize; - const int ecc_size = chip->ecc.bytes; - const int pkt_size = chip->ecc.size; - int pos = 0; /* position within physical page */ - int rem = page_size; /* bytes remaining until bbm area */ - - if (oob) - oob += bbm_size; - - aux_write(chip, &oob, metadata_size, &pos); - - while (rem > pkt_size) { - aux_write(chip, &buf, pkt_size, &pos); - aux_write(chip, &oob, ecc_size, &pos); - rem = page_size - pos; - } - - aux_write(chip, &buf, rem, &pos); - aux_write(chip, &oob_orig, bbm_size, &pos); - aux_write(chip, &buf, pkt_size - rem, &pos); - aux_write(chip, &oob, ecc_size, &pos); -} - -static int tango_read_page_raw(struct nand_chip *chip, u8 *buf, - int oob_required, int page) -{ - tango_select_target(chip, chip->cur_cs); - nand_read_page_op(chip, page, 0, null, 0); - raw_read(chip, buf, chip->oob_poi); - return 0; -} - -static int tango_write_page_raw(struct nand_chip *chip, const u8 *buf, - int oob_required, int page) -{ - tango_select_target(chip, chip->cur_cs); - nand_prog_page_begin_op(chip, page, 0, null, 0); - raw_write(chip, buf, chip->oob_poi); - return nand_prog_page_end_op(chip); -} - -static int tango_read_oob(struct nand_chip *chip, int page) -{ - tango_select_target(chip, chip->cur_cs); - nand_read_page_op(chip, page, 0, null, 0); - raw_read(chip, null, chip->oob_poi); - return 0; -} - -static int tango_write_oob(struct nand_chip *chip, int page) -{ - tango_select_target(chip, chip->cur_cs); - nand_prog_page_begin_op(chip, page, 0, null, 0); - raw_write(chip, null, chip->oob_poi); - return nand_prog_page_end_op(chip); -} - -static int oob_ecc(struct mtd_info *mtd, int idx, struct mtd_oob_region *res) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct nand_ecc_ctrl *ecc = &chip->ecc; - - if (idx >= ecc->steps) - return -erange; - - res->offset = bbm_size + metadata_size + ecc->bytes * idx; - res->length = ecc->bytes; - - return 0; -} - -static int oob_free(struct mtd_info *mtd, int idx, struct mtd_oob_region *res) -{ - return -erange; /* no free space in spare area */ -} - -static const struct mtd_ooblayout_ops tango_nand_ooblayout_ops = { - .ecc = oob_ecc, - .free = oob_free, -}; - -static u32 to_ticks(int khz, int ps) -{ - return div_round_up_ull((u64)khz * ps, nsec_per_sec); -} - -static int tango_set_timings(struct nand_chip *chip, int csline, - const struct nand_interface_config *conf) -{ - const struct nand_sdr_timings *sdr = nand_get_sdr_timings(conf); - struct tango_nfc *nfc = to_tango_nfc(chip->controller); - struct tango_chip *tchip = to_tango_chip(chip); - u32 trdy, textw, twc, twpw, tacc, thold, trpw, textr; - int khz = nfc->freq_khz; - - if (is_err(sdr)) - return ptr_err(sdr); - - if (csline == nand_data_iface_check_only) - return 0; - - trdy = to_ticks(khz, sdr->tcea_max - sdr->trea_max); - textw = to_ticks(khz, sdr->twb_max); - twc = to_ticks(khz, sdr->twc_min); - twpw = to_ticks(khz, sdr->twc_min - sdr->twp_min); - - tacc = to_ticks(khz, sdr->trea_max); - thold = to_ticks(khz, sdr->treh_min); - trpw = to_ticks(khz, sdr->trc_min - sdr->treh_min); - textr = to_ticks(khz, sdr->trhz_max); - - tchip->timing1 = timing(trdy, textw, twc, twpw); - tchip->timing2 = timing(tacc, thold, trpw, textr); - - return 0; -} - -static int tango_attach_chip(struct nand_chip *chip) -{ - struct nand_ecc_ctrl *ecc = &chip->ecc; - - ecc->engine_type = nand_ecc_engine_type_on_host; - ecc->algo = nand_ecc_algo_bch; - ecc->bytes = div_round_up(ecc->strength * field_order, bits_per_byte); - - ecc->read_page_raw = tango_read_page_raw; - ecc->write_page_raw = tango_write_page_raw; - ecc->read_page = tango_read_page; - ecc->write_page = tango_write_page; - ecc->read_oob = tango_read_oob; - ecc->write_oob = tango_write_oob; - - return 0; -} - -static const struct nand_controller_ops tango_controller_ops = { - .attach_chip = tango_attach_chip, - .setup_interface = tango_set_timings, - .exec_op = tango_exec_op, -}; - -static int chip_init(struct device *dev, struct device_node *np) -{ - u32 cs; - int err, res; - struct mtd_info *mtd; - struct nand_chip *chip; - struct tango_chip *tchip; - struct nand_ecc_ctrl *ecc; - struct tango_nfc *nfc = dev_get_drvdata(dev); - - tchip = devm_kzalloc(dev, sizeof(*tchip), gfp_kernel); - if (!tchip) - return -enomem; - - res = of_property_count_u32_elems(np, "reg"); - if (res < 0) - return res; - - if (res != 1) - return -enotsupp; /* multi-cs chips are not supported */ - - err = of_property_read_u32_index(np, "reg", 0, &cs); - if (err) - return err; - - if (cs >= max_cs) - return -einval; - - chip = &tchip->nand_chip; - ecc = &chip->ecc; - mtd = nand_to_mtd(chip); - - chip->options = nand_uses_dma | - nand_no_subpage_write | - nand_wait_tccs; - chip->controller = &nfc->hw; - tchip->base = nfc->pbus_base + (cs * 256); - - nand_set_flash_node(chip, np); - mtd_set_ooblayout(mtd, &tango_nand_ooblayout_ops); - mtd->dev.parent = dev; - - err = nand_scan(chip, 1); - if (err) - return err; - - tchip->xfer_cfg = xfer_cfg(cs, 1, ecc->steps, metadata_size); - tchip->pkt_0_cfg = pkt_cfg(ecc->size + metadata_size, ecc->strength); - tchip->pkt_n_cfg = pkt_cfg(ecc->size, ecc->strength); - tchip->bb_cfg = bb_cfg(mtd->writesize, bbm_size); - - err = mtd_device_register(mtd, null, 0); - if (err) { - nand_cleanup(chip); - return err; - } - - nfc->chips[cs] = tchip; - - return 0; -} - -static int tango_nand_remove(struct platform_device *pdev) -{ - struct tango_nfc *nfc = platform_get_drvdata(pdev); - struct nand_chip *chip; - int cs, ret; - - dma_release_channel(nfc->chan); - - for (cs = 0; cs < max_cs; ++cs) { - if (nfc->chips[cs]) { - chip = &nfc->chips[cs]->nand_chip; - ret = mtd_device_unregister(nand_to_mtd(chip)); - warn_on(ret); - nand_cleanup(chip); - } - } - - return 0; -} - -static int tango_nand_probe(struct platform_device *pdev) -{ - int err; - struct clk *clk; - struct resource *res; - struct tango_nfc *nfc; - struct device_node *np; - - nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), gfp_kernel); - if (!nfc) - return -enomem; - - res = platform_get_resource(pdev, ioresource_mem, 0); - nfc->reg_base = devm_ioremap_resource(&pdev->dev, res); - if (is_err(nfc->reg_base)) - return ptr_err(nfc->reg_base); - - res = platform_get_resource(pdev, ioresource_mem, 1); - nfc->mem_base = devm_ioremap_resource(&pdev->dev, res); - if (is_err(nfc->mem_base)) - return ptr_err(nfc->mem_base); - - res = platform_get_resource(pdev, ioresource_mem, 2); - nfc->pbus_base = devm_ioremap_resource(&pdev->dev, res); - if (is_err(nfc->pbus_base)) - return ptr_err(nfc->pbus_base); - - writel_relaxed(mode_raw, nfc->pbus_base + pbus_pad_mode); - - clk = devm_clk_get(&pdev->dev, null); - if (is_err(clk)) - return ptr_err(clk); - - nfc->chan = dma_request_chan(&pdev->dev, "rxtx"); - if (is_err(nfc->chan)) - return ptr_err(nfc->chan); - - platform_set_drvdata(pdev, nfc); - nand_controller_init(&nfc->hw); - nfc->hw.ops = &tango_controller_ops; - nfc->freq_khz = clk_get_rate(clk) / 1000; - - for_each_child_of_node(pdev->dev.of_node, np) { - err = chip_init(&pdev->dev, np); - if (err) { - tango_nand_remove(pdev); - of_node_put(np); - return err; - } - } - - return 0; -} - -static const struct of_device_id tango_nand_ids[] = { - { .compatible = "sigma,smp8758-nand" }, - { /* sentinel */ } -}; -module_device_table(of, tango_nand_ids); - -static struct platform_driver tango_nand_driver = { - .probe = tango_nand_probe, - .remove = tango_nand_remove, - .driver = { - .name = "tango-nand", - .of_match_table = tango_nand_ids, - }, -}; - -module_platform_driver(tango_nand_driver); - -module_license("gpl"); -module_author("sigma designs"); -module_description("tango4 nand flash controller driver");
|
Memory Technology Devices (MTD)
|
94d07f6a539db14ced8c0c2ae6ed4ab9623a24ab
|
arnd bergmann
|
drivers
|
mtd
|
nand, raw
|
iio: hid-sensor-accel-3d: add timestamp channel for gravity sensor
|
the accel_3d sensor already has a timestamp channel, this patch just replicate that for gravity sensor.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add timestamp channel for hid-sensors
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['c']
| 1
| 4
| 2
|
--- diff --git a/drivers/iio/accel/hid-sensor-accel-3d.c b/drivers/iio/accel/hid-sensor-accel-3d.c --- a/drivers/iio/accel/hid-sensor-accel-3d.c +++ b/drivers/iio/accel/hid-sensor-accel-3d.c +#define channel_scan_index_timestamp accel_3d_channel_max - iio_chan_soft_timestamp(3) + iio_chan_soft_timestamp(channel_scan_index_timestamp) - } + }, + iio_chan_soft_timestamp(channel_scan_index_timestamp),
|
Industrial I/O (iio)
|
4c2617207e3a9da1360e58731007ef47f85d6bf3
|
ye xiang
|
drivers
|
iio
|
accel
|
iio: hid-sensor-gyro-3d: add timestamp channel
|
each sample has a timestamp field with this change. this timestamp may be from the sensor hub when present or local kernel timestamp. and the unit of timestamp is nanosecond.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add timestamp channel for hid-sensors
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['c']
| 1
| 24
| 16
|
--- diff --git a/drivers/iio/gyro/hid-sensor-gyro-3d.c b/drivers/iio/gyro/hid-sensor-gyro-3d.c --- a/drivers/iio/gyro/hid-sensor-gyro-3d.c +++ b/drivers/iio/gyro/hid-sensor-gyro-3d.c +#define channel_scan_index_timestamp gyro_3d_channel_max - u32 gyro_val[gyro_3d_channel_max]; + struct { + u32 gyro_val[gyro_3d_channel_max]; + u64 timestamp __aligned(8); + } scan; + s64 timestamp; - } + }, + iio_chan_soft_timestamp(channel_scan_index_timestamp) -/* function to push data to buffer */ -static void hid_sensor_push_data(struct iio_dev *indio_dev, const void *data, - int len) -{ - dev_dbg(&indio_dev->dev, "hid_sensor_push_data "); - iio_push_to_buffers(indio_dev, data); -} - - if (atomic_read(&gyro_state->common_attributes.data_ready)) - hid_sensor_push_data(indio_dev, - gyro_state->gyro_val, - sizeof(gyro_state->gyro_val)); + if (atomic_read(&gyro_state->common_attributes.data_ready)) { + if (!gyro_state->timestamp) + gyro_state->timestamp = iio_get_time_ns(indio_dev); + + iio_push_to_buffers_with_timestamp(indio_dev, &gyro_state->scan, + gyro_state->timestamp); + + gyro_state->timestamp = 0; + } - gyro_state->gyro_val[channel_scan_index_x + offset] = - *(u32 *)raw_data; + gyro_state->scan.gyro_val[channel_scan_index_x + offset] = + *(u32 *)raw_data; + case hid_usage_sensor_time_timestamp: + gyro_state->timestamp = + hid_sensor_convert_timestamp(&gyro_state->common_attributes, + *(s64 *)raw_data); + break;
|
Industrial I/O (iio)
|
4648cbd8fb92de705ae2823717d152e4c71fe50d
|
ye xiang
|
drivers
|
iio
|
gyro
|
iio: hid-sensor-als: add timestamp channel
|
each sample has a timestamp field with this change. this timestamp may be from the sensor hub when present or local kernel timestamp. and the unit of timestamp is nanosecond.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add timestamp channel for hid-sensors
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['c']
| 1
| 23
| 16
|
--- diff --git a/drivers/iio/light/hid-sensor-als.c b/drivers/iio/light/hid-sensor-als.c --- a/drivers/iio/light/hid-sensor-als.c +++ b/drivers/iio/light/hid-sensor-als.c +#define channel_scan_index_timestamp channel_scan_index_max + - u32 illum[channel_scan_index_max]; + struct { + u32 illum[channel_scan_index_max]; + u64 timestamp __aligned(8); + } scan; + s64 timestamp; - } + }, + iio_chan_soft_timestamp(channel_scan_index_timestamp) -/* function to push data to buffer */ -static void hid_sensor_push_data(struct iio_dev *indio_dev, const void *data, - int len) -{ - dev_dbg(&indio_dev->dev, "hid_sensor_push_data "); - iio_push_to_buffers(indio_dev, data); -} - - if (atomic_read(&als_state->common_attributes.data_ready)) - hid_sensor_push_data(indio_dev, - &als_state->illum, - sizeof(als_state->illum)); + if (atomic_read(&als_state->common_attributes.data_ready)) { + if (!als_state->timestamp) + als_state->timestamp = iio_get_time_ns(indio_dev); + + iio_push_to_buffers_with_timestamp(indio_dev, &als_state->scan, + als_state->timestamp); + als_state->timestamp = 0; + } - als_state->illum[channel_scan_index_intensity] = sample_data; - als_state->illum[channel_scan_index_illum] = sample_data; + als_state->scan.illum[channel_scan_index_intensity] = sample_data; + als_state->scan.illum[channel_scan_index_illum] = sample_data; + case hid_usage_sensor_time_timestamp: + als_state->timestamp = hid_sensor_convert_timestamp(&als_state->common_attributes, + *(s64 *)raw_data); + break;
|
Industrial I/O (iio)
|
314f7cad1ad20ebcc3a0a1520bdea567b87e0186
|
ye xiang
|
drivers
|
iio
|
light
|
iio: hid-sensor-incl-3d: add timestamp channel
|
each sample has a timestamp field with this change. this timestamp may be from the sensor hub when present or local kernel timestamp. and the unit of timestamp is nanosecond.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add timestamp channel for hid-sensors
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['c']
| 1
| 27
| 16
|
--- diff --git a/drivers/iio/orientation/hid-sensor-incl-3d.c b/drivers/iio/orientation/hid-sensor-incl-3d.c --- a/drivers/iio/orientation/hid-sensor-incl-3d.c +++ b/drivers/iio/orientation/hid-sensor-incl-3d.c +#define channel_scan_index_timestamp incli_3d_channel_max + - u32 incl_val[incli_3d_channel_max]; + struct { + u32 incl_val[incli_3d_channel_max]; + u64 timestamp __aligned(8); + } scan; + s64 timestamp; - } + }, + iio_chan_soft_timestamp(channel_scan_index_timestamp), -/* function to push data to buffer */ -static void hid_sensor_push_data(struct iio_dev *indio_dev, u8 *data, int len) -{ - dev_dbg(&indio_dev->dev, "hid_sensor_push_data "); - iio_push_to_buffers(indio_dev, (u8 *)data); -} - - if (atomic_read(&incl_state->common_attributes.data_ready)) - hid_sensor_push_data(indio_dev, - (u8 *)incl_state->incl_val, - sizeof(incl_state->incl_val)); + if (atomic_read(&incl_state->common_attributes.data_ready)) { + if (!incl_state->timestamp) + incl_state->timestamp = iio_get_time_ns(indio_dev); + + iio_push_to_buffers_with_timestamp(indio_dev, + &incl_state->scan, + incl_state->timestamp); + + incl_state->timestamp = 0; + } - incl_state->incl_val[channel_scan_index_x] = *(u32 *)raw_data; + incl_state->scan.incl_val[channel_scan_index_x] = *(u32 *)raw_data; - incl_state->incl_val[channel_scan_index_y] = *(u32 *)raw_data; + incl_state->scan.incl_val[channel_scan_index_y] = *(u32 *)raw_data; - incl_state->incl_val[channel_scan_index_z] = *(u32 *)raw_data; + incl_state->scan.incl_val[channel_scan_index_z] = *(u32 *)raw_data; + break; + case hid_usage_sensor_time_timestamp: + incl_state->timestamp = + hid_sensor_convert_timestamp(&incl_state->common_attributes, + *(s64 *)raw_data);
|
Industrial I/O (iio)
|
04fe70d1b8aca1143304edf49c4f730753b06dcf
|
ye xiang
|
drivers
|
iio
|
orientation
|
iio: hid-sensor-magn-3d: add timestamp channel
|
each sample has a timestamp field with this change. this timestamp may be from the sensor hub when present or local kernel timestamp. and the unit of timestamp is nanosecond.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add timestamp channel for hid-sensors
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['c']
| 1
| 30
| 18
|
--- diff --git a/drivers/iio/magnetometer/hid-sensor-magn-3d.c b/drivers/iio/magnetometer/hid-sensor-magn-3d.c --- a/drivers/iio/magnetometer/hid-sensor-magn-3d.c +++ b/drivers/iio/magnetometer/hid-sensor-magn-3d.c + channel_scan_index_timestamp, + s64 timestamp; + hid_usage_sensor_time_timestamp, - } + }, + iio_chan_soft_timestamp(7) -/* function to push data to buffer */ -static void hid_sensor_push_data(struct iio_dev *indio_dev, const void *data) -{ - dev_dbg(&indio_dev->dev, "hid_sensor_push_data "); - iio_push_to_buffers(indio_dev, data); -} - - if (atomic_read(&magn_state->magn_flux_attributes.data_ready)) - hid_sensor_push_data(indio_dev, magn_state->iio_vals); + if (atomic_read(&magn_state->magn_flux_attributes.data_ready)) { + if (!magn_state->timestamp) + magn_state->timestamp = iio_get_time_ns(indio_dev); + + iio_push_to_buffers_with_timestamp(indio_dev, + magn_state->iio_vals, + magn_state->timestamp); + magn_state->timestamp = 0; + } + channel_scan_index_north_magn_tilt_comp; + case hid_usage_sensor_time_timestamp: + magn_state->timestamp = + hid_sensor_convert_timestamp(&magn_state->magn_flux_attributes, + *(s64 *)raw_data); + return ret; - st->iio_vals = devm_kcalloc(&pdev->dev, attr_count, - sizeof(u32), - gfp_kernel); + /* attr_count include timestamp channel, and the iio_vals should be aligned to 8byte */ + st->iio_vals = devm_kcalloc(&pdev->dev, + ((attr_count + 1) % 2 + (attr_count + 1) / 2) * 2, + sizeof(u32), gfp_kernel); - /* set magn_val_addr to iio value address */ - st->magn_val_addr[i] = &(st->iio_vals[*chan_count]); - magn_3d_adjust_channel_bit_mask(_channels, - *chan_count, - st->magn[i].size); + if (i != channel_scan_index_timestamp) { + /* set magn_val_addr to iio value address */ + st->magn_val_addr[i] = &st->iio_vals[*chan_count]; + magn_3d_adjust_channel_bit_mask(_channels, + *chan_count, + st->magn[i].size); + }
|
Industrial I/O (iio)
|
a6bea3d5fe6ff483199da4badce159e2ed78bfa7
|
ye xiang
|
drivers
|
iio
|
magnetometer
|
iio: hid-sensor-rotation: add timestamp channel
|
each sample has a timestamp field with this change. this timestamp may be from the sensor hub when present or local kernel timestamp. and the unit of timestamp is nanosecond.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add timestamp channel for hid-sensors
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['c']
| 1
| 26
| 20
|
--- diff --git a/drivers/iio/orientation/hid-sensor-rotation.c b/drivers/iio/orientation/hid-sensor-rotation.c --- a/drivers/iio/orientation/hid-sensor-rotation.c +++ b/drivers/iio/orientation/hid-sensor-rotation.c - u32 sampled_vals[4]; + struct { + u32 sampled_vals[4] __aligned(16); + u64 timestamp __aligned(8); + } scan; + s64 timestamp; - bit(iio_chan_info_hysteresis) - } + bit(iio_chan_info_hysteresis), + .scan_index = 0 + }, + iio_chan_soft_timestamp(1) - vals[i] = rot_state->sampled_vals[i]; + vals[i] = rot_state->scan.sampled_vals[i]; -/* function to push data to buffer */ -static void hid_sensor_push_data(struct iio_dev *indio_dev, u8 *data, int len) -{ - dev_dbg(&indio_dev->dev, "hid_sensor_push_data >> "); - iio_push_to_buffers(indio_dev, (u8 *)data); - dev_dbg(&indio_dev->dev, "hid_sensor_push_data << "); - -} - - if (atomic_read(&rot_state->common_attributes.data_ready)) - hid_sensor_push_data(indio_dev, - (u8 *)rot_state->sampled_vals, - sizeof(rot_state->sampled_vals)); + if (atomic_read(&rot_state->common_attributes.data_ready)) { + if (!rot_state->timestamp) + rot_state->timestamp = iio_get_time_ns(indio_dev); + + iio_push_to_buffers_with_timestamp(indio_dev, &rot_state->scan, + rot_state->timestamp); + + rot_state->timestamp = 0; + } - memcpy(rot_state->sampled_vals, raw_data, - sizeof(rot_state->sampled_vals)); + memcpy(&rot_state->scan.sampled_vals, raw_data, + sizeof(rot_state->scan.sampled_vals)); + - sizeof(rot_state->sampled_vals)); + sizeof(rot_state->scan.sampled_vals)); + } else if (usage_id == hid_usage_sensor_time_timestamp) { + rot_state->timestamp = hid_sensor_convert_timestamp(&rot_state->common_attributes, + *(s64 *)raw_data);
|
Industrial I/O (iio)
|
4a3582c84ad9a4e734d61a08db9b099141e32abc
|
ye xiang
|
drivers
|
iio
|
orientation
|
iio: accel: kxcjk1013: add rudimentary regulator support
|
kxcjk1013 devices have vdd and vddio power lines. need to make sure the regulators are enabled before any communication with kxcjk1013. this patch introduces vdd/vddio regulators for kxcjk1013.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add rudimentary regulator support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['accel', 'kxcjk1013']
|
['c']
| 1
| 32
| 0
|
--- diff --git a/drivers/iio/accel/kxcjk-1013.c b/drivers/iio/accel/kxcjk-1013.c --- a/drivers/iio/accel/kxcjk-1013.c +++ b/drivers/iio/accel/kxcjk-1013.c +#include <linux/regulator/consumer.h> + struct regulator_bulk_data regulators[2]; +static void kxcjk1013_disable_regulators(void *d) +{ + struct kxcjk1013_data *data = d; + + regulator_bulk_disable(array_size(data->regulators), data->regulators); +} + + data->regulators[0].supply = "vdd"; + data->regulators[1].supply = "vddio"; + ret = devm_regulator_bulk_get(&client->dev, array_size(data->regulators), + data->regulators); + if (ret) + return dev_err_probe(&client->dev, ret, "failed to get regulators "); + + ret = regulator_bulk_enable(array_size(data->regulators), + data->regulators); + if (ret) + return ret; + + ret = devm_add_action_or_reset(&client->dev, kxcjk1013_disable_regulators, data); + if (ret) + return ret; + + /* + * a typical delay of 10ms is required for powering up + * according to the data sheets of supported chips. + * hence double that to play safe. + */ + msleep(20); +
|
Industrial I/O (iio)
|
1d2e91a2db664fa5c0b935fe45314759f6f1fdc5
|
devajith v s
|
drivers
|
iio
|
accel
|
iio: adc: ad7476: add ltc2314-14 support
|
the ltc2314-14 is a 14-bit, 4.5msps, serial sampling a/d converter that draws only 6.2ma from a wide range analog supply adjustable from 2.7v to 5.25v.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add ltc2314-14 support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['adc', 'ad7476']
|
['c']
| 1
| 6
| 0
|
--- diff --git a/drivers/iio/adc/ad7476.c b/drivers/iio/adc/ad7476.c --- a/drivers/iio/adc/ad7476.c +++ b/drivers/iio/adc/ad7476.c + id_ltc2314_14, + [id_ltc2314_14] = { + .channel[0] = ad7940_chan(14), + .channel[1] = iio_chan_soft_timestamp(1), + }, + {"ltc2314-14", id_ltc2314_14},
|
Industrial I/O (iio)
|
28e37a92e30751dd16ffbbccdf36bf15d6a64152
|
dragos bogdan
|
drivers
|
iio
|
adc
|
iio:common:ms_sensors:ms_sensors_i2c: add support for alternative prom layout
|
currently, only the 112bit prom with 7 words is supported. however the ms58xx family also have devices with a 128bit prom on 8 words. see an520: c-code example for ms56xx, ms57xx (except analog sensor), and ms58xx series pressure sensors and the various device datasheets.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for alternative prom layout
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['ms_sensors:ms_sensors_i2c']
|
['c']
| 1
| 59
| 11
|
--- diff --git a/drivers/iio/common/ms_sensors/ms_sensors_i2c.c b/drivers/iio/common/ms_sensors/ms_sensors_i2c.c --- a/drivers/iio/common/ms_sensors/ms_sensors_i2c.c +++ b/drivers/iio/common/ms_sensors/ms_sensors_i2c.c - * ms_sensors_tp_crc_valid() - crc check function for + * ms_sensors_tp_crc4() - calculate prom crc for - * return: true if crc is ok. + * return: crc. -static bool ms_sensors_tp_crc_valid(u16 *prom) +static u8 ms_sensors_tp_crc4(u16 *prom) - u16 n_rem = 0x0000, crc_read = prom[0], crc = (*prom & 0xf000) >> 12; - - prom[ms_sensors_tp_prom_words_nb - 1] = 0; - prom[0] &= 0x0fff; /* clear the crc computation part */ + u16 n_rem = 0x0000; - n_rem >>= 12; - prom[0] = crc_read; - return n_rem == crc; + return n_rem >> 12; +} + +/** + * ms_sensors_tp_crc_valid_112() - crc check function for + * temperature and pressure devices for 112bit prom. + * this function is only used when reading prom coefficients + * + * @prom: pointer to prom coefficients array + * + * return: true if crc is ok. + */ +static bool ms_sensors_tp_crc_valid_112(u16 *prom) +{ + u16 w0 = prom[0], crc_read = (w0 & 0xf000) >> 12; + u8 crc; + + prom[0] &= 0x0fff; /* clear the crc computation part */ + prom[ms_sensors_tp_prom_words_nb - 1] = 0; + + crc = ms_sensors_tp_crc4(prom); + + prom[0] = w0; + + return crc == crc_read; +} + +/** + * ms_sensors_tp_crc_valid_128() - crc check function for + * temperature and pressure devices for 128bit prom. + * this function is only used when reading prom coefficients + * + * @prom: pointer to prom coefficients array + * + * return: true if crc is ok. + */ +static bool ms_sensors_tp_crc_valid_128(u16 *prom) +{ + u16 w7 = prom[7], crc_read = w7 & 0x000f; + u8 crc; + + prom[7] &= 0xff00; /* clear the crc and lsb part */ + + crc = ms_sensors_tp_crc4(prom); + + prom[7] = w7; + + return crc == crc_read; + bool valid; - if (!ms_sensors_tp_crc_valid(dev_data->prom)) { + if (dev_data->hw->prom_len == 8) + valid = ms_sensors_tp_crc_valid_128(dev_data->prom); + else + valid = ms_sensors_tp_crc_valid_112(dev_data->prom); + + if (!valid) {
|
Industrial I/O (iio)
|
9ea7c79097fb3907d7bc587f70963dba7c95658c
|
alexandre belloni
|
drivers
|
iio
|
common, ms_sensors
|
iio: dac: ad5766: add driver support for ad5766
|
the ad5766/ad5767 are 16-channel, 16-bit/12-bit, voltage output dense dacs digital-to-analog converters.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add driver support for ad5766
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dac', 'ad5766']
|
['kconfig', 'c', 'makefile']
| 3
| 654
| 0
|
--- diff --git a/drivers/iio/dac/kconfig b/drivers/iio/dac/kconfig --- a/drivers/iio/dac/kconfig +++ b/drivers/iio/dac/kconfig +config ad5766 + tristate "analog devices ad5766/ad5767 dac driver" + depends on spi_master + help + say yes here to build support for analog devices ad5766, ad5767 + digital to analog converter. + + to compile this driver as a module, choose m here: the + module will be called ad5766. + diff --git a/drivers/iio/dac/makefile b/drivers/iio/dac/makefile --- a/drivers/iio/dac/makefile +++ b/drivers/iio/dac/makefile +obj-$(config_ad5766) += ad5766.o diff --git a/drivers/iio/dac/ad5766.c b/drivers/iio/dac/ad5766.c --- /dev/null +++ b/drivers/iio/dac/ad5766.c +// spdx-license-identifier: gpl-2.0-only +/* + * analog devices ad5766, ad5767 + * digital to analog converters driver + * copyright 2019-2020 analog devices inc. + */ +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/gpio/consumer.h> +#include <linux/iio/iio.h> +#include <linux/module.h> +#include <linux/spi/spi.h> +#include <asm/unaligned.h> + +#define ad5766_upper_word_spi_mask genmask(31, 16) +#define ad5766_lower_word_spi_mask genmask(15, 0) +#define ad5766_dither_source_mask(ch) genmask(((2 * ch) + 1), (2 * ch)) +#define ad5766_dither_source(ch, source) bit((ch * 2) + source) +#define ad5766_dither_scale_mask(x) ad5766_dither_source_mask(x) +#define ad5766_dither_scale(ch, scale) (scale << (ch * 2)) +#define ad5766_dither_enable_mask(ch) bit(ch) +#define ad5766_dither_enable(ch, state) ((!state) << ch) +#define ad5766_dither_invert_mask(ch) bit(ch) +#define ad5766_dither_invert(ch, state) (state << ch) + +#define ad5766_cmd_nop_mux_out 0x00 +#define ad5766_cmd_sdo_cntrl 0x01 +#define ad5766_cmd_wr_in_reg(x) (0x10 | ((x) & genmask(3, 0))) +#define ad5766_cmd_wr_dac_reg(x) (0x20 | ((x) & genmask(3, 0))) +#define ad5766_cmd_sw_ldac 0x30 +#define ad5766_cmd_span_reg 0x40 +#define ad5766_cmd_wr_pwr_dither 0x51 +#define ad5766_cmd_wr_dac_reg_all 0x60 +#define ad5766_cmd_sw_full_reset 0x70 +#define ad5766_cmd_readback_reg(x) (0x80 | ((x) & genmask(3, 0))) +#define ad5766_cmd_dither_sig_1 0x90 +#define ad5766_cmd_dither_sig_2 0xa0 +#define ad5766_cmd_inv_dither 0xb0 +#define ad5766_cmd_dither_scale_1 0xc0 +#define ad5766_cmd_dither_scale_2 0xd0 + +#define ad5766_full_reset_code 0x1234 + +enum ad5766_type { + id_ad5766, + id_ad5767, +}; + +enum ad5766_voltage_range { + ad5766_voltage_range_m20v_0v, + ad5766_voltage_range_m16v_to_0v, + ad5766_voltage_range_m10v_to_0v, + ad5766_voltage_range_m12v_to_14v, + ad5766_voltage_range_m16v_to_10v, + ad5766_voltage_range_m10v_to_6v, + ad5766_voltage_range_m5v_to_5v, + ad5766_voltage_range_m10v_to_10v, +}; + +/** + * struct ad5766_chip_info - chip specific information + * @num_channels: number of channels + * @channels: channel specification + */ +struct ad5766_chip_info { + unsigned int num_channels; + const struct iio_chan_spec *channels; +}; + +enum { + ad5766_dither_enable, + ad5766_dither_invert, + ad5766_dither_source, +}; + +/* + * dither signal can also be scaled. + * available dither scale strings corresponding to "dither_scale" field in + * "struct ad5766_state". + */ +static const char * const ad5766_dither_scales[] = { + "1", + "0.75", + "0.5", + "0.25", +}; + +/** + * struct ad5766_state - driver instance specific data + * @spi: spi device + * @lock: lock used to restrict concurent access to spi device + * @chip_info: chip model specific constants + * @gpio_reset: reset gpio, used to reset the device + * @crt_range: current selected output range + * @dither_enable: power enable bit for each channel dither block (for + * example, d15 = dac 15,d8 = dac 8, and d0 = dac 0) + * 0 - normal operation, 1 - power down + * @dither_invert: inverts the dither signal applied to the selected dac + * outputs + * @dither_source: selects between 2 possible sources: + * 1: n0, 2: n1 + * two bits are used for each channel + * @dither_scale: two bits are used for each of the 16 channels: + * 0: 1 scaling, 1: 0.75 scaling, 2: 0.5 scaling, + * 3: 0.25 scaling. + * @data: spi transfer buffers + */ +struct ad5766_state { + struct spi_device *spi; + struct mutex lock; + const struct ad5766_chip_info *chip_info; + struct gpio_desc *gpio_reset; + enum ad5766_voltage_range crt_range; + u16 dither_enable; + u16 dither_invert; + u32 dither_source; + u32 dither_scale; + union { + u32 d32; + u16 w16[2]; + u8 b8[4]; + } data[3] ____cacheline_aligned; +}; + +struct ad5766_span_tbl { + int min; + int max; +}; + +static const struct ad5766_span_tbl ad5766_span_tbl[] = { + [ad5766_voltage_range_m20v_0v] = {-20, 0}, + [ad5766_voltage_range_m16v_to_0v] = {-16, 0}, + [ad5766_voltage_range_m10v_to_0v] = {-10, 0}, + [ad5766_voltage_range_m12v_to_14v] = {-12, 14}, + [ad5766_voltage_range_m16v_to_10v] = {-16, 10}, + [ad5766_voltage_range_m10v_to_6v] = {-10, 6}, + [ad5766_voltage_range_m5v_to_5v] = {-5, 5}, + [ad5766_voltage_range_m10v_to_10v] = {-10, 10}, +}; + +static int __ad5766_spi_read(struct ad5766_state *st, u8 dac, int *val) +{ + int ret; + struct spi_transfer xfers[] = { + { + .tx_buf = &st->data[0].d32, + .bits_per_word = 8, + .len = 3, + .cs_change = 1, + }, { + .tx_buf = &st->data[1].d32, + .rx_buf = &st->data[2].d32, + .bits_per_word = 8, + .len = 3, + }, + }; + + st->data[0].d32 = ad5766_cmd_readback_reg(dac); + st->data[1].d32 = ad5766_cmd_nop_mux_out; + + ret = spi_sync_transfer(st->spi, xfers, array_size(xfers)); + if (ret) + return ret; + + *val = st->data[2].w16[1]; + + return ret; +} + +static int __ad5766_spi_write(struct ad5766_state *st, u8 command, u16 data) +{ + st->data[0].b8[0] = command; + put_unaligned_be16(data, &st->data[0].b8[1]); + + return spi_write(st->spi, &st->data[0].b8[0], 3); +} + +static int ad5766_read(struct iio_dev *indio_dev, u8 dac, int *val) +{ + struct ad5766_state *st = iio_priv(indio_dev); + int ret; + + mutex_lock(&st->lock); + ret = __ad5766_spi_read(st, dac, val); + mutex_unlock(&st->lock); + + return ret; +} + +static int ad5766_write(struct iio_dev *indio_dev, u8 dac, u16 data) +{ + struct ad5766_state *st = iio_priv(indio_dev); + int ret; + + mutex_lock(&st->lock); + ret = __ad5766_spi_write(st, ad5766_cmd_wr_dac_reg(dac), data); + mutex_unlock(&st->lock); + + return ret; +} + +static int ad5766_reset(struct ad5766_state *st) +{ + int ret; + + if (st->gpio_reset) { + gpiod_set_value_cansleep(st->gpio_reset, 1); + ndelay(100); /* t_reset >= 100ns */ + gpiod_set_value_cansleep(st->gpio_reset, 0); + } else { + ret = __ad5766_spi_write(st, ad5766_cmd_sw_full_reset, + ad5766_full_reset_code); + if (ret < 0) + return ret; + } + + /* + * minimum time between a reset and the subsequent successful write is + * typically 25 ns + */ + ndelay(25); + + return 0; +} + +static int ad5766_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, + int *val2, + long m) +{ + struct ad5766_state *st = iio_priv(indio_dev); + int ret; + + switch (m) { + case iio_chan_info_raw: + ret = ad5766_read(indio_dev, chan->address, val); + if (ret) + return ret; + + return iio_val_int; + case iio_chan_info_offset: + *val = ad5766_span_tbl[st->crt_range].min; + + return iio_val_int; + case iio_chan_info_scale: + *val = ad5766_span_tbl[st->crt_range].max - + ad5766_span_tbl[st->crt_range].min; + *val2 = st->chip_info->channels[0].scan_type.realbits; + + return iio_val_fractional_log2; + default: + return -einval; + } +} + +static int ad5766_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, + int val2, + long info) +{ + switch (info) { + case iio_chan_info_raw: + { + const int max_val = genmask(chan->scan_type.realbits - 1, 0); + + if (val > max_val || val < 0) + return -einval; + val <<= chan->scan_type.shift; + return ad5766_write(indio_dev, chan->address, val); + } + default: + return -einval; + } +} + +static const struct iio_info ad5766_info = { + .read_raw = ad5766_read_raw, + .write_raw = ad5766_write_raw, +}; + +static int ad5766_get_dither_source(struct iio_dev *dev, + const struct iio_chan_spec *chan) +{ + struct ad5766_state *st = iio_priv(dev); + u32 source; + + source = st->dither_source & ad5766_dither_source_mask(chan->channel); + source = source >> (chan->channel * 2); + source -= 1; + + return source; +} + +static int ad5766_set_dither_source(struct iio_dev *dev, + const struct iio_chan_spec *chan, + unsigned int source) +{ + struct ad5766_state *st = iio_priv(dev); + uint16_t val; + int ret; + + st->dither_source &= ~ad5766_dither_source_mask(chan->channel); + st->dither_source |= ad5766_dither_source(chan->channel, source); + + val = field_get(ad5766_lower_word_spi_mask, st->dither_source); + ret = ad5766_write(dev, ad5766_cmd_dither_sig_1, val); + if (ret) + return ret; + + val = field_get(ad5766_upper_word_spi_mask, st->dither_source); + + return ad5766_write(dev, ad5766_cmd_dither_sig_2, val); +} + +static int ad5766_get_dither_scale(struct iio_dev *dev, + const struct iio_chan_spec *chan) +{ + struct ad5766_state *st = iio_priv(dev); + u32 scale; + + scale = st->dither_scale & ad5766_dither_scale_mask(chan->channel); + + return (scale >> (chan->channel * 2)); +} + +static int ad5766_set_dither_scale(struct iio_dev *dev, + const struct iio_chan_spec *chan, + unsigned int scale) +{ + int ret; + struct ad5766_state *st = iio_priv(dev); + uint16_t val; + + st->dither_scale &= ~ad5766_dither_scale_mask(chan->channel); + st->dither_scale |= ad5766_dither_scale(chan->channel, scale); + + val = field_get(ad5766_lower_word_spi_mask, st->dither_scale); + ret = ad5766_write(dev, ad5766_cmd_dither_scale_1, val); + if (ret) + return ret; + val = field_get(ad5766_upper_word_spi_mask, st->dither_scale); + + return ad5766_write(dev, ad5766_cmd_dither_scale_2, val); +} + +static const struct iio_enum ad5766_dither_scale_enum = { + .items = ad5766_dither_scales, + .num_items = array_size(ad5766_dither_scales), + .set = ad5766_set_dither_scale, + .get = ad5766_get_dither_scale, +}; + +static ssize_t ad5766_read_ext(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct ad5766_state *st = iio_priv(indio_dev); + + switch (private) { + case ad5766_dither_enable: + return sprintf(buf, "%u ", + !(st->dither_enable & bit(chan->channel))); + break; + case ad5766_dither_invert: + return sprintf(buf, "%u ", + !!(st->dither_invert & bit(chan->channel))); + break; + case ad5766_dither_source: + return sprintf(buf, "%d ", + ad5766_get_dither_source(indio_dev, chan)); + default: + return -einval; + } +} + +static ssize_t ad5766_write_ext(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct ad5766_state *st = iio_priv(indio_dev); + bool readin; + int ret; + + ret = kstrtobool(buf, &readin); + if (ret) + return ret; + + switch (private) { + case ad5766_dither_enable: + st->dither_enable &= ~ad5766_dither_enable_mask(chan->channel); + st->dither_enable |= ad5766_dither_enable(chan->channel, + readin); + ret = ad5766_write(indio_dev, ad5766_cmd_wr_pwr_dither, + st->dither_enable); + break; + case ad5766_dither_invert: + st->dither_invert &= ~ad5766_dither_invert_mask(chan->channel); + st->dither_invert |= ad5766_dither_invert(chan->channel, + readin); + ret = ad5766_write(indio_dev, ad5766_cmd_inv_dither, + st->dither_invert); + break; + case ad5766_dither_source: + ret = ad5766_set_dither_source(indio_dev, chan, readin); + break; + default: + return -einval; + } + + return ret ? ret : len; +} + +#define _ad5766_chan_ext_info(_name, _what, _shared) { \ + .name = _name, \ + .read = ad5766_read_ext, \ + .write = ad5766_write_ext, \ + .private = _what, \ + .shared = _shared, \ +} + +#define iio_enum_available_shared(_name, _shared, _e) \ +{ \ + .name = (_name "_available"), \ + .shared = _shared, \ + .read = iio_enum_available_read, \ + .private = (uintptr_t)(_e), \ +} + +static const struct iio_chan_spec_ext_info ad5766_ext_info[] = { + + _ad5766_chan_ext_info("dither_enable", ad5766_dither_enable, + iio_separate), + _ad5766_chan_ext_info("dither_invert", ad5766_dither_invert, + iio_separate), + _ad5766_chan_ext_info("dither_source", ad5766_dither_source, + iio_separate), + iio_enum("dither_scale", iio_separate, &ad5766_dither_scale_enum), + iio_enum_available_shared("dither_scale", + iio_separate, + &ad5766_dither_scale_enum), + {} +}; + +#define ad576x_channel(_chan, _bits) { \ + .type = iio_voltage, \ + .indexed = 1, \ + .output = 1, \ + .channel = (_chan), \ + .address = (_chan), \ + .info_mask_separate = bit(iio_chan_info_raw), \ + .info_mask_shared_by_type = bit(iio_chan_info_offset) | \ + bit(iio_chan_info_scale), \ + .scan_type = { \ + .sign = 'u', \ + .realbits = (_bits), \ + .storagebits = 16, \ + .shift = 16 - (_bits), \ + }, \ + .ext_info = ad5766_ext_info, \ +} + +#define declare_ad576x_channels(_name, _bits) \ +const struct iio_chan_spec _name[] = { \ + ad576x_channel(0, (_bits)), \ + ad576x_channel(1, (_bits)), \ + ad576x_channel(2, (_bits)), \ + ad576x_channel(3, (_bits)), \ + ad576x_channel(4, (_bits)), \ + ad576x_channel(5, (_bits)), \ + ad576x_channel(6, (_bits)), \ + ad576x_channel(7, (_bits)), \ + ad576x_channel(8, (_bits)), \ + ad576x_channel(9, (_bits)), \ + ad576x_channel(10, (_bits)), \ + ad576x_channel(11, (_bits)), \ + ad576x_channel(12, (_bits)), \ + ad576x_channel(13, (_bits)), \ + ad576x_channel(14, (_bits)), \ + ad576x_channel(15, (_bits)), \ +} + +static declare_ad576x_channels(ad5766_channels, 16); +static declare_ad576x_channels(ad5767_channels, 12); + +static const struct ad5766_chip_info ad5766_chip_infos[] = { + [id_ad5766] = { + .num_channels = array_size(ad5766_channels), + .channels = ad5766_channels, + }, + [id_ad5767] = { + .num_channels = array_size(ad5767_channels), + .channels = ad5767_channels, + }, +}; + +static int ad5766_get_output_range(struct ad5766_state *st) +{ + int i, ret, min, max, tmp[2]; + + ret = device_property_read_u32_array(&st->spi->dev, + "output-range-voltage", + tmp, 2); + if (ret) + return ret; + + min = tmp[0] / 1000; + max = tmp[1] / 1000; + for (i = 0; i < array_size(ad5766_span_tbl); i++) { + if (ad5766_span_tbl[i].min != min || + ad5766_span_tbl[i].max != max) + continue; + + st->crt_range = i; + + return 0; + } + + return -einval; +} + +static int ad5766_default_setup(struct ad5766_state *st) +{ + uint16_t val; + int ret, i; + + /* always issue a reset before writing to the span register. */ + ret = ad5766_reset(st); + if (ret) + return ret; + + ret = ad5766_get_output_range(st); + if (ret) + return ret; + + /* dither power down */ + st->dither_enable = genmask(15, 0); + ret = __ad5766_spi_write(st, ad5766_cmd_wr_pwr_dither, + st->dither_enable); + if (ret) + return ret; + + st->dither_source = 0; + for (i = 0; i < array_size(ad5766_channels); i++) + st->dither_source |= ad5766_dither_source(i, 0); + val = field_get(ad5766_lower_word_spi_mask, st->dither_source); + ret = __ad5766_spi_write(st, ad5766_cmd_dither_sig_1, val); + if (ret) + return ret; + + val = field_get(ad5766_upper_word_spi_mask, st->dither_source); + ret = __ad5766_spi_write(st, ad5766_cmd_dither_sig_2, val); + if (ret) + return ret; + + st->dither_scale = 0; + val = field_get(ad5766_lower_word_spi_mask, st->dither_scale); + ret = __ad5766_spi_write(st, ad5766_cmd_dither_scale_1, val); + if (ret) + return ret; + + val = field_get(ad5766_upper_word_spi_mask, st->dither_scale); + ret = __ad5766_spi_write(st, ad5766_cmd_dither_scale_2, val); + if (ret) + return ret; + + st->dither_invert = 0; + ret = __ad5766_spi_write(st, ad5766_cmd_inv_dither, st->dither_invert); + if (ret) + return ret; + + return __ad5766_spi_write(st, ad5766_cmd_span_reg, st->crt_range); +} + +static int ad5766_probe(struct spi_device *spi) +{ + enum ad5766_type type; + struct iio_dev *indio_dev; + struct ad5766_state *st; + int ret; + + indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); + if (!indio_dev) + return -enomem; + + st = iio_priv(indio_dev); + mutex_init(&st->lock); + + st->spi = spi; + type = spi_get_device_id(spi)->driver_data; + st->chip_info = &ad5766_chip_infos[type]; + + indio_dev->channels = st->chip_info->channels; + indio_dev->num_channels = st->chip_info->num_channels; + indio_dev->info = &ad5766_info; + indio_dev->dev.parent = &spi->dev; + indio_dev->dev.of_node = spi->dev.of_node; + indio_dev->name = spi_get_device_id(spi)->name; + indio_dev->modes = indio_direct_mode; + + st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset", + gpiod_out_low); + if (is_err(st->gpio_reset)) + return ptr_err(st->gpio_reset); + + ret = ad5766_default_setup(st); + if (ret) + return ret; + + return devm_iio_device_register(&spi->dev, indio_dev); +} + +static const struct of_device_id ad5766_dt_match[] = { + { .compatible = "adi,ad5766" }, + { .compatible = "adi,ad5767" }, + {} +}; +module_device_table(of, ad5766_dt_match); + +static const struct spi_device_id ad5766_spi_ids[] = { + { "ad5766", id_ad5766 }, + { "ad5767", id_ad5767 }, + {} +}; +module_device_table(spi, ad5766_spi_ids); + +static struct spi_driver ad5766_driver = { + .driver = { + .name = "ad5766", + .of_match_table = ad5766_dt_match, + }, + .probe = ad5766_probe, + .id_table = ad5766_spi_ids, +}; +module_spi_driver(ad5766_driver); + +module_author("denis-gabriel gheorghescu <denis.gheorghescu@analog.com>"); +module_description("analog devices ad5766/ad5767 dacs"); +module_license("gpl v2");
|
Industrial I/O (iio)
|
fd9373e41b9ba5b609f97e98a04687f4ff136aff
|
cristian pop
|
drivers
|
iio
|
dac
|
iio: gyro: bmg160: add rudimentary regulator support
|
bmg160 needs vdd and vddio regulators that might need to be explicitly enabled. add some rudimentary support to obtain and enable these regulators during probe() and disable them using a devm action.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add rudimentary regulator support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['gyro', 'bmg160']
|
['c']
| 1
| 25
| 0
|
--- diff --git a/drivers/iio/gyro/bmg160_core.c b/drivers/iio/gyro/bmg160_core.c --- a/drivers/iio/gyro/bmg160_core.c +++ b/drivers/iio/gyro/bmg160_core.c +#include <linux/regulator/consumer.h> + struct regulator_bulk_data regulators[2]; +static void bmg160_disable_regulators(void *d) +{ + struct bmg160_data *data = d; + + regulator_bulk_disable(array_size(data->regulators), data->regulators); +} + + data->regulators[0].supply = "vdd"; + data->regulators[1].supply = "vddio"; + ret = devm_regulator_bulk_get(dev, array_size(data->regulators), + data->regulators); + if (ret) + return dev_err_probe(dev, ret, "failed to get regulators "); + + ret = regulator_bulk_enable(array_size(data->regulators), + data->regulators); + if (ret) + return ret; + + ret = devm_add_action_or_reset(dev, bmg160_disable_regulators, data); + if (ret) + return ret; +
|
Industrial I/O (iio)
|
ce69361ab74681b095d72376ad173dea3f4d9c29
|
stephan gerhold linus walleij linus walleij linaro org
|
drivers
|
iio
|
gyro
|
iio: hid-sensors: add hinge sensor driver
|
the hinge sensor is a common custom sensor on laptops. it calculates the angle between the lid (screen) and the base (keyboard). in addition, it also exposes screen and the keyboard angles with respect to the ground. applications can easily get laptop's status in space through this sensor, in order to display appropriate user interface.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add hinge sensor driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['hid-sensors']
|
['kconfig', 'c', 'makefile']
| 4
| 404
| 0
|
--- diff --git a/drivers/iio/common/hid-sensors/hid-sensor-attributes.c b/drivers/iio/common/hid-sensors/hid-sensor-attributes.c --- a/drivers/iio/common/hid-sensors/hid-sensor-attributes.c +++ b/drivers/iio/common/hid-sensors/hid-sensor-attributes.c + {hid_usage_sensor_hinge, 0, 0, 17453293}, + {hid_usage_sensor_hinge, hid_usage_sensor_units_degrees, 0, 17453293}, diff --git a/drivers/iio/position/kconfig b/drivers/iio/position/kconfig --- a/drivers/iio/position/kconfig +++ b/drivers/iio/position/kconfig +config hid_sensor_custom_intel_hinge + depends on hid_sensor_hub + select iio_buffer + select iio_triggered_buffer + select hid_sensor_iio_common + select hid_sensor_iio_trigger + tristate "hid hinge" + help + this sensor present three angles, hinge angel, screen angles + and keyboard angle respect to horizon (ground). + say yes here to build support for the hid custom + intel hinge sensor. + + to compile this driver as a module, choose m here: the + module will be called hid-sensor-custom-hinge. + diff --git a/drivers/iio/position/makefile b/drivers/iio/position/makefile --- a/drivers/iio/position/makefile +++ b/drivers/iio/position/makefile +obj-$(config_hid_sensor_custom_intel_hinge) += hid-sensor-custom-intel-hinge.o diff --git a/drivers/iio/position/hid-sensor-custom-intel-hinge.c b/drivers/iio/position/hid-sensor-custom-intel-hinge.c --- /dev/null +++ b/drivers/iio/position/hid-sensor-custom-intel-hinge.c +// spdx-license-identifier: gpl-2.0-only +/* + * hid sensors driver + * copyright (c) 2020, intel corporation. + */ +#include <linux/hid-sensor-hub.h> +#include <linux/iio/buffer.h> +#include <linux/iio/iio.h> +#include <linux/platform_device.h> + +#include "../common/hid-sensors/hid-sensor-trigger.h" + +enum hinge_channel { + channel_scan_index_hinge_angle, + channel_scan_index_screen_angle, + channel_scan_index_keyboard_angle, + channel_scan_index_max, +}; + +#define channel_scan_index_timestamp channel_scan_index_max + +static const u32 hinge_addresses[channel_scan_index_max] = { + hid_usage_sensor_data_field_custom_value(1), + hid_usage_sensor_data_field_custom_value(2), + hid_usage_sensor_data_field_custom_value(3) +}; + +static const char *const hinge_labels[channel_scan_index_max] = { "hinge", + "screen", + "keyboard" }; + +struct hinge_state { + struct iio_dev *indio_dev; + struct hid_sensor_hub_attribute_info hinge[channel_scan_index_max]; + struct hid_sensor_hub_callbacks callbacks; + struct hid_sensor_common common_attributes; + const char *labels[channel_scan_index_max]; + struct { + u32 hinge_val[3]; + u64 timestamp __aligned(8); + } scan; + + int scale_pre_decml; + int scale_post_decml; + int scale_precision; + int value_offset; + u64 timestamp; +}; + +/* channel definitions */ +static const struct iio_chan_spec hinge_channels[] = { + { + .type = iio_angl, + .indexed = 1, + .channel = 0, + .info_mask_separate = bit(iio_chan_info_raw), + .info_mask_shared_by_type = + bit(iio_chan_info_offset) | bit(iio_chan_info_scale) | + bit(iio_chan_info_samp_freq) | bit(iio_chan_info_hysteresis), + .scan_index = channel_scan_index_hinge_angle, + .scan_type = { + .sign = 's', + .storagebits = 32, + }, + }, { + .type = iio_angl, + .indexed = 1, + .channel = 1, + .info_mask_separate = bit(iio_chan_info_raw), + .info_mask_shared_by_type = + bit(iio_chan_info_offset) | bit(iio_chan_info_scale) | + bit(iio_chan_info_samp_freq) | bit(iio_chan_info_hysteresis), + .scan_index = channel_scan_index_screen_angle, + .scan_type = { + .sign = 's', + .storagebits = 32, + }, + }, { + .type = iio_angl, + .indexed = 1, + .channel = 2, + .info_mask_separate = bit(iio_chan_info_raw), + .info_mask_shared_by_type = + bit(iio_chan_info_offset) | bit(iio_chan_info_scale) | + bit(iio_chan_info_samp_freq) | bit(iio_chan_info_hysteresis), + .scan_index = channel_scan_index_keyboard_angle, + .scan_type = { + .sign = 's', + .storagebits = 32, + }, + }, + iio_chan_soft_timestamp(channel_scan_index_timestamp) +}; + +/* adjust channel real bits based on report descriptor */ +static void hinge_adjust_channel_realbits(struct iio_chan_spec *channels, + int channel, int size) +{ + channels[channel].scan_type.realbits = size * 8; +} + +/* channel read_raw handler */ +static int hinge_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, int *val2, + long mask) +{ + struct hinge_state *st = iio_priv(indio_dev); + struct hid_sensor_hub_device *hsdev; + int report_id; + s32 min; + + hsdev = st->common_attributes.hsdev; + switch (mask) { + case iio_chan_info_raw: + hid_sensor_power_state(&st->common_attributes, true); + report_id = st->hinge[chan->scan_index].report_id; + min = st->hinge[chan->scan_index].logical_minimum; + if (report_id < 0) { + hid_sensor_power_state(&st->common_attributes, false); + return -einval; + } + + *val = sensor_hub_input_attr_get_raw_value(st->common_attributes.hsdev, + hsdev->usage, + hinge_addresses[chan->scan_index], + report_id, + sensor_hub_sync, min < 0); + + hid_sensor_power_state(&st->common_attributes, false); + return iio_val_int; + case iio_chan_info_scale: + *val = st->scale_pre_decml; + *val2 = st->scale_post_decml; + return st->scale_precision; + case iio_chan_info_offset: + *val = st->value_offset; + return iio_val_int; + case iio_chan_info_samp_freq: + return hid_sensor_read_samp_freq_value(&st->common_attributes, + val, val2); + case iio_chan_info_hysteresis: + return hid_sensor_read_raw_hyst_value(&st->common_attributes, + val, val2); + default: + return -einval; + } +} + +/* channel write_raw handler */ +static int hinge_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int val, int val2, + long mask) +{ + struct hinge_state *st = iio_priv(indio_dev); + + switch (mask) { + case iio_chan_info_samp_freq: + return hid_sensor_write_samp_freq_value(&st->common_attributes, + val, val2); + case iio_chan_info_hysteresis: + return hid_sensor_write_raw_hyst_value(&st->common_attributes, + val, val2); + default: + return -einval; + } +} + +static int hinge_read_label(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, char *label) +{ + struct hinge_state *st = iio_priv(indio_dev); + + return sprintf(label, "%s ", st->labels[chan->channel]); +} + +static const struct iio_info hinge_info = { + .read_raw = hinge_read_raw, + .write_raw = hinge_write_raw, + .read_label = hinge_read_label, +}; + +/* + * callback handler to send event after all samples are received + * and captured. + */ +static int hinge_proc_event(struct hid_sensor_hub_device *hsdev, + unsigned int usage_id, void *priv) +{ + struct iio_dev *indio_dev = platform_get_drvdata(priv); + struct hinge_state *st = iio_priv(indio_dev); + + if (atomic_read(&st->common_attributes.data_ready)) { + if (!st->timestamp) + st->timestamp = iio_get_time_ns(indio_dev); + + iio_push_to_buffers_with_timestamp(indio_dev, &st->scan, + st->timestamp); + + st->timestamp = 0; + } + return 0; +} + +/* capture samples in local storage */ +static int hinge_capture_sample(struct hid_sensor_hub_device *hsdev, + unsigned int usage_id, size_t raw_len, + char *raw_data, void *priv) +{ + struct iio_dev *indio_dev = platform_get_drvdata(priv); + struct hinge_state *st = iio_priv(indio_dev); + int offset; + + switch (usage_id) { + case hid_usage_sensor_data_field_custom_value(1): + case hid_usage_sensor_data_field_custom_value(2): + case hid_usage_sensor_data_field_custom_value(3): + offset = usage_id - hid_usage_sensor_data_field_custom_value(1); + st->scan.hinge_val[offset] = *(u32 *)raw_data; + return 0; + case hid_usage_sensor_time_timestamp: + st->timestamp = hid_sensor_convert_timestamp(&st->common_attributes, + *(int64_t *)raw_data); + return 0; + default: + return -einval; + } +} + +/* parse report which is specific to an usage id */ +static int hinge_parse_report(struct platform_device *pdev, + struct hid_sensor_hub_device *hsdev, + struct iio_chan_spec *channels, + unsigned int usage_id, struct hinge_state *st) +{ + int ret; + int i; + + for (i = 0; i < channel_scan_index_max; ++i) { + ret = sensor_hub_input_get_attribute_info(hsdev, + hid_input_report, + usage_id, + hinge_addresses[i], + &st->hinge[i]); + if (ret < 0) + return ret; + + hinge_adjust_channel_realbits(channels, i, st->hinge[i].size); + } + + st->scale_precision = hid_sensor_format_scale(hid_usage_sensor_hinge, + &st->hinge[channel_scan_index_hinge_angle], + &st->scale_pre_decml, &st->scale_post_decml); + + /* set sensitivity field ids, when there is no individual modifier */ + if (st->common_attributes.sensitivity.index < 0) { + sensor_hub_input_get_attribute_info(hsdev, + hid_feature_report, usage_id, + hid_usage_sensor_data_mod_change_sensitivity_abs | + hid_usage_sensor_data_field_custom_value(1), + &st->common_attributes.sensitivity); + dev_dbg(&pdev->dev, "sensitivity index:report %d:%d ", + st->common_attributes.sensitivity.index, + st->common_attributes.sensitivity.report_id); + } + + return ret; +} + +/* function to initialize the processing for usage id */ +static int hid_hinge_probe(struct platform_device *pdev) +{ + struct hinge_state *st; + struct iio_dev *indio_dev; + struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data; + int ret; + int i; + + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st)); + if (!indio_dev) + return -enomem; + + platform_set_drvdata(pdev, indio_dev); + + st = iio_priv(indio_dev); + st->common_attributes.hsdev = hsdev; + st->common_attributes.pdev = pdev; + st->indio_dev = indio_dev; + for (i = 0; i < channel_scan_index_max; i++) + st->labels[i] = hinge_labels[i]; + + ret = hid_sensor_parse_common_attributes(hsdev, hsdev->usage, + &st->common_attributes); + if (ret) { + dev_err(&pdev->dev, "failed to setup common attributes "); + return ret; + } + + indio_dev->num_channels = array_size(hinge_channels); + indio_dev->channels = devm_kmemdup(&indio_dev->dev, hinge_channels, + sizeof(hinge_channels), gfp_kernel); + if (!indio_dev->channels) + return -enomem; + + ret = hinge_parse_report(pdev, hsdev, + (struct iio_chan_spec *)indio_dev->channels, + hsdev->usage, st); + if (ret) { + dev_err(&pdev->dev, "failed to setup attributes "); + return ret; + } + + indio_dev->dev.parent = &pdev->dev; + indio_dev->info = &hinge_info; + indio_dev->name = "hinge"; + indio_dev->modes = indio_direct_mode; + + atomic_set(&st->common_attributes.data_ready, 0); + ret = hid_sensor_setup_trigger(indio_dev, indio_dev->name, + &st->common_attributes); + if (ret < 0) { + dev_err(&pdev->dev, "trigger setup failed "); + return ret; + } + + st->callbacks.send_event = hinge_proc_event; + st->callbacks.capture_sample = hinge_capture_sample; + st->callbacks.pdev = pdev; + ret = sensor_hub_register_callback(hsdev, hsdev->usage, &st->callbacks); + if (ret < 0) { + dev_err(&pdev->dev, "callback reg failed "); + goto error_remove_trigger; + } + + ret = iio_device_register(indio_dev); + if (ret) { + dev_err(&pdev->dev, "device register failed "); + goto error_remove_callback; + } + + return ret; + +error_remove_callback: + sensor_hub_remove_callback(hsdev, hsdev->usage); +error_remove_trigger: + hid_sensor_remove_trigger(indio_dev, &st->common_attributes); + return ret; +} + +/* function to deinitialize the processing for usage id */ +static int hid_hinge_remove(struct platform_device *pdev) +{ + struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data; + struct iio_dev *indio_dev = platform_get_drvdata(pdev); + struct hinge_state *st = iio_priv(indio_dev); + + iio_device_unregister(indio_dev); + sensor_hub_remove_callback(hsdev, hsdev->usage); + hid_sensor_remove_trigger(indio_dev, &st->common_attributes); + + return 0; +} + +static const struct platform_device_id hid_hinge_ids[] = { + { + /* format: hid-sensor-int-usage_id_in_hex_lowercase */ + .name = "hid-sensor-int-020b", + }, + { /* sentinel */ } +}; +module_device_table(platform, hid_hinge_ids); + +static struct platform_driver hid_hinge_platform_driver = { + .id_table = hid_hinge_ids, + .driver = { + .name = kbuild_modname, + .pm = &hid_sensor_pm_ops, + }, + .probe = hid_hinge_probe, + .remove = hid_hinge_remove, +}; +module_platform_driver(hid_hinge_platform_driver); + +module_description("hid sensor intel hinge"); +module_author("ye xiang <xiang.ye@intel.com>"); +module_license("gpl");
|
Industrial I/O (iio)
|
660987e1250334dd944aab0421144b541675d5d1
|
ye xiang
|
drivers
|
iio
|
common, hid-sensors, position
|
iio: imu: inv_mpu6050: add support for mpu-6880
|
mpu-6880 seems to be very similar to mpu-6500 and it works fine with some minor additions for the mpu6050 driver.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for mpu-6880
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['imu', 'inv_mpu6050']
|
['h', 'kconfig', 'c']
| 5
| 25
| 4
|
--- diff --git a/drivers/iio/imu/inv_mpu6050/kconfig b/drivers/iio/imu/inv_mpu6050/kconfig --- a/drivers/iio/imu/inv_mpu6050/kconfig +++ b/drivers/iio/imu/inv_mpu6050/kconfig - mpu6500/6515/9250/9255, icm20608/20609/20689, icm20602/icm20690 and - iam20680 motion tracking devices over i2c. + mpu6500/6515/6880/9250/9255, icm20608/20609/20689, icm20602/icm20690 + and iam20680 motion tracking devices over i2c. - mpu6500/6515/9250/9255, icm20608/20609/20689, icm20602/icm20690 and - iam20680 motion tracking devices over spi. + mpu6500/6515/6880/9250/9255, icm20608/20609/20689, icm20602/icm20690 + and iam20680 motion tracking devices over spi. diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c + { + .whoami = inv_mpu6880_whoami_value, + .name = "mpu6880", + .reg = ®_set_6500, + .config = &chip_config_6500, + .fifo_size = 4096, + .temp = {inv_mpu6500_temp_offset, inv_mpu6500_temp_scale}, + }, + case inv_mpu6880: diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_i2c.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_i2c.c --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_i2c.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_i2c.c + {"mpu6880", inv_mpu6880}, + { + .compatible = "invensense,mpu6880", + .data = (void *)inv_mpu6880 + }, diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h b/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h + inv_mpu6880, +#define inv_mpu6880_whoami_value 0x78 diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_spi.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_spi.c --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_spi.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_spi.c + {"mpu6880", inv_mpu6880}, + { + .compatible = "invensense,mpu6880", + .data = (void *)inv_mpu6880 + },
|
Industrial I/O (iio)
|
4df685091dfe27ff557031f8429906fb5d8240ea
|
stephan gerhold
|
drivers
|
iio
|
imu, inv_mpu6050
|
iio:light:apds9960 add detection for mshw0184 acpi device in apds9960 driver
|
the device is used in the microsoft surface book 3 and surface pro 7
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
light:apds9960 add detection for mshw0184 acpi device in apds9960 driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['c']
| 1
| 8
| 0
|
--- diff --git a/drivers/iio/light/apds9960.c b/drivers/iio/light/apds9960.c --- a/drivers/iio/light/apds9960.c +++ b/drivers/iio/light/apds9960.c +#include <linux/acpi.h> +static const struct acpi_device_id apds9960_acpi_match[] = { + { "mshw0184" }, + { } +}; +module_device_table(acpi, apds9960_acpi_match); + + .acpi_match_table = apds9960_acpi_match,
|
Industrial I/O (iio)
|
b9968e16adacb9289ab5d4659e0d3201388a12db
|
max leiter matt ranostay matt ranostay konsulko com
|
drivers
|
iio
|
light
|
iio: magnetometer: add driver for yamaha yas530
|
this adds an iio magnetometer driver for the yamaha yas530 family of magnetometer/compass chips yas530, yas532 and yas533.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add driver for yamaha yas530
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['magnetometer']
|
['kconfig', 'c', 'makefile']
| 3
| 1,066
| 0
|
--- diff --git a/drivers/iio/magnetometer/kconfig b/drivers/iio/magnetometer/kconfig --- a/drivers/iio/magnetometer/kconfig +++ b/drivers/iio/magnetometer/kconfig +config yamaha_yas530 + tristate "yamaha yas530 family of 3-axis magnetometers (i2c)" + depends on i2c + select regmap_i2c + select iio_buffer + select iio_triggered_buffer + help + say y here to add support for the yamaha yas530 series of + 3-axis magnetometers. right now yas530, yas532 and yas533 are + fully supported. + + this driver can also be compiled as a module. + to compile this driver as a module, choose m here: the module + will be called yamaha-yas. + diff --git a/drivers/iio/magnetometer/makefile b/drivers/iio/magnetometer/makefile --- a/drivers/iio/magnetometer/makefile +++ b/drivers/iio/magnetometer/makefile + +obj-$(config_yamaha_yas530) += yamaha-yas530.o diff --git a/drivers/iio/magnetometer/yamaha-yas530.c b/drivers/iio/magnetometer/yamaha-yas530.c --- /dev/null +++ b/drivers/iio/magnetometer/yamaha-yas530.c +// spdx-license-identifier: gpl-2.0-only +/* + * driver for the yamaha yas magnetic sensors, often used in samsung + * mobile phones. while all are not yet handled because of lacking + * hardware, expand this driver to handle the different variants: + * + * yas530 ms-3e (2011 samsung galaxy s advance) + * yas532 ms-3r (2011 samsung galaxy s4) + * yas533 ms-3f (vivo 1633, 1707, v3, y21l) + * (yas534 is a magnetic switch, not handled) + * yas535 ms-6c + * yas536 ms-3w + * yas537 ms-3t (2015 samsung galaxy s6, note 5, xiaomi) + * yas539 ms-3s (2018 samsung galaxy a7 sm-a750fn) + * + * code functions found in the mpu3050 yas530 and yas532 drivers + * named "inv_compass" in the tegra android kernel tree. + * copyright (c) 2012 invensense corporation + * + * author: linus walleij <linus.walleij@linaro.org> + */ +#include <linux/bitfield.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/gpio/consumer.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/mod_devicetable.h> +#include <linux/mutex.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> +#include <linux/regulator/consumer.h> +#include <linux/random.h> +#include <linux/unaligned/be_byteshift.h> + +#include <linux/iio/buffer.h> +#include <linux/iio/iio.h> +#include <linux/iio/trigger_consumer.h> +#include <linux/iio/triggered_buffer.h> + +/* this register map covers yas530 and yas532 but differs in yas 537 and yas539 */ +#define yas5xx_device_id 0x80 +#define yas5xx_actuate_init_coil 0x81 +#define yas5xx_measure 0x82 +#define yas5xx_config 0x83 +#define yas5xx_measure_interval 0x84 +#define yas5xx_offset_x 0x85 /* [-31 .. 31] */ +#define yas5xx_offset_y1 0x86 /* [-31 .. 31] */ +#define yas5xx_offset_y2 0x87 /* [-31 .. 31] */ +#define yas5xx_test1 0x88 +#define yas5xx_test2 0x89 +#define yas5xx_cal 0x90 +#define yas5xx_measure_data 0xb0 + +/* bits in the yas5xx config register */ +#define yas5xx_config_inton bit(0) /* interrupt on? */ +#define yas5xx_config_inthact bit(1) /* interrupt active high? */ +#define yas5xx_config_cck_mask genmask(4, 2) +#define yas5xx_config_cck_shift 2 + +/* bits in the measure command register */ +#define yas5xx_measure_start bit(0) +#define yas5xx_measure_ldtc bit(1) +#define yas5xx_measure_fors bit(2) +#define yas5xx_measure_dlymes bit(4) + +/* bits in the measure data register */ +#define yas5xx_measure_data_busy bit(7) + +#define yas530_device_id 0x01 /* yas530 (ms-3e) */ +#define yas530_version_a 0 /* yas530 (ms-3e a) */ +#define yas530_version_b 1 /* yas530b (ms-3e b) */ +#define yas530_version_a_coef 380 +#define yas530_version_b_coef 550 +#define yas530_data_bits 12 +#define yas530_data_center bit(yas530_data_bits - 1) +#define yas530_data_overflow (bit(yas530_data_bits) - 1) + +#define yas532_device_id 0x02 /* yas532/yas533 (ms-3r/f) */ +#define yas532_version_ab 0 /* yas532/533 ab (ms-3r/f ab) */ +#define yas532_version_ac 1 /* yas532/533 ac (ms-3r/f ac) */ +#define yas532_version_ab_coef 1800 +#define yas532_version_ac_coef_x 850 +#define yas532_version_ac_coef_y1 750 +#define yas532_version_ac_coef_y2 750 +#define yas532_data_bits 13 +#define yas532_data_center bit(yas532_data_bits - 1) +#define yas532_data_overflow (bit(yas532_data_bits) - 1) +#define yas532_20degrees 390 /* looks like kelvin */ + +/* these variant ids are known from code dumps */ +#define yas537_device_id 0x07 /* yas537 (ms-3t) */ +#define yas539_device_id 0x08 /* yas539 (ms-3s) */ + +/* turn off device regulators etc after 5 seconds of inactivity */ +#define yas5xx_autosuspend_delay_ms 5000 + +struct yas5xx_calibration { + /* linearization calibration x, y1, y2 */ + s32 r[3]; + u32 f[3]; + /* temperature compensation calibration */ + s32 cx, cy1, cy2; + /* misc calibration coefficients */ + s32 a2, a3, a4, a5, a6, a7, a8, a9, k; + /* clock divider */ + u8 dck; +}; + +/** + * struct yas5xx - state container for the yas5xx driver + * @dev: parent device pointer + * @devid: device id number + * @version: device version + * @name: device name + * @calibration: calibration settings from the otp storage + * @hard_offsets: offsets for each axis measured with initcoil actuated + * @orientation: mounting matrix, flipped axis etc + * @map: regmap to access the yax5xx registers over i2c + * @regs: the vdd and vddio power regulators + * @reset: optional gpio line used for handling reset + * @lock: locks the magnetometer for exclusive use during a measurement (which + * involves several register transactions so the regmap lock is not enough) + * so that measurements get serialized in a first-come-first serve manner + * @scan: naturally aligned measurements + */ +struct yas5xx { + struct device *dev; + unsigned int devid; + unsigned int version; + char name[16]; + struct yas5xx_calibration calibration; + u8 hard_offsets[3]; + struct iio_mount_matrix orientation; + struct regmap *map; + struct regulator_bulk_data regs[2]; + struct gpio_desc *reset; + struct mutex lock; + /* + * the scanout is 4 x 32 bits in cpu endianness. + * ensure timestamp is naturally aligned + */ + struct { + s32 channels[4]; + s64 ts __aligned(8); + } scan; +}; + +/* on yas530 the x, y1 and y2 values are 12 bits */ +static u16 yas530_extract_axis(u8 *data) +{ + u16 val; + + /* + * these are the bits used in a 16bit word: + * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + * x x x x x x x x x x x x + */ + val = get_unaligned_be16(&data[0]); + val = field_get(genmask(14, 3), val); + return val; +} + +/* on yas532 the x, y1 and y2 values are 13 bits */ +static u16 yas532_extract_axis(u8 *data) +{ + u16 val; + + /* + * these are the bits used in a 16bit word: + * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + * x x x x x x x x x x x x x + */ + val = get_unaligned_be16(&data[0]); + val = field_get(genmask(14, 2), val); + return val; +} + +/** + * yas5xx_measure() - make a measure from the hardware + * @yas5xx: the device state + * @t: the raw temperature measurement + * @x: the raw x axis measurement + * @y1: the y1 axis measurement + * @y2: the y2 axis measurement + * @return: 0 on success or error code + */ +static int yas5xx_measure(struct yas5xx *yas5xx, u16 *t, u16 *x, u16 *y1, u16 *y2) +{ + unsigned int busy; + u8 data[8]; + int ret; + u16 val; + + mutex_lock(&yas5xx->lock); + ret = regmap_write(yas5xx->map, yas5xx_measure, yas5xx_measure_start); + if (ret < 0) + goto out_unlock; + + /* + * typical time to measure 1500 us, max 2000 us so wait min 500 us + * and at most 20000 us (one magnitude more than the datsheet max) + * before timeout. + */ + ret = regmap_read_poll_timeout(yas5xx->map, yas5xx_measure_data, busy, + !(busy & yas5xx_measure_data_busy), + 500, 20000); + if (ret) { + dev_err(yas5xx->dev, "timeout waiting for measurement "); + goto out_unlock; + } + + ret = regmap_bulk_read(yas5xx->map, yas5xx_measure_data, + data, sizeof(data)); + if (ret) + goto out_unlock; + + mutex_unlock(&yas5xx->lock); + + switch (yas5xx->devid) { + case yas530_device_id: + /* + * the t value is 9 bits in big endian format + * these are the bits used in a 16bit word: + * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + * x x x x x x x x x + */ + val = get_unaligned_be16(&data[0]); + val = field_get(genmask(14, 6), val); + *t = val; + *x = yas530_extract_axis(&data[2]); + *y1 = yas530_extract_axis(&data[4]); + *y2 = yas530_extract_axis(&data[6]); + break; + case yas532_device_id: + /* + * the t value is 10 bits in big endian format + * these are the bits used in a 16bit word: + * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + * x x x x x x x x x x + */ + val = get_unaligned_be16(&data[0]); + val = field_get(genmask(14, 5), val); + *t = val; + *x = yas532_extract_axis(&data[2]); + *y1 = yas532_extract_axis(&data[4]); + *y2 = yas532_extract_axis(&data[6]); + break; + default: + dev_err(yas5xx->dev, "unknown data format "); + ret = -einval; + break; + } + + return ret; + +out_unlock: + mutex_unlock(&yas5xx->lock); + return ret; +} + +static s32 yas5xx_linearize(struct yas5xx *yas5xx, u16 val, int axis) +{ + struct yas5xx_calibration *c = &yas5xx->calibration; + static const s32 yas532ac_coef[] = { + yas532_version_ac_coef_x, + yas532_version_ac_coef_y1, + yas532_version_ac_coef_y2, + }; + s32 coef; + + /* select coefficients */ + switch (yas5xx->devid) { + case yas530_device_id: + if (yas5xx->version == yas530_version_a) + coef = yas530_version_a_coef; + else + coef = yas530_version_b_coef; + break; + case yas532_device_id: + if (yas5xx->version == yas532_version_ab) + coef = yas532_version_ab_coef; + else + /* elaborate coefficients */ + coef = yas532ac_coef[axis]; + break; + default: + dev_err(yas5xx->dev, "unknown device type "); + return val; + } + /* + * linearization formula: + * + * x' = x - (3721 + 50 * f) + (xoffset - r) * c + * + * where f and r are calibration values, c is a per-device + * and sometimes per-axis coefficient. + */ + return val - (3721 + 50 * c->f[axis]) + + (yas5xx->hard_offsets[axis] - c->r[axis]) * coef; +} + +/** + * yas5xx_get_measure() - measure a sample of all axis and process + * @yas5xx: the device state + * @to: temperature out + * @xo: x axis out + * @yo: y axis out + * @zo: z axis out + * @return: 0 on success or error code + * + * returned values are in nanotesla according to some code. + */ +static int yas5xx_get_measure(struct yas5xx *yas5xx, s32 *to, s32 *xo, s32 *yo, s32 *zo) +{ + struct yas5xx_calibration *c = &yas5xx->calibration; + u16 t, x, y1, y2; + /* these are "signed x, signed y1 etc */ + s32 sx, sy1, sy2, sy, sz; + int ret; + + /* we first get raw data that needs to be translated to [x,y,z] */ + ret = yas5xx_measure(yas5xx, &t, &x, &y1, &y2); + if (ret) + return ret; + + /* do some linearization if available */ + sx = yas5xx_linearize(yas5xx, x, 0); + sy1 = yas5xx_linearize(yas5xx, y1, 1); + sy2 = yas5xx_linearize(yas5xx, y2, 2); + + /* + * temperature compensation for x, y1, y2 respectively: + * + * cx * t + * x' = x - ------ + * 100 + */ + sx = sx - (c->cx * t) / 100; + sy1 = sy1 - (c->cy1 * t) / 100; + sy2 = sy2 - (c->cy2 * t) / 100; + + /* + * break y1 and y2 into y and z, y1 and y2 are apparently encoding + * y and z. + */ + sy = sy1 - sy2; + sz = -sy1 - sy2; + + /* + * fixme: convert to celsius? just guessing this is given + * as 1/10:s of degrees so multiply by 100 to get millicentigrades. + */ + *to = t * 100; + /* + * calibrate [x,y,z] with some formulas like this: + * + * 100 * x + a_2 * y + a_3 * z + * x' = k * --------------------------- + * 10 + * + * a_4 * x + a_5 * y + a_6 * z + * y' = k * --------------------------- + * 10 + * + * a_7 * x + a_8 * y + a_9 * z + * z' = k * --------------------------- + * 10 + */ + *xo = c->k * ((100 * sx + c->a2 * sy + c->a3 * sz) / 10); + *yo = c->k * ((c->a4 * sx + c->a5 * sy + c->a6 * sz) / 10); + *zo = c->k * ((c->a7 * sx + c->a8 * sy + c->a9 * sz) / 10); + + return 0; +} + +static int yas5xx_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, + long mask) +{ + struct yas5xx *yas5xx = iio_priv(indio_dev); + s32 t, x, y, z; + int ret; + + switch (mask) { + case iio_chan_info_raw: + pm_runtime_get_sync(yas5xx->dev); + ret = yas5xx_get_measure(yas5xx, &t, &x, &y, &z); + pm_runtime_mark_last_busy(yas5xx->dev); + pm_runtime_put_autosuspend(yas5xx->dev); + if (ret) + return ret; + switch (chan->address) { + case 0: + *val = t; + break; + case 1: + *val = x; + break; + case 2: + *val = y; + break; + case 3: + *val = z; + break; + default: + dev_err(yas5xx->dev, "unknown channel "); + return -einval; + } + return iio_val_int; + case iio_chan_info_scale: + if (chan->address == 0) { + /* temperature is unscaled */ + *val = 1; + return iio_val_int; + } + /* + * the axis values are in nanotesla according to the vendor + * drivers, but is clearly in microtesla according to + * experiments. since 1 ut = 0.01 gauss, we need to divide + * by 100000000 (10^8) to get to gauss from the raw value. + */ + *val = 1; + *val2 = 100000000; + return iio_val_fractional; + default: + /* unknown request */ + return -einval; + } +} + +static void yas5xx_fill_buffer(struct iio_dev *indio_dev) +{ + struct yas5xx *yas5xx = iio_priv(indio_dev); + s32 t, x, y, z; + int ret; + + pm_runtime_get_sync(yas5xx->dev); + ret = yas5xx_get_measure(yas5xx, &t, &x, &y, &z); + pm_runtime_mark_last_busy(yas5xx->dev); + pm_runtime_put_autosuspend(yas5xx->dev); + if (ret) { + dev_err(yas5xx->dev, "error refilling buffer "); + return; + } + yas5xx->scan.channels[0] = t; + yas5xx->scan.channels[1] = x; + yas5xx->scan.channels[2] = y; + yas5xx->scan.channels[3] = z; + iio_push_to_buffers_with_timestamp(indio_dev, &yas5xx->scan, + iio_get_time_ns(indio_dev)); +} + +static irqreturn_t yas5xx_handle_trigger(int irq, void *p) +{ + const struct iio_poll_func *pf = p; + struct iio_dev *indio_dev = pf->indio_dev; + + yas5xx_fill_buffer(indio_dev); + iio_trigger_notify_done(indio_dev->trig); + + return irq_handled; +} + + +static const struct iio_mount_matrix * +yas5xx_get_mount_matrix(const struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct yas5xx *yas5xx = iio_priv(indio_dev); + + return &yas5xx->orientation; +} + +static const struct iio_chan_spec_ext_info yas5xx_ext_info[] = { + iio_mount_matrix(iio_shared_by_dir, yas5xx_get_mount_matrix), + { } +}; + +#define yas5xx_axis_channel(axis, index) \ + { \ + .type = iio_magn, \ + .modified = 1, \ + .channel2 = iio_mod_##axis, \ + .info_mask_separate = bit(iio_chan_info_raw) | \ + bit(iio_chan_info_scale), \ + .ext_info = yas5xx_ext_info, \ + .address = index, \ + .scan_index = index, \ + .scan_type = { \ + .sign = 's', \ + .realbits = 32, \ + .storagebits = 32, \ + .endianness = iio_cpu, \ + }, \ + } + +static const struct iio_chan_spec yas5xx_channels[] = { + { + .type = iio_temp, + .info_mask_separate = bit(iio_chan_info_processed), + .address = 0, + .scan_index = 0, + .scan_type = { + .sign = 'u', + .realbits = 32, + .storagebits = 32, + .endianness = iio_cpu, + }, + }, + yas5xx_axis_channel(x, 1), + yas5xx_axis_channel(y, 2), + yas5xx_axis_channel(z, 3), + iio_chan_soft_timestamp(4), +}; + +static const unsigned long yas5xx_scan_masks[] = { genmask(3, 0), 0 }; + +static const struct iio_info yas5xx_info = { + .read_raw = &yas5xx_read_raw, +}; + +static bool yas5xx_volatile_reg(struct device *dev, unsigned int reg) +{ + return reg == yas5xx_actuate_init_coil || + reg == yas5xx_measure || + (reg >= yas5xx_measure_data && reg <= yas5xx_measure_data + 8); +} + +/* todo: enable regmap cache, using mark dirty and sync at runtime resume */ +static const struct regmap_config yas5xx_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 0xff, + .volatile_reg = yas5xx_volatile_reg, +}; + +/** + * yas53x_extract_calibration() - extracts the a2-a9 and k calibration + * @data: the bitfield to use + * @c: the calibration to populate + */ +static void yas53x_extract_calibration(u8 *data, struct yas5xx_calibration *c) +{ + u64 val = get_unaligned_be64(data); + + /* + * bitfield layout for the axis calibration data, for factor + * a2 = 2 etc, k = k, c = clock divider + * + * n 7 6 5 4 3 2 1 0 + * 0 [ 2 2 2 2 2 2 3 3 ] bits 63 .. 56 + * 1 [ 3 3 4 4 4 4 4 4 ] bits 55 .. 48 + * 2 [ 5 5 5 5 5 5 6 6 ] bits 47 .. 40 + * 3 [ 6 6 6 6 7 7 7 7 ] bits 39 .. 32 + * 4 [ 7 7 7 8 8 8 8 8 ] bits 31 .. 24 + * 5 [ 8 9 9 9 9 9 9 9 ] bits 23 .. 16 + * 6 [ 9 k k k k k c c ] bits 15 .. 8 + * 7 [ c x x x x x x x ] bits 7 .. 0 + */ + c->a2 = field_get(genmask_ull(63, 58), val) - 32; + c->a3 = field_get(genmask_ull(57, 54), val) - 8; + c->a4 = field_get(genmask_ull(53, 48), val) - 32; + c->a5 = field_get(genmask_ull(47, 42), val) + 38; + c->a6 = field_get(genmask_ull(41, 36), val) - 32; + c->a7 = field_get(genmask_ull(35, 29), val) - 64; + c->a8 = field_get(genmask_ull(28, 23), val) - 32; + c->a9 = field_get(genmask_ull(22, 15), val); + c->k = field_get(genmask_ull(14, 10), val) + 10; + c->dck = field_get(genmask_ull(9, 7), val); +} + +static int yas530_get_calibration_data(struct yas5xx *yas5xx) +{ + struct yas5xx_calibration *c = &yas5xx->calibration; + u8 data[16]; + u32 val; + int ret; + + /* dummy read, first read is always wrong */ + ret = regmap_bulk_read(yas5xx->map, yas5xx_cal, data, sizeof(data)); + if (ret) + return ret; + + /* actual calibration readout */ + ret = regmap_bulk_read(yas5xx->map, yas5xx_cal, data, sizeof(data)); + if (ret) + return ret; + dev_dbg(yas5xx->dev, "calibration data: %*ph ", 14, data); + + add_device_randomness(data, sizeof(data)); + yas5xx->version = data[15] & genmask(1, 0); + + /* extract the calibration from the bitfield */ + c->cx = data[0] * 6 - 768; + c->cy1 = data[1] * 6 - 768; + c->cy2 = data[2] * 6 - 768; + yas53x_extract_calibration(&data[3], c); + + /* + * extract linearization: + * linearization layout in the 32 bits at byte 11: + * the r factors are 6 bit values where bit 5 is the sign + * + * n 7 6 5 4 3 2 1 0 + * 0 [ xx xx xx r0 r0 r0 r0 r0 ] bits 31 .. 24 + * 1 [ r0 f0 f0 r1 r1 r1 r1 r1 ] bits 23 .. 16 + * 2 [ r1 f1 f1 r2 r2 r2 r2 r2 ] bits 15 .. 8 + * 3 [ r2 f2 f2 xx xx xx xx xx ] bits 7 .. 0 + */ + val = get_unaligned_be32(&data[11]); + c->f[0] = field_get(genmask(22, 21), val); + c->f[1] = field_get(genmask(14, 13), val); + c->f[2] = field_get(genmask(6, 5), val); + c->r[0] = sign_extend32(field_get(genmask(28, 23), val), 5); + c->r[1] = sign_extend32(field_get(genmask(20, 15), val), 5); + c->r[2] = sign_extend32(field_get(genmask(12, 7), val), 5); + return 0; +} + +static int yas532_get_calibration_data(struct yas5xx *yas5xx) +{ + struct yas5xx_calibration *c = &yas5xx->calibration; + u8 data[14]; + u32 val; + int ret; + + /* dummy read, first read is always wrong */ + ret = regmap_bulk_read(yas5xx->map, yas5xx_cal, data, sizeof(data)); + if (ret) + return ret; + /* actual calibration readout */ + ret = regmap_bulk_read(yas5xx->map, yas5xx_cal, data, sizeof(data)); + if (ret) + return ret; + dev_dbg(yas5xx->dev, "calibration data: %*ph ", 14, data); + + /* sanity check, is this all zeroes? */ + if (memchr_inv(data, 0x00, 13)) { + if (!(data[13] & bit(7))) + dev_warn(yas5xx->dev, "calibration is blank! "); + } + + add_device_randomness(data, sizeof(data)); + /* only one bit of version info reserved here as far as we know */ + yas5xx->version = data[13] & bit(0); + + /* extract calibration from the bitfield */ + c->cx = data[0] * 10 - 1280; + c->cy1 = data[1] * 10 - 1280; + c->cy2 = data[2] * 10 - 1280; + yas53x_extract_calibration(&data[3], c); + /* + * extract linearization: + * linearization layout in the 32 bits at byte 10: + * the r factors are 6 bit values where bit 5 is the sign + * + * n 7 6 5 4 3 2 1 0 + * 0 [ xx r0 r0 r0 r0 r0 r0 f0 ] bits 31 .. 24 + * 1 [ f0 r1 r1 r1 r1 r1 r1 f1 ] bits 23 .. 16 + * 2 [ f1 r2 r2 r2 r2 r2 r2 f2 ] bits 15 .. 8 + * 3 [ f2 xx xx xx xx xx xx xx ] bits 7 .. 0 + */ + val = get_unaligned_be32(&data[10]); + c->f[0] = field_get(genmask(24, 23), val); + c->f[1] = field_get(genmask(16, 15), val); + c->f[2] = field_get(genmask(8, 7), val); + c->r[0] = sign_extend32(field_get(genmask(30, 25), val), 5); + c->r[1] = sign_extend32(field_get(genmask(22, 17), val), 5); + c->r[2] = sign_extend32(field_get(genmask(14, 7), val), 5); + + return 0; +} + +static void yas5xx_dump_calibration(struct yas5xx *yas5xx) +{ + struct yas5xx_calibration *c = &yas5xx->calibration; + + dev_dbg(yas5xx->dev, "f[] = [%d, %d, %d] ", + c->f[0], c->f[1], c->f[2]); + dev_dbg(yas5xx->dev, "r[] = [%d, %d, %d] ", + c->r[0], c->r[1], c->r[2]); + dev_dbg(yas5xx->dev, "cx = %d ", c->cx); + dev_dbg(yas5xx->dev, "cy1 = %d ", c->cy1); + dev_dbg(yas5xx->dev, "cy2 = %d ", c->cy2); + dev_dbg(yas5xx->dev, "a2 = %d ", c->a2); + dev_dbg(yas5xx->dev, "a3 = %d ", c->a3); + dev_dbg(yas5xx->dev, "a4 = %d ", c->a4); + dev_dbg(yas5xx->dev, "a5 = %d ", c->a5); + dev_dbg(yas5xx->dev, "a6 = %d ", c->a6); + dev_dbg(yas5xx->dev, "a7 = %d ", c->a7); + dev_dbg(yas5xx->dev, "a8 = %d ", c->a8); + dev_dbg(yas5xx->dev, "a9 = %d ", c->a9); + dev_dbg(yas5xx->dev, "k = %d ", c->k); + dev_dbg(yas5xx->dev, "dck = %d ", c->dck); +} + +static int yas5xx_set_offsets(struct yas5xx *yas5xx, s8 ox, s8 oy1, s8 oy2) +{ + int ret; + + ret = regmap_write(yas5xx->map, yas5xx_offset_x, ox); + if (ret) + return ret; + ret = regmap_write(yas5xx->map, yas5xx_offset_y1, oy1); + if (ret) + return ret; + return regmap_write(yas5xx->map, yas5xx_offset_y2, oy2); +} + +static s8 yas5xx_adjust_offset(s8 old, int bit, u16 center, u16 measure) +{ + if (measure > center) + return old + bit(bit); + if (measure < center) + return old - bit(bit); + return old; +} + +static int yas5xx_meaure_offsets(struct yas5xx *yas5xx) +{ + int ret; + u16 center; + u16 t, x, y1, y2; + s8 ox, oy1, oy2; + int i; + + /* actuate the init coil and measure offsets */ + ret = regmap_write(yas5xx->map, yas5xx_actuate_init_coil, 0); + if (ret) + return ret; + + /* when the initcoil is active this should be around the center */ + switch (yas5xx->devid) { + case yas530_device_id: + center = yas530_data_center; + break; + case yas532_device_id: + center = yas532_data_center; + break; + default: + dev_err(yas5xx->dev, "unknown device type "); + return -einval; + } + + /* + * we set offsets in the interval +-31 by iterating + * +-16, +-8, +-4, +-2, +-1 adjusting the offsets each + * time, then writing the final offsets into the + * registers. + * + * note: these offsets are not in the same unit or magnitude + * as the values for [x, y1, y2]. the value is +/-31 + * but the effect on the raw values is much larger. + * the effect of the offset is to bring the measure + * rougly to the center. + */ + ox = 0; + oy1 = 0; + oy2 = 0; + + for (i = 4; i >= 0; i--) { + ret = yas5xx_set_offsets(yas5xx, ox, oy1, oy2); + if (ret) + return ret; + + ret = yas5xx_measure(yas5xx, &t, &x, &y1, &y2); + if (ret) + return ret; + dev_dbg(yas5xx->dev, "measurement %d: x=%d, y1=%d, y2=%d ", + 5-i, x, y1, y2); + + ox = yas5xx_adjust_offset(ox, i, center, x); + oy1 = yas5xx_adjust_offset(oy1, i, center, y1); + oy2 = yas5xx_adjust_offset(oy2, i, center, y2); + } + + /* needed for calibration algorithm */ + yas5xx->hard_offsets[0] = ox; + yas5xx->hard_offsets[1] = oy1; + yas5xx->hard_offsets[2] = oy2; + ret = yas5xx_set_offsets(yas5xx, ox, oy1, oy2); + if (ret) + return ret; + + dev_info(yas5xx->dev, "discovered hard offsets: x=%d, y1=%d, y2=%d ", + ox, oy1, oy2); + return 0; +} + +static int yas5xx_power_on(struct yas5xx *yas5xx) +{ + unsigned int val; + int ret; + + /* zero the test registers */ + ret = regmap_write(yas5xx->map, yas5xx_test1, 0); + if (ret) + return ret; + ret = regmap_write(yas5xx->map, yas5xx_test2, 0); + if (ret) + return ret; + + /* set up for no interrupts, calibrated clock divider */ + val = field_prep(yas5xx_config_cck_mask, yas5xx->calibration.dck); + ret = regmap_write(yas5xx->map, yas5xx_config, val); + if (ret) + return ret; + + /* measure interval 0 (back-to-back?) */ + return regmap_write(yas5xx->map, yas5xx_measure_interval, 0); +} + +static int yas5xx_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct iio_dev *indio_dev; + struct device *dev = &i2c->dev; + struct yas5xx *yas5xx; + int ret; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*yas5xx)); + if (!indio_dev) + return -enomem; + + yas5xx = iio_priv(indio_dev); + i2c_set_clientdata(i2c, indio_dev); + yas5xx->dev = dev; + mutex_init(&yas5xx->lock); + + ret = iio_read_mount_matrix(dev, "mount-matrix", &yas5xx->orientation); + if (ret) + return ret; + + yas5xx->regs[0].supply = "vdd"; + yas5xx->regs[1].supply = "iovdd"; + ret = devm_regulator_bulk_get(dev, array_size(yas5xx->regs), + yas5xx->regs); + if (ret) + return dev_err_probe(dev, ret, "cannot get regulators "); + + ret = regulator_bulk_enable(array_size(yas5xx->regs), yas5xx->regs); + if (ret) { + dev_err(dev, "cannot enable regulators "); + return ret; + } + + /* see comment in runtime resume callback */ + usleep_range(31000, 40000); + + /* this will take the device out of reset if need be */ + yas5xx->reset = devm_gpiod_get_optional(dev, "reset", gpiod_out_low); + if (is_err(yas5xx->reset)) { + ret = dev_err_probe(dev, ptr_err(yas5xx->reset), + "failed to get reset line "); + goto reg_off; + } + + yas5xx->map = devm_regmap_init_i2c(i2c, &yas5xx_regmap_config); + if (is_err(yas5xx->map)) { + dev_err(dev, "failed to allocate register map "); + ret = ptr_err(yas5xx->map); + goto assert_reset; + } + + ret = regmap_read(yas5xx->map, yas5xx_device_id, &yas5xx->devid); + if (ret) + goto assert_reset; + + switch (yas5xx->devid) { + case yas530_device_id: + ret = yas530_get_calibration_data(yas5xx); + if (ret) + goto assert_reset; + dev_info(dev, "detected yas530 ms-3e %s", + yas5xx->version ? "b" : "a"); + strncpy(yas5xx->name, "yas530", sizeof(yas5xx->name)); + break; + case yas532_device_id: + ret = yas532_get_calibration_data(yas5xx); + if (ret) + goto assert_reset; + dev_info(dev, "detected yas532/yas533 ms-3r/f %s", + yas5xx->version ? "ac" : "ab"); + strncpy(yas5xx->name, "yas532", sizeof(yas5xx->name)); + break; + default: + dev_err(dev, "unhandled device id %02x ", yas5xx->devid); + goto assert_reset; + } + + yas5xx_dump_calibration(yas5xx); + ret = yas5xx_power_on(yas5xx); + if (ret) + goto assert_reset; + ret = yas5xx_meaure_offsets(yas5xx); + if (ret) + goto assert_reset; + + indio_dev->info = &yas5xx_info; + indio_dev->available_scan_masks = yas5xx_scan_masks; + indio_dev->modes = indio_direct_mode; + indio_dev->name = yas5xx->name; + indio_dev->channels = yas5xx_channels; + indio_dev->num_channels = array_size(yas5xx_channels); + + ret = iio_triggered_buffer_setup(indio_dev, null, + yas5xx_handle_trigger, + null); + if (ret) { + dev_err(dev, "triggered buffer setup failed "); + goto assert_reset; + } + + ret = iio_device_register(indio_dev); + if (ret) { + dev_err(dev, "device register failed "); + goto cleanup_buffer; + } + + /* take runtime pm online */ + pm_runtime_get_noresume(dev); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + + pm_runtime_set_autosuspend_delay(dev, yas5xx_autosuspend_delay_ms); + pm_runtime_use_autosuspend(dev); + pm_runtime_put(dev); + + return 0; + +cleanup_buffer: + iio_triggered_buffer_cleanup(indio_dev); +assert_reset: + gpiod_set_value_cansleep(yas5xx->reset, 1); +reg_off: + regulator_bulk_disable(array_size(yas5xx->regs), yas5xx->regs); + + return ret; +} + +static int yas5xx_remove(struct i2c_client *i2c) +{ + struct iio_dev *indio_dev = i2c_get_clientdata(i2c); + struct yas5xx *yas5xx = iio_priv(indio_dev); + struct device *dev = &i2c->dev; + + iio_device_unregister(indio_dev); + iio_triggered_buffer_cleanup(indio_dev); + /* + * now we can't get any more reads from the device, which would + * also call pm_runtime* functions and race with our disable + * code. disable pm runtime in orderly fashion and power down. + */ + pm_runtime_get_sync(dev); + pm_runtime_put_noidle(dev); + pm_runtime_disable(dev); + gpiod_set_value_cansleep(yas5xx->reset, 1); + regulator_bulk_disable(array_size(yas5xx->regs), yas5xx->regs); + + return 0; +} + +static int __maybe_unused yas5xx_runtime_suspend(struct device *dev) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct yas5xx *yas5xx = iio_priv(indio_dev); + + gpiod_set_value_cansleep(yas5xx->reset, 1); + regulator_bulk_disable(array_size(yas5xx->regs), yas5xx->regs); + + return 0; +} + +static int __maybe_unused yas5xx_runtime_resume(struct device *dev) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct yas5xx *yas5xx = iio_priv(indio_dev); + int ret; + + ret = regulator_bulk_enable(array_size(yas5xx->regs), yas5xx->regs); + if (ret) { + dev_err(dev, "cannot enable regulators "); + return ret; + } + + /* + * the yas530 datasheet says tvskw is up to 30 ms, after that 1 ms + * for all voltages to settle. the yas532 is 10ms then 4ms for the + * i2c to come online. let's keep it safe and put this at 31ms. + */ + usleep_range(31000, 40000); + gpiod_set_value_cansleep(yas5xx->reset, 0); + + ret = yas5xx_power_on(yas5xx); + if (ret) { + dev_err(dev, "cannot power on "); + goto out_reset; + } + + return 0; + +out_reset: + gpiod_set_value_cansleep(yas5xx->reset, 1); + regulator_bulk_disable(array_size(yas5xx->regs), yas5xx->regs); + + return ret; +} + +static const struct dev_pm_ops yas5xx_dev_pm_ops = { + set_system_sleep_pm_ops(pm_runtime_force_suspend, + pm_runtime_force_resume) + set_runtime_pm_ops(yas5xx_runtime_suspend, + yas5xx_runtime_resume, null) +}; + +static const struct i2c_device_id yas5xx_id[] = { + {"yas530", }, + {"yas532", }, + {"yas533", }, + {} +}; +module_device_table(i2c, yas5xx_id); + +static const struct of_device_id yas5xx_of_match[] = { + { .compatible = "yamaha,yas530", }, + { .compatible = "yamaha,yas532", }, + { .compatible = "yamaha,yas533", }, + {} +}; +module_device_table(of, yas5xx_of_match); + +static struct i2c_driver yas5xx_driver = { + .driver = { + .name = "yas5xx", + .of_match_table = yas5xx_of_match, + .pm = &yas5xx_dev_pm_ops, + }, + .probe = yas5xx_probe, + .remove = yas5xx_remove, + .id_table = yas5xx_id, +}; +module_i2c_driver(yas5xx_driver); + +module_description("yamaha yas53x 3-axis magnetometer driver"); +module_author("linus walleij"); +module_license("gpl v2");
|
Industrial I/O (iio)
|
de8860b1ed4701ea7e6f760f02d79ca6a3b656a1
|
linus walleij
|
drivers
|
iio
|
magnetometer
|
iio: magnetometer: bmc150: add rudimentary regulator support
|
bmc150 needs vdd and vddio regulators that might need to be explicitly enabled. add some rudimentary support to obtain and enable these regulators during probe() and disable them during remove() or on the error path.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add rudimentary regulator support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['magnetometer', 'bmc150']
|
['c']
| 1
| 25
| 1
|
--- diff --git a/drivers/iio/magnetometer/bmc150_magn.c b/drivers/iio/magnetometer/bmc150_magn.c --- a/drivers/iio/magnetometer/bmc150_magn.c +++ b/drivers/iio/magnetometer/bmc150_magn.c +#include <linux/regulator/consumer.h> + struct regulator_bulk_data regulators[2]; + ret = regulator_bulk_enable(array_size(data->regulators), + data->regulators); + if (ret < 0) { + dev_err(data->dev, "failed to enable regulators: %d ", ret); + return ret; + } + /* + * 3ms power-on time according to datasheet, let's better + * be safe than sorry and set this delay to 5ms. + */ + msleep(5); + - return ret; + goto err_regulator_disable; +err_regulator_disable: + regulator_bulk_disable(array_size(data->regulators), data->regulators); + data->regulators[0].supply = "vdd"; + data->regulators[1].supply = "vddio"; + ret = devm_regulator_bulk_get(dev, array_size(data->regulators), + data->regulators); + if (ret) + return dev_err_probe(dev, ret, "failed to get regulators "); + + regulator_bulk_disable(array_size(data->regulators), data->regulators);
|
Industrial I/O (iio)
|
cce4f160ea809e906bb5bfaf0b03664cca08cdb1
|
stephan gerhold linus walleij linus walleij linaro org
|
drivers
|
iio
|
magnetometer
|
iio:pressure:ms5637: add ms5803 support
|
the ms5803 is very similar to the ms5805 but has less resolution options and has the 128bit prom layout.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add ms5803 support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['pressure:ms5637']
|
['yaml', 'c']
| 2
| 10
| 0
|
--- diff --git a/documentation/devicetree/bindings/trivial-devices.yaml b/documentation/devicetree/bindings/trivial-devices.yaml --- a/documentation/devicetree/bindings/trivial-devices.yaml +++ b/documentation/devicetree/bindings/trivial-devices.yaml - meas,ms5637 + - meas,ms5803 + # measurement specialities i2c pressure and temperature sensor - meas,ms5805 - meas,ms5837 diff --git a/drivers/iio/pressure/ms5637.c b/drivers/iio/pressure/ms5637.c --- a/drivers/iio/pressure/ms5637.c +++ b/drivers/iio/pressure/ms5637.c +static const struct ms_tp_hw_data ms5803_hw_data = { + .prom_len = 8, + .max_res_index = 4 +}; + +static const struct ms_tp_data ms5803_data = { .name = "ms5803", .hw = &ms5803_hw_data }; + + { .compatible = "meas,ms5803", .data = &ms5803_data },
|
Industrial I/O (iio)
|
649ef114a0a05541f9241442fa6b9c9bef457bb4
|
alexandre belloni rob herring robh kernel org
|
documentation
|
devicetree
|
bindings, pressure
|
iio: xilinx-xadc: add basic support for ultrascale system monitor
|
the xilinx-xadc iio driver currently has support for the xadc in the xilinx 7 series fpgas. the system-monitor is the equivalent to the xadc in the xilinx ultrascale and ultrascale+ fpgas.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add basic support for ultrascale system monitor
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['xilinx-xadc']
|
['h', 'kconfig', 'c']
| 4
| 171
| 58
|
--- diff --git a/drivers/iio/adc/kconfig b/drivers/iio/adc/kconfig --- a/drivers/iio/adc/kconfig +++ b/drivers/iio/adc/kconfig - say yes here to have support for the xilinx xadc. the driver does support - both the zynq interface to the xadc as well as the axi-xadc interface. + say yes here to have support for the xilinx 7 series xadc or + ultrascale/ultrascale+ system management wizard. + + for the 7 series the driver does support both the zynq interface + to the xadc as well as the axi-xadc interface. + + the driver also support the xilinx system management wizard ip core + that can be used to access the system monitor adc on the xilinx + ultrascale and ultrascale+ fpgas. diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c --- a/drivers/iio/adc/xilinx-xadc-core.c +++ b/drivers/iio/adc/xilinx-xadc-core.c -#define xadc_axi_adc_reg_offset 0x200 + +/* 7 series */ +#define xadc_7s_axi_adc_reg_offset 0x200 + +/* ultrascale */ +#define xadc_us_axi_adc_reg_offset 0x400 + .type = xadc_type_s7, +}; + +static const unsigned int xadc_axi_reg_offsets[] = { + [xadc_type_s7] = xadc_7s_axi_adc_reg_offset, + [xadc_type_us] = xadc_us_axi_adc_reg_offset, - xadc_read_reg(xadc, xadc_axi_adc_reg_offset + reg * 4, &val32); + xadc_read_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4, + &val32); - xadc_write_reg(xadc, xadc_axi_adc_reg_offset + reg * 4, val); + xadc_write_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4, + val); -static const struct xadc_ops xadc_axi_ops = { +static const struct xadc_ops xadc_7s_axi_ops = { + .type = xadc_type_s7, +}; + +static const struct xadc_ops xadc_us_axi_ops = { + .read = xadc_axi_read_adc_reg, + .write = xadc_axi_write_adc_reg, + .setup = xadc_axi_setup, + .get_dclk_rate = xadc_axi_get_dclk, + .update_alarm = xadc_axi_update_alarm, + .interrupt_handler = xadc_axi_interrupt_handler, + .flags = xadc_flags_buffered, + .type = xadc_type_us, + /* + * as per datasheet the power-down bits are don't care in the + * ultrascale, but as per reality setting the power-down bit for the + * non-existing adc-b powers down the main adc, so just return and don't + * do anything. + */ + if (xadc->ops->type == xadc_type_us) + return 0; + + /* ultrascale has only one adc and supports only continuous mode */ + if (xadc->ops->type == xadc_type_us) + return xadc_conf1_seq_continuous; + + unsigned int bits = chan->scan_type.realbits; - val16 >>= 4; + val16 >>= chan->scan_type.shift; - *val = sign_extend32(val16, 11); + *val = sign_extend32(val16, bits - 1); - /* v = (val * 3.0) / 4096 */ + /* v = (val * 3.0) / 2**bits */ - *val2 = 12; + *val2 = chan->scan_type.realbits; - /* temp in c = (val * 503.975) / 4096 - 273.15 */ + /* temp in c = (val * 503.975) / 2**bits - 273.15 */ - *val2 = 12; + *val2 = bits; - *val = -((273150 << 12) / 503975); + *val = -((273150 << bits) / 503975); -#define xadc_chan_temp(_chan, _scan_index, _addr) { \ +#define xadc_chan_temp(_chan, _scan_index, _addr, _bits) { \ - .realbits = 12, \ + .realbits = (_bits), \ - .shift = 4, \ + .shift = 16 - (_bits), \ -#define xadc_chan_voltage(_chan, _scan_index, _addr, _ext, _alarm) { \ +#define xadc_chan_voltage(_chan, _scan_index, _addr, _bits, _ext, _alarm) { \ - .realbits = 12, \ + .realbits = (_bits), \ - .shift = 4, \ + .shift = 16 - (_bits), \ -static const struct iio_chan_spec xadc_channels[] = { - xadc_chan_temp(0, 8, xadc_reg_temp), - xadc_chan_voltage(0, 9, xadc_reg_vccint, "vccint", true), - xadc_chan_voltage(1, 10, xadc_reg_vccaux, "vccaux", true), - xadc_chan_voltage(2, 14, xadc_reg_vccbram, "vccbram", true), - xadc_chan_voltage(3, 5, xadc_reg_vccpint, "vccpint", true), - xadc_chan_voltage(4, 6, xadc_reg_vccpaux, "vccpaux", true), - xadc_chan_voltage(5, 7, xadc_reg_vcco_ddr, "vccoddr", true), - xadc_chan_voltage(6, 12, xadc_reg_vrefp, "vrefp", false), - xadc_chan_voltage(7, 13, xadc_reg_vrefn, "vrefn", false), - xadc_chan_voltage(8, 11, xadc_reg_vpvn, null, false), - xadc_chan_voltage(9, 16, xadc_reg_vaux(0), null, false), - xadc_chan_voltage(10, 17, xadc_reg_vaux(1), null, false), - xadc_chan_voltage(11, 18, xadc_reg_vaux(2), null, false), - xadc_chan_voltage(12, 19, xadc_reg_vaux(3), null, false), - xadc_chan_voltage(13, 20, xadc_reg_vaux(4), null, false), - xadc_chan_voltage(14, 21, xadc_reg_vaux(5), null, false), - xadc_chan_voltage(15, 22, xadc_reg_vaux(6), null, false), - xadc_chan_voltage(16, 23, xadc_reg_vaux(7), null, false), - xadc_chan_voltage(17, 24, xadc_reg_vaux(8), null, false), - xadc_chan_voltage(18, 25, xadc_reg_vaux(9), null, false), - xadc_chan_voltage(19, 26, xadc_reg_vaux(10), null, false), - xadc_chan_voltage(20, 27, xadc_reg_vaux(11), null, false), - xadc_chan_voltage(21, 28, xadc_reg_vaux(12), null, false), - xadc_chan_voltage(22, 29, xadc_reg_vaux(13), null, false), - xadc_chan_voltage(23, 30, xadc_reg_vaux(14), null, false), - xadc_chan_voltage(24, 31, xadc_reg_vaux(15), null, false), +/* 7 series */ +#define xadc_7s_chan_temp(_chan, _scan_index, _addr) \ + xadc_chan_temp(_chan, _scan_index, _addr, 12) +#define xadc_7s_chan_voltage(_chan, _scan_index, _addr, _ext, _alarm) \ + xadc_chan_voltage(_chan, _scan_index, _addr, 12, _ext, _alarm) + +static const struct iio_chan_spec xadc_7s_channels[] = { + xadc_7s_chan_temp(0, 8, xadc_reg_temp), + xadc_7s_chan_voltage(0, 9, xadc_reg_vccint, "vccint", true), + xadc_7s_chan_voltage(1, 10, xadc_reg_vccaux, "vccaux", true), + xadc_7s_chan_voltage(2, 14, xadc_reg_vccbram, "vccbram", true), + xadc_7s_chan_voltage(3, 5, xadc_reg_vccpint, "vccpint", true), + xadc_7s_chan_voltage(4, 6, xadc_reg_vccpaux, "vccpaux", true), + xadc_7s_chan_voltage(5, 7, xadc_reg_vcco_ddr, "vccoddr", true), + xadc_7s_chan_voltage(6, 12, xadc_reg_vrefp, "vrefp", false), + xadc_7s_chan_voltage(7, 13, xadc_reg_vrefn, "vrefn", false), + xadc_7s_chan_voltage(8, 11, xadc_reg_vpvn, null, false), + xadc_7s_chan_voltage(9, 16, xadc_reg_vaux(0), null, false), + xadc_7s_chan_voltage(10, 17, xadc_reg_vaux(1), null, false), + xadc_7s_chan_voltage(11, 18, xadc_reg_vaux(2), null, false), + xadc_7s_chan_voltage(12, 19, xadc_reg_vaux(3), null, false), + xadc_7s_chan_voltage(13, 20, xadc_reg_vaux(4), null, false), + xadc_7s_chan_voltage(14, 21, xadc_reg_vaux(5), null, false), + xadc_7s_chan_voltage(15, 22, xadc_reg_vaux(6), null, false), + xadc_7s_chan_voltage(16, 23, xadc_reg_vaux(7), null, false), + xadc_7s_chan_voltage(17, 24, xadc_reg_vaux(8), null, false), + xadc_7s_chan_voltage(18, 25, xadc_reg_vaux(9), null, false), + xadc_7s_chan_voltage(19, 26, xadc_reg_vaux(10), null, false), + xadc_7s_chan_voltage(20, 27, xadc_reg_vaux(11), null, false), + xadc_7s_chan_voltage(21, 28, xadc_reg_vaux(12), null, false), + xadc_7s_chan_voltage(22, 29, xadc_reg_vaux(13), null, false), + xadc_7s_chan_voltage(23, 30, xadc_reg_vaux(14), null, false), + xadc_7s_chan_voltage(24, 31, xadc_reg_vaux(15), null, false), +}; + +/* ultrascale */ +#define xadc_us_chan_temp(_chan, _scan_index, _addr) \ + xadc_chan_temp(_chan, _scan_index, _addr, 10) +#define xadc_us_chan_voltage(_chan, _scan_index, _addr, _ext, _alarm) \ + xadc_chan_voltage(_chan, _scan_index, _addr, 10, _ext, _alarm) + +static const struct iio_chan_spec xadc_us_channels[] = { + xadc_us_chan_temp(0, 8, xadc_reg_temp), + xadc_us_chan_voltage(0, 9, xadc_reg_vccint, "vccint", true), + xadc_us_chan_voltage(1, 10, xadc_reg_vccaux, "vccaux", true), + xadc_us_chan_voltage(2, 14, xadc_reg_vccbram, "vccbram", true), + xadc_us_chan_voltage(3, 5, xadc_reg_vccpint, "vccpsintlp", true), + xadc_us_chan_voltage(4, 6, xadc_reg_vccpaux, "vccpsintfp", true), + xadc_us_chan_voltage(5, 7, xadc_reg_vcco_ddr, "vccpsaux", true), + xadc_us_chan_voltage(6, 12, xadc_reg_vrefp, "vrefp", false), + xadc_us_chan_voltage(7, 13, xadc_reg_vrefn, "vrefn", false), + xadc_us_chan_voltage(8, 11, xadc_reg_vpvn, null, false), + xadc_us_chan_voltage(9, 16, xadc_reg_vaux(0), null, false), + xadc_us_chan_voltage(10, 17, xadc_reg_vaux(1), null, false), + xadc_us_chan_voltage(11, 18, xadc_reg_vaux(2), null, false), + xadc_us_chan_voltage(12, 19, xadc_reg_vaux(3), null, false), + xadc_us_chan_voltage(13, 20, xadc_reg_vaux(4), null, false), + xadc_us_chan_voltage(14, 21, xadc_reg_vaux(5), null, false), + xadc_us_chan_voltage(15, 22, xadc_reg_vaux(6), null, false), + xadc_us_chan_voltage(16, 23, xadc_reg_vaux(7), null, false), + xadc_us_chan_voltage(17, 24, xadc_reg_vaux(8), null, false), + xadc_us_chan_voltage(18, 25, xadc_reg_vaux(9), null, false), + xadc_us_chan_voltage(19, 26, xadc_reg_vaux(10), null, false), + xadc_us_chan_voltage(20, 27, xadc_reg_vaux(11), null, false), + xadc_us_chan_voltage(21, 28, xadc_reg_vaux(12), null, false), + xadc_us_chan_voltage(22, 29, xadc_reg_vaux(13), null, false), + xadc_us_chan_voltage(23, 30, xadc_reg_vaux(14), null, false), + xadc_us_chan_voltage(24, 31, xadc_reg_vaux(15), null, false), - { .compatible = "xlnx,zynq-xadc-1.00.a", (void *)&xadc_zynq_ops }, - { .compatible = "xlnx,axi-xadc-1.00.a", (void *)&xadc_axi_ops }, + { + .compatible = "xlnx,zynq-xadc-1.00.a", + .data = &xadc_zynq_ops + }, { + .compatible = "xlnx,axi-xadc-1.00.a", + .data = &xadc_7s_axi_ops + }, { + .compatible = "xlnx,system-management-wiz-1.3", + .data = &xadc_us_axi_ops + }, + const struct iio_chan_spec *channel_templates; + unsigned int max_channels; - - channels = devm_kmemdup(dev, xadc_channels, - sizeof(xadc_channels), gfp_kernel); + if (xadc->ops->type == xadc_type_s7) { + channel_templates = xadc_7s_channels; + max_channels = array_size(xadc_7s_channels); + } else { + channel_templates = xadc_us_channels; + max_channels = array_size(xadc_us_channels); + } + channels = devm_kmemdup(dev, channel_templates, + sizeof(channels[0]) * max_channels, gfp_kernel); - if (num_channels >= array_size(xadc_channels)) { + if (num_channels >= max_channels) { +static const char * const xadc_type_names[] = { + [xadc_type_s7] = "xadc", + [xadc_type_us] = "xilinx-system-monitor", +}; + - indio_dev->name = "xadc"; + indio_dev->name = xadc_type_names[xadc->ops->type]; diff --git a/drivers/iio/adc/xilinx-xadc-events.c b/drivers/iio/adc/xilinx-xadc-events.c --- a/drivers/iio/adc/xilinx-xadc-events.c +++ b/drivers/iio/adc/xilinx-xadc-events.c -/* register value is msb aligned, the lower 4 bits are ignored */ -#define xadc_threshold_value_shift 4 - - *val >>= xadc_threshold_value_shift; + /* msb aligned */ + *val >>= 16 - chan->scan_type.realbits; - val <<= xadc_threshold_value_shift; + /* msb aligned */ + val <<= 16 - chan->scan_type.realbits; diff --git a/drivers/iio/adc/xilinx-xadc.h b/drivers/iio/adc/xilinx-xadc.h --- a/drivers/iio/adc/xilinx-xadc.h +++ b/drivers/iio/adc/xilinx-xadc.h +enum xadc_type { + xadc_type_s7, /* series 7 */ + xadc_type_us, /* ultrascale and ultrascale+ */ +}; + + enum xadc_type type;
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Industrial I/O (iio)
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c2b7720a7905bb8aa3a9decbf135fec98faba38d
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lars peter clausen
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drivers
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iio
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adc
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mfd: add driver for embedded controller found on acer iconia tab a500
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acer iconia tab a500 is an android tablet device, it has ene kb930 embedded controller which provides battery-gauge, led, gpio and some other functions. the ec uses firmware that is specifically customized for acer a500. this patch adds mfd driver for the embedded controller which allows to power-off / reboot the a500 device, it also provides a common register read/write api that will be used by the sub-devices.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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add driver for embedded controller found on acer iconia tab a500
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
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[]
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['kconfig', 'c', 'makefile']
| 3
| 214
| 0
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--- diff --git a/drivers/mfd/kconfig b/drivers/mfd/kconfig --- a/drivers/mfd/kconfig +++ b/drivers/mfd/kconfig +config mfd_acer_a500_ec + tristate "support for acer iconia tab a500 embedded controller" + depends on i2c + depends on (arch_tegra_2x_soc && of) || compile_test + select mfd_core + select regmap + help + support for embedded controller found on acer iconia tab a500. + the controller itself is ene kb930, it is running firmware + customized for the specific needs of the acer a500 hardware. + diff --git a/drivers/mfd/makefile b/drivers/mfd/makefile --- a/drivers/mfd/makefile +++ b/drivers/mfd/makefile +obj-$(config_mfd_acer_a500_ec) += acer-ec-a500.o diff --git a/drivers/mfd/acer-ec-a500.c b/drivers/mfd/acer-ec-a500.c --- /dev/null +++ b/drivers/mfd/acer-ec-a500.c +// spdx-license-identifier: gpl-2.0+ +/* + * acer iconia tab a500 embedded controller driver + * + * copyright 2020 grate-driver project + */ + +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/mfd/core.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/reboot.h> +#include <linux/regmap.h> + +#define a500_ec_i2c_err_timeout 500 +#define a500_ec_power_cmd_timeout 1000 + +/* + * controller's firmware expects specific command opcodes to be used for the + * corresponding registers. unsupported commands are skipped by the firmware. + */ +#define cmd_shutdown 0x0 +#define cmd_warm_reboot 0x0 +#define cmd_cold_reboot 0x1 + +enum { + reg_current_now = 0x03, + reg_shutdown = 0x52, + reg_warm_reboot = 0x54, + reg_cold_reboot = 0x55, +}; + +static struct i2c_client *a500_ec_client_pm_off; + +static int a500_ec_read(void *context, const void *reg_buf, size_t reg_size, + void *val_buf, size_t val_sizel) +{ + struct i2c_client *client = context; + unsigned int reg, retries = 5; + u16 *ret_val = val_buf; + s32 ret = 0; + + reg = *(u8 *)reg_buf; + + while (retries-- > 0) { + ret = i2c_smbus_read_word_data(client, reg); + if (ret >= 0) + break; + + msleep(a500_ec_i2c_err_timeout); + } + + if (ret < 0) { + dev_err(&client->dev, "read 0x%x failed: %d ", reg, ret); + return ret; + } + + *ret_val = ret; + + if (reg == reg_current_now) + fsleep(10000); + + return 0; +} + +static int a500_ec_write(void *context, const void *data, size_t count) +{ + struct i2c_client *client = context; + unsigned int reg, val, retries = 5; + s32 ret = 0; + + reg = *(u8 *)(data + 0); + val = *(u16 *)(data + 1); + + while (retries-- > 0) { + ret = i2c_smbus_write_word_data(client, reg, val); + if (ret >= 0) + break; + + msleep(a500_ec_i2c_err_timeout); + } + + if (ret < 0) { + dev_err(&client->dev, "write 0x%x failed: %d ", reg, ret); + return ret; + } + + return 0; +} + +static const struct regmap_config a500_ec_regmap_config = { + .name = "kb930", + .reg_bits = 8, + .val_bits = 16, + .max_register = 0xff, +}; + +static const struct regmap_bus a500_ec_regmap_bus = { + .reg_format_endian_default = regmap_endian_native, + .val_format_endian_default = regmap_endian_little, + .write = a500_ec_write, + .read = a500_ec_read, + .max_raw_read = 2, +}; + +static void a500_ec_poweroff(void) +{ + i2c_smbus_write_word_data(a500_ec_client_pm_off, + reg_shutdown, cmd_shutdown); + + mdelay(a500_ec_power_cmd_timeout); +} + +static int a500_ec_restart_notify(struct notifier_block *this, + unsigned long reboot_mode, void *data) +{ + if (reboot_mode == reboot_warm) + i2c_smbus_write_word_data(a500_ec_client_pm_off, + reg_warm_reboot, cmd_warm_reboot); + else + i2c_smbus_write_word_data(a500_ec_client_pm_off, + reg_cold_reboot, cmd_cold_reboot); + + mdelay(a500_ec_power_cmd_timeout); + + return notify_done; +} + +static struct notifier_block a500_ec_restart_handler = { + .notifier_call = a500_ec_restart_notify, + .priority = 200, +}; + +static const struct mfd_cell a500_ec_cells[] = { + { .name = "acer-a500-iconia-battery", }, + { .name = "acer-a500-iconia-leds", }, +}; + +static int a500_ec_probe(struct i2c_client *client) +{ + struct regmap *regmap; + int err; + + regmap = devm_regmap_init(&client->dev, &a500_ec_regmap_bus, + client, &a500_ec_regmap_config); + if (is_err(regmap)) + return ptr_err(regmap); + + err = devm_mfd_add_devices(&client->dev, platform_devid_auto, + a500_ec_cells, array_size(a500_ec_cells), + null, 0, null); + if (err) { + dev_err(&client->dev, "failed to add sub-devices: %d ", err); + return err; + } + + if (of_device_is_system_power_controller(client->dev.of_node)) { + a500_ec_client_pm_off = client; + + err = register_restart_handler(&a500_ec_restart_handler); + if (err) + return err; + + if (!pm_power_off) + pm_power_off = a500_ec_poweroff; + } + + return 0; +} + +static int a500_ec_remove(struct i2c_client *client) +{ + if (of_device_is_system_power_controller(client->dev.of_node)) { + if (pm_power_off == a500_ec_poweroff) + pm_power_off = null; + + unregister_restart_handler(&a500_ec_restart_handler); + } + + return 0; +} + +static const struct of_device_id a500_ec_match[] = { + { .compatible = "acer,a500-iconia-ec" }, + { } +}; +module_device_table(of, a500_ec_match); + +static struct i2c_driver a500_ec_driver = { + .driver = { + .name = "acer-a500-embedded-controller", + .of_match_table = a500_ec_match, + }, + .probe_new = a500_ec_probe, + .remove = a500_ec_remove, +}; +module_i2c_driver(a500_ec_driver); + +module_description("acer iconia tab a500 embedded controller driver"); +module_author("dmitry osipenko <digetx@gmail.com>"); +module_license("gpl");
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Multi Function Devices (MFD)
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92eba6802c2b1ffb30f1454e9d99ef980b94bbbf
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dmitry osipenko
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drivers
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mfd
| |
mfd: arizona: add support for acpi enumeration of wm5102 connected over spi
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the intel bay trail (x86/acpi) based lenovo yoga tablet 2 series use a wm5102 codec connected over spi.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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add support for acpi enumeration of wm5102 connected over spi
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['arizona']
|
['c']
| 1
| 127
| 0
|
--- diff --git a/drivers/mfd/arizona-spi.c b/drivers/mfd/arizona-spi.c --- a/drivers/mfd/arizona-spi.c +++ b/drivers/mfd/arizona-spi.c +#include <linux/acpi.h> +#include <linux/gpio/consumer.h> +#include <linux/gpio/machine.h> +#include <uapi/linux/input-event-codes.h> +#ifdef config_acpi +const struct acpi_gpio_params reset_gpios = { 1, 0, false }; +const struct acpi_gpio_params ldoena_gpios = { 2, 0, false }; + +static const struct acpi_gpio_mapping arizona_acpi_gpios[] = { + { "reset-gpios", &reset_gpios, 1, }, + { "wlf,ldoena-gpios", &ldoena_gpios, 1 }, + { } +}; + +/* + * the acpi resources for the device only describe external gpio-s. they do + * not provide mappings for the gpio-s coming from the arizona codec itself. + */ +static const struct gpiod_lookup arizona_soc_gpios[] = { + { "arizona", 2, "wlf,spkvdd-ena", 0, gpio_active_high }, + { "arizona", 4, "wlf,micd-pol", 0, gpio_active_low }, +}; + +/* + * the aosp 3.5 mm headset: accessory specification gives the following values: + * function a play/pause: 0 ohm + * function d voice assistant: 135 ohm + * function b volume up 240 ohm + * function c volume down 470 ohm + * minimum mic dc resistance 1000 ohm + * minimum ear speaker impedance 16 ohm + * note the first max value below must be less then the min. speaker impedance, + * to allow ctia/omtp detection to work. the other max values are the closest + * value from extcon-arizona.c:arizona_micd_levels halfway 2 button resistances. + */ +static const struct arizona_micd_range arizona_micd_aosp_ranges[] = { + { .max = 11, .key = key_playpause }, + { .max = 186, .key = key_voicecommand }, + { .max = 348, .key = key_volumeup }, + { .max = 752, .key = key_volumedown }, +}; + +static void arizona_spi_acpi_remove_lookup(void *lookup) +{ + gpiod_remove_lookup_table(lookup); +} + +static int arizona_spi_acpi_probe(struct arizona *arizona) +{ + struct gpiod_lookup_table *lookup; + acpi_status status; + int ret; + + /* add mappings for the 2 acpi declared gpios used for reset and ldo-ena */ + devm_acpi_dev_add_driver_gpios(arizona->dev, arizona_acpi_gpios); + + /* add lookups for the socs own gpios used for micdet-polarity and spkvdd-enable */ + lookup = devm_kzalloc(arizona->dev, + struct_size(lookup, table, array_size(arizona_soc_gpios) + 1), + gfp_kernel); + if (!lookup) + return -enomem; + + lookup->dev_id = dev_name(arizona->dev); + memcpy(lookup->table, arizona_soc_gpios, sizeof(arizona_soc_gpios)); + + gpiod_add_lookup_table(lookup); + ret = devm_add_action_or_reset(arizona->dev, arizona_spi_acpi_remove_lookup, lookup); + if (ret) + return ret; + + /* enable 32khz clock from soc to codec for jack-detect */ + status = acpi_evaluate_object(acpi_handle(arizona->dev), "clke", null, null); + if (acpi_failure(status)) + dev_warn(arizona->dev, "failed to enable 32khz clk acpi error %d ", status); + + /* + * some dsdts wrongly declare the irq trigger-type as irqf_trigger_falling + * the irq line will stay low when a new irq event happens between reading + * the irq status flags and acknowledging them. when the irq line stays + * low like this the irq will never trigger again when its type is set + * to irqf_trigger_falling. correct the irq trigger-type to fix this. + * + * note theoretically it is possible that some boards are not capable + * of handling active low level interrupts. in that case setting the + * flag to irqf_trigger_falling would not be a bug (and we would need + * to work around this) but so far all known usages of irqf_trigger_falling + * are a bug in the board's dsdt. + */ + arizona->pdata.irq_flags = irqf_trigger_low; + + /* wait 200 ms after jack insertion */ + arizona->pdata.micd_detect_debounce = 200; + + /* use standard aosp values for headset-button mappings */ + arizona->pdata.micd_ranges = arizona_micd_aosp_ranges; + arizona->pdata.num_micd_ranges = array_size(arizona_micd_aosp_ranges); + + return 0; +} + +static const struct acpi_device_id arizona_acpi_match[] = { + { + .id = "wm510204", + .driver_data = wm5102, + }, + { + .id = "wm510205", + .driver_data = wm5102, + }, + { } +}; +module_device_table(acpi, arizona_acpi_match); +#else +static int arizona_spi_acpi_probe(struct arizona *arizona) +{ + return -enodev; +} +#endif + + if (has_acpi_companion(&spi->dev)) { + ret = arizona_spi_acpi_probe(arizona); + if (ret) + return ret; + } + + .acpi_match_table = acpi_ptr(arizona_acpi_match),
|
Multi Function Devices (MFD)
|
e933836744a2606e6cd42a6a83e5e43da2a60788
|
hans de goede
|
drivers
|
mfd
| |
mfd: bd9571mwv: use devm_mfd_add_devices()
|
to remove mfd devices when unload this driver, should use devm_mfd_add_devices() instead.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for bd9574mwf
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['bd9571mwv']
|
['c']
| 1
| 3
| 3
|
--- diff --git a/drivers/mfd/bd9571mwv.c b/drivers/mfd/bd9571mwv.c --- a/drivers/mfd/bd9571mwv.c +++ b/drivers/mfd/bd9571mwv.c - ret = mfd_add_devices(bd->dev, platform_devid_auto, bd9571mwv_cells, - array_size(bd9571mwv_cells), null, 0, - regmap_irq_get_domain(bd->irq_data)); + ret = devm_mfd_add_devices(bd->dev, platform_devid_auto, + bd9571mwv_cells, array_size(bd9571mwv_cells), + null, 0, regmap_irq_get_domain(bd->irq_data));
|
Multi Function Devices (MFD)
|
c58ad0f2b052b5675d6394e03713ee41e721b44c
|
yoshihiro shimoda geert uytterhoeven geert renesas glider be matti vaittinen matti vaittinen fi rohmeurope com
|
drivers
|
mfd
| |
dt-bindings: mfd: bd9571mwv: document bd9574mwf
|
document other similar specification chip bd9574mwf.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for bd9574mwf
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['bd9571mwv']
|
['txt']
| 1
| 2
| 2
|
--- diff --git a/documentation/devicetree/bindings/mfd/bd9571mwv.txt b/documentation/devicetree/bindings/mfd/bd9571mwv.txt --- a/documentation/devicetree/bindings/mfd/bd9571mwv.txt +++ b/documentation/devicetree/bindings/mfd/bd9571mwv.txt -* rohm bd9571mwv power management integrated circuit (pmic) bindings +* rohm bd9571mwv/bd9574mwf power management integrated circuit (pmic) bindings - - compatible : should be "rohm,bd9571mwv". + - compatible : should be "rohm,bd9571mwv" or "rohm,bd9574mwf". - reg : i2c slave address. - interrupts : the interrupt line the device is connected to. - interrupt-controller : marks the device node as an interrupt controller.
|
Multi Function Devices (MFD)
|
e413c27e2ec8276ac0f25e7d1203f29adcfd8758
|
yoshihiro shimoda
|
documentation
|
devicetree
|
bindings, mfd
|
mfd: rohm-generic: add bd9571 and bd9574
|
add chip ids for bd9571mwv and bd9574mwf.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for bd9574mwf
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['bd9571mwv']
|
['h']
| 1
| 2
| 0
|
--- diff --git a/include/linux/mfd/rohm-generic.h b/include/linux/mfd/rohm-generic.h --- a/include/linux/mfd/rohm-generic.h +++ b/include/linux/mfd/rohm-generic.h + rohm_chip_type_bd9571, + rohm_chip_type_bd9574,
|
Multi Function Devices (MFD)
|
b0f87e8ac263e3b82ec314542cb7fb07a47fc8b7
|
yoshihiro shimoda matti vaittinen matti vaittinen fi rohmeurope com
|
include
|
linux
|
mfd
|
regulator: bd9571mwv: rid of using struct bd9571mwv
|
to simplify this driver, use dev_get_regmap() and rid of using struct bd9571mwv.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for bd9574mwf
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['bd9571mwv']
|
['c']
| 1
| 26
| 23
|
--- diff --git a/drivers/regulator/bd9571mwv-regulator.c b/drivers/regulator/bd9571mwv-regulator.c --- a/drivers/regulator/bd9571mwv-regulator.c +++ b/drivers/regulator/bd9571mwv-regulator.c - struct bd9571mwv *bd; + struct regmap *regmap; -static int bd9571mwv_bkup_mode_read(struct bd9571mwv *bd, unsigned int *mode) +static int bd9571mwv_bkup_mode_read(struct bd9571mwv_reg *bdreg, + unsigned int *mode) - ret = regmap_read(bd->regmap, bd9571mwv_bkup_mode_cnt, mode); + ret = regmap_read(bdreg->regmap, bd9571mwv_bkup_mode_cnt, mode); - dev_err(bd->dev, "failed to read backup mode (%d) ", ret); + dev_err(regmap_get_device(bdreg->regmap), + "failed to read backup mode (%d) ", ret); -static int bd9571mwv_bkup_mode_write(struct bd9571mwv *bd, unsigned int mode) +static int bd9571mwv_bkup_mode_write(struct bd9571mwv_reg *bdreg, + unsigned int mode) - ret = regmap_write(bd->regmap, bd9571mwv_bkup_mode_cnt, mode); + ret = regmap_write(bdreg->regmap, bd9571mwv_bkup_mode_cnt, mode); - dev_err(bd->dev, "failed to configure backup mode 0x%x (%d) ", + dev_err(regmap_get_device(bdreg->regmap), + "failed to configure backup mode 0x%x (%d) ", - ret = bd9571mwv_bkup_mode_read(bdreg->bd, &mode); + ret = bd9571mwv_bkup_mode_read(bdreg, &mode); - ret = bd9571mwv_bkup_mode_write(bdreg->bd, mode); + ret = bd9571mwv_bkup_mode_write(bdreg, mode); - ret = bd9571mwv_bkup_mode_read(bdreg->bd, &mode); + ret = bd9571mwv_bkup_mode_read(bdreg, &mode); - return bd9571mwv_bkup_mode_write(bdreg->bd, mode); + return bd9571mwv_bkup_mode_write(bdreg, mode); - return bd9571mwv_bkup_mode_write(bdreg->bd, bdreg->bkup_mode_cnt_saved); + return bd9571mwv_bkup_mode_write(bdreg, bdreg->bkup_mode_cnt_saved); - struct bd9571mwv *bd = dev_get_drvdata(pdev->dev.parent); - bdreg->bd = bd; + bdreg->regmap = dev_get_regmap(pdev->dev.parent, null); - config.dev->of_node = bd->dev->of_node; - config.driver_data = bd; - config.regmap = bd->regmap; + config.dev->of_node = pdev->dev.parent->of_node; + config.driver_data = bdreg; + config.regmap = bdreg->regmap; - dev_err(bd->dev, "failed to register %s regulator ", + dev_err(&pdev->dev, "failed to register %s regulator ", - of_property_read_u32(bd->dev->of_node, "rohm,ddr-backup-power", &val); + of_property_read_u32(config.dev->of_node, "rohm,ddr-backup-power", &val); - dev_err(bd->dev, "invalid %s mode %u ", + dev_err(&pdev->dev, "invalid %s mode %u ", - bdreg->rstbmode_level = of_property_read_bool(bd->dev->of_node, + bdreg->rstbmode_level = of_property_read_bool(config.dev->of_node, - bdreg->rstbmode_pulse = of_property_read_bool(bd->dev->of_node, + bdreg->rstbmode_pulse = of_property_read_bool(config.dev->of_node, - dev_err(bd->dev, "only one rohm,rstbmode-* may be specified"); + dev_err(&pdev->dev, "only one rohm,rstbmode-* may be specified");
|
Multi Function Devices (MFD)
|
30402f97f965fda9440e480f1aba6a6aba4572cd
|
yoshihiro shimoda mark brown broonie kernel org matti vaittinen matti vaittinen fi rohmeurope com
|
drivers
|
regulator
| |
gpio: bd9571mwv: use the spdx license identifier
|
use the spdx license identifier instead of a local description.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for bd9574mwf
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['bd9571mwv']
|
['c']
| 1
| 1
| 9
|
--- diff --git a/drivers/gpio/gpio-bd9571mwv.c b/drivers/gpio/gpio-bd9571mwv.c --- a/drivers/gpio/gpio-bd9571mwv.c +++ b/drivers/gpio/gpio-bd9571mwv.c +// spdx-license-identifier: gpl-2.0-only - * this program is free software; you can redistribute it and/or - * modify it under the terms of the gnu general public license version 2 as - * published by the free software foundation. - * - * this program is distributed "as is" without any warranty of any - * kind, whether expressed or implied; without even the implied warranty - * of merchantability or fitness for a particular purpose. see the - * gnu general public license version 2 for more details. - *
|
Multi Function Devices (MFD)
|
b9f71d14e570199bfd9a440db000e59780fe0fc7
|
yoshihiro shimoda bartosz golaszewski bgolaszewski baylibre com geert uytterhoeven geert renesas glider be linus walleij linus walleij linaro org
|
drivers
|
gpio
| |
gpio: bd9571mwv: rid of using struct bd9571mwv
|
to simplify this driver, use dev_get_regmap() and rid of using struct bd9571mwv.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for bd9574mwf
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['bd9571mwv']
|
['c']
| 1
| 9
| 10
|
--- diff --git a/drivers/gpio/gpio-bd9571mwv.c b/drivers/gpio/gpio-bd9571mwv.c --- a/drivers/gpio/gpio-bd9571mwv.c +++ b/drivers/gpio/gpio-bd9571mwv.c + struct regmap *regmap; - struct bd9571mwv *bd; - ret = regmap_read(gpio->bd->regmap, bd9571mwv_gpio_dir, &val); + ret = regmap_read(gpio->regmap, bd9571mwv_gpio_dir, &val); - regmap_update_bits(gpio->bd->regmap, bd9571mwv_gpio_dir, - bit(offset), 0); + regmap_update_bits(gpio->regmap, bd9571mwv_gpio_dir, bit(offset), 0); - regmap_update_bits(gpio->bd->regmap, bd9571mwv_gpio_out, + regmap_update_bits(gpio->regmap, bd9571mwv_gpio_out, - regmap_update_bits(gpio->bd->regmap, bd9571mwv_gpio_dir, + regmap_update_bits(gpio->regmap, bd9571mwv_gpio_dir, - ret = regmap_read(gpio->bd->regmap, bd9571mwv_gpio_in, &val); + ret = regmap_read(gpio->regmap, bd9571mwv_gpio_in, &val); - regmap_update_bits(gpio->bd->regmap, bd9571mwv_gpio_out, + regmap_update_bits(gpio->regmap, bd9571mwv_gpio_out, - gpio->bd = dev_get_drvdata(pdev->dev.parent); + gpio->regmap = dev_get_regmap(pdev->dev.parent, null); - gpio->chip.parent = gpio->bd->dev; + gpio->chip.parent = pdev->dev.parent;
|
Multi Function Devices (MFD)
|
2d7af444e8364965a1ba44b2c2ea1e1122b673d4
|
yoshihiro shimoda linus walleij linus walleij linaro org bartosz golaszewski bgolaszewski baylibre com matti vaittinen matti vaittinen fi rohmeurope com
|
drivers
|
gpio
| |
gpio: bd9571mwv: add bd9574mwf support
|
add support for bd9574mwf which is similar chip with bd9571mwv. note that bd9574mwf has additional features "recov_gpout", "freqsel" and "rtc_in", but supports gpio function only.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for bd9574mwf
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['bd9571mwv']
|
['c']
| 1
| 4
| 2
|
--- diff --git a/drivers/gpio/gpio-bd9571mwv.c b/drivers/gpio/gpio-bd9571mwv.c --- a/drivers/gpio/gpio-bd9571mwv.c +++ b/drivers/gpio/gpio-bd9571mwv.c - * rohm bd9571mwv-m gpio driver + * rohm bd9571mwv-m and bd9574mwf-m gpio driver +#include <linux/mfd/rohm-generic.h> - { "bd9571mwv-gpio", }, + { "bd9571mwv-gpio", rohm_chip_type_bd9571 }, + { "bd9574mwf-gpio", rohm_chip_type_bd9574 },
|
Multi Function Devices (MFD)
|
2e35627e6956e743a7e8e8d17a86dd243a6d51ef
|
yoshihiro shimoda linus walleij linus walleij linaro org bartosz golaszewski bgolaszewski baylibre com matti vaittinen matti vaittinen fi rohmeurope com
|
drivers
|
gpio
| |
mfd: bd9571mwv: use the spdx license identifier
|
use the spdx license identifier instead of a local description.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for bd9574mwf
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['bd9571mwv']
|
['h', 'c']
| 2
| 2
| 18
|
--- diff --git a/drivers/mfd/bd9571mwv.c b/drivers/mfd/bd9571mwv.c --- a/drivers/mfd/bd9571mwv.c +++ b/drivers/mfd/bd9571mwv.c +// spdx-license-identifier: gpl-2.0-only - * this program is free software; you can redistribute it and/or - * modify it under the terms of the gnu general public license version 2 as - * published by the free software foundation. - * - * this program is distributed "as is" without any warranty of any - * kind, whether expressed or implied; without even the implied warranty - * of merchantability or fitness for a particular purpose. see the - * gnu general public license version 2 for more details. - * diff --git a/include/linux/mfd/bd9571mwv.h b/include/linux/mfd/bd9571mwv.h --- a/include/linux/mfd/bd9571mwv.h +++ b/include/linux/mfd/bd9571mwv.h +/* spdx-license-identifier: gpl-2.0-only */ - * this program is free software; you can redistribute it and/or - * modify it under the terms of the gnu general public license version 2 as - * published by the free software foundation. - * - * this program is distributed "as is" without any warranty of any - * kind, whether expressed or implied; without even the implied warranty - * of merchantability or fitness for a particular purpose. see the - * gnu general public license version 2 for more details. - *
|
Multi Function Devices (MFD)
|
bfb26be7fe90186e5d9fe704cc124ab77bb7d127
|
yoshihiro shimoda geert uytterhoeven geert renesas glider be
|
include
|
linux
|
mfd
|
mfd: bd9571mwv: use devm_regmap_add_irq_chip()
|
use devm_regmap_add_irq_chip() to simplify the code.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for bd9574mwf
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['bd9571mwv']
|
['c']
| 1
| 6
| 21
|
--- diff --git a/drivers/mfd/bd9571mwv.c b/drivers/mfd/bd9571mwv.c --- a/drivers/mfd/bd9571mwv.c +++ b/drivers/mfd/bd9571mwv.c - ret = regmap_add_irq_chip(bd->regmap, bd->irq, irqf_oneshot, 0, - &bd9571mwv_irq_chip, &bd->irq_data); + ret = devm_regmap_add_irq_chip(bd->dev, bd->regmap, bd->irq, + irqf_oneshot, 0, &bd9571mwv_irq_chip, + &bd->irq_data); - ret = devm_mfd_add_devices(bd->dev, platform_devid_auto, - bd9571mwv_cells, array_size(bd9571mwv_cells), - null, 0, regmap_irq_get_domain(bd->irq_data)); - if (ret) { - regmap_del_irq_chip(bd->irq, bd->irq_data); - return ret; - } - - return 0; -} - -static int bd9571mwv_remove(struct i2c_client *client) -{ - struct bd9571mwv *bd = i2c_get_clientdata(client); - - regmap_del_irq_chip(bd->irq, bd->irq_data); - - return 0; + return devm_mfd_add_devices(bd->dev, platform_devid_auto, + bd9571mwv_cells, array_size(bd9571mwv_cells), + null, 0, regmap_irq_get_domain(bd->irq_data)); - .remove = bd9571mwv_remove,
|
Multi Function Devices (MFD)
|
1e40a92c651f4bb383df757b69821f74820b6e6a
|
yoshihiro shimoda matti vaittinen matti vaittinen fi rohmeurope com geert uytterhoeven geert renesas glider be
|
drivers
|
mfd
| |
mfd: bd9571mwv: make the driver more generic
|
since the driver supports bd9571mwv pmic only, this patch makes the functions and data structure become more generic so that it can support other pmic variants as well. also remove printing part name which lee jones suggested.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for bd9574mwf
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['bd9571mwv']
|
['h', 'c']
| 2
| 43
| 52
|
--- diff --git a/drivers/mfd/bd9571mwv.c b/drivers/mfd/bd9571mwv.c --- a/drivers/mfd/bd9571mwv.c +++ b/drivers/mfd/bd9571mwv.c + * copyright (c) 2020 renesas electronics corporation -static int bd9571mwv_identify(struct bd9571mwv *bd) +static int bd957x_identify(struct device *dev, struct regmap *regmap) - struct device *dev = bd->dev; - ret = regmap_read(bd->regmap, bd9571mwv_vendor_code, &value); + ret = regmap_read(regmap, bd9571mwv_vendor_code, &value); - ret = regmap_read(bd->regmap, bd9571mwv_product_code, &value); + ret = regmap_read(regmap, bd9571mwv_product_code, &value); - - if (value != bd9571mwv_product_code_val) { - dev_err(dev, "invalid product code id %02x (expected %02x) ", - value, bd9571mwv_product_code_val); - return -einval; - } - - ret = regmap_read(bd->regmap, bd9571mwv_product_revision, &value); + ret = regmap_read(regmap, bd9571mwv_product_revision, &value); - dev_info(dev, "device: bd9571mwv rev. %d ", value & 0xff); - - const struct i2c_device_id *ids) + const struct i2c_device_id *ids) - struct bd9571mwv *bd; - int ret; - - bd = devm_kzalloc(&client->dev, sizeof(*bd), gfp_kernel); - if (!bd) - return -enomem; + const struct regmap_config *regmap_config; + const struct regmap_irq_chip *irq_chip; + const struct mfd_cell *cells; + struct device *dev = &client->dev; + struct regmap *regmap; + struct regmap_irq_chip_data *irq_data; + int ret, num_cells, irq = client->irq; + + /* read the pmic product code */ + ret = i2c_smbus_read_byte_data(client, bd9571mwv_product_code); + if (ret < 0) { + dev_err(dev, "failed to read product code "); + return ret; + } - i2c_set_clientdata(client, bd); - bd->dev = &client->dev; - bd->irq = client->irq; + switch (ret) { + case bd9571mwv_product_code_bd9571mwv: + regmap_config = &bd9571mwv_regmap_config; + irq_chip = &bd9571mwv_irq_chip; + cells = bd9571mwv_cells; + num_cells = array_size(bd9571mwv_cells); + break; + default: + dev_err(dev, "unsupported device 0x%x ", ret); + return -enodev; + } - bd->regmap = devm_regmap_init_i2c(client, &bd9571mwv_regmap_config); - if (is_err(bd->regmap)) { - dev_err(bd->dev, "failed to initialize register map "); - return ptr_err(bd->regmap); + regmap = devm_regmap_init_i2c(client, regmap_config); + if (is_err(regmap)) { + dev_err(dev, "failed to initialize register map "); + return ptr_err(regmap); - ret = bd9571mwv_identify(bd); + ret = bd957x_identify(dev, regmap); - ret = devm_regmap_add_irq_chip(bd->dev, bd->regmap, bd->irq, - irqf_oneshot, 0, &bd9571mwv_irq_chip, - &bd->irq_data); + ret = devm_regmap_add_irq_chip(dev, regmap, irq, irqf_oneshot, 0, + irq_chip, &irq_data); - dev_err(bd->dev, "failed to register irq chip "); + dev_err(dev, "failed to register irq chip "); - return devm_mfd_add_devices(bd->dev, platform_devid_auto, - bd9571mwv_cells, array_size(bd9571mwv_cells), - null, 0, regmap_irq_get_domain(bd->irq_data)); + return devm_mfd_add_devices(dev, platform_devid_auto, cells, num_cells, + null, 0, regmap_irq_get_domain(irq_data)); diff --git a/include/linux/mfd/bd9571mwv.h b/include/linux/mfd/bd9571mwv.h --- a/include/linux/mfd/bd9571mwv.h +++ b/include/linux/mfd/bd9571mwv.h + * copyright (c) 2020 renesas electronics corporation -#define bd9571mwv_product_code_val 0x60 +#define bd9571mwv_product_code_bd9571mwv 0x60 - -/** - * struct bd9571mwv - state holder for the bd9571mwv driver - * - * device data may be used to access the bd9571mwv chip - */ -struct bd9571mwv { - struct device *dev; - struct regmap *regmap; - - /* irq data */ - int irq; - struct regmap_irq_chip_data *irq_data; -}; -
|
Multi Function Devices (MFD)
|
f16e1fd197f85a943b5880009f4aefe05a17df0d
|
khiem nguyen matti vaittinen matti vaittinen fi rohmeurope com
|
include
|
linux
|
mfd
|
mfd: bd9571mwv: add support for bd9574mwf
|
the new pmic bd9574mwf inherits features from bd9571mwv. add the support of new pmic to existing bd9571mwv driver.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for bd9574mwf
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['bd9571mwv']
|
['h', 'c']
| 2
| 89
| 4
|
--- diff --git a/drivers/mfd/bd9571mwv.c b/drivers/mfd/bd9571mwv.c --- a/drivers/mfd/bd9571mwv.c +++ b/drivers/mfd/bd9571mwv.c - * rohm bd9571mwv-m mfd driver + * rohm bd9571mwv-m and bd9574mvf-m core driver +#include <linux/mfd/rohm-generic.h> +static const struct mfd_cell bd9574mwf_cells[] = { + { .name = "bd9574mwf-regulator", }, + { .name = "bd9574mwf-gpio", }, +}; + +static const struct regmap_range bd9574mwf_readable_yes_ranges[] = { + regmap_reg_range(bd9571mwv_vendor_code, bd9571mwv_product_revision), + regmap_reg_range(bd9571mwv_bkup_mode_cnt, bd9571mwv_bkup_mode_cnt), + regmap_reg_range(bd9571mwv_dvfs_vinit, bd9571mwv_dvfs_setvmax), + regmap_reg_range(bd9571mwv_dvfs_setvid, bd9571mwv_dvfs_monivdac), + regmap_reg_range(bd9571mwv_gpio_in, bd9571mwv_gpio_in), + regmap_reg_range(bd9571mwv_gpio_int, bd9571mwv_gpio_intmask), + regmap_reg_range(bd9571mwv_int_intreq, bd9571mwv_int_intmask), +}; + +static const struct regmap_access_table bd9574mwf_readable_table = { + .yes_ranges = bd9574mwf_readable_yes_ranges, + .n_yes_ranges = array_size(bd9574mwf_readable_yes_ranges), +}; + +static const struct regmap_range bd9574mwf_writable_yes_ranges[] = { + regmap_reg_range(bd9571mwv_bkup_mode_cnt, bd9571mwv_bkup_mode_cnt), + regmap_reg_range(bd9571mwv_dvfs_setvid, bd9571mwv_dvfs_setvid), + regmap_reg_range(bd9571mwv_gpio_dir, bd9571mwv_gpio_out), + regmap_reg_range(bd9571mwv_gpio_int_set, bd9571mwv_gpio_intmask), + regmap_reg_range(bd9571mwv_int_intreq, bd9571mwv_int_intmask), +}; + +static const struct regmap_access_table bd9574mwf_writable_table = { + .yes_ranges = bd9574mwf_writable_yes_ranges, + .n_yes_ranges = array_size(bd9574mwf_writable_yes_ranges), +}; + +static const struct regmap_range bd9574mwf_volatile_yes_ranges[] = { + regmap_reg_range(bd9571mwv_dvfs_monivdac, bd9571mwv_dvfs_monivdac), + regmap_reg_range(bd9571mwv_gpio_in, bd9571mwv_gpio_in), + regmap_reg_range(bd9571mwv_gpio_int, bd9571mwv_gpio_int), + regmap_reg_range(bd9571mwv_int_intreq, bd9571mwv_int_intreq), +}; + +static const struct regmap_access_table bd9574mwf_volatile_table = { + .yes_ranges = bd9574mwf_volatile_yes_ranges, + .n_yes_ranges = array_size(bd9574mwf_volatile_yes_ranges), +}; + +static const struct regmap_config bd9574mwf_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .cache_type = regcache_rbtree, + .rd_table = &bd9574mwf_readable_table, + .wr_table = &bd9574mwf_writable_table, + .volatile_table = &bd9574mwf_volatile_table, + .max_register = 0xff, +}; + +static struct regmap_irq_chip bd9574mwf_irq_chip = { + .name = "bd9574mwf", + .status_base = bd9571mwv_int_intreq, + .mask_base = bd9571mwv_int_intmask, + .ack_base = bd9571mwv_int_intreq, + .init_ack_masked = true, + .num_regs = 1, + .irqs = bd9571mwv_irqs, + .num_irqs = array_size(bd9571mwv_irqs), +}; + + case bd9571mwv_product_code_bd9574mwf: + regmap_config = &bd9574mwf_regmap_config; + irq_chip = &bd9574mwf_irq_chip; + cells = bd9574mwf_cells; + num_cells = array_size(bd9574mwf_cells); + break; + { .compatible = "rohm,bd9574mwf", }, diff --git a/include/linux/mfd/bd9571mwv.h b/include/linux/mfd/bd9571mwv.h --- a/include/linux/mfd/bd9571mwv.h +++ b/include/linux/mfd/bd9571mwv.h - * rohm bd9571mwv-m driver + * rohm bd9571mwv-m and bd9574mwf-m driver -/* list of registers for bd9571mwv */ +/* list of registers for bd9571mwv and bd9574mwf */ +#define bd9571mwv_product_code_bd9574mwf 0x74 +#define bd9574mwf_vd09_vinit 0x51 +#define bd9574mwf_gpio_mux 0x67 +#define bd9574mwf_prot_error_status5 0x86 +#define bd9574mwf_system_error_status 0x87 +#define bd9574mwf_sscg_cnt 0xa0 +#define bd9574mwf_poffb_mrb 0xa1 +#define bd9574mwf_smrb_wr_prot 0xa2 +#define bd9574mwf_smrb_assert 0xa3 +#define bd9574mwf_smrb_status 0xa4 + - bd9571mwv_irq_128h_of, + bd9571mwv_irq_128h_of, /* bkup_hold on bd9574mwf */
|
Multi Function Devices (MFD)
|
b2548da647bb04737196ffd945505d47a166239b
|
khiem nguyen matti vaittinen matti vaittinen fi rohmeurope com
|
include
|
linux
|
mfd
|
mfd: intel-lpss: add intel alder lake pch-p pci ids
|
add intel alder lake lpss pci ids.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add intel alder lake pch-p pci ids
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel-lpss']
|
['c']
| 1
| 13
| 0
|
--- diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c --- a/drivers/mfd/intel-lpss-pci.c +++ b/drivers/mfd/intel-lpss-pci.c + /* adl-p */ + { pci_vdevice(intel, 0x51a8), (kernel_ulong_t)&bxt_uart_info }, + { pci_vdevice(intel, 0x51a9), (kernel_ulong_t)&bxt_uart_info }, + { pci_vdevice(intel, 0x51aa), (kernel_ulong_t)&bxt_info }, + { pci_vdevice(intel, 0x51ab), (kernel_ulong_t)&bxt_info }, + { pci_vdevice(intel, 0x51c5), (kernel_ulong_t)&bxt_i2c_info }, + { pci_vdevice(intel, 0x51c6), (kernel_ulong_t)&bxt_i2c_info }, + { pci_vdevice(intel, 0x51c7), (kernel_ulong_t)&bxt_uart_info }, + { pci_vdevice(intel, 0x51e8), (kernel_ulong_t)&bxt_i2c_info }, + { pci_vdevice(intel, 0x51e9), (kernel_ulong_t)&bxt_i2c_info }, + { pci_vdevice(intel, 0x51ea), (kernel_ulong_t)&bxt_i2c_info }, + { pci_vdevice(intel, 0x51eb), (kernel_ulong_t)&bxt_i2c_info }, + { pci_vdevice(intel, 0x51fb), (kernel_ulong_t)&bxt_info },
|
Multi Function Devices (MFD)
|
f7b6732178e79ffb388aa343a7d0f63429d06204
|
andy shevchenko
|
drivers
|
mfd
| |
mfd: intel-lpss: add intel alder lake pch-s pci ids
|
add intel alder lake lpss pci ids.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add intel alder lake pch-s pci ids
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel-lpss']
|
['c']
| 1
| 15
| 0
|
--- diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c --- a/drivers/mfd/intel-lpss-pci.c +++ b/drivers/mfd/intel-lpss-pci.c + /* adl-s */ + { pci_vdevice(intel, 0x7aa8), (kernel_ulong_t)&bxt_uart_info }, + { pci_vdevice(intel, 0x7aa9), (kernel_ulong_t)&bxt_uart_info }, + { pci_vdevice(intel, 0x7aaa), (kernel_ulong_t)&bxt_info }, + { pci_vdevice(intel, 0x7aab), (kernel_ulong_t)&bxt_info }, + { pci_vdevice(intel, 0x7acc), (kernel_ulong_t)&bxt_i2c_info }, + { pci_vdevice(intel, 0x7acd), (kernel_ulong_t)&bxt_i2c_info }, + { pci_vdevice(intel, 0x7ace), (kernel_ulong_t)&bxt_i2c_info }, + { pci_vdevice(intel, 0x7acf), (kernel_ulong_t)&bxt_i2c_info }, + { pci_vdevice(intel, 0x7adc), (kernel_ulong_t)&bxt_uart_info }, + { pci_vdevice(intel, 0x7af9), (kernel_ulong_t)&bxt_info }, + { pci_vdevice(intel, 0x7afb), (kernel_ulong_t)&bxt_info }, + { pci_vdevice(intel, 0x7afc), (kernel_ulong_t)&bxt_i2c_info }, + { pci_vdevice(intel, 0x7afd), (kernel_ulong_t)&bxt_i2c_info }, + { pci_vdevice(intel, 0x7afe), (kernel_ulong_t)&bxt_uart_info },
|
Multi Function Devices (MFD)
|
c7b79a75287141cef5bbaeaf1c942269c08cd52e
|
jarkko nikula
|
drivers
|
mfd
| |
mfd: intel-m10-bmc: expose mac address and count
|
create two sysfs entries for exposing the mac address and count from the max10 bmc register space. the mac address is the first in a sequential block of mac addresses reserved for the fpga card. the mac count is the number of mac addresses in the reserved block.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
expose mac address and count
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel-m10-bmc']
|
['h', 'c', 'sysfs-driver-intel-m10-bmc']
| 3
| 73
| 0
|
--- diff --git a/documentation/abi/testing/sysfs-driver-intel-m10-bmc b/documentation/abi/testing/sysfs-driver-intel-m10-bmc --- a/documentation/abi/testing/sysfs-driver-intel-m10-bmc +++ b/documentation/abi/testing/sysfs-driver-intel-m10-bmc + +what: /sys/bus/spi/devices/.../mac_address +date: january 2021 +kernelversion: 5.12 +contact: russ weight <russell.h.weight@intel.com> +description: read only. returns the first mac address in a block + of sequential mac addresses assigned to the board + that is managed by the intel max10 bmc. it is stored in + flash storage and is mirrored in the max10 bmc register + space. + format: "%02x:%02x:%02x:%02x:%02x:%02x". + +what: /sys/bus/spi/devices/.../mac_count +date: january 2021 +kernelversion: 5.12 +contact: russ weight <russell.h.weight@intel.com> +description: read only. returns the number of sequential mac + addresses assigned to the board managed by the intel + max10 bmc. this value is stored in flash and is mirrored + in the max10 bmc register space. + format: "%u". diff --git a/drivers/mfd/intel-m10-bmc.c b/drivers/mfd/intel-m10-bmc.c --- a/drivers/mfd/intel-m10-bmc.c +++ b/drivers/mfd/intel-m10-bmc.c +static ssize_t mac_address_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct intel_m10bmc *max10 = dev_get_drvdata(dev); + unsigned int macaddr_low, macaddr_high; + int ret; + + ret = m10bmc_sys_read(max10, m10bmc_mac_low, &macaddr_low); + if (ret) + return ret; + + ret = m10bmc_sys_read(max10, m10bmc_mac_high, &macaddr_high); + if (ret) + return ret; + + return sysfs_emit(buf, "%02x:%02x:%02x:%02x:%02x:%02x ", + (u8)field_get(m10bmc_mac_byte1, macaddr_low), + (u8)field_get(m10bmc_mac_byte2, macaddr_low), + (u8)field_get(m10bmc_mac_byte3, macaddr_low), + (u8)field_get(m10bmc_mac_byte4, macaddr_low), + (u8)field_get(m10bmc_mac_byte5, macaddr_high), + (u8)field_get(m10bmc_mac_byte6, macaddr_high)); +} +static device_attr_ro(mac_address); + +static ssize_t mac_count_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct intel_m10bmc *max10 = dev_get_drvdata(dev); + unsigned int macaddr_high; + int ret; + + ret = m10bmc_sys_read(max10, m10bmc_mac_high, &macaddr_high); + if (ret) + return ret; + + return sysfs_emit(buf, "%u ", + (u8)field_get(m10bmc_mac_count, macaddr_high)); +} +static device_attr_ro(mac_count); + + &dev_attr_mac_address.attr, + &dev_attr_mac_count.attr, diff --git a/include/linux/mfd/intel-m10-bmc.h b/include/linux/mfd/intel-m10-bmc.h --- a/include/linux/mfd/intel-m10-bmc.h +++ b/include/linux/mfd/intel-m10-bmc.h +#define m10bmc_mac_low 0x10 +#define m10bmc_mac_byte4 genmask(7, 0) +#define m10bmc_mac_byte3 genmask(15, 8) +#define m10bmc_mac_byte2 genmask(23, 16) +#define m10bmc_mac_byte1 genmask(31, 24) +#define m10bmc_mac_high 0x14 +#define m10bmc_mac_byte6 genmask(7, 0) +#define m10bmc_mac_byte5 genmask(15, 8) +#define m10bmc_mac_count genmask(23, 16)
|
Multi Function Devices (MFD)
|
296f5568c6ee906e2a8db00adc751674f1745bd8
|
russ weight
|
include
|
linux
|
mfd, testing
|
mfd: intel_msic: remove driver for deprecated platform
|
intel moorestown and medfield are quite old intel atom based 32-bit platforms, which were in limited use in some android phones, tablets and consumer electronics more than eight years ago.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove driver for deprecated platform
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel_msic']
|
['c', 'h', 'kconfig', 'maintainers', 'makefile']
| 6
| 0
| 902
|
--- diff --git a/maintainers b/maintainers --- a/maintainers +++ b/maintainers -f: drivers/mfd/intel_msic.c -f: include/linux/mfd/intel_msic.h diff --git a/arch/x86/include/asm/intel_scu_ipc_legacy.h b/arch/x86/include/asm/intel_scu_ipc_legacy.h --- a/arch/x86/include/asm/intel_scu_ipc_legacy.h +++ b/arch/x86/include/asm/intel_scu_ipc_legacy.h -/* read single register */ -static inline int intel_scu_ipc_ioread8(u16 addr, u8 *data) -{ - return intel_scu_ipc_dev_ioread8(null, addr, data); -} - -/* write single register */ -static inline int intel_scu_ipc_iowrite8(u16 addr, u8 data) -{ - return intel_scu_ipc_dev_iowrite8(null, addr, data); -} - diff --git a/drivers/mfd/kconfig b/drivers/mfd/kconfig --- a/drivers/mfd/kconfig +++ b/drivers/mfd/kconfig -config mfd_intel_msic - bool "intel msic" - depends on intel_scu - select mfd_core - help - select this option to enable access to intel msic (avatele - passage) chip. this chip embeds audio, battery, gpio, etc. - devices used in intel medfield platforms. - diff --git a/drivers/mfd/makefile b/drivers/mfd/makefile --- a/drivers/mfd/makefile +++ b/drivers/mfd/makefile -obj-$(config_mfd_intel_msic) += intel_msic.o diff --git a/drivers/mfd/intel_msic.c b/drivers/mfd/intel_msic.c --- a/drivers/mfd/intel_msic.c +++ /dev/null -// spdx-license-identifier: gpl-2.0 -/* - * driver for intel msic - * - * copyright (c) 2011, intel corporation - * author: mika westerberg <mika.westerberg@linux.intel.com> - */ - -#include <linux/err.h> -#include <linux/gpio.h> -#include <linux/io.h> -#include <linux/init.h> -#include <linux/mfd/core.h> -#include <linux/mfd/intel_msic.h> -#include <linux/platform_device.h> -#include <linux/slab.h> - -#include <asm/intel_scu_ipc.h> - -#define msic_vendor(id) ((id >> 6) & 3) -#define msic_version(id) (id & 0x3f) -#define msic_major(id) ('a' + ((id >> 3) & 7)) -#define msic_minor(id) (id & 7) - -/* - * msic interrupt tree is readable from sram at intel_msic_irq_phys_base. - * since irq block starts from address 0x002 we need to subtract that from - * the actual irq status register address. - */ -#define msic_irq_status(x) (intel_msic_irq_phys_base + ((x) - 2)) -#define msic_irq_status_accdet msic_irq_status(intel_msic_accdet) - -/* - * the scu hardware has limitation of 16 bytes per read/write buffer on - * medfield. - */ -#define scu_ipc_rwbuf_limit 16 - -/** - * struct intel_msic - an msic mfd instance - * @pdev: pointer to the platform device - * @vendor: vendor id - * @version: chip version - * @irq_base: base address of the mapped msic sram interrupt tree - */ -struct intel_msic { - struct platform_device *pdev; - unsigned vendor; - unsigned version; - void __iomem *irq_base; -}; - -static const struct resource msic_touch_resources[] = { - define_res_irq(0), -}; - -static const struct resource msic_adc_resources[] = { - define_res_irq(0), -}; - -static const struct resource msic_battery_resources[] = { - define_res_irq(0), -}; - -static const struct resource msic_gpio_resources[] = { - define_res_irq(0), -}; - -static const struct resource msic_audio_resources[] = { - define_res_irq_named(0, "irq"), - /* - * we will pass irq_base to the driver now but this can be removed - * when/if the driver starts to use intel_msic_irq_read(). - */ - define_res_mem_named(msic_irq_status_accdet, 1, "irq_base"), -}; - -static const struct resource msic_hdmi_resources[] = { - define_res_irq(0), -}; - -static const struct resource msic_thermal_resources[] = { - define_res_irq(0), -}; - -static const struct resource msic_power_btn_resources[] = { - define_res_irq(0), -}; - -static const struct resource msic_ocd_resources[] = { - define_res_irq(0), -}; - -/* - * devices that are part of the msic and are available via firmware - * populated sfi devs table. - */ -static struct mfd_cell msic_devs[] = { - [intel_msic_block_touch] = { - .name = "msic_touch", - .num_resources = array_size(msic_touch_resources), - .resources = msic_touch_resources, - }, - [intel_msic_block_adc] = { - .name = "msic_adc", - .num_resources = array_size(msic_adc_resources), - .resources = msic_adc_resources, - }, - [intel_msic_block_battery] = { - .name = "msic_battery", - .num_resources = array_size(msic_battery_resources), - .resources = msic_battery_resources, - }, - [intel_msic_block_gpio] = { - .name = "msic_gpio", - .num_resources = array_size(msic_gpio_resources), - .resources = msic_gpio_resources, - }, - [intel_msic_block_audio] = { - .name = "msic_audio", - .num_resources = array_size(msic_audio_resources), - .resources = msic_audio_resources, - }, - [intel_msic_block_hdmi] = { - .name = "msic_hdmi", - .num_resources = array_size(msic_hdmi_resources), - .resources = msic_hdmi_resources, - }, - [intel_msic_block_thermal] = { - .name = "msic_thermal", - .num_resources = array_size(msic_thermal_resources), - .resources = msic_thermal_resources, - }, - [intel_msic_block_power_btn] = { - .name = "msic_power_btn", - .num_resources = array_size(msic_power_btn_resources), - .resources = msic_power_btn_resources, - }, - [intel_msic_block_ocd] = { - .name = "msic_ocd", - .num_resources = array_size(msic_ocd_resources), - .resources = msic_ocd_resources, - }, -}; - -/* - * other msic related devices which are not directly available via sfi devs - * table. these can be pseudo devices, regulators etc. which are needed for - * different purposes. - * - * these devices appear only after the msic driver itself is initialized so - * we can guarantee that the scu ipc interface is ready. - */ -static const struct mfd_cell msic_other_devs[] = { - /* audio codec in the msic */ - { - .id = -1, - .name = "sn95031", - }, -}; - -/** - * intel_msic_reg_read - read a single msic register - * @reg: register to read - * @val: register value is placed here - * - * read a single register from msic. returns %0 on success and negative - * errno in case of failure. - * - * function may sleep. - */ -int intel_msic_reg_read(unsigned short reg, u8 *val) -{ - return intel_scu_ipc_ioread8(reg, val); -} -export_symbol_gpl(intel_msic_reg_read); - -/** - * intel_msic_reg_write - write a single msic register - * @reg: register to write - * @val: value to write to that register - * - * write a single msic register. returns 0 on success and negative - * errno in case of failure. - * - * function may sleep. - */ -int intel_msic_reg_write(unsigned short reg, u8 val) -{ - return intel_scu_ipc_iowrite8(reg, val); -} -export_symbol_gpl(intel_msic_reg_write); - -/** - * intel_msic_reg_update - update a single msic register - * @reg: register to update - * @val: value to write to the register - * @mask: specifies which of the bits are updated (%0 = don't update, - * %1 = update) - * - * perform an update to a register @reg. @mask is used to specify which - * bits are updated. returns %0 in case of success and negative errno in - * case of failure. - * - * function may sleep. - */ -int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask) -{ - return intel_scu_ipc_update_register(reg, val, mask); -} -export_symbol_gpl(intel_msic_reg_update); - -/** - * intel_msic_bulk_read - read an array of registers - * @reg: array of register addresses to read - * @buf: array where the read values are placed - * @count: number of registers to read - * - * function reads @count registers from the msic using addresses passed in - * @reg. read values are placed in @buf. reads are performed atomically - * wrt. msic. - * - * returns %0 in case of success and negative errno in case of failure. - * - * function may sleep. - */ -int intel_msic_bulk_read(unsigned short *reg, u8 *buf, size_t count) -{ - if (warn_on(count > scu_ipc_rwbuf_limit)) - return -einval; - - return intel_scu_ipc_readv(reg, buf, count); -} -export_symbol_gpl(intel_msic_bulk_read); - -/** - * intel_msic_bulk_write - write an array of values to the msic registers - * @reg: array of registers to write - * @buf: values to write to each register - * @count: number of registers to write - * - * function writes @count registers in @buf to msic. writes are performed - * atomically wrt msic. returns %0 in case of success and negative errno in - * case of failure. - * - * function may sleep. - */ -int intel_msic_bulk_write(unsigned short *reg, u8 *buf, size_t count) -{ - if (warn_on(count > scu_ipc_rwbuf_limit)) - return -einval; - - return intel_scu_ipc_writev(reg, buf, count); -} -export_symbol_gpl(intel_msic_bulk_write); - -/** - * intel_msic_irq_read - read a register from an msic interrupt tree - * @msic: msic instance - * @reg: interrupt register (between %intel_msic_irqlvl1 and - * %intel_msic_resetirq2) - * @val: value of the register is placed here - * - * this function can be used by an msic subdevice interrupt handler to read - * a register value from the msic interrupt tree. in this way subdevice - * drivers don't have to map in the interrupt tree themselves but can just - * call this function instead. - * - * function doesn't sleep and is callable from interrupt context. - * - * returns %-einval if @reg is outside of the allowed register region. - */ -int intel_msic_irq_read(struct intel_msic *msic, unsigned short reg, u8 *val) -{ - if (warn_on(reg < intel_msic_irqlvl1 || reg > intel_msic_resetirq2)) - return -einval; - - *val = readb(msic->irq_base + (reg - intel_msic_irqlvl1)); - return 0; -} -export_symbol_gpl(intel_msic_irq_read); - -static int intel_msic_init_devices(struct intel_msic *msic) -{ - struct platform_device *pdev = msic->pdev; - struct intel_msic_platform_data *pdata = dev_get_platdata(&pdev->dev); - int ret, i; - - if (pdata->gpio) { - struct mfd_cell *cell = &msic_devs[intel_msic_block_gpio]; - - cell->platform_data = pdata->gpio; - cell->pdata_size = sizeof(*pdata->gpio); - } - - if (pdata->ocd) { - unsigned gpio = pdata->ocd->gpio; - - ret = devm_gpio_request_one(&pdev->dev, gpio, - gpiof_in, "ocd_gpio"); - if (ret) { - dev_err(&pdev->dev, "failed to register ocd gpio "); - return ret; - } - - ret = gpio_to_irq(gpio); - if (ret < 0) { - dev_err(&pdev->dev, "no irq number for ocd gpio "); - return ret; - } - - /* update the irq number for the ocd */ - pdata->irq[intel_msic_block_ocd] = ret; - } - - for (i = 0; i < array_size(msic_devs); i++) { - if (!pdata->irq[i]) - continue; - - ret = mfd_add_devices(&pdev->dev, -1, &msic_devs[i], 1, null, - pdata->irq[i], null); - if (ret) - goto fail; - } - - ret = mfd_add_devices(&pdev->dev, 0, msic_other_devs, - array_size(msic_other_devs), null, 0, null); - if (ret) - goto fail; - - return 0; - -fail: - mfd_remove_devices(&pdev->dev); - - return ret; -} - -static void intel_msic_remove_devices(struct intel_msic *msic) -{ - struct platform_device *pdev = msic->pdev; - - mfd_remove_devices(&pdev->dev); -} - -static int intel_msic_probe(struct platform_device *pdev) -{ - struct intel_msic_platform_data *pdata = dev_get_platdata(&pdev->dev); - struct intel_msic *msic; - struct resource *res; - u8 id0, id1; - int ret; - - if (!pdata) { - dev_err(&pdev->dev, "no platform data passed "); - return -einval; - } - - /* first validate that we have an msic in place */ - ret = intel_scu_ipc_ioread8(intel_msic_id0, &id0); - if (ret) { - dev_err(&pdev->dev, "failed to identify the msic chip (id0) "); - return -enxio; - } - - ret = intel_scu_ipc_ioread8(intel_msic_id1, &id1); - if (ret) { - dev_err(&pdev->dev, "failed to identify the msic chip (id1) "); - return -enxio; - } - - if (msic_vendor(id0) != msic_vendor(id1)) { - dev_err(&pdev->dev, "invalid vendor id: %x, %x ", id0, id1); - return -enxio; - } - - msic = devm_kzalloc(&pdev->dev, sizeof(*msic), gfp_kernel); - if (!msic) - return -enomem; - - msic->vendor = msic_vendor(id0); - msic->version = msic_version(id0); - msic->pdev = pdev; - - /* - * map in the msic interrupt tree area in sram. this is exposed to - * the clients via intel_msic_irq_read(). - */ - res = platform_get_resource(pdev, ioresource_mem, 0); - msic->irq_base = devm_ioremap_resource(&pdev->dev, res); - if (is_err(msic->irq_base)) - return ptr_err(msic->irq_base); - - platform_set_drvdata(pdev, msic); - - ret = intel_msic_init_devices(msic); - if (ret) { - dev_err(&pdev->dev, "failed to initialize msic devices "); - return ret; - } - - dev_info(&pdev->dev, "intel msic version %c%d (vendor %#x) ", - msic_major(msic->version), msic_minor(msic->version), - msic->vendor); - - return 0; -} - -static int intel_msic_remove(struct platform_device *pdev) -{ - struct intel_msic *msic = platform_get_drvdata(pdev); - - intel_msic_remove_devices(msic); - - return 0; -} - -static struct platform_driver intel_msic_driver = { - .probe = intel_msic_probe, - .remove = intel_msic_remove, - .driver = { - .name = "intel_msic", - }, -}; -builtin_platform_driver(intel_msic_driver); diff --git a/include/linux/mfd/intel_msic.h b/include/linux/mfd/intel_msic.h --- a/include/linux/mfd/intel_msic.h +++ /dev/null -/* spdx-license-identifier: gpl-2.0 */ -/* - * core interface for intel msic - * - * copyright (c) 2011, intel corporation - * author: mika westerberg <mika.westerberg@linux.intel.com> - */ - -#ifndef __linux_mfd_intel_msic_h__ -#define __linux_mfd_intel_msic_h__ - -/* id */ -#define intel_msic_id0 0x000 /* ro */ -#define intel_msic_id1 0x001 /* ro */ - -/* irq */ -#define intel_msic_irqlvl1 0x002 -#define intel_msic_adc1int 0x003 -#define intel_msic_ccint 0x004 -#define intel_msic_pwrsrcint 0x005 -#define intel_msic_pwrsrcint1 0x006 -#define intel_msic_chrint 0x007 -#define intel_msic_chrint1 0x008 -#define intel_msic_rtcirq 0x009 -#define intel_msic_gpio0lvirq 0x00a -#define intel_msic_gpio1lvirq 0x00b -#define intel_msic_gpiohvirq 0x00c -#define intel_msic_vrint 0x00d -#define intel_msic_ocaudio 0x00e -#define intel_msic_accdet 0x00f -#define intel_msic_resetirq1 0x010 -#define intel_msic_resetirq2 0x011 -#define intel_msic_madc1int 0x012 -#define intel_msic_mccint 0x013 -#define intel_msic_mpwrsrcint 0x014 -#define intel_msic_mpwrsrcint1 0x015 -#define intel_msic_mchrint 0x016 -#define intel_msic_mchrint1 0x017 -#define intel_msic_rtcirqmask 0x018 -#define intel_msic_gpio0lvirqmask 0x019 -#define intel_msic_gpio1lvirqmask 0x01a -#define intel_msic_gpiohvirqmask 0x01b -#define intel_msic_vrintmask 0x01c -#define intel_msic_ocaudiomask 0x01d -#define intel_msic_accdetmask 0x01e -#define intel_msic_resetirq1mask 0x01f -#define intel_msic_resetirq2mask 0x020 -#define intel_msic_irqlvl1msk 0x021 -#define intel_msic_pbconfig 0x03e -#define intel_msic_pbstatus 0x03f /* ro */ - -/* gpio */ -#define intel_msic_gpio0lv7ctlo 0x040 -#define intel_msic_gpio0lv6ctlo 0x041 -#define intel_msic_gpio0lv5ctlo 0x042 -#define intel_msic_gpio0lv4ctlo 0x043 -#define intel_msic_gpio0lv3ctlo 0x044 -#define intel_msic_gpio0lv2ctlo 0x045 -#define intel_msic_gpio0lv1ctlo 0x046 -#define intel_msic_gpio0lv0ctlo 0x047 -#define intel_msic_gpio1lv7ctlos 0x048 -#define intel_msic_gpio1lv6ctlo 0x049 -#define intel_msic_gpio1lv5ctlo 0x04a -#define intel_msic_gpio1lv4ctlo 0x04b -#define intel_msic_gpio1lv3ctlo 0x04c -#define intel_msic_gpio1lv2ctlo 0x04d -#define intel_msic_gpio1lv1ctlo 0x04e -#define intel_msic_gpio1lv0ctlo 0x04f -#define intel_msic_gpio0lv7ctli 0x050 -#define intel_msic_gpio0lv6ctli 0x051 -#define intel_msic_gpio0lv5ctli 0x052 -#define intel_msic_gpio0lv4ctli 0x053 -#define intel_msic_gpio0lv3ctli 0x054 -#define intel_msic_gpio0lv2ctli 0x055 -#define intel_msic_gpio0lv1ctli 0x056 -#define intel_msic_gpio0lv0ctli 0x057 -#define intel_msic_gpio1lv7ctlis 0x058 -#define intel_msic_gpio1lv6ctli 0x059 -#define intel_msic_gpio1lv5ctli 0x05a -#define intel_msic_gpio1lv4ctli 0x05b -#define intel_msic_gpio1lv3ctli 0x05c -#define intel_msic_gpio1lv2ctli 0x05d -#define intel_msic_gpio1lv1ctli 0x05e -#define intel_msic_gpio1lv0ctli 0x05f -#define intel_msic_pwm0clkdiv1 0x061 -#define intel_msic_pwm0clkdiv0 0x062 -#define intel_msic_pwm1clkdiv1 0x063 -#define intel_msic_pwm1clkdiv0 0x064 -#define intel_msic_pwm2clkdiv1 0x065 -#define intel_msic_pwm2clkdiv0 0x066 -#define intel_msic_pwm0dutycycle 0x067 -#define intel_msic_pwm1dutycycle 0x068 -#define intel_msic_pwm2dutycycle 0x069 -#define intel_msic_gpio0hv3ctlo 0x06d -#define intel_msic_gpio0hv2ctlo 0x06e -#define intel_msic_gpio0hv1ctlo 0x06f -#define intel_msic_gpio0hv0ctlo 0x070 -#define intel_msic_gpio1hv3ctlo 0x071 -#define intel_msic_gpio1hv2ctlo 0x072 -#define intel_msic_gpio1hv1ctlo 0x073 -#define intel_msic_gpio1hv0ctlo 0x074 -#define intel_msic_gpio0hv3ctli 0x075 -#define intel_msic_gpio0hv2ctli 0x076 -#define intel_msic_gpio0hv1ctli 0x077 -#define intel_msic_gpio0hv0ctli 0x078 -#define intel_msic_gpio1hv3ctli 0x079 -#define intel_msic_gpio1hv2ctli 0x07a -#define intel_msic_gpio1hv1ctli 0x07b -#define intel_msic_gpio1hv0ctli 0x07c - -/* svid */ -#define intel_msic_svidctrl0 0x080 -#define intel_msic_svidctrl1 0x081 -#define intel_msic_svidctrl2 0x082 -#define intel_msic_svidtxlastpkt3 0x083 /* ro */ -#define intel_msic_svidtxlastpkt2 0x084 /* ro */ -#define intel_msic_svidtxlastpkt1 0x085 /* ro */ -#define intel_msic_svidtxlastpkt0 0x086 /* ro */ -#define intel_msic_svidpktoutbyte3 0x087 -#define intel_msic_svidpktoutbyte2 0x088 -#define intel_msic_svidpktoutbyte1 0x089 -#define intel_msic_svidpktoutbyte0 0x08a -#define intel_msic_svidrxvpdebug1 0x08b -#define intel_msic_svidrxvpdebug0 0x08c -#define intel_msic_svidrxlastpkt3 0x08d /* ro */ -#define intel_msic_svidrxlastpkt2 0x08e /* ro */ -#define intel_msic_svidrxlastpkt1 0x08f /* ro */ -#define intel_msic_svidrxlastpkt0 0x090 /* ro */ -#define intel_msic_svidrxchkstatus3 0x091 /* ro */ -#define intel_msic_svidrxchkstatus2 0x092 /* ro */ -#define intel_msic_svidrxchkstatus1 0x093 /* ro */ -#define intel_msic_svidrxchkstatus0 0x094 /* ro */ - -/* vreg */ -#define intel_msic_vcclatch 0x0c0 -#define intel_msic_vnnlatch 0x0c1 -#define intel_msic_vcccnt 0x0c2 -#define intel_msic_smpsramp 0x0c3 -#define intel_msic_vnncnt 0x0c4 -#define intel_msic_vnnaoncnt 0x0c5 -#define intel_msic_vcc122aoncnt 0x0c6 -#define intel_msic_v180aoncnt 0x0c7 -#define intel_msic_v500cnt 0x0c8 -#define intel_msic_vihfcnt 0x0c9 -#define intel_msic_ldoramp1 0x0ca -#define intel_msic_ldoramp2 0x0cb -#define intel_msic_vcc108aoncnt 0x0cc -#define intel_msic_vcc108ascnt 0x0cd -#define intel_msic_vcc108cnt 0x0ce -#define intel_msic_vcca100ascnt 0x0cf -#define intel_msic_vcca100cnt 0x0d0 -#define intel_msic_vcc180aoncnt 0x0d1 -#define intel_msic_vcc180cnt 0x0d2 -#define intel_msic_vcc330cnt 0x0d3 -#define intel_msic_vusb330cnt 0x0d4 -#define intel_msic_vccsdiocnt 0x0d5 -#define intel_msic_vprog1cnt 0x0d6 -#define intel_msic_vprog2cnt 0x0d7 -#define intel_msic_vemmcscnt 0x0d8 -#define intel_msic_vemmc1cnt 0x0d9 -#define intel_msic_vemmc2cnt 0x0da -#define intel_msic_vaudacnt 0x0db -#define intel_msic_vhspcnt 0x0dc -#define intel_msic_vhsncnt 0x0dd -#define intel_msic_vhdmicnt 0x0de -#define intel_msic_votgcnt 0x0df -#define intel_msic_v1p35cnt 0x0e0 -#define intel_msic_v330aoncnt 0x0e1 - -/* reset */ -#define intel_msic_chipcntrl 0x100 /* wo */ -#define intel_msic_erconfig 0x101 - -/* burst */ -#define intel_msic_batcurrentlimit12 0x102 -#define intel_msic_battimelimit12 0x103 -#define intel_msic_battimelimit3 0x104 -#define intel_msic_battimedb 0x105 -#define intel_msic_brstconfigoutputs 0x106 -#define intel_msic_brstconfigactions 0x107 -#define intel_msic_burstcontrolstatus 0x108 - -/* rtc */ -#define intel_msic_rtcb1 0x140 /* ro */ -#define intel_msic_rtcb2 0x141 /* ro */ -#define intel_msic_rtcb3 0x142 /* ro */ -#define intel_msic_rtcb4 0x143 /* ro */ -#define intel_msic_rtcob1 0x144 -#define intel_msic_rtcob2 0x145 -#define intel_msic_rtcob3 0x146 -#define intel_msic_rtcob4 0x147 -#define intel_msic_rtcab1 0x148 -#define intel_msic_rtcab2 0x149 -#define intel_msic_rtcab3 0x14a -#define intel_msic_rtcab4 0x14b -#define intel_msic_rtcwab1 0x14c -#define intel_msic_rtcwab2 0x14d -#define intel_msic_rtcwab3 0x14e -#define intel_msic_rtcwab4 0x14f -#define intel_msic_rtcsc1 0x150 -#define intel_msic_rtcsc2 0x151 -#define intel_msic_rtcsc3 0x152 -#define intel_msic_rtcsc4 0x153 -#define intel_msic_rtcstatus 0x154 /* ro */ -#define intel_msic_rtcconfig1 0x155 -#define intel_msic_rtcconfig2 0x156 - -/* charger */ -#define intel_msic_bdtimer 0x180 -#define intel_msic_battrmv 0x181 -#define intel_msic_vbusdet 0x182 -#define intel_msic_vbusdet1 0x183 -#define intel_msic_adphvdet 0x184 -#define intel_msic_adplvdet 0x185 -#define intel_msic_adpdetdbdm 0x186 -#define intel_msic_lowbattdet 0x187 -#define intel_msic_chrctrl 0x188 -#define intel_msic_chrcvoltage 0x189 -#define intel_msic_chrccurrent 0x18a -#define intel_msic_spcharger 0x18b -#define intel_msic_chrttime 0x18c -#define intel_msic_chrctrl1 0x18d -#define intel_msic_pwrsrclmt 0x18e -#define intel_msic_chrstwdt 0x18f -#define intel_msic_wdtwrite 0x190 /* wo */ -#define intel_msic_chrsafelmt 0x191 -#define intel_msic_spwrsrcint 0x192 /* ro */ -#define intel_msic_spwrsrcint1 0x193 /* ro */ -#define intel_msic_chrledpwm 0x194 -#define intel_msic_chrledctrl 0x195 - -/* adc */ -#define intel_msic_adc1cntl1 0x1c0 -#define intel_msic_adc1cntl2 0x1c1 -#define intel_msic_adc1cntl3 0x1c2 -#define intel_msic_adc1offseth 0x1c3 /* ro */ -#define intel_msic_adc1offsetl 0x1c4 /* ro */ -#define intel_msic_adc1addr0 0x1c5 -#define intel_msic_adc1addr1 0x1c6 -#define intel_msic_adc1addr2 0x1c7 -#define intel_msic_adc1addr3 0x1c8 -#define intel_msic_adc1addr4 0x1c9 -#define intel_msic_adc1addr5 0x1ca -#define intel_msic_adc1addr6 0x1cb -#define intel_msic_adc1addr7 0x1cc -#define intel_msic_adc1addr8 0x1cd -#define intel_msic_adc1addr9 0x1ce -#define intel_msic_adc1addr10 0x1cf -#define intel_msic_adc1addr11 0x1d0 -#define intel_msic_adc1addr12 0x1d1 -#define intel_msic_adc1addr13 0x1d2 -#define intel_msic_adc1addr14 0x1d3 -#define intel_msic_adc1sns0h 0x1d4 /* ro */ -#define intel_msic_adc1sns0l 0x1d5 /* ro */ -#define intel_msic_adc1sns1h 0x1d6 /* ro */ -#define intel_msic_adc1sns1l 0x1d7 /* ro */ -#define intel_msic_adc1sns2h 0x1d8 /* ro */ -#define intel_msic_adc1sns2l 0x1d9 /* ro */ -#define intel_msic_adc1sns3h 0x1da /* ro */ -#define intel_msic_adc1sns3l 0x1db /* ro */ -#define intel_msic_adc1sns4h 0x1dc /* ro */ -#define intel_msic_adc1sns4l 0x1dd /* ro */ -#define intel_msic_adc1sns5h 0x1de /* ro */ -#define intel_msic_adc1sns5l 0x1df /* ro */ -#define intel_msic_adc1sns6h 0x1e0 /* ro */ -#define intel_msic_adc1sns6l 0x1e1 /* ro */ -#define intel_msic_adc1sns7h 0x1e2 /* ro */ -#define intel_msic_adc1sns7l 0x1e3 /* ro */ -#define intel_msic_adc1sns8h 0x1e4 /* ro */ -#define intel_msic_adc1sns8l 0x1e5 /* ro */ -#define intel_msic_adc1sns9h 0x1e6 /* ro */ -#define intel_msic_adc1sns9l 0x1e7 /* ro */ -#define intel_msic_adc1sns10h 0x1e8 /* ro */ -#define intel_msic_adc1sns10l 0x1e9 /* ro */ -#define intel_msic_adc1sns11h 0x1ea /* ro */ -#define intel_msic_adc1sns11l 0x1eb /* ro */ -#define intel_msic_adc1sns12h 0x1ec /* ro */ -#define intel_msic_adc1sns12l 0x1ed /* ro */ -#define intel_msic_adc1sns13h 0x1ee /* ro */ -#define intel_msic_adc1sns13l 0x1ef /* ro */ -#define intel_msic_adc1sns14h 0x1f0 /* ro */ -#define intel_msic_adc1sns14l 0x1f1 /* ro */ -#define intel_msic_adc1bv0h 0x1f2 /* ro */ -#define intel_msic_adc1bv0l 0x1f3 /* ro */ -#define intel_msic_adc1bv1h 0x1f4 /* ro */ -#define intel_msic_adc1bv1l 0x1f5 /* ro */ -#define intel_msic_adc1bv2h 0x1f6 /* ro */ -#define intel_msic_adc1bv2l 0x1f7 /* ro */ -#define intel_msic_adc1bv3h 0x1f8 /* ro */ -#define intel_msic_adc1bv3l 0x1f9 /* ro */ -#define intel_msic_adc1bi0h 0x1fa /* ro */ -#define intel_msic_adc1bi0l 0x1fb /* ro */ -#define intel_msic_adc1bi1h 0x1fc /* ro */ -#define intel_msic_adc1bi1l 0x1fd /* ro */ -#define intel_msic_adc1bi2h 0x1fe /* ro */ -#define intel_msic_adc1bi2l 0x1ff /* ro */ -#define intel_msic_adc1bi3h 0x200 /* ro */ -#define intel_msic_adc1bi3l 0x201 /* ro */ -#define intel_msic_cccntl 0x202 -#define intel_msic_ccoffseth 0x203 /* ro */ -#define intel_msic_ccoffsetl 0x204 /* ro */ -#define intel_msic_ccadcha 0x205 /* ro */ -#define intel_msic_ccadcla 0x206 /* ro */ - -/* audio */ -#define intel_msic_audpllctrl 0x240 -#define intel_msic_dmicbuf0123 0x241 -#define intel_msic_dmicbuf45 0x242 -#define intel_msic_dmicgpo 0x244 -#define intel_msic_dmicmux 0x245 -#define intel_msic_dmicclk 0x246 -#define intel_msic_micbias 0x247 -#define intel_msic_adcconfig 0x248 -#define intel_msic_micamp1 0x249 -#define intel_msic_micamp2 0x24a -#define intel_msic_noisemux 0x24b -#define intel_msic_audiomux12 0x24c -#define intel_msic_audiomux34 0x24d -#define intel_msic_audiosinc 0x24e -#define intel_msic_audiotxen 0x24f -#define intel_msic_hseprxctrl 0x250 -#define intel_msic_ihfrxctrl 0x251 -#define intel_msic_voicetxvol 0x252 -#define intel_msic_sidetonevol 0x253 -#define intel_msic_musicsharvol 0x254 -#define intel_msic_voicetxctrl 0x255 -#define intel_msic_hsmixer 0x256 -#define intel_msic_dacconfig 0x257 -#define intel_msic_softmute 0x258 -#define intel_msic_hslvolctrl 0x259 -#define intel_msic_hsrvolctrl 0x25a -#define intel_msic_ihflvolctrl 0x25b -#define intel_msic_ihfrvolctrl 0x25c -#define intel_msic_driveren 0x25d -#define intel_msic_lineoutctrl 0x25e -#define intel_msic_vib1ctrl1 0x25f -#define intel_msic_vib1ctrl2 0x260 -#define intel_msic_vib1ctrl3 0x261 -#define intel_msic_vib1spipcm_1 0x262 -#define intel_msic_vib1spipcm_2 0x263 -#define intel_msic_vib1ctrl5 0x264 -#define intel_msic_vib2ctrl1 0x265 -#define intel_msic_vib2ctrl2 0x266 -#define intel_msic_vib2ctrl3 0x267 -#define intel_msic_vib2spipcm_1 0x268 -#define intel_msic_vib2spipcm_2 0x269 -#define intel_msic_vib2ctrl5 0x26a -#define intel_msic_btnctrl1 0x26b -#define intel_msic_btnctrl2 0x26c -#define intel_msic_pcm1txslot01 0x26d -#define intel_msic_pcm1txslot23 0x26e -#define intel_msic_pcm1txslot45 0x26f -#define intel_msic_pcm1rxslot0123 0x270 -#define intel_msic_pcm1rxslot045 0x271 -#define intel_msic_pcm2txslot01 0x272 -#define intel_msic_pcm2txslot23 0x273 -#define intel_msic_pcm2txslot45 0x274 -#define intel_msic_pcm2rxslot01 0x275 -#define intel_msic_pcm2rxslot23 0x276 -#define intel_msic_pcm2rxslot45 0x277 -#define intel_msic_pcm1ctrl1 0x278 -#define intel_msic_pcm1ctrl2 0x279 -#define intel_msic_pcm1ctrl3 0x27a -#define intel_msic_pcm2ctrl1 0x27b -#define intel_msic_pcm2ctrl2 0x27c - -/* hdmi */ -#define intel_msic_hdmipuen 0x280 -#define intel_msic_hdmistatus 0x281 /* ro */ - -/* physical address of the start of the msic interrupt tree in sram */ -#define intel_msic_irq_phys_base 0xffff7fc0 - -/** - * struct intel_msic_gpio_pdata - platform data for the msic gpio driver - * @gpio_base: base number for the gpios - */ -struct intel_msic_gpio_pdata { - unsigned gpio_base; -}; - -/** - * struct intel_msic_ocd_pdata - platform data for the msic ocd driver - * @gpio: gpio number used for ocd interrupts - * - * the msic mfd driver converts @gpio into an irq number and passes it to - * the ocd driver as %ioresource_irq. - */ -struct intel_msic_ocd_pdata { - unsigned gpio; -}; - -/* msic embedded blocks (subdevices) */ -enum intel_msic_block { - intel_msic_block_touch, - intel_msic_block_adc, - intel_msic_block_battery, - intel_msic_block_gpio, - intel_msic_block_audio, - intel_msic_block_hdmi, - intel_msic_block_thermal, - intel_msic_block_power_btn, - intel_msic_block_ocd, - - intel_msic_block_last, -}; - -/** - * struct intel_msic_platform_data - platform data for the msic driver - * @irq: array of interrupt numbers, one per device. if @irq is set to %0 - * for a given block, the corresponding platform device is not - * created. for devices which don't have an interrupt, use %0xff - * (this is same as in sfi spec). - * @gpio: platform data for the msic gpio driver - * @ocd: platform data for the msic ocd driver - * - * once the msic driver is initialized, the register interface is ready to - * use. all the platform devices for subdevices are created after the - * register interface is ready so that we can guarantee its availability to - * the subdevice drivers. - * - * interrupt numbers are passed to the subdevices via %ioresource_irq - * resources of the created platform device. - */ -struct intel_msic_platform_data { - int irq[intel_msic_block_last]; - struct intel_msic_gpio_pdata *gpio; - struct intel_msic_ocd_pdata *ocd; -}; - -struct intel_msic; - -extern int intel_msic_reg_read(unsigned short reg, u8 *val); -extern int intel_msic_reg_write(unsigned short reg, u8 val); -extern int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask); -extern int intel_msic_bulk_read(unsigned short *reg, u8 *buf, size_t count); -extern int intel_msic_bulk_write(unsigned short *reg, u8 *buf, size_t count); - -/* - * pdev_to_intel_msic - gets an msic instance from the platform device - * @pdev: platform device pointer - * - * the client drivers need to have pointer to the msic instance if they - * want to call intel_msic_irq_read(). this macro can be used for - * convenience to get the msic pointer from @pdev where needed. this is - * _only_ valid for devices which are managed by the msic. - */ -#define pdev_to_intel_msic(pdev) (dev_get_drvdata(pdev->dev.parent)) - -extern int intel_msic_irq_read(struct intel_msic *msic, unsigned short reg, - u8 *val); - -#endif /* __linux_mfd_intel_msic_h__ */
|
Multi Function Devices (MFD)
|
ef3c67b6454b8f542f50387ad481633ae30874ac
|
andy shevchenko
|
include
|
linux
|
asm, include, mfd
|
pwm: remove zte zx driver
|
the zte zx platform is getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove zte zx driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['txt', 'kconfig', 'c', 'makefile']
| 4
| 0
| 311
|
--- diff --git a/documentation/devicetree/bindings/pwm/pwm-zx.txt b/documentation/devicetree/bindings/pwm/pwm-zx.txt --- a/documentation/devicetree/bindings/pwm/pwm-zx.txt +++ /dev/null -zte zx pwm controller - -required properties: - - compatible: should be "zte,zx296718-pwm". - - reg: physical base address and length of the controller's registers. - - clocks : the phandle and specifier referencing the controller's clocks. - - clock-names: "pclk" for pclk, "wclk" for wclk to the pwm controller. the - pclk is for register access, while wclk is the reference clock for - calculating period and duty cycles. - - #pwm-cells: should be 3. see pwm.yaml in this directory for a description of - the cells format. - -example: - - pwm: pwm@1439000 { - compatible = "zte,zx296718-pwm"; - reg = <0x1439000 0x1000>; - clocks = <&lsp1crm lsp1_pwm_pclk>, - <&lsp1crm lsp1_pwm_wclk>; - clock-names = "pclk", "wclk"; - #pwm-cells = <3>; - }; diff --git a/drivers/pwm/kconfig b/drivers/pwm/kconfig --- a/drivers/pwm/kconfig +++ b/drivers/pwm/kconfig -config pwm_zx - tristate "zte zx pwm support" - depends on arch_zx || compile_test - depends on has_iomem - help - generic pwm framework driver for zte zx family socs. - - to compile this driver as a module, choose m here: the module - will be called pwm-zx. - diff --git a/drivers/pwm/makefile b/drivers/pwm/makefile --- a/drivers/pwm/makefile +++ b/drivers/pwm/makefile -obj-$(config_pwm_zx) += pwm-zx.o diff --git a/drivers/pwm/pwm-zx.c b/drivers/pwm/pwm-zx.c --- a/drivers/pwm/pwm-zx.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * copyright (c) 2017 sanechips technology co., ltd. - * copyright 2017 linaro ltd. - */ - -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/pwm.h> -#include <linux/slab.h> - -#define zx_pwm_mode 0x0 -#define zx_pwm_clkdiv_shift 2 -#define zx_pwm_clkdiv_mask genmask(11, 2) -#define zx_pwm_clkdiv(x) (((x) << zx_pwm_clkdiv_shift) & \ - zx_pwm_clkdiv_mask) -#define zx_pwm_polar bit(1) -#define zx_pwm_en bit(0) -#define zx_pwm_period 0x4 -#define zx_pwm_duty 0x8 - -#define zx_pwm_clkdiv_max 1023 -#define zx_pwm_period_max 65535 - -struct zx_pwm_chip { - struct pwm_chip chip; - struct clk *pclk; - struct clk *wclk; - void __iomem *base; -}; - -static inline struct zx_pwm_chip *to_zx_pwm_chip(struct pwm_chip *chip) -{ - return container_of(chip, struct zx_pwm_chip, chip); -} - -static inline u32 zx_pwm_readl(struct zx_pwm_chip *zpc, unsigned int hwpwm, - unsigned int offset) -{ - return readl(zpc->base + (hwpwm + 1) * 0x10 + offset); -} - -static inline void zx_pwm_writel(struct zx_pwm_chip *zpc, unsigned int hwpwm, - unsigned int offset, u32 value) -{ - writel(value, zpc->base + (hwpwm + 1) * 0x10 + offset); -} - -static void zx_pwm_set_mask(struct zx_pwm_chip *zpc, unsigned int hwpwm, - unsigned int offset, u32 mask, u32 value) -{ - u32 data; - - data = zx_pwm_readl(zpc, hwpwm, offset); - data &= ~mask; - data |= value & mask; - zx_pwm_writel(zpc, hwpwm, offset, data); -} - -static void zx_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, - struct pwm_state *state) -{ - struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip); - unsigned long rate; - unsigned int div; - u32 value; - u64 tmp; - - value = zx_pwm_readl(zpc, pwm->hwpwm, zx_pwm_mode); - - if (value & zx_pwm_polar) - state->polarity = pwm_polarity_normal; - else - state->polarity = pwm_polarity_inversed; - - if (value & zx_pwm_en) - state->enabled = true; - else - state->enabled = false; - - div = (value & zx_pwm_clkdiv_mask) >> zx_pwm_clkdiv_shift; - rate = clk_get_rate(zpc->wclk); - - tmp = zx_pwm_readl(zpc, pwm->hwpwm, zx_pwm_period); - tmp *= div * nsec_per_sec; - state->period = div_round_closest_ull(tmp, rate); - - tmp = zx_pwm_readl(zpc, pwm->hwpwm, zx_pwm_duty); - tmp *= div * nsec_per_sec; - state->duty_cycle = div_round_closest_ull(tmp, rate); -} - -static int zx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, - unsigned int duty_ns, unsigned int period_ns) -{ - struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip); - unsigned int period_cycles, duty_cycles; - unsigned long long c; - unsigned int div = 1; - unsigned long rate; - - /* find out the best divider */ - rate = clk_get_rate(zpc->wclk); - - while (1) { - c = rate / div; - c = c * period_ns; - do_div(c, nsec_per_sec); - - if (c < zx_pwm_period_max) - break; - - div++; - - if (div > zx_pwm_clkdiv_max) - return -erange; - } - - /* calculate duty cycles */ - period_cycles = c; - c *= duty_ns; - do_div(c, period_ns); - duty_cycles = c; - - /* - * if the pwm is being enabled, we have to temporarily disable it - * before configuring the registers. - */ - if (pwm_is_enabled(pwm)) - zx_pwm_set_mask(zpc, pwm->hwpwm, zx_pwm_mode, zx_pwm_en, 0); - - /* set up registers */ - zx_pwm_set_mask(zpc, pwm->hwpwm, zx_pwm_mode, zx_pwm_clkdiv_mask, - zx_pwm_clkdiv(div)); - zx_pwm_writel(zpc, pwm->hwpwm, zx_pwm_period, period_cycles); - zx_pwm_writel(zpc, pwm->hwpwm, zx_pwm_duty, duty_cycles); - - /* re-enable the pwm if needed */ - if (pwm_is_enabled(pwm)) - zx_pwm_set_mask(zpc, pwm->hwpwm, zx_pwm_mode, - zx_pwm_en, zx_pwm_en); - - return 0; -} - -static int zx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, - const struct pwm_state *state) -{ - struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip); - struct pwm_state cstate; - int ret; - - pwm_get_state(pwm, &cstate); - - if (state->polarity != cstate.polarity) - zx_pwm_set_mask(zpc, pwm->hwpwm, zx_pwm_mode, zx_pwm_polar, - (state->polarity == pwm_polarity_inversed) ? - 0 : zx_pwm_polar); - - if (state->period != cstate.period || - state->duty_cycle != cstate.duty_cycle) { - ret = zx_pwm_config(chip, pwm, state->duty_cycle, - state->period); - if (ret) - return ret; - } - - if (state->enabled != cstate.enabled) { - if (state->enabled) { - ret = clk_prepare_enable(zpc->wclk); - if (ret) - return ret; - - zx_pwm_set_mask(zpc, pwm->hwpwm, zx_pwm_mode, - zx_pwm_en, zx_pwm_en); - } else { - zx_pwm_set_mask(zpc, pwm->hwpwm, zx_pwm_mode, - zx_pwm_en, 0); - clk_disable_unprepare(zpc->wclk); - } - } - - return 0; -} - -static const struct pwm_ops zx_pwm_ops = { - .apply = zx_pwm_apply, - .get_state = zx_pwm_get_state, - .owner = this_module, -}; - -static int zx_pwm_probe(struct platform_device *pdev) -{ - struct zx_pwm_chip *zpc; - unsigned int i; - int ret; - - zpc = devm_kzalloc(&pdev->dev, sizeof(*zpc), gfp_kernel); - if (!zpc) - return -enomem; - - zpc->base = devm_platform_ioremap_resource(pdev, 0); - if (is_err(zpc->base)) - return ptr_err(zpc->base); - - zpc->pclk = devm_clk_get(&pdev->dev, "pclk"); - if (is_err(zpc->pclk)) - return ptr_err(zpc->pclk); - - zpc->wclk = devm_clk_get(&pdev->dev, "wclk"); - if (is_err(zpc->wclk)) - return ptr_err(zpc->wclk); - - ret = clk_prepare_enable(zpc->pclk); - if (ret) - return ret; - - zpc->chip.dev = &pdev->dev; - zpc->chip.ops = &zx_pwm_ops; - zpc->chip.base = -1; - zpc->chip.npwm = 4; - zpc->chip.of_xlate = of_pwm_xlate_with_flags; - zpc->chip.of_pwm_n_cells = 3; - - /* - * pwm devices may be enabled by firmware, and let's disable all of - * them initially to save power. - */ - for (i = 0; i < zpc->chip.npwm; i++) - zx_pwm_set_mask(zpc, i, zx_pwm_mode, zx_pwm_en, 0); - - ret = pwmchip_add(&zpc->chip); - if (ret < 0) { - dev_err(&pdev->dev, "failed to add pwm chip: %d ", ret); - clk_disable_unprepare(zpc->pclk); - return ret; - } - - platform_set_drvdata(pdev, zpc); - - return 0; -} - -static int zx_pwm_remove(struct platform_device *pdev) -{ - struct zx_pwm_chip *zpc = platform_get_drvdata(pdev); - int ret; - - ret = pwmchip_remove(&zpc->chip); - clk_disable_unprepare(zpc->pclk); - - return ret; -} - -static const struct of_device_id zx_pwm_dt_ids[] = { - { .compatible = "zte,zx296718-pwm", }, - { /* sentinel */ } -}; -module_device_table(of, zx_pwm_dt_ids); - -static struct platform_driver zx_pwm_driver = { - .driver = { - .name = "zx-pwm", - .of_match_table = zx_pwm_dt_ids, - }, - .probe = zx_pwm_probe, - .remove = zx_pwm_remove, -}; -module_platform_driver(zx_pwm_driver); - -module_alias("platform:zx-pwm"); -module_author("shawn guo <shawn.guo@linaro.org>"); -module_description("zte zx pwm driver"); -module_license("gpl v2");
|
Pulse-Width Modulation (PWM)
|
a2bc9b21fd3f89b1f9a5df46427855dcf344e6e7
|
arnd bergmann
|
documentation
|
devicetree
|
bindings, pwm
|
i2c: drop unused efm32 bus driver
|
support for this machine was just removed, so drop the now unused i2c bus driver, too.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
drop unused efm32 bus driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['kconfig', 'c', 'makefile']
| 3
| 0
| 477
|
--- diff --git a/drivers/i2c/busses/kconfig b/drivers/i2c/busses/kconfig --- a/drivers/i2c/busses/kconfig +++ b/drivers/i2c/busses/kconfig -config i2c_efm32 - tristate "efm32 i2c controller" - depends on arch_efm32 || compile_test - help - this driver supports the i2c block found in energy micro's efm32 - socs. - diff --git a/drivers/i2c/busses/makefile b/drivers/i2c/busses/makefile --- a/drivers/i2c/busses/makefile +++ b/drivers/i2c/busses/makefile -obj-$(config_i2c_efm32) += i2c-efm32.o diff --git a/drivers/i2c/busses/i2c-efm32.c b/drivers/i2c/busses/i2c-efm32.c --- a/drivers/i2c/busses/i2c-efm32.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * copyright (c) 2014 uwe kleine-koenig for pengutronix - */ -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/i2c.h> -#include <linux/io.h> -#include <linux/interrupt.h> -#include <linux/err.h> -#include <linux/clk.h> - -#define driver_name "efm32-i2c" - -#define mask_val(mask, val) ((val << __ffs(mask)) & mask) - -#define reg_ctrl 0x00 -#define reg_ctrl_en 0x00001 -#define reg_ctrl_slave 0x00002 -#define reg_ctrl_autoack 0x00004 -#define reg_ctrl_autose 0x00008 -#define reg_ctrl_autosn 0x00010 -#define reg_ctrl_arbdis 0x00020 -#define reg_ctrl_gcamen 0x00040 -#define reg_ctrl_clhr__mask 0x00300 -#define reg_ctrl_bito__mask 0x03000 -#define reg_ctrl_bito_off 0x00000 -#define reg_ctrl_bito_40pcc 0x01000 -#define reg_ctrl_bito_80pcc 0x02000 -#define reg_ctrl_bito_160pcc 0x03000 -#define reg_ctrl_gibito 0x08000 -#define reg_ctrl_clto__mask 0x70000 -#define reg_ctrl_clto_off 0x00000 - -#define reg_cmd 0x04 -#define reg_cmd_start 0x00001 -#define reg_cmd_stop 0x00002 -#define reg_cmd_ack 0x00004 -#define reg_cmd_nack 0x00008 -#define reg_cmd_cont 0x00010 -#define reg_cmd_abort 0x00020 -#define reg_cmd_cleartx 0x00040 -#define reg_cmd_clearpc 0x00080 - -#define reg_state 0x08 -#define reg_state_busy 0x00001 -#define reg_state_master 0x00002 -#define reg_state_transmitter 0x00004 -#define reg_state_nacked 0x00008 -#define reg_state_bushold 0x00010 -#define reg_state_state__mask 0x000e0 -#define reg_state_state_idle 0x00000 -#define reg_state_state_wait 0x00020 -#define reg_state_state_start 0x00040 -#define reg_state_state_addr 0x00060 -#define reg_state_state_addrack 0x00080 -#define reg_state_state_data 0x000a0 -#define reg_state_state_dataack 0x000c0 - -#define reg_status 0x0c -#define reg_status_pstart 0x00001 -#define reg_status_pstop 0x00002 -#define reg_status_pack 0x00004 -#define reg_status_pnack 0x00008 -#define reg_status_pcont 0x00010 -#define reg_status_pabort 0x00020 -#define reg_status_txc 0x00040 -#define reg_status_txbl 0x00080 -#define reg_status_rxdatav 0x00100 - -#define reg_clkdiv 0x10 -#define reg_clkdiv_div__mask 0x001ff -#define reg_clkdiv_div(div) mask_val(reg_clkdiv_div__mask, (div)) - -#define reg_saddr 0x14 -#define reg_saddrmask 0x18 -#define reg_rxdata 0x1c -#define reg_rxdatap 0x20 -#define reg_txdata 0x24 -#define reg_if 0x28 -#define reg_if_start 0x00001 -#define reg_if_rstart 0x00002 -#define reg_if_addr 0x00004 -#define reg_if_txc 0x00008 -#define reg_if_txbl 0x00010 -#define reg_if_rxdatav 0x00020 -#define reg_if_ack 0x00040 -#define reg_if_nack 0x00080 -#define reg_if_mstop 0x00100 -#define reg_if_arblost 0x00200 -#define reg_if_buserr 0x00400 -#define reg_if_bushold 0x00800 -#define reg_if_txof 0x01000 -#define reg_if_rxuf 0x02000 -#define reg_if_bito 0x04000 -#define reg_if_clto 0x08000 -#define reg_if_sstop 0x10000 - -#define reg_ifs 0x2c -#define reg_ifc 0x30 -#define reg_ifc__mask 0x1ffcf - -#define reg_ien 0x34 - -#define reg_route 0x38 -#define reg_route_sdapen 0x00001 -#define reg_route_sclpen 0x00002 -#define reg_route_location__mask 0x00700 -#define reg_route_location(n) mask_val(reg_route_location__mask, (n)) - -struct efm32_i2c_ddata { - struct i2c_adapter adapter; - - struct clk *clk; - void __iomem *base; - unsigned int irq; - u8 location; - unsigned long frequency; - - /* transfer data */ - struct completion done; - struct i2c_msg *msgs; - size_t num_msgs; - size_t current_word, current_msg; - int retval; -}; - -static u32 efm32_i2c_read32(struct efm32_i2c_ddata *ddata, unsigned offset) -{ - return readl(ddata->base + offset); -} - -static void efm32_i2c_write32(struct efm32_i2c_ddata *ddata, - unsigned offset, u32 value) -{ - writel(value, ddata->base + offset); -} - -static void efm32_i2c_send_next_msg(struct efm32_i2c_ddata *ddata) -{ - struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg]; - - efm32_i2c_write32(ddata, reg_cmd, reg_cmd_start); - efm32_i2c_write32(ddata, reg_txdata, i2c_8bit_addr_from_msg(cur_msg)); -} - -static void efm32_i2c_send_next_byte(struct efm32_i2c_ddata *ddata) -{ - struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg]; - - if (ddata->current_word >= cur_msg->len) { - /* cur_msg completely transferred */ - ddata->current_word = 0; - ddata->current_msg += 1; - - if (ddata->current_msg >= ddata->num_msgs) { - efm32_i2c_write32(ddata, reg_cmd, reg_cmd_stop); - complete(&ddata->done); - } else { - efm32_i2c_send_next_msg(ddata); - } - } else { - efm32_i2c_write32(ddata, reg_txdata, - cur_msg->buf[ddata->current_word++]); - } -} - -static void efm32_i2c_recv_next_byte(struct efm32_i2c_ddata *ddata) -{ - struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg]; - - cur_msg->buf[ddata->current_word] = efm32_i2c_read32(ddata, reg_rxdata); - ddata->current_word += 1; - if (ddata->current_word >= cur_msg->len) { - /* cur_msg completely transferred */ - ddata->current_word = 0; - ddata->current_msg += 1; - - efm32_i2c_write32(ddata, reg_cmd, reg_cmd_nack); - - if (ddata->current_msg >= ddata->num_msgs) { - efm32_i2c_write32(ddata, reg_cmd, reg_cmd_stop); - complete(&ddata->done); - } else { - efm32_i2c_send_next_msg(ddata); - } - } else { - efm32_i2c_write32(ddata, reg_cmd, reg_cmd_ack); - } -} - -static irqreturn_t efm32_i2c_irq(int irq, void *dev_id) -{ - struct efm32_i2c_ddata *ddata = dev_id; - struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg]; - u32 irqflag = efm32_i2c_read32(ddata, reg_if); - u32 state = efm32_i2c_read32(ddata, reg_state); - - efm32_i2c_write32(ddata, reg_ifc, irqflag & reg_ifc__mask); - - switch (state & reg_state_state__mask) { - case reg_state_state_idle: - /* arbitration lost? */ - ddata->retval = -eagain; - complete(&ddata->done); - break; - case reg_state_state_wait: - /* - * huh, this shouldn't happen. - * reset hardware state and get out - */ - ddata->retval = -eio; - efm32_i2c_write32(ddata, reg_cmd, - reg_cmd_stop | reg_cmd_abort | - reg_cmd_cleartx | reg_cmd_clearpc); - complete(&ddata->done); - break; - case reg_state_state_start: - /* "caller" is expected to send an address */ - break; - case reg_state_state_addr: - /* wait for ack or nack of slave */ - break; - case reg_state_state_addrack: - if (state & reg_state_nacked) { - efm32_i2c_write32(ddata, reg_cmd, reg_cmd_stop); - ddata->retval = -enxio; - complete(&ddata->done); - } else if (cur_msg->flags & i2c_m_rd) { - /* wait for slave to send first data byte */ - } else { - efm32_i2c_send_next_byte(ddata); - } - break; - case reg_state_state_data: - if (cur_msg->flags & i2c_m_rd) { - efm32_i2c_recv_next_byte(ddata); - } else { - /* wait for ack or nack of slave */ - } - break; - case reg_state_state_dataack: - if (state & reg_state_nacked) { - efm32_i2c_write32(ddata, reg_cmd, reg_cmd_stop); - complete(&ddata->done); - } else { - efm32_i2c_send_next_byte(ddata); - } - } - - return irq_handled; -} - -static int efm32_i2c_master_xfer(struct i2c_adapter *adap, - struct i2c_msg *msgs, int num) -{ - struct efm32_i2c_ddata *ddata = i2c_get_adapdata(adap); - int ret; - - if (ddata->msgs) - return -ebusy; - - ddata->msgs = msgs; - ddata->num_msgs = num; - ddata->current_word = 0; - ddata->current_msg = 0; - ddata->retval = -eio; - - reinit_completion(&ddata->done); - - dev_dbg(&ddata->adapter.dev, "state: %08x, status: %08x ", - efm32_i2c_read32(ddata, reg_state), - efm32_i2c_read32(ddata, reg_status)); - - efm32_i2c_send_next_msg(ddata); - - wait_for_completion(&ddata->done); - - if (ddata->current_msg >= ddata->num_msgs) - ret = ddata->num_msgs; - else - ret = ddata->retval; - - return ret; -} - -static u32 efm32_i2c_functionality(struct i2c_adapter *adap) -{ - return i2c_func_i2c | i2c_func_smbus_emul; -} - -static const struct i2c_algorithm efm32_i2c_algo = { - .master_xfer = efm32_i2c_master_xfer, - .functionality = efm32_i2c_functionality, -}; - -static u32 efm32_i2c_get_configured_location(struct efm32_i2c_ddata *ddata) -{ - u32 reg = efm32_i2c_read32(ddata, reg_route); - - return (reg & reg_route_location__mask) >> - __ffs(reg_route_location__mask); -} - -static int efm32_i2c_probe(struct platform_device *pdev) -{ - struct efm32_i2c_ddata *ddata; - struct resource *res; - unsigned long rate; - struct device_node *np = pdev->dev.of_node; - u32 location, frequency; - int ret; - u32 clkdiv; - - ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), gfp_kernel); - if (!ddata) - return -enomem; - platform_set_drvdata(pdev, ddata); - - init_completion(&ddata->done); - strlcpy(ddata->adapter.name, pdev->name, sizeof(ddata->adapter.name)); - ddata->adapter.owner = this_module; - ddata->adapter.algo = &efm32_i2c_algo; - ddata->adapter.dev.parent = &pdev->dev; - ddata->adapter.dev.of_node = pdev->dev.of_node; - i2c_set_adapdata(&ddata->adapter, ddata); - - ddata->clk = devm_clk_get(&pdev->dev, null); - if (is_err(ddata->clk)) { - ret = ptr_err(ddata->clk); - dev_err(&pdev->dev, "failed to get clock: %d ", ret); - return ret; - } - - ddata->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); - if (is_err(ddata->base)) - return ptr_err(ddata->base); - - if (resource_size(res) < 0x42) { - dev_err(&pdev->dev, "memory resource too small "); - return -einval; - } - - ret = platform_get_irq(pdev, 0); - if (ret <= 0) { - if (!ret) - ret = -einval; - return ret; - } - - ddata->irq = ret; - - ret = clk_prepare_enable(ddata->clk); - if (ret < 0) { - dev_err(&pdev->dev, "failed to enable clock (%d) ", ret); - return ret; - } - - - ret = of_property_read_u32(np, "energymicro,location", &location); - - if (ret) - /* fall back to wrongly namespaced property */ - ret = of_property_read_u32(np, "efm32,location", &location); - - if (!ret) { - dev_dbg(&pdev->dev, "using location %u ", location); - } else { - /* default to location configured in hardware */ - location = efm32_i2c_get_configured_location(ddata); - - dev_info(&pdev->dev, "fall back to location %u ", location); - } - - ddata->location = location; - - ret = of_property_read_u32(np, "clock-frequency", &frequency); - if (!ret) { - dev_dbg(&pdev->dev, "using frequency %u ", frequency); - } else { - frequency = i2c_max_standard_mode_freq; - dev_info(&pdev->dev, "defaulting to 100 khz "); - } - ddata->frequency = frequency; - - rate = clk_get_rate(ddata->clk); - if (!rate) { - dev_err(&pdev->dev, "there is no input clock available "); - ret = -einval; - goto err_disable_clk; - } - clkdiv = div_round_up(rate, 8 * ddata->frequency) - 1; - if (clkdiv >= 0x200) { - dev_err(&pdev->dev, - "input clock too fast (%lu) to divide down to bus freq (%lu)", - rate, ddata->frequency); - ret = -einval; - goto err_disable_clk; - } - - dev_dbg(&pdev->dev, "input clock = %lu, bus freq = %lu, clkdiv = %lu ", - rate, ddata->frequency, (unsigned long)clkdiv); - efm32_i2c_write32(ddata, reg_clkdiv, reg_clkdiv_div(clkdiv)); - - efm32_i2c_write32(ddata, reg_route, reg_route_sdapen | - reg_route_sclpen | - reg_route_location(ddata->location)); - - efm32_i2c_write32(ddata, reg_ctrl, reg_ctrl_en | - reg_ctrl_bito_160pcc | 0 * reg_ctrl_gibito); - - efm32_i2c_write32(ddata, reg_ifc, reg_ifc__mask); - efm32_i2c_write32(ddata, reg_ien, reg_if_txc | reg_if_ack | reg_if_nack - | reg_if_arblost | reg_if_buserr | reg_if_rxdatav); - - /* to make bus idle */ - efm32_i2c_write32(ddata, reg_cmd, reg_cmd_abort); - - ret = request_irq(ddata->irq, efm32_i2c_irq, 0, driver_name, ddata); - if (ret < 0) { - dev_err(&pdev->dev, "failed to request irq (%d) ", ret); - goto err_disable_clk; - } - - ret = i2c_add_adapter(&ddata->adapter); - if (ret) { - free_irq(ddata->irq, ddata); - -err_disable_clk: - clk_disable_unprepare(ddata->clk); - } - return ret; -} - -static int efm32_i2c_remove(struct platform_device *pdev) -{ - struct efm32_i2c_ddata *ddata = platform_get_drvdata(pdev); - - i2c_del_adapter(&ddata->adapter); - free_irq(ddata->irq, ddata); - clk_disable_unprepare(ddata->clk); - - return 0; -} - -static const struct of_device_id efm32_i2c_dt_ids[] = { - { - .compatible = "energymicro,efm32-i2c", - }, { - /* sentinel */ - } -}; -module_device_table(of, efm32_i2c_dt_ids); - -static struct platform_driver efm32_i2c_driver = { - .probe = efm32_i2c_probe, - .remove = efm32_i2c_remove, - - .driver = { - .name = driver_name, - .of_match_table = efm32_i2c_dt_ids, - }, -}; -module_platform_driver(efm32_i2c_driver); - -module_author("uwe kleine-koenig <u.kleine-koenig@pengutronix.de>"); -module_description("efm32 i2c driver"); -module_license("gpl v2"); -module_alias("platform:" driver_name);
|
Inter-Integrated Circuit (I2C + I3C)
|
e4555a32ba427e628b75fa03593d55b1f38527b1
|
uwe kleine k nig
|
drivers
|
i2c
|
busses
|
i2c: i801: add support for intel alder lake pch-p
|
add pci id of smbus controller on intel alder lake pch-p.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for intel alder lake pch-p
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['i801']
|
['c']
| 1
| 4
| 0
|
--- diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c --- a/drivers/i2c/busses/i2c-i801.c +++ b/drivers/i2c/busses/i2c-i801.c + * alder lake-p (pch) 0x51a3 32 hard yes yes yes +#define pci_device_id_intel_alder_lake_p_smbus 0x51a3 + { pci_device(pci_vendor_id_intel, pci_device_id_intel_alder_lake_p_smbus) }, + case pci_device_id_intel_alder_lake_p_smbus:
|
Inter-Integrated Circuit (I2C + I3C)
|
d1f50bcfd646b620bef0e0ccb9b7523ad14fef63
|
jarkko nikula
|
drivers
|
i2c
|
busses
|
i2c: mlxcpld: add support for i2c bus frequency setting
|
add support for i2c bus frequency setting according to the specific system capability. this capability is obtained from cpld frequency setting register, which could be provided through the platform data. if such register is provided, it specifies minimal i2c bus frequency to be used for the devices attached to the i2c bus. supported freqeuncies are 100khz, 400khz, 1mhz, while 100khz is the default.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for i2c bus frequency setting
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlxcpld']
|
['c']
| 1
| 62
| 1
|
--- diff --git a/drivers/i2c/busses/i2c-mlxcpld.c b/drivers/i2c/busses/i2c-mlxcpld.c --- a/drivers/i2c/busses/i2c-mlxcpld.c +++ b/drivers/i2c/busses/i2c-mlxcpld.c +#include <linux/platform_data/mlxreg.h> +#include <linux/regmap.h> +#define mlxcpld_i2c_freq_1000khz_set 0x04 +#define mlxcpld_i2c_freq_400khz_set 0x0f +#define mlxcpld_i2c_freq_100khz_set 0x42 + +enum mlxcpld_i2c_frequency { + mlxcpld_i2c_freq_1000khz = 1, + mlxcpld_i2c_freq_400khz = 2, + mlxcpld_i2c_freq_100khz = 3, +}; + +static int +mlxcpld_i2c_set_frequency(struct mlxcpld_i2c_priv *priv, + struct mlxreg_core_hotplug_platform_data *pdata) +{ + struct mlxreg_core_item *item = pdata->items; + struct mlxreg_core_data *data; + u32 regval; + u8 freq; + int err; + + if (!item) + return 0; + + /* read frequency setting. */ + data = item->data; + err = regmap_read(pdata->regmap, data->reg, ®val); + if (err) + return err; + + /* set frequency only if it is not 100khz, which is default. */ + switch ((data->reg & data->mask) >> data->bit) { + case mlxcpld_i2c_freq_1000khz: + freq = mlxcpld_i2c_freq_1000khz_set; + break; + case mlxcpld_i2c_freq_400khz: + freq = mlxcpld_i2c_freq_400khz_set; + break; + default: + return 0; + } + + mlxcpld_i2c_write_comm(priv, mlxcpld_lpci2c_half_cyc_reg, &freq, 1); + + return 0; +} + + struct mlxreg_core_hotplug_platform_data *pdata; + /* set i2c bus frequency if platform data provides this info. */ + pdata = dev_get_platdata(&pdev->dev); + if (pdata) { + err = mlxcpld_i2c_set_frequency(priv, pdata); + if (err) + goto mlxcpld_i2_probe_failed; + } + - mutex_destroy(&priv->lock); + goto mlxcpld_i2_probe_failed; + return 0; + +mlxcpld_i2_probe_failed: + mutex_destroy(&priv->lock);
|
Inter-Integrated Circuit (I2C + I3C)
|
66b0c2846ba8de569026a067bb5a34ea5768408c
|
vadim pasternak
|
drivers
|
i2c
|
busses
|
i2c: mux: mlxcpld: convert driver to platform driver
|
convert driver from 'i2c' to 'platform'. the motivation is to avoid i2c addressing conflict between 'i2c-mux-cpld' driver, providing mux selection and deselection through cpld 'mux control' register, and cpld host driver. the cpld is i2c device and is multi-functional device performing logic for different components, like led, 'hwmon', interrupt control, watchdog etcetera. for such configuration cpld should be host i2c device, connected to the relevant i2c bus with the relevant i2c address and all others component drivers are supposed to be its children. the hierarchy in such case will be like in the below example: ls /sys/bus/i2c/devices/44-0032 i2c-mux-mlxcpld.44 leds-mlxreg.44 mlxreg-io.44 ls /sys/bus/i2c/devices/44-0032/i2c-mux-mlxcpld.44 channel-0, , channel-x
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
extend driver functionality
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mux', 'mlxcpld']
|
['c']
| 1
| 28
| 34
|
--- diff --git a/drivers/i2c/muxes/i2c-mux-mlxcpld.c b/drivers/i2c/muxes/i2c-mux-mlxcpld.c --- a/drivers/i2c/muxes/i2c-mux-mlxcpld.c +++ b/drivers/i2c/muxes/i2c-mux-mlxcpld.c + * @pdata: platform data + struct mlxcpld_mux_plat_data pdata; -static const struct i2c_device_id mlxcpld_mux_id[] = { - { "mlxcpld_mux_module", 0 }, - { } -}; -module_device_table(i2c, mlxcpld_mux_id); - - struct i2c_client *client, u8 val) + struct mlxcpld_mux *mux, u8 val) - struct mlxcpld_mux_plat_data *pdata = dev_get_platdata(&client->dev); + struct i2c_client *client = mux->client; - i2c_smbus_write, pdata->sel_reg_addr, + i2c_smbus_write, mux->pdata.sel_reg_addr, - struct mlxcpld_mux *data = i2c_mux_priv(muxc); - struct i2c_client *client = data->client; + struct mlxcpld_mux *mux = i2c_mux_priv(muxc); - if (data->last_chan != regval) { - err = mlxcpld_mux_reg_write(muxc->parent, client, regval); - data->last_chan = err < 0 ? 0 : regval; + if (mux->last_chan != regval) { + err = mlxcpld_mux_reg_write(muxc->parent, mux, regval); + mux->last_chan = err < 0 ? 0 : regval; - struct mlxcpld_mux *data = i2c_mux_priv(muxc); - struct i2c_client *client = data->client; + struct mlxcpld_mux *mux = i2c_mux_priv(muxc); - data->last_chan = 0; + mux->last_chan = 0; - return mlxcpld_mux_reg_write(muxc->parent, client, data->last_chan); + return mlxcpld_mux_reg_write(muxc->parent, mux, mux->last_chan); -static int mlxcpld_mux_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int mlxcpld_mux_probe(struct platform_device *pdev) - struct i2c_adapter *adap = client->adapter; - struct mlxcpld_mux_plat_data *pdata = dev_get_platdata(&client->dev); + struct mlxcpld_mux_plat_data *pdata = dev_get_platdata(&pdev->dev); + struct i2c_client *client = to_i2c_client(pdev->dev.parent); - if (!i2c_check_functionality(adap, i2c_func_smbus_write_byte_data)) + if (!i2c_check_functionality(client->adapter, + i2c_func_smbus_write_byte_data)) - muxc = i2c_mux_alloc(adap, &client->dev, cpld_mux_max_nchans, + muxc = i2c_mux_alloc(client->adapter, &pdev->dev, cpld_mux_max_nchans, + platform_set_drvdata(pdev, muxc); - i2c_set_clientdata(client, muxc); + memcpy(&data->pdata, pdata, sizeof(*pdata)); -static int mlxcpld_mux_remove(struct i2c_client *client) +static int mlxcpld_mux_remove(struct platform_device *pdev) - struct i2c_mux_core *muxc = i2c_get_clientdata(client); + struct i2c_mux_core *muxc = platform_get_drvdata(pdev); -static struct i2c_driver mlxcpld_mux_driver = { - .driver = { - .name = "mlxcpld-mux", +static struct platform_driver mlxcpld_mux_driver = { + .driver = { + .name = "i2c-mux-mlxcpld", - .probe = mlxcpld_mux_probe, - .remove = mlxcpld_mux_remove, - .id_table = mlxcpld_mux_id, + .probe = mlxcpld_mux_probe, + .remove = mlxcpld_mux_remove, -module_i2c_driver(mlxcpld_mux_driver); +module_platform_driver(mlxcpld_mux_driver);
|
Inter-Integrated Circuit (I2C + I3C)
|
84af1b168c5015fca0761cf9cce4add31e354dce
|
vadim pasternak
|
drivers
|
i2c
|
muxes
|
i2c: mux: mlxcpld: prepare mux selection infrastructure for two-byte support
|
allow to program register value zero to the mux register, which is required for word address mux register space support. change key selector type from 'unsigned short' to 'integer' in order to allow to set it to -1 on deselection. rename key selector field from 'last_chan' to 'last_val', since this fields keeps actually selector value and not channel number.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
extend driver functionality
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mux', 'mlxcpld']
|
['c']
| 1
| 9
| 9
|
--- diff --git a/drivers/i2c/muxes/i2c-mux-mlxcpld.c b/drivers/i2c/muxes/i2c-mux-mlxcpld.c --- a/drivers/i2c/muxes/i2c-mux-mlxcpld.c +++ b/drivers/i2c/muxes/i2c-mux-mlxcpld.c - * @last_chan - last register value + * @last_val - last selected register value or -1 if mux deselected - u8 last_chan; + int last_val; - struct mlxcpld_mux *mux, u8 val) + struct mlxcpld_mux *mux, u32 val) - u8 regval = chan + 1; + u32 regval = chan + 1; - if (mux->last_chan != regval) { + if (mux->last_val != regval) { - mux->last_chan = err < 0 ? 0 : regval; + mux->last_val = err < 0 ? -1 : regval; - mux->last_chan = 0; + mux->last_val = -1; - return mlxcpld_mux_reg_write(muxc->parent, mux, mux->last_chan); + return mlxcpld_mux_reg_write(muxc->parent, mux, 0); - data->last_chan = 0; /* force the first selection */ + data->last_val = -1; /* force the first selection */
|
Inter-Integrated Circuit (I2C + I3C)
|
81566938083af15aec75201293cf6047bb04f4d3
|
vadim pasternak peter rosin peda axentia se
|
drivers
|
i2c
|
muxes
|
i2c: mux: mlxcpld: get rid of adapter numbers enforcement
|
do not set the argument 'force_nr' of i2c_mux_add_adapter() routine, instead provide argument 'chan_id'. rename mux ids array from 'adap_ids' to 'chan_ids'.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
extend driver functionality
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mux', 'mlxcpld']
|
['h', 'c']
| 2
| 4
| 7
|
- create only the child adapters which are actually needed - for which - to assign 'nrs' to these child adapters dynamically, with no 'nr' --- diff --git a/drivers/i2c/muxes/i2c-mux-mlxcpld.c b/drivers/i2c/muxes/i2c-mux-mlxcpld.c --- a/drivers/i2c/muxes/i2c-mux-mlxcpld.c +++ b/drivers/i2c/muxes/i2c-mux-mlxcpld.c - int num, force; - int err; + int num, err; - force = pdata->adap_ids[num]; - - err = i2c_mux_add_adapter(muxc, force, num, 0); + err = i2c_mux_add_adapter(muxc, 0, pdata->chan_ids[num], 0); diff --git a/include/linux/platform_data/mlxcpld.h b/include/linux/platform_data/mlxcpld.h --- a/include/linux/platform_data/mlxcpld.h +++ b/include/linux/platform_data/mlxcpld.h - * @adap_ids - adapter array + * @chan_ids - channels array - int *adap_ids; + int *chan_ids;
|
Inter-Integrated Circuit (I2C + I3C)
|
cae5216387d18c888f9f38a0cf5be341a0af75a6
|
vadim pasternak
|
drivers
|
i2c
|
muxes, platform_data
|
i2c: mux: mlxcpld: extend driver to support word address space devices
|
extend driver to allow i2c routing control through cpld devices with word address space. till now only cpld devices with byte address space have been supported.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
extend driver functionality
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mux', 'mlxcpld']
|
['h', 'c']
| 2
| 41
| 8
|
--- diff --git a/drivers/i2c/muxes/i2c-mux-mlxcpld.c b/drivers/i2c/muxes/i2c-mux-mlxcpld.c --- a/drivers/i2c/muxes/i2c-mux-mlxcpld.c +++ b/drivers/i2c/muxes/i2c-mux-mlxcpld.c - union i2c_smbus_data data = { .byte = val }; - - return __i2c_smbus_xfer(adap, client->addr, client->flags, - i2c_smbus_write, mux->pdata.sel_reg_addr, - i2c_smbus_byte_data, &data); + union i2c_smbus_data data; + struct i2c_msg msg; + u8 buf[3]; + + switch (mux->pdata.reg_size) { + case 1: + data.byte = val; + return __i2c_smbus_xfer(adap, client->addr, client->flags, + i2c_smbus_write, mux->pdata.sel_reg_addr, + i2c_smbus_byte_data, &data); + case 2: + buf[0] = mux->pdata.sel_reg_addr >> 8; + buf[1] = mux->pdata.sel_reg_addr; + buf[2] = val; + msg.addr = client->addr; + msg.buf = buf; + msg.len = mux->pdata.reg_size + 1; + msg.flags = 0; + return __i2c_transfer(adap, &msg, 1); + default: + return -einval; + } - u32 regval = chan + 1; + u32 regval = chan; + if (mux->pdata.reg_size == 1) + regval += 1; + + u32 func; - if (!i2c_check_functionality(client->adapter, - i2c_func_smbus_write_byte_data)) + switch (pdata->reg_size) { + case 1: + func = i2c_func_smbus_write_byte_data; + break; + case 2: + func = i2c_func_i2c; + break; + default: + return -einval; + } + + if (!i2c_check_functionality(client->adapter, func)) diff --git a/include/linux/platform_data/mlxcpld.h b/include/linux/platform_data/mlxcpld.h --- a/include/linux/platform_data/mlxcpld.h +++ b/include/linux/platform_data/mlxcpld.h + * @reg_size: register size in bytes + u8 reg_size;
|
Inter-Integrated Circuit (I2C + I3C)
|
c52a1c5f5db55c6a71110c2db9ae26b9f5269d20
|
vadim pasternak peter rosin peda axentia se michael shych michaelsh nvidia com
|
drivers
|
i2c
|
muxes, platform_data
|
i2c: mux: mlxcpld: extend supported mux number
|
allow to extend mux number supported by driver. currently it is limited by eight, which is not enough for new coming mellanox modular system with line cards, which require up to 64 mux support.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
extend driver functionality
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mux', 'mlxcpld']
|
['c']
| 1
| 2
| 8
|
--- diff --git a/drivers/i2c/muxes/i2c-mux-mlxcpld.c b/drivers/i2c/muxes/i2c-mux-mlxcpld.c --- a/drivers/i2c/muxes/i2c-mux-mlxcpld.c +++ b/drivers/i2c/muxes/i2c-mux-mlxcpld.c -#define cpld_mux_max_nchans 8 - - muxc = i2c_mux_alloc(client->adapter, &pdev->dev, cpld_mux_max_nchans, + muxc = i2c_mux_alloc(client->adapter, &pdev->dev, pdata->num_adaps, - for (num = 0; num < cpld_mux_max_nchans; num++) { - if (num >= pdata->num_adaps) - /* discard unconfigured channels */ - break; - + for (num = 0; num < pdata->num_adaps; num++) {
|
Inter-Integrated Circuit (I2C + I3C)
|
699c0506543ee9ba3f5a67ab0837b292b098aeb4
|
vadim pasternak peter rosin peda axentia se michael shych michaelsh nvidia com
|
drivers
|
i2c
|
muxes
|
i2c: mux: mlxcpld: add callback to notify mux creation completion
|
add notification to inform caller that mux objects array has been created. it allows to user, invoked platform device registration for "i2c-mux-mlxcpld" driver, to be notified that mux infrastructure is available, and thus some devices could be connected to this infrastructure.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
extend driver functionality
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mux', 'mlxcpld']
|
['h', 'c']
| 2
| 9
| 0
|
--- diff --git a/drivers/i2c/muxes/i2c-mux-mlxcpld.c b/drivers/i2c/muxes/i2c-mux-mlxcpld.c --- a/drivers/i2c/muxes/i2c-mux-mlxcpld.c +++ b/drivers/i2c/muxes/i2c-mux-mlxcpld.c + /* notify caller when all channels' adapters are created. */ + if (pdata->completion_notify) + pdata->completion_notify(pdata->handle, muxc->parent, muxc->adapter); + diff --git a/include/linux/platform_data/mlxcpld.h b/include/linux/platform_data/mlxcpld.h --- a/include/linux/platform_data/mlxcpld.h +++ b/include/linux/platform_data/mlxcpld.h + * @handle: handle to be passed by callback + * @completion_notify: callback to notify when all the adapters are created + void *handle; + int (*completion_notify)(void *handle, struct i2c_adapter *parent, + struct i2c_adapter *adapters[]);
|
Inter-Integrated Circuit (I2C + I3C)
|
a39bd92e92b96d05d676fb5c9493cf1c911d2a0a
|
vadim pasternak peter rosin peda axentia se
|
drivers
|
i2c
|
muxes, platform_data
|
i2c: remove sirf bus driver
|
the csr sirf prima2/atlas platforms are getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove sirf bus driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['txt', 'kconfig', 'c', 'makefile']
| 4
| 0
| 505
|
--- diff --git a/documentation/devicetree/bindings/i2c/i2c-sirf.txt b/documentation/devicetree/bindings/i2c/i2c-sirf.txt --- a/documentation/devicetree/bindings/i2c/i2c-sirf.txt +++ /dev/null -i2c for sirfprimaii platforms - -required properties : -- compatible : must be "sirf,prima2-i2c" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: interrupt number to the cpu. - -optional properties: -- clock-frequency : constains desired i2c/hs-i2c bus clock frequency in hz. - the absence of the property indicates the default frequency 100 khz. - -examples : - -i2c0: i2c@b00e0000 { - compatible = "sirf,prima2-i2c"; - reg = <0xb00e0000 0x10000>; - interrupts = <24>; -}; diff --git a/drivers/i2c/busses/kconfig b/drivers/i2c/busses/kconfig --- a/drivers/i2c/busses/kconfig +++ b/drivers/i2c/busses/kconfig -config i2c_sirf - tristate "csr sirfprimaii i2c interface" - depends on arch_sirf || compile_test - help - if you say yes to this option, support will be included for the - csr sirfprimaii i2c interface. - - this driver can also be built as a module. if so, the module - will be called i2c-sirf. - diff --git a/drivers/i2c/busses/makefile b/drivers/i2c/busses/makefile --- a/drivers/i2c/busses/makefile +++ b/drivers/i2c/busses/makefile -obj-$(config_i2c_sirf) += i2c-sirf.o diff --git a/drivers/i2c/busses/i2c-sirf.c b/drivers/i2c/busses/i2c-sirf.c --- a/drivers/i2c/busses/i2c-sirf.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-or-later -/* - * i2c bus driver for csr sirfprimaii - * - * copyright (c) 2011 cambridge silicon radio limited, a csr plc group company. - */ - -#include <linux/interrupt.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/slab.h> -#include <linux/platform_device.h> -#include <linux/i2c.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/io.h> - -#define sirfsoc_i2c_clk_ctrl 0x00 -#define sirfsoc_i2c_status 0x0c -#define sirfsoc_i2c_ctrl 0x10 -#define sirfsoc_i2c_io_ctrl 0x14 -#define sirfsoc_i2c_sda_delay 0x18 -#define sirfsoc_i2c_cmd_start 0x1c -#define sirfsoc_i2c_cmd_buf 0x30 -#define sirfsoc_i2c_data_buf 0x80 - -#define sirfsoc_i2c_cmd_buf_max 16 -#define sirfsoc_i2c_data_buf_max 16 - -#define sirfsoc_i2c_cmd(x) (sirfsoc_i2c_cmd_buf + (x)*0x04) -#define sirfsoc_i2c_data_mask(x) (0xff<<(((x)&3)*8)) -#define sirfsoc_i2c_data_shift(x) (((x)&3)*8) - -#define sirfsoc_i2c_div_mask (0xffff) - -/* i2c status flags */ -#define sirfsoc_i2c_stat_busy bit(0) -#define sirfsoc_i2c_stat_tip bit(1) -#define sirfsoc_i2c_stat_nack bit(2) -#define sirfsoc_i2c_stat_tr_int bit(4) -#define sirfsoc_i2c_stat_stop bit(6) -#define sirfsoc_i2c_stat_cmd_done bit(8) -#define sirfsoc_i2c_stat_err bit(9) -#define sirfsoc_i2c_cmd_index (0x1f<<16) - -/* i2c control flags */ -#define sirfsoc_i2c_reset bit(0) -#define sirfsoc_i2c_core_en bit(1) -#define sirfsoc_i2c_master_mode bit(2) -#define sirfsoc_i2c_cmd_done_en bit(11) -#define sirfsoc_i2c_err_int_en bit(12) - -#define sirfsoc_i2c_sda_delay_mask (0xff) -#define sirfsoc_i2c_sclf_filter (3<<8) - -#define sirfsoc_i2c_start_cmd bit(0) - -#define sirfsoc_i2c_cmd_rp(x) ((x)&0x7) -#define sirfsoc_i2c_nack bit(3) -#define sirfsoc_i2c_write bit(4) -#define sirfsoc_i2c_read bit(5) -#define sirfsoc_i2c_stop bit(6) -#define sirfsoc_i2c_start bit(7) - -#define sirfsoc_i2c_err_noack 1 -#define sirfsoc_i2c_err_timeout 2 - -struct sirfsoc_i2c { - void __iomem *base; - struct clk *clk; - u32 cmd_ptr; /* current position in cmd buffer */ - u8 *buf; /* buffer passed by user */ - u32 msg_len; /* message length */ - u32 finished_len; /* number of bytes read/written */ - u32 read_cmd_len; /* number of read cmd sent */ - int msg_read; /* 1 indicates a read message */ - int err_status; /* 1 indicates an error on bus */ - - u32 sda_delay; /* for suspend/resume */ - u32 clk_div; - int last; /* last message in transfer, stop cmd can be sent */ - - struct completion done; /* indicates completion of message transfer */ - struct i2c_adapter adapter; -}; - -static void i2c_sirfsoc_read_data(struct sirfsoc_i2c *siic) -{ - u32 data = 0; - int i; - - for (i = 0; i < siic->read_cmd_len; i++) { - if (!(i & 0x3)) - data = readl(siic->base + sirfsoc_i2c_data_buf + i); - siic->buf[siic->finished_len++] = - (u8)((data & sirfsoc_i2c_data_mask(i)) >> - sirfsoc_i2c_data_shift(i)); - } -} - -static void i2c_sirfsoc_queue_cmd(struct sirfsoc_i2c *siic) -{ - u32 regval; - int i = 0; - - if (siic->msg_read) { - while (((siic->finished_len + i) < siic->msg_len) - && (siic->cmd_ptr < sirfsoc_i2c_cmd_buf_max)) { - regval = sirfsoc_i2c_read | sirfsoc_i2c_cmd_rp(0); - if (((siic->finished_len + i) == - (siic->msg_len - 1)) && siic->last) - regval |= sirfsoc_i2c_stop | sirfsoc_i2c_nack; - writel(regval, - siic->base + sirfsoc_i2c_cmd(siic->cmd_ptr++)); - i++; - } - - siic->read_cmd_len = i; - } else { - while ((siic->cmd_ptr < sirfsoc_i2c_cmd_buf_max - 1) - && (siic->finished_len < siic->msg_len)) { - regval = sirfsoc_i2c_write | sirfsoc_i2c_cmd_rp(0); - if ((siic->finished_len == (siic->msg_len - 1)) - && siic->last) - regval |= sirfsoc_i2c_stop; - writel(regval, - siic->base + sirfsoc_i2c_cmd(siic->cmd_ptr++)); - writel(siic->buf[siic->finished_len++], - siic->base + sirfsoc_i2c_cmd(siic->cmd_ptr++)); - } - } - siic->cmd_ptr = 0; - - /* trigger the transfer */ - writel(sirfsoc_i2c_start_cmd, siic->base + sirfsoc_i2c_cmd_start); -} - -static irqreturn_t i2c_sirfsoc_irq(int irq, void *dev_id) -{ - struct sirfsoc_i2c *siic = (struct sirfsoc_i2c *)dev_id; - u32 i2c_stat = readl(siic->base + sirfsoc_i2c_status); - - if (i2c_stat & sirfsoc_i2c_stat_err) { - /* error conditions */ - siic->err_status = sirfsoc_i2c_err_noack; - writel(sirfsoc_i2c_stat_err, siic->base + sirfsoc_i2c_status); - - if (i2c_stat & sirfsoc_i2c_stat_nack) - dev_dbg(&siic->adapter.dev, "ack not received "); - else - dev_err(&siic->adapter.dev, "i2c error "); - - /* - * due to hardware anomaly, we need to reset i2c earlier after - * we get noack while accessing non-existing clients, otherwise - * we will get errors even we access existing clients later - */ - writel(readl(siic->base + sirfsoc_i2c_ctrl) | sirfsoc_i2c_reset, - siic->base + sirfsoc_i2c_ctrl); - while (readl(siic->base + sirfsoc_i2c_ctrl) & sirfsoc_i2c_reset) - cpu_relax(); - - complete(&siic->done); - } else if (i2c_stat & sirfsoc_i2c_stat_cmd_done) { - /* cmd buffer execution complete */ - if (siic->msg_read) - i2c_sirfsoc_read_data(siic); - if (siic->finished_len == siic->msg_len) - complete(&siic->done); - else /* fill a new cmd buffer for left data */ - i2c_sirfsoc_queue_cmd(siic); - - writel(sirfsoc_i2c_stat_cmd_done, siic->base + sirfsoc_i2c_status); - } - - return irq_handled; -} - -static void i2c_sirfsoc_set_address(struct sirfsoc_i2c *siic, - struct i2c_msg *msg) -{ - unsigned char addr; - u32 regval = sirfsoc_i2c_start | sirfsoc_i2c_cmd_rp(0) | sirfsoc_i2c_write; - - /* no data and last message -> add stop */ - if (siic->last && (msg->len == 0)) - regval |= sirfsoc_i2c_stop; - - writel(regval, siic->base + sirfsoc_i2c_cmd(siic->cmd_ptr++)); - - addr = i2c_8bit_addr_from_msg(msg); - - /* reverse direction bit */ - if (msg->flags & i2c_m_rev_dir_addr) - addr ^= 1; - - writel(addr, siic->base + sirfsoc_i2c_cmd(siic->cmd_ptr++)); -} - -static int i2c_sirfsoc_xfer_msg(struct sirfsoc_i2c *siic, struct i2c_msg *msg) -{ - u32 regval = readl(siic->base + sirfsoc_i2c_ctrl); - /* timeout waiting for the xfer to finish or fail */ - int timeout = msecs_to_jiffies((msg->len + 1) * 50); - - i2c_sirfsoc_set_address(siic, msg); - - writel(regval | sirfsoc_i2c_cmd_done_en | sirfsoc_i2c_err_int_en, - siic->base + sirfsoc_i2c_ctrl); - i2c_sirfsoc_queue_cmd(siic); - - if (wait_for_completion_timeout(&siic->done, timeout) == 0) { - siic->err_status = sirfsoc_i2c_err_timeout; - dev_err(&siic->adapter.dev, "transfer timeout "); - } - - writel(regval & ~(sirfsoc_i2c_cmd_done_en | sirfsoc_i2c_err_int_en), - siic->base + sirfsoc_i2c_ctrl); - writel(0, siic->base + sirfsoc_i2c_cmd_start); - - /* i2c control doesn't response, reset it */ - if (siic->err_status == sirfsoc_i2c_err_timeout) { - writel(readl(siic->base + sirfsoc_i2c_ctrl) | sirfsoc_i2c_reset, - siic->base + sirfsoc_i2c_ctrl); - while (readl(siic->base + sirfsoc_i2c_ctrl) & sirfsoc_i2c_reset) - cpu_relax(); - } - return siic->err_status ? -eagain : 0; -} - -static u32 i2c_sirfsoc_func(struct i2c_adapter *adap) -{ - return i2c_func_i2c | i2c_func_smbus_emul; -} - -static int i2c_sirfsoc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, - int num) -{ - struct sirfsoc_i2c *siic = adap->algo_data; - int i, ret; - - clk_enable(siic->clk); - - for (i = 0; i < num; i++) { - siic->buf = msgs[i].buf; - siic->msg_len = msgs[i].len; - siic->msg_read = !!(msgs[i].flags & i2c_m_rd); - siic->err_status = 0; - siic->cmd_ptr = 0; - siic->finished_len = 0; - siic->last = (i == (num - 1)); - - ret = i2c_sirfsoc_xfer_msg(siic, &msgs[i]); - if (ret) { - clk_disable(siic->clk); - return ret; - } - } - - clk_disable(siic->clk); - return num; -} - -/* i2c algorithms associated with this master controller driver */ -static const struct i2c_algorithm i2c_sirfsoc_algo = { - .master_xfer = i2c_sirfsoc_xfer, - .functionality = i2c_sirfsoc_func, -}; - -static int i2c_sirfsoc_probe(struct platform_device *pdev) -{ - struct sirfsoc_i2c *siic; - struct i2c_adapter *adap; - struct clk *clk; - int bitrate; - int ctrl_speed; - int irq; - - int err; - u32 regval; - - clk = clk_get(&pdev->dev, null); - if (is_err(clk)) { - err = ptr_err(clk); - dev_err(&pdev->dev, "clock get failed "); - goto err_get_clk; - } - - err = clk_prepare(clk); - if (err) { - dev_err(&pdev->dev, "clock prepare failed "); - goto err_clk_prep; - } - - err = clk_enable(clk); - if (err) { - dev_err(&pdev->dev, "clock enable failed "); - goto err_clk_en; - } - - ctrl_speed = clk_get_rate(clk); - - siic = devm_kzalloc(&pdev->dev, sizeof(*siic), gfp_kernel); - if (!siic) { - err = -enomem; - goto out; - } - adap = &siic->adapter; - adap->class = i2c_class_deprecated; - - siic->base = devm_platform_ioremap_resource(pdev, 0); - if (is_err(siic->base)) { - err = ptr_err(siic->base); - goto out; - } - - irq = platform_get_irq(pdev, 0); - if (irq < 0) { - err = irq; - goto out; - } - err = devm_request_irq(&pdev->dev, irq, i2c_sirfsoc_irq, 0, - dev_name(&pdev->dev), siic); - if (err) - goto out; - - adap->algo = &i2c_sirfsoc_algo; - adap->algo_data = siic; - adap->retries = 3; - - adap->dev.of_node = pdev->dev.of_node; - adap->dev.parent = &pdev->dev; - adap->nr = pdev->id; - - strlcpy(adap->name, "sirfsoc-i2c", sizeof(adap->name)); - - platform_set_drvdata(pdev, adap); - init_completion(&siic->done); - - /* controller initialisation */ - - writel(sirfsoc_i2c_reset, siic->base + sirfsoc_i2c_ctrl); - while (readl(siic->base + sirfsoc_i2c_ctrl) & sirfsoc_i2c_reset) - cpu_relax(); - writel(sirfsoc_i2c_core_en | sirfsoc_i2c_master_mode, - siic->base + sirfsoc_i2c_ctrl); - - siic->clk = clk; - - err = of_property_read_u32(pdev->dev.of_node, - "clock-frequency", &bitrate); - if (err < 0) - bitrate = i2c_max_standard_mode_freq; - - /* - * due to some hardware design issues, we need to tune the formula. - * since i2c is open drain interface that allows the slave to - * stall the transaction by holding the scl line at '0', the rtl - * implementation is waiting for scl feedback from the pin after - * setting it to high-z ('1'). this wait adds to the high-time - * interval counter few cycles of the input synchronization - * (depending on the scl_filter_reg field), and also the time it - * takes for the board pull-up resistor to rise the scl line. - * for slow scl settings these additions are negligible, - * but they start to affect the speed when clock is set to faster - * frequencies. - * through the actual tests, use the different user_div value(which - * in the divider formula 'fio / (fi2c * user_div)') to adapt - * the different ranges of i2c bus clock frequency, to make the scl - * more accurate. - */ - if (bitrate <= 30000) - regval = ctrl_speed / (bitrate * 5); - else if (bitrate > 30000 && bitrate <= 280000) - regval = (2 * ctrl_speed) / (bitrate * 11); - else - regval = ctrl_speed / (bitrate * 6); - - writel(regval, siic->base + sirfsoc_i2c_clk_ctrl); - if (regval > 0xff) - writel(0xff, siic->base + sirfsoc_i2c_sda_delay); - else - writel(regval, siic->base + sirfsoc_i2c_sda_delay); - - err = i2c_add_numbered_adapter(adap); - if (err < 0) - goto out; - - clk_disable(clk); - - dev_info(&pdev->dev, " i2c adapter ready to operate "); - - return 0; - -out: - clk_disable(clk); -err_clk_en: - clk_unprepare(clk); -err_clk_prep: - clk_put(clk); -err_get_clk: - return err; -} - -static int i2c_sirfsoc_remove(struct platform_device *pdev) -{ - struct i2c_adapter *adapter = platform_get_drvdata(pdev); - struct sirfsoc_i2c *siic = adapter->algo_data; - - writel(sirfsoc_i2c_reset, siic->base + sirfsoc_i2c_ctrl); - i2c_del_adapter(adapter); - clk_unprepare(siic->clk); - clk_put(siic->clk); - return 0; -} - -#ifdef config_pm -static int i2c_sirfsoc_suspend(struct device *dev) -{ - struct i2c_adapter *adapter = dev_get_drvdata(dev); - struct sirfsoc_i2c *siic = adapter->algo_data; - - clk_enable(siic->clk); - siic->sda_delay = readl(siic->base + sirfsoc_i2c_sda_delay); - siic->clk_div = readl(siic->base + sirfsoc_i2c_clk_ctrl); - clk_disable(siic->clk); - return 0; -} - -static int i2c_sirfsoc_resume(struct device *dev) -{ - struct i2c_adapter *adapter = dev_get_drvdata(dev); - struct sirfsoc_i2c *siic = adapter->algo_data; - - clk_enable(siic->clk); - writel(sirfsoc_i2c_reset, siic->base + sirfsoc_i2c_ctrl); - while (readl(siic->base + sirfsoc_i2c_ctrl) & sirfsoc_i2c_reset) - cpu_relax(); - writel(sirfsoc_i2c_core_en | sirfsoc_i2c_master_mode, - siic->base + sirfsoc_i2c_ctrl); - writel(siic->clk_div, siic->base + sirfsoc_i2c_clk_ctrl); - writel(siic->sda_delay, siic->base + sirfsoc_i2c_sda_delay); - clk_disable(siic->clk); - return 0; -} - -static const struct dev_pm_ops i2c_sirfsoc_pm_ops = { - .suspend = i2c_sirfsoc_suspend, - .resume = i2c_sirfsoc_resume, -}; -#endif - -static const struct of_device_id sirfsoc_i2c_of_match[] = { - { .compatible = "sirf,prima2-i2c", }, - {}, -}; -module_device_table(of, sirfsoc_i2c_of_match); - -static struct platform_driver i2c_sirfsoc_driver = { - .driver = { - .name = "sirfsoc_i2c", -#ifdef config_pm - .pm = &i2c_sirfsoc_pm_ops, -#endif - .of_match_table = sirfsoc_i2c_of_match, - }, - .probe = i2c_sirfsoc_probe, - .remove = i2c_sirfsoc_remove, -}; -module_platform_driver(i2c_sirfsoc_driver); - -module_description("sirf soc i2c master controller driver"); -module_author("zhiwu song <zhiwu.song@csr.com>"); -module_author("xiangzhen ye <xiangzhen.ye@csr.com>"); -module_license("gpl v2");
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Inter-Integrated Circuit (I2C + I3C)
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2cea84ddae1cc3af3969bfeae015aa303bf6e08d
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arnd bergmann barry song baohua kernel org
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documentation
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devicetree
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bindings, busses, i2c
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i2c: remove u300 bus driver
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the st-ericsson u300 platform is getting removed, so this driver is no longer needed.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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remove u300 bus driver
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
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[]
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['txt', 'kconfig', 'c', 'makefile']
| 4
| 0
| 1,037
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--- diff --git a/documentation/devicetree/bindings/i2c/i2c-stu300.txt b/documentation/devicetree/bindings/i2c/i2c-stu300.txt --- a/documentation/devicetree/bindings/i2c/i2c-stu300.txt +++ /dev/null -st microelectronics ddc i2c - -required properties : -- compatible : must be "st,ddci2c" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: interrupt number to the cpu. -- #address-cells = <1>; -- #size-cells = <0>; - -optional properties: -- child nodes conforming to i2c bus binding - -examples : - diff --git a/drivers/i2c/busses/kconfig b/drivers/i2c/busses/kconfig --- a/drivers/i2c/busses/kconfig +++ b/drivers/i2c/busses/kconfig -config i2c_stu300 - tristate "st microelectronics ddc i2c interface" - depends on mach_u300 || compile_test - default y if mach_u300 - help - if you say yes to this option, support will be included for the - i2c interface from st microelectronics simply called "ddc i2c" - supporting both i2c and ddc, used in e.g. the u300 series - mobile platforms. - - this driver can also be built as a module. if so, the module - will be called i2c-stu300. - diff --git a/drivers/i2c/busses/makefile b/drivers/i2c/busses/makefile --- a/drivers/i2c/busses/makefile +++ b/drivers/i2c/busses/makefile -obj-$(config_i2c_stu300) += i2c-stu300.o diff --git a/drivers/i2c/busses/i2c-stu300.c b/drivers/i2c/busses/i2c-stu300.c --- a/drivers/i2c/busses/i2c-stu300.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * copyright (c) 2007-2012 st-ericsson ab - * st ddc i2c master mode driver, used in e.g. u300 series platforms. - * author: linus walleij <linus.walleij@stericsson.com> - * author: jonas aaberg <jonas.aberg@stericsson.com> - */ -#include <linux/init.h> -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/delay.h> -#include <linux/i2c.h> -#include <linux/spinlock.h> -#include <linux/completion.h> -#include <linux/err.h> -#include <linux/interrupt.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/slab.h> - -/* the name of this kernel module */ -#define name "stu300" - -/* cr (control register) 8bit (r/w) */ -#define i2c_cr (0x00000000) -#define i2c_cr_reset_value (0x00) -#define i2c_cr_reset_umask (0x00) -#define i2c_cr_ddc1_enable (0x80) -#define i2c_cr_trans_enable (0x40) -#define i2c_cr_peripheral_enable (0x20) -#define i2c_cr_ddc2b_enable (0x10) -#define i2c_cr_start_enable (0x08) -#define i2c_cr_ack_enable (0x04) -#define i2c_cr_stop_enable (0x02) -#define i2c_cr_interrupt_enable (0x01) -/* sr1 (status register 1) 8bit (r/-) */ -#define i2c_sr1 (0x00000004) -#define i2c_sr1_reset_value (0x00) -#define i2c_sr1_reset_umask (0x00) -#define i2c_sr1_evf_ind (0x80) -#define i2c_sr1_add10_ind (0x40) -#define i2c_sr1_tra_ind (0x20) -#define i2c_sr1_busy_ind (0x10) -#define i2c_sr1_btf_ind (0x08) -#define i2c_sr1_adsl_ind (0x04) -#define i2c_sr1_msl_ind (0x02) -#define i2c_sr1_sb_ind (0x01) -/* sr2 (status register 2) 8bit (r/-) */ -#define i2c_sr2 (0x00000008) -#define i2c_sr2_reset_value (0x00) -#define i2c_sr2_reset_umask (0x40) -#define i2c_sr2_mask (0xbf) -#define i2c_sr2_sclfal_ind (0x80) -#define i2c_sr2_endad_ind (0x20) -#define i2c_sr2_af_ind (0x10) -#define i2c_sr2_stopf_ind (0x08) -#define i2c_sr2_arlo_ind (0x04) -#define i2c_sr2_berr_ind (0x02) -#define i2c_sr2_ddc2bf_ind (0x01) -/* ccr (clock control register) 8bit (r/w) */ -#define i2c_ccr (0x0000000c) -#define i2c_ccr_reset_value (0x00) -#define i2c_ccr_reset_umask (0x00) -#define i2c_ccr_mask (0xff) -#define i2c_ccr_fmsm (0x80) -#define i2c_ccr_cc_mask (0x7f) -/* oar1 (own address register 1) 8bit (r/w) */ -#define i2c_oar1 (0x00000010) -#define i2c_oar1_reset_value (0x00) -#define i2c_oar1_reset_umask (0x00) -#define i2c_oar1_add_mask (0xff) -/* oar2 (own address register 2) 8bit (r/w) */ -#define i2c_oar2 (0x00000014) -#define i2c_oar2_reset_value (0x40) -#define i2c_oar2_reset_umask (0x19) -#define i2c_oar2_mask (0xe6) -#define i2c_oar2_fr_25_10mhz (0x00) -#define i2c_oar2_fr_10_1667mhz (0x20) -#define i2c_oar2_fr_1667_2667mhz (0x40) -#define i2c_oar2_fr_2667_40mhz (0x60) -#define i2c_oar2_fr_40_5333mhz (0x80) -#define i2c_oar2_fr_5333_66mhz (0xa0) -#define i2c_oar2_fr_66_80mhz (0xc0) -#define i2c_oar2_fr_80_100mhz (0xe0) -#define i2c_oar2_fr_mask (0xe0) -#define i2c_oar2_add_mask (0x06) -/* dr (data register) 8bit (r/w) */ -#define i2c_dr (0x00000018) -#define i2c_dr_reset_value (0x00) -#define i2c_dr_reset_umask (0xff) -#define i2c_dr_d_mask (0xff) -/* eccr (extended clock control register) 8bit (r/w) */ -#define i2c_eccr (0x0000001c) -#define i2c_eccr_reset_value (0x00) -#define i2c_eccr_reset_umask (0xe0) -#define i2c_eccr_mask (0x1f) -#define i2c_eccr_cc_mask (0x1f) - -/* - * these events are more or less responses to commands - * sent into the hardware, presumably reflecting the state - * of an internal state machine. - */ -enum stu300_event { - stu300_event_none = 0, - stu300_event_1, - stu300_event_2, - stu300_event_3, - stu300_event_4, - stu300_event_5, - stu300_event_6, - stu300_event_7, - stu300_event_8, - stu300_event_9 -}; - -enum stu300_error { - stu300_error_none = 0, - stu300_error_acknowledge_failure, - stu300_error_bus_error, - stu300_error_arbitration_lost, - stu300_error_unknown -}; - -/* timeout waiting for the controller to respond */ -#define stu300_timeout (msecs_to_jiffies(1000)) - -/* - * the number of address send athemps tried before giving up. - * if the first one fails it seems like 5 to 8 attempts are required. - */ -#define num_addr_resend_attempts 12 - -/* i2c clock speed, in hz 0-400khz*/ -static unsigned int scl_frequency = i2c_max_standard_mode_freq; -module_param(scl_frequency, uint, 0644); - -/** - * struct stu300_dev - the stu300 driver state holder - * @pdev: parent platform device - * @adapter: corresponding i2c adapter - * @clk: hardware block clock - * @irq: assigned interrupt line - * @cmd_issue_lock: this locks the following cmd_ variables - * @cmd_complete: acknowledge completion for an i2c command - * @cmd_event: expected event coming in as a response to a command - * @cmd_err: error code as response to a command - * @speed: current bus speed in hz - * @msg_index: index of current message - * @msg_len: length of current message - */ - -struct stu300_dev { - struct platform_device *pdev; - struct i2c_adapter adapter; - void __iomem *virtbase; - struct clk *clk; - int irq; - spinlock_t cmd_issue_lock; - struct completion cmd_complete; - enum stu300_event cmd_event; - enum stu300_error cmd_err; - unsigned int speed; - int msg_index; - int msg_len; -}; - -/* local forward function declarations */ -static int stu300_init_hw(struct stu300_dev *dev); - -/* - * the block needs writes in both msw and lsw in order - * for all data lines to reach their destination. - */ -static inline void stu300_wr8(u32 value, void __iomem *address) -{ - writel((value << 16) | value, address); -} - -/* - * this merely masks off the duplicates which appear - * in bytes 1-3. you _must_ use 32-bit bus access on this - * device, else it will not work. - */ -static inline u32 stu300_r8(void __iomem *address) -{ - return readl(address) & 0x000000ffu; -} - -static void stu300_irq_enable(struct stu300_dev *dev) -{ - u32 val; - val = stu300_r8(dev->virtbase + i2c_cr); - val |= i2c_cr_interrupt_enable; - /* twice paranoia (possible hw glitch) */ - stu300_wr8(val, dev->virtbase + i2c_cr); - stu300_wr8(val, dev->virtbase + i2c_cr); -} - -static void stu300_irq_disable(struct stu300_dev *dev) -{ - u32 val; - val = stu300_r8(dev->virtbase + i2c_cr); - val &= ~i2c_cr_interrupt_enable; - /* twice paranoia (possible hw glitch) */ - stu300_wr8(val, dev->virtbase + i2c_cr); - stu300_wr8(val, dev->virtbase + i2c_cr); -} - - -/* - * tells whether a certain event or events occurred in - * response to a command. the events represent states in - * the internal state machine of the hardware. the events - * are not very well described in the hardware - * documentation and can only be treated as abstract state - * machine states. - * - * @ret 0 = event has not occurred or unknown error, any - * other value means the correct event occurred or an error. - */ - -static int stu300_event_occurred(struct stu300_dev *dev, - enum stu300_event mr_event) { - u32 status1; - u32 status2; - - /* what event happened? */ - status1 = stu300_r8(dev->virtbase + i2c_sr1); - - if (!(status1 & i2c_sr1_evf_ind)) - /* no event at all */ - return 0; - - status2 = stu300_r8(dev->virtbase + i2c_sr2); - - /* block any multiple interrupts */ - stu300_irq_disable(dev); - - /* check for errors first */ - if (status2 & i2c_sr2_af_ind) { - dev->cmd_err = stu300_error_acknowledge_failure; - return 1; - } else if (status2 & i2c_sr2_berr_ind) { - dev->cmd_err = stu300_error_bus_error; - return 1; - } else if (status2 & i2c_sr2_arlo_ind) { - dev->cmd_err = stu300_error_arbitration_lost; - return 1; - } - - switch (mr_event) { - case stu300_event_1: - if (status1 & i2c_sr1_adsl_ind) - return 1; - break; - case stu300_event_2: - case stu300_event_3: - case stu300_event_7: - case stu300_event_8: - if (status1 & i2c_sr1_btf_ind) { - return 1; - } - break; - case stu300_event_4: - if (status2 & i2c_sr2_stopf_ind) - return 1; - break; - case stu300_event_5: - if (status1 & i2c_sr1_sb_ind) - /* clear start bit */ - return 1; - break; - case stu300_event_6: - if (status2 & i2c_sr2_endad_ind) { - /* first check for any errors */ - return 1; - } - break; - case stu300_event_9: - if (status1 & i2c_sr1_add10_ind) - return 1; - break; - default: - break; - } - /* if we get here, we're on thin ice. - * here we are in a status where we have - * gotten a response that does not match - * what we requested. - */ - dev->cmd_err = stu300_error_unknown; - dev_err(&dev->pdev->dev, - "unhandled interrupt! %d sr1: 0x%x sr2: 0x%x ", - mr_event, status1, status2); - return 0; -} - -static irqreturn_t stu300_irh(int irq, void *data) -{ - struct stu300_dev *dev = data; - int res; - - /* just make sure that the block is clocked */ - clk_enable(dev->clk); - - /* see if this was what we were waiting for */ - spin_lock(&dev->cmd_issue_lock); - - res = stu300_event_occurred(dev, dev->cmd_event); - if (res || dev->cmd_err != stu300_error_none) - complete(&dev->cmd_complete); - - spin_unlock(&dev->cmd_issue_lock); - - clk_disable(dev->clk); - - return irq_handled; -} - -/* - * sends a command and then waits for the bits masked by *flagmask* - * to go high or low by irq awaiting. - */ -static int stu300_start_and_await_event(struct stu300_dev *dev, - u8 cr_value, - enum stu300_event mr_event) -{ - int ret; - - /* lock command issue, fill in an event we wait for */ - spin_lock_irq(&dev->cmd_issue_lock); - init_completion(&dev->cmd_complete); - dev->cmd_err = stu300_error_none; - dev->cmd_event = mr_event; - spin_unlock_irq(&dev->cmd_issue_lock); - - /* turn on interrupt, send command and wait. */ - cr_value |= i2c_cr_interrupt_enable; - stu300_wr8(cr_value, dev->virtbase + i2c_cr); - ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, - stu300_timeout); - if (ret < 0) { - dev_err(&dev->pdev->dev, - "wait_for_completion_interruptible_timeout() " - "returned %d waiting for event %04x ", ret, mr_event); - return ret; - } - - if (ret == 0) { - dev_err(&dev->pdev->dev, "controller timed out " - "waiting for event %d, reinit hardware ", mr_event); - (void) stu300_init_hw(dev); - return -etimedout; - } - - if (dev->cmd_err != stu300_error_none) { - dev_err(&dev->pdev->dev, "controller (start) " - "error %d waiting for event %d, reinit hardware ", - dev->cmd_err, mr_event); - (void) stu300_init_hw(dev); - return -eio; - } - - return 0; -} - -/* - * this waits for a flag to be set, if it is not set on entry, an interrupt is - * configured to wait for the flag using a completion. - */ -static int stu300_await_event(struct stu300_dev *dev, - enum stu300_event mr_event) -{ - int ret; - - /* is it already here? */ - spin_lock_irq(&dev->cmd_issue_lock); - dev->cmd_err = stu300_error_none; - dev->cmd_event = mr_event; - - init_completion(&dev->cmd_complete); - - /* turn on the i2c interrupt for current operation */ - stu300_irq_enable(dev); - - /* unlock the command block and wait for the event to occur */ - spin_unlock_irq(&dev->cmd_issue_lock); - - ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, - stu300_timeout); - if (ret < 0) { - dev_err(&dev->pdev->dev, - "wait_for_completion_interruptible_timeout()" - "returned %d waiting for event %04x ", ret, mr_event); - return ret; - } - - if (ret == 0) { - if (mr_event != stu300_event_6) { - dev_err(&dev->pdev->dev, "controller " - "timed out waiting for event %d, reinit " - "hardware ", mr_event); - (void) stu300_init_hw(dev); - } - return -etimedout; - } - - if (dev->cmd_err != stu300_error_none) { - if (mr_event != stu300_event_6) { - dev_err(&dev->pdev->dev, "controller " - "error (await_event) %d waiting for event %d, " - "reinit hardware ", dev->cmd_err, mr_event); - (void) stu300_init_hw(dev); - } - return -eio; - } - - return 0; -} - -/* - * waits for the busy bit to go low by repeated polling. - */ -#define busy_release_attempts 10 -static int stu300_wait_while_busy(struct stu300_dev *dev) -{ - unsigned long timeout; - int i; - - for (i = 0; i < busy_release_attempts; i++) { - timeout = jiffies + stu300_timeout; - - while (!time_after(jiffies, timeout)) { - /* is not busy? */ - if ((stu300_r8(dev->virtbase + i2c_sr1) & - i2c_sr1_busy_ind) == 0) - return 0; - msleep(1); - } - - dev_err(&dev->pdev->dev, "transaction timed out " - "waiting for device to be free (not busy). " - "attempt: %d ", i+1); - - dev_err(&dev->pdev->dev, "base address = " - "0x%p, reinit hardware ", dev->virtbase); - - (void) stu300_init_hw(dev); - } - - dev_err(&dev->pdev->dev, "giving up after %d attempts " - "to reset the bus. ", busy_release_attempts); - - return -etimedout; -} - -struct stu300_clkset { - unsigned long rate; - u32 setting; -}; - -static const struct stu300_clkset stu300_clktable[] = { - { 0, 0xffu }, - { 2500000, i2c_oar2_fr_25_10mhz }, - { 10000000, i2c_oar2_fr_10_1667mhz }, - { 16670000, i2c_oar2_fr_1667_2667mhz }, - { 26670000, i2c_oar2_fr_2667_40mhz }, - { 40000000, i2c_oar2_fr_40_5333mhz }, - { 53330000, i2c_oar2_fr_5333_66mhz }, - { 66000000, i2c_oar2_fr_66_80mhz }, - { 80000000, i2c_oar2_fr_80_100mhz }, - { 100000000, 0xffu }, -}; - - -static int stu300_set_clk(struct stu300_dev *dev, unsigned long clkrate) -{ - - u32 val; - int i = 0; - - /* locate the appropriate clock setting */ - while (i < array_size(stu300_clktable) - 1 && - stu300_clktable[i].rate < clkrate) - i++; - - if (stu300_clktable[i].setting == 0xffu) { - dev_err(&dev->pdev->dev, "too %s clock rate requested " - "(%lu hz). ", i ? "high" : "low", clkrate); - return -einval; - } - - stu300_wr8(stu300_clktable[i].setting, - dev->virtbase + i2c_oar2); - - dev_dbg(&dev->pdev->dev, "clock rate %lu hz, i2c bus speed %d hz " - "virtbase %p ", clkrate, dev->speed, dev->virtbase); - - if (dev->speed > i2c_max_standard_mode_freq) - /* fast mode i2c */ - val = ((clkrate/dev->speed) - 9)/3 + 1; - else - /* standard mode i2c */ - val = ((clkrate/dev->speed) - 7)/2 + 1; - - /* according to spec the divider must be > 2 */ - if (val < 0x002) { - dev_err(&dev->pdev->dev, "too low clock rate (%lu hz). ", - clkrate); - return -einval; - } - - /* we have 12 bits clock divider only! */ - if (val & 0xfffff000u) { - dev_err(&dev->pdev->dev, "too high clock rate (%lu hz). ", - clkrate); - return -einval; - } - - if (dev->speed > i2c_max_standard_mode_freq) { - /* cc6..cc0 */ - stu300_wr8((val & i2c_ccr_cc_mask) | i2c_ccr_fmsm, - dev->virtbase + i2c_ccr); - dev_dbg(&dev->pdev->dev, "set clock divider to 0x%08x, " - "fast mode i2c ", val); - } else { - /* cc6..cc0 */ - stu300_wr8((val & i2c_ccr_cc_mask), - dev->virtbase + i2c_ccr); - dev_dbg(&dev->pdev->dev, "set clock divider to " - "0x%08x, standard mode i2c ", val); - } - - /* cc11..cc7 */ - stu300_wr8(((val >> 7) & 0x1f), - dev->virtbase + i2c_eccr); - - return 0; -} - - -static int stu300_init_hw(struct stu300_dev *dev) -{ - u32 dummy; - unsigned long clkrate; - int ret; - - /* disable controller */ - stu300_wr8(0x00, dev->virtbase + i2c_cr); - /* - * set own address to some default value (0x00). - * we do not support slave mode anyway. - */ - stu300_wr8(0x00, dev->virtbase + i2c_oar1); - /* - * the i2c controller only operates properly in 26 mhz but we - * program this driver as if we didn't know. this will also set the two - * high bits of the own address to zero as well. - * there is no known hardware issue with running in 13 mhz - * however, speeds over 200 khz are not used. - */ - clkrate = clk_get_rate(dev->clk); - ret = stu300_set_clk(dev, clkrate); - - if (ret) - return ret; - /* - * enable block, do it twice (hardware glitch) - * setting bit 7 can enable ddc mode. (not used currently.) - */ - stu300_wr8(i2c_cr_peripheral_enable, - dev->virtbase + i2c_cr); - stu300_wr8(i2c_cr_peripheral_enable, - dev->virtbase + i2c_cr); - /* make a dummy read of the status register sr1 & sr2 */ - dummy = stu300_r8(dev->virtbase + i2c_sr2); - dummy = stu300_r8(dev->virtbase + i2c_sr1); - - return 0; -} - - - -/* send slave address. */ -static int stu300_send_address(struct stu300_dev *dev, - struct i2c_msg *msg, int resend) -{ - u32 val; - int ret; - - if (msg->flags & i2c_m_ten) { - /* this is probably how 10 bit addresses look */ - val = (0xf0 | (((u32) msg->addr & 0x300) >> 7)) & - i2c_dr_d_mask; - if (msg->flags & i2c_m_rd) - /* this is the direction bit */ - val |= 0x01; - } else { - val = i2c_8bit_addr_from_msg(msg); - } - - if (resend) { - if (msg->flags & i2c_m_rd) - dev_dbg(&dev->pdev->dev, "read resend "); - else - dev_dbg(&dev->pdev->dev, "write resend "); - } - - stu300_wr8(val, dev->virtbase + i2c_dr); - - /* for 10bit addressing, await 10bit request (event 9) */ - if (msg->flags & i2c_m_ten) { - ret = stu300_await_event(dev, stu300_event_9); - /* - * the slave device wants a 10bit address, send the rest - * of the bits (the lsbits) - */ - val = msg->addr & i2c_dr_d_mask; - /* this clears "event 9" */ - stu300_wr8(val, dev->virtbase + i2c_dr); - if (ret != 0) - return ret; - } - /* fixme: why no else here? two events for 10bit? - * await event 6 (normal) or event 9 (10bit) - */ - - if (resend) - dev_dbg(&dev->pdev->dev, "await event 6 "); - ret = stu300_await_event(dev, stu300_event_6); - - /* - * clear any pending event 6 no matter what happened during - * await_event. - */ - val = stu300_r8(dev->virtbase + i2c_cr); - val |= i2c_cr_peripheral_enable; - stu300_wr8(val, dev->virtbase + i2c_cr); - - return ret; -} - -static int stu300_xfer_msg(struct i2c_adapter *adap, - struct i2c_msg *msg, int stop) -{ - u32 cr; - u32 val; - u32 i; - int ret; - int attempts = 0; - struct stu300_dev *dev = i2c_get_adapdata(adap); - - clk_enable(dev->clk); - - /* remove this if (0) to trace each and every message. */ - if (0) { - dev_dbg(&dev->pdev->dev, "i2c message to: 0x%04x, len: %d, " - "flags: 0x%04x, stop: %d ", - msg->addr, msg->len, msg->flags, stop); - } - - /* - * for some reason, sending the address sometimes fails when running - * on the 13 mhz clock. no interrupt arrives. this is a work around, - * which tries to restart and send the address up to 10 times before - * really giving up. usually 5 to 8 attempts are enough. - */ - do { - if (attempts) - dev_dbg(&dev->pdev->dev, "wait while busy "); - /* check that the bus is free, or wait until some timeout */ - ret = stu300_wait_while_busy(dev); - if (ret != 0) - goto exit_disable; - - if (attempts) - dev_dbg(&dev->pdev->dev, "re-int hw "); - /* - * according to st, there is no problem if the clock is - * changed between 13 and 26 mhz during a transfer. - */ - ret = stu300_init_hw(dev); - if (ret) - goto exit_disable; - - /* send a start condition */ - cr = i2c_cr_peripheral_enable; - /* setting the start bit puts the block in master mode */ - if (!(msg->flags & i2c_m_nostart)) - cr |= i2c_cr_start_enable; - if ((msg->flags & i2c_m_rd) && (msg->len > 1)) - /* on read more than 1 byte, we need ack. */ - cr |= i2c_cr_ack_enable; - /* check that it gets through */ - if (!(msg->flags & i2c_m_nostart)) { - if (attempts) - dev_dbg(&dev->pdev->dev, "send start event "); - ret = stu300_start_and_await_event(dev, cr, - stu300_event_5); - } - - if (attempts) - dev_dbg(&dev->pdev->dev, "send address "); - - if (ret == 0) - /* send address */ - ret = stu300_send_address(dev, msg, attempts != 0); - - if (ret != 0) { - attempts++; - dev_dbg(&dev->pdev->dev, "failed sending address, " - "retrying. attempt: %d msg_index: %d/%d ", - attempts, dev->msg_index, dev->msg_len); - } - - } while (ret != 0 && attempts < num_addr_resend_attempts); - - if (attempts < num_addr_resend_attempts && attempts > 0) { - dev_dbg(&dev->pdev->dev, "managed to get address " - "through after %d attempts ", attempts); - } else if (attempts == num_addr_resend_attempts) { - dev_dbg(&dev->pdev->dev, "i give up, tried %d times " - "to resend address. ", - num_addr_resend_attempts); - goto exit_disable; - } - - - if (msg->flags & i2c_m_rd) { - /* read: we read the actual bytes one at a time */ - for (i = 0; i < msg->len; i++) { - if (i == msg->len-1) { - /* - * disable ack and set stop condition before - * reading last byte - */ - val = i2c_cr_peripheral_enable; - - if (stop) - val |= i2c_cr_stop_enable; - - stu300_wr8(val, - dev->virtbase + i2c_cr); - } - /* wait for this byte... */ - ret = stu300_await_event(dev, stu300_event_7); - if (ret != 0) - goto exit_disable; - /* this clears event 7 */ - msg->buf[i] = (u8) stu300_r8(dev->virtbase + i2c_dr); - } - } else { - /* write: we send the actual bytes one at a time */ - for (i = 0; i < msg->len; i++) { - /* write the byte */ - stu300_wr8(msg->buf[i], - dev->virtbase + i2c_dr); - /* check status */ - ret = stu300_await_event(dev, stu300_event_8); - /* next write to dr will clear event 8 */ - if (ret != 0) { - dev_err(&dev->pdev->dev, "error awaiting " - "event 8 (%d) ", ret); - goto exit_disable; - } - } - /* check nak */ - if (!(msg->flags & i2c_m_ignore_nak)) { - if (stu300_r8(dev->virtbase + i2c_sr2) & - i2c_sr2_af_ind) { - dev_err(&dev->pdev->dev, "i2c payload " - "send returned nak! "); - ret = -eio; - goto exit_disable; - } - } - if (stop) { - /* send stop condition */ - val = i2c_cr_peripheral_enable; - val |= i2c_cr_stop_enable; - stu300_wr8(val, dev->virtbase + i2c_cr); - } - } - - /* check that the bus is free, or wait until some timeout occurs */ - ret = stu300_wait_while_busy(dev); - if (ret != 0) { - dev_err(&dev->pdev->dev, "timeout waiting for transfer " - "to commence. "); - goto exit_disable; - } - - /* dummy read status registers */ - val = stu300_r8(dev->virtbase + i2c_sr2); - val = stu300_r8(dev->virtbase + i2c_sr1); - ret = 0; - - exit_disable: - /* disable controller */ - stu300_wr8(0x00, dev->virtbase + i2c_cr); - clk_disable(dev->clk); - return ret; -} - -static int stu300_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, - int num) -{ - int ret = -1; - int i; - - struct stu300_dev *dev = i2c_get_adapdata(adap); - dev->msg_len = num; - - for (i = 0; i < num; i++) { - /* - * another driver appears to send stop for each message, - * here we only do that for the last message. possibly some - * peripherals require this behaviour, then their drivers - * have to send single messages in order to get "stop" for - * each message. - */ - dev->msg_index = i; - - ret = stu300_xfer_msg(adap, &msgs[i], (i == (num - 1))); - - if (ret != 0) { - num = ret; - break; - } - } - - return num; -} - -static int stu300_xfer_todo(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) -{ - /* todo: implement polling for this case if need be. */ - warn(1, "%s: atomic transfers not implemented ", dev_name(&adap->dev)); - return -eopnotsupp; -} - -static u32 stu300_func(struct i2c_adapter *adap) -{ - /* this is the simplest thing you can think of... */ - return i2c_func_i2c | i2c_func_10bit_addr; -} - -static const struct i2c_algorithm stu300_algo = { - .master_xfer = stu300_xfer, - .master_xfer_atomic = stu300_xfer_todo, - .functionality = stu300_func, -}; - -static const struct i2c_adapter_quirks stu300_quirks = { - .flags = i2c_aq_no_zero_len, -}; - -static int stu300_probe(struct platform_device *pdev) -{ - struct stu300_dev *dev; - struct i2c_adapter *adap; - int bus_nr; - int ret = 0; - - dev = devm_kzalloc(&pdev->dev, sizeof(struct stu300_dev), gfp_kernel); - if (!dev) - return -enomem; - - bus_nr = pdev->id; - dev->clk = devm_clk_get(&pdev->dev, null); - if (is_err(dev->clk)) { - dev_err(&pdev->dev, "could not retrieve i2c bus clock "); - return ptr_err(dev->clk); - } - - dev->pdev = pdev; - dev->virtbase = devm_platform_ioremap_resource(pdev, 0); - dev_dbg(&pdev->dev, "initialize bus device i2c%d on virtual " - "base %p ", bus_nr, dev->virtbase); - if (is_err(dev->virtbase)) - return ptr_err(dev->virtbase); - - dev->irq = platform_get_irq(pdev, 0); - ret = devm_request_irq(&pdev->dev, dev->irq, stu300_irh, 0, name, dev); - if (ret < 0) - return ret; - - dev->speed = scl_frequency; - - clk_prepare_enable(dev->clk); - ret = stu300_init_hw(dev); - clk_disable(dev->clk); - if (ret != 0) { - dev_err(&dev->pdev->dev, "error initializing hardware. "); - return -eio; - } - - /* irq event handling initialization */ - spin_lock_init(&dev->cmd_issue_lock); - dev->cmd_event = stu300_event_none; - dev->cmd_err = stu300_error_none; - - adap = &dev->adapter; - adap->owner = this_module; - /* ddc class but actually often used for more generic i2c */ - adap->class = i2c_class_deprecated; - strlcpy(adap->name, "st microelectronics ddc i2c adapter", - sizeof(adap->name)); - adap->nr = bus_nr; - adap->algo = &stu300_algo; - adap->dev.parent = &pdev->dev; - adap->dev.of_node = pdev->dev.of_node; - adap->quirks = &stu300_quirks; - - i2c_set_adapdata(adap, dev); - - /* i2c device drivers may be active on return from add_adapter() */ - ret = i2c_add_numbered_adapter(adap); - if (ret) - return ret; - - platform_set_drvdata(pdev, dev); - dev_info(&pdev->dev, "st ddc i2c @ %p, irq %d ", - dev->virtbase, dev->irq); - - return 0; -} - -#ifdef config_pm_sleep -static int stu300_suspend(struct device *device) -{ - struct stu300_dev *dev = dev_get_drvdata(device); - - /* turn off everything */ - stu300_wr8(0x00, dev->virtbase + i2c_cr); - return 0; -} - -static int stu300_resume(struct device *device) -{ - int ret = 0; - struct stu300_dev *dev = dev_get_drvdata(device); - - clk_enable(dev->clk); - ret = stu300_init_hw(dev); - clk_disable(dev->clk); - - if (ret != 0) - dev_err(device, "error re-initializing hardware. "); - return ret; -} - -static simple_dev_pm_ops(stu300_pm, stu300_suspend, stu300_resume); -#define stu300_i2c_pm (&stu300_pm) -#else -#define stu300_i2c_pm null -#endif - -static int stu300_remove(struct platform_device *pdev) -{ - struct stu300_dev *dev = platform_get_drvdata(pdev); - - i2c_del_adapter(&dev->adapter); - /* turn off everything */ - stu300_wr8(0x00, dev->virtbase + i2c_cr); - return 0; -} - -static const struct of_device_id stu300_dt_match[] = { - { .compatible = "st,ddci2c" }, - {}, -}; -module_device_table(of, stu300_dt_match); - -static struct platform_driver stu300_i2c_driver = { - .driver = { - .name = name, - .pm = stu300_i2c_pm, - .of_match_table = stu300_dt_match, - }, - .probe = stu300_probe, - .remove = stu300_remove, - -}; - -static int __init stu300_init(void) -{ - return platform_driver_register(&stu300_i2c_driver); -} - -static void __exit stu300_exit(void) -{ - platform_driver_unregister(&stu300_i2c_driver); -} - -/* - * the systems using this bus often have very basic devices such - * as regulators on the i2c bus, so this needs to be loaded early. - * therefore it is registered in the subsys_initcall(). - */ -subsys_initcall(stu300_init); -module_exit(stu300_exit); - -module_author("linus walleij <linus.walleij@stericsson.com>"); -module_description("st micro ddc i2c adapter (" name ")"); -module_license("gpl"); -module_alias("platform:" name);
|
Inter-Integrated Circuit (I2C + I3C)
|
1059b2bcc683ab29c25d542af4902bfdb3f91b40
|
arnd bergmann linus walleij linus walleij linaro org
|
documentation
|
devicetree
|
bindings, busses, i2c
|
i2c: remove zte zx bus driver
|
the zte zx platform is getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove zte zx bus driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['txt', 'kconfig', 'c', 'makefile']
| 4
| 0
| 634
|
--- diff --git a/documentation/devicetree/bindings/i2c/i2c-zx2967.txt b/documentation/devicetree/bindings/i2c/i2c-zx2967.txt --- a/documentation/devicetree/bindings/i2c/i2c-zx2967.txt +++ /dev/null -zte zx2967 i2c controller - -required properties: - - compatible: must be "zte,zx296718-i2c" - - reg: physical address and length of the device registers - - interrupts: a single interrupt specifier - - clocks: clock for the device - - #address-cells: should be <1> - - #size-cells: should be <0> - - clock-frequency: the desired i2c bus clock frequency. - -examples: - - i2c@112000 { - compatible = "zte,zx296718-i2c"; - reg = <0x00112000 0x1000>; - interrupts = <gic_spi 112 irq_type_level_high>; - clocks = <&osc24m>; - #address-cells = <1> - #size-cells = <0>; - clock-frequency = <1600000>; - }; diff --git a/drivers/i2c/busses/kconfig b/drivers/i2c/busses/kconfig --- a/drivers/i2c/busses/kconfig +++ b/drivers/i2c/busses/kconfig -config i2c_zx2967 - tristate "zte zx2967 i2c support" - depends on arch_zx - default y - help - selecting this option will add zx2967 i2c driver. - this driver can also be built as a module. if so, the module will be - called i2c-zx2967. - diff --git a/drivers/i2c/busses/makefile b/drivers/i2c/busses/makefile --- a/drivers/i2c/busses/makefile +++ b/drivers/i2c/busses/makefile -obj-$(config_i2c_zx2967) += i2c-zx2967.o diff --git a/drivers/i2c/busses/i2c-zx2967.c b/drivers/i2c/busses/i2c-zx2967.c --- a/drivers/i2c/busses/i2c-zx2967.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * copyright (c) 2017 sanechips technology co., ltd. - * copyright 2017 linaro ltd. - * - * author: baoyou xie <baoyou.xie@linaro.org> - */ - -#include <linux/clk.h> -#include <linux/i2c.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include <linux/module.h> -#include <linux/platform_device.h> - -#define reg_cmd 0x04 -#define reg_devaddr_h 0x0c -#define reg_devaddr_l 0x10 -#define reg_clk_div_fs 0x14 -#define reg_clk_div_hs 0x18 -#define reg_wrconf 0x1c -#define reg_rdconf 0x20 -#define reg_data 0x24 -#define reg_stat 0x28 - -#define i2c_stop 0 -#define i2c_master bit(0) -#define i2c_addr_mode_ten bit(1) -#define i2c_irq_msk_enable bit(3) -#define i2c_rw_read bit(4) -#define i2c_cmb_rw_en bit(5) -#define i2c_start bit(6) - -#define i2c_addr_low_mask genmask(6, 0) -#define i2c_addr_low_shift 0 -#define i2c_addr_hi_mask genmask(2, 0) -#define i2c_addr_hi_shift 7 - -#define i2c_wfifo_reset bit(7) -#define i2c_rfifo_reset bit(7) - -#define i2c_irq_ack_clear bit(7) -#define i2c_int_mask genmask(6, 0) - -#define i2c_trans_done bit(0) -#define i2c_sr_edevice bit(1) -#define i2c_sr_edata bit(2) - -#define i2c_fifo_max 16 - -#define i2c_timeout msecs_to_jiffies(1000) - -#define dev(i2c) ((i2c)->adap.dev.parent) - -struct zx2967_i2c { - struct i2c_adapter adap; - struct clk *clk; - struct completion complete; - u32 clk_freq; - void __iomem *reg_base; - size_t residue; - int irq; - int msg_rd; - u8 *cur_trans; - u8 access_cnt; - int error; -}; - -static void zx2967_i2c_writel(struct zx2967_i2c *i2c, - u32 val, unsigned long reg) -{ - writel_relaxed(val, i2c->reg_base + reg); -} - -static u32 zx2967_i2c_readl(struct zx2967_i2c *i2c, unsigned long reg) -{ - return readl_relaxed(i2c->reg_base + reg); -} - -static void zx2967_i2c_writesb(struct zx2967_i2c *i2c, - void *data, unsigned long reg, int len) -{ - writesb(i2c->reg_base + reg, data, len); -} - -static void zx2967_i2c_readsb(struct zx2967_i2c *i2c, - void *data, unsigned long reg, int len) -{ - readsb(i2c->reg_base + reg, data, len); -} - -static void zx2967_i2c_start_ctrl(struct zx2967_i2c *i2c) -{ - u32 status; - u32 ctl; - - status = zx2967_i2c_readl(i2c, reg_stat); - status |= i2c_irq_ack_clear; - zx2967_i2c_writel(i2c, status, reg_stat); - - ctl = zx2967_i2c_readl(i2c, reg_cmd); - if (i2c->msg_rd) - ctl |= i2c_rw_read; - else - ctl &= ~i2c_rw_read; - ctl &= ~i2c_cmb_rw_en; - ctl |= i2c_start; - zx2967_i2c_writel(i2c, ctl, reg_cmd); -} - -static void zx2967_i2c_flush_fifos(struct zx2967_i2c *i2c) -{ - u32 offset; - u32 val; - - if (i2c->msg_rd) { - offset = reg_rdconf; - val = i2c_rfifo_reset; - } else { - offset = reg_wrconf; - val = i2c_wfifo_reset; - } - - val |= zx2967_i2c_readl(i2c, offset); - zx2967_i2c_writel(i2c, val, offset); -} - -static int zx2967_i2c_empty_rx_fifo(struct zx2967_i2c *i2c, u32 size) -{ - u8 val[i2c_fifo_max] = {0}; - int i; - - if (size > i2c_fifo_max) { - dev_err(dev(i2c), "fifo size %d over the max value %d ", - size, i2c_fifo_max); - return -einval; - } - - zx2967_i2c_readsb(i2c, val, reg_data, size); - for (i = 0; i < size; i++) { - *i2c->cur_trans++ = val[i]; - i2c->residue--; - } - - barrier(); - - return 0; -} - -static int zx2967_i2c_fill_tx_fifo(struct zx2967_i2c *i2c) -{ - size_t residue = i2c->residue; - u8 *buf = i2c->cur_trans; - - if (residue == 0) { - dev_err(dev(i2c), "residue is %d ", (int)residue); - return -einval; - } - - if (residue <= i2c_fifo_max) { - zx2967_i2c_writesb(i2c, buf, reg_data, residue); - - /* again update before writing to fifo to make sure isr sees. */ - i2c->residue = 0; - i2c->cur_trans = null; - } else { - zx2967_i2c_writesb(i2c, buf, reg_data, i2c_fifo_max); - i2c->residue -= i2c_fifo_max; - i2c->cur_trans += i2c_fifo_max; - } - - barrier(); - - return 0; -} - -static int zx2967_i2c_reset_hardware(struct zx2967_i2c *i2c) -{ - u32 val; - u32 clk_div; - - val = i2c_master | i2c_irq_msk_enable; - zx2967_i2c_writel(i2c, val, reg_cmd); - - clk_div = clk_get_rate(i2c->clk) / i2c->clk_freq - 1; - zx2967_i2c_writel(i2c, clk_div, reg_clk_div_fs); - zx2967_i2c_writel(i2c, clk_div, reg_clk_div_hs); - - zx2967_i2c_writel(i2c, i2c_fifo_max - 1, reg_wrconf); - zx2967_i2c_writel(i2c, i2c_fifo_max - 1, reg_rdconf); - zx2967_i2c_writel(i2c, 1, reg_rdconf); - - zx2967_i2c_flush_fifos(i2c); - - return 0; -} - -static void zx2967_i2c_isr_clr(struct zx2967_i2c *i2c) -{ - u32 status; - - status = zx2967_i2c_readl(i2c, reg_stat); - status |= i2c_irq_ack_clear; - zx2967_i2c_writel(i2c, status, reg_stat); -} - -static irqreturn_t zx2967_i2c_isr(int irq, void *dev_id) -{ - u32 status; - struct zx2967_i2c *i2c = (struct zx2967_i2c *)dev_id; - - status = zx2967_i2c_readl(i2c, reg_stat) & i2c_int_mask; - zx2967_i2c_isr_clr(i2c); - - if (status & i2c_sr_edevice) - i2c->error = -enxio; - else if (status & i2c_sr_edata) - i2c->error = -eio; - else if (status & i2c_trans_done) - i2c->error = 0; - else - goto done; - - complete(&i2c->complete); -done: - return irq_handled; -} - -static void zx2967_set_addr(struct zx2967_i2c *i2c, u16 addr) -{ - u16 val; - - val = (addr >> i2c_addr_low_shift) & i2c_addr_low_mask; - zx2967_i2c_writel(i2c, val, reg_devaddr_l); - - val = (addr >> i2c_addr_hi_shift) & i2c_addr_hi_mask; - zx2967_i2c_writel(i2c, val, reg_devaddr_h); - if (val) - val = zx2967_i2c_readl(i2c, reg_cmd) | i2c_addr_mode_ten; - else - val = zx2967_i2c_readl(i2c, reg_cmd) & ~i2c_addr_mode_ten; - zx2967_i2c_writel(i2c, val, reg_cmd); -} - -static int zx2967_i2c_xfer_bytes(struct zx2967_i2c *i2c, u32 bytes) -{ - unsigned long time_left; - int rd = i2c->msg_rd; - int ret; - - reinit_completion(&i2c->complete); - - if (rd) { - zx2967_i2c_writel(i2c, bytes - 1, reg_rdconf); - } else { - ret = zx2967_i2c_fill_tx_fifo(i2c); - if (ret) - return ret; - } - - zx2967_i2c_start_ctrl(i2c); - - time_left = wait_for_completion_timeout(&i2c->complete, - i2c_timeout); - if (time_left == 0) - return -etimedout; - - if (i2c->error) - return i2c->error; - - return rd ? zx2967_i2c_empty_rx_fifo(i2c, bytes) : 0; -} - -static int zx2967_i2c_xfer_msg(struct zx2967_i2c *i2c, - struct i2c_msg *msg) -{ - int ret; - int i; - - zx2967_i2c_flush_fifos(i2c); - - i2c->cur_trans = msg->buf; - i2c->residue = msg->len; - i2c->access_cnt = msg->len / i2c_fifo_max; - i2c->msg_rd = msg->flags & i2c_m_rd; - - for (i = 0; i < i2c->access_cnt; i++) { - ret = zx2967_i2c_xfer_bytes(i2c, i2c_fifo_max); - if (ret) - return ret; - } - - if (i2c->residue > 0) { - ret = zx2967_i2c_xfer_bytes(i2c, i2c->residue); - if (ret) - return ret; - } - - i2c->residue = 0; - i2c->access_cnt = 0; - - return 0; -} - -static int zx2967_i2c_xfer(struct i2c_adapter *adap, - struct i2c_msg *msgs, int num) -{ - struct zx2967_i2c *i2c = i2c_get_adapdata(adap); - int ret; - int i; - - zx2967_set_addr(i2c, msgs->addr); - - for (i = 0; i < num; i++) { - ret = zx2967_i2c_xfer_msg(i2c, &msgs[i]); - if (ret) - return ret; - } - - return num; -} - -static void -zx2967_smbus_xfer_prepare(struct zx2967_i2c *i2c, u16 addr, - char read_write, u8 command, int size, - union i2c_smbus_data *data) -{ - u32 val; - - val = zx2967_i2c_readl(i2c, reg_rdconf); - val |= i2c_rfifo_reset; - zx2967_i2c_writel(i2c, val, reg_rdconf); - zx2967_set_addr(i2c, addr); - val = zx2967_i2c_readl(i2c, reg_cmd); - val &= ~i2c_rw_read; - zx2967_i2c_writel(i2c, val, reg_cmd); - - switch (size) { - case i2c_smbus_byte: - zx2967_i2c_writel(i2c, command, reg_data); - break; - case i2c_smbus_byte_data: - zx2967_i2c_writel(i2c, command, reg_data); - if (read_write == i2c_smbus_write) - zx2967_i2c_writel(i2c, data->byte, reg_data); - break; - case i2c_smbus_word_data: - zx2967_i2c_writel(i2c, command, reg_data); - if (read_write == i2c_smbus_write) { - zx2967_i2c_writel(i2c, (data->word >> 8), reg_data); - zx2967_i2c_writel(i2c, (data->word & 0xff), - reg_data); - } - break; - } -} - -static int zx2967_smbus_xfer_read(struct zx2967_i2c *i2c, int size, - union i2c_smbus_data *data) -{ - unsigned long time_left; - u8 buf[2]; - u32 val; - - reinit_completion(&i2c->complete); - - val = zx2967_i2c_readl(i2c, reg_cmd); - val |= i2c_cmb_rw_en; - zx2967_i2c_writel(i2c, val, reg_cmd); - - val = zx2967_i2c_readl(i2c, reg_cmd); - val |= i2c_start; - zx2967_i2c_writel(i2c, val, reg_cmd); - - time_left = wait_for_completion_timeout(&i2c->complete, - i2c_timeout); - if (time_left == 0) - return -etimedout; - - if (i2c->error) - return i2c->error; - - switch (size) { - case i2c_smbus_byte: - case i2c_smbus_byte_data: - val = zx2967_i2c_readl(i2c, reg_data); - data->byte = val; - break; - case i2c_smbus_word_data: - case i2c_smbus_proc_call: - buf[0] = zx2967_i2c_readl(i2c, reg_data); - buf[1] = zx2967_i2c_readl(i2c, reg_data); - data->word = (buf[0] << 8) | buf[1]; - break; - default: - return -eopnotsupp; - } - - return 0; -} - -static int zx2967_smbus_xfer_write(struct zx2967_i2c *i2c) -{ - unsigned long time_left; - u32 val; - - reinit_completion(&i2c->complete); - val = zx2967_i2c_readl(i2c, reg_cmd); - val |= i2c_start; - zx2967_i2c_writel(i2c, val, reg_cmd); - - time_left = wait_for_completion_timeout(&i2c->complete, - i2c_timeout); - if (time_left == 0) - return -etimedout; - - if (i2c->error) - return i2c->error; - - return 0; -} - -static int zx2967_smbus_xfer(struct i2c_adapter *adap, u16 addr, - unsigned short flags, char read_write, - u8 command, int size, union i2c_smbus_data *data) -{ - struct zx2967_i2c *i2c = i2c_get_adapdata(adap); - - if (size == i2c_smbus_quick) - read_write = i2c_smbus_write; - - switch (size) { - case i2c_smbus_quick: - case i2c_smbus_byte: - case i2c_smbus_byte_data: - case i2c_smbus_word_data: - zx2967_smbus_xfer_prepare(i2c, addr, read_write, - command, size, data); - break; - default: - return -eopnotsupp; - } - - if (read_write == i2c_smbus_read) - return zx2967_smbus_xfer_read(i2c, size, data); - - return zx2967_smbus_xfer_write(i2c); -} - -static u32 zx2967_i2c_func(struct i2c_adapter *adap) -{ - return i2c_func_i2c | - i2c_func_smbus_quick | - i2c_func_smbus_byte | - i2c_func_smbus_byte_data | - i2c_func_smbus_word_data | - i2c_func_smbus_block_data | - i2c_func_smbus_proc_call | - i2c_func_smbus_i2c_block; -} - -static int __maybe_unused zx2967_i2c_suspend(struct device *dev) -{ - struct zx2967_i2c *i2c = dev_get_drvdata(dev); - - i2c_mark_adapter_suspended(&i2c->adap); - clk_disable_unprepare(i2c->clk); - - return 0; -} - -static int __maybe_unused zx2967_i2c_resume(struct device *dev) -{ - struct zx2967_i2c *i2c = dev_get_drvdata(dev); - - clk_prepare_enable(i2c->clk); - i2c_mark_adapter_resumed(&i2c->adap); - - return 0; -} - -static simple_dev_pm_ops(zx2967_i2c_dev_pm_ops, - zx2967_i2c_suspend, zx2967_i2c_resume); - -static const struct i2c_algorithm zx2967_i2c_algo = { - .master_xfer = zx2967_i2c_xfer, - .smbus_xfer = zx2967_smbus_xfer, - .functionality = zx2967_i2c_func, -}; - -static const struct i2c_adapter_quirks zx2967_i2c_quirks = { - .flags = i2c_aq_no_zero_len, -}; - -static const struct of_device_id zx2967_i2c_of_match[] = { - { .compatible = "zte,zx296718-i2c", }, - { }, -}; -module_device_table(of, zx2967_i2c_of_match); - -static int zx2967_i2c_probe(struct platform_device *pdev) -{ - struct zx2967_i2c *i2c; - void __iomem *reg_base; - struct clk *clk; - int ret; - - i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), gfp_kernel); - if (!i2c) - return -enomem; - - reg_base = devm_platform_ioremap_resource(pdev, 0); - if (is_err(reg_base)) - return ptr_err(reg_base); - - clk = devm_clk_get(&pdev->dev, null); - if (is_err(clk)) { - dev_err(&pdev->dev, "missing controller clock"); - return ptr_err(clk); - } - - ret = clk_prepare_enable(clk); - if (ret) { - dev_err(&pdev->dev, "failed to enable i2c_clk "); - return ret; - } - - ret = device_property_read_u32(&pdev->dev, "clock-frequency", - &i2c->clk_freq); - if (ret) { - dev_err(&pdev->dev, "missing clock-frequency"); - return ret; - } - - ret = platform_get_irq(pdev, 0); - if (ret < 0) - return ret; - - i2c->irq = ret; - i2c->reg_base = reg_base; - i2c->clk = clk; - - init_completion(&i2c->complete); - platform_set_drvdata(pdev, i2c); - - ret = zx2967_i2c_reset_hardware(i2c); - if (ret) { - dev_err(&pdev->dev, "failed to initialize i2c controller "); - goto err_clk_unprepare; - } - - ret = devm_request_irq(&pdev->dev, i2c->irq, - zx2967_i2c_isr, 0, dev_name(&pdev->dev), i2c); - if (ret) { - dev_err(&pdev->dev, "failed to request irq %i ", i2c->irq); - goto err_clk_unprepare; - } - - i2c_set_adapdata(&i2c->adap, i2c); - strlcpy(i2c->adap.name, "zx2967 i2c adapter", - sizeof(i2c->adap.name)); - i2c->adap.algo = &zx2967_i2c_algo; - i2c->adap.quirks = &zx2967_i2c_quirks; - i2c->adap.nr = pdev->id; - i2c->adap.dev.parent = &pdev->dev; - i2c->adap.dev.of_node = pdev->dev.of_node; - - ret = i2c_add_numbered_adapter(&i2c->adap); - if (ret) - goto err_clk_unprepare; - - return 0; - -err_clk_unprepare: - clk_disable_unprepare(i2c->clk); - return ret; -} - -static int zx2967_i2c_remove(struct platform_device *pdev) -{ - struct zx2967_i2c *i2c = platform_get_drvdata(pdev); - - i2c_del_adapter(&i2c->adap); - clk_disable_unprepare(i2c->clk); - - return 0; -} - -static struct platform_driver zx2967_i2c_driver = { - .probe = zx2967_i2c_probe, - .remove = zx2967_i2c_remove, - .driver = { - .name = "zx2967_i2c", - .of_match_table = zx2967_i2c_of_match, - .pm = &zx2967_i2c_dev_pm_ops, - }, -}; -module_platform_driver(zx2967_i2c_driver); - -module_author("baoyou xie <baoyou.xie@linaro.org>"); -module_description("zte zx2967 i2c bus controller driver"); -module_license("gpl v2");
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Inter-Integrated Circuit (I2C + I3C)
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73cc584cfced260133cfc635f9921d66da676749
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arnd bergmann
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documentation
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devicetree
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bindings, busses, i2c
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i3c: master: svc: add silvaco i3c master driver
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add support for silvaco i3c dual-role ip. the master role is supported in sdr mode only. i2c transfers have not been tested but are shared because they are very close to the i3c transfers in terms of register configuration.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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add silvaco i3c master driver
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
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['i3c', 'master', 'svc']
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['kconfig', 'c', 'makefile']
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| 1,487
| 0
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- when a slave advertizes an interrupt (sda pulled low) an interrupt - the irq handler itself does not process anything: it only queues a - the ibi job is divided in two parts: the first one is "critical" in - if the critical section got interrupted, the slave will --- diff --git a/drivers/i3c/master/kconfig b/drivers/i3c/master/kconfig --- a/drivers/i3c/master/kconfig +++ b/drivers/i3c/master/kconfig +config svc_i3c_master + tristate "silvaco i3c dual-role master driver" + depends on i3c + depends on has_iomem + depends on !(alpha || parisc) + help + support for silvaco i3c dual-role master controller. + diff --git a/drivers/i3c/master/makefile b/drivers/i3c/master/makefile --- a/drivers/i3c/master/makefile +++ b/drivers/i3c/master/makefile +obj-$(config_svc_i3c_master) += svc-i3c-master.o diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c --- /dev/null +++ b/drivers/i3c/master/svc-i3c-master.c +// spdx-license-identifier: gpl-2.0 +/* + * silvaco dual-role i3c master driver + * + * copyright (c) 2020 silvaco + * author: miquel raynal <miquel.raynal@bootlin.com> + * based on a work from: conor culhane <conor.culhane@silvaco.com> + */ + +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/completion.h> +#include <linux/errno.h> +#include <linux/i3c/master.h> +#include <linux/interrupt.h> +#include <linux/iopoll.h> +#include <linux/list.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +/* master mode registers */ +#define svc_i3c_mconfig 0x000 +#define svc_i3c_mconfig_master_en bit(0) +#define svc_i3c_mconfig_disto(x) field_prep(bit(3), (x)) +#define svc_i3c_mconfig_hkeep(x) field_prep(genmask(5, 4), (x)) +#define svc_i3c_mconfig_odstop(x) field_prep(bit(6), (x)) +#define svc_i3c_mconfig_ppbaud(x) field_prep(genmask(11, 8), (x)) +#define svc_i3c_mconfig_pplow(x) field_prep(genmask(15, 12), (x)) +#define svc_i3c_mconfig_odbaud(x) field_prep(genmask(23, 16), (x)) +#define svc_i3c_mconfig_odhpp(x) field_prep(bit(24), (x)) +#define svc_i3c_mconfig_skew(x) field_prep(genmask(27, 25), (x)) +#define svc_i3c_mconfig_i2cbaud(x) field_prep(genmask(31, 28), (x)) + +#define svc_i3c_mctrl 0x084 +#define svc_i3c_mctrl_request_mask genmask(2, 0) +#define svc_i3c_mctrl_request_none 0 +#define svc_i3c_mctrl_request_start_addr 1 +#define svc_i3c_mctrl_request_stop 2 +#define svc_i3c_mctrl_request_ibi_acknack 3 +#define svc_i3c_mctrl_request_proc_daa 4 +#define svc_i3c_mctrl_request_auto_ibi 7 +#define svc_i3c_mctrl_type_i3c 0 +#define svc_i3c_mctrl_type_i2c bit(4) +#define svc_i3c_mctrl_ibiresp_auto 0 +#define svc_i3c_mctrl_ibiresp_ack_without_byte 0 +#define svc_i3c_mctrl_ibiresp_ack_with_byte bit(7) +#define svc_i3c_mctrl_ibiresp_nack bit(6) +#define svc_i3c_mctrl_ibiresp_manual genmask(7, 6) +#define svc_i3c_mctrl_dir(x) field_prep(bit(8), (x)) +#define svc_i3c_mctrl_dir_write 0 +#define svc_i3c_mctrl_dir_read 1 +#define svc_i3c_mctrl_addr(x) field_prep(genmask(15, 9), (x)) +#define svc_i3c_mctrl_rdterm(x) field_prep(genmask(23, 16), (x)) + +#define svc_i3c_mstatus 0x088 +#define svc_i3c_mstatus_state(x) field_get(genmask(2, 0), (x)) +#define svc_i3c_mstatus_state_daa(x) (svc_i3c_mstatus_state(x) == 5) +#define svc_i3c_mstatus_state_idle(x) (svc_i3c_mstatus_state(x) == 0) +#define svc_i3c_mstatus_between(x) field_get(bit(4), (x)) +#define svc_i3c_mstatus_nacked(x) field_get(bit(5), (x)) +#define svc_i3c_mstatus_ibitype(x) field_get(genmask(7, 6), (x)) +#define svc_i3c_mstatus_ibitype_ibi 1 +#define svc_i3c_mstatus_ibitype_master_request 2 +#define svc_i3c_mstatus_ibitype_hot_join 3 +#define svc_i3c_mint_slvstart bit(8) +#define svc_i3c_mint_mctrldone bit(9) +#define svc_i3c_mint_complete bit(10) +#define svc_i3c_mint_rxpend bit(11) +#define svc_i3c_mint_txnotfull bit(12) +#define svc_i3c_mint_ibiwon bit(13) +#define svc_i3c_mint_errwarn bit(15) +#define svc_i3c_mstatus_slvstart(x) field_get(svc_i3c_mint_slvstart, (x)) +#define svc_i3c_mstatus_mctrldone(x) field_get(svc_i3c_mint_mctrldone, (x)) +#define svc_i3c_mstatus_complete(x) field_get(svc_i3c_mint_complete, (x)) +#define svc_i3c_mstatus_rxpend(x) field_get(svc_i3c_mint_rxpend, (x)) +#define svc_i3c_mstatus_txnotfull(x) field_get(svc_i3c_mint_txnotfull, (x)) +#define svc_i3c_mstatus_ibiwon(x) field_get(svc_i3c_mint_ibiwon, (x)) +#define svc_i3c_mstatus_errwarn(x) field_get(svc_i3c_mint_errwarn, (x)) +#define svc_i3c_mstatus_ibiaddr(x) field_get(genmask(30, 24), (x)) + +#define svc_i3c_ibirules 0x08c +#define svc_i3c_ibirules_addr(slot, addr) field_prep(genmask(29, 0), \ + ((addr) & 0x3f) << ((slot) * 6)) +#define svc_i3c_ibirules_addrs 5 +#define svc_i3c_ibirules_msb0 bit(30) +#define svc_i3c_ibirules_nobyte bit(31) +#define svc_i3c_ibirules_mandbyte 0 +#define svc_i3c_mintset 0x090 +#define svc_i3c_mintclr 0x094 +#define svc_i3c_mintmasked 0x098 +#define svc_i3c_merrwarn 0x09c +#define svc_i3c_mdmactrl 0x0a0 +#define svc_i3c_mdatactrl 0x0ac +#define svc_i3c_mdatactrl_flushtb bit(0) +#define svc_i3c_mdatactrl_flushrb bit(1) +#define svc_i3c_mdatactrl_unlock_trig bit(3) +#define svc_i3c_mdatactrl_txtrig_fifo_not_full genmask(5, 4) +#define svc_i3c_mdatactrl_rxtrig_fifo_not_empty 0 +#define svc_i3c_mdatactrl_rxcount(x) field_get(genmask(28, 24), (x)) +#define svc_i3c_mdatactrl_txfull bit(30) +#define svc_i3c_mdatactrl_rxempty bit(31) + +#define svc_i3c_mwdatab 0x0b0 +#define svc_i3c_mwdatab_end bit(8) + +#define svc_i3c_mwdatabe 0x0b4 +#define svc_i3c_mwdatah 0x0b8 +#define svc_i3c_mwdatahe 0x0bc +#define svc_i3c_mrdatab 0x0c0 +#define svc_i3c_mrdatah 0x0c8 +#define svc_i3c_mwmsg_sdr 0x0d0 +#define svc_i3c_mrmsg_sdr 0x0d4 +#define svc_i3c_mwmsg_ddr 0x0d8 +#define svc_i3c_mrmsg_ddr 0x0dc + +#define svc_i3c_mdynaddr 0x0e4 +#define svc_mdynaddr_valid bit(0) +#define svc_mdynaddr_addr(x) field_prep(genmask(7, 1), (x)) + +#define svc_i3c_max_devs 32 + +/* this parameter depends on the implementation and may be tuned */ +#define svc_i3c_fifo_size 16 + +struct svc_i3c_cmd { + u8 addr; + bool rnw; + u8 *in; + const void *out; + unsigned int len; + unsigned int read_len; + bool continued; +}; + +struct svc_i3c_xfer { + struct list_head node; + struct completion comp; + int ret; + unsigned int type; + unsigned int ncmds; + struct svc_i3c_cmd cmds[]; +}; + +/** + * struct svc_i3c_master - silvaco i3c master structure + * @base: i3c master controller + * @dev: corresponding device + * @regs: memory mapping + * @free_slots: bit array of available slots + * @addrs: array containing the dynamic addresses of each attached device + * @descs: array of descriptors, one per attached device + * @hj_work: hot-join work + * @ibi_work: ibi work + * @irq: main interrupt + * @pclk: system clock + * @fclk: fast clock (bus) + * @sclk: slow clock (other events) + * @xferqueue: transfer queue structure + * @xferqueue.list: list member + * @xferqueue.cur: current ongoing transfer + * @xferqueue.lock: queue lock + * @ibi: ibi structure + * @ibi.num_slots: number of slots available in @ibi.slots + * @ibi.slots: available ibi slots + * @ibi.tbq_slot: to be queued ibi slot + * @ibi.lock: ibi lock + */ +struct svc_i3c_master { + struct i3c_master_controller base; + struct device *dev; + void __iomem *regs; + u32 free_slots; + u8 addrs[svc_i3c_max_devs]; + struct i3c_dev_desc *descs[svc_i3c_max_devs]; + struct work_struct hj_work; + struct work_struct ibi_work; + int irq; + struct clk *pclk; + struct clk *fclk; + struct clk *sclk; + struct { + struct list_head list; + struct svc_i3c_xfer *cur; + /* prevent races between transfers */ + spinlock_t lock; + } xferqueue; + struct { + unsigned int num_slots; + struct i3c_dev_desc **slots; + struct i3c_ibi_slot *tbq_slot; + /* prevent races within ibi handlers */ + spinlock_t lock; + } ibi; +}; + +/** + * struct svc_i3c_i3c_dev_data - device specific data + * @index: index in the master tables corresponding to this device + * @ibi: ibi slot index in the master structure + * @ibi_pool: ibi pool associated to this device + */ +struct svc_i3c_i2c_dev_data { + u8 index; + int ibi; + struct i3c_generic_ibi_pool *ibi_pool; +}; + +static bool svc_i3c_master_error(struct svc_i3c_master *master) +{ + u32 mstatus, merrwarn; + + mstatus = readl(master->regs + svc_i3c_mstatus); + if (svc_i3c_mstatus_errwarn(mstatus)) { + merrwarn = readl(master->regs + svc_i3c_merrwarn); + writel(merrwarn, master->regs + svc_i3c_merrwarn); + dev_err(master->dev, + "error condition: mstatus 0x%08x, merrwarn 0x%08x ", + mstatus, merrwarn); + + return true; + } + + return false; +} + +static void svc_i3c_master_enable_interrupts(struct svc_i3c_master *master, u32 mask) +{ + writel(mask, master->regs + svc_i3c_mintset); +} + +static void svc_i3c_master_disable_interrupts(struct svc_i3c_master *master) +{ + u32 mask = readl(master->regs + svc_i3c_mintset); + + writel(mask, master->regs + svc_i3c_mintclr); +} + +static inline struct svc_i3c_master * +to_svc_i3c_master(struct i3c_master_controller *master) +{ + return container_of(master, struct svc_i3c_master, base); +} + +static void svc_i3c_master_hj_work(struct work_struct *work) +{ + struct svc_i3c_master *master; + + master = container_of(work, struct svc_i3c_master, hj_work); + i3c_master_do_daa(&master->base); +} + +static struct i3c_dev_desc * +svc_i3c_master_dev_from_addr(struct svc_i3c_master *master, + unsigned int ibiaddr) +{ + int i; + + for (i = 0; i < svc_i3c_max_devs; i++) + if (master->addrs[i] == ibiaddr) + break; + + if (i == svc_i3c_max_devs) + return null; + + return master->descs[i]; +} + +static void svc_i3c_master_emit_stop(struct svc_i3c_master *master) +{ + writel(svc_i3c_mctrl_request_stop, master->regs + svc_i3c_mctrl); + + /* + * this delay is necessary after the emission of a stop, otherwise eg. + * repeating ibis do not get detected. there is a note in the manual + * about it, stating that the stop condition might not be settled + * correctly if a start condition follows too rapidly. + */ + udelay(1); +} + +static void svc_i3c_master_clear_merrwarn(struct svc_i3c_master *master) +{ + writel(readl(master->regs + svc_i3c_merrwarn), + master->regs + svc_i3c_merrwarn); +} + +static int svc_i3c_master_handle_ibi(struct svc_i3c_master *master, + struct i3c_dev_desc *dev) +{ + struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); + struct i3c_ibi_slot *slot; + unsigned int count; + u32 mdatactrl; + u8 *buf; + + slot = i3c_generic_ibi_get_free_slot(data->ibi_pool); + if (!slot) + return -enospc; + + slot->len = 0; + buf = slot->data; + + while (svc_i3c_mstatus_rxpend(readl(master->regs + svc_i3c_mstatus)) && + slot->len < svc_i3c_fifo_size) { + mdatactrl = readl(master->regs + svc_i3c_mdatactrl); + count = svc_i3c_mdatactrl_rxcount(mdatactrl); + readsl(master->regs + svc_i3c_mrdatab, buf, count); + slot->len += count; + buf += count; + } + + master->ibi.tbq_slot = slot; + + return 0; +} + +static void svc_i3c_master_ack_ibi(struct svc_i3c_master *master, + bool mandatory_byte) +{ + unsigned int ibi_ack_nack; + + ibi_ack_nack = svc_i3c_mctrl_request_ibi_acknack; + if (mandatory_byte) + ibi_ack_nack |= svc_i3c_mctrl_ibiresp_ack_with_byte; + else + ibi_ack_nack |= svc_i3c_mctrl_ibiresp_ack_without_byte; + + writel(ibi_ack_nack, master->regs + svc_i3c_mctrl); +} + +static void svc_i3c_master_nack_ibi(struct svc_i3c_master *master) +{ + writel(svc_i3c_mctrl_request_ibi_acknack | + svc_i3c_mctrl_ibiresp_nack, + master->regs + svc_i3c_mctrl); +} + +static void svc_i3c_master_ibi_work(struct work_struct *work) +{ + struct svc_i3c_master *master = container_of(work, struct svc_i3c_master, ibi_work); + struct svc_i3c_i2c_dev_data *data; + unsigned int ibitype, ibiaddr; + struct i3c_dev_desc *dev; + u32 status, val; + int ret; + + /* acknowledge the incoming interrupt with the autoibi mechanism */ + writel(svc_i3c_mctrl_request_auto_ibi | + svc_i3c_mctrl_ibiresp_auto, + master->regs + svc_i3c_mctrl); + + /* wait for ibiwon, should take approximately 100us */ + ret = readl_relaxed_poll_timeout(master->regs + svc_i3c_mstatus, val, + svc_i3c_mstatus_ibiwon(val), 0, 1000); + if (ret) { + dev_err(master->dev, "timeout when polling for ibiwon "); + goto reenable_ibis; + } + + /* clear the interrupt status */ + writel(svc_i3c_mint_ibiwon, master->regs + svc_i3c_mstatus); + + status = readl(master->regs + svc_i3c_mstatus); + ibitype = svc_i3c_mstatus_ibitype(status); + ibiaddr = svc_i3c_mstatus_ibiaddr(status); + + /* handle the critical responses to ibi's */ + switch (ibitype) { + case svc_i3c_mstatus_ibitype_ibi: + dev = svc_i3c_master_dev_from_addr(master, ibiaddr); + if (!dev) + svc_i3c_master_nack_ibi(master); + else + svc_i3c_master_handle_ibi(master, dev); + break; + case svc_i3c_mstatus_ibitype_hot_join: + svc_i3c_master_ack_ibi(master, false); + break; + case svc_i3c_mstatus_ibitype_master_request: + svc_i3c_master_nack_ibi(master); + break; + default: + break; + } + + /* + * if an error happened, we probably got interrupted and the exchange + * timedout. in this case we just drop everything, emit a stop and wait + * for the slave to interrupt again. + */ + if (svc_i3c_master_error(master)) { + if (master->ibi.tbq_slot) { + data = i3c_dev_get_master_data(dev); + i3c_generic_ibi_recycle_slot(data->ibi_pool, + master->ibi.tbq_slot); + master->ibi.tbq_slot = null; + } + + svc_i3c_master_emit_stop(master); + + goto reenable_ibis; + } + + /* handle the non critical tasks */ + switch (ibitype) { + case svc_i3c_mstatus_ibitype_ibi: + if (dev) { + i3c_master_queue_ibi(dev, master->ibi.tbq_slot); + master->ibi.tbq_slot = null; + } + svc_i3c_master_emit_stop(master); + break; + case svc_i3c_mstatus_ibitype_hot_join: + queue_work(master->base.wq, &master->hj_work); + break; + case svc_i3c_mstatus_ibitype_master_request: + default: + break; + } + +reenable_ibis: + svc_i3c_master_enable_interrupts(master, svc_i3c_mint_slvstart); +} + +static irqreturn_t svc_i3c_master_irq_handler(int irq, void *dev_id) +{ + struct svc_i3c_master *master = (struct svc_i3c_master *)dev_id; + u32 active = readl(master->regs + svc_i3c_mintmasked); + + if (!svc_i3c_mstatus_slvstart(active)) + return irq_none; + + /* clear the interrupt status */ + writel(svc_i3c_mint_slvstart, master->regs + svc_i3c_mstatus); + + svc_i3c_master_disable_interrupts(master); + + /* handle the interrupt in a non atomic context */ + queue_work(master->base.wq, &master->ibi_work); + + return irq_handled; +} + +static int svc_i3c_master_bus_init(struct i3c_master_controller *m) +{ + struct svc_i3c_master *master = to_svc_i3c_master(m); + struct i3c_bus *bus = i3c_master_get_bus(m); + struct i3c_device_info info = {}; + unsigned long fclk_rate, fclk_period_ns; + unsigned int high_period_ns, od_low_period_ns; + u32 ppbaud, pplow, odhpp, odbaud, i2cbaud, reg; + int ret; + + /* timings derivation */ + fclk_rate = clk_get_rate(master->fclk); + if (!fclk_rate) + return -einval; + + fclk_period_ns = div_round_up(1000000000, fclk_rate); + + /* + * using i3c push-pull mode, target is 12.5mhz/80ns period. + * simplest configuration is using a 50% duty-cycle of 40ns. + */ + ppbaud = div_round_up(40, fclk_period_ns) - 1; + pplow = 0; + + /* + * using i3c open-drain mode, target is 4.17mhz/240ns with a + * duty-cycle tuned so that high levels are filetered out by + * the 50ns filter (target being 40ns). + */ + odhpp = 1; + high_period_ns = (ppbaud + 1) * fclk_period_ns; + odbaud = div_round_up(240 - high_period_ns, high_period_ns) - 1; + od_low_period_ns = (odbaud + 1) * high_period_ns; + + switch (bus->mode) { + case i3c_bus_mode_pure: + i2cbaud = 0; + break; + case i3c_bus_mode_mixed_fast: + case i3c_bus_mode_mixed_limited: + /* + * using i2c fm+ mode, target is 1mhz/1000ns, the difference + * between the high and low period does not really matter. + */ + i2cbaud = div_round_up(1000, od_low_period_ns) - 2; + break; + case i3c_bus_mode_mixed_slow: + /* + * using i2c fm mode, target is 0.4mhz/2500ns, with the same + * constraints as the fm+ mode. + */ + i2cbaud = div_round_up(2500, od_low_period_ns) - 2; + break; + default: + return -einval; + } + + reg = svc_i3c_mconfig_master_en | + svc_i3c_mconfig_disto(0) | + svc_i3c_mconfig_hkeep(0) | + svc_i3c_mconfig_odstop(0) | + svc_i3c_mconfig_ppbaud(ppbaud) | + svc_i3c_mconfig_pplow(pplow) | + svc_i3c_mconfig_odbaud(odbaud) | + svc_i3c_mconfig_odhpp(odhpp) | + svc_i3c_mconfig_skew(0) | + svc_i3c_mconfig_i2cbaud(i2cbaud); + writel(reg, master->regs + svc_i3c_mconfig); + + /* master core's registration */ + ret = i3c_master_get_free_addr(m, 0); + if (ret < 0) + return ret; + + info.dyn_addr = ret; + + writel(svc_mdynaddr_valid | svc_mdynaddr_addr(info.dyn_addr), + master->regs + svc_i3c_mdynaddr); + + ret = i3c_master_set_info(&master->base, &info); + if (ret) + return ret; + + svc_i3c_master_enable_interrupts(master, svc_i3c_mint_slvstart); + + return 0; +} + +static void svc_i3c_master_bus_cleanup(struct i3c_master_controller *m) +{ + struct svc_i3c_master *master = to_svc_i3c_master(m); + + svc_i3c_master_disable_interrupts(master); + + /* disable master */ + writel(0, master->regs + svc_i3c_mconfig); +} + +static int svc_i3c_master_reserve_slot(struct svc_i3c_master *master) +{ + unsigned int slot; + + if (!(master->free_slots & genmask(svc_i3c_max_devs - 1, 0))) + return -enospc; + + slot = ffs(master->free_slots) - 1; + + master->free_slots &= ~bit(slot); + + return slot; +} + +static void svc_i3c_master_release_slot(struct svc_i3c_master *master, + unsigned int slot) +{ + master->free_slots |= bit(slot); +} + +static int svc_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev) +{ + struct i3c_master_controller *m = i3c_dev_get_master(dev); + struct svc_i3c_master *master = to_svc_i3c_master(m); + struct svc_i3c_i2c_dev_data *data; + int slot; + + slot = svc_i3c_master_reserve_slot(master); + if (slot < 0) + return slot; + + data = kzalloc(sizeof(*data), gfp_kernel); + if (!data) { + svc_i3c_master_release_slot(master, slot); + return -enomem; + } + + data->ibi = -1; + data->index = slot; + master->addrs[slot] = dev->info.dyn_addr ? dev->info.dyn_addr : + dev->info.static_addr; + master->descs[slot] = dev; + + i3c_dev_set_master_data(dev, data); + + return 0; +} + +static int svc_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev, + u8 old_dyn_addr) +{ + struct i3c_master_controller *m = i3c_dev_get_master(dev); + struct svc_i3c_master *master = to_svc_i3c_master(m); + struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); + + master->addrs[data->index] = dev->info.dyn_addr ? dev->info.dyn_addr : + dev->info.static_addr; + + return 0; +} + +static void svc_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev) +{ + struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); + struct i3c_master_controller *m = i3c_dev_get_master(dev); + struct svc_i3c_master *master = to_svc_i3c_master(m); + + master->addrs[data->index] = 0; + svc_i3c_master_release_slot(master, data->index); + + kfree(data); +} + +static int svc_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev) +{ + struct i3c_master_controller *m = i2c_dev_get_master(dev); + struct svc_i3c_master *master = to_svc_i3c_master(m); + struct svc_i3c_i2c_dev_data *data; + int slot; + + slot = svc_i3c_master_reserve_slot(master); + if (slot < 0) + return slot; + + data = kzalloc(sizeof(*data), gfp_kernel); + if (!data) { + svc_i3c_master_release_slot(master, slot); + return -enomem; + } + + data->index = slot; + master->addrs[slot] = dev->addr; + + i2c_dev_set_master_data(dev, data); + + return 0; +} + +static void svc_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev) +{ + struct svc_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); + struct i3c_master_controller *m = i2c_dev_get_master(dev); + struct svc_i3c_master *master = to_svc_i3c_master(m); + + svc_i3c_master_release_slot(master, data->index); + + kfree(data); +} + +static int svc_i3c_master_readb(struct svc_i3c_master *master, u8 *dst, + unsigned int len) +{ + int ret, i; + u32 reg; + + for (i = 0; i < len; i++) { + ret = readl_poll_timeout(master->regs + svc_i3c_mstatus, reg, + svc_i3c_mstatus_rxpend(reg), 0, 1000); + if (ret) + return ret; + + dst[i] = readl(master->regs + svc_i3c_mrdatab); + } + + return 0; +} + +static int svc_i3c_master_do_daa_locked(struct svc_i3c_master *master, + u8 *addrs, unsigned int *count) +{ + u64 prov_id[svc_i3c_max_devs] = {}, nacking_prov_id = 0; + unsigned int dev_nb = 0, last_addr = 0; + u32 reg; + int ret, i; + + while (true) { + /* enter/proceed with daa */ + writel(svc_i3c_mctrl_request_proc_daa | + svc_i3c_mctrl_type_i3c | + svc_i3c_mctrl_ibiresp_nack | + svc_i3c_mctrl_dir(svc_i3c_mctrl_dir_write), + master->regs + svc_i3c_mctrl); + + /* + * either one slave will send its id, or the assignment process + * is done. + */ + ret = readl_poll_timeout(master->regs + svc_i3c_mstatus, reg, + svc_i3c_mstatus_rxpend(reg) | + svc_i3c_mstatus_mctrldone(reg), + 1, 1000); + if (ret) + return ret; + + if (svc_i3c_mstatus_rxpend(reg)) { + u8 data[6]; + + /* + * we only care about the 48-bit provisional id yet to + * be sure a device does not nack an address twice. + * otherwise, we would just need to flush the rx fifo. + */ + ret = svc_i3c_master_readb(master, data, 6); + if (ret) + return ret; + + for (i = 0; i < 6; i++) + prov_id[dev_nb] |= (u64)(data[i]) << (8 * (5 - i)); + + /* we do not care about the bcr and dcr yet */ + ret = svc_i3c_master_readb(master, data, 2); + if (ret) + return ret; + } else if (svc_i3c_mstatus_mctrldone(reg)) { + if (svc_i3c_mstatus_state_idle(reg) && + svc_i3c_mstatus_complete(reg)) { + /* + * all devices received and acked they dynamic + * address, this is the natural end of the daa + * procedure. + */ + break; + } else if (svc_i3c_mstatus_nacked(reg)) { + /* + * a slave device nacked the address, this is + * allowed only once, daa will be stopped and + * then resumed. the same device is supposed to + * answer again immediately and shall ack the + * address this time. + */ + if (prov_id[dev_nb] == nacking_prov_id) + return -eio; + + dev_nb--; + nacking_prov_id = prov_id[dev_nb]; + svc_i3c_master_emit_stop(master); + + continue; + } else { + return -eio; + } + } + + /* wait for the slave to be ready to receive its address */ + ret = readl_poll_timeout(master->regs + svc_i3c_mstatus, reg, + svc_i3c_mstatus_mctrldone(reg) && + svc_i3c_mstatus_state_daa(reg) && + svc_i3c_mstatus_between(reg), + 0, 1000); + if (ret) + return ret; + + /* give the slave device a suitable dynamic address */ + ret = i3c_master_get_free_addr(&master->base, last_addr + 1); + if (ret < 0) + return ret; + + addrs[dev_nb] = ret; + dev_dbg(master->dev, "daa: device %d assigned to 0x%02x ", + dev_nb, addrs[dev_nb]); + + writel(addrs[dev_nb], master->regs + svc_i3c_mwdatab); + last_addr = addrs[dev_nb++]; + } + + *count = dev_nb; + + return 0; +} + +static int svc_i3c_update_ibirules(struct svc_i3c_master *master) +{ + struct i3c_dev_desc *dev; + u32 reg_mbyte = 0, reg_nobyte = svc_i3c_ibirules_nobyte; + unsigned int mbyte_addr_ok = 0, mbyte_addr_ko = 0, nobyte_addr_ok = 0, + nobyte_addr_ko = 0; + bool list_mbyte = false, list_nobyte = false; + + /* create the ibirules register for both cases */ + i3c_bus_for_each_i3cdev(&master->base.bus, dev) { + if (i3c_bcr_device_role(dev->info.bcr) == i3c_bcr_i3c_master) + continue; + + if (dev->info.bcr & i3c_bcr_ibi_payload) { + reg_mbyte |= svc_i3c_ibirules_addr(mbyte_addr_ok, + dev->info.dyn_addr); + + /* ibi rules cannot be applied to devices with msb=1 */ + if (dev->info.dyn_addr & bit(7)) + mbyte_addr_ko++; + else + mbyte_addr_ok++; + } else { + reg_nobyte |= svc_i3c_ibirules_addr(nobyte_addr_ok, + dev->info.dyn_addr); + + /* ibi rules cannot be applied to devices with msb=1 */ + if (dev->info.dyn_addr & bit(7)) + nobyte_addr_ko++; + else + nobyte_addr_ok++; + } + } + + /* device list cannot be handled by hardware */ + if (!mbyte_addr_ko && mbyte_addr_ok <= svc_i3c_ibirules_addrs) + list_mbyte = true; + + if (!nobyte_addr_ko && nobyte_addr_ok <= svc_i3c_ibirules_addrs) + list_nobyte = true; + + /* no list can be properly handled, return an error */ + if (!list_mbyte && !list_nobyte) + return -erange; + + /* pick the first list that can be handled by hardware, randomly */ + if (list_mbyte) + writel(reg_mbyte, master->regs + svc_i3c_ibirules); + else + writel(reg_nobyte, master->regs + svc_i3c_ibirules); + + return 0; +} + +static int svc_i3c_master_do_daa(struct i3c_master_controller *m) +{ + struct svc_i3c_master *master = to_svc_i3c_master(m); + u8 addrs[svc_i3c_max_devs]; + unsigned long flags; + unsigned int dev_nb; + int ret, i; + + spin_lock_irqsave(&master->xferqueue.lock, flags); + ret = svc_i3c_master_do_daa_locked(master, addrs, &dev_nb); + spin_unlock_irqrestore(&master->xferqueue.lock, flags); + if (ret) + goto emit_stop; + + /* register all devices who participated to the core */ + for (i = 0; i < dev_nb; i++) { + ret = i3c_master_add_i3c_dev_locked(m, addrs[i]); + if (ret) + return ret; + } + + /* configure ibi auto-rules */ + ret = svc_i3c_update_ibirules(master); + if (ret) { + dev_err(master->dev, "cannot handle such a list of devices"); + return ret; + } + + return 0; + +emit_stop: + svc_i3c_master_emit_stop(master); + svc_i3c_master_clear_merrwarn(master); + + return ret; +} + +static int svc_i3c_master_read(struct svc_i3c_master *master, + u8 *in, unsigned int len) +{ + int offset = 0, i, ret; + u32 mdctrl; + + while (offset < len) { + unsigned int count; + + ret = readl_poll_timeout(master->regs + svc_i3c_mdatactrl, + mdctrl, + !(mdctrl & svc_i3c_mdatactrl_rxempty), + 0, 1000); + if (ret) + return ret; + + count = svc_i3c_mdatactrl_rxcount(mdctrl); + for (i = 0; i < count; i++) + in[offset + i] = readl(master->regs + svc_i3c_mrdatab); + + offset += count; + } + + return 0; +} + +static int svc_i3c_master_write(struct svc_i3c_master *master, + const u8 *out, unsigned int len) +{ + int offset = 0, ret; + u32 mdctrl; + + while (offset < len) { + ret = readl_poll_timeout(master->regs + svc_i3c_mdatactrl, + mdctrl, + !(mdctrl & svc_i3c_mdatactrl_txfull), + 0, 1000); + if (ret) + return ret; + + /* + * the last byte to be sent over the bus must either have the + * "end" bit set or be written in mwdatabe. + */ + if (likely(offset < (len - 1))) + writel(out[offset++], master->regs + svc_i3c_mwdatab); + else + writel(out[offset++], master->regs + svc_i3c_mwdatabe); + } + + return 0; +} + +static int svc_i3c_master_xfer(struct svc_i3c_master *master, + bool rnw, unsigned int xfer_type, u8 addr, + u8 *in, const u8 *out, unsigned int xfer_len, + unsigned int read_len, bool continued) +{ + u32 reg; + int ret; + + writel(svc_i3c_mctrl_request_start_addr | + xfer_type | + svc_i3c_mctrl_ibiresp_nack | + svc_i3c_mctrl_dir(rnw) | + svc_i3c_mctrl_addr(addr) | + svc_i3c_mctrl_rdterm(read_len), + master->regs + svc_i3c_mctrl); + + ret = readl_poll_timeout(master->regs + svc_i3c_mstatus, reg, + svc_i3c_mstatus_mctrldone(reg), 0, 1000); + if (ret) + goto emit_stop; + + if (rnw) + ret = svc_i3c_master_read(master, in, xfer_len); + else + ret = svc_i3c_master_write(master, out, xfer_len); + if (ret) + goto emit_stop; + + ret = readl_poll_timeout(master->regs + svc_i3c_mstatus, reg, + svc_i3c_mstatus_complete(reg), 0, 1000); + if (ret) + goto emit_stop; + + if (!continued) + svc_i3c_master_emit_stop(master); + + return 0; + +emit_stop: + svc_i3c_master_emit_stop(master); + svc_i3c_master_clear_merrwarn(master); + + return ret; +} + +static struct svc_i3c_xfer * +svc_i3c_master_alloc_xfer(struct svc_i3c_master *master, unsigned int ncmds) +{ + struct svc_i3c_xfer *xfer; + + xfer = kzalloc(struct_size(xfer, cmds, ncmds), gfp_kernel); + if (!xfer) + return null; + + init_list_head(&xfer->node); + xfer->ncmds = ncmds; + xfer->ret = -etimedout; + + return xfer; +} + +static void svc_i3c_master_free_xfer(struct svc_i3c_xfer *xfer) +{ + kfree(xfer); +} + +static void svc_i3c_master_dequeue_xfer_locked(struct svc_i3c_master *master, + struct svc_i3c_xfer *xfer) +{ + if (master->xferqueue.cur == xfer) + master->xferqueue.cur = null; + else + list_del_init(&xfer->node); +} + +static void svc_i3c_master_dequeue_xfer(struct svc_i3c_master *master, + struct svc_i3c_xfer *xfer) +{ + unsigned long flags; + + spin_lock_irqsave(&master->xferqueue.lock, flags); + svc_i3c_master_dequeue_xfer_locked(master, xfer); + spin_unlock_irqrestore(&master->xferqueue.lock, flags); +} + +static void svc_i3c_master_start_xfer_locked(struct svc_i3c_master *master) +{ + struct svc_i3c_xfer *xfer = master->xferqueue.cur; + int ret, i; + + if (!xfer) + return; + + for (i = 0; i < xfer->ncmds; i++) { + struct svc_i3c_cmd *cmd = &xfer->cmds[i]; + + ret = svc_i3c_master_xfer(master, cmd->rnw, xfer->type, + cmd->addr, cmd->in, cmd->out, + cmd->len, cmd->read_len, + cmd->continued); + if (ret) + break; + } + + xfer->ret = ret; + complete(&xfer->comp); + + if (ret < 0) + svc_i3c_master_dequeue_xfer_locked(master, xfer); + + xfer = list_first_entry_or_null(&master->xferqueue.list, + struct svc_i3c_xfer, + node); + if (xfer) + list_del_init(&xfer->node); + + master->xferqueue.cur = xfer; + svc_i3c_master_start_xfer_locked(master); +} + +static void svc_i3c_master_enqueue_xfer(struct svc_i3c_master *master, + struct svc_i3c_xfer *xfer) +{ + unsigned long flags; + + init_completion(&xfer->comp); + spin_lock_irqsave(&master->xferqueue.lock, flags); + if (master->xferqueue.cur) { + list_add_tail(&xfer->node, &master->xferqueue.list); + } else { + master->xferqueue.cur = xfer; + svc_i3c_master_start_xfer_locked(master); + } + spin_unlock_irqrestore(&master->xferqueue.lock, flags); +} + +static bool +svc_i3c_master_supports_ccc_cmd(struct i3c_master_controller *master, + const struct i3c_ccc_cmd *cmd) +{ + /* no software support for ccc commands targeting more than one slave */ + return (cmd->ndests == 1); +} + +static int svc_i3c_master_send_bdcast_ccc_cmd(struct svc_i3c_master *master, + struct i3c_ccc_cmd *ccc) +{ + unsigned int xfer_len = ccc->dests[0].payload.len + 1; + struct svc_i3c_xfer *xfer; + struct svc_i3c_cmd *cmd; + u8 *buf; + int ret; + + xfer = svc_i3c_master_alloc_xfer(master, 1); + if (!xfer) + return -enomem; + + buf = kmalloc(xfer_len, gfp_kernel); + if (!buf) { + svc_i3c_master_free_xfer(xfer); + return -enomem; + } + + buf[0] = ccc->id; + memcpy(&buf[1], ccc->dests[0].payload.data, ccc->dests[0].payload.len); + + xfer->type = svc_i3c_mctrl_type_i3c; + + cmd = &xfer->cmds[0]; + cmd->addr = ccc->dests[0].addr; + cmd->rnw = ccc->rnw; + cmd->in = null; + cmd->out = buf; + cmd->len = xfer_len; + cmd->read_len = 0; + cmd->continued = false; + + svc_i3c_master_enqueue_xfer(master, xfer); + if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) + svc_i3c_master_dequeue_xfer(master, xfer); + + ret = xfer->ret; + kfree(buf); + svc_i3c_master_free_xfer(xfer); + + return ret; +} + +static int svc_i3c_master_send_direct_ccc_cmd(struct svc_i3c_master *master, + struct i3c_ccc_cmd *ccc) +{ + unsigned int xfer_len = ccc->dests[0].payload.len; + unsigned int read_len = ccc->rnw ? xfer_len : 0; + struct svc_i3c_xfer *xfer; + struct svc_i3c_cmd *cmd; + int ret; + + xfer = svc_i3c_master_alloc_xfer(master, 2); + if (!xfer) + return -enomem; + + xfer->type = svc_i3c_mctrl_type_i3c; + + /* broadcasted message */ + cmd = &xfer->cmds[0]; + cmd->addr = i3c_broadcast_addr; + cmd->rnw = 0; + cmd->in = null; + cmd->out = &ccc->id; + cmd->len = 1; + cmd->read_len = xfer_len; + cmd->read_len = 0; + cmd->continued = true; + + /* directed message */ + cmd = &xfer->cmds[1]; + cmd->addr = ccc->dests[0].addr; + cmd->rnw = ccc->rnw; + cmd->in = ccc->rnw ? ccc->dests[0].payload.data : null; + cmd->out = ccc->rnw ? null : ccc->dests[0].payload.data, + cmd->len = xfer_len; + cmd->read_len = read_len; + cmd->continued = false; + + svc_i3c_master_enqueue_xfer(master, xfer); + if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) + svc_i3c_master_dequeue_xfer(master, xfer); + + ret = xfer->ret; + svc_i3c_master_free_xfer(xfer); + + return ret; +} + +static int svc_i3c_master_send_ccc_cmd(struct i3c_master_controller *m, + struct i3c_ccc_cmd *cmd) +{ + struct svc_i3c_master *master = to_svc_i3c_master(m); + bool broadcast = cmd->id < 0x80; + + if (broadcast) + return svc_i3c_master_send_bdcast_ccc_cmd(master, cmd); + else + return svc_i3c_master_send_direct_ccc_cmd(master, cmd); +} + +static int svc_i3c_master_priv_xfers(struct i3c_dev_desc *dev, + struct i3c_priv_xfer *xfers, + int nxfers) +{ + struct i3c_master_controller *m = i3c_dev_get_master(dev); + struct svc_i3c_master *master = to_svc_i3c_master(m); + struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); + struct svc_i3c_xfer *xfer; + int ret, i; + + xfer = svc_i3c_master_alloc_xfer(master, nxfers); + if (!xfer) + return -enomem; + + xfer->type = svc_i3c_mctrl_type_i3c; + + for (i = 0; i < nxfers; i++) { + struct svc_i3c_cmd *cmd = &xfer->cmds[i]; + + cmd->addr = master->addrs[data->index]; + cmd->rnw = xfers[i].rnw; + cmd->in = xfers[i].rnw ? xfers[i].data.in : null; + cmd->out = xfers[i].rnw ? null : xfers[i].data.out; + cmd->len = xfers[i].len; + cmd->read_len = xfers[i].rnw ? xfers[i].len : 0; + cmd->continued = (i + 1) < nxfers; + } + + svc_i3c_master_enqueue_xfer(master, xfer); + if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) + svc_i3c_master_dequeue_xfer(master, xfer); + + ret = xfer->ret; + svc_i3c_master_free_xfer(xfer); + + return ret; +} + +static int svc_i3c_master_i2c_xfers(struct i2c_dev_desc *dev, + const struct i2c_msg *xfers, + int nxfers) +{ + struct i3c_master_controller *m = i2c_dev_get_master(dev); + struct svc_i3c_master *master = to_svc_i3c_master(m); + struct svc_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); + struct svc_i3c_xfer *xfer; + int ret, i; + + xfer = svc_i3c_master_alloc_xfer(master, nxfers); + if (!xfer) + return -enomem; + + xfer->type = svc_i3c_mctrl_type_i2c; + + for (i = 0; i < nxfers; i++) { + struct svc_i3c_cmd *cmd = &xfer->cmds[i]; + + cmd->addr = master->addrs[data->index]; + cmd->rnw = xfers[i].flags & i2c_m_rd; + cmd->in = cmd->rnw ? xfers[i].buf : null; + cmd->out = cmd->rnw ? null : xfers[i].buf; + cmd->len = xfers[i].len; + cmd->read_len = cmd->rnw ? xfers[i].len : 0; + cmd->continued = (i + 1 < nxfers); + } + + svc_i3c_master_enqueue_xfer(master, xfer); + if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) + svc_i3c_master_dequeue_xfer(master, xfer); + + ret = xfer->ret; + svc_i3c_master_free_xfer(xfer); + + return ret; +} + +static int svc_i3c_master_request_ibi(struct i3c_dev_desc *dev, + const struct i3c_ibi_setup *req) +{ + struct i3c_master_controller *m = i3c_dev_get_master(dev); + struct svc_i3c_master *master = to_svc_i3c_master(m); + struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); + unsigned long flags; + unsigned int i; + + if (dev->ibi->max_payload_len > svc_i3c_fifo_size) { + dev_err(master->dev, "ibi max payload %d should be < %d ", + dev->ibi->max_payload_len, svc_i3c_fifo_size); + return -erange; + } + + data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req); + if (is_err(data->ibi_pool)) + return ptr_err(data->ibi_pool); + + spin_lock_irqsave(&master->ibi.lock, flags); + for (i = 0; i < master->ibi.num_slots; i++) { + if (!master->ibi.slots[i]) { + data->ibi = i; + master->ibi.slots[i] = dev; + break; + } + } + spin_unlock_irqrestore(&master->ibi.lock, flags); + + if (i < master->ibi.num_slots) + return 0; + + i3c_generic_ibi_free_pool(data->ibi_pool); + data->ibi_pool = null; + + return -enospc; +} + +static void svc_i3c_master_free_ibi(struct i3c_dev_desc *dev) +{ + struct i3c_master_controller *m = i3c_dev_get_master(dev); + struct svc_i3c_master *master = to_svc_i3c_master(m); + struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); + unsigned long flags; + + spin_lock_irqsave(&master->ibi.lock, flags); + master->ibi.slots[data->ibi] = null; + data->ibi = -1; + spin_unlock_irqrestore(&master->ibi.lock, flags); + + i3c_generic_ibi_free_pool(data->ibi_pool); +} + +static int svc_i3c_master_enable_ibi(struct i3c_dev_desc *dev) +{ + struct i3c_master_controller *m = i3c_dev_get_master(dev); + + return i3c_master_enec_locked(m, dev->info.dyn_addr, i3c_ccc_event_sir); +} + +static int svc_i3c_master_disable_ibi(struct i3c_dev_desc *dev) +{ + struct i3c_master_controller *m = i3c_dev_get_master(dev); + + return i3c_master_disec_locked(m, dev->info.dyn_addr, i3c_ccc_event_sir); +} + +static void svc_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev, + struct i3c_ibi_slot *slot) +{ + struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); + + i3c_generic_ibi_recycle_slot(data->ibi_pool, slot); +} + +static const struct i3c_master_controller_ops svc_i3c_master_ops = { + .bus_init = svc_i3c_master_bus_init, + .bus_cleanup = svc_i3c_master_bus_cleanup, + .attach_i3c_dev = svc_i3c_master_attach_i3c_dev, + .detach_i3c_dev = svc_i3c_master_detach_i3c_dev, + .reattach_i3c_dev = svc_i3c_master_reattach_i3c_dev, + .attach_i2c_dev = svc_i3c_master_attach_i2c_dev, + .detach_i2c_dev = svc_i3c_master_detach_i2c_dev, + .do_daa = svc_i3c_master_do_daa, + .supports_ccc_cmd = svc_i3c_master_supports_ccc_cmd, + .send_ccc_cmd = svc_i3c_master_send_ccc_cmd, + .priv_xfers = svc_i3c_master_priv_xfers, + .i2c_xfers = svc_i3c_master_i2c_xfers, + .request_ibi = svc_i3c_master_request_ibi, + .free_ibi = svc_i3c_master_free_ibi, + .recycle_ibi_slot = svc_i3c_master_recycle_ibi_slot, + .enable_ibi = svc_i3c_master_enable_ibi, + .disable_ibi = svc_i3c_master_disable_ibi, +}; + +static void svc_i3c_master_reset(struct svc_i3c_master *master) +{ + u32 reg; + + /* clear pending warnings */ + writel(readl(master->regs + svc_i3c_merrwarn), + master->regs + svc_i3c_merrwarn); + + /* set rx and tx tigger levels, flush fifos */ + reg = svc_i3c_mdatactrl_flushtb | + svc_i3c_mdatactrl_flushrb | + svc_i3c_mdatactrl_unlock_trig | + svc_i3c_mdatactrl_txtrig_fifo_not_full | + svc_i3c_mdatactrl_rxtrig_fifo_not_empty; + writel(reg, master->regs + svc_i3c_mdatactrl); + + svc_i3c_master_disable_interrupts(master); +} + +static int svc_i3c_master_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct svc_i3c_master *master; + int ret; + + master = devm_kzalloc(dev, sizeof(*master), gfp_kernel); + if (!master) + return -enomem; + + master->regs = devm_platform_ioremap_resource(pdev, 0); + if (is_err(master->regs)) + return ptr_err(master->regs); + + master->pclk = devm_clk_get(dev, "pclk"); + if (is_err(master->pclk)) + return ptr_err(master->pclk); + + master->fclk = devm_clk_get(dev, "fast_clk"); + if (is_err(master->fclk)) + return ptr_err(master->fclk); + + master->sclk = devm_clk_get(dev, "slow_clk"); + if (is_err(master->sclk)) + return ptr_err(master->sclk); + + master->irq = platform_get_irq(pdev, 0); + if (master->irq <= 0) + return -enoent; + + master->dev = dev; + + svc_i3c_master_reset(master); + + ret = clk_prepare_enable(master->pclk); + if (ret) + return ret; + + ret = clk_prepare_enable(master->fclk); + if (ret) + goto err_disable_pclk; + + ret = clk_prepare_enable(master->sclk); + if (ret) + goto err_disable_fclk; + + init_work(&master->hj_work, svc_i3c_master_hj_work); + init_work(&master->ibi_work, svc_i3c_master_ibi_work); + ret = devm_request_irq(dev, master->irq, svc_i3c_master_irq_handler, + irqf_no_suspend, "svc-i3c-irq", master); + if (ret) + goto err_disable_sclk; + + master->free_slots = genmask(svc_i3c_max_devs - 1, 0); + + spin_lock_init(&master->xferqueue.lock); + init_list_head(&master->xferqueue.list); + + spin_lock_init(&master->ibi.lock); + master->ibi.num_slots = svc_i3c_max_devs; + master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots, + sizeof(*master->ibi.slots), + gfp_kernel); + if (!master->ibi.slots) { + ret = -enomem; + goto err_disable_sclk; + } + + platform_set_drvdata(pdev, master); + + /* register the master */ + ret = i3c_master_register(&master->base, &pdev->dev, + &svc_i3c_master_ops, false); + if (ret) + goto err_disable_sclk; + + return 0; + +err_disable_sclk: + clk_disable_unprepare(master->sclk); + +err_disable_fclk: + clk_disable_unprepare(master->fclk); + +err_disable_pclk: + clk_disable_unprepare(master->pclk); + + return ret; +} + +static int svc_i3c_master_remove(struct platform_device *pdev) +{ + struct svc_i3c_master *master = platform_get_drvdata(pdev); + int ret; + + ret = i3c_master_unregister(&master->base); + if (ret) + return ret; + + free_irq(master->irq, master); + clk_disable_unprepare(master->pclk); + clk_disable_unprepare(master->fclk); + clk_disable_unprepare(master->sclk); + + return 0; +} + +static const struct of_device_id svc_i3c_master_of_match_tbl[] = { + { .compatible = "silvaco,i3c-master" }, + { /* sentinel */ }, +}; + +static struct platform_driver svc_i3c_master = { + .probe = svc_i3c_master_probe, + .remove = svc_i3c_master_remove, + .driver = { + .name = "silvaco-i3c-master", + .of_match_table = svc_i3c_master_of_match_tbl, + }, +}; +module_platform_driver(svc_i3c_master); + +module_author("conor culhane <conor.culhane@silvaco.com>"); +module_author("miquel raynal <miquel.raynal@bootlin.com>"); +module_description("silvaco dual-role i3c master driver"); +module_license("gpl v2");
|
Inter-Integrated Circuit (I2C + I3C)
|
dd3c52846d5954acd43f0e771689302f27dadc28
|
miquel raynal
|
drivers
|
i3c
|
master
|
hwmon: add aht10 temperature and humidity sensor driver
|
this patch adds a hwmon driver for the aht10 temperature and humidity sensor. it has a maximum sample rate, as the datasheet states that the chip may heat up if it is sampled more than once every two seconds.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add aht10 temperature and humidity sensor driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['makefile', 'kconfig', 'c', 'rst']
| 5
| 404
| 0
|
--- diff --git a/documentation/hwmon/aht10.rst b/documentation/hwmon/aht10.rst --- /dev/null +++ b/documentation/hwmon/aht10.rst +.. spdx-license-identifier: gpl-2.0 + +kernel driver aht10 +===================== + +supported chips: + + * aosong aht10 + + prefix: 'aht10' + + addresses scanned: none + + datasheet: + + chinese: http://www.aosong.com/userfiles/files/media/aht10%e4%ba%a7%e5%93%81%e6%89%8b%e5%86%8c%20a3%2020201210.pdf + english: https://server4.eca.ir/eshop/aht10/aosong_aht10_en_draft_0c.pdf + +author: johannes cornelis draaijer <jcdra1@gmail.com> + + +description +----------- + +the aht10 is a temperature and humidity sensor + +the address of this i2c device may only be 0x38 + +usage notes +----------- + +this driver does not probe for aht10 devices, as there is no reliable +way to determine if an i2c chip is or isn't an aht10. the device has +to be instantiated explicitly with the address 0x38. see +documentation/i2c/instantiating-devices.rst for details. + +sysfs entries +------------- + +=============== ============================================ +temp1_input measured temperature in millidegrees celcius +humidity1_input measured humidity in %h +update_interval the minimum interval for polling the sensor, + in milliseconds. writable. must be at + least 2000. +=============== ============================================ diff --git a/documentation/hwmon/index.rst b/documentation/hwmon/index.rst --- a/documentation/hwmon/index.rst +++ b/documentation/hwmon/index.rst + aht10 diff --git a/drivers/hwmon/kconfig b/drivers/hwmon/kconfig --- a/drivers/hwmon/kconfig +++ b/drivers/hwmon/kconfig +config sensors_aht10 + tristate "aosong aht10" + depends on i2c + help + if you say yes here, you get support for the aosong aht10 + temperature and humidity sensors + + this driver can also be built as a module. if so, the module + will be called aht10. + diff --git a/drivers/hwmon/makefile b/drivers/hwmon/makefile --- a/drivers/hwmon/makefile +++ b/drivers/hwmon/makefile +obj-$(config_sensors_aht10) += aht10.o diff --git a/drivers/hwmon/aht10.c b/drivers/hwmon/aht10.c --- /dev/null +++ b/drivers/hwmon/aht10.c +// spdx-license-identifier: gpl-2.0-only + +/* + * aht10.c - linux hwmon driver for aht10 temperature and humidity sensor + * copyright (c) 2020 johannes cornelis draaijer + */ + +#include <linux/delay.h> +#include <linux/hwmon.h> +#include <linux/i2c.h> +#include <linux/ktime.h> +#include <linux/module.h> + +#define aht10_meas_size 6 + +/* + * poll intervals (in milliseconds) + */ +#define aht10_default_min_poll_interval 2000 +#define aht10_min_poll_interval 2000 + +/* + * i2c command delays (in microseconds) + */ +#define aht10_meas_delay 80000 +#define aht10_cmd_delay 350000 +#define aht10_delay_extra 100000 + +/* + * command bytes + */ +#define aht10_cmd_init 0b11100001 +#define aht10_cmd_meas 0b10101100 +#define aht10_cmd_rst 0b10111010 + +/* + * flags in the answer byte/command + */ +#define aht10_cal_enabled bit(3) +#define aht10_busy bit(7) +#define aht10_mode_nor (bit(5) | bit(6)) +#define aht10_mode_cyc bit(5) +#define aht10_mode_cmd bit(6) + +#define aht10_max_poll_interval_len 30 + +/** + * struct aht10_data - all the data required to operate an aht10 chip + * @client: the i2c client associated with the aht10 + * @lock: a mutex that is used to prevent parallel access to the + * i2c client + * @min_poll_interval: the minimum poll interval + * while the poll rate limit is not 100% necessary, + * the datasheet recommends that a measurement + * is not performed too often to prevent + * the chip from warming up due to the heat it generates. + * if it's unwanted, it can be ignored setting it to + * it to 0. default value is 2000 ms + * @previous_poll_time: the previous time that the aht10 + * was polled + * @temperature: the latest temperature value received from + * the aht10 + * @humidity: the latest humidity value received from the + * aht10 + */ + +struct aht10_data { + struct i2c_client *client; + /* + * prevent simultaneous access to the i2c + * client and previous_poll_time + */ + struct mutex lock; + ktime_t min_poll_interval; + ktime_t previous_poll_time; + int temperature; + int humidity; +}; + +/** + * aht10_init() - initialize an aht10 chip + * @client: the i2c client associated with the aht10 + * @data: the data associated with this aht10 chip + * return: 0 if succesfull, 1 if not + */ +static int aht10_init(struct aht10_data *data) +{ + const u8 cmd_init[] = {aht10_cmd_init, aht10_cal_enabled | aht10_mode_cyc, + 0x00}; + int res; + u8 status; + struct i2c_client *client = data->client; + + res = i2c_master_send(client, cmd_init, 3); + if (res < 0) + return res; + + usleep_range(aht10_cmd_delay, aht10_cmd_delay + + aht10_delay_extra); + + res = i2c_master_recv(client, &status, 1); + if (res != 1) + return -enodata; + + if (status & aht10_busy) + return -ebusy; + + return 0; +} + +/** + * aht10_polltime_expired() - check if the minimum poll interval has + * expired + * @data: the data containing the time to compare + * return: 1 if the minimum poll interval has expired, 0 if not + */ +static int aht10_polltime_expired(struct aht10_data *data) +{ + ktime_t current_time = ktime_get_boottime(); + ktime_t difference = ktime_sub(current_time, data->previous_poll_time); + + return ktime_after(difference, data->min_poll_interval); +} + +/** + * aht10_read_values() - read and parse the raw data from the aht10 + * @aht10_data: the struct aht10_data to use for the lock + * return: 0 if succesfull, 1 if not + */ +static int aht10_read_values(struct aht10_data *data) +{ + const u8 cmd_meas[] = {aht10_cmd_meas, 0x33, 0x00}; + u32 temp, hum; + int res; + u8 raw_data[aht10_meas_size]; + struct i2c_client *client = data->client; + + mutex_lock(&data->lock); + if (aht10_polltime_expired(data)) { + res = i2c_master_send(client, cmd_meas, sizeof(cmd_meas)); + if (res < 0) + return res; + + usleep_range(aht10_meas_delay, + aht10_meas_delay + aht10_delay_extra); + + res = i2c_master_recv(client, raw_data, aht10_meas_size); + if (res != aht10_meas_size) { + mutex_unlock(&data->lock); + if (res >= 0) + return -enodata; + else + return res; + } + + hum = ((u32)raw_data[1] << 12u) | + ((u32)raw_data[2] << 4u) | + ((raw_data[3] & 0xf0u) >> 4u); + + temp = ((u32)(raw_data[3] & 0x0fu) << 16u) | + ((u32)raw_data[4] << 8u) | + raw_data[5]; + + temp = ((temp * 625) >> 15u) * 10; + hum = ((hum * 625) >> 16u) * 10; + + data->temperature = (int)temp - 50000; + data->humidity = hum; + data->previous_poll_time = ktime_get_boottime(); + } + mutex_unlock(&data->lock); + return 0; +} + +/** + * aht10_interval_write() - store the given minimum poll interval. + * return: 0 on success, -einval if a value lower than the + * aht10_min_poll_interval is given + */ +static ssize_t aht10_interval_write(struct aht10_data *data, + long val) +{ + data->min_poll_interval = ms_to_ktime(clamp_val(val, 2000, long_max)); + return 0; +} + +/** + * aht10_interval_read() - read the minimum poll interval + * in milliseconds + */ +static ssize_t aht10_interval_read(struct aht10_data *data, + long *val) +{ + *val = ktime_to_ms(data->min_poll_interval); + return 0; +} + +/** + * aht10_temperature1_read() - read the temperature in millidegrees + */ +static int aht10_temperature1_read(struct aht10_data *data, long *val) +{ + int res; + + res = aht10_read_values(data); + if (res < 0) + return res; + + *val = data->temperature; + return 0; +} + +/** + * aht10_humidity1_read() - read the relative humidity in millipercent + */ +static int aht10_humidity1_read(struct aht10_data *data, long *val) +{ + int res; + + res = aht10_read_values(data); + if (res < 0) + return res; + + *val = data->humidity; + return 0; +} + +static umode_t aht10_hwmon_visible(const void *data, enum hwmon_sensor_types type, + u32 attr, int channel) +{ + switch (type) { + case hwmon_temp: + case hwmon_humidity: + return 0444; + case hwmon_chip: + return 0644; + default: + return 0; + } +} + +static int aht10_hwmon_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + struct aht10_data *data = dev_get_drvdata(dev); + + switch (type) { + case hwmon_temp: + return aht10_temperature1_read(data, val); + case hwmon_humidity: + return aht10_humidity1_read(data, val); + case hwmon_chip: + return aht10_interval_read(data, val); + default: + return -eopnotsupp; + } +} + +static int aht10_hwmon_write(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long val) +{ + struct aht10_data *data = dev_get_drvdata(dev); + + switch (type) { + case hwmon_chip: + return aht10_interval_write(data, val); + default: + return -eopnotsupp; + } +} + +static const struct hwmon_channel_info *aht10_info[] = { + hwmon_channel_info(chip, hwmon_c_update_interval), + hwmon_channel_info(temp, hwmon_t_input), + hwmon_channel_info(humidity, hwmon_h_input), + null, +}; + +static const struct hwmon_ops aht10_hwmon_ops = { + .is_visible = aht10_hwmon_visible, + .read = aht10_hwmon_read, + .write = aht10_hwmon_write, +}; + +static const struct hwmon_chip_info aht10_chip_info = { + .ops = &aht10_hwmon_ops, + .info = aht10_info, +}; + +static int aht10_probe(struct i2c_client *client, + const struct i2c_device_id *aht10_id) +{ + struct device *device = &client->dev; + struct device *hwmon_dev; + struct aht10_data *data; + int res; + + if (!i2c_check_functionality(client->adapter, i2c_func_i2c)) + return -enoent; + + data = devm_kzalloc(device, sizeof(*data), gfp_kernel); + if (!data) + return -enomem; + + data->min_poll_interval = ms_to_ktime(aht10_default_min_poll_interval); + data->client = client; + + mutex_init(&data->lock); + + res = aht10_init(data); + if (res < 0) + return res; + + res = aht10_read_values(data); + if (res < 0) + return res; + + hwmon_dev = devm_hwmon_device_register_with_info(device, + client->name, + data, + &aht10_chip_info, + null); + + return ptr_err_or_zero(hwmon_dev); +} + +static const struct i2c_device_id aht10_id[] = { + { "aht10", 0 }, + { }, +}; +module_device_table(i2c, aht10_id); + +static struct i2c_driver aht10_driver = { + .driver = { + .name = "aht10", + }, + .probe = aht10_probe, + .id_table = aht10_id, +}; + +module_i2c_driver(aht10_driver); + +module_author("johannes cornelis draaijer <jcdra1@gmail.com>"); +module_description("aht10 temperature and humidity sensor driver"); +module_version("1.0"); +module_license("gpl v2");
|
Hardware monitoring (hwmon)
|
8c78f0dee4371ab3b0422edf08597525c6219512
|
johannes cornelis draaijer datdenkikniet
|
documentation
|
hwmon
| |
hwmon: add texas instruments tps23861 driver
|
add basic monitoring support as well as port on/off control for texas instruments tps23861 poe pse ic.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add texas instruments tps23861 driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['makefile', 'kconfig', 'c', 'rst']
| 5
| 655
| 0
|
--- diff --git a/documentation/hwmon/index.rst b/documentation/hwmon/index.rst --- a/documentation/hwmon/index.rst +++ b/documentation/hwmon/index.rst + tps23861 diff --git a/documentation/hwmon/tps23861.rst b/documentation/hwmon/tps23861.rst --- /dev/null +++ b/documentation/hwmon/tps23861.rst +.. spdx-license-identifier: gpl-2.0-only + +kernel driver tps23861 +====================== + +supported chips: + * texas instruments tps23861 + + prefix: 'tps23861' + + datasheet: https://www.ti.com/lit/gpn/tps23861 + +author: robert marko <robert.marko@sartura.hr> + +description +----------- + +this driver supports hardware monitoring for texas instruments tps23861 poe pse. + +tps23861 is a quad port ieee802.3at pse controller with optional i2c control +and monitoring capabilities. + +tps23861 offers three modes of operation: auto, semi-auto and manual. + +this driver only supports the auto mode of operation providing monitoring +as well as enabling/disabling the four ports. + +sysfs entries +------------- + +======================= ===================================================================== +in[0-3]_input voltage on ports [1-4] +in[0-3]_label "port[1-4]" +in4_input ic input voltage +in4_label "input" +temp1_input ic die temperature +temp1_label "die" +curr[1-4]_input current on ports [1-4] +in[1-4]_label "port[1-4]" +in[0-3]_enable enable/disable ports [1-4] +======================= ===================================================================== diff --git a/drivers/hwmon/kconfig b/drivers/hwmon/kconfig --- a/drivers/hwmon/kconfig +++ b/drivers/hwmon/kconfig +config sensors_tps23861 + tristate "texas instruments tps23861 poe pse" + depends on i2c + select regmap_i2c + help + if you say yes here you get support for texas instruments + tps23861 802.3at poe pse chips. + + this driver can also be built as a module. if so, the module + will be called tps23861. + diff --git a/drivers/hwmon/makefile b/drivers/hwmon/makefile --- a/drivers/hwmon/makefile +++ b/drivers/hwmon/makefile +obj-$(config_sensors_tps23861) += tps23861.o diff --git a/drivers/hwmon/tps23861.c b/drivers/hwmon/tps23861.c --- /dev/null +++ b/drivers/hwmon/tps23861.c +// spdx-license-identifier: gpl-2.0-only +/* + * copyright (c) 2020 sartura ltd. + * + * driver for the ti tps23861 poe pse. + * + * author: robert marko <robert.marko@sartura.hr> + */ + +#include <linux/bitfield.h> +#include <linux/debugfs.h> +#include <linux/delay.h> +#include <linux/hwmon-sysfs.h> +#include <linux/hwmon.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regmap.h> + +#define temperature 0x2c +#define input_voltage_lsb 0x2e +#define input_voltage_msb 0x2f +#define port_1_current_lsb 0x30 +#define port_1_current_msb 0x31 +#define port_1_voltage_lsb 0x32 +#define port_1_voltage_msb 0x33 +#define port_2_current_lsb 0x34 +#define port_2_current_msb 0x35 +#define port_2_voltage_lsb 0x36 +#define port_2_voltage_msb 0x37 +#define port_3_current_lsb 0x38 +#define port_3_current_msb 0x39 +#define port_3_voltage_lsb 0x3a +#define port_3_voltage_msb 0x3b +#define port_4_current_lsb 0x3c +#define port_4_current_msb 0x3d +#define port_4_voltage_lsb 0x3e +#define port_4_voltage_msb 0x3f +#define port_n_current_lsb_offset 0x04 +#define port_n_voltage_lsb_offset 0x04 +#define voltage_current_mask genmask(13, 0) +#define port_1_resistance_lsb 0x60 +#define port_1_resistance_msb 0x61 +#define port_2_resistance_lsb 0x62 +#define port_2_resistance_msb 0x63 +#define port_3_resistance_lsb 0x64 +#define port_3_resistance_msb 0x65 +#define port_4_resistance_lsb 0x66 +#define port_4_resistance_msb 0x67 +#define port_n_resistance_lsb_offset 0x02 +#define port_resistance_mask genmask(13, 0) +#define port_resistance_rsn_mask genmask(15, 14) +#define port_resistance_rsn_other 0 +#define port_resistance_rsn_low 1 +#define port_resistance_rsn_open 2 +#define port_resistance_rsn_short 3 +#define port_1_status 0x0c +#define port_2_status 0x0d +#define port_3_status 0x0e +#define port_4_status 0x0f +#define port_status_class_mask genmask(7, 4) +#define port_status_detect_mask genmask(3, 0) +#define port_class_unknown 0 +#define port_class_1 1 +#define port_class_2 2 +#define port_class_3 3 +#define port_class_4 4 +#define port_class_reserved 5 +#define port_class_0 6 +#define port_class_overcurrent 7 +#define port_class_mismatch 8 +#define port_detect_unknown 0 +#define port_detect_short 1 +#define port_detect_reserved 2 +#define port_detect_resistance_low 3 +#define port_detect_resistance_ok 4 +#define port_detect_resistance_high 5 +#define port_detect_open_circuit 6 +#define port_detect_reserved_2 7 +#define port_detect_mosfet_fault 8 +#define port_detect_legacy 9 +/* measurment beyond clamp voltage */ +#define port_detect_capacitance_invalid_beyond 10 +/* insufficient voltage delta */ +#define port_detect_capacitance_invalid_delta 11 +#define port_detect_capacitance_out_of_range 12 +#define poe_plus 0x40 +#define operating_mode 0x12 +#define operating_mode_off 0 +#define operating_mode_manual 1 +#define operating_mode_semi 2 +#define operating_mode_auto 3 +#define operating_mode_port_1_mask genmask(1, 0) +#define operating_mode_port_2_mask genmask(3, 2) +#define operating_mode_port_3_mask genmask(5, 4) +#define operating_mode_port_4_mask genmask(7, 6) + +#define detect_class_restart 0x18 +#define power_enable 0x19 +#define tps23861_num_ports 4 + +#define temperature_lsb 652 /* 0.652 degrees celsius */ +#define voltage_lsb 3662 /* 3.662 mv */ +#define shunt_resistor_default 255000 /* 255 mohm */ +#define current_lsb_255 62260 /* 62.260 ua */ +#define current_lsb_250 61039 /* 61.039 ua */ +#define resistance_lsb 110966 /* 11.0966 ohm*/ +#define resistance_lsb_low 157216 /* 15.7216 ohm*/ + +struct tps23861_data { + struct regmap *regmap; + u32 shunt_resistor; + struct i2c_client *client; + struct dentry *debugfs_dir; +}; + +static struct regmap_config tps23861_regmap_config = { + .reg_bits = 8, + .val_bits = 8, +}; + +static int tps23861_read_temp(struct tps23861_data *data, long *val) +{ + unsigned int regval; + int err; + + err = regmap_read(data->regmap, temperature, ®val); + if (err < 0) + return err; + + *val = (regval * temperature_lsb) - 20000; + + return 0; +} + +static int tps23861_read_voltage(struct tps23861_data *data, int channel, + long *val) +{ + unsigned int regval; + int err; + + if (channel < tps23861_num_ports) { + err = regmap_bulk_read(data->regmap, + port_1_voltage_lsb + channel * port_n_voltage_lsb_offset, + ®val, 2); + } else { + err = regmap_bulk_read(data->regmap, + input_voltage_lsb, + ®val, 2); + } + if (err < 0) + return err; + + *val = (field_get(voltage_current_mask, regval) * voltage_lsb) / 1000; + + return 0; +} + +static int tps23861_read_current(struct tps23861_data *data, int channel, + long *val) +{ + unsigned int current_lsb; + unsigned int regval; + int err; + + if (data->shunt_resistor == shunt_resistor_default) + current_lsb = current_lsb_255; + else + current_lsb = current_lsb_250; + + err = regmap_bulk_read(data->regmap, + port_1_current_lsb + channel * port_n_current_lsb_offset, + ®val, 2); + if (err < 0) + return err; + + *val = (field_get(voltage_current_mask, regval) * current_lsb) / 1000000; + + return 0; +} + +static int tps23861_port_disable(struct tps23861_data *data, int channel) +{ + unsigned int regval = 0; + int err; + + regval |= bit(channel + 4); + err = regmap_write(data->regmap, power_enable, regval); + + return err; +} + +static int tps23861_port_enable(struct tps23861_data *data, int channel) +{ + unsigned int regval = 0; + int err; + + regval |= bit(channel); + regval |= bit(channel + 4); + err = regmap_write(data->regmap, detect_class_restart, regval); + + return err; +} + +static umode_t tps23861_is_visible(const void *data, enum hwmon_sensor_types type, + u32 attr, int channel) +{ + switch (type) { + case hwmon_temp: + switch (attr) { + case hwmon_temp_input: + case hwmon_temp_label: + return 0444; + default: + return 0; + } + case hwmon_in: + switch (attr) { + case hwmon_in_input: + case hwmon_in_label: + return 0444; + case hwmon_in_enable: + return 0200; + default: + return 0; + } + case hwmon_curr: + switch (attr) { + case hwmon_curr_input: + case hwmon_curr_label: + return 0444; + default: + return 0; + } + default: + return 0; + } +} + +static int tps23861_write(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long val) +{ + struct tps23861_data *data = dev_get_drvdata(dev); + int err; + + switch (type) { + case hwmon_in: + switch (attr) { + case hwmon_in_enable: + if (val == 0) + err = tps23861_port_disable(data, channel); + else if (val == 1) + err = tps23861_port_enable(data, channel); + else + err = -einval; + break; + default: + return -eopnotsupp; + } + break; + default: + return -eopnotsupp; + } + + return err; +} + +static int tps23861_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + struct tps23861_data *data = dev_get_drvdata(dev); + int err; + + switch (type) { + case hwmon_temp: + switch (attr) { + case hwmon_temp_input: + err = tps23861_read_temp(data, val); + break; + default: + return -eopnotsupp; + } + break; + case hwmon_in: + switch (attr) { + case hwmon_in_input: + err = tps23861_read_voltage(data, channel, val); + break; + default: + return -eopnotsupp; + } + break; + case hwmon_curr: + switch (attr) { + case hwmon_curr_input: + err = tps23861_read_current(data, channel, val); + break; + default: + return -eopnotsupp; + } + break; + default: + return -eopnotsupp; + } + + return err; +} + +static const char * const tps23861_port_label[] = { + "port1", + "port2", + "port3", + "port4", + "input", +}; + +static int tps23861_read_string(struct device *dev, + enum hwmon_sensor_types type, + u32 attr, int channel, const char **str) +{ + switch (type) { + case hwmon_in: + case hwmon_curr: + *str = tps23861_port_label[channel]; + break; + case hwmon_temp: + *str = "die"; + break; + default: + return -eopnotsupp; + } + + return 0; +} + +static const struct hwmon_channel_info *tps23861_info[] = { + hwmon_channel_info(chip, + hwmon_c_register_tz), + hwmon_channel_info(temp, + hwmon_t_input | hwmon_t_label), + hwmon_channel_info(in, + hwmon_i_input | hwmon_i_enable | hwmon_i_label, + hwmon_i_input | hwmon_i_enable | hwmon_i_label, + hwmon_i_input | hwmon_i_enable | hwmon_i_label, + hwmon_i_input | hwmon_i_enable | hwmon_i_label, + hwmon_i_input | hwmon_i_label), + hwmon_channel_info(curr, + hwmon_c_input | hwmon_c_label, + hwmon_c_input | hwmon_c_label, + hwmon_c_input | hwmon_c_label, + hwmon_c_input | hwmon_c_label), + null +}; + +static const struct hwmon_ops tps23861_hwmon_ops = { + .is_visible = tps23861_is_visible, + .write = tps23861_write, + .read = tps23861_read, + .read_string = tps23861_read_string, +}; + +static const struct hwmon_chip_info tps23861_chip_info = { + .ops = &tps23861_hwmon_ops, + .info = tps23861_info, +}; + +static char *tps23861_port_operating_mode(struct tps23861_data *data, int port) +{ + unsigned int regval; + int mode; + + regmap_read(data->regmap, operating_mode, ®val); + + switch (port) { + case 1: + mode = field_get(operating_mode_port_1_mask, regval); + break; + case 2: + mode = field_get(operating_mode_port_2_mask, regval); + break; + case 3: + mode = field_get(operating_mode_port_3_mask, regval); + break; + case 4: + mode = field_get(operating_mode_port_4_mask, regval); + break; + default: + mode = -einval; + } + + switch (mode) { + case operating_mode_off: + return "off"; + case operating_mode_manual: + return "manual"; + case operating_mode_semi: + return "semi-auto"; + case operating_mode_auto: + return "auto"; + default: + return "invalid"; + } +} + +static char *tps23861_port_detect_status(struct tps23861_data *data, int port) +{ + unsigned int regval; + + regmap_read(data->regmap, + port_1_status + (port - 1), + ®val); + + switch (field_get(port_status_detect_mask, regval)) { + case port_detect_unknown: + return "unknown device"; + case port_detect_short: + return "short circuit"; + case port_detect_resistance_low: + return "too low resistance"; + case port_detect_resistance_ok: + return "valid resistance"; + case port_detect_resistance_high: + return "too high resistance"; + case port_detect_open_circuit: + return "open circuit"; + case port_detect_mosfet_fault: + return "mosfet fault"; + case port_detect_legacy: + return "legacy device"; + case port_detect_capacitance_invalid_beyond: + return "invalid capacitance, beyond clamp voltage"; + case port_detect_capacitance_invalid_delta: + return "invalid capacitance, insufficient voltage delta"; + case port_detect_capacitance_out_of_range: + return "valid capacitance, outside of legacy range"; + case port_detect_reserved: + case port_detect_reserved_2: + default: + return "invalid"; + } +} + +static char *tps23861_port_class_status(struct tps23861_data *data, int port) +{ + unsigned int regval; + + regmap_read(data->regmap, + port_1_status + (port - 1), + ®val); + + switch (field_get(port_status_class_mask, regval)) { + case port_class_unknown: + return "unknown"; + case port_class_reserved: + case port_class_0: + return "0"; + case port_class_1: + return "1"; + case port_class_2: + return "2"; + case port_class_3: + return "3"; + case port_class_4: + return "4"; + case port_class_overcurrent: + return "overcurrent"; + case port_class_mismatch: + return "mismatch"; + default: + return "invalid"; + } +} + +static char *tps23861_port_poe_plus_status(struct tps23861_data *data, int port) +{ + unsigned int regval; + + regmap_read(data->regmap, poe_plus, ®val); + + if (bit(port + 3) & regval) + return "yes"; + else + return "no"; +} + +static int tps23861_port_resistance(struct tps23861_data *data, int port) +{ + u16 regval; + + regmap_bulk_read(data->regmap, + port_1_resistance_lsb + port_n_resistance_lsb_offset * (port - 1), + ®val, + 2); + + switch (field_get(port_resistance_rsn_mask, regval)) { + case port_resistance_rsn_other: + return (field_get(port_resistance_mask, regval) * resistance_lsb) / 10000; + case port_resistance_rsn_low: + return (field_get(port_resistance_mask, regval) * resistance_lsb_low) / 10000; + case port_resistance_rsn_short: + case port_resistance_rsn_open: + default: + return 0; + } +} + +static int tps23861_port_status_show(struct seq_file *s, void *data) +{ + struct tps23861_data *priv = s->private; + int i; + + for (i = 1; i < tps23861_num_ports + 1; i++) { + seq_printf(s, "port: %d ", i); + seq_printf(s, "operating mode: %s ", tps23861_port_operating_mode(priv, i)); + seq_printf(s, "detected: %s ", tps23861_port_detect_status(priv, i)); + seq_printf(s, "class: %s ", tps23861_port_class_status(priv, i)); + seq_printf(s, "poe plus: %s ", tps23861_port_poe_plus_status(priv, i)); + seq_printf(s, "resistance: %d ", tps23861_port_resistance(priv, i)); + seq_putc(s, ' '); + } + + return 0; +} + +define_show_attribute(tps23861_port_status); + +static void tps23861_init_debugfs(struct tps23861_data *data) +{ + data->debugfs_dir = debugfs_create_dir(data->client->name, null); + + debugfs_create_file("port_status", + 0400, + data->debugfs_dir, + data, + &tps23861_port_status_fops); +} + +static int tps23861_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct tps23861_data *data; + struct device *hwmon_dev; + u32 shunt_resistor; + + data = devm_kzalloc(dev, sizeof(*data), gfp_kernel); + if (!data) + return -enomem; + + data->client = client; + i2c_set_clientdata(client, data); + + data->regmap = devm_regmap_init_i2c(client, &tps23861_regmap_config); + if (is_err(data->regmap)) { + dev_err(dev, "failed to allocate register map "); + return ptr_err(data->regmap); + } + + if (!of_property_read_u32(dev->of_node, "shunt-resistor-micro-ohms", &shunt_resistor)) + data->shunt_resistor = shunt_resistor; + else + data->shunt_resistor = shunt_resistor_default; + + hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, + data, &tps23861_chip_info, + null); + if (is_err(hwmon_dev)) + return ptr_err(hwmon_dev); + + tps23861_init_debugfs(data); + + return 0; +} + +static int tps23861_remove(struct i2c_client *client) +{ + struct tps23861_data *data = i2c_get_clientdata(client); + + debugfs_remove_recursive(data->debugfs_dir); + + return 0; +} + +static const struct of_device_id __maybe_unused tps23861_of_match[] = { + { .compatible = "ti,tps23861", }, + { }, +}; +module_device_table(of, tps23861_of_match); + +static struct i2c_driver tps23861_driver = { + .probe_new = tps23861_probe, + .remove = tps23861_remove, + .driver = { + .name = "tps23861", + .of_match_table = of_match_ptr(tps23861_of_match), + }, +}; +module_i2c_driver(tps23861_driver); + +module_license("gpl"); +module_author("robert marko <robert.marko@sartura.hr>"); +module_description("ti tps23861 poe pse");
|
Hardware monitoring (hwmon)
|
fff7b8ab225547828db9c57cdf05a03d5b4a7153
|
robert marko guenter roeck linux roeck us net
|
documentation
|
hwmon
| |
hwmon: (amd_energy) add amd family 19h model 30h x86 match
|
add x86 cpu match for amd family 19h model 30h. this is necessary to enable support for energy reporting via the amd_energy module.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add amd family 19h model 30h x86 match
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amd_energy']
|
['c']
| 1
| 1
| 0
|
--- diff --git a/drivers/hwmon/amd_energy.c b/drivers/hwmon/amd_energy.c --- a/drivers/hwmon/amd_energy.c +++ b/drivers/hwmon/amd_energy.c + x86_match_vendor_fam_model(amd, 0x19, 0x30, null),
|
Hardware monitoring (hwmon)
|
9f56b8eb85927c6391216e4f35a7abb34847f0fd
|
naveen krishna chatradhi
|
drivers
|
hwmon
| |
hwmon: (k10temp) zen3 ryzen desktop cpus support
|
the module has only support for zen3 server cpus right now. add support for family 0x19, model 0x21 which are zen3 ryzen desktop cpus. tested on 5800x, 5900x and 5950x cpus.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
zen3 ryzen desktop cpus support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['k10temp']
|
['c']
| 1
| 2
| 1
|
--- diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c --- a/drivers/hwmon/k10temp.c +++ b/drivers/hwmon/k10temp.c - case 0x0 ... 0x1: /* zen3 */ + case 0x0 ... 0x1: /* zen3 sp3/tr */ + case 0x21: /* zen3 ryzen desktop */
|
Hardware monitoring (hwmon)
|
c8d0d3fa946976c6bc69589375d7d063f0cb1492
|
gabriel craciunescu
|
drivers
|
hwmon
| |
hwmon: (nct6683) support asrock boards
|
tested with asrock x570 phantom gaming-itx/tb3. it also appears on other asrock boards.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support asrock boards
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['nct6683']
|
['c', 'rst']
| 2
| 4
| 0
|
--- diff --git a/documentation/hwmon/nct6683.rst b/documentation/hwmon/nct6683.rst --- a/documentation/hwmon/nct6683.rst +++ b/documentation/hwmon/nct6683.rst +asrock x570 nct6683d ec firmware version 1.0 build 06/28/19 diff --git a/drivers/hwmon/nct6683.c b/drivers/hwmon/nct6683.c --- a/drivers/hwmon/nct6683.c +++ b/drivers/hwmon/nct6683.c +#define nct6683_customer_id_asrock 0xe2c + case nct6683_customer_id_asrock: + break;
|
Hardware monitoring (hwmon)
|
bd433537fef88d76e7f427bafda18791ae60e721
|
bla hrastnik
|
documentation
|
hwmon
| |
hwmon: (pmbus/max16601) add support for max16508
|
max16508 is quite similar to max16601, except that it does not support the default_num_pop register and we thus can not dynamically determine the number of populated phases.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for max16508
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['pmbus/max16601']
|
['kconfig', 'c', 'rst']
| 3
| 66
| 24
|
--- diff --git a/documentation/hwmon/max16601.rst b/documentation/hwmon/max16601.rst --- a/documentation/hwmon/max16601.rst +++ b/documentation/hwmon/max16601.rst + * maxim max16508 + + prefix: 'max16508' + + addresses scanned: - + + datasheet: not published + ----------- -this driver supports the max16601 vr13.hc dual-output voltage regulator -chipset. +this driver supports the max16508 vr13 dual-output voltage regulator +as well as the max16601 vr13.hc dual-output voltage regulator chipsets. diff --git a/drivers/hwmon/pmbus/kconfig b/drivers/hwmon/pmbus/kconfig --- a/drivers/hwmon/pmbus/kconfig +++ b/drivers/hwmon/pmbus/kconfig - tristate "maxim max16601" + tristate "maxim max16508, max16601" - max16601. + max16508 and max16601. diff --git a/drivers/hwmon/pmbus/max16601.c b/drivers/hwmon/pmbus/max16601.c --- a/drivers/hwmon/pmbus/max16601.c +++ b/drivers/hwmon/pmbus/max16601.c - * hardware monitoring driver for maxim max16601 + * hardware monitoring driver for maxim max16508 and max16601. - * ths chip supports two rails, vcore and vsa. telemetry information for the - * two rails is reported in two subsequent i2c addresses. the driver + * this chip series supports two rails, vcore and vsa. telemetry information + * for the two rails is reported in two subsequent i2c addresses. the driver +enum chips { max16508, max16601 }; + + enum chips id; + struct max16601_data *data = to_max16601_data(info); + if (data->id != max16601) + return 0; + -static int max16601_probe(struct i2c_client *client) +static const struct i2c_device_id max16601_id[] = { + {"max16508", max16508}, + {"max16601", max16601}, + {} +}; +module_device_table(i2c, max16601_id); + +static int max16601_get_id(struct i2c_client *client) - struct max16601_data *data; + enum chips id; - if (!i2c_check_functionality(client->adapter, - i2c_func_smbus_read_byte_data | - i2c_func_smbus_read_block_data)) - return -enodev; - - if (ret < 0) + if (ret < 0 || ret < 11) - /* pmbus_ic_device_id is expected to return "max16601y.xx" */ - if (ret < 11 || strncmp(buf, "max16601", 8)) { + /* + * pmbus_ic_device_id is expected to return "max16601y.xx" + * or "max16500y.xx". + */ + if (!strncmp(buf, "max16500", 8)) { + id = max16508; + } else if (!strncmp(buf, "max16601", 8)) { + id = max16601; + } else { + return id; +} + +static int max16601_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + const struct i2c_device_id *id; + struct max16601_data *data; + int ret, chip_id; + + if (!i2c_check_functionality(client->adapter, + i2c_func_smbus_read_byte_data | + i2c_func_smbus_read_block_data)) + return -enodev; + + chip_id = max16601_get_id(client); + if (chip_id < 0) + return chip_id; + + id = i2c_match_id(max16601_id, client); + if (chip_id != id->driver_data) + dev_warn(&client->dev, + "device mismatch: configured %s (%d), detected %d ", + id->name, (int) id->driver_data, chip_id); + data->id = chip_id; -static const struct i2c_device_id max16601_id[] = { - {"max16601", 0}, - {} -}; - -module_device_table(i2c, max16601_id); -
|
Hardware monitoring (hwmon)
|
66102281f94afdf1f41cf6147c7ddce73a8e75f2
|
guenter roeck alex qiu xqiu google com alex qiu xqiu google com
|
documentation
|
hwmon
|
pmbus
|
hwmon: (pmbus/max31785) support revision "b"
|
there was an issue in how the tach feedbacks of dual rotor fans were reported during any change in fan speeds with revision "a" of the max31785. when the fan speeds would transition to a new target speed, the rotor not wired to the tach input when tachsel = 0 would report a speed of 0 until the new target was reached. this has been fixed, resulting in a revision "b" update where the mfr_revision of "b" is 0x3061.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support revision "b"
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['pmbus/max31785']
|
['c']
| 1
| 9
| 4
|
--- diff --git a/drivers/hwmon/pmbus/max31785.c b/drivers/hwmon/pmbus/max31785.c --- a/drivers/hwmon/pmbus/max31785.c +++ b/drivers/hwmon/pmbus/max31785.c +#define max31785b 0x3061 - s64 ret; + int ret; - if (ret == max31785a) { + if (ret == max31785a || ret == max31785b) { - if (!strcmp("max31785a", client->name)) - dev_warn(dev, "expected max3175a, found max31785: cannot provide secondary tachometer readings "); + if (!strcmp("max31785a", client->name) || + !strcmp("max31785b", client->name)) + dev_warn(dev, "expected max31785a/b, found max31785: cannot provide secondary tachometer readings "); + dev_err(dev, "unrecognized max31785 revision: %x ", ret); + { "max31785b", 0 }, + { .compatible = "maxim,max31785b" },
|
Hardware monitoring (hwmon)
|
996dc09c8e773f348086d03ded4cb96950f116bb
|
matthew barth
|
drivers
|
hwmon
|
pmbus
|
hwmon: (pwm-fan) support multiple fan tachometers
|
the pwm-fan driver is extended to support multiple fan tachometer signals connected to gpio inputs. this is intended to support the case where a single pwm output signal is routed to multiple fans, each of which have a tachometer output connected back to a gpio pin.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support multiple fan tachometers
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['pwm-fan']
|
['c']
| 1
| 53
| 38
|
--- diff --git a/drivers/hwmon/pwm-fan.c b/drivers/hwmon/pwm-fan.c --- a/drivers/hwmon/pwm-fan.c +++ b/drivers/hwmon/pwm-fan.c - struct pwm_fan_tach *tach; + int tach_count; + struct pwm_fan_tach *tachs; + struct hwmon_channel_info fan_channel; -static const u32 pwm_fan_channel_config_fan[] = { - hwmon_f_input, - 0 -}; - -static const struct hwmon_channel_info pwm_fan_channel_fan = { - .type = hwmon_fan, - .config = pwm_fan_channel_config_fan, -}; - - struct pwm_fan_tach *tach = ctx->tach; - int pulses; + int i; - pulses = atomic_read(&tach->pulses); - atomic_sub(pulses, &tach->pulses); - tach->rpm = (unsigned int)(pulses * 1000 * 60) / - (tach->pulses_per_revolution * delta); + for (i = 0; i < ctx->tach_count; i++) { + struct pwm_fan_tach *tach = &ctx->tachs[i]; + int pulses; + + pulses = atomic_read(&tach->pulses); + atomic_sub(pulses, &tach->pulses); + tach->rpm = (unsigned int)(pulses * 1000 * 60) / + (tach->pulses_per_revolution * delta); + } - *val = ctx->tach->rpm; + *val = ctx->tachs[channel].rpm; - int tach_count; + u32 *fan_channel_config; + int channel_count = 1; /* we always have a pwm channel. */ + int i; - tach_count = platform_irq_count(pdev); - if (tach_count < 0) - return dev_err_probe(dev, tach_count, + ctx->tach_count = platform_irq_count(pdev); + if (ctx->tach_count < 0) + return dev_err_probe(dev, ctx->tach_count, + dev_dbg(dev, "%d fan tachometer inputs ", ctx->tach_count); - channels = devm_kcalloc(dev, tach_count + 2, + if (ctx->tach_count) { + channel_count++; /* we also have a fan channel. */ + + ctx->tachs = devm_kcalloc(dev, ctx->tach_count, + sizeof(struct pwm_fan_tach), + gfp_kernel); + if (!ctx->tachs) + return -enomem; + + ctx->fan_channel.type = hwmon_fan; + fan_channel_config = devm_kcalloc(dev, ctx->tach_count + 1, + sizeof(u32), gfp_kernel); + if (!fan_channel_config) + return -enomem; + ctx->fan_channel.config = fan_channel_config; + } + + channels = devm_kcalloc(dev, channel_count + 1, - if (tach_count > 0) { - struct pwm_fan_tach *tach; + for (i = 0; i < ctx->tach_count; i++) { + struct pwm_fan_tach *tach = &ctx->tachs[i]; - tach = devm_kzalloc(dev, sizeof(struct pwm_fan_tach), - gfp_kernel); - if (!tach) - return -enomem; - ctx->tach = tach; - - tach->irq = platform_get_irq(pdev, 0); + tach->irq = platform_get_irq(pdev, i); - of_property_read_u32(dev->of_node, - "pulses-per-revolution", - &ppr); + of_property_read_u32_index(dev->of_node, + "pulses-per-revolution", + i, + &ppr); - dev_dbg(dev, "tach: irq=%d, pulses_per_revolution=%d ", - tach->irq, tach->pulses_per_revolution); + fan_channel_config[i] = hwmon_f_input; + + dev_dbg(dev, "tach%d: irq=%d, pulses_per_revolution=%d ", + i, tach->irq, tach->pulses_per_revolution); + } + if (ctx->tach_count > 0) { - channels[1] = &pwm_fan_channel_fan; + channels[1] = &ctx->fan_channel;
|
Hardware monitoring (hwmon)
|
f0dc7cb6b4c9cd24a69f80423f6d7a03825b72e4
|
paul barker
|
drivers
|
hwmon
| |
hwmon: (abx500) decomission abx500 driver
|
this deletes the abx500 hwmon driver, the only supported variant being the ab8500.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
decomission abx500 driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['abx500']
|
['c', 'h', 'kconfig', 'rst', 'makefile']
| 8
| 0
| 854
|
- activation of the ntc_thermistor.c driver, - activation of thermal zones, config_thermal - in the device tree, connecting the ntc driver to the - connecting the two ntc sensors to a "chassis" thermal zone --- diff --git a/documentation/hwmon/ab8500.rst b/documentation/hwmon/ab8500.rst --- a/documentation/hwmon/ab8500.rst +++ /dev/null -kernel driver ab8500 -==================== - -supported chips: - - * st-ericsson ab8500 - - prefix: 'ab8500' - - addresses scanned: - - - datasheet: http://www.stericsson.com/developers/documentation.jsp - -authors: - - martin persson <martin.persson@stericsson.com> - - hongbo zhang <hongbo.zhang@linaro.org> - -description ------------ - -see also documentation/hwmon/abx500.rst. this is the st-ericsson ab8500 specific -driver. - -currently only the ab8500 internal sensor and one external sensor for battery -temperature are monitored. other gpadc channels can also be monitored if needed -in future. diff --git a/documentation/hwmon/abx500.rst b/documentation/hwmon/abx500.rst --- a/documentation/hwmon/abx500.rst +++ /dev/null -kernel driver abx500 -==================== - -supported chips: - - * st-ericsson abx500 series - - prefix: 'abx500' - - addresses scanned: - - - datasheet: http://www.stericsson.com/developers/documentation.jsp - -authors: - martin persson <martin.persson@stericsson.com> - hongbo zhang <hongbo.zhang@linaro.org> - -description ------------ - -every st-ericsson ux500 soc consists of both abx500 and dbx500 physically, -this is kernel hwmon driver for abx500. - -there are some gpadcs inside abx500 which are designed for connecting to -thermal sensors, and there is also a thermal sensor inside abx500 too, which -raises interrupt when critical temperature reached. - -this abx500 is a common layer which can monitor all of the sensors, every -specific abx500 chip has its special configurations in its own file, e.g. some -sensors can be configured invisible if they are not available on that chip, and -the corresponding gpadc_addr should be set to 0, thus this sensor won't be -polled. diff --git a/documentation/hwmon/index.rst b/documentation/hwmon/index.rst --- a/documentation/hwmon/index.rst +++ b/documentation/hwmon/index.rst - ab8500 - abx500 diff --git a/drivers/hwmon/kconfig b/drivers/hwmon/kconfig --- a/drivers/hwmon/kconfig +++ b/drivers/hwmon/kconfig -config sensors_ab8500 - tristate "ab8500 thermal monitoring" - depends on ab8500_gpadc && ab8500_bm && (iio = y) - default n - help - if you say yes here you get support for the thermal sensor part - of the ab8500 chip. the driver includes thermal management for - ab8500 die and two gpadc channels. the gpadc channel are preferably - used to access sensors outside the ab8500 chip. - - this driver can also be built as a module. if so, the module - will be called abx500-temp. - diff --git a/drivers/hwmon/makefile b/drivers/hwmon/makefile --- a/drivers/hwmon/makefile +++ b/drivers/hwmon/makefile -obj-$(config_sensors_ab8500) += abx500.o ab8500.o diff --git a/drivers/hwmon/ab8500.c b/drivers/hwmon/ab8500.c --- a/drivers/hwmon/ab8500.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * copyright (c) st-ericsson 2010 - 2013 - * author: martin persson <martin.persson@stericsson.com> - * hongbo zhang <hongbo.zhang@linaro.org> - * - * when the ab8500 thermal warning temperature is reached (threshold cannot - * be changed by sw), an interrupt is set, and if no further action is taken - * within a certain time frame, kernel_power_off will be called. - * - * when ab8500 thermal shutdown temperature is reached a hardware shutdown of - * the ab8500 will occur. - */ - -#include <linux/err.h> -#include <linux/hwmon.h> -#include <linux/hwmon-sysfs.h> -#include <linux/mfd/abx500.h> -#include <linux/mfd/abx500/ab8500-bm.h> -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/power/ab8500.h> -#include <linux/reboot.h> -#include <linux/slab.h> -#include <linux/sysfs.h> -#include <linux/iio/consumer.h> -#include "abx500.h" - -#define default_power_off_delay (hz * 10) -#define thermal_vcc 1800 -#define pull_up_resistor 47000 - -#define ab8500_sensor_aux1 0 -#define ab8500_sensor_aux2 1 -#define ab8500_sensor_btemp_ball 2 -#define ab8500_sensor_bat_ctrl 3 -#define num_monitored_sensors 4 - -struct ab8500_gpadc_cfg { - const struct abx500_res_to_temp *temp_tbl; - int tbl_sz; - int vcc; - int r_up; -}; - -struct ab8500_temp { - struct iio_channel *aux1; - struct iio_channel *aux2; - struct ab8500_btemp *btemp; - struct delayed_work power_off_work; - struct ab8500_gpadc_cfg cfg; - struct abx500_temp *abx500_data; -}; - -/* - * the hardware connection is like this: - * vcc----[ r_up ]-----[ ntc ]----gnd - * where r_up is pull-up resistance, and gpadc measures voltage on ntc. - * and res_to_temp table is strictly sorted by falling resistance values. - */ -static int ab8500_voltage_to_temp(struct ab8500_gpadc_cfg *cfg, - int v_ntc, int *temp) -{ - int r_ntc, i = 0, tbl_sz = cfg->tbl_sz; - const struct abx500_res_to_temp *tbl = cfg->temp_tbl; - - if (cfg->vcc < 0 || v_ntc >= cfg->vcc) - return -einval; - - r_ntc = v_ntc * cfg->r_up / (cfg->vcc - v_ntc); - if (r_ntc > tbl[0].resist || r_ntc < tbl[tbl_sz - 1].resist) - return -einval; - - while (!(r_ntc <= tbl[i].resist && r_ntc > tbl[i + 1].resist) && - i < tbl_sz - 2) - i++; - - /* return milli-celsius */ - *temp = tbl[i].temp * 1000 + ((tbl[i + 1].temp - tbl[i].temp) * 1000 * - (r_ntc - tbl[i].resist)) / (tbl[i + 1].resist - tbl[i].resist); - - return 0; -} - -static int ab8500_read_sensor(struct abx500_temp *data, u8 sensor, int *temp) -{ - int voltage, ret; - struct ab8500_temp *ab8500_data = data->plat_data; - - if (sensor == ab8500_sensor_btemp_ball) { - *temp = ab8500_btemp_get_temp(ab8500_data->btemp); - } else if (sensor == ab8500_sensor_bat_ctrl) { - *temp = ab8500_btemp_get_batctrl_temp(ab8500_data->btemp); - } else if (sensor == ab8500_sensor_aux1) { - ret = iio_read_channel_processed(ab8500_data->aux1, &voltage); - if (ret < 0) - return ret; - ret = ab8500_voltage_to_temp(&ab8500_data->cfg, voltage, temp); - if (ret < 0) - return ret; - } else if (sensor == ab8500_sensor_aux2) { - ret = iio_read_channel_processed(ab8500_data->aux2, &voltage); - if (ret < 0) - return ret; - ret = ab8500_voltage_to_temp(&ab8500_data->cfg, voltage, temp); - if (ret < 0) - return ret; - } - - return 0; -} - -static void ab8500_thermal_power_off(struct work_struct *work) -{ - struct ab8500_temp *ab8500_data = container_of(work, - struct ab8500_temp, power_off_work.work); - struct abx500_temp *abx500_data = ab8500_data->abx500_data; - - dev_warn(&abx500_data->pdev->dev, "power off due to critical temp "); - - kernel_power_off(); -} - -static ssize_t ab8500_show_name(struct device *dev, - struct device_attribute *devattr, char *buf) -{ - return sprintf(buf, "ab8500 "); -} - -static ssize_t ab8500_show_label(struct device *dev, - struct device_attribute *devattr, char *buf) -{ - char *label; - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - int index = attr->index; - - switch (index) { - case 1: - label = "ext_adc1"; - break; - case 2: - label = "ext_adc2"; - break; - case 3: - label = "bat_temp"; - break; - case 4: - label = "bat_ctrl"; - break; - default: - return -einval; - } - - return sprintf(buf, "%s ", label); -} - -static int ab8500_temp_irq_handler(int irq, struct abx500_temp *data) -{ - struct ab8500_temp *ab8500_data = data->plat_data; - - dev_warn(&data->pdev->dev, "power off in %d s ", - default_power_off_delay / hz); - - schedule_delayed_work(&ab8500_data->power_off_work, - default_power_off_delay); - return 0; -} - -int abx500_hwmon_init(struct abx500_temp *data) -{ - struct ab8500_temp *ab8500_data; - - ab8500_data = devm_kzalloc(&data->pdev->dev, sizeof(*ab8500_data), - gfp_kernel); - if (!ab8500_data) - return -enomem; - - ab8500_data->btemp = ab8500_btemp_get(); - if (is_err(ab8500_data->btemp)) - return ptr_err(ab8500_data->btemp); - - init_delayed_work(&ab8500_data->power_off_work, - ab8500_thermal_power_off); - - ab8500_data->cfg.vcc = thermal_vcc; - ab8500_data->cfg.r_up = pull_up_resistor; - ab8500_data->cfg.temp_tbl = ab8500_temp_tbl_a_thermistor; - ab8500_data->cfg.tbl_sz = ab8500_temp_tbl_a_size; - - data->plat_data = ab8500_data; - ab8500_data->aux1 = devm_iio_channel_get(&data->pdev->dev, "aux1"); - if (is_err(ab8500_data->aux1)) { - if (ptr_err(ab8500_data->aux1) == -enodev) - return -eprobe_defer; - dev_err(&data->pdev->dev, "failed to get aux1 adc channel "); - return ptr_err(ab8500_data->aux1); - } - ab8500_data->aux2 = devm_iio_channel_get(&data->pdev->dev, "aux2"); - if (is_err(ab8500_data->aux2)) { - if (ptr_err(ab8500_data->aux2) == -enodev) - return -eprobe_defer; - dev_err(&data->pdev->dev, "failed to get aux2 adc channel "); - return ptr_err(ab8500_data->aux2); - } - - data->gpadc_addr[0] = ab8500_sensor_aux1; - data->gpadc_addr[1] = ab8500_sensor_aux2; - data->gpadc_addr[2] = ab8500_sensor_btemp_ball; - data->gpadc_addr[3] = ab8500_sensor_bat_ctrl; - data->monitored_sensors = num_monitored_sensors; - - data->ops.read_sensor = ab8500_read_sensor; - data->ops.irq_handler = ab8500_temp_irq_handler; - data->ops.show_name = ab8500_show_name; - data->ops.show_label = ab8500_show_label; - data->ops.is_visible = null; - - return 0; -} -export_symbol(abx500_hwmon_init); - -module_author("hongbo zhang <hongbo.zhang@linaro.org>"); -module_description("ab8500 temperature driver"); -module_license("gpl"); diff --git a/drivers/hwmon/abx500.c b/drivers/hwmon/abx500.c --- a/drivers/hwmon/abx500.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * copyright (c) st-ericsson 2010 - 2013 - * author: martin persson <martin.persson@stericsson.com> - * hongbo zhang <hongbo.zhang@linaro.org> - * - * abx500 does not provide auto adc, so to monitor the required temperatures, - * a periodic work is used. it is more important to not wake up the cpu than - * to perform this job, hence the use of a deferred delay. - * - * a deferred delay for thermal monitor is considered safe because: - * if the chip gets too hot during a sleep state it's most likely due to - * external factors, such as the surrounding temperature. i.e. no sw decisions - * will make any difference. - */ - -#include <linux/err.h> -#include <linux/hwmon.h> -#include <linux/hwmon-sysfs.h> -#include <linux/interrupt.h> -#include <linux/jiffies.h> -#include <linux/module.h> -#include <linux/mutex.h> -#include <linux/of.h> -#include <linux/platform_device.h> -#include <linux/pm.h> -#include <linux/slab.h> -#include <linux/sysfs.h> -#include <linux/workqueue.h> -#include "abx500.h" - -#define default_monitor_delay hz -#define default_max_temp 130 - -static inline void schedule_monitor(struct abx500_temp *data) -{ - data->work_active = true; - schedule_delayed_work(&data->work, default_monitor_delay); -} - -static void threshold_updated(struct abx500_temp *data) -{ - int i; - for (i = 0; i < data->monitored_sensors; i++) - if (data->max[i] != 0 || data->min[i] != 0) { - schedule_monitor(data); - return; - } - - dev_dbg(&data->pdev->dev, "no active thresholds. "); - cancel_delayed_work_sync(&data->work); - data->work_active = false; -} - -static void gpadc_monitor(struct work_struct *work) -{ - int temp, i, ret; - char alarm_node[30]; - bool updated_min_alarm, updated_max_alarm; - struct abx500_temp *data; - - data = container_of(work, struct abx500_temp, work.work); - mutex_lock(&data->lock); - - for (i = 0; i < data->monitored_sensors; i++) { - /* thresholds are considered inactive if set to 0 */ - if (data->max[i] == 0 && data->min[i] == 0) - continue; - - if (data->max[i] < data->min[i]) - continue; - - ret = data->ops.read_sensor(data, data->gpadc_addr[i], &temp); - if (ret < 0) { - dev_err(&data->pdev->dev, "gpadc read failed "); - continue; - } - - updated_min_alarm = false; - updated_max_alarm = false; - - if (data->min[i] != 0) { - if (temp < data->min[i]) { - if (data->min_alarm[i] == false) { - data->min_alarm[i] = true; - updated_min_alarm = true; - } - } else { - if (data->min_alarm[i] == true) { - data->min_alarm[i] = false; - updated_min_alarm = true; - } - } - } - if (data->max[i] != 0) { - if (temp > data->max[i]) { - if (data->max_alarm[i] == false) { - data->max_alarm[i] = true; - updated_max_alarm = true; - } - } else if (temp < data->max[i] - data->max_hyst[i]) { - if (data->max_alarm[i] == true) { - data->max_alarm[i] = false; - updated_max_alarm = true; - } - } - } - - if (updated_min_alarm) { - ret = sprintf(alarm_node, "temp%d_min_alarm", i + 1); - sysfs_notify(&data->pdev->dev.kobj, null, alarm_node); - } - if (updated_max_alarm) { - ret = sprintf(alarm_node, "temp%d_max_alarm", i + 1); - sysfs_notify(&data->pdev->dev.kobj, null, alarm_node); - } - } - - schedule_monitor(data); - mutex_unlock(&data->lock); -} - -/* hwmon sysfs interfaces */ -static ssize_t name_show(struct device *dev, struct device_attribute *devattr, - char *buf) -{ - struct abx500_temp *data = dev_get_drvdata(dev); - /* show chip name */ - return data->ops.show_name(dev, devattr, buf); -} - -static ssize_t label_show(struct device *dev, - struct device_attribute *devattr, char *buf) -{ - struct abx500_temp *data = dev_get_drvdata(dev); - /* show each sensor label */ - return data->ops.show_label(dev, devattr, buf); -} - -static ssize_t input_show(struct device *dev, - struct device_attribute *devattr, char *buf) -{ - int ret, temp; - struct abx500_temp *data = dev_get_drvdata(dev); - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - u8 gpadc_addr = data->gpadc_addr[attr->index]; - - ret = data->ops.read_sensor(data, gpadc_addr, &temp); - if (ret < 0) - return ret; - - return sprintf(buf, "%d ", temp); -} - -/* set functions (rw nodes) */ -static ssize_t min_store(struct device *dev, struct device_attribute *devattr, - const char *buf, size_t count) -{ - unsigned long val; - struct abx500_temp *data = dev_get_drvdata(dev); - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - int res = kstrtol(buf, 10, &val); - if (res < 0) - return res; - - val = clamp_val(val, 0, default_max_temp); - - mutex_lock(&data->lock); - data->min[attr->index] = val; - threshold_updated(data); - mutex_unlock(&data->lock); - - return count; -} - -static ssize_t max_store(struct device *dev, struct device_attribute *devattr, - const char *buf, size_t count) -{ - unsigned long val; - struct abx500_temp *data = dev_get_drvdata(dev); - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - int res = kstrtol(buf, 10, &val); - if (res < 0) - return res; - - val = clamp_val(val, 0, default_max_temp); - - mutex_lock(&data->lock); - data->max[attr->index] = val; - threshold_updated(data); - mutex_unlock(&data->lock); - - return count; -} - -static ssize_t max_hyst_store(struct device *dev, - struct device_attribute *devattr, - const char *buf, size_t count) -{ - unsigned long val; - struct abx500_temp *data = dev_get_drvdata(dev); - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - int res = kstrtoul(buf, 10, &val); - if (res < 0) - return res; - - val = clamp_val(val, 0, default_max_temp); - - mutex_lock(&data->lock); - data->max_hyst[attr->index] = val; - threshold_updated(data); - mutex_unlock(&data->lock); - - return count; -} - -/* show functions (ro nodes) */ -static ssize_t min_show(struct device *dev, struct device_attribute *devattr, - char *buf) -{ - struct abx500_temp *data = dev_get_drvdata(dev); - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - - return sprintf(buf, "%lu ", data->min[attr->index]); -} - -static ssize_t max_show(struct device *dev, struct device_attribute *devattr, - char *buf) -{ - struct abx500_temp *data = dev_get_drvdata(dev); - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - - return sprintf(buf, "%lu ", data->max[attr->index]); -} - -static ssize_t max_hyst_show(struct device *dev, - struct device_attribute *devattr, char *buf) -{ - struct abx500_temp *data = dev_get_drvdata(dev); - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - - return sprintf(buf, "%lu ", data->max_hyst[attr->index]); -} - -static ssize_t min_alarm_show(struct device *dev, - struct device_attribute *devattr, char *buf) -{ - struct abx500_temp *data = dev_get_drvdata(dev); - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - - return sprintf(buf, "%d ", data->min_alarm[attr->index]); -} - -static ssize_t max_alarm_show(struct device *dev, - struct device_attribute *devattr, char *buf) -{ - struct abx500_temp *data = dev_get_drvdata(dev); - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - - return sprintf(buf, "%d ", data->max_alarm[attr->index]); -} - -static umode_t abx500_attrs_visible(struct kobject *kobj, - struct attribute *attr, int n) -{ - struct device *dev = kobj_to_dev(kobj); - struct abx500_temp *data = dev_get_drvdata(dev); - - if (data->ops.is_visible) - return data->ops.is_visible(attr, n); - - return attr->mode; -} - -/* chip name, required by hwmon */ -static sensor_device_attr_ro(name, name, 0); - -/* gpadc - sensor1 */ -static sensor_device_attr_ro(temp1_label, label, 0); -static sensor_device_attr_ro(temp1_input, input, 0); -static sensor_device_attr_rw(temp1_min, min, 0); -static sensor_device_attr_rw(temp1_max, max, 0); -static sensor_device_attr_rw(temp1_max_hyst, max_hyst, 0); -static sensor_device_attr_ro(temp1_min_alarm, min_alarm, 0); -static sensor_device_attr_ro(temp1_max_alarm, max_alarm, 0); - -/* gpadc - sensor2 */ -static sensor_device_attr_ro(temp2_label, label, 1); -static sensor_device_attr_ro(temp2_input, input, 1); -static sensor_device_attr_rw(temp2_min, min, 1); -static sensor_device_attr_rw(temp2_max, max, 1); -static sensor_device_attr_rw(temp2_max_hyst, max_hyst, 1); -static sensor_device_attr_ro(temp2_min_alarm, min_alarm, 1); -static sensor_device_attr_ro(temp2_max_alarm, max_alarm, 1); - -/* gpadc - sensor3 */ -static sensor_device_attr_ro(temp3_label, label, 2); -static sensor_device_attr_ro(temp3_input, input, 2); -static sensor_device_attr_rw(temp3_min, min, 2); -static sensor_device_attr_rw(temp3_max, max, 2); -static sensor_device_attr_rw(temp3_max_hyst, max_hyst, 2); -static sensor_device_attr_ro(temp3_min_alarm, min_alarm, 2); -static sensor_device_attr_ro(temp3_max_alarm, max_alarm, 2); - -/* gpadc - sensor4 */ -static sensor_device_attr_ro(temp4_label, label, 3); -static sensor_device_attr_ro(temp4_input, input, 3); -static sensor_device_attr_rw(temp4_min, min, 3); -static sensor_device_attr_rw(temp4_max, max, 3); -static sensor_device_attr_rw(temp4_max_hyst, max_hyst, 3); -static sensor_device_attr_ro(temp4_min_alarm, min_alarm, 3); -static sensor_device_attr_ro(temp4_max_alarm, max_alarm, 3); - -static struct attribute *abx500_temp_attributes[] = { - &sensor_dev_attr_name.dev_attr.attr, - - &sensor_dev_attr_temp1_label.dev_attr.attr, - &sensor_dev_attr_temp1_input.dev_attr.attr, - &sensor_dev_attr_temp1_min.dev_attr.attr, - &sensor_dev_attr_temp1_max.dev_attr.attr, - &sensor_dev_attr_temp1_max_hyst.dev_attr.attr, - &sensor_dev_attr_temp1_min_alarm.dev_attr.attr, - &sensor_dev_attr_temp1_max_alarm.dev_attr.attr, - - &sensor_dev_attr_temp2_label.dev_attr.attr, - &sensor_dev_attr_temp2_input.dev_attr.attr, - &sensor_dev_attr_temp2_min.dev_attr.attr, - &sensor_dev_attr_temp2_max.dev_attr.attr, - &sensor_dev_attr_temp2_max_hyst.dev_attr.attr, - &sensor_dev_attr_temp2_min_alarm.dev_attr.attr, - &sensor_dev_attr_temp2_max_alarm.dev_attr.attr, - - &sensor_dev_attr_temp3_label.dev_attr.attr, - &sensor_dev_attr_temp3_input.dev_attr.attr, - &sensor_dev_attr_temp3_min.dev_attr.attr, - &sensor_dev_attr_temp3_max.dev_attr.attr, - &sensor_dev_attr_temp3_max_hyst.dev_attr.attr, - &sensor_dev_attr_temp3_min_alarm.dev_attr.attr, - &sensor_dev_attr_temp3_max_alarm.dev_attr.attr, - - &sensor_dev_attr_temp4_label.dev_attr.attr, - &sensor_dev_attr_temp4_input.dev_attr.attr, - &sensor_dev_attr_temp4_min.dev_attr.attr, - &sensor_dev_attr_temp4_max.dev_attr.attr, - &sensor_dev_attr_temp4_max_hyst.dev_attr.attr, - &sensor_dev_attr_temp4_min_alarm.dev_attr.attr, - &sensor_dev_attr_temp4_max_alarm.dev_attr.attr, - null -}; - -static const struct attribute_group abx500_temp_group = { - .attrs = abx500_temp_attributes, - .is_visible = abx500_attrs_visible, -}; - -static irqreturn_t abx500_temp_irq_handler(int irq, void *irq_data) -{ - struct platform_device *pdev = irq_data; - struct abx500_temp *data = platform_get_drvdata(pdev); - - data->ops.irq_handler(irq, data); - return irq_handled; -} - -static int setup_irqs(struct platform_device *pdev) -{ - int ret; - int irq = platform_get_irq_byname(pdev, "abx500_temp_warm"); - - if (irq < 0) { - dev_err(&pdev->dev, "get irq by name failed "); - return irq; - } - - ret = devm_request_threaded_irq(&pdev->dev, irq, null, - abx500_temp_irq_handler, 0, "abx500-temp", pdev); - if (ret < 0) - dev_err(&pdev->dev, "request threaded irq failed (%d) ", ret); - - return ret; -} - -static int abx500_temp_probe(struct platform_device *pdev) -{ - struct abx500_temp *data; - int err; - - data = devm_kzalloc(&pdev->dev, sizeof(*data), gfp_kernel); - if (!data) - return -enomem; - - data->pdev = pdev; - mutex_init(&data->lock); - - /* chip specific initialization */ - err = abx500_hwmon_init(data); - if (err < 0 || !data->ops.read_sensor || !data->ops.show_name || - !data->ops.show_label) - return err; - - init_deferrable_work(&data->work, gpadc_monitor); - - platform_set_drvdata(pdev, data); - - err = sysfs_create_group(&pdev->dev.kobj, &abx500_temp_group); - if (err < 0) { - dev_err(&pdev->dev, "create sysfs group failed (%d) ", err); - return err; - } - - data->hwmon_dev = hwmon_device_register(&pdev->dev); - if (is_err(data->hwmon_dev)) { - err = ptr_err(data->hwmon_dev); - dev_err(&pdev->dev, "class registration failed (%d) ", err); - goto exit_sysfs_group; - } - - if (data->ops.irq_handler) { - err = setup_irqs(pdev); - if (err < 0) - goto exit_hwmon_reg; - } - return 0; - -exit_hwmon_reg: - hwmon_device_unregister(data->hwmon_dev); -exit_sysfs_group: - sysfs_remove_group(&pdev->dev.kobj, &abx500_temp_group); - return err; -} - -static int abx500_temp_remove(struct platform_device *pdev) -{ - struct abx500_temp *data = platform_get_drvdata(pdev); - - cancel_delayed_work_sync(&data->work); - hwmon_device_unregister(data->hwmon_dev); - sysfs_remove_group(&pdev->dev.kobj, &abx500_temp_group); - - return 0; -} - -static int abx500_temp_suspend(struct platform_device *pdev, - pm_message_t state) -{ - struct abx500_temp *data = platform_get_drvdata(pdev); - - if (data->work_active) - cancel_delayed_work_sync(&data->work); - - return 0; -} - -static int abx500_temp_resume(struct platform_device *pdev) -{ - struct abx500_temp *data = platform_get_drvdata(pdev); - - if (data->work_active) - schedule_monitor(data); - - return 0; -} - -#ifdef config_of -static const struct of_device_id abx500_temp_match[] = { - { .compatible = "stericsson,abx500-temp" }, - {}, -}; -module_device_table(of, abx500_temp_match); -#endif - -static struct platform_driver abx500_temp_driver = { - .driver = { - .name = "abx500-temp", - .of_match_table = of_match_ptr(abx500_temp_match), - }, - .suspend = abx500_temp_suspend, - .resume = abx500_temp_resume, - .probe = abx500_temp_probe, - .remove = abx500_temp_remove, -}; - -module_platform_driver(abx500_temp_driver); - -module_author("martin persson <martin.persson@stericsson.com>"); -module_description("abx500 temperature driver"); -module_license("gpl"); diff --git a/drivers/hwmon/abx500.h b/drivers/hwmon/abx500.h --- a/drivers/hwmon/abx500.h +++ /dev/null -/* spdx-license-identifier: gpl-2.0-only */ -/* - * copyright (c) st-ericsson 2010 - 2013 - * author: martin persson <martin.persson@stericsson.com> - * hongbo zhang <hongbo.zhang@linaro.com> - */ - -#ifndef _abx500_h -#define _abx500_h - -#define num_sensors 5 - -struct abx500_temp; - -/* - * struct abx500_temp_ops - abx500 chip specific ops - * @read_sensor: reads gpadc output - * @irq_handler: irq handler - * @show_name: hwmon device name - * @show_label: hwmon attribute label - * @is_visible: is attribute visible - */ -struct abx500_temp_ops { - int (*read_sensor)(struct abx500_temp *, u8, int *); - int (*irq_handler)(int, struct abx500_temp *); - ssize_t (*show_name)(struct device *, - struct device_attribute *, char *); - ssize_t (*show_label) (struct device *, - struct device_attribute *, char *); - int (*is_visible)(struct attribute *, int); -}; - -/* - * struct abx500_temp - representation of temp mon device - * @pdev: platform device - * @hwmon_dev: hwmon device - * @ops: abx500 chip specific ops - * @gpadc_addr: gpadc channel address - * @min: sensor temperature min value - * @max: sensor temperature max value - * @max_hyst: sensor temperature hysteresis value for max limit - * @min_alarm: sensor temperature min alarm - * @max_alarm: sensor temperature max alarm - * @work: delayed work scheduled to monitor temperature periodically - * @work_active: true if work is active - * @lock: mutex - * @monitored_sensors: number of monitored sensors - * @plat_data: private usage, usually points to platform specific data - */ -struct abx500_temp { - struct platform_device *pdev; - struct device *hwmon_dev; - struct abx500_temp_ops ops; - u8 gpadc_addr[num_sensors]; - unsigned long min[num_sensors]; - unsigned long max[num_sensors]; - unsigned long max_hyst[num_sensors]; - bool min_alarm[num_sensors]; - bool max_alarm[num_sensors]; - struct delayed_work work; - bool work_active; - struct mutex lock; - int monitored_sensors; - void *plat_data; -}; - -int abx500_hwmon_init(struct abx500_temp *data); - -#endif /* _abx500_h */
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Hardware monitoring (hwmon)
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d349626b42f5dbd08ffcb3f2c383b1f6f433b3c1
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guenter roeck
|
documentation
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hwmon
| |
gpio: gpio-xilinx: simplify with dev_err_probe()
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common pattern of handling deferred probe can be simplified with dev_err_probe(). less code and also it prints the error value.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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update on xilinx gpio driver
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
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['gpio-xilinx']
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['c']
| 1
| 2
| 5
|
--- diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c --- a/drivers/gpio/gpio-xilinx.c +++ b/drivers/gpio/gpio-xilinx.c - if (is_err(chip->clk)) { - if (ptr_err(chip->clk) != -eprobe_defer) - dev_dbg(&pdev->dev, "input clock not found "); - return ptr_err(chip->clk); - } + if (is_err(chip->clk)) + return dev_err_probe(&pdev->dev, ptr_err(chip->clk), "input clock not found. ");
|
General Purpose I/O (gpio)
|
45c5277f347841daefb1a7b48da9904ef9b46ca9
|
srinivas neeli linus walleij linus walleij linaro org
|
drivers
|
gpio
| |
gpio: gpio-xilinx: reduce spinlock array to array
|
changed spinlock array to single. it is preparation for irq support which is shared between two channels that's why spinlock should be only one.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
update on xilinx gpio driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['gpio-xilinx']
|
['c']
| 1
| 12
| 13
|
--- diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c --- a/drivers/gpio/gpio-xilinx.c +++ b/drivers/gpio/gpio-xilinx.c - spinlock_t gpio_lock[2]; + spinlock_t gpio_lock; /* for serializing operations */ - spin_lock_irqsave(&chip->gpio_lock[index], flags); + spin_lock_irqsave(&chip->gpio_lock, flags); - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); + spin_unlock_irqrestore(&chip->gpio_lock, flags); - spin_lock_irqsave(&chip->gpio_lock[index], flags); + spin_lock_irqsave(&chip->gpio_lock, flags); - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); + spin_unlock_irqrestore(&chip->gpio_lock, flags); - spin_lock_irqsave(&chip->gpio_lock[index], flags); + spin_lock_irqsave(&chip->gpio_lock, flags); - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); + spin_unlock_irqrestore(&chip->gpio_lock, flags); - spin_lock_irqsave(&chip->gpio_lock[index], flags); + spin_lock_irqsave(&chip->gpio_lock, flags); - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); + spin_unlock_irqrestore(&chip->gpio_lock, flags); - spin_lock_irqsave(&chip->gpio_lock[index], flags); + spin_lock_irqsave(&chip->gpio_lock, flags); - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); + spin_unlock_irqrestore(&chip->gpio_lock, flags); - spin_lock_init(&chip->gpio_lock[0]); + spin_lock_init(&chip->gpio_lock); - spin_lock_init(&chip->gpio_lock[1]);
|
General Purpose I/O (gpio)
|
37ef334680800263b32bb96a5156a4b47f0244a2
|
srinivas neeli linus walleij linus walleij linaro org
|
drivers
|
gpio
| |
gpio: gpio-xilinx: add interrupt support
|
adds interrupt support to the xilinx gpio driver so that rising and falling edge line events can be supported. since interrupt support is an optional feature in the xilinx ip, the driver continues to support devices which have no interrupt provided. depends on of_gpio framework for of_xlate function to translate gpiospec to the gpio number and flags.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
update on xilinx gpio driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['gpio-xilinx']
|
['kconfig', 'c']
| 2
| 244
| 4
|
--- diff --git a/drivers/gpio/kconfig b/drivers/gpio/kconfig --- a/drivers/gpio/kconfig +++ b/drivers/gpio/kconfig + select gpiolib_irqchip + depends on of_gpio diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c --- a/drivers/gpio/gpio-xilinx.c +++ b/drivers/gpio/gpio-xilinx.c +#include <linux/interrupt.h> +#include <linux/irq.h> +#define xgpio_gier_offset 0x11c /* global interrupt enable */ +#define xgpio_gier_ie bit(31) +#define xgpio_ipisr_offset 0x120 /* ip interrupt status */ +#define xgpio_ipier_offset 0x128 /* ip interrupt enable */ + - * @gpio_state: gpio state shadow register + * @gpio_state: gpio write state shadow register + * @gpio_last_irq_read: gpio read state register from last interrupt + * @irq: irq used by gpio device + * @irqchip: irq chip + * @irq_enable: gpio irq enable/disable bitfield + * @irq_rising_edge: gpio irq rising edge enable/disable bitfield + * @irq_falling_edge: gpio irq falling edge enable/disable bitfield + u32 gpio_last_irq_read[2]; + int irq; + struct irq_chip irqchip; + u32 irq_enable[2]; + u32 irq_rising_edge[2]; + u32 irq_falling_edge[2]; +/** + * xgpio_irq_ack - acknowledge a child gpio interrupt. + * @irq_data: per irq and chip data passed down to chip functions + * this currently does nothing, but irq_ack is unconditionally called by + * handle_edge_irq and therefore must be defined. + */ +static void xgpio_irq_ack(struct irq_data *irq_data) +{ +} + +/** + * xgpio_irq_mask - write the specified signal of the gpio device. + * @irq_data: per irq and chip data passed down to chip functions + */ +static void xgpio_irq_mask(struct irq_data *irq_data) +{ + unsigned long flags; + struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); + int irq_offset = irqd_to_hwirq(irq_data); + int index = xgpio_index(chip, irq_offset); + int offset = xgpio_offset(chip, irq_offset); + + spin_lock_irqsave(&chip->gpio_lock, flags); + + chip->irq_enable[index] &= ~bit(offset); + + if (!chip->irq_enable[index]) { + /* disable per channel interrupt */ + u32 temp = xgpio_readreg(chip->regs + xgpio_ipier_offset); + + temp &= ~bit(index); + xgpio_writereg(chip->regs + xgpio_ipier_offset, temp); + } + spin_unlock_irqrestore(&chip->gpio_lock, flags); +} + +/** + * xgpio_irq_unmask - write the specified signal of the gpio device. + * @irq_data: per irq and chip data passed down to chip functions + */ +static void xgpio_irq_unmask(struct irq_data *irq_data) +{ + unsigned long flags; + struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); + int irq_offset = irqd_to_hwirq(irq_data); + int index = xgpio_index(chip, irq_offset); + int offset = xgpio_offset(chip, irq_offset); + u32 old_enable = chip->irq_enable[index]; + + spin_lock_irqsave(&chip->gpio_lock, flags); + + chip->irq_enable[index] |= bit(offset); + + if (!old_enable) { + /* clear any existing per-channel interrupts */ + u32 val = xgpio_readreg(chip->regs + xgpio_ipisr_offset) & + bit(index); + + if (val) + xgpio_writereg(chip->regs + xgpio_ipisr_offset, val); + + /* update gpio irq read data before enabling interrupt*/ + val = xgpio_readreg(chip->regs + xgpio_data_offset + + index * xgpio_channel_offset); + chip->gpio_last_irq_read[index] = val; + + /* enable per channel interrupt */ + val = xgpio_readreg(chip->regs + xgpio_ipier_offset); + val |= bit(index); + xgpio_writereg(chip->regs + xgpio_ipier_offset, val); + } + + spin_unlock_irqrestore(&chip->gpio_lock, flags); +} + +/** + * xgpio_set_irq_type - write the specified signal of the gpio device. + * @irq_data: per irq and chip data passed down to chip functions + * @type: interrupt type that is to be set for the gpio pin + * + * return: + * 0 if interrupt type is supported otherwise -einval + */ +static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type) +{ + struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); + int irq_offset = irqd_to_hwirq(irq_data); + int index = xgpio_index(chip, irq_offset); + int offset = xgpio_offset(chip, irq_offset); + + /* + * the xilinx gpio hardware provides a single interrupt status + * indication for any state change in a given gpio channel (bank). + * therefore, only rising edge or falling edge triggers are + * supported. + */ + switch (type & irq_type_sense_mask) { + case irq_type_edge_both: + chip->irq_rising_edge[index] |= bit(offset); + chip->irq_falling_edge[index] |= bit(offset); + break; + case irq_type_edge_rising: + chip->irq_rising_edge[index] |= bit(offset); + chip->irq_falling_edge[index] &= ~bit(offset); + break; + case irq_type_edge_falling: + chip->irq_rising_edge[index] &= ~bit(offset); + chip->irq_falling_edge[index] |= bit(offset); + break; + default: + return -einval; + } + + irq_set_handler_locked(irq_data, handle_edge_irq); + return 0; +} + +/** + * xgpio_irqhandler - gpio interrupt service routine + * @desc: pointer to interrupt description + */ +static void xgpio_irqhandler(struct irq_desc *desc) +{ + struct xgpio_instance *chip = irq_desc_get_handler_data(desc); + struct irq_chip *irqchip = irq_desc_get_chip(desc); + u32 num_channels = chip->gpio_width[1] ? 2 : 1; + u32 offset = 0, index; + u32 status = xgpio_readreg(chip->regs + xgpio_ipisr_offset); + + xgpio_writereg(chip->regs + xgpio_ipisr_offset, status); + + chained_irq_enter(irqchip, desc); + for (index = 0; index < num_channels; index++) { + if ((status & bit(index))) { + unsigned long rising_events, falling_events, all_events; + unsigned long flags; + u32 data, bit; + unsigned int irq; + + spin_lock_irqsave(&chip->gpio_lock, flags); + data = xgpio_readreg(chip->regs + xgpio_data_offset + + index * xgpio_channel_offset); + rising_events = data & + ~chip->gpio_last_irq_read[index] & + chip->irq_enable[index] & + chip->irq_rising_edge[index]; + falling_events = ~data & + chip->gpio_last_irq_read[index] & + chip->irq_enable[index] & + chip->irq_falling_edge[index]; + dev_dbg(chip->gc.parent, + "irq chan %u rising 0x%lx falling 0x%lx ", + index, rising_events, falling_events); + all_events = rising_events | falling_events; + chip->gpio_last_irq_read[index] = data; + spin_unlock_irqrestore(&chip->gpio_lock, flags); + + for_each_set_bit(bit, &all_events, 32) { + irq = irq_find_mapping(chip->gc.irq.domain, + offset + bit); + generic_handle_irq(irq); + } + } + offset += chip->gpio_width[index]; + } + + chained_irq_exit(irqchip, desc); +} + - u32 is_dual; + u32 is_dual = 0; + u32 cells = 2; + struct gpio_irq_chip *girq; + u32 temp; + /* update cells with gpio-cells value */ + if (of_property_read_u32(np, "#gpio-cells", &cells)) + dev_dbg(&pdev->dev, "missing gpio-cells property "); + + if (cells != 2) { + dev_err(&pdev->dev, "#gpio-cells mismatch "); + return -einval; + } + + chip->gc.of_gpio_n_cells = cells; + chip->irq = platform_get_irq_optional(pdev, 0); + if (chip->irq <= 0) + goto skip_irq; + + chip->irqchip.name = "gpio-xilinx"; + chip->irqchip.irq_ack = xgpio_irq_ack; + chip->irqchip.irq_mask = xgpio_irq_mask; + chip->irqchip.irq_unmask = xgpio_irq_unmask; + chip->irqchip.irq_set_type = xgpio_set_irq_type; + + /* disable per-channel interrupts */ + xgpio_writereg(chip->regs + xgpio_ipier_offset, 0); + /* clear any existing per-channel interrupts */ + temp = xgpio_readreg(chip->regs + xgpio_ipisr_offset); + xgpio_writereg(chip->regs + xgpio_ipisr_offset, temp); + /* enable global interrupts */ + xgpio_writereg(chip->regs + xgpio_gier_offset, xgpio_gier_ie); + + girq = &chip->gc.irq; + girq->chip = &chip->irqchip; + girq->parent_handler = xgpio_irqhandler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(&pdev->dev, 1, + sizeof(*girq->parents), + gfp_kernel); + if (!girq->parents) { + status = -enomem; + goto err_unprepare_clk; + } + girq->parents[0] = chip->irq; + girq->default_type = irq_type_none; + girq->handler = handle_bad_irq; + +skip_irq: - clk_disable_unprepare(chip->clk); - return status; + goto err_unprepare_clk; + +err_unprepare_clk: + clk_disable_unprepare(chip->clk); + return status;
|
General Purpose I/O (gpio)
|
a32c7caea292c4d1e417eae6e5a348d187546acf
|
srinivas neeli linus walleij linus walleij linaro org
|
drivers
|
gpio
| |
gpio: gpio-xilinx: add support for suspend and resume
|
add support for suspend and resume, pm runtime suspend and resume. added free and request calls.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
update on xilinx gpio driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['gpio-xilinx']
|
['c']
| 1
| 89
| 3
|
--- diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c --- a/drivers/gpio/gpio-xilinx.c +++ b/drivers/gpio/gpio-xilinx.c +#include <linux/pm_runtime.h> +static int xgpio_request(struct gpio_chip *chip, unsigned int offset) +{ + int ret; + + ret = pm_runtime_get_sync(chip->parent); + /* + * if the device is already active pm_runtime_get() will return 1 on + * success, but gpio_request still needs to return 0. + */ + return ret < 0 ? ret : 0; +} + +static void xgpio_free(struct gpio_chip *chip, unsigned int offset) +{ + pm_runtime_put(chip->parent); +} + +static int __maybe_unused xgpio_suspend(struct device *dev) +{ + struct xgpio_instance *gpio = dev_get_drvdata(dev); + struct irq_data *data = irq_get_irq_data(gpio->irq); + + if (!data) { + dev_err(dev, "irq_get_irq_data() failed "); + return -einval; + } + + if (!irqd_is_wakeup_set(data)) + return pm_runtime_force_suspend(dev); + + return 0; +} + + pm_runtime_get_sync(&pdev->dev); + pm_runtime_put_noidle(&pdev->dev); + pm_runtime_disable(&pdev->dev); +static int __maybe_unused xgpio_resume(struct device *dev) +{ + struct xgpio_instance *gpio = dev_get_drvdata(dev); + struct irq_data *data = irq_get_irq_data(gpio->irq); + + if (!data) { + dev_err(dev, "irq_get_irq_data() failed "); + return -einval; + } + + if (!irqd_is_wakeup_set(data)) + return pm_runtime_force_resume(dev); + + return 0; +} + +static int __maybe_unused xgpio_runtime_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct xgpio_instance *gpio = platform_get_drvdata(pdev); + + clk_disable(gpio->clk); + + return 0; +} + +static int __maybe_unused xgpio_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct xgpio_instance *gpio = platform_get_drvdata(pdev); + + return clk_enable(gpio->clk); +} + +static const struct dev_pm_ops xgpio_dev_pm_ops = { + set_system_sleep_pm_ops(xgpio_suspend, xgpio_resume) + set_runtime_pm_ops(xgpio_runtime_suspend, + xgpio_runtime_resume, null) +}; + + chip->gc.request = xgpio_request; + chip->gc.free = xgpio_free; + pm_runtime_get_noresume(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); - goto err_unprepare_clk; + goto err_pm_put; - goto err_unprepare_clk; + goto err_pm_put; + pm_runtime_put(&pdev->dev); -err_unprepare_clk: +err_pm_put: + pm_runtime_disable(&pdev->dev); + pm_runtime_put_noidle(&pdev->dev); + .pm = &xgpio_dev_pm_ops,
|
General Purpose I/O (gpio)
|
26b04774621ed333e8bc56479feb6e31625df58c
|
srinivas neeli linus walleij linus walleij linaro org
|
drivers
|
gpio
| |
gpio: gpio-xilinx: add check if width exceeds 32
|
add check to see if gpio-width property does not exceed 32. if it exceeds then return -einval.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
update on xilinx gpio driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['gpio-xilinx']
|
['c']
| 1
| 5
| 0
|
--- diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c --- a/drivers/gpio/gpio-xilinx.c +++ b/drivers/gpio/gpio-xilinx.c + if (chip->gpio_width[0] > 32) + return -einval; + + if (chip->gpio_width[1] > 32) + return -einval;
|
General Purpose I/O (gpio)
|
6e551bfa9872cd335d0929411cfdefe99ce65a1d
|
srinivas neeli william breathitt gray vilhelm gray gmail com linus walleij linus walleij linaro org
|
drivers
|
gpio
| |
gpio: intel-mid: remove driver for deprecated platform
|
intel moorestown and medfield are quite old intel atom based 32-bit platforms, which were in limited use in some android phones, tablets and consumer electronics more than eight years ago.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove driver for deprecated platform
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel-mid']
|
['c', 'kconfig', 'todo', 'maintainers', 'makefile']
| 5
| 1
| 424
|
--- diff --git a/maintainers b/maintainers --- a/maintainers +++ b/maintainers -f: drivers/gpio/gpio-intel-mid.c diff --git a/drivers/gpio/kconfig b/drivers/gpio/kconfig --- a/drivers/gpio/kconfig +++ b/drivers/gpio/kconfig -config gpio_intel_mid - bool "intel mid gpio support" - depends on x86_intel_mid - select gpiolib_irqchip - help - say y here to support intel mid gpio. - diff --git a/drivers/gpio/makefile b/drivers/gpio/makefile --- a/drivers/gpio/makefile +++ b/drivers/gpio/makefile -obj-$(config_gpio_intel_mid) += gpio-intel-mid.o diff --git a/drivers/gpio/todo b/drivers/gpio/todo --- a/drivers/gpio/todo +++ b/drivers/gpio/todo -gpio-pch. in similar way gpio-intel-mid into gpio-pxa. +gpio-pch. diff --git a/drivers/gpio/gpio-intel-mid.c b/drivers/gpio/gpio-intel-mid.c --- a/drivers/gpio/gpio-intel-mid.c +++ /dev/null -// spdx-license-identifier: gpl-2.0 -/* - * intel mid gpio driver - * - * copyright (c) 2008-2014,2016 intel corporation. - */ - -/* supports: - * moorestown platform langwell chip. - * medfield platform penwell chip. - * clovertrail platform cloverview chip. - */ - -#include <linux/delay.h> -#include <linux/gpio/driver.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include <linux/kernel.h> -#include <linux/pci.h> -#include <linux/platform_device.h> -#include <linux/pm_runtime.h> -#include <linux/slab.h> -#include <linux/stddef.h> - -#define intel_mid_irq_type_edge (1 << 0) -#define intel_mid_irq_type_level (1 << 1) - -/* - * langwell chip has 64 pins and thus there are 2 32bit registers to control - * each feature, while penwell chip has 96 pins for each block, and need 3 32bit - * registers to control them, so we only define the order here instead of a - * structure, to get a bit offset for a pin (use gpdr as an example): - * - * nreg = ngpio / 32; - * reg = offset / 32; - * bit = offset % 32; - * reg_addr = reg_base + gpdr * nreg * 4 + reg * 4; - * - * so the bit of reg_addr is to control pin offset's gpdr feature -*/ - -enum gpio_reg { - gplr = 0, /* pin level read-only */ - gpdr, /* pin direction */ - gpsr, /* pin set */ - gpcr, /* pin clear */ - grer, /* rising edge detect */ - gfer, /* falling edge detect */ - gedr, /* edge detect result */ - gafr, /* alt function */ -}; - -/* intel_mid gpio driver data */ -struct intel_mid_gpio_ddata { - u16 ngpio; /* number of gpio pins */ - u32 chip_irq_type; /* chip interrupt type */ -}; - -struct intel_mid_gpio { - struct gpio_chip chip; - void __iomem *reg_base; - spinlock_t lock; - struct pci_dev *pdev; -}; - -static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset, - enum gpio_reg reg_type) -{ - struct intel_mid_gpio *priv = gpiochip_get_data(chip); - unsigned nreg = chip->ngpio / 32; - u8 reg = offset / 32; - - return priv->reg_base + reg_type * nreg * 4 + reg * 4; -} - -static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset, - enum gpio_reg reg_type) -{ - struct intel_mid_gpio *priv = gpiochip_get_data(chip); - unsigned nreg = chip->ngpio / 32; - u8 reg = offset / 16; - - return priv->reg_base + reg_type * nreg * 4 + reg * 4; -} - -static int intel_gpio_request(struct gpio_chip *chip, unsigned offset) -{ - void __iomem *gafr = gpio_reg_2bit(chip, offset, gafr); - u32 value = readl(gafr); - int shift = (offset % 16) << 1, af = (value >> shift) & 3; - - if (af) { - value &= ~(3 << shift); - writel(value, gafr); - } - return 0; -} - -static int intel_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - void __iomem *gplr = gpio_reg(chip, offset, gplr); - - return !!(readl(gplr) & bit(offset % 32)); -} - -static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value) -{ - void __iomem *gpsr, *gpcr; - - if (value) { - gpsr = gpio_reg(chip, offset, gpsr); - writel(bit(offset % 32), gpsr); - } else { - gpcr = gpio_reg(chip, offset, gpcr); - writel(bit(offset % 32), gpcr); - } -} - -static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -{ - struct intel_mid_gpio *priv = gpiochip_get_data(chip); - void __iomem *gpdr = gpio_reg(chip, offset, gpdr); - u32 value; - unsigned long flags; - - if (priv->pdev) - pm_runtime_get(&priv->pdev->dev); - - spin_lock_irqsave(&priv->lock, flags); - value = readl(gpdr); - value &= ~bit(offset % 32); - writel(value, gpdr); - spin_unlock_irqrestore(&priv->lock, flags); - - if (priv->pdev) - pm_runtime_put(&priv->pdev->dev); - - return 0; -} - -static int intel_gpio_direction_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - struct intel_mid_gpio *priv = gpiochip_get_data(chip); - void __iomem *gpdr = gpio_reg(chip, offset, gpdr); - unsigned long flags; - - intel_gpio_set(chip, offset, value); - - if (priv->pdev) - pm_runtime_get(&priv->pdev->dev); - - spin_lock_irqsave(&priv->lock, flags); - value = readl(gpdr); - value |= bit(offset % 32); - writel(value, gpdr); - spin_unlock_irqrestore(&priv->lock, flags); - - if (priv->pdev) - pm_runtime_put(&priv->pdev->dev); - - return 0; -} - -static int intel_mid_irq_type(struct irq_data *d, unsigned type) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct intel_mid_gpio *priv = gpiochip_get_data(gc); - u32 gpio = irqd_to_hwirq(d); - unsigned long flags; - u32 value; - void __iomem *grer = gpio_reg(&priv->chip, gpio, grer); - void __iomem *gfer = gpio_reg(&priv->chip, gpio, gfer); - - if (gpio >= priv->chip.ngpio) - return -einval; - - if (priv->pdev) - pm_runtime_get(&priv->pdev->dev); - - spin_lock_irqsave(&priv->lock, flags); - if (type & irq_type_edge_rising) - value = readl(grer) | bit(gpio % 32); - else - value = readl(grer) & (~bit(gpio % 32)); - writel(value, grer); - - if (type & irq_type_edge_falling) - value = readl(gfer) | bit(gpio % 32); - else - value = readl(gfer) & (~bit(gpio % 32)); - writel(value, gfer); - spin_unlock_irqrestore(&priv->lock, flags); - - if (priv->pdev) - pm_runtime_put(&priv->pdev->dev); - - return 0; -} - -static void intel_mid_irq_unmask(struct irq_data *d) -{ -} - -static void intel_mid_irq_mask(struct irq_data *d) -{ -} - -static struct irq_chip intel_mid_irqchip = { - .name = "intel_mid-gpio", - .irq_mask = intel_mid_irq_mask, - .irq_unmask = intel_mid_irq_unmask, - .irq_set_type = intel_mid_irq_type, -}; - -static const struct intel_mid_gpio_ddata gpio_lincroft = { - .ngpio = 64, -}; - -static const struct intel_mid_gpio_ddata gpio_penwell_aon = { - .ngpio = 96, - .chip_irq_type = intel_mid_irq_type_edge, -}; - -static const struct intel_mid_gpio_ddata gpio_penwell_core = { - .ngpio = 96, - .chip_irq_type = intel_mid_irq_type_edge, -}; - -static const struct intel_mid_gpio_ddata gpio_cloverview_aon = { - .ngpio = 96, - .chip_irq_type = intel_mid_irq_type_edge | intel_mid_irq_type_level, -}; - -static const struct intel_mid_gpio_ddata gpio_cloverview_core = { - .ngpio = 96, - .chip_irq_type = intel_mid_irq_type_edge, -}; - -static const struct pci_device_id intel_gpio_ids[] = { - { - /* lincroft */ - pci_device(pci_vendor_id_intel, 0x080f), - .driver_data = (kernel_ulong_t)&gpio_lincroft, - }, - { - /* penwell aon */ - pci_device(pci_vendor_id_intel, 0x081f), - .driver_data = (kernel_ulong_t)&gpio_penwell_aon, - }, - { - /* penwell core */ - pci_device(pci_vendor_id_intel, 0x081a), - .driver_data = (kernel_ulong_t)&gpio_penwell_core, - }, - { - /* cloverview aon */ - pci_device(pci_vendor_id_intel, 0x08eb), - .driver_data = (kernel_ulong_t)&gpio_cloverview_aon, - }, - { - /* cloverview core */ - pci_device(pci_vendor_id_intel, 0x08f7), - .driver_data = (kernel_ulong_t)&gpio_cloverview_core, - }, - { } -}; - -static void intel_mid_irq_handler(struct irq_desc *desc) -{ - struct gpio_chip *gc = irq_desc_get_handler_data(desc); - struct intel_mid_gpio *priv = gpiochip_get_data(gc); - struct irq_data *data = irq_desc_get_irq_data(desc); - struct irq_chip *chip = irq_data_get_irq_chip(data); - u32 base, gpio, mask; - unsigned long pending; - void __iomem *gedr; - - /* check gpio controller to check which pin triggered the interrupt */ - for (base = 0; base < priv->chip.ngpio; base += 32) { - gedr = gpio_reg(&priv->chip, base, gedr); - while ((pending = readl(gedr))) { - gpio = __ffs(pending); - mask = bit(gpio); - /* clear before handling so we can't lose an edge */ - writel(mask, gedr); - generic_handle_irq(irq_find_mapping(gc->irq.domain, - base + gpio)); - } - } - - chip->irq_eoi(data); -} - -static int intel_mid_irq_init_hw(struct gpio_chip *chip) -{ - struct intel_mid_gpio *priv = gpiochip_get_data(chip); - void __iomem *reg; - unsigned base; - - for (base = 0; base < priv->chip.ngpio; base += 32) { - /* clear the rising-edge detect register */ - reg = gpio_reg(&priv->chip, base, grer); - writel(0, reg); - /* clear the falling-edge detect register */ - reg = gpio_reg(&priv->chip, base, gfer); - writel(0, reg); - /* clear the edge detect status register */ - reg = gpio_reg(&priv->chip, base, gedr); - writel(~0, reg); - } - - return 0; -} - -static int __maybe_unused intel_gpio_runtime_idle(struct device *dev) -{ - int err = pm_schedule_suspend(dev, 500); - return err ?: -ebusy; -} - -static const struct dev_pm_ops intel_gpio_pm_ops = { - set_runtime_pm_ops(null, null, intel_gpio_runtime_idle) -}; - -static int intel_gpio_probe(struct pci_dev *pdev, - const struct pci_device_id *id) -{ - void __iomem *base; - struct intel_mid_gpio *priv; - u32 gpio_base; - u32 irq_base; - int retval; - struct gpio_irq_chip *girq; - struct intel_mid_gpio_ddata *ddata = - (struct intel_mid_gpio_ddata *)id->driver_data; - - retval = pcim_enable_device(pdev); - if (retval) - return retval; - - retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev)); - if (retval) { - dev_err(&pdev->dev, "i/o memory mapping error "); - return retval; - } - - base = pcim_iomap_table(pdev)[1]; - - irq_base = readl(base); - gpio_base = readl(sizeof(u32) + base); - - /* release the io mapping, since we already get the info from bar1 */ - pcim_iounmap_regions(pdev, 1 << 1); - - priv = devm_kzalloc(&pdev->dev, sizeof(*priv), gfp_kernel); - if (!priv) - return -enomem; - - priv->reg_base = pcim_iomap_table(pdev)[0]; - priv->chip.label = dev_name(&pdev->dev); - priv->chip.parent = &pdev->dev; - priv->chip.request = intel_gpio_request; - priv->chip.direction_input = intel_gpio_direction_input; - priv->chip.direction_output = intel_gpio_direction_output; - priv->chip.get = intel_gpio_get; - priv->chip.set = intel_gpio_set; - priv->chip.base = gpio_base; - priv->chip.ngpio = ddata->ngpio; - priv->chip.can_sleep = false; - priv->pdev = pdev; - - spin_lock_init(&priv->lock); - - girq = &priv->chip.irq; - girq->chip = &intel_mid_irqchip; - girq->init_hw = intel_mid_irq_init_hw; - girq->parent_handler = intel_mid_irq_handler; - girq->num_parents = 1; - girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents, - sizeof(*girq->parents), - gfp_kernel); - if (!girq->parents) - return -enomem; - girq->parents[0] = pdev->irq; - girq->first = irq_base; - girq->default_type = irq_type_none; - girq->handler = handle_simple_irq; - - pci_set_drvdata(pdev, priv); - - retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv); - if (retval) { - dev_err(&pdev->dev, "gpiochip_add error %d ", retval); - return retval; - } - - pm_runtime_put_noidle(&pdev->dev); - pm_runtime_allow(&pdev->dev); - - return 0; -} - -static struct pci_driver intel_gpio_driver = { - .name = "intel_mid_gpio", - .id_table = intel_gpio_ids, - .probe = intel_gpio_probe, - .driver = { - .pm = &intel_gpio_pm_ops, - }, -}; - -builtin_pci_driver(intel_gpio_driver);
|
General Purpose I/O (gpio)
|
5f7582aa2d3c2ea0a9c9be17bcb53d29c0417ae5
|
andy shevchenko
|
drivers
|
gpio
| |
gpio: mvebu: add pwm support for armada 8k/7k
|
use the marvell,pwm-offset dt property to store the location of pwm signal duration registers.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add pwm support for armada 8k/7k
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mvebu']
|
['c']
| 1
| 68
| 33
|
--- diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c --- a/drivers/gpio/gpio-mvebu.c +++ b/drivers/gpio/gpio-mvebu.c +#define pwm_blink_counter_b_off 0x8 +/* armada 8k variant gpios register offsets */ +#define ap80x_gpio0_off_a8k 0x1040 +#define cp11x_gpio0_off_a8k 0x100 +#define cp11x_gpio1_off_a8k 0x140 + u32 offset; - return pwm_blink_on_duration_off; + return mvpwm->offset + pwm_blink_on_duration_off; - return pwm_blink_off_duration_off; + return mvpwm->offset + pwm_blink_off_duration_off; + u32 offset; - if (!of_device_is_compatible(mvchip->chip.of_node, - "marvell,armada-370-gpio")) - return 0; - - /* - * there are only two sets of pwm configuration registers for - * all the gpio lines on those socs which this driver reserves - * for the first two gpio chips. so if the resource is missing - * we can't treat it as an error. - */ - if (!platform_get_resource_byname(pdev, ioresource_mem, "pwm")) + if (of_device_is_compatible(mvchip->chip.of_node, + "marvell,armada-370-gpio")) { + /* + * there are only two sets of pwm configuration registers for + * all the gpio lines on those socs which this driver reserves + * for the first two gpio chips. so if the resource is missing + * we can't treat it as an error. + */ + if (!platform_get_resource_byname(pdev, ioresource_mem, "pwm")) + return 0; + offset = 0; + } else if (mvchip->soc_variant == mvebu_gpio_soc_variant_a8k) { + int ret = of_property_read_u32(dev->of_node, + "marvell,pwm-offset", &offset); + if (ret < 0) + return 0; + } else { + } - /* - * use set a for lines of gpio chip with id 0, b for gpio chip - * with id 1. don't allow further gpio chips to be used for pwm. - */ - if (id == 0) - set = 0; - else if (id == 1) - set = u32_max; - else - return -einval; - regmap_write(mvchip->regs, - gpio_blink_cnt_select_off + mvchip->offset, set); - + mvpwm->offset = offset; + + if (mvchip->soc_variant == mvebu_gpio_soc_variant_a8k) { + mvpwm->regs = mvchip->regs; + + switch (mvchip->offset) { + case ap80x_gpio0_off_a8k: + case cp11x_gpio0_off_a8k: + /* blink counter a */ + set = 0; + break; + case cp11x_gpio1_off_a8k: + /* blink counter b */ + set = u32_max; + mvpwm->offset += pwm_blink_counter_b_off; + break; + default: + return -einval; + } + } else { + base = devm_platform_ioremap_resource_byname(pdev, "pwm"); + if (is_err(base)) + return ptr_err(base); - base = devm_platform_ioremap_resource_byname(pdev, "pwm"); - if (is_err(base)) - return ptr_err(base); + mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base, + &mvebu_gpio_regmap_config); + if (is_err(mvpwm->regs)) + return ptr_err(mvpwm->regs); - mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base, - &mvebu_gpio_regmap_config); - if (is_err(mvpwm->regs)) - return ptr_err(mvpwm->regs); + /* + * use set a for lines of gpio chip with id 0, b for gpio chip + * with id 1. don't allow further gpio chips to be used for pwm. + */ + if (id == 0) + set = 0; + else if (id == 1) + set = u32_max; + else + return -einval; + } + + regmap_write(mvchip->regs, + gpio_blink_cnt_select_off + mvchip->offset, set);
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General Purpose I/O (gpio)
|
85b7d8abfec70ae820ddfea493f93b0af7e50b51
|
baruch siach
|
drivers
|
gpio
| |
gpio: pca953x: add support for pca9506
|
according to the reference manual "the pca9505 is identical to the pca9506 except that it includes 100 k internal pull-up resistors on all the i/os." so the pca9506 device can be considered identical to the pca9505 for the gpio driver.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for pca9506
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['pca953x']
|
['c']
| 1
| 2
| 0
|
--- diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c + { "pca9506", 40 | pca953x_type | pca_int, }, + { .compatible = "nxp,pca9506", .data = of_953x(40, pca_int), },
|
General Purpose I/O (gpio)
|
1421b447ae7b419ed8303c1af8632b5884b59704
|
uwe kleine k nig
|
drivers
|
gpio
| |
gpio: rcar: add r-car v3u (r8a779a0) support
|
add support for the gpio controller block in the r-car v3u (r8a779a0) soc, which is very similar to the block found on other r-car gen3 socs. however, this block has a new general input enable register (inen), whose reset state is to have all inputs disabled.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add r-car v3u (r8a779a0) support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['rcar']
|
['c']
| 1
| 35
| 0
|
--- diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c + bool has_inen; +#define inen 0x50 /* general input enable register */ + .has_inen = false, + .has_inen = false, + .has_inen = false, +}; + +static const struct gpio_rcar_info gpio_rcar_info_v3u = { + .has_outdtsel = true, + .has_both_edge_trigger = true, + .has_always_in = true, + .has_inen = true, + .compatible = "renesas,gpio-r8a779a0", + .data = &gpio_rcar_info_v3u, + }, { +static void gpio_rcar_enable_inputs(struct gpio_rcar_priv *p) +{ + u32 mask = genmask(p->gpio_chip.ngpio - 1, 0); + + /* select "input enable" in inen */ + if (p->gpio_chip.valid_mask) + mask &= p->gpio_chip.valid_mask[0]; + if (mask) + gpio_rcar_write(p, inen, gpio_rcar_read(p, inen) | mask); +} + + if (p->info.has_inen) { + pm_runtime_get_sync(p->dev); + gpio_rcar_enable_inputs(p); + pm_runtime_put(p->dev); + } + + if (p->info.has_inen) + gpio_rcar_enable_inputs(p); +
|
General Purpose I/O (gpio)
|
93ac0b0c68c0cff8e49d2a7c08525824dbb8642e
|
geert uytterhoeven
|
drivers
|
gpio
| |
gpio: remove zte zx driver
|
the zte zx platform is getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove zte zx driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['txt', 'kconfig', 'c', 'makefile']
| 4
| 0
| 321
|
--- diff --git a/documentation/devicetree/bindings/gpio/zx296702-gpio.txt b/documentation/devicetree/bindings/gpio/zx296702-gpio.txt --- a/documentation/devicetree/bindings/gpio/zx296702-gpio.txt +++ /dev/null -zte zx296702 gpio controller - -required properties: -- compatible : "zte,zx296702-gpio" -- #gpio-cells : should be two. the first cell is the pin number and the - second cell is used to specify optional parameters: - - bit 0 specifies polarity (0 for normal, 1 for inverted) -- gpio-controller : marks the device node as a gpio controller. -- interrupts : interrupt mapping for gpio irq. -- gpio-ranges : interaction with the pinctrl subsystem. - -gpio1: gpio@b008040 { - compatible = "zte,zx296702-gpio"; - reg = <0xb008040 0x40>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 54 2 &pmx0 2 59 14>; - interrupts = <gic_spi 26 irq_type_level_high>; - interrupt-parent = <&intc>; - interrupt-controller; - #interrupt-cells = <2>; - clock-names = "gpio_pclk"; - clocks = <&lsp0clk zx296702_gpio_clk>; -}; diff --git a/drivers/gpio/kconfig b/drivers/gpio/kconfig --- a/drivers/gpio/kconfig +++ b/drivers/gpio/kconfig -config gpio_zx - bool "zte zx gpio support" - depends on arch_zx || compile_test - select gpiolib_irqchip - help - say yes here to support the gpio device on zte zx socs. - diff --git a/drivers/gpio/makefile b/drivers/gpio/makefile --- a/drivers/gpio/makefile +++ b/drivers/gpio/makefile -obj-$(config_gpio_zx) += gpio-zx.o diff --git a/drivers/gpio/gpio-zx.c b/drivers/gpio/gpio-zx.c --- a/drivers/gpio/gpio-zx.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * zte zx296702 gpio driver - * - * author: jun nie <jun.nie@linaro.org> - * - * copyright (c) 2015 linaro ltd. - */ -#include <linux/bitops.h> -#include <linux/device.h> -#include <linux/errno.h> -#include <linux/gpio/driver.h> -#include <linux/irqchip/chained_irq.h> -#include <linux/init.h> -#include <linux/of.h> -#include <linux/pinctrl/consumer.h> -#include <linux/platform_device.h> -#include <linux/pm.h> -#include <linux/slab.h> -#include <linux/spinlock.h> - -#define zx_gpio_dir 0x00 -#define zx_gpio_ive 0x04 -#define zx_gpio_iv 0x08 -#define zx_gpio_iep 0x0c -#define zx_gpio_ien 0x10 -#define zx_gpio_di 0x14 -#define zx_gpio_do1 0x18 -#define zx_gpio_do0 0x1c -#define zx_gpio_do 0x20 - -#define zx_gpio_im 0x28 -#define zx_gpio_ie 0x2c - -#define zx_gpio_mis 0x30 -#define zx_gpio_ic 0x34 - -#define zx_gpio_nr 16 - -struct zx_gpio { - raw_spinlock_t lock; - - void __iomem *base; - struct gpio_chip gc; -}; - -static int zx_direction_input(struct gpio_chip *gc, unsigned offset) -{ - struct zx_gpio *chip = gpiochip_get_data(gc); - unsigned long flags; - u16 gpiodir; - - if (offset >= gc->ngpio) - return -einval; - - raw_spin_lock_irqsave(&chip->lock, flags); - gpiodir = readw_relaxed(chip->base + zx_gpio_dir); - gpiodir &= ~bit(offset); - writew_relaxed(gpiodir, chip->base + zx_gpio_dir); - raw_spin_unlock_irqrestore(&chip->lock, flags); - - return 0; -} - -static int zx_direction_output(struct gpio_chip *gc, unsigned offset, - int value) -{ - struct zx_gpio *chip = gpiochip_get_data(gc); - unsigned long flags; - u16 gpiodir; - - if (offset >= gc->ngpio) - return -einval; - - raw_spin_lock_irqsave(&chip->lock, flags); - gpiodir = readw_relaxed(chip->base + zx_gpio_dir); - gpiodir |= bit(offset); - writew_relaxed(gpiodir, chip->base + zx_gpio_dir); - - if (value) - writew_relaxed(bit(offset), chip->base + zx_gpio_do1); - else - writew_relaxed(bit(offset), chip->base + zx_gpio_do0); - raw_spin_unlock_irqrestore(&chip->lock, flags); - - return 0; -} - -static int zx_get_value(struct gpio_chip *gc, unsigned offset) -{ - struct zx_gpio *chip = gpiochip_get_data(gc); - - return !!(readw_relaxed(chip->base + zx_gpio_di) & bit(offset)); -} - -static void zx_set_value(struct gpio_chip *gc, unsigned offset, int value) -{ - struct zx_gpio *chip = gpiochip_get_data(gc); - - if (value) - writew_relaxed(bit(offset), chip->base + zx_gpio_do1); - else - writew_relaxed(bit(offset), chip->base + zx_gpio_do0); -} - -static int zx_irq_type(struct irq_data *d, unsigned trigger) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct zx_gpio *chip = gpiochip_get_data(gc); - int offset = irqd_to_hwirq(d); - unsigned long flags; - u16 gpiois, gpioi_epos, gpioi_eneg, gpioiev; - u16 bit = bit(offset); - - if (offset < 0 || offset >= zx_gpio_nr) - return -einval; - - raw_spin_lock_irqsave(&chip->lock, flags); - - gpioiev = readw_relaxed(chip->base + zx_gpio_iv); - gpiois = readw_relaxed(chip->base + zx_gpio_ive); - gpioi_epos = readw_relaxed(chip->base + zx_gpio_iep); - gpioi_eneg = readw_relaxed(chip->base + zx_gpio_ien); - - if (trigger & (irq_type_level_high | irq_type_level_low)) { - gpiois |= bit; - if (trigger & irq_type_level_high) - gpioiev |= bit; - else - gpioiev &= ~bit; - } else - gpiois &= ~bit; - - if ((trigger & irq_type_edge_both) == irq_type_edge_both) { - gpioi_epos |= bit; - gpioi_eneg |= bit; - } else { - if (trigger & irq_type_edge_rising) { - gpioi_epos |= bit; - gpioi_eneg &= ~bit; - } else if (trigger & irq_type_edge_falling) { - gpioi_eneg |= bit; - gpioi_epos &= ~bit; - } - } - - writew_relaxed(gpiois, chip->base + zx_gpio_ive); - writew_relaxed(gpioi_epos, chip->base + zx_gpio_iep); - writew_relaxed(gpioi_eneg, chip->base + zx_gpio_ien); - writew_relaxed(gpioiev, chip->base + zx_gpio_iv); - raw_spin_unlock_irqrestore(&chip->lock, flags); - - return 0; -} - -static void zx_irq_handler(struct irq_desc *desc) -{ - unsigned long pending; - int offset; - struct gpio_chip *gc = irq_desc_get_handler_data(desc); - struct zx_gpio *chip = gpiochip_get_data(gc); - struct irq_chip *irqchip = irq_desc_get_chip(desc); - - chained_irq_enter(irqchip, desc); - - pending = readw_relaxed(chip->base + zx_gpio_mis); - writew_relaxed(pending, chip->base + zx_gpio_ic); - if (pending) { - for_each_set_bit(offset, &pending, zx_gpio_nr) - generic_handle_irq(irq_find_mapping(gc->irq.domain, - offset)); - } - - chained_irq_exit(irqchip, desc); -} - -static void zx_irq_mask(struct irq_data *d) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct zx_gpio *chip = gpiochip_get_data(gc); - u16 mask = bit(irqd_to_hwirq(d) % zx_gpio_nr); - u16 gpioie; - - raw_spin_lock(&chip->lock); - gpioie = readw_relaxed(chip->base + zx_gpio_im) | mask; - writew_relaxed(gpioie, chip->base + zx_gpio_im); - gpioie = readw_relaxed(chip->base + zx_gpio_ie) & ~mask; - writew_relaxed(gpioie, chip->base + zx_gpio_ie); - raw_spin_unlock(&chip->lock); -} - -static void zx_irq_unmask(struct irq_data *d) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct zx_gpio *chip = gpiochip_get_data(gc); - u16 mask = bit(irqd_to_hwirq(d) % zx_gpio_nr); - u16 gpioie; - - raw_spin_lock(&chip->lock); - gpioie = readw_relaxed(chip->base + zx_gpio_im) & ~mask; - writew_relaxed(gpioie, chip->base + zx_gpio_im); - gpioie = readw_relaxed(chip->base + zx_gpio_ie) | mask; - writew_relaxed(gpioie, chip->base + zx_gpio_ie); - raw_spin_unlock(&chip->lock); -} - -static struct irq_chip zx_irqchip = { - .name = "zx-gpio", - .irq_mask = zx_irq_mask, - .irq_unmask = zx_irq_unmask, - .irq_set_type = zx_irq_type, -}; - -static int zx_gpio_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct zx_gpio *chip; - struct gpio_irq_chip *girq; - int irq, id, ret; - - chip = devm_kzalloc(dev, sizeof(*chip), gfp_kernel); - if (!chip) - return -enomem; - - chip->base = devm_platform_ioremap_resource(pdev, 0); - if (is_err(chip->base)) - return ptr_err(chip->base); - - id = of_alias_get_id(dev->of_node, "gpio"); - - raw_spin_lock_init(&chip->lock); - chip->gc.request = gpiochip_generic_request; - chip->gc.free = gpiochip_generic_free; - chip->gc.direction_input = zx_direction_input; - chip->gc.direction_output = zx_direction_output; - chip->gc.get = zx_get_value; - chip->gc.set = zx_set_value; - chip->gc.base = zx_gpio_nr * id; - chip->gc.ngpio = zx_gpio_nr; - chip->gc.label = dev_name(dev); - chip->gc.parent = dev; - chip->gc.owner = this_module; - - /* - * irq_chip support - */ - writew_relaxed(0xffff, chip->base + zx_gpio_im); - writew_relaxed(0, chip->base + zx_gpio_ie); - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; - girq = &chip->gc.irq; - girq->chip = &zx_irqchip; - girq->parent_handler = zx_irq_handler; - girq->num_parents = 1; - girq->parents = devm_kcalloc(&pdev->dev, 1, - sizeof(*girq->parents), - gfp_kernel); - if (!girq->parents) - return -enomem; - girq->parents[0] = irq; - girq->default_type = irq_type_none; - girq->handler = handle_simple_irq; - - ret = gpiochip_add_data(&chip->gc, chip); - if (ret) - return ret; - - platform_set_drvdata(pdev, chip); - dev_info(dev, "zx gpio chip registered "); - - return 0; -} - -static const struct of_device_id zx_gpio_match[] = { - { - .compatible = "zte,zx296702-gpio", - }, - { }, -}; - -static struct platform_driver zx_gpio_driver = { - .probe = zx_gpio_probe, - .driver = { - .name = "zx_gpio", - .of_match_table = of_match_ptr(zx_gpio_match), - }, -}; -builtin_platform_driver(zx_gpio_driver)
|
General Purpose I/O (gpio)
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f0a2c77eb8e9ac5a4d783ef04c3e0f712cb707d6
|
arnd bergmann linus walleij linus walleij linaro org
|
documentation
|
devicetree
|
bindings, gpio
|
gpio: visconti: add toshiba visconti gpio support
|
add the gpio driver for toshiba visconti arm socs.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add toshiba visconti gpio support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['visconti']
|
['kconfig', 'c', 'makefile']
| 4
| 252
| 0
|
--- diff --git a/drivers/gpio/kconfig b/drivers/gpio/kconfig --- a/drivers/gpio/kconfig +++ b/drivers/gpio/kconfig +config gpio_visconti + tristate "toshiba visconti gpio support" + depends on arch_visconti || compile_test + depends on of_gpio + select gpiolib_irqchip + select gpio_generic + select irq_domain_hierarchy + help + say yes here to support gpio on tohisba visconti. + diff --git a/drivers/gpio/makefile b/drivers/gpio/makefile --- a/drivers/gpio/makefile +++ b/drivers/gpio/makefile +obj-$(config_gpio_visconti) += gpio-visconti.o diff --git a/drivers/gpio/gpio-visconti.c b/drivers/gpio/gpio-visconti.c --- /dev/null +++ b/drivers/gpio/gpio-visconti.c +// spdx-license-identifier: gpl-2.0 +/* + * toshiba visconti gpio support + * + * (c) copyright 2020 toshiba electronic devices & storage corporation + * (c) copyright 2020 toshiba corporation + * + * nobuhiro iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> + */ + +#include <linux/gpio/driver.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/module.h> +#include <linux/io.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/bitops.h> + +/* register offset */ +#define gpio_dir 0x00 +#define gpio_idata 0x08 +#define gpio_odata 0x10 +#define gpio_oset 0x18 +#define gpio_oclr 0x20 +#define gpio_intmode 0x30 + +#define base_hw_irq 24 + +struct visconti_gpio { + void __iomem *base; + spinlock_t lock; /* protect gpio register */ + struct gpio_chip gpio_chip; + struct irq_chip irq_chip; +}; + +static int visconti_gpio_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct visconti_gpio *priv = gpiochip_get_data(gc); + u32 offset = irqd_to_hwirq(d); + u32 bit = bit(offset); + u32 intc_type = irq_type_edge_rising; + u32 intmode, odata; + int ret = 0; + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + + odata = readl(priv->base + gpio_odata); + intmode = readl(priv->base + gpio_intmode); + + switch (type) { + case irq_type_edge_rising: + odata &= ~bit; + intmode &= ~bit; + break; + case irq_type_edge_falling: + odata |= bit; + intmode &= ~bit; + break; + case irq_type_edge_both: + intmode |= bit; + break; + case irq_type_level_high: + intc_type = irq_type_level_high; + odata &= ~bit; + intmode &= ~bit; + break; + case irq_type_level_low: + intc_type = irq_type_level_high; + odata |= bit; + intmode &= ~bit; + break; + default: + ret = -einval; + goto err; + } + + writel(odata, priv->base + gpio_odata); + writel(intmode, priv->base + gpio_intmode); + irq_set_irq_type(offset, intc_type); + + ret = irq_chip_set_type_parent(d, type); +err: + spin_unlock_irqrestore(&priv->lock, flags); + return ret; +} + +static int visconti_gpio_child_to_parent_hwirq(struct gpio_chip *gc, + unsigned int child, + unsigned int child_type, + unsigned int *parent, + unsigned int *parent_type) +{ + /* interrupts 0..15 mapped to interrupts 24..39 on the gic */ + if (child < 16) { + /* all these interrupts are level high in the cpu */ + *parent_type = irq_type_level_high; + *parent = child + base_hw_irq; + return 0; + } + return -einval; +} + +static void *visconti_gpio_populate_parent_fwspec(struct gpio_chip *chip, + unsigned int parent_hwirq, + unsigned int parent_type) +{ + struct irq_fwspec *fwspec; + + fwspec = kmalloc(sizeof(*fwspec), gfp_kernel); + if (!fwspec) + return null; + + fwspec->fwnode = chip->irq.parent_domain->fwnode; + fwspec->param_count = 3; + fwspec->param[0] = 0; + fwspec->param[1] = parent_hwirq; + fwspec->param[2] = parent_type; + + return fwspec; +} + +static int visconti_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct visconti_gpio *priv; + struct irq_chip *irq_chip; + struct gpio_irq_chip *girq; + struct irq_domain *parent; + struct device_node *irq_parent; + struct fwnode_handle *fwnode; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), gfp_kernel); + if (!priv) + return -enomem; + + spin_lock_init(&priv->lock); + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (is_err(priv->base)) + return ptr_err(priv->base); + + irq_parent = of_irq_find_parent(dev->of_node); + if (!irq_parent) { + dev_err(dev, "no irq parent node "); + return -enodev; + } + + parent = irq_find_host(irq_parent); + if (!parent) { + dev_err(dev, "no irq parent domain "); + return -enodev; + } + + fwnode = of_node_to_fwnode(irq_parent); + of_node_put(irq_parent); + + ret = bgpio_init(&priv->gpio_chip, dev, 4, + priv->base + gpio_idata, + priv->base + gpio_oset, + priv->base + gpio_oclr, + priv->base + gpio_dir, + null, + 0); + if (ret) { + dev_err(dev, "unable to init generic gpio "); + return ret; + } + + irq_chip = &priv->irq_chip; + irq_chip->name = dev_name(dev); + irq_chip->irq_mask = irq_chip_mask_parent; + irq_chip->irq_unmask = irq_chip_unmask_parent; + irq_chip->irq_eoi = irq_chip_eoi_parent; + irq_chip->irq_set_type = visconti_gpio_irq_set_type; + irq_chip->flags = irqchip_set_type_masked | irqchip_mask_on_suspend; + + girq = &priv->gpio_chip.irq; + girq->chip = irq_chip; + girq->fwnode = fwnode; + girq->parent_domain = parent; + girq->child_to_parent_hwirq = visconti_gpio_child_to_parent_hwirq; + girq->populate_parent_alloc_arg = visconti_gpio_populate_parent_fwspec; + girq->default_type = irq_type_none; + girq->handler = handle_level_irq; + + ret = devm_gpiochip_add_data(dev, &priv->gpio_chip, priv); + if (ret) { + dev_err(dev, "failed to add gpio chip "); + return ret; + } + + platform_set_drvdata(pdev, priv); + + return ret; +} + +static const struct of_device_id visconti_gpio_of_match[] = { + { .compatible = "toshiba,gpio-tmpv7708", }, + { /* end of table */ } +}; +module_device_table(of, visconti_gpio_of_match); + +static struct platform_driver visconti_gpio_driver = { + .probe = visconti_gpio_probe, + .driver = { + .name = "visconti_gpio", + .of_match_table = of_match_ptr(visconti_gpio_of_match), + } +}; +module_platform_driver(visconti_gpio_driver); + +module_author("nobuhiro iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>"); +module_description("toshiba visconti gpio driver"); +module_license("gpl v2"); diff --git a/drivers/pinctrl/visconti/pinctrl-common.c b/drivers/pinctrl/visconti/pinctrl-common.c --- a/drivers/pinctrl/visconti/pinctrl-common.c +++ b/drivers/pinctrl/visconti/pinctrl-common.c +static int visconti_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + const struct visconti_mux *gpio_mux = &priv->devdata->gpio_mux[pin]; + unsigned long flags; + unsigned int val; + + dev_dbg(priv->dev, "%s: pin = %d ", __func__, pin); + + /* update mux */ + spin_lock_irqsave(&priv->lock, flags); + val = readl(priv->base + gpio_mux->offset); + val &= ~gpio_mux->mask; + val |= gpio_mux->val; + writel(val, priv->base + gpio_mux->offset); + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + + .gpio_request_enable = visconti_gpio_request_enable,
|
General Purpose I/O (gpio)
|
2ad74f40dacc411546d737ce92197384cd8587bd
|
nobuhiro iwamatsu punit agrawal punit agrawal toshiba co jp linus walleij linus walleij linaro org
|
drivers
|
pinctrl
|
visconti
|
gpio: msic: remove driver for deprecated platform
|
intel moorestown and medfield are quite old intel atom based 32-bit platforms, which were in limited use in some android phones, tablets and consumer electronics more than eight years ago.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove driver for deprecated platform
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['msic']
|
['kconfig', 'maintainers', 'c']
| 3
| 0
| 322
|
--- diff --git a/maintainers b/maintainers --- a/maintainers +++ b/maintainers -f: drivers/gpio/gpio-msic.c diff --git a/drivers/gpio/kconfig b/drivers/gpio/kconfig --- a/drivers/gpio/kconfig +++ b/drivers/gpio/kconfig -config gpio_msic - bool "intel msic mixed signal gpio support" - depends on (x86 || compile_test) && mfd_intel_msic - help - enable support for gpio on intel msic controllers found in - intel mid devices - diff --git a/drivers/gpio/gpio-msic.c b/drivers/gpio/gpio-msic.c --- a/drivers/gpio/gpio-msic.c +++ /dev/null -// spdx-license-identifier: gpl-2.0 -/* - * intel medfield msic gpio driver> - * copyright (c) 2011, intel corporation. - * - * author: mathias nyman <mathias.nyman@linux.intel.com> - * based on intel_pmic_gpio.c - */ - -#include <linux/gpio/driver.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/kernel.h> -#include <linux/mfd/intel_msic.h> -#include <linux/platform_device.h> -#include <linux/slab.h> - -/* the offset for the mapping of global gpio pin to irq */ -#define msic_gpio_irq_offset 0x100 - -#define msic_gpio_dir_in 0 -#define msic_gpio_dir_out bit(5) -#define msic_gpio_trig_fall bit(1) -#define msic_gpio_trig_rise bit(2) - -/* masks for msic gpio output gpioxxxxctlo registers */ -#define msic_gpio_dir_mask bit(5) -#define msic_gpio_drv_mask bit(4) -#define msic_gpio_ren_mask bit(3) -#define msic_gpio_rval_mask (bit(2) | bit(1)) -#define msic_gpio_dout_mask bit(0) - -/* masks for msic gpio input gpioxxxxctli registers */ -#define msic_gpio_glbyp_mask bit(5) -#define msic_gpio_dbnc_mask (bit(4) | bit(3)) -#define msic_gpio_intcnt_mask (bit(2) | bit(1)) -#define msic_gpio_din_mask bit(0) - -#define msic_num_gpio 24 - -struct msic_gpio { - struct platform_device *pdev; - struct mutex buslock; - struct gpio_chip chip; - int irq; - unsigned irq_base; - unsigned long trig_change_mask; - unsigned trig_type; -}; - -/* - * msic has 24 gpios, 16 low voltage (1.2-1.8v) and 8 high voltage (3v). - * both the high and low voltage gpios are divided in two banks. - * gpios are numbered with gpio0lv0 as gpio_base in the following order: - * gpio0lv0..gpio0lv7: low voltage, bank 0, gpio_base - * gpio1lv0..gpio1lv7: low voltage, bank 1, gpio_base + 8 - * gpio0hv0..gpio0hv3: high voltage, bank 0, gpio_base + 16 - * gpio1hv0..gpio1hv3: high voltage, bank 1, gpio_base + 20 - */ - -static int msic_gpio_to_ireg(unsigned offset) -{ - if (offset >= msic_num_gpio) - return -einval; - - if (offset < 8) - return intel_msic_gpio0lv0ctli - offset; - if (offset < 16) - return intel_msic_gpio1lv0ctli - offset + 8; - if (offset < 20) - return intel_msic_gpio0hv0ctli - offset + 16; - - return intel_msic_gpio1hv0ctli - offset + 20; -} - -static int msic_gpio_to_oreg(unsigned offset) -{ - if (offset >= msic_num_gpio) - return -einval; - - if (offset < 8) - return intel_msic_gpio0lv0ctlo - offset; - if (offset < 16) - return intel_msic_gpio1lv0ctlo - offset + 8; - if (offset < 20) - return intel_msic_gpio0hv0ctlo - offset + 16; - - return intel_msic_gpio1hv0ctlo - offset + 20; -} - -static int msic_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -{ - int reg; - - reg = msic_gpio_to_oreg(offset); - if (reg < 0) - return reg; - - return intel_msic_reg_update(reg, msic_gpio_dir_in, msic_gpio_dir_mask); -} - -static int msic_gpio_direction_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - int reg; - unsigned mask; - - value = (!!value) | msic_gpio_dir_out; - mask = msic_gpio_dir_mask | msic_gpio_dout_mask; - - reg = msic_gpio_to_oreg(offset); - if (reg < 0) - return reg; - - return intel_msic_reg_update(reg, value, mask); -} - -static int msic_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - u8 r; - int ret; - int reg; - - reg = msic_gpio_to_ireg(offset); - if (reg < 0) - return reg; - - ret = intel_msic_reg_read(reg, &r); - if (ret < 0) - return ret; - - return !!(r & msic_gpio_din_mask); -} - -static void msic_gpio_set(struct gpio_chip *chip, unsigned offset, int value) -{ - int reg; - - reg = msic_gpio_to_oreg(offset); - if (reg < 0) - return; - - intel_msic_reg_update(reg, !!value , msic_gpio_dout_mask); -} - -/* - * this is called from genirq with mg->buslock locked and - * irq_desc->lock held. we can not access the scu bus here, so we - * store the change and update in the bus_sync_unlock() function below - */ -static int msic_irq_type(struct irq_data *data, unsigned type) -{ - struct msic_gpio *mg = irq_data_get_irq_chip_data(data); - u32 gpio = data->irq - mg->irq_base; - - if (gpio >= mg->chip.ngpio) - return -einval; - - /* mark for which gpio the trigger changed, protected by buslock */ - mg->trig_change_mask |= (1 << gpio); - mg->trig_type = type; - - return 0; -} - -static int msic_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct msic_gpio *mg = gpiochip_get_data(chip); - return mg->irq_base + offset; -} - -static void msic_bus_lock(struct irq_data *data) -{ - struct msic_gpio *mg = irq_data_get_irq_chip_data(data); - mutex_lock(&mg->buslock); -} - -static void msic_bus_sync_unlock(struct irq_data *data) -{ - struct msic_gpio *mg = irq_data_get_irq_chip_data(data); - int offset; - int reg; - u8 trig = 0; - - /* we can only get one change at a time as the buslock covers the - entire transaction. the irq_desc->lock is dropped before we are - called but that is fine */ - if (mg->trig_change_mask) { - offset = __ffs(mg->trig_change_mask); - - reg = msic_gpio_to_ireg(offset); - if (reg < 0) - goto out; - - if (mg->trig_type & irq_type_edge_rising) - trig |= msic_gpio_trig_rise; - if (mg->trig_type & irq_type_edge_falling) - trig |= msic_gpio_trig_fall; - - intel_msic_reg_update(reg, trig, msic_gpio_intcnt_mask); - mg->trig_change_mask = 0; - } -out: - mutex_unlock(&mg->buslock); -} - -/* firmware does all the masking and unmasking for us, no masking here. */ -static void msic_irq_unmask(struct irq_data *data) { } - -static void msic_irq_mask(struct irq_data *data) { } - -static struct irq_chip msic_irqchip = { - .name = "msic-gpio", - .irq_mask = msic_irq_mask, - .irq_unmask = msic_irq_unmask, - .irq_set_type = msic_irq_type, - .irq_bus_lock = msic_bus_lock, - .irq_bus_sync_unlock = msic_bus_sync_unlock, -}; - -static void msic_gpio_irq_handler(struct irq_desc *desc) -{ - struct irq_data *data = irq_desc_get_irq_data(desc); - struct msic_gpio *mg = irq_data_get_irq_handler_data(data); - struct irq_chip *chip = irq_data_get_irq_chip(data); - struct intel_msic *msic = pdev_to_intel_msic(mg->pdev); - unsigned long pending; - int i; - int bitnr; - u8 pin; - - for (i = 0; i < (mg->chip.ngpio / bits_per_byte); i++) { - intel_msic_irq_read(msic, intel_msic_gpio0lvirq + i, &pin); - pending = pin; - - for_each_set_bit(bitnr, &pending, bits_per_byte) - generic_handle_irq(mg->irq_base + i * bits_per_byte + bitnr); - } - chip->irq_eoi(data); -} - -static int platform_msic_gpio_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct intel_msic_gpio_pdata *pdata = dev_get_platdata(dev); - struct msic_gpio *mg; - int irq = platform_get_irq(pdev, 0); - int retval; - int i; - - if (irq < 0) { - dev_err(dev, "no irq line: %d ", irq); - return irq; - } - - if (!pdata || !pdata->gpio_base) { - dev_err(dev, "incorrect or missing platform data "); - return -einval; - } - - mg = kzalloc(sizeof(*mg), gfp_kernel); - if (!mg) - return -enomem; - - dev_set_drvdata(dev, mg); - - mg->pdev = pdev; - mg->irq = irq; - mg->irq_base = pdata->gpio_base + msic_gpio_irq_offset; - mg->chip.label = "msic_gpio"; - mg->chip.direction_input = msic_gpio_direction_input; - mg->chip.direction_output = msic_gpio_direction_output; - mg->chip.get = msic_gpio_get; - mg->chip.set = msic_gpio_set; - mg->chip.to_irq = msic_gpio_to_irq; - mg->chip.base = pdata->gpio_base; - mg->chip.ngpio = msic_num_gpio; - mg->chip.can_sleep = true; - mg->chip.parent = dev; - - mutex_init(&mg->buslock); - - retval = gpiochip_add_data(&mg->chip, mg); - if (retval) { - dev_err(dev, "adding msic gpio chip failed "); - goto err; - } - - for (i = 0; i < mg->chip.ngpio; i++) { - irq_set_chip_data(i + mg->irq_base, mg); - irq_set_chip_and_handler(i + mg->irq_base, - &msic_irqchip, - handle_simple_irq); - } - irq_set_chained_handler_and_data(mg->irq, msic_gpio_irq_handler, mg); - - return 0; -err: - kfree(mg); - return retval; -} - -static struct platform_driver platform_msic_gpio_driver = { - .driver = { - .name = "msic_gpio", - }, - .probe = platform_msic_gpio_probe, -}; - -static int __init platform_msic_gpio_init(void) -{ - return platform_driver_register(&platform_msic_gpio_driver); -} -subsys_initcall(platform_msic_gpio_init);
|
General Purpose I/O (gpio)
|
aee25798acf00978a2d9d39ae8b2c2353757d01d
|
andy shevchenko
|
drivers
|
gpio
| |
leds: apu: extend support for pc engines apu1 with newer firmware
|
the dmi_product_name entry on current firmware of pc engines apu1 changed from "apu" to "apu1"
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
extend support for pc engines apu1 with newer firmware
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['apu']
|
['c']
| 1
| 10
| 1
|
--- diff --git a/drivers/leds/leds-apu.c b/drivers/leds/leds-apu.c --- a/drivers/leds/leds-apu.c +++ b/drivers/leds/leds-apu.c + /* pc engines apu with factory bios "sagebios_pcengines_apu-45" */ + /* pc engines apu with "mainline" bios >= 4.6.8 */ + { + .ident = "apu", + .matches = { + dmi_match(dmi_sys_vendor, "pc engines"), + dmi_match(dmi_product_name, "apu1") + } + }, - dmi_match(dmi_product_name, "apu"))) { + (dmi_match(dmi_product_name, "apu") || dmi_match(dmi_product_name, "apu1")))) {
|
Leds
|
1b40faf7e4abe10db2f730cf66b2b47551110940
|
andreas eberlein
|
drivers
|
leds
| |
leds: lgm: add led controller driver for lgm soc
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parallel to serial conversion, which is also called sso controller, can drive external shift register for led outputs, reset or general purpose outputs.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add led controller driver for lgm soc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['lgm']
|
['kconfig', 'c', 'makefile']
| 5
| 916
| 0
|
--- diff --git a/drivers/leds/kconfig b/drivers/leds/kconfig --- a/drivers/leds/kconfig +++ b/drivers/leds/kconfig +comment "led blink" +source "drivers/leds/blink/kconfig" + diff --git a/drivers/leds/makefile b/drivers/leds/makefile --- a/drivers/leds/makefile +++ b/drivers/leds/makefile + +# led blink +obj-$(config_leds_blink) += blink/ diff --git a/drivers/leds/blink/kconfig b/drivers/leds/blink/kconfig --- /dev/null +++ b/drivers/leds/blink/kconfig +menuconfig leds_blink + bool "led blink support" + depends on leds_class + help + this option enables blink support for the leds class. + if unsure, say y. + +if leds_blink + +config leds_blink_lgm + tristate "led support for intel lgm soc series" + depends on leds_class + depends on mfd_syscon + depends on of + help + parallel to serial conversion, which is also called sso controller, + can drive external shift register for led outputs. + this enables led support for serial shift output controller(sso). + +endif # leds_blink diff --git a/drivers/leds/blink/makefile b/drivers/leds/blink/makefile --- /dev/null +++ b/drivers/leds/blink/makefile +# spdx-license-identifier: gpl-2.0 +obj-$(config_leds_blink_lgm) += leds-lgm-sso.o diff --git a/drivers/leds/blink/leds-lgm-sso.c b/drivers/leds/blink/leds-lgm-sso.c --- /dev/null +++ b/drivers/leds/blink/leds-lgm-sso.c +// spdx-license-identifier: gpl-2.0 +/* + * intel lightning mountain soc led serial shift output controller driver + * + * copyright (c) 2020 intel corporation. + */ + +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/leds.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/property.h> +#include <linux/regmap.h> +#include <linux/sizes.h> +#include <linux/uaccess.h> + +#define sso_dev_name "lgm-sso" + +#define led_blink_h8_0 0x0 +#define led_blink_h8_1 0x4 +#define get_freq_offset(pin, src) (((pin) * 6) + ((src) * 2)) +#define get_src_offset(pinc) (((pin) * 6) + 4) + +#define duty_cycle(x) (0x8 + ((x) * 4)) +#define sso_con0 0x2b0 +#define sso_con0_rzfl bit(26) +#define sso_con0_blink_r bit(30) +#define sso_con0_swu bit(31) + +#define sso_con1 0x2b4 +#define sso_con1_fcdsc genmask(21, 20) /* fixed divider shift clock */ +#define sso_con1_fpid genmask(24, 23) +#define sso_con1_gptd genmask(26, 25) +#define sso_con1_us genmask(31, 30) + +#define sso_cpu 0x2b8 +#define sso_con2 0x2c4 +#define sso_con3 0x2c8 + +/* driver macro */ +#define max_pin_num_per_bank sz_32 +#define max_group_num sz_4 +#define pins_per_group sz_8 +#define fpid_freq_rank_max sz_4 +#define sso_led_max_num sz_32 +#define max_freq_rank 10 +#define def_gptc_clk_rate 200000000 +#define sso_def_brightness led_half +#define data_clk_edge 0 /* 0-rising, 1-falling */ + +static const u32 freq_div_tbl[] = {4000, 2000, 1000, 800}; +static const int freq_tbl[] = {2, 4, 8, 10, 50000, 100000, 200000, 250000}; +static const int shift_clk_freq_tbl[] = {25000000, 12500000, 6250000, 3125000}; + +/* + * update source to update the souts + * sw - software has to update the swu bit + * gptc - general purpose timer is used as clock source + * fpid - divided fsc clock (fpid) is used as clock source + */ +enum { + us_sw = 0, + us_gptc = 1, + us_fpid = 2 +}; + +enum { + max_fpid_freq_rank = 5, /* 1 to 4 */ + max_gptc_freq_rank = 9, /* 5 to 8 */ + max_gptc_hs_freq_rank = 10, /* 9 to 10 */ +}; + +enum { + led_grp0_pin_max = 24, + led_grp1_pin_max = 29, + led_grp2_pin_max = 32, +}; + +enum { + led_grp0_0_23, + led_grp1_24_28, + led_grp2_29_31, + led_group_max, +}; + +enum { + clk_src_fpid = 0, + clk_src_gptc = 1, + clk_src_gptc_hs = 2, +}; + +struct sso_led_priv; + +struct sso_led_desc { + const char *name; + const char *default_trigger; + unsigned int brightness; + unsigned int blink_rate; + unsigned int retain_state_suspended:1; + unsigned int retain_state_shutdown:1; + unsigned int panic_indicator:1; + unsigned int hw_blink:1; + unsigned int hw_trig:1; + unsigned int blinking:1; + int freq_idx; + u32 pin; +}; + +struct sso_led { + struct list_head list; + struct led_classdev cdev; + struct gpio_desc *gpiod; + struct sso_led_desc desc; + struct sso_led_priv *priv; +}; + +struct sso_gpio { + struct gpio_chip chip; + int shift_clk_freq; + int edge; + int freq; + u32 pins; + u32 alloc_bitmap; +}; + +struct sso_led_priv { + struct regmap *mmap; + struct device *dev; + struct platform_device *pdev; + struct clk *gclk; + struct clk *fpid_clk; + u32 fpid_clkrate; + u32 gptc_clkrate; + u32 freq[max_freq_rank]; + struct list_head led_list; + struct sso_gpio gpio; +}; + +static int sso_get_blink_rate_idx(struct sso_led_priv *priv, u32 rate) +{ + int i; + + for (i = 0; i < max_freq_rank; i++) { + if (rate <= priv->freq[i]) + return i; + } + + return -1; +} + +static unsigned int sso_led_pin_to_group(u32 pin) +{ + if (pin < led_grp0_pin_max) + return led_grp0_0_23; + else if (pin < led_grp1_pin_max) + return led_grp1_24_28; + else + return led_grp2_29_31; +} + +static u32 sso_led_get_freq_src(int freq_idx) +{ + if (freq_idx < max_fpid_freq_rank) + return clk_src_fpid; + else if (freq_idx < max_gptc_freq_rank) + return clk_src_gptc; + else + return clk_src_gptc_hs; +} + +static u32 sso_led_pin_blink_off(u32 pin, unsigned int group) +{ + if (group == led_grp2_29_31) + return pin - led_grp1_pin_max; + else if (group == led_grp1_24_28) + return pin - led_grp0_pin_max; + else /* led 0 - 23 in led 32 location */ + return sso_led_max_num - led_grp1_pin_max; +} + +static struct sso_led +*cdev_to_sso_led_data(struct led_classdev *led_cdev) +{ + return container_of(led_cdev, struct sso_led, cdev); +} + +static void sso_led_freq_set(struct sso_led_priv *priv, u32 pin, int freq_idx) +{ + u32 reg, off, freq_src, val_freq; + u32 low, high, val; + unsigned int group; + + if (!freq_idx) + return; + + group = sso_led_pin_to_group(pin); + freq_src = sso_led_get_freq_src(freq_idx); + off = sso_led_pin_blink_off(pin, group); + + if (group == led_grp0_0_23) + return; + else if (group == led_grp1_24_28) + reg = led_blink_h8_0; + else + reg = led_blink_h8_1; + + if (freq_src == clk_src_fpid) + val_freq = freq_idx - 1; + else if (freq_src == clk_src_gptc) + val_freq = freq_idx - max_fpid_freq_rank; + + /* set blink rate idx */ + if (freq_src != clk_src_gptc_hs) { + low = get_freq_offset(off, freq_src); + high = low + 2; + val = val_freq << high; + regmap_update_bits(priv->mmap, reg, genmask(high, low), val); + } + + /* select clock source */ + low = get_src_offset(off); + high = low + 2; + val = freq_src << high; + regmap_update_bits(priv->mmap, reg, genmask(high, low), val); +} + +static void sso_led_brightness_set(struct led_classdev *led_cdev, + enum led_brightness brightness) +{ + struct sso_led_priv *priv; + struct sso_led_desc *desc; + struct sso_led *led; + int val; + + led = cdev_to_sso_led_data(led_cdev); + priv = led->priv; + desc = &led->desc; + + desc->brightness = brightness; + regmap_write(priv->mmap, duty_cycle(desc->pin), brightness); + + if (brightness == led_off) + val = 0; + else + val = 1; + + /* hw blink off */ + if (desc->hw_blink && !val && desc->blinking) { + desc->blinking = 0; + regmap_update_bits(priv->mmap, sso_con2, bit(desc->pin), 0); + } else if (desc->hw_blink && val && !desc->blinking) { + desc->blinking = 1; + regmap_update_bits(priv->mmap, sso_con2, bit(desc->pin), + 1 << desc->pin); + } + + if (!desc->hw_trig && led->gpiod) + gpiod_set_value(led->gpiod, val); +} + +static enum led_brightness sso_led_brightness_get(struct led_classdev *led_cdev) +{ + struct sso_led *led = cdev_to_sso_led_data(led_cdev); + + return (enum led_brightness)led->desc.brightness; +} + +static int +delay_to_freq_idx(struct sso_led *led, unsigned long *delay_on, + unsigned long *delay_off) +{ + struct sso_led_priv *priv = led->priv; + unsigned long delay; + int freq_idx; + u32 freq; + + if (!*delay_on && !*delay_off) { + *delay_on = *delay_off = (1000 / priv->freq[0]) / 2; + return 0; + } + + delay = *delay_on + *delay_off; + freq = 1000 / delay; + + freq_idx = sso_get_blink_rate_idx(priv, freq); + if (freq_idx == -1) + freq_idx = max_freq_rank - 1; + + delay = 1000 / priv->freq[freq_idx]; + *delay_on = *delay_off = delay / 2; + + if (!*delay_on) + *delay_on = *delay_off = 1; + + return freq_idx; +} + +static int +sso_led_blink_set(struct led_classdev *led_cdev, unsigned long *delay_on, + unsigned long *delay_off) +{ + struct sso_led_priv *priv; + struct sso_led *led; + int freq_idx; + + led = cdev_to_sso_led_data(led_cdev); + priv = led->priv; + freq_idx = delay_to_freq_idx(led, delay_on, delay_off); + + sso_led_freq_set(priv, led->desc.pin, freq_idx); + regmap_update_bits(priv->mmap, sso_con2, bit(led->desc.pin), + 1 << led->desc.pin); + led->desc.freq_idx = freq_idx; + led->desc.blink_rate = priv->freq[freq_idx]; + led->desc.blinking = 1; + + return 1; +} + +static void sso_led_hw_cfg(struct sso_led_priv *priv, struct sso_led *led) +{ + struct sso_led_desc *desc = &led->desc; + + /* set freq */ + if (desc->hw_blink) { + sso_led_freq_set(priv, desc->pin, desc->freq_idx); + regmap_update_bits(priv->mmap, sso_con2, bit(desc->pin), + 1 << desc->pin); + } + + if (desc->hw_trig) + regmap_update_bits(priv->mmap, sso_con3, bit(desc->pin), + 1 << desc->pin); + + /* set brightness */ + regmap_write(priv->mmap, duty_cycle(desc->pin), desc->brightness); + + /* enable output */ + if (!desc->hw_trig && desc->brightness) + gpiod_set_value(led->gpiod, 1); +} + +static int sso_create_led(struct sso_led_priv *priv, struct sso_led *led, + struct fwnode_handle *child) +{ + struct sso_led_desc *desc = &led->desc; + struct led_init_data init_data; + int err; + + init_data.fwnode = child; + init_data.devicename = sso_dev_name; + init_data.default_label = ":"; + + led->cdev.default_trigger = desc->default_trigger; + led->cdev.brightness_set = sso_led_brightness_set; + led->cdev.brightness_get = sso_led_brightness_get; + led->cdev.brightness = desc->brightness; + led->cdev.max_brightness = led_full; + + if (desc->retain_state_shutdown) + led->cdev.flags |= led_retain_at_shutdown; + if (desc->retain_state_suspended) + led->cdev.flags |= led_core_suspendresume; + if (desc->panic_indicator) + led->cdev.flags |= led_panic_indicator; + + if (desc->hw_blink) + led->cdev.blink_set = sso_led_blink_set; + + sso_led_hw_cfg(priv, led); + + err = devm_led_classdev_register_ext(priv->dev, &led->cdev, &init_data); + if (err) + return err; + + list_add(&led->list, &priv->led_list); + + return 0; +} + +static void sso_init_freq(struct sso_led_priv *priv) +{ + int i; + + priv->freq[0] = 0; + for (i = 1; i < max_freq_rank; i++) { + if (i < max_fpid_freq_rank) { + priv->freq[i] = priv->fpid_clkrate / freq_div_tbl[i - 1]; + } else if (i < max_gptc_freq_rank) { + priv->freq[i] = priv->gptc_clkrate / + freq_div_tbl[i - max_fpid_freq_rank]; + } else if (i < max_gptc_hs_freq_rank) { + priv->freq[i] = priv->gptc_clkrate; + } + } +} + +static int sso_gpio_request(struct gpio_chip *chip, unsigned int offset) +{ + struct sso_led_priv *priv = gpiochip_get_data(chip); + + if (priv->gpio.alloc_bitmap & bit(offset)) + return -einval; + + priv->gpio.alloc_bitmap |= bit(offset); + regmap_write(priv->mmap, duty_cycle(offset), 0xff); + + return 0; +} + +static void sso_gpio_free(struct gpio_chip *chip, unsigned int offset) +{ + struct sso_led_priv *priv = gpiochip_get_data(chip); + + priv->gpio.alloc_bitmap &= ~bit(offset); + regmap_write(priv->mmap, duty_cycle(offset), 0x0); +} + +static int sso_gpio_get_dir(struct gpio_chip *chip, unsigned int offset) +{ + return gpiof_dir_out; +} + +static int +sso_gpio_dir_out(struct gpio_chip *chip, unsigned int offset, int value) +{ + struct sso_led_priv *priv = gpiochip_get_data(chip); + bool bit = !!value; + + regmap_update_bits(priv->mmap, sso_cpu, bit(offset), bit << offset); + if (!priv->gpio.freq) + regmap_update_bits(priv->mmap, sso_con0, sso_con0_swu, + sso_con0_swu); + + return 0; +} + +static int sso_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct sso_led_priv *priv = gpiochip_get_data(chip); + u32 reg_val; + + regmap_read(priv->mmap, sso_cpu, ®_val); + + return !!(reg_val & bit(offset)); +} + +static void sso_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + struct sso_led_priv *priv = gpiochip_get_data(chip); + + regmap_update_bits(priv->mmap, sso_cpu, bit(offset), value << offset); + if (!priv->gpio.freq) + regmap_update_bits(priv->mmap, sso_con0, sso_con0_swu, + sso_con0_swu); +} + +static int sso_gpio_gc_init(struct device *dev, struct sso_led_priv *priv) +{ + struct gpio_chip *gc = &priv->gpio.chip; + + gc->request = sso_gpio_request; + gc->free = sso_gpio_free; + gc->get_direction = sso_gpio_get_dir; + gc->direction_output = sso_gpio_dir_out; + gc->get = sso_gpio_get; + gc->set = sso_gpio_set; + + gc->label = "lgm-sso"; + gc->base = -1; + /* to exclude pins from control, use "gpio-reserved-ranges" */ + gc->ngpio = priv->gpio.pins; + gc->parent = dev; + gc->owner = this_module; + gc->of_node = dev->of_node; + + return devm_gpiochip_add_data(dev, gc, priv); +} + +static int sso_gpio_get_freq_idx(int freq) +{ + int idx; + + for (idx = 0; idx < array_size(freq_tbl); idx++) { + if (freq <= freq_tbl[idx]) + return idx; + } + + return -1; +} + +static void sso_register_shift_clk(struct sso_led_priv *priv) +{ + int idx, size = array_size(shift_clk_freq_tbl); + u32 val = 0; + + for (idx = 0; idx < size; idx++) { + if (shift_clk_freq_tbl[idx] <= priv->gpio.shift_clk_freq) { + val = idx; + break; + } + } + + if (idx == size) + dev_warn(priv->dev, "%s: invalid freq %d ", + __func__, priv->gpio.shift_clk_freq); + + regmap_update_bits(priv->mmap, sso_con1, sso_con1_fcdsc, + field_prep(sso_con1_fcdsc, val)); +} + +static int sso_gpio_freq_set(struct sso_led_priv *priv) +{ + int freq_idx; + u32 val; + + freq_idx = sso_gpio_get_freq_idx(priv->gpio.freq); + if (freq_idx == -1) + freq_idx = array_size(freq_tbl) - 1; + + val = freq_idx % fpid_freq_rank_max; + + if (!priv->gpio.freq) { + regmap_update_bits(priv->mmap, sso_con0, sso_con0_blink_r, 0); + regmap_update_bits(priv->mmap, sso_con1, sso_con1_us, + field_prep(sso_con1_us, us_sw)); + } else if (freq_idx < fpid_freq_rank_max) { + regmap_update_bits(priv->mmap, sso_con0, sso_con0_blink_r, + sso_con0_blink_r); + regmap_update_bits(priv->mmap, sso_con1, sso_con1_us, + field_prep(sso_con1_us, us_fpid)); + regmap_update_bits(priv->mmap, sso_con1, sso_con1_fpid, + field_prep(sso_con1_fpid, val)); + } else { + regmap_update_bits(priv->mmap, sso_con0, sso_con0_blink_r, + sso_con0_blink_r); + regmap_update_bits(priv->mmap, sso_con1, sso_con1_us, + field_prep(sso_con1_us, us_gptc)); + regmap_update_bits(priv->mmap, sso_con1, sso_con1_gptd, + field_prep(sso_con1_gptd, val)); + } + + return 0; +} + +static int sso_gpio_hw_init(struct sso_led_priv *priv) +{ + u32 activate; + int i, err; + + /* clear all duty cycles */ + for (i = 0; i < priv->gpio.pins; i++) { + err = regmap_write(priv->mmap, duty_cycle(i), 0); + if (err) + return err; + } + + /* 4 groups for total 32 pins */ + for (i = 1; i <= max_group_num; i++) { + activate = !!(i * pins_per_group <= priv->gpio.pins || + priv->gpio.pins > (i - 1) * pins_per_group); + err = regmap_update_bits(priv->mmap, sso_con1, bit(i - 1), + activate << (i - 1)); + if (err) + return err; + } + + /* no hw directly controlled pin by default */ + err = regmap_write(priv->mmap, sso_con3, 0); + if (err) + return err; + + /* no blink for all pins */ + err = regmap_write(priv->mmap, sso_con2, 0); + if (err) + return err; + + /* output 0 by default */ + err = regmap_write(priv->mmap, sso_cpu, 0); + if (err) + return err; + + /* update edge */ + err = regmap_update_bits(priv->mmap, sso_con0, sso_con0_rzfl, + field_prep(sso_con0_rzfl, priv->gpio.edge)); + if (err) + return err; + + /* set gpio update rate */ + sso_gpio_freq_set(priv); + + /* register shift clock */ + sso_register_shift_clk(priv); + + return 0; +} + +static void sso_led_shutdown(struct sso_led *led) +{ + struct sso_led_priv *priv = led->priv; + + /* unregister led */ + devm_led_classdev_unregister(priv->dev, &led->cdev); + + /* clear hw control bit */ + if (led->desc.hw_trig) + regmap_update_bits(priv->mmap, sso_con3, bit(led->desc.pin), 0); + + if (led->gpiod) + devm_gpiod_put(priv->dev, led->gpiod); + + led->priv = null; +} + +static int +__sso_led_dt_parse(struct sso_led_priv *priv, struct fwnode_handle *fw_ssoled) +{ + struct fwnode_handle *fwnode_child; + struct device *dev = priv->dev; + struct sso_led_desc *desc; + struct sso_led *led; + struct list_head *p; + const char *tmp; + u32 prop; + int ret; + + fwnode_for_each_child_node(fw_ssoled, fwnode_child) { + led = devm_kzalloc(dev, sizeof(*led), gfp_kernel); + if (!led) + return -enomem; + + init_list_head(&led->list); + led->priv = priv; + desc = &led->desc; + + led->gpiod = devm_fwnode_get_gpiod_from_child(dev, null, + fwnode_child, + gpiod_asis, null); + if (is_err(led->gpiod)) { + dev_err(dev, "led: get gpio fail! "); + goto __dt_err; + } + + fwnode_property_read_string(fwnode_child, + "linux,default-trigger", + &desc->default_trigger); + + if (fwnode_property_present(fwnode_child, + "retain-state-suspended")) + desc->retain_state_suspended = 1; + + if (fwnode_property_present(fwnode_child, + "retain-state-shutdown")) + desc->retain_state_shutdown = 1; + + if (fwnode_property_present(fwnode_child, "panic-indicator")) + desc->panic_indicator = 1; + + ret = fwnode_property_read_u32(fwnode_child, "reg", &prop); + if (ret != 0 || prop >= sso_led_max_num) { + dev_err(dev, "invalid led pin:%u ", prop); + goto __dt_err; + } + desc->pin = prop; + + if (fwnode_property_present(fwnode_child, "intel,sso-hw-blink")) + desc->hw_blink = 1; + + desc->hw_trig = fwnode_property_read_bool(fwnode_child, + "intel,sso-hw-trigger"); + if (desc->hw_trig) { + desc->default_trigger = null; + desc->retain_state_shutdown = 0; + desc->retain_state_suspended = 0; + desc->panic_indicator = 0; + desc->hw_blink = 0; + } + + if (fwnode_property_read_u32(fwnode_child, + "intel,sso-blink-rate-hz", &prop)) { + /* default first freq rate */ + desc->freq_idx = 0; + desc->blink_rate = priv->freq[desc->freq_idx]; + } else { + desc->freq_idx = sso_get_blink_rate_idx(priv, prop); + if (desc->freq_idx == -1) + desc->freq_idx = max_freq_rank - 1; + + desc->blink_rate = priv->freq[desc->freq_idx]; + } + + if (!fwnode_property_read_string(fwnode_child, "default-state", &tmp)) { + if (!strcmp(tmp, "on")) + desc->brightness = led_full; + } + + if (sso_create_led(priv, led, fwnode_child)) + goto __dt_err; + } + fwnode_handle_put(fw_ssoled); + + return 0; +__dt_err: + fwnode_handle_put(fw_ssoled); + /* unregister leds */ + list_for_each(p, &priv->led_list) { + led = list_entry(p, struct sso_led, list); + sso_led_shutdown(led); + } + + return -einval; +} + +static int sso_led_dt_parse(struct sso_led_priv *priv) +{ + struct fwnode_handle *fwnode = dev_fwnode(priv->dev); + struct fwnode_handle *fw_ssoled; + struct device *dev = priv->dev; + int count; + int ret; + + count = device_get_child_node_count(dev); + if (!count) + return 0; + + fw_ssoled = fwnode_get_named_child_node(fwnode, "ssoled"); + if (fw_ssoled) { + ret = __sso_led_dt_parse(priv, fw_ssoled); + if (ret) + return ret; + } + + return 0; +} + +static int sso_probe_gpios(struct sso_led_priv *priv) +{ + struct device *dev = priv->dev; + int ret; + + if (device_property_read_u32(dev, "ngpios", &priv->gpio.pins)) + priv->gpio.pins = max_pin_num_per_bank; + + if (priv->gpio.pins > max_pin_num_per_bank) + return -einval; + + if (device_property_read_u32(dev, "intel,sso-update-rate-hz", + &priv->gpio.freq)) + priv->gpio.freq = 0; + + priv->gpio.edge = data_clk_edge; + priv->gpio.shift_clk_freq = -1; + + ret = sso_gpio_hw_init(priv); + if (ret) + return ret; + + return sso_gpio_gc_init(dev, priv); +} + +static void sso_clk_disable(void *data) +{ + struct sso_led_priv *priv = data; + + clk_disable_unprepare(priv->fpid_clk); + clk_disable_unprepare(priv->gclk); +} + +static int intel_sso_led_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct sso_led_priv *priv; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), gfp_kernel); + if (!priv) + return -enomem; + + priv->pdev = pdev; + priv->dev = dev; + + /* gate clock */ + priv->gclk = devm_clk_get(dev, "sso"); + if (is_err(priv->gclk)) { + dev_err(dev, "get sso gate clock failed! "); + return ptr_err(priv->gclk); + } + + ret = clk_prepare_enable(priv->gclk); + if (ret) { + dev_err(dev, "failed to prepate/enable sso gate clock! "); + return ret; + } + + priv->fpid_clk = devm_clk_get(dev, "fpid"); + if (is_err(priv->fpid_clk)) { + dev_err(dev, "failed to get fpid clock! "); + return ptr_err(priv->fpid_clk); + } + + ret = clk_prepare_enable(priv->fpid_clk); + if (ret) { + dev_err(dev, "failed to prepare/enable fpid clock! "); + return ret; + } + priv->fpid_clkrate = clk_get_rate(priv->fpid_clk); + + ret = devm_add_action_or_reset(dev, sso_clk_disable, priv); + if (ret) { + dev_err(dev, "failed to devm_add_action_or_reset, %d ", ret); + return ret; + } + + priv->mmap = syscon_node_to_regmap(dev->of_node); + if (is_err(priv->mmap)) { + dev_err(dev, "failed to map iomem! "); + return ptr_err(priv->mmap); + } + + ret = sso_probe_gpios(priv); + if (ret) { + regmap_exit(priv->mmap); + return ret; + } + + init_list_head(&priv->led_list); + + platform_set_drvdata(pdev, priv); + sso_init_freq(priv); + + priv->gptc_clkrate = def_gptc_clk_rate; + + ret = sso_led_dt_parse(priv); + if (ret) { + regmap_exit(priv->mmap); + return ret; + } + dev_info(priv->dev, "sso led init success! "); + + return 0; +} + +static int intel_sso_led_remove(struct platform_device *pdev) +{ + struct sso_led_priv *priv; + struct list_head *pos, *n; + struct sso_led *led; + + priv = platform_get_drvdata(pdev); + + list_for_each_safe(pos, n, &priv->led_list) { + list_del(pos); + led = list_entry(pos, struct sso_led, list); + sso_led_shutdown(led); + } + + clk_disable_unprepare(priv->fpid_clk); + clk_disable_unprepare(priv->gclk); + regmap_exit(priv->mmap); + + return 0; +} + +static const struct of_device_id of_sso_led_match[] = { + { .compatible = "intel,lgm-ssoled" }, + {} +}; + +module_device_table(of, of_sso_led_match); + +static struct platform_driver intel_sso_led_driver = { + .probe = intel_sso_led_probe, + .remove = intel_sso_led_remove, + .driver = { + .name = "lgm-ssoled", + .of_match_table = of_match_ptr(of_sso_led_match), + }, +}; + +module_platform_driver(intel_sso_led_driver); + +module_description("intel sso led/gpio driver"); +module_license("gpl v2");
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Leds
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c3987cd2bca34ddfec69027acedb2fae5ffcf7a0
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amireddy mallikarjuna reddy
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drivers
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leds
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blink
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leds: trigger: implement a tty trigger
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usage is as follows:
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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implement a tty trigger
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
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['trigger']
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['sysfs-class-led-trigger-tty', 'kconfig', 'c', 'makefile']
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| 0
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--- diff --git a/documentation/abi/testing/sysfs-class-led-trigger-tty b/documentation/abi/testing/sysfs-class-led-trigger-tty --- /dev/null +++ b/documentation/abi/testing/sysfs-class-led-trigger-tty +what: /sys/class/leds/<led>/ttyname +date: dec 2020 +kernelversion: 5.10 +contact: linux-leds@vger.kernel.org +description: + specifies the tty device name of the triggering tty diff --git a/drivers/leds/trigger/kconfig b/drivers/leds/trigger/kconfig --- a/drivers/leds/trigger/kconfig +++ b/drivers/leds/trigger/kconfig +config leds_trigger_tty + tristate "led trigger for tty devices" + depends on tty + help + this allows leds to be controlled by activity on ttys which includes + serial devices like /dev/ttys0. + + when build as a module this driver will be called ledtrig-tty. + diff --git a/drivers/leds/trigger/makefile b/drivers/leds/trigger/makefile --- a/drivers/leds/trigger/makefile +++ b/drivers/leds/trigger/makefile +obj-$(config_leds_trigger_tty) += ledtrig-tty.o diff --git a/drivers/leds/trigger/ledtrig-tty.c b/drivers/leds/trigger/ledtrig-tty.c --- /dev/null +++ b/drivers/leds/trigger/ledtrig-tty.c +// spdx-license-identifier: gpl-2.0 + +#include <linux/delay.h> +#include <linux/leds.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/tty.h> +#include <uapi/linux/serial.h> + +struct ledtrig_tty_data { + struct led_classdev *led_cdev; + struct delayed_work dwork; + struct mutex mutex; + const char *ttyname; + struct tty_struct *tty; + int rx, tx; +}; + +static void ledtrig_tty_restart(struct ledtrig_tty_data *trigger_data) +{ + schedule_delayed_work(&trigger_data->dwork, 0); +} + +static ssize_t ttyname_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ledtrig_tty_data *trigger_data = led_trigger_get_drvdata(dev); + ssize_t len = 0; + + mutex_lock(&trigger_data->mutex); + + if (trigger_data->ttyname) + len = sprintf(buf, "%s ", trigger_data->ttyname); + + mutex_unlock(&trigger_data->mutex); + + return len; +} + +static ssize_t ttyname_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t size) +{ + struct ledtrig_tty_data *trigger_data = led_trigger_get_drvdata(dev); + char *ttyname; + ssize_t ret = size; + bool running; + + if (size > 0 && buf[size - 1] == ' ') + size -= 1; + + if (size) { + ttyname = kmemdup_nul(buf, size, gfp_kernel); + if (!ttyname) { + ret = -enomem; + goto out_unlock; + } + } else { + ttyname = null; + } + + mutex_lock(&trigger_data->mutex); + + running = trigger_data->ttyname != null; + + kfree(trigger_data->ttyname); + tty_kref_put(trigger_data->tty); + trigger_data->tty = null; + + trigger_data->ttyname = ttyname; + +out_unlock: + mutex_unlock(&trigger_data->mutex); + + if (ttyname && !running) + ledtrig_tty_restart(trigger_data); + + return ret; +} +static device_attr_rw(ttyname); + +static void ledtrig_tty_work(struct work_struct *work) +{ + struct ledtrig_tty_data *trigger_data = + container_of(work, struct ledtrig_tty_data, dwork.work); + struct serial_icounter_struct icount; + int ret; + + mutex_lock(&trigger_data->mutex); + + if (!trigger_data->ttyname) { + /* exit without rescheduling */ + mutex_unlock(&trigger_data->mutex); + return; + } + + /* try to get the tty corresponding to $ttyname */ + if (!trigger_data->tty) { + dev_t devno; + struct tty_struct *tty; + int ret; + + ret = tty_dev_name_to_number(trigger_data->ttyname, &devno); + if (ret < 0) + /* + * a device with this name might appear later, so keep + * retrying. + */ + goto out; + + tty = tty_kopen_shared(devno); + if (is_err(tty) || !tty) + /* what to do? retry or abort */ + goto out; + + trigger_data->tty = tty; + } + + ret = tty_get_icount(trigger_data->tty, &icount); + if (ret) { + dev_info(trigger_data->tty->dev, "failed to get icount, stopped polling "); + mutex_unlock(&trigger_data->mutex); + return; + } + + if (icount.rx != trigger_data->rx || + icount.tx != trigger_data->tx) { + led_set_brightness(trigger_data->led_cdev, led_on); + + trigger_data->rx = icount.rx; + trigger_data->tx = icount.tx; + } else { + led_set_brightness(trigger_data->led_cdev, led_off); + } + +out: + mutex_unlock(&trigger_data->mutex); + schedule_delayed_work(&trigger_data->dwork, msecs_to_jiffies(100)); +} + +static struct attribute *ledtrig_tty_attrs[] = { + &dev_attr_ttyname.attr, + null +}; +attribute_groups(ledtrig_tty); + +static int ledtrig_tty_activate(struct led_classdev *led_cdev) +{ + struct ledtrig_tty_data *trigger_data; + + trigger_data = kzalloc(sizeof(*trigger_data), gfp_kernel); + if (!trigger_data) + return -enomem; + + led_set_trigger_data(led_cdev, trigger_data); + + init_delayed_work(&trigger_data->dwork, ledtrig_tty_work); + trigger_data->led_cdev = led_cdev; + mutex_init(&trigger_data->mutex); + + return 0; +} + +static void ledtrig_tty_deactivate(struct led_classdev *led_cdev) +{ + struct ledtrig_tty_data *trigger_data = led_get_trigger_data(led_cdev); + + cancel_delayed_work_sync(&trigger_data->dwork); + + kfree(trigger_data); +} + +static struct led_trigger ledtrig_tty = { + .name = "tty", + .activate = ledtrig_tty_activate, + .deactivate = ledtrig_tty_deactivate, + .groups = ledtrig_tty_groups, +}; +module_led_trigger(ledtrig_tty); + +module_author("uwe kleine-konig <u.kleine-koenig@pengutronix.de>"); +module_description("uart led trigger"); +module_license("gpl v2");
|
Leds
|
fd4a641ac88fbbaf8b90e00823397597a287cfcd
|
uwe kleine k nig
|
drivers
|
leds
|
testing, trigger
|
dmaengine: add intel lgm soc dma support.
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add dma controller driver for lightning mountain (lgm) family of socs.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add intel lgm soc dma support
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['kconfig', 'c', 'makefile']
| 5
| 1,753
| 0
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--- diff --git a/drivers/dma/kconfig b/drivers/dma/kconfig --- a/drivers/dma/kconfig +++ b/drivers/dma/kconfig +source "drivers/dma/lgm/kconfig" + diff --git a/drivers/dma/makefile b/drivers/dma/makefile --- a/drivers/dma/makefile +++ b/drivers/dma/makefile +obj-$(config_intel_ldma) += lgm/ diff --git a/drivers/dma/lgm/kconfig b/drivers/dma/lgm/kconfig --- /dev/null +++ b/drivers/dma/lgm/kconfig +# spdx-license-identifier: gpl-2.0-only +config intel_ldma + bool "lightning mountain centralized dma controllers" + select dma_engine + select dma_virtual_channels + help + enable support for intel lightning mountain soc dma controllers. + these controllers provide dma capabilities for a variety of on-chip + devices such as hsnand and gswip (gigabit switch ip). diff --git a/drivers/dma/lgm/makefile b/drivers/dma/lgm/makefile --- /dev/null +++ b/drivers/dma/lgm/makefile +# spdx-license-identifier: gpl-2.0 +obj-$(config_intel_ldma) += lgm-dma.o diff --git a/drivers/dma/lgm/lgm-dma.c b/drivers/dma/lgm/lgm-dma.c --- /dev/null +++ b/drivers/dma/lgm/lgm-dma.c +// spdx-license-identifier: gpl-2.0 +/* + * lightning mountain centralized dma controller driver + * + * copyright (c) 2016 - 2020 intel corporation. + */ + +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/dma-mapping.h> +#include <linux/dmapool.h> +#include <linux/err.h> +#include <linux/export.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/iopoll.h> +#include <linux/of_dma.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/reset.h> + +#include "../dmaengine.h" +#include "../virt-dma.h" + +#define driver_name "lgm-dma" + +#define dma_id 0x0008 +#define dma_id_rev genmask(7, 0) +#define dma_id_pnr genmask(19, 16) +#define dma_id_chnr genmask(26, 20) +#define dma_id_dw_128b bit(27) +#define dma_id_aw_36b bit(28) +#define dma_ver32 0x32 +#define dma_ver31 0x31 +#define dma_ver22 0x0a + +#define dma_ctrl 0x0010 +#define dma_ctrl_rst bit(0) +#define dma_ctrl_dsram_path bit(1) +#define dma_ctrl_dburst_wr bit(3) +#define dma_ctrl_vld_df_ack bit(4) +#define dma_ctrl_ch_fl bit(6) +#define dma_ctrl_ds_fod bit(7) +#define dma_ctrl_drb bit(8) +#define dma_ctrl_enbe bit(9) +#define dma_ctrl_desc_tmout_cnt_v31 genmask(27, 16) +#define dma_ctrl_desc_tmout_en_v31 bit(30) +#define dma_ctrl_pktarb bit(31) + +#define dma_cpoll 0x0014 +#define dma_cpoll_cnt genmask(15, 4) +#define dma_cpoll_en bit(31) + +#define dma_cs 0x0018 +#define dma_cs_mask genmask(5, 0) + +#define dma_cctrl 0x001c +#define dma_cctrl_on bit(0) +#define dma_cctrl_rst bit(1) +#define dma_cctrl_ch_poll_en bit(2) +#define dma_cctrl_ch_abc bit(3) /* adaptive burst chop */ +#define dma_cdba_msb genmask(7, 4) +#define dma_cctrl_dir_tx bit(8) +#define dma_cctrl_class genmask(11, 9) +#define dma_cctrl_classh genmask(19, 18) +#define dma_cctrl_wr_np_en bit(21) +#define dma_cctrl_pden bit(23) +#define dma_max_class (sz_32 - 1) + +#define dma_cdba 0x0020 +#define dma_cdlen 0x0024 +#define dma_cis 0x0028 +#define dma_cie 0x002c +#define dma_ci_eop bit(1) +#define dma_ci_dur bit(2) +#define dma_ci_descpt bit(3) +#define dma_ci_choff bit(4) +#define dma_ci_rderr bit(5) +#define dma_ci_all \ + (dma_ci_eop | dma_ci_dur | dma_ci_descpt | dma_ci_choff | dma_ci_rderr) + +#define dma_ps 0x0040 +#define dma_pctrl 0x0044 +#define dma_pctrl_rxbl16 bit(0) +#define dma_pctrl_txbl16 bit(1) +#define dma_pctrl_rxbl genmask(3, 2) +#define dma_pctrl_rxbl_8 3 +#define dma_pctrl_txbl genmask(5, 4) +#define dma_pctrl_txbl_8 3 +#define dma_pctrl_pden bit(6) +#define dma_pctrl_rxbl32 bit(7) +#define dma_pctrl_rxendi genmask(9, 8) +#define dma_pctrl_txendi genmask(11, 10) +#define dma_pctrl_txbl32 bit(15) +#define dma_pctrl_mem_flush bit(16) + +#define dma_irnen1 0x00e8 +#define dma_irncr1 0x00ec +#define dma_irnen 0x00f4 +#define dma_irncr 0x00f8 +#define dma_c_dp_tick 0x100 +#define dma_c_dp_tick_tiknarb genmask(15, 0) +#define dma_c_dp_tick_tikarb genmask(31, 16) + +#define dma_c_hdrm 0x110 +/* + * if header mode is set in dma descriptor, + * if bit 30 is disabled, hdr_len must be configured according to channel + * requirement. + * if bit 30 is enabled(checksum with heade mode), hdr_len has no need to + * be configured. it will enable check sum for switch + * if header mode is not set in dma descriptor, + * this register setting doesn't matter + */ +#define dma_c_hdrm_hdr_sum bit(30) + +#define dma_c_boff 0x120 +#define dma_c_boff_bof_len genmask(7, 0) +#define dma_c_boff_en bit(31) + +#define dma_orrc 0x190 +#define dma_orrc_orrcnt genmask(8, 4) +#define dma_orrc_en bit(31) + +#define dma_c_endian 0x200 +#define dma_c_end_dataendi genmask(1, 0) +#define dma_c_end_de_en bit(7) +#define dma_c_end_desendi genmask(9, 8) +#define dma_c_end_des_en bit(16) + +/* dma controller capability */ +#define dma_addr_36bit bit(0) +#define dma_data_128bit bit(1) +#define dma_chan_flow_ctl bit(2) +#define dma_desc_fod bit(3) +#define dma_desc_in_sram bit(4) +#define dma_en_byte_en bit(5) +#define dma_dburst_wr bit(6) +#define dma_valid_desc_fetch_ack bit(7) +#define dma_dft_drb bit(8) + +#define dma_orrc_max_cnt (sz_32 - 1) +#define dma_dft_poll_cnt sz_4 +#define dma_dft_burst_v22 sz_2 +#define dma_burstl_8dw sz_8 +#define dma_burstl_16dw sz_16 +#define dma_burstl_32dw sz_32 +#define dma_dft_burst dma_burstl_16dw +#define dma_max_desc_num (sz_8k - 1) +#define dma_chan_boff_max (sz_256 - 1) +#define dma_dft_endian 0 + +#define dma_dft_desc_tcnt 50 +#define dma_hdr_len_max (sz_16k - 1) + +/* dma flags */ +#define dma_tx_ch bit(0) +#define dma_rx_ch bit(1) +#define device_alloc_desc bit(2) +#define chan_in_use bit(3) +#define dma_hw_desc bit(4) + +/* descriptor fields */ +#define desc_data_len genmask(15, 0) +#define desc_byte_off genmask(25, 23) +#define desc_eop bit(28) +#define desc_sop bit(29) +#define desc_c bit(30) +#define desc_own bit(31) + +#define dma_chan_rst 1 +#define dma_max_size (bit(16) - 1) +#define max_lower_chans 32 +#define mask_lower_chans genmask(4, 0) +#define dma_own 1 +#define high_4_bits genmask(3, 0) +#define dma_dft_desc_num 1 +#define dma_pkt_drop_dis 0 + +enum ldma_chan_on_off { + dma_ch_off = 0, + dma_ch_on = 1, +}; + +enum { + dma_type_tx = 0, + dma_type_rx, + dma_type_mcpy, +}; + +struct ldma_dev; +struct ldma_port; + +struct ldma_chan { + struct virt_dma_chan vchan; + struct ldma_port *port; /* back pointer */ + char name[8]; /* channel name */ + int nr; /* channel id in hardware */ + u32 flags; /* central way or channel based way */ + enum ldma_chan_on_off onoff; + dma_addr_t desc_phys; + void *desc_base; /* virtual address */ + u32 desc_cnt; /* number of descriptors */ + int rst; + u32 hdrm_len; + bool hdrm_csum; + u32 boff_len; + u32 data_endian; + u32 desc_endian; + bool pden; + bool desc_rx_np; + bool data_endian_en; + bool desc_endian_en; + bool abc_en; + bool desc_init; + struct dma_pool *desc_pool; /* descriptors pool */ + u32 desc_num; + struct dw2_desc_sw *ds; + struct work_struct work; + struct dma_slave_config config; +}; + +struct ldma_port { + struct ldma_dev *ldev; /* back pointer */ + u32 portid; + u32 rxbl; + u32 txbl; + u32 rxendi; + u32 txendi; + u32 pkt_drop; +}; + +/* instance specific data */ +struct ldma_inst_data { + bool desc_in_sram; + bool chan_fc; + bool desc_fod; /* fetch on demand */ + bool valid_desc_fetch_ack; + u32 orrc; /* outstanding read count */ + const char *name; + u32 type; +}; + +struct ldma_dev { + struct device *dev; + void __iomem *base; + struct reset_control *rst; + struct clk *core_clk; + struct dma_device dma_dev; + u32 ver; + int irq; + struct ldma_port *ports; + struct ldma_chan *chans; /* channel list on this dma or port */ + spinlock_t dev_lock; /* controller register exclusive */ + u32 chan_nrs; + u32 port_nrs; + u32 channels_mask; + u32 flags; + u32 pollcnt; + const struct ldma_inst_data *inst; + struct workqueue_struct *wq; +}; + +struct dw2_desc { + u32 field; + u32 addr; +} __packed __aligned(8); + +struct dw2_desc_sw { + struct virt_dma_desc vdesc; + struct ldma_chan *chan; + dma_addr_t desc_phys; + size_t desc_cnt; + size_t size; + struct dw2_desc *desc_hw; +}; + +static inline void +ldma_update_bits(struct ldma_dev *d, u32 mask, u32 val, u32 ofs) +{ + u32 old_val, new_val; + + old_val = readl(d->base + ofs); + new_val = (old_val & ~mask) | (val & mask); + + if (new_val != old_val) + writel(new_val, d->base + ofs); +} + +static inline struct ldma_chan *to_ldma_chan(struct dma_chan *chan) +{ + return container_of(chan, struct ldma_chan, vchan.chan); +} + +static inline struct ldma_dev *to_ldma_dev(struct dma_device *dma_dev) +{ + return container_of(dma_dev, struct ldma_dev, dma_dev); +} + +static inline struct dw2_desc_sw *to_lgm_dma_desc(struct virt_dma_desc *vdesc) +{ + return container_of(vdesc, struct dw2_desc_sw, vdesc); +} + +static inline bool ldma_chan_tx(struct ldma_chan *c) +{ + return !!(c->flags & dma_tx_ch); +} + +static inline bool ldma_chan_is_hw_desc(struct ldma_chan *c) +{ + return !!(c->flags & dma_hw_desc); +} + +static void ldma_dev_reset(struct ldma_dev *d) + +{ + unsigned long flags; + + spin_lock_irqsave(&d->dev_lock, flags); + ldma_update_bits(d, dma_ctrl_rst, dma_ctrl_rst, dma_ctrl); + spin_unlock_irqrestore(&d->dev_lock, flags); +} + +static void ldma_dev_pkt_arb_cfg(struct ldma_dev *d, bool enable) +{ + unsigned long flags; + u32 mask = dma_ctrl_pktarb; + u32 val = enable ? dma_ctrl_pktarb : 0; + + spin_lock_irqsave(&d->dev_lock, flags); + ldma_update_bits(d, mask, val, dma_ctrl); + spin_unlock_irqrestore(&d->dev_lock, flags); +} + +static void ldma_dev_sram_desc_cfg(struct ldma_dev *d, bool enable) +{ + unsigned long flags; + u32 mask = dma_ctrl_dsram_path; + u32 val = enable ? dma_ctrl_dsram_path : 0; + + spin_lock_irqsave(&d->dev_lock, flags); + ldma_update_bits(d, mask, val, dma_ctrl); + spin_unlock_irqrestore(&d->dev_lock, flags); +} + +static void ldma_dev_chan_flow_ctl_cfg(struct ldma_dev *d, bool enable) +{ + unsigned long flags; + u32 mask, val; + + if (d->inst->type != dma_type_tx) + return; + + mask = dma_ctrl_ch_fl; + val = enable ? dma_ctrl_ch_fl : 0; + + spin_lock_irqsave(&d->dev_lock, flags); + ldma_update_bits(d, mask, val, dma_ctrl); + spin_unlock_irqrestore(&d->dev_lock, flags); +} + +static void ldma_dev_global_polling_enable(struct ldma_dev *d) +{ + unsigned long flags; + u32 mask = dma_cpoll_en | dma_cpoll_cnt; + u32 val = dma_cpoll_en; + + val |= field_prep(dma_cpoll_cnt, d->pollcnt); + + spin_lock_irqsave(&d->dev_lock, flags); + ldma_update_bits(d, mask, val, dma_cpoll); + spin_unlock_irqrestore(&d->dev_lock, flags); +} + +static void ldma_dev_desc_fetch_on_demand_cfg(struct ldma_dev *d, bool enable) +{ + unsigned long flags; + u32 mask, val; + + if (d->inst->type == dma_type_mcpy) + return; + + mask = dma_ctrl_ds_fod; + val = enable ? dma_ctrl_ds_fod : 0; + + spin_lock_irqsave(&d->dev_lock, flags); + ldma_update_bits(d, mask, val, dma_ctrl); + spin_unlock_irqrestore(&d->dev_lock, flags); +} + +static void ldma_dev_byte_enable_cfg(struct ldma_dev *d, bool enable) +{ + unsigned long flags; + u32 mask = dma_ctrl_enbe; + u32 val = enable ? dma_ctrl_enbe : 0; + + spin_lock_irqsave(&d->dev_lock, flags); + ldma_update_bits(d, mask, val, dma_ctrl); + spin_unlock_irqrestore(&d->dev_lock, flags); +} + +static void ldma_dev_orrc_cfg(struct ldma_dev *d) +{ + unsigned long flags; + u32 val = 0; + u32 mask; + + if (d->inst->type == dma_type_rx) + return; + + mask = dma_orrc_en | dma_orrc_orrcnt; + if (d->inst->orrc > 0 && d->inst->orrc <= dma_orrc_max_cnt) + val = dma_orrc_en | field_prep(dma_orrc_orrcnt, d->inst->orrc); + + spin_lock_irqsave(&d->dev_lock, flags); + ldma_update_bits(d, mask, val, dma_orrc); + spin_unlock_irqrestore(&d->dev_lock, flags); +} + +static void ldma_dev_df_tout_cfg(struct ldma_dev *d, bool enable, int tcnt) +{ + u32 mask = dma_ctrl_desc_tmout_cnt_v31; + unsigned long flags; + u32 val; + + if (enable) + val = dma_ctrl_desc_tmout_en_v31 | field_prep(dma_ctrl_desc_tmout_cnt_v31, tcnt); + else + val = 0; + + spin_lock_irqsave(&d->dev_lock, flags); + ldma_update_bits(d, mask, val, dma_ctrl); + spin_unlock_irqrestore(&d->dev_lock, flags); +} + +static void ldma_dev_dburst_wr_cfg(struct ldma_dev *d, bool enable) +{ + unsigned long flags; + u32 mask, val; + + if (d->inst->type != dma_type_rx && d->inst->type != dma_type_mcpy) + return; + + mask = dma_ctrl_dburst_wr; + val = enable ? dma_ctrl_dburst_wr : 0; + + spin_lock_irqsave(&d->dev_lock, flags); + ldma_update_bits(d, mask, val, dma_ctrl); + spin_unlock_irqrestore(&d->dev_lock, flags); +} + +static void ldma_dev_vld_fetch_ack_cfg(struct ldma_dev *d, bool enable) +{ + unsigned long flags; + u32 mask, val; + + if (d->inst->type != dma_type_tx) + return; + + mask = dma_ctrl_vld_df_ack; + val = enable ? dma_ctrl_vld_df_ack : 0; + + spin_lock_irqsave(&d->dev_lock, flags); + ldma_update_bits(d, mask, val, dma_ctrl); + spin_unlock_irqrestore(&d->dev_lock, flags); +} + +static void ldma_dev_drb_cfg(struct ldma_dev *d, int enable) +{ + unsigned long flags; + u32 mask = dma_ctrl_drb; + u32 val = enable ? dma_ctrl_drb : 0; + + spin_lock_irqsave(&d->dev_lock, flags); + ldma_update_bits(d, mask, val, dma_ctrl); + spin_unlock_irqrestore(&d->dev_lock, flags); +} + +static int ldma_dev_cfg(struct ldma_dev *d) +{ + bool enable; + + ldma_dev_pkt_arb_cfg(d, true); + ldma_dev_global_polling_enable(d); + + enable = !!(d->flags & dma_dft_drb); + ldma_dev_drb_cfg(d, enable); + + enable = !!(d->flags & dma_en_byte_en); + ldma_dev_byte_enable_cfg(d, enable); + + enable = !!(d->flags & dma_chan_flow_ctl); + ldma_dev_chan_flow_ctl_cfg(d, enable); + + enable = !!(d->flags & dma_desc_fod); + ldma_dev_desc_fetch_on_demand_cfg(d, enable); + + enable = !!(d->flags & dma_desc_in_sram); + ldma_dev_sram_desc_cfg(d, enable); + + enable = !!(d->flags & dma_dburst_wr); + ldma_dev_dburst_wr_cfg(d, enable); + + enable = !!(d->flags & dma_valid_desc_fetch_ack); + ldma_dev_vld_fetch_ack_cfg(d, enable); + + if (d->ver > dma_ver22) { + ldma_dev_orrc_cfg(d); + ldma_dev_df_tout_cfg(d, true, dma_dft_desc_tcnt); + } + + dev_dbg(d->dev, "%s controller 0x%08x configuration done ", + d->inst->name, readl(d->base + dma_ctrl)); + + return 0; +} + +static int ldma_chan_cctrl_cfg(struct ldma_chan *c, u32 val) +{ + struct ldma_dev *d = to_ldma_dev(c->vchan.chan.device); + u32 class_low, class_high; + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&d->dev_lock, flags); + ldma_update_bits(d, dma_cs_mask, c->nr, dma_cs); + reg = readl(d->base + dma_cctrl); + /* read from hardware */ + if (reg & dma_cctrl_dir_tx) + c->flags |= dma_tx_ch; + else + c->flags |= dma_rx_ch; + + /* keep the class value unchanged */ + class_low = field_get(dma_cctrl_class, reg); + class_high = field_get(dma_cctrl_classh, reg); + val &= ~dma_cctrl_class; + val |= field_prep(dma_cctrl_class, class_low); + val &= ~dma_cctrl_classh; + val |= field_prep(dma_cctrl_classh, class_high); + writel(val, d->base + dma_cctrl); + spin_unlock_irqrestore(&d->dev_lock, flags); + + return 0; +} + +static void ldma_chan_irq_init(struct ldma_chan *c) +{ + struct ldma_dev *d = to_ldma_dev(c->vchan.chan.device); + unsigned long flags; + u32 enofs, crofs; + u32 cn_bit; + + if (c->nr < max_lower_chans) { + enofs = dma_irnen; + crofs = dma_irncr; + } else { + enofs = dma_irnen1; + crofs = dma_irncr1; + } + + cn_bit = bit(c->nr & mask_lower_chans); + spin_lock_irqsave(&d->dev_lock, flags); + ldma_update_bits(d, dma_cs_mask, c->nr, dma_cs); + + /* clear all interrupts and disabled it */ + writel(0, d->base + dma_cie); + writel(dma_ci_all, d->base + dma_cis); + + ldma_update_bits(d, cn_bit, 0, enofs); + writel(cn_bit, d->base + crofs); + spin_unlock_irqrestore(&d->dev_lock, flags); +} + +static void ldma_chan_set_class(struct ldma_chan *c, u32 val) +{ + struct ldma_dev *d = to_ldma_dev(c->vchan.chan.device); + u32 class_val; + + if (d->inst->type == dma_type_mcpy || val > dma_max_class) + return; + + /* 3 bits low */ + class_val = field_prep(dma_cctrl_class, val & 0x7); + /* 2 bits high */ + class_val |= field_prep(dma_cctrl_classh, (val >> 3) & 0x3); + + ldma_update_bits(d, dma_cs_mask, c->nr, dma_cs); + ldma_update_bits(d, dma_cctrl_class | dma_cctrl_classh, class_val, + dma_cctrl); +} + +static int ldma_chan_on(struct ldma_chan *c) +{ + struct ldma_dev *d = to_ldma_dev(c->vchan.chan.device); + unsigned long flags; + + /* if descriptors not configured, not allow to turn on channel */ + if (warn_on(!c->desc_init)) + return -einval; + + spin_lock_irqsave(&d->dev_lock, flags); + ldma_update_bits(d, dma_cs_mask, c->nr, dma_cs); + ldma_update_bits(d, dma_cctrl_on, dma_cctrl_on, dma_cctrl); + spin_unlock_irqrestore(&d->dev_lock, flags); + + c->onoff = dma_ch_on; + + return 0; +} + +static int ldma_chan_off(struct ldma_chan *c) +{ + struct ldma_dev *d = to_ldma_dev(c->vchan.chan.device); + unsigned long flags; + u32 val; + int ret; + + spin_lock_irqsave(&d->dev_lock, flags); + ldma_update_bits(d, dma_cs_mask, c->nr, dma_cs); + ldma_update_bits(d, dma_cctrl_on, 0, dma_cctrl); + spin_unlock_irqrestore(&d->dev_lock, flags); + + ret = readl_poll_timeout_atomic(d->base + dma_cctrl, val, + !(val & dma_cctrl_on), 0, 10000); + if (ret) + return ret; + + c->onoff = dma_ch_off; + + return 0; +} + +static void ldma_chan_desc_hw_cfg(struct ldma_chan *c, dma_addr_t desc_base, + int desc_num) +{ + struct ldma_dev *d = to_ldma_dev(c->vchan.chan.device); + unsigned long flags; + + spin_lock_irqsave(&d->dev_lock, flags); + ldma_update_bits(d, dma_cs_mask, c->nr, dma_cs); + writel(lower_32_bits(desc_base), d->base + dma_cdba); + + /* higher 4 bits of 36 bit addressing */ + if (is_enabled(config_64bit)) { + u32 hi = upper_32_bits(desc_base) & high_4_bits; + + ldma_update_bits(d, dma_cdba_msb, + field_prep(dma_cdba_msb, hi), dma_cctrl); + } + writel(desc_num, d->base + dma_cdlen); + spin_unlock_irqrestore(&d->dev_lock, flags); + + c->desc_init = true; +} + +static struct dma_async_tx_descriptor * +ldma_chan_desc_cfg(struct dma_chan *chan, dma_addr_t desc_base, int desc_num) +{ + struct ldma_chan *c = to_ldma_chan(chan); + struct ldma_dev *d = to_ldma_dev(c->vchan.chan.device); + struct dma_async_tx_descriptor *tx; + struct dw2_desc_sw *ds; + + if (!desc_num) { + dev_err(d->dev, "channel %d must allocate descriptor first ", + c->nr); + return null; + } + + if (desc_num > dma_max_desc_num) { + dev_err(d->dev, "channel %d descriptor number out of range %d ", + c->nr, desc_num); + return null; + } + + ldma_chan_desc_hw_cfg(c, desc_base, desc_num); + + c->flags |= dma_hw_desc; + c->desc_cnt = desc_num; + c->desc_phys = desc_base; + + ds = kzalloc(sizeof(*ds), gfp_nowait); + if (!ds) + return null; + + tx = &ds->vdesc.tx; + dma_async_tx_descriptor_init(tx, chan); + + return tx; +} + +static int ldma_chan_reset(struct ldma_chan *c) +{ + struct ldma_dev *d = to_ldma_dev(c->vchan.chan.device); + unsigned long flags; + u32 val; + int ret; + + ret = ldma_chan_off(c); + if (ret) + return ret; + + spin_lock_irqsave(&d->dev_lock, flags); + ldma_update_bits(d, dma_cs_mask, c->nr, dma_cs); + ldma_update_bits(d, dma_cctrl_rst, dma_cctrl_rst, dma_cctrl); + spin_unlock_irqrestore(&d->dev_lock, flags); + + ret = readl_poll_timeout_atomic(d->base + dma_cctrl, val, + !(val & dma_cctrl_rst), 0, 10000); + if (ret) + return ret; + + c->rst = 1; + c->desc_init = false; + + return 0; +} + +static void ldma_chan_byte_offset_cfg(struct ldma_chan *c, u32 boff_len) +{ + struct ldma_dev *d = to_ldma_dev(c->vchan.chan.device); + u32 mask = dma_c_boff_en | dma_c_boff_bof_len; + u32 val; + + if (boff_len > 0 && boff_len <= dma_chan_boff_max) + val = field_prep(dma_c_boff_bof_len, boff_len) | dma_c_boff_en; + else + val = 0; + + ldma_update_bits(d, dma_cs_mask, c->nr, dma_cs); + ldma_update_bits(d, mask, val, dma_c_boff); +} + +static void ldma_chan_data_endian_cfg(struct ldma_chan *c, bool enable, + u32 endian_type) +{ + struct ldma_dev *d = to_ldma_dev(c->vchan.chan.device); + u32 mask = dma_c_end_de_en | dma_c_end_dataendi; + u32 val; + + if (enable) + val = dma_c_end_de_en | field_prep(dma_c_end_dataendi, endian_type); + else + val = 0; + + ldma_update_bits(d, dma_cs_mask, c->nr, dma_cs); + ldma_update_bits(d, mask, val, dma_c_endian); +} + +static void ldma_chan_desc_endian_cfg(struct ldma_chan *c, bool enable, + u32 endian_type) +{ + struct ldma_dev *d = to_ldma_dev(c->vchan.chan.device); + u32 mask = dma_c_end_des_en | dma_c_end_desendi; + u32 val; + + if (enable) + val = dma_c_end_des_en | field_prep(dma_c_end_desendi, endian_type); + else + val = 0; + + ldma_update_bits(d, dma_cs_mask, c->nr, dma_cs); + ldma_update_bits(d, mask, val, dma_c_endian); +} + +static void ldma_chan_hdr_mode_cfg(struct ldma_chan *c, u32 hdr_len, bool csum) +{ + struct ldma_dev *d = to_ldma_dev(c->vchan.chan.device); + u32 mask, val; + + /* nb, csum disabled, hdr length must be provided */ + if (!csum && (!hdr_len || hdr_len > dma_hdr_len_max)) + return; + + mask = dma_c_hdrm_hdr_sum; + val = dma_c_hdrm_hdr_sum; + + if (!csum && hdr_len) + val = hdr_len; + + ldma_update_bits(d, dma_cs_mask, c->nr, dma_cs); + ldma_update_bits(d, mask, val, dma_c_hdrm); +} + +static void ldma_chan_rxwr_np_cfg(struct ldma_chan *c, bool enable) +{ + struct ldma_dev *d = to_ldma_dev(c->vchan.chan.device); + u32 mask, val; + + /* only valid for rx channel */ + if (ldma_chan_tx(c)) + return; + + mask = dma_cctrl_wr_np_en; + val = enable ? dma_cctrl_wr_np_en : 0; + + ldma_update_bits(d, dma_cs_mask, c->nr, dma_cs); + ldma_update_bits(d, mask, val, dma_cctrl); +} + +static void ldma_chan_abc_cfg(struct ldma_chan *c, bool enable) +{ + struct ldma_dev *d = to_ldma_dev(c->vchan.chan.device); + u32 mask, val; + + if (d->ver < dma_ver32 || ldma_chan_tx(c)) + return; + + mask = dma_cctrl_ch_abc; + val = enable ? dma_cctrl_ch_abc : 0; + + ldma_update_bits(d, dma_cs_mask, c->nr, dma_cs); + ldma_update_bits(d, mask, val, dma_cctrl); +} + +static int ldma_port_cfg(struct ldma_port *p) +{ + unsigned long flags; + struct ldma_dev *d; + u32 reg; + + d = p->ldev; + reg = field_prep(dma_pctrl_txendi, p->txendi); + reg |= field_prep(dma_pctrl_rxendi, p->rxendi); + + if (d->ver == dma_ver22) { + reg |= field_prep(dma_pctrl_txbl, p->txbl); + reg |= field_prep(dma_pctrl_rxbl, p->rxbl); + } else { + reg |= field_prep(dma_pctrl_pden, p->pkt_drop); + + if (p->txbl == dma_burstl_32dw) + reg |= dma_pctrl_txbl32; + else if (p->txbl == dma_burstl_16dw) + reg |= dma_pctrl_txbl16; + else + reg |= field_prep(dma_pctrl_txbl, dma_pctrl_txbl_8); + + if (p->rxbl == dma_burstl_32dw) + reg |= dma_pctrl_rxbl32; + else if (p->rxbl == dma_burstl_16dw) + reg |= dma_pctrl_rxbl16; + else + reg |= field_prep(dma_pctrl_rxbl, dma_pctrl_rxbl_8); + } + + spin_lock_irqsave(&d->dev_lock, flags); + writel(p->portid, d->base + dma_ps); + writel(reg, d->base + dma_pctrl); + spin_unlock_irqrestore(&d->dev_lock, flags); + + reg = readl(d->base + dma_pctrl); /* read back */ + dev_dbg(d->dev, "port control 0x%08x configuration done ", reg); + + return 0; +} + +static int ldma_chan_cfg(struct ldma_chan *c) +{ + struct ldma_dev *d = to_ldma_dev(c->vchan.chan.device); + unsigned long flags; + u32 reg; + + reg = c->pden ? dma_cctrl_pden : 0; + reg |= c->onoff ? dma_cctrl_on : 0; + reg |= c->rst ? dma_cctrl_rst : 0; + + ldma_chan_cctrl_cfg(c, reg); + ldma_chan_irq_init(c); + + if (d->ver <= dma_ver22) + return 0; + + spin_lock_irqsave(&d->dev_lock, flags); + ldma_chan_set_class(c, c->nr); + ldma_chan_byte_offset_cfg(c, c->boff_len); + ldma_chan_data_endian_cfg(c, c->data_endian_en, c->data_endian); + ldma_chan_desc_endian_cfg(c, c->desc_endian_en, c->desc_endian); + ldma_chan_hdr_mode_cfg(c, c->hdrm_len, c->hdrm_csum); + ldma_chan_rxwr_np_cfg(c, c->desc_rx_np); + ldma_chan_abc_cfg(c, c->abc_en); + spin_unlock_irqrestore(&d->dev_lock, flags); + + if (ldma_chan_is_hw_desc(c)) + ldma_chan_desc_hw_cfg(c, c->desc_phys, c->desc_cnt); + + return 0; +} + +static void ldma_dev_init(struct ldma_dev *d) +{ + unsigned long ch_mask = (unsigned long)d->channels_mask; + struct ldma_port *p; + struct ldma_chan *c; + int i; + u32 j; + + spin_lock_init(&d->dev_lock); + ldma_dev_reset(d); + ldma_dev_cfg(d); + + /* dma port initialization */ + for (i = 0; i < d->port_nrs; i++) { + p = &d->ports[i]; + ldma_port_cfg(p); + } + + /* dma channel initialization */ + for_each_set_bit(j, &ch_mask, d->chan_nrs) { + c = &d->chans[j]; + ldma_chan_cfg(c); + } +} + +static int ldma_cfg_init(struct ldma_dev *d) +{ + struct fwnode_handle *fwnode = dev_fwnode(d->dev); + struct ldma_port *p; + int i; + + if (fwnode_property_read_bool(fwnode, "intel,dma-byte-en")) + d->flags |= dma_en_byte_en; + + if (fwnode_property_read_bool(fwnode, "intel,dma-dburst-wr")) + d->flags |= dma_dburst_wr; + + if (fwnode_property_read_bool(fwnode, "intel,dma-drb")) + d->flags |= dma_dft_drb; + + if (fwnode_property_read_u32(fwnode, "intel,dma-poll-cnt", + &d->pollcnt)) + d->pollcnt = dma_dft_poll_cnt; + + if (d->inst->chan_fc) + d->flags |= dma_chan_flow_ctl; + + if (d->inst->desc_fod) + d->flags |= dma_desc_fod; + + if (d->inst->desc_in_sram) + d->flags |= dma_desc_in_sram; + + if (d->inst->valid_desc_fetch_ack) + d->flags |= dma_valid_desc_fetch_ack; + + if (d->ver > dma_ver22) { + if (!d->port_nrs) + return -einval; + + for (i = 0; i < d->port_nrs; i++) { + p = &d->ports[i]; + p->rxendi = dma_dft_endian; + p->txendi = dma_dft_endian; + p->rxbl = dma_dft_burst; + p->txbl = dma_dft_burst; + p->pkt_drop = dma_pkt_drop_dis; + } + } + + return 0; +} + +static void dma_free_desc_resource(struct virt_dma_desc *vdesc) +{ + struct dw2_desc_sw *ds = to_lgm_dma_desc(vdesc); + struct ldma_chan *c = ds->chan; + + dma_pool_free(c->desc_pool, ds->desc_hw, ds->desc_phys); + kfree(ds); +} + +static struct dw2_desc_sw * +dma_alloc_desc_resource(int num, struct ldma_chan *c) +{ + struct device *dev = c->vchan.chan.device->dev; + struct dw2_desc_sw *ds; + + if (num > c->desc_num) { + dev_err(dev, "sg num %d exceed max %d ", num, c->desc_num); + return null; + } + + ds = kzalloc(sizeof(*ds), gfp_nowait); + if (!ds) + return null; + + ds->chan = c; + ds->desc_hw = dma_pool_zalloc(c->desc_pool, gfp_atomic, + &ds->desc_phys); + if (!ds->desc_hw) { + dev_dbg(dev, "out of memory for link descriptor "); + kfree(ds); + return null; + } + ds->desc_cnt = num; + + return ds; +} + +static void ldma_chan_irq_en(struct ldma_chan *c) +{ + struct ldma_dev *d = to_ldma_dev(c->vchan.chan.device); + unsigned long flags; + + spin_lock_irqsave(&d->dev_lock, flags); + writel(c->nr, d->base + dma_cs); + writel(dma_ci_eop, d->base + dma_cie); + writel(bit(c->nr), d->base + dma_irnen); + spin_unlock_irqrestore(&d->dev_lock, flags); +} + +static void ldma_issue_pending(struct dma_chan *chan) +{ + struct ldma_chan *c = to_ldma_chan(chan); + struct ldma_dev *d = to_ldma_dev(c->vchan.chan.device); + unsigned long flags; + + if (d->ver == dma_ver22) { + spin_lock_irqsave(&c->vchan.lock, flags); + if (vchan_issue_pending(&c->vchan)) { + struct virt_dma_desc *vdesc; + + /* get the next descriptor */ + vdesc = vchan_next_desc(&c->vchan); + if (!vdesc) { + c->ds = null; + spin_unlock_irqrestore(&c->vchan.lock, flags); + return; + } + list_del(&vdesc->node); + c->ds = to_lgm_dma_desc(vdesc); + ldma_chan_desc_hw_cfg(c, c->ds->desc_phys, c->ds->desc_cnt); + ldma_chan_irq_en(c); + } + spin_unlock_irqrestore(&c->vchan.lock, flags); + } + ldma_chan_on(c); +} + +static void ldma_synchronize(struct dma_chan *chan) +{ + struct ldma_chan *c = to_ldma_chan(chan); + + /* + * clear any pending work if any. in that + * case the resource needs to be free here. + */ + cancel_work_sync(&c->work); + vchan_synchronize(&c->vchan); + if (c->ds) + dma_free_desc_resource(&c->ds->vdesc); +} + +static int ldma_terminate_all(struct dma_chan *chan) +{ + struct ldma_chan *c = to_ldma_chan(chan); + unsigned long flags; + list_head(head); + + spin_lock_irqsave(&c->vchan.lock, flags); + vchan_get_all_descriptors(&c->vchan, &head); + spin_unlock_irqrestore(&c->vchan.lock, flags); + vchan_dma_desc_free_list(&c->vchan, &head); + + return ldma_chan_reset(c); +} + +static int ldma_resume_chan(struct dma_chan *chan) +{ + struct ldma_chan *c = to_ldma_chan(chan); + + ldma_chan_on(c); + + return 0; +} + +static int ldma_pause_chan(struct dma_chan *chan) +{ + struct ldma_chan *c = to_ldma_chan(chan); + + return ldma_chan_off(c); +} + +static enum dma_status +ldma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct ldma_chan *c = to_ldma_chan(chan); + struct ldma_dev *d = to_ldma_dev(c->vchan.chan.device); + enum dma_status status = dma_complete; + + if (d->ver == dma_ver22) + status = dma_cookie_status(chan, cookie, txstate); + + return status; +} + +static void dma_chan_irq(int irq, void *data) +{ + struct ldma_chan *c = data; + struct ldma_dev *d = to_ldma_dev(c->vchan.chan.device); + u32 stat; + + /* disable channel interrupts */ + writel(c->nr, d->base + dma_cs); + stat = readl(d->base + dma_cis); + if (!stat) + return; + + writel(readl(d->base + dma_cie) & ~dma_ci_all, d->base + dma_cie); + writel(stat, d->base + dma_cis); + queue_work(d->wq, &c->work); +} + +static irqreturn_t dma_interrupt(int irq, void *dev_id) +{ + struct ldma_dev *d = dev_id; + struct ldma_chan *c; + unsigned long irncr; + u32 cid; + + irncr = readl(d->base + dma_irncr); + if (!irncr) { + dev_err(d->dev, "dummy interrupt "); + return irq_none; + } + + for_each_set_bit(cid, &irncr, d->chan_nrs) { + /* mask */ + writel(readl(d->base + dma_irnen) & ~bit(cid), d->base + dma_irnen); + /* ack */ + writel(readl(d->base + dma_irncr) | bit(cid), d->base + dma_irncr); + + c = &d->chans[cid]; + dma_chan_irq(irq, c); + } + + return irq_handled; +} + +static void prep_slave_burst_len(struct ldma_chan *c) +{ + struct ldma_port *p = c->port; + struct dma_slave_config *cfg = &c->config; + + if (cfg->dst_maxburst) + cfg->src_maxburst = cfg->dst_maxburst; + + /* tx and rx has the same burst length */ + p->txbl = ilog2(cfg->src_maxburst); + p->rxbl = p->txbl; +} + +static struct dma_async_tx_descriptor * +ldma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sglen, enum dma_transfer_direction dir, + unsigned long flags, void *context) +{ + struct ldma_chan *c = to_ldma_chan(chan); + struct ldma_dev *d = to_ldma_dev(c->vchan.chan.device); + size_t len, avail, total = 0; + struct dw2_desc *hw_ds; + struct dw2_desc_sw *ds; + struct scatterlist *sg; + int num = sglen, i; + dma_addr_t addr; + + if (!sgl) + return null; + + if (d->ver > dma_ver22) + return ldma_chan_desc_cfg(chan, sgl->dma_address, sglen); + + for_each_sg(sgl, sg, sglen, i) { + avail = sg_dma_len(sg); + if (avail > dma_max_size) + num += div_round_up(avail, dma_max_size) - 1; + } + + ds = dma_alloc_desc_resource(num, c); + if (!ds) + return null; + + c->ds = ds; + + num = 0; + /* sop and eop has to be handled nicely */ + for_each_sg(sgl, sg, sglen, i) { + addr = sg_dma_address(sg); + avail = sg_dma_len(sg); + total += avail; + + do { + len = min_t(size_t, avail, dma_max_size); + + hw_ds = &ds->desc_hw[num]; + switch (sglen) { + case 1: + hw_ds->field &= ~desc_sop; + hw_ds->field |= field_prep(desc_sop, 1); + + hw_ds->field &= ~desc_eop; + hw_ds->field |= field_prep(desc_eop, 1); + break; + default: + if (num == 0) { + hw_ds->field &= ~desc_sop; + hw_ds->field |= field_prep(desc_sop, 1); + + hw_ds->field &= ~desc_eop; + hw_ds->field |= field_prep(desc_eop, 0); + } else if (num == (sglen - 1)) { + hw_ds->field &= ~desc_sop; + hw_ds->field |= field_prep(desc_sop, 0); + hw_ds->field &= ~desc_eop; + hw_ds->field |= field_prep(desc_eop, 1); + } else { + hw_ds->field &= ~desc_sop; + hw_ds->field |= field_prep(desc_sop, 0); + + hw_ds->field &= ~desc_eop; + hw_ds->field |= field_prep(desc_eop, 0); + } + break; + } + /* only 32 bit address supported */ + hw_ds->addr = (u32)addr; + + hw_ds->field &= ~desc_data_len; + hw_ds->field |= field_prep(desc_data_len, len); + + hw_ds->field &= ~desc_c; + hw_ds->field |= field_prep(desc_c, 0); + + hw_ds->field &= ~desc_byte_off; + hw_ds->field |= field_prep(desc_byte_off, addr & 0x3); + + /* ensure data ready before ownership change */ + wmb(); + hw_ds->field &= ~desc_own; + hw_ds->field |= field_prep(desc_own, dma_own); + + /* ensure ownership changed before moving forward */ + wmb(); + num++; + addr += len; + avail -= len; + } while (avail); + } + + ds->size = total; + prep_slave_burst_len(c); + + return vchan_tx_prep(&c->vchan, &ds->vdesc, dma_ctrl_ack); +} + +static int +ldma_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg) +{ + struct ldma_chan *c = to_ldma_chan(chan); + + memcpy(&c->config, cfg, sizeof(c->config)); + + return 0; +} + +static int ldma_alloc_chan_resources(struct dma_chan *chan) +{ + struct ldma_chan *c = to_ldma_chan(chan); + struct ldma_dev *d = to_ldma_dev(c->vchan.chan.device); + struct device *dev = c->vchan.chan.device->dev; + size_t desc_sz; + + if (d->ver > dma_ver22) { + c->flags |= chan_in_use; + return 0; + } + + if (c->desc_pool) + return c->desc_num; + + desc_sz = c->desc_num * sizeof(struct dw2_desc); + c->desc_pool = dma_pool_create(c->name, dev, desc_sz, + __alignof__(struct dw2_desc), 0); + + if (!c->desc_pool) { + dev_err(dev, "unable to allocate descriptor pool "); + return -enomem; + } + + return c->desc_num; +} + +static void ldma_free_chan_resources(struct dma_chan *chan) +{ + struct ldma_chan *c = to_ldma_chan(chan); + struct ldma_dev *d = to_ldma_dev(c->vchan.chan.device); + + if (d->ver == dma_ver22) { + dma_pool_destroy(c->desc_pool); + c->desc_pool = null; + vchan_free_chan_resources(to_virt_chan(chan)); + ldma_chan_reset(c); + } else { + c->flags &= ~chan_in_use; + } +} + +static void dma_work(struct work_struct *work) +{ + struct ldma_chan *c = container_of(work, struct ldma_chan, work); + struct dma_async_tx_descriptor *tx = &c->ds->vdesc.tx; + struct virt_dma_chan *vc = &c->vchan; + struct dmaengine_desc_callback cb; + struct virt_dma_desc *vd, *_vd; + unsigned long flags; + list_head(head); + + spin_lock_irqsave(&c->vchan.lock, flags); + list_splice_tail_init(&vc->desc_completed, &head); + spin_unlock_irqrestore(&c->vchan.lock, flags); + dmaengine_desc_get_callback(tx, &cb); + dma_cookie_complete(tx); + dmaengine_desc_callback_invoke(&cb, null); + + list_for_each_entry_safe(vd, _vd, &head, node) { + dmaengine_desc_get_callback(tx, &cb); + dma_cookie_complete(tx); + list_del(&vd->node); + dmaengine_desc_callback_invoke(&cb, null); + + vchan_vdesc_fini(vd); + } + c->ds = null; +} + +static void +update_burst_len_v22(struct ldma_chan *c, struct ldma_port *p, u32 burst) +{ + if (ldma_chan_tx(c)) + p->txbl = ilog2(burst); + else + p->rxbl = ilog2(burst); +} + +static void +update_burst_len_v3x(struct ldma_chan *c, struct ldma_port *p, u32 burst) +{ + if (ldma_chan_tx(c)) + p->txbl = burst; + else + p->rxbl = burst; +} + +static int +update_client_configs(struct of_dma *ofdma, struct of_phandle_args *spec) +{ + struct ldma_dev *d = ofdma->of_dma_data; + u32 chan_id = spec->args[0]; + u32 port_id = spec->args[1]; + u32 burst = spec->args[2]; + struct ldma_port *p; + struct ldma_chan *c; + + if (chan_id >= d->chan_nrs || port_id >= d->port_nrs) + return 0; + + p = &d->ports[port_id]; + c = &d->chans[chan_id]; + c->port = p; + + if (d->ver == dma_ver22) + update_burst_len_v22(c, p, burst); + else + update_burst_len_v3x(c, p, burst); + + ldma_port_cfg(p); + + return 1; +} + +static struct dma_chan *ldma_xlate(struct of_phandle_args *spec, + struct of_dma *ofdma) +{ + struct ldma_dev *d = ofdma->of_dma_data; + u32 chan_id = spec->args[0]; + int ret; + + if (!spec->args_count) + return null; + + /* if args_count is 1 driver use default settings */ + if (spec->args_count > 1) { + ret = update_client_configs(ofdma, spec); + if (!ret) + return null; + } + + return dma_get_slave_channel(&d->chans[chan_id].vchan.chan); +} + +static void ldma_dma_init_v22(int i, struct ldma_dev *d) +{ + struct ldma_chan *c; + + c = &d->chans[i]; + c->nr = i; /* real channel number */ + c->rst = dma_chan_rst; + c->desc_num = dma_dft_desc_num; + snprintf(c->name, sizeof(c->name), "chan%d", c->nr); + init_work(&c->work, dma_work); + c->vchan.desc_free = dma_free_desc_resource; + vchan_init(&c->vchan, &d->dma_dev); +} + +static void ldma_dma_init_v3x(int i, struct ldma_dev *d) +{ + struct ldma_chan *c; + + c = &d->chans[i]; + c->data_endian = dma_dft_endian; + c->desc_endian = dma_dft_endian; + c->data_endian_en = false; + c->desc_endian_en = false; + c->desc_rx_np = false; + c->flags |= device_alloc_desc; + c->onoff = dma_ch_off; + c->rst = dma_chan_rst; + c->abc_en = true; + c->hdrm_csum = false; + c->boff_len = 0; + c->nr = i; + c->vchan.desc_free = dma_free_desc_resource; + vchan_init(&c->vchan, &d->dma_dev); +} + +static int ldma_init_v22(struct ldma_dev *d, struct platform_device *pdev) +{ + int ret; + + ret = device_property_read_u32(d->dev, "dma-channels", &d->chan_nrs); + if (ret < 0) { + dev_err(d->dev, "unable to read dma-channels property "); + return ret; + } + + d->irq = platform_get_irq(pdev, 0); + if (d->irq < 0) + return d->irq; + + ret = devm_request_irq(&pdev->dev, d->irq, dma_interrupt, 0, + driver_name, d); + if (ret) + return ret; + + d->wq = alloc_ordered_workqueue("dma_wq", wq_mem_reclaim | + wq_highpri); + if (!d->wq) + return -enomem; + + return 0; +} + +static void ldma_clk_disable(void *data) +{ + struct ldma_dev *d = data; + + clk_disable_unprepare(d->core_clk); + reset_control_assert(d->rst); +} + +static const struct ldma_inst_data dma0 = { + .name = "dma0", + .chan_fc = false, + .desc_fod = false, + .desc_in_sram = false, + .valid_desc_fetch_ack = false, +}; + +static const struct ldma_inst_data dma2tx = { + .name = "dma2tx", + .type = dma_type_tx, + .orrc = 16, + .chan_fc = true, + .desc_fod = true, + .desc_in_sram = true, + .valid_desc_fetch_ack = true, +}; + +static const struct ldma_inst_data dma1rx = { + .name = "dma1rx", + .type = dma_type_rx, + .orrc = 16, + .chan_fc = false, + .desc_fod = true, + .desc_in_sram = true, + .valid_desc_fetch_ack = false, +}; + +static const struct ldma_inst_data dma1tx = { + .name = "dma1tx", + .type = dma_type_tx, + .orrc = 16, + .chan_fc = true, + .desc_fod = true, + .desc_in_sram = true, + .valid_desc_fetch_ack = true, +}; + +static const struct ldma_inst_data dma0tx = { + .name = "dma0tx", + .type = dma_type_tx, + .orrc = 16, + .chan_fc = true, + .desc_fod = true, + .desc_in_sram = true, + .valid_desc_fetch_ack = true, +}; + +static const struct ldma_inst_data dma3 = { + .name = "dma3", + .type = dma_type_mcpy, + .orrc = 16, + .chan_fc = false, + .desc_fod = false, + .desc_in_sram = true, + .valid_desc_fetch_ack = false, +}; + +static const struct ldma_inst_data toe_dma30 = { + .name = "toe_dma30", + .type = dma_type_mcpy, + .orrc = 16, + .chan_fc = false, + .desc_fod = false, + .desc_in_sram = true, + .valid_desc_fetch_ack = true, +}; + +static const struct ldma_inst_data toe_dma31 = { + .name = "toe_dma31", + .type = dma_type_mcpy, + .orrc = 16, + .chan_fc = false, + .desc_fod = false, + .desc_in_sram = true, + .valid_desc_fetch_ack = true, +}; + +static const struct of_device_id intel_ldma_match[] = { + { .compatible = "intel,lgm-cdma", .data = &dma0}, + { .compatible = "intel,lgm-dma2tx", .data = &dma2tx}, + { .compatible = "intel,lgm-dma1rx", .data = &dma1rx}, + { .compatible = "intel,lgm-dma1tx", .data = &dma1tx}, + { .compatible = "intel,lgm-dma0tx", .data = &dma0tx}, + { .compatible = "intel,lgm-dma3", .data = &dma3}, + { .compatible = "intel,lgm-toe-dma30", .data = &toe_dma30}, + { .compatible = "intel,lgm-toe-dma31", .data = &toe_dma31}, + {} +}; + +static int intel_ldma_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct dma_device *dma_dev; + unsigned long ch_mask; + struct ldma_chan *c; + struct ldma_port *p; + struct ldma_dev *d; + u32 id, bitn = 32, j; + int i, ret; + + d = devm_kzalloc(dev, sizeof(*d), gfp_kernel); + if (!d) + return -enomem; + + /* link controller to platform device */ + d->dev = &pdev->dev; + + d->inst = device_get_match_data(dev); + if (!d->inst) { + dev_err(dev, "no device match found "); + return -enodev; + } + + d->base = devm_platform_ioremap_resource(pdev, 0); + if (is_err(d->base)) + return ptr_err(d->base); + + /* power up and reset the dma engine, some dmas always on?? */ + d->core_clk = devm_clk_get_optional(dev, null); + if (is_err(d->core_clk)) + return ptr_err(d->core_clk); + clk_prepare_enable(d->core_clk); + + d->rst = devm_reset_control_get_optional(dev, null); + if (is_err(d->rst)) + return ptr_err(d->rst); + reset_control_deassert(d->rst); + + ret = devm_add_action_or_reset(dev, ldma_clk_disable, d); + if (ret) { + dev_err(dev, "failed to devm_add_action_or_reset, %d ", ret); + return ret; + } + + id = readl(d->base + dma_id); + d->chan_nrs = field_get(dma_id_chnr, id); + d->port_nrs = field_get(dma_id_pnr, id); + d->ver = field_get(dma_id_rev, id); + + if (id & dma_id_aw_36b) + d->flags |= dma_addr_36bit; + + if (is_enabled(config_64bit) && (id & dma_id_aw_36b)) + bitn = 36; + + if (id & dma_id_dw_128b) + d->flags |= dma_data_128bit; + + ret = dma_set_mask_and_coherent(dev, dma_bit_mask(bitn)); + if (ret) { + dev_err(dev, "no usable dma configuration "); + return ret; + } + + if (d->ver == dma_ver22) { + ret = ldma_init_v22(d, pdev); + if (ret) + return ret; + } + + ret = device_property_read_u32(dev, "dma-channel-mask", &d->channels_mask); + if (ret < 0) + d->channels_mask = genmask(d->chan_nrs - 1, 0); + + dma_dev = &d->dma_dev; + + dma_cap_zero(dma_dev->cap_mask); + dma_cap_set(dma_slave, dma_dev->cap_mask); + + /* channel initializations */ + init_list_head(&dma_dev->channels); + + /* port initializations */ + d->ports = devm_kcalloc(dev, d->port_nrs, sizeof(*p), gfp_kernel); + if (!d->ports) + return -enomem; + + /* channels initializations */ + d->chans = devm_kcalloc(d->dev, d->chan_nrs, sizeof(*c), gfp_kernel); + if (!d->chans) + return -enomem; + + for (i = 0; i < d->port_nrs; i++) { + p = &d->ports[i]; + p->portid = i; + p->ldev = d; + } + + ret = ldma_cfg_init(d); + if (ret) + return ret; + + dma_dev->dev = &pdev->dev; + + ch_mask = (unsigned long)d->channels_mask; + for_each_set_bit(j, &ch_mask, d->chan_nrs) { + if (d->ver == dma_ver22) + ldma_dma_init_v22(j, d); + else + ldma_dma_init_v3x(j, d); + } + + dma_dev->device_alloc_chan_resources = ldma_alloc_chan_resources; + dma_dev->device_free_chan_resources = ldma_free_chan_resources; + dma_dev->device_terminate_all = ldma_terminate_all; + dma_dev->device_issue_pending = ldma_issue_pending; + dma_dev->device_tx_status = ldma_tx_status; + dma_dev->device_resume = ldma_resume_chan; + dma_dev->device_pause = ldma_pause_chan; + dma_dev->device_prep_slave_sg = ldma_prep_slave_sg; + + if (d->ver == dma_ver22) { + dma_dev->device_config = ldma_slave_config; + dma_dev->device_synchronize = ldma_synchronize; + dma_dev->src_addr_widths = bit(dma_slave_buswidth_4_bytes); + dma_dev->dst_addr_widths = bit(dma_slave_buswidth_4_bytes); + dma_dev->directions = bit(dma_mem_to_dev) | + bit(dma_dev_to_mem); + dma_dev->residue_granularity = + dma_residue_granularity_descriptor; + } + + platform_set_drvdata(pdev, d); + + ldma_dev_init(d); + + ret = dma_async_device_register(dma_dev); + if (ret) { + dev_err(dev, "failed to register slave dma engine device "); + return ret; + } + + ret = of_dma_controller_register(pdev->dev.of_node, ldma_xlate, d); + if (ret) { + dev_err(dev, "failed to register of dma controller "); + dma_async_device_unregister(dma_dev); + return ret; + } + + dev_info(dev, "init done - rev: %x, ports: %d channels: %d ", d->ver, + d->port_nrs, d->chan_nrs); + + return 0; +} + +static struct platform_driver intel_ldma_driver = { + .probe = intel_ldma_probe, + .driver = { + .name = driver_name, + .of_match_table = intel_ldma_match, + }, +}; + +/* + * perform this driver as device_initcall to make sure initialization happens + * before its dma clients of some are platform specific and also to provide + * registered dma channels and dma capabilities to clients before their + * initialization. + */ +static int __init intel_ldma_init(void) +{ + return platform_driver_register(&intel_ldma_driver); +} + +device_initcall(intel_ldma_init);
|
DMA engines
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32d31c79a1a4fbc48aab594a4dc9ffa087ab59a3
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amireddy mallikarjuna reddy
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drivers
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dma
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lgm
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dt-bindings: dma: add yaml schemas for dw-axi-dmac
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yaml schemas device tree (dt) binding is the new format for dt to replace the old format. introduce yaml schemas dt binding for dw-axi-dmac and remove the old version.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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support intel keembay axidma
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
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['dw-axi-dmac']
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['txt', 'yaml']
| 2
| 121
| 39
|
--- diff --git a/documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt b/documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt --- a/documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt +++ /dev/null -synopsys designware axi dma controller - -required properties: -- compatible: "snps,axi-dma-1.01a" -- reg: address range of the dmac registers. this should include - all of the per-channel registers. -- interrupt: should contain the dmac interrupt number. -- dma-channels: number of channels supported by hardware. -- snps,dma-masters: number of axi masters supported by the hardware. -- snps,data-width: maximum axi data width supported by hardware. - (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits) -- snps,priority: priority of channel. array size is equal to the number of - dma-channels. priority value must be programmed within [0:dma-channels-1] - range. (0 - minimum priority) -- snps,block-size: maximum block size supported by the controller channel. - array size is equal to the number of dma-channels. - -optional properties: -- snps,axi-max-burst-len: restrict master axi burst length by value specified - in this property. if this property is missing the maximum axi burst length - supported by dmac is used. [1:256] - -example: - -dmac: dma-controller@80000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0x80000 0x400>; - clocks = <&core_clk>, <&cfgr_clk>; - clock-names = "core-clk", "cfgr-clk"; - interrupt-parent = <&intc>; - interrupts = <27>; - - dma-channels = <4>; - snps,dma-masters = <2>; - snps,data-width = <3>; - snps,block-size = <4096 4096 4096 4096>; - snps,priority = <0 1 2 3>; - snps,axi-max-burst-len = <16>; -}; diff --git a/documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml --- /dev/null +++ b/documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +# spdx-license-identifier: (gpl-2.0-only or bsd-2-clause) +%yaml 1.2 +--- +$id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: synopsys designware axi dma controller + +maintainers: + - eugeniy paltsev <eugeniy.paltsev@synopsys.com> + +description: + synopsys designware axi dma controller dt binding + +allof: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + enum: + - snps,axi-dma-1.01a + + reg: + items: + - description: address range of the dmac registers + + reg-names: + items: + - const: axidma_ctrl_regs + + interrupts: + maxitems: 1 + + clocks: + items: + - description: bus clock + - description: module clock + + clock-names: + items: + - const: core-clk + - const: cfgr-clk + + '#dma-cells': + const: 1 + + dma-channels: + minimum: 1 + maximum: 8 + + snps,dma-masters: + description: | + number of axi masters supported by the hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + + snps,data-width: + description: | + axi data width supported by hardware. + (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits) + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6] + + snps,priority: + description: | + channel priority specifier associated with the dma channels. + $ref: /schemas/types.yaml#/definitions/uint32-array + minitems: 1 + maxitems: 8 + + snps,block-size: + description: | + channel block size specifier associated with the dma channels. + $ref: /schemas/types.yaml#/definitions/uint32-array + minitems: 1 + maxitems: 8 + + snps,axi-max-burst-len: + description: | + restrict master axi burst length by value specified in this property. + if this property is missing the maximum axi burst length supported by + dmac is used. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 256 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - '#dma-cells' + - dma-channels + - snps,dma-masters + - snps,data-width + - snps,priority + - snps,block-size + +additionalproperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + /* example with snps,dw-axi-dmac */ + dmac: dma-controller@80000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x80000 0x400>; + clocks = <&core_clk>, <&cfgr_clk>; + clock-names = "core-clk", "cfgr-clk"; + interrupt-parent = <&intc>; + interrupts = <27>; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <2>; + snps,data-width = <3>; + snps,block-size = <4096 4096 4096 4096>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <16>; + };
|
DMA engines
|
8c70fb7e0a0ab477504e0bd761d301ddd616c8eb
|
sia jee heng eugeniy paltsev eugeniy paltsev synopsys com rob herring robh kernel org
|
documentation
|
devicetree
|
bindings, dma
|
dmaengine: dw-axi-dmac: simplify descriptor management
|
simplify and refactor the descriptor management by removing the redundant linked list item (lli) queue control logic from the axidma driver. the descriptor is split into virtual descriptor and hardware lli so that only hardware lli memories are allocated from the dma memory pool.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support intel keembay axidma
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dw-axi-dmac']
|
['h', 'c']
| 2
| 102
| 71
|
--- diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +#include <linux/slab.h> -static struct axi_dma_desc *axi_desc_get(struct axi_dma_chan *chan) +static struct axi_dma_desc *axi_desc_alloc(u32 num) - struct dw_axi_dma *dw = chan->chip->dw; + + desc = kzalloc(sizeof(*desc), gfp_nowait); + if (!desc) + return null; + + desc->hw_desc = kcalloc(num, sizeof(*desc->hw_desc), gfp_nowait); + if (!desc->hw_desc) { + kfree(desc); + return null; + } + + return desc; +} + +static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan, + dma_addr_t *addr) +{ + struct dw_axi_dma *dw = chan->chip->dw; + struct axi_dma_lli *lli; - desc = dma_pool_zalloc(dw->desc_pool, gfp_nowait, &phys); - if (unlikely(!desc)) { + lli = dma_pool_zalloc(dw->desc_pool, gfp_nowait, &phys); + if (unlikely(!lli)) { - init_list_head(&desc->xfer_list); - desc->vd.tx.phys = phys; - desc->chan = chan; + *addr = phys; - return desc; + return lli; - struct axi_dma_desc *child, *_next; - unsigned int descs_put = 0; + int count = atomic_read(&chan->descs_allocated); + struct axi_dma_hw_desc *hw_desc; + int descs_put; - list_for_each_entry_safe(child, _next, &desc->xfer_list, xfer_list) { - list_del(&child->xfer_list); - dma_pool_free(dw->desc_pool, child, child->vd.tx.phys); - descs_put++; + for (descs_put = 0; descs_put < count; descs_put++) { + hw_desc = &desc->hw_desc[descs_put]; + dma_pool_free(dw->desc_pool, hw_desc->lli, hw_desc->llp); - dma_pool_free(dw->desc_pool, desc, desc->vd.tx.phys); - descs_put++; - + kfree(desc->hw_desc); + kfree(desc); -static void write_desc_llp(struct axi_dma_desc *desc, dma_addr_t adr) +static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr) - desc->lli.llp = cpu_to_le64(adr); + desc->lli->llp = cpu_to_le64(adr); - write_chan_llp(chan, first->vd.tx.phys | lms); + write_chan_llp(chan, first->hw_desc[0].llp | lms); -static void set_desc_last(struct axi_dma_desc *desc) +static void set_desc_last(struct axi_dma_hw_desc *desc) - val = le32_to_cpu(desc->lli.ctl_hi); + val = le32_to_cpu(desc->lli->ctl_hi); - desc->lli.ctl_hi = cpu_to_le32(val); + desc->lli->ctl_hi = cpu_to_le32(val); -static void write_desc_sar(struct axi_dma_desc *desc, dma_addr_t adr) +static void write_desc_sar(struct axi_dma_hw_desc *desc, dma_addr_t adr) - desc->lli.sar = cpu_to_le64(adr); + desc->lli->sar = cpu_to_le64(adr); -static void write_desc_dar(struct axi_dma_desc *desc, dma_addr_t adr) +static void write_desc_dar(struct axi_dma_hw_desc *desc, dma_addr_t adr) - desc->lli.dar = cpu_to_le64(adr); + desc->lli->dar = cpu_to_le64(adr); -static void set_desc_src_master(struct axi_dma_desc *desc) +static void set_desc_src_master(struct axi_dma_hw_desc *desc) - val = le32_to_cpu(desc->lli.ctl_lo); + val = le32_to_cpu(desc->lli->ctl_lo); - desc->lli.ctl_lo = cpu_to_le32(val); + desc->lli->ctl_lo = cpu_to_le32(val); -static void set_desc_dest_master(struct axi_dma_desc *desc) +static void set_desc_dest_master(struct axi_dma_hw_desc *hw_desc, + struct axi_dma_desc *desc) - val = le32_to_cpu(desc->lli.ctl_lo); + val = le32_to_cpu(hw_desc->lli->ctl_lo); - desc->lli.ctl_lo = cpu_to_le32(val); + hw_desc->lli->ctl_lo = cpu_to_le32(val); - struct axi_dma_desc *first = null, *desc = null, *prev = null; - u32 xfer_width, reg; + struct axi_dma_hw_desc *hw_desc = null; + struct axi_dma_desc *desc = null; + u32 xfer_width, reg, num; + u64 llp = 0; + xfer_width = axi_chan_get_xfer_width(chan, src_adr, dst_adr, len); + num = div_round_up(len, max_block_ts << xfer_width); + desc = axi_desc_alloc(num); + if (unlikely(!desc)) + goto err_desc_get; + desc->chan = chan; + num = 0; + hw_desc = &desc->hw_desc[num]; - desc = axi_desc_get(chan); - if (unlikely(!desc)) + hw_desc->lli = axi_desc_get(chan, &hw_desc->llp); + if (unlikely(!hw_desc->lli)) - write_desc_sar(desc, src_adr); - write_desc_dar(desc, dst_adr); - desc->lli.block_ts_lo = cpu_to_le32(block_ts - 1); + write_desc_sar(hw_desc, src_adr); + write_desc_dar(hw_desc, dst_adr); + hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1); - desc->lli.ctl_hi = cpu_to_le32(reg); + hw_desc->lli->ctl_hi = cpu_to_le32(reg); - desc->lli.ctl_lo = cpu_to_le32(reg); + hw_desc->lli->ctl_lo = cpu_to_le32(reg); - set_desc_src_master(desc); - set_desc_dest_master(desc); + set_desc_src_master(hw_desc); + set_desc_dest_master(hw_desc, desc); - /* manage transfer list (xfer_list) */ - if (!first) { - first = desc; - } else { - list_add_tail(&desc->xfer_list, &first->xfer_list); - write_desc_llp(prev, desc->vd.tx.phys | lms); - } - prev = desc; + num++; - if (unlikely(!first)) + if (unlikely(!desc)) - set_desc_last(desc); + set_desc_last(&desc->hw_desc[num - 1]); + /* managed transfer list */ + do { + hw_desc = &desc->hw_desc[--num]; + write_desc_llp(hw_desc, llp | lms); + llp = hw_desc->llp; + } while (num); - return vchan_tx_prep(&chan->vc, &first->vd, flags); + return vchan_tx_prep(&chan->vc, &desc->vd, flags); - if (first) - axi_desc_put(first); + if (desc) + axi_desc_put(desc); - struct axi_dma_desc *desc) + struct axi_dma_hw_desc *desc) - le64_to_cpu(desc->lli.sar), - le64_to_cpu(desc->lli.dar), - le64_to_cpu(desc->lli.llp), - le32_to_cpu(desc->lli.block_ts_lo), - le32_to_cpu(desc->lli.ctl_hi), - le32_to_cpu(desc->lli.ctl_lo)); + le64_to_cpu(desc->lli->sar), + le64_to_cpu(desc->lli->dar), + le64_to_cpu(desc->lli->llp), + le32_to_cpu(desc->lli->block_ts_lo), + le32_to_cpu(desc->lli->ctl_hi), + le32_to_cpu(desc->lli->ctl_lo)); - struct axi_dma_desc *desc; + int count = atomic_read(&chan->descs_allocated); + int i; - axi_chan_dump_lli(chan, desc_head); - list_for_each_entry(desc, &desc_head->xfer_list, xfer_list) - axi_chan_dump_lli(chan, desc); + for (i = 0; i < count; i++) + axi_chan_dump_lli(chan, &desc_head->hw_desc[i]); - sizeof(struct axi_dma_desc), 64, 0); + sizeof(struct axi_dma_lli), 64, 0); diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h + struct axi_dma_desc *desc; +struct axi_dma_hw_desc { + struct axi_dma_lli *lli; + dma_addr_t llp; +}; + - struct axi_dma_lli lli; + struct axi_dma_hw_desc *hw_desc; - struct list_head xfer_list;
|
DMA engines
|
ef6fb2d6f1abd56cc067c694253ea362159b5ac3
|
sia jee heng
|
drivers
|
dma
|
dw-axi-dmac
|
dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources()
|
the dma memory block is created at driver load time and exist for device lifetime. move the dma_pool_create() to the ->chan_resource() callback function allowing the dma memory blocks to be created as needed and destroyed when the channel is freed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support intel keembay axidma
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dw-axi-dmac']
|
['h', 'c']
| 2
| 14
| 12
|
--- diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c - struct dw_axi_dma *dw = chan->chip->dw; - lli = dma_pool_zalloc(dw->desc_pool, gfp_nowait, &phys); + lli = dma_pool_zalloc(chan->desc_pool, gfp_nowait, &phys); - struct dw_axi_dma *dw = chan->chip->dw; - dma_pool_free(dw->desc_pool, hw_desc->lli, hw_desc->llp); + dma_pool_free(chan->desc_pool, hw_desc->lli, hw_desc->llp); + /* lli address must be aligned to a 64-byte boundary */ + chan->desc_pool = dma_pool_create(dev_name(chan2dev(chan)), + chan->chip->dev, + sizeof(struct axi_dma_lli), + 64, 0); + if (!chan->desc_pool) { + dev_err(chan2dev(chan), "no memory for descriptors "); + return -enomem; + } + dma_pool_destroy(chan->desc_pool); + chan->desc_pool = null; - /* lli address must be aligned to a 64-byte boundary */ - dw->desc_pool = dmam_pool_create(kbuild_modname, chip->dev, - sizeof(struct axi_dma_lli), 64, 0); - if (!dw->desc_pool) { - dev_err(chip->dev, "no memory for descriptors dma pool "); - return -enomem; - } diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h + struct dma_pool *desc_pool; - struct dma_pool *desc_pool;
|
DMA engines
|
0b9d2fb368b97823a477221649ac82d17a9af11b
|
sia jee heng andy shevchenko andriy shevchenko linux intel com eugeniy paltsev eugeniy paltsev synopsys com eugeniy paltsev eugeniy paltsev synopsys com
|
drivers
|
dma
|
dw-axi-dmac
|
dmaengine: dw-axi-dmac: add device_synchronize() callback
|
add support for device_synchronize() callback function to sync with dmaengine_terminate_sync().
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support intel keembay axidma
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dw-axi-dmac']
|
['c']
| 1
| 8
| 0
|
--- diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +static void dw_axi_dma_synchronize(struct dma_chan *dchan) +{ + struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); + + vchan_synchronize(&chan->vc); +} + + dw->dma.device_synchronize = dw_axi_dma_synchronize;
|
DMA engines
|
67b2e39f4acb764cbc0ab9b2af07b18aec7b2cce
|
sia jee heng andy shevchenko andriy shevchenko linux intel com eugeniy paltsev eugeniy paltsev synopsys com eugeniy paltsev eugeniy paltsev synopsys com
|
drivers
|
dma
|
dw-axi-dmac
|
dmaengine: dw-axi-dmac: add device_config operation
|
add device_config() callback function so that the device address can be passed to the dma driver.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support intel keembay axidma
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dw-axi-dmac']
|
['h', 'c']
| 2
| 12
| 0
|
--- diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +static int dw_axi_dma_chan_slave_config(struct dma_chan *dchan, + struct dma_slave_config *config) +{ + struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); + + memcpy(&chan->config, config, sizeof(*config)); + + return 0; +} + + dw->dma.device_config = dw_axi_dma_chan_slave_config; diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h + struct dma_slave_config config;
|
DMA engines
|
66c6c9455efce0185911d7befb14992122c99474
|
sia jee heng
|
drivers
|
dma
|
dw-axi-dmac
|
dmaengine: dw-axi-dmac: support device_prep_slave_sg
|
add device_prep_slave_sg() callback function so that dma_mem_to_dev and dma_dev_to_mem operations in single mode can be supported.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support intel keembay axidma
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dw-axi-dmac']
|
['h', 'c']
| 2
| 155
| 0
|
--- diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c + switch (chan->direction) { + case dma_mem_to_dev: + reg |= (chan->config.device_fc ? + dwaxidmac_tt_fc_mem_to_per_dst : + dwaxidmac_tt_fc_mem_to_per_dmac) + << ch_cfg_h_tt_fc_pos; + break; + case dma_dev_to_mem: + reg |= (chan->config.device_fc ? + dwaxidmac_tt_fc_per_to_mem_src : + dwaxidmac_tt_fc_per_to_mem_dmac) + << ch_cfg_h_tt_fc_pos; + break; + default: + break; + } +static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan, + struct axi_dma_hw_desc *hw_desc, + dma_addr_t mem_addr, size_t len) +{ + unsigned int data_width = bit(chan->chip->dw->hdata->m_data_width); + unsigned int reg_width; + unsigned int mem_width; + dma_addr_t device_addr; + size_t axi_block_ts; + size_t block_ts; + u32 ctllo, ctlhi; + u32 burst_len; + + axi_block_ts = chan->chip->dw->hdata->block_size[chan->id]; + + mem_width = __ffs(data_width | mem_addr | len); + if (mem_width > dwaxidmac_trans_width_32) + mem_width = dwaxidmac_trans_width_32; + + switch (chan->direction) { + case dma_mem_to_dev: + reg_width = __ffs(chan->config.dst_addr_width); + device_addr = chan->config.dst_addr; + ctllo = reg_width << ch_ctl_l_dst_width_pos | + mem_width << ch_ctl_l_src_width_pos | + dwaxidmac_ch_ctl_l_noinc << ch_ctl_l_dst_inc_pos | + dwaxidmac_ch_ctl_l_inc << ch_ctl_l_src_inc_pos; + block_ts = len >> mem_width; + break; + case dma_dev_to_mem: + reg_width = __ffs(chan->config.src_addr_width); + device_addr = chan->config.src_addr; + ctllo = reg_width << ch_ctl_l_src_width_pos | + mem_width << ch_ctl_l_dst_width_pos | + dwaxidmac_ch_ctl_l_inc << ch_ctl_l_dst_inc_pos | + dwaxidmac_ch_ctl_l_noinc << ch_ctl_l_src_inc_pos; + block_ts = len >> reg_width; + break; + default: + return -einval; + } + + if (block_ts > axi_block_ts) + return -einval; + + hw_desc->lli = axi_desc_get(chan, &hw_desc->llp); + if (unlikely(!hw_desc->lli)) + return -enomem; + + ctlhi = ch_ctl_h_lli_valid; + + if (chan->chip->dw->hdata->restrict_axi_burst_len) { + burst_len = chan->chip->dw->hdata->axi_rw_burst_len; + ctlhi |= ch_ctl_h_arlen_en | ch_ctl_h_awlen_en | + burst_len << ch_ctl_h_arlen_pos | + burst_len << ch_ctl_h_awlen_pos; + } + + hw_desc->lli->ctl_hi = cpu_to_le32(ctlhi); + + if (chan->direction == dma_mem_to_dev) { + write_desc_sar(hw_desc, mem_addr); + write_desc_dar(hw_desc, device_addr); + } else { + write_desc_sar(hw_desc, device_addr); + write_desc_dar(hw_desc, mem_addr); + } + + hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1); + + ctllo |= dwaxidmac_burst_trans_len_4 << ch_ctl_l_dst_msize_pos | + dwaxidmac_burst_trans_len_4 << ch_ctl_l_src_msize_pos; + hw_desc->lli->ctl_lo = cpu_to_le32(ctllo); + + set_desc_src_master(hw_desc); + + return 0; +} + +static struct dma_async_tx_descriptor * +dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, + unsigned int sg_len, + enum dma_transfer_direction direction, + unsigned long flags, void *context) +{ + struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); + struct axi_dma_hw_desc *hw_desc = null; + struct axi_dma_desc *desc = null; + struct scatterlist *sg; + unsigned int i; + u32 mem, len; + int status; + u64 llp = 0; + u8 lms = 0; /* select axi0 master for lli fetching */ + + if (unlikely(!is_slave_direction(direction) || !sg_len)) + return null; + + chan->direction = direction; + + desc = axi_desc_alloc(sg_len); + if (unlikely(!desc)) + goto err_desc_get; + + desc->chan = chan; + + for_each_sg(sgl, sg, sg_len, i) { + mem = sg_dma_address(sg); + len = sg_dma_len(sg); + hw_desc = &desc->hw_desc[i]; + + status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, len); + if (status < 0) + goto err_desc_get; + } + + /* set end-of-link to the last link descriptor of list */ + set_desc_last(&desc->hw_desc[sg_len - 1]); + + /* managed transfer list */ + do { + hw_desc = &desc->hw_desc[--sg_len]; + write_desc_llp(hw_desc, llp | lms); + llp = hw_desc->llp; + } while (sg_len); + + return vchan_tx_prep(&chan->vc, &desc->vd, flags); + +err_desc_get: + if (desc) + axi_desc_put(desc); + + return null; +} + + dma_cap_set(dma_slave, dw->dma.cap_mask); + dw->dma.directions |= bit(dma_mem_to_dev) | bit(dma_dev_to_mem); + dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg; diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h + enum dma_transfer_direction direction;
|
DMA engines
|
eec91760539ef4257cc0e4649d3db27e3762c579
|
sia jee heng
|
drivers
|
dma
|
dw-axi-dmac
|
dmaegine: dw-axi-dmac: support device_prep_dma_cyclic()
|
add support for device_prep_dma_cyclic() callback function to benefit dma cyclic client, for example alsa.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support intel keembay axidma
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dw-axi-dmac']
|
['h', 'c']
| 2
| 106
| 7
|
--- diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +#include <linux/iopoll.h> +#include <linux/io-64-nonatomic-lo-hi.h> +static struct dma_async_tx_descriptor * +dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr, + size_t buf_len, size_t period_len, + enum dma_transfer_direction direction, + unsigned long flags) +{ + struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); + struct axi_dma_hw_desc *hw_desc = null; + struct axi_dma_desc *desc = null; + dma_addr_t src_addr = dma_addr; + u32 num_periods = buf_len / period_len; + unsigned int i; + int status; + u64 llp = 0; + u8 lms = 0; /* select axi0 master for lli fetching */ + + desc = axi_desc_alloc(num_periods); + if (unlikely(!desc)) + goto err_desc_get; + + chan->direction = direction; + desc->chan = chan; + chan->cyclic = true; + + for (i = 0; i < num_periods; i++) { + hw_desc = &desc->hw_desc[i]; + + status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr, + period_len); + if (status < 0) + goto err_desc_get; + + /* set end-of-link to the linked descriptor, so that cyclic + * callback function can be triggered during interrupt. + */ + set_desc_last(hw_desc); + + src_addr += period_len; + } + + llp = desc->hw_desc[0].llp; + + /* managed transfer list */ + do { + hw_desc = &desc->hw_desc[--num_periods]; + write_desc_llp(hw_desc, llp | lms); + llp = hw_desc->llp; + } while (num_periods); + + return vchan_tx_prep(&chan->vc, &desc->vd, flags); + +err_desc_get: + if (desc) + axi_desc_put(desc); + + return null; +} + + int count = atomic_read(&chan->descs_allocated); + struct axi_dma_hw_desc *hw_desc; + struct axi_dma_desc *desc; + u64 llp; + int i; - /* remove the completed descriptor from issued list before completing */ - list_del(&vd->node); - vchan_cookie_complete(vd); - /* submit queued descriptors after processing the completed ones */ - axi_chan_start_first_queued(chan); + if (chan->cyclic) { + vchan_cyclic_callback(vd); + desc = vd_to_axi_desc(vd); + if (desc) { + llp = lo_hi_readq(chan->chan_regs + ch_llp); + for (i = 0; i < count; i++) { + hw_desc = &desc->hw_desc[i]; + if (hw_desc->llp == llp) { + axi_chan_irq_clear(chan, hw_desc->lli->status_lo); + hw_desc->lli->ctl_hi |= ch_ctl_h_lli_valid; + desc->completed_blocks = i; + break; + } + } + + axi_chan_enable(chan); + } + } else { + /* remove the completed descriptor from issued list before completing */ + list_del(&vd->node); + vchan_cookie_complete(vd); + + /* submit queued descriptors after processing the completed ones */ + axi_chan_start_first_queued(chan); + } + u32 chan_active = bit(chan->id) << dmac_chan_en_shift; + u32 val; + int ret; - spin_lock_irqsave(&chan->vc.lock, flags); - + ret = readl_poll_timeout_atomic(chan->chip->regs + dmac_chen, val, + !(val & chan_active), 1000, 10000); + if (ret == -etimedout) + dev_warn(dchan2dev(dchan), + "%s failed to stop ", axi_chan_name(chan)); + + spin_lock_irqsave(&chan->vc.lock, flags); + + chan->cyclic = false; + dma_cap_set(dma_cyclic, dw->dma.cap_mask); + dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic; diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h + bool cyclic; + u32 completed_blocks;
|
DMA engines
|
1deb96c0fa58afe0f5c4aa8e5916baa9454979d6
|
sia jee heng
|
drivers
|
dma
|
dw-axi-dmac
|
dmaengine: dw-axi-dmac: support of_dma_controller_register()
|
add support for of_dma_controller_register() so that dma clients can pass in device handshake number to the axidma driver.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support intel keembay axidma
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dw-axi-dmac']
|
['h', 'c']
| 2
| 27
| 0
|
--- diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +#include <linux/of_dma.h> +static struct dma_chan *dw_axi_dma_of_xlate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + struct dw_axi_dma *dw = ofdma->of_dma_data; + struct axi_dma_chan *chan; + struct dma_chan *dchan; + + dchan = dma_get_any_slave_channel(&dw->dma); + if (!dchan) + return null; + + chan = dchan_to_axi_dma_chan(dchan); + chan->hw_handshake_num = dma_spec->args[0]; + return dchan; +} + + /* register with of helpers for dma lookups */ + ret = of_dma_controller_register(pdev->dev.of_node, + dw_axi_dma_of_xlate, dw); + if (ret < 0) + dev_warn(&pdev->dev, + "failed to register of dma controller, fallback to mem_to_mem mode "); + + of_dma_controller_free(chip->dev->of_node); + diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h + u8 hw_handshake_num;
|
DMA engines
|
b428c6fa41125fdbba36baa92de4e439e04ccfc8
|
sia jee heng
|
drivers
|
dma
|
dw-axi-dmac
|
dmaengine: dw-axi-dmac: support burst residue granularity
|
add support for dma_residue_granularity_burst so that axidma can report dma residue.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support intel keembay axidma
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dw-axi-dmac']
|
['h', 'c']
| 2
| 38
| 7
|
--- diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c - enum dma_status ret; + struct virt_dma_desc *vdesc; + enum dma_status status; + u32 completed_length; + unsigned long flags; + u32 completed_blocks; + size_t bytes = 0; + u32 length; + u32 len; - ret = dma_cookie_status(dchan, cookie, txstate); + status = dma_cookie_status(dchan, cookie, txstate); + if (status == dma_complete || !txstate) + return status; - if (chan->is_paused && ret == dma_in_progress) - ret = dma_paused; + spin_lock_irqsave(&chan->vc.lock, flags); - return ret; + vdesc = vchan_find_desc(&chan->vc, cookie); + if (vdesc) { + length = vd_to_axi_desc(vdesc)->length; + completed_blocks = vd_to_axi_desc(vdesc)->completed_blocks; + len = vd_to_axi_desc(vdesc)->hw_desc[0].len; + completed_length = completed_blocks * len; + bytes = length - completed_length; + } else { + bytes = vd_to_axi_desc(vdesc)->length; + } + + spin_unlock_irqrestore(&chan->vc.lock, flags); + dma_set_residue(txstate, bytes); + + return status; + hw_desc->len = len; + desc->length = 0; + desc->length += hw_desc->len; + desc->length = 0; + desc->length += hw_desc->len; + desc->length = 0; - + hw_desc->len = xfer_len; + desc->length += hw_desc->len; - dw->dma.residue_granularity = dma_residue_granularity_descriptor; + dw->dma.residue_granularity = dma_residue_granularity_burst; diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h + u32 len; + u32 length;
|
DMA engines
|
8e55444da65c01143082a7d1ed08dfeeec7c244b
|
sia jee heng
|
drivers
|
dma
|
dw-axi-dmac
|
dt-binding: dma: dw-axi-dmac: add support for intel keembay axidma
|
add support for intel keembay axidma to the dw-axi-dmac schemas dt binding.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support intel keembay axidma
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dw-axi-dmac']
|
['yaml']
| 1
| 5
| 0
|
--- diff --git a/documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml --- a/documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +++ b/documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml - eugeniy paltsev <eugeniy.paltsev@synopsys.com> + - jee heng sia <jee.heng.sia@intel.com> - snps,axi-dma-1.01a + - intel,kmb-axi-dma + minitems: 1 - description: address range of the dmac registers + - description: address range of the dmac apb registers - const: axidma_ctrl_regs + - const: axidma_apb_regs
|
DMA engines
|
0a35c9a017d3e4d7f8eb503827a8cdbb8a47d7b0
|
sia jee heng eugeniy paltsev eugeniy paltsev synopsys com rob herring robh kernel org
|
documentation
|
devicetree
|
bindings, dma
|
dmaengine: dw-axi-dmac: add intel keembay dma register fields
|
add support for intel keembay dma registers. these registers are required to run data transfer between device to memory and memory to device on intel keembay soc.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support intel keembay axidma
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dw-axi-dmac']
|
['h']
| 1
| 14
| 0
|
--- diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h + void __iomem *apb_regs; +/* these apb registers are used by intel keembay soc */ +#define dmac_apb_cfg 0x000 /* dmac apb configuration register */ +#define dmac_apb_stat 0x004 /* dmac apb status register */ +#define dmac_apb_debug_stat_0 0x008 /* dmac apb debug status register 0 */ +#define dmac_apb_debug_stat_1 0x00c /* dmac apb debug status register 1 */ +#define dmac_apb_hw_hs_sel_0 0x010 /* dmac apb hw hs register 0 */ +#define dmac_apb_hw_hs_sel_1 0x014 /* dmac apb hw hs register 1 */ +#define dmac_apb_lpi 0x018 /* dmac apb low power interface reg */ +#define dmac_apb_byte_wr_ch_en 0x01c /* dmac apb byte write enable */ +#define dmac_apb_halfword_wr_ch_en 0x020 /* dmac halfword write enables */ + +#define unused_channel 0x3f /* set unused dma channel to 0x3f */ +#define max_block_size 0x1000 /* 1024 blocks * 4 bytes data width */
|
DMA engines
|
8fb1dae09091b937e4966be4d024edeb80576ca6
|
sia jee heng andy shevchenko andriy shevchenko linux intel com eugeniy paltsev eugeniy paltsev synopsys com eugeniy paltsev eugeniy paltsev synopsys com
|
drivers
|
dma
|
dw-axi-dmac
|
dmaengine: drivers: kconfig: add has_iomem dependency to dw_axi_dmac
|
if has_iomem is not defined and dw_axi_dmac is enabled under compile_test, the build fails with the following error: dw-axi-dmac-platform.c:(.text+0xc4): undefined reference to 'devm_ioremap_resource' link: https://www.spinics.net/lists/dmaengine/msg25188.html
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support intel keembay axidma
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dw-axi-dmac']
|
['kconfig']
| 1
| 1
| 0
|
--- diff --git a/drivers/dma/kconfig b/drivers/dma/kconfig --- a/drivers/dma/kconfig +++ b/drivers/dma/kconfig + depends on has_iomem
|
DMA engines
|
cd0f00c39ff48006cb0523b09b22842d21f70e72
|
sia jee heng
|
drivers
|
dma
| |
dmaengine: dw-axi-dmac: add intel keembay axidma support
|
add support for intel keembay axidma to the .compatible field. the axidma apb region will be accessible if the compatible string matches the "intel,kmb-axi-dma".
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support intel keembay axidma
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dw-axi-dmac']
|
['c']
| 1
| 8
| 0
|
--- diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c + struct device_node *node = pdev->dev.of_node; + if (of_device_is_compatible(node, "intel,kmb-axi-dma")) { + chip->apb_regs = devm_platform_ioremap_resource(pdev, 1); + if (is_err(chip->apb_regs)) + return ptr_err(chip->apb_regs); + } + + { .compatible = "intel,kmb-axi-dma" },
|
DMA engines
|
3df2d81f878dcd67716f09403a3f4bfa5c319d3b
|
sia jee heng andy shevchenko andriy shevchenko linux intel com eugeniy paltsev eugeniy paltsev synopsys com eugeniy paltsev eugeniy paltsev synopsys com
|
drivers
|
dma
|
dw-axi-dmac
|
dmaengine: dw-axi-dmac: add intel keembay axidma handshake
|
add support for intel keembay axidma device handshake programming. device handshake number passed in to the axidma shall be written to the intel keembay axidma hardware handshake registers before dma operations are started.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support intel keembay axidma
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dw-axi-dmac']
|
['c']
| 1
| 50
| 0
|
--- diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +static void dw_axi_dma_set_hw_channel(struct axi_dma_chip *chip, + u32 handshake_num, bool set) +{ + unsigned long start = 0; + unsigned long reg_value; + unsigned long reg_mask; + unsigned long reg_set; + unsigned long mask; + unsigned long val; + + if (!chip->apb_regs) { + dev_dbg(chip->dev, "apb_regs not initialized "); + return; + } + + /* + * an unused dma channel has a default value of 0x3f. + * lock the dma channel by assign a handshake number to the channel. + * unlock the dma channel by assign 0x3f to the channel. + */ + if (set) { + reg_set = unused_channel; + val = handshake_num; + } else { + reg_set = handshake_num; + val = unused_channel; + } + + reg_value = lo_hi_readq(chip->apb_regs + dmac_apb_hw_hs_sel_0); + + for_each_set_clump8(start, reg_mask, ®_value, 64) { + if (reg_mask == reg_set) { + mask = genmask_ull(start + 7, start); + reg_value &= ~mask; + reg_value |= rol64(val, start); + lo_hi_writeq(reg_value, + chip->apb_regs + dmac_apb_hw_hs_sel_0); + break; + } + } +} + + dw_axi_dma_set_hw_channel(chan->chip, chan->hw_handshake_num, true); + + dw_axi_dma_set_hw_channel(chan->chip, chan->hw_handshake_num, true); + + if (chan->direction != dma_mem_to_mem) + dw_axi_dma_set_hw_channel(chan->chip, + chan->hw_handshake_num, false); +
|
DMA engines
|
425c8a53e87478de2012c94208d7e6c59213d5ca
|
sia jee heng andy shevchenko andriy shevchenko linux intel com eugeniy paltsev eugeniy paltsev synopsys com eugeniy paltsev eugeniy paltsev synopsys com
|
drivers
|
dma
|
dw-axi-dmac
|
dmaengine: dw-axi-dmac: add intel keembay axidma byte and halfword registers
|
add support for intel keembay axidma byte and halfword registers programming.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support intel keembay axidma
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dw-axi-dmac']
|
['c']
| 1
| 26
| 0
|
--- diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +static void dw_axi_dma_set_byte_halfword(struct axi_dma_chan *chan, bool set) +{ + u32 offset = dmac_apb_byte_wr_ch_en; + u32 reg_width, val; + + if (!chan->chip->apb_regs) { + dev_dbg(chan->chip->dev, "apb_regs not initialized "); + return; + } + + reg_width = __ffs(chan->config.dst_addr_width); + if (reg_width == dwaxidmac_trans_width_16) + offset = dmac_apb_halfword_wr_ch_en; + + val = ioread32(chan->chip->apb_regs + offset); + + if (set) + val |= bit(chan->id); + else + val &= ~bit(chan->id); + + iowrite32(val, chan->chip->apb_regs + offset); +} + dw_axi_dma_set_byte_halfword(chan, true); + if (chan->direction == dma_mem_to_dev) + dw_axi_dma_set_byte_halfword(chan, false);
|
DMA engines
|
f74b3025506046e8662ebb2026697d7755b1d6ff
|
sia jee heng
|
drivers
|
dma
|
dw-axi-dmac
|
dmaengine: dw-axi-dmac: set constraint to the max segment size
|
add support for dma scatter-gather (sg) constraint so that dma clients can handle the axidma limitation.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support intel keembay axidma
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dw-axi-dmac']
|
['h', 'c']
| 2
| 9
| 0
|
--- diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +#include <linux/dma-mapping.h> + /* + * synopsis designware axidma datasheet mentioned maximum + * supported blocks is 1024. device register width is 4 bytes. + * therefore, set constraint to 1024 * 4. + */ + dw->dma.dev->dma_parms = &dw->dma_parms; + dma_set_max_seg_size(&pdev->dev, max_block_size); diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h + struct device_dma_parameters dma_parms;
|
DMA engines
|
78a90a1e489e3f19b0adf8327f432ee0684a7680
|
sia jee heng
|
drivers
|
dma
|
dw-axi-dmac
|
dmaengine: dw-axi-dmac: virtually split the linked-list
|
axidma driver exposed the dma_set_max_seg_size() to the dmaengine. it shall helps the dma clients to create size-optimized linked-list for the controller.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support intel keembay axidma
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dw-axi-dmac']
|
['h', 'c']
| 2
| 92
| 20
|
--- diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c + if (!is_aligned(mem_addr, 4)) { + dev_err(chan->chip->dev, "invalid buffer alignment "); + return -einval; + } + +static size_t calculate_block_len(struct axi_dma_chan *chan, + dma_addr_t dma_addr, size_t buf_len, + enum dma_transfer_direction direction) +{ + u32 data_width, reg_width, mem_width; + size_t axi_block_ts, block_len; + + axi_block_ts = chan->chip->dw->hdata->block_size[chan->id]; + + switch (direction) { + case dma_mem_to_dev: + data_width = bit(chan->chip->dw->hdata->m_data_width); + mem_width = __ffs(data_width | dma_addr | buf_len); + if (mem_width > dwaxidmac_trans_width_32) + mem_width = dwaxidmac_trans_width_32; + + block_len = axi_block_ts << mem_width; + break; + case dma_dev_to_mem: + reg_width = __ffs(chan->config.src_addr_width); + block_len = axi_block_ts << reg_width; + break; + default: + block_len = 0; + } + + return block_len; +} + - u32 num_periods = buf_len / period_len; + u32 num_periods, num_segments; + size_t axi_block_len; + u32 total_segments; + u32 segment_len; - desc = axi_desc_alloc(num_periods); + num_periods = buf_len / period_len; + + axi_block_len = calculate_block_len(chan, dma_addr, buf_len, direction); + if (axi_block_len == 0) + return null; + + num_segments = div_round_up(period_len, axi_block_len); + segment_len = div_round_up(period_len, num_segments); + + total_segments = num_periods * num_segments; + + desc = axi_desc_alloc(total_segments); + desc->period_len = period_len; - for (i = 0; i < num_periods; i++) { + for (i = 0; i < total_segments; i++) { - period_len); + segment_len); - src_addr += period_len; + src_addr += segment_len; - hw_desc = &desc->hw_desc[--num_periods]; + hw_desc = &desc->hw_desc[--total_segments]; - } while (num_periods); + } while (total_segments); + u32 num_segments, segment_len; + unsigned int loop = 0; + size_t axi_block_len; + u32 len, num_sgs = 0; - u32 mem, len; + dma_addr_t mem; - chan->direction = direction; + mem = sg_dma_address(sgl); + len = sg_dma_len(sgl); + + axi_block_len = calculate_block_len(chan, mem, len, direction); + if (axi_block_len == 0) + return null; - desc = axi_desc_alloc(sg_len); + for_each_sg(sgl, sg, sg_len, i) + num_sgs += div_round_up(sg_dma_len(sg), axi_block_len); + + desc = axi_desc_alloc(num_sgs); + chan->direction = direction; - hw_desc = &desc->hw_desc[i]; - - status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, len); - if (status < 0) - goto err_desc_get; - desc->length += hw_desc->len; + num_segments = div_round_up(sg_dma_len(sg), axi_block_len); + segment_len = div_round_up(sg_dma_len(sg), num_segments); + + do { + hw_desc = &desc->hw_desc[loop++]; + status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, segment_len); + if (status < 0) + goto err_desc_get; + + desc->length += hw_desc->len; + len -= segment_len; + mem += segment_len; + } while (len >= segment_len); - set_desc_last(&desc->hw_desc[sg_len - 1]); + set_desc_last(&desc->hw_desc[num_sgs - 1]); - hw_desc = &desc->hw_desc[--sg_len]; + hw_desc = &desc->hw_desc[--num_sgs]; - } while (sg_len); + } while (num_sgs); - vchan_cyclic_callback(vd); + + if (((hw_desc->len * (i + 1)) % desc->period_len) == 0) + vchan_cyclic_callback(vd); diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h + u32 period_len;
|
DMA engines
|
f80f7c96f77258da1ea291d7ccfc731b279339f1
|
sia jee heng
|
drivers
|
dma
|
dw-axi-dmac
|
dmaengine: idxd: add module parameter to force disable of sva
|
add a module parameter that overrides the sva feature enabling. this keeps the driver in legacy mode even when intel_iommu=sm_on is set. in this mode, the descriptor fields must be programmed with dma_addr_t from the linux dma api for source, destination, and completion descriptors.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add module parameter to force disable of sva
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['idxd']
|
['txt', 'c']
| 2
| 13
| 1
|
--- diff --git a/documentation/admin-guide/kernel-parameters.txt b/documentation/admin-guide/kernel-parameters.txt --- a/documentation/admin-guide/kernel-parameters.txt +++ b/documentation/admin-guide/kernel-parameters.txt + idxd.sva= [hw] + format: <bool> + allow force disabling of shared virtual memory (sva) + support for the idxd driver. by default it is set to + true (1). + diff --git a/drivers/dma/idxd/init.c b/drivers/dma/idxd/init.c --- a/drivers/dma/idxd/init.c +++ b/drivers/dma/idxd/init.c +static bool sva = true; +module_param(sva, bool, 0644); +module_parm_desc(sva, "toggle sva support on/off"); + - if (is_enabled(config_intel_idxd_svm)) { + if (is_enabled(config_intel_idxd_svm) && sva) { + } else if (!sva) { + dev_warn(dev, "user forced sva off via module param. ");
|
DMA engines
|
03d939c7e3d8800a9feb54808929c5776ac510eb
|
dave jiang
|
drivers
|
dma
|
idxd
|
dmaengine: jz4780: add support for the jz4760(b)
|
add support for the jz4760 and jz4760b socs.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for the jz4760(b)
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['jz4780']
|
['c']
| 1
| 14
| 0
|
--- diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c --- a/drivers/dma/dma-jz4780.c +++ b/drivers/dma/dma-jz4780.c +static const struct jz4780_dma_soc_data jz4760_dma_soc_data = { + .nb_channels = 5, + .transfer_ord_max = 6, + .flags = jz_soc_data_per_chan_pm | jz_soc_data_no_dckes_dckec, +}; + +static const struct jz4780_dma_soc_data jz4760b_dma_soc_data = { + .nb_channels = 5, + .transfer_ord_max = 6, + .flags = jz_soc_data_per_chan_pm, +}; + + { .compatible = "ingenic,jz4760-dma", .data = &jz4760_dma_soc_data }, + { .compatible = "ingenic,jz4760b-dma", .data = &jz4760b_dma_soc_data },
|
DMA engines
|
d2852a3e8ba98c170bac5e4b8d048f584683c23a
|
paul cercueil
|
drivers
|
dma
| |
dmaengine: owl: add compatible for the actions semi s500 dma controller
|
the dma controller present on the actions semi s500 soc is compatible with the s900 variant, so add it to the list of devices supported by the actions semi owl dma driver. additionally, order the entries alphabetically.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add compatible for the actions semi s500 dma controller
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['owl']
|
['c']
| 1
| 2
| 1
|
--- diff --git a/drivers/dma/owl-dma.c b/drivers/dma/owl-dma.c --- a/drivers/dma/owl-dma.c +++ b/drivers/dma/owl-dma.c - { .compatible = "actions,s900-dma", .data = (void *)s900_dma,}, + { .compatible = "actions,s500-dma", .data = (void *)s900_dma,}, + { .compatible = "actions,s900-dma", .data = (void *)s900_dma,},
|
DMA engines
|
c518a2fd1bcfb00bfae9007913090d8645651637
|
cristian ciocaltea manivannan sadhasivam manivannan sadhasivam linaro org
|
drivers
|
dma
| |
dmaengine: rcar-dmac: add support for r-car v3u
|
the dmacs (both sys-dmac and rt-dmac) on r-car v3u differ slightly from the dmacs on r-car gen2 and other r-car gen3 socs: 1. the per-channel registers are located in a second register block. add support for mapping the second block, using the appropriate offsets and stride. 2. the common channel clear register (dmachclr) was replaced by a per-channel register. update rcar_dmac_chan_clear{,_all}() to handle this. as rcar_dmac_init() needs to clear the status before the individual channels are probed, channel index and base address initialization are moved forward.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for r-car v3u
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['rcar-dmac']
|
['c']
| 1
| 58
| 23
|
--- diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c --- a/drivers/dma/sh/rcar-dmac.c +++ b/drivers/dma/sh/rcar-dmac.c - * @iomem: remapped i/o memory base + * @dmac_base: remapped base register block + * @chan_base: remapped channel register block (optional) - void __iomem *iomem; + void __iomem *dmac_base; + void __iomem *chan_base; -#define rcar_dmachclr 0x0080 +#define rcar_dmachclr 0x0080 /* not on r-car v3u */ +/* for r-car v3u */ +#define rcar_v3u_dmachclr 0x0100 + - writew(data, dmac->iomem + reg); + writew(data, dmac->dmac_base + reg); - writel(data, dmac->iomem + reg); + writel(data, dmac->dmac_base + reg); - return readw(dmac->iomem + reg); + return readw(dmac->dmac_base + reg); - return readl(dmac->iomem + reg); + return readl(dmac->dmac_base + reg); - rcar_dmac_write(dmac, rcar_dmachclr, bit(chan->index)); + if (dmac->chan_base) + rcar_dmac_chan_write(chan, rcar_v3u_dmachclr, 1); + else + rcar_dmac_write(dmac, rcar_dmachclr, bit(chan->index)); - rcar_dmac_write(dmac, rcar_dmachclr, dmac->channels_mask); + struct rcar_dmac_chan *chan; + unsigned int i; + + if (dmac->chan_base) { + for_each_rcar_dmac_chan(i, dmac, chan) + rcar_dmac_chan_write(chan, rcar_v3u_dmachclr, 1); + } else { + rcar_dmac_write(dmac, rcar_dmachclr, dmac->channels_mask); + } - struct rcar_dmac_chan *rchan, - const struct rcar_dmac_of_data *data, - unsigned int index) + struct rcar_dmac_chan *rchan) - rchan->index = index; - rchan->iomem = dmac->iomem + data->chan_offset_base + - data->chan_offset_stride * index; - sprintf(pdev_irqname, "ch%u", index); + sprintf(pdev_irqname, "ch%u", rchan->index); - dev_name(dmac->dev), index); + dev_name(dmac->dev), rchan->index); + void __iomem *chan_base; - dmac->iomem = devm_platform_ioremap_resource(pdev, 0); - if (is_err(dmac->iomem)) - return ptr_err(dmac->iomem); + dmac->dmac_base = devm_platform_ioremap_resource(pdev, 0); + if (is_err(dmac->dmac_base)) + return ptr_err(dmac->dmac_base); + + if (!data->chan_offset_base) { + dmac->chan_base = devm_platform_ioremap_resource(pdev, 1); + if (is_err(dmac->chan_base)) + return ptr_err(dmac->chan_base); + + chan_base = dmac->chan_base; + } else { + chan_base = dmac->dmac_base + data->chan_offset_base; + } + + for_each_rcar_dmac_chan(i, dmac, chan) { + chan->index = i; + chan->iomem = chan_base + i * data->chan_offset_stride; + } - ret = rcar_dmac_chan_probe(dmac, chan, data, i); + ret = rcar_dmac_chan_probe(dmac, chan); - .chan_offset_base = 0x8000, - .chan_offset_stride = 0x80, + .chan_offset_base = 0x8000, + .chan_offset_stride = 0x80, +}; + +static const struct rcar_dmac_of_data rcar_v3u_dmac_data = { + .chan_offset_base = 0x0, + .chan_offset_stride = 0x1000, + }, { + .compatible = "renesas,dmac-r8a779a0", + .data = &rcar_v3u_dmac_data,
|
DMA engines
|
e5bfbbb916a43a80801458e10369cf02229278eb
|
geert uytterhoeven
|
drivers
|
dma
|
sh
|
dmaengine: remove coh901318 driver
|
the st-ericsson u300 platform is getting removed, so this driver is no longer needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove coh901318 driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['c', 'h', 'kconfig', 'txt', 'makefile']
| 7
| 0
| 3,374
|
--- diff --git a/documentation/devicetree/bindings/dma/ste-coh901318.txt b/documentation/devicetree/bindings/dma/ste-coh901318.txt --- a/documentation/devicetree/bindings/dma/ste-coh901318.txt +++ /dev/null -st-ericsson coh 901 318 dma controller - -this is a dma controller which has begun as a fork of the -arm pl08x primecell vhdl code. - -required properties: -- compatible: should be "stericsson,coh901318" -- reg: register locations and length -- interrupts: the single dma irq -- #dma-cells: must be set to <1>, as the channels on the - coh 901 318 are simple and identified by a single number -- dma-channels: the number of dma channels handled - -example: - -dmac: dma-controller@c00020000 { - compatible = "stericsson,coh901318"; - reg = <0xc0020000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <2>; - #dma-cells = <1>; - dma-channels = <40>; -}; - -consumers example: - -uart0: serial@c0013000 { - compatible = "..."; - (...) - dmas = <&dmac 17 &dmac 18>; - dma-names = "tx", "rx"; -}; diff --git a/drivers/dma/kconfig b/drivers/dma/kconfig --- a/drivers/dma/kconfig +++ b/drivers/dma/kconfig -config coh901318 - bool "st-ericsson coh901318 dma support" - select dma_engine - depends on arch_u300 || compile_test - help - enable support for st-ericsson coh 901 318 dma. - diff --git a/drivers/dma/makefile b/drivers/dma/makefile --- a/drivers/dma/makefile +++ b/drivers/dma/makefile -obj-$(config_coh901318) += coh901318.o coh901318_lli.o diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c --- a/drivers/dma/coh901318.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * driver/dma/coh901318.c - * - * copyright (c) 2007-2009 st-ericsson - * dma driver for coh 901 318 - * author: per friden <per.friden@stericsson.com> - */ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/kernel.h> /* printk() */ -#include <linux/fs.h> /* everything... */ -#include <linux/scatterlist.h> -#include <linux/slab.h> /* kmalloc() */ -#include <linux/dmaengine.h> -#include <linux/platform_device.h> -#include <linux/device.h> -#include <linux/irqreturn.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include <linux/uaccess.h> -#include <linux/debugfs.h> -#include <linux/platform_data/dma-coh901318.h> -#include <linux/of_dma.h> - -#include "coh901318.h" -#include "dmaengine.h" - -#define coh901318_mod32_mask (0x1f) -#define coh901318_word_mask (0xffffffff) -/* int_status - interrupt status registers 32bit (r/-) */ -#define coh901318_int_status1 (0x0000) -#define coh901318_int_status2 (0x0004) -/* tc_int_status - terminal count interrupt status registers 32bit (r/-) */ -#define coh901318_tc_int_status1 (0x0008) -#define coh901318_tc_int_status2 (0x000c) -/* tc_int_clear - terminal count interrupt clear registers 32bit (-/w) */ -#define coh901318_tc_int_clear1 (0x0010) -#define coh901318_tc_int_clear2 (0x0014) -/* raw_tc_int_status - raw term count interrupt status registers 32bit (r/-) */ -#define coh901318_raw_tc_int_status1 (0x0018) -#define coh901318_raw_tc_int_status2 (0x001c) -/* be_int_status - bus error interrupt status registers 32bit (r/-) */ -#define coh901318_be_int_status1 (0x0020) -#define coh901318_be_int_status2 (0x0024) -/* be_int_clear - bus error interrupt clear registers 32bit (-/w) */ -#define coh901318_be_int_clear1 (0x0028) -#define coh901318_be_int_clear2 (0x002c) -/* raw_be_int_status - raw term count interrupt status registers 32bit (r/-) */ -#define coh901318_raw_be_int_status1 (0x0030) -#define coh901318_raw_be_int_status2 (0x0034) - -/* - * cx_cfg - channel configuration registers 32bit (r/w) - */ -#define coh901318_cx_cfg (0x0100) -#define coh901318_cx_cfg_spacing (0x04) -/* channel enable activates tha dma job */ -#define coh901318_cx_cfg_ch_enable (0x00000001) -#define coh901318_cx_cfg_ch_disable (0x00000000) -/* request mode */ -#define coh901318_cx_cfg_rm_mask (0x00000006) -#define coh901318_cx_cfg_rm_memory_to_memory (0x0 << 1) -#define coh901318_cx_cfg_rm_primary_to_memory (0x1 << 1) -#define coh901318_cx_cfg_rm_memory_to_primary (0x1 << 1) -#define coh901318_cx_cfg_rm_primary_to_secondary (0x3 << 1) -#define coh901318_cx_cfg_rm_secondary_to_primary (0x3 << 1) -/* linked channel request field. rm must == 11 */ -#define coh901318_cx_cfg_lcrf_shift 3 -#define coh901318_cx_cfg_lcrf_mask (0x000001f8) -#define coh901318_cx_cfg_lcr_disable (0x00000000) -/* terminal counter interrupt request mask */ -#define coh901318_cx_cfg_tc_irq_enable (0x00000200) -#define coh901318_cx_cfg_tc_irq_disable (0x00000000) -/* bus error interrupt mask */ -#define coh901318_cx_cfg_be_irq_enable (0x00000400) -#define coh901318_cx_cfg_be_irq_disable (0x00000000) - -/* - * cx_stat - channel status registers 32bit (r/-) - */ -#define coh901318_cx_stat (0x0200) -#define coh901318_cx_stat_spacing (0x04) -#define coh901318_cx_stat_rbe_irq_ind (0x00000008) -#define coh901318_cx_stat_rtc_irq_ind (0x00000004) -#define coh901318_cx_stat_active (0x00000002) -#define coh901318_cx_stat_enabled (0x00000001) - -/* - * cx_ctrl - channel control registers 32bit (r/w) - */ -#define coh901318_cx_ctrl (0x0400) -#define coh901318_cx_ctrl_spacing (0x10) -/* transfer count enable */ -#define coh901318_cx_ctrl_tc_enable (0x00001000) -#define coh901318_cx_ctrl_tc_disable (0x00000000) -/* transfer count value 0 - 4095 */ -#define coh901318_cx_ctrl_tc_value_mask (0x00000fff) -/* burst count */ -#define coh901318_cx_ctrl_burst_count_mask (0x0000e000) -#define coh901318_cx_ctrl_burst_count_64_bytes (0x7 << 13) -#define coh901318_cx_ctrl_burst_count_48_bytes (0x6 << 13) -#define coh901318_cx_ctrl_burst_count_32_bytes (0x5 << 13) -#define coh901318_cx_ctrl_burst_count_16_bytes (0x4 << 13) -#define coh901318_cx_ctrl_burst_count_8_bytes (0x3 << 13) -#define coh901318_cx_ctrl_burst_count_4_bytes (0x2 << 13) -#define coh901318_cx_ctrl_burst_count_2_bytes (0x1 << 13) -#define coh901318_cx_ctrl_burst_count_1_byte (0x0 << 13) -/* source bus size */ -#define coh901318_cx_ctrl_src_bus_size_mask (0x00030000) -#define coh901318_cx_ctrl_src_bus_size_32_bits (0x2 << 16) -#define coh901318_cx_ctrl_src_bus_size_16_bits (0x1 << 16) -#define coh901318_cx_ctrl_src_bus_size_8_bits (0x0 << 16) -/* source address increment */ -#define coh901318_cx_ctrl_src_addr_inc_enable (0x00040000) -#define coh901318_cx_ctrl_src_addr_inc_disable (0x00000000) -/* destination bus size */ -#define coh901318_cx_ctrl_dst_bus_size_mask (0x00180000) -#define coh901318_cx_ctrl_dst_bus_size_32_bits (0x2 << 19) -#define coh901318_cx_ctrl_dst_bus_size_16_bits (0x1 << 19) -#define coh901318_cx_ctrl_dst_bus_size_8_bits (0x0 << 19) -/* destination address increment */ -#define coh901318_cx_ctrl_dst_addr_inc_enable (0x00200000) -#define coh901318_cx_ctrl_dst_addr_inc_disable (0x00000000) -/* master mode (master2 is only connected to msl) */ -#define coh901318_cx_ctrl_master_mode_mask (0x00c00000) -#define coh901318_cx_ctrl_master_mode_m2r_m1w (0x3 << 22) -#define coh901318_cx_ctrl_master_mode_m1r_m2w (0x2 << 22) -#define coh901318_cx_ctrl_master_mode_m2rw (0x1 << 22) -#define coh901318_cx_ctrl_master_mode_m1rw (0x0 << 22) -/* terminal count flag to per enable */ -#define coh901318_cx_ctrl_tcp_enable (0x01000000) -#define coh901318_cx_ctrl_tcp_disable (0x00000000) -/* terminal count flags to cpu enable */ -#define coh901318_cx_ctrl_tc_irq_enable (0x02000000) -#define coh901318_cx_ctrl_tc_irq_disable (0x00000000) -/* hand shake to peripheral */ -#define coh901318_cx_ctrl_hsp_enable (0x04000000) -#define coh901318_cx_ctrl_hsp_disable (0x00000000) -#define coh901318_cx_ctrl_hss_enable (0x08000000) -#define coh901318_cx_ctrl_hss_disable (0x00000000) -/* dma mode */ -#define coh901318_cx_ctrl_ddma_mask (0x30000000) -#define coh901318_cx_ctrl_ddma_legacy (0x0 << 28) -#define coh901318_cx_ctrl_ddma_demand_dma1 (0x1 << 28) -#define coh901318_cx_ctrl_ddma_demand_dma2 (0x2 << 28) -/* primary request data destination */ -#define coh901318_cx_ctrl_prdd_mask (0x40000000) -#define coh901318_cx_ctrl_prdd_dest (0x1 << 30) -#define coh901318_cx_ctrl_prdd_source (0x0 << 30) - -/* - * cx_src_addr - channel source address registers 32bit (r/w) - */ -#define coh901318_cx_src_addr (0x0404) -#define coh901318_cx_src_addr_spacing (0x10) - -/* - * cx_dst_addr - channel destination address registers 32bit r/w - */ -#define coh901318_cx_dst_addr (0x0408) -#define coh901318_cx_dst_addr_spacing (0x10) - -/* - * cx_lnk_addr - channel link address registers 32bit (r/w) - */ -#define coh901318_cx_lnk_addr (0x040c) -#define coh901318_cx_lnk_addr_spacing (0x10) -#define coh901318_cx_lnk_link_immediate (0x00000001) - -/** - * struct coh901318_params - parameters for dmac configuration - * @config: dma config register - * @ctrl_lli_last: dma control register for the last lli in the list - * @ctrl_lli: dma control register for an lli - * @ctrl_lli_chained: dma control register for a chained lli - */ -struct coh901318_params { - u32 config; - u32 ctrl_lli_last; - u32 ctrl_lli; - u32 ctrl_lli_chained; -}; - -/** - * struct coh_dma_channel - dma channel base - * @name: ascii name of dma channel - * @number: channel id number - * @desc_nbr_max: number of preallocated descriptors - * @priority_high: prio of channel, 0 low otherwise high. - * @param: configuration parameters - */ -struct coh_dma_channel { - const char name[32]; - const int number; - const int desc_nbr_max; - const int priority_high; - const struct coh901318_params param; -}; - -/** - * struct powersave - dma power save structure - * @lock: lock protecting data in this struct - * @started_channels: bit mask indicating active dma channels - */ -struct powersave { - spinlock_t lock; - u64 started_channels; -}; - -/* points out all dma slave channels. - * syntax is [a1, b1, a2, b2, .... ,-1,-1] - * select all channels from a to b, end of list is marked with -1,-1 - */ -static int dma_slave_channels[] = { - u300_dma_msl_tx_0, u300_dma_spi_rx, - u300_dma_uart1_tx, u300_dma_uart1_rx, -1, -1}; - -/* points out all dma memcpy channels. */ -static int dma_memcpy_channels[] = { - u300_dma_general_purpose_0, u300_dma_general_purpose_8, -1, -1}; - -#define flags_memcpy_config (coh901318_cx_cfg_ch_disable | \ - coh901318_cx_cfg_rm_memory_to_memory | \ - coh901318_cx_cfg_lcr_disable | \ - coh901318_cx_cfg_tc_irq_enable | \ - coh901318_cx_cfg_be_irq_enable) -#define flags_memcpy_lli_chained (coh901318_cx_ctrl_tc_enable | \ - coh901318_cx_ctrl_burst_count_32_bytes | \ - coh901318_cx_ctrl_src_bus_size_32_bits | \ - coh901318_cx_ctrl_src_addr_inc_enable | \ - coh901318_cx_ctrl_dst_bus_size_32_bits | \ - coh901318_cx_ctrl_dst_addr_inc_enable | \ - coh901318_cx_ctrl_master_mode_m1rw | \ - coh901318_cx_ctrl_tcp_disable | \ - coh901318_cx_ctrl_tc_irq_disable | \ - coh901318_cx_ctrl_hsp_disable | \ - coh901318_cx_ctrl_hss_disable | \ - coh901318_cx_ctrl_ddma_legacy | \ - coh901318_cx_ctrl_prdd_source) -#define flags_memcpy_lli (coh901318_cx_ctrl_tc_enable | \ - coh901318_cx_ctrl_burst_count_32_bytes | \ - coh901318_cx_ctrl_src_bus_size_32_bits | \ - coh901318_cx_ctrl_src_addr_inc_enable | \ - coh901318_cx_ctrl_dst_bus_size_32_bits | \ - coh901318_cx_ctrl_dst_addr_inc_enable | \ - coh901318_cx_ctrl_master_mode_m1rw | \ - coh901318_cx_ctrl_tcp_disable | \ - coh901318_cx_ctrl_tc_irq_disable | \ - coh901318_cx_ctrl_hsp_disable | \ - coh901318_cx_ctrl_hss_disable | \ - coh901318_cx_ctrl_ddma_legacy | \ - coh901318_cx_ctrl_prdd_source) -#define flags_memcpy_lli_last (coh901318_cx_ctrl_tc_enable | \ - coh901318_cx_ctrl_burst_count_32_bytes | \ - coh901318_cx_ctrl_src_bus_size_32_bits | \ - coh901318_cx_ctrl_src_addr_inc_enable | \ - coh901318_cx_ctrl_dst_bus_size_32_bits | \ - coh901318_cx_ctrl_dst_addr_inc_enable | \ - coh901318_cx_ctrl_master_mode_m1rw | \ - coh901318_cx_ctrl_tcp_disable | \ - coh901318_cx_ctrl_tc_irq_enable | \ - coh901318_cx_ctrl_hsp_disable | \ - coh901318_cx_ctrl_hss_disable | \ - coh901318_cx_ctrl_ddma_legacy | \ - coh901318_cx_ctrl_prdd_source) - -static const struct coh_dma_channel chan_config[u300_dma_channels] = { - { - .number = u300_dma_msl_tx_0, - .name = "msl tx 0", - .priority_high = 0, - }, - { - .number = u300_dma_msl_tx_1, - .name = "msl tx 1", - .priority_high = 0, - .param.config = coh901318_cx_cfg_ch_disable | - coh901318_cx_cfg_lcr_disable | - coh901318_cx_cfg_tc_irq_enable | - coh901318_cx_cfg_be_irq_enable, - .param.ctrl_lli_chained = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_enable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_disable | - coh901318_cx_ctrl_master_mode_m1r_m2w | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_source, - .param.ctrl_lli = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_enable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_disable | - coh901318_cx_ctrl_master_mode_m1r_m2w | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_source, - .param.ctrl_lli_last = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_enable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_disable | - coh901318_cx_ctrl_master_mode_m1r_m2w | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_source, - }, - { - .number = u300_dma_msl_tx_2, - .name = "msl tx 2", - .priority_high = 0, - .param.config = coh901318_cx_cfg_ch_disable | - coh901318_cx_cfg_lcr_disable | - coh901318_cx_cfg_tc_irq_enable | - coh901318_cx_cfg_be_irq_enable, - .param.ctrl_lli_chained = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_enable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_disable | - coh901318_cx_ctrl_master_mode_m1r_m2w | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_source, - .param.ctrl_lli = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_enable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_disable | - coh901318_cx_ctrl_master_mode_m1r_m2w | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_source, - .param.ctrl_lli_last = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_enable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_disable | - coh901318_cx_ctrl_master_mode_m1r_m2w | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_source, - .desc_nbr_max = 10, - }, - { - .number = u300_dma_msl_tx_3, - .name = "msl tx 3", - .priority_high = 0, - .param.config = coh901318_cx_cfg_ch_disable | - coh901318_cx_cfg_lcr_disable | - coh901318_cx_cfg_tc_irq_enable | - coh901318_cx_cfg_be_irq_enable, - .param.ctrl_lli_chained = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_enable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_disable | - coh901318_cx_ctrl_master_mode_m1r_m2w | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_source, - .param.ctrl_lli = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_enable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_disable | - coh901318_cx_ctrl_master_mode_m1r_m2w | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_source, - .param.ctrl_lli_last = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_enable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_disable | - coh901318_cx_ctrl_master_mode_m1r_m2w | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_source, - }, - { - .number = u300_dma_msl_tx_4, - .name = "msl tx 4", - .priority_high = 0, - .param.config = coh901318_cx_cfg_ch_disable | - coh901318_cx_cfg_lcr_disable | - coh901318_cx_cfg_tc_irq_enable | - coh901318_cx_cfg_be_irq_enable, - .param.ctrl_lli_chained = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_enable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_disable | - coh901318_cx_ctrl_master_mode_m1r_m2w | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_source, - .param.ctrl_lli = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_enable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_disable | - coh901318_cx_ctrl_master_mode_m1r_m2w | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_source, - .param.ctrl_lli_last = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_enable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_disable | - coh901318_cx_ctrl_master_mode_m1r_m2w | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_source, - }, - { - .number = u300_dma_msl_tx_5, - .name = "msl tx 5", - .priority_high = 0, - }, - { - .number = u300_dma_msl_tx_6, - .name = "msl tx 6", - .priority_high = 0, - }, - { - .number = u300_dma_msl_rx_0, - .name = "msl rx 0", - .priority_high = 0, - }, - { - .number = u300_dma_msl_rx_1, - .name = "msl rx 1", - .priority_high = 0, - .param.config = coh901318_cx_cfg_ch_disable | - coh901318_cx_cfg_lcr_disable | - coh901318_cx_cfg_tc_irq_enable | - coh901318_cx_cfg_be_irq_enable, - .param.ctrl_lli_chained = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_disable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_enable | - coh901318_cx_ctrl_master_mode_m2r_m1w | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_demand_dma1 | - coh901318_cx_ctrl_prdd_dest, - .param.ctrl_lli = 0, - .param.ctrl_lli_last = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_disable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_enable | - coh901318_cx_ctrl_master_mode_m2r_m1w | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_demand_dma1 | - coh901318_cx_ctrl_prdd_dest, - }, - { - .number = u300_dma_msl_rx_2, - .name = "msl rx 2", - .priority_high = 0, - .param.config = coh901318_cx_cfg_ch_disable | - coh901318_cx_cfg_lcr_disable | - coh901318_cx_cfg_tc_irq_enable | - coh901318_cx_cfg_be_irq_enable, - .param.ctrl_lli_chained = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_disable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_enable | - coh901318_cx_ctrl_master_mode_m2r_m1w | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_demand_dma1 | - coh901318_cx_ctrl_prdd_dest, - .param.ctrl_lli = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_disable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_enable | - coh901318_cx_ctrl_master_mode_m2r_m1w | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_demand_dma1 | - coh901318_cx_ctrl_prdd_dest, - .param.ctrl_lli_last = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_disable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_enable | - coh901318_cx_ctrl_master_mode_m2r_m1w | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_demand_dma1 | - coh901318_cx_ctrl_prdd_dest, - }, - { - .number = u300_dma_msl_rx_3, - .name = "msl rx 3", - .priority_high = 0, - .param.config = coh901318_cx_cfg_ch_disable | - coh901318_cx_cfg_lcr_disable | - coh901318_cx_cfg_tc_irq_enable | - coh901318_cx_cfg_be_irq_enable, - .param.ctrl_lli_chained = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_disable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_enable | - coh901318_cx_ctrl_master_mode_m2r_m1w | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_demand_dma1 | - coh901318_cx_ctrl_prdd_dest, - .param.ctrl_lli = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_disable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_enable | - coh901318_cx_ctrl_master_mode_m2r_m1w | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_demand_dma1 | - coh901318_cx_ctrl_prdd_dest, - .param.ctrl_lli_last = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_disable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_enable | - coh901318_cx_ctrl_master_mode_m2r_m1w | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_demand_dma1 | - coh901318_cx_ctrl_prdd_dest, - }, - { - .number = u300_dma_msl_rx_4, - .name = "msl rx 4", - .priority_high = 0, - .param.config = coh901318_cx_cfg_ch_disable | - coh901318_cx_cfg_lcr_disable | - coh901318_cx_cfg_tc_irq_enable | - coh901318_cx_cfg_be_irq_enable, - .param.ctrl_lli_chained = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_disable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_enable | - coh901318_cx_ctrl_master_mode_m2r_m1w | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_demand_dma1 | - coh901318_cx_ctrl_prdd_dest, - .param.ctrl_lli = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_disable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_enable | - coh901318_cx_ctrl_master_mode_m2r_m1w | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_demand_dma1 | - coh901318_cx_ctrl_prdd_dest, - .param.ctrl_lli_last = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_disable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_enable | - coh901318_cx_ctrl_master_mode_m2r_m1w | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_demand_dma1 | - coh901318_cx_ctrl_prdd_dest, - }, - { - .number = u300_dma_msl_rx_5, - .name = "msl rx 5", - .priority_high = 0, - .param.config = coh901318_cx_cfg_ch_disable | - coh901318_cx_cfg_lcr_disable | - coh901318_cx_cfg_tc_irq_enable | - coh901318_cx_cfg_be_irq_enable, - .param.ctrl_lli_chained = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_disable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_enable | - coh901318_cx_ctrl_master_mode_m2r_m1w | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_demand_dma1 | - coh901318_cx_ctrl_prdd_dest, - .param.ctrl_lli = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_disable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_enable | - coh901318_cx_ctrl_master_mode_m2r_m1w | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_demand_dma1 | - coh901318_cx_ctrl_prdd_dest, - .param.ctrl_lli_last = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_32_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_disable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_enable | - coh901318_cx_ctrl_master_mode_m2r_m1w | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_demand_dma1 | - coh901318_cx_ctrl_prdd_dest, - }, - { - .number = u300_dma_msl_rx_6, - .name = "msl rx 6", - .priority_high = 0, - }, - /* - * don't set up device address, burst count or size of src - * or dst bus for this peripheral - handled by primecell - * dma extension. - */ - { - .number = u300_dma_mmcsd_rx_tx, - .name = "mmcsd rx tx", - .priority_high = 0, - .param.config = coh901318_cx_cfg_ch_disable | - coh901318_cx_cfg_lcr_disable | - coh901318_cx_cfg_tc_irq_enable | - coh901318_cx_cfg_be_irq_enable, - .param.ctrl_lli_chained = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy, - .param.ctrl_lli = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy, - .param.ctrl_lli_last = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy, - - }, - { - .number = u300_dma_mspro_tx, - .name = "mspro tx", - .priority_high = 0, - }, - { - .number = u300_dma_mspro_rx, - .name = "mspro rx", - .priority_high = 0, - }, - /* - * don't set up device address, burst count or size of src - * or dst bus for this peripheral - handled by primecell - * dma extension. - */ - { - .number = u300_dma_uart0_tx, - .name = "uart0 tx", - .priority_high = 0, - .param.config = coh901318_cx_cfg_ch_disable | - coh901318_cx_cfg_lcr_disable | - coh901318_cx_cfg_tc_irq_enable | - coh901318_cx_cfg_be_irq_enable, - .param.ctrl_lli_chained = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy, - .param.ctrl_lli = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy, - .param.ctrl_lli_last = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy, - }, - { - .number = u300_dma_uart0_rx, - .name = "uart0 rx", - .priority_high = 0, - .param.config = coh901318_cx_cfg_ch_disable | - coh901318_cx_cfg_lcr_disable | - coh901318_cx_cfg_tc_irq_enable | - coh901318_cx_cfg_be_irq_enable, - .param.ctrl_lli_chained = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy, - .param.ctrl_lli = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy, - .param.ctrl_lli_last = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy, - }, - { - .number = u300_dma_apex_tx, - .name = "apex tx", - .priority_high = 0, - }, - { - .number = u300_dma_apex_rx, - .name = "apex rx", - .priority_high = 0, - }, - { - .number = u300_dma_pcm_i2s0_tx, - .name = "pcm i2s0 tx", - .priority_high = 1, - .param.config = coh901318_cx_cfg_ch_disable | - coh901318_cx_cfg_lcr_disable | - coh901318_cx_cfg_tc_irq_enable | - coh901318_cx_cfg_be_irq_enable, - .param.ctrl_lli_chained = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_16_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_enable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_disable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_source, - .param.ctrl_lli = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_16_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_enable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_disable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_source, - .param.ctrl_lli_last = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_16_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_enable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_disable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_source, - }, - { - .number = u300_dma_pcm_i2s0_rx, - .name = "pcm i2s0 rx", - .priority_high = 1, - .param.config = coh901318_cx_cfg_ch_disable | - coh901318_cx_cfg_lcr_disable | - coh901318_cx_cfg_tc_irq_enable | - coh901318_cx_cfg_be_irq_enable, - .param.ctrl_lli_chained = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_16_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_disable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_enable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_dest, - .param.ctrl_lli = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_16_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_disable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_enable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_dest, - .param.ctrl_lli_last = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_16_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_disable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_enable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_dest, - }, - { - .number = u300_dma_pcm_i2s1_tx, - .name = "pcm i2s1 tx", - .priority_high = 1, - .param.config = coh901318_cx_cfg_ch_disable | - coh901318_cx_cfg_lcr_disable | - coh901318_cx_cfg_tc_irq_enable | - coh901318_cx_cfg_be_irq_enable, - .param.ctrl_lli_chained = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_16_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_enable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_disable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_source, - .param.ctrl_lli = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_16_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_enable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_disable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_source, - .param.ctrl_lli_last = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_16_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_enable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_disable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_source, - }, - { - .number = u300_dma_pcm_i2s1_rx, - .name = "pcm i2s1 rx", - .priority_high = 1, - .param.config = coh901318_cx_cfg_ch_disable | - coh901318_cx_cfg_lcr_disable | - coh901318_cx_cfg_tc_irq_enable | - coh901318_cx_cfg_be_irq_enable, - .param.ctrl_lli_chained = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_16_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_disable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_enable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_dest, - .param.ctrl_lli = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_16_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_disable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_enable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_dest, - .param.ctrl_lli_last = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_burst_count_16_bytes | - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_src_addr_inc_disable | - coh901318_cx_ctrl_dst_bus_size_32_bits | - coh901318_cx_ctrl_dst_addr_inc_enable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_enable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy | - coh901318_cx_ctrl_prdd_dest, - }, - { - .number = u300_dma_xgam_cdi, - .name = "xgam cdi", - .priority_high = 0, - }, - { - .number = u300_dma_xgam_pdi, - .name = "xgam pdi", - .priority_high = 0, - }, - /* - * don't set up device address, burst count or size of src - * or dst bus for this peripheral - handled by primecell - * dma extension. - */ - { - .number = u300_dma_spi_tx, - .name = "spi tx", - .priority_high = 0, - .param.config = coh901318_cx_cfg_ch_disable | - coh901318_cx_cfg_lcr_disable | - coh901318_cx_cfg_tc_irq_enable | - coh901318_cx_cfg_be_irq_enable, - .param.ctrl_lli_chained = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy, - .param.ctrl_lli = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy, - .param.ctrl_lli_last = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy, - }, - { - .number = u300_dma_spi_rx, - .name = "spi rx", - .priority_high = 0, - .param.config = coh901318_cx_cfg_ch_disable | - coh901318_cx_cfg_lcr_disable | - coh901318_cx_cfg_tc_irq_enable | - coh901318_cx_cfg_be_irq_enable, - .param.ctrl_lli_chained = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_disable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy, - .param.ctrl_lli = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy, - .param.ctrl_lli_last = 0 | - coh901318_cx_ctrl_tc_enable | - coh901318_cx_ctrl_master_mode_m1rw | - coh901318_cx_ctrl_tcp_disable | - coh901318_cx_ctrl_tc_irq_enable | - coh901318_cx_ctrl_hsp_enable | - coh901318_cx_ctrl_hss_disable | - coh901318_cx_ctrl_ddma_legacy, - - }, - { - .number = u300_dma_general_purpose_0, - .name = "general 00", - .priority_high = 0, - - .param.config = flags_memcpy_config, - .param.ctrl_lli_chained = flags_memcpy_lli_chained, - .param.ctrl_lli = flags_memcpy_lli, - .param.ctrl_lli_last = flags_memcpy_lli_last, - }, - { - .number = u300_dma_general_purpose_1, - .name = "general 01", - .priority_high = 0, - - .param.config = flags_memcpy_config, - .param.ctrl_lli_chained = flags_memcpy_lli_chained, - .param.ctrl_lli = flags_memcpy_lli, - .param.ctrl_lli_last = flags_memcpy_lli_last, - }, - { - .number = u300_dma_general_purpose_2, - .name = "general 02", - .priority_high = 0, - - .param.config = flags_memcpy_config, - .param.ctrl_lli_chained = flags_memcpy_lli_chained, - .param.ctrl_lli = flags_memcpy_lli, - .param.ctrl_lli_last = flags_memcpy_lli_last, - }, - { - .number = u300_dma_general_purpose_3, - .name = "general 03", - .priority_high = 0, - - .param.config = flags_memcpy_config, - .param.ctrl_lli_chained = flags_memcpy_lli_chained, - .param.ctrl_lli = flags_memcpy_lli, - .param.ctrl_lli_last = flags_memcpy_lli_last, - }, - { - .number = u300_dma_general_purpose_4, - .name = "general 04", - .priority_high = 0, - - .param.config = flags_memcpy_config, - .param.ctrl_lli_chained = flags_memcpy_lli_chained, - .param.ctrl_lli = flags_memcpy_lli, - .param.ctrl_lli_last = flags_memcpy_lli_last, - }, - { - .number = u300_dma_general_purpose_5, - .name = "general 05", - .priority_high = 0, - - .param.config = flags_memcpy_config, - .param.ctrl_lli_chained = flags_memcpy_lli_chained, - .param.ctrl_lli = flags_memcpy_lli, - .param.ctrl_lli_last = flags_memcpy_lli_last, - }, - { - .number = u300_dma_general_purpose_6, - .name = "general 06", - .priority_high = 0, - - .param.config = flags_memcpy_config, - .param.ctrl_lli_chained = flags_memcpy_lli_chained, - .param.ctrl_lli = flags_memcpy_lli, - .param.ctrl_lli_last = flags_memcpy_lli_last, - }, - { - .number = u300_dma_general_purpose_7, - .name = "general 07", - .priority_high = 0, - - .param.config = flags_memcpy_config, - .param.ctrl_lli_chained = flags_memcpy_lli_chained, - .param.ctrl_lli = flags_memcpy_lli, - .param.ctrl_lli_last = flags_memcpy_lli_last, - }, - { - .number = u300_dma_general_purpose_8, - .name = "general 08", - .priority_high = 0, - - .param.config = flags_memcpy_config, - .param.ctrl_lli_chained = flags_memcpy_lli_chained, - .param.ctrl_lli = flags_memcpy_lli, - .param.ctrl_lli_last = flags_memcpy_lli_last, - }, - { - .number = u300_dma_uart1_tx, - .name = "uart1 tx", - .priority_high = 0, - }, - { - .number = u300_dma_uart1_rx, - .name = "uart1 rx", - .priority_high = 0, - } -}; - -#define cohc_2_dev(cohc) (&cohc->chan.dev->device) - -#ifdef verbose_debug -#define coh_dbg(x) ({ if (1) x; 0; }) -#else -#define coh_dbg(x) ({ if (0) x; 0; }) -#endif - -struct coh901318_desc { - struct dma_async_tx_descriptor desc; - struct list_head node; - struct scatterlist *sg; - unsigned int sg_len; - struct coh901318_lli *lli; - enum dma_transfer_direction dir; - unsigned long flags; - u32 head_config; - u32 head_ctrl; -}; - -struct coh901318_base { - struct device *dev; - void __iomem *virtbase; - unsigned int irq; - struct coh901318_pool pool; - struct powersave pm; - struct dma_device dma_slave; - struct dma_device dma_memcpy; - struct coh901318_chan *chans; -}; - -struct coh901318_chan { - spinlock_t lock; - int allocated; - int id; - int stopped; - - struct work_struct free_work; - struct dma_chan chan; - - struct tasklet_struct tasklet; - - struct list_head active; - struct list_head queue; - struct list_head free; - - unsigned long nbr_active_done; - unsigned long busy; - - struct dma_slave_config config; - u32 addr; - u32 ctrl; - - struct coh901318_base *base; -}; - -static void coh901318_list_print(struct coh901318_chan *cohc, - struct coh901318_lli *lli) -{ - struct coh901318_lli *l = lli; - int i = 0; - - while (l) { - dev_vdbg(cohc_2_dev(cohc), "i %d, lli %p, ctrl 0x%x, src %pad" - ", dst %pad, link %pad virt_link_addr 0x%p ", - i, l, l->control, &l->src_addr, &l->dst_addr, - &l->link_addr, l->virt_link_addr); - i++; - l = l->virt_link_addr; - } -} - -#ifdef config_debug_fs - -#define coh901318_debugfs_assign(x, y) (x = y) - -static struct coh901318_base *debugfs_dma_base; -static struct dentry *dma_dentry; - -static ssize_t coh901318_debugfs_read(struct file *file, char __user *buf, - size_t count, loff_t *f_pos) -{ - u64 started_channels = debugfs_dma_base->pm.started_channels; - int pool_count = debugfs_dma_base->pool.debugfs_pool_counter; - char *dev_buf; - char *tmp; - int ret; - int i; - - dev_buf = kmalloc(4*1024, gfp_kernel); - if (dev_buf == null) - return -enomem; - tmp = dev_buf; - - tmp += sprintf(tmp, "dma -- enabled dma channels "); - - for (i = 0; i < u300_dma_channels; i++) { - if (started_channels & (1ull << i)) - tmp += sprintf(tmp, "channel %d ", i); - } - - tmp += sprintf(tmp, "pool alloc nbr %d ", pool_count); - - ret = simple_read_from_buffer(buf, count, f_pos, dev_buf, - tmp - dev_buf); - kfree(dev_buf); - return ret; -} - -static const struct file_operations coh901318_debugfs_status_operations = { - .open = simple_open, - .read = coh901318_debugfs_read, - .llseek = default_llseek, -}; - - -static int __init init_coh901318_debugfs(void) -{ - - dma_dentry = debugfs_create_dir("dma", null); - - debugfs_create_file("status", s_ifreg | s_irugo, dma_dentry, null, - &coh901318_debugfs_status_operations); - return 0; -} - -static void __exit exit_coh901318_debugfs(void) -{ - debugfs_remove_recursive(dma_dentry); -} - -module_init(init_coh901318_debugfs); -module_exit(exit_coh901318_debugfs); -#else - -#define coh901318_debugfs_assign(x, y) - -#endif /* config_debug_fs */ - -static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan) -{ - return container_of(chan, struct coh901318_chan, chan); -} - -static int coh901318_dma_set_runtimeconfig(struct dma_chan *chan, - struct dma_slave_config *config, - enum dma_transfer_direction direction); - -static inline const struct coh901318_params * -cohc_chan_param(struct coh901318_chan *cohc) -{ - return &chan_config[cohc->id].param; -} - -static inline const struct coh_dma_channel * -cohc_chan_conf(struct coh901318_chan *cohc) -{ - return &chan_config[cohc->id]; -} - -static void enable_powersave(struct coh901318_chan *cohc) -{ - unsigned long flags; - struct powersave *pm = &cohc->base->pm; - - spin_lock_irqsave(&pm->lock, flags); - - pm->started_channels &= ~(1ull << cohc->id); - - spin_unlock_irqrestore(&pm->lock, flags); -} -static void disable_powersave(struct coh901318_chan *cohc) -{ - unsigned long flags; - struct powersave *pm = &cohc->base->pm; - - spin_lock_irqsave(&pm->lock, flags); - - pm->started_channels |= (1ull << cohc->id); - - spin_unlock_irqrestore(&pm->lock, flags); -} - -static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control) -{ - int channel = cohc->id; - void __iomem *virtbase = cohc->base->virtbase; - - writel(control, - virtbase + coh901318_cx_ctrl + - coh901318_cx_ctrl_spacing * channel); - return 0; -} - -static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf) -{ - int channel = cohc->id; - void __iomem *virtbase = cohc->base->virtbase; - - writel(conf, - virtbase + coh901318_cx_cfg + - coh901318_cx_cfg_spacing*channel); - return 0; -} - - -static int coh901318_start(struct coh901318_chan *cohc) -{ - u32 val; - int channel = cohc->id; - void __iomem *virtbase = cohc->base->virtbase; - - disable_powersave(cohc); - - val = readl(virtbase + coh901318_cx_cfg + - coh901318_cx_cfg_spacing * channel); - - /* enable channel */ - val |= coh901318_cx_cfg_ch_enable; - writel(val, virtbase + coh901318_cx_cfg + - coh901318_cx_cfg_spacing * channel); - - return 0; -} - -static int coh901318_prep_linked_list(struct coh901318_chan *cohc, - struct coh901318_lli *lli) -{ - int channel = cohc->id; - void __iomem *virtbase = cohc->base->virtbase; - - bug_on(readl(virtbase + coh901318_cx_stat + - coh901318_cx_stat_spacing*channel) & - coh901318_cx_stat_active); - - writel(lli->src_addr, - virtbase + coh901318_cx_src_addr + - coh901318_cx_src_addr_spacing * channel); - - writel(lli->dst_addr, virtbase + - coh901318_cx_dst_addr + - coh901318_cx_dst_addr_spacing * channel); - - writel(lli->link_addr, virtbase + coh901318_cx_lnk_addr + - coh901318_cx_lnk_addr_spacing * channel); - - writel(lli->control, virtbase + coh901318_cx_ctrl + - coh901318_cx_ctrl_spacing * channel); - - return 0; -} - -static struct coh901318_desc * -coh901318_desc_get(struct coh901318_chan *cohc) -{ - struct coh901318_desc *desc; - - if (list_empty(&cohc->free)) { - /* alloc new desc because we're out of used ones - * todo: alloc a pile of descs instead of just one, - * avoid many small allocations. - */ - desc = kzalloc(sizeof(struct coh901318_desc), gfp_nowait); - if (desc == null) - goto out; - init_list_head(&desc->node); - dma_async_tx_descriptor_init(&desc->desc, &cohc->chan); - } else { - /* reuse an old desc. */ - desc = list_first_entry(&cohc->free, - struct coh901318_desc, - node); - list_del(&desc->node); - /* initialize it a bit so it's not insane */ - desc->sg = null; - desc->sg_len = 0; - desc->desc.callback = null; - desc->desc.callback_param = null; - } - - out: - return desc; -} - -static void -coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd) -{ - list_add_tail(&cohd->node, &cohc->free); -} - -/* call with irq lock held */ -static void -coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc) -{ - list_add_tail(&desc->node, &cohc->active); -} - -static struct coh901318_desc * -coh901318_first_active_get(struct coh901318_chan *cohc) -{ - return list_first_entry_or_null(&cohc->active, struct coh901318_desc, - node); -} - -static void -coh901318_desc_remove(struct coh901318_desc *cohd) -{ - list_del(&cohd->node); -} - -static void -coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc) -{ - list_add_tail(&desc->node, &cohc->queue); -} - -static struct coh901318_desc * -coh901318_first_queued(struct coh901318_chan *cohc) -{ - return list_first_entry_or_null(&cohc->queue, struct coh901318_desc, - node); -} - -static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli) -{ - struct coh901318_lli *lli = in_lli; - u32 bytes = 0; - - while (lli) { - bytes += lli->control & coh901318_cx_ctrl_tc_value_mask; - lli = lli->virt_link_addr; - } - return bytes; -} - -/* - * get the number of bytes left to transfer on this channel, - * it is unwise to call this before stopping the channel for - * absolute measures, but for a rough guess you can still call - * it. - */ -static u32 coh901318_get_bytes_left(struct dma_chan *chan) -{ - struct coh901318_chan *cohc = to_coh901318_chan(chan); - struct coh901318_desc *cohd; - struct list_head *pos; - unsigned long flags; - u32 left = 0; - int i = 0; - - spin_lock_irqsave(&cohc->lock, flags); - - /* - * if there are many queued jobs, we iterate and add the - * size of them all. we take a special look on the first - * job though, since it is probably active. - */ - list_for_each(pos, &cohc->active) { - /* - * the first job in the list will be working on the - * hardware. the job can be stopped but still active, - * so that the transfer counter is somewhere inside - * the buffer. - */ - cohd = list_entry(pos, struct coh901318_desc, node); - - if (i == 0) { - struct coh901318_lli *lli; - dma_addr_t ladd; - - /* read current transfer count value */ - left = readl(cohc->base->virtbase + - coh901318_cx_ctrl + - coh901318_cx_ctrl_spacing * cohc->id) & - coh901318_cx_ctrl_tc_value_mask; - - /* see if the transfer is linked... */ - ladd = readl(cohc->base->virtbase + - coh901318_cx_lnk_addr + - coh901318_cx_lnk_addr_spacing * - cohc->id) & - ~coh901318_cx_lnk_link_immediate; - /* single transaction */ - if (!ladd) - continue; - - /* - * linked transaction, follow the lli, find the - * currently processing lli, and proceed to the next - */ - lli = cohd->lli; - while (lli && lli->link_addr != ladd) - lli = lli->virt_link_addr; - - if (lli) - lli = lli->virt_link_addr; - - /* - * follow remaining lli links around to count the total - * number of bytes left - */ - left += coh901318_get_bytes_in_lli(lli); - } else { - left += coh901318_get_bytes_in_lli(cohd->lli); - } - i++; - } - - /* also count bytes in the queued jobs */ - list_for_each(pos, &cohc->queue) { - cohd = list_entry(pos, struct coh901318_desc, node); - left += coh901318_get_bytes_in_lli(cohd->lli); - } - - spin_unlock_irqrestore(&cohc->lock, flags); - - return left; -} - -/* - * pauses a transfer without losing data. enables power save. - * use this function in conjunction with coh901318_resume. - */ -static int coh901318_pause(struct dma_chan *chan) -{ - u32 val; - unsigned long flags; - struct coh901318_chan *cohc = to_coh901318_chan(chan); - int channel = cohc->id; - void __iomem *virtbase = cohc->base->virtbase; - - spin_lock_irqsave(&cohc->lock, flags); - - /* disable channel in hw */ - val = readl(virtbase + coh901318_cx_cfg + - coh901318_cx_cfg_spacing * channel); - - /* stopping infinite transfer */ - if ((val & coh901318_cx_ctrl_tc_enable) == 0 && - (val & coh901318_cx_cfg_ch_enable)) - cohc->stopped = 1; - - - val &= ~coh901318_cx_cfg_ch_enable; - /* enable twice, hw bug work around */ - writel(val, virtbase + coh901318_cx_cfg + - coh901318_cx_cfg_spacing * channel); - writel(val, virtbase + coh901318_cx_cfg + - coh901318_cx_cfg_spacing * channel); - - /* spin-wait for it to actually go inactive */ - while (readl(virtbase + coh901318_cx_stat+coh901318_cx_stat_spacing * - channel) & coh901318_cx_stat_active) - cpu_relax(); - - /* check if we stopped an active job */ - if ((readl(virtbase + coh901318_cx_ctrl+coh901318_cx_ctrl_spacing * - channel) & coh901318_cx_ctrl_tc_value_mask) > 0) - cohc->stopped = 1; - - enable_powersave(cohc); - - spin_unlock_irqrestore(&cohc->lock, flags); - return 0; -} - -/* resumes a transfer that has been stopped via 300_dma_stop(..). - power save is handled. -*/ -static int coh901318_resume(struct dma_chan *chan) -{ - u32 val; - unsigned long flags; - struct coh901318_chan *cohc = to_coh901318_chan(chan); - int channel = cohc->id; - - spin_lock_irqsave(&cohc->lock, flags); - - disable_powersave(cohc); - - if (cohc->stopped) { - /* enable channel in hw */ - val = readl(cohc->base->virtbase + coh901318_cx_cfg + - coh901318_cx_cfg_spacing * channel); - - val |= coh901318_cx_cfg_ch_enable; - - writel(val, cohc->base->virtbase + coh901318_cx_cfg + - coh901318_cx_cfg_spacing*channel); - - cohc->stopped = 0; - } - - spin_unlock_irqrestore(&cohc->lock, flags); - return 0; -} - -bool coh901318_filter_id(struct dma_chan *chan, void *chan_id) -{ - unsigned long ch_nr = (unsigned long) chan_id; - - if (ch_nr == to_coh901318_chan(chan)->id) - return true; - - return false; -} -export_symbol(coh901318_filter_id); - -struct coh901318_filter_args { - struct coh901318_base *base; - unsigned int ch_nr; -}; - -static bool coh901318_filter_base_and_id(struct dma_chan *chan, void *data) -{ - struct coh901318_filter_args *args = data; - - if (&args->base->dma_slave == chan->device && - args->ch_nr == to_coh901318_chan(chan)->id) - return true; - - return false; -} - -static struct dma_chan *coh901318_xlate(struct of_phandle_args *dma_spec, - struct of_dma *ofdma) -{ - struct coh901318_filter_args args = { - .base = ofdma->of_dma_data, - .ch_nr = dma_spec->args[0], - }; - dma_cap_mask_t cap; - dma_cap_zero(cap); - dma_cap_set(dma_slave, cap); - - return dma_request_channel(cap, coh901318_filter_base_and_id, &args); -} -/* - * dma channel allocation - */ -static int coh901318_config(struct coh901318_chan *cohc, - struct coh901318_params *param) -{ - const struct coh901318_params *p; - int channel = cohc->id; - void __iomem *virtbase = cohc->base->virtbase; - - if (param) - p = param; - else - p = cohc_chan_param(cohc); - - /* clear any pending be or tc interrupt */ - if (channel < 32) { - writel(1 << channel, virtbase + coh901318_be_int_clear1); - writel(1 << channel, virtbase + coh901318_tc_int_clear1); - } else { - writel(1 << (channel - 32), virtbase + - coh901318_be_int_clear2); - writel(1 << (channel - 32), virtbase + - coh901318_tc_int_clear2); - } - - coh901318_set_conf(cohc, p->config); - coh901318_set_ctrl(cohc, p->ctrl_lli_last); - - return 0; -} - -/* must lock when calling this function - * start queued jobs, if any - * todo: start all queued jobs in one go - * - * returns descriptor if queued job is started otherwise null. - * if the queue is empty null is returned. - */ -static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc) -{ - struct coh901318_desc *cohd; - - /* - * start queued jobs, if any - * todo: transmit all queued jobs in one go - */ - cohd = coh901318_first_queued(cohc); - - if (cohd != null) { - /* remove from queue */ - coh901318_desc_remove(cohd); - /* initiate dma job */ - cohc->busy = 1; - - coh901318_desc_submit(cohc, cohd); - - /* program the transaction head */ - coh901318_set_conf(cohc, cohd->head_config); - coh901318_set_ctrl(cohc, cohd->head_ctrl); - coh901318_prep_linked_list(cohc, cohd->lli); - - /* start dma job on this channel */ - coh901318_start(cohc); - - } - - return cohd; -} - -/* - * this tasklet is called from the interrupt handler to - * handle each descriptor (dma job) that is sent to a channel. - */ -static void dma_tasklet(struct tasklet_struct *t) -{ - struct coh901318_chan *cohc = from_tasklet(cohc, t, tasklet); - struct coh901318_desc *cohd_fin; - unsigned long flags; - struct dmaengine_desc_callback cb; - - dev_vdbg(cohc_2_dev(cohc), "[%s] chan_id %d" - " nbr_active_done %ld ", __func__, - cohc->id, cohc->nbr_active_done); - - spin_lock_irqsave(&cohc->lock, flags); - - /* get first active descriptor entry from list */ - cohd_fin = coh901318_first_active_get(cohc); - - if (cohd_fin == null) - goto err; - - /* locate callback to client */ - dmaengine_desc_get_callback(&cohd_fin->desc, &cb); - - /* sign this job as completed on the channel */ - dma_cookie_complete(&cohd_fin->desc); - - /* release the lli allocation and remove the descriptor */ - coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli); - - /* return desc to free-list */ - coh901318_desc_remove(cohd_fin); - coh901318_desc_free(cohc, cohd_fin); - - spin_unlock_irqrestore(&cohc->lock, flags); - - /* call the callback when we're done */ - dmaengine_desc_callback_invoke(&cb, null); - - spin_lock_irqsave(&cohc->lock, flags); - - /* - * if another interrupt fired while the tasklet was scheduling, - * we don't get called twice, so we have this number of active - * counter that keep track of the number of irqs expected to - * be handled for this channel. if there happen to be more than - * one irq to be ack:ed, we simply schedule this tasklet again. - */ - cohc->nbr_active_done--; - if (cohc->nbr_active_done) { - dev_dbg(cohc_2_dev(cohc), "scheduling tasklet again, new irqs " - "came in while we were scheduling this tasklet "); - if (cohc_chan_conf(cohc)->priority_high) - tasklet_hi_schedule(&cohc->tasklet); - else - tasklet_schedule(&cohc->tasklet); - } - - spin_unlock_irqrestore(&cohc->lock, flags); - - return; - - err: - spin_unlock_irqrestore(&cohc->lock, flags); - dev_err(cohc_2_dev(cohc), "[%s] no active dma desc ", __func__); -} - - -/* called from interrupt context */ -static void dma_tc_handle(struct coh901318_chan *cohc) -{ - /* - * if the channel is not allocated, then we shouldn't have - * any tc interrupts on it. - */ - if (!cohc->allocated) { - dev_err(cohc_2_dev(cohc), "spurious interrupt from " - "unallocated channel "); - return; - } - - /* - * when we reach this point, at least one queue item - * should have been moved over from cohc->queue to - * cohc->active and run to completion, that is why we're - * getting a terminal count interrupt is it not? - * if you get this bug() the most probable cause is that - * the individual nodes in the lli chain have irq enabled, - * so check your platform config for lli chain ctrl. - */ - bug_on(list_empty(&cohc->active)); - - cohc->nbr_active_done++; - - /* - * this attempt to take a job from cohc->queue, put it - * into cohc->active and start it. - */ - if (coh901318_queue_start(cohc) == null) - cohc->busy = 0; - - /* - * this tasklet will remove items from cohc->active - * and thus terminates them. - */ - if (cohc_chan_conf(cohc)->priority_high) - tasklet_hi_schedule(&cohc->tasklet); - else - tasklet_schedule(&cohc->tasklet); -} - - -static irqreturn_t dma_irq_handler(int irq, void *dev_id) -{ - u32 status1; - u32 status2; - int i; - int ch; - struct coh901318_base *base = dev_id; - struct coh901318_chan *cohc; - void __iomem *virtbase = base->virtbase; - - status1 = readl(virtbase + coh901318_int_status1); - status2 = readl(virtbase + coh901318_int_status2); - - if (unlikely(status1 == 0 && status2 == 0)) { - dev_warn(base->dev, "spurious dma irq from no channel! "); - return irq_handled; - } - - /* todo: consider handle irq in tasklet here to - * minimize interrupt latency */ - - /* check the first 32 dma channels for irq */ - while (status1) { - /* find first bit set, return as a number. */ - i = ffs(status1) - 1; - ch = i; - - cohc = &base->chans[ch]; - spin_lock(&cohc->lock); - - /* mask off this bit */ - status1 &= ~(1 << i); - /* check the individual channel bits */ - if (test_bit(i, virtbase + coh901318_be_int_status1)) { - dev_crit(cohc_2_dev(cohc), - "dma bus error on channel %d! ", ch); - bug_on(1); - /* clear be interrupt */ - __set_bit(i, virtbase + coh901318_be_int_clear1); - } else { - /* caused by tc, really? */ - if (unlikely(!test_bit(i, virtbase + - coh901318_tc_int_status1))) { - dev_warn(cohc_2_dev(cohc), - "ignoring interrupt not caused by terminal count on channel %d ", ch); - /* clear tc interrupt */ - bug_on(1); - __set_bit(i, virtbase + coh901318_tc_int_clear1); - } else { - /* enable powersave if transfer has finished */ - if (!(readl(virtbase + coh901318_cx_stat + - coh901318_cx_stat_spacing*ch) & - coh901318_cx_stat_enabled)) { - enable_powersave(cohc); - } - - /* must clear tc interrupt before calling - * dma_tc_handle - * in case tc_handle initiate a new dma job - */ - __set_bit(i, virtbase + coh901318_tc_int_clear1); - - dma_tc_handle(cohc); - } - } - spin_unlock(&cohc->lock); - } - - /* check the remaining 32 dma channels for irq */ - while (status2) { - /* find first bit set, return as a number. */ - i = ffs(status2) - 1; - ch = i + 32; - cohc = &base->chans[ch]; - spin_lock(&cohc->lock); - - /* mask off this bit */ - status2 &= ~(1 << i); - /* check the individual channel bits */ - if (test_bit(i, virtbase + coh901318_be_int_status2)) { - dev_crit(cohc_2_dev(cohc), - "dma bus error on channel %d! ", ch); - /* clear be interrupt */ - bug_on(1); - __set_bit(i, virtbase + coh901318_be_int_clear2); - } else { - /* caused by tc, really? */ - if (unlikely(!test_bit(i, virtbase + - coh901318_tc_int_status2))) { - dev_warn(cohc_2_dev(cohc), - "ignoring interrupt not caused by terminal count on channel %d ", ch); - /* clear tc interrupt */ - __set_bit(i, virtbase + coh901318_tc_int_clear2); - bug_on(1); - } else { - /* enable powersave if transfer has finished */ - if (!(readl(virtbase + coh901318_cx_stat + - coh901318_cx_stat_spacing*ch) & - coh901318_cx_stat_enabled)) { - enable_powersave(cohc); - } - /* must clear tc interrupt before calling - * dma_tc_handle - * in case tc_handle initiate a new dma job - */ - __set_bit(i, virtbase + coh901318_tc_int_clear2); - - dma_tc_handle(cohc); - } - } - spin_unlock(&cohc->lock); - } - - return irq_handled; -} - -static int coh901318_terminate_all(struct dma_chan *chan) -{ - unsigned long flags; - struct coh901318_chan *cohc = to_coh901318_chan(chan); - struct coh901318_desc *cohd; - void __iomem *virtbase = cohc->base->virtbase; - - /* the remainder of this function terminates the transfer */ - coh901318_pause(chan); - spin_lock_irqsave(&cohc->lock, flags); - - /* clear any pending be or tc interrupt */ - if (cohc->id < 32) { - writel(1 << cohc->id, virtbase + coh901318_be_int_clear1); - writel(1 << cohc->id, virtbase + coh901318_tc_int_clear1); - } else { - writel(1 << (cohc->id - 32), virtbase + - coh901318_be_int_clear2); - writel(1 << (cohc->id - 32), virtbase + - coh901318_tc_int_clear2); - } - - enable_powersave(cohc); - - while ((cohd = coh901318_first_active_get(cohc))) { - /* release the lli allocation*/ - coh901318_lli_free(&cohc->base->pool, &cohd->lli); - - /* return desc to free-list */ - coh901318_desc_remove(cohd); - coh901318_desc_free(cohc, cohd); - } - - while ((cohd = coh901318_first_queued(cohc))) { - /* release the lli allocation*/ - coh901318_lli_free(&cohc->base->pool, &cohd->lli); - - /* return desc to free-list */ - coh901318_desc_remove(cohd); - coh901318_desc_free(cohc, cohd); - } - - - cohc->nbr_active_done = 0; - cohc->busy = 0; - - spin_unlock_irqrestore(&cohc->lock, flags); - - return 0; -} - -static int coh901318_alloc_chan_resources(struct dma_chan *chan) -{ - struct coh901318_chan *cohc = to_coh901318_chan(chan); - unsigned long flags; - - dev_vdbg(cohc_2_dev(cohc), "[%s] dma channel %d ", - __func__, cohc->id); - - if (chan->client_count > 1) - return -ebusy; - - spin_lock_irqsave(&cohc->lock, flags); - - coh901318_config(cohc, null); - - cohc->allocated = 1; - dma_cookie_init(chan); - - spin_unlock_irqrestore(&cohc->lock, flags); - - return 1; -} - -static void -coh901318_free_chan_resources(struct dma_chan *chan) -{ - struct coh901318_chan *cohc = to_coh901318_chan(chan); - int channel = cohc->id; - unsigned long flags; - - spin_lock_irqsave(&cohc->lock, flags); - - /* disable hw */ - writel(0x00000000u, cohc->base->virtbase + coh901318_cx_cfg + - coh901318_cx_cfg_spacing*channel); - writel(0x00000000u, cohc->base->virtbase + coh901318_cx_ctrl + - coh901318_cx_ctrl_spacing*channel); - - cohc->allocated = 0; - - spin_unlock_irqrestore(&cohc->lock, flags); - - coh901318_terminate_all(chan); -} - - -static dma_cookie_t -coh901318_tx_submit(struct dma_async_tx_descriptor *tx) -{ - struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc, - desc); - struct coh901318_chan *cohc = to_coh901318_chan(tx->chan); - unsigned long flags; - dma_cookie_t cookie; - - spin_lock_irqsave(&cohc->lock, flags); - cookie = dma_cookie_assign(tx); - - coh901318_desc_queue(cohc, cohd); - - spin_unlock_irqrestore(&cohc->lock, flags); - - return cookie; -} - -static struct dma_async_tx_descriptor * -coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, - size_t size, unsigned long flags) -{ - struct coh901318_lli *lli; - struct coh901318_desc *cohd; - unsigned long flg; - struct coh901318_chan *cohc = to_coh901318_chan(chan); - int lli_len; - u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last; - int ret; - - spin_lock_irqsave(&cohc->lock, flg); - - dev_vdbg(cohc_2_dev(cohc), - "[%s] channel %d src %pad dest %pad size %zu ", - __func__, cohc->id, &src, &dest, size); - - if (flags & dma_prep_interrupt) - /* trigger interrupt after last lli */ - ctrl_last |= coh901318_cx_ctrl_tc_irq_enable; - - lli_len = size >> max_dma_packet_size_shift; - if ((lli_len << max_dma_packet_size_shift) < size) - lli_len++; - - lli = coh901318_lli_alloc(&cohc->base->pool, lli_len); - - if (lli == null) - goto err; - - ret = coh901318_lli_fill_memcpy( - &cohc->base->pool, lli, src, size, dest, - cohc_chan_param(cohc)->ctrl_lli_chained, - ctrl_last); - if (ret) - goto err; - - coh_dbg(coh901318_list_print(cohc, lli)); - - /* pick a descriptor to handle this transfer */ - cohd = coh901318_desc_get(cohc); - cohd->lli = lli; - cohd->flags = flags; - cohd->desc.tx_submit = coh901318_tx_submit; - - spin_unlock_irqrestore(&cohc->lock, flg); - - return &cohd->desc; - err: - spin_unlock_irqrestore(&cohc->lock, flg); - return null; -} - -static struct dma_async_tx_descriptor * -coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, - unsigned int sg_len, enum dma_transfer_direction direction, - unsigned long flags, void *context) -{ - struct coh901318_chan *cohc = to_coh901318_chan(chan); - struct coh901318_lli *lli; - struct coh901318_desc *cohd; - const struct coh901318_params *params; - struct scatterlist *sg; - int len = 0; - int size; - int i; - u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained; - u32 ctrl = cohc_chan_param(cohc)->ctrl_lli; - u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last; - u32 config; - unsigned long flg; - int ret; - - if (!sgl) - goto out; - if (sg_dma_len(sgl) == 0) - goto out; - - spin_lock_irqsave(&cohc->lock, flg); - - dev_vdbg(cohc_2_dev(cohc), "[%s] sg_len %d dir %d ", - __func__, sg_len, direction); - - if (flags & dma_prep_interrupt) - /* trigger interrupt after last lli */ - ctrl_last |= coh901318_cx_ctrl_tc_irq_enable; - - params = cohc_chan_param(cohc); - config = params->config; - /* - * add runtime-specific control on top, make - * sure the bits you set per peripheral channel are - * cleared in the default config from the platform. - */ - ctrl_chained |= cohc->ctrl; - ctrl_last |= cohc->ctrl; - ctrl |= cohc->ctrl; - - if (direction == dma_mem_to_dev) { - u32 tx_flags = coh901318_cx_ctrl_prdd_source | - coh901318_cx_ctrl_src_addr_inc_enable; - - config |= coh901318_cx_cfg_rm_memory_to_primary; - ctrl_chained |= tx_flags; - ctrl_last |= tx_flags; - ctrl |= tx_flags; - } else if (direction == dma_dev_to_mem) { - u32 rx_flags = coh901318_cx_ctrl_prdd_dest | - coh901318_cx_ctrl_dst_addr_inc_enable; - - config |= coh901318_cx_cfg_rm_primary_to_memory; - ctrl_chained |= rx_flags; - ctrl_last |= rx_flags; - ctrl |= rx_flags; - } else - goto err_direction; - - /* the dma only supports transmitting packages up to - * max_dma_packet_size. calculate to total number of - * dma elemts required to send the entire sg list - */ - for_each_sg(sgl, sg, sg_len, i) { - unsigned int factor; - size = sg_dma_len(sg); - - if (size <= max_dma_packet_size) { - len++; - continue; - } - - factor = size >> max_dma_packet_size_shift; - if ((factor << max_dma_packet_size_shift) < size) - factor++; - - len += factor; - } - - pr_debug("allocate %d lli:s for this transfer ", len); - lli = coh901318_lli_alloc(&cohc->base->pool, len); - - if (lli == null) - goto err_dma_alloc; - - coh901318_dma_set_runtimeconfig(chan, &cohc->config, direction); - - /* initiate allocated lli list */ - ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len, - cohc->addr, - ctrl_chained, - ctrl, - ctrl_last, - direction, coh901318_cx_ctrl_tc_irq_enable); - if (ret) - goto err_lli_fill; - - - coh_dbg(coh901318_list_print(cohc, lli)); - - /* pick a descriptor to handle this transfer */ - cohd = coh901318_desc_get(cohc); - cohd->head_config = config; - /* - * set the default head ctrl for the channel to the one from the - * lli, things may have changed due to odd buffer alignment - * etc. - */ - cohd->head_ctrl = lli->control; - cohd->dir = direction; - cohd->flags = flags; - cohd->desc.tx_submit = coh901318_tx_submit; - cohd->lli = lli; - - spin_unlock_irqrestore(&cohc->lock, flg); - - return &cohd->desc; - err_lli_fill: - err_dma_alloc: - err_direction: - spin_unlock_irqrestore(&cohc->lock, flg); - out: - return null; -} - -static enum dma_status -coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie, - struct dma_tx_state *txstate) -{ - struct coh901318_chan *cohc = to_coh901318_chan(chan); - enum dma_status ret; - - ret = dma_cookie_status(chan, cookie, txstate); - if (ret == dma_complete || !txstate) - return ret; - - dma_set_residue(txstate, coh901318_get_bytes_left(chan)); - - if (ret == dma_in_progress && cohc->stopped) - ret = dma_paused; - - return ret; -} - -static void -coh901318_issue_pending(struct dma_chan *chan) -{ - struct coh901318_chan *cohc = to_coh901318_chan(chan); - unsigned long flags; - - spin_lock_irqsave(&cohc->lock, flags); - - /* - * busy means that pending jobs are already being processed, - * and then there is no point in starting the queue: the - * terminal count interrupt on the channel will take the next - * job on the queue and execute it anyway. - */ - if (!cohc->busy) - coh901318_queue_start(cohc); - - spin_unlock_irqrestore(&cohc->lock, flags); -} - -/* - * here we wrap in the runtime dma control interface - */ -struct burst_table { - int burst_8bit; - int burst_16bit; - int burst_32bit; - u32 reg; -}; - -static const struct burst_table burst_sizes[] = { - { - .burst_8bit = 64, - .burst_16bit = 32, - .burst_32bit = 16, - .reg = coh901318_cx_ctrl_burst_count_64_bytes, - }, - { - .burst_8bit = 48, - .burst_16bit = 24, - .burst_32bit = 12, - .reg = coh901318_cx_ctrl_burst_count_48_bytes, - }, - { - .burst_8bit = 32, - .burst_16bit = 16, - .burst_32bit = 8, - .reg = coh901318_cx_ctrl_burst_count_32_bytes, - }, - { - .burst_8bit = 16, - .burst_16bit = 8, - .burst_32bit = 4, - .reg = coh901318_cx_ctrl_burst_count_16_bytes, - }, - { - .burst_8bit = 8, - .burst_16bit = 4, - .burst_32bit = 2, - .reg = coh901318_cx_ctrl_burst_count_8_bytes, - }, - { - .burst_8bit = 4, - .burst_16bit = 2, - .burst_32bit = 1, - .reg = coh901318_cx_ctrl_burst_count_4_bytes, - }, - { - .burst_8bit = 2, - .burst_16bit = 1, - .burst_32bit = 0, - .reg = coh901318_cx_ctrl_burst_count_2_bytes, - }, - { - .burst_8bit = 1, - .burst_16bit = 0, - .burst_32bit = 0, - .reg = coh901318_cx_ctrl_burst_count_1_byte, - }, -}; - -static int coh901318_dma_set_runtimeconfig(struct dma_chan *chan, - struct dma_slave_config *config, - enum dma_transfer_direction direction) -{ - struct coh901318_chan *cohc = to_coh901318_chan(chan); - dma_addr_t addr; - enum dma_slave_buswidth addr_width; - u32 maxburst; - u32 ctrl = 0; - int i = 0; - - /* we only support mem to per or per to mem transfers */ - if (direction == dma_dev_to_mem) { - addr = config->src_addr; - addr_width = config->src_addr_width; - maxburst = config->src_maxburst; - } else if (direction == dma_mem_to_dev) { - addr = config->dst_addr; - addr_width = config->dst_addr_width; - maxburst = config->dst_maxburst; - } else { - dev_err(cohc_2_dev(cohc), "illegal channel mode "); - return -einval; - } - - dev_dbg(cohc_2_dev(cohc), "configure channel for %d byte transfers ", - addr_width); - switch (addr_width) { - case dma_slave_buswidth_1_byte: - ctrl |= - coh901318_cx_ctrl_src_bus_size_8_bits | - coh901318_cx_ctrl_dst_bus_size_8_bits; - - while (i < array_size(burst_sizes)) { - if (burst_sizes[i].burst_8bit <= maxburst) - break; - i++; - } - - break; - case dma_slave_buswidth_2_bytes: - ctrl |= - coh901318_cx_ctrl_src_bus_size_16_bits | - coh901318_cx_ctrl_dst_bus_size_16_bits; - - while (i < array_size(burst_sizes)) { - if (burst_sizes[i].burst_16bit <= maxburst) - break; - i++; - } - - break; - case dma_slave_buswidth_4_bytes: - /* direction doesn't matter here, it's 32/32 bits */ - ctrl |= - coh901318_cx_ctrl_src_bus_size_32_bits | - coh901318_cx_ctrl_dst_bus_size_32_bits; - - while (i < array_size(burst_sizes)) { - if (burst_sizes[i].burst_32bit <= maxburst) - break; - i++; - } - - break; - default: - dev_err(cohc_2_dev(cohc), - "bad runtimeconfig: alien address width "); - return -einval; - } - - ctrl |= burst_sizes[i].reg; - dev_dbg(cohc_2_dev(cohc), - "selected burst size %d bytes for address width %d bytes, maxburst %d ", - burst_sizes[i].burst_8bit, addr_width, maxburst); - - cohc->addr = addr; - cohc->ctrl = ctrl; - - return 0; -} - -static int coh901318_dma_slave_config(struct dma_chan *chan, - struct dma_slave_config *config) -{ - struct coh901318_chan *cohc = to_coh901318_chan(chan); - - memcpy(&cohc->config, config, sizeof(*config)); - - return 0; -} - -static void coh901318_base_init(struct dma_device *dma, const int *pick_chans, - struct coh901318_base *base) -{ - int chans_i; - int i = 0; - struct coh901318_chan *cohc; - - init_list_head(&dma->channels); - - for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) { - for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) { - cohc = &base->chans[i]; - - cohc->base = base; - cohc->chan.device = dma; - cohc->id = i; - - /* todo: do we really need this lock if only one - * client is connected to each channel? - */ - - spin_lock_init(&cohc->lock); - - cohc->nbr_active_done = 0; - cohc->busy = 0; - init_list_head(&cohc->free); - init_list_head(&cohc->active); - init_list_head(&cohc->queue); - - tasklet_setup(&cohc->tasklet, dma_tasklet); - - list_add_tail(&cohc->chan.device_node, - &dma->channels); - } - } -} - -static int __init coh901318_probe(struct platform_device *pdev) -{ - int err = 0; - struct coh901318_base *base; - int irq; - struct resource *io; - - io = platform_get_resource(pdev, ioresource_mem, 0); - if (!io) - return -enodev; - - /* map dma controller registers to virtual memory */ - if (devm_request_mem_region(&pdev->dev, - io->start, - resource_size(io), - pdev->dev.driver->name) == null) - return -enomem; - - base = devm_kzalloc(&pdev->dev, - align(sizeof(struct coh901318_base), 4) + - u300_dma_channels * - sizeof(struct coh901318_chan), - gfp_kernel); - if (!base) - return -enomem; - - base->chans = ((void *)base) + align(sizeof(struct coh901318_base), 4); - - base->virtbase = devm_ioremap(&pdev->dev, io->start, resource_size(io)); - if (!base->virtbase) - return -enomem; - - base->dev = &pdev->dev; - spin_lock_init(&base->pm.lock); - base->pm.started_channels = 0; - - coh901318_debugfs_assign(debugfs_dma_base, base); - - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; - - err = devm_request_irq(&pdev->dev, irq, dma_irq_handler, 0, - "coh901318", base); - if (err) - return err; - - base->irq = irq; - - err = coh901318_pool_create(&base->pool, &pdev->dev, - sizeof(struct coh901318_lli), - 32); - if (err) - return err; - - /* init channels for device transfers */ - coh901318_base_init(&base->dma_slave, dma_slave_channels, - base); - - dma_cap_zero(base->dma_slave.cap_mask); - dma_cap_set(dma_slave, base->dma_slave.cap_mask); - - base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources; - base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources; - base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg; - base->dma_slave.device_tx_status = coh901318_tx_status; - base->dma_slave.device_issue_pending = coh901318_issue_pending; - base->dma_slave.device_config = coh901318_dma_slave_config; - base->dma_slave.device_pause = coh901318_pause; - base->dma_slave.device_resume = coh901318_resume; - base->dma_slave.device_terminate_all = coh901318_terminate_all; - base->dma_slave.dev = &pdev->dev; - - err = dma_async_device_register(&base->dma_slave); - - if (err) - goto err_register_slave; - - /* init channels for memcpy */ - coh901318_base_init(&base->dma_memcpy, dma_memcpy_channels, - base); - - dma_cap_zero(base->dma_memcpy.cap_mask); - dma_cap_set(dma_memcpy, base->dma_memcpy.cap_mask); - - base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources; - base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources; - base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy; - base->dma_memcpy.device_tx_status = coh901318_tx_status; - base->dma_memcpy.device_issue_pending = coh901318_issue_pending; - base->dma_memcpy.device_config = coh901318_dma_slave_config; - base->dma_memcpy.device_pause = coh901318_pause; - base->dma_memcpy.device_resume = coh901318_resume; - base->dma_memcpy.device_terminate_all = coh901318_terminate_all; - base->dma_memcpy.dev = &pdev->dev; - /* - * this controller can only access address at even 32bit boundaries, - * i.e. 2^2 - */ - base->dma_memcpy.copy_align = dmaengine_align_4_bytes; - err = dma_async_device_register(&base->dma_memcpy); - - if (err) - goto err_register_memcpy; - - err = of_dma_controller_register(pdev->dev.of_node, coh901318_xlate, - base); - if (err) - goto err_register_of_dma; - - platform_set_drvdata(pdev, base); - dev_info(&pdev->dev, "initialized coh901318 dma on virtual base 0x%p ", - base->virtbase); - - return err; - - err_register_of_dma: - dma_async_device_unregister(&base->dma_memcpy); - err_register_memcpy: - dma_async_device_unregister(&base->dma_slave); - err_register_slave: - coh901318_pool_destroy(&base->pool); - return err; -} -static void coh901318_base_remove(struct coh901318_base *base, const int *pick_chans) -{ - int chans_i; - int i = 0; - struct coh901318_chan *cohc; - - for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) { - for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) { - cohc = &base->chans[i]; - - tasklet_kill(&cohc->tasklet); - } - } - -} - -static int coh901318_remove(struct platform_device *pdev) -{ - struct coh901318_base *base = platform_get_drvdata(pdev); - - devm_free_irq(&pdev->dev, base->irq, base); - - coh901318_base_remove(base, dma_slave_channels); - coh901318_base_remove(base, dma_memcpy_channels); - - of_dma_controller_free(pdev->dev.of_node); - dma_async_device_unregister(&base->dma_memcpy); - dma_async_device_unregister(&base->dma_slave); - coh901318_pool_destroy(&base->pool); - return 0; -} - -static const struct of_device_id coh901318_dt_match[] = { - { .compatible = "stericsson,coh901318" }, - {}, -}; - -static struct platform_driver coh901318_driver = { - .remove = coh901318_remove, - .driver = { - .name = "coh901318", - .of_match_table = coh901318_dt_match, - }, -}; - -static int __init coh901318_init(void) -{ - return platform_driver_probe(&coh901318_driver, coh901318_probe); -} -subsys_initcall(coh901318_init); - -static void __exit coh901318_exit(void) -{ - platform_driver_unregister(&coh901318_driver); -} -module_exit(coh901318_exit); - -module_license("gpl"); -module_author("per friden"); diff --git a/drivers/dma/coh901318.h b/drivers/dma/coh901318.h --- a/drivers/dma/coh901318.h +++ /dev/null -/* spdx-license-identifier: gpl-2.0-only */ -/* - * copyright (c) 2007-2013 st-ericsson - * dma driver for coh 901 318 - * author: per friden <per.friden@stericsson.com> - */ - -#ifndef coh901318_h -#define coh901318_h - -#define max_dma_packet_size_shift 11 -#define max_dma_packet_size (1 << max_dma_packet_size_shift) - -struct device; - -struct coh901318_pool { - spinlock_t lock; - struct dma_pool *dmapool; - struct device *dev; - -#ifdef config_debug_fs - int debugfs_pool_counter; -#endif -}; - -/** - * struct coh901318_lli - linked list item for dmac - * @control: control settings for dmac - * @src_addr: transfer source address - * @dst_addr: transfer destination address - * @link_addr: physical address to next lli - * @virt_link_addr: virtual address of next lli (only used by pool_free) - * @phy_this: physical address of current lli (only used by pool_free) - */ -struct coh901318_lli { - u32 control; - dma_addr_t src_addr; - dma_addr_t dst_addr; - dma_addr_t link_addr; - - void *virt_link_addr; - dma_addr_t phy_this; -}; - -/** - * coh901318_pool_create() - creates an dma pool for lli:s - * @pool: pool handle - * @dev: dma device - * @lli_nbr: number of lli:s in the pool - * @algin: address alignemtn of lli:s - * returns 0 on success otherwise none zero - */ -int coh901318_pool_create(struct coh901318_pool *pool, - struct device *dev, - size_t lli_nbr, size_t align); - -/** - * coh901318_pool_destroy() - destroys the dma pool - * @pool: pool handle - * returns 0 on success otherwise none zero - */ -int coh901318_pool_destroy(struct coh901318_pool *pool); - -/** - * coh901318_lli_alloc() - allocates a linked list - * - * @pool: pool handle - * @len: length to list - * return: none null if success otherwise null - */ -struct coh901318_lli * -coh901318_lli_alloc(struct coh901318_pool *pool, - unsigned int len); - -/** - * coh901318_lli_free() - returns the linked list items to the pool - * @pool: pool handle - * @lli: reference to lli pointer to be freed - */ -void coh901318_lli_free(struct coh901318_pool *pool, - struct coh901318_lli **lli); - -/** - * coh901318_lli_fill_memcpy() - prepares the lli:s for dma memcpy - * @pool: pool handle - * @lli: allocated lli - * @src: src address - * @size: transfer size - * @dst: destination address - * @ctrl_chained: ctrl for chained lli - * @ctrl_last: ctrl for the last lli - * returns number of cpu interrupts for the lli, negative on error. - */ -int -coh901318_lli_fill_memcpy(struct coh901318_pool *pool, - struct coh901318_lli *lli, - dma_addr_t src, unsigned int size, - dma_addr_t dst, u32 ctrl_chained, u32 ctrl_last); - -/** - * coh901318_lli_fill_single() - prepares the lli:s for dma single transfer - * @pool: pool handle - * @lli: allocated lli - * @buf: transfer buffer - * @size: transfer size - * @dev_addr: address of periphal - * @ctrl_chained: ctrl for chained lli - * @ctrl_last: ctrl for the last lli - * @dir: direction of transfer (to or from device) - * returns number of cpu interrupts for the lli, negative on error. - */ -int -coh901318_lli_fill_single(struct coh901318_pool *pool, - struct coh901318_lli *lli, - dma_addr_t buf, unsigned int size, - dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_last, - enum dma_transfer_direction dir); - -/** - * coh901318_lli_fill_single() - prepares the lli:s for dma scatter list transfer - * @pool: pool handle - * @lli: allocated lli - * @sg: scatter gather list - * @nents: number of entries in sg - * @dev_addr: address of periphal - * @ctrl_chained: ctrl for chained lli - * @ctrl: ctrl of middle lli - * @ctrl_last: ctrl for the last lli - * @dir: direction of transfer (to or from device) - * @ctrl_irq_mask: ctrl mask for cpu interrupt - * returns number of cpu interrupts for the lli, negative on error. - */ -int -coh901318_lli_fill_sg(struct coh901318_pool *pool, - struct coh901318_lli *lli, - struct scatterlist *sg, unsigned int nents, - dma_addr_t dev_addr, u32 ctrl_chained, - u32 ctrl, u32 ctrl_last, - enum dma_transfer_direction dir, u32 ctrl_irq_mask); - -#endif /* coh901318_h */ diff --git a/drivers/dma/coh901318_lli.c b/drivers/dma/coh901318_lli.c --- a/drivers/dma/coh901318_lli.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * driver/dma/coh901318_lli.c - * - * copyright (c) 2007-2009 st-ericsson - * support functions for handling lli for dma - * author: per friden <per.friden@stericsson.com> - */ - -#include <linux/spinlock.h> -#include <linux/memory.h> -#include <linux/gfp.h> -#include <linux/dmapool.h> -#include <linux/dmaengine.h> - -#include "coh901318.h" - -#if (defined(config_debug_fs) && defined(config_u300_debug)) -#define debugfs_pool_counter_reset(pool) (pool->debugfs_pool_counter = 0) -#define debugfs_pool_counter_add(pool, add) (pool->debugfs_pool_counter += add) -#else -#define debugfs_pool_counter_reset(pool) -#define debugfs_pool_counter_add(pool, add) -#endif - -static struct coh901318_lli * -coh901318_lli_next(struct coh901318_lli *data) -{ - if (data == null || data->link_addr == 0) - return null; - - return (struct coh901318_lli *) data->virt_link_addr; -} - -int coh901318_pool_create(struct coh901318_pool *pool, - struct device *dev, - size_t size, size_t align) -{ - spin_lock_init(&pool->lock); - pool->dev = dev; - pool->dmapool = dma_pool_create("lli_pool", dev, size, align, 0); - - debugfs_pool_counter_reset(pool); - return 0; -} - -int coh901318_pool_destroy(struct coh901318_pool *pool) -{ - - dma_pool_destroy(pool->dmapool); - return 0; -} - -struct coh901318_lli * -coh901318_lli_alloc(struct coh901318_pool *pool, unsigned int len) -{ - int i; - struct coh901318_lli *head; - struct coh901318_lli *lli; - struct coh901318_lli *lli_prev; - dma_addr_t phy; - - if (len == 0) - return null; - - spin_lock(&pool->lock); - - head = dma_pool_alloc(pool->dmapool, gfp_nowait, &phy); - - if (head == null) - goto err; - - debugfs_pool_counter_add(pool, 1); - - lli = head; - lli->phy_this = phy; - lli->link_addr = 0x00000000; - lli->virt_link_addr = null; - - for (i = 1; i < len; i++) { - lli_prev = lli; - - lli = dma_pool_alloc(pool->dmapool, gfp_nowait, &phy); - - if (lli == null) - goto err_clean_up; - - debugfs_pool_counter_add(pool, 1); - lli->phy_this = phy; - lli->link_addr = 0x00000000; - lli->virt_link_addr = null; - - lli_prev->link_addr = phy; - lli_prev->virt_link_addr = lli; - } - - spin_unlock(&pool->lock); - - return head; - - err: - spin_unlock(&pool->lock); - return null; - - err_clean_up: - lli_prev->link_addr = 0x00000000u; - spin_unlock(&pool->lock); - coh901318_lli_free(pool, &head); - return null; -} - -void coh901318_lli_free(struct coh901318_pool *pool, - struct coh901318_lli **lli) -{ - struct coh901318_lli *l; - struct coh901318_lli *next; - - if (lli == null) - return; - - l = *lli; - - if (l == null) - return; - - spin_lock(&pool->lock); - - while (l->link_addr) { - next = l->virt_link_addr; - dma_pool_free(pool->dmapool, l, l->phy_this); - debugfs_pool_counter_add(pool, -1); - l = next; - } - dma_pool_free(pool->dmapool, l, l->phy_this); - debugfs_pool_counter_add(pool, -1); - - spin_unlock(&pool->lock); - *lli = null; -} - -int -coh901318_lli_fill_memcpy(struct coh901318_pool *pool, - struct coh901318_lli *lli, - dma_addr_t source, unsigned int size, - dma_addr_t destination, u32 ctrl_chained, - u32 ctrl_eom) -{ - int s = size; - dma_addr_t src = source; - dma_addr_t dst = destination; - - lli->src_addr = src; - lli->dst_addr = dst; - - while (lli->link_addr) { - lli->control = ctrl_chained | max_dma_packet_size; - lli->src_addr = src; - lli->dst_addr = dst; - - s -= max_dma_packet_size; - lli = coh901318_lli_next(lli); - - src += max_dma_packet_size; - dst += max_dma_packet_size; - } - - lli->control = ctrl_eom | s; - lli->src_addr = src; - lli->dst_addr = dst; - - return 0; -} - -int -coh901318_lli_fill_single(struct coh901318_pool *pool, - struct coh901318_lli *lli, - dma_addr_t buf, unsigned int size, - dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_eom, - enum dma_transfer_direction dir) -{ - int s = size; - dma_addr_t src; - dma_addr_t dst; - - - if (dir == dma_mem_to_dev) { - src = buf; - dst = dev_addr; - - } else if (dir == dma_dev_to_mem) { - - src = dev_addr; - dst = buf; - } else { - return -einval; - } - - while (lli->link_addr) { - size_t block_size = max_dma_packet_size; - lli->control = ctrl_chained | max_dma_packet_size; - - /* if we are on the next-to-final block and there will - * be less than half a dma packet left for the last - * block, then we want to make this block a little - * smaller to balance the sizes. this is meant to - * avoid too small transfers if the buffer size is - * (max_dma_packet_size*n + 1) */ - if (s < (max_dma_packet_size + max_dma_packet_size/2)) - block_size = max_dma_packet_size/2; - - s -= block_size; - lli->src_addr = src; - lli->dst_addr = dst; - - lli = coh901318_lli_next(lli); - - if (dir == dma_mem_to_dev) - src += block_size; - else if (dir == dma_dev_to_mem) - dst += block_size; - } - - lli->control = ctrl_eom | s; - lli->src_addr = src; - lli->dst_addr = dst; - - return 0; -} - -int -coh901318_lli_fill_sg(struct coh901318_pool *pool, - struct coh901318_lli *lli, - struct scatterlist *sgl, unsigned int nents, - dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl, - u32 ctrl_last, - enum dma_transfer_direction dir, u32 ctrl_irq_mask) -{ - int i; - struct scatterlist *sg; - u32 ctrl_sg; - dma_addr_t src = 0; - dma_addr_t dst = 0; - u32 bytes_to_transfer; - u32 elem_size; - - if (lli == null) - goto err; - - spin_lock(&pool->lock); - - if (dir == dma_mem_to_dev) - dst = dev_addr; - else if (dir == dma_dev_to_mem) - src = dev_addr; - else - goto err; - - for_each_sg(sgl, sg, nents, i) { - if (sg_is_chain(sg)) { - /* sg continues to the next sg-element don't - * send ctrl_finish until the last - * sg-element in the chain - */ - ctrl_sg = ctrl_chained; - } else if (i == nents - 1) - ctrl_sg = ctrl_last; - else - ctrl_sg = ctrl ? ctrl : ctrl_last; - - - if (dir == dma_mem_to_dev) - /* increment source address */ - src = sg_dma_address(sg); - else - /* increment destination address */ - dst = sg_dma_address(sg); - - bytes_to_transfer = sg_dma_len(sg); - - while (bytes_to_transfer) { - u32 val; - - if (bytes_to_transfer > max_dma_packet_size) { - elem_size = max_dma_packet_size; - val = ctrl_chained; - } else { - elem_size = bytes_to_transfer; - val = ctrl_sg; - } - - lli->control = val | elem_size; - lli->src_addr = src; - lli->dst_addr = dst; - - if (dir == dma_dev_to_mem) - dst += elem_size; - else - src += elem_size; - - bug_on(lli->link_addr & 3); - - bytes_to_transfer -= elem_size; - lli = coh901318_lli_next(lli); - } - - } - spin_unlock(&pool->lock); - - return 0; - err: - spin_unlock(&pool->lock); - return -einval; -} diff --git a/include/linux/platform_data/dma-coh901318.h b/include/linux/platform_data/dma-coh901318.h --- a/include/linux/platform_data/dma-coh901318.h +++ /dev/null -/* spdx-license-identifier: gpl-2.0-only */ -/* - * platform data for the coh901318 dma controller - * copyright (c) 2007-2013 st-ericsson - */ - -#ifndef plat_coh901318_h -#define plat_coh901318_h - -#ifdef config_coh901318 - -/* we only support the u300 dma channels */ -#define u300_dma_msl_tx_0 0 -#define u300_dma_msl_tx_1 1 -#define u300_dma_msl_tx_2 2 -#define u300_dma_msl_tx_3 3 -#define u300_dma_msl_tx_4 4 -#define u300_dma_msl_tx_5 5 -#define u300_dma_msl_tx_6 6 -#define u300_dma_msl_rx_0 7 -#define u300_dma_msl_rx_1 8 -#define u300_dma_msl_rx_2 9 -#define u300_dma_msl_rx_3 10 -#define u300_dma_msl_rx_4 11 -#define u300_dma_msl_rx_5 12 -#define u300_dma_msl_rx_6 13 -#define u300_dma_mmcsd_rx_tx 14 -#define u300_dma_mspro_tx 15 -#define u300_dma_mspro_rx 16 -#define u300_dma_uart0_tx 17 -#define u300_dma_uart0_rx 18 -#define u300_dma_apex_tx 19 -#define u300_dma_apex_rx 20 -#define u300_dma_pcm_i2s0_tx 21 -#define u300_dma_pcm_i2s0_rx 22 -#define u300_dma_pcm_i2s1_tx 23 -#define u300_dma_pcm_i2s1_rx 24 -#define u300_dma_xgam_cdi 25 -#define u300_dma_xgam_pdi 26 -#define u300_dma_spi_tx 27 -#define u300_dma_spi_rx 28 -#define u300_dma_general_purpose_0 29 -#define u300_dma_general_purpose_1 30 -#define u300_dma_general_purpose_2 31 -#define u300_dma_general_purpose_3 32 -#define u300_dma_general_purpose_4 33 -#define u300_dma_general_purpose_5 34 -#define u300_dma_general_purpose_6 35 -#define u300_dma_general_purpose_7 36 -#define u300_dma_general_purpose_8 37 -#define u300_dma_uart1_tx 38 -#define u300_dma_uart1_rx 39 - -#define u300_dma_device_channels 32 -#define u300_dma_channels 40 - -/** - * coh901318_filter_id() - dma channel filter function - * @chan: dma channel handle - * @chan_id: id of dma channel to be filter out - * - * in dma_request_channel() it specifies what channel id to be requested - */ -bool coh901318_filter_id(struct dma_chan *chan, void *chan_id); -#else -static inline bool coh901318_filter_id(struct dma_chan *chan, void *chan_id) -{ - return false; -} -#endif - -#endif /* plat_coh901318_h */
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DMA engines
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a033a74e8b66336fc2ea379842be6bcf176cbfbc
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arnd bergmann linus walleij linus walleij linaro org
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documentation
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devicetree
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bindings, dma, platform_data
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dmaengine: remove sirfsoc driver
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the csr sirf prima2/atlas platforms are getting removed, so this driver is no longer needed.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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remove sirfsoc driver
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
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[]
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['c', 'h', 'kconfig', 'txt', 'makefile']
| 5
| 0
| 1,229
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--- diff --git a/documentation/devicetree/bindings/dma/sirfsoc-dma.txt b/documentation/devicetree/bindings/dma/sirfsoc-dma.txt --- a/documentation/devicetree/bindings/dma/sirfsoc-dma.txt +++ /dev/null -* csr sirfsoc dma controller - -see dma.txt first - -required properties: -- compatible: should be "sirf,prima2-dmac", "sirf,atlas7-dmac" or - "sirf,atlas7-dmac-v2" -- reg: should contain dma registers location and length. -- interrupts: should contain one interrupt shared by all channel -- #dma-cells: must be <1>. used to represent the number of integer - cells in the dmas property of client device. -- clocks: clock required - -example: - -controller: -dmac0: dma-controller@b00b0000 { - compatible = "sirf,prima2-dmac"; - reg = <0xb00b0000 0x10000>; - interrupts = <12>; - clocks = <&clks 24>; - #dma-cells = <1>; -}; - - -client: -fill the specific dma request line in dmas. in the below example, spi0 read -channel request line is 9 of the 2nd dma controller, while write channel uses -4 of the 2nd dma controller; spi1 read channel request line is 12 of the 1st -dma controller, while write channel uses 13 of the 1st dma controller: - -spi0: spi@b00d0000 { - compatible = "sirf,prima2-spi"; - dmas = <&dmac1 9>, - <&dmac1 4>; - dma-names = "rx", "tx"; -}; - -spi1: spi@b0170000 { - compatible = "sirf,prima2-spi"; - dmas = <&dmac0 12>, - <&dmac0 13>; - dma-names = "rx", "tx"; -}; diff --git a/drivers/dma/kconfig b/drivers/dma/kconfig --- a/drivers/dma/kconfig +++ b/drivers/dma/kconfig -config sirf_dma - tristate "csr sirfprimaii/sirfmarco dma support" - depends on arch_sirf - select dma_engine - help - enable support for the csr sirfprimaii dma engine. - diff --git a/drivers/dma/makefile b/drivers/dma/makefile --- a/drivers/dma/makefile +++ b/drivers/dma/makefile -obj-$(config_sirf_dma) += sirf-dma.o diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c --- a/drivers/dma/sirf-dma.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-or-later -/* - * dma controller driver for csr sirfprimaii - * - * copyright (c) 2011 cambridge silicon radio limited, a csr plc group company. - */ - -#include <linux/module.h> -#include <linux/dmaengine.h> -#include <linux/dma-mapping.h> -#include <linux/pm_runtime.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include <linux/slab.h> -#include <linux/of_irq.h> -#include <linux/of_address.h> -#include <linux/of_device.h> -#include <linux/of_platform.h> -#include <linux/clk.h> -#include <linux/of_dma.h> -#include <linux/sirfsoc_dma.h> - -#include "dmaengine.h" - -#define sirfsoc_dma_ver_a7v1 1 -#define sirfsoc_dma_ver_a7v2 2 -#define sirfsoc_dma_ver_a6 4 - -#define sirfsoc_dma_descriptors 16 -#define sirfsoc_dma_channels 16 -#define sirfsoc_dma_table_num 256 - -#define sirfsoc_dma_ch_addr 0x00 -#define sirfsoc_dma_ch_xlen 0x04 -#define sirfsoc_dma_ch_ylen 0x08 -#define sirfsoc_dma_ch_ctrl 0x0c - -#define sirfsoc_dma_width_0 0x100 -#define sirfsoc_dma_ch_valid 0x140 -#define sirfsoc_dma_ch_int 0x144 -#define sirfsoc_dma_int_en 0x148 -#define sirfsoc_dma_int_en_clr 0x14c -#define sirfsoc_dma_ch_loop_ctrl 0x150 -#define sirfsoc_dma_ch_loop_ctrl_clr 0x154 -#define sirfsoc_dma_width_atlas7 0x10 -#define sirfsoc_dma_valid_atlas7 0x14 -#define sirfsoc_dma_int_atlas7 0x18 -#define sirfsoc_dma_int_en_atlas7 0x1c -#define sirfsoc_dma_loop_ctrl_atlas7 0x20 -#define sirfsoc_dma_cur_data_addr 0x34 -#define sirfsoc_dma_mul_atlas7 0x38 -#define sirfsoc_dma_ch_loop_ctrl_atlas7 0x158 -#define sirfsoc_dma_ch_loop_ctrl_clr_atlas7 0x15c -#define sirfsoc_dma_iobg_scmd_en 0x800 -#define sirfsoc_dma_early_resp_set 0x818 -#define sirfsoc_dma_early_resp_clr 0x81c - -#define sirfsoc_dma_mode_ctrl_bit 4 -#define sirfsoc_dma_dir_ctrl_bit 5 -#define sirfsoc_dma_mode_ctrl_bit_atlas7 2 -#define sirfsoc_dma_chain_ctrl_bit_atlas7 3 -#define sirfsoc_dma_dir_ctrl_bit_atlas7 4 -#define sirfsoc_dma_tab_num_atlas7 7 -#define sirfsoc_dma_chain_int_bit_atlas7 5 -#define sirfsoc_dma_chain_flag_shift_atlas7 25 -#define sirfsoc_dma_chain_addr_shift 32 - -#define sirfsoc_dma_int_fini_int_atlas7 bit(0) -#define sirfsoc_dma_int_cnt_int_atlas7 bit(1) -#define sirfsoc_dma_int_pau_int_atlas7 bit(2) -#define sirfsoc_dma_int_loop_int_atlas7 bit(3) -#define sirfsoc_dma_int_inv_int_atlas7 bit(4) -#define sirfsoc_dma_int_end_int_atlas7 bit(5) -#define sirfsoc_dma_int_all_atlas7 0x3f - -/* xlen and dma_width register is in 4 bytes boundary */ -#define sirfsoc_dma_word_len 4 -#define sirfsoc_dma_xlen_max_v1 0x800 -#define sirfsoc_dma_xlen_max_v2 0x1000 - -struct sirfsoc_dma_desc { - struct dma_async_tx_descriptor desc; - struct list_head node; - - /* sirfprimaii 2d-dma parameters */ - - int xlen; /* dma xlen */ - int ylen; /* dma ylen */ - int width; /* dma width */ - int dir; - bool cyclic; /* is loop dma? */ - bool chain; /* is chain dma? */ - u32 addr; /* dma buffer address */ - u64 chain_table[sirfsoc_dma_table_num]; /* chain tbl */ -}; - -struct sirfsoc_dma_chan { - struct dma_chan chan; - struct list_head free; - struct list_head prepared; - struct list_head queued; - struct list_head active; - struct list_head completed; - unsigned long happened_cyclic; - unsigned long completed_cyclic; - - /* lock for this structure */ - spinlock_t lock; - - int mode; -}; - -struct sirfsoc_dma_regs { - u32 ctrl[sirfsoc_dma_channels]; - u32 interrupt_en; -}; - -struct sirfsoc_dma { - struct dma_device dma; - struct tasklet_struct tasklet; - struct sirfsoc_dma_chan channels[sirfsoc_dma_channels]; - void __iomem *base; - int irq; - struct clk *clk; - int type; - void (*exec_desc)(struct sirfsoc_dma_desc *sdesc, - int cid, int burst_mode, void __iomem *base); - struct sirfsoc_dma_regs regs_save; -}; - -struct sirfsoc_dmadata { - void (*exec)(struct sirfsoc_dma_desc *sdesc, - int cid, int burst_mode, void __iomem *base); - int type; -}; - -enum sirfsoc_dma_chain_flag { - sirfsoc_dma_chain_normal = 0x01, - sirfsoc_dma_chain_pause = 0x02, - sirfsoc_dma_chain_loop = 0x03, - sirfsoc_dma_chain_end = 0x04 -}; - -#define drv_name "sirfsoc_dma" - -static int sirfsoc_dma_runtime_suspend(struct device *dev); - -/* convert struct dma_chan to struct sirfsoc_dma_chan */ -static inline -struct sirfsoc_dma_chan *dma_chan_to_sirfsoc_dma_chan(struct dma_chan *c) -{ - return container_of(c, struct sirfsoc_dma_chan, chan); -} - -/* convert struct dma_chan to struct sirfsoc_dma */ -static inline struct sirfsoc_dma *dma_chan_to_sirfsoc_dma(struct dma_chan *c) -{ - struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(c); - return container_of(schan, struct sirfsoc_dma, channels[c->chan_id]); -} - -static void sirfsoc_dma_execute_hw_a7v2(struct sirfsoc_dma_desc *sdesc, - int cid, int burst_mode, void __iomem *base) -{ - if (sdesc->chain) { - /* dma v2 hw chain mode */ - writel_relaxed((sdesc->dir << sirfsoc_dma_dir_ctrl_bit_atlas7) | - (sdesc->chain << - sirfsoc_dma_chain_ctrl_bit_atlas7) | - (0x8 << sirfsoc_dma_tab_num_atlas7) | 0x3, - base + sirfsoc_dma_ch_ctrl); - } else { - /* dma v2 legacy mode */ - writel_relaxed(sdesc->xlen, base + sirfsoc_dma_ch_xlen); - writel_relaxed(sdesc->ylen, base + sirfsoc_dma_ch_ylen); - writel_relaxed(sdesc->width, base + sirfsoc_dma_width_atlas7); - writel_relaxed((sdesc->width*((sdesc->ylen+1)>>1)), - base + sirfsoc_dma_mul_atlas7); - writel_relaxed((sdesc->dir << sirfsoc_dma_dir_ctrl_bit_atlas7) | - (sdesc->chain << - sirfsoc_dma_chain_ctrl_bit_atlas7) | - 0x3, base + sirfsoc_dma_ch_ctrl); - } - writel_relaxed(sdesc->chain ? sirfsoc_dma_int_end_int_atlas7 : - (sirfsoc_dma_int_fini_int_atlas7 | - sirfsoc_dma_int_loop_int_atlas7), - base + sirfsoc_dma_int_en_atlas7); - writel(sdesc->addr, base + sirfsoc_dma_ch_addr); - if (sdesc->cyclic) - writel(0x10001, base + sirfsoc_dma_loop_ctrl_atlas7); -} - -static void sirfsoc_dma_execute_hw_a7v1(struct sirfsoc_dma_desc *sdesc, - int cid, int burst_mode, void __iomem *base) -{ - writel_relaxed(1, base + sirfsoc_dma_iobg_scmd_en); - writel_relaxed((1 << cid), base + sirfsoc_dma_early_resp_set); - writel_relaxed(sdesc->width, base + sirfsoc_dma_width_0 + cid * 4); - writel_relaxed(cid | (burst_mode << sirfsoc_dma_mode_ctrl_bit) | - (sdesc->dir << sirfsoc_dma_dir_ctrl_bit), - base + cid * 0x10 + sirfsoc_dma_ch_ctrl); - writel_relaxed(sdesc->xlen, base + cid * 0x10 + sirfsoc_dma_ch_xlen); - writel_relaxed(sdesc->ylen, base + cid * 0x10 + sirfsoc_dma_ch_ylen); - writel_relaxed(readl_relaxed(base + sirfsoc_dma_int_en) | - (1 << cid), base + sirfsoc_dma_int_en); - writel(sdesc->addr >> 2, base + cid * 0x10 + sirfsoc_dma_ch_addr); - if (sdesc->cyclic) { - writel((1 << cid) | 1 << (cid + 16) | - readl_relaxed(base + sirfsoc_dma_ch_loop_ctrl_atlas7), - base + sirfsoc_dma_ch_loop_ctrl_atlas7); - } - -} - -static void sirfsoc_dma_execute_hw_a6(struct sirfsoc_dma_desc *sdesc, - int cid, int burst_mode, void __iomem *base) -{ - writel_relaxed(sdesc->width, base + sirfsoc_dma_width_0 + cid * 4); - writel_relaxed(cid | (burst_mode << sirfsoc_dma_mode_ctrl_bit) | - (sdesc->dir << sirfsoc_dma_dir_ctrl_bit), - base + cid * 0x10 + sirfsoc_dma_ch_ctrl); - writel_relaxed(sdesc->xlen, base + cid * 0x10 + sirfsoc_dma_ch_xlen); - writel_relaxed(sdesc->ylen, base + cid * 0x10 + sirfsoc_dma_ch_ylen); - writel_relaxed(readl_relaxed(base + sirfsoc_dma_int_en) | - (1 << cid), base + sirfsoc_dma_int_en); - writel(sdesc->addr >> 2, base + cid * 0x10 + sirfsoc_dma_ch_addr); - if (sdesc->cyclic) { - writel((1 << cid) | 1 << (cid + 16) | - readl_relaxed(base + sirfsoc_dma_ch_loop_ctrl), - base + sirfsoc_dma_ch_loop_ctrl); - } - -} - -/* execute all queued dma descriptors */ -static void sirfsoc_dma_execute(struct sirfsoc_dma_chan *schan) -{ - struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan); - int cid = schan->chan.chan_id; - struct sirfsoc_dma_desc *sdesc = null; - void __iomem *base; - - /* - * lock has been held by functions calling this, so we don't hold - * lock again - */ - base = sdma->base; - sdesc = list_first_entry(&schan->queued, struct sirfsoc_dma_desc, - node); - /* move the first queued descriptor to active list */ - list_move_tail(&sdesc->node, &schan->active); - - if (sdma->type == sirfsoc_dma_ver_a7v2) - cid = 0; - - /* start the dma transfer */ - sdma->exec_desc(sdesc, cid, schan->mode, base); - - if (sdesc->cyclic) - schan->happened_cyclic = schan->completed_cyclic = 0; -} - -/* interrupt handler */ -static irqreturn_t sirfsoc_dma_irq(int irq, void *data) -{ - struct sirfsoc_dma *sdma = data; - struct sirfsoc_dma_chan *schan; - struct sirfsoc_dma_desc *sdesc = null; - u32 is; - bool chain; - int ch; - void __iomem *reg; - - switch (sdma->type) { - case sirfsoc_dma_ver_a6: - case sirfsoc_dma_ver_a7v1: - is = readl(sdma->base + sirfsoc_dma_ch_int); - reg = sdma->base + sirfsoc_dma_ch_int; - while ((ch = fls(is) - 1) >= 0) { - is &= ~(1 << ch); - writel_relaxed(1 << ch, reg); - schan = &sdma->channels[ch]; - spin_lock(&schan->lock); - sdesc = list_first_entry(&schan->active, - struct sirfsoc_dma_desc, node); - if (!sdesc->cyclic) { - /* execute queued descriptors */ - list_splice_tail_init(&schan->active, - &schan->completed); - dma_cookie_complete(&sdesc->desc); - if (!list_empty(&schan->queued)) - sirfsoc_dma_execute(schan); - } else - schan->happened_cyclic++; - spin_unlock(&schan->lock); - } - break; - - case sirfsoc_dma_ver_a7v2: - is = readl(sdma->base + sirfsoc_dma_int_atlas7); - - reg = sdma->base + sirfsoc_dma_int_atlas7; - writel_relaxed(sirfsoc_dma_int_all_atlas7, reg); - schan = &sdma->channels[0]; - spin_lock(&schan->lock); - sdesc = list_first_entry(&schan->active, - struct sirfsoc_dma_desc, node); - if (!sdesc->cyclic) { - chain = sdesc->chain; - if ((chain && (is & sirfsoc_dma_int_end_int_atlas7)) || - (!chain && - (is & sirfsoc_dma_int_fini_int_atlas7))) { - /* execute queued descriptors */ - list_splice_tail_init(&schan->active, - &schan->completed); - dma_cookie_complete(&sdesc->desc); - if (!list_empty(&schan->queued)) - sirfsoc_dma_execute(schan); - } - } else if (sdesc->cyclic && (is & - sirfsoc_dma_int_loop_int_atlas7)) - schan->happened_cyclic++; - - spin_unlock(&schan->lock); - break; - - default: - break; - } - - /* schedule tasklet */ - tasklet_schedule(&sdma->tasklet); - - return irq_handled; -} - -/* process completed descriptors */ -static void sirfsoc_dma_process_completed(struct sirfsoc_dma *sdma) -{ - dma_cookie_t last_cookie = 0; - struct sirfsoc_dma_chan *schan; - struct sirfsoc_dma_desc *sdesc; - struct dma_async_tx_descriptor *desc; - unsigned long flags; - unsigned long happened_cyclic; - list_head(list); - int i; - - for (i = 0; i < sdma->dma.chancnt; i++) { - schan = &sdma->channels[i]; - - /* get all completed descriptors */ - spin_lock_irqsave(&schan->lock, flags); - if (!list_empty(&schan->completed)) { - list_splice_tail_init(&schan->completed, &list); - spin_unlock_irqrestore(&schan->lock, flags); - - /* execute callbacks and run dependencies */ - list_for_each_entry(sdesc, &list, node) { - desc = &sdesc->desc; - - dmaengine_desc_get_callback_invoke(desc, null); - last_cookie = desc->cookie; - dma_run_dependencies(desc); - } - - /* free descriptors */ - spin_lock_irqsave(&schan->lock, flags); - list_splice_tail_init(&list, &schan->free); - schan->chan.completed_cookie = last_cookie; - spin_unlock_irqrestore(&schan->lock, flags); - } else { - if (list_empty(&schan->active)) { - spin_unlock_irqrestore(&schan->lock, flags); - continue; - } - - /* for cyclic channel, desc is always in active list */ - sdesc = list_first_entry(&schan->active, - struct sirfsoc_dma_desc, node); - - /* cyclic dma */ - happened_cyclic = schan->happened_cyclic; - spin_unlock_irqrestore(&schan->lock, flags); - - desc = &sdesc->desc; - while (happened_cyclic != schan->completed_cyclic) { - dmaengine_desc_get_callback_invoke(desc, null); - schan->completed_cyclic++; - } - } - } -} - -/* dma tasklet */ -static void sirfsoc_dma_tasklet(struct tasklet_struct *t) -{ - struct sirfsoc_dma *sdma = from_tasklet(sdma, t, tasklet); - - sirfsoc_dma_process_completed(sdma); -} - -/* submit descriptor to hardware */ -static dma_cookie_t sirfsoc_dma_tx_submit(struct dma_async_tx_descriptor *txd) -{ - struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(txd->chan); - struct sirfsoc_dma_desc *sdesc; - unsigned long flags; - dma_cookie_t cookie; - - sdesc = container_of(txd, struct sirfsoc_dma_desc, desc); - - spin_lock_irqsave(&schan->lock, flags); - - /* move descriptor to queue */ - list_move_tail(&sdesc->node, &schan->queued); - - cookie = dma_cookie_assign(txd); - - spin_unlock_irqrestore(&schan->lock, flags); - - return cookie; -} - -static int sirfsoc_dma_slave_config(struct dma_chan *chan, - struct dma_slave_config *config) -{ - struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan); - unsigned long flags; - - if ((config->src_addr_width != dma_slave_buswidth_4_bytes) || - (config->dst_addr_width != dma_slave_buswidth_4_bytes)) - return -einval; - - spin_lock_irqsave(&schan->lock, flags); - schan->mode = (config->src_maxburst == 4 ? 1 : 0); - spin_unlock_irqrestore(&schan->lock, flags); - - return 0; -} - -static int sirfsoc_dma_terminate_all(struct dma_chan *chan) -{ - struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan); - struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan); - int cid = schan->chan.chan_id; - unsigned long flags; - - spin_lock_irqsave(&schan->lock, flags); - - switch (sdma->type) { - case sirfsoc_dma_ver_a7v1: - writel_relaxed(1 << cid, sdma->base + sirfsoc_dma_int_en_clr); - writel_relaxed(1 << cid, sdma->base + sirfsoc_dma_ch_int); - writel_relaxed((1 << cid) | 1 << (cid + 16), - sdma->base + - sirfsoc_dma_ch_loop_ctrl_clr_atlas7); - writel_relaxed(1 << cid, sdma->base + sirfsoc_dma_ch_valid); - break; - case sirfsoc_dma_ver_a7v2: - writel_relaxed(0, sdma->base + sirfsoc_dma_int_en_atlas7); - writel_relaxed(sirfsoc_dma_int_all_atlas7, - sdma->base + sirfsoc_dma_int_atlas7); - writel_relaxed(0, sdma->base + sirfsoc_dma_loop_ctrl_atlas7); - writel_relaxed(0, sdma->base + sirfsoc_dma_valid_atlas7); - break; - case sirfsoc_dma_ver_a6: - writel_relaxed(readl_relaxed(sdma->base + sirfsoc_dma_int_en) & - ~(1 << cid), sdma->base + sirfsoc_dma_int_en); - writel_relaxed(readl_relaxed(sdma->base + - sirfsoc_dma_ch_loop_ctrl) & - ~((1 << cid) | 1 << (cid + 16)), - sdma->base + sirfsoc_dma_ch_loop_ctrl); - writel_relaxed(1 << cid, sdma->base + sirfsoc_dma_ch_valid); - break; - default: - break; - } - - list_splice_tail_init(&schan->active, &schan->free); - list_splice_tail_init(&schan->queued, &schan->free); - - spin_unlock_irqrestore(&schan->lock, flags); - - return 0; -} - -static int sirfsoc_dma_pause_chan(struct dma_chan *chan) -{ - struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan); - struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan); - int cid = schan->chan.chan_id; - unsigned long flags; - - spin_lock_irqsave(&schan->lock, flags); - - switch (sdma->type) { - case sirfsoc_dma_ver_a7v1: - writel_relaxed((1 << cid) | 1 << (cid + 16), - sdma->base + - sirfsoc_dma_ch_loop_ctrl_clr_atlas7); - break; - case sirfsoc_dma_ver_a7v2: - writel_relaxed(0, sdma->base + sirfsoc_dma_loop_ctrl_atlas7); - break; - case sirfsoc_dma_ver_a6: - writel_relaxed(readl_relaxed(sdma->base + - sirfsoc_dma_ch_loop_ctrl) & - ~((1 << cid) | 1 << (cid + 16)), - sdma->base + sirfsoc_dma_ch_loop_ctrl); - break; - - default: - break; - } - - spin_unlock_irqrestore(&schan->lock, flags); - - return 0; -} - -static int sirfsoc_dma_resume_chan(struct dma_chan *chan) -{ - struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan); - struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan); - int cid = schan->chan.chan_id; - unsigned long flags; - - spin_lock_irqsave(&schan->lock, flags); - switch (sdma->type) { - case sirfsoc_dma_ver_a7v1: - writel_relaxed((1 << cid) | 1 << (cid + 16), - sdma->base + sirfsoc_dma_ch_loop_ctrl_atlas7); - break; - case sirfsoc_dma_ver_a7v2: - writel_relaxed(0x10001, - sdma->base + sirfsoc_dma_loop_ctrl_atlas7); - break; - case sirfsoc_dma_ver_a6: - writel_relaxed(readl_relaxed(sdma->base + - sirfsoc_dma_ch_loop_ctrl) | - ((1 << cid) | 1 << (cid + 16)), - sdma->base + sirfsoc_dma_ch_loop_ctrl); - break; - - default: - break; - } - - spin_unlock_irqrestore(&schan->lock, flags); - - return 0; -} - -/* alloc channel resources */ -static int sirfsoc_dma_alloc_chan_resources(struct dma_chan *chan) -{ - struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan); - struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan); - struct sirfsoc_dma_desc *sdesc; - unsigned long flags; - list_head(descs); - int i; - - pm_runtime_get_sync(sdma->dma.dev); - - /* alloc descriptors for this channel */ - for (i = 0; i < sirfsoc_dma_descriptors; i++) { - sdesc = kzalloc(sizeof(*sdesc), gfp_kernel); - if (!sdesc) { - dev_notice(sdma->dma.dev, "memory allocation error. " - "allocated only %u descriptors ", i); - break; - } - - dma_async_tx_descriptor_init(&sdesc->desc, chan); - sdesc->desc.flags = dma_ctrl_ack; - sdesc->desc.tx_submit = sirfsoc_dma_tx_submit; - - list_add_tail(&sdesc->node, &descs); - } - - /* return error only if no descriptors were allocated */ - if (i == 0) - return -enomem; - - spin_lock_irqsave(&schan->lock, flags); - - list_splice_tail_init(&descs, &schan->free); - spin_unlock_irqrestore(&schan->lock, flags); - - return i; -} - -/* free channel resources */ -static void sirfsoc_dma_free_chan_resources(struct dma_chan *chan) -{ - struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan); - struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan); - struct sirfsoc_dma_desc *sdesc, *tmp; - unsigned long flags; - list_head(descs); - - spin_lock_irqsave(&schan->lock, flags); - - /* channel must be idle */ - bug_on(!list_empty(&schan->prepared)); - bug_on(!list_empty(&schan->queued)); - bug_on(!list_empty(&schan->active)); - bug_on(!list_empty(&schan->completed)); - - /* move data */ - list_splice_tail_init(&schan->free, &descs); - - spin_unlock_irqrestore(&schan->lock, flags); - - /* free descriptors */ - list_for_each_entry_safe(sdesc, tmp, &descs, node) - kfree(sdesc); - - pm_runtime_put(sdma->dma.dev); -} - -/* send pending descriptor to hardware */ -static void sirfsoc_dma_issue_pending(struct dma_chan *chan) -{ - struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan); - unsigned long flags; - - spin_lock_irqsave(&schan->lock, flags); - - if (list_empty(&schan->active) && !list_empty(&schan->queued)) - sirfsoc_dma_execute(schan); - - spin_unlock_irqrestore(&schan->lock, flags); -} - -/* check request completion status */ -static enum dma_status -sirfsoc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, - struct dma_tx_state *txstate) -{ - struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan); - struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan); - unsigned long flags; - enum dma_status ret; - struct sirfsoc_dma_desc *sdesc; - int cid = schan->chan.chan_id; - unsigned long dma_pos; - unsigned long dma_request_bytes; - unsigned long residue; - - spin_lock_irqsave(&schan->lock, flags); - - if (list_empty(&schan->active)) { - ret = dma_cookie_status(chan, cookie, txstate); - dma_set_residue(txstate, 0); - spin_unlock_irqrestore(&schan->lock, flags); - return ret; - } - sdesc = list_first_entry(&schan->active, struct sirfsoc_dma_desc, node); - if (sdesc->cyclic) - dma_request_bytes = (sdesc->xlen + 1) * (sdesc->ylen + 1) * - (sdesc->width * sirfsoc_dma_word_len); - else - dma_request_bytes = sdesc->xlen * sirfsoc_dma_word_len; - - ret = dma_cookie_status(chan, cookie, txstate); - - if (sdma->type == sirfsoc_dma_ver_a7v2) - cid = 0; - - if (sdma->type == sirfsoc_dma_ver_a7v2) { - dma_pos = readl_relaxed(sdma->base + sirfsoc_dma_cur_data_addr); - } else { - dma_pos = readl_relaxed( - sdma->base + cid * 0x10 + sirfsoc_dma_ch_addr) << 2; - } - - residue = dma_request_bytes - (dma_pos - sdesc->addr); - dma_set_residue(txstate, residue); - - spin_unlock_irqrestore(&schan->lock, flags); - - return ret; -} - -static struct dma_async_tx_descriptor *sirfsoc_dma_prep_interleaved( - struct dma_chan *chan, struct dma_interleaved_template *xt, - unsigned long flags) -{ - struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan); - struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan); - struct sirfsoc_dma_desc *sdesc = null; - unsigned long iflags; - int ret; - - if ((xt->dir != dma_mem_to_dev) && (xt->dir != dma_dev_to_mem)) { - ret = -einval; - goto err_dir; - } - - /* get free descriptor */ - spin_lock_irqsave(&schan->lock, iflags); - if (!list_empty(&schan->free)) { - sdesc = list_first_entry(&schan->free, struct sirfsoc_dma_desc, - node); - list_del(&sdesc->node); - } - spin_unlock_irqrestore(&schan->lock, iflags); - - if (!sdesc) { - /* try to free completed descriptors */ - sirfsoc_dma_process_completed(sdma); - ret = 0; - goto no_desc; - } - - /* place descriptor in prepared list */ - spin_lock_irqsave(&schan->lock, iflags); - - /* - * number of chunks in a frame can only be 1 for prima2 - * and ylen (number of frame - 1) must be at least 0 - */ - if ((xt->frame_size == 1) && (xt->numf > 0)) { - sdesc->cyclic = 0; - sdesc->xlen = xt->sgl[0].size / sirfsoc_dma_word_len; - sdesc->width = (xt->sgl[0].size + xt->sgl[0].icg) / - sirfsoc_dma_word_len; - sdesc->ylen = xt->numf - 1; - if (xt->dir == dma_mem_to_dev) { - sdesc->addr = xt->src_start; - sdesc->dir = 1; - } else { - sdesc->addr = xt->dst_start; - sdesc->dir = 0; - } - - list_add_tail(&sdesc->node, &schan->prepared); - } else { - pr_err("sirfsoc dma invalid xfer "); - ret = -einval; - goto err_xfer; - } - spin_unlock_irqrestore(&schan->lock, iflags); - - return &sdesc->desc; -err_xfer: - spin_unlock_irqrestore(&schan->lock, iflags); -no_desc: -err_dir: - return err_ptr(ret); -} - -static struct dma_async_tx_descriptor * -sirfsoc_dma_prep_cyclic(struct dma_chan *chan, dma_addr_t addr, - size_t buf_len, size_t period_len, - enum dma_transfer_direction direction, unsigned long flags) -{ - struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan); - struct sirfsoc_dma_desc *sdesc = null; - unsigned long iflags; - - /* - * we only support cycle transfer with 2 period - * if the x-length is set to 0, it would be the loop mode. - * the dma address keeps increasing until reaching the end of a loop - * area whose size is defined by (dma_width x (y_length + 1)). then - * the dma address goes back to the beginning of this area. - * in loop mode, the dma data region is divided into two parts, bufa - * and bufb. dma controller generates interrupts twice in each loop: - * when the dma address reaches the end of bufa or the end of the - * bufb - */ - if (buf_len != 2 * period_len) - return err_ptr(-einval); - - /* get free descriptor */ - spin_lock_irqsave(&schan->lock, iflags); - if (!list_empty(&schan->free)) { - sdesc = list_first_entry(&schan->free, struct sirfsoc_dma_desc, - node); - list_del(&sdesc->node); - } - spin_unlock_irqrestore(&schan->lock, iflags); - - if (!sdesc) - return null; - - /* place descriptor in prepared list */ - spin_lock_irqsave(&schan->lock, iflags); - sdesc->addr = addr; - sdesc->cyclic = 1; - sdesc->xlen = 0; - sdesc->ylen = buf_len / sirfsoc_dma_word_len - 1; - sdesc->width = 1; - list_add_tail(&sdesc->node, &schan->prepared); - spin_unlock_irqrestore(&schan->lock, iflags); - - return &sdesc->desc; -} - -/* - * the dma controller consists of 16 independent dma channels. - * each channel is allocated to a different function - */ -bool sirfsoc_dma_filter_id(struct dma_chan *chan, void *chan_id) -{ - unsigned int ch_nr = (unsigned int) chan_id; - - if (ch_nr == chan->chan_id + - chan->device->dev_id * sirfsoc_dma_channels) - return true; - - return false; -} -export_symbol(sirfsoc_dma_filter_id); - -#define sirfsoc_dma_buswidths \ - (bit(dma_slave_buswidth_undefined) | \ - bit(dma_slave_buswidth_1_byte) | \ - bit(dma_slave_buswidth_2_bytes) | \ - bit(dma_slave_buswidth_4_bytes) | \ - bit(dma_slave_buswidth_8_bytes)) - -static struct dma_chan *of_dma_sirfsoc_xlate(struct of_phandle_args *dma_spec, - struct of_dma *ofdma) -{ - struct sirfsoc_dma *sdma = ofdma->of_dma_data; - unsigned int request = dma_spec->args[0]; - - if (request >= sirfsoc_dma_channels) - return null; - - return dma_get_slave_channel(&sdma->channels[request].chan); -} - -static int sirfsoc_dma_probe(struct platform_device *op) -{ - struct device_node *dn = op->dev.of_node; - struct device *dev = &op->dev; - struct dma_device *dma; - struct sirfsoc_dma *sdma; - struct sirfsoc_dma_chan *schan; - struct sirfsoc_dmadata *data; - struct resource res; - ulong regs_start, regs_size; - u32 id; - int ret, i; - - sdma = devm_kzalloc(dev, sizeof(*sdma), gfp_kernel); - if (!sdma) - return -enomem; - - data = (struct sirfsoc_dmadata *) - (of_match_device(op->dev.driver->of_match_table, - &op->dev)->data); - sdma->exec_desc = data->exec; - sdma->type = data->type; - - if (of_property_read_u32(dn, "cell-index", &id)) { - dev_err(dev, "fail to get dmac index "); - return -enodev; - } - - sdma->irq = irq_of_parse_and_map(dn, 0); - if (!sdma->irq) { - dev_err(dev, "error mapping irq! "); - return -einval; - } - - sdma->clk = devm_clk_get(dev, null); - if (is_err(sdma->clk)) { - dev_err(dev, "failed to get a clock. "); - return ptr_err(sdma->clk); - } - - ret = of_address_to_resource(dn, 0, &res); - if (ret) { - dev_err(dev, "error parsing memory region! "); - goto irq_dispose; - } - - regs_start = res.start; - regs_size = resource_size(&res); - - sdma->base = devm_ioremap(dev, regs_start, regs_size); - if (!sdma->base) { - dev_err(dev, "error mapping memory region! "); - ret = -enomem; - goto irq_dispose; - } - - ret = request_irq(sdma->irq, &sirfsoc_dma_irq, 0, drv_name, sdma); - if (ret) { - dev_err(dev, "error requesting irq! "); - ret = -einval; - goto irq_dispose; - } - - dma = &sdma->dma; - dma->dev = dev; - - dma->device_alloc_chan_resources = sirfsoc_dma_alloc_chan_resources; - dma->device_free_chan_resources = sirfsoc_dma_free_chan_resources; - dma->device_issue_pending = sirfsoc_dma_issue_pending; - dma->device_config = sirfsoc_dma_slave_config; - dma->device_pause = sirfsoc_dma_pause_chan; - dma->device_resume = sirfsoc_dma_resume_chan; - dma->device_terminate_all = sirfsoc_dma_terminate_all; - dma->device_tx_status = sirfsoc_dma_tx_status; - dma->device_prep_interleaved_dma = sirfsoc_dma_prep_interleaved; - dma->device_prep_dma_cyclic = sirfsoc_dma_prep_cyclic; - dma->src_addr_widths = sirfsoc_dma_buswidths; - dma->dst_addr_widths = sirfsoc_dma_buswidths; - dma->directions = bit(dma_dev_to_mem) | bit(dma_mem_to_dev); - - init_list_head(&dma->channels); - dma_cap_set(dma_slave, dma->cap_mask); - dma_cap_set(dma_cyclic, dma->cap_mask); - dma_cap_set(dma_interleave, dma->cap_mask); - dma_cap_set(dma_private, dma->cap_mask); - - for (i = 0; i < sirfsoc_dma_channels; i++) { - schan = &sdma->channels[i]; - - schan->chan.device = dma; - dma_cookie_init(&schan->chan); - - init_list_head(&schan->free); - init_list_head(&schan->prepared); - init_list_head(&schan->queued); - init_list_head(&schan->active); - init_list_head(&schan->completed); - - spin_lock_init(&schan->lock); - list_add_tail(&schan->chan.device_node, &dma->channels); - } - - tasklet_setup(&sdma->tasklet, sirfsoc_dma_tasklet); - - /* register dma engine */ - dev_set_drvdata(dev, sdma); - - ret = dma_async_device_register(dma); - if (ret) - goto free_irq; - - /* device-tree dma controller registration */ - ret = of_dma_controller_register(dn, of_dma_sirfsoc_xlate, sdma); - if (ret) { - dev_err(dev, "failed to register dma controller "); - goto unreg_dma_dev; - } - - pm_runtime_enable(&op->dev); - dev_info(dev, "initialized sirfsoc dmac driver "); - - return 0; - -unreg_dma_dev: - dma_async_device_unregister(dma); -free_irq: - free_irq(sdma->irq, sdma); -irq_dispose: - irq_dispose_mapping(sdma->irq); - return ret; -} - -static int sirfsoc_dma_remove(struct platform_device *op) -{ - struct device *dev = &op->dev; - struct sirfsoc_dma *sdma = dev_get_drvdata(dev); - - of_dma_controller_free(op->dev.of_node); - dma_async_device_unregister(&sdma->dma); - free_irq(sdma->irq, sdma); - tasklet_kill(&sdma->tasklet); - irq_dispose_mapping(sdma->irq); - pm_runtime_disable(&op->dev); - if (!pm_runtime_status_suspended(&op->dev)) - sirfsoc_dma_runtime_suspend(&op->dev); - - return 0; -} - -static int __maybe_unused sirfsoc_dma_runtime_suspend(struct device *dev) -{ - struct sirfsoc_dma *sdma = dev_get_drvdata(dev); - - clk_disable_unprepare(sdma->clk); - return 0; -} - -static int __maybe_unused sirfsoc_dma_runtime_resume(struct device *dev) -{ - struct sirfsoc_dma *sdma = dev_get_drvdata(dev); - int ret; - - ret = clk_prepare_enable(sdma->clk); - if (ret < 0) { - dev_err(dev, "clk_enable failed: %d ", ret); - return ret; - } - return 0; -} - -static int __maybe_unused sirfsoc_dma_pm_suspend(struct device *dev) -{ - struct sirfsoc_dma *sdma = dev_get_drvdata(dev); - struct sirfsoc_dma_regs *save = &sdma->regs_save; - struct sirfsoc_dma_chan *schan; - int ch; - int ret; - int count; - u32 int_offset; - - /* - * if we were runtime-suspended before, resume to enable clock - * before accessing register - */ - if (pm_runtime_status_suspended(dev)) { - ret = sirfsoc_dma_runtime_resume(dev); - if (ret < 0) - return ret; - } - - if (sdma->type == sirfsoc_dma_ver_a7v2) { - count = 1; - int_offset = sirfsoc_dma_int_en_atlas7; - } else { - count = sirfsoc_dma_channels; - int_offset = sirfsoc_dma_int_en; - } - - /* - * dma controller will lose all registers while suspending - * so we need to save registers for active channels - */ - for (ch = 0; ch < count; ch++) { - schan = &sdma->channels[ch]; - if (list_empty(&schan->active)) - continue; - save->ctrl[ch] = readl_relaxed(sdma->base + - ch * 0x10 + sirfsoc_dma_ch_ctrl); - } - save->interrupt_en = readl_relaxed(sdma->base + int_offset); - - /* disable clock */ - sirfsoc_dma_runtime_suspend(dev); - - return 0; -} - -static int __maybe_unused sirfsoc_dma_pm_resume(struct device *dev) -{ - struct sirfsoc_dma *sdma = dev_get_drvdata(dev); - struct sirfsoc_dma_regs *save = &sdma->regs_save; - struct sirfsoc_dma_desc *sdesc; - struct sirfsoc_dma_chan *schan; - int ch; - int ret; - int count; - u32 int_offset; - u32 width_offset; - - /* enable clock before accessing register */ - ret = sirfsoc_dma_runtime_resume(dev); - if (ret < 0) - return ret; - - if (sdma->type == sirfsoc_dma_ver_a7v2) { - count = 1; - int_offset = sirfsoc_dma_int_en_atlas7; - width_offset = sirfsoc_dma_width_atlas7; - } else { - count = sirfsoc_dma_channels; - int_offset = sirfsoc_dma_int_en; - width_offset = sirfsoc_dma_width_0; - } - - writel_relaxed(save->interrupt_en, sdma->base + int_offset); - for (ch = 0; ch < count; ch++) { - schan = &sdma->channels[ch]; - if (list_empty(&schan->active)) - continue; - sdesc = list_first_entry(&schan->active, - struct sirfsoc_dma_desc, - node); - writel_relaxed(sdesc->width, - sdma->base + width_offset + ch * 4); - writel_relaxed(sdesc->xlen, - sdma->base + ch * 0x10 + sirfsoc_dma_ch_xlen); - writel_relaxed(sdesc->ylen, - sdma->base + ch * 0x10 + sirfsoc_dma_ch_ylen); - writel_relaxed(save->ctrl[ch], - sdma->base + ch * 0x10 + sirfsoc_dma_ch_ctrl); - if (sdma->type == sirfsoc_dma_ver_a7v2) { - writel_relaxed(sdesc->addr, - sdma->base + sirfsoc_dma_ch_addr); - } else { - writel_relaxed(sdesc->addr >> 2, - sdma->base + ch * 0x10 + sirfsoc_dma_ch_addr); - - } - } - - /* if we were runtime-suspended before, suspend again */ - if (pm_runtime_status_suspended(dev)) - sirfsoc_dma_runtime_suspend(dev); - - return 0; -} - -static const struct dev_pm_ops sirfsoc_dma_pm_ops = { - set_runtime_pm_ops(sirfsoc_dma_runtime_suspend, sirfsoc_dma_runtime_resume, null) - set_system_sleep_pm_ops(sirfsoc_dma_pm_suspend, sirfsoc_dma_pm_resume) -}; - -static struct sirfsoc_dmadata sirfsoc_dmadata_a6 = { - .exec = sirfsoc_dma_execute_hw_a6, - .type = sirfsoc_dma_ver_a6, -}; - -static struct sirfsoc_dmadata sirfsoc_dmadata_a7v1 = { - .exec = sirfsoc_dma_execute_hw_a7v1, - .type = sirfsoc_dma_ver_a7v1, -}; - -static struct sirfsoc_dmadata sirfsoc_dmadata_a7v2 = { - .exec = sirfsoc_dma_execute_hw_a7v2, - .type = sirfsoc_dma_ver_a7v2, -}; - -static const struct of_device_id sirfsoc_dma_match[] = { - { .compatible = "sirf,prima2-dmac", .data = &sirfsoc_dmadata_a6,}, - { .compatible = "sirf,atlas7-dmac", .data = &sirfsoc_dmadata_a7v1,}, - { .compatible = "sirf,atlas7-dmac-v2", .data = &sirfsoc_dmadata_a7v2,}, - {}, -}; -module_device_table(of, sirfsoc_dma_match); - -static struct platform_driver sirfsoc_dma_driver = { - .probe = sirfsoc_dma_probe, - .remove = sirfsoc_dma_remove, - .driver = { - .name = drv_name, - .pm = &sirfsoc_dma_pm_ops, - .of_match_table = sirfsoc_dma_match, - }, -}; - -static __init int sirfsoc_dma_init(void) -{ - return platform_driver_register(&sirfsoc_dma_driver); -} - -static void __exit sirfsoc_dma_exit(void) -{ - platform_driver_unregister(&sirfsoc_dma_driver); -} - -subsys_initcall(sirfsoc_dma_init); -module_exit(sirfsoc_dma_exit); - -module_author("rongjun ying <rongjun.ying@csr.com>"); -module_author("barry song <baohua.song@csr.com>"); -module_description("sirfsoc dma control driver"); -module_license("gpl v2"); diff --git a/include/linux/sirfsoc_dma.h b/include/linux/sirfsoc_dma.h --- a/include/linux/sirfsoc_dma.h +++ /dev/null -/* spdx-license-identifier: gpl-2.0 */ -#ifndef _sirfsoc_dma_h_ -#define _sirfsoc_dma_h_ - -bool sirfsoc_dma_filter_id(struct dma_chan *chan, void *chan_id); - -#endif
|
DMA engines
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ec6ab42f5aadd765b0b8c4e2d21508ac1e20f2ed
|
arnd bergmann barry song baohua kernel org
|
include
|
linux
|
bindings, dma
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dmaengine: remove zte zx driver
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the zte zx platform is getting removed, so this driver is no longer needed.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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remove zte zx driver
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
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[]
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['txt', 'kconfig', 'c', 'makefile']
| 4
| 0
| 989
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--- diff --git a/documentation/devicetree/bindings/dma/zxdma.txt b/documentation/devicetree/bindings/dma/zxdma.txt --- a/documentation/devicetree/bindings/dma/zxdma.txt +++ /dev/null -* zte zx296702 dma controller - -required properties: -- compatible: should be "zte,zx296702-dma" -- reg: should contain dma registers location and length. -- interrupts: should contain one interrupt shared by all channel -- #dma-cells: see dma.txt, should be 1, para number -- dma-channels: physical channels supported -- dma-requests: virtual channels supported, each virtual channel - have specific request line -- clocks: clock required - -example: - -controller: - dma: dma-controller@09c00000{ - compatible = "zte,zx296702-dma"; - reg = <0x09c00000 0x1000>; - clocks = <&topclk zx296702_dma_aclk>; - interrupts = <gic_spi 66 irq_type_level_high>; - #dma-cells = <1>; - dma-channels = <24>; - dma-requests = <24>; - }; - -client: -use specific request line passing from dmax -for example, spdif0 tx channel request line is 4 - spdif0: spdif0@b004000 { - #sound-dai-cells = <0>; - compatible = "zte,zx296702-spdif"; - reg = <0x0b004000 0x1000>; - clocks = <&lsp0clk zx296702_spdif0_div>; - clock-names = "tx"; - interrupts = <gic_spi 21 irq_type_level_high>; - dmas = <&dma 4>; - dma-names = "tx"; - } diff --git a/drivers/dma/kconfig b/drivers/dma/kconfig --- a/drivers/dma/kconfig +++ b/drivers/dma/kconfig -config zx_dma - tristate "zte zx dma support" - depends on arch_zx || compile_test - select dma_engine - select dma_virtual_channels - help - support the dma engine for zte zx family platform devices. - - diff --git a/drivers/dma/makefile b/drivers/dma/makefile --- a/drivers/dma/makefile +++ b/drivers/dma/makefile -obj-$(config_zx_dma) += zx_dma.o diff --git a/drivers/dma/zx_dma.c b/drivers/dma/zx_dma.c --- a/drivers/dma/zx_dma.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-only -/* - * copyright 2015 linaro. - */ -#include <linux/sched.h> -#include <linux/device.h> -#include <linux/dmaengine.h> -#include <linux/dma-mapping.h> -#include <linux/dmapool.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/slab.h> -#include <linux/spinlock.h> -#include <linux/of_device.h> -#include <linux/of.h> -#include <linux/clk.h> -#include <linux/of_dma.h> - -#include "virt-dma.h" - -#define driver_name "zx-dma" -#define dma_align 4 -#define dma_max_size (0x10000 - 512) -#define lli_block_size (4 * page_size) - -#define reg_zx_src_addr 0x00 -#define reg_zx_dst_addr 0x04 -#define reg_zx_tx_x_count 0x08 -#define reg_zx_tx_zy_count 0x0c -#define reg_zx_src_zy_step 0x10 -#define reg_zx_dst_zy_step 0x14 -#define reg_zx_lli_addr 0x1c -#define reg_zx_ctrl 0x20 -#define reg_zx_tc_irq 0x800 -#define reg_zx_src_err_irq 0x804 -#define reg_zx_dst_err_irq 0x808 -#define reg_zx_cfg_err_irq 0x80c -#define reg_zx_tc_irq_raw 0x810 -#define reg_zx_src_err_irq_raw 0x814 -#define reg_zx_dst_err_irq_raw 0x818 -#define reg_zx_cfg_err_irq_raw 0x81c -#define reg_zx_status 0x820 -#define reg_zx_dma_grp_prio 0x824 -#define reg_zx_dma_arb 0x828 - -#define zx_force_close bit(31) -#define zx_dst_burst_width(x) (((x) & 0x7) << 13) -#define zx_max_burst_len 16 -#define zx_src_burst_len(x) (((x) & 0xf) << 9) -#define zx_src_burst_width(x) (((x) & 0x7) << 6) -#define zx_irq_enable_all (3 << 4) -#define zx_dst_fifo_mode bit(3) -#define zx_src_fifo_mode bit(2) -#define zx_soft_req bit(1) -#define zx_ch_enable bit(0) - -#define zx_dma_buswidths \ - (bit(dma_slave_buswidth_undefined) | \ - bit(dma_slave_buswidth_1_byte) | \ - bit(dma_slave_buswidth_2_bytes) | \ - bit(dma_slave_buswidth_4_bytes) | \ - bit(dma_slave_buswidth_8_bytes)) - -enum zx_dma_burst_width { - zx_dma_width_8bit = 0, - zx_dma_width_16bit = 1, - zx_dma_width_32bit = 2, - zx_dma_width_64bit = 3, -}; - -struct zx_desc_hw { - u32 saddr; - u32 daddr; - u32 src_x; - u32 src_zy; - u32 src_zy_step; - u32 dst_zy_step; - u32 reserved1; - u32 lli; - u32 ctr; - u32 reserved[7]; /* pack as hardware registers region size */ -} __aligned(32); - -struct zx_dma_desc_sw { - struct virt_dma_desc vd; - dma_addr_t desc_hw_lli; - size_t desc_num; - size_t size; - struct zx_desc_hw *desc_hw; -}; - -struct zx_dma_phy; - -struct zx_dma_chan { - struct dma_slave_config slave_cfg; - int id; /* request phy chan id */ - u32 ccfg; - u32 cyclic; - struct virt_dma_chan vc; - struct zx_dma_phy *phy; - struct list_head node; - dma_addr_t dev_addr; - enum dma_status status; -}; - -struct zx_dma_phy { - u32 idx; - void __iomem *base; - struct zx_dma_chan *vchan; - struct zx_dma_desc_sw *ds_run; - struct zx_dma_desc_sw *ds_done; -}; - -struct zx_dma_dev { - struct dma_device slave; - void __iomem *base; - spinlock_t lock; /* lock for ch and phy */ - struct list_head chan_pending; - struct zx_dma_phy *phy; - struct zx_dma_chan *chans; - struct clk *clk; - struct dma_pool *pool; - u32 dma_channels; - u32 dma_requests; - int irq; -}; - -#define to_zx_dma(dmadev) container_of(dmadev, struct zx_dma_dev, slave) - -static struct zx_dma_chan *to_zx_chan(struct dma_chan *chan) -{ - return container_of(chan, struct zx_dma_chan, vc.chan); -} - -static void zx_dma_terminate_chan(struct zx_dma_phy *phy, struct zx_dma_dev *d) -{ - u32 val = 0; - - val = readl_relaxed(phy->base + reg_zx_ctrl); - val &= ~zx_ch_enable; - val |= zx_force_close; - writel_relaxed(val, phy->base + reg_zx_ctrl); - - val = 0x1 << phy->idx; - writel_relaxed(val, d->base + reg_zx_tc_irq_raw); - writel_relaxed(val, d->base + reg_zx_src_err_irq_raw); - writel_relaxed(val, d->base + reg_zx_dst_err_irq_raw); - writel_relaxed(val, d->base + reg_zx_cfg_err_irq_raw); -} - -static void zx_dma_set_desc(struct zx_dma_phy *phy, struct zx_desc_hw *hw) -{ - writel_relaxed(hw->saddr, phy->base + reg_zx_src_addr); - writel_relaxed(hw->daddr, phy->base + reg_zx_dst_addr); - writel_relaxed(hw->src_x, phy->base + reg_zx_tx_x_count); - writel_relaxed(0, phy->base + reg_zx_tx_zy_count); - writel_relaxed(0, phy->base + reg_zx_src_zy_step); - writel_relaxed(0, phy->base + reg_zx_dst_zy_step); - writel_relaxed(hw->lli, phy->base + reg_zx_lli_addr); - writel_relaxed(hw->ctr, phy->base + reg_zx_ctrl); -} - -static u32 zx_dma_get_curr_lli(struct zx_dma_phy *phy) -{ - return readl_relaxed(phy->base + reg_zx_lli_addr); -} - -static u32 zx_dma_get_chan_stat(struct zx_dma_dev *d) -{ - return readl_relaxed(d->base + reg_zx_status); -} - -static void zx_dma_init_state(struct zx_dma_dev *d) -{ - /* set same priority */ - writel_relaxed(0x0, d->base + reg_zx_dma_arb); - /* clear all irq */ - writel_relaxed(0xffffffff, d->base + reg_zx_tc_irq_raw); - writel_relaxed(0xffffffff, d->base + reg_zx_src_err_irq_raw); - writel_relaxed(0xffffffff, d->base + reg_zx_dst_err_irq_raw); - writel_relaxed(0xffffffff, d->base + reg_zx_cfg_err_irq_raw); -} - -static int zx_dma_start_txd(struct zx_dma_chan *c) -{ - struct zx_dma_dev *d = to_zx_dma(c->vc.chan.device); - struct virt_dma_desc *vd = vchan_next_desc(&c->vc); - - if (!c->phy) - return -eagain; - - if (bit(c->phy->idx) & zx_dma_get_chan_stat(d)) - return -eagain; - - if (vd) { - struct zx_dma_desc_sw *ds = - container_of(vd, struct zx_dma_desc_sw, vd); - /* - * fetch and remove request from vc->desc_issued - * so vc->desc_issued only contains desc pending - */ - list_del(&ds->vd.node); - c->phy->ds_run = ds; - c->phy->ds_done = null; - /* start dma */ - zx_dma_set_desc(c->phy, ds->desc_hw); - return 0; - } - c->phy->ds_done = null; - c->phy->ds_run = null; - return -eagain; -} - -static void zx_dma_task(struct zx_dma_dev *d) -{ - struct zx_dma_phy *p; - struct zx_dma_chan *c, *cn; - unsigned pch, pch_alloc = 0; - unsigned long flags; - - /* check new dma request of running channel in vc->desc_issued */ - list_for_each_entry_safe(c, cn, &d->slave.channels, - vc.chan.device_node) { - spin_lock_irqsave(&c->vc.lock, flags); - p = c->phy; - if (p && p->ds_done && zx_dma_start_txd(c)) { - /* no current txd associated with this channel */ - dev_dbg(d->slave.dev, "pchan %u: free ", p->idx); - /* mark this channel free */ - c->phy = null; - p->vchan = null; - } - spin_unlock_irqrestore(&c->vc.lock, flags); - } - - /* check new channel request in d->chan_pending */ - spin_lock_irqsave(&d->lock, flags); - while (!list_empty(&d->chan_pending)) { - c = list_first_entry(&d->chan_pending, - struct zx_dma_chan, node); - p = &d->phy[c->id]; - if (!p->vchan) { - /* remove from d->chan_pending */ - list_del_init(&c->node); - pch_alloc |= 1 << c->id; - /* mark this channel allocated */ - p->vchan = c; - c->phy = p; - } else { - dev_dbg(d->slave.dev, "pchan %u: busy! ", c->id); - } - } - spin_unlock_irqrestore(&d->lock, flags); - - for (pch = 0; pch < d->dma_channels; pch++) { - if (pch_alloc & (1 << pch)) { - p = &d->phy[pch]; - c = p->vchan; - if (c) { - spin_lock_irqsave(&c->vc.lock, flags); - zx_dma_start_txd(c); - spin_unlock_irqrestore(&c->vc.lock, flags); - } - } - } -} - -static irqreturn_t zx_dma_int_handler(int irq, void *dev_id) -{ - struct zx_dma_dev *d = (struct zx_dma_dev *)dev_id; - struct zx_dma_phy *p; - struct zx_dma_chan *c; - u32 tc = readl_relaxed(d->base + reg_zx_tc_irq); - u32 serr = readl_relaxed(d->base + reg_zx_src_err_irq); - u32 derr = readl_relaxed(d->base + reg_zx_dst_err_irq); - u32 cfg = readl_relaxed(d->base + reg_zx_cfg_err_irq); - u32 i, irq_chan = 0, task = 0; - - while (tc) { - i = __ffs(tc); - tc &= ~bit(i); - p = &d->phy[i]; - c = p->vchan; - if (c) { - spin_lock(&c->vc.lock); - if (c->cyclic) { - vchan_cyclic_callback(&p->ds_run->vd); - } else { - vchan_cookie_complete(&p->ds_run->vd); - p->ds_done = p->ds_run; - task = 1; - } - spin_unlock(&c->vc.lock); - irq_chan |= bit(i); - } - } - - if (serr || derr || cfg) - dev_warn(d->slave.dev, "dma err src 0x%x, dst 0x%x, cfg 0x%x ", - serr, derr, cfg); - - writel_relaxed(irq_chan, d->base + reg_zx_tc_irq_raw); - writel_relaxed(serr, d->base + reg_zx_src_err_irq_raw); - writel_relaxed(derr, d->base + reg_zx_dst_err_irq_raw); - writel_relaxed(cfg, d->base + reg_zx_cfg_err_irq_raw); - - if (task) - zx_dma_task(d); - return irq_handled; -} - -static void zx_dma_free_chan_resources(struct dma_chan *chan) -{ - struct zx_dma_chan *c = to_zx_chan(chan); - struct zx_dma_dev *d = to_zx_dma(chan->device); - unsigned long flags; - - spin_lock_irqsave(&d->lock, flags); - list_del_init(&c->node); - spin_unlock_irqrestore(&d->lock, flags); - - vchan_free_chan_resources(&c->vc); - c->ccfg = 0; -} - -static enum dma_status zx_dma_tx_status(struct dma_chan *chan, - dma_cookie_t cookie, - struct dma_tx_state *state) -{ - struct zx_dma_chan *c = to_zx_chan(chan); - struct zx_dma_phy *p; - struct virt_dma_desc *vd; - unsigned long flags; - enum dma_status ret; - size_t bytes = 0; - - ret = dma_cookie_status(&c->vc.chan, cookie, state); - if (ret == dma_complete || !state) - return ret; - - spin_lock_irqsave(&c->vc.lock, flags); - p = c->phy; - ret = c->status; - - /* - * if the cookie is on our issue queue, then the residue is - * its total size. - */ - vd = vchan_find_desc(&c->vc, cookie); - if (vd) { - bytes = container_of(vd, struct zx_dma_desc_sw, vd)->size; - } else if ((!p) || (!p->ds_run)) { - bytes = 0; - } else { - struct zx_dma_desc_sw *ds = p->ds_run; - u32 clli = 0, index = 0; - - bytes = 0; - clli = zx_dma_get_curr_lli(p); - index = (clli - ds->desc_hw_lli) / - sizeof(struct zx_desc_hw) + 1; - for (; index < ds->desc_num; index++) { - bytes += ds->desc_hw[index].src_x; - /* end of lli */ - if (!ds->desc_hw[index].lli) - break; - } - } - spin_unlock_irqrestore(&c->vc.lock, flags); - dma_set_residue(state, bytes); - return ret; -} - -static void zx_dma_issue_pending(struct dma_chan *chan) -{ - struct zx_dma_chan *c = to_zx_chan(chan); - struct zx_dma_dev *d = to_zx_dma(chan->device); - unsigned long flags; - int issue = 0; - - spin_lock_irqsave(&c->vc.lock, flags); - /* add request to vc->desc_issued */ - if (vchan_issue_pending(&c->vc)) { - spin_lock(&d->lock); - if (!c->phy && list_empty(&c->node)) { - /* if new channel, add chan_pending */ - list_add_tail(&c->node, &d->chan_pending); - issue = 1; - dev_dbg(d->slave.dev, "vchan %p: issued ", &c->vc); - } - spin_unlock(&d->lock); - } else { - dev_dbg(d->slave.dev, "vchan %p: nothing to issue ", &c->vc); - } - spin_unlock_irqrestore(&c->vc.lock, flags); - - if (issue) - zx_dma_task(d); -} - -static void zx_dma_fill_desc(struct zx_dma_desc_sw *ds, dma_addr_t dst, - dma_addr_t src, size_t len, u32 num, u32 ccfg) -{ - if ((num + 1) < ds->desc_num) - ds->desc_hw[num].lli = ds->desc_hw_lli + (num + 1) * - sizeof(struct zx_desc_hw); - ds->desc_hw[num].saddr = src; - ds->desc_hw[num].daddr = dst; - ds->desc_hw[num].src_x = len; - ds->desc_hw[num].ctr = ccfg; -} - -static struct zx_dma_desc_sw *zx_alloc_desc_resource(int num, - struct dma_chan *chan) -{ - struct zx_dma_chan *c = to_zx_chan(chan); - struct zx_dma_desc_sw *ds; - struct zx_dma_dev *d = to_zx_dma(chan->device); - int lli_limit = lli_block_size / sizeof(struct zx_desc_hw); - - if (num > lli_limit) { - dev_dbg(chan->device->dev, "vch %p: sg num %d exceed max %d ", - &c->vc, num, lli_limit); - return null; - } - - ds = kzalloc(sizeof(*ds), gfp_atomic); - if (!ds) - return null; - - ds->desc_hw = dma_pool_zalloc(d->pool, gfp_nowait, &ds->desc_hw_lli); - if (!ds->desc_hw) { - dev_dbg(chan->device->dev, "vch %p: dma alloc fail ", &c->vc); - kfree(ds); - return null; - } - ds->desc_num = num; - return ds; -} - -static enum zx_dma_burst_width zx_dma_burst_width(enum dma_slave_buswidth width) -{ - switch (width) { - case dma_slave_buswidth_1_byte: - case dma_slave_buswidth_2_bytes: - case dma_slave_buswidth_4_bytes: - case dma_slave_buswidth_8_bytes: - return ffs(width) - 1; - default: - return zx_dma_width_32bit; - } -} - -static int zx_pre_config(struct zx_dma_chan *c, enum dma_transfer_direction dir) -{ - struct dma_slave_config *cfg = &c->slave_cfg; - enum zx_dma_burst_width src_width; - enum zx_dma_burst_width dst_width; - u32 maxburst = 0; - - switch (dir) { - case dma_mem_to_mem: - c->ccfg = zx_ch_enable | zx_soft_req - | zx_src_burst_len(zx_max_burst_len - 1) - | zx_src_burst_width(zx_dma_width_32bit) - | zx_dst_burst_width(zx_dma_width_32bit); - break; - case dma_mem_to_dev: - c->dev_addr = cfg->dst_addr; - /* dst len is calculated from src width, len and dst width. - * we need make sure dst len not exceed max len. - * trailing single transaction that does not fill a full - * burst also require identical src/dst data width. - */ - dst_width = zx_dma_burst_width(cfg->dst_addr_width); - maxburst = cfg->dst_maxburst; - maxburst = maxburst < zx_max_burst_len ? - maxburst : zx_max_burst_len; - c->ccfg = zx_dst_fifo_mode | zx_ch_enable - | zx_src_burst_len(maxburst - 1) - | zx_src_burst_width(dst_width) - | zx_dst_burst_width(dst_width); - break; - case dma_dev_to_mem: - c->dev_addr = cfg->src_addr; - src_width = zx_dma_burst_width(cfg->src_addr_width); - maxburst = cfg->src_maxburst; - maxburst = maxburst < zx_max_burst_len ? - maxburst : zx_max_burst_len; - c->ccfg = zx_src_fifo_mode | zx_ch_enable - | zx_src_burst_len(maxburst - 1) - | zx_src_burst_width(src_width) - | zx_dst_burst_width(src_width); - break; - default: - return -einval; - } - return 0; -} - -static struct dma_async_tx_descriptor *zx_dma_prep_memcpy( - struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, - size_t len, unsigned long flags) -{ - struct zx_dma_chan *c = to_zx_chan(chan); - struct zx_dma_desc_sw *ds; - size_t copy = 0; - int num = 0; - - if (!len) - return null; - - if (zx_pre_config(c, dma_mem_to_mem)) - return null; - - num = div_round_up(len, dma_max_size); - - ds = zx_alloc_desc_resource(num, chan); - if (!ds) - return null; - - ds->size = len; - num = 0; - - do { - copy = min_t(size_t, len, dma_max_size); - zx_dma_fill_desc(ds, dst, src, copy, num++, c->ccfg); - - src += copy; - dst += copy; - len -= copy; - } while (len); - - c->cyclic = 0; - ds->desc_hw[num - 1].lli = 0; /* end of link */ - ds->desc_hw[num - 1].ctr |= zx_irq_enable_all; - return vchan_tx_prep(&c->vc, &ds->vd, flags); -} - -static struct dma_async_tx_descriptor *zx_dma_prep_slave_sg( - struct dma_chan *chan, struct scatterlist *sgl, unsigned int sglen, - enum dma_transfer_direction dir, unsigned long flags, void *context) -{ - struct zx_dma_chan *c = to_zx_chan(chan); - struct zx_dma_desc_sw *ds; - size_t len, avail, total = 0; - struct scatterlist *sg; - dma_addr_t addr, src = 0, dst = 0; - int num = sglen, i; - - if (!sgl) - return null; - - if (zx_pre_config(c, dir)) - return null; - - for_each_sg(sgl, sg, sglen, i) { - avail = sg_dma_len(sg); - if (avail > dma_max_size) - num += div_round_up(avail, dma_max_size) - 1; - } - - ds = zx_alloc_desc_resource(num, chan); - if (!ds) - return null; - - c->cyclic = 0; - num = 0; - for_each_sg(sgl, sg, sglen, i) { - addr = sg_dma_address(sg); - avail = sg_dma_len(sg); - total += avail; - - do { - len = min_t(size_t, avail, dma_max_size); - - if (dir == dma_mem_to_dev) { - src = addr; - dst = c->dev_addr; - } else if (dir == dma_dev_to_mem) { - src = c->dev_addr; - dst = addr; - } - - zx_dma_fill_desc(ds, dst, src, len, num++, c->ccfg); - - addr += len; - avail -= len; - } while (avail); - } - - ds->desc_hw[num - 1].lli = 0; /* end of link */ - ds->desc_hw[num - 1].ctr |= zx_irq_enable_all; - ds->size = total; - return vchan_tx_prep(&c->vc, &ds->vd, flags); -} - -static struct dma_async_tx_descriptor *zx_dma_prep_dma_cyclic( - struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, - size_t period_len, enum dma_transfer_direction dir, - unsigned long flags) -{ - struct zx_dma_chan *c = to_zx_chan(chan); - struct zx_dma_desc_sw *ds; - dma_addr_t src = 0, dst = 0; - int num_periods = buf_len / period_len; - int buf = 0, num = 0; - - if (period_len > dma_max_size) { - dev_err(chan->device->dev, "maximum period size exceeded "); - return null; - } - - if (zx_pre_config(c, dir)) - return null; - - ds = zx_alloc_desc_resource(num_periods, chan); - if (!ds) - return null; - c->cyclic = 1; - - while (buf < buf_len) { - if (dir == dma_mem_to_dev) { - src = dma_addr; - dst = c->dev_addr; - } else if (dir == dma_dev_to_mem) { - src = c->dev_addr; - dst = dma_addr; - } - zx_dma_fill_desc(ds, dst, src, period_len, num++, - c->ccfg | zx_irq_enable_all); - dma_addr += period_len; - buf += period_len; - } - - ds->desc_hw[num - 1].lli = ds->desc_hw_lli; - ds->size = buf_len; - return vchan_tx_prep(&c->vc, &ds->vd, flags); -} - -static int zx_dma_config(struct dma_chan *chan, - struct dma_slave_config *cfg) -{ - struct zx_dma_chan *c = to_zx_chan(chan); - - if (!cfg) - return -einval; - - memcpy(&c->slave_cfg, cfg, sizeof(*cfg)); - - return 0; -} - -static int zx_dma_terminate_all(struct dma_chan *chan) -{ - struct zx_dma_chan *c = to_zx_chan(chan); - struct zx_dma_dev *d = to_zx_dma(chan->device); - struct zx_dma_phy *p = c->phy; - unsigned long flags; - list_head(head); - - dev_dbg(d->slave.dev, "vchan %p: terminate all ", &c->vc); - - /* prevent this channel being scheduled */ - spin_lock(&d->lock); - list_del_init(&c->node); - spin_unlock(&d->lock); - - /* clear the tx descriptor lists */ - spin_lock_irqsave(&c->vc.lock, flags); - vchan_get_all_descriptors(&c->vc, &head); - if (p) { - /* vchan is assigned to a pchan - stop the channel */ - zx_dma_terminate_chan(p, d); - c->phy = null; - p->vchan = null; - p->ds_run = null; - p->ds_done = null; - } - spin_unlock_irqrestore(&c->vc.lock, flags); - vchan_dma_desc_free_list(&c->vc, &head); - - return 0; -} - -static int zx_dma_transfer_pause(struct dma_chan *chan) -{ - struct zx_dma_chan *c = to_zx_chan(chan); - u32 val = 0; - - val = readl_relaxed(c->phy->base + reg_zx_ctrl); - val &= ~zx_ch_enable; - writel_relaxed(val, c->phy->base + reg_zx_ctrl); - - return 0; -} - -static int zx_dma_transfer_resume(struct dma_chan *chan) -{ - struct zx_dma_chan *c = to_zx_chan(chan); - u32 val = 0; - - val = readl_relaxed(c->phy->base + reg_zx_ctrl); - val |= zx_ch_enable; - writel_relaxed(val, c->phy->base + reg_zx_ctrl); - - return 0; -} - -static void zx_dma_free_desc(struct virt_dma_desc *vd) -{ - struct zx_dma_desc_sw *ds = - container_of(vd, struct zx_dma_desc_sw, vd); - struct zx_dma_dev *d = to_zx_dma(vd->tx.chan->device); - - dma_pool_free(d->pool, ds->desc_hw, ds->desc_hw_lli); - kfree(ds); -} - -static const struct of_device_id zx6702_dma_dt_ids[] = { - { .compatible = "zte,zx296702-dma", }, - {} -}; -module_device_table(of, zx6702_dma_dt_ids); - -static struct dma_chan *zx_of_dma_simple_xlate(struct of_phandle_args *dma_spec, - struct of_dma *ofdma) -{ - struct zx_dma_dev *d = ofdma->of_dma_data; - unsigned int request = dma_spec->args[0]; - struct dma_chan *chan; - struct zx_dma_chan *c; - - if (request >= d->dma_requests) - return null; - - chan = dma_get_any_slave_channel(&d->slave); - if (!chan) { - dev_err(d->slave.dev, "get channel fail in %s. ", __func__); - return null; - } - c = to_zx_chan(chan); - c->id = request; - dev_info(d->slave.dev, "zx_dma: pchan %u: alloc vchan %p ", - c->id, &c->vc); - return chan; -} - -static int zx_dma_probe(struct platform_device *op) -{ - struct zx_dma_dev *d; - int i, ret = 0; - - d = devm_kzalloc(&op->dev, sizeof(*d), gfp_kernel); - if (!d) - return -enomem; - - d->base = devm_platform_ioremap_resource(op, 0); - if (is_err(d->base)) - return ptr_err(d->base); - - of_property_read_u32((&op->dev)->of_node, - "dma-channels", &d->dma_channels); - of_property_read_u32((&op->dev)->of_node, - "dma-requests", &d->dma_requests); - if (!d->dma_requests || !d->dma_channels) - return -einval; - - d->clk = devm_clk_get(&op->dev, null); - if (is_err(d->clk)) { - dev_err(&op->dev, "no dma clk "); - return ptr_err(d->clk); - } - - d->irq = platform_get_irq(op, 0); - ret = devm_request_irq(&op->dev, d->irq, zx_dma_int_handler, - 0, driver_name, d); - if (ret) - return ret; - - /* a dma memory pool for llis, align on 32-byte boundary */ - d->pool = dmam_pool_create(driver_name, &op->dev, - lli_block_size, 32, 0); - if (!d->pool) - return -enomem; - - /* init phy channel */ - d->phy = devm_kcalloc(&op->dev, - d->dma_channels, sizeof(struct zx_dma_phy), gfp_kernel); - if (!d->phy) - return -enomem; - - for (i = 0; i < d->dma_channels; i++) { - struct zx_dma_phy *p = &d->phy[i]; - - p->idx = i; - p->base = d->base + i * 0x40; - } - - init_list_head(&d->slave.channels); - dma_cap_set(dma_slave, d->slave.cap_mask); - dma_cap_set(dma_memcpy, d->slave.cap_mask); - dma_cap_set(dma_cyclic, d->slave.cap_mask); - dma_cap_set(dma_private, d->slave.cap_mask); - d->slave.dev = &op->dev; - d->slave.device_free_chan_resources = zx_dma_free_chan_resources; - d->slave.device_tx_status = zx_dma_tx_status; - d->slave.device_prep_dma_memcpy = zx_dma_prep_memcpy; - d->slave.device_prep_slave_sg = zx_dma_prep_slave_sg; - d->slave.device_prep_dma_cyclic = zx_dma_prep_dma_cyclic; - d->slave.device_issue_pending = zx_dma_issue_pending; - d->slave.device_config = zx_dma_config; - d->slave.device_terminate_all = zx_dma_terminate_all; - d->slave.device_pause = zx_dma_transfer_pause; - d->slave.device_resume = zx_dma_transfer_resume; - d->slave.copy_align = dma_align; - d->slave.src_addr_widths = zx_dma_buswidths; - d->slave.dst_addr_widths = zx_dma_buswidths; - d->slave.directions = bit(dma_mem_to_mem) | bit(dma_mem_to_dev) - | bit(dma_dev_to_mem); - d->slave.residue_granularity = dma_residue_granularity_segment; - - /* init virtual channel */ - d->chans = devm_kcalloc(&op->dev, - d->dma_requests, sizeof(struct zx_dma_chan), gfp_kernel); - if (!d->chans) - return -enomem; - - for (i = 0; i < d->dma_requests; i++) { - struct zx_dma_chan *c = &d->chans[i]; - - c->status = dma_in_progress; - init_list_head(&c->node); - c->vc.desc_free = zx_dma_free_desc; - vchan_init(&c->vc, &d->slave); - } - - /* enable clock before accessing registers */ - ret = clk_prepare_enable(d->clk); - if (ret < 0) { - dev_err(&op->dev, "clk_prepare_enable failed: %d ", ret); - goto zx_dma_out; - } - - zx_dma_init_state(d); - - spin_lock_init(&d->lock); - init_list_head(&d->chan_pending); - platform_set_drvdata(op, d); - - ret = dma_async_device_register(&d->slave); - if (ret) - goto clk_dis; - - ret = of_dma_controller_register((&op->dev)->of_node, - zx_of_dma_simple_xlate, d); - if (ret) - goto of_dma_register_fail; - - dev_info(&op->dev, "initialized "); - return 0; - -of_dma_register_fail: - dma_async_device_unregister(&d->slave); -clk_dis: - clk_disable_unprepare(d->clk); -zx_dma_out: - return ret; -} - -static int zx_dma_remove(struct platform_device *op) -{ - struct zx_dma_chan *c, *cn; - struct zx_dma_dev *d = platform_get_drvdata(op); - - /* explictly free the irq */ - devm_free_irq(&op->dev, d->irq, d); - - dma_async_device_unregister(&d->slave); - of_dma_controller_free((&op->dev)->of_node); - - list_for_each_entry_safe(c, cn, &d->slave.channels, - vc.chan.device_node) { - list_del(&c->vc.chan.device_node); - } - clk_disable_unprepare(d->clk); - - return 0; -} - -#ifdef config_pm_sleep -static int zx_dma_suspend_dev(struct device *dev) -{ - struct zx_dma_dev *d = dev_get_drvdata(dev); - u32 stat = 0; - - stat = zx_dma_get_chan_stat(d); - if (stat) { - dev_warn(d->slave.dev, - "chan %d is running fail to suspend ", stat); - return -1; - } - clk_disable_unprepare(d->clk); - return 0; -} - -static int zx_dma_resume_dev(struct device *dev) -{ - struct zx_dma_dev *d = dev_get_drvdata(dev); - int ret = 0; - - ret = clk_prepare_enable(d->clk); - if (ret < 0) { - dev_err(d->slave.dev, "clk_prepare_enable failed: %d ", ret); - return ret; - } - zx_dma_init_state(d); - return 0; -} -#endif - -static simple_dev_pm_ops(zx_dma_pmops, zx_dma_suspend_dev, zx_dma_resume_dev); - -static struct platform_driver zx_pdma_driver = { - .driver = { - .name = driver_name, - .pm = &zx_dma_pmops, - .of_match_table = zx6702_dma_dt_ids, - }, - .probe = zx_dma_probe, - .remove = zx_dma_remove, -}; - -module_platform_driver(zx_pdma_driver); - -module_description("zte zx296702 dma driver"); -module_author("jun nie jun.nie@linaro.org"); -module_license("gpl v2");
|
DMA engines
|
1c8963f830136c26f01af5d2523470a2b958ce80
|
arnd bergmann
|
documentation
|
devicetree
|
bindings, dma
|
dmaengine: ti: k3-udma: add support for burst_size configuration for mem2mem
|
the udma and bcdma can provide higher throughput if the burst_size of the channel is changed from it's default (which is 64 bytes) for ultra-high and high capacity channels.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for burst_size configuration for mem2mem
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['ti', 'k3-udma']
|
['c']
| 1
| 111
| 5
|
--- diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c +#define udma_flag_burst_size bit(3) +#define udma_flags_j7_class (udma_flag_pdma_acc32 | \ + udma_flag_pdma_burst | \ + udma_flag_tdtype | \ + udma_flag_burst_size) + u8 burst_size[3]; +static u8 udma_get_chan_tpl_index(struct udma_tpl *tpl_map, int chan_id) +{ + int i; + + for (i = 0; i < tpl_map->levels; i++) { + if (chan_id >= tpl_map->start_idx[i]) + return i; + } + + return 0; +} + + u8 burst_size = 0; + u8 tpl; + if (ud->match_data->flags & udma_flag_burst_size) { + tpl = udma_get_chan_tpl_index(&ud->tchan_tpl, tchan->id); + + burst_size = ud->match_data->burst_size[tpl]; + } + + if (burst_size) { + req_tx.valid_params |= ti_sci_msg_value_rm_udmap_ch_burst_size_valid; + req_tx.tx_burst_size = burst_size; + } + if (burst_size) { + req_rx.valid_params |= ti_sci_msg_value_rm_udmap_ch_burst_size_valid; + req_rx.rx_burst_size = burst_size; + } + u8 burst_size = 0; + u8 tpl; + + if (ud->match_data->flags & udma_flag_burst_size) { + tpl = udma_get_chan_tpl_index(&ud->bchan_tpl, bchan->id); + + burst_size = ud->match_data->burst_size[tpl]; + } + if (burst_size) { + req_tx.valid_params |= ti_sci_msg_value_rm_udmap_ch_burst_size_valid; + req_tx.tx_burst_size = burst_size; + } + .burst_size = { + ti_sci_rm_udmap_chan_burst_size_64_bytes, /* normal channels */ + ti_sci_rm_udmap_chan_burst_size_64_bytes, /* h channels */ + 0, /* no uh channels */ + }, + .burst_size = { + ti_sci_rm_udmap_chan_burst_size_64_bytes, /* normal channels */ + ti_sci_rm_udmap_chan_burst_size_64_bytes, /* h channels */ + 0, /* no uh channels */ + }, - .flags = udma_flag_pdma_acc32 | udma_flag_pdma_burst | udma_flag_tdtype, + .flags = udma_flags_j7_class, + .burst_size = { + ti_sci_rm_udmap_chan_burst_size_64_bytes, /* normal channels */ + ti_sci_rm_udmap_chan_burst_size_256_bytes, /* h channels */ + ti_sci_rm_udmap_chan_burst_size_256_bytes, /* uh channels */ + }, - .flags = udma_flag_pdma_acc32 | udma_flag_pdma_burst | udma_flag_tdtype, + .flags = udma_flags_j7_class, + .burst_size = { + ti_sci_rm_udmap_chan_burst_size_64_bytes, /* normal channels */ + ti_sci_rm_udmap_chan_burst_size_128_bytes, /* h channels */ + 0, /* no uh channels */ + }, - .flags = udma_flag_pdma_acc32 | udma_flag_pdma_burst | udma_flag_tdtype, + .flags = udma_flags_j7_class, + .burst_size = { + ti_sci_rm_udmap_chan_burst_size_64_bytes, /* normal channels */ + 0, /* no h channels */ + 0, /* no uh channels */ + }, - .flags = udma_flag_pdma_acc32 | udma_flag_pdma_burst | udma_flag_tdtype, + .flags = udma_flags_j7_class, + .burst_size = { + ti_sci_rm_udmap_chan_burst_size_64_bytes, /* normal channels */ + 0, /* no h channels */ + 0, /* no uh channels */ + }, +static enum dmaengine_alignment udma_get_copy_align(struct udma_dev *ud) +{ + const struct udma_match_data *match_data = ud->match_data; + u8 tpl; + + if (!match_data->enable_memcpy_support) + return dmaengine_align_8_bytes; + + /* get the highest tpl level the device supports for memcpy */ + if (ud->bchan_cnt) + tpl = udma_get_chan_tpl_index(&ud->bchan_tpl, 0); + else if (ud->tchan_cnt) + tpl = udma_get_chan_tpl_index(&ud->tchan_tpl, 0); + else + return dmaengine_align_8_bytes; + + switch (match_data->burst_size[tpl]) { + case ti_sci_rm_udmap_chan_burst_size_256_bytes: + return dmaengine_align_256_bytes; + case ti_sci_rm_udmap_chan_burst_size_128_bytes: + return dmaengine_align_128_bytes; + case ti_sci_rm_udmap_chan_burst_size_64_bytes: + fallthrough; + default: + return dmaengine_align_64_bytes; + } +} + - ud->ddev.copy_align = dmaengine_align_8_bytes; + /* configure the copy_align to the maximum burst size the device supports */ + ud->ddev.copy_align = udma_get_copy_align(ud); +
|
DMA engines
|
046d679b5b8194184efb9f0fe6e6e3f9e06d2c90
|
peter ujfalusi
|
drivers
|
dma
|
ti
|
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