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, 2024.
- ^ Milmo, Dan (November 21, 2024). "Google must sell Chrome to end search monopoly, says US justice department". The Guardian. ISSN 0261-3077. Retrieved January 7, 2025.
- ^ Godoy, Jody (December 23, 2024). "Google offers to loosen search deals in US antitrust case remedy". Reuters. Retrieved January 7, 2025.
- ^ Duffy, Jonathan (June 20, 2003). "Google calls in the 'language police'". BBC News. Archived from the original on June 29, 2012. Retrieved April 10, 2019.
- ^ Ash, Karen Artz;
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2. Retrieved April 10, 2019.
- ^ Ash, Karen Artz; Danow, Bret J. ""Google It": The Search Engine's Trademark May Be a Verb, But It's Not Generic". The National Law Review. Archived from the original on April 10, 2019. Retrieved April 10, 2019.
- ^ "Feedback: Weight in dollars squared". New Scientist. June 5, 2013. Archived from the original on April 26, 2021. Retrieved November 8, 2020.
- ^ Schwartz, Barry (May 20, 2013). "Google Drops "Translated Foreign Pages" Search Option Due To Lack Of Use"
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https://en.wikipedia.org/wiki/Google_Search#169
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d Foreign Pages" Search Option Due To Lack Of Use". Search Engine Land. Archived from the original on October 17, 2017. Retrieved December 15, 2017.
- ^ "Google Instant Search: The Complete User's Guide". Search Engine Land. September 8, 2010. Archived from the original on October 20, 2021. Retrieved October 5, 2021.
Google Instant only works for searchers in the US or who are logged in to a Google account in selected countries outside the US
- ^ Mayer, Marissa (September 8, 2010). "Search: now
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https://en.wikipedia.org/wiki/Google_Search#170
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Mayer, Marissa (September 8, 2010). "Search: now faster than the speed of type". Official Google Blog. Archived from the original on December 15, 2017. Retrieved December 15, 2017.
- ^ Wagner, Matt Van (September 20, 2010). "How Google Saved $100 Million By Launching Google Instant". Search Engine Land. Archived from the original on October 19, 2017. Retrieved December 15, 2017.
- ^ Gomes, Ben (September 9, 2010). "Google Instant, behind the scenes". Official Google Blog. Archived from the orig
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nes". Official Google Blog. Archived from the original on December 15, 2017. Retrieved December 15, 2017.
- ^ Pash, Adam (September 8, 2010). "How to Turn Off Google Instant Search". Lifehacker. Univision Communications. Archived from the original on December 16, 2017. Retrieved December 15, 2017.
- ^ Axon, Samuel (September 28, 2010). "Which Words Does Google Instant Blacklist?". Mashable. Ziff Davis. Archived from the original on December 15, 2017. Retrieved December 15, 2017.
- ^ Horn, Leslie
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https://en.wikipedia.org/wiki/Google_Search#172
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017. Retrieved December 15, 2017.
- ^ Horn, Leslie (September 29, 2010). "Google Instant Blacklist: Which Words Are Blocked?". PC Magazine. Ziff Davis. Retrieved December 15, 2017.
- ^ Schwartz, Barry (July 26, 2017). "Google has dropped Google Instant Search". Search Engine Land. Archived from the original on December 15, 2017. Retrieved December 15, 2017.
- ^ Statt, Nick (July 26, 2017). "Google will stop showing search results as you type because it makes no sense on mobile". The Verge. Vox M
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https://en.wikipedia.org/wiki/Google_Search#173
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use it makes no sense on mobile". The Verge. Vox Media. Archived from the original on December 15, 2017. Retrieved December 15, 2017.
- ^ Singel, Ryan (November 9, 2010). "Google Gives Searchers 'Instant Previews' of Result Pages". Wired. Retrieved October 5, 2021.
- ^ "Google Drops Instant Previews Over Low Usage". seroundtable.com. April 25, 2013. Archived from the original on October 5, 2021. Retrieved October 5, 2021.
- ^ "SSL Search: Features – Web Search Help". Web Search Help. May 2010. A
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s – Web Search Help". Web Search Help. May 2010. Archived from the original on May 24, 2010. Retrieved July 7, 2010.
- ^ "Encrypted.google.com". Archived from the original on December 29, 2013. Retrieved August 4, 2012.
- ^ "Google Will Start Encrypting Your Searches". Time. March 13, 2014. Retrieved February 6, 2017.
- ^ "Encrypted.google.com is going away". Google Inc. Archived from the original on March 27, 2018. Retrieved May 18, 2018.
- ^ "Google launches Real-Time Search" Archived January
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oogle launches Real-Time Search" Archived January 26, 2021, at the Wayback Machine. Mashable. Retrieved July 12, 2010.
- ^ "Relevance meets the real-time web" Archived April 7, 2019, at the Wayback Machine. Google. Retrieved July 12, 2010.
- ^ "As Deal With Twitter Expires, Google Realtime Search Goes Offline". Searchengineland.com. July 4, 2011. Archived from the original on November 11, 2013. Retrieved March 3, 2014.
- ^ "Google Real-Time Search Now Includes A Fraction Of Facebook Status Updat
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h Now Includes A Fraction Of Facebook Status Updates" Archived October 31, 2019, at the Wayback Machine. TechCrunch. Retrieved July 12, 2010.
- ^ "Google's Real-Time Search Ready to Challenge Bing" Archived July 6, 2012, at the Wayback Machine. PC World. Retrieved July 12, 2010.
- ^ Quotes delayed at least 15 min (December 31, 1999). "Business news: Financial, stock & investing news online - MSN Money". Money.msn.com. Archived from the original on April 2, 2011. Retrieved March 3, 2014.
{{cite w
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n April 2, 2011. Retrieved March 3, 2014.
{{cite web}}
: CS1 maint: numeric names: authors list (link) - ^ "Google Realtime Search Goes Missing". Searchengineland.com. July 3, 2011. Archived from the original on February 14, 2014. Retrieved March 3, 2014.
Further reading
- Google Hacks from O'Reilly is a book containing tips about using Google effectively. Now in its third edition (2006). ISBN 0-596-52706-3.
- Google: The Missing Manual by Sarah Milstein and Rael Dornfest (O'Reilly, 2004). ISBN
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https://en.wikipedia.org/wiki/Google_Search#178
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Milstein and Rael Dornfest (O'Reilly, 2004). ISBN 0-596-00613-6
- How to Do Everything with Google by Fritz Schneider, Nancy Blachman, and Eric Fredricksen (McGraw-Hill Osborne Media, 2003). ISBN 0-07-223174-2
- Google Power by Chris Sherman (McGraw-Hill Osborne Media, 2005). ISBN 0-07-225787-3
- Barroso, Luiz Andre; Dean, Jeffrey; Hölzle, Urs (2003). "Web Search for a Planet: The Google Cluster Architecture". IEEE Micro. 23 (2): 22–28. doi:10.1109/MM.2003.1196112. ISSN 0272-1732. S2CID 15886858
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https://en.wikipedia.org/wiki/Google_Search#179
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09/MM.2003.1196112. ISSN 0272-1732. S2CID 15886858.
- Broderick, Ryan (August 28, 2023). "The end of the Googleverse". The Verge. Archived from the original on August 28, 2023. Retrieved August 30, 2023.
- Belanger, Ashley (October 27, 2023). "Google loses fight to hide 2021 money pit: $26B in default contracts". Ars Technica. Retrieved October 28, 2023.
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https://en.wikipedia.org/wiki/Michael_Gschwind#0
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Michael Gschwind
Michael Karl Gschwind is an American computer scientist at Nvidia in Santa Clara, California. He is recognized for his seminal contributions to the design and exploitation of general-purpose programmable accelerators, as an early advocate of sustainability in computer design and as a prolific inventor.[1]
Accelerators
[edit]Gschwind led hardware and software architecture for the first general-purpose programmable accelerator Accelerators and is widely recognized for his contribu
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lerators and is widely recognized for his contributionsHeterogeneous computing as architect of the Cell Broadband Engine processor used in the Sony PlayStation 3,[2][3] and RoadRunner, the first supercomputer to reach sustained Petaflop operation. As Chief Architect for IBM System Architecture, he led the integration of Nvidia GPUs and IBM CPUs to create the Summit and Sierra supercomputers.
Gschwind was an early advocate for accelerator virtualization[4][5] and as IBM System Chief Architect led
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zation[4][5] and as IBM System Chief Architect led I/O and accelerator virtualization.[6]
Gschwind has had a critical influence on the development of accelerator programming models with the development of APIs and best practices for accelerator programming,[7][8][9][10][11] application studies for a diverse range of HPC[12] and non-HPC applications.[13] and as co-editor of books[14] and journals[15] on practice and experience of programming accelerator-based systems.
AI acceleration
[edit]Gschwi
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erator-based systems.
AI acceleration
[edit]Gschwind was an early advocate of AI Hardware Acceleration with GPUs and programmable accelerators. As IBM's Chief Engineer for AI, he led the development of IBM's first AI products and initiated the PowerAI project which brought to market AI-optimized hardware (codenamed "Minsky"), and the first prebuilt hardware-optimized AI frameworks. These frameworks were delivered as the firstfreely installable, binary package-managed AI software stacks paving th
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inary package-managed AI software stacks paving the path for adoption.[16]
At Facebook, Gschwind demonstrated accelerated Large Language Models (LLMs) for Facebook's First Generation ASIC accelerators and for GPUs, leading the first LLLM production deployments at scale for embedding serving for content analysis and platform safety, and for numerous user surfaces such as Facebook Assistant, and FB Marketplace starting in 2020.[17] Gschwind led the development of and is one of the architects of Mu
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development of and is one of the architects of Multiray, an accelerator-based platform for serving foundation models and the first production system to serve Large Language Models at scale in the industry, serving over 800 billion queries per day in 2022.[18][19]
Gschwind led the company-wide adoption of ASIC[20] and Facebook's subsequent "strategic pivot" to GPU Inference, deploying GPU Inference at scale, a move highlighted by FB CEO Mark Zuckerburg in his earnings call. Among the first recom
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erburg in his earnings call. Among the first recommendation models deployed with GPU Inference was a Reels video recommendation model which delivered a 30% user surge within 2 weeks of deployment, as reported by FB CEO Mark Zuckerburg in his Q1 2022 earnings call,[21] and a subsequent $3B to $10B growth for REeels year-over-year.[22]
Gschwind also led AI Accelerator Enablement for PyTorch with a particular focus on LLM acceleration, leading the development of Accelerated Transformers[23] (former
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evelopment of Accelerated Transformers[23] (formerly "Better Transformer"[24]) and partnered with companies such as HuggingFace to drive industry-wide LLM Acceleration[25] to establish PyTorch 2.0 as the standard ecosystem for Large Language Models and Generative AI.[26][27][28] [29]
Gschwind subsequently led expanding LLM acceleration to on-device AI models with ExecuTorch, the PyTorch ecosystem solution for on-device AI, making on-device generative AI feasible for the first time.[30] ExecuTorc
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tive AI feasible for the first time.[30] ExecuTorch LLM acceleration (across multiple surfaces including NPUs, MPS, and Qualcomm accelerators) delivered significant speedups making it practical to deploy Llama3 unmodified on servers and on-device (demonstrated on iOS, Android, and Raspberry Pi 5) at launch with developers reporting up to 5x-10x speedups over prior on-device AI solutions.[31][32]
Gschwind's multiple contributions to AI software stacks and frameworks, AI accelerators, mobile/embed
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acks and frameworks, AI accelerators, mobile/embedded on-device AI and low-precision numeric representations in torchchat,[33][34] representing a seminal milestone as the industry's first integrated softwarestack for servers and on-device AI with support for a broad set of server and embedded/mobile accelerators.
Gschwind is a pioneer and advocate of Sustainable AI.[35]
Supercomputer design
[edit]Gschwind was a chief architect for hardware design and software architecture for several supercomput
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and software architecture for several supercomputers, including three top-ranked supercomputer systems Roadrunner (June 2008 – November 2009), Sequoia (June 2012 – November 2012), and Summit (June 2018 – June 2020).
Roadrunner was a supercomputer built by IBM for the Los Alamos National Laboratory in New Mexico, USA. The US$100-million Roadrunner was designed for a peak performance of 1.7 petaflops. It achieved 1.026 petaflops on May 25, 2008, to become the world's first TOP500 LINPACK sustaine
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o become the world's first TOP500 LINPACK sustained 1.0 petaflops system.[36][37] It was also the fourth-most energy-efficient supercomputer in the world on the Supermicro Green500 list, with an operational rate of 444.94 megaflops per watt of power used.
Sequoia was a petascale Blue Gene/Q supercomputer constructed by IBM for the National Nuclear Security Administration as part of the Advanced Simulation and Computing Program (ASC). It was delivered to the Lawrence Livermore National Laboratory
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ered to the Lawrence Livermore National Laboratory (LLNL) in 2011 and was fully deployed in June 2012.[38] Sequoia was dismantled in 2020, its last position on the top500.org list was #22 in the November 2019 list.
Summit is a supercomputer developed by IBM for use at Oak Ridge Leadership Computing Facility (OLCF), a facility at the Oak Ridge National Laboratory. It held the number 1 position from November 2018 to June 2020.[39][40] Its current LINPACK benchmark is clocked at 148.6 petaFLOPS.[41
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INPACK benchmark is clocked at 148.6 petaFLOPS.[41]
Many-core processor design
[edit]Gschwind was an early advocate of many-core processor design to overcome the power and performance limitations of single-processor designs. Gschwind co-authored an analysis of the limitations of frequency scaling which arguably led to an industry-wide transition to many-core designs.[42] Gschwind was a lead architect for several many-core designs, including the first commercial many-core processor Cell with 9 co
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irst commercial many-core processor Cell with 9 cores, BlueGene/Q with 18 cores, and several enterprise and mainframe processors (POWER7/POWER8/POWER9 with up to 24 cores; z10-z15 with up to 12 cores).
As chip chief architect and chief microarchitect, Gschwind was critical to the reboot of the POWER architecture after the POWER6 high-frequency high-power dead-end, leading revival of the POWER5-style out-of-order design with POWER7, serving as unit lead and chief microarchitect for the instructio
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t lead and chief microarchitect for the instruction fetch, decode and branch prediction unit (also including logical instruction execution), and as acting lead for most other units at one point during the design. In subsequent generations of the POWER architecture, integration of the VMX SIMD design and FPU into VSX, little-endian support in POWER8 laying the foundation for little-endian PowerLinux (used in the Google POWER prototype and for GPU integration for the Minsky PowerAI system), and in
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integration for the Minsky PowerAI system), and integration of NVLink for optimized GPU/CPU integration; and native support for Linux-style hardware-managed radix page-tables in POWER9, used in the world-leading Summit and Sierra Power+Nvidia supercomputers; and the introduction of PC-relative addressing and prefix instructions to transcend the limitations of the 32-bit instruction encodings of RISC architectures in POWER 10.
As architecture lead/manager and cross-platform chief architect, Gschw
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/manager and cross-platform chief architect, Gschwind also led the reboot of system z mainframe, with introduction of compiled code efficiency (with a particular view to C, C++ and Java) in IBM z10, out-of-order execution, PCIe-based I/O in z196 and z114, support for transactional memory in IBM zEC12, introduction of hardware multithreading and z/Vector SIMD architecture[43] (including shared software infrastructure with Power's VSX) in IBM z13; and the sunsetting of ESA390 for operating systems
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and the sunsetting of ESA390 for operating systems[44] substantially reducing verification and design complexity and improving time-to-market in IBM z14.
System reliability
[edit]Gschwind coined the term "reliability wall" for obstacles to sustained operation of large-scale systems. He has made major contributions to system-level reliability modeling and improvements, with a particular view to enabling sustained supercomputing system operation. As chief architect of BlueGene/Q, he led system-lev
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s chief architect of BlueGene/Q, he led system-level reliability and processor design in addition to being the chief ISA architect and QPU vector floating point unit design lead.[45][46]
Gschwind led the first processor and chip-level architectural vulnerability modeling and selective hardening to achieve target MTBF, first implemented in BlueGene/Q using stacked DICE latches for critical state-holding latches.[47] To increase system reliability while avoiding the performance and power cost asso
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while avoiding the performance and power cost associated with ECC-based designs, Gschwind proposed and led the design of register files and minor buses protected with parity with state recovery. In accordance with this approach, error detection is implemented in datapaths which may occur in parallel with initiating compute operations, with a recovery operation when a soft error is detected in parallel with the operation. Recovery then proceeds from good-state maintained in alternate copies of th
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om good-state maintained in alternate copies of the register file commonly used to scale the number of register file read portsa and reduce wiring delay from register file reads to execution units.[48]
Compiler technologies
[edit]Gschwind has made seminal contributions to compiler technology, with a particular emphasis on pioneering contributions to just-in-time compilation, dynamic optimization, binary translation and compilers in supercomputing.
Just-in-time-compilation
[edit]Gschwid was an ea
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.
Just-in-time-compilation
[edit]Gschwid was an early proponent of just-in-time compilation and has been a driving force in the field. He has proposed critical improvements for the implementation of JIT compilation based systems, with a particular view to dynamic optimization, binary translation and virtual machine implementation. Gschwind's contributions includes implementation of precise exceptions with deferred state materialization,[49] high-performance computing optimization such as softwar
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performance computing optimization such as software pipelining at JIT translation time,[50][51] hardware/software co-design for binary emulation and dynamic optimization.[52][53][54][55] Gschwind's seminal contributions to Virtual Machine design and implementation are reflected by being the most-cited author in the `Virtual Machines' textbook by Smith and Nair.[56]
Compilation for accelerators and accelerator-based supercomputers
[edit]Gschwind is credited with seminal contributions for compiler
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s credited with seminal contributions for compilers and programming environments for general-purpose programmable accelerators and GPUs, building the first general purpose GPU frameworks, APIs and optimizations for Cell. His contributions include performance monitoring, code partitioning, code optimization, code partitioning and APIs for accelerators. [57] [58] [59] [60] [61] [62]
His innovations include compiler/hardware co-design for integrated register files to resolve phase ordering issues i
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register files to resolve phase ordering issues in auto-vectorization between unit assignment and vectorization decisions to simplify the cost model, an innovation adopted by general-purpose programmable accelerators, including the Cell SPU and GPUs, and general-purpose CPU designs, starting with Gschwind's pioneering work for SIMD CPU accelerators.
More recently, his contributions to HPC compilation have included pioneering work in enabling high-performance execution of AI workloads.[63] [29]
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h-performance execution of AI workloads.[63] [29] [30]
System and compiler APIs
[edit]Gschwind led the development of the ELFv2 Power execution environment, which has been broadly adopted for Power execution environments. Advantageously, the new environment updates the APIs and ABIs for object-oriented environments. Departing from traditional Power architecture big-endian data conventions, the ELFv2 ABI and APIs were first launched to support a new little-endian version of Linux on Power. This h
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ew little-endian version of Linux on Power. This has since been adopted for all Linux versions on Power servers and to support GPU acceleration with Nvidia GPUs, e.g., in the Minsky AI-optimized servers and the Summit and Sierra supercomputers.[64][65][66]
SIMD Parallel vector architecture
[edit]Gschwind is a pioneer of SIMD parallel vector architecture to increase the number of operations which can be performed per cycle. To enable efficient compilation, Gschwind proposed the implementation of
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pilation, Gschwind proposed the implementation of merged scalar and vector execution units, eliminating the cost of copies between scalar and vectorized code, and simplifying compiler architecture by resolving phase ordering problems in compilers.
The Cell's accelerator cores (Synergistic Processor Unit SPU) contain a single 128 element register file with 128 bit per register. Registers may hold either scalar or a vector of multiple values.[67] The simplified cost model leads to significantly im
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he simplified cost model leads to significantly improved vectorization success, improving overall program performance and efficiency.[68]
The vector-scalar approach was also adopted by the IBM Power VSX (Vector Scalar Extension) SIMD instructions,[69] BlueGene/Q vector instructions[70][71] and System/z mainframe vector instruction set,[43][72] the design of all three IBM vector-scalar architectures having been led by Gschwind as Chief Architect for IBM System Architecture.
Service, education, di
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or IBM System Architecture.
Service, education, diversity, inclusion and digital inclusion
[edit]Gschwind is a strong believer in the power of education and its power to help overcome the effects of all types of discrimination and colonialism. He has served as faculty member at [Princeton] and [TU Wien] to advance education. To overcome the effects of colonialism and bridge the digital divide, Gschwind has volunteered in Senegal to contribute to the expansion and improvement of Senegal's educati
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the expansion and improvement of Senegal's education and research network, snRER.
Background
[edit]Gschwind was born in Vienna and obtained his doctorate degree in Computer Engineering at the Technische Universität Wien in 1996. He joined the IBM Thomas J. Watson Research Center in Yorktown Heights, NY and also held positions IBM Systems product group and at its corporate headquarters in Armonk, NY. At Huawei, Gschwind served Vice President of Artificial Intelligence and Accelerated Systems at H
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tificial Intelligence and Accelerated Systems at Huawei. Gschwind is currently a software engineer at Meta Platforms where he has been responsible for AI Acceleration and AI infrastructure.[citation needed]
References
[edit]- ^ "Michael Karl Gschwind". www.ppubs.uspto.gov.
- ^ David Becker (December 3, 2004). "PlayStation 3 chip goes easy on developers". CNET. Retrieved January 13, 2019.
- ^ Scarpino, M. (2008). Programming the cell processor: for games, graphics, and computation. Pearson Educat
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https://en.wikipedia.org/wiki/Michael_Gschwind#33
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r games, graphics, and computation. Pearson Education.
- ^ https://on-demand.gputechconf.com/gtc/2017/presentation/S7320-tim-kaldewey-optimizing-efficiency-of-deep-learning-workloads-through-gpu-virtualization.pdf, https://on-demand.gputechconf.com/gtc/2017/presentation/S7320-tim-kaldewey-optimizing-efficiency-of-deep-learning-workloads-through-gpu-virtualization.pdf
- ^ Optimizing the efficiency of deep learning through accelerator virtualization, https://ieeexplore.ieee.org/document/8030299
-
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n, https://ieeexplore.ieee.org/document/8030299
- ^ I/O Vrtualization and System Acceleration in Power9, https://old.hotchips.org/wp-content/uploads/hc_archives/hc27/HC27.24-Monday-Epub/HC27.24.30-HP-Cloud-Comm-Epub/HC27.24.340-IO-Virtualization-POWER8-Gschwind-IBM.pdf
- ^ Gschwind, Michael (2007-06-01). "The Cell Broadband Engine: Exploiting Multiple Levels of Parallelism in a Chip Multiprocessor". International Journal of Parallel Programming. 35 (3): 233–262. doi:10.1007/s10766-007-0035-4. IS
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https://en.wikipedia.org/wiki/Michael_Gschwind#35
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35 (3): 233–262. doi:10.1007/s10766-007-0035-4. ISSN 1573-7640.
- ^ "ntegrated execution: A programming model for accelerators". Retrieved 2024-09-04.
- ^ Chip Multiprocessing and the Cell Broadband Engine, https://computingfrontiers.org/2006/cf06-gschwind.pdf
- ^ CBE Programming Handbook
- ^ CBE Programming Tutorial, https://public.dhe.ibm.com/software/dw/cell/CBE_Programming_Tutorial_v3.1.pdf
- ^ Shi, Guochun; Kindratenko, Volodymyr; Pratas, Frederico; Trancoso, Pedro; Gschwind, Michael (2010)
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https://en.wikipedia.org/wiki/Michael_Gschwind#36
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ederico; Trancoso, Pedro; Gschwind, Michael (2010). "Application acceleration with the cell broadband engine". Computing in Science and Engineering. 12 (1): 76–81. Bibcode:2010CSE....12a..76S. doi:10.1109/MCSE.2010.4. ISSN 1521-9615.
- ^ Cell GC: using the cell synergistic processor as a garbage collection coprocessor, ACM Virtual Execution Environments, https://dominoweb.draco.res.ibm.com/reports/rc24520.pdf
- ^ M. Gschwind, F. Gustavson, J. Prins (eds), High Performance Computing with the Cell
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https://en.wikipedia.org/wiki/Michael_Gschwind#37
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ns (eds), High Performance Computing with the Cell Broadband Engine Scientific Programming 2009, https://www.semanticscholar.org/paper/High-Performance-Computing-with-the-Cell-Broadband-Gschwind-Gustavson/c6775765100eb3b9eb7b7bc003a8eba1ca90667f
- ^ M. Gschwind, M. Perrone (Eds), Topical Issue On Hybrid Systems IBM Journal of Research and Development 53(5):1-2 September 2009, DOI:10.1147/JRD.2009.5429079
- ^ "PowerAI: A Co-Optimized Software Stack for AI on Power". Retrieved 2024-09-04.
- ^ "Fro
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https://en.wikipedia.org/wiki/Michael_Gschwind#38
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k for AI on Power". Retrieved 2024-09-04.
- ^ "From Ingestion to Deployment for Large Language Models | GTC Digital September 2022 | NVIDIA On-Demand". NVIDIA. Retrieved 2024-09-04.
- ^ "MultiRay: Optimizing efficiency for large-scale AI models". ai.meta.com. Retrieved 2023-10-28.
- ^ MultiRay: An Accelerated Embedding Service for Content Understanding, https://static.sched.com/hosted_files/pytorch2023/60/PyTorch_Conf_2023-Multiray.pdf
- ^ First-Generation Inference Accelerator Deployment at Fac
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https://en.wikipedia.org/wiki/Michael_Gschwind#39
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Generation Inference Accelerator Deployment at Facebook, https://arxiv.org/pdf/2107.04140.pdf
- ^ "Mark Zuckerberg says AI boosts monetization by 30% on Instagram, 40% on Facebook". Yahoo Finance. 2023-04-27. Retrieved 2024-09-04.
- ^ Gairola, Ananya. "From $3B to $10B: Meta's AI-Driven Reels Skyrocketed Revenue Growth Beyond Expectations - Meta Platforms (NASDAQ:META)". Benzinga. Retrieved 2024-09-04.
- ^ "PyTorch". www.pytorch.org. Retrieved 2023-10-28.
- ^ "A BetterTransformer for Fast Transf
|
https://en.wikipedia.org/wiki/Michael_Gschwind#40
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23-10-28.
- ^ "A BetterTransformer for Fast Transformer Inference". pytorch.org. Retrieved 2023-10-28.
- ^ Belkada, Younes (2022-11-21). "BetterTransformer, Out of the Box Performance for Hugging Face Transformers". PyTorch. Retrieved 2024-09-04.
- ^ "PyTorch 2.0: Our next generation release that is faster, more Pythonic and Dynamic as ever". PyTorch. Retrieved 2024-09-04.
- ^ "Accelerated Generative Diffusion Models with PyTorch 2". PyTorch. Retrieved 2024-09-04.
- ^ "Accelerating Large Languag
|
https://en.wikipedia.org/wiki/Michael_Gschwind#41
|
rieved 2024-09-04.
- ^ "Accelerating Large Language Models with Accelerated Transformers". PyTorch. Retrieved 2024-09-04.
- ^ a b Ansel, Jason; Yang, Edward; He, Horace; Gimelshein, Natalia; Jain, Animesh; et al. (27 April 2024). "PyTorch 2: Faster Machine Learning Through Dynamic Python Bytecode Transformation and Graph Compilation". Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '24), Volume 2. ACM. pp. 929–
|
https://en.wikipedia.org/wiki/Michael_Gschwind#42
|
ting Systems (ASPLOS '24), Volume 2. ACM. pp. 929–947. doi:10.1145/3620665.3640366.
- ^ a b "ExecuTorch Alpha: Taking LLMs and AI to the Edge with Our Community and Partners". PyTorch. Retrieved 2024-09-04.
- ^ "Layla v4.6.0 has been published!". Layla. 2024-04-26. Retrieved 2024-09-04.
- ^ "⚡️Blazing fast LLama2-7B-Chat on 8GB RAM Android device via Executorch". r/LocalLLaMA. 2024-05-15. Retrieved 2024-09-04.
- ^ "Introducing torchchat: Accelerating Local LLM Inference on Laptop, Desktop and Mo
|
https://en.wikipedia.org/wiki/Michael_Gschwind#43
|
ting Local LLM Inference on Laptop, Desktop and Mobile". PyTorch. Retrieved 2024-09-04.
- ^ pytorch/torchchat, pytorch, 2024-09-04, retrieved 2024-09-04
- ^ Sustainable AI: Environmental Implications, Challenges and Opportunities, https://arxiv.org/pdf/2111.00364.pdf
- ^ Gaudin, Sharon (2008-06-09). "IBM's Roadrunner smashes 4-minute mile of supercomputing". Computerworld. Archived from the original on 2008-12-24. Retrieved 2008-06-10.
- ^ Fildes, Jonathan (2008-06-09). "Supercomputer sets petaf
|
https://en.wikipedia.org/wiki/Michael_Gschwind#44
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, Jonathan (2008-06-09). "Supercomputer sets petaflop pace". BBC News. Retrieved 2008-06-09.
- ^ NNSA awards IBM contract to build next generation supercomputer, February 3, 2009
- ^ Lohr, Steve (8 June 2018). "Move Over, China: U.S. Is Again Home to World's Speediest Supercomputer". The New York Times. Retrieved 19 July 2018.
- ^ "Top 500 List - November 2022". TOP500. November 2022. Retrieved 13 April 2022.
- ^ "November 2022 | TOP500 Supercomputer Sites". TOP500. Retrieved 13 April 2022.
- ^
|
https://en.wikipedia.org/wiki/Michael_Gschwind#45
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uter Sites". TOP500. Retrieved 13 April 2022.
- ^ "Optimizing pipelines for power and performance". Retrieved 2024-09-04.
- ^ a b Schwarz, E. M.; Krishnamurthy, R. B.; Parris, C. J.; Bradbury, J. D.; Nnebe, I. M.; Gschwind, M. (2015-07-01). "The SIMD accelerator for business analytics on the IBM z13". IBM J. Res. Dev. 59 (4–5): 2:1–2:16. doi:10.1147/JRD.2015.2426576. ISSN 0018-8646.
- ^ Common boot sequence for control utility able to be initialized in multiple architectures, US Patent 9,588,774
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https://en.wikipedia.org/wiki/Michael_Gschwind#46
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zed in multiple architectures, US Patent 9,588,774, https://patents.google.com/patent/US9588774B2
- ^ "Michael Gschwind - ICS 2012 BlueGeneQ keynote presentation". Retrieved 2024-09-04.
- ^ US9081501B2, Asaad, Sameh; Bellofatto, Ralph E. & Blocksome, Michael A. et al., "Multi-petascale highly efficient parallel supercomputer", issued 2015-07-14
- ^ Gschwind, Michael; Salapura, Valentina; Trammell, Catherine; McKee, Sally A. (2011). "SoftBeam: Precise tracking of transient faults and vulnerabilit
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https://en.wikipedia.org/wiki/Michael_Gschwind#47
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cise tracking of transient faults and vulnerability analysis at processor design time". 2011 IEEE 29th International Conference on Computer Design (ICCD). pp. 404–410. doi:10.1109/ICCD.2011.6081430. ISBN 978-1-4577-1954-7. Retrieved 2024-09-04.
- ^ US7512772B2, Gschwind, Michael Karl & Philhower, Robert, "Soft error handling in microprocessors", issued 2009-03-31
- ^ "Efficient instruction scheduling with precise exceptions". Retrieved 2024-09-04.
- ^ "Optimizations and oracle parallelism with d
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https://en.wikipedia.org/wiki/Michael_Gschwind#48
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.
- ^ "Optimizations and oracle parallelism with dynamic translation". Retrieved 2024-09-04.
- ^ "Dynamic and Transparent Binary Translation". Retrieved 2024-09-04.
- ^ "Dynamic binary translation and optimization". Retrieved 2024-09-04.
- ^ Altman, E.R.; Ebcioglu, K.; Gschwind, M.; Sathaye, S. (2001). "Advances and future challenges in binary translation and optimization". Proceedings of the IEEE. 89 (11): 1710–1722. doi:10.1109/5.964447. Retrieved 2024-09-04.
- ^ Binary translation and archite
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https://en.wikipedia.org/wiki/Michael_Gschwind#49
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ved 2024-09-04.
- ^ Binary translation and architecture convergence issues for IBM System/390, https://www.researchgate.net/profile/Michael-Gschwind/publication/221235791_Binary_translation_and_architecture_convergence_issues_for_IBM_system390/links/0046352f27d9de5653000000/Binary-translation-and-architecture-convergence-issues-for-IBM-system-390.pdf
- ^ Advances and future challenges in binary translation and optimization, Proceedings of the IEEE, https://ieeexplore.ieee.org/document/964447
- ^
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https://en.wikipedia.org/wiki/Michael_Gschwind#50
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E, https://ieeexplore.ieee.org/document/964447
- ^ Smith, Nair, Virtual Machines: Versatile Platforms for Systems and Processes, https://www.amazon.com/Virtual-Machines-Versatile-Platforms-Architecture/dp/1558609105
- ^ Valentina Salapura; Karthik Ganesan; Alan Gara; Michael Gschwind; James C. Sexton; Robert E. Walkup (2008). Next-Generation Performance Counters: Towards Monitoring Over Thousand Concurrent Events. ISPASS 2008 - IEEE International Symposium on Performance Analysis of Systems and
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https://en.wikipedia.org/wiki/Michael_Gschwind#51
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Symposium on Performance Analysis of Systems and software. IEEE.
- ^ Eichenberger, Alexandre E.; O'Brien, Kathryn; O'Brien, Kevin; Wu, Peng; Chen, Tong; Oden, Peter H.; Prener, Daniel A.; Shepherd, Janice C.; So, Byoungro; Sura, Zehra; Wang, Amy; Zhang, Tao; Zhao, Peng; Gschwind, Michael (2005-09-17). "14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05)". 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05). PACT '
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https://en.wikipedia.org/wiki/Michael_Gschwind#52
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tures and Compilation Techniques (PACT'05). PACT '05. USA: IEEE Computer Society. pp. 161–172. doi:10.1109/PACT.2005.33. ISBN 978-0-7695-2429-0.
- ^ Gschwind, Michael; Erb, David; Manning, Sid; Nutter, Mark (25 June 2007). "An Open Source Environment for Cell Broadband Engine System Software". Computer. 40 (6). IEEE: 37–47. doi:10.1109/MC.2007.192. ISSN 0018-9162. Retrieved 2024-09-04.
- ^ Michael Gschwind (2006). Chip Multiprocessing and the Cell Broadband Engine (PDF). ACM Computing Frontiers
|
https://en.wikipedia.org/wiki/Michael_Gschwind#53
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l Broadband Engine (PDF). ACM Computing Frontiers 2006 (Keynote speech).
- ^ Gschwind, Michael (2007-06-01). "The Cell Broadband Engine: Exploiting Multiple Levels of Parallelism in a Chip Multiprocessor". International Journal of Parallel Programming. 35 (3): 233–262. doi:10.1007/s10766-007-0035-4. ISSN 1573-7640.
- ^ Gschwind, M. (2009). "Integrated execution: A programming model for accelerators". IBM Journal of Research and Development. 53 (5): 4:1–4:14. doi:10.1147/JRD.2009.5429070.
- ^ "Fi
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https://en.wikipedia.org/wiki/Michael_Gschwind#54
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): 4:1–4:14. doi:10.1147/JRD.2009.5429070.
- ^ "First-Generation Inference Accelerator Deployment at Facebook". research.facebook.com. Retrieved 2024-09-04.
- ^ OpenPOWER Reengineering a server ecosystem for large-scale data centers, https://old.hotchips.org/wp-content/uploads/hc_archives/hc26/HC26-12-day2-epub/HC26.12-7-Dense-Servers-epub/HC26.12.730-%20OpenPower-Gschwind-IBM.pdf
- ^ Power Architecture 64-Bit ELF V2 ABI Specification, https://ftp.rtems.org/pub/rtems/people/sebh/ABI64BitOpenPOWE
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https://en.wikipedia.org/wiki/Michael_Gschwind#55
|
p.rtems.org/pub/rtems/people/sebh/ABI64BitOpenPOWERv1.1_16July2015_pub.pdf
- ^ "Reengineering a server ecosystem for enhanced portability and performance". Retrieved 2024-09-04.
- ^ Gschwind, Michael; Hofstee, H. Peter; Flachs, Brian; Hopkins, Martin; Watanabe, Yukio; Yamazaki, Takeshi (2006). "Synergistic Processing in Cell's Multicore Architecture". IEEE Micro. 26 (2): 10–24. doi:10.1109/MM.2006.41. Retrieved 2024-09-04.
- ^ Eichenberger, Alexandre E.; O'Brien, Kathryn; O'Brien, Kevin; Wu, Pen
|
https://en.wikipedia.org/wiki/Michael_Gschwind#56
|
ndre E.; O'Brien, Kathryn; O'Brien, Kevin; Wu, Peng; Chen, Tong; Oden, Peter H.; Prener, Daniel A.; Shepherd, Janice C.; So, Byoungro; Sura, Zehra; Wang, Amy; Zhang, Tao; Zhao, Peng; Gschwind, Michael (2005-09-17). "Optimizing Compiler for the CELL Processor". 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05). PACT '05. USA: IEEE Computer Society. pp. 161–172. doi:10.1109/PACT.2005.33. ISBN 978-0-7695-2429-0.
- ^ Gschwind, M. (2016). "Workload accelerat
|
https://en.wikipedia.org/wiki/Michael_Gschwind#57
|
29-0.
- ^ Gschwind, M. (2016). "Workload acceleration with the IBM POWER vector-scalar architecture". IBM Journal of Research and Development. 60 (2–3): 14:1–14:18. doi:10.1147/JRD.2016.2527418. Retrieved 2024-09-04.
- ^ Haring, Ruud; Ohmacht, Martin; Fox, Thomas; Gschwind, Michael; Satterfield, David; Sugavanam, Krishnan; Coteus, Paul; Heidelberger, Philip; Blumrich, Matthias; Wisniewski, Robert; Gara, Alan; Chiu, George; Boyle, Peter; Chist, Norman; Kim, Changhoan (2012). "The IBM Blue Gene/Q
|
https://en.wikipedia.org/wiki/Michael_Gschwind#58
|
rman; Kim, Changhoan (2012). "The IBM Blue Gene/Q Compute Chip". IEEE Micro. 32 (2): 48–60. doi:10.1109/MM.2011.108. Retrieved 2024-09-04.
- ^ Morgan, Timothy Prickett (22 November 2010). "IBM uncloaks 20 petaflops BlueGene/Q super". The Register.
- ^ SIMD Processing on IBM z14, z13 and z13s, https://www.ibm.com/downloads/cas/WVPALM0N
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https://en.wikipedia.org/wiki/Central_processing_unit#0
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Central processing unit
A central processing unit (CPU), also called a central processor, main processor, or just processor, is the primary processor in a given computer.[1][2] Its electronic circuitry executes instructions of a computer program, such as arithmetic, logic, controlling, and input/output (I/O) operations.[3][4][5] This role contrasts with that of external components, such as main memory and I/O circuitry,[6] and specialized coprocessors such as graphics processing units (GPUs).
Th
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ssors such as graphics processing units (GPUs).
The form, design, and implementation of CPUs have changed over time, but their fundamental operation remains almost unchanged.[7] Principal components of a CPU include the arithmetic–logic unit (ALU) that performs arithmetic and logic operations, processor registers that supply operands to the ALU and store the results of ALU operations, and a control unit that orchestrates the fetching (from memory), decoding and execution (of instructions) by dir
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), decoding and execution (of instructions) by directing the coordinated operations of the ALU, registers, and other components. Modern CPUs devote a lot of semiconductor area to caches and instruction-level parallelism to increase performance and to CPU modes to support operating systems and virtualization.
Most modern CPUs are implemented on integrated circuit (IC) microprocessors, with one or more CPUs on a single IC chip. Microprocessor chips with multiple CPUs are called multi-core processo
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with multiple CPUs are called multi-core processors.[8] The individual physical CPUs, called processor cores, can also be multithreaded to support CPU-level multithreading.[9]
An IC that contains a CPU may also contain memory, peripheral interfaces, and other components of a computer;[10] such integrated devices are variously called microcontrollers or systems on a chip (SoC).
History
[edit]Early computers such as the ENIAC had to be physically rewired to perform different tasks, which caused t
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rewired to perform different tasks, which caused these machines to be called "fixed-program computers".[11] The "central processing unit" term has been in use since as early as 1955.[12][13] Since the term "CPU" is generally defined as a device for software (computer program) execution, the earliest devices that could rightly be called CPUs came with the advent of the stored-program computer.
The idea of a stored-program computer had already been present in the design of John Presper Eckert and
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present in the design of John Presper Eckert and John William Mauchly's ENIAC, but was initially omitted so that it could be finished sooner.[14] On June 30, 1945, before ENIAC was made, mathematician John von Neumann distributed a paper entitled First Draft of a Report on the EDVAC. It was the outline of a stored-program computer that would eventually be completed in August 1949.[15] EDVAC was designed to perform a certain number of instructions (or operations) of various types. Significantly,
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s (or operations) of various types. Significantly, the programs written for EDVAC were to be stored in high-speed computer memory rather than specified by the physical wiring of the computer.[16] This overcame a severe limitation of ENIAC, which was the considerable time and effort required to reconfigure the computer to perform a new task.[17] With von Neumann's design, the program that EDVAC ran could be changed simply by changing the contents of the memory. EDVAC was not the first stored-prog
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of the memory. EDVAC was not the first stored-program computer; the Manchester Baby, which was a small-scale experimental stored-program computer, ran its first program on 21 June 1948[18] and the Manchester Mark 1 ran its first program during the night of 16–17 June 1949.[19]
Early CPUs were custom designs used as part of a larger and sometimes distinctive computer.[20] However, this method of designing custom CPUs for a particular application has largely given way to the development of multi-p
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as largely given way to the development of multi-purpose processors produced in large quantities. This standardization began in the era of discrete transistor mainframes and minicomputers, and has rapidly accelerated with the popularization of the integrated circuit (IC). The IC has allowed increasingly complex CPUs to be designed and manufactured to tolerances on the order of nanometers.[21] Both the miniaturization and standardization of CPUs have increased the presence of digital devices in m
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ave increased the presence of digital devices in modern life far beyond the limited application of dedicated computing machines. Modern microprocessors appear in electronic devices ranging from automobiles[22] to cellphones,[23] and sometimes even in toys.[24][25]
While von Neumann is most often credited with the design of the stored-program computer because of his design of EDVAC, and the design became known as the von Neumann architecture, others before him, such as Konrad Zuse, had suggested
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rs before him, such as Konrad Zuse, had suggested and implemented similar ideas.[26] The so-called Harvard architecture of the Harvard Mark I, which was completed before EDVAC,[27][28] also used a stored-program design using punched paper tape rather than electronic memory.[29] The key difference between the von Neumann and Harvard architectures is that the latter separates the storage and treatment of CPU instructions and data, while the former uses the same memory space for both.[30] Most mode
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uses the same memory space for both.[30] Most modern CPUs are primarily von Neumann in design, but CPUs with the Harvard architecture are seen as well, especially in embedded applications; for instance, the Atmel AVR microcontrollers are Harvard-architecture processors.[31]
Relays and vacuum tubes (thermionic tubes) were commonly used as switching elements;[32][33] a useful computer requires thousands or tens of thousands of switching devices. The overall speed of a system is dependent on the sp
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e overall speed of a system is dependent on the speed of the switches. Vacuum-tube computers such as EDVAC tended to average eight hours between failures, whereas relay computers—such as the slower but earlier Harvard Mark I—failed very rarely.[13] In the end, tube-based CPUs became dominant because the significant speed advantages afforded generally outweighed the reliability problems. Most of these early synchronous CPUs ran at low clock rates compared to modern microelectronic designs. Clock
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compared to modern microelectronic designs. Clock signal frequencies ranging from 100 kHz to 4 MHz were very common at this time, limited largely by the speed of the switching devices they were built with.[34]
Transistor CPUs
[edit]The design complexity of CPUs increased as various technologies facilitated the building of smaller and more reliable electronic devices. The first such improvement came with the advent of the transistor. Transistorized CPUs during the 1950s and 1960s no longer had to
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d CPUs during the 1950s and 1960s no longer had to be built out of bulky, unreliable, and fragile switching elements, like vacuum tubes and relays.[35] With this improvement, more complex and reliable CPUs were built onto one or several printed circuit boards containing discrete (individual) components.
In 1964, IBM introduced its IBM System/360 computer architecture that was used in a series of computers capable of running the same programs with different speeds and performances.[36] This was s
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different speeds and performances.[36] This was significant at a time when most electronic computers were incompatible with one another, even those made by the same manufacturer. To facilitate this improvement, IBM used the concept of a microprogram (often called "microcode"), which still sees widespread use in modern CPUs.[37] The System/360 architecture was so popular that it dominated the mainframe computer market for decades and left a legacy that is continued by similar modern computers li
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y that is continued by similar modern computers like the IBM zSeries.[38][39] In 1965, Digital Equipment Corporation (DEC) introduced another influential computer aimed at the scientific and research markets—the PDP-8.[40]
Transistor-based computers had several distinct advantages over their predecessors. Aside from facilitating increased reliability and lower power consumption, transistors also allowed CPUs to operate at much higher speeds because of the short switching time of a transistor in
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se of the short switching time of a transistor in comparison to a tube or relay.[41] The increased reliability and dramatically increased speed of the switching elements, which were almost exclusively transistors by this time; CPU clock rates in the tens of megahertz were easily obtained during this period.[42] Additionally, while discrete transistor and IC CPUs were in heavy usage, new high-performance designs like single instruction, multiple data (SIMD) vector processors began to appear.[43]
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ata (SIMD) vector processors began to appear.[43] These early experimental designs later gave rise to the era of specialized supercomputers like those made by Cray Inc and Fujitsu Ltd.[43]
Small-scale integration CPUs
[edit]During this period, a method of manufacturing many interconnected transistors in a compact space was developed. The integrated circuit (IC) allowed a large number of transistors to be manufactured on a single semiconductor-based die, or "chip". At first, only very basic non-s
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ed die, or "chip". At first, only very basic non-specialized digital circuits such as NOR gates were miniaturized into ICs.[44] CPUs based on these "building block" ICs are generally referred to as "small-scale integration" (SSI) devices. SSI ICs, such as the ones used in the Apollo Guidance Computer, usually contained up to a few dozen transistors. To build an entire CPU out of SSI ICs required thousands of individual chips, but still consumed much less space and power than earlier discrete tra
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uch less space and power than earlier discrete transistor designs.[45]
IBM's System/370, follow-on to the System/360, used SSI ICs rather than Solid Logic Technology discrete-transistor modules.[46][47] DEC's PDP-8/I and KI10 PDP-10 also switched from the individual transistors used by the PDP-8 and KA PDP-10 to SSI ICs,[48] and their extremely popular PDP-11 line was originally built with SSI ICs, but was eventually implemented with LSI components once these became practical.
Large-scale integr
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ts once these became practical.
Large-scale integration CPUs
[edit]Lee Boysel published influential articles, including a 1967 "manifesto", which described how to build the equivalent of a 32-bit mainframe computer from a relatively small number of large-scale integration circuits (LSI).[49][50] The only way to build LSI chips, which are chips with a hundred or more gates, was to build them using a metal–oxide–semiconductor (MOS) semiconductor manufacturing process (either PMOS logic, NMOS logic
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nufacturing process (either PMOS logic, NMOS logic, or CMOS logic). However, some companies continued to build processors out of bipolar transistor–transistor logic (TTL) chips because bipolar junction transistors were faster than MOS chips up until the 1970s (a few companies such as Datapoint continued to build processors out of TTL chips until the early 1980s).[50] In the 1960s, MOS ICs were slower and initially considered useful only in applications that required low power.[51][52] Following
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ations that required low power.[51][52] Following the development of silicon-gate MOS technology by Federico Faggin at Fairchild Semiconductor in 1968, MOS ICs largely replaced bipolar TTL as the standard chip technology in the late 1970s.[53]
As the microelectronic technology advanced, an increasing number of transistors were placed on ICs, decreasing the number of individual ICs needed for a complete CPU. MSI and LSI ICs increased transistor counts to hundreds, and then thousands. By 1968, the
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unts to hundreds, and then thousands. By 1968, the number of ICs required to build a complete CPU had been reduced to 24 ICs of eight different types, with each IC containing roughly 1000 MOSFETs.[54] In stark contrast with its SSI and MSI predecessors, the first LSI implementation of the PDP-11 contained a CPU composed of only four LSI integrated circuits.[55]
Microprocessors
[edit]Since microprocessors were first introduced they have almost completely overtaken all other central processing uni
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pletely overtaken all other central processing unit implementation methods. The first commercially available microprocessor, made in 1971, was the Intel 4004, and the first widely used microprocessor, made in 1974, was the Intel 8080. Mainframe and minicomputer manufacturers of the time launched proprietary IC development programs to upgrade their older computer architectures, and eventually produced instruction set compatible microprocessors that were backward-compatible with their older hardwa
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t were backward-compatible with their older hardware and software. Combined with the advent and eventual success of the ubiquitous personal computer, the term CPU is now applied almost exclusively[a] to microprocessors. Several CPUs (denoted cores) can be combined in a single processing chip.[56]
Previous generations of CPUs were implemented as discrete components and numerous small integrated circuits (ICs) on one or more circuit boards.[57] Microprocessors, on the other hand, are CPUs manufact
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roprocessors, on the other hand, are CPUs manufactured on a very small number of ICs; usually just one.[58] The overall smaller CPU size, as a result of being implemented on a single die, means faster switching time because of physical factors like decreased gate parasitic capacitance.[59][60] This has allowed synchronous microprocessors to have clock rates ranging from tens of megahertz to several gigahertz. Additionally, the ability to construct exceedingly small transistors on an IC has incre
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