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https://en.wikipedia.org/wiki/Central_processing_unit#28 | t exceedingly small transistors on an IC has increased the complexity and number of transistors in a single CPU many fold. This widely observed trend is described by Moore's law, which had proven to be a fairly accurate predictor of the growth of CPU (and other IC) complexity until 2016.[61][62]
While the complexity, s... |
https://en.wikipedia.org/wiki/Central_processing_unit#29 | uch at all. Almost all common CPUs today can be very accurately described as von Neumann stored-program machines.[64][b] As Moore's law no longer holds, concerns have arisen about the limits of integrated circuit transistor technology. Extreme miniaturization of electronic gates is causing the effects of phenomena like... |
https://en.wikipedia.org/wiki/Central_processing_unit#30 | s causing researchers to investigate new methods of computing such as the quantum computer, as well as to expand the use of parallelism and other methods that extend the usefulness of the classical von Neumann model.
Operation
[edit]The fundamental operation of most CPUs, regardless of the physical form they take, is t... |
https://en.wikipedia.org/wiki/Central_processing_unit#31 | puter memory. Nearly all CPUs follow the fetch, decode and execute steps in their operation, which are collectively known as the instruction cycle.
After the execution of an instruction, the entire process repeats, with the next instruction cycle normally fetching the next-in-sequence instruction because of the increme... |
https://en.wikipedia.org/wiki/Central_processing_unit#32 | of the instruction that was jumped to and program execution continues normally. In more complex CPUs, multiple instructions can be fetched, decoded and executed simultaneously. This section describes what is generally referred to as the "classic RISC pipeline", which is quite common among the simple CPUs used in many e... |
https://en.wikipedia.org/wiki/Central_processing_unit#33 | tage of the pipeline.
Some instructions manipulate the program counter rather than producing result data directly; such instructions are generally called "jumps" and facilitate program behavior like loops, conditional program execution (through the use of a conditional jump), and existence of functions.[c] In some proc... |
https://en.wikipedia.org/wiki/Central_processing_unit#34 | behaves, since they often indicate the outcome of various operations. For example, in such processors a "compare" instruction evaluates two values and sets or clears bits in the flags register to indicate which one is greater or whether they are equal; one of these flags could then be used by a later jump instruction t... |
https://en.wikipedia.org/wiki/Central_processing_unit#35 | umbers) from program memory. The instruction's location (address) in program memory is determined by the program counter (PC; called the "instruction pointer" in Intel x86 microprocessors), which stores a number that identifies the address of the next instruction to be fetched. After an instruction is fetched, the PC i... |
https://en.wikipedia.org/wiki/Central_processing_unit#36 | en, the instruction to be fetched must be retrieved from relatively slow memory, causing the CPU to stall while waiting for the instruction to be returned. This issue is largely addressed in modern processors by caches and pipeline architectures (see below).
Decode
[edit]The instruction that the CPU fetches from memory... |
https://en.wikipedia.org/wiki/Central_processing_unit#37 | instruction is converted into signals that control other parts of the CPU.
The way in which the instruction is interpreted is defined by the CPU's instruction set architecture (ISA).[e] Often, one group of bits (that is, a "field") within the instruction, called the opcode, indicates which operation is to be performed,... |
https://en.wikipedia.org/wiki/Central_processing_unit#38 | nds may be specified as a constant value (called an immediate value), or as the location of a value that may be a processor register or a memory address, as determined by some addressing mode.
In some CPU designs, the instruction decoder is implemented as a hardwired, unchangeable binary decoder circuit. In others, a m... |
https://en.wikipedia.org/wiki/Central_processing_unit#39 | lock pulses. In some cases the memory that stores the microprogram is rewritable, making it possible to change the way in which the CPU decodes instructions.
Execute
[edit]After the fetch and decode steps, the execute step is performed. Depending on the CPU architecture, this may consist of a single action or a sequenc... |
https://en.wikipedia.org/wiki/Central_processing_unit#40 | or part of the desired operation. The action is then completed, typically in response to a clock pulse. Very often the results are written to an internal CPU register for quick access by subsequent instructions. In other cases results may be written to slower, but less expensive and higher capacity main memory.
For exa... |
https://en.wikipedia.org/wiki/Central_processing_unit#41 | ed, as are the parts of the arithmetic logic unit (ALU) that perform addition. When the clock pulse occurs, the operands flow from the source registers into the ALU, and the sum appears at its output. On subsequent clock pulses, other components are enabled (and disabled) to move the output (the sum of the operation) t... |
https://en.wikipedia.org/wiki/Central_processing_unit#42 | arithmetic overflow flag will be set, influencing the next operation.
Structure and implementation
[edit]Hardwired into a CPU's circuitry is a set of basic operations it can perform, called an instruction set. Such operations may involve, for example, adding or subtracting two numbers, comparing two numbers, or jumping... |
https://en.wikipedia.org/wiki/Central_processing_unit#43 | opcode. While processing an instruction, the CPU decodes the opcode (via a binary decoder) into control signals, which orchestrate the behavior of the CPU. A complete machine language instruction consists of an opcode and, in many cases, additional bits that specify arguments for the operation (for example, the numbers... |
https://en.wikipedia.org/wiki/Central_processing_unit#44 | machine language instructions that the CPU executes.
The actual mathematical operation for each instruction is performed by a combinational logic circuit within the CPU's processor known as the arithmetic–logic unit or ALU. In general, a CPU executes an instruction by fetching it from memory, using its ALU to perform a... |
https://en.wikipedia.org/wiki/Central_processing_unit#45 | s other machine instructions exist, such as those for loading data from memory and storing it back, branching operations, and mathematical operations on floating-point numbers performed by the CPU's floating-point unit (FPU).[68]
Control unit
[edit]The control unit (CU) is a component of the CPU that directs the operat... |
https://en.wikipedia.org/wiki/Central_processing_unit#46 | instructions that have been sent to the processor.
It directs the operation of the other units by providing timing and control signals. Most computer resources are managed by the CU. It directs the flow of data between the CPU and the other devices. John von Neumann included the control unit as part of the von Neumann ... |
https://en.wikipedia.org/wiki/Central_processing_unit#47 | ration unchanged since its introduction.[69]
Arithmetic logic unit
[edit]The arithmetic logic unit (ALU) is a digital circuit within the processor that performs integer arithmetic and bitwise logic operations. The inputs to the ALU are the data words to be operated on (called operands), status information from previous... |
https://en.wikipedia.org/wiki/Central_processing_unit#48 | the operands may come from internal CPU registers, external memory, or constants generated by the ALU itself.
When all input signals have settled and propagated through the ALU circuitry, the result of the performed operation appears at the ALU's outputs. The result consists of both a data word, which may be stored in ... |
https://en.wikipedia.org/wiki/Central_processing_unit#49 | e.
Modern CPUs typically contain more than one ALU to improve performance.
Address generation unit
[edit]The address generation unit (AGU), sometimes also called the address computation unit (ACU),[70] is an execution unit inside the CPU that calculates addresses used by the CPU to access main memory. By having address... |
https://en.wikipedia.org/wiki/Central_processing_unit#50 | for executing various machine instructions can be reduced, bringing performance improvements.
While performing various operations, CPUs need to calculate memory addresses required for fetching data from the memory; for example, in-memory positions of array elements must be calculated before the CPU can fetch the data f... |
https://en.wikipedia.org/wiki/Central_processing_unit#51 | on, subtraction, modulo operations, or bit shifts. Often, calculating a memory address involves more than one general-purpose machine instruction, which do not necessarily decode and execute quickly. By incorporating an AGU into a CPU design, together with introducing specialized instructions that use the AGU, various ... |
https://en.wikipedia.org/wiki/Central_processing_unit#52 | .
Capabilities of an AGU depend on a particular CPU and its architecture. Thus, some AGUs implement and expose more address-calculation operations, while some also include more advanced specialized instructions that can operate on multiple operands at a time. Some CPU architectures include multiple AGUs so more than on... |
https://en.wikipedia.org/wiki/Central_processing_unit#53 | ar nature of advanced CPU designs. For example, Intel incorporates multiple AGUs into its Sandy Bridge and Haswell microarchitectures, which increase bandwidth of the CPU memory subsystem by allowing multiple memory-access instructions to be executed in parallel.
Memory management unit (MMU)
[edit]Many microprocessors ... |
https://en.wikipedia.org/wiki/Central_processing_unit#54 | RAM addresses, providing memory protection and paging abilities, useful for virtual memory. Simpler processors, especially microcontrollers, usually don't include an MMU.
Cache
[edit]A CPU cache[71] is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) t... |
https://en.wikipedia.org/wiki/Central_processing_unit#55 | ta from frequently used main memory locations. Most CPUs have different independent caches, including instruction and data caches, where the data cache is usually organized as a hierarchy of several cache levels (L1, L2, L3, L4, etc.). Each ascending cache level is typically slower but larger than the preceding level w... |
https://en.wikipedia.org/wiki/Central_processing_unit#56 | els of CPU caches. The first CPUs that used a cache had only one level of cache; unlike later level 1 caches, it was not split into L1d (for data) and L1i (for instructions). Almost all current CPUs with caches have a split L1 cache. They also have L2 caches and, for larger processors, L3 caches as well. The L2 cache i... |
https://en.wikipedia.org/wiki/Central_processing_unit#57 | icated L2 cache and is usually not shared between the cores. The L3 cache, and higher-level caches, are shared between the cores and are not split. An L4 cache is currently uncommon, and is generally on dynamic random-access memory (DRAM), rather than on static random-access memory (SRAM), on a separate die or chip. Th... |
https://en.wikipedia.org/wiki/Central_processing_unit#58 | the possible exception of the last level. Each extra level of cache tends to be bigger and is optimized differently.
Other types of caches exist (that are not counted towards the "cache size" of the most important caches mentioned above), such as the translation lookaside buffer (TLB) that is part of the memory managem... |
https://en.wikipedia.org/wiki/Central_processing_unit#59 | s, although the IBM z13 has a 96 KiB L1 instruction cache.[72]
Clock rate
[edit]Most CPUs are synchronous circuits, which means they employ a clock signal to pace their sequential operations. The clock signal is produced by an external oscillator circuit that generates a consistent number of pulses each second in the f... |
https://en.wikipedia.org/wiki/Central_processing_unit#60 | sequently, the faster the clock, the more instructions the CPU will execute each second.
To ensure proper operation of the CPU, the clock period is longer than the maximum time needed for all signals to propagate (move) through the CPU. In setting the clock period to a value well above the worst-case propagation delay,... |
https://en.wikipedia.org/wiki/Central_processing_unit#61 | has the advantage of simplifying the CPU significantly, both from a design perspective and a component-count perspective. However, it also carries the disadvantage that the entire CPU must wait on its slowest elements, even though some portions of it are much faster. This limitation has largely been compensated for by ... |
https://en.wikipedia.org/wiki/Central_processing_unit#62 | backs of globally synchronous CPUs. For example, a clock signal is subject to the delays of any other electrical signal. Higher clock rates in increasingly complex CPUs make it more difficult to keep the clock signal in phase (synchronized) throughout the entire unit. This has led many modern CPUs to require multiple i... |
https://en.wikipedia.org/wiki/Central_processing_unit#63 | her major issue, as clock rates increase dramatically, is the amount of heat that is dissipated by the CPU. The constantly changing clock causes many components to switch regardless of whether they are being used at that time. In general, a component that is switching uses more energy than an element in a static state.... |
https://en.wikipedia.org/wiki/Central_processing_unit#64 | PU cooling solutions.
One method of dealing with the switching of unneeded components is called clock gating, which involves turning off the clock signal to unneeded components (effectively disabling them). However, this is often regarded as difficult to implement and therefore does not see common usage outside of very... |
https://en.wikipedia.org/wiki/Central_processing_unit#65 | 360; this reduces the power requirements of the Xbox 360.[73]
Clockless CPUs
[edit]Another method of addressing some of the problems with a global clock signal is the removal of the clock signal altogether. While removing the global clock signal makes the design process considerably more complex in many ways, asynchron... |
https://en.wikipedia.org/wiki/Central_processing_unit#66 | us designs. While somewhat uncommon, entire asynchronous CPUs have been built without using a global clock signal. Two notable examples of this are the ARM compliant AMULET and the MIPS R3000 compatible MiniMIPS.[74]
Rather than totally removing the clock signal, some CPU designs allow certain portions of the device to... |
https://en.wikipedia.org/wiki/Central_processing_unit#67 | e gains. While it is not altogether clear whether totally asynchronous designs can perform at a comparable or better level than their synchronous counterparts, it is evident that they do at least excel in simpler math operations. This, combined with their excellent power consumption and heat dissipation properties, mak... |
https://en.wikipedia.org/wiki/Central_processing_unit#68 | ging module which regulates on-demand voltage supply to the CPU circuitry allowing it to keep balance between performance and power consumption.
Integer range
[edit]Every CPU represents numerical values in a specific way. For example, some early digital computers represented numbers as familiar decimal (base 10) numera... |
https://en.wikipedia.org/wiki/Central_processing_unit#69 | e 3). Nearly all modern CPUs represent numbers in binary form, with each digit being represented by some two-valued physical quantity such as a "high" or "low" voltage.[g]
Related to numeric representation is the size and precision of integer numbers that a CPU can represent. In the case of a binary CPU, this is measur... |
https://en.wikipedia.org/wiki/Central_processing_unit#70 | only called word size, bit width, data path width, integer precision, or integer size. A CPU's integer size determines the range of integer values on which it can directly operate.[h] For example, an 8-bit CPU can directly manipulate integers represented by eight bits, which have a range of 256 (28) discrete integer va... |
https://en.wikipedia.org/wiki/Central_processing_unit#71 | presenting a specific memory location). For example, if a binary CPU uses 32 bits to represent a memory address then it can directly address 232 memory locations. To circumvent this limitation and for various other reasons, some CPUs use mechanisms (such as memory management or bank switching) that allow additional mem... |
https://en.wikipedia.org/wiki/Central_processing_unit#72 | ume more power (and therefore generate more heat). As a result, smaller 4- or 8-bit microcontrollers are commonly used in modern applications even though CPUs with much larger word sizes (such as 16, 32, 64, even 128-bit) are available. When higher performance is required, however, the benefits of a larger word size (l... |
https://en.wikipedia.org/wiki/Central_processing_unit#73 | e to reduce size and cost. For example, even though the IBM System/360 instruction set architecture was a 32-bit instruction set, the System/360 Model 30 and Model 40 had 8-bit data paths in the arithmetic logical unit, so that a 32-bit add required four cycles, one for each 8 bits of the operands, and, even though the... |
https://en.wikipedia.org/wiki/Central_processing_unit#74 | n the arithmetic logical unit, so that a 32-bit add required two cycles.
To gain some of the advantages afforded by both lower and higher bit lengths, many instruction sets have different bit widths for integer and floating-point data, allowing CPUs implementing that instruction set to have different bit widths for dif... |
https://en.wikipedia.org/wiki/Central_processing_unit#75 | -point values to facilitate greater accuracy and range in floating-point numbers.[37] The System/360 Model 65 had an 8-bit adder for decimal and fixed-point binary arithmetic and a 60-bit adder for floating-point arithmetic.[76] Many later CPU designs use similar mixed bit width, especially when the processor is meant ... |
https://en.wikipedia.org/wiki/Central_processing_unit#76 | cription of the basic operation of a CPU offered in the previous section describes the simplest form that a CPU can take. This type of CPU, usually referred to as subscalar, operates on and executes one instruction on one or two pieces of data at a time, that is less than one instruction per clock cycle (IPC < 1).
This... |
https://en.wikipedia.org/wiki/Central_processing_unit#77 | U must wait for that instruction to complete before proceeding to the next instruction. As a result, the subscalar CPU gets "hung up" on instructions which take more than one clock cycle to complete execution. Even adding a second execution unit (see below) does not improve performance much; rather than one pathway bei... |
https://en.wikipedia.org/wiki/Central_processing_unit#78 | on resources can operate on only one instruction at a time, can only possibly reach scalar performance (one instruction per clock cycle, IPC = 1). However, the performance is nearly always subscalar (less than one instruction per clock cycle, IPC < 1).
Attempts to achieve scalar and better performance have resulted in ... |
https://en.wikipedia.org/wiki/Central_processing_unit#79 | n CPUs, two terms are generally used to classify these design techniques:
- instruction-level parallelism (ILP), which seeks to increase the rate at which instructions are executed within a CPU (that is, to increase the use of on-die execution resources);
- task-level parallelism (TLP), which purposes to increase the n... |
https://en.wikipedia.org/wiki/Central_processing_unit#80 | mplemented, as well as the relative effectiveness they afford in increasing the CPU's performance for an application.[i]
Instruction-level parallelism
[edit]One of the simplest methods for increased parallelism is to begin the first steps of instruction fetching and decoding before the prior instruction finishes execut... |
https://en.wikipedia.org/wiki/Central_processing_unit#81 | multiple instruction to be executed at a time by breaking the execution pathway into discrete stages. This separation can be compared to an assembly line, in which an instruction is made more complete at each stage until it exits the execution pipeline and is retired.
Pipelining does, however, introduce the possibility... |
https://en.wikipedia.org/wiki/Central_processing_unit#82 | ta dependency conflict. Therefore, pipelined processors must check for these sorts of conditions and delay a portion of the pipeline if necessary. A pipelined processor can become very nearly scalar, inhibited only by pipeline stalls (an instruction spending more than one clock cycle in a stage).
Improvements in instru... |
https://en.wikipedia.org/wiki/Central_processing_unit#83 | ng instruction pipeline and multiple identical execution units, such as load–store units, arithmetic–logic units, floating-point units and address generation units.[77] In a superscalar pipeline, instructions are read and passed to a dispatcher, which decides whether or not the instructions can be executed in parallel ... |
https://en.wikipedia.org/wiki/Central_processing_unit#84 | of instructions that a superscalar CPU will complete in a cycle is dependent on the number of instructions it is able to dispatch simultaneously to execution units.
Most of the difficulty in the design of a superscalar CPU architecture lies in creating an effective dispatcher. The dispatcher needs to be able to quickly... |
https://en.wikipedia.org/wiki/Central_processing_unit#85 | units busy as possible. This requires that the instruction pipeline is filled as often as possible and requires significant amounts of CPU cache. It also makes hazard-avoiding techniques like branch prediction, speculative execution, register renaming, out-of-order execution and transactional memory crucial to maintain... |
https://en.wikipedia.org/wiki/Central_processing_unit#86 | inimize the number of times that the entire pipeline must wait until a conditional instruction is completed. Speculative execution often provides modest performance increases by executing portions of code that may not be needed after a conditional operation completes. Out-of-order execution somewhat rearranges the orde... |
https://en.wikipedia.org/wiki/Central_processing_unit#87 | e data stream, a case when a lot of data from the same type has to be processed, modern processors can disable parts of the pipeline so that when a single instruction is executed many times, the CPU skips the fetch and decode phases and thus greatly increases performance on certain occasions, especially in highly monot... |
https://en.wikipedia.org/wiki/Central_processing_unit#88 | at is not suffers a performance penalty due to scheduling stalls. The Intel P5 Pentium had two superscalar ALUs which could accept one instruction per clock cycle each, but its FPU could not. Thus the P5 was integer superscalar but not floating point superscalar. Intel's successor to the P5 architecture, P6, added supe... |
https://en.wikipedia.org/wiki/Central_processing_unit#89 | execute instructions at rates surpassing one instruction per clock cycle. Most modern CPU designs are at least somewhat superscalar, and nearly all general purpose CPUs designed in the last decade are superscalar. In later years some of the emphasis in designing high-ILP computers has been moved out of the CPU's hardwa... |
https://en.wikipedia.org/wiki/Central_processing_unit#90 | auses some ILP to become implied directly by the software, reducing the CPU's work in boosting ILP and thereby reducing design complexity.
Task-level parallelism
[edit]Another strategy of achieving performance is to execute multiple threads or processes in parallel. This area of research is known as parallel computing.... |
https://en.wikipedia.org/wiki/Central_processing_unit#91 | sed for this purpose is multiprocessing (MP).[80] The initial type of this technology is known as symmetric multiprocessing (SMP), where a small number of CPUs share a coherent view of their memory system. In this scheme, each CPU has additional hardware to maintain a constantly up-to-date view of memory. By avoiding s... |
https://en.wikipedia.org/wiki/Central_processing_unit#92 | number of cooperating CPUs beyond a handful, schemes such as non-uniform memory access (NUMA) and directory-based coherence protocols were introduced in the 1990s. SMP systems are limited to a small number of CPUs while NUMA systems have been built with thousands of processors. Initially, multiprocessing was built usin... |
https://en.wikipedia.org/wiki/Central_processing_unit#93 | ect are all implemented on a single chip, the technology is known as chip-level multiprocessing (CMP) and the single chip as a multi-core processor.
It was later recognized that finer-grain parallelism existed with a single program. A single program might have several threads (or functions) that could be executed separ... |
https://en.wikipedia.org/wiki/Central_processing_unit#94 | ccess as a separate thread from the computation thread. A more general approach to this technology was introduced in the 1970s when systems were designed to run multiple computation threads in parallel. This technology is known as multi-threading (MT). The approach is considered more cost-effective than multiprocessing... |
https://en.wikipedia.org/wiki/Central_processing_unit#95 | n MT, the execution units and the memory system including the caches are shared among multiple threads. The downside of MT is that the hardware support for multithreading is more visible to software than that of MP and thus supervisor software like operating systems have to undergo larger changes to support MT. One typ... |
https://en.wikipedia.org/wiki/Central_processing_unit#96 | a to return from external memory. In this scheme, the CPU would then quickly context switch to another thread which is ready to run, the switch often done in one CPU clock cycle, such as the UltraSPARC T1. Another type of MT is simultaneous multithreading, where instructions from multiple threads are executed in parall... |
https://en.wikipedia.org/wiki/Central_processing_unit#97 | purpose CPUs was largely on achieving high ILP through technologies such as pipelining, caches, superscalar execution, out-of-order execution, etc. This trend culminated in large, power-hungry CPUs such as the Intel Pentium 4. By the early 2000s, CPU designers were thwarted from achieving higher performance from ILP te... |
https://en.wikipedia.org/wiki/Central_processing_unit#98 | g CPU power dissipation owing to more esoteric ILP techniques.
CPU designers then borrowed ideas from commercial computing markets such as transaction processing, where the aggregate performance of multiple programs, also known as throughput computing, was more important than the performance of a single thread or proce... |
https://en.wikipedia.org/wiki/Central_processing_unit#99 | designs resembling its less superscalar P6 architecture. Late designs in several processor families feature chip-level multiprocessing, including the x86-64 Opteron and Athlon 64 X2, the SPARC UltraSPARC T1, IBM POWER4 and POWER5, as well as several video game console CPUs like the Xbox 360's triple-core PowerPC design... |
https://en.wikipedia.org/wiki/Central_processing_unit#100 | processors (and indeed, computing in general) deals with data parallelism. The processors discussed earlier are all referred to as some type of scalar device.[j] As the name implies, vector processors deal with multiple pieces of data in the context of one instruction. This contrasts with scalar processors, which deal ... |
https://en.wikipedia.org/wiki/Central_processing_unit#101 | ed to as single instruction stream, multiple data stream (SIMD) and single instruction stream, single data stream (SISD), respectively. The great utility in creating processors that deal with vectors of data lies in optimizing tasks that tend to require the same operation (for example, a sum or a dot product) to be per... |
https://en.wikipedia.org/wiki/Central_processing_unit#102 | und), as well as many types of scientific and engineering tasks. Whereas a scalar processor must complete the entire process of fetching, decoding and executing each instruction and value in a set of data, a vector processor can perform a single operation on a comparatively large set of data with one instruction. This ... |
https://en.wikipedia.org/wiki/Central_processing_unit#103 | tor processors, such as the Cray-1, were associated almost exclusively with scientific research and cryptography applications. However, as multimedia has largely shifted to digital media, the need for some form of SIMD in general-purpose processors has become significant. Shortly after inclusion of floating-point units... |
https://en.wikipedia.org/wiki/Central_processing_unit#104 | began to appear for general-purpose processors in the mid-1990s. Some of these early SIMD specifications – like HP's Multimedia Acceleration eXtensions (MAX) and Intel's MMX – were integer-only. This proved to be a significant impediment for some software developers, since many of the applications that benefit from SIM... |
https://en.wikipedia.org/wiki/Central_processing_unit#105 | mmon modern SIMD specifications, which are usually associated with one instruction set architecture (ISA). Some notable modern examples include Intel's Streaming SIMD Extensions (SSE) and the PowerPC-related AltiVec (also known as VMX).[k]
Hardware performance counter
[edit]Many modern architectures (including embedded... |
https://en.wikipedia.org/wiki/Central_processing_unit#106 | bugging or analysis of running software metrics.[81][82] HPC may also be used to discover and analyze unusual or suspicious activity of the software, such as return-oriented programming (ROP) or sigreturn-oriented programming (SROP) exploits etc.[83] This is usually done by software-security teams to assess and find ma... |
https://en.wikipedia.org/wiki/Central_processing_unit#107 | C/C++) that can be used to collect data from the CPU's registers in order to get metrics.[85] Operating system vendors also provide software like perf
(Linux) to record, benchmark, or trace CPU events running kernels and applications.
Hardware counters provide a low-overhead method for collecting comprehensive performa... |
https://en.wikipedia.org/wiki/Central_processing_unit#108 | e profilers.[86] Additionally, they generally eliminate the need to modify the underlying source code of a program.[87] Because hardware designs differ between architectures, the specific types and interpretations of hardware counters will also change.
Privileged modes
[edit]Most modern CPUs have privileged modes to su... |
https://en.wikipedia.org/wiki/Central_processing_unit#109 | (vCPUs) for separate users.[89]
A host is the virtual equivalent of a physical machine, on which a virtual system is operating.[90] When there are several physical machines operating in tandem and managed as a whole, the grouped computing and memory resources form a cluster. In some systems, it is possible to dynamical... |
https://en.wikipedia.org/wiki/Central_processing_unit#110 | ne granularity.
Performance
[edit]The performance or speed of a processor depends on, among many other factors, the clock rate (generally given in multiples of hertz) and the instructions per clock (IPC), which together are the factors for the instructions per second (IPS) that the CPU can perform.[91] Many reported IP... |
https://en.wikipedia.org/wiki/Central_processing_unit#111 | s consist of a mix of instructions and applications, some of which take longer to execute than others. The performance of the memory hierarchy also greatly affects processor performance, an issue barely considered in IPS calculations. Because of these problems, various standardized tests, often called "benchmarks" for ... |
https://en.wikipedia.org/wiki/Central_processing_unit#112 | tions.
Processing performance of computers is increased by using multi-core processors, which essentially is plugging two or more individual processors (called cores in this sense) into one integrated circuit.[92] Ideally, a dual core processor would be nearly twice as powerful as a single core processor. In practice, ... |
https://en.wikipedia.org/wiki/Central_processing_unit#113 | umber of cores in a processor (i.e. dual-core, quad-core, etc.) increases the workload that can be handled. This means that the processor can now handle numerous asynchronous events, interrupts, etc. which can take a toll on the CPU when overwhelmed. These cores can be thought of as different floors in a processing pla... |
https://en.wikipedia.org/wiki/Central_processing_unit#114 | ngle core is not enough to handle the information. Multi-core CPUs enhance a computer's ability to run several tasks simultaneously by providing additional processing power. However, the increase in speed is not directly proportional to the number of cores added. This is because the cores need to interact through speci... |
https://en.wikipedia.org/wiki/Central_processing_unit#115 | ties of modern CPUs, such as simultaneous multithreading and uncore, which involve sharing of actual CPU resources while aiming at increased utilization, monitoring performance levels and hardware use gradually became a more complex task.[95] As a response, some CPUs implement additional hardware logic that monitors ac... |
https://en.wikipedia.org/wiki/Central_processing_unit#116 | Monitor technology.[9]
Overclocking
[edit]Overclocking is a process of increasing the clock speed of a CPU (and other components) to increase the performance of the CPU. Overclocking might increase CPU temperature and cause it to overheat, so most users do not overclock and leave the clock speed unchanged. Some version... |
https://en.wikipedia.org/wiki/Central_processing_unit#117 | g mode
- AMD Accelerated Processing Unit
- Complex instruction set computer
- Computer bus
- Computer engineering
- CPU core voltage
- CPU socket
- Data processing unit
- Digital signal processor
- Graphics processing unit
- Comparison of instruction set architectures
- Protection ring
- Reduced instruction set compute... |
https://en.wikipedia.org/wiki/Central_processing_unit#118 | sed to implement all CPUs, except for a few machines designed to withstand large electromagnetic pulses, say from a nuclear weapon.
- ^ The so-called "von Neumann" memo expounded the idea of stored programs,[65] which for example may be stored on punched cards, paper tape, or magnetic tape.
- ^ Some early computers, li... |
https://en.wikipedia.org/wiki/Central_processing_unit#119 | uld run. It is largely for this reason that these computers are often not considered to contain a proper CPU, despite their close similarity to stored-program computers.
- ^ Since the program counter counts memory addresses and not instructions, it is incremented by the number of memory units that the instruction word ... |
https://en.wikipedia.org/wiki/Central_processing_unit#120 | -bit instruction word ISA that uses 8-bit memory words would always increment the PC by four (except in the case of jumps). ISAs that use variable-length instruction words increment the PC by the number of memory words corresponding to the last instruction's length.
- ^ Because the instruction set architecture of a CPU... |
https://en.wikipedia.org/wiki/Central_processing_unit#121 | " uses some variant of the PowerPC ISA. A CPU of a certain ISA can execute a different ISA by running an emulator.
- ^ A few specialized CPUs, accelerators or microcontrollers do not have a cache. To be fast, if needed/wanted, they still have an on-chip scratchpad memory that has a similar function, while software mana... |
https://en.wikipedia.org/wiki/Central_processing_unit#122 | ory latencies of loads are predictable.
- ^ The physical concept of voltage is an analog one by nature, practically having an infinite range of possible values. For the purpose of physical representation of binary numbers, two specific ranges of voltages are defined, one for logic '0' and another for logic '1'. These r... |
https://en.wikipedia.org/wiki/Central_processing_unit#123 | hile a CPU's integer size sets a limit on integer ranges, this can (and often is) overcome using a combination of software and hardware techniques. By using additional memory, software can represent integers many magnitudes larger than the CPU can. Sometimes the CPU's instruction set will even facilitate operations on ... |
https://en.wikipedia.org/wiki/Central_processing_unit#124 | ethod of dealing with large integers is slower than utilizing a CPU with higher integer size, but is a reasonable trade-off in cases where natively supporting the full integer range needed would be cost-prohibitive. See Arbitrary-precision arithmetic for more details on purely software-supported arbitrary-sized integer... |
https://en.wikipedia.org/wiki/Central_processing_unit#125 | lism. As such, they both have advantages and disadvantages, which are often determined by the type of software that the processor is intended to run. High-TLP CPUs are often used in applications that lend themselves well to being split up into numerous smaller applications, so-called "embarrassingly parallel problems".... |
https://en.wikipedia.org/wiki/Central_processing_unit#126 | es significantly more time on high ILP devices like superscalar CPUs, and vice versa.
- ^ Earlier the term scalar was used to compare the IPC count afforded by various ILP methods. Here the term is used in the strictly mathematical sense to contrast with vectors. See scalar (mathematics) and vector (geometric).
- ^ Alt... |
https://en.wikipedia.org/wiki/Central_processing_unit#127 | lly done by providing most of the MMX functionality with the same hardware that supports the much more expansive SSE instruction sets.
References
[edit]- ^ Team, YCT Expert. Engineering Drawing & Basic Science. Youth Competition Times. p. 425.
- ^ Nagpal, D. P. (2008). Computer Fundamentals. S. Chand Publishing. p. 33.... |
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