| # 32-bit-RISC-processor-using-HDL-Verilog | |
| The proposed processor is designed using HDL Verilog having separate instruction and data memory. The salient feature of proposed processor is pipelining, used for improving performance, such that on every clock cycle one instruction will be executed. Another important feature is that instruction set contains 14 instructions, which is very simple, easy to learn and compact. The proposed processor has 32-bit ALU, Thirty two 32-bit general-purpose registers, no flag register and memory word size of 32 bits. Another advantage of the proposed processor is that it can execute programs with as many instructions with very few addressing modes like register, immediate, register indexed etc. such that any practical programs can be fitted into it. The proposed processor is physically verified on Xilinx Spartan 6 FPGA board having chipset XC6SLX9 with 50MHz clock cycle. HDL Verilog is quite different from Implementation in sequential languages mainly because of the parallel nature of the HDLs, where sequential language code is executed by a digital core step by step, HDL code describes the functioning of a digital hardware, it is taken by synthesis tools that try to find a digital hardware implementation of the description, thus there is no step by step execution of the statement of HDL, and each statement is a smaller circuit in itself. | |