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Incomputer science, an algorithm formatching wildcards(also known asglobbing) is useful in comparing text strings that may containwildcard syntax.[1]Common uses of these algorithms includecommand-line interfaces, e.g. theBourne shell[2]orMicrosoft Windowscommand-line[3]or text editor or file manager, as well as the interfaces for some search engines[4]and databases.[5]Wildcard matching is a subset of the problem of matchingregular expressionsandstring matchingin general.[6] A wildcard matcher tests a wildcard patternpagainst an input strings. It performs ananchoredmatch, returns true only whenpmatches the entirety ofs. The pattern can be based on any common syntax (seeglobbing), but on Windows programmers tend to only discuss a simplified syntax supported by the native C runtime:[7][8] This article mainly discusses the Windows formulation of the problem, unless otherwise stated. Stated in zero-based indices, the wildcard-matching problem can be defined recursively as: wheremijis the result of matching the patternpagainst the textttruncated atiandjcharacters respectively. This is the formulation used by Richter's algorithm and theSnippetsalgorithm found in Cantatore's collection.[9][10]This description is similar to theLevenshtein distance. Directly related problems in computer science include: Early algorithms for matching wildcards often relied onrecursion, but the technique was criticized on grounds of performance[10]and reliability[8]considerations. Non-recursive algorithms for matching wildcards have gained favor in light of these considerations. Among both recursive and non-recursive algorithms, strategies for performing the pattern matching operation vary widely, as evidenced among the variety of example algorithms referenced below.Test casedevelopment and performance optimization techniques have been demonstrably brought to bear on certain algorithms, particularly those developed by critics of the recursive algorithms. The recursion generally happens on matchingwhen there is more suffix to match against. This is a form ofbacktracking, also done by some regular expression matchers. The general form of these algorithms are the same. On recursion the algorithm slices the input into substrings, and considers a match to have happened when ONE of the substrings return a positive match. Fordowild("X", "abcX"), it would greedily calldowild("X", "abcX"),dowild("X", "bcX"),dowild("X", "cX")anddowild("X", "X"). They usually differ by less-important things like support for features and by more important factors such as minor but highly effective optimizations. Some of them include: Martin Richter's algorithm is an exception to this pattern, although the overall operation is equivalent. On * it recurses into increasingeitherof the indexes, following the dynamic programming formulation of the problem. The "ABORT" technique is applicable to it as well.[9]On typical patterns (as tested by Cantatore) it is slower than the greedy-call implementations.[10] The recursive algorithms are in general easier to reason about, and with the ABORT modification they perform acceptably in terms of worst-case complexity. On strings without * they take linear-to-string-size time to match since there is a fixed one-to-one relation. The following are developed by critics of the recursive algorithms: The following is not: The iterative functions above implement backtracking by saving an old set of pattern/text pointers, and reverting to it should a match fails. According to Kurt, since only one successful match is required, only one such set needs to be saved.[17] In addition, the problem of wildcard matching can be converted intoregular expressionmatching using a naivetext-replacement approach. Although non-recursive regular expression matchers such asThompson's constructionare less used in practice due to lack of backreference support, wildcard matching in general does not come with a similarly rich set of features. (In fact, many of the algorithms above only has support for?and*.) The Russ Cox implementation of Thompson NFA can be trivially modified for such.[26]Gustavo Navarro'sBDM-based nrgrep algorithm provides a more streamlined implementation with emphasis on efficient suffixes.[27]See alsoregular expression § Implementations.	https://en.wikipedia.org/wiki/Matching_wildcards
Intheoretical computer scienceandformal language theory, aregular tree grammaris aformal grammarthat describes a set ofdirected trees, orterms.[1]Aregular word grammarcan be seen as a special kind of regular tree grammar, describing a set of single-pathtrees. A regular tree grammarGis defined by the tuple G= (N, Σ,Z,P), where The grammarGimplicitly defines a set of trees: any tree that can be derived fromZusing the rule setPis said to bedescribedbyG. This set of trees is known as thelanguageofG. More formally, the relation ⇒Gon the setTΣ(N) is defined as follows: A treet1∈TΣ(N)can bederived in a single stepinto a treet2∈TΣ(N)(in short:t1⇒Gt2), if there is a contextSand a production(A→t) ∈Psuch that: Here, acontextmeans a tree with exactly one hole in it; ifSis such a context,S[t] denotes the result of filling the treetinto the hole ofS. The tree language generated byGis the languageL(G) = {t∈TΣ\|Z⇒Gt}. Here,TΣdenotes the set of all trees composed from symbols of Σ, while ⇒Gdenotes successive applications of ⇒G. A language generated by some regular tree grammar is called aregulartree language. LetG1= (N1,Σ1,Z1,P1), where An example derivation from the grammarG1is BList⇒cons(Bool,BList) ⇒cons(false,cons(Bool,BList)) ⇒cons(false,cons(true,nil)). The image shows the correspondingderivation tree; it is a tree of trees (main picture), whereas a derivation tree inword grammarsis a tree of strings (upper left table). The tree language generated byG1is the set of all finite lists of boolean values, that is,L(G1) happens to equalTΣ1. The grammarG1corresponds to the algebraic data type declarations (in theStandard MLprogramming language): Every member ofL(G1) corresponds to a Standard-ML value of type BList. For another example, letG2= (N1, Σ1,BList1,P1∪P2), using the nonterminal set and the alphabet from above, but extending the production set byP2, consisting of the following productions: The languageL(G2) is the set of all finite lists of boolean values that containtrueat least once. The setL(G2) has nodatatypecounterpart in Standard ML, nor in any other functional language. It is a proper subset ofL(G1). The above example term happens to be inL(G2), too, as the following derivation shows: BList1⇒cons(false,BList1) ⇒cons(false,cons(true,BList)) ⇒cons(false,cons(true,nil)). IfL1,L2both are regular tree languages, then the tree setsL1∩L2,L1∪L2, andL1\L2are also regular tree languages, and it is decidable whetherL1⊆L2, and whetherL1=L2. Applications of regular tree grammars include:	https://en.wikipedia.org/wiki/Regular_tree_grammar
Incomputer science,Thompson's constructionalgorithm, also called theMcNaughton–Yamada–Thompson algorithm,[1]is a method of transforming aregular expressioninto an equivalentnondeterministic finite automaton(NFA).[2]This NFA can be used tomatch stringsagainst the regular expression. This algorithm is credited toKen Thompson. Regular expressions and nondeterministic finite automata are two representations offormal languages. For instance,text processingutilities use regular expressions to describe advanced search patterns, but NFAs are better suited for execution on a computer. Hence, this algorithm is of practical interest, since it cancompileregular expressions into NFAs. From a theoretical point of view, this algorithm is a part of the proof that they both accept exactly the same languages, that is, theregular languages. An NFA can be made deterministic by thepowerset constructionand then beminimizedto get an optimal automaton corresponding to the given regular expression. However, an NFA may also beinterpreted directly. To decide whether two given regular expressions describe the same language, each can be converted into an equivalent minimaldeterministic finite automatonvia Thompson's construction,powerset construction, andDFA minimization. If, and only if, the resulting automata agreeup torenaming of states, the regular expressions' languages agree. The algorithm worksrecursivelyby splitting an expression into its constituent subexpressions, from which the NFA will be constructed using a set of rules.[3]More precisely, from a regular expressionE, the obtained automatonAwith the transition functionΔ[clarification needed]respects the following properties: The following rules are depicted according to Aho et al. (2007),[1]p. 122. In what follows,N(s) andN(t) are the NFA of the subexpressionssandt, respectively. Theempty-expressionε is converted to Asymbolaof the input alphabet is converted to Theunion expressions\|tis converted to Stateqgoes via ε either to the initial state ofN(s) orN(t). Their final states become intermediate states of the whole NFA and merge via two ε-transitions into the final state of the NFA. Theconcatenation expressionstis converted to The initial state ofN(s) is the initial state of the whole NFA. The final state ofN(s) becomes the initial state ofN(t). The final state ofN(t) is the final state of the whole NFA. TheKleene starexpressionsis converted to An ε-transition connects initial and final state of the NFA with the sub-NFAN(s) in between. Another ε-transition from the inner final to the inner initial state ofN(s) allows for repetition of expressionsaccording to the star operator. With these rules, using theempty expressionandsymbolrules as base cases, it is possible to prove withstructural inductionthat any regular expression may be converted into an equivalent NFA.[1] Two examples are now given, a small informal one with the result, and a bigger with a step by step application of the algorithm. The picture below shows the result of Thompson's construction on(ε\|ab). The purple oval corresponds toa, the teal oval corresponds toa, the green oval corresponds tob, the orange oval corresponds toab, and the blue oval corresponds toε. As an example, the picture shows the result of Thompson's construction algorithm on the regular expression(0\|(1(01(00)0)1))*that denotes the set of binary numbers that are multiples of 3: The upper right part shows the logical structure (syntax tree) of the expression, with "." denoting concatenation (assumed to have variable arity); subexpressions are nameda-qfor reference purposes. The left part shows the nondeterministic finite automaton resulting from Thompson's algorithm, with theentryandexitstate of each subexpression colored inmagentaandcyan, respectively. An ε as transition label is omitted for clarity — unlabelled transitions are in fact ε transitions. The entry and exit state corresponding to the root expressionqis the start and accept state of the automaton, respectively. The algorithm's steps are as follows: An equivalent minimal deterministic automaton is shown below. Thompson's is one of several algorithms for constructing NFAs from regular expressions;[5]an earlier algorithm was given by McNaughton and Yamada.[6]Converse to Thompson's construction,Kleene's algorithmtransforms a finite automaton into a regular expression. Glushkov's construction algorithmis similar to Thompson's construction, once the ε-transitions are removed. Regular expressions are often used to specify patterns that software is then asked to match. Generating an NFA by Thompson's construction, and using an appropriate algorithm to simulate it, it is possible to create pattern-matching software with performance that is⁠O(mn){\displaystyle O(mn)}⁠, wheremis the length of the regular expression andnis the length of the string being matched. This is much better than is achieved by many popular programming-language implementations;[7]however, it is restricted to purely regular expressions and does not supportpatterns for non-regular languageslike backreferences.	https://en.wikipedia.org/wiki/Thompson%27s_construction
Inautomata theory, afinite-state machineis called adeterministic finite automaton(DFA), if Anondeterministic finite automaton(NFA), ornondeterministic finite-state machine, does not need to obey these restrictions. In particular, every DFA is also an NFA. Sometimes the termNFAis used in a narrower sense, referring to an NFA that isnota DFA, but not in this article. Using thesubset construction algorithm, each NFA can be translated to an equivalent DFA; i.e., a DFA recognizing the sameformal language.[1]Like DFAs, NFAs only recognizeregular languages. NFAs were introduced in 1959 byMichael O. RabinandDana Scott,[2]who also showed their equivalence to DFAs. NFAs are used in the implementation ofregular expressions:Thompson's constructionis an algorithm for compiling a regular expression to an NFA that can efficiently perform pattern matching on strings. Conversely,Kleene's algorithmcan be used to convert an NFA into a regular expression (whose size is generally exponential in the input automaton). NFAs have been generalized in multiple ways, e.g.,nondeterministic finite automata with ε-moves,finite-state transducers,pushdown automata,alternating automata,ω-automata, andprobabilistic automata. Besides the DFAs, other known special cases of NFAs areunambiguous finite automata(UFA) andself-verifying finite automata(SVFA). There are at least two equivalent ways to describe the behavior of an NFA. The first way makes use of thenondeterminismin the name of an NFA. For each input symbol, the NFA transitions to a new state until all input symbols have been consumed. In each step, the automaton nondeterministically "chooses" one of the applicable transitions. If there exists at least one "lucky run", i.e. some sequence of choices leading to an accepting state after completely consuming the input, it is accepted. Otherwise, i.e. if no choice sequence at all can consume all the input[3]and lead to an accepting state, the input is rejected.[4][5]: 319[6] In the second way, the NFA consumes a string of input symbols, one by one. In each step, whenever two or more transitions are applicable, it "clones" itself into appropriately many copies, each one following a different transition. If no transition is applicable, the current copy is in a dead end, and it "dies". If, after consuming the complete input, any of the copies is in an accept state, the input is accepted, else, it is rejected.[4][7][6] For a more elementary introduction of the formal definition, seeautomata theory. AnNFAis represented formally by a 5-tuple,(Q,Σ,δ,q0,F){\displaystyle (Q,\Sigma ,\delta ,q_{0},F)}, consisting of Here,P(Q){\displaystyle {\mathcal {P}}(Q)}denotes thepower setofQ{\displaystyle Q}. Given an NFAM=(Q,Σ,δ,q0,F){\displaystyle M=(Q,\Sigma ,\delta ,q_{0},F)}, its recognized language is denoted byL(M){\displaystyle L(M)}, and is defined as the set of all strings over the alphabetΣ{\displaystyle \Sigma }that are accepted byM{\displaystyle M}. Loosely corresponding to theaboveinformal explanations, there are several equivalent formal definitions of a stringw=a1a2...an{\displaystyle w=a_{1}a_{2}...a_{n}}being accepted byM{\displaystyle M}: The above automaton definition uses asingle initial state, which is not necessary. Sometimes, NFAs are defined with a set of initial states. There is an easy construction that translates an NFA with multiple initial states to an NFA with a single initial state, which provides a convenient notation. The following automatonM, with a binary alphabet, determines if the input ends with a 1. LetM=({p,q},{0,1},δ,p,{q}){\displaystyle M=(\{p,q\},\{0,1\},\delta ,p,\{q\})}where the transition functionδ{\displaystyle \delta }can be defined by thisstate transition table(cf. upper left picture): Since the setδ(p,1){\displaystyle \delta (p,1)}contains more than one state,Mis nondeterministic. The language ofMcan be described by theregular languagegiven by theregular expression(0\|1)1. All possible state sequences for the input string "1011" are shown in the lower picture. The string is accepted byMsince one state sequence satisfies the above definition; it does not matter that other sequences fail to do so. The picture can be interpreted in a couple of ways: The feasibility to read the same picture in two ways also indicates the equivalence of both above explanations. In contrast, the string "10" is rejected byM(all possible state sequences for that input are shown in the upper right picture), since there is no way to reach the only accepting state,q, by reading the final 0 symbol. Whileqcan be reached after consuming the initial "1", this does not mean that the input "10" is accepted; rather, it means that an input string "1" would be accepted. Adeterministic finite automaton(DFA) can be seen as a special kind of NFA, in which for each state and symbol, the transition function has exactly one state. Thus, it is clear that everyformal languagethat can be recognized by a DFA can be recognized by an NFA. Conversely, for each NFA, there is a DFA such that it recognizes the same formal language. The DFA can be constructed using thepowerset construction. This result shows that NFAs, despite their additional flexibility, are unable to recognize languages that cannot be recognized by some DFA. It is also important in practice for converting easier-to-construct NFAs into more efficiently executable DFAs. However, if the NFA hasnstates, the resulting DFA may have up to 2nstates, which sometimes makes the construction impractical for large NFAs. Nondeterministic finite automaton with ε-moves (NFA-ε) is a further generalization to NFA. In this kind of automaton, the transition function is additionally defined on theempty stringε. A transition without consuming an input symbol is called an ε-transition and is represented in state diagrams by an arrow labeled "ε". ε-transitions provide a convenient way of modeling systems whose current states are not precisely known: i.e., if we are modeling a system and it is not clear whether the current state (after processing some input string) should be q or q', then we can add an ε-transition between these two states, thus putting the automaton in both states simultaneously. AnNFA-εis represented formally by a 5-tuple,(Q,Σ,δ,q0,F){\displaystyle (Q,\Sigma ,\delta ,q_{0},F)}, consisting of Here,P(Q){\displaystyle {\mathcal {P}}(Q)}denotes thepower setofQ{\displaystyle Q}andϵ{\displaystyle \epsilon }denotes empty string. For a stateq∈Q{\displaystyle q\in Q}, letE(q){\displaystyle E(q)}denote the set of states that are reachable fromq{\displaystyle q}by following ε-transitions in the transition functionδ{\displaystyle \delta }, i.e.,p∈E(q){\displaystyle p\in E(q)}if there is a sequence of statesq1,...,qk{\displaystyle q_{1},...,q_{k}}such that E(q){\displaystyle E(q)}is known as theepsilon closure, (alsoε-closure) ofq{\displaystyle q}. The ε-closure of a setP{\displaystyle P}of states of an NFA is defined as the set of states reachable from any state inP{\displaystyle P}following ε-transitions. Formally, forP⊆Q{\displaystyle P\subseteq Q}, defineE(P)=⋃q∈PE(q){\displaystyle E(P)=\bigcup \limits _{q\in P}E(q)}. Similar to NFA without ε-moves, the transition functionδ{\displaystyle \delta }of an NFA-ε can be extended to strings. Informally,δ∗(q,w){\displaystyle \delta ^{}(q,w)}denotes the set of all states the automaton may have reached when starting in stateq∈Q{\displaystyle q\in Q}and reading the stringw∈Σ∗.{\displaystyle w\in \Sigma ^{}.}The functionδ∗:Q×Σ∗→P(Q){\displaystyle \delta ^{}:Q\times \Sigma ^{}\rightarrow {\mathcal {P}}(Q)}can be defined recursively as follows. The automaton is said to accept a stringw{\displaystyle w}if that is, if readingw{\displaystyle w}may drive the automaton from its start stateq0{\displaystyle q_{0}}to some accepting state inF.{\displaystyle F.}[11] LetM{\displaystyle M}be a NFA-ε, with a binary alphabet, that determines if the input contains an even number of 0s or an even number of 1s. Note that 0 occurrences is an even number of occurrences as well. In formal notation, letM=({S0,S1,S2,S3,S4},{0,1},δ,S0,{S1,S3}){\displaystyle M=(\{S_{0},S_{1},S_{2},S_{3},S_{4}\},\{0,1\},\delta ,S_{0},\{S_{1},S_{3}\})}where the transition relationδ{\displaystyle \delta }can be defined by thisstate transition table: M{\displaystyle M}can be viewed as the union of twoDFAs: one with states{S1,S2}{\displaystyle \{S_{1},S_{2}\}}and the other with states{S3,S4}{\displaystyle \{S_{3},S_{4}\}}. The language ofM{\displaystyle M}can be described by theregular languagegiven by thisregular expression(1∗01∗01∗)∗∪(0∗10∗10∗)∗{\displaystyle (1^{}01^{}01^{})^{}\cup (0^{}10^{}10^{})^{}}. We defineM{\displaystyle M}using ε-moves butM{\displaystyle M}can be defined without using ε-moves. To show NFA-ε is equivalent to NFA, first note that NFA is a special case of NFA-ε, so it remains to show for every NFA-ε, there exists an equivalent NFA. Given an NFA with epsilon movesM=(Q,Σ,δ,q0,F),{\displaystyle M=(Q,\Sigma ,\delta ,q_{0},F),}define an NFAM′=(Q,Σ,δ′,q0,F′),{\displaystyle M'=(Q,\Sigma ,\delta ',q_{0},F'),}where and One has to distinguish the transition functions ofM{\displaystyle M}andM′,{\displaystyle M',}viz.δ{\displaystyle \delta }andδ′,{\displaystyle \delta ',}and their extensions to strings,δ{\displaystyle \delta }andδ′∗,{\displaystyle \delta '^{},}respectively. By construction,M′{\displaystyle M'}has no ε-transitions. One can prove thatδ′∗(q0,w)=δ∗(q0,w){\displaystyle \delta '^{}(q_{0},w)=\delta ^{}(q_{0},w)}for each stringw≠ε{\displaystyle w\neq \varepsilon }, byinductionon the length ofw.{\displaystyle w.} Based on this, one can show thatδ′∗(q0,w)∩F′≠{}{\displaystyle \delta '^{}(q_{0},w)\cap F'\neq \{\}}if, and only if,δ∗(q0,w)∩F≠{},{\displaystyle \delta ^{}(q_{0},w)\cap F\neq \{\},}for each stringw∈Σ∗:{\displaystyle w\in \Sigma ^{*}:} Since NFA is equivalent to DFA, NFA-ε is also equivalent to DFA. The set of languages recognized by NFAs isclosed underthe following operations. These closure operations are used inThompson's construction algorithm, which constructs an NFA from anyregular expression. They can also be used to prove that NFAs recognize exactly theregular languages. Since NFAs are equivalent to nondeterministic finite automaton with ε-moves (NFA-ε), the above closures are proved using closure properties of NFA-ε. The machine starts in the specified initial state and reads in a string of symbols from itsalphabet. The automaton uses thestate transition functionΔ to determine the next state using the current state, and the symbol just read or the empty string. However, "the next state of an NFA depends not only on the current input event, but also on an arbitrary number of subsequent input events. Until these subsequent events occur it is not possible to determine which state the machine is in".[13]If, when the automaton has finished reading, it is in an accepting state, the NFA is said to accept the string, otherwise it is said to reject the string. The set of all strings accepted by an NFA is the language the NFA accepts. This language is aregular language. For every NFA adeterministic finite automaton(DFA) can be found that accepts the same language. Therefore, it is possible to convert an existing NFA into a DFA for the purpose of implementing a (perhaps) simpler machine. This can be performed using thepowerset construction, which may lead to an exponential rise in the number of necessary states. For a formal proof of the powerset construction, please see thePowerset constructionarticle. There are many ways to implement a NFA: NFAs and DFAs are equivalent in that if a language is recognized by an NFA, it is also recognized by a DFA and vice versa. The establishment of such equivalence is important and useful. It is useful because constructing an NFA to recognize a given language is sometimes much easier than constructing a DFA for that language. It is important because NFAs can be used to reduce the complexity of the mathematical work required to establish many important properties in thetheory of computation. For example, it is much easier to proveclosure propertiesofregular languagesusing NFAs than DFAs.	https://en.wikipedia.org/wiki/Nondeterministic_finite_automaton
Collective intelligenceCollective actionSelf-organized criticalityHerd mentalityPhase transitionAgent-based modellingSynchronizationAnt colony optimizationParticle swarm optimizationSwarm behaviour Social network analysisSmall-world networksCentralityMotifsGraph theoryScalingRobustnessSystems biologyDynamic networks Evolutionary computationGenetic algorithmsGenetic programmingArtificial lifeMachine learningEvolutionary developmental biologyArtificial intelligenceEvolutionary robotics Reaction–diffusion systemsPartial differential equationsDissipative structuresPercolationCellular automataSpatial ecologySelf-replication Conversation theoryEntropyFeedbackGoal-orientedHomeostasisInformation theoryOperationalizationSecond-order cyberneticsSelf-referenceSystem dynamicsSystems scienceSystems thinkingSensemakingVariety Ordinary differential equationsPhase spaceAttractorsPopulation dynamicsChaosMultistabilityBifurcation Rational choice theoryBounded rationality Cyberneticsis thetransdisciplinarystudy of circular causal[1]processes such asfeedbackandrecursion, where the effects of asystem's actions (its outputs) return as inputs to that system, influencing subsequent action.[2]It is concerned with general principles that are relevant across multiple contexts,[3]including inengineering,ecological,economic,biological,cognitiveandsocial systemsand also in practical activities such asdesigning,[4]learning, andmanaging. Cybernetics' transdisciplinary[5]character has meant that itintersectswith a number of other fields, leading to it having both wide influence and diverse interpretations. The field is named after an example of circular causal feedback—that of steering a ship (the ancientGreekκυβερνήτης (kybernḗtēs) refers to the person who steers a ship). In steering a ship, the position of the rudder is adjusted in continual response to the effect it is observed as having, forming a feedback loop through which a steady course can be maintained in a changing environment, responding to disturbances from cross winds and tide.[6][7] Cybernetics has its origins in exchanges between numerous disciplines during the1940s. Initial developments were consolidated through meetings such as theMacy Conferencesand theRatio Club. Early focuses included purposeful behaviour,[8]neural networks,heterarchy,information theory, and self-organising systems.[9]As cybernetics developed, it became broader in scope to include work in design, family therapy, management and organisation, pedagogy,sociology, the creative arts and the counterculture.[10] Cybernetics has been defined in a variety of ways, reflecting "the richness of its conceptual base."[11]One of the best known definitions is that of the American scientistNorbert Wiener, who characterised cybernetics as concerned with "control and communication in the animal and the machine."[12]Another early definition is that of theMacy cybernetics conferences, where cybernetics was understood as the study of "circular causal and feedback mechanisms in biological and social systems."[13]Margaret Meademphasised the role of cybernetics as "a form of cross-disciplinary thought which made it possible for members of many disciplines to communicate with each other easily in a language which all could understand."[14] Other definitions include:[15]"the art of governing or the science of government" (André-Marie Ampère); "the art of steersmanship" (Ross Ashby); "the study of systems of any nature which are capable of receiving, storing, and processing information so as to use it for control" (Andrey Kolmogorov); and "a branch of mathematics dealing with problems of control, recursiveness, and information, focuses on forms and the patterns that connect" (Gregory Bateson). TheAncient Greekterm κυβερνητικός (kubernētikos, '(good at) steering') appears inPlato'sRepublic[16]andAlcibiades, where the metaphor of asteersmanis used to signify thegovernanceof people.[17]The French wordcybernétiquewas also used in 1834 by the physicistAndré-Marie Ampèreto denote the sciences of government in his classification system of human knowledge. According to Norbert Wiener, the wordcyberneticswas coined by a research group involving himself andArturo Rosenbluethin the summer of 1947.[12]It has been attested in print since at least 1948 through Wiener's bookCybernetics: Or Control and Communication in the Animal and the Machine.[note 1]In the book, Wiener states: After much consideration, we have come to the conclusion that all the existing terminology has too heavy a bias to one side or another to serve the future development of the field as well as it should; and as happens so often to scientists, we have been forced to coin at least one artificial neo-Greek expression to fill the gap. We have decided to call the entire field of control and communication theory, whether in the machine or in the animal, by the nameCybernetics, which we form from theGreekκυβερνήτηςorsteersman. Moreover, Wiener explains, the term was chosen to recognizeJames Clerk Maxwell's 1868 publication on feedback mechanisms involvinggovernors, noting that the termgovernoris also derived from κυβερνήτης (kubernḗtēs) via a Latin corruptiongubernator. Finally, Wiener motivates the choice bysteering engines of a shipbeing "one of the earliest and best-developed forms of feedback mechanisms".[12] The initial focus of cybernetics was on parallels between regulatory feedback processes in biological and technological systems. Two foundational articles were published in 1943: "Behavior, Purpose and Teleology" by Arturo Rosenblueth, Norbert Wiener, andJulian Bigelow– based on the research on living organisms that Rosenblueth did in Mexico – and the paper "A Logical Calculus of the Ideas Immanent in Nervous Activity" byWarren McCullochandWalter Pitts. The foundations of cybernetics were then developed through a series of transdisciplinary conferences funded by the Josiah Macy, Jr. Foundation, between 1946 and 1953. The conferences were chaired byMcCullochand had participants includedRoss Ashby,Gregory Bateson,Heinz von Foerster,Margaret Mead,John von Neumann, andNorbert Wiener. In the UK, similar focuses were explored by theRatio Club, an informal dining club of young psychiatrists, psychologists, physiologists, mathematicians and engineers that met between 1949 and 1958. Wiener introduced the neologismcyberneticsto denote the study of "teleological mechanisms" and popularized it through the bookCybernetics: Or Control and Communication in the Animal and the Machine.[12] During the 1950s, cybernetics was developed as a primarily technical discipline, such as inQian Xuesen's 1954 "Engineering Cybernetics".In the Soviet Union, Cybernetics was initially considered with suspicion[19]but became accepted from the mid to late 1950s. By the 1960s and 1970s, however, cybernetics' transdisciplinarity fragmented, with technical focuses separating into separate fields.Artificial intelligence(AI) was founded as a distinct discipline at theDartmouth workshopin 1956, differentiating itself from the broader cybernetics field. After some uneasy coexistence, AI gained funding and prominence. Consequently, cybernetic sciences such as the study ofartificial neural networkswere downplayed.[20]Similarly,computer sciencebecame defined as a distinct academic discipline in the 1950s and early 1960s.[21] The second wave of cybernetics came to prominence from the 1960s onwards, with its focus inflecting away from technology toward social, ecological, and philosophical concerns. It was still grounded in biology, notablyMaturanaandVarela'sautopoiesis, and built on earlier work onself-organising systemsand the presence of anthropologists Mead and Bateson in the Macy meetings. The Biological Computer Laboratory, founded in 1958 and active until the mid-1970s under the direction ofHeinz von Foersterat theUniversity of Illinois at Urbana–Champaign, was a major incubator of this trend in cybernetics research.[22] Focuses of the second wave of cybernetics included management cybernetics, such as Stafford Beer's biologically inspiredviable system model; work in family therapy, drawing on Bateson; social systems, such as in the work ofNiklas Luhmann; epistemology and pedagogy, such as in the development of radical constructivism.[23]Cybernetics' core theme of circular causality was developed beyond goal-oriented processes to concerns with reflexivity and recursion. This was especially so in the development ofsecond-order cybernetics(or the cybernetics of cybernetics), developed and promoted by Heinz von Foerster, which focused on questions of observation, cognition, epistemology, and ethics. The 1960s onwards also saw cybernetics begin to develop exchanges with the creative arts, design, and architecture, notably with theCybernetic Serendipityexhibition (ICA, London, 1968), curated byJasia Reichardt,[24][25]and the unrealised Fun Palace project (London, unrealised, 1964 onwards), whereGordon Paskwas consultant to architect Cedric Price and theatre director Joan Littlewood.[26] From the 1990s onwards, there has been a renewed interest in cybernetics from a number of directions. Early cybernetic work on artificial neural networks has been returned to as aparadigminmachine learningand artificial intelligence. The entanglements of society with emerging technologies has led to exchanges withfeminist technoscienceandposthumanism. Re-examinations of cybernetics' history have seen science studies scholars emphasising cybernetics' unusual qualities as a science, such as its "performativeontology".[27]Practical design disciplines have drawn on cybernetics fortheoreticalunderpinning and transdisciplinary connections. Emerging topics include how cybernetics' engagements with social, human, and ecological contexts might come together with its earlier technological focus, whether as a critical discourse[28][29]or a "new branch of engineering".[30] The central theme in cybernetics isfeedback. Feedback is a process where the observed outcomes of actions are taken as inputs for further action in ways that support the pursuit, maintenance, or disruption of particular conditions, forming a circular causal relationship. In steering a ship, the helmsperson maintains a steady course in a changing environment by adjusting their steering in continual response to the effect it is observed as having.[6] Other examples of circular causal feedback include: technological devices such as thethermostat, where the action of a heater responds to measured changes in temperature regulating the temperature of the room within a set range, and thecentrifugal governorof a steam engine, which regulates the engine speed; biological examples such as the coordination of volitional movement through thenervous systemand thehomeostaticprocesses that regulate variables such as blood sugar; and processes of social interaction such as conversation.[31] Negative feedbackprocesses are those that maintain particular conditions by reducing (hence 'negative') the difference from a desired state, such as where a thermostat turns on a heater when it is too cold and turns a heater off when it is too hot.Positive feedbackprocesses increase (hence 'positive') the difference from a desired state. An example of positive feedback is when a microphone picks up the sound that it is producing through a speaker, which is then played through the speaker, and so on. In addition to feedback, cybernetics is concerned with other forms of circular processes including:feedforward,recursion, andreflexivity. Other key concepts and theories in cybernetics include: Cybernetics' central concept of circular causality is of wide applicability, leading to diverse applications and relations with other fields. Many of the initial applications of cybernetics focused onengineering,biology, and exchanges between the two, such asmedical cyberneticsandroboticsand topics such asneural networks,heterarchy.[35]In the social and behavioral sciences, cybernetics has included and influenced work inanthropology,sociology,economics,family therapy,[36]cognitive science, andpsychology.[37][38] As cybernetics has developed, it broadened in scope to include work in management, design,[4]pedagogy,[39][40]and the creative arts,[41]while also developing exchanges with constructivist philosophies, counter-cultural movements,[42]and media studies.[43]The development ofmanagement cyberneticshas led to a variety of applications, notably to the national economy of Chile under theAllendegovernment inProject Cybersyn. In design, cybernetics has been influential oninteractive architecture, human-computer interaction,[44]design research,[45]and the development ofsystemic designandmetadesignpractices. Cybernetics is often understood within the context of systems science,systems theory, andsystems thinking.[46][47]Systems approaches influenced by cybernetics includecritical systems thinking, which incorporates theviable system model;systemic design; andsystem dynamics, which is based on the concept of causal feedback loops. Many fields trace their origins in whole or part to work carried out in cybernetics, or were partially absorbed into cybernetics when it was developed. These includeartificial intelligence,bionics,cognitive science,control theory,complexity science,computer science,information theoryandrobotics. Some aspects of modernartificial intelligence, particularly thesocial machine, are often described in cybernetic terms.[48] Academic journals with focuses in cybernetics include: Academic societies primarily concerned with cybernetics or aspects of it include: General Societies and journals	https://en.wikipedia.org/wiki/Cybernetics
Ahorn analyzeris a test instrument dedicated to determine theresonanceandanti-resonancefrequencies ofultrasonicparts such astransducers, converters, horns/sonotrodesand acoustic stacks, which are used forultrasonic welding, cutting,cleaning, medical and industrial applications. In addition, digital horn analyzers are able to determine theelectrical impedanceofpiezoelectricmaterials, the Butterworth-Van Dyke (BVD) equivalent circuit and the mechanical quality factor (Qm). A digital horn analyzer performs a frequency sweep while monitoring the current flowing through the device under test, in order to detect the resonance and anti-resonance frequencies and their respective electrical impedances. The anti-resonance is the frequency at which the current encounters maximum impedance, and the resonance is the frequency of minimum impedance. In analogmicroampere-meter-based horn analyzers, the user identifies the frequencies manually, using the meter to detect the points of minimum and maximum current while sweeping the driving frequency. In digital analyzers, frequency detection and impedance calculation are performed automatically through embedded software. Impedance analyzers can be used as advanced horn analyzers, but are not usually a cost-effective alternative for everyday industrial demands, due to their higher cost, larger size and greater complexity. Horn analyzers are widely used by manufacturers of power ultrasonic equipment, to allow the proper tuning and quality control of sonotrodes, transducers and boosters.[1]Horn analyzers are also employed by end-users for preventive and corrective maintenance. Accurate frequency tuning is indispensable for the proper use of power ultrasonic equipment.[2]In an acoustic set, the parts act like narrow pass-band filters, and their central frequencies should be perfectly aligned to avoid heating losses and to improve energy transmission. Horn analyzers can be tuned to the desired frequency using alatheormilling machineby adjusting the part dimensions to the desired value.[3]	https://en.wikipedia.org/wiki/Horn_analyzer
This is alist ofsensorssorted by sensor type. Speed sensors are machines used to detect the speed of an object, usually a transport vehicle. They include:	https://en.wikipedia.org/wiki/List_of_sensors
Atactile sensoris a device that measures information arising from physical interaction with its environment. Tactile sensors are generally modeled after the biological sense ofcutaneous touchwhich is capable of detecting stimuli resulting from mechanical stimulation, temperature, and pain (although pain sensing is not common in artificial tactile sensors). Tactilesensorsare used inrobotics,computer hardwareandsecurity systems. A common application of tactile sensors is intouchscreendevices onmobile phonesandcomputing. Tactile sensors may be of different types includingpiezoresistive,piezoelectric, optical, capacitive and elastoresistive sensors.[3] Tactile sensors appear in everyday life such as elevator buttons and lamps which dim or brighten by touching the base. There are also innumerable other applications for tactile sensors of which most people are never aware. Sensors that measure very small changes must have very high sensitivities. Sensors need to be designed to have a small effect on what is measured; making the sensor smaller often improves this and may introduce other advantages. Tactile sensors can be used to test the performance of all types of applications. For example, these sensors have been used in themanufacturingofautomobiles(brakes, clutches, door seals,gasket),batterylamination, bolted joints,fuel cellsetc. Tactile imaging, as a medical imaging modality, translating the sense of touch into a digital image is based on the tactile sensors. Tactile imaging closely mimics manual palpation, since the probe of the device with a pressuresensor arraymounted on its face acts similar to human fingers during clinical examination, deforming soft tissue by the probe and detecting resulting changes in the pressure pattern. Robotsdesigned to interact with objects requiring handling involving precision,dexterity, or interaction with unusual objects, need sensory apparatus which is functionally equivalent to a human's tactile ability. Tactile sensors have been developed for use with robots.[4][5][6][better source needed]Tactile sensors can complement visual systems by providing added information when the robot begins to grip an object. At this time vision is no longer sufficient, as the mechanical properties of the object cannot be determined by vision alone. Determining weight, texture,stiffness,center of mass, curvature,coefficient of friction, andthermal conductivityrequire object interaction and some sort of tactile sensing. Several classes of tactile sensors are used in robots of different kinds, for tasks spanning collision avoidance and manipulation.[citation needed]Some methods forsimultaneous localization and mappingare based on tactile sensors.[7] Pressure sensor arrays are large grids of tactels. A "tactel" is a 'tactile element'. Each tactel is capable of detecting normal forces. Tactel-based sensors provide a high resolution 'image' of the contact surface. Alongside spatial resolution and force sensitivity, systems-integration questions such as wiring and signal routing are important.[8]Pressure sensor arrays are available inthin-filmform. They are primarily used as analytical tools used in themanufacturingandR&Dprocesses by engineers and technicians, and have been adapted for use in robots. Examples of such sensors available to consumers include arrays built fromconductive rubber,[9]lead zirconate titanate(PZT),polyvinylidene fluoride(PVDF), PVDF-TrFE,[10]FET,[11]and metalliccapacitive sensing[12][13]elements. Several kinds of tactile sensors have been developed that take advantage of camera-like technology to provide high-resolution data. A key exemplar is the Gelsight technology first developed at MIT which uses a camera behind an opaque gel layer to achieve high-resolution tactile feedback.[14][15]The Samsung ``See-through-your-skin(STS) sensor uses a semi-transparent gel to produce combined tactile and optical imaging.[16] Strain gauges rosettes are constructed from multiplestrain gauges, with each gauge detecting the force in a particular direction. When the information from each strain gauge is combined, the information allows determination of a pattern of forces or torques.[17] A variety of biologically inspired designs have been suggested ranging from simple whisker-like sensors which measure only one point at a time[18]through more advanced fingertip-like sensors,[19][20][21]to complete skin-like sensors as on the latestiCub[citation needed]. Biologically inspired tactile sensors often incorporate more than one sensing strategy. For example, they might detect both the distribution of pressures, and the pattern of forces that would come from pressure sensor arrays and strain gauge rosettes, allowingtwo-point discriminationand force sensing, with human-like ability. Advanced versions of biologically designed tactile sensors includevibrationsensing which has been determined to be important for understanding interactions between the tactile sensor and objects where the sensor slides over the object. Such interactions are now understood to be important for human tool use and judging the texture even curvature of an object.[19][6]One such sensor combines force sensing, vibration sensing, and heat transfer sensing.[1] A recent breakthrough bioinspired tactile sensor that lets robots "feel" their surroundings with 1.76° precision, enabling blind navigation (0.2mm accuracy) and texture recognition (97% success). Its ultra-robust design withstands extreme deformations for reliable operation in real-world environments.[6] Recently, a sophisticated tactile sensor has been madeopen-hardware, enabling enthusiasts and hobbyists to experiment with an otherwise expensive technology.[22]Furthermore, with the advent of cheap optical cameras, novel sensors have been proposed which can be built easily and cheaply with a 3D printer.[23]	https://en.wikipedia.org/wiki/Tactile_sensor
Backtrackingis a class ofalgorithmsfor finding solutions to somecomputational problems, notablyconstraint satisfaction problems, that incrementally builds candidates to the solutions, and abandons a candidate ("backtracks") as soon as it determines that the candidate cannot possibly be completed to a valid solution.[1] The classic textbook example of the use of backtracking is theeight queens puzzle, that asks for all arrangements of eightchessqueenson a standardchessboardso that no queen attacks any other. In the common backtracking approach, the partial candidates are arrangements ofkqueens in the firstkrows of the board, all in different rows and columns. Any partial solution that contains two mutually attacking queens can be abandoned. Backtracking can be applied only for problems which admit the concept of a "partial candidate solution" and a relatively quick test of whether it can possibly be completed to a valid solution. It is useless, for example, for locating a given value in an unordered table. When it is applicable, however, backtracking is often much faster thanbrute-force enumerationof all complete candidates, since it can eliminate many candidates with a single test. Backtracking is an important tool for solvingconstraint satisfaction problems,[2]such ascrosswords,verbal arithmetic,Sudoku, and many other puzzles. It is often the most convenient technique forparsing,[3]for theknapsack problemand othercombinatorial optimizationproblems. It is also the program execution strategy used in the programming languagesIcon,PlannerandProlog. Backtracking depends on user-given "black box procedures" that define the problem to be solved, the nature of the partial candidates, and how they are extended into complete candidates. It is therefore ametaheuristicrather than a specific algorithm – although, unlike many other meta-heuristics, it is guaranteed to find all solutions to a finite problem in a bounded amount of time. The term "backtrack" was coined by American mathematicianD. H. Lehmerin the 1950s.[4]The pioneer string-processing languageSNOBOL(1962) may have been the first to provide a built-in general backtracking facility. The backtracking algorithm enumerates a set ofpartial candidatesthat, in principle, could becompletedin various ways to give all the possible solutions to the given problem. The completion is done incrementally, by a sequence ofcandidate extension steps. Conceptually, the partial candidates are represented as the nodes of atree structure, thepotential search tree.Each partial candidate is the parent of the candidates that differ from it by a single extension step; the leaves of the tree are the partial candidates that cannot be extended any further. The backtracking algorithm traverses this search treerecursively, from the root down, indepth-first order. At each nodec, the algorithm checks whetherccan be completed to a valid solution. If it cannot, the whole sub-tree rooted atcis skipped (pruned). Otherwise, the algorithm (1) checks whethercitself is a valid solution, and if so reports it to the user; and (2) recursively enumerates all sub-trees ofc. The two tests and the children of each node are defined by user-given procedures. Therefore, theactual search treethat is traversed by the algorithm is only a part of the potential tree. The total cost of the algorithm is the number of nodes of the actual tree times the cost of obtaining and processing each node. This fact should be considered when choosing the potential search tree and implementing the pruning test. In order to apply backtracking to a specific class of problems, one must provide the dataPfor the particular instance of the problem that is to be solved, and sixprocedural parameters,root,reject,accept,first,next, andoutput. These procedures should take the instance dataPas a parameter and should do the following: The backtracking algorithm reduces the problem to the callbacktrack(P,root(P)), wherebacktrackis the following recursive procedure: Therejectprocedure should be aBoolean-valued functionthat returnstrueonly if it is certain that no possible extension ofcis a valid solution forP. If the procedure cannot reach a definite conclusion, it should returnfalse. An incorrecttrueresult may cause thebacktrackprocedure to miss some valid solutions. The procedure may assume thatreject(P,t) returnedfalsefor every ancestortofcin the search tree. On the other hand, the efficiency of the backtracking algorithm depends onrejectreturningtruefor candidates that are as close to the root as possible. Ifrejectalways returnsfalse, the algorithm will still find all solutions, but it will be equivalent to a brute-force search. Theacceptprocedure should returntrueifcis a complete and valid solution for the problem instanceP, andfalseotherwise. It may assume that the partial candidatecand all its ancestors in the tree have passed therejecttest. The general pseudo-code above does not assume that the valid solutions are always leaves of the potential search tree. In other words, it admits the possibility that a valid solution forPcan be further extended to yield other valid solutions. Thefirstandnextprocedures are used by the backtracking algorithm to enumerate the children of a nodecof the tree, that is, the candidates that differ fromcby a single extension step. The callfirst(P,c) should yield the first child ofc, in some order; and the callnext(P,s) should return the next sibling of nodes, in that order. Both functions should return a distinctive "NULL" candidate, if the requested child does not exist. Together, theroot,first, andnextfunctions define the set of partial candidates and the potential search tree. They should be chosen so that every solution ofPoccurs somewhere in the tree, and no partial candidate occurs more than once. Moreover, they should admit an efficient and effectiverejectpredicate. The pseudo-code above will calloutputfor all candidates that are a solution to the given instanceP. The algorithm can be modified to stop after finding the first solution, or a specified number of solutions; or after testing a specified number of partial candidates, or after spending a given amount ofCPUtime. Examples where backtracking can be used to solve puzzles or problems include: The following is an example where backtracking is used for theconstraint satisfaction problem: The generalconstraint satisfaction problemconsists in finding a list of integersx= (x[1],x[2], …,x[n]), each in some range{1, 2, …,m}, that satisfies some arbitrary constraint (Boolean function)F. For this class of problems, the instance dataPwould be the integersmandn, and the predicateF. In a typical backtracking solution to this problem, one could define a partial candidate as a list of integersc= (c[1],c[2], …,c[k]), for anykbetween 0 andn, that are to be assigned to the firstkvariablesx[1],x[2], …,x[k]. The root candidate would then be the empty list (). Thefirstandnextprocedures would then be Herelength(c) is the number of elements in the listc. The callreject(P,c) should returntrueif the constraintFcannot be satisfied by any list ofnintegers that begins with thekelements ofc. For backtracking to be effective, there must be a way to detect this situation, at least for some candidatesc, without enumerating all thosemn−kn-tuples. For example, ifFis theconjunctionof several Boolean predicates,F=F[1] ∧F[2] ∧ … ∧F[p], and eachF[i] depends only on a small subset of the variablesx[1], …,x[n], then therejectprocedure could simply check the termsF[i] that depend only on variablesx[1], …,x[k], and returntrueif any of those terms returnsfalse. In fact,rejectneeds only check those terms that do depend onx[k], since the terms that depend only onx[1], …,x[k− 1]will have been tested further up in the search tree. Assuming thatrejectis implemented as above, thenaccept(P,c) needs only check whethercis complete, that is, whether it hasnelements. It is generally better to order the list of variables so that it begins with the most critical ones (i.e. the ones with fewest value options, or which have a greater impact on subsequent choices). One could also allow thenextfunction to choose which variable should be assigned when extending a partial candidate, based on the values of the variables already assigned by it. Further improvements can be obtained by the technique ofconstraint propagation. In addition to retaining minimal recovery values used in backing up, backtracking implementations commonly keep a variable trail, to record value change history. An efficient implementation will avoid creating a variable trail entry between two successive changes when there is no choice point, as the backtracking will erase all of the changes as a single operation. An alternative to the variable trail is to keep atimestampof when the last change was made to the variable. The timestamp is compared to the timestamp of a choice point. If the choice point has an associated time later than that of the variable, it is unnecessary to revert the variable when the choice point is backtracked, as it was changed before the choice point occurred.	https://en.wikipedia.org/wiki/Backtracking
Incomputer science, achart parseris a type ofparsersuitable forambiguous grammars(including grammars ofnatural languages). It uses thedynamic programmingapproach—partial hypothesized results are stored in a structure called a chart and can be re-used. This eliminatesbacktrackingand prevents acombinatorial explosion. Chart parsing is generally credited toMartin Kay.[1] A common approach is to use a variant of theViterbi algorithm. TheEarley parseris a type of chart parser mainly used for parsing incomputational linguistics, named for its inventor. Another chart parsing algorithm is theCocke-Younger-Kasami(CYK) algorithm. Chart parsers can also be used for parsing computer languages. Earley parsers in particular have been used incompiler-compilerswhere their ability to parse using arbitraryContext-free grammarseases the task of writing the grammar for a particular language. However their lower efficiency has led to people avoiding them for most compiler work. In bidirectional chart parsing, edges of the chart are marked with a direction, either forwards or backwards, and rules are enforced on the direction in which edges must point in order to be combined into further edges. In incremental chart parsing, the chart is constructed incrementally as the text is edited by the user, with each change to the text resulting in the minimal possible corresponding change to the chart. Chart parsers are distinguished betweentop-downandbottom-up, as well as active and passive.	https://en.wikipedia.org/wiki/Chart_parser
Incomputer science, acompiler-compilerorcompiler generatoris a programming tool that creates aparser,interpreter, orcompilerfrom some form of formal description of aprogramming languageand machine. The most common type of compiler-compiler is called aparser generator.[1]It handles onlysyntactic analysis. A formal description of a language is usually agrammarused as an input to a parser generator. It often resemblesBackus–Naur form(BNF),extended Backus–Naur form(EBNF), or has its own syntax. Grammar files describe asyntaxof a generated compiler's target programming language and actions that should be taken against its specific constructs. Source codefor a parser of the programming language is returned as the parser generator's output. This source code can then be compiled into a parser, which may be either standalone or embedded. The compiled parser then accepts the source code of the target programming language as an input and performs an action or outputs anabstract syntax tree(AST). Parser generators do not handle thesemanticsof the AST, or thegeneration of machine codefor the target machine.[2] Ametacompileris a software development tool used mainly in the construction ofcompilers,translators, andinterpretersfor other programming languages.[3]The input to a metacompiler is acomputer programwritten in aspecializedprogrammingmetalanguagedesigned mainly for the purpose of constructing compilers.[3][4]The language of the compiler produced is called the object language. The minimal input producing a compiler is ametaprogramspecifying the object language grammar andsemantictransformations into anobject program.[4][5] A typical parser generator associates executable code with each of the rules of the grammar that should be executed when these rules are applied by the parser. These pieces of code are sometimes referred to as semantic action routines since they define the semantics of the syntactic structure that is analyzed by the parser. Depending upon the type of parser that should be generated, these routines may construct aparse tree(orabstract syntax tree), or generate executable code directly. One of the earliest (1964), surprisingly powerful, versions of compiler-compilers isMETA II, which accepted an analytical grammar with output facilitiesthat produce stack machinecode, and is able to compile its own source code and other languages. Among the earliest programs of the originalUnixversions being built atBell Labswas the two-partlexandyaccsystem, which was normally used to outputC programming languagecode, but had a flexible output system that could be used for everything from programming languages to text file conversion. Their modernGNUversions areflexandbison. Some experimental compiler-compilers take as input a formal description of programming language semantics, typically usingdenotational semantics. This approach is often called 'semantics-based compiling', and was pioneered byPeter Mosses' Semantic Implementation System (SIS) in 1978.[6]However, both the generated compiler and the code it produced were inefficient in time and space. No production compilers are currently built in this way, but research continues. The Production Quality Compiler-Compiler (PQCC) project atCarnegie Mellon Universitydoes not formalize semantics, but does have a semi-formal framework for machine description. Compiler-compilers exist in many flavors, including bottom-up rewrite machine generators (seeJBurg) used to tile syntax trees according to a rewrite grammar for code generation, andattribute grammarparser generators (e.g.ANTLRcan be used for simultaneous type checking, constant propagation, and more during the parsing stage). Metacompilers reduce the task of writing compilers by automating the aspects that are the same regardless of the object language. This makes possible the design ofdomain-specific languageswhich are appropriate to the specification of a particular problem. A metacompiler reduces the cost of producingtranslatorsfor suchdomain-specificobject languages to a point where it becomes economically feasible to include in the solution of a problem adomain-specific languagedesign.[4] As a metacompiler'smetalanguagewill usually be a powerful string and symbol processing language, they often have strong applications for general-purpose applications, including generating a wide range of other software engineering and analysis tools.[4][7] Besides being useful fordomain-specific languagedevelopment, a metacompiler is a prime example of a domain-specific language, designed for the domain of compiler writing. A metacompiler is ametaprogramusually written in its own metalanguageor an existing computer programming language. The process of a metacompiler, written in its own metalanguage, compiling itself is equivalent toself-hosting compiler. Most common compilers written today are self-hosting compilers. Self-hosting is a powerful tool, of many metacompilers, allowing the easy extension of their own metaprogramming metalanguage. The feature that separates a metacompiler apart from other compiler compilers is that it takes as input a specializedmetaprogramminglanguage that describes all aspects of the compiler's operation. A metaprogram produced by a metacompiler is as complete a program as aprogramwritten inC++,BASICor any other generalprogramming language. The metaprogrammingmetalanguageis a powerful attribute allowing easier development of computer programming languages and other computer tools. Command line processors, text string transforming and analysis are easily coded using metaprogramming metalanguages of metacompilers. A full featured development package includes alinkerand arun timesupportlibrary. Usually, a machine-orientedsystem programming language, such asCor C++, is needed to write the support library. A library consisting of support functions needed for the compiling process usually completes the full metacompiler package. In computer science, the prefixmetais commonly used to meanabout (its own category). For example,metadataare data that describe other data. A language that is used to describe other languages is ametalanguage. Meta may also meanon a higher level of abstraction. Ametalanguageoperates on a higher level of abstraction in order to describe properties of a language.Backus–Naur form(BNF) is a formalmetalanguageoriginally used to defineALGOL 60. BNF is a weakmetalanguage, for it describes only thesyntaxand says nothing about thesemanticsor meaning. Metaprogramming is the writing ofcomputer programswith the ability to treatprogramsas their data. A metacompiler takes as input ametaprogramwritten in aspecialized metalanguages(a higher level abstraction) specifically designed for the purpose of metaprogramming.[4][5]The output is an executable object program. An analogy can be drawn: That as aC++compiler takes as input aC++programming language program, ametacompiler takes as input ametaprogrammingmetalanguageprogram. Many advocates of the languageForthcall the process of creating a new implementation of Forth a meta-compilation and that it constitutes a metacompiler. The Forth definition of metacompiler is: This Forth use of the term metacompiler is disputed in mainstream computer science. SeeForth (programming language)andHistory of compiler construction. The actual Forth process of compiling itself is a combination of a Forth being aself-hostingextensible programminglanguage and sometimescross compilation, long established terminology in computer science. Metacompilers are a general compiler writing system. Besides the Forth metacompiler concept being indistinguishable from self-hosting and extensible language. The actual process acts at a lower level defining a minimum subset of forthwords, that can be used to define additional forth words, A full Forth implementation can then be defined from the base set. This sounds like a bootstrap process. The problem is that almost every general purpose language compiler also fits the Forth metacompiler description. Just replace X with any common language, C, C++,Java,Pascal,COBOL,Fortran,Ada,Modula-2, etc. And X would be a metacompiler according to the Forth usage of metacompiler. A metacompiler operates at an abstraction level above the compiler it compiles. It only operates at the same (self-hosting compiler) level when compiling itself. One has to see the problem with this definition of metacompiler. It can be applied to most any language. However, on examining the concept of programming in Forth, adding new words to the dictionary, extending the language in this way is metaprogramming. It is this metaprogramming in Forth that makes it a metacompiler. Programming in Forth is adding new words to the language. Changing the language in this way ismetaprogramming. Forth is a metacompiler, because Forth is a language specifically designed for metaprogramming. Programming in Forth is extending Forth adding words to the Forth vocabulary creates a new Forthdialect. Forth is a specialized metacompiler for Forth language dialects. Design of the original compiler-compiler was started byTony Brookerand Derrick Morris in 1959, with initial testing beginning in March 1962.[8]The Brooker Morris Compiler Compiler (BMCC) was used to create compilers for the newAtlascomputer at theUniversity of Manchester, for several languages:Mercury Autocode, Extended Mercury Autocode,Atlas Autocode,ALGOL 60and ASAFortran. At roughly the same time, related work was being done by E. T. (Ned) Irons at Princeton, and Alick Glennie at the Atomic Weapons Research Establishment at Aldermaston whose "Syntax Machine" paper (declassified in 1977) inspired the META series of translator writing systems mentioned below. The early history of metacompilers is closely tied with the history of SIG/PLAN Working group 1 on Syntax Driven Compilers. The group was started primarily through the effort of Howard Metcalfe in the Los Angeles area.[9]In the fall of 1962, Howard Metcalfe designed two compiler-writing interpreters. One used a bottom-to-top analysis technique based on a method described by Ledley and Wilson.[10]The other used a top-to-bottom approach based on work by Glennie to generate random English sentences from a context-free grammar.[11] At the same time, Val Schorre described two "meta machines", one generative and one analytic. The generative machine was implemented and produced random algebraic expressions. Meta I the first metacompiler was implemented by Schorre on an IBM 1401 at UCLA in January 1963. His original interpreters and metamachines were written directly in a pseudo-machine language.META II, however, was written in a higher-level metalanguage able to describe its own compilation into the pseudo-machine language.[12][13][14] Lee Schmidt at Bolt, Beranek, and Newman wrote a metacompiler in March 1963 that utilized a CRT display on the time-sharing PDP-l.[15]This compiler produced actual machine code rather than interpretive code and was partially bootstrapped from Meta I.[citation needed] Schorre bootstrapped Meta II from Meta I during the spring of 1963. The paper on the refined metacompiler system presented at the 1964 Philadelphia ACM conference is the first paper on a metacompiler available as a general reference. The syntax and implementation technique of Schorre's system laid the foundation for most of the systems that followed. The system was implemented on a small 1401, and was used to implement a smallALGOL-like language.[citation needed] Many similar systems immediately followed.[citation needed] Roger Rutman ofAC Delcodeveloped and implemented LOGIK, a language for logical design simulation, on the IBM 7090 in January 1964.[16]This compiler used an algorithm that produced efficient code for Boolean expressions.[citation needed] Another paper in the 1964 ACM proceedings describesMeta III, developed bySchneiderand Johnson at UCLA for the IBM 7090.[17]Meta III represents an attempt to produce efficient machine code, for a large class of languages. Meta III was implemented completely in assembly language. Two compilers were written in Meta III, CODOL, a compiler-writing demonstration compiler, and PUREGOL, a dialect of ALGOL 60. (It was pure gall to call it ALGOL). Late in 1964, Lee Schmidt bootstrapped the metacompiler EQGEN, from the PDP-l to the Beckman 420. EQGEN was a logic equation generating language. In 1964, System Development Corporation began a major effort in the development of metacompilers. This effort includes powerful metacompilers, Bookl, and Book2 written inLispwhich have extensive tree-searching and backup ability. An outgrowth of one of theQ-32systems at SDC is Meta 5.[18]The Meta 5 system incorporates backup of the input stream and enough other facilities to parse any context-sensitive language. This system was successfully released to a wide number of users and had many string-manipulation applications other than compiling. It has many elaborate push-down stacks, attribute setting and testing facilities, and output mechanisms. That Meta 5 successfully translatesJOVIALprograms toPL/Iprograms demonstrates its power and flexibility. Robert McClure atTexas Instrumentsinvented a compiler-compiler calledTMG(presented in 1965). TMG was used to create early compilers for programming languages likeB,PL/IandALTRAN. Together with metacompiler of Val Schorre, it was an early inspiration for the last chapter ofDonald Knuth'sThe Art of Computer Programming.[19] The LOT system was developed during 1966 at Stanford Research Institute and was modeled very closely after Meta II.[20]It had new special-purpose constructs allowing it to generate a compiler which could in turn, compile a subset of PL/I. This system had extensive statistic-gathering facilities and was used to study the characteristics of top-down analysis. SIMPLE is a specialized translator system designed to aid the writing of pre-processors for PL/I, SIMPLE, written in PL/I, is composed of three components: An executive, a syntax analyzer and a semantic constructor.[21] TheTREE-METAcompiler was developed at Stanford Research Institute in Menlo Park, California. April 1968. The early metacompiler history is well documented in theTREE META manual.TREE META paralleled some of the SDC developments. Unlike earlier metacompilers it separated the semantics processing from the syntax processing. The syntax rules containedtreebuilding operations that combined recognized language elements with tree nodes. The tree structure representation of the input was then processed by a simple form of unparse rules. The unparse rules used node recognition and attribute testing that when matched resulted in the associated action being performed. In addition like tree element could also be tested in an unparse rule. Unparse rules were also a recursive language being able to call unparse rules passing elements of thee tree before the action of the unparse rule was performed. The concept of the metamachine originally put forth by Glennie is so simple that three hardware versions have been designed and one actually implemented. The latter at Washington University in St. Louis. This machine was built from macro-modular components and has for instructions the codes described by Schorre. CWIC (Compiler for Writing and Implementing Compilers) is the last known Schorre metacompiler. It was developed at Systems Development Corporation by Erwin Book, Dewey Val Schorre and Steven J. Sherman With the full power of (lisp 2) a list processing language optimizing algorithms could operate on syntax generated lists and trees before code generation. CWIC also had a symbol table built into the language. With the resurgence of domain-specific languages and the need for parser generators which are easy to use, easy to understand, and easy to maintain, metacompilers are becoming a valuable tool for advanced software engineering projects. Other examples of parser generators in the yacc vein areANTLR,Coco/R,[22]CUP,[citation needed]GNU Bison, Eli,[23]FSL,[citation needed]SableCC, SID (Syntax Improving Device),[24]andJavaCC. While useful, pure parser generators only address the parsing part of the problem of building a compiler. Tools with broader scope, such asPQCC,Coco/RandDMS Software Reengineering Toolkitprovide considerable support for more difficult post-parsing activities such as semantic analysis, code optimization and generation. The earliest Schorre metacompilers, META I and META II, were developed by D. Val Schorre at UCLA. Other Schorre based metacompilers followed. Each adding improvements to language analysis and/or code generation. In programming it is common to use the programming language name to refer to both the compiler and the programming language, the context distinguishing the meaning. A C++ program is compiled using a C++ compiler. That also applies in the following. For example, META II is both the compiler and the language. The metalanguages in the Schorre line of metacompilers are functional programming languages that use top down grammar analyzing syntax equations having embedded output transformation constructs. A syntax equation: is a compiledtestfunction returningsuccessorfailure. <name> is the function name. <body> is a form of logical expression consisting of tests that may be grouped, have alternates, and output productions. Atestis like aboolin other languages,successbeingtrueandfailurebeingfalse. Defining a programming language analytically top down is natural. For example, a program could be defined as: Defining a program as a sequence of zero or more declaration(s). In the Schorre METAXlanguages there is a driving rule. The program rule above is an example of a driving rule. The program rule is atestfunction that calls declaration, atestrule, that returnssuccessorfailure. The $ loop operator repeatedly calling declaration untilfailureis returned. The $ operator is always successful, even when there are zero declaration. Above program would always return success. (In CWIC a long fail can bypass declaration. A long-fail is part of the backtracking system of CWIC) The character sets of these early compilers were limited. The character/was used for the alternant (or) operator. "A or B" is written as A / B. Parentheses ( ) are used for grouping. Describes a construct of A followed by B or C. As a boolean expression it would be A sequence X Y has an implied XandY meaning.( )are grouping and/theoroperator. The order of evaluation is always left to right as an input character sequence is being specified by the ordering of the tests. Special operator words whose first character is a "." are used for clarity. .EMPTY is used as the last alternate when no previous alternant need be present. Indicates that X is optionally followed by AorB. This is a specific characteristic of these metalanguages being programming languages. Backtracking is avoided by the above. Other compiler constructor systems may have declared the three possible sequences and left it up to the parser to figure it out. The characteristics of the metaprogramming metalanguages above are common to all Schorre metacompilers and those derived from them. META I was a hand compiled metacompiler used to compile META II. Little else is known of META I except that the initial compilation of META II produced nearly identical code to that of the hand coded META I compiler. Each rule consists optionally of tests, operators, and output productions. A rule attempts to match some part of the input program source character stream returning success or failure. On success the input is advanced over matched characters. On failure the input is not advanced. Output productions produced a form of assembly code directly from a syntax rule. TREE-META introduced tree building operators:<node_name> and[<number>]moving the output production transforms to unparsed rules. The tree building operators were used in the grammar rules directly transforming the input into anabstract syntax tree. Unparse rules are also test functions that matched tree patterns. Unparse rules are called from a grammar rule when an abstract syntax tree is to be transformed into output code. The building of an abstract syntax tree and unparse rules allowed local optimizations to be performed by analyzing the parse tree. Moving of output productions to the unparse rules made a clear separation of grammar analysis and code production. This made the programming easier to read and understand. In 1968–1970, Erwin Book, Dewey Val Schorre, and Steven J. Sherman developed CWIC.[4](Compiler for Writing and Implementing Compilers) atSystem Development CorporationCharles Babbage Institute Center for the History of Information Technology (Box 12, folder 21), CWIC is a compiler development system composed of three special-purpose, domain specific, languages, each intended to permit the description of certain aspects of translation in a straight forward manner. The syntax language is used to describe the recognition of source text and the construction from it to an intermediatetreestructure. The generator language is used to describe the transformation of the tree into appropriate object language. The syntax language follows Dewey Val Schorre's previous line of metacompilers. It most resembles TREE-META havingtreebuilding operators in the syntax language. The unparse rules of TREE-META are extended to work with the object based generator language based onLISP 2. CWIC includes three languages: Generators Language had semantics similar toLisp. The parsetreewas thought of as a recursive list. The general form of a Generator Language function is: The code to process a giventreeincluded the features of a general purpose programming language, plus a form: <stuff>, which would emit (stuff) onto the output file. A generator call may be used in the unparse_rule. The generator is passed the element of unparse_rule pattern in which it is placed and its return values are listed in (). For example: That is, if the parsetreelooks like (ADD[<something1>,<something2>]), expr_gen(x) would be called with <something1> and return x. A variable in the unparse rule is a local variable that can be used in the production_code_generator. expr_gen(y) is called with <something2> and returns y. Here is a generator call in an unparse rule is passed the element in the position it occupies. Hopefully in the above x and y will be registers on return. The last transforms is intended to load an atomic into a register and return the register. The first production would be used to generate the 360 "AR" (Add Register) instruction with the appropriate values in general registers. The above example is only a part of a generator. Every generator expression evaluates to a value that con then be further processed. The last transform could just as well have been written as: In this case load returns its first parameter, the register returned by getreg(). the functions load and getreg are other CWIC generators. From the authors of CWIC: "A metacompiler assists the task of compiler-building by automating its non creative aspects, those aspects that are the same regardless of the language which the produced compiler is to translate. This makes possible the design of languages which are appropriate to the specification of a particular problem. It reduces the cost of producing processors for such languages to a point where it becomes economically feasible to begin the solution of a problem with language design."[4]	https://en.wikipedia.org/wiki/Compiler-compiler
Innatural language processing,deterministic parsingrefers toparsingalgorithmsthat do notbacktrack.LR-parsersare an example. (This meaning of the words "deterministic" and "non-deterministic" differs from that used to describenondeterministic algorithms.) The deterministic behavior is desired and expected incompilingprogramming languages. In natural language processing, it was thought for a long time that deterministic parsing is impossible due to ambiguity inherent in natural languages (many sentences have more than one plausible parse). Thus, non-deterministic approaches such as thechart parserhad to be applied. However,Mitch Marcusproposed in 1978 the Parsifal parser that was able to deal withambiguitieswhile still keeping the deterministic behavior. Thiscomputer sciencearticle is astub. You can help Wikipedia byexpanding it.	https://en.wikipedia.org/wiki/Deterministic_parsing
TheDMS Software Reengineering Toolkitis a proprietary set ofprogram transformationtools available for automating custom source program analysis, modification, translation or generation of software systems for arbitrary mixtures of source languages for large scale software systems.[1]DMS was originally motivated by a theory for maintaining designs of software calledDesign Maintenance Systems.[2]DMS and "Design Maintenance System" are registered trademarks of Semantic Designs. DMS has been used to implementdomain-specific languages(such as code generation for factory control), test coverage[3]and profiling tools,clone detection,[4]language migration tools, C++ component reengineering.,[5]and for research into difficult topics such as refactoring C++ reliably.[6] The toolkit provides means for defining language grammars and will produceparserswhich automatically constructabstract syntax trees(ASTs), andprettyprintersto convert original or modified ASTs back into compilable source text. The parse trees capture, and the prettyprinters regenerate, complete detail about the original source program, including source position, comments, radix and format of numbers, etc., to ensure that regenerated source text is as recognizable to a programmer as the original text modulo any applied transformations. DMS usesGLRparsing technology with semantic predicates. This enables it to handle all context-free grammars as well as most non-context-free language syntaxes, such asFortran, which requires matching of multiple DO loops with shared CONTINUE statements by label to produce ASTs for correctly nested loops as it parses. DMS has a variety of predefined language front ends, covering most real dialects ofCandC++includingC++0x,C#,Java,Python,PHP,EGL,Fortran,COBOL,Visual Basic,Verilog,VHDLand some 20 or more other languages. DMS can handleASCII,ISO-8859,UTF-8,UTF-16,EBCDIC,Shift-JISand a variety of Microsoft character encodings. DMS providesattribute grammarevaluators for computing custom analyses over ASTs, such as metrics, and includes support forsymbol tableconstruction. Other program facts can be extracted by built-in control- and data-flow analysisengines, local and globalpointer analysis, whole-programcall graphextraction, and symbolic range analysis byabstract interpretation. DMS is implemented in aparallel programminglanguage, PARLANSE, which allows usingsymmetric multiprocessingto speed up large analyses and conversions.[7] Changes to ASTs can be accomplished by both procedural methods coded in PARLANSE and source-to-source tree transformations coded asrewrite rulesusing surface-syntax conditioned by any extracted program facts, using DMS's Rule Specification Language (RSL). The rewrite rule engine supporting RSL handles associative and commutative rules. A rewrite rule for C to replace a complex condition by the?:operator be written as: Rewriterules have names, e.g.simplify_conditional_assignment. Each rule has a"match this"and"replace by that"pattern pair separated by->, in our example, on separate lines for readability. The patterns must correspond to language syntax categories; in this case, both patterns must be of syntax categorystatementalso separated in sympathy with the patterns by->. Target language (e.g., C) surface syntax is coded inside meta-quotes", to separate rewrite-rule syntax from that of the target language. Backslashes inside meta-quotes represent domain escapes, to indicate pattern meta variables (e.g.,\v,\e1,\e2) that match any language construct corresponding to the metavariable declaration in the signature line, e.g.,e1must be of syntactic category:(any) expression. If a metavariable is mentioned multiple times in thematchpattern, it must match to identical subtrees; the same identically shapedvmust occur in both assignments in the match pattern in this example. Metavariables in thereplacepattern are replaced by the corresponding matches from the left side. A conditional clauseifprovides an additional condition that must be met for the rule to apply, e.g., that the matched metavariablev, being an arbitrary left-hand side, must not have a side effect (e.g., cannot be of the form ofa[i++]; theno_side_effectspredicate is defined by an analyzer built with other DMS mechanisms). Achieving a complex transformation on code is accomplished by providing a number of rules that cooperate to achieve the desired effect. The ruleset is focused on portions of the program by metaprograms coded in PARLANSE. A complete example of a language definition and source-to-source transformation rules defined and applied is shown using high schoolalgebraand a bit ofcalculusas a domain-specific language.	https://en.wikipedia.org/wiki/DMS_Software_Reengineering_Toolkit
Agrammar checker, incomputingterms, is aprogram, or part of a program, that attempts to verify written text forgrammatical correctness. Grammar checkers are most often implemented as a feature of a larger program, such as aword processor, but are also available as a stand-aloneapplicationthat can be activated from within programs that work with editable text. The implementation of a grammar checker makes use ofnatural language processing.[1][2] The earliest "grammar checkers" were programs that checked for punctuation and style inconsistencies, rather than a complete range of possible grammatical errors. The first system was calledWriter's Workbench, and was a set of writing tools included withUnixsystems as far back as the 1970s.[3][4]The wholeWriter's Workbenchpackage included several separate tools to check for various writing problems. The "diction" tool checked for wordy, trite, clichéd or misused phrases in a text. The tool would output a list of questionable phrases, and provide suggestions for improving the writing. The "style" tool analyzed the writing style of a given text. It performed a number of readability tests on the text and output the results, and gave some statistical information about the sentences of the text. Aspen Software ofAlbuquerque, New Mexicoreleased the earliest version of a diction and style checker for personal computers,Grammatik, in 1981.Grammatikwas first available for aRadio Shack-TRS-80, and soon had versions forCP/Mand theIBM PC.Reference Software Internationalof San Francisco, California, acquiredGrammatikin 1985. Development ofGrammatikcontinued, and it became an actual grammar checker that could detect writing errors beyond simple style checking. Other early diction and style checking programs includedPunctuation & Style,Correct Grammar,RightWriterandPowerEdit.[5]While all the earliest programs started out as simple diction and style checkers, all eventually added various levels of language processing, and developed some level of true grammar checking capability. Until 1992, grammar checkers were sold as add-on programs. There were a large number of different word processing programs available at that time, withWordPerfectandMicrosoft Wordthe top two in market share. In 1992,Microsoftdecided to add grammar checking as a feature of Word, and licensed CorrecText, a grammar checker fromHoughton Mifflinthat had not yet been marketed as a standalone product. WordPerfect answered Microsoft's move by acquiring Reference Software, and the direct descendant ofGrammatikis still included with WordPerfect. As of 2019, grammar checkers are built into systems likeGoogle Docsand Sapling.ai,[6]browser extensions likeGrammarlyandQordoba, desktop applications likeGinger,free and open-sourcesoftware likeLanguageTool,[7]and text editor plugins like those available from WebSpellChecker Software. The earliest writing style programs checked for wordy,trite,clichéd, or misused phrases in a text. This process was based on simplepattern matching. The heart of the program was a list of many hundreds or thousands of phrases that are considered poor writing by many experts. The list of questionable phrases included alternative wording for each phrase. The checking program would simply break text into sentences, check for any matches in the phrase dictionary, flag suspect phrases and show an alternative. These programs could also perform some mechanical checks. For example, they would typically flag doubled words, doubled punctuation, somecapitalizationerrors, and other simple mechanical mistakes. True grammar checking is more complex. While aprogramming languagehas a very specific syntax and grammar, this is not so fornatural languages. One can write a somewhat completeformal grammarfor a natural language, but there are usually so many exceptions in real usage that a formal grammar is of minimal help in writing a grammar checker. One of the most important parts of a natural language grammar checker is adictionaryof all the words in the language, along with the part of speech of each word. The fact that a natural word may be used as any one of several parts of speech (such as "free" being used as an adjective, adverb, noun, or verb) greatly increases the complexity of any grammar checker. A grammar checker will find each sentence in a text, look up each word in the dictionary, and then attempt toparsethe sentence into a form that matches a grammar. Using various rules, the program can then detect various errors, such as agreement intense, number,word order, and so on. It is also possible to detect some stylistic problems with the text. For example, some popular style guides such asThe Elements of Styledeprecate excessive use of thepassive voice. Grammar checkers may attempt to identify passive sentences and suggest an active-voice alternative. The software elements required for grammar checking are closely related to some of the development issues that need to be addressed forspeech recognitionsoftware. In voice recognition, parsing can be used to help predict which word is most likely intended, based on part of speech and position in the sentence. In grammar checking, the parsing is used to detect words that fail to follow accepted grammar usage. Recently,[when?]research has focused on developing algorithms which can recognize grammar errors based on thecontextof the surrounding words.[clarification needed] Grammar checkers are considered as a type offoreign language writing aidwhich non-native speakers can use to proofread their writings as such programs endeavor to identify syntactical errors.[8]However, as with other computerized writing aids such asspell checkers, popular grammar checkers are often criticized when they fail to spot errors and incorrectly flag correct text as erroneous. The linguistGeoffrey K. Pullumargued in 2007 that they were generally so inaccurate as to do more harm than good: "for the most part, accepting the advice of a computer grammar checker on your prose will make itmuchworse, sometimes hilariously incoherent."[9]	https://en.wikipedia.org/wiki/Grammar_checker
Aninverse parser, as its name suggests, is aparserthat works in reverse. Rather than the user typing into the computer, the computer presents a list of words fitting the context, and excludes words that would be unreasonable. This ensures the user knows all of their options. The concept and an implementation were originally developed andpatentedbyTexas Instruments. A few years later, it was independently developed byChris Crawford, a game designer, for his game,Trust & Betrayal: The Legacy of Siboot, but the implementation was different enough not to infringe on the patent. Thiscomputer sciencearticle is astub. You can help Wikipedia byexpanding it.	https://en.wikipedia.org/wiki/Inverse_parser
Incomputer science, anLALR parser[a](look-ahead, left-to-right, rightmost derivation parser) is part of the compiling process where human readable text is converted into a structured representation to be read by computers. An LALR parser is a software tool to process (parse) text into a very specific internal representation that other programs, such as compilers, can work with. This process happens according to a set ofproduction rulesspecified by aformal grammarfor acomputer language. An LALR parser is a simplified version of acanonical LR parser. The LALR parser was invented byFrank DeRemerin his 1969 PhD dissertation,Practical Translators for LR(k) languages,[1]in his treatment of the practical difficulties at that time of implementing LR(1) parsers. He showed that the LALR parser has more language recognition power than the LR(0) parser, while requiring the same number of states as the LR(0) parser for a language that can be recognized by both parsers. This makes the LALR parser a memory-efficient alternative to the LR(1) parser for languages that are LALR. It was also proven that there exist LR(1) languages that are not LALR. Despite this weakness, the power of the LALR parser is sufficient for many mainstream computer languages,[2]includingJava,[3]though the reference grammars for many languages fail to be LALR due to beingambiguous.[2] The original dissertation gave no algorithm for constructing such a parser given a formal grammar. The first algorithms for LALR parser generation were published in 1973.[4]In 1982, DeRemer and Tom Pennello published an algorithm that generated highly memory-efficient LALR parsers.[5]LALR parsers can be automatically generated from a grammar by anLALR parser generatorsuch asYaccorGNU Bison. The automatically generated code may be augmented by hand-written code to augment the power of the resulting parser. In 1965,Donald Knuthinvented theLR parser(Left to Right,Rightmost derivation). The LR parser can recognize anydeterministic context-free languagein linear-bounded time.[6]Rightmost derivation has very large memory requirements and implementing an LR parser was impractical due to the limitedmemoryof computers at that time. To address this shortcoming, in 1969, Frank DeRemer proposed two simplified versions of the LR parser, namely theLook-Ahead LR(LALR)[1]and theSimple LR parser(SLR) that had much lower memory requirements at the cost of less language-recognition power, with the LALR parser being the most-powerful alternative.[1]In 1977, memory optimizations for the LR parser were invented[7]but still the LR parser was less memory-efficient than the simplified alternatives. In 1979, Frank DeRemer andTom Pennelloannounced a series of optimizations for the LALR parser that would further improve its memory efficiency.[8]Their work was published in 1982.[5] Generally, the LALR parser refers to the LALR(1) parser,[b]just as the LR parser generally refers to the LR(1) parser. The "(1)" denotes one-token lookahead, to resolve differences between rule patterns during parsing. Similarly, there is an LALR(2) parser with two-token lookahead, and LALR(k) parsers withk-token lookup, but these are rare in actual use. The LALR parser is based on the LR(0) parser, so it can also be denoted LALR(1) = LA(1)LR(0) (1 token of lookahead, LR(0)) or more generally LALR(k) = LA(k)LR(0) (k tokens of lookahead, LR(0)). There is in fact a two-parameter family of LA(k)LR(j) parsers for all combinations ofjandk, which can be derived from the LR(j+k) parser,[9]but these do not see practical use. As with other types of LR parsers, an LALR parser is quite efficient at finding the single correctbottom-up parsein a single left-to-right scan over the input stream, because it does not need to usebacktracking. Being a lookahead parser by definition, it always uses a lookahead, withLALR(1)being the most-common case. The LALR(1) parser is less powerful than the LR(1) parser, and more powerful than the SLR(1) parser, though they all use the sameproduction rules. The simplification that the LALR parser introduces consists in merging rules that have identicalkernel item sets, because during the LR(0) state-construction process the lookaheads are not known. This reduces the power of the parser because not knowing the lookahead symbols can confuse the parser as to which grammar rule to pick next, resulting inreduce/reduce conflicts. All conflicts that arise in applying a LALR(1) parser to an unambiguous LR(1) grammar are reduce/reduce conflicts. The SLR(1) parser performs further merging, which introduces additional conflicts. The standard example of an LR(1) grammar that cannot be parsed with the LALR(1) parser, exhibiting such a reduce/reduce conflict, is:[10][11] In the LALR table construction, two states will be merged into one state and later the lookaheads will be found to be ambiguous. The one state with lookaheads is: An LR(1) parser will create two different states (with non-conflicting lookaheads), neither of which is ambiguous. In an LALR parser this one state has conflicting actions (given lookahead c or d, reduce to E or F), a "reduce/reduce conflict"; the above grammar will be declared ambiguous by aLALR parser generatorand conflicts will be reported. To recover, this ambiguity is resolved by choosing E, because it occurs before F in the grammar. However, the resultant parser will not be able to recognize the valid input sequenceb e c, since the ambiguous sequencee cis reduced to(E → e) c, rather than the correct(F → e) c, butb E cis not in the grammar. The LALR(j) parsers are incomparable withLL(k) parsers: for anyjandkboth greater than 0, there are LALR(j) grammars that are notLL(k) grammarsand vice versa. In fact, it is undecidable whether a given LL(1) grammar is LALR(k) for anyk>0{\displaystyle k>0}.[2] Depending on the presence of empty derivations, a LL(1) grammar can be equal to a SLR(1) or a LALR(1) grammar. If the LL(1) grammar has no empty derivations it is SLR(1) and if all symbols with empty derivations have non-empty derivations it is LALR(1). If symbols having only an empty derivation exist, the grammar may or may not be LALR(1).[12]	https://en.wikipedia.org/wiki/LALR_parser
Incomputer science, aleft corner parseris a type ofchart parserused for parsingcontext-free grammars. It combines the top-down and bottom-up approaches of parsing. The name derives from the use of theleft cornerof the grammar's production rules. An early description of a left corner parser is "A Syntax-Oriented Translator" by Peter Zilahy Ingerman.[1][2] Thiscomputer sciencearticle is astub. You can help Wikipedia byexpanding it.	https://en.wikipedia.org/wiki/Left_corner_parser
Lexical tokenizationis conversion of a text into (semantically or syntactically) meaningfullexical tokensbelonging to categories defined by a "lexer" program. In case of a natural language, those categories include nouns, verbs, adjectives, punctuations etc. In case of a programming language, the categories includeidentifiers,operators,grouping symbols,data typesand language keywords. Lexical tokenization is related to the type of tokenization used inlarge language models(LLMs) but with two differences. First, lexical tokenization is usually based on alexical grammar, whereas LLM tokenizers are usuallyprobability-based. Second, LLM tokenizers perform a second step that converts the tokens into numerical values. A rule-based program, performing lexical tokenization, is calledtokenizer,[1]orscanner, althoughscanneris also a term for the first stage of a lexer. A lexer forms the first phase of acompiler frontendin processing. Analysis generally occurs in one pass. Lexers and parsers are most often used for compilers, but can be used for other computer language tools, such asprettyprintersorlinters. Lexing can be divided into two stages: thescanning, which segments the input string into syntactic units calledlexemesand categorizes these into token classes, and theevaluating, which converts lexemes into processed values. Lexers are generally quite simple, with most of the complexity deferred to thesyntactic analysisorsemantic analysisphases, and can often be generated by alexer generator, notablylexor derivatives. However, lexers can sometimes include some complexity, such asphrase structureprocessing to make input easier and simplify the parser, and may be written partly or fully by hand, either to support more features or for performance. What is called "lexeme" in rule-basednatural language processingis not equal to what is calledlexemein linguistics. What is called "lexeme" in rule-based natural language processing can be equal to the linguistic equivalent only inanalytic languages, such as English, but not in highlysynthetic languages, such asfusional languages. What is called a lexeme in rule-based natural language processing is more similar to what is called awordin linguistics (not to be confused with aword in computer architecture), although in some cases it may be more similar to amorpheme. Alexical tokenis astringwith an assigned and thus identified meaning, in contrast to the probabilistic token used inlarge language models. A lexical token consists of atoken nameand an optionaltoken value. The token name is a category of a rule-based lexical unit.[2] (Lexical category) Consider this expression in theCprogramming language: The lexical analysis of this expression yields the following sequence of tokens: A token name is what might be termed apart of speechin linguistics. Lexical tokenizationis the conversion of a raw text into (semantically or syntactically) meaningful lexical tokens, belonging to categories defined by a "lexer" program, such as identifiers, operators, grouping symbols, and data types. The resulting tokens are then passed on to some other form of processing. The process can be considered a sub-task ofparsinginput. For example, in the textstring: the string is not implicitly segmented on spaces, as anatural languagespeaker would do. The raw input, the 43 characters, must be explicitly split into the 9 tokens with a given space delimiter (i.e., matching the string" "orregular expression/\s{1}/). When a token class represents more than one possible lexeme, the lexer often saves enough information to reproduce the original lexeme, so that it can be used insemantic analysis. The parser typically retrieves this information from the lexer and stores it in theabstract syntax tree. This is necessary in order to avoid information loss in the case where numbers may also be valid identifiers. Tokens are identified based on the specific rules of the lexer. Some methods used to identify tokens includeregular expressions, specific sequences of characters termed aflag, specific separating characters calleddelimiters, and explicit definition by a dictionary. Special characters, including punctuation characters, are commonly used by lexers to identify tokens because of their natural use in written and programming languages. A lexical analyzer generally does nothing with combinations of tokens, a task left for aparser. For example, a typical lexical analyzer recognizes parentheses as tokens but does nothing to ensure that each "(" is matched with a ")". When a lexer feeds tokens to the parser, the representation used is typically anenumerated type, which is a list of number representations. For example, "Identifier" can be represented with 0, "Assignment operator" with 1, "Addition operator" with 2, etc. Tokens are often defined byregular expressions, which are understood by a lexical analyzer generator such aslex, or handcoded equivalentfinite-state automata. The lexical analyzer (generated automatically by a tool like lex or hand-crafted) reads in a stream of characters, identifies thelexemesin the stream, and categorizes them into tokens. This is termedtokenizing. If the lexer finds an invalid token, it will report an error. Following tokenizing isparsing. From there, the interpreted data may be loaded into data structures for general use, interpretation, orcompiling. The specification of aprogramming languageoften includes a set of rules, thelexical grammar, which defines the lexical syntax. The lexical syntax is usually aregular language, with the grammar rules consisting ofregular expressions; they define the set of possible character sequences (lexemes) of a token. A lexer recognizes strings, and for each kind of string found, the lexical program takes an action, most simply producing a token. Two important common lexical categories arewhite spaceandcomments. These are also defined in the grammar and processed by the lexer but may be discarded (not producing any tokens) and considerednon-significant, at most separating two tokens (as inif xinstead ofifx). There are two important exceptions to this. First, inoff-side rulelanguages that delimitblockswith indenting, initial whitespace is significant, as it determines block structure, and is generally handled at the lexer level; seephrase structure, below. Secondly, in some uses of lexers, comments and whitespace must be preserved – for examples, aprettyprinteralso needs to output the comments and some debugging tools may provide messages to the programmer showing the original source code. In the 1960s, notably forALGOL, whitespace and comments were eliminated as part of theline reconstructionphase (the initial phase of thecompiler frontend), but this separate phase has been eliminated and these are now handled by the lexer. The first stage, thescanner, is usually based on afinite-state machine(FSM). It has encoded within it information on the possible sequences of characters that can be contained within any of the tokens it handles (individual instances of these character sequences are termedlexemes). For example, anintegerlexeme may contain any sequence ofnumerical digitcharacters. In many cases, the first non-whitespace character can be used to deduce the kind of token that follows and subsequent input characters are then processed one at a time until reaching a character that is not in the set of characters acceptable for that token (this is termed themaximal munch, orlongest match, rule). In some languages, the lexeme creation rules are more complex and may involvebacktrackingover previously read characters. For example, in C, one 'L' character is not enough to distinguish between an identifier that begins with 'L' and a wide-character string literal. Alexeme, however, is only a string of characters known to be of a certain kind (e.g., a string literal, a sequence of letters). In order to construct a token, the lexical analyzer needs a second stage, theevaluator, which goes over the characters of the lexeme to produce avalue. The lexeme's type combined with its value is what properly constitutes a token, which can be given to a parser. Some tokens such as parentheses do not really have values, and so the evaluator function for these can return nothing: Only the type is needed. Similarly, sometimes evaluators can suppress a lexeme entirely, concealing it from the parser, which is useful for whitespace and comments. The evaluators for identifiers are usually simple (literally representing the identifier), but may include someunstropping. The evaluators forinteger literalsmay pass the string on (deferring evaluation to the semantic analysis phase), or may perform evaluation themselves, which can be involved for different bases or floating point numbers. For a simple quoted string literal, the evaluator needs to remove only the quotes, but the evaluator for anescaped string literalincorporates a lexer, which unescapes the escape sequences. For example, in the source code of a computer program, the string might be converted into the following lexical token stream; whitespace is suppressed and special characters have no value: Lexers may be written by hand. This is practical if the list of tokens is small, but lexers generated by automated tooling as part of acompiler-compilertoolchainare more practical for a larger number of potential tokens. These tools generally accept regular expressions that describe the tokens allowed in the input stream. Each regular expression is associated with aproduction rulein the lexical grammar of the programming language that evaluates the lexemes matching the regular expression. These tools may generate source code that can be compiled and executed or construct astate transition tablefor afinite-state machine(which is plugged into template code for compiling and executing). Regular expressions compactly represent patterns that the characters in lexemes might follow. For example, for anEnglish-based language, an IDENTIFIER token might be any English alphabetic character or an underscore, followed by any number of instances of ASCII alphanumeric characters and/or underscores. This could be represented compactly by the string[a-zA-Z_][a-zA-Z_0-9]*. This means "any character a-z, A-Z or _, followed by 0 or more of a-z, A-Z, _ or 0-9". Regular expressions and the finite-state machines they generate are not powerful enough to handle recursive patterns, such as "nopening parentheses, followed by a statement, followed bynclosing parentheses." They are unable to keep count, and verify thatnis the same on both sides, unless a finite set of permissible values exists forn. It takes a full parser to recognize such patterns in their full generality. A parser can push parentheses on a stack and then try to pop them off and see if the stack is empty at the end (see example[3]in theStructure and Interpretation of Computer Programsbook). Typically, lexical tokenization occurs at the word level. However, it is sometimes difficult to define what is meant by a "word". Often, a tokenizer relies on simple heuristics, for example: In languages that use inter-word spaces (such as most that use the Latin alphabet, and most programming languages), this approach is fairly straightforward. However, even here there are many edge cases such ascontractions,hyphenatedwords,emoticons, and larger constructs such asURIs(which for some purposes may count as single tokens). A classic example is "New York-based", which a naive tokenizer may break at the space even though the better break is (arguably) at the hyphen. Tokenization is particularly difficult for languages written inscriptio continua, which exhibit no word boundaries, such asAncient Greek,Chinese,[4]orThai.Agglutinative languages, such as Korean, also make tokenization tasks complicated. Some ways to address the more difficult problems include developing more complex heuristics, querying a table of common special cases, or fitting the tokens to alanguage modelthat identifies collocations in a later processing step. Lexers are often generated by alexer generator, analogous toparser generators, and such tools often come together. The most established islex, paired with theyaccparser generator, or rather some of their many reimplementations, likeflex(often paired withGNU Bison). These generators are a form ofdomain-specific language, taking in a lexical specification – generally regular expressions with some markup – and emitting a lexer. These tools yield very fast development, which is very important in early development, both to get a working lexer and because a language specification may change often. Further, they often provide advanced features, such as pre- and post-conditions which are hard to program by hand. However, an automatically generated lexer may lack flexibility, and thus may require some manual modification, or an all-manually written lexer. Lexer performance is a concern, and optimizing is worthwhile, more so in stable languages where the lexer runs very often (such as C or HTML). lex/flex-generated lexers are reasonably fast, but improvements of two to three times are possible using more tuned generators. Hand-written lexers are sometimes used, but modern lexer generators produce faster lexers than most hand-coded ones. The lex/flex family of generators uses a table-driven approach which is much less efficient than the directly coded approach.[dubious–discuss]With the latter approach the generator produces an engine that directly jumps to follow-up states via goto statements. Tools likere2c[5]have proven to produce engines that are between two and three times faster than flex produced engines.[citation needed]It is in general difficult to hand-write analyzers that perform better than engines generated by these latter tools. Lexical analysis mainly segments the input stream of characters into tokens, simply grouping the characters into pieces and categorizing them. However, the lexing may be significantly more complex; most simply, lexers may omit tokens or insert added tokens. Omitting tokens, notably whitespace and comments, is very common when these are not needed by the compiler. Less commonly, added tokens may be inserted. This is done mainly to group tokens intostatements, or statements into blocks, to simplify the parser. Line continuationis a feature of some languages where a newline is normally a statement terminator. Most often, ending a line with a backslash (immediately followed by anewline) results in the line beingcontinued– the following line isjoinedto the prior line. This is generally done in the lexer: The backslash and newline are discarded, rather than the newline being tokenized. Examples includebash,[6]other shell scripts and Python.[7] Many languages use the semicolon as a statement terminator. Most often this is mandatory, but in some languages the semicolon is optional in many contexts. This is mainly done at the lexer level, where the lexer outputs a semicolon into the token stream, despite one not being present in the input character stream, and is termedsemicolon insertionorautomatic semicolon insertion. In these cases, semicolons are part of the formal phrase grammar of the language, but may not be found in input text, as they can be inserted by the lexer. Optional semicolons or other terminators or separators are also sometimes handled at the parser level, notably in the case oftrailing commasor semicolons. Semicolon insertion is a feature ofBCPLand its distant descendantGo,[8]though it is absent in B or C.[9]Semicolon insertion is present inJavaScript, though the rules are somewhat complex and much-criticized; to avoid bugs, some recommend always using semicolons, while others use initial semicolons, termeddefensive semicolons, at the start of potentially ambiguous statements. Semicolon insertion (in languages with semicolon-terminated statements) and line continuation (in languages with newline-terminated statements) can be seen as complementary: Semicolon insertion adds a token even though newlines generally donotgenerate tokens, while line continuation prevents a token from being generated even though newlines generallydogenerate tokens. Theoff-side rule(blocks determined by indenting) can be implemented in the lexer, as inPython, where increasing the indenting results in the lexer emitting an INDENT token and decreasing the indenting results in the lexer emitting one or more DEDENT tokens.[10]These tokens correspond to the opening brace{and closing brace}in languages that use braces for blocks and means that the phrase grammar does not depend on whether braces or indenting are used. This requires that the lexer hold state, namely a stack of indent levels, and thus can detect changes in indenting when this changes, and thus the lexical grammar is notcontext-free: INDENT–DEDENT depend on the contextual information of prior indent levels. Generally lexical grammars are context-free, or almost so, and thus require no looking back or ahead, or backtracking, which allows a simple, clean, and efficient implementation. This also allows simple one-way communication from lexer to parser, without needing any information flowing back to the lexer. There are exceptions, however. Simple examples include semicolon insertion in Go, which requires looking back one token; concatenation of consecutive string literals in Python,[7]which requires holding one token in a buffer before emitting it (to see if the next token is another string literal); and the off-side rule in Python, which requires maintaining a count of indent level (indeed, a stack of each indent level). These examples all only require lexical context, and while they complicate a lexer somewhat, they are invisible to the parser and later phases. A more complex example isthe lexer hackin C, where the token class of a sequence of characters cannot be determined until the semantic analysis phase sincetypedefnames and variable names are lexically identical but constitute different token classes. Thus in the hack, the lexer calls the semantic analyzer (say, symbol table) and checks if the sequence requires a typedef name. In this case, information must flow back not from the parser only, but from the semantic analyzer back to the lexer, which complicates design.	https://en.wikipedia.org/wiki/Lexical_analysis
Incomputer science, anoperator-precedence parseris abottom-up parserthat interprets anoperator-precedence grammar. For example, mostcalculatorsuse operator-precedence parsers to convert from the human-readableinfix notationrelying onorder of operationsto a format that is optimized for evaluation such asReverse Polish notation(RPN). Edsger Dijkstra'sshunting yard algorithmis commonly used to implement operator-precedence parsers. An operator-precedence parser is a simpleshift-reduce parserthat is capable of parsing a subset ofLR(1)grammars. More precisely, the operator-precedence parser can parse all LR(1) grammars where two consecutivenonterminalsandepsilonnever appear in the right-hand side of any rule. Operator-precedence parsers are not used often in practice; however they do have some properties that make them useful within a larger design. First, they are simple enough to write by hand, which is not generally the case with more sophisticated right shift-reduce parsers. Second, they can be written to consult an operator table atrun time, which makes them suitable for languages that can add to or change their operators while parsing. (An example isHaskell, which allows user-defined infix operators with custom associativity and precedence; consequently, an operator-precedence parser must be run on the programafterparsing of all referenced modules.) Rakusandwiches an operator-precedence parser between tworecursive descent parsersin order to achieve a balance of speed and dynamism.GCC's C and C++ parsers, which are hand-coded recursive descent parsers, are both sped up by an operator-precedence parser that can quickly examine arithmetic expressions. Operator-precedence parsers are also embedded withincompiler-compiler-generated parsers to noticeably speed up the recursive descent approach to expression parsing.[1] The precedence climbing method is a compact, efficient, and flexible algorithm for parsing expressions that was first described by Martin Richards and Colin Whitby-Strevens.[2] An infix-notation expression grammar inEBNFformat will usually look like this: With many levels of precedence, implementing this grammar with a predictive recursive-descent parser can become inefficient. Parsing a number, for example, can require five function calls: one for each non-terminal in the grammar until reachingprimary. An operator-precedence parser can do the same more efficiently.[1]The idea is that we can left associate the arithmetic operations as long as we find operators with the same precedence, but we have to save a temporary result to evaluate higher precedence operators. The algorithm that is presented here does not need an explicit stack; instead, it uses recursive calls to implement the stack. The algorithm is not a pure operator-precedence parser like the Dijkstra shunting yard algorithm. It assumes that theprimarynonterminal is parsed in a separate subroutine, like in a recursive descent parser. The pseudocode for the algorithm is as follows. The parser starts at functionparse_expression. Precedence levels are greater than or equal to 0. Note that in the case of a production rule like this (where the operator can only appear once): the algorithm must be modified to accept only binary operators whose precedence is >min_precedence. An example execution on the expression 2 + 3 * 4 + 5 == 19 is as follows. We give precedence 0 to equality expressions, 1 to additive expressions, 2 to multiplicative expressions. parse_expression_1(lhs= 2,min_precedence= 0) 1 is returned. Another precedence parser known as Pratt parsing was first described byVaughan Prattin the 1973 paper "Top Down Operator Precedence",[3]based onrecursive descent. Though it predates precedence climbing, it can be viewed as a generalization of precedence climbing.[4] Pratt designed the parser originally to implement theCGOLprogramming language, and it was treated in much more depth in a Masters Thesis under his supervision.[5] Tutorials and implementations: There are other ways to apply operator precedence rules. One is to build a tree of the original expression and then apply tree rewrite rules to it. Such trees do not necessarily need to be implemented using data structures conventionally used for trees. Instead, tokens can be stored in flat structures, such as tables, by simultaneously building a priority list which states what elements to process in which order. Another approach is to first fully parenthesize the expression, inserting a number of parentheses around each operator, such that they lead to the correct precedence even when parsed with a linear, left-to-right parser. This algorithm was used in the earlyFORTRAN Icompiler:[7] The Fortran I compiler would expand each operator with a sequence of parentheses. In a simplified form of the algorithm, it would Although not obvious, the algorithm was correct, and, in the words ofKnuth, “The resulting formula is properly parenthesized, believe it or not.”[8] Example code of a simple C application that handles parenthesisation of basic math operators (+,-,,/,^,(and)): First, you need to compile your program. Assuming your program is written in C and the source code is in a file named program.c, you would use the following command: The above command tells gcc to compile program.c and create an executable named program. Command to run the program with parameters, For example; a b + c ^ d / e it produces as output on the console. A limitation to this strategy is that unary operators must all have higher precedence than infix operators. The "negative" operator in the above code has a higher precedence than exponentiation. Running the program with this input produces this output which is probably not what is intended.	https://en.wikipedia.org/wiki/Pratt_parser
Aprogram transformationis any operation that takes acomputer programand generates another program. In many cases the transformed program is required to besemantically equivalentto the original, relative to a particularformal semanticsand in fewer cases the transformations result in programs that semantically differ from the original in predictable ways.[1] While the transformations can be performed manually, it is often more practical to use aprogram transformation systemthat applies specifications of the required transformations. Program transformations may be specified as automated procedures that modify compiler data structures (e.g.abstract syntax trees) representing the program text, or may be specified more conveniently using patterns or templates representing parameterized source code fragments. A practical requirement forsource codetransformation systems is that they be able to effectively process programs written in aprogramming language. This usually requires integration of a full front-end for the programming language of interest, including source codeparsing, building internal program representations of code structures, the meaning of program symbols, usefulstatic analyses, and regeneration of valid source code from transformed program representations. The problem of building and integrating adequate front ends for conventional languages (Java,C++,PHPetc.) may be of equal difficulty as building the program transformation system itself because of the complexity of such languages. To be widely useful, a transformation system must be able to handle many target programming languages, and must provide some means of specifying such front ends. A generalisation of semantic equivalence is the notion ofprogram refinement: one program is a refinement of another if it terminates on all the initial states for which the original program terminates, and for each such state it is guaranteed to terminate in a possible final state for the original program. In other words, a refinement of a program ismore definedandmore deterministicthan the original program. If two programs are refinements of each other, then the programs are equivalent.[clarification needed] Thiscomputer sciencearticle is astub. You can help Wikipedia byexpanding it. Thisprogramming-language-related article is astub. You can help Wikipedia byexpanding it.	https://en.wikipedia.org/wiki/Program_transformation
Shallow parsing(alsochunkingorlightparsing) is an analysis of asentencewhich first identifies constituent parts of sentences (nouns, verbs, adjectives, etc.) and then links them to higher order units that have discrete grammatical meanings (noungroups orphrases, verb groups, etc.). While the most elementary chunking algorithms simply link constituent parts on the basis of elementary search patterns (e.g., as specified byregular expressions), approaches that usemachine learning techniques(classifiers,topic modeling, etc.) can take contextual information into account and thus compose chunks in such a way that they better reflect the semantic relations between the basic constituents.[1]That is, these more advanced methods get around the problem that combinations of elementary constituents can have different higher level meanings depending on the context of the sentence. It is a technique widely used innatural language processing. It is similar to the concept oflexical analysisfor computer languages. Under the name "shallow structure hypothesis", it is also used as an explanation for whysecond languagelearners often fail to parse complex sentences correctly.[2] Thiscomputational linguistics-related article is astub. You can help Wikipedia byexpanding it.	https://en.wikipedia.org/wiki/Shallow_parsing
Sentence processingtakes place whenever a reader or listener processes a language utterance, either in isolation or in thecontextof a conversation or a text. Many studies of the human language comprehension process have focused on reading of single utterances (sentences) without context. Extensive research has shown that language comprehension is affected by context preceding a given utterance as well as many other factors. Sentence comprehension has to deal with ambiguity[1]in spoken and written utterances, for examplelexical,structural, andsemantic ambiguities. Ambiguity is ubiquitous, but people usually resolve it so effortlessly that they do not even notice it. For example, the sentenceTime flies like an arrowhas (at least) the interpretationsTime moves as quickly as an arrow,A special kind of fly, called time fly, likes arrowsandMeasure the speed of flies like you would measure the speed of an arrow. Usually, readers will be aware of only the first interpretation. Educated readers though, spontaneously think about thearrow of timebut inhibit that interpretation because it deviates from the original phrase and the temporal lobe acts as a switch. Instances of ambiguity can be classified aslocalorglobalambiguities. A sentence is globally ambiguous if it has two distinct interpretations. Examples are sentences likeSomeone shot the servant of the actress who was on the balcony(was it the servant or the actress who was on the balcony?) orThe cop chased the criminal with a fast car(did the cop or the criminal have a fast car?). Comprehenders may have a preferential interpretation for either of these cases, but syntactically and semantically, neither of the possible interpretations can be ruled out. Local ambiguities persist only for a short amount of time as an utterance is heard or written and are resolved during the course of the utterance so the complete utterance has only one interpretation. Examples include sentences likeThe critic wrote the book was enlightening, which is ambiguous whenThe critic wrote the bookhas been encountered, butwas enlighteningremains to be processed. Then, the sentence could end, stating that the critic is the author of the book, or it could go on to clarify that the critic wrote something about a book. The ambiguity ends atwas enlightening, which determines that the second alternative is correct. When readers process a local ambiguity, they settle on one of the possible interpretations immediately without waiting to hear or read more words that might help decide which interpretation is correct (the behaviour is calledincremental processing). If readers are surprised by the turn the sentence really takes, processing is slowed and is visible for example in reading times. Locally-ambiguous sentences have, therefore, been used as test cases to investigate the influence of a number of different factors on human sentence processing. If a factor helps readers to avoid difficulty, it is clear that the factor plays a factor in sentence processing. Experimental research has spawned a large number of hypotheses about the architecture and mechanisms of sentence comprehension. Issues like modularity versus interactive processing and serial versus parallel computation of analyses have been theoretical divides in the field. A modular view of sentence processing assumes that each factor involved in sentence processing is computed in its own module, which has limited means of communication with the other modules. For example, syntactic analysis creation takes place without input from semantic analysis or context-dependent information, which are processed separately. A common assumption of modular accounts is afeed-forwardarchitecture in which the output of one processing step is passed on to the next step without feedback mechanisms that would allow the output of the first module to be corrected. Syntactic processing is usually taken to be the most basic analysis step, which feeds into semantic processing and the inclusion of other information. A separate mental module parses sentences and lexical access happens first. Then, one syntactic hypothesis is considered at a time. There is no initial influence of meaning, or semantic. Sentence processing is supported by a temporo-frontal network. Within the network, temporal regions subserve aspects of identification and frontal regions the building of syntactic and semantic relations. Temporal analyses of brain activation within this network support syntax-first models because they reveal that building of syntactic structure precedes semantic processes and that these interact only during a later stage.[2][3] Interactive accounts assume that all available information is processed at the same time and can immediately influence the computation of the final analysis. In the interactive model of sentence processing, there is no separate module for parsing. Lexical access, syntactic structure assignment, and meaning assignment happen at the same time in parallel. Several syntactic hypotheses can be considered at a time. The interactive model demonstrates an on-line interaction between the structural and lexical and phonetic levels of sentence processing. Each word, as it is heard in the context of normal discourse, is immediately entered into the processing system at all levels of description, and is simultaneously analyzed at all these levels in the light of whatever information is available at each level at that point in the processing of the sentence.[4]Interactive models of language processing assume that information flows both bottom-up and top-down, so that the representations formed at each level may be influenced by higher as well as lower levels. A framework called the interactive activation framework that embeds this key assumption among others, including the assumption that influences from different sources are combined nonlinearly. The nonlinearity means that information that may be decisive under some circumstances may have little or no effect under other conditions. In the interactive activation framework, the knowledge that guides processing is stored in the connections between units on the same and adjacent levels. The processing units that they connect may receive input from a number of different sources, which allows the knowledge that guides processing to be completely local while, at the same time, allowing the results of processing at one level to influence processing at other levels, both above and below. A basic assumption of the framework is that processing interactions are always reciprocal; it is this bi-directional characteristic that makes the system interactive. Bi-directional excitatory interactions between levels allow mutual simultaneous constraint among adjacent levels, and bi-directional inhibitory interactions within a level allow for competition among mutually incompatible interpretations of a portion of an input. The between-level excitatory interactions are captured in the models in two-way excitatory connections between mutually compatible processing units. Syntactic ambiguities are in fact based at the lexical level. In addition, more recent studies with more sensitive eye tracking machines have shown early context effects. Frequency and contextual information will modulate the activation of alternatives even when they are resolved in favor of the simple interpretation. Structural simplicity is cofounded with frequency, which goes against the garden path theory[5] Serial accounts assume that humans construct only one of the possible interpretations at first and try another only if the first one turns out to be wrong. Parallel accounts assume the construction of multiple interpretations at the same time. To explain why comprehenders are usually only aware of one possible analysis of what they hear, models can assume that all analyses ranked, and the highest-ranking one is entertained. There are a number of influential models of human sentence processing that draw on different combinations of architectural choices. The garden path model (Frazier 1987) is a serial modular parsing model. It proposes that a single parse is constructed by a syntactic module. Contextual and semantic factors influence processing at a later stage and can induce re-analysis of the syntactic parse. Re-analysis is costly and leads to an observable slowdown in reading. When the parser encounters an ambiguity, it is guided by two principles: late closure and minimal attachment. The model has been supported with research on theearly left anterior negativity, anevent-related potentialoften elicited as a response tophrase structure violations. Late closurecauses new words or phrases to be attached to the current clause. For example, "John said he would leave yesterday" would be parsed asJohn said (he would leave yesterday), and not asJohn said (he would leave) yesterday(i.e., he spoke yesterday). Minimal attachmentis a strategy of parsimony: The parser builds the simplest syntactic structure possible (that is, the one with the fewest phrasal nodes). Constraint-based theories of language comprehension[6]emphasize how people make use of the vast amount of probabilistic information available in the linguistic signal. Throughstatistical learning,[7]the frequencies and distribution of events in linguistic environments can be picked upon, which inform language comprehension. As such, language users are said to arrive at a particular interpretation over another during the comprehension of an ambiguous sentence by rapidly integrating these probabilistic constraints. The good enough approach to language comprehension, developed byFernanda Ferreiraand others, assumes that listeners do not always engage in full detailed processing of linguistic input. Rather, the system has a tendency to develop shallow and superficial representations when confronted with some difficulty. The theory takes an approach that somewhat combines both the garden path model and the constraint based model. The theory focuses on two main issues. The first is that representations formed from complex or difficult material are often shallow and incomplete. The second is that limited information sources are often consulted in cases where the comprehension system encounters difficulty. The theory can be put to test using various experiments in psycholinguistics that involve garden path misinterpretation, etc.[8][9] In behavioral studies, subjects are often presented with linguistic stimuli and asked to perform an action. For example, they may be asked to make a judgment about a word (lexical decision), reproduce the stimulus, or name a visually presented word aloud. Speed (often reaction time: time taken to respond to the stimulus) and accuracy (proportion of correct responses) are commonly employed measures of performance in behavioral tasks. Researchers infer that the nature of the underlying process(es) required by the task gives rise to differences; slower rates and lower accuracy on these tasks are taken as measures of increased difficulty. An important component of any behavioral task is that it stays relatively true to 'normal' language comprehension—the ability to generalize the results of any task is restricted when the task has little in common with how people actually encounter language. A common behavioral paradigm involvespriming effects, wherein participants are presented first with a prime and then with a target word. The response time for the target word is affected by the relationship between the prime and the target. For example, Fischler (1977) investigated word encoding using the lexical decision task. She asked participants to make decisions about whether two strings of letters were English words. Sometimes the strings would be actual English words requiring a "yes" response, and other times they would be nonwords requiring a "no" response. A subset of the licit words were related semantically (e.g., cat-dog) while others were unrelated (e.g., bread-stem). Fischler found that related word pairs were responded to faster when compared to unrelated word pairs, which suggests that semantic relatedness can facilitate word encoding.[10] Eye trackinghas been used to study online language processing. This method has been influential in informing knowledge of reading.[11]Additionally, Tanenhaus et al. (1995)[12]established the visual world paradigm, which takes advantage of eye movements to study online spoken language processing. This area of research capitalizes on the linking hypothesis that eye movements are closely linked to the current focus of attention. The rise of non-invasive techniques provides myriad opportunities for examining the brain bases of language comprehension. Common examples includepositron emission tomography(PET),functional magnetic resonance imaging(fMRI),event-related potentials(ERPs) inelectroencephalography(EEG) andmagnetoencephalography(MEG), andtranscranial magnetic stimulation(TMS). These techniques vary in their spatial and temporal resolutions (fMRI has a resolution of a few thousand neurons per pixel, and ERP has millisecond accuracy), and each type of methodology presents a set of advantages and disadvantages for studying a particular problem in language comprehension. Computational modeling is another means by which to explore language comprehension. Models, such as those instantiated inneural networks, are particularly useful because they requires theorists to be explicit in their hypotheses and because they can be used to generate accurate predictions for theoretical models that are so complex that they renderdiscursive analysisunreliable. A classic example of computational modeling in language research isMcClellandandElman'sTRACEmodel of speech perception.[13]A model of sentence processing can be found in Hale (2011)'s 'rational' Generalized Left Corner parser.[14]This model derives garden path effects as well as local coherence phenomena. Computational modeling can also help to relate sentence processing to other functions of language. For example, one model of ERP effects in sentence processing (e.g., N400 and P600) argues that these phenomena arise out learning processes that support language acquisition and linguistic adaptation.[15]	https://en.wikipedia.org/wiki/Sentence_processing
Incomputer science,automatic programming[1]is a type ofcomputer programmingin which some mechanism generates acomputer program, to allow humanprogrammersto write the code at a higher abstraction level. There has been little agreement on the precise definition of automatic programming, mostly because its meaning has changed over time.David Parnas, tracing the history of "automatic programming" in published research, noted that in the 1940s it described automation of the manual process of punchingpaper tape. Later it referred to translation ofhigh-level programming languageslikeFortranandALGOL. In fact, one of the earliest programs identifiable as acompilerwas calledAutocode.Parnasconcluded that "automatic programming has always been aeuphemismfor programming in a higher-level language than was then available to the programmer."[2] Program synthesisis one type of automatic programming where a procedure is created from scratch, based on mathematical requirements. Mildred Koss, an earlyUNIVACprogrammer, explains: "Writing machine code involved several tedious steps—breaking down a process into discrete instructions, assigning specific memory locations to all the commands, and managing the I/O buffers. After following these steps to implement mathematical routines, a sub-routine library, and sorting programs, our task was to look at the larger programming process. We needed to understand how we might reuse tested code and have the machine help in programming. As we programmed, we examined the process and tried to think of ways to abstract these steps to incorporate them into higher-level language. This led to the development of interpreters, assemblers, compilers, and generators—programs designed to operate on or produce other programs, that is,automatic programming."[3] Generative programmingand the related termmeta-programming[4]are concepts whereby programs can be written "to manufacture software components in an automated way"[5]just as automation has improved "production of traditional commodities such as garments, automobiles, chemicals, and electronics."[6][7] The goal is to improveprogrammerproductivity.[8]It is often related to code-reuse topics such ascomponent-based software engineering. Source-code generationis the process of generating source code based on a description of the problem[9]or anontologicalmodel such as a template and is accomplished with aprogramming toolsuch as atemplate processoror anintegrated development environment(IDE). These tools allow the generation ofsource codethrough any of various means. Modern programming languages are well supported by tools likeJson4Swift(Swift) andJson2Kotlin(Kotlin). Programs that could generateCOBOLcode include: These application generators supported COBOL inserts and overrides. Amacroprocessor, such as theC preprocessor, which replaces patterns in source code according to relatively simple rules, is a simple form of source-code generator.Source-to-sourcecode generation tools also exist.[11][12] Large language modelssuch asChatGPTare capable of generating a program's source code from a description of the program given in a natural language.[13] Manyrelational database systemsprovide a function that will export the content of the database asSQLdata definitionqueries, which may then be executed to re-import the tables and their data, or migrate them to another RDBMS. Alow-code development platform(LCDP) is software that provides an environmentprogrammersuse to createapplication softwarethroughgraphical user interfacesand configuration instead of traditionalcomputer programming.	https://en.wikipedia.org/wiki/Source_code_generation
Amorphomeis a function in linguistics which is purelymorphologicalor has an irreducibly morphological component. The term is particularly used byMartin Maiden[1]followingMark Aronoff's identification of morphomic functions and the morphomic level—a level of linguistic structure intermediate between and independent ofphonologyandsyntax. In distinguishing this additional level, Aronoff makes the empirical claim that all mappings from the morphosyntactic level to the level of phonological realisation pass through the intermediate morphomic level.[2] Functions defined at the morphomic level are of many qualitatively different types. One example is the different ways theperfect participlecan be realised in English––sometimes, this form is created throughsuffixation, as inbittenandpacked, sometimes through a process ofablaut, as insung, and sometimes through a combination of these, such asbroken, which uses ablaut as well as the suffix-n.[2] Another is the division oflexemesinto distinct inflectional classes. Inflectional classes present distinct morphological forms, but these distinctions bear no meaning beyond signalling inflectional patterns; they are internal to morphology, and thus morphomic.[citation needed]Martin Maiden's theory of morphomes has been mostly developed with regard to the Romance languages,[3]where he identified many examples of morphomic stem distributions. A different typology of morphomic patterns has been put forth by Erich Round.[4]He distinguishes rhizomorphomes, which are a property of roots (corresponding to the traditional notion of inflectional class), metamorphomes, which are a property of paradigms, a set of cells which behave in a particular way (corresponding to the morphome in Maiden's terms, such as patterns of stem distribution), and meromorphomes, which are a property ofexponents, and have only been identified for now inKayardildand related languages.[citation needed] Thislinguistic morphologyarticle is astub. You can help Wikipedia byexpanding it.	https://en.wikipedia.org/wiki/Morphome_(linguistics)
Morphological typologyis awayof classifying the languages of the world that groups languages according to their commonmorphologicalstructures. The field organizes languages on the basis of how those languages formwordsby combiningmorphemes.Analyticlanguages contain very littleinflection, instead relying on features likeword orderand auxiliary words to convey meaning.Syntheticlanguages, ones that are not analytic, are divided into two categories:agglutinativeandfusionallanguages. Agglutinative languages rely primarily on discrete particles (prefixes,suffixes, andinfixes) for inflection, while fusional languages "fuse" inflectional categories together, often allowing one word ending to contain several categories, such that the original root can be difficult to extract. A further subcategory of agglutinative languages arepolysyntheticlanguages, which takeagglutinationto a higher level by constructing entire sentences, includingnouns, as one word. Analytic, fusional, and agglutinative languages can all be found in many regions of the world. However, each category is dominant in some families and regions and essentially nonexistent in others. Analytic languages encompass theSino-Tibetanfamily, includingChinese, many languages in Southeast Asia, the Pacific, and West Africa, and a few of theGermanic languages. Fusional languages encompass most of theIndo-Europeanfamily—for example,French,Russian, andHindi—as well as theSemiticfamily and a few members of theUralicfamily. Most of the world's languages, however, are agglutinative, including theTurkic,Japonic,Dravidian, andBantulanguages and most families in the Americas, Australia, the Caucasus, and non-SlavicRussia.Constructed languagestake a variety of morphological alignments. The concept of discrete morphological categories has been criticized. Some linguists argue that most, if not all, languages are in a permanent state of transition, normally from fusional to analytic to agglutinative to fusional again. Others take issue with the definitions of the categories, arguing that they conflate several distinct, if related, variables. The field was first developed by brothersFriedrich von SchlegelandAugust von Schlegel.[citation needed] Analytic languages show a low ratio ofmorphemestowords; in fact, the correspondence is nearly one-to-one. Sentences in analytic languages are composed of independent root morphemes. Grammatical relations between words are expressed by separate words where they might otherwise be expressed by affixes, which are present to a minimal degree in such languages. There is little to no morphological change in words: they tend to be uninflected. Grammatical categories are indicated by word order (for example, inversion of verb and subject for interrogative sentences) or by bringing in additional words (for example, a word for "some" or "many" instead of a pluralinflectionlike English-s). Individual words carry a general meaning (root concept); nuances are expressed by other words. Finally, in analytic languages context and syntax are more important thanmorphology. Analytic languages include some of the majorEast Asian languages, such asChinese, andVietnamese. Note that theideographic writingsystems of these languages play a strong role in regimenting linguistic continuity according to an analytic, or isolating, morphology (cf.orthography).[citation needed] Additionally,Englishis moderately analytic, and it andAfrikaanscan be considered as some of the most analytic of all Indo-European languages. However, they are traditionally analyzed asfusional languages. A related concept is theisolating language, one in which there is only one, or on average close to one,morphemeper word. Not all analytic languages are isolating; for example, Chinese and English possess manycompound words, but contain few inflections for them. Synthetic languages form words by affixing a given number of dependent morphemes to a root morpheme. The morphemes may be distinguishable from the root, or they may not. They may be fused with it or among themselves (in that multiple pieces of grammatical information may potentially be packed into one morpheme). Word order is less important for these languages than it is for analytic languages, since individual words express the grammatical relations that would otherwise be indicated by syntax. In addition, there tends to be a high degree ofconcordance(agreement, or cross-reference between different parts of the sentence). Therefore, morphology in synthetic languages is more important than syntax. MostIndo-European languagesare moderately synthetic. There are two subtypes of synthesis, according to whether morphemes are clearly differentiable or not. These subtypes areagglutinativeandfusional(orinflectionalorflectionalin older terminology). Morphemes in fusional languages are not readily distinguishable from the root or among themselves. Several grammatical bits of meaning may be fused into one affix. Morphemes may also be expressed by internal phonological changes in the root (i.e.morphophonology), such asconsonant gradationandvowel gradation, or bysuprasegmentalfeatures such asstressortone, which are of course inseparable from the root. TheIndo-EuropeanandSemiticlanguages are the most typically cited examples of fusional languages.[1]However, others have been described. For example,Navajois sometimes categorized as a fusional language because its complex system of verbal affixes has become condensed and irregular enough that discerning individual morphemes is rarely possible.[2][3]SomeUralic languagesare described as fusional, particularly theSami languagesandEstonian. On the other hand, not all Indo-European languages are fusional; for example, English andAfrikaans, as well as someNorth Germanic languageslean more toward the analytic. Agglutinative languages have words containing several morphemes that are always clearly differentiable from one another in that each morpheme represents only one grammatical meaning and the boundaries between those morphemes are easily demarcated; that is, the bound morphemes are affixes, and they may be individually identified. Agglutinative languages tend to have a high number of morphemes per word, and their morphology is usually highly regular, with a notable exception beingGeorgian, among others. Agglutinative languages includeHungarian,Tamil,Telugu,Kannada,Malayalam,Turkish,Saho,Mongolian,Korean,Japanese,Swahili,ZuluandIndonesian. In 1836,Wilhelm von Humboldtproposed a third category for classifying languages, a category that he labeledpolysynthetic. (The termpolysynthesiswas first used in linguistics byPeter Stephen DuPonceauwho borrowed it from chemistry.) These languages have a high morpheme-to-word ratio, a highly regular morphology, and a tendency for verb forms to include morphemes that refer to several arguments besides the subject (polypersonalism). Another feature of polysynthetic languages is commonly expressed as "the ability to form words that are equivalent to whole sentences in other languages". The distinction between synthetic languages and polysynthetic languages is therefore relative: the place of one language largely depends on its relation to other languages displaying similar characteristics on the same scale. Many Amerindian languages are polysynthetic; indeed, most of the world's polysynthetic languages are native to North America.[4]Inuktitutis one example, for instance the word-phrase:tavvakiqutiqarpiitroughly translates to "Do you have any tobacco for sale?".[citation needed]However, it is a common misconception that polysynthetic morphology is universal among Amerindian languages.ChinookandShoshone, for instance, are simply agglutinative, as their nouns stand mostly separate from their verbs.[1] Oligosynthetic languages are ones in which very few morphemes, perhaps only a few hundred, combine as in polysynthetic languages.Benjamin WhorfcategorizedNahuatlandBlackfootas oligosynthetic, but most linguists disagree with this classification and instead label them polysynthetic or simply agglutinative. No known languages are widely accepted as oligosynthetic.[citation needed] Constructed languages(conlangs) take a variety of morphological alignments. Despite theIndo-Europeanfamily's typical fusional alignment, mostuniversal auxiliary languagesbased on the family have ended up being agglutinative morphologically because agglutination is more transparent than fusion and thus furthers various goals of the language creators. This pattern began withVolapük, which is strongly agglutinative, and was continued withEsperanto, which tends to be agglutinative as well.[5]Other languages inspired by Esperanto likeIdoandNovialalso tend to be agglutinative, although some examples likeInterlinguamight be considered more fusional.Zonal constructed languagessuch asInterslavictend to follow the language families they are based on. Fictional languagesvary amongJ. R. R. Tolkien's languages for theMiddle earthuniverse, for example,Sindarinis fusional whileQuenyais agglutinative.[6]Amongengineered languages,Toki Ponais completely analytic, as it contains only a limited set of words with no inflections or compounds.Lojbanis analytic to the extent that everygismu(basic word, not counting particles) involves pre-determined syntactical roles for everygismucoming after it in a clause, though it does involve agglutination of roots when formingcalques.[7]Ithkuil, on the other hand, contains both agglutination in its addition of affixes and extreme fusion in that these affixes often result from the fusion of numerous morphemes viaablaut.[8] While the above scheme of analytic, fusional, and agglutinative languages dominated linguistics for many years—at least since the 1920s—it has fallen out of favor more recently. A common objection has been that most languages display features of all three types, if not in equal measure, some of them contending that a fully fusional language would be completelysuppletive. Jennifer Garland of theUniversity of California, Santa BarbaragivesSinhalaas an example of a language that demonstrates the flaws in the traditional scheme: she argues that while its affixes,clitics, andpostpositionswould normally be considered markers of agglutination, they are too closely intertwined to the root, yet classifying the language as primarily fusional, as it usually is, is also unsatisfying.[9] R. M. W. Dixon(1998) theorizes that languages normally evolve in a cycle fromfusionaltoanalytictoagglutinativeto fusional again. He analogizes this cycle to a clock, placing fusional languages at 12:00, analytic languages at 4:00, and agglutinative languages at 8:00. Dixon suggests that, for example,Old Chinesewas at about 3:00 (mostly analytic with some fusional elements), while modern varieties are around 5:00 (leaning instead toward agglutination), and also guesses thatProto-Tai-Kadaimay have been fusional. On the other hand, he argues that modernFinno-UgricandDravidianlanguages are on the transition from agglutinative to fusional, with the Finno-Ugric family being further along. Dixon cites theEgyptian languageas one that has undergone the entire cycle in three thousand years.[10] Other linguists have proposed similar concepts. For instance,Elly van Gelderensees the regular patterns of linguistic change as a cycle. In the unidirectional cycles, older features are replaced by newer items. One example isgrammaticalization, where a lexical item became a grammatical marker. The markers may further grammaticalize, and a new marker may come in place to substitute the loss of meaning of the previous marker.[11][12] TheWorld Atlas of Language Structures(WALS) sees the categorization of languages as strictly analytic, agglutinative, or fusional as misleading, arguing that these categories conflate multiple variables. WALS lists these variables as: These categories allow to capture non-traditional distributions of typological traits. For example, high exponence for nouns (e.g., case + number) is typically thought of as a trait of fusional languages. However, it is absent in many traditionally fusional languages likeArabicbut present in many traditionally agglutinative languages likeFinnish,Yaqui, andCree.[14]	https://en.wikipedia.org/wiki/Morphological_richness
Grammaticalization(also known asgrammatizationorgrammaticization) is alinguisticprocess in which words change from representing objects or actions to servinggrammaticalfunctions. Grammaticalization can involvecontent words, such asnounsandverbs, developing into newfunction wordsthat express grammatical relationships among other words in a sentence. This may happen rather than speakers deriving such new function words from (for example) existingbound,inflectionalconstructions. For example, theOld Englishverbwillan'to want', 'to wish' has become theModern Englishauxiliary verbwill, which expresses intention or simplyfuturity. Some concepts are often grammaticalized; others, such asevidentiality, less frequently.[1] In explaining this process, linguistics distinguishes between two types of linguistic items: Some linguists define grammaticalization in terms of the change whereby lexical items and constructions come in certain linguistic contexts to serve grammatical functions, and how grammatical items develop new grammatical functions.[2]Where grammaticalization takes place, nouns and verbs which carry certain lexical meaning develop over time into grammatical items such asauxiliaries,case markers, inflections, andsentence connectives. A well-known example of grammaticalization is that of the process in which the lexical clusterlet us, for example in "let us eat", is reduced tolet'sas in "let's you and me fight". Here, the phrase has lost its lexical meaning of "allow us" and has become an auxiliary introducing a suggestion, the pronoun 'us' reduced first to a suffix and then to an unanalyzedphoneme. In other areas of linguistics, the termgrammaticalizationhas taken on a much broader meaning. These other senses of the term are discussedbelow. The concept was developed in the works ofBopp(1816), Schlegel (1818),Humboldt(1825) andGabelentz(1891). Humboldt, for instance, came up with the idea of evolutionary language. He suggested that in all languages grammatical structures evolved out of a language stage in which there were only words for concrete objects and ideas. In order to successfully communicate these ideas, grammatical structures slowly came into existence. Grammar slowly developed through four different stages, each in which the grammatical structure would be more developed. Thoughneo-grammarianslikeBrugmannrejected the separation of language into distinct "stages" in favour ofuniformitarianassumptions,[3]they were positively inclined towards some of these earlier linguists' hypotheses.[4] The term "grammaticalization" in the modern sense was coined by the French linguistAntoine Meilletin hisL'évolution des formes grammaticales(1912). Meillet's definition was "the attribution of a grammatical nature to a formerly autonomous word".[5]Meillet showed that what was at issue was not the origins of grammatical forms but their transformations. He was thus able to present a notion of the creation of grammatical forms as a legitimate study for linguistics. Later studies in the field have further developed and altered Meillet's ideas and have introduced many other examples of grammaticalization. During the second half of the twentieth century, the field oflinguisticswas strongly concerned withsynchronicstudies of language change, with less emphasis on historical approaches such as grammaticalization. It did however, mostly inIndo-European studies, remain an instrument for explaining language change. It was not until the 1970s, with the growth of interest indiscourse analysisandlinguistic universals, that the interest for grammaticalization in linguistic studies began to grow again. A greatly influential work in the domain wasChristian Lehmann[de]'sThoughts on Grammaticalization(1982). This was the first work to emphasize the continuity of research from the earliest period to the present, and it provided a survey of the major work in the field. Lehmann also invented a set of 'parameters', a method along whichgrammaticalitycould be measured both synchronically and diachronically.[6] Another important work wasHeineandReh[de]'sGrammaticalization and Reanalysis in African Languages(1984). This work focussed onAfrican languagessynchronically from the point of view of grammaticalization. They saw grammaticalization as an important tool for describing the workings of languages and their universal aspects and it provided an exhaustive list of the pathways of grammaticalization. The great number of studies on grammaticalization in the last decade (up to 2018) show grammaticalization remains a popular item and is regarded as an important field within linguistic studies in general. Among recent publications there is a wide range ofdescriptivestudies trying to come up with umbrella definitions and exhaustive lists, while others tend to focus more on its nature and significance, questioning the opportunities and boundaries of grammaticalization. An important and popular topic which is still debated is the question of unidirectionality. It is difficult to capture the term "grammaticalization" in one clear definition (see the 'various views on grammaticalization' section below). However, there are some processes that are often linked to grammaticalization. These are semantic bleaching, morphological reduction, phonetic erosion, and obligatorification. Semantic bleaching, or desemanticization, has been seen from early on as a characteristic of grammaticalization. It can be described as the loss of semantic content. More specifically, with reference to grammaticalization, bleaching refers to the loss of all (or most) lexical content of an entity while only its grammatical content is retained.[7]For example,James Matisoffdescribed bleaching as "the partial effacement of a morpheme's semantic features, the stripping away of some of its precise content so it can be used in an abstracter, grammatical-hardware-like way".[8]John Haimanwrote that "semantic reduction, or bleaching, occurs as a morpheme loses its intention: From describing a narrow set of ideas, it comes to describe an ever broader range of them, and eventually may lose its meaning altogether".[9]He saw this as one of the two kinds of change that are always associated with grammaticalization (the other being phonetic reduction). For example, both English suffixes-ly(as inbodilyandangrily), and-like(as incatlikeoryellow-like) ultimately come from an earlier Proto-Germanic etymon,līką, which meantbodyorcorpse. There is no salient trace of that original meaning in the present suffixes for the native speaker, but speakers instead treat the more newly-formed suffixes as bits of grammar that help them form new words. One could make the connection between the body or shape of a physical being and the abstract property of likeness or similarity, but only through metonymic reasoning, after one is explicitly made aware of this connection. Once alinguisticexpression has changed from alexicalto agrammaticalmeaning (bleaching), it is likely to losemorphologicalandsyntacticelements that were characteristic of its initial category, but which are not relevant to thegrammatical function.[10]This is calleddecategorialization,ormorphological reduction. For example, thedemonstrative'that' as in "that book" came to be used as arelative clausemarker, and lost the grammatical category ofnumber('that' singular vs. 'those' plural), as in "the book that I know" versus "the things that I know". Phonetic erosion (also called phonological attrition or phonological reduction), is another process that is often linked to grammaticalization. It implies that a linguistic expression losesphoneticsubstance when it has undergone grammaticalization. Heine writes that "once alexemeis conventionalized as agrammatical marker, it tends to undergo erosion; that is, thephonologicalsubstance is likely to be reduced in some way and to become more dependent on surroundingphoneticmaterial".[11] Bernd HeineandTania Kutevahave described different kinds of phonetic erosion for applicable cases: 'Going to' → 'gonna' (or even 'I am going to' → 'I'm gonna' → 'I'mma') and 'because' → 'coz' are examples of erosion in English. Some linguists trace erosion to the speaker's tendency to follow theprinciple of least effort, while others think that erosion is a sign of changes taking place. However, phonetic erosion, a common process of language change that can take place with no connection to grammaticalization, is not a necessary property of grammaticalization.[12]For example, the Latin construction of the typeclarā mente, meaning 'with a clear mind' is the source of modern Romance productive adverb formation, as inItalianchiaramente, andSpanishclaramente'clearly'. In both of those languages, -mentein this usage is interpretable by today's native speakers only as a morpheme signaling 'adverb' and it has undergone no phonological erosion from the Latin source,mente. This example also illustrates thatsemantic bleachingof a form in its grammaticalized morphemic role does not necessarily imply bleaching of its lexical source, and that the two can separate neatly in spite of maintaining identical phonological form: the nounmenteis alive and well today in both Italian and Spanish with its meaning 'mind', yet native speakers do not recognize the noun 'mind' in the suffix-mente. The phonetic erosion may bring a brand-new look to the phonological system of a language, by changing the inventory of phones and phonemes, making new arrangements in the phonotactic patterns of a syllable, etc. Special treatise on the phonological consequences of grammaticalization andlexicalizationin the Chinese languages can be found inWei-Heng Chen(2011), which provides evidence that a morphophonological change can later change into a purely phonological change, and evidence that there is a typological difference in the phonetic and phonological consequences of grammaticalization betweenmonosyllabic languages(featuring an obligatory match betweensyllableandmorpheme, with exceptions of either loanwords or derivations likereduplicativesordiminutives, other morphological alternations) vs non-monosyllabic languages (includingdisyllabicor bisyllabic Austronesian languages,Afro-Asiatic languagesfeaturing atri-consonantalword root,Indo-European languageswithout a 100% obligatory match between such a sound unit as syllable and such a meaning unit as morpheme or word, despite an assumed majority of monosyllabic reconstructed word stems/roots in theProto-Indo-Europeanhypothesis), a difference mostly initiated by the German linguistW. Humboldt, puttingSino-Tibetan languagesin a sharp contrast to the other languages in the world in typology. Obligatorification occurs when the use of linguistic structures becomes increasingly more obligatory in the process of grammaticalization.[13]Lehmann describes it as a reduction in transparadigmatic variability, by which he means that "the freedom of the language user with regard to the paradigm as a whole" is reduced.[14]Examples of obligatoriness can be found in the category of number, which can be obligatory in some languages or in specific contexts, in the development of articles, and in the development ofpersonal pronounsof some languages. Some linguists, like Heine and Kuteva, stress the fact that even though obligatorification can be seen as an important process, it is not necessary for grammaticalization to take place, and it also occurs in other types of language change.[15] Although these 'parameters of grammaticalization' are often linked to the theory, linguists such asBybeeet al. (1994) have acknowledged that independently, they are not essential to grammaticalization. In addition, most are not limited to grammaticalization but can be applied in the wider context of language change. Critics of the theory of grammaticalization have used these difficulties to claim that grammaticalization has no independent status of its own, that all processes involved can be described separately from the theory of grammaticalization. Janda, for example, wrote that "given that even writers on grammaticalization themselves freely acknowledge the involvement of several distinct processes in the larger set of phenomena, it is hard to avoid the conclusion that the notion of grammaticalization, too, tends to represent an epiphenomenal telescoping. That is, it may involve certain typical "path(way)s", but the latter seem to be built out of separate stepping-stones which can often be seen in isolation and whose individual outlines are always distinctly recognizable".[16] In the process of grammaticalization, an uninflected lexical word (or content word) is transformed into a grammar word (orfunction word). The process by which the word leaves itsword classand enters another is not sudden, but occurs by a gradual series of individual shifts. The overlapping stages of grammaticalization form a chain, generally called acline. These shifts generally follow similar patterns in different languages.[17]Linguists do not agree on the precise definition of a cline or on its exact characteristics in given instances. It is believed that the stages on the cline do not always have a fixed position, but vary. However, Hopper andTraugott's famous pattern for the cline of grammaticalization illustrates the various stages of the form: This particular cline is called "the cline of grammaticality"[18]or the "cycle of categorial downgrading",[19]and it is a common one. In this cline every item to the right represents a moregrammaticaland lesslexicalform than the one to its left. It is very common for full verbs to becomeauxiliariesand eventually inflexional endings. An example of this phenomenon can be seen in the change from theOld English(OE)verbwillan('to want/to wish') to an auxiliary verb signifying intention inMiddle English(ME). InPresent-Day English(PDE), this form is even shortened to 'll and no longer necessarily implies intention, but often is simply a mark of future tense (seeshall and will). The PDE verb 'will' can thus be said to have less lexical meaning than its preceding form in OE.[20] The final stage of grammaticalization has happened in many languages. For example, inSerbo-Croatian, theOld Church Slavonicverbxъtěti("to want/to wish") has gone from a content word (hoće hoditi"s/he wants to walk") to an auxiliary verb in phonetically reduced form (on/onaće hoditi"s/he will walk") to a clitic (hoditi će), and finally to a fused inflection (hodiće"s/he will walk"). Compare theGermanverbwollenwhich has partially undergone a similar path of grammaticalization, and note the simultaneous existence of the non-grammaticalized Modern English verbto will(e.g. "Hewilled himself to continue along the steep path.") orhotetiin Serbo-Croatian (Hoċu da hodim= I want that I walk). In Latin the original future tense forms (e.g.cantabo) were dropped when they became phonetically too close to the imperfect forms (cantabam). Instead, a phrase likecantare habeo(literally, 'I have got to sing') acquired the sense of futurity (cf. I have to sing). Finally it became the true future tense in almost all Romance languages and the auxiliary became a full-fledged inflection (cf.Spanishcantaré,cantarás,cantará,Frenchje chanterai,tu chanteras,il/elle chantera,Italiancanterò,canterai,canterà, 'I will sing', 'you will sing', 's/he will sing'). In some verbs the process went further and produced irregular forms—cf. Spanishharé(instead ofhaceré, 'I'll do') andtendré(notteneré, 'I'll have'; the loss ofefollowed by epenthesis ofdis especially common)—and even regular forms (in Italian, the change of theain the stemcantaretoeincanteròhas affected the whole class of conjugation type I verbs). An illustrative example of this cline is in the orthography of Japanesecompound verbs. Many Japanese words are formed by connecting two verbs, as in 'go and ask (listen)'(行って聞く,ittekiku), and in Japanese orthography lexical items are generally written withkanji(here行くand聞く), while grammatical items are written withhiragana(as in the connectingて). Compound verbs are thus generally written with a kanji for each constituent verb, but some suffixes have become grammaticalized, and are written in hiragana, such as 'try out, see'(〜みる,-miru), from 'see'(見る,miru), as in 'try eating (it) and see'(食べてみる,tabetemiru). InGrammaticalization(2003) Hopper andTraugottstate that the cline of grammaticalization has both diachronic and synchronic implications. Diachronically (i.e. looking at changes over time), clines represent a natural path along which forms or words change over time. However, synchronically (i.e. looking at a single point in time), clines can be seen as an arrangement of forms along imaginary lines, with at one end a 'fuller' or lexical form and at the other a more 'reduced' or grammatical form.[21]What Hopper and Traugott mean is that from a diachronic or historical point of view, changes of word forms is seen as a natural process, whereas synchronically, this process can be seen as inevitable instead of historical. The studying and documentation of recurrentclinesenable linguists to form general laws of grammaticalization and language change in general. It plays an important role in the reconstruction of older states of a language. Moreover, the documenting of changes can help to reveal the lines along which a language is likely to develop in the future. Theunidirectionality hypothesisis the idea that grammaticalization, the development oflexicalelements intogrammaticalones, or less grammatical into more grammatical, is the preferred direction of linguistic change and that a grammatical item is much less likely to move backwards rather than forwards on Hopper &Traugott's cline of grammaticalization.[22] In the words ofBernd Heine, "grammaticalization is a unidirectional process, that is, it leads from less grammatical to more grammatical forms and constructions".[23]That is one of the strongest claims about grammaticalization, and is often cited as one of its basic principles. In addition, unidirectionality refers to a general developmental orientation which all (or the large majority) of the cases of grammaticalization have in common, and which can be paraphrased in abstract, general terms, independent of any specific case.[24] The idea of unidirectionality is an important one when trying to predict language change through grammaticalization (and for making the claim that grammaticalization can be predicted).Lessaunotes that "unidirectionality in itself is a predictive assertion in that it selects the general type of possible development (it predicts the direction of any given incipient case)," and unidirectionality also rules out an entire range of development types that do not follow this principle, hereby limiting the amount of possible paths of development.[25] Although unidirectionality is a key element of grammaticalization, exceptions exist. Indeed, the possibility of counterexamples, coupled with their rarity, is given as evidence for the general operating principle of unidirectionality. According toLyle Campbell, however, advocates often minimize the counterexamples or redefine them as not being part of the grammaticalization cline.[26]He gives the example ofHopperandTraugott(1993), who treat some putative counterexamples as cases of lexicalization in which a grammatical form is incorporated into a lexical item but does not itself become a lexical item. An example is the phraseto up the ante,which incorporates the prepositionup(a function word) in a verb (a content word) but withoutupbecoming a verb outside of this lexical item. Since it is the entire phraseto up the antethat is the verb, Hopper and Traugott argue that the wordupitself cannot be said to have degrammaticalized, a view that is challenged to some extent by parallel usages such asto up the bid,to up the payment,to up the deductions,to up the medication, by the fact that in all casesthecan be replaced by a possessive (my, your, her, Bill's, etc.), and by further extensions still:he upped his game'he improved his performance'. Examples that are not confined to a specific lexical item are less common. One is the Englishgenitive-'s, which, inOld English, was a suffix but, in Modern English, is a clitic. As Jespersen (1894) put it, InModern English...(compared to OE) the -s is much more independent: it can be separated from its main word by an adverb such as else (somebody else's hat ), by a prepositional clause such as of England (the queen of England's power ), or even by a relative clause such as I saw yesterday (the man I saw yesterday's car)...the English genitive is in fact no longer a flexional form...historically attested facts show us in the most unequivocal way a development - not, indeed, from an originally self-existent word to a mere flexional ending, but the exactly opposite development of what was an inseparable part of a complicated flexional system to greater and greater emancipation and independence.[27] Traugott cites a counterexample from function to content word proposed byKate Burridge(1998): the development inPennsylvania Germanof the auxiliarywotteof the preterite subjunctivemodalwelle'would' (from 'wanted') into a full verb 'to wish, to desire'.[28] In comparison to various instances of grammaticalization, there are relatively few counterexamples to the unidirectionality hypothesis, and they often seem to require special circumstances to occur. One is found in the development ofIrish Gaelicwith the origin of the first-person-plural pronounmuid(a function word) from the inflectional suffix-mid(as intáimid'we are') because of a reanalysis based on the verb-pronoun order of the other persons of the verb.[29]Another well-known example is the degrammaticalization of theNorth Saamiabessive('without') case suffix -hagato the postpositionhaga'without' and further to a preposition and a free-standing adverb.[30]Moreover, the morphologically analogous derivational suffix -naga'stained with' (e.g.,gáffenaga'stained with coffee',oljonaga'stained with oil') – itself based on theessivecase marker -na– has degrammaticalized into an independent nounnaga'stain'.[31] Linguists have come up with different interpretation of the term 'grammaticalization', and there are many alternatives to the definition given in the introduction. The following will be a non-exhaustive list of authors who have written about the subject with their individual approaches to the nature of the term 'grammaticalization'. Since then, the study of grammaticalization has become broader, and linguists have extended the term into various directions. From Language Sciences Volume 23, March (2001):	https://en.wikipedia.org/wiki/Grammaticalization
Incomputing,multitaskingis theconcurrentexecution of multiple tasks (also known asprocesses) over a certain period of time. New tasks can interrupt already started ones before they finish, instead of waiting for them to end. As a result, a computer executes segments of multiple tasks in an interleaved manner, while the tasks share common processing resources such ascentral processing units(CPUs) andmain memory. Multitasking automatically interrupts the running program, saving its state (partial results, memory contents and computer register contents) and loading the saved state of another program and transferring control to it. This "context switch" may be initiated at fixed time intervals (pre-emptive multitasking), or the running program may be coded to signal to the supervisory software when it can be interrupted (cooperative multitasking). Multitasking does not requireparallel executionof multiple tasks at exactly the same time; instead, it allows more than one task to advance over a given period of time.[1]Even onmultiprocessorcomputers, multitasking allows many more tasks to be run than there are CPUs. Multitasking is a common feature of computer operating systems since at least the 1960s. It allows more efficient use of the computer hardware; when a program is waiting for some external event such as a user input or aninput/outputtransfer with a peripheral to complete, the central processor can still be used with another program. In atime-sharingsystem, multiple human operators use the same processor as if it was dedicated to their use, while behind the scenes the computer is serving many users by multitasking their individual programs. Inmultiprogrammingsystems, a task runs until it must wait for an external event or until the operating system'sschedulerforcibly swaps the running task out of the CPU.Real-timesystems such as those designed to control industrial robots, require timely processing; a single processor might be shared between calculations of machine movement, communications, and user interface.[2] Often multitasking operating systems include measures to change the priority of individual tasks, so that important jobs receive more processor time than those considered less significant. Depending on the operating system, a task might be as large as an entire application program, or might be made up of smallerthreadsthat carry out portions of the overall program. A processor intended for use with multitasking operating systems may include special hardware to securely support multiple tasks, such asmemory protection, andprotection ringsthat ensure the supervisory software cannot be damaged or subverted by user-mode program errors. The term "multitasking" has become an international term, as the same word is used in many other languages such as German, Italian, Dutch, Romanian, Czech, Danish and Norwegian. In the early days of computing,CPU timewas expensive, andperipheralswere very slow. When the computer ran a program that needed access to a peripheral, the central processing unit (CPU) would have to stop executing program instructions while the peripheral processed the data. This was usually very inefficient. Multiprogramming is a computing technique that enables multiple programs to be concurrently loaded and executed into a computer's memory, allowing the CPU to switch between them swiftly. This optimizes CPU utilization by keeping it engaged with the execution of tasks, particularly useful when one program is waiting for I/O operations to complete. TheBull Gamma 60, initially designed in 1957 and first released in 1960, was the first computer designed with multiprogramming in mind. Its architecture featured a central memory and a Program Distributor feeding up to twenty-five autonomous processing units with code and data, and allowing concurrent operation of multiple clusters. Another such computer was theLEO III, first released in 1961. Duringbatch processing, several different programs were loaded in the computer memory, and the first one began to run. When the first program reached an instruction waiting for a peripheral, the context of this program was stored away, and the second program in memory was given a chance to run. The process continued until all programs finished running.[3] Multiprogramming gives no guarantee that a program will run in a timely manner. Indeed, the first program may very well run for hours without needing access to a peripheral. As there were no users waiting at an interactive terminal, this was no problem: users handed in a deck of punched cards to an operator, and came back a few hours later for printed results. Multiprogramming greatly reduced wait times when multiple batches were being processed.[4][5] Early multitasking systems used applications that voluntarily ceded time to one another. This approach, which was eventually supported by many computeroperating systems, is known today as cooperative multitasking. Although it is now rarely used in larger systems except for specific applications such asCICSor theJES2subsystem, cooperative multitasking was once the only scheduling scheme employed byMicrosoft Windowsandclassic Mac OSto enable multiple applications to run simultaneously. Cooperative multitasking is still used today onRISC OSsystems.[6] As a cooperatively multitasked system relies on each process regularly giving up time to other processes on the system, one poorly designed program can consume all of the CPU time for itself, either by performing extensive calculations or bybusy waiting; both would cause the whole system tohang. In a server environment, this is a hazard that makes the entire environment unacceptably fragile. Preemptive multitasking allows the computer system to more reliably guarantee to each process a regular "slice" of operating time. It also allows the system to deal rapidly with important external events like incoming data, which might require the immediate attention of one or another process. Operating systems were developed to take advantage of these hardware capabilities and run multiple processes preemptively. Preemptive multitasking was implemented inthe PDP-6 MonitorandMulticsin 1964, inOS/360 MFTin 1967, and inUnixin 1969, and was available insome operating systemsfor computers as small as DEC's PDP-8; it is a core feature of allUnix-likeoperating systems, such asLinux,SolarisandBSDwith itsderivatives,[7]as well as modern versions of Windows. Possibly the earliest preemptive multitasking OS available to home users wasMicroware'sOS-9, available for computers based on theMotorola 6809such as theTRS-80 Color Computer 2,[8]with the operating system supplied by Tandy as an upgrade for disk-equipped systems.[9]Sinclair QDOSon theSinclair QLfollowed in 1984, but it was not a big success. Commodore'sAmigawas released the following year, offering a combination of multitasking and multimedia capabilities. Microsoft made preemptive multitasking a core feature of their flagship operating system in the early 1990s when developingWindows NT 3.1and thenWindows 95. In 1988 Apple offeredA/UXas aUNIX System V-based alternative to theClassic Mac OS. In 2001 Apple switched to theNeXTSTEP-influencedMac OS X. A similar model is used inWindows 9xand theWindows NT family, where native 32-bit applications are multitasked preemptively.[10]64-bit editions of Windows, both for thex86-64andItaniumarchitectures, no longer support legacy 16-bit applications, and thus provide preemptive multitasking for all supported applications. Another reason for multitasking was in the design ofreal-time computingsystems, where there are a number of possibly unrelated external activities needed to be controlled by a single processor system. In such systems a hierarchical interrupt system is coupled with process prioritization to ensure that key activities were given a greater share of availableprocess time.[11] Threadswere born from the idea that the most efficient way for cooperating processes to exchange data would be to share their entire memory space. Thus, threads are effectively processes that run in the same memory context and share other resources with theirparent processes, such as open files. Threads are described aslightweight processesbecause switching between threads does not involve changing the memory context.[12][13][14] While threads are scheduled preemptively, some operating systems provide a variant to threads, namedfibers, that are scheduled cooperatively. On operating systems that do not provide fibers, an application may implement its own fibers using repeated calls to worker functions. Fibers are even more lightweight than threads, and somewhat easier to program with, although they tend to lose some or all of the benefits of threads onmachines with multiple processors.[15] Some systems directly supportmultithreading in hardware. Essential to any multitasking system is to safely and effectively share access to system resources. Access to memory must be strictly managed to ensure that no process can inadvertently or deliberately read or write to memory locations outside the process's address space. This is done for the purpose of general system stability and data integrity, as well as data security. In general, memory access management is a responsibility of the operating system kernel, in combination with hardware mechanisms that provide supporting functionalities, such as amemory management unit(MMU). If a process attempts to access a memory location outside its memory space, the MMU denies the request and signals the kernel to take appropriate actions; this usually results in forcibly terminating the offending process. Depending on the software and kernel design and the specific error in question, the user may receive an access violation error message such as "segmentation fault". In a well designed and correctly implemented multitasking system, a given process can never directly access memory that belongs to another process. An exception to this rule is in the case of shared memory; for example, in theSystem Vinter-process communication mechanism the kernel allocates memory to be mutually shared by multiple processes. Such features are often used by database management software such as PostgreSQL. Inadequate memory protection mechanisms, either due to flaws in their design or poor implementations, allow for security vulnerabilities that may be potentially exploited by malicious software. Use of aswap fileor swap partition is a way for the operating system to provide more memory than is physically available by keeping portions of the primary memory insecondary storage. While multitasking and memory swapping are two completely unrelated techniques, they are very often used together, as swapping memory allows more tasks to be loaded at the same time. Typically, a multitasking system allows another process to run when the running process hits a point where it has to wait for some portion of memory to be reloaded from secondary storage.[16] Over the years, multitasking systems have been refined. Modern operating systems generally include detailed mechanisms for prioritizing processes, whilesymmetric multiprocessinghas introduced new complexities and capabilities.[17]	https://en.wikipedia.org/wiki/Computer_multitasking
Cooperative multitasking, also known asnon-preemptive multitasking, is acomputer multitaskingtechnique in which theoperating systemnever initiates acontext switchfrom a runningprocessto another process. Instead, in order to run multiple applications concurrently, processes voluntarilyyield controlperiodically or when idle or logicallyblocked. This type of multitasking is calledcooperativebecause all programs must cooperate for the scheduling scheme to work. In this scheme, theprocess schedulerof an operating system is known as acooperative schedulerwhose role is limited to starting the processes and letting them return control back to it voluntarily.[1][2] This is related to theasynchronous programmingapproach. Although it is rarely used as the primary scheduling mechanism in modern operating systems, it is widely used in memory-constrainedembedded systemsand also, in specific applications such asCICSor theJES2subsystem. Cooperative multitasking was the primary scheduling scheme for 16-bit applications employed byMicrosoft WindowsbeforeWindows 95andWindows NT, and by theclassic Mac OS.Windows 9xused non-preemptive multitaskingfor 16-bit legacy applications, and thePowerPCVersions of Mac OS X prior toLeopardused it forclassicapplications.[1]NetWare, which is a network-oriented operating system, used cooperative multitasking up to NetWare 6.5. Cooperative multitasking is still used onRISC OSsystems.[3] Cooperative multitasking is similar toasync/awaitin languages, such asJavaScriptorPython, that feature a single-threaded event-loop in their runtime. This contrasts with cooperative multitasking in that await cannot be invoked from a non-async function, but only an async function, which is a kind ofcoroutine.[4][5] Cooperative multitasking allows much simpler implementation of applications because their execution is never unexpectedly interrupted by the process scheduler; for example, variousfunctionsinside the application do not need to bereentrant.[2] As a cooperatively multitasked system relies on each process regularly giving up time to other processes on the system, one poorly designed program can consume all of the CPU time for itself, either by performing extensive calculations or bybusy waiting; both would cause the whole system tohang. In aserverenvironment, this is a hazard that is often considered to make the entire environment unacceptably fragile,[1]though, as noted above, cooperative multitasking has been used frequently in server environments including NetWare and CICS. In contrast,preemptivemultitasking interrupts applications and gives control to other processes outside the application's control. The potential for system hang can be alleviated by using awatchdog timer, often implemented in hardware; this typically invokes ahardware reset.	https://en.wikipedia.org/wiki/Cooperative_multitasking
Theactivity selection problemis acombinatorial optimizationproblem concerning the selection of non-conflictingactivitiesto perform within a giventime frame, given a set of activities each marked by a start time (si) and finish time (fi). The problem is to select the maximum number of activities that can be performed by a single person ormachine, assuming that a person can only work on a single activity at a time. Theactivity selection problemis also known as theInterval scheduling maximization problem (ISMP), which is a special type of the more generalInterval Schedulingproblem. A classic application of this problem is in scheduling a room for multiplecompetingevents, each having its own time requirements (start and end time), and many more arise within the framework ofoperations research. Assume there existnactivities with each of them being represented by a start timesiand finish timefi. Two activitiesiandjare said to be non-conflicting ifsi≥fjorsj≥fi. The activity selection problem consists in finding the maximal solution set (S) of non-conflicting activities, or more precisely there must exist nosolution setS' such that \|S'\| > \|S\| in the case that multiple maximal solutions have equal sizes. The activity selection problem is notable in that using agreedy algorithmto find a solution will always result in anoptimal solution. Apseudocodesketch of the iterative version of the algorithm and a proof of the optimality of its result are included below. Line 1:This algorithm is calledGreedy-Iterative-Activity-Selector, because it is first of all a greedy algorithm, and then it is iterative. There's also a recursive version of this greedy algorithm. Note that these arrays are indexed starting from 1 up to the length of the corresponding array. Line 3:Sorts inincreasing order of finish timesthe array of activitiesA{\displaystyle A}by using the finish times stored in the arrayf{\displaystyle f}. This operation can be done inO(n⋅log⁡n){\displaystyle O(n\cdot \log n)}time, using for example merge sort, heap sort, or quick sort algorithms. Line 4:Creates a setS{\displaystyle S}to store theselected activities, and initialises it with the activityA[1]{\displaystyle A[1]}that has the earliest finish time. Line 5:Creates a variablek{\displaystyle k}that keeps track of the index of the last selected activity. Line 9:Starts iterating from the second element of that arrayA{\displaystyle A}up to its last element. Lines 10,11:If thestart times[i]{\displaystyle s[i]}of theith{\displaystyle ith}activity (A[i]{\displaystyle A[i]}) is greater or equal to thefinish timef[k]{\displaystyle f[k]}of thelast selected activity(A[k]{\displaystyle A[k]}), thenA[i]{\displaystyle A[i]}is compatible to the selected activities in the setS{\displaystyle S}, and thus it can be added toS{\displaystyle S}. Line 12:The index of the last selected activity is updated to the just added activityA[i]{\displaystyle A[i]}. LetS={1,2,…,n}{\displaystyle S=\{1,2,\ldots ,n\}}be the set of activities ordered by finish time. Assume thatA⊆S{\displaystyle A\subseteq S}is an optimal solution, also ordered by finish time; and that the index of the first activity inAisk≠1{\displaystyle k\neq 1}, i.e., this optimal solutiondoes notstart with the greedy choice. We will show thatB=(A∖{k})∪{1}{\displaystyle B=(A\setminus \{k\})\cup \{1\}}, which begins with the greedy choice (activity 1), is another optimal solution. Sincef1≤fk{\displaystyle f_{1}\leq f_{k}}, and the activities in A aredisjointby definition, the activities in B are also disjoint. SinceBhas the same number of activities asA, that is,\|A\|=\|B\|{\displaystyle \|A\|=\|B\|},Bis also optimal. Once the greedy choice is made, the problem reduces to finding an optimal solution for the subproblem. IfAis an optimal solution to the original problemScontaining the greedy choice, thenA′=A∖{1}{\displaystyle A^{\prime }=A\setminus \{1\}}is an optimal solution to the activity-selection problemS′={i∈S:si≥f1}{\displaystyle S'=\{i\in S:s_{i}\geq f_{1}\}}. Why? If this were not the case, pick a solutionB′ toS′ with more activities thanA′ containing the greedy choice forS′. Then, adding 1 toB′ would yield a feasible solutionBtoSwith more activities thanA, contradicting the optimality. The generalized version of the activity selection problem involves selecting an optimal set of non-overlapping activities such that the total weight is maximized. Unlike the unweighted version, there is no greedy solution to the weighted activity selection problem. However, adynamic programmingsolution can readily be formed using the following approach:[1] Consider an optimal solution containing activityk. We now have non-overlapping activities on the left and right ofk. We can recursively find solutions for these two sets because of optimal sub-structure. As we don't knowk, we can try each of the activities. This approach leads to anO(n3){\displaystyle O(n^{3})}solution. This can be optimized further considering that for each set of activities in(i,j){\displaystyle (i,j)}, we can find the optimal solution if we had known the solution for(i,t){\displaystyle (i,t)}, wheretis the last non-overlapping interval withjin(i,j){\displaystyle (i,j)}. This yields anO(n2){\displaystyle O(n^{2})}solution. This can be further optimized considering the fact that we do not need to consider all ranges(i,j){\displaystyle (i,j)}but instead just(1,j){\displaystyle (1,j)}. The following algorithm thus yields anO(nlog⁡n){\displaystyle O(n\log n)}solution:	https://en.wikipedia.org/wiki/Activity_selection_problem
Incomputer scienceforOperating systems,aging(US English) orageingis aschedulingtechnique used to avoidstarvation.Fixed priority schedulingis a scheduling discipline, in whichtasksqueued for utilizing a system resource are assigned a priority each. A task with a high priority is allowed to access a specific system resource before a task with a lower priority is allowed to do the same. A disadvantage of this approach is that tasks assigned with a lower priority may be starved when a large number of high priority tasks are queued. Aging is used to gradually increase thepriorityof a task, based on its waiting time in theready queue. In priority-basedscheduling algorithms, a major problem is indefinite block, orstarvation. A process that is ready to run but waiting for the CPU can be considered blocked. A priority scheduling algorithm can leave some low-priority processes waiting indefinitely. A steady stream of higher-priority processes can prevent a low-priority process from ever getting the CPU.[1] Aging is used to ensure that jobs with lower priority will eventually complete their execution. This technique can be used to reducestarvationof low priority tasks.[2]There are many ways to implement aging, but all have the same principle that the priority of a process should increase as it waits in the ready queue. The increase in priority may or may not be equal to the waiting time of the process. Suppose a system with priority range of 0-511. In this system, 0 means highest priority. Consider a process with priority 127. If we increase its priority by 1 every 15 minutes, then in more than 32 hours the process will age to 0 priority and get executed. Thisoperating-system-related article is astub. You can help Wikipedia byexpanding it. ^ Silberschatz, Galvin, Gagne Operating System Principles, 6th ed., p.162	https://en.wikipedia.org/wiki/Aging_(scheduling)
Automated planning and scheduling, sometimes denoted as simplyAI planning,[1]is a branch ofartificial intelligencethat concerns the realization ofstrategiesor action sequences, typically for execution byintelligent agents,autonomous robotsandunmanned vehicles. Unlike classicalcontrolandclassificationproblems, the solutions are complex and must be discovered and optimized in multidimensional space. Planning is also related todecision theory. In known environments with available models, planning can be done offline. Solutions can be found and evaluated prior to execution. In dynamically unknown environments, thestrategyoften needs to be revised online. Models and policies must be adapted. Solutions usually resort to iterativetrial and errorprocesses commonly seen inartificial intelligence. These includedynamic programming,reinforcement learningandcombinatorial optimization. Languages used to describe planning and scheduling are often calledaction languages. Given a description of the possible initial states of the world, a description of the desired goals, and a description of a set of possible actions, the planning problem is to synthesize a plan that is guaranteed (when applied to any of the initial states) to generate a state which contains the desired goals (such a state is called a goal state). The difficulty of planning is dependent on the simplifying assumptions employed. Several classes of planning problems can be identified depending on the properties the problems have in several dimensions. The simplest possible planning problem, known as the Classical Planning Problem, is determined by: Since the initial state is known unambiguously, and all actions are deterministic, the state of the world after any sequence of actions can be accurately predicted, and the question of observability is irrelevant for classical planning. Further, plans can be defined as sequences of actions, because it is always known in advance which actions will be needed. With nondeterministic actions or other events outside the control of the agent, the possible executions form a tree, and plans have to determine the appropriate actions for every node of the tree. Discrete-timeMarkov decision processes(MDP) are planning problems with: When full observability is replaced by partial observability, planning corresponds to apartially observable Markov decision process(POMDP). If there are more than one agent, we havemulti-agent planning, which is closely related togame theory. In AI planning, planners typically input a domain model (a description of a set of possible actions which model the domain) as well as the specific problem to be solved specified by the initial state and goal, in contrast to those in which there is no input domain specified. Such planners are called "domain independent" to emphasize the fact that they can solve planning problems from a wide range of domains. Typical examples of domains are block-stacking, logistics, workflow management, and robot task planning. Hence a single domain-independent planner can be used to solve planning problems in all these various domains. On the other hand, a route planner is typical of a domain-specific planner. The most commonly used languages for representing planning domains and specific planning problems, such asSTRIPSandPDDLfor Classical Planning, are based on state variables. Each possible state of the world is an assignment of values to the state variables, and actions determine how the values of the state variables change when that action is taken. Since a set of state variables induce a state space that has a size that is exponential in the set, planning, similarly to many other computational problems, suffers from thecurse of dimensionalityand thecombinatorial explosion. An alternative language for describing planning problems is that ofhierarchical task networks, in which a set of tasks is given, and each task can be either realized by a primitive action or decomposed into a set of other tasks. This does not necessarily involve state variables, although in more realistic applications state variables simplify the description of task networks. Temporal planning can be solved with methods similar to classical planning. The main difference is, because of the possibility of several, temporally overlapping actions with a duration being taken concurrently, that the definition of a state has to include information about the current absolute time and how far the execution of each active action has proceeded. Further, in planning with rational or real time, the state space may be infinite, unlike in classical planning or planning with integer time. Temporal planning is closely related toschedulingproblems when uncertainty is involved and can also be understood in terms oftimed automata. The Simple Temporal Network with Uncertainty (STNU) is a scheduling problem which involves controllable actions, uncertain events and temporal constraints. Dynamic Controllability for such problems is a type of scheduling which requires a temporal planning strategy to activate controllable actions reactively as uncertain events are observed so that all constraints are guaranteed to be satisfied.[2] Probabilistic planning can be solved with iterative methods such asvalue iterationandpolicy iteration, when the state space is sufficiently small. With partial observability, probabilistic planning is similarly solved with iterative methods, but using a representation of the value functions defined for the space of beliefs instead of states. In preference-based planning, the objective is not only to produce a plan but also to satisfy user-specifiedpreferences. A difference to the more common reward-based planning, for example corresponding to MDPs, preferences don't necessarily have a precise numerical value. Deterministic planning was introduced with theSTRIPSplanning system, which is a hierarchical planner. Action names are ordered in a sequence and this is a plan for the robot. Hierarchical planning can be compared with an automatic generatedbehavior tree.[3]The disadvantage is, that a normal behavior tree is not so expressive like a computer program. That means, the notation of a behavior graph contains action commands, but noloopsor if-then-statements. Conditional planning overcomes the bottleneck and introduces an elaborated notation which is similar to acontrol flow, known from other programming languages likePascal. It is very similar toprogram synthesis, which means a planner generates sourcecode which can be executed by an interpreter.[4] An early example of a conditional planner is “Warplan-C” which was introduced in the mid 1970s.[5]What is the difference between a normal sequence and a complicated plan, which contains if-then-statements? It has to do with uncertainty atruntimeof a plan. The idea is that a plan can react tosensor signalswhich are unknown for the planner. The planner generates two choices in advance. For example, if an object was detected, then action A is executed, if an object is missing, then action B is executed.[6]A major advantage of conditional planning is the ability to handlepartial plans.[7]An agent is not forced to plan everything from start to finish but can divide the problem intochunks. This helps to reduce the state space and solves much more complex problems. We speak of "contingent planning" when the environment is observable through sensors, which can be faulty. It is thus a situation where the planning agent acts under incomplete information. For a contingent planning problem, a plan is no longer a sequence of actions but adecision treebecause each step of the plan is represented by a set of states rather than a single perfectly observable state, as in the case of classical planning.[8]The selected actions depend on the state of the system. For example, if it rains, the agent chooses to take the umbrella, and if it doesn't, they may choose not to take it. Michael L. Littman showed in 1998 that with branching actions, the planning problem becomesEXPTIME-complete.[9][10]A particular case of contiguous planning is represented by FOND problems - for "fully-observable and non-deterministic". If the goal is specified in LTLf (linear time logic on finite trace) then the problem is always EXPTIME-complete[11]and 2EXPTIME-complete if the goal is specified with LDLf. Conformant planning is when the agent is uncertain about the state of the system, and it cannot make any observations. The agent then has beliefs about the real world, but cannot verify them with sensing actions, for instance. These problems are solved by techniques similar to those of classical planning,[12][13]but where the state space is exponential in the size of the problem, because of the uncertainty about the current state. A solution for a conformant planning problem is a sequence of actions. Haslum and Jonsson have demonstrated that the problem of conformant planning isEXPSPACE-complete,[14]and 2EXPTIME-complete when the initial situation is uncertain, and there is non-determinism in the actions outcomes.[10]	https://en.wikipedia.org/wiki/Automated_planning_and_scheduling
Acyclic executive[1][2]is an alternative to areal-time operating system. It is a form ofcooperative multitasking, in which there is only onetask. The sole task is typically realized as an infinite loop inmain(), e.g. inC. The basic scheme is to cycle through a repeating sequence of activities, at a set frequency (a.k.a.time-triggered cyclic executive). For example, consider the example of anembedded systemdesigned to monitor atemperature sensorand update anLCDdisplay. The LCD may need to be written twenty times a second (i.e., every 50 ms). If the temperature sensor must be read every 100 ms for other reasons, we might construct a loop of the following appearance: The outer 100 ms cycle is called the major cycle. In this case, there is also an inner minor cycle of 50 ms. In this first example the outer versus inner cycles aren't obvious. We can use a counting mechanism to clarify the major and minor cycles.	https://en.wikipedia.org/wiki/Cyclic_executive
Dynamic priority schedulingis a type ofscheduling algorithmin which the priorities are calculated during the execution of the system. The goal of dynamic priority scheduling is to adapt to dynamically changing progress and to form an optimal configuration in a self-sustained manner. It can be very hard to produce well-defined policies to achieve the goal depending on the difficulty of a given problem. Earliest deadline first schedulingandLeast slack time schedulingare examples of Dynamic priority scheduling algorithms. The idea of real-time scheduling is to confine processor utilization under schedulable utilization of a certain scheduling algorithm, which is scaled from 0 to 1. Higher schedulable utilization means higher utilization of resource and the better the algorithm. In preemptible scheduling, dynamic priority scheduling such asearliest deadline first (EDF)provides the optimal schedulable utilization of 1 in contrast to less than 0.69 with fixed priority scheduling such asrate-monotonic (RM).[1] In periodic real-time task model, a task's processor utilization is defined as execution time over period. Every set of periodic tasks with total processor utilization less or equal to the schedulable utilization of an algorithm can be feasibly scheduled by that algorithm. Unlike fixed priority, dynamic priority scheduling could dynamically prioritize task deadlines achieving optimal schedulable utilization in the preemptible case. Thiscomputer sciencearticle is astub. You can help Wikipedia byexpanding it.	https://en.wikipedia.org/wiki/Dynamic_priority_scheduling
Foreground-backgroundis ascheduling algorithmthat is used to control an execution of multiple processes on a single processor. It is based on two waiting lists, the first one is calledforegroundbecause this is the one in which all processes initially enter, and the second one is calledbackgroundbecause all processes, after using all of theirexecution timein foreground, are moved to background.[1] When a process becomes ready it begins its execution in foreground immediately, forcing the processor to give up execution of the current process in the background and execute the newly created process for a predefined period. This period is usually 2 or morequanta. If the process is not finished after its execution in the foreground it is moved to background waiting list where it will be executed only when the foreground list is empty. After being moved to the background, the process is then run longer than before, usually 4 quanta. The time of execution is increased because the process needs more than 2 quanta to finish (this is the reason it was moved to background). This gives the process the opportunity to finish within this newly designated time. If the process does not finish after this, it is then preempted and moved to the end of the background list. The advantage of the foreground-background algorithm is that it gives the process the opportunity to execute immediately after its creation, but scheduling in the background list is pureround-robin scheduling.[citation needed]	https://en.wikipedia.org/wiki/Foreground-background
Aninterruptible operating systemis anoperating systemwith ability to handle multipleinterruptsconcurrently, or in other words, which allow interrupts to be interrupted. Concurrent interrupt handling essentially mean concurrent execution ofkernelcode and hence induces the additional complexity of concurrency control in accessing kernel datastructures. It also means that the system can stop any program that is already running, which is a feature on nearly all modern operating systems. Thisoperating-system-related article is astub. You can help Wikipedia byexpanding it.	https://en.wikipedia.org/wiki/Interruptible_operating_system
Least slack time(LST)schedulingis analgorithmfordynamic priority scheduling. It assigns priorities to processes based on theirslack time. Slack time is the amount of time left after a job if the job was started now. This algorithm is also known asleast laxity first. Its most common use is inembedded systems, especially those with multiple processors. It imposes the simple constraint that each process on each available processor possesses the same run time, and that individual processes do nothave an affinity toa certain processor. This is what lends it a suitability to embedded systems. This scheduling algorithm first selects those processes that have the smallest "slack time". Slack time is defined as the temporal difference between the deadline, the ready time and the run time. More formally, theslack times{\displaystyle s}for a process is defined as: s=(d−t)−c′{\displaystyle s=(d-t)-c'} whered{\displaystyle d}is the process deadline,t{\displaystyle t}is the real time since the cycle start, andc′{\displaystyle c'}is the remaining computation time. In realtime scheduling algorithms for periodic jobs, an acceptance test is needed before accepting a sporadic job with a hard deadline. One of the simplest acceptance tests for a sporadic job is calculating the amount of slack time between the release time and deadline of the job. LST scheduling is most useful in systems comprising mainly aperiodic tasks, because no prior assumptions are made on the events' rate of occurrence. The main weakness of LST is that it does not look ahead, and works only on the current system state. Thus, during a brief overload of system resources, LST can be suboptimal. It will also be suboptimal when used with uninterruptible processes. However, like theearliest deadline first, and unlikerate monotonic scheduling, this algorithm can be used for processor utilization up to 100%.	https://en.wikipedia.org/wiki/Least_slack_time_scheduling
Lottery schedulingis aprobabilisticscheduling algorithmforprocessesin anoperating system. Processes are each assigned some number oflottery tickets, and theschedulerdraws a random ticket to select the next process. The distribution of tickets need not be uniform; granting a process more tickets provides it a relative higher chance of selection. This technique can be used to approximate other schedulingalgorithms, such asShortest job nextandFair-share scheduling. Lottery scheduling solves the problem ofstarvation. Giving each process at least one lottery ticket guarantees that it has non-zero probability of being selected at each scheduling operation. Implementations of lottery scheduling should take into consideration that there could be billions of tickets distributed among a large pool ofthreads. To have anarraywhere eachindexrepresents a ticket, and each location contains the thread corresponding to that ticket, may be highly inefficient. Lottery scheduling can bepreemptiveor non-preemptive.	https://en.wikipedia.org/wiki/Lottery_scheduling
Incomputer science,priority inversionis a scenario inschedulingin which a high-prioritytaskis indirectly superseded by a lower-priority task, effectively inverting the assigned priorities of the tasks. This violates the priority model that high-priority tasks can only be prevented from running by higher-priority tasks. Inversion occurs when there is aresource contentionwith a low-priority task that is thenpreemptedby a medium-priority task. Consider two tasksHandL, of high and low priority respectively, either of which can acquire exclusive use of a shared resourceR. IfHattempts to acquireRafterLhas acquired it, thenHbecomes blocked untilLrelinquishes the resource. Sharing an exclusive-use resource (Rin this case) in a well-designed system typically involvesLrelinquishingRpromptly so thatH(a higher-priority task) does not stay blocked for excessive periods of time. Despite good design, however, it is possible that a third taskMof medium priority becomes runnable duringL's use ofR. At this point,Mbeing higher in priority thanL, preemptsL(sinceMdoes not depend onR), causingLto not be able to relinquishRpromptly, in turn causingH—the highest-priority process—to be unable to run (that is,Hsuffers unexpected blockage indirectly caused by lower-priority tasks likeM). In some cases, priority inversion can occur without causing immediate harm—the delayed execution of the high-priority task goes unnoticed, and eventually, the low-priority task releases the shared resource. However, there are also many situations in which priority inversion can cause serious problems. If the high-priority task is leftstarvedof the resources, it might lead to a system malfunction or the triggering of pre-defined corrective measures, such as awatchdog timerresetting the entire system. The trouble experienced by theMars Pathfinderlander in 1997[1][2]is a classic example of problems caused by priority inversion inrealtimesystems. Priority inversion can also reduce theperceived performanceof the system. Low-priority tasks usually have a low priority because it is not important for them to finish promptly (for example, they might be abatch jobor another non-interactive activity). Similarly, a high-priority task has a high priority because it is more likely to be subject to strict time constraints—it may be providing data to an interactive user, or acting subject to real-time response guarantees. Because priority inversion results in the execution of a lower-priority task blocking the high-priority task, it can lead to reduced system responsiveness or even the violation of response time guarantees. A similar problem calleddeadline interchangecan occur withinearliest deadline first scheduling(EDF). The existence of this problem has been known since the 1970s. Lampson and Redell[3]published one of the first papers to point out the priority inversion problem. Systems such as the UNIX kernel were already addressing the problem with the splx() primitive. There is no foolproof method to predict the situation. There are however many existing solutions, of which the most common ones are:	https://en.wikipedia.org/wiki/Priority_inversion
In amultitaskingcomputersystem,processesmay occupy a variety ofstates. These distinct states may not be recognized as such by theoperating systemkernel. However, they are a useful abstraction for the understanding of processes. The following typical process states are possible on computer systems of all kinds. In most of these states, processes are "stored" onmain memory. When a process is first created, it occupies the "created" or "new" state. In this state, the process awaits admission to the "ready" state. Admission will be approved or delayed by a long-term, or admission,scheduler. Typically in mostdesktop computersystems, this admission will be approved automatically. However, forreal-time operating systemsthis admission may be delayed. In a realtime system, admitting too many processes to the "ready" state may lead to oversaturation andovercontentionof the system's resources, leading to an inability to meet process deadlines. A "ready" or "waiting" process has been loaded intomain memoryand is awaiting execution on aCPU(to be context switched onto the CPU by the dispatcher, or short-term scheduler). There may be many "ready" processes at any one point of the system's execution—for example, in a one-processor system, only one process can be executing at any one time, and all other "concurrently executing" processes will be waiting for execution. Aready queueorrun queueis used incomputer scheduling. Modern computers are capable of running many different programs or processes at the same time. However, the CPU is only capable of handling one process at a time. Processes that are ready for the CPU are kept in aqueuefor "ready" processes. Other processes that are waiting for an event to occur, such as loading information from a hard drive or waiting on an internet connection, are not in the ready queue. A process moves into the running state when it is chosen for execution. The process's instructions are executed by one of the CPUs (or cores) of the system. There is at most one running process per CPU or core. A process can run in either of the two modes, namelykernel modeoruser mode.[1][2] A process transitions to ablockedstate when it cannot carry on without an external change in state or event occurring. For example, a process may block on a call to an I/O device such as a printer, if the printer is not available. Processes also commonly block when they require user input, or require access to acritical sectionwhich must be executed atomically. Such critical sections are protected using a synchronization object such as a semaphore or mutex. A process may beterminated, either from the "running" state by completing its execution or by explicitly being killed. In either of these cases, the process moves to the "terminated" state. The underlying program is no longer executing, but the process remains in theprocess tableas azombie processuntil its parent process calls thewaitsystem callto read itsexit status, at which point the process is removed from the process table, finally ending the process's lifetime. If the parent fails to callwait, this continues to consume the process table entry (concretely theprocess identifieror PID), and causes aresource leak. Two additional states are available for processes in systems that supportvirtual memory. In both of these states, processes are "stored" on secondary memory (typically ahard disk). (Also calledsuspended and waiting.) In systems that support virtual memory, a process may be swapped out, that is, removed from main memory and placed on external storage by the scheduler. From here the process may be swapped back into the waiting state. (Also calledsuspended and blocked.) Processes that are blocked may also be swapped out. In this event the process is both swapped out and blocked, and may be swapped back in again under the same circumstances as a swapped out and waiting process (although in this case, the process will move to the blocked state, and may still be waiting for a resource to become available).	https://en.wikipedia.org/wiki/Process_states
Queueing theoryis the mathematical study ofwaiting lines, orqueues.[1]A queueing model is constructed so that queue lengths and waiting time can be predicted.[1]Queueing theory is generally considered a branch ofoperations researchbecause the results are often used when making business decisions about the resources needed to provide a service. Queueing theory has its origins in research byAgner Krarup Erlang, who created models to describe the system of incoming calls at the Copenhagen Telephone Exchange Company.[1]These ideas were seminal to the field ofteletraffic engineeringand have since seen applications intelecommunications,traffic engineering,computing,[2]project management, and particularlyindustrial engineering, where they are applied in the design of factories, shops, offices, and hospitals.[3][4] The spelling "queueing" over "queuing" is typically encountered in the academic research field. In fact, one of the flagship journals of the field isQueueing Systems. Queueing theory is one of the major areas of study in the discipline ofmanagement science. Through management science, businesses are able to solve a variety of problems using different scientific and mathematical approaches. Queueing analysis is the probabilistic analysis of waiting lines, and thus the results, also referred to as the operating characteristics, are probabilistic rather than deterministic.[5]The probability that n customers are in the queueing system, the average number of customers in the queueing system, the average number of customers in the waiting line, the average time spent by a customer in the total queuing system, the average time spent by a customer in the waiting line, and finally the probability that the server is busy or idle are all of the different operating characteristics that these queueing models compute.[5]The overall goal of queueing analysis is to compute these characteristics for the current system and then test several alternatives that could lead to improvement. Computing the operating characteristics for the current system and comparing the values to the characteristics of the alternative systems allows managers to see the pros and cons of each potential option. These systems help in the final decision making process by showing ways to increase savings, reduce waiting time, improve efficiency, etc. The main queueing models that can be used are the single-server waiting line system and the multiple-server waiting line system, which are discussed further below. These models can be further differentiated depending on whether service times are constant or undefined, the queue length is finite, the calling population is finite, etc.[5] Aqueueorqueueing nodecan be thought of as nearly ablack box.Jobs(also calledcustomersorrequests, depending on the field) arrive to the queue, possibly wait some time, take some time being processed, and then depart from the queue. However, the queueing node is not quite a pure black box since some information is needed about the inside of the queueing node. The queue has one or moreserverswhich can each be paired with an arriving job. When the job is completed and departs, that server will again be free to be paired with another arriving job. An analogy often used is that of the cashier at a supermarket. Customers arrive, are processed by the cashier, and depart. Each cashier processes one customer at a time, and hence this is a queueing node with only one server. A setting where a customer will leave immediately if the cashier is busy when the customer arrives, is referred to as a queue with nobuffer(or nowaiting area). A setting with a waiting zone for up toncustomers is called a queue with a buffer of sizen. The behaviour of a single queue (also called aqueueing node) can be described by abirth–death process, which describes the arrivals and departures from the queue, along with the number of jobs currently in the system. Ifkdenotes the number of jobs in the system (either being serviced or waiting if the queue has a buffer of waiting jobs), then an arrival increaseskby 1 and a departure decreaseskby 1. The system transitions between values ofkby "births" and "deaths", which occur at the arrival ratesλi{\displaystyle \lambda _{i}}and the departure ratesμi{\displaystyle \mu _{i}}for each jobi{\displaystyle i}. For a queue, these rates are generally considered not to vary with the number of jobs in the queue, so a singleaveragerate of arrivals/departures per unit time is assumed. Under this assumption, this process has an arrival rate ofλ=avg(λ1,λ2,…,λk){\displaystyle \lambda ={\text{avg}}(\lambda _{1},\lambda _{2},\dots ,\lambda _{k})}and a departure rate ofμ=avg(μ1,μ2,…,μk){\displaystyle \mu ={\text{avg}}(\mu _{1},\mu _{2},\dots ,\mu _{k})}. Thesteady stateequations for the birth-and-death process, known as thebalance equations, are as follows. HerePn{\displaystyle P_{n}}denotes the steady state probability to be in staten. The first two equations imply and By mathematical induction, The condition∑n=0∞Pn=P0+P0∑n=1∞∏i=0n−1λiμi+1=1{\displaystyle \sum _{n=0}^{\infty }P_{n}=P_{0}+P_{0}\sum _{n=1}^{\infty }\prod _{i=0}^{n-1}{\frac {\lambda _{i}}{\mu _{i+1}}}=1}leads to which, together with the equation forPn{\displaystyle P_{n}}(n≥1){\displaystyle (n\geq 1)}, fully describes the required steady state probabilities. Single queueing nodes are usually described using Kendall's notation in the form A/S/cwhereAdescribes the distribution of durations between each arrival to the queue,Sthe distribution of service times for jobs, andcthe number of servers at the node.[6][7]For an example of the notation, theM/M/1 queueis a simple model where a single server serves jobs that arrive according to aPoisson process(where inter-arrival durations areexponentially distributed) and have exponentially distributed service times (the M denotes aMarkov process). In anM/G/1 queue, the G stands for "general" and indicates an arbitraryprobability distributionfor service times. Consider a queue with one server and the following characteristics: Further, letEn{\displaystyle E_{n}}represent the number of times the system enters staten, andLn{\displaystyle L_{n}}represent the number of times the system leaves staten. Then\|En−Ln\|∈{0,1}{\displaystyle \left\vert E_{n}-L_{n}\right\vert \in \{0,1\}}for alln. That is, the number of times the system leaves a state differs by at most 1 from the number of times it enters that state, since it will either return into that state at some time in the future (En=Ln{\displaystyle E_{n}=L_{n}}) or not (\|En−Ln\|=1{\displaystyle \left\vert E_{n}-L_{n}\right\vert =1}). When the system arrives at a steady state, the arrival rate should be equal to the departure rate. Thus the balance equations imply The fact thatP0+P1+⋯=1{\displaystyle P_{0}+P_{1}+\cdots =1}leads to thegeometric distributionformula whereρ=λμ<1{\displaystyle \rho ={\frac {\lambda }{\mu }}<1}. A common basic queueing system is attributed toErlangand is a modification ofLittle's Law. Given an arrival rateλ, a dropout rateσ, and a departure rateμ, length of the queueLis defined as: Assuming an exponential distribution for the rates, the waiting timeWcan be defined as the proportion of arrivals that are served. This is equal to the exponential survival rate of those who do not drop out over the waiting period, giving: The second equation is commonly rewritten as: The two-stage one-box model is common inepidemiology.[8] In 1909,Agner Krarup Erlang, a Danish engineer who worked for the Copenhagen Telephone Exchange, published the first paper on what would now be called queueing theory.[9][10][11]He modeled the number of telephone calls arriving at an exchange by aPoisson processand solved theM/D/1 queuein 1917 andM/D/kqueueingmodel in 1920.[12]In Kendall's notation: If the node has more jobs than servers, then jobs will queue and wait for service. TheM/G/1 queuewas solved byFelix Pollaczekin 1930,[13]a solution later recast in probabilistic terms byAleksandr Khinchinand now known as thePollaczek–Khinchine formula.[12][14] After the 1940s, queueing theory became an area of research interest to mathematicians.[14]In 1953,David George Kendallsolved the GI/M/kqueue[15]and introduced the modern notation for queues, now known asKendall's notation. In 1957, Pollaczek studied the GI/G/1 using anintegral equation.[16]John Kingmangave a formula for themean waiting timein aG/G/1 queue, now known asKingman's formula.[17] Leonard Kleinrockworked on the application of queueing theory tomessage switchingin the early 1960s andpacket switchingin the early 1970s. His initial contribution to this field was his doctoral thesis at theMassachusetts Institute of Technologyin 1962, published in book form in 1964. His theoretical work published in the early 1970s underpinned the use of packet switching in theARPANET, a forerunner to the Internet. Thematrix geometric methodandmatrix analytic methodshave allowed queues withphase-type distributedinter-arrival and service time distributions to be considered.[18] Systems with coupled orbits are an important part in queueing theory in the application to wireless networks and signal processing.[19] Modern day application of queueing theory concerns among other thingsproduct developmentwhere (material) products have a spatiotemporal existence, in the sense that products have a certain volume and a certain duration.[20] Problems such as performance metrics for theM/G/kqueueremain an open problem.[12][14] Various scheduling policies can be used at queueing nodes: Server failures occur according to a stochastic (random) process (usually Poisson) and are followed by setup periods during which the server is unavailable. The interrupted customer remains in the service area until server is fixed.[27] Arriving customers not served (either due to the queue having no buffer, or due to balking or reneging by the customer) are also known asdropouts. The average rate of dropouts is a significant parameter describing a queue. Queue networks are systems in which multiple queues are connected bycustomer routing. When a customer is serviced at one node, it can join another node and queue for service, or leave the network. For networks ofmnodes, the state of the system can be described by anm–dimensional vector (x1,x2, ...,xm) wherexirepresents the number of customers at each node. The simplest non-trivial networks of queues are calledtandem queues.[28]The first significant results in this area wereJackson networks,[29][30]for which an efficientproduct-form stationary distributionexists and themean value analysis[31](which allows average metrics such as throughput and sojourn times) can be computed.[32]If the total number of customers in the network remains constant, the network is called aclosed networkand has been shown to also have a product–form stationary distribution by theGordon–Newell theorem.[33]This result was extended to theBCMP network,[34]where a network with very general service time, regimes, and customer routing is shown to also exhibit a product–form stationary distribution. Thenormalizing constantcan be calculated with theBuzen's algorithm, proposed in 1973.[35] Networks of customers have also been investigated, such asKelly networks, where customers of different classes experience different priority levels at different service nodes.[36]Another type of network areG-networks, first proposed byErol Gelenbein 1993:[37]these networks do not assume exponential time distributions like the classic Jackson network. In discrete-time networks where there is a constraint on which service nodes can be active at any time, the max-weight scheduling algorithm chooses a service policy to give optimal throughput in the case that each job visits only a single-person service node.[21]In the more general case where jobs can visit more than one node,backpressure routinggives optimal throughput. Anetwork schedulermust choose aqueueing algorithm, which affects the characteristics of the larger network.[38] Mean-field modelsconsider the limiting behaviour of theempirical measure(proportion of queues in different states) as the number of queuesmapproaches infinity. The impact of other queues on any given queue in the network is approximated by a differential equation. The deterministic model converges to the same stationary distribution as the original model.[39] In a system with high occupancy rates (utilisation near 1), a heavy traffic approximation can be used to approximate the queueing length process by areflected Brownian motion,[40]Ornstein–Uhlenbeck process, or more generaldiffusion process.[41]The number of dimensions of the Brownian process is equal to the number of queueing nodes, with the diffusion restricted to the non-negativeorthant. Fluid models are continuous deterministic analogs of queueing networks obtained by taking the limit when the process is scaled in time and space, allowing heterogeneous objects. This scaled trajectory converges to a deterministic equation which allows the stability of the system to be proven. It is known that a queueing network can be stable but have an unstable fluid limit.[42] Queueing theory finds widespread application in computer science and information technology. In networking, for instance, queues are integral to routers and switches, where packets queue up for transmission. By applying queueing theory principles, designers can optimize these systems, ensuring responsive performance and efficient resource utilization. Beyond the technological realm, queueing theory is relevant to everyday experiences. Whether waiting in line at a supermarket or for public transportation, understanding the principles of queueing theory provides valuable insights into optimizing these systems for enhanced user satisfaction. At some point, everyone will be involved in an aspect of queuing. What some may view to be an inconvenience could possibly be the most effective method. Queueing theory, a discipline rooted in applied mathematics and computer science, is a field dedicated to the study and analysis of queues, or waiting lines, and their implications across a diverse range of applications. This theoretical framework has proven instrumental in understanding and optimizing the efficiency of systems characterized by the presence of queues. The study of queues is essential in contexts such as traffic systems, computer networks, telecommunications, and service operations. Queueing theory delves into various foundational concepts, with the arrival process and service process being central. The arrival process describes the manner in which entities join the queue over time, often modeled using stochastic processes like Poisson processes. The efficiency of queueing systems is gauged through key performance metrics. These include the average queue length, average wait time, and system throughput. These metrics provide insights into the system's functionality, guiding decisions aimed at enhancing performance and reducing wait times.[43][44][45]	https://en.wikipedia.org/wiki/Queuing_theory
Incomputer science,rate-monotonic scheduling(RMS)[1]is a priority assignment algorithm used inreal-time operating systems(RTOS) with a static-priority scheduling class.[2]The static priorities are assigned according to the cycle duration of the job, so a shorter cycle duration results in a higher job priority. These operating systems are generallypreemptiveand have deterministic guarantees with regard to response times. Rate monotonic analysis is used in conjunction with those systems to provide scheduling guarantees for a particular application. A simple version of rate-monotonic analysis assumes that threads have the following properties: It is a mathematical model that contains a calculated simulation of periods in a closed system, whereround-robinandtime-sharingschedulers fail to meet the scheduling needs otherwise. Rate monotonic scheduling looks at a run modeling of all threads in the system and determines how much time is needed to meet the guarantees for the set of threads in question. The rate-monotonic priority assignment isoptimalunder the given assumptions, meaning that if any static-priority scheduling algorithm can meet all the deadlines, then the rate-monotonic algorithm can too. Thedeadline-monotonic schedulingalgorithm is also optimal with equal periods and deadlines, in fact in this case the algorithms are identical; in addition, deadline monotonic scheduling is optimal when deadlines are less than periods.[3]For the task model in which deadlines can be greater than periods, Audsley's algorithm endowed with an exact schedulability test for this model finds an optimal priority assignment.[4] Liu & Layland (1973)proved that for a set ofnperiodic tasks with unique periods, a feasible schedule that will always meet deadlines exists if theCPUutilization is below a specific bound (depending on the number of tasks). The schedulability test for RMS is: whereUis the utilization factor,Ciis the computation time for processi,Tiis the release period (with deadline one period later) for processi, andnis the number of processes to be scheduled. For example,U ≤ 0.8284for two processes. When the number of processes tends towardsinfinity, this expression will tend towards: Therefore, a rough estimate whenn≥10{\displaystyle {n}\geq {10}}is that RMS can meet all of the deadlines if total CPU utilization,U, is less than 70%. The other 30% of the CPU can be dedicated to lower-priority, non-real-time tasks. For smaller values ofnor in cases whereUis close to this estimate, the calculated utilization bound should be used. In practice, for theith{\displaystyle {i^{th}}}process,Ci{\displaystyle {C_{i}}}should represent the worst-case (i.e. longest) computation time andTi{\displaystyle {T_{i}}}should represent the worst-case deadline (i.e. shortest period) in which all processing must occur. Inqueueing theory,Tiis called theinterarrival time, andCiis called theservice time. These two parameters are often specified as rates: The utilization for each task, denotedρi, is then: as above. Liu and Layland noted that this bound may be relaxed to the maximum possible value of 1.0, if for tasksTm{\displaystyle {T_{m}}},Ti{\displaystyle {T_{i}}}whereTm>Ti{\displaystyle {T_{m}}{>}{T_{i}}}andi=1...m−1{\displaystyle i=1...m-1},Tm{\displaystyle {T_{m}}}is an integer multiple ofTi{\displaystyle {T_{i}}}, which is to say that all tasks have a period that is not just a multiple of the shortest period,T1{\displaystyle {T_{1}}}, but instead that any task's period is a multiple of all shorter periods. This is known as anharmonic task set. An example of this would be:[T1,T2,T3,T4]=[1,3,6,12]{\displaystyle [{T_{1}},{T_{2}},{T_{3}},{T_{4}}]=[1,3,6,12]}. It is acknowledged by Liu and Layland that it is not always feasible to have a harmonic task set and that in practice other mitigation measures, such as buffering for tasks with soft-time deadlines or using a dynamic priority assignment approach may be used instead to allow for a higher bound. Kuo and Mok[5]showed that for a task set made up ofKharmonic task subsets (known asharmonic chains), the least upper bound test becomes: In the instance where for each task, its period is an exact multiple of every other task that has a shorter period, the task set can be thought of as being composed ofnharmonic task subsets of size 1 and thereforeK=n{\displaystyle {K}{=}{n}}, which makes this generalization equivalent to Liu and Layland's least upper bound. WhenK=1{\displaystyle {K}{=}{1}}, the upper bound becomes 1.0, representing full utilization. It has been shown that a randomly generated periodic task system will usually meet all deadlines when the utilization is 88% or less,[6]however this fact depends on knowing the exact task statistics (periods, deadlines) which cannot be guaranteed for all task sets, and in some cases the authors found that the utilization reached the least upper bound presented by Liu and Layland. The hyperbolic bound[7]is a tighter sufficient condition for schedulability than the one presented by Liu and Layland: whereUiis the CPU utilization for each task. It is the tightest upper bound that can be found using only the individual task utilization factors. In many practical applications, resources are shared and the unmodifiedRMSwill be subject topriority inversionanddeadlockhazards. In practice, this is solved by disabling preemption or bypriority inheritance. Alternative methods are to uselock-free algorithmsor avoid the sharing of a mutex/semaphore across threads with different priorities. This is so that resource conflicts cannot result in the first place. Priority inheritance algorithms can be characterized by two parameters. First, is the inheritance lazy (only when essential) or immediate (boost priority before there is a conflict). Second is the inheritance optimistic (boost a minimum amount) or pessimistic (boost by more than the minimum amount): In practice there is no mathematical difference (in terms of the Liu-Layland system utilization bound) between the lazy and immediate algorithms, and the immediate algorithms are more efficient to implement, and so they are the ones used by most practical systems.[citation needed] An example of usage of basic priority inheritance is related to the "Mars Pathfinderreset bug"[13][14]which was fixed on Mars by changing the creation flags for the semaphore so as to enable the priority inheritance. Allinterrupt service routines(ISRs), whether they have a hard real-time deadline or not should be included in RMS analysis to determine schedulability in cases where ISRs have priorities above all scheduler-controlled tasks. An ISR may already be appropriately prioritized under RMS rules if its processing period is shorter than that of the shortest, non-ISR process. However, an ISR with a period/deadline longer than any non-ISR process period with a critical deadline results in a violation of RMS and prevents the use of the calculated bounds for determining schedulability of a task set. One method for mitigating a mis-prioritized ISR is to adjust the analysis by reducing the ISR's period to be equal to that of the shortest period, if possible. Imposing this shorter period results in prioritization that conforms to RMS, but also results in a higher utilization factor for the ISR and therefore for the total utilization factor, which may still be below the allowable bound and therefore schedulability can be proven. As an example, consider a hardware ISR that has a computation time,Cisr{\displaystyle {C_{isr}}}of 500 microseconds and a period,Tisr{\displaystyle {T_{isr}}}, of 4 milliseconds. If the shortest scheduler-controlled task has a period,T1{\displaystyle {T_{1}}}of 1 millisecond, then the ISR would have a higher priority, but a lower rate, which violates RMS. For the purposes of proving schedulability, setTisr=T1{\displaystyle {T_{isr}}={T_{1}}}and recalculate the utilization factor for the ISR (which also raises the total utilization factor). In this case,Uisr=Cisr/Tisr{\displaystyle {U_{isr}}{=}{C_{isr}}/{T_{isr}}}will change from0.5ms/4ms=0.125{\displaystyle {0.5ms}/{4ms}{=}0.125}to0.5ms/1ms=0.5{\displaystyle {0.5ms}/{1ms}{=}0.5}. This utilization factor would be used when adding up the total utilization factor for the task set and comparing to the upper bound to prove schedulability. It should be emphasized that adjusting the period of the ISR is for analysis only and that the true period of the ISR remains unchanged. Another method for mitigating a mis-prioritized ISR is to use the ISR to only set a new semaphore/mutex while moving the time-intensive processing to a new process that has been appropriately prioritized using RMS and will block on the new semaphore/mutex. When determining schedulability, a margin of CPU utilization due to ISR activity should be subtracted from the least upper bound. ISRs with negligible utilization may be ignored. Under RMS, P2 has the highest release rate (i.e. the shortest release period) and so would have the highest priority, followed by P1 and finally P3. The utilization will be: The sufficient condition for3{\displaystyle 3\,}processes, under which we can conclude that the system is schedulable is: BecauseU<Ulub{\displaystyle U<U_{lub}}, and because being below the Least Upper Bound is a sufficient condition, the system is guaranteed to be schedulable. Under RMS, P2 has the highest release rate (i.e. the shortest release period) and so would have the highest priority, followed by P3 and finally P1. Using the Liu and Layland bound, as in Example 1, the sufficient condition for3{\displaystyle 3\,}processes, under which we can conclude that the task set is schedulable, remains: The total utilization will be: SinceU>Ulub{\displaystyle U>U_{lub}}, the system is determinednotto be guaranteed to be schedulable by the Liu and Layland bound. Using the tighter Hyperbolic bound as follows: it is found that the task setisschedulable. Under RMS, P2 has the highest rate (i.e. the shortest period) and so would have the highest priority, followed by P3 and finally P1. Using the Liu and Layland bound, as in Example 1, the sufficient condition for3{\displaystyle 3\,}processes, under which we can conclude that the task set is schedulable, remains: The total utilization will be: SinceU>Ulub{\displaystyle U>U_{lub}}, the system is determinednotto be guaranteed to be schedulable by the Liu and Layland bound. Using the tighter Hyperbolic bound as follows: Since2.0<2.0475{\displaystyle 2.0{<}2.0475}the system is determined tonotbe guaranteed to be schedulable by the Hyperbolic bound. BecauseT3=2T2{\displaystyle {T_{3}}={2{T_{2}}}}, tasks 2 and 3 can be considered a harmonic task subset. Task 1 forms its own harmonic task subset. Therefore, the number of harmonic task subsets,K, is2. Using the total utilization factor calculated above (0.81875), since0.81875<0.828{\displaystyle 0.81875<0.828}the system is determined to be schedulable.	https://en.wikipedia.org/wiki/Rate-monotonic_scheduling
Schedulingis the process of arranging, controlling and optimizing work and workloads in aproductionprocess ormanufacturingprocess. Scheduling is used to allocate plant and machinery resources, planhuman resources, plan production processes andpurchasematerials. It is an important tool formanufacturingandengineering, where it can have a major impact on the productivity of a process. In manufacturing, the purpose of scheduling is to keep due dates of customers and then minimize the production time and costs, by telling a production facility when to make, with which staff, and on which equipment. Production scheduling aims to maximize the efficiency of the operation, utilize maximum resources available and reduce costs. In some situations, scheduling can involve random attributes, such as random processing times, random due dates, random weights, and stochastic machine breakdowns. In this case, the scheduling problems are referred to as "stochastic scheduling". Scheduling is the process of arranging, controlling and optimizing work and workloads in a production process. Companies use backward and forward scheduling to allocate plant and machinery resources, plan human resources, plan production processes and purchase materials. The benefits of production scheduling include: Production scheduling tools greatly outperform older manual scheduling methods. These provide the production scheduler with powerful graphical interfaces which can be used to visually optimize real-time work loads in various stages of production, and pattern recognition allows the software toautomatically create scheduling opportunitieswhich might not be apparent without this view into the data. For example, an airline might wish to minimize the number of airport gates required for its aircraft, in order to reduce costs, and scheduling software can allow the planners to see how this can be done, by analysing time tables, aircraft usage, or the flow of passengers. A key character of scheduling is the productivity, the relation between quantity of inputs and quantity of output. Key concepts here are: Production scheduling can take a significant amount of computing power if there are a large number of tasks. Therefore, a range of short-cut algorithms (heuristics) (a.k.a.dispatchingrules) are used: Batch productionscheduling is the practice of planning and scheduling of batch manufacturing processes. Although scheduling may apply to traditionally continuous processes such as refining,[1][2]it is especially important for batch processes such as those for pharmaceutical active ingredients, biotechnology processes and many specialty chemical processes.[3][4]Batch production scheduling shares some concepts and techniques with finite capacity scheduling which has been applied to many manufacturing problems.[5]	https://en.wikipedia.org/wiki/Scheduling_(production_processes)
Stochastic schedulingconcernsschedulingproblems involving random attributes, such as random processing times, random due dates, random weights, and stochastic machine breakdowns. Major applications arise in manufacturing systems, computer systems, communication systems, logistics and transportation, and machine learning, among others.[citation needed] The objective of the stochastic scheduling problems can be regular objectives such as minimizing the total flowtime, themakespan, or the total tardiness cost of missing the due dates; or can be irregular objectives such as minimizing both earliness and tardiness costs of completing the jobs, or the total cost of scheduling tasks under likely arrival of a disastrous event such as a severe typhoon.[1] The performance of such systems, as evaluated by a regular performance measure or an irregular performance measure, can be significantly affected by the scheduling policy adopted to prioritize over time the access of jobs to resources. The goal of stochastic scheduling is to identify scheduling policies that can optimize the objective. Stochastic scheduling problems can be classified into three broad types: problems concerning the scheduling of a batch of stochastic jobs,multi-armed banditproblems, and problems concerning the scheduling of queueing systems.[2]These three types are usually under the assumption that complete information is available in the sense that the probability distributions of the random variables involved are known in advance. When such distributions are not fully specified and there are multiple competing distributions to model the random variables of interest, the problem is referred to as incomplete information. TheBayesian methodhas been applied to treat stochastic scheduling problems with incomplete information. In this class of models, a fixed batch ofn{\displaystyle n}jobs with random process times, whose distributions are known, have to be completed by a set ofm{\displaystyle m}machines to optimize a given performance objective. The simplest model in this class is the problem of sequencing a set ofn{\displaystyle n}jobs on a single machine to minimize the expected weighted flowtime. Job processing times are independent random variables with a general distributionGi(⋅){\displaystyle G_{i}(\cdot )}with meanpi{\displaystyle p_{i}}for jobi{\displaystyle i}. Admissible policies must be nonanticipative (scheduling decisions are based on the system's history up to and including the present time) and nonpreemptive (processing of a job must proceed uninterruptedly to completion once started). Letwi≥0{\displaystyle w_{i}\geq 0}denote the cost rate incurred per unit time in the system for jobi{\displaystyle i}, and letC~i{\displaystyle {\tilde {C}}_{i}}denote its random completion time. LetΠ{\displaystyle \Pi }denote the class of all admissible policies, and letEπ[⋅]{\displaystyle E_{\pi }[\cdot ]}denote expectation under policyπ∈Π{\displaystyle \pi \in \Pi }. The problem can be stated as minπ∈Πw1Eπ[C~1]+⋯+wnEπ[C~n].{\displaystyle \min _{\pi \in \Pi }w_{1}E_{\pi }[{\tilde {C}}_{1}]+\cdots +w_{n}E_{\pi }[{\tilde {C}}_{n}].} The optimal solution in the special deterministic case is given by the Shortest Weighted Processing Time rule of Smith:[3]sequence jobs in nonincreasing order of the priority indexwipi{\displaystyle w_{i}p_{i}}. The natural extension of Smith's rule is also optimal to the above stochastic model.[4] In general, the rule that assigns higher priority to jobs with shorter expected processing time is optimal for the flowtime objective under the following assumptions: when all the job processing time distributions are exponential;[5]when all the jobs have a common general processing time distribution with a nondecreasing hazard rate function;[6]and when job processing time distributions are stochastically ordered.[7] Multi-armed banditmodels form a particular type of optimal resource allocation (usually working with time assignment), in which a number of machines or processors are to be allocated to serve a set of competing projects (termed as arms). In the typical framework, the system consists of a single machine and a set of stochastically independent projects, which will contribute random rewards continuously or at certain discrete time points, when they are served. The objective is to maximize the expected total discounted rewards over all dynamically revisable policies.[1] The first version of multi-bandit problems was formulated in the area of sequential designs by Robbins (1952).[8]Since then, there had not been any essential progress in two decades, until Gittins and his collaborators made celebrated research achievements in Gittins (1979),[9]Gittins and Jones (1974),[10]Gittins and Glazebrook (1977),[11]and Whittle (1980)[12]under the Markov and semi-Markov settings. In this early model, each arm is modeled by a Markov or semi-Markov process in which the time points of making state transitions are decision epochs. The machine can at each epoch pick an arm to serve with a reward represented as a function of the current state of the arm being processed, and the solution is characterized by allocation indices assigned to each state that depends only on the states of the arms. These indices are therefore known as Gittins indices and the optimal policies are usually calledGittins indexpolicies, due to his reputable contributions. Soon after the seminal paper of Gittins, the extension to branching bandit problem to model stochastic arrivals (also known as the open bandit or arm acquiring bandit problem) was investigated by Whittle (1981).[13]Other extensions include the models of restless bandit, formulated by Whittle (1988),[14]in which each arm evolves restlessly according to two different mechanisms (idle fashion and busy fashion), and the models with switching costs/delays by Van Oyen et al. (1992),[15]who showed that no index policy is optimal when switching between arms incurs costs/delays. Models in this class are concerned with the problems of designing optimal service disciplines in queueing systems, where the jobs to be completed arrive at random epochs over time, instead of being available at the start. The main class of models in this setting is that of multiclass queueing networks (MQNs), widely applied as versatile models of computer communications and manufacturing systems. The simplest types of MQNs involve scheduling a number of job classes in a single server. Similarly as in the two model categories discussed previously, simple priority-index rules have been shown to be optimal for a variety of such models. More general MQN models involve features such as changeover times for changing service from one job class to another (Levy and Sidi, 1990),[16]or multiple processing stations, which provide service to corresponding nonoverlapping subsets of job classes. Due to the intractability of such models, researchers have aimed to design relatively simple heuristic policies which achieve a performance close to optimal. The majority of studies on stochastic scheduling models have largely been established based on the assumption of complete information, in the sense that the probability distributions of the random variables involved, such as the processing times and the machine up/downtimes, are completely specified a priori. However, there are circumstances where the information is only partially available. Examples of scheduling with incomplete information can be found in environmental clean-up,[17]project management,[18]petroleum exploration,[19]sensor scheduling in mobile robots,[20]and cycle time modeling,[21]among many others. As a result of incomplete information, there may be multiple competing distributions to model the random variables of interest. An effective approach was developed by Cai et al. (2009),[22]to tackle this problem, based on Bayesian information update. It identifies each competing distribution by a realization of a random variable, sayΘ{\displaystyle \Theta }. Initially,Θ{\displaystyle \Theta }has a prior distribution based on historical information or assumption (which may be non-informative if no historical information is available). Information onΘ{\displaystyle \Theta }may be updated after realizations of the random variables are observed. A key concern in decision making is how to utilize the updated information to refine and enhance the decisions. When the scheduling policy is static in the sense that it does not change over time, optimal sequences are identified to minimize the expected discounted reward and stochastically minimize the number of tardy jobs under a common exponential due date.[22]When the scheduling policy is dynamic in the sense that it can make adjustments during the process based on up-to-date information, posterior Gittins index is developed to find the optimal policy that minimizes the expected discounted reward in the class of dynamic policies.[22]	https://en.wikipedia.org/wiki/Stochastic_scheduling
ATime/Utility Function(TUF), néeTime/Value Function, specifies the application-specificutilitythat anaction(e.g., computational task, mechanical movement) yields depending on its completion time.[1][2]TUFs and their utility interpretations (semantics), scales, and values are derived from application domain-specific subject matter knowledge. An example (but not the only) interpretation of utility is an action's relativeimportance,which otherwise is independent of itstimeliness. The traditional deadline represented as a TUF is a special case—a downward step of utility from 1 to 0 at the deadline time—e.g., timeliness without importance. A TUF is more general—it has acritical time,with application-specific shapes and utility values on each side, after which it does not increase. The various researcher and practitioner definitions offirmandsoftreal-time can also be represented as special cases of the TUF model. The optimality criterion forschedulingmultiple TUF-constrained actions has historically in the literature been only maximalutility accrual(UA)—e.g., a (perhaps expected) weighted sum of the individual actions' completion utilities. This thus takes into account timeliness with respect to critical times. Additional criteria (e.g., energy, predictability), constraints (e.g., dependencies), system models, scheduling algorithms, and assurances have been added as the TUF/UA paradigm and its use cases have evolved. More expressively, TUF/UA allows accrued utility, timeliness, predictability, and other scheduling criteria and constraints to be traded off against one another for the schedule to yield situationalapplication QoS[a]—as opposed to only timeliness per se. Instances of the TUF/UA paradigm have been employed in a wide variety of application domains, most frequently in military systems. The TUF/UA paradigm was originally created to address certain action timeliness, predictability of timeliness, andapplication QoS-based scheduling needs of various military applications for which traditional real-time concepts and practices are not sufficiently expressive (e.g., for dynamically timeliness-critical systems not having deadlines) and load resilience (e.g., for systems subject to routine action overloads). An important common example class of such applications is missile defense (notionally[3][4][5]). Subsequently, numerous variations on the original TUF model, the TUF/UA paradigm's system model, and thus scheduling techniques and algorithms, have been studied in the academic literature—e.g.,[6][7][8][9][10]—and applied in civilian contexts. Some examples of the latter include: cyber-physical systems,[11]AI,[12]multi-robot systems,[13]drone scheduling,[14]autonomous robots,[15]intelligent vehicle-to-cloud data transfers,[16]industrial process control,[17]transaction systems,[18]high performance computing,[19]cloud systems,[20]heterogeneous clusters,[21]service-oriented computing,[22]networking,[23]and memory management for real[24]and virtual[25]machines. A steel mill example is briefly described in the Introduction of Clark's Ph.D. thesis.[26] TUFs and their utility interpretations (semantics), scales, and values are derived from domain-specific subject matter knowledge.[27][5]A historically frequent interpretation of utility is actions' relativeimportance.[b]A framework for á priori assigning static utility values subject to strong constraints on system models has been devised,[8]but subsequent (like prior) TUF/UA research and development have preferred to depend on exploiting application-specificity rather than attempting to create more general frameworks. However, such frameworks and tools remain an important research topic. By traditional convention, a TUF is aconcave function, including linear ones. See the depiction of some example TUFs. TUF/UA papers in the research literature, with few exceptions, e.g.,[28][6][29][30][8][10]are for only either linear or piecewise linear[31](including conventional deadline-based) TUFs because they are easier to specify and schedule. In many cases, the TUFs are onlymonotonically decreasing. Aconstant functionrepresents an action's utility that is not related to the action's completion time—for example, the action's constant relative importance. This allows both time-dependent and time-independent actions to be scheduled coherently. A TUF has a globalcritical time, after which its utility does not increase. If a TUF never decreases, its global critical time is the first time when its maximum utility is reached. A constant TUF has an arbitrary critical time for the purpose of scheduling—such as the action's release time, or the TUF's termination time. The global critical time may be followed by local critical times[2]—for example, consider a TUF having a sequence of downward steps, perhaps to approximate a smooth downward curve.[c] TUF utility values are usually either integers or rational numbers. TUF utility may include negative values. (A TUF that has negative values in its range is not necessarily dropped from scheduling consideration or aborted during its operation—that decision depends on the scheduling algorithm.) A conventional deadline time (d) represented as a TUF is a special case—a downward step TUF[d]having a unit penalty (i.e., having utility values1before and0after its critical time). More generally, a TUF allows downward (and upward) step functions to have any pre- and post-critical time utilities. Tardiness[32]represented as a TUF is a special case whose non-zero utility is thelinearfunctionC-d, whereCis the action's completion time—either current, expected, or believed.[e]More generally, a TUF allows non-zero earliness and tardiness to benon-linear—e.g., increasing tardiness may result in non-linearly decreasing utility, such as when detecting a threat. Thus, TUFs provide a rich generalization of traditional action completion time constraints inreal-time computing. Alternatively, the TUF/UA paradigm can be employed to use timeliness with respect to the global critical time as a means to a utility accrual end—i.e., application-level Quality of Service (QoS)—instead of timeliness per se being an end in itself (seebelow). A TUF (its shape and values) may be dynamically adapted by an application or its operational environment,[2]independently for any actions currently either waiting or operating.[f] These adaptations ordinarily occur at discrete events—e.g., at an application mode change such as for ballistic missile flight phases.[5] Alternatively, these adaptations may occur continuously, such as for actions whose operational durations and TUFs are application-specific functions of when those actions are either released or begin operation. The operation durations may increase or decrease or both, and may be non-monotonic. This continuous case is calledtime-dependent scheduling.[33][34]Time-dependent scheduling was introduced for (but is not limited to) certain real-time military applications, such as radar tracking systems.[35][36][g] Multiple actions in a system may contend for access to sequentially exclusively[h]shared resources—physical ones such as processors, networks, exogenous application devices (sensors, actuators, etc.)—and logical ones such as synchronizers, data. The TUF/UA paradigm resolves each instance of this contention using an application-specific algorithmic technique that creates (or updates) ascheduleatscheduling events—e.g., times (such as action arrival or completion) or states. The instance's contending actions are dispatched for resource access sequentially in order from the front of the schedule. Thus, action UA sequencing is not greedy.[i] The algorithmic technique creates a schedule based on one or more application-specificobjectives(i.e., optimality criteria). The primary objective for scheduling actions having TUFs is maximalutility accrual(UA). The accrued utility is an application-specific polynomial sum of the schedule's completed actions' utilities. When actions have one or more stochastic parameters (e.g., operation duration), the accrued utility is also stochastic (i.e., an expected polynomial sum). Utility and accrued utility are generic, their interpretations (semantics) and scales are application-specific.[27] An action's operation duration may be fixed and known at system configuration time. More generally, it may be either fixed or stochastic but not known (either with certainty or in expectation) until it either arrives or is released. An operation duration may be an application-specific function of the action's operation starting time—it may increase or decrease or both, and may be non-monotonic. This case is calledtime-dependent scheduling.[33][34][35][36]	https://en.wikipedia.org/wiki/Time-utility_function
Amultiprocessor(MP)systemis defined as "a system with more than oneprocessor", and, more precisely, "a number of central processing units linked together to enable parallel processing to take place".[1][2][3] The key objective of a multiprocessor is to boost a system's execution speed. The other objectives are fault tolerance and application matching.[4] The term "multiprocessor" can be confused with the term "multiprocessing". While multiprocessing is a type of processing in which two or more processors work together to execute multiple programs simultaneously, multiprocessor refers to a hardware architecture that allows multiprocessing.[5] Multiprocessor systems are classified according to how processor memory access is handled and whether system processors are of a single type or various ones. There are many types of multiprocessor systems: In loosely-coupled multiprocessor systems, each processor has its own local memory,input/output (I/O)channels, andoperating system. Processors exchange data over a high-speed communication network by sending messages via a technique known as "message passing". Loosely-coupled multiprocessor systems are also known as distributed-memory systems, as the processors do not share physical memory and have individual I/O channels. Multiprocessor system with a shared memory closely connected to the processors. A symmetric multiprocessing system is a system with centralized shared memory called main memory (MM) operating under a singleoperating systemwith two or more homogeneous processors. There are two types of systems: Aheterogeneous multiprocessing systemcontains multiple, but not homogeneous, processing units – central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), or any type of application-specific integrated circuits (ASICs). The system architecture allows any accelerator – for instance, a graphics processor – to operate at the same processing level as the system's CPU. Systems operating under a single OS (operating system) with two or more homogeneous processors and with a centralized shared main memory. A symmetric multiprocessor system (SMP) is a system with a pool of homogeneous processors running under a single OS with a centralized, shared main memory. Each processor, executing different programs and working on different sets of data, has the ability to share common resources (memory, I/O device, interrupt system, and so on) that are connected using a system bus, a crossbar, or a mix of the two, or an address bus and data crossbar. Each processor has its own cache memory that acts as a bridge between the processor and main memory. The function of the cache is to alleviate the need for main-memory data access, thus reducing system-bus traffic. Use of shared memory allows for a uniform memory-access time (UMA). It is known that the SMP system has limited scalability. To overcome this limitation, the architecture called "cc-NUMA" (cache coherency–non-uniform memory access) is normally used. The main characteristic of a cc-NUMA system is having shared global memory that is distributed to each node, although the effective "access" a processor has to the memory of a remote component subsystem, or "node", is slower compared to local memory access, which is why the memory access is "non-uniform". A cc–NUMA system is a cluster of SMP systems – each called a "node", which can have a single processor, a multi-core processor, or a mix of the two, of one or other kinds of architecture – connected via a high-speed "connection network" that can be a "link" that can be a single or double-reverse ring, or multi-ring, point-to-point connections,[6][7]or a mix of these (e.g.IBM Power Systems[6][8]), bus interconnection (e.g. NUMAq[9]), "crossbar", "segmented bus" (NUMABull HN ISI exHoneywell,[10]) "mesh router", etc. cc-NUMA is also called "distributed shared memory" (DSM) architecture.[11] The difference in access times between local and remote memory can be also an order of magnitude, depending on the kind of connection network used (faster in segmented bus, crossbar, and point-to-point interconnection; slower in serial rings connection). To overcome this limit, a large remote cache (seeRemote cache) is normally used. With this solution, the cc-NUMA system becomes very close to a large SMP system. Both architectures have trade-offs which may be summarized as follows: An intermediate approach, between those of the two previous architectures, is having common resources and local resources, such as local memories (LM), in each processor. The common resources are accessible from all processors via the system bus, while local resources are only accessible to the local processor. Cache memories can be viewed in this perspective as local memories. This system (patented by F. Zulian[12]), used on the DPX/2 300 Unix based system (Bull Hn Information Systems Italia (ex Honeywell)),[13][14]is a mix of tightly and loosely coupled systems and makes use of all the advancements of these two architectures. The local memory is divided into two sectors, global data (GD) and local data (LD). The basic concept of this architecture is to have global data, which is modifiable information, accessible by all processors. This information is duplicated and stored in each local memory of each processor. Each time the global data is modified in a local memory, a hardware write-broadcasting is sent to the system bus to all other local memories to maintain the global data coherency. Thus, global data may be read by each processor accessing its own local memory without involving the system bus. System bus access is only required when global data is modified in a local memory to update the copy of this data stored in the other local memories. Local data can be exchanged in a loosely coupled system viamessage-passing	https://en.wikipedia.org/wiki/Multiprocessor_system_architecture
Symmetric multiprocessingorshared-memory multiprocessing[1](SMP) involves amultiprocessorcomputer hardware and software architecture where two or more identical processors are connected to a single, sharedmain memory, have full access to all input and output devices, and are controlled by a single operating system instance that treats all processors equally, reserving none for special purposes. Most multiprocessor systems today use an SMP architecture. In the case ofmulti-core processors, the SMP architecture applies to the cores, treating them as separate processors. Professor John D. Kubiatowicz considers traditionally SMP systems to contain processors without caches.[2]Culler and Pal-Singh in their 1998 book "Parallel Computer Architecture: A Hardware/Software Approach" mention: "The term SMP is widely used but causes a bit of confusion. [...] The more precise description of what is intended by SMP is a shared memory multiprocessor where the cost of accessing a memory location is the same for all processors; that is, it has uniform access costs when the access actually is to memory. If the location is cached, the access will be faster, but cache access times and memory access times are the same on all processors."[3] SMP systems aretightly coupled multiprocessorsystemswith a pool of homogeneous processors running independently of each other. Each processor, executing different programs and working on different sets of data, has the capability of sharing common resources (memory, I/O device, interrupt system and so on) that are connected using asystem busor acrossbar. SMP systems have centralizedshared memorycalledmain memory(MM) operating under a singleoperating systemwith two or more homogeneous processors. Usually each processor has an associated private high-speed memory known ascache memory(or cache) to speed up the main memory data access and to reduce the system bus traffic. Processors may be interconnected using buses,crossbar switchesor on-chip mesh networks. The bottleneck in the scalability of SMP using buses or crossbar switches is the bandwidth and power consumption of the interconnect among the various processors, the memory, and the disk arrays. Mesh architectures avoid these bottlenecks, and provide nearly linear scalability to much higher processor counts at the sacrifice of programmability: Serious programming challenges remain with this kind of architecture because it requires two distinct modes of programming; one for the CPUs themselves and one for the interconnect between the CPUs. A single programming language would have to be able to not only partition the workload, but also comprehend the memory locality, which is severe in a mesh-based architecture.[4] SMP systems allow any processor to work on any task no matter where the data for that task is located in memory, provided that each task in the system is not in execution on two or more processors at the same time. With properoperating systemsupport, SMP systems can easily move tasks between processors to balance the workload efficiently. The earliest production system with multiple identical processors was the BurroughsB5000, which was functional around 1961. However at run-time this wasasymmetric, with one processor restricted to application programs while the other processor mainly handled the operating system and hardware interrupts. The Burroughs D825 first implemented SMP in 1962.[5][6] IBM offered dual-processor computer systems based on itsSystem/360Model 65and the closely relatedModel 67[7]and 67–2.[8]The operating systems that ran on these machines wereOS/360M65MP[9]andTSS/360. Other software developed at universities, notably theMichigan Terminal System(MTS), used both CPUs. Both processors could access data channels and initiate I/O. In OS/360 M65MP, peripherals could generally be attached to either processor since the operating system kernel ran on both processors (though with a "big lock" around the I/O handler).[10]The MTS supervisor (UMMPS) has the ability to run on both CPUs of the IBM System/360 model 67–2. Supervisor locks were small and used to protect individual common data structures that might be accessed simultaneously from either CPU.[11] Other mainframes that supported SMP included theUNIVAC 1108 II, released in 1965, which supported up to three CPUs, and theGE-635 and GE-645,[12][13]althoughGECOSon multiprocessor GE-635 systems ran in a master-slave asymmetric fashion, unlikeMulticson multiprocessor GE-645 systems, which ran in a symmetric fashion.[14] Starting with its version 7.0 (1972),Digital Equipment Corporation's operating systemTOPS-10implemented the SMP feature, the earliest system running SMP was theDECSystem 1077dual KI10 processor system.[15]Later KL10 system could aggregate up to 8 CPUs in a SMP manner. In contrast, DECs first multi-processorVAXsystem, the VAX-11/782, was asymmetric,[16]but later VAX multiprocessor systems were SMP.[17] Early commercial Unix SMP implementations included theSequent Computer SystemsBalance 8000 (released in 1984) and Balance 21000 (released in 1986).[18]Both models were based on 10 MHzNational SemiconductorNS32032processors, each with a small write-through cache connected to a common memory to form ashared memorysystem. Another early commercial Unix SMP implementation was the NUMA based Honeywell Information Systems Italy XPS-100 designed by Dan Gielan of VAST Corporation in 1985. Its design supported up to 14 processors, but due to electrical limitations, the largest marketed version was a dual processor system. The operating system was derived and ported by VAST Corporation from AT&T 3B20 Unix SysVr3 code used internally within AT&T. Earlier non-commercial multiprocessing UNIX ports existed, including a port named MUNIX created at theNaval Postgraduate Schoolby 1975.[19] Time-sharingandserversystems can often use SMP without changes to applications, as they may have multipleprocessesrunning in parallel, and a system with more than one process running can run different processes on different processors. Onpersonal computers, SMP is less useful for applications that have not been modified. If the system rarely runs more than one process at a time, SMP is useful only for applications that have been modified formultithreaded(multitasked) processing. Custom-programmedsoftwarecan be written or modified to use multiple threads, so that it can make use of multiple processors. Multithreaded programs can also be used in time-sharing and server systems that support multithreading, allowing them to make more use of multiple processors. In current SMP systems, all of the processors are tightly coupled inside the same box with a bus or switch; on earlier SMP systems, a single CPU took an entire cabinet. Some of the components that are shared are global memory, disks, and I/O devices. Only one copy of an OS runs on all the processors, and the OS must be designed to take advantage of this architecture. Some of the basic advantages involves cost-effective ways to increase throughput. To solve different problems and tasks, SMP applies multiple processors to that one problem, known asparallel programming. However, there are a few limits on the scalability of SMP due tocache coherenceand shared objects. Uniprocessor and SMP systems require different programming methods to achieve maximum performance. Programs running on SMP systems may experience an increase in performance even when they have been written for uniprocessor systems. This is because hardwareinterruptsusually suspends program execution while thekernelthat handles them can execute on an idle processor instead. The effect in most applications (e.g. games) is not so much a performance increase as the appearance that the program is running much more smoothly. Some applications, particularly building software and somedistributed computingprojects, run faster by a factor of (nearly) the number of additional processors. (Compilers by themselves are single threaded, but, when building a software project with multiple compilation units, if each compilation unit is handled independently, this creates anembarrassingly parallelsituation across the entire multi-compilation-unit project, allowing near linear scaling of compilation time. Distributed computing projects are inherently parallel by design.) Systems programmers must build support for SMP into theoperating system, otherwise, the additional processors remain idle and the system functions as a uniprocessor system. SMP systems can also lead to more complexity regarding instruction sets. A homogeneous processor system typically requires extra registers for "special instructions" such as SIMD (MMX, SSE, etc.), while a heterogeneous system can implement different types of hardware for different instructions/uses. When more than one program executes at the same time, an SMP system has considerably better performance than a uniprocessor system, because different programs can run on different CPUs simultaneously. Conversely,asymmetric multiprocessing(AMP) usually allows only one processor to run a program or task at a time. For example, AMP can be used in assigning specific tasks to CPU based to priority and importance of task completion. AMP was created well before SMP in terms of handling multiple CPUs, which explains the lack of performance based on the example provided. In cases where an SMP environment processes many jobs, administrators often experience a loss of hardware efficiency. Software programs have been developed to schedule jobs and other functions of the computer so that the processor utilization reaches its maximum potential. Good software packages can achieve this maximum potential by scheduling each CPU separately, as well as being able to integrate multiple SMP machines and clusters. Access to RAM is serialized; this andcache coherencyissues cause performance to lag slightly behind the number of additional processors in the system. SMP uses a single sharedsystem busthat represents one of the earliest styles of multiprocessor machine architectures, typically used for building smaller computers with up to 8 processors. Larger computer systems might use newer architectures such asNUMA(Non-Uniform Memory Access), which dedicates different memory banks to different processors. In a NUMA architecture, processors may access local memory quickly and remote memory more slowly. This can dramatically improve memory throughput as long as the data are localized to specific processes (and thus processors). On the downside, NUMA makes the cost of moving data from one processor to another, as in workload balancing, more expensive. The benefits of NUMA are limited to particular workloads, notably onserverswhere the data are often associated strongly with certain tasks or users. Finally, there iscomputer clusteredmultiprocessing (such asBeowulf), in which not all memory is available to all processors. Clustering techniques are used fairly extensively to build very large supercomputers. Variable Symmetric Multiprocessing (vSMP) is a specific mobile use case technology initiated by NVIDIA. This technology includes an extra fifth core in a quad-core device, called the Companion core, built specifically for executing tasks at a lower frequency during mobile active standby mode, video playback, and music playback. Project Kal-El (Tegra 3),[20]patented by NVIDIA, was the first SoC (System on Chip) to implement this new vSMP technology. This technology not only reduces mobile power consumption during active standby state, but also maximizes quad core performance during active usage for intensive mobile applications. Overall this technology addresses the need for increase in battery life performance during active and standby usage by reducing the power consumption in mobile processors. Unlike current SMP architectures, the vSMP Companion core is OS transparent meaning that the operating system and the running applications are totally unaware of this extra core but are still able to take advantage of it. Some of the advantages of the vSMP architecture includes cache coherency, OS efficiency, and power optimization. The advantages for this architecture are explained below: These advantages lead the vSMP architecture to considerably benefit[peacock prose]over other architectures using asynchronous clocking technologies.	https://en.wikipedia.org/wiki/Symmetric_multiprocessing
Anasymmetric multiprocessing(AMPorASMP) system is amultiprocessorcomputer system where not all of the multiple interconnected central processing units (CPUs) are treated equally. For example, a system might allow (either at the hardware oroperating systemlevel) only one CPU to execute operating system code or might allow only one CPU to perform I/O operations. Other AMP systems might allow any CPU to execute operating system code and perform I/O operations, so that they were symmetric with regard to processor roles, but attached some or all peripherals to particular CPUs, so that they were asymmetric with respect to the peripheral attachment. Asymmetric multiprocessing was the only method for handling multiple CPUs beforesymmetric multiprocessing(SMP) was available. It has also been used to provide less expensive options[1]on systems where SMP was available. For the room-size computers of the 1960s and 1970s, a cost-effective way to increase compute power was to add a second CPU. Since these computers were already close to the fastest available (near the peak of the price:performance ratio), two standard-speed CPUs were much less expensive than a CPU that ran twice as fast. Also, adding a second CPU was less expensive than a second complete computer, which would need its own peripherals, thus requiring much more floor space and an increased operations staff. Notable early AMP offerings by computer manufacturers were theBurroughs B5000, theDECsystem-1055, and theIBM System/360model 65MP. There were also dual-CPU machines built at universities.[2] The problem with adding a second CPU to a computer system was that the operating system had been developed for single-CPU systems, and extending it to handle multiple CPUs efficiently and reliably took a long time. To fill this gap, operating systems intended for single CPUs were initially extended to provide minimal support for a second CPU. In this minimal support, the operating system ran on the “boot” processor, with the other only allowed to run user programs. In the case of the Burroughs B5000, the second processor's hardware was not capable of running "control state" code.[3] Other systems allowed the operating system to run on all processors, but either attached all the peripherals to one processor or attached particular peripherals to particular processors. An option on the Burroughs B5000 was “Processor B”. This second processor, unlike “Processor A” had no connection to the peripherals, though the two processors shared main memory, and Processor B could not run in Control State.[3]The operating system ran only on Processor A. When there was a user job to be executed, it might be run on Processor B, but when that job tried to access the operating system the processor halted and signaled Processor A. The requested operating system service was then run on Processor A. On the B5500, either Processor A or Processor B could be designated as Processor 1 by a switch on the engineer's panel, with the other processor being Processor 2; both processors shared main memory and had hardware access to the I/O processors hence the peripherals, but only Processor 1 could respond to peripheral interrupts.[4]When a job on Processor 2 required an operating system service it would be rescheduled on Processor 1, which was responsible for both initiating I/O processor activity and responding to interrupts indicating completion. In practice, this meant that while user jobs could run on either Processor 1 or Processor 2 and could access intrinsic library routines that didn't require kernel support, the operating system would schedule them on the latter whenever possible.[5] Control Data Corporation offered two configurations of itsCDC 6000 seriesthat featured twocentral processors. The CDC 6500[6]was a CDC 6400 with two central processors. The CDC 6700 was a CDC 6600 with the CDC 6400 central processor added to it. These systems were organized quite differently from the other multiprocessors in this article. The operating system ran on theperipheral processors, while the user's application ran on the CPUs. Thus, the terms ASMP and SMP do not properly apply to these multiprocessors. Digital Equipment Corporation(DEC) offered a dual-processor version of itsDECsystem-1050which used two KA10 processors; all peripherals were attached to one processor, the primary processor, and the primary processor ran the operating system code.[7]This offering was extended to the KL-10 and KS-10 processors in the PDP-10 line; in those systems, the boot CPU is designated the "policy CPU", which runs the command interpreter, swaps jobs in and out of memory, and performs a few other functions; other operating system functions, and I/O, can be performed by any of the processors, and if the policy processor fails, another processor takes over as the policy processor.[8] Digital Equipment Corporationdeveloped, but never released, a multiprocessorPDP-11, the PDP-11/74,[9]running a multiprocessor version ofRSX-11M.[10]In that system, either processor could run operating system code, and could perform I/O, but not all peripherals were accessible to all processors; most peripherals were attached to one or the other of the CPUs, so that a processor to which a peripheral wasn't attached would, when it needed to perform an I/O operation on that peripheral, request the processor to which the peripheral was attached to perform the operation.[10] DEC's first multi-processorVAXsystem, the VAX-11/782, was an asymmetric dual-processor system; only the first processor had access to the I/O devices.[11] Two options were available for theIBM System/370 Model 168for attaching a second processor.[12]One was the IBM 3062Attached Processing Unit, in which the second processor had no access to the channels, and was therefore similar to the B5000's Processor B or the second processor on a VAX-11/782. The other option offered a complete second CPU, and was thus more like the System/360 model 65MP.	https://en.wikipedia.org/wiki/Asymmetric_multiprocessing
Amulti-core processor(MCP) is amicroprocessoron a singleintegrated circuit(IC) with two or more separatecentral processing units(CPUs), calledcoresto emphasize their multiplicity (for example,dual-coreorquad-core). Each core reads and executesprogram instructions,[1]specifically ordinaryCPU instructions(such as add, move data, and branch). However, the MCP can run instructions on separate cores at the same time, increasing overall speed for programs that supportmultithreadingor otherparallel computingtechniques.[2]Manufacturers typically integrate the cores onto a single ICdie, known as achip multiprocessor(CMP), or onto multiple dies in a singlechip package. As of 2024, the microprocessors used in almost all newpersonal computersare multi-core. A multi-core processor implementsmultiprocessingin a single physical package. Designers may couple cores in a multi-core device tightly or loosely. For example, cores may or may not sharecaches, and they may implementmessage passingorshared-memoryinter-core communication methods. Commonnetwork topologiesused to interconnect cores includebus,ring, two-dimensionalmesh, andcrossbar. Homogeneous multi-core systems include only identical cores;heterogeneousmulti-core systems have cores that are not identical (e.g.big.LITTLEhave heterogeneous cores that share the sameinstruction set, whileAMD Accelerated Processing Unitshave cores that do not share the same instruction set). Just as with single-processor systems, cores in multi-core systems may implement architectures such asVLIW,superscalar,vector, ormultithreading. Multi-core processors are widely used across many application domains, includinggeneral-purpose,embedded,network,digital signal processing(DSP), andgraphics(GPU). Core count goes up to even dozens, and for specialized chips over 10,000,[3]and insupercomputers(i.e. clusters of chips) the count can go over 10 million (and inone caseup to 20 million processing elements total in addition to host processors).[4] The improvement in performance gained by the use of a multi-core processor depends very much on thesoftwarealgorithms used and their implementation. In particular, possible gains are limited by the fraction of the software that canrun in parallelsimultaneously on multiple cores; this effect is described byAmdahl's law. In the best case, so-calledembarrassingly parallelproblems may realize speedup factors near the number of cores, or even more if the problem is split up enough to fit within each core's cache(s), avoiding use of much slower main-system memory. Most applications, however, are not accelerated as much unless programmers invest effort inrefactoring.[5] The parallelization of software is a significant ongoing topic of research. Cointegration of multiprocessor applications provides flexibility in network architecture design. Adaptability within parallel models is an additional feature of systems utilizing these protocols.[6] In the consumer market, dual-core processors (that is, microprocessors with two units) started becoming commonplace on personal computers in the late 2000s.[7]Quad-core processors were also being adopted in that era for higher-end systems before becoming standard. In the late 2010s, hexa-core (six cores) started entering the mainstream[8]and since the early 2020s has overtaken quad-core in many spaces.[9] The termsmulti-coreanddual-coremost commonly refer to some sort ofcentral processing unit(CPU), but are sometimes also applied todigital signal processors(DSP) andsystem on a chip(SoC). The terms are generally used only to refer to multi-core microprocessors that are manufactured on thesameintegrated circuitdie; separate microprocessor dies in the same package are generally referred to by another name, such asmulti-chip module. This article uses the terms "multi-core" and "dual-core" for CPUs manufactured on thesameintegrated circuit, unless otherwise noted. In contrast to multi-core systems, the termmulti-CPUrefers to multiple physically separate processing-units (which often contain special circuitry to facilitate communication between each other). The termsmany-coreandmassively multi-coreare sometimes used to describe multi-core architectures with an especially high number of cores (tens to thousands[10]).[11] Some systems use manysoft microprocessorcores placed on a singleFPGA. Each "core" can be considered a "semiconductor intellectual property core" as well as a CPU core.[citation needed] While manufacturing technology improves, reducing the size of individual gates, physical limits ofsemiconductor-basedmicroelectronicshave become a major design concern. These physical limitations can cause significant heat dissipation and data synchronization problems. Various other methods are used to improve CPU performance. Someinstruction-level parallelism(ILP) methods such assuperscalarpipeliningare suitable for many applications, but are inefficient for others that contain difficult-to-predict code. Many applications are better suited tothread-level parallelism(TLP) methods, and multiple independent CPUs are commonly used to increase a system's overall TLP. A combination of increased available space (due to refined manufacturing processes) and the demand for increased TLP led to the development of multi-core CPUs. In the 1990s,Kunle Olukotunled the Stanford Hydra Chip Multiprocessor (CMP) research project. This initiative was among the first to demonstrate the viability of integrating multiple processors on a single chip, a concept that laid the groundwork for today's multicore processors. The Hydra project introduced support for thread-level speculation (TLS), enabling more efficient parallel execution of programs. Several business motives drive the development of multi-core architectures. For decades, it was possible to improve performance of a CPU by shrinking the area of the integrated circuit (IC), which reduced the cost per device on the IC. Alternatively, for the same circuit area, more transistors could be used in the design, which increased functionality, especially forcomplex instruction set computing(CISC) architectures.Clock ratesalso increased by orders of magnitude in the decades of the late 20th century, from several megahertz in the 1980s to several gigahertz in the early 2000s. As the rate of clock speed improvements slowed, increased use of parallel computing in the form of multi-core processors has been pursued to improve overall processing performance. Multiple cores were used on the same CPU chip, which could then lead to better sales of CPU chips with two or more cores. For example,Intelhas produced a 48-core processor for research in cloud computing; each core has anx86architecture.[12][13] Since computer manufacturers have long implementedsymmetric multiprocessing(SMP) designs using discrete CPUs, the issues regarding implementing multi-core processor architecture and supporting it with software are well known. Additionally: In order to continue delivering regular performance improvements for general-purpose processors, manufacturers such asIntelandAMDhave turned to multi-core designs, sacrificing lower manufacturing-costs for higher performance in some applications and systems. Multi-core architectures are being developed, but so are the alternatives. An especially strong contender for established markets is the further integration of peripheral functions into the chip. The proximity of multiple CPU cores on the same die allows thecache coherencycircuitry to operate at a much higher clock rate than what is possible if the signals have to travel off-chip. Combining equivalent CPUs on a single die significantly improves the performance ofcache snoop(alternative:Bus snooping) operations. Put simply, this means thatsignalsbetween different CPUs travel shorter distances, and therefore those signalsdegradeless. These higher-quality signals allow more data to be sent in a given time period, since individual signals can be shorter and do not need to be repeated as often. Assuming that the die can physically fit into the package, multi-core CPU designs require much lessprinted circuit board(PCB) space than do multi-chipSMPdesigns. Also, a dual-core processor uses slightly less power than two coupled single-core processors, principally because of the decreased power required to drive signals external to the chip. Furthermore, the cores share some circuitry, like the L2 cache and the interface to thefront-side bus(FSB). In terms of competing technologies for the available silicon die area, multi-core design can make use of proven CPU core library designs and produce a product with lower risk of design error than devising a new wider-core design. Also, adding more cache suffers from diminishing returns. Multi-core chips also allow higher performance at lower energy. This can be a big factor in mobile devices that operate on batteries. Since each core in a multi-core CPU is generally more energy-efficient, the chip becomes more efficient than having a single large monolithic core. This allows higher performance with less energy. A challenge in this, however, is the additional overhead of writing parallel code.[15] Maximizing the usage of the computing resources provided by multi-core processors requires adjustments both to theoperating system(OS) support and to existing application software. Also, the ability of multi-core processors to increase application performance depends on the use of multiple threads within applications. Integration of a multi-core chip can lower the chip production yields. They are also more difficult to manage thermally than lower-density single-core designs. Intel has partially countered this first problem by creating its quad-core designs by combining two dual-core ones on a single die with a unified cache, hence any two working dual-core dies can be used, as opposed to producing four cores on a single die and requiring all four to work to produce a quad-core CPU. From an architectural point of view, ultimately, single CPU designs may make better use of the silicon surface area than multiprocessing cores, so a development commitment to this architecture may carry the risk of obsolescence. Finally, raw processing power is not the only constraint on system performance. Two processing cores sharing the same system bus and memory bandwidth limits the real-world performance advantage. The trend in processor development has been towards an ever-increasing number of cores, as processors with hundreds or even thousands of cores become theoretically possible.[16]In addition, multi-core chips mixed withsimultaneous multithreading, memory-on-chip, and special-purpose"heterogeneous"(or asymmetric) cores promise further performance and efficiency gains, especially in processing multimedia, recognition and networking applications. For example, abig.LITTLEcore includes a high-performance core (called 'big') and a low-power core (called 'LITTLE'). There is also a trend towards improving energy-efficiency by focusing on performance-per-watt with advanced fine-grain or ultra fine-grainpower managementand dynamicvoltageandfrequency scaling(i.e.laptopcomputers andportable media players). Chips designed from the outset for a large number of cores (rather than having evolved from single core designs) are sometimes referred to asmanycoredesigns, emphasising qualitative differences. The composition and balance of the cores in multi-core architecture show great variety. Some architectures use one core design repeated consistently ("homogeneous"), while others use a mixture of different cores, each optimized for a different, "heterogeneous" role. How multiple cores are implemented and integrated significantly affects both the developer's programming skills and the consumer's expectations of apps and interactivity versus the device.[17]A device advertised as being octa-core will only have independent cores if advertised asTrue Octa-core, or similar styling, as opposed to being merely two sets of quad-cores each with fixed clock speeds.[18][19] The article "CPU designers debate multi-core future" by Rick Merritt, EE Times 2008,[20]includes these comments: Chuck Moore [...] suggested computers should be like cellphones, using a variety of specialty cores to run modular software scheduled by a high-level applications programming interface. [...] Atsushi Hasegawa, a senior chief engineer atRenesas, generally agreed. He suggested the cellphone's use of many specialty cores working in concert is a good model for future multi-core designs. [...]Anant Agarwal, founder and chief executive of startupTilera, took the opposing view. He said multi-core chips need to be homogeneous collections of general-purpose cores to keep the software model simple. An outdated version of an anti-virus application may create a new thread for a scan process, while itsGUIthread waits for commands from the user (e.g. cancel the scan). In such cases, a multi-core architecture is of little benefit for the application itself due to the single thread doing all the heavy lifting and the inability to balance the work evenly across multiple cores. Programming truly multithreaded code often requires complex co-ordination of threads and can easily introduce subtle and difficult-to-find bugs due to the interweaving of processing on data shared between threads (seethread-safety). Consequently, such code is much more difficult to debug than single-threaded code when it breaks. There has been a perceived lack of motivation for writing consumer-level threaded applications because of the relative rarity of consumer-level demand for maximum use of computer hardware. Also, serial tasks like decoding theentropy encodingalgorithms used invideo codecsare impossible to parallelize because each result generated is used to help create the next result of the entropy decoding algorithm. Given the increasing emphasis on multi-core chip design, stemming from the grave thermal and power consumption problems posed by any further significant increase in processor clock speeds, the extent to which software can be multithreaded to take advantage of these new chips is likely to be the single greatest constraint on computer performance in the future. If developers are unable to design software to fully exploit the resources provided by multiple cores, then they will ultimately reach an insurmountable performance ceiling. The telecommunications market had been one of the first that needed a new design of parallel datapath packet processing because there was a very quick adoption of these multiple-core processors for the datapath and the control plane. These MPUs are going to replace[21]the traditional Network Processors that were based on proprietarymicrocodeorpicocode. Parallel programmingtechniques can benefit from multiple cores directly. Some existingparallel programming modelssuch asCilk Plus,OpenMP,OpenHMPP,FastFlow, Skandium,MPI, andErlangcan be used on multi-core platforms. Intel introduced a new abstraction for C++ parallelism calledTBB. Other research efforts include theCodeplay Sieve System, Cray'sChapel, Sun'sFortress, and IBM'sX10. Multi-core processing has also affected the ability of modern computational software development. Developers programming in newer languages might find that their modern languages do not support multi-core functionality. This then requires the use ofnumerical librariesto access code written in languages likeCandFortran, which perform math computations faster[citation needed]than newer languages likeC#. Intel's MKL and AMD'sACMLare written in these native languages and take advantage of multi-core processing. Balancing the application workload across processors can be problematic, especially if they have different performance characteristics. There are different conceptual models to deal with the problem, for example using a coordination language and program building blocks (programming libraries or higher-order functions). Each block can have a different native implementation for each processor type. Users simply program using these abstractions and an intelligent compiler chooses the best implementation based on the context.[22] Managingconcurrencyacquires a central role in developing parallel applications. The basic steps in designing parallel applications are: On the other hand, on theserver side, multi-core processors are ideal because they allow many users to connect to a site simultaneously and have independentthreadsof execution. This allows for Web servers and application servers that have much betterthroughput. Vendors may license some software "per processor". This can give rise to ambiguity, because a "processor" may consist either of a single core or of a combination of cores. Embedded computingoperates in an area of processor technology distinct from that of "mainstream" PCs. The same technological drives towards multi-core apply here too. Indeed, in many cases the application is a "natural" fit for multi-core technologies, if the task can easily be partitioned between the different processors. In addition, embedded software is typically developed for a specific hardware release, making issues ofsoftware portability, legacy code or supporting independent developers less critical than is the case for PC or enterprise computing. As a result, it is easier for developers to adopt new technologies and as a result there is a greater variety of multi-core processing architectures and suppliers. As of 2010[update], multi-corenetwork processorshave become mainstream, with companies such asFreescale Semiconductor,Cavium Networks,WintegraandBroadcomall manufacturing products with eight processors. For the system developer, a key challenge is how to exploit all the cores in these devices to achieve maximum networking performance at the system level, despite the performance limitations inherent in asymmetric multiprocessing(SMP) operating system. Companies such as6WINDprovide portable packet processing software designed so that the networking data plane runs in a fast path environment outside the operating system of the network device.[25] Indigital signal processingthe same trend applies:Texas Instrumentshas the three-core TMS320C6488 and four-core TMS320C5441,Freescalethe four-core MSC8144 and six-core MSC8156 (and both have stated they are working on eight-core successors). Newer entries include the Storm-1 family fromStream Processors, Incwith 40 and 80 general purpose ALUs per chip, all programmable in C as a SIMD engine andPicochipwith 300 processors on a single die, focused on communication applications. Inheterogeneous computing, where a system uses more than one kind of processor or cores, multi-core solutions are becoming more common:XilinxZynq UltraScale+ MPSoC has a quad-core ARM Cortex-A53 and dual-core ARM Cortex-R5. Software solutions such as OpenAMP are being used to help with inter-processor communication. Mobile devices may use theARM big.LITTLEarchitecture. The research and development of multicore processors often compares many options, and benchmarks are developed to help such evaluations. Existing benchmarks include SPLASH-2, PARSEC, and COSMIC for heterogeneous systems.[49]	https://en.wikipedia.org/wiki/Multi-core_processor
Binary Modular Dataflow Machine(BMDFM) is a software package that enables running an application in parallel on shared memorysymmetric multiprocessing(SMP) computers using the multiple processors to speed up the execution of single applications. BMDFM automatically identifies and exploits parallelism due to the static and mainlydynamic schedulingof thedataflowinstruction sequences derived from the formerly sequential program. The BMDFM dynamic scheduling subsystem performs asymmetric multiprocessing(SMP)emulationof atagged-tokendataflowmachineto provide the transparent dataflow semantics for the applications. No directives for parallel execution are needed. Current parallel shared memory SMPs are complex machines, where a large number of architectural aspects must be addressed simultaneously to achieve high performance. Recent commodity SMP machines for technical computing can have many tightly coupled cores (good examples are SMP machines based on multi-core processors fromIntel(CoreorXeon) orIBM(Power)). The number of cores per SMP node is planned to double every few years according to computer makers' announcements. Multi-core processorsare intended to exploit a thread-level parallelism, identified by software. Hence, the most challenging task is to find an efficient way to harness power of multi-core processors for processing an application program in parallel. Existent OpenMP paradigm of the static parallelization with a fork-join runtime library works pretty well for loop-intensive regular array-based computations only, however, compile-time parallelization methods are weak in general and almost inapplicable for irregular applications: The BMDFM technology mainly uses dynamic scheduling to exploit parallelism of an application program, thus, BMDFM avoids mentioned disadvantages of the compile-time methods.[1][2]BMDFM is a parallel programming environment for multi-core SMP that provides: BMDFM combines the advantages of known architectural principles into a single hybrid architecture that is able to exploitimplicit parallelismof the applications having negligible dynamic scheduling overhead and no bottlenecks. Mainly, the basic dataflow principle is used. The dataflow principle says: "An instruction or a function can be executed as soon as all its arguments are ready. A dataflow machine manages the tags for every piece of data at runtime. Data is marked with ready tag when data has been computed. Instructions with ready arguments get executed marking their result data ready". The main feature of BMDFM is to provide a conventional programming paradigm at the top level, so-called transparent dataflow semantics. A user understands BMDFM as avirtual machine(VM), which runs all statements of an application program in parallel, having all parallelizing and synchronizing mechanisms fully transparent. The statements of an application program are normal operators, of which any single threaded program might consist: they include variable assignments, conditional processing, loops, function calls, etc. Suppose we have the code fragment shown below: The two first statements are independent, so a dataflow engine of BMDFM can run them on different processors or processor's cores. The two last statements can also run in parallel but only after "a" and "b" are computed. The dataflow engine recognizes dependencies automatically because of its ability to build a dataflow graph dynamically at runtime. Additionally, the dataflow engine correctly orders the output stream to output the results sequentially. Thus even after the out-of-order processing the results will appear in a natural way. Suppose that above code fragment now is nested in a loop: The dataflow engine of BMDFM will keep variables "a" and "b" under unique contexts for each iteration. Actually, these are different copies of the variables. A context variable exists until it is referenced by instruction consumers. Later non-referenced contexts will be garbage collected at runtime. Therefore, the dataflow engine can exploit both local parallelism within the iteration and global parallelism as well running multiple iterations simultaneously. BMDFM is a convenient parallel programming environment and an efficient runtime engine for multi-core SMP due to the MIMD unification of several architectural paradigms (von-Neumann, SMP and dataflow): BMDFM is intended for use in a role of the parallel runtime engine (instead of conventional fork-join runtime library) able to run irregular applications automatically in parallel. Due to the transparent dataflow semantics on top, BMDFM is a simple parallelization technique for application programmers and, at the same time, is a much better parallel programming and compiling technology for multi-core SMP computers. The basic concept of BMDFM relies on underlying commodity SMP hardware, which is available on the market. Normally, SMP vendors provide their own SMP Operating System (OS) with an SVR4/POSIX UNIX interface (Linux, HP-UX, SunOS/Solaris, Tru64OSF1, IRIX, AIX, BSD, MacOS, etc.). On top of an SMP OS, the multithreaded dataflow runtime engine performs a software emulation of the dataflow machine. Such a virtual machine has interfaces to the virtual machine language and to C providing the transparent dataflow semantics for conventional programming. BMDFM is built as a hybrid of several architectural principles: An application program (input sequential program) is processed in three stages: preliminary code reorganization (code reorganizer), static scheduling of the statements (static scheduler) and compiling/loading (compiler, loader). The output after the static scheduling stages is a multiple clusters flow that feeds the multithreaded engine via the interface designed in a way to avoid bottlenecks. The multiple clusters flow can be thought of as a compiled input program split into marshaled clusters, in which all addresses are resolved and extended with context information. Splitting into marshaled clusters allows loading them multithreadedly. Context information lets iterations be processed in parallel. Listener thread orders the output stream after the out-of-order processing. The BMDFM dynamic scheduling subsystem is an efficient SMP emulator of the tagged-token dataflow machine. The Shared Memory Pool is divided in three main parts:input/outputring buffer port(IORBP),data buffer(DB), andoperation queue(OQ). Thefront-end controlvirtual machineschedules an input application program statically and puts clustered instructions and data of the input program into the IORBP. The ring buffer service processes (IORBP PROC) move data into the DB and instructions into the OQ. The operation queue service processes (OQ PROC) tag the instructions as ready for execution if the required operands' data is accessible. Execution processes (CPU PROC) execute instructions, which are tagged as ready and output computed data into the DB or to the IORBP. Additionally, IORBP PROC and OQ PROC are responsible for freeing memory after contexts have been processed. The context is a special unique identifier representing a copy of data within different iteration bodies accordingly to the tagged-token dataflow architecture. This allows the dynamic scheduler to handle several iterations in parallel. Running under an SMP OS, the processes will occupy all available real machine processors and processor cores. In order to allow several processes accessing the same data concurrently, the BMDFM dynamic scheduler locks objects in the shared memory pool via SVR4/POSIX semaphore operations. Locking policy provides multiple read-only access and exclusive access for modification. Every machine supportingANSI CandPOSIX;UNIX System V(SVR4) may run BMDFM. BMDFM is provided as full multi-threaded versions for:	https://en.wikipedia.org/wiki/BMDFM
Inmultiprocessorcomputer systems,software lockoutis the issue of performance degradation due to the idle wait times spent by theCPUsinkernel-levelcritical sections. Software lockout is the major cause ofscalabilitydegradation in a multiprocessor system, posing a limit on the maximum useful number of processors. To mitigate the phenomenon, the kernel must be designed to have itscritical sectionsas short as possible, therefore decomposing eachdata structurein smaller substructures. In most multiprocessor systems, each processor schedules and controls itself, therefore there's no "supervisor" processor,[1]and kerneldata structuresare globally shared; sections of code that access those shared data structures arecritical sections. This design choice is made to improve scaling, reliability and modularity.[1]Examples of such kernel data structure areready listandcommunication channels. A "conflict" happens when more than oneprocessoris trying to access the same resource (a memory portion) at the same time. To preventcritical racesandinconsistency, only one processor (CPU) at a given time is allowed to access a particulardata structure(a memory portion), while other CPUs trying to access at the same time arelocked-out, waiting in idle status.[1][2] Three cases can be distinguished when this idle wait is either necessary, convenient, or not convenient. The idle wait is necessary when the access is to a ready list for a low levelschedulingoperation. The idle wait is not necessary but convenient in the case of a critical section forsynchronization/IPCoperations, which require less time than acontext switch(executing anotherprocessto avoid idle wait). Idle wait is instead not convenient in case of a kernel critical section fordevice management, present inmonolithic kernelsonly. Amicrokernelinstead falls on just the first two of the above cases. In a multiprocessor system, most of the conflicts arekernel-level conflicts, due to the access to the kernel level critical sections, and thus the idle wait periods generated by them have a major impact in performance degradation. This idle wait time increases the average number of idle processors and thus decreasesscalabilityandrelative efficiency. Taking as parameters the average time interval spent by aprocessorin kernel level critical sections (L, for time in locked state), and the average time interval spent by a processor in tasks outside critical sections (E),[1]the ratioL/Eis crucial in evaluating software lockout. Typical values forL/Erange from 0.01 to 0.1.[3]In a system with aL/Eratio of 0.05, for instance, if there are 15 CPUs, it is expected that on average 1 CPU will always be idle;[3]with 21 CPUs, 2.8 will be idle;[4]with 40 CPUs, 19 will be idle; with 41 CPUs, 20 will be idle.[3]Therefore, adding more than 40 CPUs to that system would be useless. In general, for eachL/Evalue, there's a threshold for the maximum number of useful CPUs. To reduce the performance degradation of software lockout to reasonable levels (L/Ebetween 0.05 and 0.1), the kernel and/or the operating system must be designed accordingly. Conceptually, the most valid solution is to decompose each kernel data structure in smaller independent substructures, having each a shorter elaboration time. This allows more than one CPU to access the original data structure. Manyuniprocessorsystems withhierarchical protection domainshave been estimated to spend up to 50% of the time performing "supervisor mode" operations. If such systems were adapted formultiprocessingby setting a lock at any access to "supervisor state",L/Ewould easily be greater than 1,[3]resulting in a system with the same throughput as the uniprocessor despite the number of CPUs.	https://en.wikipedia.org/wiki/Software_lockout
OpenHMPP(HMPP[1]for Hybrid Multicore Parallel Programming) - programming standard forheterogeneous computing. Based on a set of compiler directives, standard is a programming model designed to handlehardware acceleratorswithout the complexity associated withGPU programming. This approach based on directives has been implemented because they enable a loose relationship between an application code and the use of a hardware accelerator (HWA). The OpenHMPP directive-based programming model offers a syntax to offload computations on hardware accelerators and to optimize data movement to/from the hardware memory. The model is based on works initialized by CAPS (Compiler and Architecture for Embedded and Superscalar Processors), a common project fromINRIA,CNRS, theUniversity of Rennes 1and the INSA of Rennes. OpenHMPP is based on the concept of codelets, functions that can be remotely executed on HWAs. A codelet has the following properties: These properties ensure that a codeletRPCcan be remotely executed by a HWA. This RPC and its associated data transfers can be asynchronous. HMPP provides synchronous and asynchronous RPC. Implementation of asynchronous operation is hardware dependent. HMPP considers two address spaces: the host processor one and the HWA memory. The OpenHMPP directives may be seen as “meta-information” added in the application source code. They are safe meta-information i.e. they do not change the original code behavior. They address the remote execution (RPC) of a function as well as the transfers of data to/from the HWA memory. The table below introduces the OpenHMPP directives. OpenHMPP directives address different needs: some of them are dedicated to declarations and others are dedicated to the management of the execution. One of the fundamental points of the HMPP approach is the concept of directives and their associated labels which makes it possible to expose a coherent structure on a whole set of directives disseminated in an application. There are two kinds of labels: In order to simplify the notations,regular expressionswill be used to describe the syntax of the HMPP directives. The color convention below is used for the description of syntax directives: The general syntax of OpenHMPP directives is: Where: The parameters associated to a directive may be of different types. Below are the directive parameters defined in OpenHMPP: Acodeletdirective declares a computation to be remotely executed on a hardware accelerator. For thecodeletdirective: The syntax of the directive is: More than one codelet directive can be added to a function in order to specify different uses or different execution contexts. However, there can be only one codelet directive for a given call site label. Thecallsitedirective specifies how the use a codelet at a given point in the program. The syntax of the directive is: An example is shown here : In some cases, a specific management of the data throughout the application is required (CPU/GPU data movements optimization, shared variables...). Thegroupdirective allows the declaration of a group of codelets. The parameters defined in this directive are applied to all codelets belonging to the group. The syntax of the directive is: When using a HWA, the main bottleneck is often the data transfers between the HWA and the main processor.To limit the communication overhead, data transfers can be overlapped with successive executions of the same codelet by using the asynchronous property of the HWA. Theallocatedirective locks the HWA and allocates the needed amount of memory. Thereleasedirective specifies when to release the HWA for a group or a stand-alone codelet. Theadvancedloaddirective prefetches data before the remote execution of the codelet. Thedelegatedstoredirective is a synchronization barrier to wait for an asynchronous codelet execution to complete and to then download the results. Thesynchronizedirective specifies to wait until the completion of an asynchronous callsite execution. For the synchronize directive, the codelet label is always mandatory and the group label is required if the codelet belongs to a group. In the following example, the device initialization, memory allocation and upload of the input data are done only once outside the loop and not in each iteration of the loop. Thesynchronizedirective allows to wait for the asynchronous execution of the codelet to complete before launching another iteration. Finally thedelegatedstoredirective outside the loop uploads the sgemm result. Those directives map together all the arguments sharing the given name for all the group. The types and dimensions of all mapped arguments must be identical. Themapdirective maps several arguments on the device. This directive is quite similar as themapdirective except that the arguments to be mapped are directly specified by their name. Themapbynamedirective is equivalent to multiplemapdirectives. Theresidentdirective declares some variables as global within a group. Those variables can then be directly accessed from any codelet belonging to the group. This directive applies to the declaration statement just following it in the source code. The syntax of this directive is: The notation::var_namewith the prefix::, indicates an application's variable declared as resident. A region is a merge of the codelet/callsite directives. The goal is to avoid code restructuration to build the codelet. Therefore, all the attributes available forcodeletorcallsitedirectives can be used onregionsdirectives. In C language: The OpenHMPP Open Standard is based on HMPP Version 2.3 (May 2009, CAPS entreprise). The OpenHMPP directive-based programming model is implemented in: OpenHMPP is used byHPCactors[who?]in Oil & Gas,[citation needed]Energy,[citation needed]Manufacturing,[citation needed]Finance,[citation needed]Education & Research.[citation needed]	https://en.wikipedia.org/wiki/OpenHMPP
In computer science,asynchronous I/O(alsonon-sequential I/O) is a form ofinput/outputprocessing that permits otherprocessingto continue before the I/O operation has finished. A name used for asynchronous I/O in the Windows API isoverlapped I/O. Input and output(I/O) operations on a computer can be extremely slow compared to the processing of data. An I/O device can incorporate mechanical devices that must physically move, such as a hard drive seeking a track to read or write; this is oftenorders of magnitudeslower than the switching of electric current. For example, during a disk operation that takes ten milliseconds to perform, a processor that is clocked at onegigahertzcould have performed ten million instruction-processing cycles. A simple approach to I/O would be to start the access and then wait for it to complete. But such an approach, calledsynchronous I/Oorblocking I/O, would block the progress of a program while the communication is in progress, leavingsystem resourcesidle. When a program makes many I/O operations (such as a program mainly or largely dependent onuser input), this means that the processor can spend almost all of its time idle waiting for I/O operations to complete. Alternatively, it is possible to start the communication and then perform processing that does not require that the I/O be completed. This approach is called asynchronous input/output. Any task that depends on the I/O having completed (this includes both using the input values and critical operations that claim to assure that a write operation has been completed) still needs to wait for the I/O operation to complete, and thus is still blocked, but other processing that does not have a dependency on the I/O operation can continue. Many operating system functions exist to implement asynchronous I/O at many levels. In fact, one of the main functions of all but the most rudimentary ofoperating systemsis to perform at least some form of basic asynchronous I/O, though this may not be particularly apparent to the user or the programmer. In the simplest software solution, the hardware device status ispolledat intervals to detect whether the device is ready for its next operation. (For example, theCP/Moperating system was built this way. Itssystem callsemantics did not require any more elaborate I/O structure than this, though most implementations were more complex, and thereby more efficient.)Direct memory access(DMA) can greatly increase the efficiency of a polling-based system, andhardware interruptscan eliminate the need for polling entirely.Multitaskingoperating systems can exploit the functionality provided by hardware interrupts, whilst hiding the complexity of interrupt handling from the user.Spoolingwas one of the first forms of multitasking designed to exploit asynchronous I/O. Finally,multithreadingand explicit asynchronous I/OAPIswithin user processes can exploit asynchronous I/O further, at the cost of extra software complexity. Asynchronous I/O is used to improve energy efficiency, and in some cases, throughput. However, it can have negative effects on latency and throughput in some cases. Forms of I/O and examples of POSIX functions: All forms of asynchronous I/O open applications up to potential resource conflicts and associated failure. Careful programming (often usingmutual exclusion,semaphores, etc.) is required to prevent this. When exposing asynchronous I/O to applications there are a few broad classes of implementation. The form of theAPIprovided to the application does not necessarily correspond with the mechanism actually provided by the operating system; emulations are possible. Furthermore, more than one method may be used by a single application, depending on its needs and the desires of its programmer(s). Many operating systems provide more than one of these mechanisms, it is possible that some may provide all of them. Available in early Unix. In amultitaskingoperating system, processing can be distributed across different processes, which run independently, have their own memory, and process their own I/O flows; these flows are typically connected inpipelines. Processes are fairly expensive to create and maintain,[citation needed]so this solution only works well if the set of processes is small and relatively stable. It also assumes that the individual processes can operate independently, apart from processing each other's I/O; if they need to communicate in other ways, coordinating them can become difficult.[citation needed] An extension of this approach isdataflow programming, which allows more complicated networks than just the chains that pipes support. Variations: Polling provides non-blocking synchronous API which may be used to implement some asynchronous API. Available in traditional Unix andWindows. Its major problem is that it can waste CPU time polling repeatedly when there is nothing else for the issuing process to do, reducing the time available for other processes. Also, because a polling application is essentially single-threaded it may be unable to fully exploit I/O parallelism that the hardware is capable of. Available inBSDUnix, and almost anything else with aTCP/IPprotocol stack that either utilizes or is modeled after the BSD implementation. A variation on the theme of polling, a select loop uses theselectsystem call tosleepuntil a condition occurs on afile descriptor(e.g., when data is available for reading), atimeoutoccurs, or asignalis received (e.g., when a child process dies). By examining the return parameters of theselectcall, the loop finds out which file descriptor has changed and executes the appropriate code. Often, for ease of use, the select loop is implemented as anevent loop, perhaps usingcallback functions; the situation lends itself particularly well toevent-driven programming. While this method is reliable and relatively efficient, it depends heavily on theUnixparadigm that "everything is a file"; any blocking I/O that does not involve a file descriptor will block the process. The select loop also relies on being able to involve all I/O in the centralselectcall; libraries that conduct their own I/O are particularly problematic in this respect. An additional potential problem is that the select and the I/O operations are still sufficiently decoupled that select's result may effectively be a lie: if two processes are reading from a single file descriptor (arguably bad design) the select may indicate the availability of read data that has disappeared by the time that the read is issued, thus resulting in blocking; if two processes are writing to a single file descriptor (not that uncommon) the select may indicate immediate writability yet the write may still block, because a buffer has been filled by the other process in the interim, or due to the write being too large for the available buffer or in other ways unsuitable to the recipient. The select loop does not reach the ultimate system efficiency possible with, say, thecompletion queuesmethod, because the semantics of theselectcall, allowing as it does for per-call tuning of the acceptable event set, consumes some amount of time per invocation traversing the selection array. This creates little overhead for user applications that might have open one file descriptor for thewindowing systemand a few for open files, but becomes more of a problem as the number of potential event sources grows, and can hinder development of many-client server applications, as in theC10k problem; other asynchronous methods may be noticeably more efficient in such cases. Some Unixes provide system-specific calls with better scaling; for example,epollinLinux(that fills the return selection array with only those event sources on which an event has occurred),kqueueinFreeBSD, andevent ports(and/dev/poll) inSolaris. SVR3Unixprovided thepollsystem call. Arguably better-named thanselect, for the purposes of this discussion it is essentially the same thing. SVR4 Unixes (and thusPOSIX) offer both calls. Available inBSDandPOSIXUnix. I/O is issued asynchronously, and when it is completed asignal(interrupt) is generated. As in low-level kernel programming, the facilities available for safe use within the signal handler are limited, and the main flow of the process could have been interrupted at nearly any point, resulting in inconsistent data structures as seen by the signal handler. The signal handler is usually not able to issue further asynchronous I/O by itself. Thesignalapproach, though relatively simple to implement within the OS, brings to the application program the unwelcome baggage associated with writing an operating system's kernel interrupt system. Its worst characteristic is thateveryblocking (synchronous) system call is potentially interruptible; the programmer must usually incorporate retry code at each call.[citation needed] Available in theclassic Mac OS,VMSandWindows. Bears many of the characteristics of thesignalmethod as it is fundamentally the same thing, though rarely recognized as such. The difference is that each I/O request usually can have its own completion function, whereas thesignalsystem has a single callback. On the other hand, a potential problem of using callbacks is that stack depth can grow unmanageably, as an extremely common thing to do when one I/O is finished is to schedule another. If this should be satisfied immediately, the firstcallbackis not 'unwound' off the stack before the next one is invoked. Systems to prevent this (like 'mid-ground' scheduling of new work) add complexity and reduce performance. In practice, however, this is generally not a problem because the new I/O will itself usually return as soon as the new I/O is started allowing the stack to be 'unwound'. The problem can also be prevented by avoiding any further callbacks, by means of a queue, until the first callback returns. Light-weight processes(LWPs) orthreadsare available in most modern operating systems. Like theprocessmethod, but with lower overhead and without the data isolation that hampers coordination of the flows. Each LWP or thread itself uses traditional blocking synchronous I/O, which simplifies programming logic; this is a common paradigm used in many programming languages including Java and Rust. Multithreading needs to use kernel-provided synchronization mechanisms andthread-safelibraries. This method is not most suitable for extremely large-scale applications like web servers due to the large numbers of threads needed. This approach is also used in theErlangprogramming language runtime system. The Erlangvirtual machineuses asynchronous I/O using a small pool of only a few threads or sometimes just one process, to handle I/O from up to millions of Erlang processes. I/O handling in each process is written mostly using blocking synchronous I/O. This way high performance of asynchronous I/O is merged with simplicity of normal I/O (cf. theActor model). Many I/O problems in Erlang are mapped to message passing, which can be easily processed using built-in selective receive. Fibers/Coroutinescan be viewed as a similarly lightweight approach to do asynchronous I/O outside of the Erlang runtime system, although they do not provide exactly the same guarantees as Erlang processes. Available inMicrosoft Windows,Solaris,AmigaOS,DNIXandLinux(usingio_uring, available on 5.1 and above).[1]I/O requests are issued asynchronously, but notifications of completion are provided via a synchronizing queue mechanism in the order they are completed. Usually associated with astate-machinestructuring of the main process (event-driven programming), which can bear little resemblance to a process that does not use asynchronous I/O or that uses one of the other forms, hampering code reuse[citation needed]. Does not require additional special synchronization mechanisms orthread-safelibraries, nor are the textual (code) and time (event) flows separated. Available inVMSandAmigaOS(often used in conjunction with a completion port). Bears many of the characteristics of thecompletion queuemethod, as it is essentially a completion queue of depth one. To simulate the effect of queue 'depth', an additional event flag is required for each potential unprocessed (but completed) event, or event information can be lost. Waiting for the next available event in such a clump requires synchronizing mechanisms that may not scale well to larger numbers of potentially parallel events. Available in mainframes byIBM,Groupe Bull, andUnisys.Channel I/Ois designed to maximize CPU utilization and throughput by offloading most I/O onto a coprocessor. The coprocessor has onboard DMA, handles device interrupts, is controlled by the main CPU, and only interrupts the main CPU when it's truly necessary. This architecture also supports so-called channel programs that run on the channel processor to do heavy lifting for I/O activities and protocols. Available inWindows Server 2012andWindows 8. Optimized for applications that process large numbers of small messages to achieve higherI/O operations per secondwith reduced jitter and latency.[2] The vast majority of general-purpose computing hardware relies entirely upon two methods of implementing asynchronous I/O: polling and interrupts. Usually both methods are used together, the balance depends heavily upon the design of the hardware and its required performance characteristics. (DMAis not itself another independent method, it is merely a means by which more work can be done per poll or interrupt.) Pure polling systems are entirely possible, small microcontrollers (such as systems using thePIC) are often built this way.CP/Msystems could also be built this way (though rarely were), with or without DMA. Also, when the utmost performance is necessary for only afewtasks, at the expense of any other potential tasks, polling may also be appropriate as the overhead of taking interrupts may be unwelcome. (Servicing an interrupt requires time [and space] to save at least part of the processor state, along with the time required to resume the interrupted task.) Most general-purpose computing systems rely heavily upon interrupts. A pure interrupt system may be possible, though usually some component of polling is also required, as it is very common for multiple potential sources of interrupts to share a common interrupt signal line, in which case polling is used within thedevice driverto resolve the actual source. (This resolution time also contributes to an interrupt system's performance penalty. Over the years a great deal of work has been done to try to minimize the overhead associated with servicing an interrupt. Current interrupt systems are ratherlackadaisicalwhen compared to some highly tuned earlier ones, but the general increase in hardware performance has greatly mitigated this.) Hybrid approaches are also possible, wherein an interrupt can trigger the beginning of some burst of asynchronous I/O, and polling is used within the burst itself. This technique is common in high-speed device drivers, such as network or disk, where the time lost in returning to the pre-interrupt task is greater than the time until the next required servicing. (Common I/O hardware in use these days relies heavily upon DMA and large data buffers to make up for a relatively poorly-performing interrupt system. These characteristically use polling inside the driver loops, and can exhibit tremendous throughput. Ideally the per-datum polls are always successful, or at most repeated a small number of times.) At one time this sort of hybrid approach was common in disk and network drivers where there was not DMA or significant buffering available. Because the desired transfer speeds were faster even than could tolerate the minimum four-operation per-datum loop (bit-test, conditional-branch-to-self, fetch, and store), the hardware would often be built with automaticwait stategeneration on the I/O device, pushing the data ready poll out of software and onto the processor's fetch or store hardware and reducing the programmed loop to two operations. (In effect using the processor itself as a DMA engine.) The6502processor offered an unusual means to provide a three-element per-datum loop, as it had a hardware pin that, when asserted, would cause the processor's Overflow bit to be set directly. (Obviously one would have to take great care in the hardware design to avoid overriding the Overflow bit outside of the device driver!) Using only these two tools (polling, and interrupts), all the other forms of asynchronous I/O discussed above may be (and in fact, are) synthesized. In an environment such as aJava virtual machine(JVM), asynchronous I/O can be synthesizedeven thoughthe environment the JVM is running in may not offer it at all. This is due to the interpreted nature of the JVM. The JVM may poll (or take an interrupt) periodically to institute an internal flow of control change, effecting the appearance of multiple simultaneous processes, at least some of which presumably exist in order to perform asynchronous I/O. (Of course, at the microscopic level the parallelism may be rather coarse and exhibit some non-ideal characteristics, but on the surface it will appear to be as desired.) That, in fact, is the problem with using polling in any form to synthesize a different form of asynchronous I/O. Every CPU cycle that is a poll is wasted, and lost to overhead rather than accomplishing a desired task. Every CPU cycle that isnota poll represents an increase in latency of reaction to pending I/O. Striking an acceptable balance between these two opposing forces is difficult. (This is why hardware interrupt systems were invented in the first place.) The trick to maximize efficiency is to minimize the amount of work that has to be done upon reception of an interrupt in order to awaken the appropriate application. Secondarily (but perhaps no less important) is the method the application itself uses to determine what it needs to do. Particularly problematic (for application efficiency) are the exposed polling methods, including the select/poll mechanisms. Though the underlying I/O events they are interested in are in all likelihood interrupt-driven, the interactiontothis mechanism is polled and can consume a large amount of time in the poll. This is particularly true of the potentially large-scale polling possible through select (and poll). Interrupts map very well to Signals, Callback functions, Completion Queues, and Event flags, such systems can be very efficient. The following examples show three approaches to reading I/O. The objects and functions are abstract. 1. Blocking, synchronous: 2. Blocking and non-blocking, synchronous: (hereIO.poll()blocks for up to 5 seconds, butdevice.read()doesn't) 3. Non-blocking, asynchronous: Here is the same example withasync/await: Here is the example withReactor pattern:	https://en.wikipedia.org/wiki/Asynchronous_I/O
Incomputer science,I/O boundrefers to a condition in which the time it takes to complete acomputationis determined principally by the period spent waiting forinput/outputoperations to be completed, which can be juxtaposed with beingCPU bound. This circumstance arises when the rate at whichdatais requested is slower than the rate it is consumed or, in other words, more time is spent requesting data than processing it.[1] The I/O bound state has been identified as a problem in computing almost since its inception. TheVon Neumann architecture, which is employed by many computing devices, this involves multiple possible solutions such as implementing a logically separatecentral processor unitwhich along with storing the instructions of the program also retrieves actual data usually frommain memoryand makes use of this more accessible data for working. When the process is terminated it writes back the results to the original storage (usually themain memory). Since data must be moved between the CPU and memory along abuswhich has a limiteddata transfer rate, there exists a condition that is known as theVon Neumann bottleneck. Put simply, this means that the databandwidthbetween the CPU and memory tends to limit the overall speed of computation. In terms of the actual technology that makes up a computer, the Von Neumann Bottleneck predicts that it is easier to make the CPU perform calculations faster than it is to supply it with data at the necessary rate for this to be possible. In recent history, the Von Neumann bottleneck has become more apparent. The design philosophy of modern computers is based upon a physically separate CPU and main memory. It is possible to make the CPU run at a high data transfer rate because data is moved between locations inside them across tiny distances. The physical separation between CPU and main memory, however, requires a data bus to move data across comparatively long distances of centimetres or more. The problem of making this part of the system operate sufficiently fast to keep up with the CPU has been a great challenge to designers.[2] The I/O bound state is considered undesirable because it means that theCPUmust stall its operation while waiting for data to be loaded or unloaded frommain memoryorsecondary storage. With faster computation speed being the primary goal of new computer designs and components such as the CPU and memory being expensive, there is a strong imperative to avoid I/O bound states and eliminating them can yield a more economic improvement in performance than upgrading the CPU or memory. As CPU gets faster, processes tend to get more I/O-bound Or in simpler terms: As CPU gets faster, processes tend to not increase in speed in proportion to CPU speed because they get more I/O-bound. This means that I/O bound processes are slower than non-I/O bound processes, not faster. This is due to increases in the rate of data processing in the core, while the rate at which data is transferred from storage to the processor does not increase with it. As CPU clock speed increases, allowing more instructions to be executed in a given time window, the limiting factor of effective execution is the rate at which instructions can be delivered to the processor from storage, and sent from the processor to their destination. In short, programs naturally shift to being more and more I/O bound.[3] Assume we have one CPU-bound process and many I/O-bound processes. As the processes flow around the system, the following scenario may result. The CPU-bound process will get and hold the CPU. During this time, all the other processes will finish their I/O and will move into the ready queue, waiting for the CPU. While the processes wait in the ready queue, the I/O devices are idle. Eventually, the CPU-bound process finishes its CPU burst and moves to an I/O device. All the I/O-bound processes, which have short CPU bursts, execute quickly and move back to the I/O queues. At this point, the CPU sits idle. The CPU-bound process will then move back to the ready queue and be allocated the CPU. Again, all the I/O processes end up waiting in the ready queue until the CPU-bound process is done. There is aconvoy effectas all the other processes wait for the one big process to get off the CPU. This effect results in lower CPU and device utilization than might be possible if the shorter processes were allowed to go first.[4]	https://en.wikipedia.org/wiki/I/O_bound
In computing, aninput deviceis a piece of equipment used to provide data and control signals to an information processing system, such as a computer or information appliance. Examples of input devices includekeyboards,computer mice,scanners, cameras,joysticks, andmicrophones. Input devices can be categorized based on: Akeyboardis ahuman interface devicewhich is represented as a matrix of buttons. Each button, or key, can be used to either input an alphanumeric character to a computer, or to call upon a particular function of the computer. It acts as the maintext entry interfacefor most users.[1] Keyboards are available in many form factors, depending on the use case. Standard keyboards can be categorized by its size and number of keys, and the type of switch it employs. Other keyboards cater to specific use cases, such as anumeric keypador akeyer. Desktop keyboards are typically large, often have full key travel distance, and features such as multimedia keys and a numeric keypad. Keyboards on laptops and tablets typically compromise on comfort to achieve a thin figure. There are various switch technologies used in modern keyboards, such asmechanical switches(which use springs), scissor switches (usually found on a laptop keyboard), or a membrane. Other keyboards do not have physical keys, such as avirtual keyboard, or aprojection keyboard. Apointing deviceallows a user to input spatial data to a computer. It is commonly used as a simple and intuitive way to select items on a computer screen on agraphical user interface(GUI), either by moving amouse pointer, or, in the case of a touch screen, by physically touching the item on screen. Common pointing devices include mice, touchpads, and touch screens.[2] Whereas mice operate by detecting their displacement on a surface, analog devices, such as3D mice, joysticks, or pointing sticks, function by reporting their angle of deflection. Pointing devices can be classified on: Direct input is almost necessarily absolute, but indirect input may be either absolute or relative. For example, digitizinggraphics tabletsthat do not have an embedded screen involve indirect input and sense absolute positions and are often run in an absolute input mode, but they may also be set up to simulate a relative input mode like that of atouchpad, where thestylusor puck can be lifted and repositioned.Embedded LCD tablets, which are also referred to as graphics tablet monitors, are the extension of digitizing graphics tablets. They enable users to see the real-time positions via the screen while being used. Asensoris an input device which produces data based on physical properties.[4] Sensors are commonly found inmobile devicesto detect their physical orientation and acceleration, but may also be found indesktop computersin the form of a thermometer used to monitor system temperature. Some sensors can be built withMEMS, which allows them to be microscopic in size. Some devices allow many continuousdegrees of freedomas input. These can be used as pointing devices, but are generally used in ways that don't involve pointing to a location in space, such as the control of a camera angle while in 3D applications. These kinds of devices are typically used invirtual reality systems (CAVEs), where input that registerssix degrees of freedomis required.[citation needed] Input devices, such as buttons andjoysticks, can be combined on a single physical device that could be thought of as a composite device. Manygamingdevices have controllers like this. Technically mice are composite devices, as they both track movement and provide buttons for clicking, but composite devices are generally considered to have more than two different forms of input. Video input devices are used to digitize images or video from the outside world into the computer. The information can be stored in a multitude of formats depending on the user's requirement. Many video input devices use acamera sensor. Voice input devices are used to capture sound. In some cases, an audiooutput devicecan be used as an input device, in order to capture produced sound. Audio input devices allow a user to send audio info to a computer for processing, recording, or carrying out commands. Devices such as microphones allow users to speak to the computer in order to record a voice message or navigate software. Aside from recording, audio input devices are also used withspeech recognitionsoftware. Punched cardsandpunched tapeswere used often in the 20th century. A punched hole represented a one; its absence represented a zero. A mechanical or optical reader was used to input a punched card or tape.	https://en.wikipedia.org/wiki/Input_device
Anoutput deviceis any piece ofcomputer hardwarethat converts information or data into a human-perceptible form or, historically, into a physical machine-readable form for use with other non-computerized equipment. It can be text, graphics, tactile, audio, or video. Examples includemonitors,printersandsound cards. In an industrial setting, output devices also include "printers" for paper tape and punched cards, especially where the tape or cards are subsequently used to control industrial equipment, such as an industrial loom with electrical robotics which is not fully computerized Adisplay deviceis the most common form of output device which presents output visually on computer screen. The output appears temporarily on the screen and can easily be altered or erased. With all-in-one PCs, notebook computers, hand held PCs and other devices; the term display screen is used for the display device. The display devices are also used in home entertainment systems, mobile systems, cameras and video game systems. Display devices form images by illuminating a desired configuration of . Raster display devices are organized in the form of a 2-dimensional matrix with rows and columns. This is done many times within a second, typically 60, 75, 120 or 144 Hz on consumer devices. The interface between a computer'sCPUand the display is aGraphics Processing Unit(GPU). This processor is used to form images on aframebuffer. When the image is to be sent to the display, the GPU sends its image through avideo display controllerto generate avideo signal, which is then sent to adisplay interfacesuch asHDMI,VGA, orDVI GPUs can be divided intodiscreteandintegratedunits, the former being an external unit and the latter of which is included within a CPU die.[1]Discrete graphics cards are almost always connected to the host through thePCI Expressbus, while older graphics cards may have usedAGPorPCI. Some mobile computers support an external graphics card throughThunderbolt(via PCIe). A monitor is a standalone display commonly used with adesktop computer, or in conjunction to alaptopas an external display. The monitor is connected to the host through the use of a display cable, such asHDMI,DisplayPort,VGA, and more. Older monitors useCRTtechnology, while modern monitors are typicallyflat panel displaysusing a plethora of technologies such asTFT-LCD,LED,OLED, and more. Almost all mobile devices incorporate an internal display. These internal displays are connected to the computer through an internal display interface such asLVDSoreDP. The chief advantage of these displays is their portability. Prior to the development of modern pixel-oriented displays,computer terminalswere used, composed of a character-oriented display device known as aVDUand acomputer keyboard.[2] These terminals were often monochromatic, and could only display text. Rudimentary graphics could be displayed through the use ofASCII artalong withbox-drawing characters.Teleprinterswere the precursors to these devices. A projector is a display that projects the computer image onto a surface through the use of a high power lamp. These displays are seen in use to show slideshow presentations or in movie screenings.[3] Display technologies can be classified based on working principle, lighting (or lack thereof), pixel layout, and more. A monochrome display is a type of CRT common in the early days ofcomputing, from the 1960s through the 1980s, before color monitors became popular.[4] They are still widely used in applications such as computerized cash register systems. Green screen was the common name for a monochrome monitor using a green "P1" phosphor screen. Color monitors, sometimes calledRGBmonitors, accept three separate signals (red, green, and blue), unlike a monochromatic display which accepts one. Color monitors implement the RGB color model by using three different phosphors that appear red, green, and blue when activated. By placing the phosphors directly next to each other, and activating them with different intensities, color monitors can create an unlimited number of colors. In practice, however, the real number of colors that any monitor can display is controlled by thevideo adapter.[5] Aspeakeris an output device that produces sound through an oscillatingtransducercalled a driver. The equivalent input device is amicrophone. Speakers are plugged into a computer'ssound cardvia a myriad of interfaces, such as aphone connectorfor analog audio, orSPDIFfor digital audio. While speakers can be connected through cables,wireless speakersare connected to the host device through radio technology such asBluetooth. Speakers are most often used in pairs, which allows the speaker system to producepositional audio. When more than one pair is used, it is referred to assurround sound. Certain models of computers includes a built-in speaker, which may sacrifice audio quality in favor of size. For example, the built-in speaker of a smartphone allows the users to listen to media without attaching an external speaker. The interface between an auditory output device and a computer is thesound card. Sound cards may beincludedon a computer'smotherboard, installed as anexpansion card, or as adesktop unit.[6][7] The sound card may offer either an analog ordigitaloutput. In the latter case, output is often transmitted usingSPDIFas either an electrical signal or anopticalinterface known asTOSLINK. Digital outputs are then decoded by anAV receiver. In the case of wireless audio, the computer merely transmits aradio signal, and responsibility of decoding and output is shifted to the speaker. While speakers can be used for any purpose, there arecomputer speakerswhich are built for computer use. These speakers are designed to sit on a desk, and as such, cannot be as large as conventional speakers.[8] Computer speakers may be powered viaUSB, and are most often connected through a 3.5mm phone connector. ThePC speakeris a simple loudspeaker built intoIBM PCcompatible computers. Unlike a speaker used with a sound card, the PC speaker is only meant to producesquare wavesto produce sounds such asbeeping. Modern computers utilize apiezoelectric buzzeror a small speaker as the PC speaker. PC speakers are used duringPower-on self-testto identify errors during the computer's boot process, without needing a video output device to be present and functional. AStudio monitoris a speaker used in astudioenvironment. These speakers optimize for accuracy.[9]A monitor produces a flat (linear) frequency response which does not emphasize or de-emphasize of particular frequencies. Headphones,earphones, andearpiecesare a kind of speaker which is supported either on the user's head, or the user's ear. Unlike a speaker, headphones are not meant to be audible to people nearby, which suits them for use in thepublic,officeor other quiet environments. Noise-cancelling headphonesare built withambient noise reductioncapabilities which may employactive noise cancelling. Loudspeakers are composed of several components within anenclosure, such as severaldrivers,active amplifiers,crossovers, and other electronics. Multiple drivers are used to reproduce the full frequencyrange of human hearing, withtweetersproducing high pitches andwoofersproducing low pitches.Full-range speakersuse only one driver to produce as much of a frequency response as possible.[10] WhileHi-Fispeakers attempt to produce high quality sound, computer speakers may compromise on these aspects due to their limited size and to be inexpensive, and the latter often uses full-range speakers as a result.[8] Arefreshable braille displayoutputs braille characters through the use of pins raised out of holes on its surface. It is ordinarily used byvisually-impairedindividuals as an alternative to ascreen reader.[11] Haptic technologyinvolves the use of vibration and other motion to induce a sense of touch.[12]Haptic technology was introduced in the late 1990s for use ingame controllers, to provide tactile feedback while a user is playing a video game. Haptic feedback has seen further uses in the automotive field,aircraft simulationsystems, andbrain-computer interfaces.[13][14] In mobile devices,Appleadded haptic technology in various devices, marketed as 3D Touch andForce Touch. In this form, several devices could sense the amount of force exerted on its touchscreen, whileMacBookscould sense two levels of force on itstouchpad, which will produce a haptic sensation.[15] Aprinteris a device that outputs data to be put on a physical item, usually a piece ofpaper. Printers operate by transferring ink onto this medium in the form of the image received from the host. Early printers could only print text, but later developments allowed printing of graphics. Modern printers can receive data in multiple forms likevector graphics, as animage, a program written in apage description language, or a string of characters. Multiple types of printers exist: Aplotteris a type of printer used to printvector graphics. Instead of drawing pixels onto the printing medium, the plotter draws lines, which may be done with awriting implementsuch as a pencil or pen.[16] Ateleprinterorteletypewriter(TTY) is a type of printer that is meant for sending and receiving messages. Before displays were used to display data visually, early computers would only have a teleprinter for use to access thesystem console. As the operator would enter commands into its keyboard, the teleprinter would output the results onto a piece of paper. The teleprinter would ultimately be succeeded by acomputer terminal, which had a display instead of a printer. A computer can still function without an output device, as is commonly done withservers, where the primary interaction is typically over a data network. A number of protocols exist over serial ports or LAN cables to determine operational status, and to gain control over low-level configuration from a remote location without having a local display device. If the server is configured with a video output, it is often possible to connect a temporary display device for maintenance or administration purposes while the server continues to operate normally; sometimes several servers are multiplexed to a single display device though aKVM switchor equivalent. Some methods to use remote systems are:	https://en.wikipedia.org/wiki/Output_device
This is alist of university networks, showing formalized cooperations among institutions of tertiary education.	https://en.wikipedia.org/wiki/List_of_university_networks
Nettwerk Music Groupis an independent record label founded in 1984.[1][2] The Vancouver-based company was created by principalsTerry McBrideand Mark Jowett[2]as a record label to distribute recordings by the bandMoev, but the label expanded in Canada and internationally.[2]Initially specializing inelectronic musicincludingalternative danceandindustrial,[2]the label expanded its roster to includepop,rockand numerous singer-songwriters in the late 1980s and 1990s. Early artists includedColdplay,Sarah McLachlan, andBarenaked Ladies. In 2023, Nettwerk recapitalized to invest in catalog acquisitions and artist investments.[3]The label was named in Billboard’s Indie Power Players list in 2024.[4] In 1984,Terry McBrideand his friendMark Jowettattended — and both dropped out of — the University of British Columbia. McBride had studied civil engineering while Jowett took classes in creative writing, theater and English. The two met at a house party where Jowett's electronic music bandMoevwas performing.[5] Once out of college, McBride began managing Moev, for whom Jowett played guitar. Moev was signed to Go Records, a small San Francisco label that went bankrupt, leaving the band without distribution.[6]They'd spend time at his small apartment with friends such as the members of the electro-industrial bandSkinny Puppy, and soon he and Jowett starting putting out their records, along with Moev's andThe Grapes of Wrath.[7] McBride had previously started a label, Noetix, and though it was unsuccessful, he and Jowett were willing to give the record business another try. The company officially opened its doors in 1985. Their first release was The Grapes of Wrath'sself-titled EPfollowed by their full-length,September Bowl of Green. It piqued the attention ofCapitol Records, and paved the way for a distribution deal for the band and Nettwerk as a label in 1986.[8]Also in 1986, Nettwerk brought on Ric Arboit as a third partner and managing director.[9] Despite having an eclectic initial roster of artists,[6]Nettwerk gained a reputation as anindustrial dancelabel, an assumption bolstered by the label's roster of homegrown and licensed industrial acts including Skinny Puppy,Severed Heads,SPK, Manufacture, andSingle Gun Theory. On this point, George Maniatis, one of the label's early promotion managers, stated:"'Remission' (Skinny Puppy's mini-album), which was one of our first releases, grabbed everybody by the you-know-whats... Because of it, everybody assumed we were just industrial dance. But we never set out in that direction — It's just that they hit first."[10] Regardless of intent, the industrial dance and electronic genres proved lucrative and resulted in many international cross-licensing deals. Among them: Belgium'sPlay It Again Samlabel running the Nettwerk Europe imprint in exchange for Nettwerk licensingFront 242in Canada; licensingTackhead's North American distribution rights from England's On-U Sound; and cross-licensing with Australia'sVolitionlabel which brought Severed Heads and Single Gun Theory to North America.[10]Cross-licensing, including distribution through the majors (Capitol for Skinny Puppy andAtlanticfor Moev), and respectable club chart performances (including singles by Manufacture, Severed Heads, and Moev) all contributed to significant visibility and growth for the label at the close of the 1980s.[9] The label's reputation as a strictly electronic dance imprint would soon change. At a show in Halifax, McBride met nineteen-year-old singer-songwriter namedSarah McLachlan[11]– he'd been introduced to her music through Jowett, and tried to recruit her to front Moev. Her parents initially rejected the idea, saying she was too young,[11]but by then she had her moved out of her parents home and rented an apartment down the street while in her first year of art school. McBride offered McLachlan a five-record deal, and she agreed, saying “Ok. Sure. Why not?"[12] At this point, McBride and Jowett had moved Nettwerk into a new office, and McLachlan relocated toVancouverto write, finishing her debut,Touch, in 1988. The first single, "Vox", was a hit, and led to her signing a worldwide deal withArista Records(Nettwerk retained her for Canada). She followed up withSolacein 1991 andFumbling Towards Ecstasyin 1993.Surfacingin 1997 contained two hit singles: "Building a Mystery" and "I Will Remember You", and winning twoGrammy Awards. In 1994, Nettwerk switched its US distribution from Capitol–EMI toSony Music, laterSony BMG. The distribution in Canada remained with EMI until end of 2005, when in 2006, distribution was handled through Sony BMG, later Sony Music in Canada until 2019. Presently, distribution in the US is through AMPED Distribution. Lilith Fairwas initially McLachlan's idea;[13]she was tired of the standard touring, and wanted to do something different, something inventive. Though McBride was resistant at first, he pushed forward, and they assembled a lineup that they then were told was "suicidal":Paula Cole,Aimee Mann,Patti Smith,Lisa Loeband McLachlan to close.[14]It was a success, and the next summer they launched a touring version; it grossed $16 million, a large portion of which was donated to women's charities.[13]Founded by McLachlan, McBride, Nettwerk co-ownerDan Fraserand New York talent agentMarty Diamond, Lilith Fair was the top-grossing festival tour of 1997 and ranked 16th among the year's Top 100 Tours. In 1998, Lilith Fair grossed just over $6 million and remained the top-grossing summer concert package tour of the season.[15] Nettwerk then signedBarenaked Ladies, at the time viewed as a novelty act.[16]After steady radio promotion, McBride booked the band for a show atCity Hall PlazainBostonto launch their albumStunt.[17]The concert drew 80,000 fans, and the first single, "One Week", reached number one on the charts, also earning the band aGrammynomination and aJuno Awardfor Best Pop Album. They have since gone on to sell over 10 million albums. Nettwerk brought onDidoin 1999, as well asSum 41.Avril Lavignewas sixteen when she walked into the Nettwerk offices; Arista had sent her to McBride, hoping to figure out what to make of her.[18]Though Lavigne would release her records through Arista, she continued with Nettwerk for her management.[19] In 2000,EMIdecided against a North American release forColdplay's debut albumParachutes, which was distributed by subsidiaryParlophonein the United Kingdom. This led Nettwerk to pick up the album and make it available in Canada and the United States. Nettwerk embraced new digital formats.[20]McBride studied reports showing the sea change in fan preference, and realized that he'd rather cater to the growing MP3 culture rather than work against it. In 2005, Nettmusic became one of the first major music companies to sell MP3s free of DRM (digital rights management),[21]and supported the consumer case in the battle against theRecording Industry Association of America. Nettwerk has offered to pay the legal fees of a teenager in Texas who is being sued for downloading songs.[22] At the same time, Nettwerk continued to focus on other new, innovative and both artist-and-fan friendly models. McBride conceived of a concept he called "collapsed copyright", set to revolve around a new business model that empowered artists themselves and not just the corporations. The premise allowed artists to release music under their own label (therefore retaining the intellectual property), marketed and promoted through Nettwerk.[23] On June 9, 2010, Nettwerk announced that for its distribution and marketing in the United States, it would depart from Sony Music and its catalogue would now be distributed byWMG'sAlternative Distribution Alliance.[24]In 2013, Nettwerk raised $10.25 million in equity financing to sign artists and purchase catalogs.[25] In July 2016, Nettwerk sold its publishing catalog toKobaltInvestment Fund, an independent investment fund established in 2011.[26] In September 2017, Nettwerk Records announced that The Ballroom Thieves joined the label roster.[27] In 2008, Nettwerk founder Terry McBride revived a retired sub-label of Nettwerk calledNutone Records, with the objective of releasing devotional, chant and world music. He also launched a chain of wellness centers in Canada called YYoga.[28]	https://en.wikipedia.org/wiki/Nettwerk
Netzwerkis theGermanword for "network". It may also refer to:	https://en.wikipedia.org/wiki/Netzwerk_(disambiguation)
The following tables compare general and technical information for a number offile systems. Note that in addition to the below table, block capabilities can be implemented below the file system layer in Linux (LVM, integritysetup,cryptsetup) or Windows (Volume Shadow Copy Service,SECURITY), etc. "Online" and "offline" are synonymous with "mounted" and "not mounted". Experimental port available to 2.6.32 and later[75][76] While storage devices usually have their size expressed in powers of 10 (for instance a 1TBSolid State Drive will contain at least 1,000,000,000,000 (1012, 10004) bytes), filesystem limits are invariably powers of 2, so usually expressed with IEC prefixes. For instance, a 1TiBlimit means 240, 10244bytes. Approximations (rounding down) using power of 10 are also given below to clarify. InPOSIXnamespace: anyUTF-16code unit (case-sensitive) except/as well asNUL[115] InPOSIXnamespace: anyUTF-16code unit (case-sensitive) except/as well asNUL[117][118]	https://en.wikipedia.org/wiki/Comparison_of_file_systems
Computer data storageordigital data storageis a technology consisting ofcomputercomponents andrecording mediathat are used to retaindigital data. It is a core function and fundamental component of computers.[1]: 15–16 Thecentral processing unit(CPU) of a computer is what manipulates data by performing computations. In practice, almost all computers use astorage hierarchy,[1]: 468–473which puts fast but expensive and small storage options close to the CPU and slower but less expensive and larger options further away. Generally, the fast[a]technologies are referred to as "memory", while slower persistent technologies are referred to as "storage". Even the first computer designs,Charles Babbage'sAnalytical EngineandPercy Ludgate's Analytical Machine, clearly distinguished between processing and memory (Babbage stored numbers as rotations of gears, while Ludgate stored numbers as displacements of rods in shuttles). This distinction was extended in theVon Neumann architecture, where the CPU consists of two main parts: Thecontrol unitand thearithmetic logic unit(ALU). The former controls the flow of data between the CPU and memory, while the latter performs arithmetic andlogical operationson data. Without a significant amount of memory, a computer would merely be able to perform fixed operations and immediately output the result. It would have to be reconfigured to change its behavior. This is acceptable for devices such as deskcalculators,digital signal processors, and other specialized devices.Von Neumannmachines differ in having a memory in which they store their operatinginstructionsand data.[1]: 20Such computers are more versatile in that they do not need to have their hardware reconfigured for each new program, but can simply bereprogrammedwith new in-memory instructions; they also tend to be simpler to design, in that a relatively simple processor may keepstatebetween successive computations to build up complex procedural results. Most modern computers are von Neumann machines. A moderndigital computerrepresentsdatausing thebinary numeral system. Text, numbers, pictures, audio, and nearly any other form of information can be converted into a string ofbits, or binary digits, each of which has a value of 0 or 1. The most common unit of storage is thebyte, equal to 8 bits. A piece of information can be handled by any computer or device whose storage space is large enough to accommodatethe binary representation of the piece of information, or simplydata. For example, thecomplete works of Shakespeare, about 1250 pages in print, can be stored in about fivemegabytes(40 million bits) with one byte per character. Data areencodedby assigning a bit pattern to eachcharacter,digit, ormultimediaobject. Many standards exist for encoding (e.g.character encodingslikeASCII, image encodings likeJPEG, and video encodings likeMPEG-4). By adding bits to each encoded unit, redundancy allows the computer to detect errors in coded data and correct them based on mathematical algorithms. Errors generally occur in low probabilities due torandombit value flipping, or "physical bit fatigue", loss of the physical bit in the storage of its ability to maintain a distinguishable value (0 or 1), or due to errors in inter or intra-computer communication. A randombit flip(e.g. due to randomradiation) is typically corrected upon detection. A bit or a group of malfunctioning physical bits (the specific defective bit is not always known; group definition depends on the specific storage device) is typically automatically fenced out, taken out of use by the device, and replaced with another functioning equivalent group in the device, where the corrected bit values are restored (if possible). Thecyclic redundancy check(CRC) method is typically used in communications and storage forerror detection. A detected error is then retried. Data compressionmethods allow in many cases (such as a database) to represent a string of bits by a shorter bit string ("compress") and reconstruct the original string ("decompress") when needed. This utilizes substantially less storage (tens of percent) for many types of data at the cost of more computation (compress and decompress when needed). Analysis of the trade-off between storage cost saving and costs of related computations and possible delays in data availability is done before deciding whether to keep certain data compressed or not. Forsecurity reasons, certain types of data (e.g.credit cardinformation) may be keptencryptedin storage to prevent the possibility of unauthorized information reconstruction from chunks of storage snapshots. Generally, the lower a storage is in the hierarchy, the lesser itsbandwidthand the greater its accesslatencyis from the CPU. This traditional division of storage to primary, secondary, tertiary, and off-line storage is also guided by cost per bit. In contemporary usage,memoryis usually fast but temporarysemiconductorread-write memory, typicallyDRAM(dynamic RAM) or other such devices.Storageconsists of storage devices and their media not directly accessible by theCPU(secondaryortertiary storage), typicallyhard disk drives,optical discdrives, and other devices slower than RAM butnon-volatile(retaining contents when powered down).[2] Historically,memoryhas, depending on technology, been calledcentral memory,core memory,core storage,drum,main memory,real storage, orinternal memory. Meanwhile, slower persistent storage devices have been referred to assecondary storage,external memory, orauxiliary/peripheral storage. Primary storage(also known asmain memory,internal memory, orprime memory), often referred to simply asmemory, is the only one directly accessible to the CPU. The CPU continuously reads instructions stored there and executes them as required. Any data actively operated on is also stored there in a uniform manner. Historically,early computersuseddelay lines,Williams tubes, or rotatingmagnetic drumsas primary storage. By 1954, those unreliable methods were mostly replaced bymagnetic-core memory. Core memory remained dominant until the 1970s, when advances inintegrated circuittechnology allowedsemiconductor memoryto become economically competitive. This led to modernrandom-access memory(RAM). It is small-sized, light, but quite expensive at the same time. The particular types of RAM used for primary storage arevolatile, meaning that they lose the information when not powered. Besides storing opened programs, it serves asdisk cacheandwrite bufferto improve both reading and writing performance. Operating systems borrow RAM capacity for caching so long as it's not needed by running software.[3]Spare memory can be utilized asRAM drivefor temporary high-speed data storage. As shown in the diagram, traditionally there are two more sub-layers of the primary storage, besides main large-capacity RAM: Main memory is directly or indirectly connected to the central processing unit via amemory bus. It is actually two buses (not on the diagram): anaddress busand adata bus. The CPU firstly sends a number through an address bus, a number calledmemory address, that indicates the desired location of data. Then it reads or writes the data in thememory cellsusing the data bus. Additionally, amemory management unit(MMU) is a small device between CPU and RAM recalculating the actual memory address, for example to provide an abstraction ofvirtual memoryor other tasks. As the RAM types used for primary storage are volatile (uninitialized at start up), a computer containing only such storage would not have a source to read instructions from, in order to start the computer. Hence,non-volatile primary storagecontaining a small startup program (BIOS) is used tobootstrapthe computer, that is, to read a larger program from non-volatilesecondarystorage to RAM and start to execute it. A non-volatile technology used for this purpose is called ROM, forread-only memory(the terminology may be somewhat confusing as most ROM types are also capable ofrandom access). Many types of "ROM" are not literallyread only, as updates to them are possible; however it is slow and memory must be erased in large portions before it can be re-written. Someembedded systemsrun programs directly from ROM (or similar), because such programs are rarely changed. Standard computers do not store non-rudimentary programs in ROM, and rather, use large capacities of secondary storage, which is non-volatile as well, and not as costly. Recently,primary storageandsecondary storagein some uses refer to what was historically called, respectively,secondary storageandtertiary storage.[4] The primary storage, includingROM,EEPROM,NOR flash, andRAM,[5]are usuallybyte-addressable. Secondary storage(also known asexternal memoryorauxiliary storage) differs from primary storage in that it is not directly accessible by the CPU. The computer usually uses its input/output channels to access secondary storage and transfer the desired data to primary storage. Secondary storage is non-volatile (retaining data when its power is shut off). Modern computer systems typically have two orders of magnitude more secondary storage than primary storage because secondary storage is less expensive. In modern computers,hard disk drives(HDDs) orsolid-state drives(SSDs) are usually used as secondary storage. Theaccess timeper byte for HDDs or SSDs is typically measured inmilliseconds(thousandths of a second), while the access time per byte for primary storage is measured innanoseconds(billionths of a second). Thus, secondary storage is significantly slower than primary storage. Rotatingoptical storagedevices, such asCDandDVDdrives, have even longer access times. Other examples of secondary storage technologies includeUSB flash drives,floppy disks,magnetic tape,paper tape,punched cards, andRAM disks. Once thedisk read/write headon HDDs reaches the proper placement and the data, subsequent data on the track are very fast to access. To reduce the seek time and rotational latency, data are transferred to and from disks in large contiguous blocks. Sequential or block access on disks is orders of magnitude faster than random access, and many sophisticated paradigms have been developed to design efficient algorithms based on sequential and block access. Another way to reduce the I/O bottleneck is to use multiple disks in parallel to increase the bandwidth between primary and secondary memory.[6] Secondary storage is often formatted according to afile systemformat, which provides the abstraction necessary to organize data intofilesanddirectories, while also providingmetadatadescribing the owner of a certain file, the access time, the access permissions, and other information. Most computeroperating systemsuse the concept ofvirtual memory, allowing the utilization of more primary storage capacity than is physically available in the system. As the primary memory fills up, the system moves the least-used chunks (pages) to a swap file or page file on secondary storage, retrieving them later when needed. If a lot of pages are moved to slower secondary storage, the system performance is degraded. The secondary storage, includingHDD,ODDandSSD, are usually block-addressable. Tertiary storageortertiary memory[7]is a level below secondary storage. Typically, it involves a robotic mechanism which willmount(insert) anddismountremovable mass storage media into a storage device according to the system's demands; such data are often copied to secondary storage before use. It is primarily used for archiving rarely accessed information since it is much slower than secondary storage (e.g. 5–60 seconds vs. 1–10 milliseconds). This is primarily useful for extraordinarily large data stores, accessed without human operators. Typical examples includetape librariesandoptical jukeboxes. When a computer needs to read information from the tertiary storage, it will first consult a catalogdatabaseto determine which tape or disc contains the information. Next, the computer will instruct arobotic armto fetch the medium and place it in a drive. When the computer has finished reading the information, the robotic arm will return the medium to its place in the library. Tertiary storage is also known asnearline storagebecause it is "near to online". The formal distinction between online, nearline, and offline storage is:[8] For example, always-on spinning hard disk drives are online storage, while spinning drives that spin down automatically, such as in massive arrays of idle disks (MAID), are nearline storage. Removable media such astape cartridgesthat can be automatically loaded, as intape libraries, are nearline storage, while tape cartridges that must be manually loaded are offline storage. Off-line storageis computer data storage on a medium or a device that is not under the control of aprocessing unit.[9]The medium is recorded, usually in a secondary or tertiary storage device, and then physically removed or disconnected. It must be inserted or connected by a human operator before a computer can access it again. Unlike tertiary storage, it cannot be accessed without human interaction. Off-linestorage is used totransfer informationsince the detached medium can easily be physically transported. Additionally, it is useful for cases of disaster, where, for example, a fire destroys the original data, a medium in a remote location will be unaffected, enablingdisaster recovery. Off-line storage increases generalinformation securitysince it is physically inaccessible from a computer, and data confidentiality or integrity cannot be affected by computer-based attack techniques. Also, if the information stored for archival purposes is rarely accessed, off-line storage is less expensive than tertiary storage. In modern personal computers, most secondary and tertiary storage media are also used for off-line storage. Optical discs and flash memory devices are the most popular, and to a much lesser extent removable hard disk drives; older examples include floppy disks and Zip disks. In enterprise uses, magnetic tape cartridges are predominant; older examples include open-reel magnetic tape and punched cards. Storage technologies at all levels of the storage hierarchy can be differentiated by evaluating certain core characteristics as well as measuring characteristics specific to a particular implementation. These core characteristics are volatility, mutability, accessibility, and addressability. For any particular implementation of any storage technology, the characteristics worth measuring are capacity and performance. Non-volatile memoryretains the stored information even if not constantly supplied with electric power. It is suitable for long-term storage of information.Volatile memoryrequires constant power to maintain the stored information. The fastest memory technologies are volatile ones, although that is not a universal rule. Since the primary storage is required to be very fast, it predominantly uses volatile memory. Dynamic random-access memoryis a form of volatile memory that also requires the stored information to be periodically reread and rewritten, orrefreshed, otherwise it would vanish.Static random-access memoryis a form of volatile memory similar to DRAM with the exception that it never needs to be refreshed as long as power is applied; it loses its content when the power supply is lost. Anuninterruptible power supply(UPS) can be used to give a computer a brief window of time to move information from primary volatile storage into non-volatile storage before the batteries are exhausted. Some systems, for exampleEMC Symmetrix, have integrated batteries that maintain volatile storage for several minutes. Utilities such ashdparmandsarcan be used to measure IO performance in Linux. Full disk encryption,volume and virtual disk encryption, andor file/folder encryptionis readily available for most storage devices.[17] Hardware memory encryption is available in Intel Architecture, supporting Total Memory Encryption (TME) and page granular memory encryption with multiple keys (MKTME).[18][19]and inSPARCM7 generation since October 2015.[20] Distinct types of data storage have different points of failure and various methods ofpredictive failure analysis. Vulnerabilities that can instantly lead to total loss arehead crashingon mechanical hard drives andfailure of electronic componentson flash storage. Impending failure onhard disk drivesis estimable using S.M.A.R.T. diagnostic data that includes thehours of operationand the count of spin-ups, though its reliability is disputed.[21] Flash storage may experience downspiking transfer rates as a result of accumulating errors, which theflash memory controllerattempts to correct. The health ofoptical mediacan be determined bymeasuring correctable minor errors, of which high counts signify deteriorating and/or low-quality media. Too many consecutive minor errors can lead to data corruption. Not all vendors and models ofoptical drivessupport error scanning.[22] As of 2011[update], the most commonly used data storage media are semiconductor, magnetic, and optical, while paper still sees some limited usage. Some other fundamental storage technologies, such as all-flash arrays (AFAs) are proposed for development. Semiconductor memoryusessemiconductor-basedintegrated circuit(IC) chips to store information. Data are typically stored inmetal–oxide–semiconductor(MOS)memory cells. A semiconductor memory chip may contain millions of memory cells, consisting of tinyMOS field-effect transistors(MOSFETs) and/orMOS capacitors. Bothvolatileandnon-volatileforms of semiconductor memory exist, the former using standard MOSFETs and the latter usingfloating-gate MOSFETs. In modern computers, primary storage almost exclusively consists of dynamic volatile semiconductorrandom-access memory(RAM), particularlydynamic random-access memory(DRAM). Since the turn of the century, a type of non-volatilefloating-gatesemiconductor memory known asflash memoryhas steadily gained share as off-line storage for home computers. Non-volatile semiconductor memory is also used for secondary storage in various advanced electronic devices and specialized computers that are designed for them. As early as 2006,notebookanddesktop computermanufacturers started using flash-basedsolid-state drives(SSDs) as default configuration options for the secondary storage either in addition to or instead of the more traditional HDD.[23][24][25][26][27] Magnetic storageuses different patterns ofmagnetizationon amagneticallycoated surface to store information. Magnetic storage isnon-volatile. The information is accessed using one or more read/write heads which may contain one or more recording transducers. A read/write head only covers a part of the surface so that the head or medium or both must be moved relative to another in order to access data. In modern computers, magnetic storage will take these forms: In early computers, magnetic storage was also used as: Magnetic storage does not have a definite limit of rewriting cycles like flash storage and re-writeable optical media, as altering magnetic fields causes no physical wear. Rather, their life span is limited by mechanical parts.[28][29] Optical storage, the typicaloptical disc, stores information in deformities on the surface of a circular disc and reads this information by illuminating the surface with alaser diodeand observing the reflection. Optical disc storage isnon-volatile. The deformities may be permanent (read only media), formed once (write once media) or reversible (recordable or read/write media). The following forms are in common use as of 2009[update]:[30] Magneto-optical disc storageis optical disc storage where the magnetic state on aferromagneticsurface stores information. The information is read optically and written by combining magnetic and optical methods. Magneto-optical disc storage isnon-volatile,sequential access, slow write, fast read storage used for tertiary and off-line storage. 3D optical data storagehas also been proposed. Light induced magnetization melting in magnetic photoconductors has also been proposed for high-speed low-energy consumption magneto-optical storage.[31] Paper data storage, typically in the form ofpaper tapeorpunched cards, has long been used to store information for automatic processing, particularly before general-purpose computers existed. Information was recorded by punching holes into the paper or cardboard medium and was read mechanically (or later optically) to determine whether a particular location on the medium was solid or contained a hole.Barcodesmake it possible for objects that are sold or transported to have some computer-readable information securely attached. Relatively small amounts of digital data (compared to other digital data storage) may be backed up on paper as amatrix barcodefor very long-term storage, as the longevity of paper typically exceeds even magnetic data storage.[32][33] While a group of bits malfunction may be resolved by error detection and correction mechanisms (see above), storage device malfunction requires different solutions. The following solutions are commonly used and valid for most storage devices: Device mirroring and typical RAID are designed to handle a single device failure in the RAID group of devices. However, if a second failure occurs before the RAID group is completely repaired from the first failure, then data can be lost. The probability of a single failure is typically small. Thus the probability of two failures in the same RAID group in time proximity is much smaller (approximately the probability squared, i.e., multiplied by itself). If a database cannot tolerate even such a smaller probability of data loss, then the RAID group itself is replicated (mirrored). In many cases such mirroring is done geographically remotely, in a different storage array, to handle recovery from disasters (see disaster recovery above). A secondary or tertiary storage may connect to a computer utilizingcomputer networks. This concept does not pertain to the primary storage, which is shared between multiple processors to a lesser degree. Large quantities of individual magnetic tapes, and optical or magneto-optical discs may be stored in robotic tertiary storage devices. In tape storage field they are known astape libraries, and in optical storage fieldoptical jukeboxes, or optical disk libraries per analogy. The smallest forms of either technology containing just one drive device are referred to asautoloadersorautochangers. Robotic-access storage devices may have a number of slots, each holding individual media, and usually one or more picking robots that traverse the slots and load media to built-in drives. The arrangement of the slots and picking devices affects performance. Important characteristics of such storage are possible expansion options: adding slots, modules, drives, robots. Tape libraries may have from 10 to more than 100,000 slots, and provideterabytesorpetabytesof near-line information. Optical jukeboxes are somewhat smaller solutions, up to 1,000 slots. Robotic storage is used forbackups, and for high-capacity archives in imaging, medical, and video industries.Hierarchical storage managementis a most known archiving strategy of automaticallymigratinglong-unused files from fast hard disk storage to libraries or jukeboxes. If the files are needed, they areretrievedback to disk. This article incorporatespublic domain materialfromFederal Standard 1037C.General Services Administration. Archived fromthe originalon 22 January 2022.	https://en.wikipedia.org/wiki/Computer_data_storage
Adisk quotais a limit set by asystem administratorthat restricts certain aspects offile systemusage on modernoperating systems. The function of using disk quotas is to allocate limited disk space in a reasonable way.[1] There are two basic types of disk quotas. The first, known as ausage quotaorblock quota, limits the amount of disk space that can be used. The second, known as afile quotaorinode quota, limits the number of files and directories that can be created. In addition, administrators usually define a warning level, orsoft quota, at which users are informed they are nearing their limit, that is less than the effective limit, orhard quota. There may also be a smallgrace interval, which allows users to temporarily violate their quotas by certain amounts if necessary. Disk quotas are typically implemented on a per-user or per-group basis. That is, asystem administratordefines a usage or file quota specific to a certain user or group. In some filesystems (e.g.ext4,XFS,f2fs,ZFS,Lustre) it is also possible to also define block and inode quota limits for a particular project or directory, by adding a project ID to files that directory tree and defining quota limits for the project ID. In doing so, an administrator can prevent one user from consuming an entire file system's resources, or create a system of tiered access, whereby users can have different levels of restriction. This is used, for example, byweb hostingcompanies to provide different levels of service based upon the needs and means of individual clients. In most cases, quotas are also specific to individual file systems. Should an administrator want to limit the usage of a specific user on all file systems, a separate quota would have to be specified on each. When a soft quota is violated, the system normally sends the user (and sometimes the administrator as well) some sort of message. No further action is typically taken. Some systems prevent disk write operations that would result in hard quota violations from completing successfully, while others wait until the quota has been physically violated before denying write requests. The user is typically notified through the failed write operation error messages generated by the violating applications, while the administrator is almost always sent a notification as well. Disk quotas are supported by most modern operating systems, includingUnix-likesystems, such asAIX(usingJFSorJFS2filesystem),Linux(usingext3, ext4, ext2, XFS (integrated support) among other filesystems),Solaris(usingUFSorZFS),Microsoft Windowsstarting withWindows 2000,Novell NetWare,VMS, and others. The method of administration for disk quotas varies between each of these operating systems. Unix-like systems typically provide aquotacommand for both administration and monitoring; graphical front-ends to the command may also be used. Unix and Unix-like operating systems frequently feature agrace periodwhere users may exceed their quota limits for a brief period of time. Windows 2000 and newer versions use the "Quota" tab of the disk properties dialog. Other systems provide their own quota management utilities.	https://en.wikipedia.org/wiki/Disk_quota
The following lists identify, characterize, and link to more thorough information onfile systems. Many olderoperating systemssupport only their one "native" file system, which does not bear any name apart from the name of the operating system itself. Disk file systems are usually block-oriented. Files in a block-oriented file system are sequences of blocks, often featuring fully random-access read, write, and modify operations. These file systems have built-in checksumming and either mirroring or parity for extra redundancy on one or several block devices: Solid state media, such asflash memory, are similar to disks in their interfaces, but have different problems. At low level, they require special handling such aswear levelingand differenterror detection and correctionalgorithms. Typically a device such as asolid-state drivehandles such operations internally and therefore a regular file system can be used. However, for certain specialized installations (embedded systems, industrial applications) a file system optimized for plain flash memory is advantageous. Inrecord-oriented file systemsfiles are stored as a collection ofrecords. They are typically associated withmainframeandminicomputeroperating systems. Programs read and write whole records, rather than bytes or arbitrary byte ranges, and can seek to a record boundary but not within records. The more sophisticated record-oriented file systems have more in common with simpledatabasesthan with other file systems. Shared-disk file systems (also calledshared-storage file systems,SAN file system,Clustered file systemor evencluster file systems) are primarily used in astorage area networkwhere all nodes directly access theblock storagewhere the file system is located. This makes it possible for nodes to fail without affecting access to the file system from the other nodes. Shared-disk file systems are normally used in ahigh-availability clustertogether with storage on hardwareRAID. Shared-disk file systems normally do not scale over 64 or 128 nodes. Shared-disk file systems may besymmetricwheremetadatais distributed among the nodes orasymmetricwith centralizedmetadataservers. Distributed file systemsare also called network file systems. Many implementations have been made, they are location dependent and they haveaccess control lists(ACLs), unless otherwise stated below. Distributedfault-tolerantreplication of data between nodes (between servers or servers/clients) forhigh availabilityandoffline(disconnected) operation. Distributedparallelfile systems stripe data over multiple servers for high performance. They are normally used inhigh-performance computing (HPC). Some of the distributed parallel file systems use anobject storage device(OSD) (in Lustre called OST) for chunks of data together with centralizedmetadataservers. Distributed file systems, which also areparallelandfault tolerant, stripe and replicate data over multiple servers for high performance and to maintaindata integrity. Even if a server fails no data is lost. The file systems are used in bothhigh-performance computing (HPC)andhigh-availability clusters. All file systems listed here focus onhigh availability,scalabilityand high performance unless otherwise stated below. In development: Some of these may be calledcooperative storage cloud. These are not really file systems; they allow access to file systems from an operating system standpoint.	https://en.wikipedia.org/wiki/List_of_file_systems
This is a list of theshellcommandsof the most recent version of the Portable Operating System Interface (POSIX) –IEEEStd 1003.1-2024 which is part of theSingle UNIX Specification(SUS). These commands are implemented in many shells on modernUnix,Unix-likeand otheroperating systems. This list does not cover commands for all versions of Unix and Unix-like shells nor other versions of POSIX.	https://en.wikipedia.org/wiki/List_of_Unix_commands
Incomputing, adirectory structureis the way anoperating systemarrangesfilesthat are accessible to the user. Files are typically displayed in ahierarchical tree structure. Afilenameis a string used to uniquely identify a file stored on this structure. Before the advent of32-bitoperating systems, file names were typically limited to short names (6 to 14 characters in size). Modern operating systems now typically allow much longer filenames (more than 250 characters perpathnameelement). InCP/M,DOS,Windows, andOS/2, the root directory is "drive:\", for example on modern systems, the root directory is usually "C:\". The directory separator is usually a "\", but many operating systems also internally recognize a "/". Physical and virtual drives are named by a drive letter, as opposed to being combined as one.[1]This means that there is no "formal" root directory, but rather that there are independent root directories on each drive. However, it is possible to combine two drives into one virtual drive letter, by setting a hard drive into aRAIDsetting of 0.[2] The following folders may appear in the root of aboot partition. \PerfLogs \Program Files 64-bit architecture:64-bit programs are installed in this folder. \Program Files (x86) \ProgramData(hidden) \Users \Windows Although Unix does not have a single standard for directory structures, in most implementations, files and directories appear under the root directory "/", even if they are stored on different physical devices.[8]	https://en.wikipedia.org/wiki/Directory_structure
Incomputing, ashared resource, ornetwork share, is acomputer resourcemade available from onehostto other hosts on acomputer network.[1][2]It is a device or piece of information on a computer that can be remotely accessed from another computer transparently as if it were a resource in the local machine. Network sharing is made possible byinter-process communicationover the network.[2][3] Some examples of shareable resources arecomputer programs,data,storage devices, andprinters. E.g.shared file access(also known asdisk sharingandfolder sharing), shared printer access, shared scanner access, etc. The shared resource is called ashared disk,shared folderorshared document The termfile sharingtraditionally means shared file access, especially in the context of operating systems andLANandIntranetservices, for example in Microsoft Windows documentation.[4]Though, asBitTorrentand similar applications became available in the early 2000s, the termfile sharingincreasingly has become associated withpeer-to-peer file sharingover the Internet. Shared file and printer access require anoperating systemon the client that supports access to resources on a server, an operating system on the server that supports access to its resources from a client, and anapplication layer(in the four or five layerTCP/IP reference model) file sharingprotocolandtransport layerprotocol to provide that shared access. Modern operating systems forpersonal computersincludedistributed file systemsthat support file sharing, while hand-held computing devices sometimes require additional software for shared file access. The most common such file systems and protocols are: The "primary operating system" is the operating system on which the file sharing protocol in question is most commonly used. OnMicrosoft Windows, a network share is provided by the Windows network component "File and Printer Sharing for Microsoft Networks", using Microsoft's SMB (Server Message Block) protocol. Other operating systems might also implement that protocol; for example,Sambais an SMB server running onUnix-likeoperating systems and some other non-MS-DOS/non-Windows operating systems such asOpenVMS. Samba can be used to create network shares which can be accessed, using SMB, from computers runningMicrosoft Windows. An alternative approach is ashared disk file system, where each computer has access to the "native" filesystem on a shared disk drive. Shared resource access can also be implemented withWeb-based Distributed Authoring and Versioning(WebDAV). The share can be accessed by client computers through some naming convention, such asUNC(Universal Naming Convention) used onDOSandWindowsPC computers. This implies that a network share can be addressed according to the following: whereServerComputerNameis theWINSname,DNSname orIP addressof the server computer, andShareNamemay be a folder or file name, or itspath. The shared folder can also be given a ShareName that is different from the folder local name at the server side. For example,\\ServerComputerName\c$usually denotes a drive with drive letterC:on a Windows machine. A shared drive or folder is oftenmappedat the client PC computer, meaning that it is assigned adrive letteron the local PC computer. For example, the drive letterH:is typically used for the user home directory on a central file server. A network share can become a security liability when access to the shared files is gained (often by devious means) by those who should not have access to them. Manycomputer wormshave spread through network shares. Network shares would consume extensive communication capacity in non-broadband network access. Because of that, shared printer and file access is normally prohibited infirewallsfrom computers outside thelocal area networkor enterpriseIntranet. However, by means ofvirtual private networks(VPN), shared resources can securely be made available for certified users outside the local network. A network share is typically made accessible to other users by marking anyfolderor file as shared, or by changing thefile system permissionsor access rights in the properties of the folder. For example, a file or folder may be accessible only to one user (the owner), to system administrators, to a certain group of users to public, i.e. to all logged in users. The exact procedure varies by platform. In operating system editions for homes and small offices, there may be a specialpre-shared folderthat is accessible to all users with a user account and password on the local computer. Network access to the pre-shared folder can be turned on. In the English version of theWindows XP Home Editionoperating system, the preshared folder is namedShared documents, typically with thepathC:\Documents and Settings\All users\Shared documents. InWindows VistaandWindows 7, the pre-shared folder is namedPublic documents, typically with the pathC:\Users\Public\Public documents.[6] In home and small office networks, adecentralizedapproach is often used, where every user may make their local folders and printers available to others. This approach is sometimes denoted aWorkgrouporpeer-to-peernetwork topology, since the same computer may be used as client as well as server. In large enterprise networks, a centralizedfile serverorprint server, sometimes denotedclient–server paradigm, is typically used. A client process on the local user computer takes the initiative to start the communication, while a server process on thefile serverorprint serverremote computer passively waits for requests to start a communication session In very large networks, aStorage Area Network(SAN) approach may be used. Online storageon a server outside the local network is currently an option, especially for homes and small office networks. Shared file access should not be confused with file transfer using thefile transfer protocol(FTP), or theBluetoothIRDAOBject EXchange(OBEX) protocol. Shared access involves automatic synchronization of folder information whenever a folder is changed on the server, and may provide server side file searching, while file transfer is a more rudimentary service.[7] Shared file access is normally considered as a local area network (LAN) service, while FTP is an Internet service. Shared file access is transparent to the user, as if it was a resource in the local file system, and supports a multi-user environment. This includesconcurrency controlorlockingof a remote file while a user is editing it, andfile system permissions. Shared file access involves but should not be confused withfile synchronizationand other information synchronization. Internet-based information synchronization may, for example, use theSyncMLlanguage. Shared file access is based on server-side pushing of folder information, and is normally used over an "always on"Internet socket. File synchronization allows the user to be offline from time to time and is normally based on an agent software that polls synchronized machines at reconnect, and sometimes repeatedly with a certain time interval, to discover differences. Modern operating systems often include a localcacheof remote files, allowingoffline accessand synchronization when reconnected. The first international heterogenous network for resource sharing was the 1973 interconnection of theARPANETwith earlyBritish academic networksthrough the computer science department atUniversity College London(UCL).[8][9][10]	https://en.wikipedia.org/wiki/Shared_resource
Aclustered file system(CFS) is afile systemwhich is shared by being simultaneouslymountedon multipleservers. There are several approaches toclustering, most of which do not employ a clustered file system (onlydirect attached storagefor each node). Clustered file systems can provide features like location-independent addressing and redundancy which improve reliability or reduce the complexity of the other parts of the cluster.Parallel file systemsare a type of clustered file system that spread data across multiple storage nodes, usually for redundancy or performance.[1] Ashared-disk file systemuses astorage area network(SAN) to allow multiple computers to gain direct disk access at theblock level. Access control and translation from file-level operations that applications use to block-level operations used by the SAN must take place on the client node. The most common type of clustered file system, the shared-disk file system – by adding mechanisms forconcurrency control– provides a consistent andserializableview of the file system, avoiding corruption and unintendeddata losseven when multiple clients try to access the same files at the same time. Shared-disk file-systems commonly employ some sort offencingmechanism to prevent data corruption in case of node failures, because an unfenced device can cause data corruption if it loses communication with its sister nodes and tries to access the same information other nodes are accessing. The underlying storage area network may use any of a number of block-level protocols, includingSCSI,iSCSI,HyperSCSI,ATA over Ethernet(AoE),Fibre Channel,network block device, andInfiniBand. There are different architectural approaches to a shared-disk filesystem. Some distribute file information across all the servers in a cluster (fully distributed).[2] Distributed file systemsdo not shareblock level accessto the same storage but use a networkprotocol.[3][4]These are commonly known as network file systems, even though they are not the only file systems that use the network to send data.[5]Distributed file systems can restrict access to the file system depending onaccess listsorcapabilitieson both the servers and the clients, depending on how the protocol is designed. The difference between a distributed file system and adistributed data storeis that a distributed file system allows files to be accessed using the same interfaces and semantics as local files – for example, mounting/unmounting, listing directories, read/write at byte boundaries, system's native permission model. Distributed data stores, by contrast, require using a different API or library and have different semantics (most often those of a database).[6] Distributed file systems may aim for "transparency" in a number of aspects. That is, they aim to be "invisible" to client programs, which "see" a system which is similar to a local file system. Behind the scenes, the distributed file system handles locating files, transporting data, and potentially providing other features listed below. TheIncompatible Timesharing Systemused virtual devices for transparent inter-machine file system access in the 1960s. More file servers were developed in the 1970s. In 1976,Digital Equipment Corporationcreated theFile Access Listener(FAL), an implementation of theData Access Protocolas part ofDECnetPhase II which became the first widely used network file system. In 1984,Sun Microsystemscreated the file system called "Network File System" (NFS) which became the first widely usedInternet Protocolbased network file system.[4]Other notable network file systems areAndrew File System(AFS),Apple Filing Protocol(AFP),NetWare Core Protocol(NCP), andServer Message Block(SMB) which is also known as Common Internet File System (CIFS). In 1986,IBMannounced client and server support for Distributed Data Management Architecture (DDM) for theSystem/36,System/38, and IBM mainframe computers runningCICS. This was followed by the support forIBM Personal Computer,AS/400, IBM mainframe computers under theMVSandVSEoperating systems, andFlexOS. DDM also became the foundation forDistributed Relational Database Architecture, also known as DRDA. There are manypeer-to-peernetwork protocolsfor open-sourcedistributed file systems for cloudor closed-source clustered file systems, e. g.:9P,AFS,Coda,CIFS/SMB,DCE/DFS, WekaFS,[7]Lustre, PanFS,[8]Google File System,Mnet,Chord Project. Network-attached storage (NAS) provides both storage and a file system, like a shared disk file system on top of a storage area network (SAN). NAS typically uses file-based protocols (as opposed to block-based protocols a SAN would use) such asNFS(popular onUNIXsystems), SMB/CIFS (Server Message Block/Common Internet File System) (used with MS Windows systems),AFP(used withApple Macintoshcomputers), orNCP(used withOESandNovell NetWare). The failure of disk hardware or a given storage node in a cluster can create asingle point of failurethat can result indata lossor unavailability.Fault toleranceand high availability can be provided throughdata replicationof one sort or another, so that data remains intact and available despite the failure of any single piece of equipment. For examples, see the lists ofdistributed fault-tolerant file systemsanddistributed parallel fault-tolerant file systems. A commonperformancemeasurementof a clustered file system is the amount of time needed to satisfy service requests. In conventional systems, this time consists of a disk-access time and a small amount ofCPU-processing time. But in a clustered file system, a remote access has additional overhead due to the distributed structure. This includes the time to deliver the request to a server, the time to deliver the response to the client, and for each direction, a CPU overhead of running thecommunication protocolsoftware. Concurrency control becomes an issue when more than one person or client is accessing the same file or block and want to update it. Hence updates to the file from one client should not interfere with access and updates from other clients. This problem is more complex with file systems due to concurrent overlapping writes, where different writers write to overlapping regions of the file concurrently.[9]This problem is usually handled byconcurrency controlorlockingwhich may either be built into the file system or provided by an add-on protocol. IBM mainframes in the 1970s could share physical disks and file systems if each machine had its own channel connection to the drives' control units. In the 1980s,Digital Equipment Corporation'sTOPS-20andOpenVMSclusters (VAX/ALPHA/IA64) included shared disk file systems.[10]	https://en.wikipedia.org/wiki/Distributed_file_system
Distributed Data Management Architecture(DDM) isIBM's open, publishedsoftware architecturefor creating, managing and accessing data on a remote computer. DDM was initially designed to supportrecord-oriented files; it was extended to supporthierarchical directories,stream-oriented files,queues, and system command processing; it was further extended to be the base of IBM'sDistributed Relational Database Architecture(DRDA); and finally, it was extended to supportdata description and conversion. Defined in the period from 1980 to 1993, DDM specifies necessary components, messages, and protocols, all based on the principles ofobject-orientation. DDM is not, in itself, a piece of software; the implementation of DDM takes the form of client and server products. As anopen architecture, products can implement subsets of DDM architecture and products can extend DDM to meet additional requirements. Taken together, DDM products implement adistributed file system. The designers of distributed applications must determine the best placement of the application's programs and data in terms of the quantity and frequency of data to be transmitted, along with data management, security, and timeliness considerations. There are threeclient–server modelsfor the design of distributed applications: The DDM architecture was initially designed to support thefat clientmodel of distributed applications; it also supports whole-file transfers. The DDM architecture provides distributed applications with the following benefits:[1] DDM architecture is a set of specifications for messages and protocols that enable data distributed throughout a network of computers to be managed and accessed.[2] IBM'sSystems Network Architecture(SNA) was initially designed to enable the hierarchical connection of workstations to IBM mainframe computers. The communication networks available at the time were rigidly designed in terms of fixed connections between a mainframe and its suite of workstations, which were under the complete software control of the mainframe computer. Other communications between mainframes was also in terms of fixed connections used by software defined for specific purposes. As communication networks became more flexible and dynamic, genericpeer-to-peercommunications were desirable, in which a program on one computer could initiate and interact with a program on a different computer. When IBM's SNAAdvanced Program to Program Communications(APPC) architecture was defined in the early 1980s, it was also apparent that APPC could be used to provide operating system services on remote computers. An SNA workgroup pursued this idea and outlined several possible distributed services, such as file services, printer services, and system console services, but was unable to initiate product development. APPC software was not yet available on mainframes and, more basically, mainframes were still viewed primarily as stand-alone systems. As a result, work on distributed services was suspended by the SNA work group. Members of the SNA work group from IBM's Rochester, Minnesota development laboratory were convinced that a business case existed for distributed services among the mid-range computer systems produced in Rochester. A primitive form of distributed file services, calledDistributed Data File Facility(DDFF) had been implemented to connect theIBM System/3,IBM System/34, andIBM System/36minicomputers. Further, theIBM System/36and theIBM System/38computers were being sold to customers in multiples and there was a clear need to enable, for example, the headquarters computers of a company to interact with the computers in its various warehouses. APPC was implemented on these systems and used by various customer applications. The idea of distributed operating system services was then revived as theGolden Gateproject and an attempt made to justify its development. This attempt also failed; the whole idea of distributed services was too new for IBM product planners to be able to quantify the value of software that interconnected heterogeneous computers. However, oneGolden Gateplanner, John Bondy, remained convinced and persuaded management to create a department outside of the normal control of the Rochester laboratory so that there would be no immediate need for a predefined business case. Further, he narrowed its mission to include only support forDistributed Data Management(DDM), in particular, support forrecord-oriented files. He then convinced an experienced software architect, Richard A. Demers, to join him in the tasks of defining DDM architecture and selling the idea of DDM to the IBM system houses. The first year of this effort was largely fruitless as the IBM system houses continued to demand up-front business cases and as they insisted on message formats isomorphic to the control block interfaces of their local file systems. Further, asPersonal Computersbegan to be used as terminals attached to mainframe computers, it was argued that simply enhancing the3270 data streamwould enable PCs to access mainframe data. During this period, Demers designed an architectural model of DDM clients and servers, of their components, and of interactions between communicating computers. Further, he defined a generic format for DDM messages based on the principles of object-orientation as pioneered by theSmalltalkprogramming language and by the IBM System/38. This model made it clear how DDM products could be implemented on various systems. SeeHow DDM works. In 1982, the System/36 planners became convinced there was a sufficient market for DDM record-oriented file services.[3] The generic format of DDM messages had already been designed, but what specific messages should be defined? The System/36 file system had been defined to meet the record-oriented needs of third generation programming languages (3GLs), such asFortran,COBOL,PL/I, andIBM RPG, and so had the System/38 file system and theVirtual Storage Access Method(VSAM) file system of the IBM mainframe computers. And yet, their actual facilities and interfaces varied considerably, so what facilities and interfaces should DDM architecture support? Seerecord-oriented files. The initial work on DDM by theGolden Gateproject had followed the lead of theFile Transfer Access and Management(FTAM) international standard for distributed files, but it was very abstract and difficult to map to local file services. In fact, this had been one of the barriers to acceptance by the IBM system houses. Kenneth Lawrence, the system architect responsible for System/36 file services, argued that it would be better to define messages that at least one IBM system could easily implement and then let other systems request whatever changes they needed. Naturally, he argued for support of System/36 requirements. After a year of failure to sell the idea of DDM to other IBM system houses, Lawrence's arguments prevailed. Richard Sanders joined the DDM architecture team and worked with Lawrence and Demers to define the specific messages needed for System/36 DDM. Progress in the definition of DDM encouraged System/38 to also participate. This broadened the scope of DDM record-file support to meet many of the requirements of the System/38's advanced file system. Files exist in a context provided by an operating system that provides services for organizing files, for sharing them with concurrent users and for securing them from unwarranted access. In level 1 of DDM, access to remote file directories was not supported beyond the transmission of the fully qualified name of the file to be used. Security and sharing, however, were required. Sanders did the design work in these areas. Sanders also defined specific protocols regarding the use of communication facilities, which were incorporated in a component called the DDM Conversational Communications Manager. Initially implemented using APPC, it was later implemented usingTCP/IP. With the completion of the System/36 DDM product, Lawrence worked with programmers from the IBM Hursley Park, UK laboratory to adapt much of the System/36 DDM server programming for use in the IBMCustomer Information Control System(CICS) transaction processing environment, thereby making CICS a DDM server for both the MVS and VSE mainframe operating systems.[4]Lawrence also worked with programmers from the IBM Cary, North Carolina laboratory to implement a DDM record-oriented client forIBM PC DOS. Level 1 of DDM Architecture was formally published in 1986. At the time of this announcement, IBM presented anOutstanding Technical Achievement Awardto Kenneth Lawrence, anOutstanding Contribution Awardto Richard Sanders, and anOutstanding Innovation Awardto Richard Demers. With the increasing importance of the IBM PC and the Unix operating system in network environments, DDM support was also needed for the hierarchical directories and stream-oriented files of theIBM Personal ComputerrunningIBM PC DOSand theIBM RS/6000runningIBM AIX(IBM's version of Unix). SeeStream-oriented files. DDM Architecture Level 2 was published in 1988. Jan Fisher and Sunil Gaitonde did most of the architecture work on DDM support for directories and stream files. In 1986, IBM marketed four differentrelational database(RDB) products, each built for a specific IBM operating system. Scientists at IBM's Almaden Research Laboratory had developed System/R, a prototype of a distributed RDB and they felt it was now time to turn it into marketable products. However, System/R was based on System/R, a research prototype of a RDB, and could not be easily added to the IBM RDB products. See[6]for a discussion of RDBs in a distributed processing environment. Roger Reinsch from the IBM Santa Theresa Programming Center lead a cross-product team to define aDistributed Relational Database Architecture(DRDA). He enlisted: In 1990, DDM Architecture Level 3 and DRDA[7]were published at the same time. Both DDM and DRDA were designated as strategic components of IBM'sSystems Application Architecture(SAA). DRDA was implemented by all four of the IBM RDB products and by other vendors. Awards were given to key participants in the design of DRDA. Richard Sanders received anOutstanding Contribution Awardand Roger Reinsch and Richard Demers receivedOutstanding Innovation Awards. TheDistributed File Management(DFM)[8]project was initiated to add DDM services to IBM's MVS operating system to enable programs on remote computers to create, manage, and accessVSAMfiles. John Hufferd, the manager of the DFM project looked to the DDM Architecture team for a means of converting the data fields in records as they flowed between systems. Richard Demers took the lead on this issue, aided by Koichi Yamaguchi from the DFM project. SeeData description and conversion. The following additional services were defined by Richard Sanders, Jan Fisher and Sunil Gaitonde in DDM architecture at Level 4: DDM architecture level 4 was published in 1992. Architecture work on DDM level 5 consisted of support for Jan Fisher was the architect responsible for DDM level 5, which was published by theOpen Group, rather than IBM. Shortly thereafter, the IBM DDM architecture group was disbanded. DDM architecture is a formally defined and highly structured set of specifications. This section introduces key technical concepts that underlie DDM.[2] DDM architecture defines a client/server protocol; that is, a client requests services from a server which interacts with its local resources to perform the requested service, the results of which, data and status indicators, are returned to the client. The above diagram illustrates the roles of DDM clients and servers in relation to local resources. (The common terminology ofclientsandserversis used here, but in DDM architecture, a client is called aSource Serverand a Server is called aTarget Server.) DDM architecture isobject-oriented. All entities defined by DDM are objects defined by self-definingClassobjects. The messages, replies and data that flow between systems are serialized objects. Each object specifies its length, identifies its class by means of a DDM codepoint, and contains data as defined by its class. Further, its class specifies the commands that can be sent to its instances when an object resides in a DDM client or server, thereby encapsulating the object by a limited set of operations. Structurally, DDM architecture consists of hierarchical levels of objects, each level manifesting emergent properties at increasingly higher levels. While DDM architecture is object-oriented, the DDM products were implemented using the languages and methods typical of their host systems. A Smalltalk version of DDM was developed for the IBM PC byObject Technology International, with appropriate Smalltalk classes automatically created from the DDM Reference Manual. DDM is an open architecture. DDM products can implement subsets of DDM architecture; they can also create their own extensions.[11] The DDM 'Exchange Server Attributes' command is the first command sent when a client is connected with a server. It identifies the client and specifies the managers the client requires and the level of DDM architecture at which support is required. The server responds by identifying itself and specifying at what level it supports the requested managers. A general rule is that a product that supports Level X of a DDM manager must also support Level X-1 so that new server products connect with older client products. Subsets of DDM can be implemented to meet varying product requirements: When a DDM client is connected to a known DDM server, such as a System/38 client to a System/38 server, DDM architecture can also be extended by adding Such extensions can be defined within DDM's object-oriented framework so that existing DDM message handling facilities can be used. In a purely object-oriented implementation of DDM, clients and servers and all of their contained managers and objects exist in a memory heap, with pointers (memory addresses) used to interconnect them. For example, a command object points to each of its parameter objects. But a command cannot be transmitted from a client to a server in this way; an isomorphic copy of the command must be created as a single, contiguous string of bits. In the heap, a command consists of the size of the command in the heap, a pointer to the command's class, and pointers to each of the command's parameter objects. Linearized, the command consists of the total length of the linearized command, a code point identifying the command's class, and each of its linearized parameter objects. DDM architecture assigns unique code points to each class of object. This straightforward technique is used for all objects transmitted between client's and servers, including commands, records, and reply messages. All of these linearized objects are put into envelopes that enable the client and server agents to coordinate their processing. In DDM architecture, these envelopes are calledData Stream Structures(DSS). Commands are put into aRequest DSS(RQSDSS), replies are put into aReply DSS(RPYDSS), and other objects are put into anObject DSS(OBJDSS). There can be only one command in a RQSDSS and only one reply in RPYDSS, but many objects, such as records, can be put into an OBJDSS. Further many OBJDSSes can be chained to a RQSDSS or a PRYDSS to accommodate as many objects as necessary. A DSS consists of the total length of the DSS, a flag byte identifying the type of DSS, a request identifier, and the linearized objects in the DSS. The request identifier ties an RQSDSS with subsequent OBJDSSes from the client, such as the records to be loaded into a file by theLoad Filecommand. The request identifier also ties the RQSDSS from the client with a RPYDSS or the OBJDSSes from the server to the client. The DDM Reference Manual[12][13]consists of named Menu, Help, and Class objects. The subclasses of DDM classClassare described by variables that specify These objects can contain references to other named objects in text and specifications, thereby creatinghypertextlinkages among the pages of the DDM Reference Manual. Menu and Help pages form an integrated tutorial about DDM. The paper version of the DDM Reference Manual Level 3 is bulky, at over 1400 pages, and somewhat awkward to use, but an interactive version was also built using internal IBM communication facilities. Given the relatively slow speed of those communication facilities, it was primarily of use within the IBM Rochester laboratory. In addition to the DDM Reference Manual, a General Information[1]document provide's executive level information about DDM, and a Programmer's Guide[11]summarizes DDM concepts for programmers implementing clients and servers. Three general file models are defined by DDM architecture: record-oriented files, stream-oriented files and hierarchical directories. The following services are provided by DDM architecture for managing remote files: Record-oriented files were designed to meet the data input, output, and storage requirements of third generation (3GL) programming languages, such as Fortran, Cobol, PL/I, and RPG. Rather than have each language provide its own support for these capabilities, they were incorporated into services provided by operating systems. Arecordis a series of related data fields, such as the name, address, identification number and salary of a single employee, in which each field is encoded and mapped to a contiguous string of bytes. Early computers had limited input and output capabilities, typically in the form of stacks of 80 column punched cards or in the form of paper or magnetic tapes. Application records, such as employee data records, were sequentially read or written a record at a time and processed in batches. When direct access storage devices became available, programming languages added ways for programs to randomly access records one at a time, such as access by the values of key fields or by the position of a record in a file. All of the records in a file can be of the same format (as in a payroll file) or of varying formats (as in an event log). Some files are read-only in that their records, once written to the file, can only be read, while other files allow their records to be updated. The DDM record-oriented file models consist of file attributes, such as its creation date, the date of last update, the size of its records, and slots in which records can be stored. The records can be of either fixed or varying length, depending on the media used to store the file's records. DDM defines four kinds of record-oriented files: DDM architecture also defines a variety ofaccess methodsfor working with record-oriented files in various ways. An access method is an instance of the use of a file created by means of an OPEN command that connects itself to the file after determining if the client is authorized to use it. The access method is disconnected from a file by means of a CLOSE command. An access method keeps track of the record being currently processed by means of a cursor. Using various SET commands, the cursor can be made to point to the beginning or end of the file, to the next or previous sequential record of the file, to the record with a specific key value, or to the next or previous record as ordered by their keys. Multiple instances of access methods can be opened on a file at the same time, each serving a single client. If a file is opened for update access, conflicts can occur when the same record is being accessed by multiple clients. To prevent such conflicts, a lock can be obtained on an entire file. Also, if a file is opened forupdatea lock is obtained on a record by the first client to read it and released when that client updates it. All other clients must wait for the lock's release. Stream-oriented files consist of a single sequence of bytes on which programs can map application data however they want. Stream files are the primary file model supported byUnixandUnix-likeoperating systems and byWindows. DDM defines a single stream file model and a single stream access method. The DDM stream file model consists of file attributes, such as its creation date and the size of the stream and a continuous stream of bytes. The stream can be accessed by means of the Stream Access Method. Application programs write data onto portions of the stream, even if that data consists of records. They keep track of the location of data items in the stream in any way they want. For example, the data stream of document files is defined by a text processing program such asMicrosoft Wordand that of a spreadsheet file by a program such asMicrosoft Excel. A Stream access method is an instance of use of a stream file by a single client. A cursor keeps track of the position of the current byte of the sub-stream in use by the client. Using various SET commands, the cursor can be made to point to the beginning or end of the file, to any specific position in the file, or to any positive or negative offset from the current position. Multiple instances of the Stream access method can be opened on a file at the same time, each serving a single client. If a file is opened for "update" access, conflicts can occur when the same sub-stream is being accessed by multiple clients. To prevent such conflicts, a lock can be obtained on an entire file. Also, if a file is opened forupdatea lock is obtained on a sub-stream by the first client to "read" it and released when that client "updates" it. All other clients must wait for the lock's release. Hierarchical directoriesare files whose records each associate a name with a location. A hierarchy occurs when a directory record identifies the name and location of another directory. Using DDM client and server products, a program can create, delete and rename directories in a remote computer. They can also list and change the file attributes of remote directories. The records in a directory can be sequentially read by using the DDM Directory Access Method. The files identified by directory records can be renamed, copied, and moved to a different directory. Queues are a communication mechanism that enables generally short term communication among programs by means of records. A DDM queue resides in a single system, but it can be accessed by programs on multiple systems. There are three subclasses of DDM queues that can be created on a target system by means of distinct creation commands: The DDM queue model consists of queue attributes, such as its creation date, the number of records the queue can contain, and the length of the records. The records in a queue can be either fixed or varying length. Unlike the DDM file models, it is not necessary to open an access method on a queue. Programs can add records to a queue and receive records from a queue as determined by the class of the queue. Programs can also clear records from a queue, stop operations on a queue, list the attributes of a queue, and change the attributes of a queue. Programs can also lock a queue or individual records in a queue to inhibit contention from other programs. All other clients must wait for the lock's release. Arelational database(RDB) is an implementation of theStructured Query Language(SQL) that supports the creation, management, querying, updating, indexing and interrelationships of tables of data. An interactive user or program can issue SQL statements to a RDB and receive tables of data and status indicators in reply. However, SQL statements can also be compiled and stored in the RDB as packages and then invoked by package name. This is important for the efficient operation of application programs that issue complex, high-frequency queries. It is especially important when the tables to be accessed are located in remote systems. TheDistributed Relational Database Architecture(DRDA) fits nicely into the overall DDM framework, as discussed inObject-Orientation. (However, DDM can also be viewed as a component architecture of DRDA since other specifications are also required[2]). The DDM manager-level objects supporting DRDA are named RDB (for relational database) and SQLAM (for SQL Application Manager). Transparency is a key objective of DDM architecture. Without recompilation, it should be possible to redirect existing application programs to the data management services of a remote computer. For files, this was largely accomplished by DDM clients at the interface/functional level, but what about the data fields in a record? Complete transparency requires that client application programs be able to write and read fields as encoded by their local data management system, regardless of how any remote server encodes them, and that implies automaticdata conversions. For example, IBM mainframe computers encode floating point numbers inhexadecimalformat and character data inEBCDIC, while IBM Personal computers encode them inIEEEformat andASCII. Further complexity arose because of the ways in which various programming language compilers map record fields onto strings of bits, bytes, and words in memory. Transparent conversion of a record requires detailed descriptions of both the client view and the server view of a record. Given these descriptions, the fields of the client and server views can be matched, by field name, and appropriate conversions can be performed. The key issue is obtaining sufficiently detailed record descriptions, but record descriptions are generally specified abstractly in application programs by declaration statements defined by the programming language, with the language compiler handling encoding and mapping details. In a distributed processing environment, what is needed is a single, standardized way of describing records that is independent of all programming languages, one that can describe the wide variety of fixed and varying length record formats found in existing files. The result was the definition of a comprehensiveData Description and Conversionarchitecture (DD&C),[14]based on a new, specialized programming language,A Data Language(ADL),[15]for describing client and server views of data records and for specifying conversions. Compiled ADL programs can then be called by a server to perform necessary conversions as records flowed to or from the server. DD&C architecture went further and defined a means by which programming language declaration statements can be automatically converted to and from ADL, and thus from one programming language to another. This capability was never implemented because of its complexity and cost. However, an ADL compiler was created and ADL programs are called, when available, to perform conversions by DFM and by the IBM 4680 Store System.[16]However, it is necessary for application programmers to manually write the ADL programs. The following IBM products implemented various subsets of DDM architecture: For a complete list of the products that have implemented DRDA, see theOpen Source DRDA Product Identifier Table.	https://en.wikipedia.org/wiki/Distributed_Data_Management_Architecture
Afile managerorfile browseris acomputer programthat provides auser interfaceto managefilesandfolders.[1]The most commonoperationsperformed on files or groups of files include creating, opening (e.g.viewing, playing, editing orprinting), renaming,copying,moving,deletingand searching for files, as well as modifyingfile attributes, properties andfile permissions.Foldersand files may be displayed in ahierarchical treebased on theirdirectory structure. Graphicalfile managers may support copying and moving of files through "copy and paste" and "cut and paste" respectively, as well as throughdrag and drop, and a separate menu for selecting the target path.[2] While transferring files, a file manager may show the source and destination directories, transfer progress in percentage and/or size, progress bar, name of the file currently being transferred, remaining and/or total number of files, numerical transfer rate, and graphical transfer rate. The ability to pause the file transfer allows temporarily granting other software full sequential read access while allowing to resume later without having to restart the file transfer.[3] Some file managers move multiple files by copying and deleting each selected file from the source individually, while others first copy all selected files, then delete them from the source afterwards, as described incomputer file § Moving methods. Conflicting file names in a target directory may be handled through renaming, overwriting, or skipping. Renaming is typically numerical. Overwriting may be conditional, such as when the source file is newer or differs in size.[4]Files could technically be compared withchecksums, but that would require reading through the entire source and target files, which would slow down the process significantly on larger files. Some file managers contain features analogous toweb browsers, including forward and backnavigational buttons, an address bar,tabs, and a bookmark side bar. Some file managers providenetworkconnectivity viaprotocols, such asFTP,HTTP,NFS,SMBorWebDAV. This is achieved by allowing the user to browse for afile server(connecting and accessing the server's file system like a local file system) or by providing its own full client implementations for file server protocols. A term thatpredates[citation needed]the usage offile managerisdirectory editor. An early directory editor,DIRED, was developed circa 1974 at theStanford Artificial Intelligence LaboratorybyStan Kugell.[5][6] A directory editor was written forEXEC 8at the University of Maryland, and was available to other users at that time. The term was used by other developers, includingJay Lepreau, who wrote thediredprogram in 1980,[7]which ran onBSD. This was in turn inspired by an older program with the same name running onTOPS-20.Diredinspired other programs, includingdired, the editor script (foremacsand similar editors), andded.[8] File-listfile managers are lesser known and older than orthodox file managers. One such file manager wasneptune. It ran on theXerox Altoin the 1973-1974 time frame. It had some of the same features that would end up in orthodox file managers. Another such file manager is flist, which was introduced sometime before 1980 on theConversational Monitor System.[9][10][11]This is a variant of FULIST, which originated before late 1978, according to comments by its author, Theo Alkema.[12] The flist program provided a list of files in the user's minidisk,[13]and allowed sorting by any file attribute. The file attributes could be passed to scripts or function-key definitions, making it simple to use flist as part ofCMS EXEC,EXEC 2orXEDITscripts. This program ran only on IBM VM/SP CMS, but was the inspiration for other programs, including filelist[14][15][16](a script run via theXediteditor), and programs running on other operating systems, including a program also called flist, which ran onOpenVMS,[17]and FULIST (from the name of the corresponding internal IBM program),[18]which runs onUnix.[19] Orthodox file managers (sometimesabbreviatedto "OFM") or command-based file managers are text-menu based file managers that commonly have three windows (two panels and one command line window). Orthodox file managers are one of the longest running families of file managers, precedinggraphical user interface-based types. Developers create applications that duplicate and extend the manager that was introduced byPathMinderandJohn Socha'sNorton CommanderforDOS.[citation needed]The concept dates to the mid-1980s—PathMinder was released in 1984, and Norton Commander version 1.0 was released in 1986. Despite the age of this concept, file managers based on Norton Commander are actively developed, and dozens of implementations exist for DOS, Unix, and Microsoft Windows.Nikolai Bezroukovpublishes his own set of criteria for an OFM standard (version 1.2 dated June 1997).[20] An orthodox file manager typically has three windows. Two of the windows are called panels and are positioned symmetrically at the top of the screen. The third is the command line, which is essentially a minimized command (shell) window that can be expanded to full screen. Only one of the panels is active at a given time. The active panel contains the "file cursor". Panels are resizable and can be hidden. Files in the active panel serve as the source of file operations performed by the manager. For example, files can be copied or moved from the active panel to the location represented in the passive panel. This scheme is most effective for systems in which the keyboard is the primary or sole input device. The active panel shows information about thecurrent working directoryand the files that it contains. The passive (inactive) panel shows the content of the same or another directory (the default target for file operations). Users may customize the display of columns that show relevant file information. The active panel and passive panel can be switched (often by pressing thetab key). The following features describe the class of orthodox file managers. Other common features include: The introduction of tabbed panels in some file managers (for exampleTotal Commander) made it possible to manipulate more than one active and passive directory at a time. Orthodox file managers[21]are among the most portable file managers. Examples are available on almost any platform, with both command-line and graphical interfaces. This is unusual among command line managers in that something purporting to be a standard for the interface is published. They are also actively supported by developers. This makes it possible to do the same work on different platforms without much relearning of the interface. Sometimes they are calleddual-pane managers, a term that is typically used for programs such as theWindows File Explorer(see below). But they have three panes including a command line pane below (or hidden behind) two symmetric panes. Furthermore, most of these programs allow using just one of the two larger panes with the second hidden. Some also add an item to the Context Menu in Windows to "Open two Explorers, side by side". Notable ones include: Anavigational file manageris a newer type of file manager. Since the advent ofGUIs, it has become the dominant type of file manager for desktop computers.[22][better source needed] Typically, it has two panes, with the filesystem tree in the left pane and the contents of the current directory in the right pane. For macOS, theMiller columnsview inFinder(originating inNeXTStep) is a variation on the navigational file manager theme.[dubious–discuss] The interface in a navigational file manager often resembles aweb browser, complete withbackandforwardbuttons, and oftenreloadbuttons. Most also contain an address bar into which the file or directory path (orURI) can be typed. Most navigational file managers have two panes, the left pane being atree viewof the filesystem. This means that unlike orthodox file managers, the two panes are asymmetrical in their content and use. Selecting a directory in the Navigation pane on the left designates it as the current directory, displaying its contents in the Contents pane on the right. However, expanding (+) or collapsing (-) a portion of the tree without selecting a directory will not alter the contents of the right pane. The exception to this behavior applies when collapsing a parent of the current directory, in which case the selection is refocused on the collapsed parent directory, thus altering the list in the Contents pane. The process of moving from one location to another need not open a new window. Several instances of the file manager can be opened simultaneously and communicate with each other viadrag-and-dropandclipboardoperations, so it is possible to view several directories simultaneously and perform cut-and paste operations between instances. File operations are based on drag-and-drop and editor metaphors: users can select and copy files or directories onto the clipboard and then paste them in a different place in the filesystem or even in a different instance of the file manager. Notable examples of navigational file managers include: Spatial file managersuse a spatialmetaphorto representfilesanddirectoriesas if they were actual physical objects. A spatial file manager imitates the way people interact with physical objects. Some ideas behind the concept of a spatial file manager are: As in navigational file managers, when a directory is opened, theiconrepresenting the directory changes—perhaps from an image showing a closed drawer to an opened one, perhaps the directory's icon turns into a silhouette filled with a pattern—and a new window is opened to represent that directory. Examples of file managers that use a spatial metaphor to some extent include: Dysfunctional spatial file managers: Some projects have attempted to implement athree-dimensionalmethod of displaying files and directory structures. Three-dimensional file browsing has not become popular; the exact implementation tends to differ between projects, and there are no common standards to follow. Examples of three-dimensional file managers include: Web-based file managers are typically scripts written in eitherPHP,Ajax,Perl,ASPor anotherserver-side language. When installed on a local server or on a remote server, they allow files and directories located there to be managed and edited, using a web browser, without the need forFTP Access. More advanced, and usually commercially distributed, web-based file management scripts allow the administrator of the file manager to configure secure, individual user accounts, each with individual account permissions. Authorized users have access to documents stored on the server or in their individual user directories anytime, from anywhere, via a web browser. A web-based file manager can serve as an organization's digital repository. For example, documents, digital media, publishing layouts, and presentations can be stored, managed, and shared between customers, suppliers, and remote workers, or just internally. Web-based file managers are becoming increasingly popular due to the rise in popularity of dynamic webcontent management systems(CMS) and the need for non-technical website moderators to manage media on their websites powered by these platforms. An example isnet2ftp, a PHP- and JavaScript-based FTP client. Operating systems typically ship afile picker, which allows specifying in which location to save a file (usually accessed through the "Save as" option in software), and where to open a file from. Sometimes, a folder is selected instead of a file or destination path. Some file pickers also allow file management to some degree, such as searching, moving, copying, renaming, and copying the path to clipboard. Some software might have a customized file picker.	https://en.wikipedia.org/wiki/File_manager
Incomputing,file system fragmentation, sometimes calledfile system aging, is the tendency of afile systemto lay out the contents offilesnon-continuously to allow in-place modification of their contents. It is a special case ofdata fragmentation. File system fragmentation negatively impactsseek timein spinning storage media, which is known to hinderthroughput. Fragmentation can be remedied by re-organizing files and free space back into contiguous areas, a process calleddefragmentation. Solid-state drivesdo not physically seek, so their non-sequential data access is hundreds of times faster than moving drives, making fragmentation less of an issue. It is recommended to not manually defragment solid-state storage, because this can prematurely wear drives via unnecessary write–erase operations.[1] Whena file system is first initializedon apartition, it contains only a few small internal structures and is otherwise one contiguous block of empty space.[a]This means that the file system is able to place newly created files anywhere on the partition. For some time after creation, files can be laid out near-optimally. When theoperating systemandapplicationsare installed orarchivesare unpacked, separate files end up occurring sequentially so related files are positioned close to each other. As existing files are deleted or truncated, new regions of free space are created. When existing files are appended to, it is often impossible to resume the write exactly where the file used to end, as another file may already be allocated there; thus, a new fragment has to be allocated. As time goes on, and the same factors are continuously present, free space as well as frequently appended files tend to fragment more. Shorter regions of free space also mean that the file system is no longer able to allocate new files contiguously, and has to break them into fragments. This is especially true when the file system becomes full and large contiguous regions of free space are unavailable. The following example is a simplification of an otherwise complicated subject. Consider the following scenario: A new disk has had five files, named A, B, C, D and E, saved continuously and sequentially in that order. Each file is using 10blocksof space. (Here, the block size is unimportant.) The remainder of the disk space is one free block. Thus, additional files can be created and saved after the file E. If the file B is deleted, a second region of ten blocks of free space is created, and the disk becomes fragmented. The empty space is simply left there, marked as and available for later use, then used again as needed.[b]The file systemcoulddefragment the disk immediately after a deletion, but doing so would incur a severe performance penalty at unpredictable times. Now, a new file called F, which requires seven blocks of space, can be placed into the first seven blocks of the newly freed space formerly holding the file B, and the three blocks following it will remain available. If another new file called G, which needs only three blocks, is added, it could then occupy the space after F and before C. If subsequently F needs to be expanded, since the space immediately following it is occupied, there are three options for the file system: The second option is probably impractical for performance reasons, as is the third when the file is very large. The third option is impossible when there is no single contiguous free space large enough to hold the new file. Thus the usual practice is simply to create anextentsomewhere else and chain the new extent onto the old one. Material added to the end of file F would be part of the same extent. But if there is so much material that no room is available after the last extent, thenanotherextent would have to be created, and so on. Eventually the file system has free segments in many places and some files may be spread over many extents. Access time for those files (or for all files) may become excessively long. Some early file systems were unable to fragment files. One such example was theAcorn DFSfile system used on theBBC Micro. Due to its inability to fragment files, the error messagecan't extendwould at times appear, and the user would often be unable to save a file even if the disk had adequate space for it. DFS used a very simple disk structure andfilesondiskwere located only by their length and starting sector. This meant that all files had to exist as a continuous block of sectors and fragmentation was not possible. Using the example in the table above, the attempt to expand file F in step five would have failed on such a system with thecan't extenderror message. Regardless of how much free space might remain on the disk in total, it was not available to extend the data file. Standards oferror handlingat the time were primitive and in any case programs squeezed into the limited memory of the BBC Micro could rarely afford to waste space attempting to handle errors gracefully. Instead, the user would find themselves dumped back at the command prompt with theCan't extendmessage and all the data which had yet to be appended to the file would be lost. The problem could not be solved by simply checking the free space on the disk beforehand, either. While free space on the disk may exist, the size of the largest contiguous block of free space was not immediately apparent without analyzing the numbers presented by the disk catalog and so would escape the user's notice. In addition, almost all DFS users had previously usedcassette file storage, which does not suffer from this error. The upgrade to afloppy disksystem was an expensive upgrade, and it was a shock that the upgrade might without warning causedata loss.[2][3] File system fragmentation may occur on several levels: Individual file fragmentation occurs when a single file has been broken into multiple pieces (calledextentson extent-based file systems). While disk file systems attempt to keep individual files contiguous, this is not often possible without significant performance penalties. File system check and defragmentation tools typically only account for file fragmentation in their "fragmentation percentage" statistic. Free (unallocated) space fragmentation occurs when there are several unused areas of the file system where new files or metadata can be written to. Unwanted free space fragmentation is generally caused by deletion or truncation of files, but file systems may also intentionally insert fragments ("bubbles") of free space in order to facilitate extending nearby files (seepreventing fragmentationbelow). File segmentation, also called related-file fragmentation, or application-level (file) fragmentation, refers to the lack oflocality of reference(within the storing medium) between related files. Unlike the previous two types of fragmentation, file scattering is a much more vague concept, as it heavily depends on the access pattern of specific applications. This also makes objectively measuring or estimating it very difficult. However, arguably, it is the most critical type of fragmentation, as studies have found that the most frequently accessed files tend to be small compared to available disk throughput per second.[4] To avoid related file fragmentation and improve locality of reference (in this case calledfile contiguity), assumptions or active observations about the operation of applications have to be made. A very frequent assumption made is that it is worthwhile to keep smaller files within a singledirectorytogether, and lay them out in the natural file system order. While it is often a reasonable assumption, it does not always hold. For example, an application might read several different files, perhaps in different directories, in exactly the same order they were written. Thus, a file system that simply orders all writes successively, might work faster for the given application. The catalogs or indices used by a file system itself can also become fragmented over time, as the entries they contain are created, changed, or deleted. This is more of a concern when the volume contains a multitude of very small files than when a volume is filled with fewer larger files. Depending on the particular file system design, the files or regions containing that data may also become fragmented (as described above for 'regular' files), regardless of any fragmentation of the actual data records maintained within those files or regions.[5] For some file systems (such asNTFS[c]andHFS/HFS Plus[6]), thecollation/sorting/compactionneeded to optimize this data cannot easily occur while the file system is in use.[7] File system fragmentation is more problematic with consumer-gradehard disk drivesbecause of the increasing disparity betweensequential accessspeed androtational latency(and to a lesser extentseek time) on which file systems are usually placed.[8]Thus, fragmentation is an important problem in file system research and design. The containment of fragmentation not only depends on the on-disk format of the file system, but also heavily on its implementation.[9]File system fragmentation has less performance impact uponsolid-state drives, as there is no mechanicalseek timeinvolved.[10]However, the file system needs to store additional metadata for each non-contiguous part of the file. Each piece of metadata itself occupies space and requires processing power and processor time. If the maximum fragmentation limit is reached, write requests fail.[10] In simple file systembenchmarks, the fragmentation factor is often omitted, as realistic aging and fragmentation is difficult to model. Rather, for simplicity of comparison, file system benchmarks are often run on empty file systems. Thus, the results may vary heavily from real-life access patterns.[11] Several techniques have been developed to fight fragmentation. They can usually be classified into two categories:preemptiveandretroactive. Due to the difficulty of predicting access patterns these techniques are most oftenheuristicin nature and may degrade performance under unexpected workloads. Preemptive techniques attempt to keep fragmentation to a minimum at the time data is being written on the disk. The simplest is appending data to an existing fragment in place where possible, instead of allocating new blocks to a new fragment. Many of today's file systems attempt to pre-allocate longer chunks, or chunks from different free space fragments, calledextentsto files that are actively appended to. This largely avoids file fragmentation when several files are concurrently being appended to, thus avoiding their becoming excessively intertwined.[9] If the final size of a file subject to modification is known, storage for the entire file may be preallocated. For example, theMicrosoft Windowsswap file(page file) can be resized dynamically under normal operation, and therefore can become highly fragmented. This can be prevented by specifying a page file with the same minimum and maximum sizes, effectively preallocating the entire file. BitTorrentand otherpeer-to-peerfilesharingapplications limit fragmentation by preallocating the full space needed for a file when initiatingdownloads.[12] A relatively recent technique isdelayed allocationinXFS,HFS+[13]andZFS; the same technique is also called allocate-on-flush inreiser4andext4. When the file system is being written to, file system blocks are reserved, but the locations of specific files are not laid down yet. Later, when the file system is forced to flush changes as a result of memory pressure or a transaction commit, the allocator will have much better knowledge of the files' characteristics. Most file systems with this approach try to flush files in a single directory contiguously. Assuming that multiple reads from a single directory are common, locality of reference is improved.[14]Reiser4 also orders the layout of files according to the directoryhash table, so that when files are being accessed in the natural file system order (as dictated byreaddir), they are always read sequentially.[15] Retroactive techniques attempt to reduce fragmentation, or the negative effects of fragmentation, after it has occurred. Many file systems providedefragmentationtools, which attempt to reorder fragments of files, and sometimes also decrease their scattering (i.e. improve their contiguity, orlocality of reference) by keeping either smaller files indirectories, or directory trees, or even file sequences close to each other on the disk. TheHFS Plusfile system transparently defragments files that are less than 20MiBin size and are broken into 8 or more fragments, when the file is being opened.[16] The now obsolete Commodore AmigaSmart File System(SFS) defragmented itself while the filesystem was in use. The defragmentation process is almost completely stateless (apart from the location it is working on), so that it can be stopped and started instantly. During defragmentation data integrity is ensured for both metadata and normal data.	https://en.wikipedia.org/wiki/File_system_fragmentation
Afilename extension,file name extensionorfile extensionis a suffix to thenameof acomputer file(for example,.txt,.mp3,.exe) that indicates a characteristic of the file contents or its intended use. A filename extension is typically delimited from the rest of the filename with afull stop(period), but in some systems[1]it is separated with spaces. Somefile systemsimplement filename extensions as a feature of the file system itself and may limit the length and format of the extension (as seen inDOS), while others treat filename extensions as part of the filename without special distinction (as seen inUnix) and instead prefer to usefile signatures. TheMulticsfile system stores the file name as a single string, not split into base name and extension components, allowing the "." to be just another character allowed in file names. It allows for variable-length filenames, permitting more than one dot, and hence multiple suffixes, as well as no dot, and hence no suffix. Some components of Multics, and applications running on it, use suffixes to indicate file types, but not all files are required to have a suffix — for example, executables and ordinary text files usually have no suffixes in their names. File systems forUNIX-likeoperating systems also store the file name as a single string, with "." as just another character in the file name. A file with more than one suffix is sometimes said to have more than one extension, although terminology varies in this regard, and most authors defineextensionin a way that does not allow more than one in the same file name.[citation needed]More than one extension usually represents nested transformations, such asfiles.tar.gz(the.tarindicates that the file is atar archiveof one or more files, and the.gzindicates that the tar archive file is compressed withgzip). Programs transforming or creating files may add the appropriate extension to names inferred from input file names (unless explicitly given an output file name), but programs reading files usually ignore the information; it is mostly intended for the human user. It is more common, especially in binary files, for the file to containinternalorexternalmetadata describing its contents. This model generally requires the full filename to be provided in commands, whereas the metadata approach often allows the extension to be omitted. CTSSwas an early operating system in which the filename and file type were separately stored. Continuing this practice, and also using a dot as a separator for display and input purposes (while not storing the dot), were variousDECoperating systems (such asRT-11), followed byCP/Mand subsequentlyDOS. InDOSand 16-bitWindows, file names have a maximum of 8 characters, a period, and an extension of up to three letters. TheFATfile system for DOS and Windows stores file names as an 8-character name and a three-character extension. The period character is not stored. TheHigh Performance File System(HPFS), used in Microsoft andIBM'sOS/2stores the file name as a single string, with the "." character as just another character in the file name. The convention of using suffixes continued, even though HPFS supports extended attributes for files, allowing a file's type to be stored in the file as an extended attribute. Microsoft'sWindows NT's native file system,NTFS, and the laterReFS, also store the file name as a single string; again, the convention of using suffixes to simulate extensions continued, for compatibility with existing versions of Windows. InWindows NT 3.5, a variant of the FAT file system, calledVFATappeared; it supports longer file names, with the file name being treated as a single string. Windows 95, with VFAT, introduced support for long file names, and removed the 8.3 name/extension split in file names from non-NT Windows. Theclassic Mac OSdisposed of filename-based extension metadata entirely; it used, instead, a distinct filetype codeto identify the file format. Additionally, acreator codewas specified to determine which application would be launched when the file'siconwasdouble-clicked.[2]macOS, however, uses filename suffixes as a consequence of being derived from the UNIX-likeNeXTSTEPoperating system, in addition to using type and creator codes. In Commodore systems, files can only have four extensions: PRG, SEQ, USR, REL. However, these are used to separate data types used by a program and are irrelevant for identifying their contents. With the advent ofgraphical user interfaces, the issue of file management and interface behavior arose. Microsoft Windows allowed multiple applications to beassociatedwith a given extension, and different actions were available for selecting the required application, such as acontext menuoffering a choice between viewing, editing or printing the file. The assumption was still that any extension represented a single file type; there was an unambiguous mapping between extension and icon. When theInternetage first arrived, those using Windows systems that were still restricted to8.3filename formats had to create web pages with names ending in.HTM, while those usingMacintoshor UNIX computers could use the recommended.htmlfilename extension. This also became a problem for programmers experimenting with theJava programming language, since itrequiresthe four-letter suffix.javaforsource codefiles and the five-letter suffix.classfor Javacompilerobject codeoutput files.[3] Filename extensions may be considered a type ofmetadata.[4]They are commonly used to imply information about the way data might be stored in the file. The exact definition, giving the criteria for deciding what part of the file name is its extension, belongs to the rules of the specificfile systemused; usually the extension is the substring which follows the last occurrence, if any, of thedot character(example:txtis the extension of the filenamereadme.txt, andhtmlthe extension ofindex.html). On file systems of some mainframe systems such asCMSinVM,VMS, and of PC systems such asCP/Mand derivative systems such asMS-DOS, the extension is a separatenamespacefrom the filename. Under Microsoft'sDOSandWindows, extensions such asEXE,COMorBATindicate that a file is a programexecutable. InOS/360 and successors, the part of the dataset name following the last period, called the low level qualifier, is treated as an extension by some software, e.g.,TSOEDIT, but it has no special significance to the operating system itself; the same applies to Unix files in MVS. The filename extension was originally used to determine the file's generic type.[citation needed]The need to condense a file's type intothree charactersfrequently led to abbreviated extensions. Examples include using.GFXfor graphics files,.TXTforplain text, and.MUSfor music. However, because many different software programs have been made that all handle these data types (and others) in a variety of ways, filename extensions started to become closely associated with certain products—even specific product versions. For example, earlyWordStarfiles used.WSor.WSn, wherenwas the program's version number. Also, conflicting uses of some filename extensions developed. One example is.rpm, used for bothRPM Package Managerpackages andRealPlayerMedia files;.[5]Others are.qif, shared byDESQviewfonts,Quickenfinancial ledgers, andQuickTimepictures;[6].gba, shared byGrabItscripts andGame Boy AdvanceROM images;[7].sb, used forSmallBasicandScratch; and.dts, being used forDynamix Three SpaceandDTS. In manyInternetprotocols, such asHTTPandMIME email, the type of a bitstream is stated as themedia type, or MIME type, of the stream, rather than a filename extension. This is given in a line of text preceding the stream, such asContent-type: text/plain. There is no standard mapping between filename extensions and media types, resulting in possible mismatches in interpretation between authors, web servers, and client software when transferring files over the Internet. For instance, a content author may specify the extensionsvgzfor a compressedScalable Vector Graphicsfile, but a web server that does not recognize this extension may not send the proper content typeapplication/svg+xmland its required compression header, leaving web browsers unable to correctly interpret and display the image. BeOS, whoseBFSfile system supports extended attributes, would tag a file with its media type as an extended attribute. Somedesktop environments, such asKDE PlasmaandGNOME, associate a media type with a file by examining both the filename suffix and the contents of the file, in the fashion of thefilecommand, as aheuristic. They choose the application to launch when a file is opened based on that media type, reducing the dependency on filename extensions.macOSuses both filename extensions and media types, as well asfile type codes, to select aUniform Type Identifierby which to identify the file type internally. The use of a filename extension in a command name appears occasionally, usually as a side effect of the command having been implemented as a script, e.g., for theBourne shellor forPython, and the interpreter name being suffixed to the command name, a practice common on systems that rely on associations between filename extension and interpreter, but sharply deprecated[8]inUnix-likesystems, such asLinux,Oracle Solaris,BSD-based systems, and Apple'smacOS, where the interpreter is normally specified as a header in the script ("shebang"). On association-based systems, the filename extension is generally mapped to a single, system-wide selection of interpreter for that extension (such as ".py" meaning to use Python), and the command itself is runnable from the command line even if the extension is omitted (assuming appropriate setup is done). If the implementation language is changed, the command name extension is changed as well, and the OS provides a consistentAPIby allowing the same extensionless version of the command to be used in both cases. This method suffers somewhat from the essentially global nature of the association mapping, as well as from developers' incomplete avoidance of extensions when calling programs, and that developers can not force that avoidance. Windows is the only remaining widespread employer of this mechanism. On systems withinterpreter directives, including virtually all versions of Unix, command name extensions have no special significance, and are by standard practice not used, since the primary method to set interpreters for scripts is to start them with a single line specifying the interpreter to use. In these environments, including the extension in a command name unnecessarily exposes an implementation detail which puts all references to the commands from other programs at future risk if the implementation changes. For example, it would be perfectly normal for a shell script to be reimplemented in Python or Ruby, and later in C or C++, all of which would change the name of the command were extensions used. Without extensions, a program always has the same extension-less name, with only theinterpreter directiveormagic numberchanging, and references to the program from other programs remain valid. File extensions alone are not a reliable indicator of a file's type, as the extension can be modified without changing the file's contents, such as to disguisemalicious content. Therefore, especially in the context ofcybersecurity, a file's true nature should be examined forits signature, which is a distinctive sequence of bytes affixed to a file's header. This is accomplished using file identification software or ahex editor, which provides ahex dumpof a file's contents.[9]For example, onUNIX-likesystems, it is not uncommon to find files with no extensions at all,[10]as commands such asfileare meant to be used instead, and will read the file's header to determine its content.[citation needed] Malware such asTrojan horsestypically takes the form of anexecutable, but any file type that performsinput/outputoperations may contain malicious code. A fewdata filetypes such asPDFshave been found to be vulnerable to exploits that causebuffer overflows.[11]There have been instances of malware crafted to exploit such vulnerabilities in some Windows applications when opening a file with an overly long, unhandled filename extension. File managersmay have an option to hide filenames extensions. This is the case forFile Explorer, the file browser provided withMicrosoft Windows, which by default does not display extensions. Malicious users have tried to spreadcomputer virusesandcomputer wormsby using file names formed likeLOVE-LETTER-FOR-YOU.TXT.vbs. The idea is that this will appear asLOVE-LETTER-FOR-YOU.TXT, a harmless text file, without alerting the user to the fact that it is a harmful computer program, in this case, written inVBScript.[11]The default behavior forReactOSis to display filename extensions inReactOS Explorer. Later Windows versions (starting withWindows XP Service Pack 2andWindows Server 2003) included customizable lists of filename extensions that should be considered "dangerous" in certain "zones" of operation, such as whendownloadedfrom thewebor received as an e-mail attachment. Modernantivirus softwaresystems also help to defend users against such attempted attacks where possible.[citation needed] A virus may couple itself with an executable without actually modifying the executable. These viruses, known ascompanion viruses, attach themselves in such a way that they are executed when the original file is requested. One way such a virus does this involves giving the virus the same name as the target file, but with a different extension to which the operating system gives priority, and often assigning the former a "hidden"attributeto conceal the malware's existence. The efficacy of this approach depends on whether the user attempts to open the intended file by entering a command and whether the user includes the extension. Later versions of DOS and Windows check for and attempt to run.COMfiles first by default, followed by.EXEand finally.BATfiles. In this case, the infected file is the one with the.COMextension, which the user unwittingly executes.[10][11] Some viruses take advantage of the similarity between the ".com"top-level domainand the.COMfilename extension by emailing malicious, executable command-file attachments under names superficially similar to URLs (e.g., "myparty.yahoo.com"), with the effect that unaware users click on email-embedded links that they think lead to websites but actually download and execute the malicious attachments.[citation needed]	https://en.wikipedia.org/wiki/Filename_extension
Incomputer storage, aglobal file systemis adistributed file systemthat can be accessed from multiple locations, typically across a wide-area network, and provides concurrent access to aglobal namespacefrom all locations. In order for a file system to be considered global, it must allow for files to be created, modified, and deleted from any location. This access is typically provided by acloud storage gatewayat each edge location, which provides access using the NFS or SMB network file sharing protocols.[1] There are a number of benefits to using a global file system. First, global file systems can improve the availability of data by allowing multiple copies to be stored in different locations, as well as allowing for rapid restoration of lost data from a remote location. This can be helpful in the event of a disaster, such as a power outage or a natural disaster. Second, global file systems can improve performance by allowing data to be cached closer to the users who are accessing it. This can be especially beneficial in cases where data is accessed by users in different parts of the world. Finally, in contrast to traditionalNetwork attached storage, global file systems can improve the ability of users to collaborate across multiple sites, in a manner similar toEnterprise file synchronization and sharing.[1] The term global file system has historically referred to adistributedvirtualname spacebuilt on a set of localfile systemsto provide transparent access to multiple, potentially distributed, systems.[2]These global file systems had the same properties such as blocking interface, no buffering etc. but guaranteed that the same path name corresponds to the same object on all computers deploying the filesystem. Also calleddistributed file systemsthese file systems rely on redirection to distributed systems, therefore latency and scalability can affect file access depending on where the target systems reside. TheAndrew File Systemattempted to solve this for a campus environment usingcachingand aweak consistency modelto achieve local access to remote files. In the 2000's, global file systems have found a use case in providinghybrid cloud storage, that combine cloud or anyobject storage, versioning and local caching to create a single, unified, globally accessible file system that does not rely on redirection to a storage device[3]but serves files from the local cache while maintaining the single file system and all meta data in the object storage.[4]As described inGoogle's patents, advantages of these global file systems include the ability to scale with the object storage, use snapshots stored in the object storage for versioning to replace backup, and create a centrally managed consolidated storage repository in the object storage. When it comes to hybrid file storage, there are two main approaches: network attached storage (NAS) with cloud connectivity and global file system (GFS). The two solutions are fundamentally different.[5] NAS with cloud connectivity is typically used to supplement on-premises storage. Public clouds may be combined with on-premises NAS for tasks such as backup, tiering, or disaster recovery. This type of setup uses the cloud for specific use cases to complement on-premises storage. On-premises NAS is sold by well-established IT vendors includingDell,IBM,NetApp, and others, and most build in support for some type of cloud connectivity.[5] A Global File System utilizes a fundamentally different architecture. In these solutions, cloud storage – typically object storage – serves as the core storage element, while caching devices are utilized on-premises to provide data access. These devices can be physical but are increasingly available as virtual solutions that can be deployed in ahypervisor. The use of caching devices reduces the amount of required on-premises storage capacity, and the associated capital expense.[5] Global file systems are better suited for remote collaboration, as they make it easier to manage access to files across dispersed geographic areas. Utilizing the cloud as a central storage location enables users to access the same data regardless of their location.[5] There are some trade-offs to consider when choosing a GFS solution, however. One trade off is that because the gold copy of data is stored off-site, there may be latency issues when retrieving infrequently accessed files.[5] Notable vendors in the global filesystem area include:[1]	https://en.wikipedia.org/wiki/Global_file_system
Object storage(also known asobject-based storage[1]orblob storage) is acomputer data storageapproach that manages data as "blobs" or "objects", as opposed to other storage architectures likefile systems, which manage data as a file hierarchy, andblock storage, which manages data as blocks within sectors and tracks.[2]Each object is typically associated with a variable amount ofmetadata, and aglobally unique identifier. Object storage can be implemented at multiple levels, including the device level (object-storage device), the system level, and the interface level. In each case, object storage seeks to enable capabilities not addressed by other storage architectures, like interfaces that are directly programmable by the application, a namespace that can span multiple instances of physical hardware, and data-management functions likedata replicationand data distribution at object-level granularity. Object storage systems allow retention of massive amounts ofunstructured datain which data is written once and read once (or many times).[3]Object storage is used for purposes such as storing objects like videos and photos onFacebook, songs onSpotify, or files in online collaboration services, such asDropbox.[4]One of the limitations with object storage is that it is not intended fortransactional data, as object storage was not designed to replaceNASfile access and sharing; it does not support the locking and sharing mechanisms needed to maintain a single, accurately updated version of a file.[3] Jim Starkeycoined the term "blob"[when?]working atDigital Equipment Corporationto refer to opaque data entities. The terminology was adopted forRdb/VMS. "Blob" is often humorously explained to be an abbreviation for "binary large object". According to Starkey, thisbackronymarose when Terry McKiever, working in marketing atApollo Computerfelt that the term needed to be an abbreviation. McKiever began using the expansion "Basic Large Object". This was later eclipsed by the retroactive explanation of blobs as "Binary Large Objects". According to Starkey, "Blob don't stand for nothin'." Rejecting the acronym, he explained his motivation behind the coinage, saying, "A blob is the thing that ate Cincinnatti [sic], Cleveland, or whatever," referring to the 1958 science fiction filmThe Blob.[5] In 1995, research led byGarth GibsononNetwork-Attached Secure Disksfirst promoted the concept of splitting less common operations, like namespace manipulations, from common operations, like reads and writes, to optimize the performance and scale of both.[6]In the same year, a Belgian company - FilePool - was established to build the basis for archiving functions. Object storage was proposed at Gibson'sCarnegie Mellon Universitylab as a research project in 1996.[7]Another key concept was abstracting the writes and reads of data to more flexible data containers (objects). Fine grained access control through object storage architecture[8]was further described by one of the NASD team, Howard Gobioff, who later was one of the inventors of theGoogle File System.[9] Other related work includes theCodafilesystem project atCarnegie Mellon, which started in 1987, and spawned theLustre file system.[10]There is also the OceanStore project at UC Berkeley,[11]which started in 1999[12]and the Logistical Networking project at the University of Tennessee Knoxville, which started in 1998.[13]In 1999, Gibson foundedPanasasto commercialize the concepts developed by the NASD team. Seagate Technologyplayed a central role in the development of object storage. According to theStorage Networking Industry Association(SNIA), "Object storage originated in the late 1990s: Seagate specifications from 1999 Introduced some of the first commands and how operating system effectively removed from consumption of the storage."[14] A preliminary version of the "OBJECT BASED STORAGE DEVICES Command Set Proposal" dated 10/25/1999 was submitted by Seagate as edited by Seagate's Dave Anderson and was the product of work by the National Storage Industry Consortium (NSIC) including contributions byCarnegie Mellon University, Seagate, IBM, Quantum, and StorageTek.[15]This paper was proposed to INCITS T-10 (International Committee for Information Technology Standards) with a goal to form a committee and design a specification based on the SCSI interface protocol. This defined objects as abstracted data, with unique identifiers and metadata, how objects related to file systems, along with many other innovative concepts. Anderson presented many of these ideas at the SNIA conference in October 1999. The presentation revealed an IP Agreement that had been signed in February 1997 between the original collaborators (with Seagate represented by Anderson and Chris Malakapalli) and covered the benefits of object storage, scalable computing, platform independence, and storage management.[16] One of the design principles of object storage is to abstract some of the lower layers of storage away from the administrators and applications. Thus, data is exposed and managed as objects instead ofblocksor (exclusively) files. Objects contain additional descriptive properties which can be used for better indexing or management. Administrators do not have to perform lower-level storage functions like constructing and managinglogical volumesto utilize disk capacity or settingRAIDlevels to deal with disk failure. Object storage also allows the addressing and identification of individual objects by more than just file name and file path. Object storage adds a unique identifier within a bucket, or across the entire system, to support much larger namespaces and eliminate name collisions. Object storage explicitly separates file metadata from data to support additional capabilities. As opposed to fixed metadata in file systems (filename, creation date, type, etc.), object storage provides for full function, custom, object-level metadata in order to: Additionally, in some object-based file-system implementations: Object-based storage devices(OSD) as well as some software implementations (e.g., DataCore Swarm) manage metadata and data at the storage device level: Object storage provides programmatic interfaces to allow applications to manipulate data. At the base level, this includes Create, read, update and delete (CRUD) functions for basic read, write and delete operations. Some object storage implementations go further, supporting additional functionality likeobject/file versioning, object replication, life-cycle management and movement of objects between different tiers and types of storage. Most API implementations areREST-based, allowing the use of many standardHTTPcalls. The vast majority of cloud storage available in the market leverages an object-storage architecture. Some notable examples areAmazon Web Services S3, which debuted in March 2006,Microsoft AzureBlob Storage,Rackspace Cloud Files(whose code was donated in 2010 to Openstack project and released asOpenStack Swift), andGoogle Cloud Storagereleased in May 2010. Some distributed file systems use an object-based architecture, where file metadata is stored in metadata servers and file data is stored in object storage servers. File system client software interacts with the distinct servers, and abstracts them to present a full file system to users and applications. Some early incarnations of object storage were used for archiving, as implementations were optimized for data services like immutability, not performance.EMC Centeraand Hitachi HCP (formerly known as HCAP) are two commonly cited object storage products for archiving. Another example isQuantumActiveScale Object Storage Platform. More general-purpose object-storage systems came to market around 2008. Lured by the incredible growth of "captive" storage systems within web applications like Yahoo Mail and the early success of cloud storage, object-storage systems promised the scale and capabilities of cloud storage, with the ability to deploy the system within an enterprise, or at an aspiring cloud-storage service provider. A few object-storage systems support Unified File and Object storage, allowing clients to store objects on a storage system while simultaneously other clients store files on the same storage system.[17]Other vendors in the area ofHybrid cloud storageare usingCloud storage gatewaysto provide a file access layer over object storage, implementing file access protocols such as SMB and NFS. Some large Internet companies developed their own software when object-storage products were not commercially available or use cases were very specific. Facebook famously invented their own object-storage software, code-named Haystack, to address their particular massive-scale photo management needs efficiently.[18] Object storage at the protocol and device layer was proposed 20 years ago[ambiguous]and approved for theSCSIcommand set nearly 10 years ago[ambiguous]as "Object-based Storage Device Commands" (OSD),[19]however, it had not been put into production until the development of the Seagate Kinetic Open Storage platform.[20][21]TheSCSIcommand set for Object Storage Devices was developed by a working group of the SNIA for the T10 committee of theInternational Committee for Information Technology Standards(INCITS).[22]T10 is responsible for all SCSI standards. One of the first object-storage products,Lustre, is used in 70% of the Top 100 supercomputers and ~50% of theTop 500.[23]As of June 16, 2013, this includes 7 of the top 10, including the current fourth fastest system on the list - China's Tianhe-2 and the seventh fastest, theTitan supercomputerat theOak Ridge National Laboratory.[24] Object-storage systems had good adoption in the early 2000s as an archive platform, particularly in the wake of compliance laws likeSarbanes-Oxley. After five years in the market, EMC's Centera product claimed over 3,500 customers and 150petabytesshipped by 2007.[25]Hitachi's HCP product also claims manypetabyte-scale customers.[26]Newer object storage systems have also gotten some traction, particularly around very large custom applications like eBay's auction site, where EMC Atmos is used to manage over 500 million objects a day.[27]As of March 3, 2014, EMC claims to have sold over 1.5 exabytes of Atmos storage.[28]On July 1, 2014,Los Alamos National Labchose theScality RINGas the basis for a 500-petabyte storage environment, which would be among the largest ever.[29] "Captive" object storage systems like Facebook's Haystack have scaled impressively. In April 2009, Haystack was managing 60 billion photos and 1.5 petabytes of storage, adding 220 million photos and 25 terabytes a week.[18]Facebook more recently stated that they were adding 350 million photos a day and were storing 240 billion photos.[30]This could equal as much as 357 petabytes.[31] Cloud storage has become pervasive as many new web and mobile applications choose it as a common way to storebinary data.[32]As the storage back-end to many popular applications likeSmugmugandDropbox,Amazon S3has grown to massive scale, citing over 2-trillion objects stored in April 2013.[33]Two months later, Microsoft claimed that they stored even more objects in Azure at 8.5 trillion.[34]By April 2014, Azure claimed over 20-trillion objects stored.[35]Windows Azure Storage manages Blobs (user files), Tables (structured storage), and Queues (message delivery) and counts them all as objects.[36] IDChas begun to assess the object-based-storage market annually using its MarketScape methodology. IDC describes the MarketScape as: "...a quantitative and qualitative assessment of the characteristics that assess a vendor's current and future success in the said market or market segment and provide a measure of their ascendancy to become a Leader or maintain a leadership. IDC MarketScape assessments are particularly helpful in emerging markets that are often fragmented, have several players, and lack clear leaders."[37] In 2019, IDC ratedDell EMC,Hitachi Data Systems,IBM,NetApp, andScalityas leaders. In the first version of the OSD standard,[38]objects are specified with a 64-bit partition ID and a 64-bit object ID. Partitions are created and deleted within an OSD, and objects are created and deleted within partitions. There are no fixed sizes associated with partitions or objects; they are allowed to grow subject to physical size limitations of the device or logical quota constraints on a partition. An extensible set of attributes describe objects. Some attributes are implemented directly by the OSD, such as the number of bytes in an object and the modification time of an object. There is a special policy tag attribute that is part of the security mechanism. Other attributes are uninterpreted by the OSD. These are set on objects by the higher-level storage systems that use the OSD for persistent storage. For example, attributes might be used to classify objects, or to capture relationships among different objects stored on different OSDs. A list command returns a list of identifiers for objects within a partition, optionally filtered by matches against their attribute values. A list command can also return selected attributes of the listed objects. Read and write commands can be combined, or piggy-backed, with commands to get and set attributes. This ability reduces the number of times a high-level storage system has to cross the interface to the OSD, which can improve overall efficiency. A second generation of the SCSI command set, "Object-Based Storage Devices - 2" (OSD-2) added support for snapshots, collections of objects, and improved error handling.[39] Asnapshotis a point-in-time copy of all the objects in a partition into a new partition. The OSD can implement a space-efficient copy usingcopy-on-writetechniques so that the two partitions share objects that are unchanged between the snapshots, or the OSD might physically copy the data to the new partition. The standard defines clones, which are writeable, and snapshots, which are read-only. A collection is a special kind of object that contains the identifiers of other objects. There are operations to add and delete from collections, and there are operations to get or set attributes for all the objects in a collection. Collections are also used for error reporting. If an object becomes damaged by the occurrence of a media defect (i.e., a bad spot on the disk) or by a software error within the OSD implementation, its identifier is put into a special error collection. The higher-level storage system that uses the OSD can query this collection and take corrective action as necessary. The border between an object store and akey–value storeis blurred, with key–value stores being sometimes loosely referred to as object stores. A traditional block storage interface uses a series of fixed size blocks which are numbered starting at 0. Data must be that exact fixed size and can be stored in a particular block which is identified by its logical block number (LBN). Later, one can retrieve that block of data by specifying its unique LBN. With a key–value store, data is identified by a key rather than a LBN. A key might be "cat" or "olive" or "42". It can be an arbitrary sequence of bytes of arbitrary length. Data (called a value in this parlance) does not need to be a fixed size and also can be an arbitrary sequence of bytes of arbitrary length. One stores data by presenting the key and data (value) to the data store and can later retrieve the data by presenting the key. This concept is seen in programming languages. Python calls them dictionaries, Perl calls them hashes, Java, Rust and C++ call them maps, etc. Several data stores also implement key–value stores such as Memcached, Redis and CouchDB. Object stores are similar to key–value stores in two respects. First, the object identifier orURL(the equivalent of the key) can be an arbitrary string.[40]Second, data may be of an arbitrary size. There are, however, a few key differences between key–value stores and object stores. First, object stores also allow one to associate a limited set of attributes (metadata) with each piece of data. The combination of a key, value, and set of attributes is referred to as an object. Second, object stores are optimized for large amounts of data (hundreds of megabytes or even gigabytes), whereas for key–value stores the value is expected to be relatively small (kilobytes). Finally, object stores usually offer weaker consistency guarantees such aseventual consistency, whereas key–value stores offerstrong consistency.	https://en.wikipedia.org/wiki/Object_storage
Storage efficiencyis the ability to store and manage data that consumes the least amount of space with little to no impact on performance; resulting in a lower total operational cost. Efficiency addresses the real-world demands of managing costs, reducing complexity and limiting risk. TheStorage Networking Industry Association(SNIA) defines storage efficiency in the SNIA Dictionary as follows: The efficiency of an empty enterprise level system is commonly in the 40–70% range, depending on what combination ofRAID, mirroring and other data protection technologies are deployed, and may be even lower for highly redundant remotely mirrored systems. As data is stored on the system, technologies such as deduplication andcompressionmay store data at a greater than 1-to-1 data size-to-space consumed ratio, and efficiency rises, often to over 100% for primary data, and thousands of percent for backup data. Different technologies exist at different and sometimes multiple levels: Snapshottechnology—known formally as "delta snapshot technology"—gives the ability to use the same dataset multiple times for multiple reasons, while storing only the changes between each dataset. Some storage vendors integrate their snapshot capabilities at the operating system and/or application level, enabling access to the data the snapshots are holding at the system and/or application management layers. Terminology around snapshots and "clones" is currently confusing, and care must be taken when evaluating vendor claims. In particular, some vendors call full point-in-time copies "snapshots" or "clones", while others use the same terms to refer to shared-block "delta" snapshots or clones. And some implementations can only do read-only snapshots, while others are able to provide writable ones as well. Data deduplicationtechnologycan be used to very efficiently track and remove duplicate blocks of data inside a storage unit. There are a multitude of implementations, each with their separate advantages and disadvantages. Deduplication is most efficient at the shared storage layer, however, implementations in software and even databases exist. The most suitable candidates for deduplication arebackupandplatform virtualization, because both applications typically produce or use a lot of almost identical copies. However, some vendors are now offering in-place deduplication, which deduplicates primary storage. Thin provisioningtechnologyis a technique to prevent under-utilization by sharing the allocated, but not yet utilized capacity. A good example isGmail, where every Gmail account has a large amount of allocated capacity. Because most Gmail users only use a fraction of the allocated capacity, this "free space" is "shared" among all Gmail users. Actively increasing storage efficiency using these techniques has the following advantages: Backup and restore. Using snapshots, time used for both backup and restoreRTOcan be minimized. This can greatly reduce cost, and reduce hours of downtime to seconds of downtime. Snapshots also allow for betterRPOvalues. Reducing floorspace. When less storage is required to store a given amount of data, less data center floorspace is required. Reducing energy use. When fewer spindles are required to store a given amount of data, less power is required. Provisioning efficiency. Writable delta snapshot technology allows for very fast provisioning of writable data copies. This reduces waiting time in processes that require that data. Examples aredata mining,test data, etc. Snapshot integration at theOSand/or application level also leads to faster provisioning, because system and/or application managers are able to manage their own snapshots without having to wait for storage managers and/or provisioning procedures. All major vendors are implementing one or more of these technologies, because storage efficiency is becoming more and more popular. Customers are facing storage requirements that are growing exponentially and a strong demand for cost-cutting. The major vendors areNetApp,EMC,HDS,IBMandHP. Thiscomputer-storage-related article is astub. You can help Wikipedia byexpanding it.	https://en.wikipedia.org/wiki/Storage_efficiency
Incomputer science, asynthetic file systemor apseudo file systemis a hierarchical interface to non-file objects that appear as if they were regular files in the tree of a disk-based or long-term-storagefile system. These non-file objects may be accessed with the samesystem callsorutility programsas regular files anddirectories. The common term for both regular files and the non-file objects isnode. The benefit of synthetic file systems is that well-known file system semantics can be reused for a universal and easily implementable approach tointerprocess communication. Clients can use such a file system to perform simple file operations on its nodes and do not have to implement complexmessage encoding and passingmethods and other aspects ofprotocol engineering. For most operations, common file utilities can be used, so evenscriptingis quite easy. This is commonly known aseverything is a fileand is generally regarded to have originated fromUnix. In the Unix-world, there is commonly a special filesystemmountedat/proc. This filesystem is implemented within thekerneland publishes information aboutprocesses. For each process, there is a directory (named by theprocess ID), containing detailed information about the process:status, open files,memory maps, mounts, etc. /proc first appeared in Unix 8th Edition,[1]and its functionality was greatly expanded inPlan 9 from Bell Labs.[2] The /sys filesystem on Linux complements /proc, by providing a lot of (non-process related) detailed information about the in-kernel status to userspace. More traditional Unix systems locate this information in sysctl calls. ObexFS is aFUSE-based filesystem that provides access toOBEXobjects via a filesystem. Applications can work on remote objects via the OBEX protocol as if they were simply (local) files. On thePlan 9 from Bell Labsoperating system family, the concept of9Psynthetic filesystem is used as a genericIPCmethod. Contrary to most other operating systems, Plan 9's design is heavily distributed: while in other OS worlds, there are many (and often large) libraries and frameworks for common things, Plan 9 encapsulates them into fileservers. The most important benefit is that applications can be much simpler and that services run network and platform agnostic - they can reside on virtually any host and platform in the network, and virtually any kind of network, as long the fileserver can be mounted by the application. Plan 9 drives this concept expansively: most operating system services, e.g. hardware access and networking stack are presented as fileservers. This way it is trivial to use these resources remotely (e.g. one host directly accessing another host's block devices or network interfaces) without the need of additional protocols. Other implementations of the 9P file system protocol also exists for many other systems and environments.[3] Debugging embedded systems or even system-on-chip (SoC) devices is widely known to be difficult.[citation needed]Several protocols have been implemented to provide direct access to in-chip devices, but they tend to be proprietary, complex and hard to handle. Based on9P, Plan 9's network filesystem, studies suggest using synthetic filesystems as universal access scheme to that information. The major benefit is that 9P is very simple and so quite easy to implement in hardware and can be easily used and over virtually any kind of network (from a serial link up to the internet). The major argument for using synthetic filesystems might be the flexibility and easy access toservice-oriented architectures. Once a noticeable number of applications use this scheme, the overall overhead (code, resource consumption, maintenance work) can be reduced significantly. Many general arguments for SOAs also apply here. Arguments against synthetic filesystems include the fact that filesystem semantics may not fit all application scenarios. For example, complexremote procedure callswith many parameters tend to be hard to map to filesystem schemes,[citation needed]and may require application redesign.	https://en.wikipedia.org/wiki/Synthetic_file_system
Avirtual file system(VFS) orvirtual filesystem switchis an abstract layer on top of a more concretefile system. The purpose of a VFS is to allow client applications to access different types of concrete file systems in a uniform way. A VFS can, for example, be used to accesslocaland network storage devices transparently without the client application noticing the difference. It can be used to bridge the differences inWindows,classic Mac OS/macOSandUnixfilesystems, so that applications can access files on local file systems of those types without having to know what type of file system they are accessing. A VFS specifies aninterface(or a "contract") between thekerneland a concrete file system. Therefore, it is easy to add support for new file system types to the kernel simply by fulfilling the contract. The terms of the contract might change incompatibly from release to release, which would require that concrete file system support be recompiled, and possibly modified before recompilation, to allow it to work with a new release of the operating system; or the supplier of the operating system might make only backward-compatible changes to the contract, so that concrete file system support built for a given release of the operating system would work with future versions of the operating system. One of the first virtual file system mechanisms onUnix-likesystems was introduced bySun MicrosystemsinSunOS2.0 in 1985.[2]It allowed Unix system calls to access localUFSfile systems and remoteNFSfile systems transparently. For this reason, Unix vendors who licensed the NFS code from Sun often copied the design of Sun's VFS. Other file systems could be plugged into it also: there was an implementation of theMS-DOSFATfile system developed at Sun that plugged into the SunOS VFS, although it wasn't shipped as a product until SunOS 4.1. The SunOS implementation was the basis of the VFS mechanism inSystem V Release 4. John Heidemanndeveloped astackingVFS under SunOS 4.0 for the experimentalFicus file system. This design provided forcode reuseamong file system types with differing but similar semantics (e.g., an encrypting file system could reuse all of the naming and storage-management code of a non-encrypting file system). Heidemann adapted this work for use in4.4BSDas a part of histhesisresearch; descendants of this code underpin the file system implementations in modern BSD derivatives includingmacOS. Other Unix virtual file systems include the File System Switch inSystem V Release 3, the Generic File System inUltrix, and the VFS inLinux. InOS/2andMicrosoft Windows, the virtual file system mechanism is called theInstallable File System. TheFilesystem in Userspace(FUSE) mechanism allowsuserlandcode to plug into the virtual file system mechanism in Linux,NetBSD,FreeBSD,OpenSolaris, and macOS. In Microsoft Windows, virtual filesystems can also be implemented through userlandShell namespace extensions; however, they do not support the lowest-level file system accessapplication programming interfacesin Windows, so not all applications will be able to access file systems that are implemented as namespace extensions.KIOandGVfs/GIOprovide similar mechanisms in theKDEandGNOMEdesktop environments (respectively), with similar limitations, although they can be made to use FUSE techniques and therefore integrate smoothly into the system. Sometimes Virtual File System refers to a file or a group of files (not necessarily inside a concrete file system) that acts as a manageable container which should provide the functionality of a concrete file system through the usage of software. Examples of such containers are CBFS Storage or asingle-file virtual file systemin an emulator likePCTaskor so-calledWinUAE, Oracle'sVirtualBox, Microsoft'sVirtual PC,VMware. The primary benefit for this type of file system is that it is centralized and easy to remove. A single-file virtual file system may include all the basic features expected of any file system (virtual or otherwise), but access to the internal structure of these file systems is often limited to programs specifically written to make use of the single-file virtual file system (instead of implementation through a driver allowing universal access). Another major drawback is that performance is relatively low when compared to other virtual file systems. Low performance is mostly due to the cost of shuffling virtual files when data is written or deleted from the virtual file system. Direct examples of single-file virtual file systems include emulators, such as PCTask and WinUAE, which encapsulate not only the filesystem data but also emulated disk layout. This makes it easy to treat an OS installation like any other piece of software—transferring it with removable media or over the network. TheAmigaemulatorPCTaskemulated anIntelPC8088based machine clocked at 4.77MHz(and later an80486SX clocked at 25 MHz). Users of PCTask could create a file of large size on the Amiga filesystem, and this file would be virtually accessed from the emulator as if it were a real PC Hard Disk. The file could be formatted with the FAT16 filesystem to store normal MS-DOS or Windows files.[1][2] TheUAEforWindows,WinUAE, allows for large single files on Windows to be treated as Amiga file systems. In WinUAE this file is called ahardfile.[3] UAE could also treat a directory on the host filesystem (Windows,Linux,macOS,AmigaOS) as an Amiga filesystem.[4]	https://en.wikipedia.org/wiki/Virtual_file_system
Theinode pointer structureis a structure adopted by theinodeof a file in theVersion 6 Unixfile system,Version 7 Unixfile system, andUnix File System(UFS) to list the addresses of a file'sdata blocks. It is also adopted by many related file systems, including theext3file system, popular with Linux users. In the file system used inVersion 6 Unix, an inode contains eight pointers:[1] In the file system used inVersion 7 Unix, an inode contains thirteen pointers:[2] In theUnix file system, an inode contains fifteen pointers:[3] The levels of indirection indicate the number of pointer that must be followed before reaching actual file data. The structure is partially illustrated in the diagram accompanying this article. The structure allows for inodes to describe very large files in file systems with a fixed logical block size. Central to the mechanism is that blocks of addresses (also calledindirect blocks) are only allocated as needed. For example, in theUnix file system, a 12-block file would be described using just the inode because its blocks fit into the number of direct pointers available. However, a 13-block file needs an indirect block to contain the thirteenth address. The inode pointer structure not only allows for files to easily be allocated to non-contiguous blocks, it also allows the data at a particular location inside a file to be easily located. This is possible because the logical block size is fixed. For example, if each block is 8 kB, file data at 112 kB to 120 kB would be pointed to by the third pointer of the first indirect block (assuming twelve direct pointers in the inode pointer structure). Unlike inodes, which are fixed in number and allocated in a special part of the file system, the indirect blocks may be of any number and are allocated in the same part of the file system as data blocks. The number of pointers in the indirect blocks is dependent on the block size and size of block pointers. Example: with a 512-byte block size, and 4-byte block pointers, each indirect block can consist of 128 (512 / 4) pointers.	https://en.wikipedia.org/wiki/Inode_pointer_structure
inotify(inodenotify) is aLinux kernelsubsystem created by John McCutchan, which monitors changes to thefilesystem, and reports those changes to applications. It can be used to automatically update directory views, reload configuration files, log changes, backup, synchronize, and upload. Theinotifywaitandinotifywatchcommands (maintained by Eric Curtin as part of the inotify-tools project) allow using the inotify subsystem from the command line.[1]One major use is indesktop searchutilities likeBeagle, where its functionality permitsreindexingof changed files without scanning the filesystem for changes every few minutes, which would be very inefficient. inotify replaced an earlier facility,dnotify, which had similar goals. Inotify was merged into theLinux kernel mainlinein kernel version 2.6.13, released on August 29, 2005;[2]later kernel versions included further improvements. The required library interfaces were added into theGNU C Library(glibc) in its version 2.4, released in March 2006, while the support for inotify was completed in glibc version 2.5, released in September 2006.[3] Limitations imposed by inotify include the following: There are a number of advantages when using inotify when compared to the olderdnotifyAPI that it replaced.[7][8][9]With dnotify, a program had to use onefile descriptorfor each directory that it was monitoring. This can become a bottleneck since the limit of file descriptors per process could be reached. Later, fanotify was created to overcome this issue. The use of file descriptors along with dnotify also proved to be a problem when using removable media. Devices could not be unmounted since file descriptors kept the resource busy. Another drawback of dnotify is the level of granularity, since programmers can only monitor changes at the directory level. To access detailed information about the environmental changes that occur when a notification message is sent, a stat structure must be used; this is considered a necessary evil in that a cache of stat structures has to be maintained, for every new stat structure generated a comparison is run against the cached one. The inotify API uses fewer file descriptors, allowing programmers to use the established select and poll interface, rather than the signal notification system used bydnotify. This also makes integration with existing select- or poll-based libraries (likeGLib) easier.	https://en.wikipedia.org/wiki/Inotify
Carry-less Multiplication(CLMUL) is an extension to thex86instruction set used bymicroprocessorsfromIntelandAMDwhich was proposed by Intel in March 2008[1]and made available in theIntel Westmere processorsannounced in early 2010. Mathematically, the instruction implements multiplication of polynomials over thefinite fieldGF(2) where the bitstringa0a1…a63{\displaystyle a_{0}a_{1}\ldots a_{63}}represents the polynomiala0+a1X+a2X2+⋯+a63X63{\displaystyle a_{0}+a_{1}X+a_{2}X^{2}+\cdots +a_{63}X^{63}}. The CLMUL instruction also allows a more efficient implementation of the closely related multiplication of larger finite fields GF(2k) than the traditional instruction set.[2] One use of these instructions is to improve the speed of applications doing block cipher encryption inGalois/Counter Mode, which depends on finite field GF(2k) multiplication. Another application is the fast calculation ofCRC values,[3]including those used to implement theLZ77sliding windowDEFLATEalgorithm inzlibandpngcrush.[4] ARMv8 also has a version of CLMUL. SPARC calls their version XMULX, for "XOR multiplication". The instruction computes the 128-bitcarry-less productof two 64-bit values. The destination is a128-bit XMM register. The source may be another XMM register or memory. An immediate operand specifies which halves of the 128-bit operands are multiplied.Mnemonicsspecifying specific values of the immediate operand are also defined: A EVEX vectorized version (VPCLMULQDQ) is seen inAVX-512. The presence of the CLMUL instruction set can be checked by testing one of theCPU feature bits.	https://en.wikipedia.org/wiki/CLMUL_instruction_set
RDRAND(for "read random") is aninstructionfor returning random numbers from anIntelon-chiphardware random number generatorwhich has been seeded by an on-chip entropy source.[1]It is also known asIntel Secure Key Technology,[2]codenamedBull Mountain.[3]Intel introduced the feature around 2012, and AMD added support for the instruction in June 2015. (RDRANDis available inIvy Bridgeprocessors[a]and is part of theIntel 64andIA-32instruction set architectures.)[5] The random number generator is compliant with security and cryptographic standards such asNIST SP 800-90A,[6]FIPS 140-2, andANSI X9.82.[1]Intel also requested Cryptography Research Inc. to review the random number generator in 2012, which resulted in the paperAnalysis of Intel's Ivy Bridge Digital Random Number Generator.[7] RDSEEDis similar toRDRANDand provides lower-level access to the entropy-generating hardware. TheRDSEEDgenerator and processor instructionrdseedare available withIntel Broadwell CPUs[8]andAMD Zen CPUs.[9] TheCPUIDinstruction can be used on both AMD and IntelCPUsto check whether theRDRANDinstruction is supported. If it is, bit 30 of the ECX register is set after calling CPUID standard function01H.[10]AMD processors are checked for the feature using the same test.[11]RDSEEDavailability can be checked on Intel CPUs in a similar manner. IfRDSEEDis supported, the bit 18 of the EBX register is set after calling CPUID standard function07H.[12] The opcode forRDRANDis0x0F 0xC7, followed by a ModRM byte that specifies the destination register and optionally combined with a REX prefix in 64-bit mode.[13] Intel Secure KeyisIntel's name for both theRDRANDinstruction and the underlyingrandom number generator(RNG) hardware implementation,[1]which was codenamed "Bull Mountain" during development.[14]Intel calls their RNG a "digital random number generator" or DRNG. The generator takes pairs of 256-bit raw entropy samples generated by the hardwareentropy sourceand applies them to anAdvanced Encryption Standard(AES) (inCBC-MACmode) conditioner which reduces them to a single 256-bit conditioned entropy sample. A deterministic random-bit generator calledCTR DRBGdefined inNIST SP 800-90Ais seeded by the output from the conditioner, providing cryptographically secure random numbers to applications requesting them via theRDRANDinstruction.[1][14]The hardware will issue a maximum of 511 128-bit samples before changing the seed value. Using theRDSEEDoperation provides access to the conditioned 256-bit samples from the AES-CBC-MAC. TheRDSEEDinstruction was added to Intel Secure Key for seeding another pseudorandom number generator,[15]available inBroadwellCPUs. The entropy source for theRDSEEDinstruction runs asynchronously on a self-timed circuit and uses thermal noise within the silicon to output a random stream of bits at the rate of 3 GHz,[16]slower than the effective 6.4 Gbit/s obtainable fromRDRAND(both rates are shared between allcoresandthreads).[17]TheRDSEEDinstruction is intended for seeding asoftware PRNGof arbitrary width, whereas theRDRANDis intended for applications that merely require high-quality random numbers. If cryptographic security is not required, a software PRNG such asXorshiftis usually faster.[18] On an Intel Core i7-7700K, 4500 MHz (45 × 100 MHz) processor (Kaby Lake-S microarchitecture), a singleRDRANDorRDSEEDinstruction takes 110 ns, or 463 clock cycles, regardless of the operand size (16/32/64 bits). This number of clock cycles applies to all processors withSkylakeorKaby Lakemicroarchitecture. On theSilvermontmicroarchitecture processors, each of the instructions take around 1472 clock cycles, regardless of the operand size; and onIvy BridgeprocessorsRDRANDtakes up to 117 clock cycles.[19] On an AMD Ryzen CPU, each of the instructions takes around 1200 clock cycles for 16-bit or 32-bit operand, and around 2500 clock cycles for a 64-bit operand.[19] An astrophysical Monte Carlo simulator examined the time to generate 10764-bit random numbers usingRDRANDon a quad-core Intel i7-3740 QM processor. They found that a C implementation ofRDRANDran about 2× slower than the default random number generator in C, and about 20× slower than theMersenne Twister. Although a Python module ofRDRANDhas been constructed, it was found to be 20× slower than the default random number generator in Python,[20]although a performance comparison between aPRNGandCSPRNGcannot be made. A microcode update released by Intel in June 2020, designed to mitigate the CrossTalk vulnerability (see thesecurity issuessection below), negatively impacts the performance ofRDRANDandRDSEEDdue to additional security controls. On processors with the mitigations applied, each affected instruction incurs additional latency and simultaneous execution ofRDRANDorRDSEEDacross cores is effectively serialised. Intel introduced a mechanism to relax these security checks, thus reducing the performance impact in most scenarios, but Intel processors do not apply this security relaxation by default.[21] Visual C++ 2015 provides intrinsic wrapper support for theRDRANDandRDSEEDfunctions.[22]GCC4.6+ andClang3.2+ provideintrinsic functionsforRDRANDwhen-mrdrndis specified in theflags,[23]also setting__RDRND__to allowconditional compilation. Newer versions additionally provideimmintrin.hto wrap these built-ins into functions compatible with version 12.1+ of Intel's C Compiler. These functions write random data to the location pointed to by their parameter, and return 1 on success.[24] It is an option to generate cryptographically secure random numbers usingRDRANDandRDSEEDinOpenSSL, to help secure communications. Scientific application ofRDRANDin aMonte Carlosimulator was evaluated, focusing on performance and reproducibility, compared to other random number generators. It led to the conclusion that usingRDRANDas opposed to Mersenne Twister doesn't provide different results, but worse performance and reproducibility.[25][20] In September 2013, in response to aNew York Timesarticlerevealing the NSA's effort to weaken encryption,[26]Theodore Ts'opublicly posted concerning the use ofRDRANDfor/dev/randomin theLinux kernel:[27] I am so glad I resisted pressure from Intel engineers to let/dev/randomrely only on theRDRANDinstruction. To quote from the [New York Times article[26]]: "By this year, theSigint Enabling Projecthad found ways inside some of the encryption chips that scramble information for businesses and governments, either by working with chipmakers to insert back doors..." Relying solely on the hardware random number generator which is using an implementation sealed inside a chip which is impossible to audit is a BAD idea. Linus Torvaldsdismissed concerns about the use ofRDRANDin the Linux kernel and pointed out that it is not used as the only source of entropy for/dev/random, but rather used to improve the entropy by combining the values received fromRDRANDwith other sources of randomness.[28][29]However, Taylor Hornby of Defuse Security demonstrated that the Linux random number generator could become insecure if a backdoor is introduced into theRDRANDinstruction that specifically targets the code using it. Hornby's proof-of-concept implementation works on an unmodified Linux kernel prior to version 3.13.[30][31][32]The issue was mitigated in the Linux kernel in 2013.[33] Developers changed theFreeBSDkernel away from usingRDRANDandVIA PadLockdirectly with the comment "For FreeBSD 10, we are going to backtrack and removeRDRANDand Padlock backends and feed them intoYarrowinstead of delivering their output directly to/dev/random. It will still be possible to access hardware random number generators, that is,RDRAND, Padlock etc., directly by inline assembly or by using OpenSSL from userland, if required, but we cannot trust them any more."[28][34]FreeBSD /dev/random usesFortunaand RDRAND started from FreeBSD 11.[35] On 9 June 2020, researchers fromVrije Universiteit Amsterdampublished aside-channel attacknamed CrossTalk (CVE-2020-0543) that affectedRDRANDon a number of Intel processors.[36]They discovered that outputs from the hardware digital random number generator (DRNG) were stored in a staging buffer that was shared across all cores. The vulnerability allowed malicious code running on an affected processor to readRDRANDandRDSEEDinstruction results from a victim application running on another core of that same processor, including applications running insideIntel SGX enclaves.[36]The researchers developed a proof-of-concept exploit[37]which extracted a completeECDSAkey from an SGX enclave running on a separate CPU core after only one signature operation.[36]The vulnerability affects scenarios where untrusted code runs alongside trusted code on the same processor, such as in a shared hosting environment. Intel refers to the CrossTalk vulnerability as Special Register Buffer Data Sampling (SRBDS). In response to the research, Intel released microcode updates to mitigate the issue. The updated microcode ensures that off-core accesses are delayed until sensitive operations – specifically theRDRAND,RDSEED, andEGETKEYinstructions – are completed and the staging buffer has been overwritten.[21]The SRBDS attack also affects other instructions, such as those that readMSRs, but Intel did not apply additional security protections to them due to performance concerns and the reduced need for confidentiality of those instructions' results.[21]A wide range of Intel processors released between 2012 and 2019 were affected, including desktop, mobile, and server processors.[38][39]The mitigations themselves resulted in negative performance impacts when using the affected instructions, particularly when executed in parallel by multi-threaded applications, due to increased latency introduced by the security checks and the effective serialisation of affected instructions across cores. Intel introduced an opt-out option, configurable via theIA32_MCU_OPT_CTRLMSR on each logical processor, which improves performance by disabling the additional security checks for instructions executing outside of an SGX enclave.[21]	https://en.wikipedia.org/wiki/RDRAND
Advanced Vector Extensions(AVX, also known asGesher New Instructionsand thenSandy Bridge New Instructions) areSIMDextensions to thex86instruction set architectureformicroprocessorsfromIntelandAdvanced Micro Devices(AMD). They were proposed by Intel in March 2008 and first supported by Intel with theSandy Bridge[1]microarchitecture shipping in Q1 2011 and later by AMD with theBulldozer[2]microarchitecture shipping in Q4 2011. AVX provides new features, new instructions, and a new coding scheme. AVX2(also known asHaswell New Instructions) expands most integer commands to 256 bits and introduces new instructions. They were first supported by Intel with theHaswellmicroarchitecture, which shipped in 2013. AVX-512expands AVX to 512-bit support using a newEVEX prefixencoding proposed by Intel in July 2013 and first supported by Intel with theKnights Landingco-processor, which shipped in 2016.[3][4]In conventional processors, AVX-512 was introduced withSkylakeserver and HEDT processors in 2017. AVX uses sixteen YMM registers to perform a single instruction on multiple pieces of data (seeSIMD). Each YMM register can hold and do simultaneous operations (math) on: The width of the SIMD registers is increased from 128 bits to 256 bits, and renamed from XMM0–XMM7 to YMM0–YMM7 (inx86-64mode, from XMM0–XMM15 to YMM0–YMM15). The legacySSEinstructions can still be utilized via theVEX prefixto operate on the lower 128 bits of the YMM registers. AVX introduces a three-operand SIMD instruction format calledVEX coding scheme, where the destination register is distinct from the two source operands. For example, anSSEinstruction using the conventional two-operand forma←a+bcan now use a non-destructive three-operand formc←a+b, preserving both source operands. Originally, AVX's three-operand format was limited to the instructions with SIMD operands (YMM), and did not include instructions with general purpose registers (e.g. EAX). It was later used for coding new instructions on general purpose registers in later extensions, such asBMI. VEX coding is also used for instructions operating on the k0-k7 mask registers that were introduced withAVX-512. Thealignmentrequirement of SIMD memory operands is relaxed.[5]Unlike their non-VEX coded counterparts, most VEX coded vector instructions no longer require their memory operands to be aligned to the vector size. Notably, theVMOVDQAinstruction still requires its memory operand to be aligned. The newVEX coding schemeintroduces a new set of code prefixes that extends theopcodespace, allows instructions to have more than two operands, and allows SIMD vector registers to be longer than 128 bits. The VEX prefix can also be used on the legacy SSE instructions giving them a three-operand form, and making them interact more efficiently with AVX instructions without the need forVZEROUPPERandVZEROALL. The AVX instructions support both 128-bit and 256-bit SIMD. The 128-bit versions can be useful to improve old code without needing to widen the vectorization, and avoid the penalty of going from SSE to AVX, they are also faster on some early AMD implementations of AVX. This mode is sometimes known as AVX-128.[6] These AVX instructions are in addition to the ones that are 256-bit extensions of the legacy 128-bit SSE instructions; most are usable on both 128-bit and 256-bit operands. Issues regarding compatibility between future Intel and AMD processors are discussed underXOP instruction set. AVX adds new register-state through the 256-bit wide YMM register file, so explicitoperating systemsupport is required to properly save and restore AVX's expanded registers betweencontext switches. The following operating system versions support AVX: Advanced Vector Extensions 2 (AVX2), also known asHaswell New Instructions,[24]is an expansion of the AVX instruction set introduced in Intel'sHaswell microarchitecture. AVX2 makes the following additions: Sometimes three-operandfused multiply-accumulate(FMA3) extension is considered part of AVX2, as it was introduced by Intel in the same processor microarchitecture. This is a separate extension using its ownCPUIDflag and is described onits own pageand not below. AVX-512are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture proposed byIntelin July 2013.[3] AVX-512 instructions are encoded with the newEVEX prefix. It allows 4 operands, 8 new 64-bitopmask registers, scalar memory mode with automatic broadcast, explicit rounding control, and compressed displacement memoryaddressing mode. The width of the register file is increased to 512 bits and total register count increased to 32 (registers ZMM0-ZMM31) in x86-64 mode. AVX-512 consists of multiple instruction subsets, not all of which are meant to be supported by all processors implementing them. The instruction set consists of the following: Only the core extension AVX-512F (AVX-512 Foundation) is required by all implementations, though all current implementations also support CD (conflict detection). All central processors with AVX-512 also support VL, DQ and BW. The ER, PF, 4VNNIW and 4FMAPS instruction set extensions are currently only implemented in Intel computing coprocessors. The updated SSE/AVX instructions in AVX-512F use the same mnemonics as AVX versions; they can operate on 512-bit ZMM registers, and will also support 128/256 bit XMM/YMM registers (with AVX-512VL) and byte, word, doubleword and quadword integer operands (with AVX-512BW/DQ and VBMI).[26]: 23 [28] ^Note 1: Intel does not officially support AVX-512 family of instructions on theAlder Lakemicroprocessors. In early 2022, Intel began disabling in silicon (fusing off) AVX-512 in Alder Lake microprocessors to prevent customers from enabling AVX-512.[29]In older Alder Lake family CPUs with some legacy combinations of BIOS and microcode revisions, it was possible to execute AVX-512 family instructions when disabling all the efficiency cores which do not contain the silicon for AVX-512.[30][31][32] AVX-VNNI is aVEX-coded variant of theAVX512-VNNIinstruction set extension. Similarly, AVX-IFMA is aVEX-coded variant ofAVX512-IFMA. These extensions provide the same sets of operations as their AVX-512 counterparts, but are limited to 256-bit vectors and do not support any additional features ofEVEXencoding, such as broadcasting, opmask registers or accessing more than 16 vector registers. These extensions allow support of VNNI and IFMA operations even when fullAVX-512support is not implemented in the processor. AVX10, announced in July 2023,[38]is a new, "converged" AVX instruction set. It addresses several issues of AVX-512, in particular that it is split into too many parts[39](20 feature flags). The initial technical paper also made 512-bit vectors optional to support, but as of revision 3.0 vector length enumeration is removed and 512-bit vectors are mandatory.[40] AVX10 presents a simplified CPUID interface to test for instruction support, consisting of the AVX10 version number (indicating the set of instructions supported, with later versions always being a superset of an earlier one).[41]For example, AVX10.2 indicates that a CPU is capable of the second version of AVX10.[42]Initial revisions of the AVX10 technical specifications also included maximum supported vector length as part of the ISA extension name, e.g. AVX10.2/256 would mean a second version of AVX10 with vector length up to 256 bits, but later revisions made that unnecessary. The first version of AVX10, notated AVX10.1, doesnotintroduce any instructions or encoding features beyond what is already in AVX-512 (specifically, in IntelSapphire Rapids: AVX-512F, CD, VL, DQ, BW, IFMA, VBMI, VBMI2, BITALG, VNNI, GFNI, VPOPCNTDQ, VPCLMULQDQ, VAES, BF16, FP16). For CPUs supporting AVX10 and 512-bit vectors, all legacy AVX-512 feature flags will remain set to facilitate applications supporting AVX-512 to continue using AVX-512 instructions.[42] AVX10.1 was first released in IntelGranite Rapids[42](Q3 2024) and AVX10.2 will be available inDiamond Rapids.[43] APX is a new extension. It is not focused on vector computation, but provides RISC-like extensions to the x86-64 architecture by doubling the number of general-purpose registers to 32 and introducing three-operand instruction formats. AVX is only tangentially affected as APX introduces extended operands.[44][45] Since AVX instructions are wider, they consume more power and generate more heat. Executing heavy AVX instructions at high CPU clock frequencies may affect CPU stability due to excessivevoltage droopduring load transients. Some Intel processors have provisions to reduce theTurbo Boostfrequency limit when such instructions are being executed. This reduction happens even if the CPU hasn't reached its thermal and power consumption limits. OnSkylakeand its derivatives, the throttling is divided into three levels:[66][67] The frequency transition can be soft or hard. Hard transition means the frequency is reduced as soon as such an instruction is spotted; soft transition means that the frequency is reduced only after reaching a threshold number of matching instructions. The limit is per-thread.[66] InIce Lake, only two levels persist:[68] Rocket Lakeprocessors do not trigger frequency reduction upon executing any kind of vector instructions regardless of the vector size.[68]However, downclocking can still happen due to other reasons, such as reaching thermal and power limits. Downclocking means that using AVX in a mixed workload with an Intel processor can incur a frequency penalty. Avoiding the use of wide and heavy instructions help minimize the impact in these cases. AVX-512VL allows for using 256-bit or 128-bit operands in AVX-512 instructions, making it a sensible default for mixed loads.[69] On supported and unlocked variants of processors that down-clock, the clock ratio reduction offsets (typically called AVX and AVX-512 offsets) are adjustable and may be turned off entirely (set to 0x) via Intel's Overclocking / Tuning utility or in BIOS if supported there.[70]	https://en.wikipedia.org/wiki/Advanced_Vector_Extensions_2
AVX-512are 512-bit extensions to the 256-bitAdvanced Vector ExtensionsSIMDinstructions forx86instruction set architecture(ISA) proposed byIntelin July 2013, and first implemented in the 2016 IntelXeon Phi x200(Knights Landing),[1]and then later in a number ofAMDand other Intel CPUs (see list below). AVX-512 consists of multiple extensions that may be implemented independently.[2]This policy is a departure from the historical requirement of implementing the entire instruction block. Only the core extension AVX-512F (AVX-512 Foundation) is required by all AVX-512 implementations. Besides widening most 256-bit instructions, the extensions introduce various new operations, such as new data conversions,scatteroperations, and permutations.[2]The number of AVX registers is increased from 16 to 32, and eight new "mask registers" are added, which allow for variable selection and blending of the results of instructions. In CPUs with the vector length (VL) extension—included in most AVX-512-capable processors (see§ CPUs with AVX-512)—these instructions may also be used on the 128-bit and 256-bit vector sizes. AVX-512 is not the first 512-bit SIMD instruction set that Intel has introduced in processors: the earlier 512-bit SIMD instructions used in the first generationXeon Phicoprocessors, derived from Intel'sLarrabeeproject, are similar but not binary compatible and only partially source compatible.[1] The successor to AVX-512 isAVX10, announced in July 2023.[3]AVX10 simplifies detection of supported instructions by introducing a version of the instruction set, where each subsequent version includes all instructions from the previous one. In the initial revisions of the AVX10 specification, the support for 512-bit vectors was made optional, which would allow Intel to support it in theirE-cores. In later revisions, Intel made 512-bit vectors mandatory, with the intention to support 512-bit vectors both in P- and E-cores. The initial version 1 of AVX10 does not add new instructions compared to AVX-512, and for processors supporting 512-bit vectors it is equivalent to AVX-512 (in the set supported by IntelSapphire Rapidsprocessors). Later AVX10 versions will introduce new features. The AVX-512 instruction set consists of several separate sets each having their own unique CPUID feature bit. However, they are typically grouped by the processor generation that implements them. F, CD, ER, PF:introduced withXeon Phi x200 (Knights Landing)and Xeon Scalable (Skylake SP"Purley"), with the last two (ER and PF) being specific to Knights Landing & Knights Mill. 4VNNIW, 4FMAPS:introduced with and specific toKnights Mill.[4][5] VL, DQ, BW:introduced with Skylake-X/SP andCannon Lake. IFMA, VBMI:introduced withCannon Lake.[7] VNNI:introduced with Cascade Lake. VPOPCNTDQ:Vectorpopulation countinstruction. Introduced with Knights Mill andIce Lake.[8] VBMI2, BITALG:introduced with Ice Lake.[8] VP2INTERSECT:introduced with Tiger Lake. GFNI, VPCLMULQDQ, VAES:introduced with Ice Lake.[8] TheVEX prefixused by AVX and AVX2, while flexible, did not leave enough room for the features Intel wanted to add to AVX-512. This has led them to define a new prefix calledEVEX. Compared to VEX, EVEX adds the following benefits:[5] The extended registers, SIMD width bit, and opmask registers of AVX-512 are mandatory and all require support from the OS. The AVX-512 instructions are designed to mix with 128/256-bit AVX/AVX2 instructions without a performance penalty. However, AVX-512VL extensions allows the use of AVX-512 instructions on 128/256-bit registers XMM/YMM, so most SSE and AVX/AVX2 instructions havenew AVX-512 versions encoded with the EVEX prefixwhich allow access to new features such as opmask and additional registers. Unlike AVX-256, the new instructions do not have new mnemonics but share namespace with AVX, making the distinction between VEX and EVEX encoded versions of an instruction ambiguous in the source code. Since AVX-512F only works on 32- and 64-bit values, SSE and AVX/AVX2 instructions that operate on bytes or words are available only with the AVX-512BW extension (byte & word support).[5] The width of theSIMDregister file is increased from 256 bits to 512 bits, and expanded from 16 to a total of 32 registers ZMM0–ZMM31. These registers can be addressed as 256 bit YMM registers from AVX extensions and 128-bit XMM registers fromStreaming SIMD Extensions, and legacy AVX and SSE instructions can be extended to operate on the 16 additional registers XMM16-XMM31 and YMM16-YMM31 when using EVEX encoded form. AVX-512 vector instructions may indicate an opmask register to control which values are written to the destination, the instruction encoding supports 0–7 for this field, however, only opmask registers k1–k7 (of k0–k7) can be used as the mask corresponding to the value 1–7, whereas the value 0 is reserved for indicating no opmask register is used, i.e. a hardcoded constant (instead of 'k0') is used to indicate unmasked operations. The special opmask register 'k0' is still a functioning, valid register, it can be used in opmask register manipulation instructions or used as the destination opmask register.[9]A flag controls the opmask behavior, which can either be "zero", which zeros everything not selected by the mask, or "merge", which leaves everything not selected untouched. The merge behavior is identical to the blend instructions. The opmask registers are normally 16 bits wide, but can be up to 64 bits with the AVX-512BW extension.[5]How many of the bits are actually used, though, depends on the vector type of the instructions masked. For the 32-bit single float or double words, 16 bits are used to mask the 16 elements in a 512-bit register. For double float and quad words, at most 8 mask bits are used. The opmask register is the reason why several bitwise instructions which naturally have no element widths had them added in AVX-512. For instance, bitwise AND, OR or 128-bit shuffle now exist in both double-word and quad-word variants with the only difference being in the final masking. The opmask registers have a new mini extension of instructions operating directly on them. Unlike the rest of the AVX-512 instructions, these instructions are all VEX encoded. The initial opmask instructions are all 16-bit (Word) versions. With AVX-512DQ 8-bit (Byte) versions were added to better match the needs of masking 8 64-bit values, and with AVX-512BW 32-bit (Double) and 64-bit (Quad) versions were added so they can mask up to 64 8-bit values. The instructions KORTEST and KTEST can be used to set the x86 flags based on mask registers, so that they may be used together with non-SIMD x86 branch and conditional instructions. Many AVX-512 instructions are simply EVEX versions of old SSE or AVX instructions. There are, however, several new instructions, and old instructions that have been replaced with new AVX-512 versions. The new or heavily reworked instructions are listed below. Thesefoundationinstructions also include the extensions from AVX-512VL and AVX-512BW since those extensions merely add new versions of these instructions instead of new instructions. There are no EVEX-prefixed versions of the blend instructions fromSSE4; instead, AVX-512 has a new set of blending instructions using mask registers as selectors. Together with the general compare into mask instructions below, these may be used to implement generic ternary operations or cmov, similar toXOP's VPCMOV. Since blending is an integral part of the EVEX encoding, these instructions may also be considered basic move instructions. Using the zeroing blend mode, they can also be used as masking instructions. AVX-512F has four new compare instructions. Like theirXOPcounterparts they use the immediate field to select between 8 different comparisons. Unlike their XOP inspiration, however, they save the result to a mask register and initially only support doubleword and quadword comparisons. The AVX-512BW extension provides the byte and word versions. Note that two mask registers may be specified for the instructions, one to write to and one to declare regular masking.[5] The final way to set masks is using Logical Set Mask. These instructions perform either AND or NAND, and then set the destination opmask based on the result values being zero or non-zero. Note that like the comparison instructions, these take two opmask registers, one as destination and one a regular opmask. The compress and expand instructions match theAPLoperations of the same name. They use the opmask in a slightly different way from other AVX-512 instructions. Compress only saves the values marked in the mask, but saves them compacted by skipping and not reserving space for unmarked values. Expand operates in the opposite way, by loading as many values as indicated in the mask and then spreading them to the selected positions. A new set ofpermute instructionshave been added for full two input permutations. They all take three arguments, two source registers and one index; the result is output by either overwriting the first source register or the index register. AVX-512BW extends the instructions to also include 16-bit (word) versions, and the AVX-512_VBMI extension defines the byte versions of the instructions. Two new instructions added can logically implement all possible bitwise operations between three inputs. They take three registers as input and an 8-bit immediate field. Each bit in the output is generated using a lookup of the three corresponding bits in the inputs to select one of the 8 positions in the 8-bit immediate. Since only 8 combinations are possible using three bits, this allow all possible 3 input bitwise operations to be performed.[5]These are the only bitwise vector instructions in AVX-512F; EVEX versions of the two source SSE and AVX bitwise vector instructions AND, ANDN, OR and XOR were added in AVX-512DQ. The difference in the doubleword and quadword versions is only the application of the opmask. A number of conversion or move instructions were added; these complete the set of conversion instructions available from SSE2. Among the unique new features in AVX-512F are instructions to decompose floating-point values and handlespecial floating-point values. Since these methods are completely new, they also exist in scalar versions. This is the second set of new floating-point methods, which includes new scaling and approximate calculation of reciprocal, and reciprocal of square root. The approximate reciprocal instructions guarantee to have at most a relative error of 2−14.[5] The instructions in AVX-512 conflict detection (AVX-512CD) are designed to help efficiently calculate conflict-free subsets of elements in loops that normally could not be safely vectorized.[10] AVX-512 exponential and reciprocal (AVX-512ER) instructions contain more accurate approximate reciprocal instructions than those in the AVX-512 foundation; relative error is at most 2−28. They also contain two new exponential functions that have a relative error of at most 2−23.[5] AVX-512 prefetch (AVX-512PF) instructions contain new prefetch operations for the new scatter and gather functionality introduced inAVX2and AVX-512.T0prefetch means prefetching into level 1 cache andT1means prefetching into level 2 cache. The two sets of instructions perform multiple iterations of processing. They are generally only found in Xeon Phi products. AVX-512DQ adds new doubleword and quadword instructions. AVX-512BW adds byte and words versions of the same instructions, and adds byte and word version of doubleword/quadword instructions in AVX-512F. A few instructions which get only word forms with AVX-512BW acquire byte forms with the AVX-512_VBMI extension (VPERMB,VPERMI2B,VPERMT2B,VPMULTISHIFTQB). Two new instructions were added to the mask instructions set:KADDandKTEST(B and W forms with AVX-512DQ, D and Q with AVX-512BW). The rest of mask instructions, which had only word forms, got byte forms with AVX-512DQ and doubleword/quadword forms with AVX-512BW.KUNPCKBWwas extended toKUNPCKWDandKUNPCKDQby AVX-512BW. Among the instructions added by AVX-512DQ are several SSE and AVX instructions that didn't get AVX-512 versions with AVX-512F, among those are all the two input bitwise instructions and extract/insert integer instructions. Instructions that are completely new are covered below. Three new floating-point operations are introduced. Since they are not only new to AVX-512 they have both packed/SIMD and scalar versions. TheVFPCLASSinstructions tests if the floating-point value is one of eight special floating-point values, which of the eight values will trigger a bit in the output mask register is controlled by the immediate field. TheVRANGEinstructions perform minimum or maximum operations depending on the value of the immediate field, which can also control if the operation is done absolute or not and separately how the sign is handled. TheVREDUCEinstructions operate on a single source, and subtract from that the integer part of the source value plus a number of bits specified in the immediate field of its fraction. Extend VPCOMPRESS and VPEXPAND with byte and word variants. Shift instructions are new. Vector Neural Network Instructions:[11]AVX512-VNNI addsEVEX-coded instructions described below. With AVX-512F, these instructions can operate on 512-bit vectors, and AVX-512VL further adds support for 128- and 256-bit vectors. A laterAVX-VNNIextension addsVEXencodings of these instructions which can only operate on 128- or 256-bit vectors. AVX-VNNI is not part of the AVX-512 suite, it does not require AVX-512F and can be implemented independently. Integer fused multiply-add instructions. AVX512-IFMA addsEVEX-coded instructions described below. A separateAVX-IFMAinstruction set extension definesVEXencoding of these instructions. This extension is not part of the AVX-512 suite and can be implemented independently. Galois fieldnew instructions are useful for cryptography,[12]as they can be used to implementRijndael-style S-boxessuch as those used in AES,Camellia, andSM4.[13]These instructions may also be used for bit manipulation in networking and signal processing.[12] GFNI is a standalone instruction set extension and can be enabled separately from AVX or AVX-512. Depending on whether AVX and AVX-512F support is indicated by the CPU, GFNI support enables legacy (SSE), VEX or EVEX-coded instructions operating on 128, 256 or 512-bit vectors. VPCLMULQDQ with AVX-512F adds an EVEX-encoded 512-bit version of thePCLMULQDQinstruction. With AVX-512VL, it adds EVEX-encoded 256- and 128-bit versions. VPCLMULQDQ alone (that is, on non-AVX512 CPUs) adds only VEX-encoded 256-bit version. (Availability of the VEX-encoded 128-bit version is indicated by different CPUID bits: PCLMULQDQ and AVX.) The wider than 128-bit variations of the instruction perform the same operation on each 128-bit portion of input registers, but they do not extend it to select quadwords from different 128-bit fields (the meaning of imm8 operand is the same: either low or high quadword of the 128-bit field is selected). VEX- and EVEX-encodedAESinstructions. The wider than 128-bit variations of the instruction perform the same operation on each 128-bit portion of input registers. The VEX versions can be used without AVX-512 support. AI acceleration instructions operating on theBfloat16numbers. An extension of the earlierF16Cinstruction set, adding comprehensive support for thebinary16floating-point numbers (also known as FP16, float16 or half-precision floating-point numbers). The new instructions implement most operations that were previously available forsingleanddouble-precision floating-point numbers and also introduce newcomplex numberinstructions and conversion instructions. Scalar and packed operations are supported. Unlike the single and double-precision format instructions, the half-precision operands are neither conditionally flushed to zero (FTZ) nor conditionally treated as zero (DAZ) based onMXCSRsettings.Subnormalvalues are processed at full speed by hardware to facilitate using the full dynamic range of the FP16 numbers. Instructions that create FP32 and FP64 numbers still respect theMXCSR.FTZbit.[14] ^Note 1: Intel does not officially support AVX-512 family of instructions on theAlder Lakemicroprocessors. In early 2022, Intel began disabling in silicon (fusing off) AVX-512 in Alder Lake microprocessors to prevent customers from enabling AVX-512.[35]In older Alder Lake family CPUs with some legacy combinations of BIOS and microcode revisions, it was possible to execute AVX-512 family instructions when disabling all the efficiency cores which do not contain the silicon for AVX-512.[36][37][24] Intel Vectorization Advisor(starting from version 2017) supports native AVX-512 performance and vector code quality analysis (for "Core", Xeon andIntel Xeon Phiprocessors). Along with traditional hotspots profile, Advisor Recommendations and "seamless" integration of Intel Compiler vectorization diagnostics, Advisor Survey analysis also provides AVX-512 ISA metrics and new AVX-512-specific "traits", e.g. Scatter, Compress/Expand, mask utilization.[38][39] On some processors (mostly pre-Ice LakeIntel), AVX-512 instructions can cause a frequency throttling even greater than its predecessors, causing a penalty for mixed workloads. The additional downclocking is triggered by the 512-bit width of vectors and depends on the nature of instructions being executed; using the 128 or 256-bit part of AVX-512 (AVX-512VL) does not trigger it. As a result,gccandclangdefault to prefer using the 256-bit vectors for Intel targets.[40][41][42] C/C++compilers also automatically handleloop unrollingand preventingstalls in the pipelinein order to use AVX-512 most effectively, which means a programmer using languageintrinsicsto try to force use of AVX-512 can sometimes result in worse performance relative to the code generated by the compiler when it encounters loops plainly written in the source code.[43]In other cases, using AVX-512 intrinsics in C/C++ code can result in a performance improvement relative to plainly written C/C++.[44] There are many examples ofAVX-512 applications, including media processing, cryptography,video games,[45]neural networks,[46]and evenOpenJDK, which employs AVX-512 forsorting.[47] In a much-cited quote from 2020,Linus Torvaldssaid "I hope AVX-512 dies a painful death, and that Intel starts fixing real problems instead of trying to create magic instructions to then create benchmarks that they can look good on,"[48]stating that he would prefer thetransistor budgetbe spent on additionalcoresand integer performance instead, and that he "detests" floating pointbenchmarks.[49] Numentatouts their "highlysparse"[50]neural network technology, which they say obviates the need forGPUsas their algorithms run on CPUs with AVX-512.[51]They claim a ten timesspeeduprelative toA100largely because their algorithms reduce the size of the neural network, while maintainingaccuracy, by techniques such as the Sparse Evolutionary Training (SET) algorithm[52]and Foresight Pruning.[53]	https://en.wikipedia.org/wiki/AVX-512
Bit manipulation instructions sets(BMI sets) are extensions to thex86instruction set architectureformicroprocessorsfromIntelandAMD. The purpose of these instruction sets is to improve the speed ofbit manipulation. All the instructions in these sets are non-SIMDand operate only on general-purposeregisters. There are two sets published by Intel: BMI (now referred to as BMI1) and BMI2; they were both introduced with theHaswellmicroarchitecture with BMI1 matching features offered by AMD's ABM instruction set and BMI2 extending them. Another two sets were published by AMD: ABM (Advanced Bit Manipulation, which is also a subset ofSSE4aimplemented by Intel as part ofSSE4.2and BMI1), and TBM (Trailing Bit Manipulation, an extension introduced withPiledriver-based processors as an extension to BMI1, but dropped again inZen-based processors).[1] AMD was the first to introduce the instructions that now form Intel's BMI1 as part of its ABM (Advanced Bit Manipulation) instruction set, then later added support for Intel's new BMI2 instructions. AMD today advertises the availability of these features via Intel's BMI1 and BMI2 cpuflags and instructs programmers to target them accordingly.[2] While Intel considersPOPCNTas part of SSE4.2 andLZCNTas part of BMI1, both Intel and AMD advertise the presence of these two instructions individually.POPCNThas a separateCPUIDflag of the same name, and Intel and AMD use AMD'sABMflag to indicateLZCNTsupport (sinceLZCNTcombined with BMI1 and BMI2 completes the expanded ABM instruction set).[2][3] LZCNTis related to the Bit Scan Reverse (BSR) instruction, but sets the ZF (if the result is zero) and CF (if the source is zero) flags rather than setting the ZF (if the source is zero). Also, it produces a defined result (the source operand size in bits) if the source operand is zero. For a non-zero argument, sum ofLZCNTandBSRresults is argument bit width minus 1 (for example, if 32-bit argument is0x000f0000, LZCNT gives 12, and BSR gives 19). The encoding ofLZCNTis such that if ABM is not supported, then theBSRinstruction is executed instead.[4]: 227 The instructions below are those enabled by theBMIbit in CPUID. Intel officially considersLZCNTas part of BMI, but advertisesLZCNTsupport using theABMCPUID feature flag.[3]BMI1 is available in AMD'sJaguar,[5]Piledriver[6]and newer processors, and in Intel'sHaswell[7]and newer processors. TZCNTis almost identical to the Bit Scan Forward (BSF) instruction, but sets the ZF (if the result is zero) and CF (if the source is zero) flags rather than setting the ZF (if the source is zero). For a non-zero argument, the result ofTZCNTandBSFis equal. As withLZCNT, the encoding ofTZCNTis such that if BMI1 is not supported, then theBSFinstruction is executed instead.[4]: 352 Intel introduced BMI2 together with BMI1 in its line of Haswell processors. Only AMD has produced processors supporting BMI1 without BMI2; BMI2 is supported by AMDsExcavatorarchitecture and newer.[11] ThePDEPandPEXTinstructions are new generalized bit-level compress and expand instructions. They take two inputs; one is a source, and the other is a selector. The selector is a bitmap selecting the bits that are to be packed or unpacked.PEXTcopies selected bits from the source to contiguous low-order bits of the destination; higher-order destination bits are cleared.PDEPdoes the opposite for the selected bits: contiguous low-order bits are copied to selected bits of the destination; other destination bits are cleared. This can be used to extract any bitfield of the input, and even do a lot of bit-level shuffling that previously would have been expensive. While what these instructions do is similar to bit levelgather-scatterSIMD instructions,PDEPandPEXTinstructions (like the rest of the BMI instruction sets) operate on general-purpose registers.[12] The instructions are available in 32-bit and 64-bit versions. An example using arbitrary source and selector in 32-bit mode is: AMD processors before Zen 3[13]that implement PDEP and PEXT do so in microcode, with a latency of 18 cycles[14]rather than (Zen 3) 3 cycles.[15]As a result it is often faster to use other instructions on these processors.[16] TBM consists of instructions complementary to the instruction set started by BMI1; their complementary nature means they do not necessarily need to be used directly but can be generated by an optimizing compiler when supported. AMD introduced TBM together with BMI1 in itsPiledriver[6]line of processors; later AMD Jaguar and Zen-based processors do not support TBM.[5]No Intel processors (at least throughAlder Lake) support TBM. Note that instruction extension support means the processor is capable of executing the supported instructions for software compatibility purposes. The processor might not perform well doing so. For example, Excavator through Zen 2 processors implement PEXT and PDEP instructions using microcode resulting in the instructions executing significantly slower than the same behaviour recreated using other instructions.[20](A software method called "zp7" is, in fact, faster on these machines.)[21]For optimum performance it is recommended that compiler developers choose to use individual instructions in the extensions based on architecture specific performance profiles rather than on extension availability.	https://en.wikipedia.org/wiki/X86_Bit_manipulation_instruction_set
In thex86architecture, theCPUIDinstruction (identified by aCPUIDopcode) is aprocessor supplementary instruction(its name derived from "CPUIdentification") allowing software to discover details of the processor. It was introduced byIntelin 1993 with the launch of thePentiumandSL-enhanced 486processors.[1] A program can use theCPUIDto determine processor type and whether features such asMMX/SSEare implemented. Prior to the general availability of theCPUIDinstruction, programmers would write esotericmachine codewhich exploited minor differences in CPU behavior in order to determine the processor make and model.[2][3][4][5]With the introduction of the 80386 processor, EDX on reset indicated the revision but this was only readable after reset and there was no standard way for applications to read the value. Outside the x86 family, developers are mostly still required to use esoteric processes (involving instruction timing or CPU fault triggers) to determine the variations in CPU design that are present. For example, in theMotorola 68000 series— which never had aCPUIDinstruction of any kind — certain specific instructions required elevated privileges. These could be used to tell various CPU family members apart. In theMotorola 68010the instructionMOVE from SRbecame privileged. Because the68000offered an unprivilegedMOVE from SRthe two different CPUs could be told apart by a CPU error condition being triggered. While theCPUIDinstruction is specific to the x86 architecture, other architectures (like ARM) often provide on-chip registers which can be read in prescribed ways to obtain the same sorts of information provided by the x86CPUIDinstruction. TheCPUIDopcode is0F A2. Inassembly language, theCPUIDinstruction takes no parameters asCPUIDimplicitly uses the EAX register to determine the main category of information returned. In Intel's more recent terminology, this is called the CPUID leaf.CPUIDshould be called withEAX = 0first, as this will store in the EAX register the highest EAX calling parameter (leaf) that the CPU implements. To obtain extended function informationCPUIDshould be called with the most significant bit of EAX set. To determine the highest extended function calling parameter, callCPUIDwithEAX = 80000000h. CPUID leaves greater than 3 but less than 80000000 are accessible only when themodel-specific registershave IA32_MISC_ENABLE.BOOT_NT4 [bit 22] = 0 (which is so by default). As the name suggests,Windows NT 4.0until SP6 did not boot properly unless this bit was set,[6]but later versions of Windows do not need it, so basic leaves greater than 4 can be assumed visible on current Windows systems. As of April 2024[update], basic valid leaves go up to 23h, but the information returned by some leaves are not disclosed in the publicly available documentation, i.e. they are "reserved". Some of the more recently added leaves also have sub-leaves, which are selected via the ECX register before callingCPUID. This returns the CPU's manufacturer ID string – a twelve-characterASCIIstring stored in EBX, EDX, ECX (in that order). The highest basic calling parameter (the largest value that EAX can be set to before callingCPUID) is returned in EAX. Here is a list of processors and the highest function implemented. The following are known processor manufacturer ID strings: The following are ID strings used by open sourcesoft CPU cores: The following are known ID strings from virtual machines: For instance, on aGenuineIntelprocessor, values returned in EBX is0x756e6547, EDX is0x49656e69and ECX is0x6c65746e. The following example code displays the vendor ID string as well as the highest calling parameter that the CPU implements. On some processors, it is possible to modify the Manufacturer ID string reported by CPUID.(EAX=0) by writing a new ID string to particular MSRs (Model-specific registers) using theWRMSRinstruction. This has been used on non-Intel processors to enable features and optimizations that have been disabled in software for CPUs that don't return theGenuineIntelID string.[22]Processors that are known to possess such MSRs include: This returns the CPU'sstepping, model, and family information in register EAX (also called thesignatureof a CPU), feature flags in registers EDX and ECX, and additional feature info in register EBX.[30] As of October 2023, the following x86 processor family IDs are known:[32] CPUID.01.EDX.CLFSH [bit 19]= 1 The nearest power-of-2 integer that is not smaller than this value is the number of unique initial APIC IDs reserved for addressing different logical processors in a physical package.[a] Former use: Number of logical processors per physical processor; two for the Pentium 4 processor with Hyper-Threading Technology.[47] CPUID.01.EDX.HTT [bit 28]= 1 The processor info and feature flags are manufacturer specific but usually, the Intel values are used by other manufacturers for the sake of compatibility. Processors noted to exhibit this behavior include Cyrix MII[48]and IDT WinChip 2.[49] In older documentation, this bit is often listed as a "Hyper-threadingtechnology"[61]flag - however, while this flag is a prerequisite for Hyper-Threading support, it does not by itself indicate support for Hyper-Threading and it has been set on many CPUs that do not feature any form of multi-threading technology.[62] Reserved fields should be masked before using them for processor identification purposes. This returns a list of descriptors indicating cache andTLBcapabilities in EAX, EBX, ECX and EDX registers. On processors that support this leaf, callingCPUIDwith EAX=2 will cause the bottom byte of EAX to be set to01h[a]and the remaining 15 bytes of EAX/EBX/ECX/EDX to be filled with 15 descriptors, one byte each. These descriptors provide information about the processor's caches, TLBs and prefetch. This is typically one cache or TLB per descriptor, but some descriptor-values provide other information as well - in particular,00his used for an empty descriptor,FFhindicates that the leaf does not contain valid cache information and that leaf 4h should be used instead, andFEhindicates that the leaf does not contain valid TLB information and that leaf 18h should be used instead. The descriptors may appear in any order. For each of the four registers (EAX,EBX,ECX,EDX), if bit 31 is set, then the register should not be considered to contain valid descriptors (e.g. on Itanium in IA-32 mode, CPUID(EAX=2) returns80000000hin EDX - this should be interpreted to mean that EDX contains no valid information, not that it contains a descriptor for a 512K L2 cache.) The table below provides, for known descriptor values, a condensed description of the cache or TLB indicated by that descriptor value (or other information, where that applies). The suffixes used in the table are: This returns the processor's serial number. The processor serial number was introduced on IntelPentium III, but due to privacy concerns, this feature is no longer implemented on later models (the PSN feature bit is always cleared).Transmeta'sEfficeon and Crusoe processors also provide this feature. AMD CPUs however, do not implement this feature in any CPU models. For Intel Pentium III CPUs, the serial number is returned in the EDX:ECX registers. For Transmeta Efficeon CPUs, it is returned in the EBX:EAX registers. And for Transmeta Crusoe CPUs, it is returned in the EBX register only. Note that the processor serial number feature must be enabled in theBIOSsetting in order to function. These two leaves are used to provide information about thecache hierarchylevels available to the processor core on which theCPUIDinstruction is run. Leaf4is used on Intel processors and leaf8000'001Dhis used on AMD processors - they both return data in EAX, EBX, ECX and EDX, using the same data format except that leaf4returns a few additional fields that are considered "reserved" for leaf8000'001Dh. They both provide CPU cache information in a series of sub-leaves selected by ECX - to get information about all the cache levels, it is necessary to invokeCPUIDrepeatedly, with EAX=4or8000'001Dhand ECX set to increasing values starting from 0 (0,1,2,...) until a sub-leaf not describing any caches (EAX[4:0]=0) is found. The sub-leaves that do return cache information may appear in any order, but all of them will appear before the first sub-leaf not describing any caches. In the below table, fields that are defined for leaf4but not for leaf8000'001Dhare highlighted with yellow cell coloring and a(#4)item. For any caches that are valid and not fully-associative, the value returned in ECX is the number of sets in the cache minus 1. (For fully-associative caches, ECX should be treated as if it return the value 0.) For any given cache described by a sub-leaf ofCPUIDleaf4or8000'001Dh, the total cache size in bytes can be computed as: CacheSize = (EBX[11:0]+1) * (EBX[21:12]+1) * (EBX[31:22]+1) * (ECX+1) For example, on IntelCrystalwellCPUs, executing CPUID with EAX=4 and ECX=4 will cause the processor to return the following size information for its level-4 cache in EBX and ECX:EBX=03C0F03FandECX=00001FFF- this should be taken to mean that this cache has a cache line size of 64 bytes (EBX[11:0]+1), has 16 cache lines per tag (EBX[21:12]+1), is 16-way set-associative (EBX[31:22]+1) with 8192 sets (ECX+1), for a total size of 6416168192=134217728 bytes, or 128 binary megabytes. These two leaves are used for processor topology (thread, core, package) and cache hierarchy enumeration in Intel multi-core (and hyperthreaded) processors.[89]As of 2013[update]AMD does not use these leaves but has alternate ways of doing the core enumeration.[90] Unlike most other CPUID leaves, leaf Bh will return different values in EDX depending on which logical processor the CPUID instruction runs; the value returned in EDX is actually thex2APICid of the logical processor. The x2APIC id space is not continuously mapped to logical processors, however; there can be gaps in the mapping, meaning that some intermediate x2APIC ids don't necessarily correspond to any logical processor. Additional information for mapping the x2APIC ids to cores is provided in the other registers. Although the leaf Bh has sub-leaves (selected by ECX as described further below), the value returned in EDX is only affected by the logical processor on which the instruction is running but not by the subleaf. The processor(s) topology exposed by leaf Bh is a hierarchical one, but with the strange caveat that the order of (logical) levels in this hierarchy doesn't necessarily correspond to the order in the physical hierarchy (SMT/core/package). However, every logical level can be queried as an ECX subleaf (of the Bh leaf) for its correspondence to a "level type", which can be either SMT, core, or "invalid". The level id space starts at 0 and is continuous, meaning that if a level id is invalid, all higher level ids will also be invalid. The level type is returned in bits 15:08 of ECX, while the number of logical processors at the level queried is returned in EBX. Finally, the connection between these levels and x2APIC ids is returned in EAX[4:0] as the number of bits that the x2APIC id must be shifted in order to obtain a unique id at the next level. As an example, a dual-coreWestmereprocessor capable ofhyperthreading(thus having two cores and four threads in total) could have x2APIC ids 0, 1, 4 and 5 for its four logical processors. Leaf Bh (=EAX), subleaf 0 (=ECX) of CPUID could for instance return 100h in ECX, meaning that level 0 describes the SMT (hyperthreading) layer, and return 2 in EBX because there are two logical processors (SMT units) per physical core. The value returned in EAX for this 0-subleaf should be 1 in this case, because shifting the aforementioned x2APIC ids to the right by one bit gives a unique core number (at the next level of the level id hierarchy) and erases the SMT id bit inside each core. A simpler way to interpret this information is that the last bit (bit number 0) of the x2APIC id identifies the SMT/hyperthreading unit inside each core in our example. Advancing to subleaf 1 (by making another call to CPUID with EAX=Bh and ECX=1) could for instance return 201h in ECX, meaning that this is a core-type level, and 4 in EBX because there are 4 logical processors in the package; EAX returned could be any value greater than 3, because it so happens that bit number 2 is used to identify the core in the x2APIC id. Note that bit number 1 of the x2APIC id is not used in this example. However, EAX returned at this level could well be 4 (and it happens to be so on a Clarkdale Core i3 5x0) because that also gives a unique id at the package level (=0 obviously) when shifting the x2APIC id by 4 bits. Finally, you may wonder what the EAX=4 leaf can tell us that we didn't find out already. In EAX[31:26] it returns the APIC mask bitsreservedfor a package; that would be 111b in our example because bits 0 to 2 are used for identifying logical processors inside this package, but bit 1 is also reserved although not used as part of the logical processor identification scheme. In other words, APIC ids 0 to 7 are reserved for the package, even though half of these values don't map to a logical processor. The cache hierarchy of the processor is explored by looking at the sub-leaves of leaf 4. The APIC ids are also used in this hierarchy to convey information about how the different levels of cache are shared by the SMT units and cores. To continue our example, the L2 cache, which is shared by SMT units of the same core but not between physical cores on the Westmere is indicated by EAX[26:14] being set to 1, while the information that the L3 cache is shared by the whole package is indicated by setting those bits to (at least) 111b. The cache details, including cache type, size, and associativity are communicated via the other registers on leaf 4. Beware that older versions of the Intel app note 485 contain some misleading information, particularly with respect to identifying and counting cores in a multi-core processor;[91]errors from misinterpreting this information have even been incorporated in the Microsoft sample code for using CPUID, even for the 2013 edition of Visual Studio,[92]and also in the sandpile.org page for CPUID,[93]but the Intel code sample for identifying processor topology[89]has the correct interpretation, and the current Intel Software Developer's Manual has a more clear language. The (open source) cross-platform production code[94]fromWildfire Gamesalso implements the correct interpretation of the Intel documentation. Topology detection examples involving older (pre-2010) Intel processors that lack x2APIC (thus don't implement the EAX=Bh leaf) are given in a 2010 Intel presentation.[95]Beware that using that older detection method on 2010 and newer Intel processors may overestimate the number of cores and logical processors because the old detection method assumes there are no gaps in the APIC id space, and this assumption is violated by some newer processors (starting with the Core i3 5x0 series), but these newer processors also come with an x2APIC, so their topology can be correctly determined using the EAX=Bh leaf method. This returns feature information related to theMONITORandMWAITinstructions in the EAX, EBX, ECX and EDX registers. This returns feature bits in the EAX register and additional information in the EBX, ECX and EDX registers. This returns extended feature flags in EBX, ECX, and EDX. Returns the maximum ECX value for EAX=7 in EAX. This returns extended feature flags in all four registers. This returns extended feature flags in EDX. EAX, EBX and ECX are reserved. IPRED_DIS prevents instructions at an indirect branch target from speculatively executing until the branch target address is resolved. BHI_DIS_S prevents predicted targets of indirect branches executed in ring0/1/2 from being selected based on branch history from branches executed in ring 3. This leaf is used to enumerate XSAVE features and state components. The XSAVE instruction set extension is designed to save/restore CPU extended state (typically for the purpose ofcontext switching) in a manner that can be extended to cover new instruction set extensions without the OS context-switching code needing to understand the specifics of the new extensions. This is done by defining a series ofstate-components, each with a size and offset within a given save area, and each corresponding to a subset of the state needed for one CPU extension or another. TheEAX=0DhCPUID leaf is used to provide information about which state-components the CPU supports and what their sizes/offsets are, so that the OS can reserve the proper amount of space and set the associated enable-bits. The state-components can be subdivided into two groups: user-state (state-items that are visible to the application, e.g.AVX-512vector registers), and supervisor-state (state items that affect the application but are not directly user-visible, e.g. user-mode interrupt configuration). The user-state items are enabled by setting their associated bits in theXCR0control register, while the supervisor-state items are enabled by setting their associated bits in theIA32_XSS(0DA0h) MSR - the indicated state items then become the state-components that can be saved and restored with theXSAVE/XRSTORfamily of instructions. The XSAVE mechanism can handle up to 63 state-components in this manner. State-components 0 and 1 (x87andSSE, respectively) have fixed offsets and sizes - for state-components 2 to 62, their sizes, offsets and a few additional flags can be queried by executingCPUIDwithEAX=0DhandECXset to the index of the state-component. This will return the following items in EAX, EBX and ECX (with EDX being reserved): (This offset is 0 for supervisor state-components, since these can only be saved with theXSAVES/XRSTORSinstruction, which use compacting.) If this bit is set for a state-component, then, when storing state with compaction, padding will be inserted between the preceding state-component and this state-component as needed to provide 64-byte alignment. If this bit is not set, the state-component will be stored directly after the preceding one. Attempting to query an unsupported state-component in this manner results in EAX,EBX,ECX and EDX all being set to 0. Sub-leaves 0 and 1 ofCPUIDleaf0Dhare used to provide feature information: As of July 2023, the XSAVE state-components that have been architecturally defined are: This leaf provides information about the supported capabilities of the IntelSoftware Guard Extensions(SGX) feature. The leaf provides multiple sub-leaves, selected with ECX. Sub-leaf 0 provides information about supported SGX leaf functions in EAX and maximum supported SGX enclave sizes in EDX; ECX is reserved. EBX provides a bitmap of bits that can be set in the MISCSELECT field in the SECS (SGX Enclave Control Structure) - this field is used to control information written to the MISC region of the SSA (SGX Save State Area) when an AEX (SGX Asynchronous Enclave Exit) occurs. Sub-leaf 1 provides a bitmap of which bits can be set in the 128-bit ATTRIBUTES field of SECS in EDX:ECX:EBX:EAX (this applies to the SECS copy used as input to theENCLS[ECREATE]leaf function). The top 64 bits (given in EDX:ECX) are a bitmap of which bits can be set in the XFRM (X-feature request mask) - this mask is a bitmask of which CPU state-components (see leaf 0Dh) will be saved to the SSA in case of an AEX; this has the same layout as theXCR0control register. The other bits are given in EAX and EBX, as follows: Sub-leaves 2 and up are used to provide information about which physical memory regions are available for use as EPC (Enclave Page Cache) sections under SGX. This sub-leaf provides feature information for IntelProcessor Trace(also known as Real Time Instruction Trace). The value returned in EAX is the index of the highest sub-leaf supported for CPUID with EAX=14h. EBX and ECX provide feature flags, EDX is reserved. These two leaves provide information about various frequencies in the CPU in EAX, EBX and ECX (EDX is reserved in both leaves). If the returned values in EBX and ECX of leaf 15h are both nonzero, then the TSC (Time Stamp Counter) frequency in Hz is given byTSCFreq = ECX(EBX/EAX). On some processors (e.g. IntelSkylake), CPUID_15h_ECX is zero but CPUID_16h_EAX is present and not zero. On all known processors where this is the case,[121]the TSC frequency is equal to the Processor Base Frequency, and the Core Crystal Clock Frequency in Hz can be computed asCoreCrystalFreq = (CPUID_16h_EAX * 10000000) * (CPUID_15h_EAX/CPUID_15h_EBX). On processors that enumerate the TSC/Core Crystal Clock ratio in CPUID leaf 15h, theAPICtimer frequency will be the Core Crystal Clock frequency divided by the divisor specified by the APIC's Divide Configuration Register.[122] This leaf is present in systems where an x86 CPUIP coreis implemented in an SoC (System on chip) from another vendor - whereas the other leaves ofCPUIDprovide information about the x86 CPU core, this leaf provides information about the SoC. This leaf takes a sub-leaf index in ECX. Sub-leaf 0 returns a maximum sub-leaf index in EAX (at least 3), and SoC identification information in EBX/ECX/EDX: Sub-leaves 1 to 3 return a 48-byte SoC vendor brand string inUTF-8format. Sub-leaf 1 returns the first 16 bytes in EAX,EBX,ECX,EDX (in that order); sub-leaf 2 returns the next 16 bytes and sub-leaf 3 returns the last 16 bytes. The string is allowed but not required to benull-terminated. This leaf provides feature information for Intel Key Locker in EAX, EBX and ECX. EDX is reserved. WhenECX=0, the highest supported "palette" subleaf is enumerated in EAX. WhenECX≥1, information on palettenis returned. This leaf returns information on theTMUL(tile multiplier) unit. This leaf returns feature flags on theTMUL(tile multiplier) unit. When Intel TDX (Trust Domain Extensions) is active, attempts to execute theCPUIDinstruction by a TD (Trust Domain) guest will be intercepted by the TDX module. This module will, whenCPUIDis invoked withEAX=21handECX=0(leaf21h, sub-leaf 0), return the index of the highest supported sub-leaf for leaf21hinEAXand a TDX module vendor ID string as a 12-byte ASCII string in EBX,EDX,ECX (in that order). Intel's own module implementation returns the vendor ID string"IntelTDX"(with four trailing spaces)[124]- for this module, additional feature information is not available throughCPUIDand must instead be obtained through the TDX-specificTDCALLinstruction. This leaf is reserved in hardware and will (on processors whose highest basic leaf is21hor higher) return 0 in EAX/EBX/ECX/EDX when run directly on the CPU. This returns a maximum supported sub-leaf in EAX and AVX10 feature information in EBX.[113](ECX and EDX are reserved.) Subleaf 1 is reserved for AVX10 features not bound to a version. The highest function is returned in EAX. This leaf is only present onXeon Phiprocessors.[127] This function returns feature flags. When theCPUIDinstruction is executed underIntel VT-x or AMD-v virtualization, it will be intercepted by the hypervisor, enabling the hypervisor to returnCPUIDfeature flags that differ from those of the underlying hardware.CPUIDleaves40000000hto4FFFFFFFhare not implemented in hardware, and are reserved for use by hypervisors to provide hypervisor-specific identification and feature information through this interception mechanism. For leaf40000000h, the hypervisor is expected to return the index of the highest supported hypervisor CPUID leaf in EAX, and a 12-character hypervisor ID string in EBX,ECX,EDX (in that order). For leaf40000001h, the hypervisor may return an interface identification signature in EAX - e.g. hypervisors that wish to advertise that they areHyper-Vcompatible may return0x31237648—"Hv#1"in EAX.[128][129]The formats of leaves40000001hand up to the highest supported leaf are otherwise hypervisor-specific. Hypervisors that implement these leaves will normally also set bit 31 of ECX for CPUID leaf 1 to indicate their presence. Hypervisors that expose more than one hypervisor interface may provide additional sets of CPUID leaves for the additional interfaces, at a spacing of100hleaves per interface. For example, whenQEMUis configured to provide bothHyper-VandKVMinterfaces, it will provide Hyper-V information starting from CPUID leaf40000000hand KVM information starting from leaf40000100h.[130][131] Some hypervisors that are known to return a hypervisor ID string in leaf40000000hinclude: Lower-case string also used in bhyve-derived hypervisors such as xhyve and HyperKit.[136] (KGT also returns a signature inCPUIDleaf 3: ECX=0x4D4D5645 "EVMM"and EDX=0x43544E49 "INTC") The highest calling parameter is returned in EAX. EBX/ECX/EDX return the manufacturer ID string (same as EAX=0) on AMD but not Intel CPUs. This returns extended feature flags in EDX and ECX. Many of the bits inEDX(bits 0 through 9, 12 through 17, 23, and 24) are duplicates ofEDXfrom theEAX=1leaf - these bits are highlighted in light yellow. (These duplicated bits are present on AMD but not Intel CPUs.) AMD feature flagsare as follows:[150][151] These instructions were first introduced on Model 7[152]- the CPUID bit to indicate their support was moved[153]to EDX bit 11 from Model 8 (AMD K6-2) onwards. These return the processor brand string in EAX, EBX, ECX and EDX.CPUIDmust be issued with each parameter in sequence to get the entire 48-byte ASCII processor brand string.[162]It is necessary to check whether the feature is present in the CPU by issuingCPUIDwithEAX = 80000000hfirst and checking if the returned value is not less than80000004h. The string is specified in Intel/AMD documentation to benull-terminated, however this is not always the case (e.g. DM&PVortex86DX3and AMDRyzen 7 6800HSare known to return non-null-terminated brand strings in leaves80000002h-80000004h[163][164]), and software should not rely on it. On AMD processors, from180nm Athlononwards (AuthenticAMDFamily 6 Model 2 and later), it is possible to modify the processor brand string returned by CPUID leaves80000002h-80000004hby using theWRMSRinstruction to write a 48-byte replacement string to MSRsC0010030h-C0010035h.[159][165]This can also be done on AMD Geode GX/LX, albeit using MSRs300Ah-300Fh.[166] In some cases, determining the CPU vendor requires examining not just the Vendor ID in CPUID leaf 0 and the CPU signature in leaf 1, but also the Processor Brand String in leaves80000002h-80000004h. Known cases include: This provides information about the processor's level-1 cache andTLBcharacteristics in EAX, EBX, ECX and EDX as follows:[a] Returns details of the L2 cache in ECX, including the line size in bytes (Bits 07 - 00), type of associativity (encoded by a 4 bits field; Bits 15 - 12) and the cache size in KB (Bits 31 - 16). This function provides information about power management, power reporting and RAS (Reliability, availability and serviceability) capabilities of the CPU. PPIN_CTL(C001_02F0) andPPIN(C001_02F1) MSRs are present[174] This leaf returns information about AMD SVM (Secure Virtual Machine) features in EAX, EBX and EDX. Later AMD documentation, such as #25481 "CPUID specification" rev 2.18[179]and later, only lists the bit as reserved. In rev 2.30[180]and later, a different bit is listed as reserved for hypervisor use:CPUID.(EAX=1):ECX[bit 31]. Rev 2.28 of #25481 lists the bit as "Ssse3Sse5Dis"[182]- in rev 2.34, it is listed as having been removed from the spec at rev 2.32 under the name "SseIsa10Compat".[183] Several AMD CPU models will, for CPUID withEAX=8FFFFFFFh, return an Easter Egg string in EAX, EBX, ECX and EDX.[190][191]Known Easter Egg strings include: Returns index of highest Centaur leaf in EAX. If the returned value in EAX is less thanC0000001h, then Centaur extended leaves are not supported. Present in CPUs fromVIAandZhaoxin. On IDTWinChipCPUs (CentaurHaulsFamily 5), the extended leavesC0000001h-C0000005hdo not encode any Centaur-specific functionality but are instead aliases of leaves80000001h-80000005h.[193] This leaf returns Centaur feature information (mainlyVIA/Zhaoxin PadLock) in EDX.[194][195][196][197](EAX, EBX and ECX are reserved.) This information is easy to access from other languages as well. For instance, the C code for gcc below prints the first five values, returned by the cpuid: In MSVC and Borland/Embarcadero C compilers (bcc32) flavored inline assembly, the clobbering information is implicit in the instructions: If either version was written in plain assembly language, the programmer must manually save the results of EAX, EBX, ECX, and EDX elsewhere if they want to keep using the values. GCC also provides a header called<cpuid.h>on systems that have CPUID. The__cpuidis a macro expanding to inline assembly. Typical usage would be: But if one requested an extended feature not present on this CPU, they would not notice and might get random, unexpected results. Safer version is also provided in<cpuid.h>. It checks for extended features and does some more safety checks. The output values are not passed using reference-like macro parameters, but more conventional pointers. Notice the ampersands in&a, &b, &c, &dand the conditional statement. If the__get_cpuidcall receives a correct request, it will return a non-zero value, if it fails, zero.[199] Microsoft Visual C compiler has builtin function__cpuid()so the cpuid instruction may be embedded without using inline assembly, which is handy since the x86-64 version of MSVC does not allow inline assembly at all. The same program forMSVCwould be: Many interpreted or compiled scripting languages are capable of using CPUID via anFFIlibrary.One such implementationshows usage of the Ruby FFI module to execute assembly language that includes the CPUID opcode. .NET5 and later versions provide theSystem.Runtime.Intrinsics.X86.X86base.CpuIdmethod. For instance, the C# code below prints the processor brand if it supports CPUID instruction: Some of the non-x86 CPU architectures also provide certain forms of structured information about the processor's abilities, commonly as a set of special registers: DSPandtransputer-like chip families have not taken up the instruction in any noticeable way, in spite of having (in relative terms) as many variations in design. Alternate ways of silicon identification might be present; for example, DSPs fromTexas Instrumentscontain a memory-based register set for each functional unit that starts with identifiers determining the unit type and model, itsASICdesign revision and features selected at the design phase, and continues with unit-specific control and data registers. Access to these areas is performed by simply using the existing load and store instructions; thus, for such devices, there is no need for extending the register set for device identification purposes.[citation needed]	https://en.wikipedia.org/wiki/CPUID
Instructions that have at some point been present as documented instructions in one or morex86processors, but where the processor series containing the instructions are discontinued or superseded, with no known plans to reintroduce the instructions. The following instructions were introduced in the Intel 80386, but later discontinued: Opcodes briefly reused forCMPXCHGin Intel 486 stepping A only −CMPXCHGwas moved to different opcode from 486 stepping B onwards. Opcodes later reused forVIA PadLock. Present in allCyrixCPUs. These instructions are only present in the x86 operation mode of early Intel Itanium processors with hardware support for x86. This support was added in "Merced" and removed in "Montecito", replaced withsoftware emulation. These instructions were introduced in 6th generation Intel Core"Skylake"CPUs. The last CPU generation to support them was the 9th generation Core "Coffee Lake" CPUs. Intel MPX adds 4 new registers, BND0 to BND3, that each contains a pair of addresses. MPX also defines a bounds-table as a 2-level directory/table data structure in memory that contains sets of upper/lower bounds. The lower bound is given by base component of address, the upper bound by 1-s complement of the address as a whole. BNDCL,BNDCUandBNDCLall produce a #BR exception if the bounds check fails. The Hardware Lock Elision feature ofIntel TSXis marked in the Intel SDM as removed from 2019 onwards.[2]This feature took the form of two instruction prefixes,XACQUIREandXRELEASE, that could be attached to memory atomics/stores to elide the memory locking that they represent. The VP2INTERSECT instructions (an AVX-512 subset) were introduced inTiger Lake(11th generation mobile Core processors), but were never officially supported on any other Intel processors - they are now considered deprecated[3]and are listed in the Intel SDM as removed from 2023 onwards.[2] As of July 2024, the VP2INTERSECT instructions have been re-introduced on AMDZen 5processors.[4] The first generationXeon Phiprocessors, codenamed "Knights Corner" (KNC), supported a large number of instructions that are not seen in any later x86 processor. An instruction reference is available[5]− the instructions/opcodes unique to KNC are the ones with VEX and MVEX prefixes (except for theKMOV,KNOTandKORTESTinstructions − these are kept with the same opcodes and function in AVX-512, but with an added "W" appended to their instruction names). Most of these KNC-unique instructions are similar but not identical to instructions inAVX-512− later Xeon Phi processors replaced these instructions with AVX-512. Early versions of AVX-512 avoided the instruction encodings used by KNC's MVEX prefix, however with the introduction of Intel APX (Advanced Performance Extensions) in 2023, some of the old KNC MVEX instruction encodings have been reused for new APX encodings. For example, both KNC and APX accept the instruction encoding62 F1 79 48 6F 04 C1as valid, but assign different meanings to it: Some of the AVX-512 instructions in theXeon Phi"Knights Landing" and later models belong to theAVX-512subsets "AVX512ER", "AVX512_4FMAPS", "AVX512PF" and "AVX512_4VNNIW", all of which are unique to the Xeon Phi series of processors. The ER and PF subsets were introduced in "Knights Landing" − the 4FMAPS and 4VNNIW instructions were later added in "Knights Mill". The ER and 4FMAPS instructions are floating-point arithmetic instructions that all follow a given pattern where: The AVX512PF instructions are a set of 16 prefetch instructions. These instructions all use VSIB encoding, where a memory addressing mode using the SIB byte is required, and where the index part of the SIB byte is taken to index into the AVX512 vector register file rather than the GPR register file. The selected AVX512 vector register is then interpreted as a vector of indexes, causing the standard x86 base+index+displacement address calculation to be performed for each vector lane, causing one associated memory operation (prefetches in case of the AVX512PF instructions) to be performed for each active lane. The instruction encodings all follow a pattern where: The AVX512_4VNNIW instructions read a 128-bit data item from memory, containing 4 two-component vectors (each component being signed 16-bit). Then, for each of 4 consecutive AVX-512 registers, they will, for each 32-bit lane, interpret the lane as a two-component vector (signed 16-bit) and perform a dot-product with the corresponding two-component vector that was read from memory (the first two-component vector from memory is used for the first AVX-512 source register, and so on). These results are then accumulated into a destination vector register. Xeon Phi processors (from Knights Landing onwards) also featured thePREFETCHWT1 m8instruction (opcode0F 0D /2, prefetch into L2 cache with intent to write) − these were the only Intel CPUs to officially support this instruction, but it continues to be supported on some non-Intel processors (e.g.ZhaoxinYongFeng). A handful of instructions to supportSystem Management Modewere introduced in the Am386SXLV and Am386DXLV processors.[7][8]They were also present in the later Am486SXLV/DXLV andElanSC300/310 processors.[9] The SMM functionality of these processors was implemented using IntelICEmicrocodewithout a valid license, resulting in a lawsuit that AMD lost in late 1994.[10]As a result of this loss, the ICE microcode was removed from all later AMD CPUs, and the SMM instructions removed with it. These SMM instructions were also present on theIBM 386SLCand its derivatives (albeit with theLOADALL-like SMM return opcode0F 07namedICERET),[12][14][11]as well as on theUMC U5Sprocessor.[15] The 3DNow! instruction set extension was introduced in the AMDK6-2, mainly adding support for floating-point SIMD instructions using the MMX registers (twoFP32components in a 64-bit vector register). The instructions were mainly promoted by AMD, but were supported on some non-AMD CPUs as well. The processors supporting 3DNow! were: If the bottom 32 bits ofmm0initially contains a value X in FP32 format, then the instruction sequence: must fill both 32-bit lanes ofmm0with1.0X{\displaystyle {\frac {1.0}{X}}}in FP32 format, computed with an error of at most 1ulp. must fill both 32-bit lanes ofmm1with1.0X{\displaystyle {\frac {1.0}{\sqrt {X}}}}in FP32 format, computed with an error of at most 1 ulp. Some assemblers/disassemblers, such as NASM, resolve this ambiguity by using the mnemonicPMULHRWAfor the 3DNow! instruction andPMULHRWCfor the EMMI instruction. 3DNow! also introduced a couple of prefetch instructions:PREFETCH m8(opcode0F 0D /0) andPREFETCHW m8(opcode0F 0D /1). These instructions, unlike the rest of 3DNow!, are not discontinued but continue to be supported on modern AMD CPUs. ThePREFETCHWinstruction is also supported on Intel CPUs starting with65 nmPentium 4,[19]albeit executed as NOP untilBroadwell. The undocumented variant ofPF2IWin K6-2 would set the top 16 bits of each 32-bit result lane to all-0s, while the documented variant in later processors would sign-extend the 16-bit result to 32 bits.[20][21] SSE5 was a proposed SSE extension by AMD, using a new "DREX" instruction encoding to add support for new 3-operand and 4-operand instructions to SSE.[22]The bundle did not include the full set of Intel's SSE4 instructions, making it a competitor to SSE4 rather than a successor. AMD chose not to implement SSE5 as originally proposed − it was instead reworked into FMA4 and XOP,[23]which provided similar functionality but with a quite different instruction encoding − using theVEX prefixfor the FMA4 instructions and the new VEX-like XOP prefix for most of the remaining instructions. Introduced with the Bulldozer processor core, removed again fromZen (microarchitecture)onward. A revision of most of the SSE5 instruction set. The XOP instructions mostly make use of the XOP prefix, which is a 3-byte prefix with the following layout: where: The XOP instructions encoded with the XOP prefix are as follows: VPCMOV dst,src1,src2,src3performs the equivalent ofdst <- (src1 AND src3) OR (src2 AND NOT(src3)) For each vector-register lane, compare src1 to src2, then set destination to all-1s if the comparison passes, all-0s if it fails. The imm8 argument specifies comparison function to perform: For each N-bit lane, split the lane into a series of M-bit lanes, add the M-bit lanes together, then store the result into the destination as an N-bit zero/sign-extended value. For each N-bit lane, split the lane into two signed sub-lanes of N/2 bits each, then subtract the upper lane from the lower lane, then store the result as a signed N-bit result. For each N-bit lane, performdest <- src1*src2 + src3 For src1 and src2, the factors to multiply may be taken as signed values from the low half of each lane, high half of each lane or the lane in full (picked in the same way for src1 and src2) − the addend and the result use the full lane. For each 32-bit lane, treat src1 and src2 as 2-component vectors of signed 16-bit values, then compute their dot-product, then add src3 as a 32-bit value. ForVPPERM dst,src1,src2,src3, src2:src1 are considered a 32-element vector of bytes. For each byte-lane, the byte in src3 is used to index into this 32-byte vector and transform the element: Rotation amount is given in the last source argument. It may be provided as an immediate or a vector register − in the latter case, the rotation amount is provided on a per-lane basis. Shift-amount is provided on a per-vector-lane basis, and is taken from the bottom 8 bits of each lane of the last source argument. The shift-amount is considered signed − a positive value will cause left-shift, while a negative value causes right-shift. XOP also included two vector instructions that used the VEX prefix instead of the XOP prefix: The instructionsVPERMIL2PDandVPERMIL2PSwere originally defined by Intel in early drafts of the AVX specification[24]− they were removed in later drafts[25][26]and were never implemented in any Intel processor. They were, however, implemented by AMD, who designated them as being a part of the XOP instruction set extension. (Like the other parts of XOP, they've been removed inAMD Zen.) Supported in AMD processors starting with theBulldozerarchitecture, removed inZen. Not supported by any Intel chip as of 2023. Fused multiply-addwith four operands. FMA4 was realized in hardware before FMA3. AMD introduced TBM together with BMI1 in itsPiledriver[27]line of processors; later AMD Jaguar and Zen-based processors do not support TBM.[28]No Intel processors (as of 2023) support TBM. The TBM instructions are all encoded using the XOP prefix. They are all available in 32-bit and 64-bit forms, selected with the XOP.W bit (0=32bit, 1=64bit). (XOP.W is ignored outside 64-bit mode.) Like all instructions encoded with VEX/XOP prefixes, they are unavailable in Real Mode and Virtual-8086 mode. The imm32 is interpreted as follows: The AMD Lightweight Profiling (LWP) feature was introduced in AMDBulldozerand removed inAMD Zen. On all supported CPUs, the latest available microcode updates have disabled LWP due toSpectremitigations.[31] These instructions are available in Ring 3, but not available in Real Mode and Virtual-8086 mode. All of them use the XOP prefix. Loading an address of 0 disables LWP. Loading a nonzero address will cause the CPU to perform validation of the specified LWPCB, then enable LWP if the validation passed. If LWP was already enabled, state for the previous LWPCB is flushed to memory. If LWP is not enabled, the stored address is 0. TheLWPINSinstruction sets CF=1 if LWP is enabled and the ring buffer is full, CF=0 otherwise. Executes as NOP if LWP is not enabled or if the event counter is not enabled. If no event record is inserted, then the second argument (which may be a memory argument) is not accessed. These instructions are specific to the NEC V20/V30 CPUs and their successors, and do not appear in any non-NEC CPUs. Many of their opcodes have been reassigned to other instructions in later non-NEC CPUs. First argument specifies an 8/16-bit register or memory location to test a bit in. Second argument specifies which bit to test. Performs a string addition of integers in packed BCD format (2 BCD digits per byte). DS:SI points to a source integer, ES:DI to a destination integer, and CL provides the number of digits to add. The operation is then: destination <- destination + source destination <- destination − source Concatenates its 8-bit argument with the bottom 4 bits of AL to form a 12-bit bitvector, then left-rotates this bitvector by 4 bits, then writes this bitvector back to its argument and the bottom 4 bits of AL. Perform a bitfield read from memory. DS:SI (DS0:IX in NEC nomenclature) points to memory location to read from, first argument specifies bit-offset to read from, and second argument specifies the number of bits to read minus 1. The result is placed in AX. After the bitfield read, SI and the first argument are updated to point just beyond the just-read bitfield. Perform a bitfield write to memory. ES:DI (DS1:IY in NEC nomenclature) points to memory location to write to, AX contains data to write, first argument specifies bit-offset to write to, and second argument specifies the number of bits to write minus 1. After the bitfield write, DI and the first argument are updated to point just beyond the just-written bitfield. The FPO2 escape opcodes are used by the NEC 72291 floating-point coprocessor - this coprocessor also uses the standardD8-DFescape opcodes, but uses them to encode an instruction set that is unique to the 72291 and not compatible with x87. A listing of the opcodes/instructions supported by the 72291 is available.[34] Jump to an address picked from the IVT (Interrupt Vector Table) using the imm8 argument, similar to the 8086INTinstruction, but start executing asIntel 8080code rather than x86 code. Jump to an address picked from the IVT using the imm8 argument. Enables a simple memory paging mechanism after reading the IVT but before executing the jump. The paging mechanism uses an on-chip page table with 16Kbyte pages and no access rights checking.[35] Jump to an address picked from the IVT using the imm8 argument. Disables paging after reading the IVT but before executing the jump. The first argument specifies a V25/V35 Special Function Register to test a bit in. The second argument specifies a bit position in that register. The third argument specifies a short branch offset. If the bit was set to 1, then it is cleared and a short branch is taken, else the branch is not taken. Differs from the conventional 8086HLTinstruction in that the clock is stopped too, so that an NMI or CPU reset is needed to resume operation. Jump to an address picked from the IVT using the imm8 argument, and then continue execution with "Software Guard" enabled. The "Software Guard" is an 8-bitSubstitution cipherthat, during instruction fetch/decode, translates opcode bytes using a 256-entry lookup table stored in an on-chipMask ROM. The DS2 and DS3 registers (which are specific to the NEC V55) act similar to regular x86real modesegment registers except that they are left-shifted by 8 rather than 4, enabling access to 16MB of memory. Block transfer instructions, such as MOVBKW, can access the 16MB memory space by simultaneously prefixing with DS2 and DS3.[39] When used with string instructions such as MOVBKW, the DS2: prefix overrides the DS segment, while the DS3: prefix overrides the ES segment. These instructions are present in Cyrix CPUs as well as NatSemi/AMD Geode CPUs derived from Cyrix microarchitectures (Geode GX and LX, but not NX). They are also present inCyrix manufacturing partner CPUsfrom IBM, ST and TI, as well as the VIACyrix III("Joshua" core only, not "Samuel") and a few SoCs such as STPC ATLAS and ZFMicro ZFx86.[43]Many of these opcodes have been reassigned to other instructions in later non-Cyrix CPUs. The first 8 bytes are the descriptor, the last two bytes are the selector.[44] Not present on stepping A of Cx486SLC and Cx486DLC.[45] Present on Cx486SLC/e[46]and all later Cyrix CPUs. Present on all Cyrix-derived Geode CPUs. Uses0F 7Eencoding on Cyrix 486, 5x86, 6x86 and ZFx86. Uses0F 38encoding on Cyrix 6x86MX, MII, MediaGX and Geode. Not available on any Ti486 processors. VIA Cyrix III[51] NatSemi Geode GXm, GXLV, GX1 AMD Geode GX, LX[47] These instructions were introduced in the Cyrix6x86MXand MII processors, and were also present in theMediaGXmand Geode GX1[53]processors. (In later non-Cyrix processors, all of their opcodes have been used for SSE or SSE2 instructions.) These instructions are integer SIMD instructions acting on 64-bit vectors in MMX registers or memory. Each instruction takes two explicit operands, where the first one is an MMX register operand and the second one is either a memory operand or a second MMX register. In addition, several of the instructions take an implied operand, which is an MMX register implied from the first operand as follows: In the instruction descriptions in the below table,arg1andarg2refer to the two explicit operands of the instruction, andimpto the implied operand. Condition is evaluated on a per-byte-lane basis, by comparing byte lanes in the implied source to zero (with signed compare) − if the comparison passes, then the corresponding destination lane is loaded from memory, otherwise it keeps its original value. Some assemblers/disassemblers, such as NASM, resolve this ambiguity by using the mnemonicPMULHRWAfor the 3DNow! instruction andPMULHRWCfor the EMMI instruction. AllVIA C3processors support the VIA AIS (Alternate Instruction Set). The x86 instructions present in these processors to support AIS are: 32-bit immediate is treated as a 32-bit instruction of the RISC-like Alternate Instruction Set. An instruction set reference is available.[56] These instructions are not present inVIA C7or any later VIA processor. The C&T F8680 PC/Chip is a system-on-a-chip featuring an 80186-compatible CPU core, with a few additional instructions to support the F8680-specific "SuperState R"[58]supervisor/system-management feature. Some of the added instructions for "SuperState R" are:[59] C&T also developed a 386-compatible processor known as the Super386. This processor supports, in addition to the basic Intel 386 instruction set, a number of instructions to support the Super386-specific"SuperState V"system-management feature. The added instructions for"SuperState V"are:[7] TheM6117series of embedded microcontrollers feature an Intel 386SX compatible CPU core derived from V.M. Technology (VMT) VM386SX+ processor. VMT VM386SX+ adds a few processor specific additions to the Intel 386 instruction set. The ones documented for DM&P M6117D are:[63] Several 80387-class floating-point coprocessors provided extra instructions in addition to the standard 80387 ones − none of these are supported in later processors: or DB E5[12] Instruction to signal to the FPU that the main CPU is exiting protected mode, similar to how the FSETPM instruction is used to signal to the FPU that the CPU is entering protected mode. Different sources provide different encodings for this instruction. FMUL4X4 C code"RECIP28EXP2.c"archivedon Sep 18, 2023.	https://en.wikipedia.org/wiki/List_of_discontinued_x86_instructions
Incomputing, aBloom filteris a space-efficientprobabilisticdata structure, conceived byBurton Howard Bloomin 1970, that is used to test whether anelementis a member of aset.False positivematches are possible, butfalse negativesare not – in other words, a query returns either "possibly in set" or "definitely not in set". Elements can be added to the set, but not removed (though this can be addressed with thecounting Bloom filtervariant); the more items added, the larger the probability of false positives. Bloom proposed the technique for applications where the amount of source data would require an impractically large amount of memory if "conventional" error-freehashingtechniques were applied. He gave the example of ahyphenation algorithmfor a dictionary of 500,000 words, out of which 90% follow simple hyphenation rules, but the remaining 10% require expensive disk accesses to retrieve specific hyphenation patterns. With sufficientcore memory, an error-free hash could be used to eliminate all unnecessary disk accesses; on the other hand, with limited core memory, Bloom's technique uses a smaller hash area but still eliminates most unnecessary accesses. For example, a hash area only 18% of the size needed by an ideal error-free hash still eliminates 87% of the disk accesses.[1] More generally, fewer than 10bitsper element are required for a 1% false positive probability, independent of the size or number of elements in the set.[2] Anempty Bloom filteris abit arrayofmbits, all set to 0. It is equipped withkdifferenthash functions, which map set elements to one of thempossible array positions. To be optimal, the hash functions should beuniformly distributedandindependent. Typically,kis a small constant which depends on the desired false error rateε, whilemis proportional tokand the number of elements to be added. Toaddan element, feed it to each of thekhash functions to getkarray positions. Set the bits at all these positions to 1. Totestwhether an element is in the set, feed it to each of thekhash functions to getkarray positions. Ifanyof the bits at these positions is 0, the element is definitely not in the set; if it were, then all the bits would have been set to 1 when it was inserted. If all are 1, then either the element is in the set,orthe bits have by chance been set to 1 during the insertion of other elements, resulting in afalse positive. In a simple Bloom filter, there is no way to distinguish between the two cases, but more advanced techniques can address this problem. The requirement of designingkdifferent independent hash functions can be prohibitive for largek. For a good hash function with a wide output, there should be little if any correlation between different bit-fields of such a hash, so this type of hash can be used to generate multiple "different" hash functions by slicing its output into multiple bit fields. Alternatively, one can passkdifferent initial values (such as 0, 1, ...,k− 1) to a hash function that takes an initial value; or add (or append) these values to the key. For largermand/ork, independence among the hash functions can be relaxed with negligible increase in false positive rate.[3](Specifically,Dillinger & Manolios (2004b)show the effectiveness of deriving thekindices usingenhanced double hashingandtriple hashing, variants ofdouble hashingthat are effectively simple random number generators seeded with the two or three hash values.) Removing an element from this simple Bloom filter is impossible because there is no way to tell which of thekbits it maps to should be cleared. Although setting any one of thosekbits to zero suffices to remove the element, it would also remove any other elements that happen to map onto that bit. Since the simple algorithm provides no way to determine whether any other elements have been added that affect the bits for the element to be removed, clearing any of the bits would introduce the possibility of false negatives. One-time removal of an element from a Bloom filter can be simulated by having a second Bloom filter that contains items that have been removed. However, false positives in the second filter become false negatives in the composite filter, which may be undesirable. In this approach re-adding a previously removed item is not possible, as one would have to remove it from the "removed" filter. It is often the case that all the keys are available but are expensive to enumerate (for example, requiring many disk reads). When the false positive rate gets too high, the filter can be regenerated; this should be a relatively rare event. While risking false positives, Bloom filters have a substantial space advantage over other data structures for representing sets, such asself-balancing binary search trees,tries,hash tables, or simplearraysorlinked listsof the entries. Most of these require storing at least the data items themselves, which can require anywhere from a small number of bits, for small integers, to an arbitrary number of bits, such as for strings (triesare an exception since they can share storage between elements with equal prefixes). However, Bloom filters do not store the data items at all, and a separate solution must be provided for the actual storage. Linked structures incur an additional linear space overhead for pointers. A Bloom filter with a 1% error and an optimal value ofk, in contrast, requires only about 9.6 bits per element, regardless of the size of the elements. This advantage comes partly from its compactness, inherited from arrays, and partly from its probabilistic nature. The 1% false-positive rate can be reduced by a factor of ten by adding only about 4.8 bits per element. However, if the number of potential values is small and many of them can be in the set, the Bloom filter is easily surpassed by the deterministicbit array, which requires only one bit for each potential element. Hash tables gain a space and time advantage if they begin ignoring collisions and store only whether each bucket contains an entry; in this case, they have effectively become Bloom filters withk= 1.[4] Bloom filters also have the unusual property that the time needed either to add items or to check whether an item is in the set is a fixed constant,O(k), completely independent of the number of items already in the set. No other constant-space set data structure has this property, but the average access time of sparsehash tablescan make them faster in practice than some Bloom filters. In a hardware implementation, however, the Bloom filter shines because itsklookups are independent and can be parallelized. To understand its space efficiency, it is instructive to compare the general Bloom filter with its special case whenk= 1. Ifk= 1, then in order to keep the false positive rate sufficiently low, a small fraction of bits should be set, which means the array must be very large and contain long runs of zeros. Theinformation contentof the array relative to its size is low. The generalized Bloom filter (kgreater than 1) allows many more bits to be set while still maintaining a low false positive rate; if the parameters (kandm) are chosen well, about half of the bits will be set,[5]and these will be apparently random, minimizing redundancy and maximizing information content. Assume that ahash functionselects each array position with equal probability. Ifmis the number of bits in the array, the probability that a certain bit is not set to 1 by a certain hash function during the insertion of an element is Ifkis the number of hash functions and each has no significant correlation between each other, then the probability that the bit is not set to 1 by any of the hash functions is We can use the well-known identity fore−1 to conclude that, for largem, If we have insertednelements, the probability that a certain bit is still 0 is the probability that it is 1 is therefore Now test membership of an element that is not in the set. Each of thekarray positions computed by the hash functions is 1 with a probability as above. The probability of all of them being 1, which would cause thealgorithmto erroneously claim that the element is in the set, is often given as This is not strictly correct as it assumes independence for the probabilities of each bit being set. However, assuming it is a close approximation we have that the probability of false positives decreases asm(the number of bits in the array) increases, and increases asn(the number of inserted elements) increases. The true probability of a false positive, without assuming independence, is where the {braces} denoteStirling numbers of the second kind.[6] An alternative analysis arriving at the same approximation without the assumption of independence is given by Mitzenmacher and Upfal.[7]After allnitems have been added to the Bloom filter, letqbe the fraction of thembits that are set to 0. (That is, the number of bits still set to 0 isqm.) Then, when testing membership of an element not in the set, for the array position given by any of thekhash functions, the probability that the bit is found set to 1 is1−q{\displaystyle 1-q}. So the probability that allkhash functions find their bit set to 1 is(1−q)k{\displaystyle (1-q)^{k}}. Further, the expected value ofqis the probability that a given array position is left untouched by each of thekhash functions for each of thenitems, which is (as above) It is possible to prove, without the independence assumption, thatqis very strongly concentrated around its expected value. In particular, from theAzuma–Hoeffding inequality, they prove that[8] Because of this, we can say that the exact probability of false positives is as before. The number of hash functions,k, must be a positive integer. Putting this constraint aside, for a givenmandn, the value ofkthat minimizes the false positive probability is The required number of bits,m, givenn(the number of inserted elements) and a desired false positive probabilityε(and assuming the optimal value ofkis used) can be computed by substituting the optimal value ofkin the probability expression above: which can be simplified to: This results in: So the optimal number of bits per element is with the corresponding number of hash functionsk(ignoring integrality): This means that for a given false positive probabilityε, the length of a Bloom filtermis proportionate to the number of elements being filterednand the required number of hash functions only depends on the target false positive probabilityε.[9] The formulam=−nln⁡ε(ln⁡2)2{\displaystyle m=-{\frac {n\ln \varepsilon }{(\ln 2)^{2}}}}is approximate for three reasons. First, and of least concern, it approximates1−1m{\displaystyle 1-{\frac {1}{m}}}ase−1m{\displaystyle e^{-{\frac {1}{m}}}}, which is a good asymptotic approximation (i.e., which holds asm→∞). Second, of more concern, it assumes that during the membership test the event that one tested bit is set to 1 is independent of the event that any other tested bit is set to 1. Third, of most concern, it assumes thatk=mnln⁡2{\displaystyle k={\frac {m}{n}}\ln 2}is fortuitously integral. Goel and Gupta,[10]however, give a rigorous upper bound that makes no approximations and requires no assumptions. They show that the false positive probability for a finite Bloom filter withmbits (m>1{\displaystyle m>1}),nelements, andkhash functions is at most This bound can be interpreted as saying that the approximate formula(1−e−knm)k{\displaystyle \left(1-e^{-{\frac {kn}{m}}}\right)^{k}}can be applied at a penalty of at most half an extra element and at most one fewer bit. The number of items in a Bloom filter can be approximated with the following formula, wheren∗{\displaystyle n^{}}is an estimate of the number of items in the filter,mis the length (size) of the filter,kis the number of hash functions, andXis the number of bits set to one.[11] Bloom filters are a way of compactly representing a set of items. It is common to try to compute the size of the intersection or union between two sets. Bloom filters can be used to approximate the size of the intersection and union of two sets. For two Bloom filters of lengthm, their counts, respectively can be estimated as and The size of their union can be estimated as wheren(A∪B){\displaystyle n(A\cup B)}is the number of bits set to one in either of the two Bloom filters. Finally, the intersection can be estimated as using the three formulas together.[11] Classic Bloom filters use1.44log2⁡(1/ε){\displaystyle 1.44\log _{2}(1/\varepsilon )}bits of space per inserted key, whereε{\displaystyle \varepsilon }is the false positive rate of the Bloom filter. However, the space that is strictly necessary for any data structure playing the same role as a Bloom filter is onlylog2⁡(1/ε){\displaystyle \log _{2}(1/\varepsilon )}per key.[26]Hence Bloom filters use 44% more space than an equivalent optimal data structure. Pagh et al. provide a data structure that uses(1+o(1))nlog2⁡(1/ϵ)+O(n){\textstyle (1+o(1))n\log _{2}(1/\epsilon )+O(n)}bits while supporting constant amortized expected-time operations.[27]Their data structure is primarily theoretical, but it is closely related to the widely-usedquotient filter, which can be parameterized to use(1+δ)nlog⁡ϵ−1+3n{\displaystyle (1+\delta )n\log \epsilon ^{-1}+3n}bits of space, for an arbitrary parameterδ>0{\displaystyle \delta >0}, while supportingO(δ−2){\displaystyle O(\delta ^{-2})}-time operations.[28]Advantages of the quotient filter, when compared to the Bloom filter, include itslocality of referenceand the ability to support deletions. Another alternative to classic Bloom filter is thecuckoo filter, based on space-efficient variants ofcuckoo hashing. In this case, a hash table is constructed, holding neither keys nor values, but short fingerprints (small hashes) of the keys. If looking up the key finds a matching fingerprint, then key is probably in the set. Cuckoo filters support deletions and have betterlocality of referencethan Bloom filters.[29]Additionally, in some parameter regimes, cuckoo filters can be parameterized to offer nearly optimal space guarantees.[29] Many alternatives to Bloom filters, includingquotient filtersandcuckoo filters, are based on the idea of hashing keys to random(log⁡n+log⁡ϵ−1){\displaystyle (\log n+\log \epsilon ^{-1})}-bit fingerprints, and then storing those fingerprints in a compact hash table. This technique, which was first introduced by Carter et al. in 1978,[26]relies on the fact that compact hash tables can be implemented to use roughlynlog⁡n{\displaystyle n\log n}bits less space than their non-compact counterparts. Usingsuccincthash tables, the space usage can be reduced to as little asnlog2⁡(e/ϵ)+o(n){\displaystyle n\log _{2}(e/\epsilon )+o(n)}bits[30]while supporting constant-time operations in a wide variety of parameter regimes. Putze, Sanders & Singler (2007)have studied some variants of Bloom filters that are either faster or use less space than classic Bloom filters. The basic idea of the fast variant is to locate the k hash values associated with each key into one or two blocks having the same size as processor's memory cache blocks (usually 64 bytes). This will presumably improve performance by reducing the number of potential memorycache misses. The proposed variants have however the drawback of using about 32% more space than classic Bloom filters. The space efficient variant relies on using a single hash function that generates for each key a value in the range[0,n/ε]{\displaystyle \left[0,n/\varepsilon \right]}whereε{\displaystyle \varepsilon }is the requested false positive rate. The sequence of values is then sorted and compressed usingGolomb coding(or some other compression technique) to occupy a space close tonlog2⁡(1/ε){\displaystyle n\log _{2}(1/\varepsilon )}bits. To query the Bloom filter for a given key, it will suffice to check if its corresponding value is stored in the Bloom filter. Decompressing the whole Bloom filter for each query would make this variant totally unusable. To overcome this problem the sequence of values is divided into small blocks of equal size that are compressed separately. At query time only half a block will need to be decompressed on average. Because of decompression overhead, this variant may be slower than classic Bloom filters but this may be compensated by the fact that a single hash function needs to be computed. Graf & Lemire (2020)describes an approach called an xor filter, where they store fingerprints in a particular type ofperfect hashtable, producing a filter which is more memory efficient (1.23log2⁡(1/ε){\displaystyle 1.23\log _{2}(1/\varepsilon )}bits per key) and faster than Bloom or cuckoo filters. (The time saving comes from the fact that a lookup requires exactly three memory accesses, which can all execute in parallel.) However, filter creation is more complex than Bloom and cuckoo filters, and it is not possible to modify the set after creation. There are over 60 variants of Bloom filters, many surveys of the field, and a continuing churn of applications (see e.g., Luo,et al[31]). Some of the variants differ sufficiently from the original proposal to be breaches from or forks of the original data structure and its philosophy.[31]A treatment which unifies Bloom filters with other work onrandom projections,compressive sensing, andlocality sensitive hashingremains to be done (though see Dasgupta,et al[32]for one attempt inspired by neuroscience). Content delivery networksdeployweb cachesaround the world to cache and serve web content to users with greater performance and reliability. A key application of Bloom filters is their use in efficiently determining which web objects to store in these web caches. Nearly three-quarters of the URLs accessed from a typical web cache are "one-hit-wonders" that are accessed by users only once and never again. It is clearly wasteful of disk resources to store one-hit-wonders in a web cache, since they will never be accessed again. To prevent caching one-hit-wonders, a Bloom filter is used to keep track of all URLs that are accessed by users. A web object is cached only when it has been accessed at least once before, i.e., the object is cached on its second request. The use of a Bloom filter in this fashion significantly reduces the disk write workload, since most one-hit-wonders are not written to the disk cache. Further, filtering out the one-hit-wonders also saves cache space on disk, increasing the cache hit rates.[13] Kisset aldescribed a new construction for the Bloom filter that avoids false positives in addition to the typical non-existence of false negatives.[33]The construction applies to a finite universe from which set elements are taken. It relies on existing non-adaptive combinatorial group testing scheme by Eppstein, Goodrich and Hirschberg. Unlike the typical Bloom filter, elements are hashed to a bit array through deterministic, fast and simple-to-calculate functions. The maximal set size for which false positives are completely avoided is a function of the universe size and is controlled by the amount of allocated memory. Alternatively, an initial Bloom filter can be constructed in the standard way and then, with a finite and tractably-enumerable domain, all false positives can be exhaustively found and then a second Bloom filter constructed from that list; false positives in the second filter are similarly handled by constructing a third, and so on. As the universe is finite and the set of false positives strictly shrinks with each step, this procedure results in a finitecascadeof Bloom filters that (on this closed, finite domain) will produce only true positives and true negatives. To check for membership in the filter cascade, the initial filter is queried, and, if the result is positive, the second filter is then consulted, and so on. This construction is used inCRLite, a proposedcertificate revocation statusdistribution mechanism for theWeb PKI, andCertificate Transparencyis exploited to close the set of extant certificates.[34] Counting filters provide a way to implement adeleteoperation on a Bloom filter without recreating the filter afresh. In a counting filter, the array positions (buckets) are extended from being a single bit to being a multibit counter. In fact, regular Bloom filters can be considered as counting filters with a bucket size of one bit. Counting filters were introduced byFan et al. (2000). The insert operation is extended toincrementthe value of the buckets, and the lookup operation checks that each of the required buckets is non-zero. The delete operation then consists of decrementing the value of each of the respective buckets. Arithmetic overflowof the buckets is a problem and the buckets should be sufficiently large to make this case rare. If it does occur then the increment and decrement operations must leave the bucket set to the maximum possible value in order to retain the properties of a Bloom filter. The size of counters is usually 3 or 4 bits. Hence counting Bloom filters use 3 to 4 times more space than static Bloom filters. In contrast, the data structures ofPagh, Pagh & Rao (2005)andFan et al. (2014)also allow deletions but use less space than a static Bloom filter. Another issue with counting filters is limited scalability. Because the counting Bloom filter table cannot be expanded, the maximal number of keys to be stored simultaneously in the filter must be known in advance. Once the designed capacity of the table is exceeded, the false positive rate will grow rapidly as more keys are inserted. Bonomi et al. (2006)introduced a data structure based on d-left hashing that is functionally equivalent but uses approximately half as much space as counting Bloom filters. The scalability issue does not occur in this data structure. Once the designed capacity is exceeded, the keys could be reinserted in a new hash table of double size. The space efficient variant byPutze, Sanders & Singler (2007)could also be used to implement counting filters by supporting insertions and deletions. Rottenstreich, Kanizo & Keslassy (2012)introduced a new general method based on variable increments that significantly improves the false positive probability of counting Bloom filters and their variants, while still supporting deletions. Unlike counting Bloom filters, at each element insertion, the hashed counters are incremented by a hashed variable increment instead of a unit increment. To query an element, the exact values of the counters are considered and not just their positiveness. If a sum represented by a counter value cannot be composed of the corresponding variable increment for the queried element, a negative answer can be returned to the query. Kim et al. (2019)shows that false positive of Counting Bloom filter decreases from k=1 to a point definedkopt{\displaystyle k_{opt}}, and increases fromkopt{\displaystyle k_{opt}}to positive infinity, and findskopt{\displaystyle k_{opt}}as a function of count threshold.[35] Bloom filters can be organized in distributeddata structuresto perform fully decentralized computations ofaggregate functions. Decentralized aggregation makes collective measurements locally available in every node of a distributed network without involving a centralized computational entity for this purpose.[36] Parallel Bloom filters can be implemented to take advantage of the multipleprocessing elements(PEs) present inparallel shared-nothing machines. One of the main obstacles for a parallel Bloom filter is the organization and communication of the unordered data which is, in general, distributed evenly over all PEs at the initiation or at batch insertions. To order the data two approaches can be used, either resulting in a Bloom filter over all data being stored on each PE, called replicating bloom filter, or the Bloom filter over all data being split into equal parts, each PE storing one part of it.[37]For both approaches a "Single Shot" Bloom filter is used which only calculates one hash, resulting in one flipped bit per element, to reduce the communication volume. Distributed Bloom filtersare initiated by first hashing all elements on their local PE and then sorting them by their hashes locally. This can be done in linear time using e.g.Bucket sortand also allows local duplicate detection. The sorting is used to group the hashes with their assigned PE as separator to create a Bloom filter for each group. After encoding these Bloom filters using e.g.Golomb codingeach bloom filter is sent as packet to the PE responsible for the hash values that where inserted into it. A PE p is responsible for all hashes between the valuesp∗(s/\|PE\|){\displaystyle p(s/\|{\text{PE}}\|)}and(p+1)∗(s/\|PE\|){\displaystyle (p+1)(s/\|{\text{PE}}\|)}, where s is the total size of the Bloom filter over all data. Because each element is only hashed once and therefore only a single bit is set, to check if an element was inserted into the Bloom filter only the PE responsible for the hash value of the element needs to be operated on. Single insertion operations can also be done efficiently because the Bloom filter of only one PE has to be changed, compared to Replicating Bloom filters where every PE would have to update its Bloom filter. By distributing the global Bloom filter over all PEs instead of storing it separately on each PE the Bloom filters size can be far larger, resulting in a larger capacity and lower false positive rate.Distributed Bloom filters can be used to improve duplicate detection algorithms[38]by filtering out the most 'unique' elements. These can be calculated by communicating only the hashes of elements, not the elements themselves which are far larger in volume, and removing them from the set, reducing the workload for the duplicate detection algorithm used afterwards. During the communication of the hashes the PEs search for bits that are set in more than one of the receiving packets, as this would mean that two elements had the same hash and therefore could be duplicates. If this occurs a message containing the index of the bit, which is also the hash of the element that could be a duplicate, is sent to the PEs which sent a packet with the set bit. If multiple indices are sent to the same PE by one sender it can be advantageous to encode the indices as well. All elements that didn't have their hash sent back are now guaranteed to not be a duplicate and won't be evaluated further, for the remaining elements a Repartitioning algorithm[39]can be used. First all the elements that had their hash value sent back are sent to the PE that their hash is responsible for. Any element and its duplicate is now guaranteed to be on the same PE. In the second step each PE uses a sequential algorithm for duplicate detection on the receiving elements, which are only a fraction of the amount of starting elements. By allowing a false positive rate for the duplicates, the communication volume can be reduced further as the PEs don't have to send elements with duplicated hashes at all and instead any element with a duplicated hash can simply be marked as a duplicate. As a result, the false positive rate for duplicate detection is the same as the false positive rate of the used bloom filter. The process of filtering out the most 'unique' elements can also be repeated multiple times by changing the hash function in each filtering step. If only a single filtering step is used it has to archive a small false positive rate, however if the filtering step is repeated once the first step can allow a higher false positive rate while the latter one has a higher one but also works on less elements as many have already been removed by the earlier filtering step. While using more than two repetitions can reduce the communication volume further if the number of duplicates in a set is small, the payoff for the additional complications is low. Replicating Bloom filtersorganize their data by using a well knownhypercubealgorithm for gossiping, e.g.[40]First each PE calculates the Bloom filter over all local elements and stores it. By repeating a loop where in each step i the PEs send their local Bloom filter over dimension i and merge the Bloom filter they receive over the dimension with their local Bloom filter, it is possible to double the elements each Bloom filter contains in every iteration. After sending and receiving Bloom filters over alllog⁡\|PE\|{\displaystyle \log \|{\text{PE}}\|}dimensions each PE contains the global Bloom filter over all elements. Replicating Bloom filters are more efficient when the number of queries is much larger than the number of elements that the Bloom filter contains, the break even point compared to Distributed Bloom filters is approximately after\|PE\|∗\|Elements\|/logf+⁡\|PE\|{\displaystyle \|{\text{PE}}\|\|{\text{Elements}}\|/\log _{f^{\text{+}}}\|{\text{PE}}\|}accesses, withf+{\displaystyle f^{\text{+}}}as the false positive rate of the bloom filter. Bloom filters can be used for approximatedata synchronizationas inByers et al. (2004). Counting Bloom filters can be used to approximate the number of differences between two sets and this approach is described inAgarwal & Trachtenberg (2006). Bloom filters can be adapted to the context of streaming data. For instance,Deng & Rafiei (2006)proposed Stable Bloom filters, which consist of a counting Bloom filter where insertion of a new element sets the associated counters to a valuec, and then only a fixed amountsof counters are decreased by 1, hence the memory mostly contains information about recent elements (intuitively, one could assume that the lifetime of an element inside a SBF ofNcounters is aroundcsN{\displaystyle c{\tfrac {s}{N}}}). Another solution is the Aging Bloom filter, that consists of two Bloom filter each occupying half the total available memory: when one filter is full, the second filter is erased and newer elements are then added to this newly empty filter.[41] However, it has been shown[42]that no matter the filter, afterninsertions, the sum of the false positiveFP{\displaystyle FP}and false negativeFN{\displaystyle FN}probabilities is bounded below byFP+FN≥1−1−(1−1L)m1−(1−1L)n{\displaystyle FP+FN\geq 1-{\frac {1-\left(1-{\frac {1}{L}}\right)^{m}}{1-\left(1-{\frac {1}{L}}\right)^{n}}}}whereLis the amount of all possible elements (the alphabet size),mthe memory size (in bits), assumingn>m{\displaystyle n>m}. This result shows that forLbig enough andngoing to infinity, then the lower bound converges toFP+FN=1{\displaystyle FP+FN=1}, which is the characteristic relation of a random filter. Hence, after enough insertions, and if the alphabet is too big to be stored in memory (which is assumed in the context of probabilistic filters), it is impossible for a filter to perform better than randomness. This result can be leveraged by only expecting a filter to operate on a sliding window rather than the whole stream. In this case, the exponentnin the formula above is replaced byw, which gives a formula that might deviate from 1, ifwis not too small. Chazelle et al. (2004)designed a generalization of Bloom filters that could associate a value with each element that had been inserted, implementing anassociative array. Like Bloom filters, these structures achieve a small space overhead by accepting a small probability of false positives. In the case of "Bloomier filters", afalse positiveis defined as returning a result when the key is not in the map. The map will never return the wrong value for a key thatisin the map. Boldi & Vigna (2005)proposed alattice-based generalization of Bloom filters. Acompact approximatorassociates to each key an element of a lattice (the standard Bloom filters being the case of the Boolean two-element lattice). Instead of a bit array, they have an array of lattice elements. When adding a new association between a key and an element of the lattice, they compute the maximum of the current contents of thekarray locations associated to the key with the lattice element. When reading the value associated to a key, they compute the minimum of the values found in theklocations associated to the key. The resulting value approximates from above the original value. This implementation used a separate array for each hash function. This method allows for parallel hash calculations for both insertions and inquiries.[43] Almeida et al. (2007)proposed a variant of Bloom filters that can adapt dynamically to the number of elements stored, while assuring a minimum false positive probability. The technique is based on sequences of standard Bloom filters with increasing capacity and tighter false positive probabilities, so as to ensure that a maximum false positive probability can be set beforehand, regardless of the number of elements to be inserted. Spatial Bloom filters (SBF) were originally proposed byPalmieri, Calderoni & Maio (2014)as a data structure designed to storelocation information, especially in the context of cryptographic protocols for locationprivacy. However, the main characteristic of SBFs is their ability to storemultiple setsin a single data structure, which makes them suitable for a number of different application scenarios.[44]Membership of an element to a specific set can be queried, and the false positive probability depends on the set: the first sets to be entered into the filter during construction have higher false positive probabilities than sets entered at the end.[45]This property allows a prioritization of the sets, where sets containing more "important" elements can be preserved. A layered Bloom filter consists of multiple Bloom filter layers. Layered Bloom filters allow keeping track of how many times an item was added to the Bloom filter by checking how many layers contain the item. With a layered Bloom filter a check operation will normally return the deepest layer number the item was found in.[46] An attenuated Bloom filter of depth D can be viewed as an array of D normal Bloom filters. In the context of service discovery in a network, each node stores regular and attenuated Bloom filters locally. The regular or local Bloom filter indicates which services are offered by the node itself. The attenuated filter of level i indicates which services can be found on nodes that are i-hops away from the current node. The i-th value is constructed by taking a union of local Bloom filters for nodes i-hops away from the node.[47] For example, consider a small network, shown on the graph below. Say we are searching for a service A whose id hashes to bits 0,1, and 3 (pattern 11010). Let n1 node to be the starting point. First, we check whether service A is offered by n1 by checking its local filter. Since the patterns don't match, we check the attenuated Bloom filter in order to determine which node should be the next hop. We see that n2 doesn't offer service A but lies on the path to nodes that do. Hence, we move to n2 and repeat the same procedure. We quickly find that n3 offers the service, and hence the destination is located.[48] By using attenuated Bloom filters consisting of multiple layers, services at more than one hop distance can be discovered while avoiding saturation of the Bloom filter by attenuating (shifting out) bits set by sources further away.[47] Bloom filters are often used to search large chemical structure databases (seechemical similarity). In the simplest case, the elements added to the filter (called a fingerprint in this field) are just the atomic numbers present in the molecule, or a hash based on the atomic number of each atom and the number and type of its bonds. This case is too simple to be useful. More advanced filters also encode atom counts, larger substructure features like carboxyl groups, and graph properties like the number of rings. In hash-based fingerprints, a hash function based on atom and bond properties is used to turn a subgraph into aPRNGseed, and the first output values used to set bits in the Bloom filter. Molecular fingerprints started in the late 1940s as way to search for chemical structures searched on punched cards. However, it wasn't until around 1990 that Daylight Chemical Information Systems, Inc. introduced a hash-based method to generate the bits, rather than use a precomputed table. Unlike the dictionary approach, the hash method can assign bits for substructures which hadn't previously been seen. In the early 1990s, the term "fingerprint" was considered different from "structural keys", but the term has since grown to encompass most molecular characteristics which can be used for a similarity comparison, including structural keys, sparse count fingerprints, and 3D fingerprints. Unlike Bloom filters, the Daylight hash method allows the number of bits assigned per feature to be a function of the feature size, but most implementations of Daylight-like fingerprints use a fixed number of bits per feature, which makes them a Bloom filter. The original Daylight fingerprints could be used for both similarity and screening purposes. Many other fingerprint types, like the popular ECFP2, can be used for similarity but not for screening because they include local environmental characteristics that introduce false negatives when used as a screen. Even if these are constructed with the same mechanism, these are not Bloom filters because they cannot be used to filter.	https://en.wikipedia.org/wiki/Bloom_filter
Incomputer science,consistent hashing[1][2]is a special kind ofhashingtechnique such that when ahash tableis resized, onlyn/m{\displaystyle n/m}keys need to be remapped on average wheren{\displaystyle n}is the number of keys andm{\displaystyle m}is the number of slots. In contrast, in most traditional hash tables, a change in the number of array slots causes nearly all keys to be remapped because the mapping between the keys and the slots is defined by amodular operation. Consistent hashing evenly distributes cache keys acrossshards, even if some of the shards crash or become unavailable.[3] The term "consistent hashing" was introduced byDavid Kargeret al.atMITfor use indistributed caching, particularly for theweb.[4]This academic paper from 1997 inSymposium on Theory of Computingintroduced the term "consistent hashing" as a way of distributing requests among a changing population of web servers.[5]Each slot is then represented by a server in a distributed system or cluster. The addition of a server and the removal of a server (during scalability or outage) requires onlynum_keys/num_slots{\displaystyle num\_keys/num\_slots}items to be re-shuffled when the number of slots (i.e. servers) change. The authors mentionlinear hashingand its ability to handle sequential server addition and removal, while consistent hashing allows servers to be added and removed in an arbitrary order.[1]The paper was later re-purposed to address technical challenge of keeping track of a file inpeer-to-peer networkssuch as adistributed hash table.[6][7] Teradataused this technique in their distributed database[citation needed], released in 1986, although they did not use this term. Teradata still uses the concept of ahash tableto fulfill exactly this purpose.Akamai Technologieswas founded in 1998 by the scientistsDaniel LewinandF. Thomson Leighton(co-authors of the article coining "consistent hashing"). In Akamai's content delivery network,[8]consistent hashing is used to balance the load within a cluster of servers, while astable marriagealgorithm is used to balance load across clusters.[2] Consistent hashing has also been used to reduce the impact of partial system failures in large web applications to provide robust caching without incurring the system-wide fallout of a failure.[9]Consistent hashing is also the cornerstone ofdistributed hash tables(DHTs), which employ hash values to partition a keyspace across a distributed set of nodes, then construct an overlay network of connected nodes that provide efficient node retrieval by key. Rendezvous hashing, designed in 1996, is a simpler and more general technique[citation needed]. It achieves the goals of consistent hashing using the very different highest random weight (HRW) algorithm. In the problem ofload balancing, for example, when aBLOBhas to be assigned to one ofn{\displaystyle n}servers on acluster, a standard hash function could be used in such a way that we calculate the hash value for that BLOB, assuming the resultant value of the hash isβ{\displaystyle \beta }, we performmodular operationwith the number of servers (n{\displaystyle n}in this case) to determine the server in which we can place the BLOB:ζ=β%n{\displaystyle \zeta =\beta \ \%\ n}; hence the BLOB will be placed in the server whoseserver ID{\displaystyle {\text{server ID}}}is successor ofζ{\displaystyle \zeta }in this case. However, when a server is added or removed during outage or scaling (whenn{\displaystyle n}changes), all the BLOBs in every server should be reassigned and moved due torehashing, but this operation is expensive. Consistent hashing was designed to avoid the problem of having to reassign every BLOB when a server is added or removed throughout the cluster. The central idea is to use a hash function that maps both the BLOB and servers to a unit circle, usually2π{\displaystyle 2\pi }radians. For example,ζ=Φ%360{\displaystyle \zeta =\Phi \ \%\ 360}(whereΦ{\displaystyle \Phi }is hash of a BLOB or server's identifier, likeIP addressorUUID). Each BLOB is then assigned to the next server that appears on the circle in clockwise order. Usually,binary search algorithmorlinear searchis used to find a "spot" or server to place that particular BLOB inO(log⁡N){\displaystyle O(\log N)}orO(N){\displaystyle O(N)}complexities respectively; and in every iteration, which happens in clockwise manner, an operationζ≤Ψ{\displaystyle \zeta \ \leq \ \Psi }(whereΨ{\displaystyle \Psi }is the value of the server within the cluster) is performed to find the server to place the BLOB. This provides an even distribution of BLOBs to servers. But, more importantly, if a server fails and is removed from the circle, only the BLOBs that were mapped to the failed server need to be reassigned to the next server in clockwise order. Likewise, if a new server is added, it is added to the unit circle, and only the BLOBs mapped to that server need to be reassigned. Importantly, when a server is added or removed, the vast majority of the BLOBs maintain their prior server assignments, and the addition ofnth{\displaystyle n^{th}}server only causes1/n{\displaystyle 1/n}fraction of the BLOBs to relocate. Although the process of moving BLOBs across cache servers in the cluster depends on the context, commonly, the newly added cache server identifies its "predecessor" and moves all the BLOBs, whose mapping belongs to this server (i.e. whose hash value is less than that of the new server), from it. However, in the case ofweb page caches, in most implementations there is no involvement of moving or copying, assuming the cached BLOB is small enough. When a request hits a newly added cache server, acache misshappens and a request to the actualweb serveris made and the BLOB is cached locally for future requests. The redundant BLOBs on the previously used cache servers would be removed as per thecache eviction policies.[10] Lethb(x){\displaystyle h_{b}(x)}andhs(x){\displaystyle h_{s}(x)}be the hash functions used for the BLOB and server's unique identifier respectively. In practice, abinary search tree(BST) is used to dynamically maintain theserver ID{\displaystyle {\text{server ID}}}within a cluster or hashring, and to find the successor or minimum within the BST,tree traversalis used. To avoidskewnessof multiple nodes within the radian, which happen due to lack ofuniform distributionof the servers within the cluster, multiple labels are used. Those duplicate labels are called "virtual nodes" i.e. multiple labels which point to a single "real" label or server within the cluster. The amount of virtual nodes or duplicate labels used for a particular server within a cluster is called the "weight" of that particular server.[14] A number of extensions to the basic technique are needed for effectively using consistent hashing for load balancing in practice. In the basic scheme above, if a server fails, all its BLOBs are reassigned to the next server in clockwise order, potentially doubling the load of that server. This may not be desirable. To ensure a more even redistribution of BLOBs on server failure, each server can be hashed to multiple locations on the unit circle. When a server fails, the BLOBs assigned to each of its replicas on the unit circle will get reassigned to a different server in clockwise order, thus redistributing the BLOBs more evenly. Another extension concerns a situation where a single BLOB gets "hot" and is accessed a large number of times and will have to be hosted in multiple servers. In this situation, the BLOB may be assigned to multiple contiguous servers by traversing the unit circle in clockwise order. A more complex practical consideration arises when two BLOBs are hashed near each other in the unit circle and both get "hot" at the same time. In this case, both BLOBs will use the same set of contiguous servers in the unit circle. This situation can be ameliorated by each BLOB choosing a different hash function for mapping servers to the unit circle.[2] Rendezvous hashing, designed in 1996, is a simpler and more general technique, and permits fully distributed agreement on a set ofk{\displaystyle k}options out of a possible set ofn{\displaystyle n}options.It can in fact be shownthat consistent hashing is a special case of rendezvous hashing. Because of its simplicity and generality, rendezvous hashing is now being used in place of Consistent Hashing in many applications. If key values will always increasemonotonically, an alternative approach using ahash table with monotonic keysmay be more suitable than consistent hashing.[citation needed] TheO(K/N){\displaystyle O(K/N)}is an average cost for redistribution of keys and theO(log⁡N){\displaystyle O(\log N)}complexity for consistent hashing comes from the fact that abinary searchamong nodes angles is required to find the next node on the ring.[citation needed] Known examples of consistent hashing use include:	https://en.wikipedia.org/wiki/Consistent_hashing
Extendible hashingis a type ofhashsystem which treats a hash as a bit string and uses atriefor bucket lookup.[1]Because of the hierarchical nature of the system, re-hashing is an incremental operation (done one bucket at a time, as needed). This means that time-sensitive applications are less affected by table growth than by standard full-table rehashes. Extendible hashing was described byRonald Faginin 1979. Practically all modern filesystems use either extendible hashing orB-trees. In particular, theGlobal File System,ZFS, and the SpadFS filesystem use extendible hashing.[2] Assume that the hash functionh(k){\displaystyle h(k)}returns a string of bits. The firsti{\displaystyle i}bits of each string will be used as indices to figure out where they will go in the "directory" (hash table), wherei{\displaystyle i}is the smallest number such that the index of every item in the table is unique. Keys to be used: Let's assume that for this particular example, the bucket size is 1. The first two keys to be inserted, k1and k2, can be distinguished by themost significant bit, and would be inserted into the table as follows: Now, if k3were to be hashed to the table, it wouldn't be enough to distinguish all three keys by one bit (because both k3and k1have 1 as their leftmost bit). Also, because the bucket size is one, the table would overflow. Because comparing the first two most significant bits would give each key a unique location, the directory size is doubled as follows: And so now k1and k3have a unique location, being distinguished by the first two leftmost bits. Because k2is in the top half of the table, both 00 and 01 point to it because there is no other key to compare to that begins with a 0. The above example is fromFagin et al. (1979). Now, k4needs to be inserted, and it has the first two bits as 01..(1110), and using a 2 bit depth in the directory, this maps from 01 to Bucket A. Bucket A is full (max size 1), so it must be split; because there is more than one pointer to Bucket A, there is no need to increase the directory size. What is needed is information about: In order to distinguish the two action cases: Examining the initial case of an extendible hash structure, if each directory entry points to one bucket, then the local depth should be equal to the global depth. The number of directory entries is equal to 2global depth, and the initial number of buckets is equal to 2local depth. Thus if global depth = local depth = 0, then 20= 1, so an initial directory of one pointer to one bucket. Back to the two action cases; if the bucket is full: Key 01 points to Bucket A, and Bucket A's local depth of 1 is less than the directory's global depth of 2, which means keys hashed to Bucket A have only used a 1 bit prefix (i.e. 0), and the bucket needs to have its contents split using keys 1 + 1 = 2 bits in length; in general, for any local depth d where d is less than D, the global depth, then d must be incremented after a bucket split, and the new d used as the number of bits of each entry's key to redistribute the entries of the former bucket into the new buckets. Now, is tried again, with 2 bits 01.., and now key 01 points to a new bucket but there is still⁠k2{\displaystyle k_{2}}⁠in it (h(k2)=010110{\displaystyle h(k_{2})=010110}and also begins with 01). If⁠k2{\displaystyle k_{2}}⁠had been 000110, with key 00, there would have been no problem, because⁠k2{\displaystyle k_{2}}⁠would have remained in the new bucket A' and bucket D would have been empty. (This would have been the most likely case by far when buckets are of greater size than 1 and the newly split buckets would be exceedingly unlikely to overflow, unless all the entries were all rehashed to one bucket again. But just to emphasize the role of the depth information, the example will be pursued logically to the end.) So Bucket D needs to be split, but a check of its local depth, which is 2, is the same as the global depth, which is 2, so the directory must be split again, in order to hold keys of sufficient detail, e.g. 3 bits. Now,h(k2)=010110{\displaystyle h(k_{2})=010110}is in D andh(k4)=011110{\displaystyle h(k_{4})=011110}is tried again, with 3 bits 011.., and it points to bucket D which already contains⁠k2{\displaystyle k_{2}}⁠so is full; D's local depth is 2 but now the global depth is 3 after the directory doubling, so now D can be split into bucket's D' and E, the contents of D,⁠k2{\displaystyle k_{2}}⁠has itsh(k2){\displaystyle h(k_{2})}retried with a new global depth bitmask of 3 and⁠k2{\displaystyle k_{2}}⁠ends up in D', then the new entry⁠k4{\displaystyle k_{4}}⁠is retried withh(k4){\displaystyle h(k_{4})}bitmasked using the new global depth bit count of 3 and this gives 011 which now points to a new bucket E which is empty. So⁠k4{\displaystyle k_{4}}⁠goes in Bucket E. Below is the extendible hashing algorithm inPython, with the disc block / memory page association, caching and consistency issues removed. Note a problem exists if the depth exceeds the bit size of an integer, because then doubling of the directory or splitting of a bucket won't allow entries to be rehashed to different buckets. The code uses theleast significant bits, which makes it more efficient to expand the table, as the entire directory can be copied as one block (Ramakrishnan & Gehrke (2003)).	https://en.wikipedia.org/wiki/Extendible_hashing
Ahash array mapped trie[1](HAMT) is an implementation of anassociative arraythat combines the characteristics of ahash tableand anarray mapped trie.[1]It is a refined version of the more general notion of ahash tree. A HAMT is an array mapped trie where the keys are first hashed to ensure an even distribution of keys and a constant key length. In a typical implementation of HAMT's array mapped trie, each node contains a table with some fixed number N of slots with each slot containing either a nil pointer or a pointer to another node. N is commonly 32. As allocating space for N pointers for each node would be expensive, each node instead contains a bitmap which is N bits long where each bit indicates the presence of a non-nil pointer. This is followed by an array of pointers equal in length to the number of ones in the bitmap (itsHamming weight). The hash array mapped trie achieves almost hash table-like speed while using memory much more economically. Also, a hash table may have to be periodically resized, an expensive operation, whereas HAMTs grow dynamically. Generally, HAMT performance is improved by a larger root table with some multiple of N slots; some HAMT variants allow the root to grow lazily[1]with negligible impact on performance. Implementation of a HAMT involves the use of thepopulation countfunction, which counts the number of ones in the binary representation of a number. This operation is available inmany instruction set architectures, but it isavailable in only some high-level languages. Although population count can be implemented in software inO(1)time using aseries of shift and add instructions, doing so may perform the operation an order of magnitude slower.[citation needed] The programming languagesClojure,[2]Scala, andFrege[3]use apersistentvariant of hash array mapped tries for their native hash map type. TheHaskelllibrary "unordered-containers" uses the same to implement persistent map and set data structures.[4]Another Haskell library "stm-containers" adapts the algorithm for use in the context ofsoftware transactional memory.[5]AJavascriptHAMT library[6]based on the Clojure implementation is also available. TheRubinius[7]implementation ofRubyincludes a HAMT, mostly written in Ruby but with 3[8]primitives. Large maps inErlanguse apersistentHAMT representation internally since release 18.0.[9]The Pony programming language uses a HAMT for the hash map in its persistent collections package.[10]The im and im-rc crates, which provide persistent collection types for the Rust programming language, use a HAMT for their persistent hash tables and hash sets.[11] The concurrent lock-free version[12]of the hash trie calledCtrieis a mutable thread-safe implementation which ensures progress. The data-structure has been proven to be correct[13]- Ctrie operations have been shown to have theatomicity,linearizabilityandlock-freedomproperties.	https://en.wikipedia.org/wiki/Hash_array_mapped_trie
Incomputer science,lazy deletionrefers to a method of deleting elements from ahash tablethat usesopen addressing. In this method, deletions are done by marking an element as deleted, rather than erasing it entirely. Deleted locations are treated as empty when inserting and as occupied during a search. The deleted locations are sometimes referred to astombstones.[1] The problem with this scheme is that as the number of delete/insert operations increases, the cost of a successful search increases. To improve this, when an element is searched and found in the table, the element is relocated to the first location marked for deletion that was probed during the search. Instead of finding an element to relocate when the deletion occurs, the relocation occurs lazily during the next search.[2][3] Thisalgorithmsordata structures-related article is astub. You can help Wikipedia byexpanding it.	https://en.wikipedia.org/wiki/Lazy_deletion
Pearson hashingis anon-cryptographic hash functiondesigned for fast execution on processors with 8-bitregisters. Given an input consisting of any number of bytes, it produces as output a single byte that is strongly dependent on every byte of the input. Its implementation requires only a few instructions, plus a 256-bytelookup tablecontaining apermutationof the values 0 through 255.[1] This hash function is aCBC-MACthat uses an 8-bitsubstitution cipherimplemented via thesubstitution table. An 8-bitcipherhas negligible cryptographic security, so the Pearson hash function is notcryptographically strong, but it is useful for implementinghash tablesor as adata integrity check code, for which purposes it offers these benefits: One of its drawbacks when compared with other hashing algorithms designed for8-bit processorsis the suggested 256 byte lookup table, which can be prohibitively large for a smallmicrocontrollerwith a program memory size on the order of hundreds of bytes. A workaround to this is to use a simple permutation function instead of a table stored in program memory. However, using a too simple function, such asT[i] = 255-i, partly defeats the usability as a hash function asanagramswill result in the same hash value; using a too complex function, on the other hand, will affect speed negatively. Using a function rather than a table also allows extending the block size. Such functions naturally have to bebijective, like their table variants. The algorithm can be described by the followingpseudocode, which computes the hash of messageCusing the permutation tableT: The hash variable (h) may be initialized differently, e.g. to the length of the data (C) modulo 256.	https://en.wikipedia.org/wiki/Pearson_hashing
PhotoDNAis aproprietaryimage-identification andcontent filteringtechnology[1]widely used byonline service providers.[2][3] PhotoDNA was developed byMicrosoft ResearchandHany Farid, professor atDartmouth College, beginning in 2009. From a database of known images and video files, it creates uniquehashesto represent each image, which can then be used to identify other instances of those images.[4] The hashing method initially relied on converting images into a black-and-white format, dividing them into squares, and quantifying the shading of the squares,[5]did not employ facial recognition technology, nor could it identify a person or object in the image.[citation needed]The method sought to be resistant to alterations in the image, including resizing and minor color alterations.[4]Since 2015,[6]similar methods are used for individualvideo framesin video files.[7] Microsoft donated[failed verification]the PhotoDNA technology toProject VIC, managed and supported by theInternational Centre for Missing & Exploited Children(ICMEC) and used as part ofdigital forensicsoperations[8][9]by storing "fingerprints" that can be used to uniquely identify an individual photo.[9][10]The database includes hashes for millions of items.[11] In December 2014, Microsoft made PhotoDNA available to qualified organizations in asoftware as a servicemodel for free through theAzure Marketplace.[12] In the 2010s and 2020s, PhotoDNA was put forward in connection with policy proposals relating tocontent moderationandinternet censorship,[13]includingUS Senatehearings (2019 on "digital responsibility",[2]2022 on theEARN IT Act[14]) and various proposals by theEuropean Commissiondubbed "upload filters" by civil society[15][16]such as so-called voluntary codes (in 2016[17]on hate speech[18]after2015 events, 2018[19]and 2022[20]on disinformation), copyright legislation (chiefly the2019 copyright directivedebated between 2014[21]and 2021[22]),terrorism-related regulations (TERREG)[23]andinternet wiretappingregulations (2021 "chat control").[24] In 2016, Hany Farid proposed to extend usage of the technology toterrorism-related content.[25]In December 2016, Facebook, Twitter, Google and Microsoft announced plans to use PhotoDNA to remove extremist content such as terrorist recruitment videos or violent terrorist imagery.[26]In 2018 Facebook stated that PhotoDNA was used to automatically removeal-Qaedavideos.[13] By 2019,big techcompanies including Microsoft, Facebook and Google publicly announced that since 2017 they were running theGIFCTas a shared database of content to be automatically censored.[2]As of 2021,Applewas thought to be usingNeuralHashfor similar purposes.[27] In 2022,The New York Timescovered the story of two dads whose Google accounts were closed after photos they took of their child for medical purposes were automatically uploaded to Google's servers.[28]The article compares PhotoDNA, which requires a database of known hashes, with Google's AI-based technology, which can recognize previously unseen exploitative images.[29][30] Microsoft originally used PhotoDNA on its own services includingBingandOneDrive.[31]As of 2022, PhotoDNA was widely used byonline service providersfor theircontent moderationefforts[10][32][33]includingGoogle'sGmail,Twitter,[34]Facebook,[35]Adobe Systems,[36]Reddit,[37]andDiscord.[38] The UKInternet Watch Foundation, which has been compiling a reference database of PhotoDNA signatures, reportedly had over 300,000 hashes of known child sexual exploitation materials.[citation needed]Another source of the database was theNational Center for Missing & Exploited Children(NCMEC).[39][40] PhotoDNA is widely used to remove content,[2]disable accounts, and report people.[7] In 2021, Anish Athalye was able to partially invert PhotoDNA hashes with a neural network, which raises concerns about the reversibility of a PhotoDNA hash.[41]	https://en.wikipedia.org/wiki/PhotoDNA
Incomputer science, theRabin–Karp algorithmorKarp–Rabin algorithmis astring-searching algorithmcreated byRichard M. KarpandMichael O. Rabin(1987) that useshashingto find an exact match of a pattern string in a text. It uses arolling hashto quickly filter out positions of the text that cannot match the pattern, and then checks for a match at the remaining positions. Generalizations of the same idea can be used to find more than one match of a single pattern, or to find matches for more than one pattern. To find a single match of a single pattern, theexpected timeof the algorithm islinearin the combined length of the pattern and text, although itsworst-case time complexityis the product of the two lengths. To find multiple matches, the expected time is linear in the input lengths, plus the combined length of all the matches, which could be greater than linear. In contrast, theAho–Corasick algorithmcan find all matches of multiple patterns in worst-case time and space linear in the input length and the number of matches (instead of the total length of the matches). A practical application of the algorithm isdetecting plagiarism. Given source material, the algorithm can rapidly search through a paper for instances of sentences from the source material, ignoring details such as case and punctuation. Because of the abundance of the sought strings, single-string searching algorithms are impractical. A naive string matching algorithm compares the given pattern against all positions in the given text. Each comparison takes time proportional to the length of the pattern, and the number of positions is proportional to the length of the text. Therefore, the worst-case time for such a method is proportional to the product of the two lengths. In many practical cases, this time can be significantly reduced by cutting short the comparison at each position as soon as a mismatch is found, but this idea cannot guarantee any speedup. Several string-matching algorithms, including theKnuth–Morris–Pratt algorithmand theBoyer–Moore string-search algorithm, reduce the worst-case time for string matching by extracting more information from each mismatch, allowing them to skip over positions of the text that are guaranteed not to match the pattern. The Rabin–Karp algorithm instead achieves its speedup by using ahash functionto quickly perform an approximate check for each position, and then only performing an exact comparison at the positions that pass this approximate check. A hash function is a function which converts every string into a numeric value, called itshash value; for example, we might havehash("hello")=5. If two strings are equal, their hash values are also equal. For a well-designed hash function, the inverse is true, in an approximate sense: strings that are unequal are very unlikely to have equal hash values. The Rabin–Karp algorithm proceeds by computing, at each position of the text, the hash value of a string starting at that position with the same length as the pattern. If this hash value equals the hash value of the pattern, it performs a full comparison at that position. In order for this to work well, the hash function should be selected randomly from a family of hash functions that are unlikely to produce manyfalse positives, that is, positions of the text which have the same hash value as the pattern but do not actually match the pattern. These positions contribute to the running time of the algorithm unnecessarily, without producing a match. Additionally, the hash function used should be arolling hash, a hash function whose value can be quickly updated from each position of the text to the next. Recomputing the hash function from scratch at each position would be too slow. The algorithm is as shown: Lines 2, 4, and 6 each requireO(m) time. However, line 2 is only executed once, and line 6 is only executed if the hash values match, which is unlikely to happen more than a few times. Line 5 is executed O(n) times, but each comparison only requires constant time, so its impact is O(n). The issue is line 4. Naively computing the hash value for the substrings[i+1..i+m]requires O(m) time because each character is examined. Since the hash computation is done on each loop, the algorithm with a naive hash computation requires O(mn) time, the same complexity as a straightforward string matching algorithm. For speed, the hash must be computed in constant time. The trick is the variablehsalready contains the previous hash value ofs[i..i+m-1]. If that value can be used to compute the next hash value in constant time, then computing successive hash values will be fast. The trick can be exploited using arolling hash. A rolling hash is a hash function specially designed to enable this operation. A trivial (but not very good) rolling hash function just adds the values of each character in the substring. This rolling hash formula can compute the next hash value from the previous value in constant time: This simple function works, but will result in statement 5 being executed more often than other more sophisticated rolling hash functions such as those discussed in the next section. Good performance requires a good hashing function for the encountered data. If the hashing is poor (such as producing the same hash value for every input), then line 6 would be executed O(n) times (i.e. on every iteration of the loop). Because character-by-character comparison of strings with lengthmtakes O(m) time, the whole algorithm then takes a worst-case O(mn) time. The key to the Rabin–Karp algorithm's performance is the efficient computation ofhash valuesof the successive substrings of the text. TheRabin fingerprintis a popular and effective rolling hash function. The hash function described here is not a Rabin fingerprint, but it works equally well. It treats every substring as a number in some base, the base being usually the size of the character set. For example, if the substring is "hi", the base is 256, and prime modulus is 101, then the hash value would be Technically, this algorithm is only similar to the true number in a non-decimal system representation, since for example we could have the "base" less than one of the "digits". Seehash functionfor a much more detailed discussion. The essential benefit achieved by using arolling hashsuch as the Rabin fingerprint is that it is possible to compute the hash value of the next substring from the previous one by doing only a constant number of operations, independent of the substrings' lengths. For example, if we have text "abracadabra" and we are searching for a pattern of length 3, the hash of the first substring, "abr", using 256 as the base, and 101 as the prime modulus is: We can then compute the hash of the next substring, "bra", from the hash of "abr" by subtracting the number added for the first 'a' of "abr", i.e. 97 × 2562, multiplying by the base and adding for the last a of "bra", i.e. 97 × 2560. Like so: If we are matching the search string "bra", using similar calculation of hash("abr"), If the substrings in question are long, this algorithm achieves great savings compared with many other hashing schemes. Theoretically, there exist other algorithms that could provide convenient recomputation, e.g. multiplying together ASCII values of all characters so that shifting substring would only entail dividing the previous hash by the first character value, then multiplying by the new last character's value. The limitation, however, is the limited size of the integerdata typeand the necessity of usingmodular arithmeticto scale down the hash results.[e]Meanwhile, naive hash functions do not produce large numbers quickly, but, just like adding ASCII values, are likely to cause manyhash collisionsand hence slow down the algorithm. Hence the described hash function is typically the preferred one in the Rabin–Karp algorithm. The Rabin–Karp algorithm is inferior for single pattern searching toKnuth–Morris–Pratt algorithm,Boyer–Moore string-search algorithmand other faster single patternstring searching algorithmsbecause of its slow worst case behavior. However, it is a useful algorithm formultiple pattern search. To find any of a large number, sayk, fixed length patterns in a text, a simple variant of the Rabin–Karp algorithm uses aBloom filteror aset data structureto check whether the hash of a given string belongs to a set of hash values of patterns we are looking for: We assume all the substrings have a fixed lengthm. A naïve way to search forkpatterns is to repeat a single-pattern search taking O(n+m) time, totaling in O((n+m)k) time. In contrast, the above algorithm can find allkpatterns in O(n+km) expected time, assuming that a hash table check works in O(1) expected time.	https://en.wikipedia.org/wiki/Rabin%E2%80%93Karp_string_search_algorithm
Incomputer science, asearch data structure[citation needed]is anydata structurethat allows the efficientretrievalof specific items from asetof items, such as a specificrecordfrom adatabase. The simplest, most general, and least efficient search structure is merely an unordered sequentiallistof all the items. Locating the desired item in such a list, by thelinear searchmethod, inevitably requires a number of operations proportional to the numbernof items, in theworst caseas well as in theaverage case. Useful search data structures allow faster retrieval; however, they are limited to queries of some specific kind. Moreover, since the cost of building such structures is at least proportional ton, they only pay off if several queries are to be performed on the same database (or on a database that changes little between queries). Staticsearch structures are designed for answering manyquerieson a fixed database;dynamicstructures also allow insertion, deletion, ormodificationof items between successive queries. In the dynamic case, one must also consider the cost of fixing the search structure to account for the changes in the database. The simplest kind of query is to locate a record that has a specific field (thekey) equal to a specified valuev. Other common kinds of query are "find the item with smallest (or largest) key value", "find the item with largest key value not exceedingv", "find all items with key values between specified boundsvminandvmax". In certain databases the key values may be points in somemulti-dimensional space. For example, the key may be a geographic position (latitudeandlongitude) on theEarth. In that case, common kinds of queries are "find the record with a key closest to a given pointv", or "find all items whose key lies at a given distance fromv", or "find all items within a specified regionRof the space". A common special case of the latter are simultaneous range queries on two or more simple keys, such as "find all employee records with salary between 50,000 and 100,000 and hired between 1995 and 2007". In this table, theasymptoticnotationO(f(n))means "not exceeding some fixed multiple off(n) in the worst case." Note: Insert on an unsorted array is sometimes quoted as beingO(n) due to the assumption that the element to be inserted must be inserted at one particular location of the array, which would require shifting all the subsequent elements by one position. However, in a classic array, the array is used to store arbitrary unsorted elements, and hence the exact position of any given element is of no consequence, and insert is carried out by increasing the array size by 1 and storing the element at the end of the array, which is aO(1) operation.[3][4]Likewise, the deletion operation is sometimes quoted as beingO(n) due to the assumption that subsequent elements must be shifted, but in a classic unsorted array the order is unimportant (though elements are implicitly ordered by insert-time), so deletion can be carried out by swapping the element to be deleted with the last element in the array and then decrementing the array size by 1, which is aO(1) operation.[5] This table is only an approximate summary; for each data structure there are special situations and variants that may lead to different costs. Also two or more data structures can be combined to obtain lower costs.	https://en.wikipedia.org/wiki/Search_data_structure
Incomputer science,consistent hashing[1][2]is a special kind ofhashingtechnique such that when ahash tableis resized, onlyn/m{\displaystyle n/m}keys need to be remapped on average wheren{\displaystyle n}is the number of keys andm{\displaystyle m}is the number of slots. In contrast, in most traditional hash tables, a change in the number of array slots causes nearly all keys to be remapped because the mapping between the keys and the slots is defined by amodular operation. Consistent hashing evenly distributes cache keys acrossshards, even if some of the shards crash or become unavailable.[3] The term "consistent hashing" was introduced byDavid Kargeret al.atMITfor use indistributed caching, particularly for theweb.[4]This academic paper from 1997 inSymposium on Theory of Computingintroduced the term "consistent hashing" as a way of distributing requests among a changing population of web servers.[5]Each slot is then represented by a server in a distributed system or cluster. The addition of a server and the removal of a server (during scalability or outage) requires onlynum_keys/num_slots{\displaystyle num\_keys/num\_slots}items to be re-shuffled when the number of slots (i.e. servers) change. The authors mentionlinear hashingand its ability to handle sequential server addition and removal, while consistent hashing allows servers to be added and removed in an arbitrary order.[1]The paper was later re-purposed to address technical challenge of keeping track of a file inpeer-to-peer networkssuch as adistributed hash table.[6][7] Teradataused this technique in their distributed database[citation needed], released in 1986, although they did not use this term. Teradata still uses the concept of ahash tableto fulfill exactly this purpose.Akamai Technologieswas founded in 1998 by the scientistsDaniel LewinandF. Thomson Leighton(co-authors of the article coining "consistent hashing"). In Akamai's content delivery network,[8]consistent hashing is used to balance the load within a cluster of servers, while astable marriagealgorithm is used to balance load across clusters.[2] Consistent hashing has also been used to reduce the impact of partial system failures in large web applications to provide robust caching without incurring the system-wide fallout of a failure.[9]Consistent hashing is also the cornerstone ofdistributed hash tables(DHTs), which employ hash values to partition a keyspace across a distributed set of nodes, then construct an overlay network of connected nodes that provide efficient node retrieval by key. Rendezvous hashing, designed in 1996, is a simpler and more general technique[citation needed]. It achieves the goals of consistent hashing using the very different highest random weight (HRW) algorithm. In the problem ofload balancing, for example, when aBLOBhas to be assigned to one ofn{\displaystyle n}servers on acluster, a standard hash function could be used in such a way that we calculate the hash value for that BLOB, assuming the resultant value of the hash isβ{\displaystyle \beta }, we performmodular operationwith the number of servers (n{\displaystyle n}in this case) to determine the server in which we can place the BLOB:ζ=β%n{\displaystyle \zeta =\beta \ \%\ n}; hence the BLOB will be placed in the server whoseserver ID{\displaystyle {\text{server ID}}}is successor ofζ{\displaystyle \zeta }in this case. However, when a server is added or removed during outage or scaling (whenn{\displaystyle n}changes), all the BLOBs in every server should be reassigned and moved due torehashing, but this operation is expensive. Consistent hashing was designed to avoid the problem of having to reassign every BLOB when a server is added or removed throughout the cluster. The central idea is to use a hash function that maps both the BLOB and servers to a unit circle, usually2π{\displaystyle 2\pi }radians. For example,ζ=Φ%360{\displaystyle \zeta =\Phi \ \%\ 360}(whereΦ{\displaystyle \Phi }is hash of a BLOB or server's identifier, likeIP addressorUUID). Each BLOB is then assigned to the next server that appears on the circle in clockwise order. Usually,binary search algorithmorlinear searchis used to find a "spot" or server to place that particular BLOB inO(log⁡N){\displaystyle O(\log N)}orO(N){\displaystyle O(N)}complexities respectively; and in every iteration, which happens in clockwise manner, an operationζ≤Ψ{\displaystyle \zeta \ \leq \ \Psi }(whereΨ{\displaystyle \Psi }is the value of the server within the cluster) is performed to find the server to place the BLOB. This provides an even distribution of BLOBs to servers. But, more importantly, if a server fails and is removed from the circle, only the BLOBs that were mapped to the failed server need to be reassigned to the next server in clockwise order. Likewise, if a new server is added, it is added to the unit circle, and only the BLOBs mapped to that server need to be reassigned. Importantly, when a server is added or removed, the vast majority of the BLOBs maintain their prior server assignments, and the addition ofnth{\displaystyle n^{th}}server only causes1/n{\displaystyle 1/n}fraction of the BLOBs to relocate. Although the process of moving BLOBs across cache servers in the cluster depends on the context, commonly, the newly added cache server identifies its "predecessor" and moves all the BLOBs, whose mapping belongs to this server (i.e. whose hash value is less than that of the new server), from it. However, in the case ofweb page caches, in most implementations there is no involvement of moving or copying, assuming the cached BLOB is small enough. When a request hits a newly added cache server, acache misshappens and a request to the actualweb serveris made and the BLOB is cached locally for future requests. The redundant BLOBs on the previously used cache servers would be removed as per thecache eviction policies.[10] Lethb(x){\displaystyle h_{b}(x)}andhs(x){\displaystyle h_{s}(x)}be the hash functions used for the BLOB and server's unique identifier respectively. In practice, abinary search tree(BST) is used to dynamically maintain theserver ID{\displaystyle {\text{server ID}}}within a cluster or hashring, and to find the successor or minimum within the BST,tree traversalis used. To avoidskewnessof multiple nodes within the radian, which happen due to lack ofuniform distributionof the servers within the cluster, multiple labels are used. Those duplicate labels are called "virtual nodes" i.e. multiple labels which point to a single "real" label or server within the cluster. The amount of virtual nodes or duplicate labels used for a particular server within a cluster is called the "weight" of that particular server.[14] A number of extensions to the basic technique are needed for effectively using consistent hashing for load balancing in practice. In the basic scheme above, if a server fails, all its BLOBs are reassigned to the next server in clockwise order, potentially doubling the load of that server. This may not be desirable. To ensure a more even redistribution of BLOBs on server failure, each server can be hashed to multiple locations on the unit circle. When a server fails, the BLOBs assigned to each of its replicas on the unit circle will get reassigned to a different server in clockwise order, thus redistributing the BLOBs more evenly. Another extension concerns a situation where a single BLOB gets "hot" and is accessed a large number of times and will have to be hosted in multiple servers. In this situation, the BLOB may be assigned to multiple contiguous servers by traversing the unit circle in clockwise order. A more complex practical consideration arises when two BLOBs are hashed near each other in the unit circle and both get "hot" at the same time. In this case, both BLOBs will use the same set of contiguous servers in the unit circle. This situation can be ameliorated by each BLOB choosing a different hash function for mapping servers to the unit circle.[2] Rendezvous hashing, designed in 1996, is a simpler and more general technique, and permits fully distributed agreement on a set ofk{\displaystyle k}options out of a possible set ofn{\displaystyle n}options.It can in fact be shownthat consistent hashing is a special case of rendezvous hashing. Because of its simplicity and generality, rendezvous hashing is now being used in place of Consistent Hashing in many applications. If key values will always increasemonotonically, an alternative approach using ahash table with monotonic keysmay be more suitable than consistent hashing.[citation needed] TheO(K/N){\displaystyle O(K/N)}is an average cost for redistribution of keys and theO(log⁡N){\displaystyle O(\log N)}complexity for consistent hashing comes from the fact that abinary searchamong nodes angles is required to find the next node on the ring.[citation needed] Known examples of consistent hashing use include:	https://en.wikipedia.org/wiki/Stable_hashing
Incomputer science, asuccinct data structureis adata structurewhich uses an amount of space that is "close" to theinformation-theoreticlower bound, but (unlike other compressed representations) still allows for efficient query operations. The concept was originally introduced by Jacobson[1]to encodebit vectors, (unlabeled)trees, andplanar graphs. Unlike generallossless data compressionalgorithms, succinct data structures retain the ability to use them in-place, without decompressing them first. A related notion is that of acompressed data structure, insofar as the size of the stored or encoded data similarly depends upon the specific content of the data itself. Suppose thatZ{\displaystyle Z}is the information-theoretical optimal number of bits needed to store some data. A representation of this data is called: For example, a data structure that uses2Z{\displaystyle 2Z}bits of storage is compact,Z+Z{\displaystyle Z+{\sqrt {Z}}}bits is succinct,Z+lg⁡Z{\displaystyle Z+\lg Z}bits is also succinct, andZ+3{\displaystyle Z+3}bits is implicit. Implicit structures are thus usually reduced to storing information using somepermutationof the input data; the most well-known example of this is theheap. Succinct indexable dictionaries, also calledrank/selectdictionaries, form the basis of a number of succinct representation techniques, includingbinary trees,k{\displaystyle k}-ary trees andmultisets,[2]as well assuffix treesandarrays.[3]The basic problem is to store a subsetS{\displaystyle S}of a universeU=[0…n)={0,1,…,n−1}{\displaystyle U=[0\dots n)=\{0,1,\dots ,n-1\}}, usually represented as a bit arrayB[0…n){\displaystyle B[0\dots n)}whereB[i]=1{\displaystyle B[i]=1}iffi∈S.{\displaystyle i\in S.}An indexable dictionary supports the usual methods on dictionaries (queries, and insertions/deletions in the dynamic case) as well as the following operations: forq∈{0,1}{\displaystyle q\in \{0,1\}}. In other words,rankq(x){\displaystyle \mathbf {rank} _{q}(x)}returns the number of elements equal toq{\displaystyle q}up to positionx{\displaystyle x}whileselectq(x){\displaystyle \mathbf {select} _{q}(x)}returns the position of thex{\displaystyle x}-th occurrence ofq{\displaystyle q}. There is a simple representation[4]which usesn+o(n){\displaystyle n+o(n)}bits of storage space (the original bit array and ano(n){\displaystyle o(n)}auxiliary structure) and supportsrankandselectin constant time. It uses an idea similar to that forrange-minimum queries; there are a constant number of recursions before stopping at a subproblem of a limited size. The bit arrayB{\displaystyle B}is partitioned intolarge blocksof sizel=lg2⁡n{\displaystyle l=\lg ^{2}n}bits andsmall blocksof sizes=lg⁡n/2{\displaystyle s=\lg n/2}bits. For each large block, the rank of its first bit is stored in a separate tableRl[0…n/l){\displaystyle R_{l}[0\dots n/l)}; each such entry takeslg⁡n{\displaystyle \lg n}bits for a total of(n/l)lg⁡n=n/lg⁡n{\displaystyle (n/l)\lg n=n/\lg n}bits of storage. Within a large block, another directoryRs[0…l/s){\displaystyle R_{s}[0\dots l/s)}stores the rank of each of thel/s=2lg⁡n{\displaystyle l/s=2\lg n}small blocks it contains. The difference here is that it only needslg⁡l=lg⁡lg2⁡n=2lg⁡lg⁡n{\displaystyle \lg l=\lg \lg ^{2}n=2\lg \lg n}bits for each entry, since only the differences from the rank of the first bit in the containing large block need to be stored. Thus, this table takes a total of(n/s)lg⁡l=4nlg⁡lg⁡n/lg⁡n{\displaystyle (n/s)\lg l=4n\lg \lg n/\lg n}bits. A lookup tableRp{\displaystyle R_{p}}can then be used that stores the answer to every possible rank query on a bit string of lengths{\displaystyle s}fori∈[0,s){\displaystyle i\in [0,s)}; this requires2sslg⁡s=O(nlg⁡nlg⁡lg⁡n){\displaystyle 2^{s}s\lg s=O({\sqrt {n}}\lg n\lg \lg n)}bits of storage space. Thus, since each of these auxiliary tables takeo(n){\displaystyle o(n)}space, this data structure supports rank queries inO(1){\displaystyle O(1)}time andn+o(n){\displaystyle n+o(n)}bits of space. To answer a query forrank1(x){\displaystyle \mathbf {rank} _{1}(x)}in constant time, a constant time algorithm computes: In practice, the lookup tableRp{\displaystyle R_{p}}can be replaced by bitwise operations and smaller tables that can be used to find the number of bits set in the small blocks. This is often beneficial, since succinct data structures find their uses in large data sets, in which case cache misses become much more frequent and the chances of the lookup table being evicted from closer CPU caches becomes higher.[5]Select queries can be easily supported by doing a binary search on the same auxiliary structure used forrank; however, this takesO(lg⁡n){\displaystyle O(\lg n)}time in the worst case. A more complicated structure using3n/lg⁡lg⁡n+O(nlg⁡nlg⁡lg⁡n)=o(n){\displaystyle 3n/\lg \lg n+O({\sqrt {n}}\lg n\lg \lg n)=o(n)}bits of additional storage can be used to supportselectin constant time.[6]In practice, many of these solutions have hidden constants in theO(⋅){\displaystyle O(\cdot )}notation which dominate before any asymptotic advantage becomes apparent; implementations using broadword operations and word-aligned blocks often perform better in practice.[7] Then+o(n){\displaystyle n+o(n)}space approach can be improved by noting that there are(nm){\displaystyle \textstyle {\binom {n}{m}}}distinctm{\displaystyle m}-subsets of[n){\displaystyle [n)}(or binary strings of lengthn{\displaystyle n}with exactlym{\displaystyle m}1’s), and thusB(m,n)=⌈lg⁡(nm)⌉{\displaystyle \textstyle {\mathcal {B}}(m,n)=\lceil \lg {\binom {n}{m}}\rceil }is an information theoretic lower bound on the number of bits needed to storeB{\displaystyle B}. There is a succinct (static) dictionary which attains this bound, namely usingB(m,n)+o(B(m,n)){\displaystyle {\mathcal {B}}(m,n)+o({\mathcal {B}}(m,n))}space.[8]This structure can be extended to supportrankandselectqueries and takesB(m,n)+O(m+nlg⁡lg⁡n/lg⁡n){\displaystyle {\mathcal {B}}(m,n)+O(m+n\lg \lg n/\lg n)}space.[2]Correctrankqueries in this structure are however limited to elements contained in the set, analogous to how minimal perfect hashing functions work. This bound can be reduced to a space/time tradeoff by reducing the storage space of the dictionary toB(m,n)+O(ntt/lgt⁡n+n3/4){\displaystyle {\mathcal {B}}(m,n)+O(nt^{t}/\lg ^{t}n+n^{3/4})}with queries takingO(t){\displaystyle O(t)}time.[9] It is also possible to construct a indexible dictionary supporting rank (but not select) that uses fewer thanB(m,n){\displaystyle \textstyle {\mathcal {B}}(m,n)}bits. Such a dictionary is called amonotone minimal perfect hash function, and can be implemented using as few asO(mlog⁡log⁡log⁡n){\displaystyle O(m\log \log \log n)}bits.[10][11] A succinct hash table, also known as asuccinct unordered dictionary,is a data structure that storesm{\displaystyle m}keys from a universe{0,1,…,n−1}{\displaystyle \{0,1,\dots ,n-1\}}using space(1+o(1))B(m,n){\displaystyle (1+o(1)){\mathcal {B}}(m,n)}bits, and while supporting membership queries in constant expected time. If a succinct hash table also supports insertions and deletions in constant expected time, then it is referred to asdynamic, and otherwise it is referred to asstatic. The first dynamic succinct hash table was due to Raman and Rao in 2003.[12]In the case wheren=poly(m){\displaystyle n={\text{poly}}(m)}, their solution uses spaceB(m,n)+O(mlog⁡log⁡m){\displaystyle {\mathcal {B}}(m,n)+O(m\log \log m)}bits. Subsequently, it was shown that this space bound could be improved toB(m,n)+O(mlog⁡log⁡log⁡⋯log⁡m){\displaystyle {\mathcal {B}}(m,n)+O(m\log \log \log \cdots \log m)}bits for any constant number of logarithms[13]and a little after that this bound was also optimal.[14][15]The latter solution supports all operations in worst-case constant time with high probability. The first static succinct hash table was due to Pagh in 1999.[16][17]In the case wheren=poly(m){\displaystyle n={\text{poly}}(m)}, their solution uses spaceB(m,n)+O(m(log⁡log⁡m)2/log⁡m){\displaystyle {\mathcal {B}}(m,n)+O(m(\log \log m)^{2}/\log m)}bits, and supportsworst-caseconstant-time queries. This bound was subsequently improved toB(m,n)+m/polylog⁡m{\displaystyle {\mathcal {B}}(m,n)+m/{\text{poly}}\log m}bits,[18]and then toB(m,n)+polylog⁡m{\displaystyle {\mathcal {B}}(m,n)+{\text{poly}}\log m}bits.[19]Whereas the first two solutions[17][18]support worst-case constant-time queries, the final one supports constant expected-time queries.[19]The final solution also requires access to a lookup table of sizenϵ{\displaystyle n^{\epsilon }}, but this lookup table is independent of the set of elements being stored.[19] A string with an arbitrary length (Pascal string) takesZ+ log(Z) space, and is thus succinct. If there is a maximum length – which is the case in practice, since 232= 4 GiB of data is a very long string, and 264= 16 EiB of data is larger than any string in practice – then a string with a length is also implicit, takingZ+kspace, wherekis the number of data to represent the maximum length (e.g., 64 bits). When a sequence of variable-length items (such as strings) needs to be encoded, there are various possibilities. A direct approach is to store a length and an item in each record – these can then be placed one after another. This allows efficient next, but not finding thekth item. An alternative is to place the items in order with a delimiter (e.g.,null-terminated string). This uses a delimiter instead of a length, and is substantially slower, since the entire sequence must be scanned for delimiters. Both of these are space-efficient. An alternative approach is out-of-band separation: the items can simply be placed one after another, with no delimiters. Item bounds can then be stored as a sequence of length, or better, offsets into this sequence. Alternatively, a separate binary string consisting of 1s in the positions where an item begins, and 0s everywhere else is encoded along with it. Given this string, theselect{\displaystyle select}function can quickly determine where each item begins, given its index.[20]This iscompactbut notsuccinct,as it takes 2Zspace, which is O(Z). Another example is the representation of abinary tree: an arbitrary binary tree onn{\displaystyle n}nodes can be represented in2n+o(n){\displaystyle 2n+o(n)}bits while supporting a variety of operations on any node, which includes finding its parent, its left and right child, and returning the size of its subtree, each in constant time. The number of different binary trees onn{\displaystyle n}nodes is(2nn){\displaystyle {\tbinom {2n}{n}}}/(n+1){\displaystyle /(n+1)}. For largen{\displaystyle n}, this is about4n{\displaystyle 4^{n}}; thus we need at least aboutlog2⁡(4n)=2n{\displaystyle \log _{2}(4^{n})=2n}bits to encode it. A succinct binary tree therefore would occupy only2{\displaystyle 2}bits per node.	https://en.wikipedia.org/wiki/Succinct_hash_table
This article describes thecalling conventionsused when programmingx86architecturemicroprocessors. Calling conventions describe the interface of called code: This is intimately related with the assignment of sizes and formats to programming-language types. Another closely related topic isname mangling, which determines how symbol names in the code are mapped to symbol names used by the linker. Calling conventions, type representations, and name mangling are all part of what is known as anapplication binary interface(ABI). There are subtle differences in how various compilers implement these conventions, so it is often difficult to interface code which is compiled by different compilers. On the other hand, conventions which are used as an API standard (such as stdcall) are very uniformly implemented. ThestandardforIBM PC compatibleswas defined by theIntel processors(8086, 80386) and the literal hardware IBM shipped. Hardware extensions and allsoftware standards(save for aBIOScalling convention) were thrown open to market competition. A multitude of independent software firms offered operating systems, compilers for many programming languages, and applications. Many different calling schemes were implemented by the firms, often mutually exclusive, based on different requirements, historical practices, and programmer creativity. After the IBM compatible market shakeout,Microsoftoperating systems and programming tools (with differing conventions) predominated, while second-tier firms likeBorlandandNovell, and open-source projects likeGNU Compiler Collection(GCC), still maintained their own standards. Provisions forinteroperabilitybetween vendors and products were eventually adopted, simplifying the problem of choosing a viable convention.[1] In these types of calling conventions, the caller cleans the arguments from the stack (resets the state of the stack just as it was before the callee function was called). Thecdecl(which stands forC declaration) is a calling convention for the programming languageCand is used by many C compilers for thex86 architecture.[1]In cdecl, subroutine arguments are passed on thestack. If the return values are Integer values or memory addresses they are put into the EAXregisterby the callee, whereas floating point values are put in the ST0x87register. Registers EAX, ECX, and EDX are caller-saved, and the rest are callee-saved. Thex87floating point registers ST0 to ST7 must be empty (popped or freed) when calling a new function, and ST1 to ST7 must be empty on exiting a function. ST0 must also be empty when not used for returning a value. In the context of the language C, function arguments are pushed on the stack in the right-to-left (RTL) order, i.e. the last argument is pushed first. Consider the following C source code snippet: Onx86, it might produce the followingassembly code(Intel syntax): The caller cleans the stack after the function call returns. Thecdeclcalling convention is usually the default calling convention for x86 Ccompilers, although many compilers provide options to automatically change the calling conventions used. To manually define a function to be cdecl, some support the following syntax: There are some variations in the interpretation of cdecl. As a result, x86 programs compiled for different operating system platforms and/or by different compilers can be incompatible, even if they both use the "cdecl" convention and do not call out to the underlying environment. Some compilers return simple data structures with a length of 2 registers or less in the register pair EAX:EDX and larger structures and class objects requiring special treatment by the exception handler (e.g., a defined constructor, destructor, or assignment) are returned in memory. To pass "in memory", the caller allocates memory and passes a pointer to it as a hidden first parameter; the callee populates the memory and returns the pointer, popping the hidden pointer when returning.[2] InLinux,GCCsets thede factostandard for calling conventions. Since GCC version 4.5, the stack must be aligned to a 16-byte boundary when calling a function (prior versions only required a 4-byte alignment).[1][3] A version ofcdeclis described in System V ABI for i386 systems.[4] This is similar to cdecl in that arguments are pushed right-to-left. However, EAX, ECX, and EDX are not preserved, and the size of the parameter list in doublewords is passed in AL. Syscall is the standard calling convention for 32 bitOS/2API. Arguments are pushed right-to-left. The three first (leftmost) arguments are passed in EAX, EDX, and ECX and up to four floating-point arguments are passed in ST0 through ST3, although space for them is reserved in the argument list on the stack. Results are returned in EAX or ST0. Registers EBP, EBX, ESI, and EDI are preserved. Optlink is used by theIBM VisualAgecompilers. In these conventions, the callee cleans up the arguments from the stack. Functions which use these conventions are easy to recognize in ASM code because they willunwind the stackafter returning. The x86retinstruction allows an optional16-bitparameter that specifies the number of stack bytes to release after returning to the caller. Such code looks like this: Conventions namedfastcallorregisterhave not been standardized, and have been implemented differently, depending on the compiler vendor.[1]Typically register based calling conventions pass one or more arguments in registers which reduces the number of memory accesses required for the call and, thus, usually make them faster. Based on theBorlandTurbo Pascallanguage's calling convention, the parameters are pushed on the stack in left-to-right (LTR) order (opposite of cdecl), and the callee is responsible for removing them from the stack. Returning the result works as follows: This calling convention was common in the following 16-bit APIs:OS/21.x,Microsoft Windows3.x, andBorlandDelphiversion 1.x. Modern versions of the Windows API usestdcall, which still has the callee restoring the stack as in the Pascal convention, but the parameters are now pushed right to left. The stdcall[5]calling convention is a variation on the Pascal calling convention in which the callee is responsible for cleaning up the stack, but the parameters are pushed onto the stack in right-to-left order, as in the _cdecl calling convention. Registers EAX, ECX, and EDX are designated for use within the function. Return values are stored in the EAX register. stdcall is the standard calling convention for the MicrosoftWin32APIand forOpen Watcom C++. Microsoft__fastcallconvention (aka__msfastcall[citation needed]) passes the first two arguments (evaluated left to right) that fit, into ECX and EDX.[6]Remaining arguments are pushed onto the stack from right to left. When the compiler compiles forIA64orAMD64, it ignores the__fastcallkeyword (or any other calling convention keyword aside from__vectorcall) and usesthe Microsoft default64-bitcalling convention instead. Other compilers likeGCC,[7]Clang,[8]andICC[citation needed]provide similar "fastcall" calling conventions, although they are not necessarily compatible with each other or with Microsoft fastcall.[9] Consider the following C snippet: x86 decompilation of the main function will look like (in Intel syntax): The first two arguments are passed in the left to right order, and the third argument is pushed on the stack. There is no stack cleanup, as stack cleanup is performed by the callee. The disassembly of the callee function is: As the two arguments were passed through the registers and only one parameter was pushed in the stack, the pushed value is being cleared by the retn instruction, as int is 4 bytes in size in x86 systems. InVisual Studio2013, Microsoft introduced the__vectorcallcalling convention in response to efficiency concerns from game, graphic, video/audio, and codec developers. The scheme allows for larger vector types (float,double,__m128,__m256) to be passed in registers as opposed to on the stack.[10] For IA-32 and x64 code,__vectorcallis similar to__fastcalland theoriginal x64calling conventions respectively, but extends them to support passing vector arguments usingSIMDregisters. In IA-32, the integer values are passed as usual, and the first six SIMD (XMM/YMM0-5) registers hold up to six floating-point, vector, or HVA values sequentially from left to right, regardless of actual positions caused by, e.g. an int argument appearing between them. In x64, however, the rule from the original x64 convention still apply, so that XMM/YMM0-5 only hold floating-point, vector, or HVA arguments when they happen to be the first through the sixth.[11] __vectorcalladds support for passing homogeneous vector aggregate (HVA) values, which are composite types (structs) consisting solely of up to four identical vector types, using the same six registers. Once the registers have been allocated for vector type arguments, the unused registers are allocated to HVA arguments from left to right. The positioning rules still apply. Resulting vector type and HVA values are returned using the first four XMM/YMM registers.[11] The Clang compiler and the Intel C++ Compiler also implement vectorcall.[12]ICC has a similar, earlier convention called__regcall;[13]it is also supported by Clang.[14] Evaluating arguments from left to right, it passes three arguments via EAX, EDX, ECX. Remaining arguments are pushed onto the stack, also left to right.[15]It is the default calling convention of the 32-bit compiler ofDelphi, where it is known asregister. This calling convention is also used by Embarcadero's C++Builder, where it is called__fastcall.[16]In this compiler,Microsoft'sfastcallcan be used as__msfastcall.[17] GCC and Clang can be made to use a similar calling convention by using__stdcallwith theregparmfunction attribute or the-mregparm=3switch. (The stack order is inverted.) It is also possible to produce a caller clean-up variant usingcdeclor extend this to also use SSE registers.[18]Acdecl-based version is used by the Linux kernel on i386 since version 2.6.20 (released February 2007).[19] Watcomdoes not support the__fastcallkeyword except to alias it to null. The register calling convention may be selected by command line switch. Up to 4 registers are assigned to arguments in the order EAX, EDX, EBX, ECX. Arguments are assigned to registers from left to right. If any argument cannot be assigned to a register (say it is too large) it, and all subsequent arguments, are assigned to the stack. Arguments assigned to the stack are pushed from right to left. Names are mangled by adding a suffixed underscore. Variadic functions fall back to the Watcom stack based calling convention. The Watcom C/C++ compiler also uses the#pragma aux[20]directive that allows the user to specify their own calling convention. As its manual states, "Very few users are likely to need this method, but if it is needed, it can be a lifesaver". The first four integer parameters are passed in registers eax, ebx, ecx and edx. Floating point parameters are passed on the floating point stack – registers st0, st1, st2, st3, st4, st5 and st6. Structure parameters are always passed on the stack. Added parameters are passed on the stack after registers are exhausted. Integer values are returned in eax, pointers in edx and floating point types in st0. InDelphiandFree PascalonMicrosoft Windows, the safecall calling convention encapsulates COM (Component Object Model) error handling, thus exceptions aren't leaked out to the caller, but are reported in theHRESULTreturn value, as required by COM/OLE. When calling a safecall function from Delphi code, Delphi also automatically checks the returned HRESULT and raises an exception if needed. The safecall calling convention is the same as the stdcall calling convention, except that exceptions are passed back to the caller in EAX as a HResult (instead of in FS:[0]), while the function result is passed by reference on the stack as though it were a final "out" parameter. When calling a Delphi function from Delphi this calling convention will appear just like any other calling convention, because although exceptions are passed back in EAX, they are automatically converted back to proper exceptions by the caller. When using COM objects created in other languages, the HResults will be automatically raised as exceptions, and the result for Get functions is in the result rather than a parameter. When creating COM objects in Delphi with safecall, there is no need to worry about HResults, as exceptions can be raised as normal but will be seen as HResults in other languages. Returns a result and raises exceptions like a normal Delphi function, but it passes values and exceptions as though it was: This calling convention is used for calling C++ non-static member functions. There are two primary versions ofthiscallused depending on the compiler and whether or not the function uses a variable number of arguments. For the GCC compiler,thiscallis almost identical tocdecl: The caller cleans the stack, and the parameters are passed in right-to-left order. The difference is the addition of thethispointer, which is pushed onto the stack last, as if it were the first parameter in the function prototype. On the Microsoft Visual C++ compiler, thethispointer is passed in ECX and it is thecalleethat cleans the stack, mirroring thestdcallconvention used in C for this compiler and in Windows API functions. When functions use a variable number of arguments, it is the caller that cleans the stack (cf.cdecl). Thethiscallcalling convention can only be explicitly specified on Microsoft Visual C++ 2005 and later. On any other compilerthiscallis not a keyword. (However, disassemblers, such asIDA, must specify it. So IDA uses keyword__thiscallfor this.) Another part of a calling convention is which registers are guaranteed to retain their values after a subroutine call. This behavior is known as register preservation. According to the Intel ABI to which the vast majority of compilers conform, the EAX, EDX, and ECX are to be free for use within a procedure or function, and need not be preserved.[citation needed] As the name implies, these general-purpose registers usually hold temporary (volatile) information, that can be overwritten by any subroutine. Therefore, it is the caller's responsibility to push each of these registers onto the stack, if it would like to restore their values after a subroutine call. The other registers are used to hold long-lived values (non-volatile), that should be preserved across calls. In other words, when the caller makes a procedure call, it can expect that those registers will hold the same value after the callee returns. Thus, making it the callee's responsibility to both save (push at the start) and restore (pop accordingly) them before returning to the caller. As in the prior case, this practice should only be done on registers that the callee changes. x86-64 calling conventions take advantage of the added register space to pass more arguments in registers. Also, the number of incompatible calling conventions has been reduced. There are two in common use. The Microsoft x64 calling convention[21][22]is followed onWindowsand pre-bootUEFI(forlong modeonx86-64). The first four arguments are placed onto the registers. That means RCX, RDX, R8, R9 (in that order) for integer, struct or pointer arguments, and XMM0, XMM1, XMM2, XMM3 for floating point arguments. Added arguments are pushed onto the stack (right to left). Integer return values (similar to x86) are returned in RAX if 64 bits or less. Floating point return values are returned in XMM0. Parameters less than 64 bits long are not zero extended; the high bits are not zeroed. Structs and unions with sizes that match integers are passed and returned as if they were integers. Otherwise they are replaced with a pointer when used as an argument. When a return of an oversized struct is needed, another pointer to a caller-provided space is prepended as the first argument, shifting all other arguments to the right by one place.[23] When compiling for the x64 architecture in a Windows context (whether using Microsoft or non-Microsoft tools), stdcall, thiscall, cdecl, and fastcall all resolve to using this convention. In the Microsoft x64 calling convention, it is the caller's responsibility to allocate 32 bytes of "shadow space" on the stack right before calling the function (regardless of the actual number of parameters used), and to pop the stack after the call. The shadow space is used to spill RCX, RDX, R8, and R9,[24]but must be made available to all functions, even those with fewer than four parameters. The registers RAX, RCX, RDX, R8, R9, R10, R11 are considered volatile (caller-saved).[25] The registers RBX, RBP, RDI, RSI, RSP, R12, R13, R14, and R15 are considered nonvolatile (callee-saved).[25] For example, a function taking 5 integer arguments will take the first to fourth in registers, and the fifth will be pushed on top of the shadow space. So when the called function is entered, the stack will be composed of (in ascending order) the return address, followed by the shadow space (32 bytes) followed by the fifth parameter. Inx86-64, Visual Studio 2008 stores floating point numbers in XMM6 and XMM7 (as well as XMM8 through XMM15); consequently, forx86-64, user-written assembly language routines must preserve XMM6 and XMM7 (as compared tox86wherein user-written assembly language routines did not need to preserve XMM6 and XMM7). In other words, user-written assembly language routines must be updated to save/restore XMM6 and XMM7 before/after the function when being ported fromx86tox86-64. Starting with Visual Studio 2013, Microsoft introduced the__vectorcallcalling convention which extends the x64 convention. The calling convention of theSystem VAMD64ABIis followed onSolaris,Linux,FreeBSD,macOS,[26]and is the de facto standard among Unix and Unix-like operating systems. TheOpenVMSCalling Standard on x86-64 is based on the System V ABI with some extensions needed for backwards compatibility.[27]The first six integer or pointer arguments are passed in registers RDI, RSI, RDX, RCX, R8, R9 (R10 is used as a static chain pointer in case of nested functions[28]: 21), while XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6 and XMM7 are used for the first floating point arguments.[28]: 22As in the Microsoft x64 calling convention, added arguments are passed on the stack.[28]: 22Integer return values up to 64 bits in size are stored in RAX while values up to 128 bit are stored in RAX and RDX. Floating-point return values are similarly stored in XMM0 and XMM1.[28]: 25The wider YMM and ZMM registers are used for passing and returning wider values in place of XMM when they exist.[28]: 26, 55 Struct and union parameters with sizes of two (eight in case of only SSE fields) pointers or fewer that are aligned on 64-bit boundaries are decomposed into "eightbytes" and each one is classified and passed as a separate parameter.[28]: 24Otherwise they are replaced with a pointer when used as an argument. Struct and union return types with sizes of two pointers or fewer are returned in RAX and RDX (or XMM0 and XMM1). When an oversized struct return is needed, another pointer to a caller-provided space is prepended as the first argument, shifting all other arguments to the right by one place, and the value of this pointer is returned in RAX.[28]: 27 If the callee wishes to use registers RBX, RSP, RBP, and R12–R15, it must restore their original values before returning control to the caller. All other registers must be saved by the caller if it wishes to preserve their values.[28]: 16 For leaf-node functions (functions which do not call any other function(s)), a 128-byte space is stored just beneath the stack pointer of the function. The space is called thered zone. This zone will not be overwritten by any signal or interrupt handlers. Compilers can thus use this zone to save local variables. Compilers may omit some instructions at the starting of the function (adjustment of RSP, RBP) by using this zone. However, other functions may overwrite this zone. Therefore, this zone should only be used for leaf-node functions.gccandclangoffer the-mno-red-zoneflag to disable red-zone optimizations. If the callee is avariadic function, then the number of floating point arguments passed to the function in vector registers must be provided by the caller in the AL register.[28]: 55 Unlike the Microsoft calling convention, a shadow space is not provided; on function entry, the return address is adjacent to the seventh integer argument on the stack. This is a list of x86 calling conventions.[1]These are conventions primarily intended for C/C++ compilers (especially the 64-bit part below), and thus largely special cases. Other languages may use other formats and conventions in their implementations. Stack aligned on 16-byte boundary due to a bug. Stack aligned on 4-byte boundary.	https://en.wikipedia.org/wiki/X86_calling_conventions
Thex86instruction setrefers to the set of instructions thatx86-compatiblemicroprocessorssupport. The instructions are usually part of anexecutableprogram, often stored as acomputer fileand executed on the processor. The x86 instruction set has been extended several times, introducing widerregistersand datatypes as well as new functionality.[1] Below is the full8086/8088instruction set of Intel (81 instructions total).[2]These instructions are also available in 32-bit mode, in which they operate on 32-bit registers (eax,ebx, etc.) and values instead of their 16-bit (ax,bx, etc.) counterparts. The updated instruction set is grouped according to architecture (i186,i286,i386,i486,i586/i686) and is referred to as (32-bit)x86and (64-bit)x86-64(also known asAMD64). This is the original instruction set. In the 'Notes' column,rmeansregister,mmeansmemory addressandimmmeansimmediate(i.e. a value). Note that since the lower half is the same for unsigned and signed multiplication, this version of the instruction can be used for unsigned multiplication as well. The new instructions added in 80286 add support for x86protected mode. Some but not all of the instructions are available inreal modeas well. The TSS (Task State Segment) specified by the 16-bit argument is marked busy, but a task switch is not done. The 80386 added support for 32-bit operation to the x86 instruction set. This was done by widening the general-purpose registers to 32 bits and introducing the concepts ofOperandSizeandAddressSize– most instruction forms that would previously take 16-bit data arguments were given the ability to take 32-bit arguments by setting their OperandSize to 32 bits, and instructions that could take 16-bit address arguments were given the ability to take 32-bit address arguments by setting their AddressSize to 32 bits. (Instruction forms that work on 8-bit data continue to be 8-bit regardless of OperandSize. Using a data size of 16 bits will cause only the bottom 16 bits of the 32-bit general-purpose registers to be modified – the top 16 bits are left unchanged.) The default OperandSize and AddressSize to use for each instruction is given by the D bit of thesegment descriptorof the current code segment -D=0makes both 16-bit,D=1makes both 32-bit. Additionally, they can be overridden on a per-instruction basis with two new instruction prefixes that were introduced in the 80386: The 80386 also introduced the two new segment registersFSandGSas well as the x86control,debugandtest registers. The new instructions introduced in the 80386 can broadly be subdivided into two classes: For instruction forms where the operand size can be inferred from the instruction's arguments (e.g.ADD EAX,EBXcan be inferred to have a 32-bit OperandSize due to its use of EAX as an argument), new instruction mnemonics are not needed and not provided. Mainly used to prepare a dividend for the 32-bitIDIV(signed divide) instruction. Instruction is serializing. Second operand specifies which bit of the first operand to test. The bit to test is copied toEFLAGS.CF. Second operand specifies which bit of the first operand to test and set. Second operand specifies which bit of the first operand to test and clear. Second operand specifies which bit of the first operand to test and toggle. Differs from older variants of conditional jumps in that they accept a 16/32-bit offset rather than just an 8-bit offset. Offset part is stored in destination register argument, segment part in FS/GS/SS segment register as indicated by the instruction mnemonic.[i] Moves to theCR3control register are serializing and will flush theTLB.[l] On Pentium and later processors, moves to theCR0andCR4control registers are also serializing.[m] On Pentium and later processors, moves to the DR0-DR7 debug registers are serializing. Performs software interrupt #1 if executed when not using in-circuit emulation.[p] Performs same operation asMOVif executed when not doing in-circuit emulation.[q] UsingBSWAPwith a 16-bit register argument produces an undefined result.[a] Instruction atomic only if used withLOCKprefix. Instruction atomic only if used withLOCKprefix. Instruction is serializing. Integer/system instructions that were not present in the basic 80486 instruction set, but were added in various x86 processors prior to the introduction of SSE. (Discontinued instructionsare not included.) Instruction is, with some exceptions, serializing.[c] Instruction is serializing. Instruction is serializing, and causes a mandatory #VMEXIT under virtualization. Support forCPUIDcan be checked by toggling bit 21 ofEFLAGS(EFLAGS.ID) – if this bit can be toggled,CPUIDis present. Instruction atomic only if used withLOCKprefix.[k] In early processors, the TSC was a cycle counter, incrementing by 1 for each clock cycle (which could cause its rate to vary on processors that could change clock speed at runtime) – in later processors, it increments at a fixed rate that doesn't necessarily match the CPU clock speed.[n] Other than AMD K7/K8, broadly unsupported in non-Intel processors released before 2005.[v][60] These instructions are provided for software testing to explicitly generate invalid opcodes. The opcodes for these instructions are reserved for this purpose. WRMSRto the x2APIC ICR (Interrupt Command Register; MSR830h) is commonly used to produce an IPI (Inter-processor interrupt) - on Intel[40]but not AMD[41]CPUs, such an IPI can be reordered before an older memory store. For cases where there is a need to use more than 9 bytes of NOP padding, it is recommended to use multiple NOPs. These instructions can only be encoded in 64 bit mode. They fall in four groups: Most instructions with a 64 bit operand size encode this using aREX.Wprefix; in the absence of theREX.Wprefix, the corresponding instruction with 32 bit operand size is encoded. This mechanism also applies to most other instructions with 32 bit operand size. These are not listed here as they do not gain a new mnemonic in Intel syntax when used with a 64 bit operand size. Bit manipulation instructions. For all of theVEX-encodedinstructions defined by BMI1 and BMI2, the operand size may be 32 or 64 bits, controlled by the VEX.W bit – none of these instructions are available in 16-bit variants. The VEX-encoded instructions are not available in Real Mode and Virtual-8086 mode - other than that, the bit manipulation instructions are available in all operating modes on supported CPUs. Intel CET (Control-Flow Enforcement Technology) adds two distinct features to help protect against security exploits such asreturn-oriented programming: ashadow stack(CET_SS), andindirect branch tracking(CET_IBT). The XSAVE instruction set extensions are designed to save/restore CPU extended state (typically for the purpose ofcontext switching) in a manner that can be extended to cover new instruction set extensions without the OS context-switching code needing to understand the specifics of the new extensions. This is done by defining a series ofstate-components, each with a size and offset within a given save area, and each corresponding to a subset of the state needed for one CPU extension or another. TheEAX=0DhCPUIDleaf is used to provide information about which state-components the CPU supports and what their sizes/offsets are, so that the OS can reserve the proper amount of space and set the associated enable-bits. Instruction is serializing on AMD but not Intel CPUs. The C-states are processor-specific power states, which do not necessarily correspond 1:1 toACPI C-states. Any unsupported value in EAX causes an #UD exception. Any unsupported value in the register argument causes a #GP exception. Depending on function, the instruction may return data in RBX and/or an error code in EAX. Depending on function, the instruction may return data/status information in EAX and/or RCX. Instruction returns status information in EAX. If the instruction fails, it will set EFLAGS.ZF=1 and return an error code in EAX. If it is successful, it sets EFLAGS.ZF=0 and EAX=0. The register argument to theUMWAITandTPAUSEinstructions specifies extra flags to control the operation of the instruction.[q] PopsRIP,RFLAGSandRSPoff the stack, in that order.[u] Part of Intel DSA (Data Streaming AcceleratorArchitecture).[126] The instruction differs from the olderWRMSRinstruction in that it is not serializing. The instruction is not serializing. Part of Intel TSE (Total Storage Encryption), and available in 64-bit mode only. If the instruction fails, it will set EFLAGS.ZF=1 and return an error code in EAX. If it is successful, it sets EFLAGS.ZF=0 and EAX=0. Intel XED uses the mnemonicshint-takenandhint-not-takenfor these branch hints.[115] Any unsupported value in EAX causes a #GP exception. Any unsupported value in EAX causes a #GP exception.TheEENTERandERESUMEfunctions cannot be executed inside an SGX enclave – the other functions can only be executed inside an enclave. Any unsupported value in EAX causes a #GP exception.TheENCLVinstruction is only present on systems that support the EPC Oversubscription Extensions to SGX ("OVERSUB"). Any unsupported value in EAX causes a #GP(0) exception. The value of the MSR is returned in EDX:EAX. Unsupported values in ECX return 0. Thex87coprocessor, if present, provides support for floating-point arithmetic. The coprocessor provides eight data registers, each holding one 80-bit floating-point value (1 sign bit, 15 exponent bits, 64 mantissa bits) – these registers are organized as a stack, with the top-of-stack register referred to as "st" or "st(0)", and the other registers referred to as st(1), st(2), ...st(7). It additionally provides a number of control and status registers, including "PC" (precision control, to control whether floating-point operations should be rounded to 24, 53 or 64 mantissa bits) and "RC" (rounding control, to pick rounding-mode: round-to-zero, round-to-positive-infinity, round-to-negative-infinity, round-to-nearest-even) and a 4-bit condition code register "CC", whose four bits are individually referred to as C0, C1, C2 and C3). Not all of the arithmetic instructions provided by x87 obey PC and RC. C1 is set to the sign-bit of st(0), regardless of whether st(0) is Empty or not. x86 also includes discontinued instruction sets which are no longer supported by Intel and AMD, and undocumented instructions which execute but are not officially documented. The x86 CPUs containundocumented instructionswhich are implemented on the chips but not listed in some official documents. They can be found in various sources across the Internet, such asRalf Brown's Interrupt Listand atsandpile.org Some of these instructions are widely available across many/most x86 CPUs, while others are specific to a narrow range of CPUs. The actual operation isAH ← AL/imm8; AL ← AL mod imm8for any imm8 value (except zero, which produces a divide-by-zero exception).[143] The actual operation isAL ← (AL+(AH*imm8)) & 0FFh; AH ← 0for any imm8 value. Unavailable on some 80486 steppings.[146][147] Introduced in the Pentium Pro in 1995, but remained undocumented until March 2006.[61][158][159] Unavailable on AMD K6, AMD Geode LX, VIA Nehemiah.[161] On AMD CPUs,0F 0D /rwith a memory argument is documented asPREFETCH/PREFETCHWsince K6-2 – originally as part of 3Dnow!, but has been kept in later AMD CPUs even after the rest of 3Dnow! was dropped. Available on Intel CPUs since65 nmPentium 4. Microsoft Windows 95 Setup is known to depend on0F FFbeing invalid[165][166]– it is used as a self check to test that its #UD exception handler is working properly. Other invalid opcodes that are being relied on by commercial software to produce #UD exceptions includeFF FF(DIF-2,[167]LaserLok[168]) andC4 C4("BOP"[169][170]), however as of January 2022 they are not published as intentionally invalid opcodes. STOREALL In some implementations, emulated throughBIOSas ahaltingsequence.[173] Ina forum post at the Vintage Computing Federation, this instruction (withF1prefix) is explained asSAVEALL. It interacts with ICE mode. Opcode reused forSYSCALLin AMD K6 and later CPUs. Opcode reused forSYSRETin AMD K6 and later CPUs. Opcodes reused for SSE instructions in later CPUs. The NexGen Nx586 CPU uses "hyper code"[180](x86 code sequences unpacked at boot time and only accessible in a special "hyper mode" operation mode, similar to DEC Alpha'sPALcodeand Intel's XuCode[181]) for many complicated operations that are implemented with microcode in most other x86 CPUs. The Nx586 provides a large number of undocumented instructions to assist hyper mode operation. Instruction known to be recognized byMASM6.13 and 6.14. Opcode reused for documentedPSWAPDinstruction from AMD K7 onwards. 64 0F (80..8F) rel16/32 Segment prefixes on conditional branches are accepted but ignored by non-NetBurst CPUs. On at least AMD K6-2, all of the unassigned 3DNow! opcodes (other than the undocumentedPF2IW,PI2FWandPSWAPWinstructions) are reported to execute as equivalents ofPOR(MMX bitwise-OR instruction).[183] GP2MEM Supported by OpenSSL[191]as part of itsVIA PadLocksupport, and listed in a Zhaoxin-supplied Linux kernel patch,[192]but not documented by the VIA PadLock Programming Guide. Listed in a VIA-supplied patch to add support for VIA Nano-specific PadLock instructions to OpenSSL,[193]but not documented by the VIA PadLock Programming Guide. FENI8087_NOP Present on all Intel x87 FPUs from 80287 onwards. For FPUs other than the ones where they were introduced on (8087 forFENI/FDISIand 80287 forFSETPM), they act asNOPs. These instructions and their operation on modern CPUs are commonly mentioned in later Intel documentation, but with opcodes omitted and opcode table entries left blank (e.g.Intel SDM 325462-077, April 2022mentions them twice without opcodes). The opcodes are, however, recognized by Intel XED.[199] FDISI8087_NOP FSETPM287_NOP Their actual operation is not known, nor is it known whether their operation is the same on all of these CPUs.	https://en.wikipedia.org/wiki/X86_instruction_listings
TheMotorola 68000 series(also known as680x0,m68000,m68k, or68k) is a family of32-bitcomplex instruction set computer(CISC)microprocessors. During the 1980s and early 1990s, they were popular inpersonal computersandworkstationsand were the primary competitors ofIntel'sx86microprocessors. They were best known as the processors used in the early AppleMacintosh, the SharpX68000, the CommodoreAmiga, theSinclair QL, theAtari STandFalcon, theAtari Jaguar, theSega Genesis(Mega Drive) andSega CD, thePhilips CD-i, theCapcom System I(Arcade), theAT&T UNIX PC, the TandyModel 16/16B/6000, the Sun MicrosystemsSun-1,Sun-2andSun-3, theNeXT Computer,NeXTcube,NeXTstation, andNeXTcube Turbo, earlySilicon GraphicsIRIS workstations, theAesthedes, computers fromMASSCOMP, theTexas InstrumentsTI-89/TI-92calculators, thePalm Pilot(all models running Palm OS 4.x or earlier), theControl Data CorporationCDCNETDevice Interface, theVTechPrecomputer Unlimited and theSpace Shuttle. Although no modern desktop computers are based on processors in the 680x0 series, derivative processors are still widely used inembedded systems. Motorolaceased development of the 680x0 series architecture in 1994, replacing it with thePowerPCRISCarchitecture, which was developed in conjunction withIBMandApple Computeras part of theAIM alliance. 68010: 68020: 68030: 68040: 68060: The 680x0 line of processors has been used in a variety of systems, from high-endTexas Instrumentscalculators (theTI-89,TI-92, andVoyage 200lines) to all of the members of thePalm Pilotseries that run Palm OS 1.x to 4.x (OS 5.x isARM-based), and evenradiation-hardenedversions in the critical control systems of theSpace Shuttle. The 680x0 CPU family became most well known for poweringdesktop computersandvideo game consolessuch as theMacintosh 128K,Amiga,Sinclair QL,Atari ST,Genesis / Mega Drive,NG AES/Neo Geo CD,CDTV. They were the processors of choice in the 1980s forUnixworkstationsandserverssuch as AT&T'sUNIX PC, Tandy'sModel 16/16B/6000, Sun Microsystems'Sun-1,Sun-2,Sun-3,NeXT Computer,Silicon Graphics(SGI), and numerous others. TheSaturnuses the 68000 for audio processing and other I/O tasks, while theJaguarincludes a 68000 intended for basic system control and input processing, but was frequently used for running game logic. Many arcade boards also use 68000 processors including those from Capcom, SNK, and Sega. The first several versions of Adobe'sPostScriptinterpreters were 68000-based. The 68000 in the AppleLaserWriterand LaserWriter Plus was clocked faster than the version used then in Macintosh computers. A fast 68030 in later PostScript interpreters, including the standard resolution LaserWriter IIntx, IIf and IIg (also 300 dpi), the higher resolution LaserWriter Pro 600 series (usually 600 dpi, but limited to 300 dpi with minimum RAM installed) and the very high resolutionLinotronicimagesetters, the 200PS (1500+ dpi) and 300PS (2500+ dpi). Thereafter, Adobe generally preferred a RISC for its processor, as its competitors, with their PostScript clones, had already gone with RISCs, often an AMD 29000-series. The early 68000-based Adobe PostScript interpreters and their hardware were named forCold War-era U.S. rockets and missiles: Atlas, Redstone, etc. Microcontrollersderived from the 68000 family have been used in a huge variety of applications.CPU32andColdFiremicrocontrollers have been manufactured in the millions as automotive engine controllers. Many proprietary video editing systems used 68000 processors, such as the MacroSystem Casablanca, which was a black box with an easy to use graphic interface (1997). It was intended for the amateur and hobby videographer market. It is also worth noting its earlier, bigger and more professional counterpart, the "DraCo" (1995). The groundbreakingQuantel Paintboxseries of early based 24-bit paint and effects system was originally released in 1981 and during its lifetime it used nearly the entire range of 68000 family processors, with the sole exception of the 68060, which was never implemented in its design. Another contender in the video arena, the Abekas 8150 DVE system, used the 680EC30, and the Play Trinity, later renamed Globecaster, uses several 68030s. The Bosch FGS-4000/4500 Video Graphics System manufactured by Robert Bosch Corporation, later BTS (1983), used a 68000 as its main processor; it drove several others to perform 3D animation in a computer that could easily apply Gouraud and Phong shading. It ran a modifiedMotorola VERSAdosoperating system. People who are familiar with thePDP-11orVAXusually feel comfortable with the 68000 series. With the exception of the split of general-purpose registers into specialized data and address registers, the 68000 architecture is in many ways a 32-bit PDP-11. It had a moreorthogonal instruction setthan those of many processors that came before (e.g., 8080) and after (e.g., x86). That is, it was typically possible to combine operations freely with operands, rather than being restricted to using certain addressing modes with certain instructions. This property made programming relatively easy for humans, and also made it easier to write code generators for compilers. The 68000 series has eight 32-bit general-purpose dataregisters(D0-D7), and eight address registers (A0-A7). The last address register is thestack pointer, and assemblers accept the label SP as equivalent to A7. In addition, it has a 16-bit status register. The upper 8 bits is the system byte, and modification of it is privileged. The lower 8 bits is the user byte, also known as the condition code register (CCR), and modification of it is not privileged. The 68000 comparison, arithmetic, and logic operations modify condition codes to record their results for use by later conditional jumps. The condition code bits are "zero" (Z), "carry" (C), "overflow" (V), "extend" (X), and "negative" (N). The "extend" (X) flag deserves special mention, because it is separate from thecarry flag. This permits the extra bit from arithmetic, logic, and shift operations to be separated from the carry for flow-of-control and linkage. While the 68000 had a 'supervisor mode', it did not meet thePopek and Goldberg virtualization requirementsdue to the single instruction 'MOVE from SR', which copies the status register to another register, being unprivileged but sensitive. In theMotorola 68010and later, this was made privileged, to better support virtualization software. The 68000 seriesinstruction setcan be divided into the following broad categories: TheMotorola 68020added some new instructions that include some minor improvements and extensions to the supervisor state, several instructions for software management of a multiprocessing system (which were removed in the 68060), some support for high-level languages which did not get used much (and was removed from future 680x0 processors), bigger multiply (32×32→64 bits) and divide (64÷32→32 bits quotient and 32 bits remainder) instructions, and bit field manipulations. The standardaddressing modesare: Plus: access to thestatus register, and, in later models, other special registers. The Motorola 68020 added ascaled indexingaddress mode, and added another level ofindirectionto many of the pre-existing modes. Most instructions have dot-letter suffixes, permitting operations to occur on 8-bit bytes (".b"), 16-bit words (".w"), and 32-bit longs (".l"). Most instructions aredyadic, that is, the operation has a source, and a destination, and the destination is changed. Notable instructions were: Motorola mainly used even numbers for major revisions to the CPU core such as 68000, 68020, 68040 and 68060. The 68010 was a revised version of the 68000 with minor modifications to the core, and likewise the 68030 was a revised 68020 with some more powerful features, none of them significant enough to classify as a major upgrade to the core. The 68050 was reportedly "a minor upgrade of the 68040" that lost a battle for resources within Motorola, competing against projects that had been scheduled to succeed it: the 0.5μm, low-power, low-cost "LP040", and the superscalar, superpipelined "Q", borrowing from the 88110 and anticipated as the 68060.[19]Subsequent reports indicated that Motorola had considered the 68050 as not meriting the necessary investment in production of the part.[20]Odd-numbered releases had always been reactions to issues raised within the prior even numbered part; hence, it was generally expected that the 68050 would have reduced the 68040's power consumption (and thus heat dissipation), improved exception handling in the FPU, used a smaller feature size and optimized the microcode in line with program use of instructions. Many of these optimizations were included with the 68060 and were part of its design goals. For any number of reasons, likely that the 68060 was in development, that the Intel 80486 was not progressing as quickly as Motorola assumed it would, and that 68060 was a demanding project, the 68050 was cancelled early in development. There is also no revision of the68060, as Motorola was in the process of shifting away from the 68000 and88kprocessor lines into its newPowerPCbusiness, so the 68070 was never developed. Had it been, it would have been a revised 68060, likely with a superior FPU (pipelining was widely speculated upon on Usenet). There was a CPU with the68070designation, which was a licensed and somewhat slower version of the 16/32-bit 68000 with a basic DMA controller,I²Chost and an on-chip serial port. This 68070 was used as the main CPU in thePhilipsCD-i. This CPU was, however, produced byPhilipsand not officially part of Motorola's 680x0 lineup. Motorola had announced a product roadmap beyond the 68060 featuring the 68080 rated at 200-350 MIPS, due by 1995, and a product rated at 800 MIPS, possibly with the name 68100, by 2000.[20] The 4th-generation68060provided equivalent functionality (though not instruction-set-architecture compatibility) to most of the features of the IntelP5 microarchitecture. The Personal ComputersXT/370andAT/370PC-based IBM-compatible mainframeseach included two modified Motorola 68000 processors with custommicrocodeto emulateS/370mainframe instructions.[21][22] An Arizona-based company,Edge Computer Corp, reportedly founded by former Honeywell designers, produced processors compatible with the 68000 series, these being claimed as having "a three to five times performance – and18 to 24 months' time– advantage" over Motorola's own products.[23]In 1987, the company introduced the Edge 1000 range of "32-bit superminicomputers implementing the Motorola instruction set in the Edge mainframe architecture", employing two independent pipelines - an instruction fetch pipeline (IFP) and operand executive pipeline (OEP) - relying on a branch prediction unit featuring a 4096-entry branch cache, retrieving instructions and operands over multiple buses.[24]An agreement between Edge Computer and Olivetti subsequently led to the latter introducing products in its own "Linea Duo" range based on Edge Computer's machines.[25]The company was subsequently renamed to Edgcore Technology Inc.[26]: 12(also reported as Edgecore Technology Inc.[27]). Edgcore's deal withOlivettiin 1987 to supply the company's E1000 processor was followed in 1989 by another deal withPhilips Telecommunications Data Systemsto supply the E2000 processor, this supporting the 68030 instruction set and reportedly offering a performance rating of 16 VAX MIPS.[28]Similar deals withNixdorf ComputerandHitachiwere also signed in 1989.[29][30] Edge Computer reportedly had an agreement with Motorola.[27]Despite increasing competition from RISC products, Edgcore sought to distinguish its products in the market by emphasising its "alliance" with Motorola, employing a marketing campaign drawing from Aesop's fables with "the fox (Edgecore) who climbs on the back of the stallion (Motorola) to pluck fruit off the higher branches of the tree".[31]Other folktale advertising themes such asLittle Red Riding Hoodwere employed.[32]With the company's investors having declined to finance the company further, and with a number of companies having been involved in discussions with other parties,Arix Corp. announced the acquisition of Edgcore in July 1989.[30]Arix was reportedly able to renew its deal with Hitachi in 1990, whereas the future of previous deals with Olivetti and Philips remained in some doubt after the acquisition of Edgcore.[33] In 1992, a company calledInternational Meta Systems(IMS) announced a RISC-based CPU, theIMS 3250, that could reportedly emulate the "Intel 486 or Motorola 68040 at full native speeds and at a fraction of their cost". Clocked at100MHz, emulations had supposedly been developed of a25 MHz486 and30 MHz68040, including floating-point unit support, with the product aiming for mid-1993 production at a per-unit cost of$50 to 60.[34]Amidst the apparent proliferation of emulation support in processors such as thePowerPC 615, in 1994, IMS had reportedly filed a patent on its emulation technology but had not found any licensees.[35]Repeated delays to the introduction of this product, blamed on one occasion on "a need to improve the chip's speech-processing capabilities",[36]apparently led to the company seeking to introduce another chip, theMeta6000, aiming to compete with Intel's P6 products.[37]Ultimately, IMS entered bankruptcy having sold patents to a litigator, TechSearch, who in 1998 attempted to sue Intel for infringement of an IMS patent.[38]TechSearch reportedly lost their case but sought to appeal, also seeking to sue Intel for "libel and slander" on the basis of comments made by an Intel representative who had characterised TechSearch's business model unfavourably in remarks to the press.[39] After the mainline 68000 processors' demise, the 68000 family has been used to some extent inmicrocontrollerand embedded microprocessor versions. These chips include the ones listed under "other" above, i.e. theCPU32(aka68330), theColdFire, theQUICCand theDragonBall. With the advent ofFPGAtechnology an international team of hardware developers have re-created the68000with many enhancements as an FPGA core. Their core is known as the68080and is used in Vampire-branded Amiga accelerators.[40] Magnetic Scrollsused a subset of the 68000's instructions as a base for the virtual machine in theirtext adventures. During the 1980s and early 1990s, when the 68000 was widely used in desktop computers, it mainly competed againstIntel'sx86architecture used inIBM PC compatibles. Generation 1 68000 CPUs competed against mainly the16-bit8086,8088, and80286. Generation 2 competed against the80386(the first 32-bit x86 processor), and generation 3 against the80486. The fourth generation competed with theP5Pentiumline, but it was not nearly as widely used as its predecessors, since much of the old 68000 marketplace was either defunct or nearly so (as was the case with Atari and NeXT), or converting to newer architectures (PowerPCfor theMacintoshandAmiga,SPARCforSun, andMIPSforSilicon Graphics(SGI)). There are dozens of processor architectures that are successful inembedded systems. Some are microcontrollers which are much simpler, smaller, and cheaper than the 68000, while others are relatively sophisticated and can run complex software. Embedded versions of the 68000 often compete with processor architectures based onPowerPC,ARM,MIPS,SuperH, and others.	https://en.wikipedia.org/wiki/680x0
PowerPC(with thebackronymPerformance Optimization With Enhanced RISC – Performance Computing, sometimes abbreviated asPPC) is areduced instruction set computer(RISC)instruction set architecture(ISA) created by the 1991Apple–IBM–Motorolaalliance, known asAIM. PowerPC, as an evolving instruction set, has been namedPower ISAsince 2006, while the old name lives on as atrademarkfor some implementations ofPower Architecture–based processors. Originally intended forpersonal computers, the architecture is well known for being used by Apple's desktop and laptop lines from 1994 until 2006, and in severalvideogame consolesincluding Microsoft'sXbox 360, Sony'sPlayStation 3, and Nintendo'sGameCube,Wii, andWii U. PowerPC was also used for theCuriosityandPerseverancerovers on Mars and a variety of satellites. It has since become a niche architecture for personal computers, particularly withAmigaOS 4implementations, but remains popular forembedded systems. PowerPC was the cornerstone of AIM'sPRePandCommon Hardware Reference Platform(CHRP) initiatives in the 1990s. It is largely based on the earlierIBM POWER architecture, and retains a high level of compatibility with it; the architectures have remained close enough that the same programs andoperating systemswill run on both if some care is taken in preparation; newer chips in thePower seriesuse thePower ISA. The history of RISC began with IBM's801research project, on whichJohn Cockewas the lead developer, where he developed the concepts ofRISCin 1975–78. 801-based microprocessors were used in a number of IBM embedded products, eventually becoming the 16-registerIBM ROMPprocessor used in theIBM RT PC. The RT PC was a rapid design implementing the RISC architecture. Between the years of 1982 and 1984, IBM started a project to build the fastest microprocessor on the market; this new32-bitarchitecture became referred to as theAmerica Projectthroughout its development cycle, which lasted for approximately 5–6 years. The result is thePOWER instruction set architecture, introduced with theRISC System/6000in early 1990. Theoriginal POWER microprocessor, one of the firstsuperscalarRISC implementations, is a high performance, multi-chip design. IBM soon realized that a single-chip microprocessor was needed in order to scale its RS/6000 line from lower-end to high-end machines. Work began on a one-chip POWER microprocessor, designated the RSC (RISC Single Chip). In early 1991, IBM realized its design could potentially become a high-volume microprocessor used across the industry. Apple had already realized the limitations and risks of its dependency upon a single CPU vendor at a time when Motorola was falling behind on delivering the68040CPU. Furthermore, Apple had conducted its own research and made an experimental quad-core CPU design called Aquarius,[2]: 86–90which convinced the company's technology leadership that the future of computing was in the RISC methodology.[2]: 287–288IBM approached Apple with the goal of collaborating on the development of a family of single-chip microprocessors based on the POWER architecture. Soon after, Apple, being one of Motorola's largest customers of desktop-class microprocessors,[3]asked Motorola to join the discussions due to their long relationship, Motorola having had more extensive experience with manufacturing high-volume microprocessors than IBM, and to form a second source for the microprocessors. This three-way collaboration between Apple, IBM, and Motorola became known as theAIM alliance. In 1991, the PowerPC was just one facet of a larger alliance among these three companies. At the time, most of the personal computer industry was shipping systems based on the Intel 80386 and 80486 chips, which have acomplex instruction set computer(CISC) architecture, and development of thePentiumprocessor was well underway. The PowerPC chip was one of several joint ventures involving the three alliance members, in their efforts to counter the growing Microsoft-Intel dominance of personal computing. For Motorola, POWER looked like an unbelievable deal. It allowed the company to sell a widely tested and powerful RISC CPU for little design cash on its own part. It also maintained ties with an important customer, Apple, and seemed to offer the possibility of adding IBM too, which might buy smaller versions from Motorola instead of making its own. At this point Motorola already had its own RISC design in the form of the88000, which was doing poorly in the market. Motorola was doing well with its68000family and the majority of the funding was focused on this. The 88000 effort was somewhat starved for resources. The 88000 was already in production, however;Data Generalwas shipping 88000 machines and Apple already had 88000 prototype machines running. The 88000 had also achieved a number of embedded design wins in telecom applications. If the new POWER one-chip version could be made bus-compatible at a hardware level with the 88000, that would allow both Apple and Motorola to bring machines to market far faster since they would not have to redesign their board architecture. The result of these various requirements is the PowerPC (performance computing) specification. The differences between the earlier POWER instruction set and that of PowerPC is outlined in Appendix E of the manual for PowerPC ISA v.2.02.[1] Since 1991, IBM had a long-standing desire for a unifying operating system that would simultaneously host all existing operating systems as personalities upon one microkernel. From 1991 to 1995, the company designed and aggressively evangelized what would becomeWorkplace OS, primarily targeting PowerPC.[2]: 290–291 When the first PowerPC products reached the market, they were met with enthusiasm. In addition to Apple, both IBM and the Motorola Computer Group offered systems built around the processors.MicrosoftreleasedWindows NT 3.51for the architecture, which was used in Motorola's PowerPC servers, andSun Microsystemsoffered a version of itsSolarisOS. IBM ported itsAIXUnix. Workplace OS featured a new port ofOS/2(with Intel emulation for application compatibility), pending a successful launch of the PowerPC 620. Throughout the mid-1990s, PowerPC processors achievedbenchmarktest scores that matched or exceeded those of the fastest x86 CPUs. Ultimately, demand for the new architecture on the desktop never truly materialized. Windows, OS/2, and Sun customers, faced with the lack of application software for the PowerPC, almost universally ignored the chip. IBM's Workplace OS platform (and thus, OS/2 for PowerPC) was summarily canceled upon its first developers' release in December 1995 due to the simultaneous buggy launch of the PowerPC 620. The PowerPC versions of Solaris and Windows were discontinued after only a brief period on the market. Only on the Macintosh, due to Apple's persistence, did the PowerPC gain traction. To Apple, the performance of the PowerPC was a bright spot in the face of increased competition from Windows 95 and Windows NT-based PCs. With the cancellation of Workplace OS, the general PowerPC platform (especially AIM'sCommon Hardware Reference Platform) was instead seen as a hardware-only compromise to run many operating systems one at a time upon a single unifying vendor-neutral hardware platform.[2]: 287–288 In parallel with the alliance between IBM and Motorola, both companies had development efforts underway internally. ThePowerQUICCline was the result of this work inside Motorola. The 4xx series of embedded processors was underway inside IBM. The IBM embedded processor business grew to nearly US$100 million in revenue and attracted hundreds of customers. The development of the PowerPC is centered at an Austin, Texas, facility called the Somerset Design Center. The building is named after the site in Arthurian legend where warring forces put aside their swords, and members of the three teams that staff the building say the spirit that inspired the name has been a key factor in the project's success thus far. Part of the culture here is not to have an IBM or Motorola or Apple culture, but to have our own. Toward the close of the decade, manufacturing issues began plaguing the AIM alliance in much the same way they did Motorola, which consistently pushed back deployments of new processors for Apple and other vendors: first from Motorola in the 1990s with the PowerPC 7xx and 74xx processors, and IBM with the 64-bit PowerPC 970 processor in 2003. In 2004, Motorola exited the chip manufacturing business by spinning off its semiconductor business as an independent company calledFreescale Semiconductor. Around the same time, IBM exited the 32-bit embedded processor market by selling its line of PowerPC products toApplied Micro Circuits Corporation(AMCC) and focusing on 64-bit chip designs, while maintaining its commitment of PowerPC CPUs toward game console makers such asNintendo'sGameCube,WiiandWii U,Sony'sPlayStation 3andMicrosoft'sXbox 360, of which the latter two both use 64-bit processors. In 2005, Apple announced they would no longer use PowerPC processors in their Apple Macintosh computers, favoringIntel-produced processors instead, citing the performance limitations of the chip for future personal computer hardware specifically related to heat generation and energy usage, as well as the inability of IBM to move the 970 processor to the 3 GHz range. The IBM-Freescale alliance was replaced by anopen standardsbody called Power.org. Power.org operates under the governance of the IEEE with IBM continuing to use and evolve the PowerPC processor on game consoles and Freescale Semiconductor focusing solely on embedded devices. IBM continues to develop PowerPC microprocessor cores for use in theirapplication-specific integrated circuit(ASIC) offerings. Many high volume applications embed PowerPC cores. The PowerPC specification is now handled by Power.org where IBM, Freescale, and AMCC are members. PowerPC, Cell and POWER processors are now jointly marketed as thePower Architecture. Power.org released a unified ISA, combining POWER and PowerPC ISAs into the new Power ISA v.2.03 specification and a new reference platform for servers called PAPR (Power Architecture Platform Reference). Many PowerPC designs are named and labeled by their apparent technology generation. That began with the "G3", which was an internal project name insideAIMfor the development of what would become thePowerPC 750 family.[5]Apple popularized the term "G3" when they introducedPower Mac G3andPowerBook G3at an event at 10 November 1997. Motorola and Apple liked the moniker and used the term "G4" for the 7400 family introduced in 1998[6][7]and thePower Mac G4in 1999. At the time the G4 was launched, Motorola categorized all their PowerPC models (former, current and future) according to what generation they adhered to, even renaming the older 603e core "G2". Motorola had aG5 projectthat never came to fruition, and Apple later used the name when the970 familylaunched in 2003, though it was designed and built by IBM. The PowerPC is designed alongRISC principlesand allows for asuperscalarimplementation. Versions of the design exist in both 32-bit and 64-bit implementations. Starting with the basic POWER specification, the PowerPC added: Some instructions present in the POWER instruction set were deemed too complex and were removed in the PowerPC architecture. Some removed instructions could be emulated by theoperating systemif necessary. The removed instructions are: Most PowerPC chips switch endianness via a bit in the MSR (machine state register), with a second bit provided to allow the OS to run with a different endianness. Accesses to the "inverted page table" (a hash table that functions as aTLBwith off-chip storage) are always done in big-endian mode. The processor starts in big-endian mode. In little-endian mode, the three lowest-order bits of the effective address areexclusive-ORedwith a three bit value selected by the length of the operand. This is enough to appear fully little-endian to normal software. An operating system will see a warped view of the world when it accesses external chips such as video and network hardware. Fixing this warped view requires that the motherboard perform an unconditional 64-bit byte swap on all data entering or leaving the processor. Endianness thus becomes a property of the motherboard. An OS that operates in little-endian mode on a big-endian motherboard must both swap bytes and undo the exclusive-OR when accessing little-endian chips. AltiVecoperations, despite being 128-bit, are treated as if they were 64-bit. This allows for compatibility with little-endian motherboards that were designed prior to AltiVec. An interesting side effect of this implementation is that a program can store a 64-bit value (the longest operand format) to memory while in one endian mode, switch modes, and read back the same 64-bit value without seeing a change of byte order. This will not be the case if the motherboard is switched at the same time. Mercury SystemsandMatroxran the PowerPC in little-endian mode. This was done so that PowerPC devices serving as co-processors on PCI boards could share data structures with host computers based onx86. Both PCI and x86 are little-endian. OS/2 and Windows NT for PowerPC ran the processor in little-endian mode while Solaris, AIX and Linux ran in big endian.[9] Some of IBM's embedded PowerPC chips use a per-pageendiannessbit. None of the previous applies to them. The first implementation of the architecture was thePowerPC 601, released in 1992, based on the RSC, implementing a hybrid of thePOWER1and PowerPC instructions. This allowed the chip to be used by IBM in their existing POWER1-based platforms, although it also meant some slight pain when switching to the 2nd generation "pure" PowerPC designs. Apple continued work on a new line of Macintosh computers based on the chip, and eventually released them as the 601-basedPower Macintoshon March 14, 1994. Accelerator cards based on the first-generation PowerPC chips were created for theAmigain anticipation for a move to a possible new Amiga platform designed around the PowerPC. The accelerator cards also included either aMotorola 68040or68060CPU in order to maintain backwards compatibility, as very few apps at the time could run natively on the PPC chips. However, the new machines never materialized, and Commodore subsequently declared bankruptcy. Over a decade later,AmigaOS 4would be released, which would put the platform permanently on the architecture. OS4 is compatible with those first-generation accelerators, as well as several custom motherboards created for a new incarnation of the Amiga platform. IBM also had a full line of PowerPC based desktops built and ready to ship; unfortunately, the operating system that IBM had intended to run on these desktops—MicrosoftWindows NT—was not complete by early 1993, when the machines were ready for marketing. Accordingly, and further because IBM had developed animosity toward Microsoft, IBM decided to portOS/2to the PowerPC in the form of Workplace OS. This new software platform spent three years (1992 to 1995) in development and was canceled with the December 1995 developer release, because of the disappointing launch of the PowerPC 620. For this reason, the IBM PowerPC desktops did not ship, although the reference design (codenamed Sandalbow) based on the PowerPC 601 CPU was released as an RS/6000 model (Byte's April 1994 issue included an extensive article about the Apple and IBM PowerPC desktops). Apple, which also lacked a PowerPC based OS, took a different route. Utilizing the portability platform yielded by the secretStar Trek project, the company ported the essential pieces of theirMac OSoperating system to the PowerPC architecture, and further wrote a68k emulatorthat could run68kbased applications and the parts of the OS that had not been rewritten. The second generation was "pure" and includes the "low end"PowerPC 603and "high end"PowerPC 604. The 603 is notable due to its very low cost and power consumption. This was a deliberate design goal on Motorola's part, who used the 603 project to build the basic core for all future generations of PPC chips. Apple tried to use the 603 in a new laptop design but was unable due to the small 8KBlevel 1 cache. The 68000 emulator in the Mac OS could not fit in 8 KB and thus slowed the computer drastically.[10][11]The603esolved this problem by having a 16 KBL1 cache, which allowed the emulator to run efficiently. In 1993, developers at IBM'sEssex Junction, Burlington, Vermontfacility started to work on a version of the PowerPC that would support the Intelx86instruction set directly on the CPU. While this was just one of several concurrent power architecture projects that IBM was working on, this chip began to be known inside IBM and by the media as thePowerPC 615. Profitability concerns and rumors of performance issues in the switching between the x86 and native PowerPC instruction sets resulted in the project being canceled in 1995 after only a limited number of chips were produced for in-house testing. Aside the rumors, the switching process took only 5 cycles, or the amount of time needed for the processor to empty its instruction pipeline. Microsoft also aided the processor's demise by refusing to support the PowerPC mode.[12] The first 64-bit implementation is thePowerPC 620, but it appears to have seen little use because Apple didn't want to buy it and because, with its large die area, it was too costly for the embedded market. It was later and slower than promised, and IBM used their ownPOWER3design instead, offering no 64-bit "small" version until the late-2002 introduction of thePowerPC 970. The 970 is a 64-bit processor derived from thePOWER4server processor. To create it, the POWER4 core was modified to be backward-compatible with 32-bit PowerPC processors, and a vector unit (similar to theAltiVecextensions in Motorola's 74xx series) was added. IBM'sRS64processors are a family of chips implementing the "Amazon" variant of the PowerPC architecture. These processors are used in theRS/6000andIBM AS/400computer families; the Amazon architecture includes proprietary extensions used by AS/400.[13]The POWER4 and later POWER processors implement the Amazon architecture and replaced the RS64 chips in the RS/6000 and AS/400 families. IBM developed a separate product line called the "4xx" line focused on the embedded market. These designs included the 401, 403, 405, 440, and 460. In 2004, IBM sold their 4xx product line to Applied Micro Circuits Corporation (AMCC). AMCC continues to develop new high performance products, partly based on IBM's technology, along with technology that was developed within AMCC. These products focus on a variety of applications including networking, wireless, storage, printing/imaging and industrial automation. Numerically, the PowerPC is mostly found in controllers in cars. For the automotive market, Freescale Semiconductor initially offered many variations called theMPC5xxfamily such as the MPC555, built on a variation of the 601 core called the 8xx and designed in Israel by MSIL (Motorola Silicon Israel Limited). The 601 core is single issue, meaning it can only issue one instruction in a clock cycle. To this they add various bits of custom hardware, to allow for I/O on the one chip. In 2004, the next-generation four-digit55xxdevices were launched for the automotive market. These use the newere200series of PowerPC cores. Networking is another area where embedded PowerPC processors are found in large numbers. MSIL took theQUICCengine from theMC68302and made thePowerQUICCMPC860. This was a very famous processor used in manyCiscoedge routers in the late 1990s. Variants of the PowerQUICC include the MPC850, and the MPC823/MPC823e. All variants include a separate RISC microengine called theCPMthat offloads communications processing tasks from the central processor and has functions forDMA. The follow-on chip from this family, the MPC8260, has a 603e-based core and a different CPM. Honda also uses PowerPC processors for itsASIMOrobot.[14] In 2003,BAE Systems Platform Solutionsdelivered the Vehicle-Management Computer for theF-35fighter jet. This platform consists of dual PowerPCs made by Freescale in a triple redundant setup.[15] Aeronautical Development Establishmenttested a high-performance digital flight control computer, powered by a quadraplex PowerPC-based processor setup on aHAL Tejas Mark 1Ain 2024.[16] Operating systems that work on the PowerPC architecture are generally divided into those that are oriented toward the general-purpose PowerPC systems, and those oriented toward theembeddedPowerPC systems. Companies that have licensed the 64-bit POWER or 32-bit PowerPC from IBM include: PowerPC processors were used in a number of now-discontinuedvideo game consolesandarcade system boards: The Power architecture is currently used in the following desktop computers: The Power architecture is currently used in the following embedded applications:	https://en.wikipedia.org/wiki/PowerPC
This article gives a list ofAMDmicroprocessors, sorted by generation and release year. If applicable and openly known, the designation(s) of each processor's core (versions) is (are) listed in parentheses. For an overview over concrete product, you then need to consult further articles, like e.g.list of AMD accelerated processing units. APU features table Am9080(second source forIntel 8080) Am29X305 (second source forSignetics 8X305) AMD Opteron A1100 series (second-sourcedx86processors produced under contract withIntel) K8 series K10 series CPUs(2007–2013) K10 series APUs(2011–2012) Bulldozer Series CPUs Zen-based CPUs and some APUs use theRyzen brand, while some APUs use theAthlon brand. Zenseries CPUs and APUs(released 2017) Zen+series CPUs and APUs(released 2018) Zen 2series CPUs and APUs(released 2019) Zen 3series CPUs and APUs(released 2020) Zen 3+series CPUs and APUs(released 2022) Zen 4series CPUs and APUs(released 2022) Zen 5series CPUs and APUs(released 2024)	https://en.wikipedia.org/wiki/List_of_AMD_processors

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