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lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On Wed, Nov 26, 2025 at 02:22:13PM +0000, Ryan Roberts wrote:
Yeah, it kinda sucks to bake that assumption in too even if we can prove it
currently _is_ correct, and it becomes tricky because to somebody observing this
they might well think 'oh so we don't need to think about tearing here' but in
reality we are just a... | {
"author": "Lorenzo Stoakes <lorenzo.stoakes@oracle.com>",
"date": "Wed, 26 Nov 2025 14:37:10 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/26/25 15:22, Ryan Roberts wrote:
Yeah, I'm also still trying to understand how it could work.
With __PAGETABLE_PMD_FOLDED we treat the PUD to be fake-present, like
static inline int pud_present(pud_t pud) { return 1; }
And obtaining the pmd_t* is essentially cast of the pud_t*
static inline pmd_t * pmd_offs... | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Wed, 26 Nov 2025 15:46:40 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On Wed, Nov 26, 2025 at 03:46:40PM +0100, David Hildenbrand (Red Hat) wrote:
Would the pmdp_get() never get invoked then? Or otherwise wouldn't that end up
requiring a READ_ONCE() further up the stack?
Even if we could make this work, I don't love that there's some implicit
assumption there that could easily break l... | {
"author": "Lorenzo Stoakes <lorenzo.stoakes@oracle.com>",
"date": "Wed, 26 Nov 2025 14:52:15 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/26/25 15:37, Lorenzo Stoakes wrote:
Looking at include/asm-generic/pgtable-nopmd.h, PUD entries there are
* always present (pud_present() == 1)
* always a page table (pud_leaf() == 0)
And pmd_offset() is just a typecast.
So I wonder if that means that we can make pudp_get() be a simple load
(!READ_ONCE) beca... | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Wed, 26 Nov 2025 15:53:30 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/26/25 15:52, Lorenzo Stoakes wrote:
See my other reply, I think the pmdp_get() is required because all pud_*
functions are just simple stubs.
Looking at include/asm-generic/pgtable-nopmd.h I am not sure we are
talking about implicit assumptions here. It's kind-of the design that
the pud_t values are dummies... | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Wed, 26 Nov 2025 15:56:13 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On Wed, Nov 26, 2025 at 03:56:13PM +0100, David Hildenbrand (Red Hat) wrote:
OK, thought you were saying we should push further down the stack? Or up
depending on how you view these things :P as in READ_ONCE at leaf?
Anyway. I am now designating you the expert at this ;)
I mean I'm waving my hands around like I'm w... | {
"author": "Lorenzo Stoakes <lorenzo.stoakes@oracle.com>",
"date": "Wed, 26 Nov 2025 15:08:43 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/26/25 16:08, Lorenzo Stoakes wrote:
I think at leaf because I think the previous ones should essentially be
only used by stubs.
But I haven't fully digested how this is all working. Or supposed to work.
I'm trying to chew through the arch/arm/include/asm/pgtable-2level.h
example to see if I can make sense of... | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Wed, 26 Nov 2025 16:12:59 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 26/11/2025 15:12, David Hildenbrand (Red Hat) wrote:
I wonder if we can think about this slightly differently;
READ_ONCE() has two important properties:
- It guarrantees that a load will be issued, *even if output is unused*
- It guarrantees that the read will be single-copy-atomic (no tearing)
I think for the... | {
"author": "Ryan Roberts <ryan.roberts@arm.com>",
"date": "Wed, 26 Nov 2025 16:07:23 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 26/11/2025 16:07, Ryan Roberts wrote:
I'm not sure this works. It looks like the compiler is free to move non-volatile
asm sections which might be problematic for places where we are currently using
READ_ONCE() in lockless algorithms, (e.g. GUP?). We wouldn't want to end up with
a stale value.
Another idea:
Given... | {
"author": "Ryan Roberts <ryan.roberts@arm.com>",
"date": "Wed, 26 Nov 2025 16:34:51 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/26/25 17:34, Ryan Roberts wrote:
Let's take a step back and realize that with __PAGETABLE_PMD_FOLDED
(a) *pudp does not make any sense
For a folded PMD, *pudp == *pmdp and consequently we would actually
get a PMD, not a PUD.
For this reason all these pud_* helpers ignore the passed value
completely. It would ... | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Wed, 26 Nov 2025 21:31:59 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/26/25 21:31, David Hildenbrand (Red Hat) wrote:
Staring at GUP-fast and perf_get_pgtable_size()---which should better be
converted to pudp_get() etc--I guess we might have to rework
p4d_offset_lockless() to do something that doesn't rely on
passing variables of local variables.
We might have to enlighten thes... | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Thu, 27 Nov 2025 08:14:45 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/27/25 08:14, David Hildenbrand (Red Hat) wrote:
Talking to myself (I know), handling this might be as simple as having
diff --git a/include/asm-generic/pgtable-nopmd.h b/include/asm-generic/pgtable-nopmd.h
index 8ffd64e7a24cb..60e5ba02bcf06 100644
--- a/include/asm-generic/pgtable-nopmd.h
+++ b/include/asm-gene... | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Thu, 27 Nov 2025 08:31:52 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Le 26/11/2025 à 15:22, Ryan Roberts a écrit :
I think you can't assume pgdp_get() was already called, because some
parts of code will directly descend to PMD level using pmd_off() or
pmd_off_k()
static inline pmd_t *pmd_off(struct mm_struct *mm, unsigned long va)
{
return pmd_offset(pud_offset(p4d_offset(pgd_offse... | {
"author": "\"Christophe Leroy (CS GROUP)\" <chleroy@kernel.org>",
"date": "Thu, 27 Nov 2025 09:26:39 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/27/25 09:26, Christophe Leroy (CS GROUP) wrote:
I'll note that these (nesty) helpers only work when you know that you
have folded page tables.
And that's why I am arguing that the pmdp_get() must actually be kept as is.
--
Cheers
David
_______________________________________________
linux-riscv mailing lis... | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Thu, 27 Nov 2025 09:35:37 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 27/11/2025 07:31, David Hildenbrand (Red Hat) wrote:
I'm struggling with this statement. The PMD is folded, not the PUD. So the PMD
table consists of a single entry, which overlays the entry in the PUD, right? So
the PUD exists and *pudp must be valid?
Now, pgtable-nopmd.h includes pgtable-nopud.h so actually the ... | {
"author": "Ryan Roberts <ryan.roberts@arm.com>",
"date": "Thu, 27 Nov 2025 15:32:34 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 13/11/2025 01:45, Samuel Holland wrote:
I don't think this is a good solution.
arm64, at least, expects and requires that only pointers to entries in pgtables
are passed to the arch helpers (e.g. set_pte(), ptep_get(), etc). For PTEs,
arm64 accesses adjacent entries within the page table to manage contiguous
mappi... | {
"author": "Ryan Roberts <ryan.roberts@arm.com>",
"date": "Thu, 27 Nov 2025 16:57:06 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/27/25 17:57, Ryan Roberts wrote:
Agreed,
set_pmd(&pmd, pmd);
is rather horrible.
--
Cheers
David
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Thu, 27 Nov 2025 18:47:38 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Le 26/11/2025 à 17:34, Ryan Roberts a écrit :
Take care about macros with unused parameters, it can be a problem
sometimes, see commit 05a4ab823983 ("powerpc/uaccess: fix warning/error
with access_ok()")
Christophe
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradea... | {
"author": "\"Christophe Leroy (CS GROUP)\" <chleroy@kernel.org>",
"date": "Thu, 27 Nov 2025 20:39:01 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Le 26/11/2025 à 17:34, Ryan Roberts a écrit :
What about adding a memory clobber to the non-volatile asm ? Compiler
shouldn't move the asm section in that case.
Christophe
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/lis... | {
"author": "\"Christophe Leroy (CS GROUP)\" <chleroy@kernel.org>",
"date": "Thu, 27 Nov 2025 20:44:16 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On Wed, Nov 12, 2025 at 05:45:32PM -0800, Samuel Holland wrote:
I'm not sure how I feel about this. So here are my random thoughts on
it.
I wonder if another arch may need something similar. I don't think
arm64 ever would as aliases are not allowed. That may have happened on
arm32, but that's all pretty mature at ... | {
"author": "Rob Herring <robh@kernel.org>",
"date": "Thu, 4 Dec 2025 09:12:32 -0600",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/13/25 03:45, Samuel Holland wrote:
Then why don't you solve this at the DMA API layer ? Are those
alternative PMAs going to be used for something else ? If the only
usecase is to support noncoherent DMA I suggest playing with
arch_dma_set_uncached and/or arch_dma_prep_coherent, we can deal with
this similar t... | {
"author": "Nick Kossifidis <mick@ics.forth.gr>",
"date": "Thu, 4 Dec 2025 18:23:11 +0200",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 2025-11-14 4:17 AM, David Hildenbrand (Red Hat) wrote:
Even if some functions a new incompatible pointer type, don't we still have the
problem that neither type would be safe to dereference?
A similar option to a new type would be to add a sparse annotation to the
pointers that reference hardware page tables, simi... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Thu, 11 Dec 2025 09:29:28 +0900",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 2025-11-28 2:47 AM, David Hildenbrand (Red Hat) wrote:
I agree that this patch is ugly. The only way I see to avoid code like this is
to refactor (or duplicate) the functions so no function takes pointers to both
hardware page tables and on-stack page table entries. Is that sort of
refactoring the right direction to... | {
"author": "Samuel Holland <samuel.holland@sifive.com>",
"date": "Thu, 11 Dec 2025 09:33:41 +0900",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 11/12/2025 00:33, Samuel Holland wrote:
From a quick look at the code, I think that some cases are solvable by
refactoring to pass the value instead of the pointer, and leave it to the higher
level decide how to read the value from the pointer - it knows if it is pointing
to HW pgtable or if it's a (e.g) stack valu... | {
"author": "Ryan Roberts <ryan.roberts@arm.com>",
"date": "Thu, 11 Dec 2025 13:59:53 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On Thu, Dec 11, 2025 at 01:59:53PM +0000, Ryan Roberts wrote:
Ugh. We do need to nip this in the bud I think!
I think we've got ourselves in a jumble with pte vs ptep vs pteval
vs. etc. etc. and we aren't always consistent with it.
So I think we ought to put 'hw' somewhere in the name.
And we can also now get away... | {
"author": "Lorenzo Stoakes <lorenzo.stoakes@oracle.com>",
"date": "Tue, 16 Dec 2025 10:29:13 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 16/12/2025 10:29, Lorenzo Stoakes wrote:
Yeah that would probably give the best end result. I was thinking that ptep/pXdp
might reduce churn since we already use it in function names. Stack pointers are
definitely a small minority so easier to change their convention.
But having an explicit "hw" would probably be ... | {
"author": "Ryan Roberts <ryan.roberts@arm.com>",
"date": "Tue, 16 Dec 2025 17:46:57 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On 12/11/25 14:59, Ryan Roberts wrote:
This is what I had in mind when we last discussed this topic and I
suggested a way forward to not play whack-a-mole with new users that do
*ptep showing up.
Agreed that we ideally indicate that this is a HW PTE pointer that must
be de-referenced through ptep_get() or similar.... | {
"author": "\"David Hildenbrand (Red Hat)\" <david@kernel.org>",
"date": "Thu, 18 Dec 2025 10:49:26 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | On Tue, Dec 16, 2025 at 05:46:57PM +0000, Ryan Roberts wrote:
Yeah, unfortunately I think the existing inconsistencies call for a clean
break.
Sure hw_pte_t works!
Right.
Yeah it's nice to be able to hide properties like this, I did think the use
of an incomplete type pointer was quite nice there :)
NIce.
Ye... | {
"author": "Lorenzo Stoakes <lorenzo.stoakes@oracle.com>",
"date": "Thu, 18 Dec 2025 17:27:13 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Hello:
This series was applied to riscv/linux.git (fixes)
by Andrew Morton <akpm@linux-foundation.org>:
On Wed, 12 Nov 2025 17:45:13 -0800 you wrote:
Here is the summary with links:
- [v3,01/22] mm/ptdump: replace READ_ONCE() with standard page table accessors
https://git.kernel.org/riscv/c/11119b19f62d
- [v... | {
"author": "patchwork-bot+linux-riscv@kernel.org",
"date": "Fri, 19 Dec 2025 08:10:01 +0000",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv |
On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
DRAM is mapped to multiple physical address ranges, with each alias
having a different set of statically-determined Physical Memory
Attributes (PMAs), such as cacheability. Software can alter the PMAs for
a page by selecting a PFN from the correspo... | null | null | null | [PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases | Hi Samuel
On Fri, 2025-12-19 at 08:10 +0000, patchwork-bot+linux-riscv@kernel.org wrote:
Any idea what happened to patches 04-22 as I don't think anything other than patches 01-03 ever got applied
anywhere. Or am I missing anything?
For what it's worth I carried an updated patch set through up to v6.19.4 [1] and lat... | {
"author": "Marcel Ziswiler <marcel@ziswiler.com>",
"date": "Fri, 27 Feb 2026 11:54:54 +0100",
"is_openbsd": false,
"thread_id": "d4e44b3659859e8967a1cee7cbbeeeeb399a4536.camel@ziswiler.com.mbox.gz"
} |
lkml_critique | linux-riscv | K230 SoC USB PHY requires configuring registers for control and
configuration. Add USB phy bindings for K230 SoC.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
---
.../bindings/phy/canaan,k230-usb-phy.yaml | 35 +++++++++++++++++++
1 file changed, 35 inser... | null | null | null | [PATCH v5 1/4] dt-bindings: phy: Add Canaan K230 USB PHY | Add driver for the USB 2.0 PHY in Canaan K230 SoC, which supports PHY
initialization and power management.
Add Kconfig/Makefile under drivers/phy/canaan/.
Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
---
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile | 1 +
drivers/phy/canaa... | {
"author": "Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>",
"date": "Wed, 21 Jan 2026 22:55:24 +0800",
"is_openbsd": false,
"thread_id": "aZ7ntvit57TaPgyw@duge-virtual-machine.mbox.gz"
} |
lkml_critique | linux-riscv | K230 SoC USB PHY requires configuring registers for control and
configuration. Add USB phy bindings for K230 SoC.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
---
.../bindings/phy/canaan,k230-usb-phy.yaml | 35 +++++++++++++++++++
1 file changed, 35 inser... | null | null | null | [PATCH v5 1/4] dt-bindings: phy: Add Canaan K230 USB PHY | Add top syscon and USB PHY subdevice nodes, USB0/USB1 dwc2 controller
to K230 DTSI, and enable UART0 and USB0/USB1 in DshanPI DT.
Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
---
.../boot/dts/canaan/k230-canmv-dshanpi.dts | 17 +++++++++
arch/riscv/boot/dts/canaan/k230.dtsi | 35 ++++++++++++++++... | {
"author": "Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>",
"date": "Wed, 21 Jan 2026 22:55:25 +0800",
"is_openbsd": false,
"thread_id": "aZ7ntvit57TaPgyw@duge-virtual-machine.mbox.gz"
} |
lkml_critique | linux-riscv | K230 SoC USB PHY requires configuring registers for control and
configuration. Add USB phy bindings for K230 SoC.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
---
.../bindings/phy/canaan,k230-usb-phy.yaml | 35 +++++++++++++++++++
1 file changed, 35 inser... | null | null | null | [PATCH v5 1/4] dt-bindings: phy: Add Canaan K230 USB PHY | Add 'canaan,k230-usb' compatible string with 'snps,dwc2' as fallback
for the DWC2 IP which is used by Canaan K230.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
---
Documentation/devicetree/bindings/usb/dwc2.yaml | 3 +++
1 file changed, 3 insertions(+)
diff ... | {
"author": "Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>",
"date": "Wed, 21 Jan 2026 22:55:23 +0800",
"is_openbsd": false,
"thread_id": "aZ7ntvit57TaPgyw@duge-virtual-machine.mbox.gz"
} |
lkml_critique | linux-riscv | K230 SoC USB PHY requires configuring registers for control and
configuration. Add USB phy bindings for K230 SoC.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
---
.../bindings/phy/canaan,k230-usb-phy.yaml | 35 +++++++++++++++++++
1 file changed, 35 inser... | null | null | null | [PATCH v5 1/4] dt-bindings: phy: Add Canaan K230 USB PHY | Add support for the USB PHY and DWC2 IP which is used by Canaan K230,
and made relevant changes to the DTS.
This series is based on the initial 100ask K230 DshanPi series [1] which
is based on the clock and pinctrl series. Check the details in the link.
Link: https://lore.kernel.org/all/20260115060801.16819-1-jiayu.r... | {
"author": "Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>",
"date": "Wed, 21 Jan 2026 22:55:21 +0800",
"is_openbsd": false,
"thread_id": "aZ7ntvit57TaPgyw@duge-virtual-machine.mbox.gz"
} |
lkml_critique | linux-riscv | K230 SoC USB PHY requires configuring registers for control and
configuration. Add USB phy bindings for K230 SoC.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
---
.../bindings/phy/canaan,k230-usb-phy.yaml | 35 +++++++++++++++++++
1 file changed, 35 inser... | null | null | null | [PATCH v5 1/4] dt-bindings: phy: Add Canaan K230 USB PHY | On Wed, Jan 21, 2026 at 10:55:21PM +0800, Jiayu Du wrote:
Hello Vinod, could you please take a look at this patch? Thank you!
Regards,
Jiayu Du
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>",
"date": "Mon, 2 Feb 2026 19:31:36 +0800",
"is_openbsd": false,
"thread_id": "aZ7ntvit57TaPgyw@duge-virtual-machine.mbox.gz"
} |
lkml_critique | linux-riscv | K230 SoC USB PHY requires configuring registers for control and
configuration. Add USB phy bindings for K230 SoC.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
---
.../bindings/phy/canaan,k230-usb-phy.yaml | 35 +++++++++++++++++++
1 file changed, 35 inser... | null | null | null | [PATCH v5 1/4] dt-bindings: phy: Add Canaan K230 USB PHY | On Mon, Feb 02, 2026 at 07:31:36PM +0800, Jiayu Du wrote:
Hi Vinod, will you review this patch? Thank you again!
Regards,
Jiayu Du
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>",
"date": "Wed, 25 Feb 2026 20:14:46 +0800",
"is_openbsd": false,
"thread_id": "aZ7ntvit57TaPgyw@duge-virtual-machine.mbox.gz"
} |
lkml_critique | linux-riscv | K230 SoC USB PHY requires configuring registers for control and
configuration. Add USB phy bindings for K230 SoC.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
---
.../bindings/phy/canaan,k230-usb-phy.yaml | 35 +++++++++++++++++++
1 file changed, 35 inser... | null | null | null | [PATCH v5 1/4] dt-bindings: phy: Add Canaan K230 USB PHY | On Wed, 21 Jan 2026 22:55:21 +0800, Jiayu Du wrote:
Applied, thanks!
[1/4] dt-bindings: phy: Add Canaan K230 USB PHY
commit: 50357e7d7992ba8f02c87ff7a5c4db17918635da
[3/4] phy: usb: Add driver for Canaan K230 USB 2.0 PHY
commit: 8787fa1da603e9e51efff11841e97b5d374aef34
Best regards,
--
~Vinod
_______... | {
"author": "Vinod Koul <vkoul@kernel.org>",
"date": "Fri, 27 Feb 2026 20:59:12 +0530",
"is_openbsd": false,
"thread_id": "aZ7ntvit57TaPgyw@duge-virtual-machine.mbox.gz"
} |
lkml_critique | linux-riscv | While fuzzing KVM on RISC-V, a use-after-free was observed in
kvm_riscv_gstage_get_leaf(), where ptep_get() dereferences a
freed gstage page table page during gfn unmap.
The crash manifests as:
use-after-free in ptep_get include/linux/pgtable.h:340 [inline]
use-after-free in kvm_riscv_gstage_get_leaf arch/riscv/k... | null | null | null | [PATCH v2] RISC-V: KVM: Fix use-after-free in kvm_riscv_gstage_get_leaf() | On Mon, Feb 2, 2026 at 9:31 AM Jiakai Xu <xujiakai2025@iscas.ac.cn> wrote:
Unconditionally locking mmu_lock over here cause following crash
when powering off the KVM Guest.
[ 88.985889] rcu: INFO: rcu_sched self-detected stall on CPU
[ 88.986721] rcu: 1-....: (5249 ticks this GP)
idle=9184/1/0x400000000000000... | {
"author": "Anup Patel <anup@brainfault.org>",
"date": "Thu, 26 Feb 2026 13:56:54 +0530",
"is_openbsd": false,
"thread_id": "CAAhSdy3V2kipH8sPzXkmnXP=Sh=7wwqhHaAWDyucJnytbL+qtw@mail.gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | While fuzzing KVM on RISC-V, a use-after-free was observed in
kvm_riscv_gstage_get_leaf(), where ptep_get() dereferences a
freed gstage page table page during gfn unmap.
The crash manifests as:
use-after-free in ptep_get include/linux/pgtable.h:340 [inline]
use-after-free in kvm_riscv_gstage_get_leaf arch/riscv/k... | null | null | null | [PATCH v2] RISC-V: KVM: Fix use-after-free in kvm_riscv_gstage_get_leaf() | Hi Anup,
Thanks for taking care of this and queuing the fix.
Best regards,
Jiakai
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "\"Jiakai Xu\" <xujiakai2025@iscas.ac.cn>",
"date": "Thu, 26 Feb 2026 17:08:31 +0800 (GMT+08:00)",
"is_openbsd": false,
"thread_id": "CAAhSdy3V2kipH8sPzXkmnXP=Sh=7wwqhHaAWDyucJnytbL+qtw@mail.gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | The crash memory allocation, and the exclude of crashk_res, crashk_low_res
and crashk_cma memory are almost identical across different architectures,
This patch set handle them in crash core in a general way, which eliminate
a lot of duplication code.
And add support for crashkernel CMA reservation for arm64 and riscv... | null | null | null | [PATCH v7 0/5] arm64/riscv: Add support for crashkernel CMA reservation | From: Sourabh Jain <sourabhjain@linux.ibm.com>
During a memory hot-remove event, the elfcorehdr is rebuilt to exclude
the removed memory. While updating the crash memory ranges for this
operation, the crash memory ranges array can become unsorted. This
happens because remove_mem_range() may split a memory range into t... | {
"author": "Jinjie Ruan <ruanjinjie@huawei.com>",
"date": "Thu, 26 Feb 2026 21:04:33 +0800",
"is_openbsd": false,
"thread_id": "20260226130437.1867658-5-ruanjinjie@huawei.com.mbox.gz"
} |
lkml_critique | linux-riscv | The crash memory allocation, and the exclude of crashk_res, crashk_low_res
and crashk_cma memory are almost identical across different architectures,
This patch set handle them in crash core in a general way, which eliminate
a lot of duplication code.
And add support for crashkernel CMA reservation for arm64 and riscv... | null | null | null | [PATCH v7 0/5] arm64/riscv: Add support for crashkernel CMA reservation | The crash memory exclude of crashk_res and crashk_cma memory on powerpc
are almost identical to the generic crash_exclude_core_ranges().
By introducing the architecture-specific arch_crash_exclude_mem_range()
function with a default implementation of crash_exclude_mem_range(),
and using crash_exclude_mem_range_guarded... | {
"author": "Jinjie Ruan <ruanjinjie@huawei.com>",
"date": "Thu, 26 Feb 2026 21:04:35 +0800",
"is_openbsd": false,
"thread_id": "20260226130437.1867658-5-ruanjinjie@huawei.com.mbox.gz"
} |
lkml_critique | linux-riscv | The crash memory allocation, and the exclude of crashk_res, crashk_low_res
and crashk_cma memory are almost identical across different architectures,
This patch set handle them in crash core in a general way, which eliminate
a lot of duplication code.
And add support for crashkernel CMA reservation for arm64 and riscv... | null | null | null | [PATCH v7 0/5] arm64/riscv: Add support for crashkernel CMA reservation | Commit 35c18f2933c5 ("Add a new optional ",cma" suffix to the
crashkernel= command line option") and commit ab475510e042 ("kdump:
implement reserve_crashkernel_cma") added CMA support for kdump
crashkernel reservation.
Crash kernel memory reservation wastes production resources if too
large, risks kdump failure if too... | {
"author": "Jinjie Ruan <ruanjinjie@huawei.com>",
"date": "Thu, 26 Feb 2026 21:04:36 +0800",
"is_openbsd": false,
"thread_id": "20260226130437.1867658-5-ruanjinjie@huawei.com.mbox.gz"
} |
lkml_critique | linux-riscv | The crash memory allocation, and the exclude of crashk_res, crashk_low_res
and crashk_cma memory are almost identical across different architectures,
This patch set handle them in crash core in a general way, which eliminate
a lot of duplication code.
And add support for crashkernel CMA reservation for arm64 and riscv... | null | null | null | [PATCH v7 0/5] arm64/riscv: Add support for crashkernel CMA reservation | Commit 35c18f2933c5 ("Add a new optional ",cma" suffix to the
crashkernel= command line option") and commit ab475510e042 ("kdump:
implement reserve_crashkernel_cma") added CMA support for kdump
crashkernel reservation. This allows the kernel to dynamically allocate
contiguous memory for crash dumping when needed, rathe... | {
"author": "Jinjie Ruan <ruanjinjie@huawei.com>",
"date": "Thu, 26 Feb 2026 21:04:37 +0800",
"is_openbsd": false,
"thread_id": "20260226130437.1867658-5-ruanjinjie@huawei.com.mbox.gz"
} |
lkml_critique | linux-riscv | The crash memory allocation, and the exclude of crashk_res, crashk_low_res
and crashk_cma memory are almost identical across different architectures,
This patch set handle them in crash core in a general way, which eliminate
a lot of duplication code.
And add support for crashkernel CMA reservation for arm64 and riscv... | null | null | null | [PATCH v7 0/5] arm64/riscv: Add support for crashkernel CMA reservation | The crash memory alloc, and the exclude of crashk_res, crashk_low_res
and crashk_cma memory are almost identical across different architectures,
handling them in the crash core would eliminate a lot of duplication, so
do them in the common code.
To achieve the above goal, three architecture-specific functions are
intr... | {
"author": "Jinjie Ruan <ruanjinjie@huawei.com>",
"date": "Thu, 26 Feb 2026 21:04:34 +0800",
"is_openbsd": false,
"thread_id": "20260226130437.1867658-5-ruanjinjie@huawei.com.mbox.gz"
} |
lkml_critique | linux-riscv | The crash memory allocation, and the exclude of crashk_res, crashk_low_res
and crashk_cma memory are almost identical across different architectures,
This patch set handle them in crash core in a general way, which eliminate
a lot of duplication code.
And add support for crashkernel CMA reservation for arm64 and riscv... | null | null | null | [PATCH v7 0/5] arm64/riscv: Add support for crashkernel CMA reservation | On 26/02/26 18:34, Jinjie Ruan wrote:
update_crash_elfcorehdr() in arch/powerpc/kexec/crash.c still calls
crash_exclude_mem_range_guarded(), causing a build failure. ld:
arch/powerpc/kexec/crash.o: in function `update_crash_elfcorehdr':
/root/linux/arch/powerpc/kexec/crash.c:454: undefined reference to
`crash_exclu... | {
"author": "Sourabh Jain <sourabhjain@linux.ibm.com>",
"date": "Fri, 27 Feb 2026 20:13:56 +0530",
"is_openbsd": false,
"thread_id": "20260226130437.1867658-5-ruanjinjie@huawei.com.mbox.gz"
} |
lkml_critique | linux-riscv | The crash memory allocation, and the exclude of crashk_res, crashk_low_res
and crashk_cma memory are almost identical across different architectures,
This patch set handle them in crash core in a general way, which eliminate
a lot of duplication code.
And add support for crashkernel CMA reservation for arm64 and riscv... | null | null | null | [PATCH v7 0/5] arm64/riscv: Add support for crashkernel CMA reservation | Resend of:
https://lore.kernel.org/all/19cf18b5-362d-4ff2-8b85-e2e72809250c@linux.ibm.com/
On 26/02/26 18:34, Jinjie Ruan wrote:
update_crash_elfcorehdr() in arch/powerpc/kexec/crash.c still calls
crash_exclude_mem_range_guarded(), causing a build failure.
ld: arch/powerpc/kexec/crash.o: in function `update_crash_... | {
"author": "Sourabh Jain <sourabhjain@linux.ibm.com>",
"date": "Fri, 27 Feb 2026 20:20:34 +0530",
"is_openbsd": false,
"thread_id": "20260226130437.1867658-5-ruanjinjie@huawei.com.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Hi all,
the XOR library used for the RAID5 parity is a bit of a mess right now.
The main file sits in crypto/ despite not being cryptography and not
using the crypto API, with the generic implementations sitting in
include/asm-generic and the arch implementations sitting in an asm/
header in theory. The latter doesn'... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:12 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | XOR_SELECT_TEMPLATE is only ever called with a NULL argument, so all the
ifdef'ery doesn't do anything. With our without this, the time travel
mode should work fine on CPUs that support AVX2, as the AVX2
implementation is forced in this case, and won't work otherwise.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:15 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Move the RAID XOR code to lib/raid/ as it has nothing to do with the
crypto API.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
crypto/Kconfig | 2 --
crypto/Makefile | 1 -
lib/Kconfig | 1 +
lib/Makefile | 2 +... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:16 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Originally, the XOR code benchmarked all algorithms at load time, but
it has since then been hacked multiple times to allow forcing an
algorithm, and then commit 524ccdbdfb52 ("crypto: xor - defer load time
benchmark to a later time") changed the logic to a two-step process
or registration and benchmarking, but only wh... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:18 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Most of the optimized xor_blocks versions require FPU/vector registers,
which generally are not supported in interrupt context.
Both callers already are in user context, so enforce this at the highest
level.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
crypto/xor.c | 2 ++
1 file changed, 2 insertions(+)
diff ... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:13 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Update the to of file comment to be correct and non-redundant, and drop
the unused BH_TRACE define.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
lib/raid/xor/xor-core.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/lib/raid/xor/xor-core.c b/lib/raid/xor/xor-core.c
index 864f3604e867..28... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:17 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Keep xor.h for the public API, and split the struct xor_block_template
definition that is only needed by the xor.ko core and
architecture-specific optimizations into a separate xor_impl.h header.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/lib/xor-neon.c | 1 +
arch/s390/lib/xor.c | 2... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:19 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Drop the pretty confusing historic XOR_TRY_TEMPLATES and
XOR_SELECT_TEMPLATE, and instead let the architectures provide a
arch_xor_init that calls either xor_register to register candidates
or xor_force to force a specific implementation.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/alpha/include/asm/xor.h ... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:20 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Move the generic implementations from asm-generic/xor.h to
per-implementaion .c files in lib/raid.
Note that this would cause the second xor_block_8regs instance created by
arch/arm/lib/xor-neon.c to be generated instead of discarded as dead
code, so add a NO_TEMPLATE symbol to disable it for this case.
Signed-off-by... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:21 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Move the optimized XOR code out of line into lib/raid.
Note that the giant inline assembly block might be better off as a
separate assembly source file now, but I'll leave that to the alpha
maintainers.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/alpha/include/asm/xor.h | 853 +----------------------------... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:22 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Move the optimized XOR into lib/raid and include it it in the main
xor.ko instead of building a separate module for it.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 190 +-----------------
arch/arm/lib/Makefile | 5 -
lib/raid/xor/Makefile... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:23 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Move the optimized XOR into lib/raid and include it it in the main
xor.ko instead of building a separate module for it.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm64/include/asm/xor.h | 58 +------------------
arch/arm64/lib/Makefile | 6 --
lib/raid/xor/Makefile... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:24 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Move the optimized XOR into lib/raid and include it it in xor.ko
instead of always building it into the main kernel image.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/loongarch/include/asm/xor.h | 24 ++----------
arch/loongarch/include/asm/xor_simd.h | 34 ----------------
arch/loonga... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:25 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Move the optimized XOR into lib/raid and include it it in xor.ko
instead of always building it into the main kernel image.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/powerpc/include/asm/xor.h | 17 +----
arch/powerpc/include/asm/xor_altivec.h | 22 ------
arch/powerpc/lib/Makefile ... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:26 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Move the optimized XOR into lib/raid and include it it in xor.ko
instead of always building it into the main kernel image.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/riscv/include/asm/xor.h | 54 +------------------
arch/riscv/lib/Makefile | 1 -
lib/raid/xor/Makefile... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:27 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Move the optimized XOR into lib/raid and include it it in xor.ko
instead of unconditionally building it into the main kernel image.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/s390/lib/Makefile | 2 +-
lib/raid/xor/Makefile | 1 +
{arch/s390/lib => lib/raid/xor/s390... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:29 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Move the optimized XOR into lib/raid and include it it in xor.ko
instead of always building it into the main kernel image.
This also splits the sparc64 code into separate files for the two
implementations.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/sparc/include/asm/asm-prototypes.h | 1 -
arch/s... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:28 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Remove the inner xor_block_templates, and instead have two separate
actual template that call into the neon-enabled compilation unit.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm64/include/asm/xor.h | 13 ++--
lib/raid/xor/arm64/xor-neon-glue.c | 95 +++++++++++++++---------------
lib/raid/xor/arm... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:31 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Move the optimized XOR code out of line into lib/raid.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/x86/include/asm/xor.h | 518 ++----------------
arch/x86/include/asm/xor_64.h | 32 --
lib/raid/xor/Makefile | 8 +
.../xor_avx.h => lib/raid/xor/... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:30 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Replace use of the loop around xor_blocks with the easier to use xor_gen
API.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
crypto/async_tx/async_xor.c | 16 ++--------------
1 file changed, 2 insertions(+), 14 deletions(-)
diff --git a/crypto/async_tx/async_xor.c b/crypto/async_tx/async_xor.c
index 2c499654a36c... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:34 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Move the asm/xor.h headers to lib/raid/xor/$(SRCARCH)/xor_arch.h and
include/linux/raid/xor_impl.h to lib/raid/xor/xor_impl.h so that the
xor.ko module implementation is self-contained in lib/raid/.
As this remove the asm-generic mechanism a new kconfig symbol is
added to indicate that a architecture-specific implemen... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:32 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | xor_blocks is very annoying to use, because it is limited to 4 + 1
sources / destinations, has an odd argument order and is completely
undocumented.
Lift the code that loops around it from btrfs and async_tx/async_xor into
common code under the name xor_gen and properly document it.
Signed-off-by: Christoph Hellwig <... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:33 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Use the new xor_gen helper instead of open coding the loop around
xor_blocks. This helper is very similar to the existing run_xor helper
in btrfs, except that the destination buffer is passed explicitly.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
fs/btrfs/raid56.c | 27 ++++-----------------------
1 file chan... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:35 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Avoid the indirect call for xor_generation by using a static_call.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
lib/raid/xor/xor-32regs.c | 2 +-
lib/raid/xor/xor-core.c | 29 ++++++++++++++---------------
lib/raid/xor/xor_impl.h | 4 ++++
3 files changed, 19 insertions(+), 16 deletions(-)
diff --git a/li... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:37 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | Currently the high-level xor code chunks up all operations into small
units for only up to 1 + 4 vectors, and passes it to four different
methods. This means the FPU/vector context is entered and left a lot
for wide stripes, and a lot of indirect expensive indirect calls are
performed. Switch to passing the entire ge... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Thu, 26 Feb 2026 07:10:36 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | On Thu, Feb 26, 2026, at 16:10, Christoph Hellwig wrote:
Acked-by: Arnd Bergmann <arnd@arndb.de> # for asm-generic
The #include is slightly ugly, but I see it gets better in a later patch,
and is clearly worth it either way.
The rest of the series looks good to me as well. I had a brief
look at each patch, but nothi... | {
"author": "\"Arnd Bergmann\" <arnd@arndb.de>",
"date": "Thu, 26 Feb 2026 16:40:21 +0100",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | On Thu, 26 Feb 2026 07:10:12 -0800 Christoph Hellwig <hch@lst.de> wrote:
Thanks, I'll add this to mm.git's mm-nonmm-unstable tree for some
testing in linux-next.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux... | {
"author": "Andrew Morton <akpm@linux-foundation.org>",
"date": "Thu, 26 Feb 2026 10:20:37 -0800",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | ----- Ursprüngliche Mail -----
IIRC Johannes added XOR_SELECT_TEMPLATE() here to skip
the template selection logic because it didn't work with time travel mode.
Johannes, can you please test whether this change does not break
time travel mode?
Thanks,
//richard
_______________________________________________
linux-... | {
"author": "Richard Weinberger <richard@nod.at>",
"date": "Thu, 26 Feb 2026 22:45:26 +0100 (CET)",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | On Thu, Feb 26, 2026 at 10:45:26PM +0100, Richard Weinberger wrote:
I'm pretty sure that was the intent, but as I wrote above it worked
and still works on AVX-supporting CPUs by chance, and already doesn't
on older CPUs, and unless my git blaming went wrong someewhere already
didn't when this was originally added.
_... | {
"author": "hch <hch@lst.de>",
"date": "Thu, 26 Feb 2026 23:00:38 +0100",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | On Thu, 2026-02-26 at 22:45 +0100, Richard Weinberger wrote:
It does work, even if it reports nonsense (as you'd expect):
xor: measuring software checksum speed
prefetch64-sse : 12816000 MB/sec
sse : 12816000 MB/sec
xor: using function: prefetch64-sse (12816000 MB/sec)
I think it works now because... | {
"author": "Johannes Berg <johannes@sipsolutions.net>",
"date": "Fri, 27 Feb 2026 08:39:47 +0100",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | On Thu, Feb 26, 2026 at 07:10:29AM -0800, Christoph Hellwig wrote:
FWIW:
Acked-by: Heiko Carstens <hca@linux.ibm.com>
However, I just had a look at the s390 implementation and just saw that the
inline assembly constraints for xor_xc_2() are incorrect. "bytes", "p1",
and "p2" are input operands, while all three of the... | {
"author": "Heiko Carstens <hca@linux.ibm.com>",
"date": "Fri, 27 Feb 2026 10:09:59 +0100",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | On Fri, Feb 27, 2026 at 10:09:59AM +0100, Heiko Carstens wrote:
Two comments on that: I thin kin the long run simply moving the
implementation to a pure assembly file might be easier to maintain.
Also with this series you can now optimize for more than 5 stripes,
which should be the mormal case. I'll try to make sur... | {
"author": "Christoph Hellwig <hch@lst.de>",
"date": "Fri, 27 Feb 2026 15:13:11 +0100",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | On Thu, Feb 26, 2026 at 07:10:13AM -0800, Christoph Hellwig wrote:
Your changelog makes it sound like you want:
WARN_ON_ONCE(!in_task());
But perhaps something like so:
lockdep_assert_preempt_enabled();
Would do? That ensures we are in preemptible context, which is much the
same. That also ensures the cost of th... | {
"author": "Peter Zijlstra <peterz@infradead.org>",
"date": "Fri, 27 Feb 2026 15:24:55 +0100",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | On Thu, Feb 26, 2026 at 07:10:30AM -0800, Christoph Hellwig wrote:
I gotta ask, why lib/raid/xor/$arch/ instead of something like
arch/$arch/lib/xor ?
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Peter Zijlstra <peterz@infradead.org>",
"date": "Fri, 27 Feb 2026 15:30:16 +0100",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | xor_blocks can't be called from interrupt context, so remove the
handling for that.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/arm/include/asm/xor.h | 41 +++++++++++---------------------------
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/as... | null | null | null | [PATCH 02/25] arm/xor: remove in_interrupt() handling | On Thu, Feb 26, 2026 at 07:10:37AM -0800, Christoph Hellwig wrote:
Nice!
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Peter Zijlstra <peterz@infradead.org>",
"date": "Fri, 27 Feb 2026 15:36:06 +0100",
"is_openbsd": false,
"thread_id": "20260226151106.144735-5-hch@lst.de.mbox.gz"
} |
lkml_critique | linux-riscv | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Hi,
Order in which early memory reservation for hugetlb happens depends on
architecture, on configuration options and on command line parameters.
Some architectures rely on the core MM to call hugetlb_bootmem_alloc()
while others call it very early to allow pre-all... | null | null | null | [PATCH v3 00/29] arch, mm: consolidate hugetlb early reservation | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Move calculations of zone limits to a dedicated arch_zone_limits_init()
function.
Later MM core will use this function as an architecture specific callback
during nodes and zones initialization and thus there won't be a need to
call free_area_init() from every archi... | {
"author": "Mike Rapoport <rppt@kernel.org>",
"date": "Sun, 11 Jan 2026 10:20:35 +0200",
"is_openbsd": false,
"thread_id": "87seaohgf5.ritesh.list@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Hi,
Order in which early memory reservation for hugetlb happens depends on
architecture, on configuration options and on command line parameters.
Some architectures rely on the core MM to call hugetlb_bootmem_alloc()
while others call it very early to allow pre-all... | null | null | null | [PATCH v3 00/29] arch, mm: consolidate hugetlb early reservation | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Move calculations of zone limits to a dedicated arch_zone_limits_init()
function.
Later MM core will use this function as an architecture specific callback
during nodes and zones initialization and thus there won't be a need to
call free_area_init() from every archi... | {
"author": "Mike Rapoport <rppt@kernel.org>",
"date": "Sun, 11 Jan 2026 10:20:36 +0200",
"is_openbsd": false,
"thread_id": "87seaohgf5.ritesh.list@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Hi,
Order in which early memory reservation for hugetlb happens depends on
architecture, on configuration options and on command line parameters.
Some architectures rely on the core MM to call hugetlb_bootmem_alloc()
while others call it very early to allow pre-all... | null | null | null | [PATCH v3 00/29] arch, mm: consolidate hugetlb early reservation | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Move calculations of zone limits to a dedicated arch_zone_limits_init()
function.
Later MM core will use this function as an architecture specific callback
during nodes and zones initialization and thus there won't be a need to
call free_area_init() from every archi... | {
"author": "Mike Rapoport <rppt@kernel.org>",
"date": "Sun, 11 Jan 2026 10:20:37 +0200",
"is_openbsd": false,
"thread_id": "87seaohgf5.ritesh.list@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Hi,
Order in which early memory reservation for hugetlb happens depends on
architecture, on configuration options and on command line parameters.
Some architectures rely on the core MM to call hugetlb_bootmem_alloc()
while others call it very early to allow pre-all... | null | null | null | [PATCH v3 00/29] arch, mm: consolidate hugetlb early reservation | From: Klara Modin <klarasmodin@gmail.com>
Unlike most architectures, arm keeps a struct page pointer to the
empty_zero_page and to initialize it requires conversion of a virtual
address to page which makes it necessary to have memory map initialized
before creating the empty_zero_page.
Make empty_zero_page a stataic ... | {
"author": "Mike Rapoport <rppt@kernel.org>",
"date": "Sun, 11 Jan 2026 10:20:38 +0200",
"is_openbsd": false,
"thread_id": "87seaohgf5.ritesh.list@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Hi,
Order in which early memory reservation for hugetlb happens depends on
architecture, on configuration options and on command line parameters.
Some architectures rely on the core MM to call hugetlb_bootmem_alloc()
while others call it very early to allow pre-all... | null | null | null | [PATCH v3 00/29] arch, mm: consolidate hugetlb early reservation | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Move calculations of zone limits to a dedicated arch_zone_limits_init()
function.
Later MM core will use this function as an architecture specific callback
during nodes and zones initialization and thus there won't be a need to
call free_area_init() from every archi... | {
"author": "Mike Rapoport <rppt@kernel.org>",
"date": "Sun, 11 Jan 2026 10:20:39 +0200",
"is_openbsd": false,
"thread_id": "87seaohgf5.ritesh.list@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Hi,
Order in which early memory reservation for hugetlb happens depends on
architecture, on configuration options and on command line parameters.
Some architectures rely on the core MM to call hugetlb_bootmem_alloc()
while others call it very early to allow pre-all... | null | null | null | [PATCH v3 00/29] arch, mm: consolidate hugetlb early reservation | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Move calculations of zone limits to a dedicated arch_zone_limits_init()
function.
Later MM core will use this function as an architecture specific callback
during nodes and zones initialization and thus there won't be a need to
call free_area_init() from every archi... | {
"author": "Mike Rapoport <rppt@kernel.org>",
"date": "Sun, 11 Jan 2026 10:20:40 +0200",
"is_openbsd": false,
"thread_id": "87seaohgf5.ritesh.list@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Hi,
Order in which early memory reservation for hugetlb happens depends on
architecture, on configuration options and on command line parameters.
Some architectures rely on the core MM to call hugetlb_bootmem_alloc()
while others call it very early to allow pre-all... | null | null | null | [PATCH v3 00/29] arch, mm: consolidate hugetlb early reservation | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Move calculations of zone limits to a dedicated arch_zone_limits_init()
function.
Later MM core will use this function as an architecture specific callback
during nodes and zones initialization and thus there won't be a need to
call free_area_init() from every archi... | {
"author": "Mike Rapoport <rppt@kernel.org>",
"date": "Sun, 11 Jan 2026 10:20:41 +0200",
"is_openbsd": false,
"thread_id": "87seaohgf5.ritesh.list@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Hi,
Order in which early memory reservation for hugetlb happens depends on
architecture, on configuration options and on command line parameters.
Some architectures rely on the core MM to call hugetlb_bootmem_alloc()
while others call it very early to allow pre-all... | null | null | null | [PATCH v3 00/29] arch, mm: consolidate hugetlb early reservation | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Move calculations of zone limits to a dedicated arch_zone_limits_init()
function.
Later MM core will use this function as an architecture specific callback
during nodes and zones initialization and thus there won't be a need to
call free_area_init() from every archi... | {
"author": "Mike Rapoport <rppt@kernel.org>",
"date": "Sun, 11 Jan 2026 10:20:42 +0200",
"is_openbsd": false,
"thread_id": "87seaohgf5.ritesh.list@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Hi,
Order in which early memory reservation for hugetlb happens depends on
architecture, on configuration options and on command line parameters.
Some architectures rely on the core MM to call hugetlb_bootmem_alloc()
while others call it very early to allow pre-all... | null | null | null | [PATCH v3 00/29] arch, mm: consolidate hugetlb early reservation | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Move calculations of zone limits to a dedicated arch_zone_limits_init()
function.
Later MM core will use this function as an architecture specific callback
during nodes and zones initialization and thus there won't be a need to
call free_area_init() from every archi... | {
"author": "Mike Rapoport <rppt@kernel.org>",
"date": "Sun, 11 Jan 2026 10:20:43 +0200",
"is_openbsd": false,
"thread_id": "87seaohgf5.ritesh.list@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Hi,
Order in which early memory reservation for hugetlb happens depends on
architecture, on configuration options and on command line parameters.
Some architectures rely on the core MM to call hugetlb_bootmem_alloc()
while others call it very early to allow pre-all... | null | null | null | [PATCH v3 00/29] arch, mm: consolidate hugetlb early reservation | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Move calculations of zone limits to a dedicated arch_zone_limits_init()
function.
Later MM core will use this function as an architecture specific callback
during nodes and zones initialization and thus there won't be a need to
call free_area_init() from every archi... | {
"author": "Mike Rapoport <rppt@kernel.org>",
"date": "Sun, 11 Jan 2026 10:20:44 +0200",
"is_openbsd": false,
"thread_id": "87seaohgf5.ritesh.list@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Hi,
Order in which early memory reservation for hugetlb happens depends on
architecture, on configuration options and on command line parameters.
Some architectures rely on the core MM to call hugetlb_bootmem_alloc()
while others call it very early to allow pre-all... | null | null | null | [PATCH v3 00/29] arch, mm: consolidate hugetlb early reservation | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Move calculations of zone limits to a dedicated arch_zone_limits_init()
function.
Later MM core will use this function as an architecture specific callback
during nodes and zones initialization and thus there won't be a need to
call free_area_init() from every archi... | {
"author": "Mike Rapoport <rppt@kernel.org>",
"date": "Sun, 11 Jan 2026 10:20:45 +0200",
"is_openbsd": false,
"thread_id": "87seaohgf5.ritesh.list@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Hi,
Order in which early memory reservation for hugetlb happens depends on
architecture, on configuration options and on command line parameters.
Some architectures rely on the core MM to call hugetlb_bootmem_alloc()
while others call it very early to allow pre-all... | null | null | null | [PATCH v3 00/29] arch, mm: consolidate hugetlb early reservation | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Move calculations of zone limits to a dedicated arch_zone_limits_init()
function.
Later MM core will use this function as an architecture specific callback
during nodes and zones initialization and thus there won't be a need to
call free_area_init() from every archi... | {
"author": "Mike Rapoport <rppt@kernel.org>",
"date": "Sun, 11 Jan 2026 10:20:46 +0200",
"is_openbsd": false,
"thread_id": "87seaohgf5.ritesh.list@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Hi,
Order in which early memory reservation for hugetlb happens depends on
architecture, on configuration options and on command line parameters.
Some architectures rely on the core MM to call hugetlb_bootmem_alloc()
while others call it very early to allow pre-all... | null | null | null | [PATCH v3 00/29] arch, mm: consolidate hugetlb early reservation | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Move calculations of zone limits to a dedicated arch_zone_limits_init()
function.
Later MM core will use this function as an architecture specific callback
during nodes and zones initialization and thus there won't be a need to
call free_area_init() from every archi... | {
"author": "Mike Rapoport <rppt@kernel.org>",
"date": "Sun, 11 Jan 2026 10:20:47 +0200",
"is_openbsd": false,
"thread_id": "87seaohgf5.ritesh.list@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Hi,
Order in which early memory reservation for hugetlb happens depends on
architecture, on configuration options and on command line parameters.
Some architectures rely on the core MM to call hugetlb_bootmem_alloc()
while others call it very early to allow pre-all... | null | null | null | [PATCH v3 00/29] arch, mm: consolidate hugetlb early reservation | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Move calculations of zone limits to a dedicated arch_zone_limits_init()
function.
Later MM core will use this function as an architecture specific callback
during nodes and zones initialization and thus there won't be a need to
call free_area_init() from every archi... | {
"author": "Mike Rapoport <rppt@kernel.org>",
"date": "Sun, 11 Jan 2026 10:20:48 +0200",
"is_openbsd": false,
"thread_id": "87seaohgf5.ritesh.list@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Hi,
Order in which early memory reservation for hugetlb happens depends on
architecture, on configuration options and on command line parameters.
Some architectures rely on the core MM to call hugetlb_bootmem_alloc()
while others call it very early to allow pre-all... | null | null | null | [PATCH v3 00/29] arch, mm: consolidate hugetlb early reservation | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Move calculations of zone limits to a dedicated arch_zone_limits_init()
function.
Later MM core will use this function as an architecture specific callback
during nodes and zones initialization and thus there won't be a need to
call free_area_init() from every archi... | {
"author": "Mike Rapoport <rppt@kernel.org>",
"date": "Sun, 11 Jan 2026 10:20:49 +0200",
"is_openbsd": false,
"thread_id": "87seaohgf5.ritesh.list@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Hi,
Order in which early memory reservation for hugetlb happens depends on
architecture, on configuration options and on command line parameters.
Some architectures rely on the core MM to call hugetlb_bootmem_alloc()
while others call it very early to allow pre-all... | null | null | null | [PATCH v3 00/29] arch, mm: consolidate hugetlb early reservation | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Move calculations of zone limits to a dedicated arch_zone_limits_init()
function.
Later MM core will use this function as an architecture specific callback
during nodes and zones initialization and thus there won't be a need to
call free_area_init() from every archi... | {
"author": "Mike Rapoport <rppt@kernel.org>",
"date": "Sun, 11 Jan 2026 10:20:50 +0200",
"is_openbsd": false,
"thread_id": "87seaohgf5.ritesh.list@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Hi,
Order in which early memory reservation for hugetlb happens depends on
architecture, on configuration options and on command line parameters.
Some architectures rely on the core MM to call hugetlb_bootmem_alloc()
while others call it very early to allow pre-all... | null | null | null | [PATCH v3 00/29] arch, mm: consolidate hugetlb early reservation | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Move calculations of zone limits to a dedicated arch_zone_limits_init()
function.
Later MM core will use this function as an architecture specific callback
during nodes and zones initialization and thus there won't be a need to
call free_area_init() from every archi... | {
"author": "Mike Rapoport <rppt@kernel.org>",
"date": "Sun, 11 Jan 2026 10:20:51 +0200",
"is_openbsd": false,
"thread_id": "87seaohgf5.ritesh.list@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Hi,
Order in which early memory reservation for hugetlb happens depends on
architecture, on configuration options and on command line parameters.
Some architectures rely on the core MM to call hugetlb_bootmem_alloc()
while others call it very early to allow pre-all... | null | null | null | [PATCH v3 00/29] arch, mm: consolidate hugetlb early reservation | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Move calculations of zone limits to a dedicated arch_zone_limits_init()
function.
Later MM core will use this function as an architecture specific callback
during nodes and zones initialization and thus there won't be a need to
call free_area_init() from every archi... | {
"author": "Mike Rapoport <rppt@kernel.org>",
"date": "Sun, 11 Jan 2026 10:20:52 +0200",
"is_openbsd": false,
"thread_id": "87seaohgf5.ritesh.list@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Hi,
Order in which early memory reservation for hugetlb happens depends on
architecture, on configuration options and on command line parameters.
Some architectures rely on the core MM to call hugetlb_bootmem_alloc()
while others call it very early to allow pre-all... | null | null | null | [PATCH v3 00/29] arch, mm: consolidate hugetlb early reservation | From: "Mike Rapoport (Microsoft)" <rppt@kernel.org>
Move calculations of zone limits to a dedicated arch_zone_limits_init()
function.
Later MM core will use this function as an architecture specific callback
during nodes and zones initialization and thus there won't be a need to
call free_area_init() from every archi... | {
"author": "Mike Rapoport <rppt@kernel.org>",
"date": "Sun, 11 Jan 2026 10:20:53 +0200",
"is_openbsd": false,
"thread_id": "87seaohgf5.ritesh.list@gmail.com.mbox.gz"
} |
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