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values | subject large_stringclasses 418
values | critique large_stringlengths 101 1.26M ⌀ | metadata dict |
|---|---|---|---|---|---|---|---|---|
lkml_critique | linux-riscv | Hi,
arm64, riscv and x86 all implement shadow stack support and use a
similar pattern for mapping the user shadow stack (originally cloned
from x86). Extract this common pattern into a shared helper -
vm_mmap_shadow_stack().
Patch 1 introduces vm_mmap_shadow_stack() in mm/util.c, which wraps
do_mmap() with the flags ... | null | null | null | [PATCH 0/5] mm: arch/shstk: Common shadow stack mapping helper and VM_NOHUGEPAGE | Replace the arm64 map_shadow_stack() content with a call to
vm_mmap_shadow_stack().
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
---
arch/arm64/mm/gcs.c | 14 +-------------
1 file changed, ... | {
"author": "Catalin Marinas <catalin.marinas@arm.com>",
"date": "Tue, 24 Feb 2026 17:57:54 +0000",
"is_openbsd": false,
"thread_id": "20260224175800.2500729-1-catalin.marinas@arm.com.mbox.gz"
} |
lkml_critique | linux-riscv | Hi,
arm64, riscv and x86 all implement shadow stack support and use a
similar pattern for mapping the user shadow stack (originally cloned
from x86). Extract this common pattern into a shared helper -
vm_mmap_shadow_stack().
Patch 1 introduces vm_mmap_shadow_stack() in mm/util.c, which wraps
do_mmap() with the flags ... | null | null | null | [PATCH 0/5] mm: arch/shstk: Common shadow stack mapping helper and VM_NOHUGEPAGE | Replace part of the allocate_shadow_stack() content with a call to
vm_mmap_shadow_stack().
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Paul Walmsley <pjw@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Alexandre Ghiti <alex@ghiti.fr>
Cc: Deepak Gupta <debu... | {
"author": "Catalin Marinas <catalin.marinas@arm.com>",
"date": "Tue, 24 Feb 2026 17:57:55 +0000",
"is_openbsd": false,
"thread_id": "20260224175800.2500729-1-catalin.marinas@arm.com.mbox.gz"
} |
lkml_critique | linux-riscv | Hi,
arm64, riscv and x86 all implement shadow stack support and use a
similar pattern for mapping the user shadow stack (originally cloned
from x86). Extract this common pattern into a shared helper -
vm_mmap_shadow_stack().
Patch 1 introduces vm_mmap_shadow_stack() in mm/util.c, which wraps
do_mmap() with the flags ... | null | null | null | [PATCH 0/5] mm: arch/shstk: Common shadow stack mapping helper and VM_NOHUGEPAGE | Replace part of the x86 alloc_shstk() content with a call to
vm_mmap_shadow_stack().
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Thomas Gleixner <tglx@kernel.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: H. Peter Anvin <hpa... | {
"author": "Catalin Marinas <catalin.marinas@arm.com>",
"date": "Tue, 24 Feb 2026 17:57:56 +0000",
"is_openbsd": false,
"thread_id": "20260224175800.2500729-1-catalin.marinas@arm.com.mbox.gz"
} |
lkml_critique | linux-riscv | Hi,
arm64, riscv and x86 all implement shadow stack support and use a
similar pattern for mapping the user shadow stack (originally cloned
from x86). Extract this common pattern into a shared helper -
vm_mmap_shadow_stack().
Patch 1 introduces vm_mmap_shadow_stack() in mm/util.c, which wraps
do_mmap() with the flags ... | null | null | null | [PATCH 0/5] mm: arch/shstk: Common shadow stack mapping helper and VM_NOHUGEPAGE | The default shadow stack size allocated on first prctl() for the main
thread or subsequently on clone() is either half of RLIMIT_STACK or half
of a thread's stack size (for arm64). Both of these are likely to be
suitable for a THP allocation and the kernel is more aggressive in
creating such mappings. However, it does ... | {
"author": "Catalin Marinas <catalin.marinas@arm.com>",
"date": "Tue, 24 Feb 2026 17:57:57 +0000",
"is_openbsd": false,
"thread_id": "20260224175800.2500729-1-catalin.marinas@arm.com.mbox.gz"
} |
lkml_critique | linux-riscv | Hi,
arm64, riscv and x86 all implement shadow stack support and use a
similar pattern for mapping the user shadow stack (originally cloned
from x86). Extract this common pattern into a shared helper -
vm_mmap_shadow_stack().
Patch 1 introduces vm_mmap_shadow_stack() in mm/util.c, which wraps
do_mmap() with the flags ... | null | null | null | [PATCH 0/5] mm: arch/shstk: Common shadow stack mapping helper and VM_NOHUGEPAGE | On Tue, 2026-02-24 at 17:57 +0000, Catalin Marinas wrote:
I ran it through the selftest. It would be nice to have a bit more information
in the log, like that there is no functional change. Otherwise,
Reviewed-by: Rick Edgecombe <rick.p.edgecombe@intel.com>
Tested-by: Rick Edgecombe <rick.p.edgecombe@intel.com>
___... | {
"author": "\"Edgecombe, Rick P\" <rick.p.edgecombe@intel.com>",
"date": "Tue, 24 Feb 2026 19:47:14 +0000",
"is_openbsd": false,
"thread_id": "20260224175800.2500729-1-catalin.marinas@arm.com.mbox.gz"
} |
lkml_critique | linux-riscv | Hi,
arm64, riscv and x86 all implement shadow stack support and use a
similar pattern for mapping the user shadow stack (originally cloned
from x86). Extract this common pattern into a shared helper -
vm_mmap_shadow_stack().
Patch 1 introduces vm_mmap_shadow_stack() in mm/util.c, which wraps
do_mmap() with the flags ... | null | null | null | [PATCH 0/5] mm: arch/shstk: Common shadow stack mapping helper and VM_NOHUGEPAGE | On Tue, 2026-02-24 at 17:57 +0000, Catalin Marinas wrote:
We allow mprotect()ing shadow stack memory with PROT_WRITE to set or clear
shadow stack type of writability. So PROT_WRITE doesn't even imply normal
writable memory in the real mmap() syscall. I agree the code is clearer with
this change.
Why does it need to ... | {
"author": "\"Edgecombe, Rick P\" <rick.p.edgecombe@intel.com>",
"date": "Tue, 24 Feb 2026 19:47:10 +0000",
"is_openbsd": false,
"thread_id": "20260224175800.2500729-1-catalin.marinas@arm.com.mbox.gz"
} |
lkml_critique | linux-riscv | Hi,
arm64, riscv and x86 all implement shadow stack support and use a
similar pattern for mapping the user shadow stack (originally cloned
from x86). Extract this common pattern into a shared helper -
vm_mmap_shadow_stack().
Patch 1 introduces vm_mmap_shadow_stack() in mm/util.c, which wraps
do_mmap() with the flags ... | null | null | null | [PATCH 0/5] mm: arch/shstk: Common shadow stack mapping helper and VM_NOHUGEPAGE | + Kito, Jesse, Valentin and Heinrich.
I had to rebuild toolchain by bumping up prctl (prctl conflict in 7.0 merge led
to landing pad prctls bumping by 1)
Jesse/Kito,
So you might want to do that as well before sending out next iteration of libc
changes.
Rest inline.
On Tue, Feb 24, 2026 at 05:57:52PM +0000, Catali... | {
"author": "Deepak Gupta <debug@rivosinc.com>",
"date": "Tue, 24 Feb 2026 16:06:13 -0800",
"is_openbsd": false,
"thread_id": "20260224175800.2500729-1-catalin.marinas@arm.com.mbox.gz"
} |
lkml_critique | linux-riscv | Hi,
arm64, riscv and x86 all implement shadow stack support and use a
similar pattern for mapping the user shadow stack (originally cloned
from x86). Extract this common pattern into a shared helper -
vm_mmap_shadow_stack().
Patch 1 introduces vm_mmap_shadow_stack() in mm/util.c, which wraps
do_mmap() with the flags ... | null | null | null | [PATCH 0/5] mm: arch/shstk: Common shadow stack mapping helper and VM_NOHUGEPAGE | Hi Deepak,
On Tue, Feb 24, 2026 at 04:06:13PM -0800, Deepak Gupta wrote:
[...]
[...]
That's great, thanks!
--
Catalin
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Catalin Marinas <catalin.marinas@arm.com>",
"date": "Wed, 25 Feb 2026 08:08:41 +0000",
"is_openbsd": false,
"thread_id": "20260224175800.2500729-1-catalin.marinas@arm.com.mbox.gz"
} |
lkml_critique | linux-riscv | Hi,
arm64, riscv and x86 all implement shadow stack support and use a
similar pattern for mapping the user shadow stack (originally cloned
from x86). Extract this common pattern into a shared helper -
vm_mmap_shadow_stack().
Patch 1 introduces vm_mmap_shadow_stack() in mm/util.c, which wraps
do_mmap() with the flags ... | null | null | null | [PATCH 0/5] mm: arch/shstk: Common shadow stack mapping helper and VM_NOHUGEPAGE | On Tue, Feb 24, 2026 at 07:47:14PM +0000, Edgecombe, Rick P wrote:
Good point, I'll add this to the other arch patches as well.
Thanks.
--
Catalin
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Catalin Marinas <catalin.marinas@arm.com>",
"date": "Wed, 25 Feb 2026 08:12:28 +0000",
"is_openbsd": false,
"thread_id": "20260224175800.2500729-1-catalin.marinas@arm.com.mbox.gz"
} |
lkml_critique | linux-riscv | Hi,
arm64, riscv and x86 all implement shadow stack support and use a
similar pattern for mapping the user shadow stack (originally cloned
from x86). Extract this common pattern into a shared helper -
vm_mmap_shadow_stack().
Patch 1 introduces vm_mmap_shadow_stack() in mm/util.c, which wraps
do_mmap() with the flags ... | null | null | null | [PATCH 0/5] mm: arch/shstk: Common shadow stack mapping helper and VM_NOHUGEPAGE | _______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Wed, 25 Feb 2026 12:25:59 +0000",
"is_openbsd": false,
"thread_id": "20260224175800.2500729-1-catalin.marinas@arm.com.mbox.gz"
} |
lkml_critique | linux-riscv | Hi,
arm64, riscv and x86 all implement shadow stack support and use a
similar pattern for mapping the user shadow stack (originally cloned
from x86). Extract this common pattern into a shared helper -
vm_mmap_shadow_stack().
Patch 1 introduces vm_mmap_shadow_stack() in mm/util.c, which wraps
do_mmap() with the flags ... | null | null | null | [PATCH 0/5] mm: arch/shstk: Common shadow stack mapping helper and VM_NOHUGEPAGE | On 2/24/26 18:57, Catalin Marinas wrote:
MM nowadays tends to use two tabs here.
And here as well.
Agreed that the ifdef for the function declaration is not required.
Acked-by: David Hildenbrand (Arm) <david@kernel.org>
--
Cheers,
David
_______________________________________________
linux-riscv mailing list
l... | {
"author": "\"David Hildenbrand (Arm)\" <david@kernel.org>",
"date": "Wed, 25 Feb 2026 14:32:37 +0100",
"is_openbsd": false,
"thread_id": "20260224175800.2500729-1-catalin.marinas@arm.com.mbox.gz"
} |
lkml_critique | linux-riscv | Hi,
arm64, riscv and x86 all implement shadow stack support and use a
similar pattern for mapping the user shadow stack (originally cloned
from x86). Extract this common pattern into a shared helper -
vm_mmap_shadow_stack().
Patch 1 introduces vm_mmap_shadow_stack() in mm/util.c, which wraps
do_mmap() with the flags ... | null | null | null | [PATCH 0/5] mm: arch/shstk: Common shadow stack mapping helper and VM_NOHUGEPAGE | On 2/24/26 18:57, Catalin Marinas wrote:
Reviewed-by: David Hildenbrand (Arm) <david@kernel.org>
--
Cheers,
David
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "\"David Hildenbrand (Arm)\" <david@kernel.org>",
"date": "Wed, 25 Feb 2026 14:32:51 +0100",
"is_openbsd": false,
"thread_id": "20260224175800.2500729-1-catalin.marinas@arm.com.mbox.gz"
} |
lkml_critique | linux-riscv | Hi,
arm64, riscv and x86 all implement shadow stack support and use a
similar pattern for mapping the user shadow stack (originally cloned
from x86). Extract this common pattern into a shared helper -
vm_mmap_shadow_stack().
Patch 1 introduces vm_mmap_shadow_stack() in mm/util.c, which wraps
do_mmap() with the flags ... | null | null | null | [PATCH 0/5] mm: arch/shstk: Common shadow stack mapping helper and VM_NOHUGEPAGE | On 2/24/26 18:57, Catalin Marinas wrote:
Acked-by: David Hildenbrand (Arm) <david@kernel.org>
--
Cheers,
David
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "\"David Hildenbrand (Arm)\" <david@kernel.org>",
"date": "Wed, 25 Feb 2026 14:34:44 +0100",
"is_openbsd": false,
"thread_id": "20260224175800.2500729-1-catalin.marinas@arm.com.mbox.gz"
} |
lkml_critique | linux-riscv | Hi,
arm64, riscv and x86 all implement shadow stack support and use a
similar pattern for mapping the user shadow stack (originally cloned
from x86). Extract this common pattern into a shared helper -
vm_mmap_shadow_stack().
Patch 1 introduces vm_mmap_shadow_stack() in mm/util.c, which wraps
do_mmap() with the flags ... | null | null | null | [PATCH 0/5] mm: arch/shstk: Common shadow stack mapping helper and VM_NOHUGEPAGE | On Wed, Feb 25, 2026 at 01:02:36PM +0000, Mark Brown wrote:
Thanks.
If the first access is a write, the kernel allocates a THP from the
start without subsequent splitting. Also since 6.13 (commit 1ced09e0331f
"mm: allocate THP on hugezeropage wp-fault"), we go for another THP on
write. It's still wasting memory and ... | {
"author": "Catalin Marinas <catalin.marinas@arm.com>",
"date": "Wed, 25 Feb 2026 15:51:20 +0000",
"is_openbsd": false,
"thread_id": "20260224175800.2500729-1-catalin.marinas@arm.com.mbox.gz"
} |
lkml_critique | linux-riscv | Introduce a compatible string for the USB2 PHY in SpacemiT K3 SoC. The IP
of USB2 PHY mostly shares the same functionalities with K1 SoC, while has
some register layout changes.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
Documentation/devicetree... | null | null | null | [PATCH v2 1/3] dt-bindings: phy: spacemit: k3: add USB2 PHY
support | Add USB2 PHY support for SpacemiT K3 SoC.
Register layout of handling USB disconnect operation has been changed,
So introducing a platform data to distinguish the different SoCs.
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
drivers/phy/spacemit/phy-k1-usb2.c | 34 +++++++++++++++++++++++++++++-----
1 file changed,... | {
"author": "Yixun Lan <dlan@kernel.org>",
"date": "Sat, 14 Feb 2026 20:29:16 +0800",
"is_openbsd": false,
"thread_id": "20260214-11-k3-usb2-phy-v2-0-6ed31e031ab4@kernel.org.mbox.gz"
} |
lkml_critique | linux-riscv | Introduce a compatible string for the USB2 PHY in SpacemiT K3 SoC. The IP
of USB2 PHY mostly shares the same functionalities with K1 SoC, while has
some register layout changes.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
Documentation/devicetree... | null | null | null | [PATCH v2 1/3] dt-bindings: phy: spacemit: k3: add USB2 PHY
support | A disconnect status BIT of USB2 PHY need to be cleared, otherwise
it will fail to work properly during next connection when devices
connect to roothub directly.
Fixes: fe4bc1a08638 ("phy: spacemit: support K1 USB2.0 PHY controller")
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
drivers/phy/spacemit/phy-k1-usb2.c | 1... | {
"author": "Yixun Lan <dlan@kernel.org>",
"date": "Sat, 14 Feb 2026 20:29:15 +0800",
"is_openbsd": false,
"thread_id": "20260214-11-k3-usb2-phy-v2-0-6ed31e031ab4@kernel.org.mbox.gz"
} |
lkml_critique | linux-riscv | Introduce a compatible string for the USB2 PHY in SpacemiT K3 SoC. The IP
of USB2 PHY mostly shares the same functionalities with K1 SoC, while has
some register layout changes.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
Documentation/devicetree... | null | null | null | [PATCH v2 1/3] dt-bindings: phy: spacemit: k3: add USB2 PHY
support | The series trys to add USB2 PHY support for SpacemiT K3 SoC,
while patch [2/3] implement a disconnect function which is
needed during next connection.
No DTS part has been inclueded in this series, instead I plan
to submit while adding USB host support.
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
Changes in v2:
- ... | {
"author": "Yixun Lan <dlan@kernel.org>",
"date": "Sat, 14 Feb 2026 20:29:13 +0800",
"is_openbsd": false,
"thread_id": "20260214-11-k3-usb2-phy-v2-0-6ed31e031ab4@kernel.org.mbox.gz"
} |
lkml_critique | linux-riscv | Introduce a compatible string for the USB2 PHY in SpacemiT K3 SoC. The IP
of USB2 PHY mostly shares the same functionalities with K1 SoC, while has
some register layout changes.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
Documentation/devicetree... | null | null | null | [PATCH v2 1/3] dt-bindings: phy: spacemit: k3: add USB2 PHY
support | On Sat, Feb 14, 2026 at 08:29:16PM +0800, Yixun Lan wrote:
Reviewed-by: Yao Zi <me@ziyao.cc>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Yao Zi <me@ziyao.cc>",
"date": "Mon, 16 Feb 2026 04:39:59 +0000",
"is_openbsd": false,
"thread_id": "20260214-11-k3-usb2-phy-v2-0-6ed31e031ab4@kernel.org.mbox.gz"
} |
lkml_critique | linux-riscv | Introduce a compatible string for the USB2 PHY in SpacemiT K3 SoC. The IP
of USB2 PHY mostly shares the same functionalities with K1 SoC, while has
some register layout changes.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
Documentation/devicetree... | null | null | null | [PATCH v2 1/3] dt-bindings: phy: spacemit: k3: add USB2 PHY
support | Hello Yixun,
On Sat, Feb 14, 2026 at 08:29:15PM +0800, Yixun Lan wrote:
Please align function arguments to the open parenthesis.
Since we are in the merge window, it is likely that new features will
not be picked up at this stage.
But this seems to be a fix for existing SpacemiT K1 support, currently
in the linux-p... | {
"author": "Vladimir Oltean <olteanv@gmail.com>",
"date": "Mon, 16 Feb 2026 11:01:12 +0200",
"is_openbsd": false,
"thread_id": "20260214-11-k3-usb2-phy-v2-0-6ed31e031ab4@kernel.org.mbox.gz"
} |
lkml_critique | linux-riscv | Introduce a compatible string for the USB2 PHY in SpacemiT K3 SoC. The IP
of USB2 PHY mostly shares the same functionalities with K1 SoC, while has
some register layout changes.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
Documentation/devicetree... | null | null | null | [PATCH v2 1/3] dt-bindings: phy: spacemit: k3: add USB2 PHY
support | On 11:01 Mon 16 Feb , Vladimir Oltean wrote:
Ok
Sure, no problem and I expect this is normal..
Ok, done
http://lore.kernel.org/r/20260216152653.25244-1-dlan@kernel.org
will do once new -rc1 is tagged
--
Yixun Lan (dlan)
_______________________________________________
linux-riscv mailing list
linux-riscv@lists... | {
"author": "Yixun Lan <dlan@gentoo.org>",
"date": "Mon, 16 Feb 2026 23:29:54 +0800",
"is_openbsd": false,
"thread_id": "20260214-11-k3-usb2-phy-v2-0-6ed31e031ab4@kernel.org.mbox.gz"
} |
lkml_critique | linux-riscv | Introduce a compatible string for the USB2 PHY in SpacemiT K3 SoC. The IP
of USB2 PHY mostly shares the same functionalities with K1 SoC, while has
some register layout changes.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
Documentation/devicetree... | null | null | null | [PATCH v2 1/3] dt-bindings: phy: spacemit: k3: add USB2 PHY
support | On 14-02-26, 20:29, Yixun Lan wrote:
Please match this with preceding open parenthesis
--
~Vinod
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Vinod Koul <vkoul@kernel.org>",
"date": "Fri, 27 Feb 2026 20:29:43 +0530",
"is_openbsd": false,
"thread_id": "20260214-11-k3-usb2-phy-v2-0-6ed31e031ab4@kernel.org.mbox.gz"
} |
lkml_critique | linux-riscv | This patch series adds basic audio support for Sophgo CV1800B,
as used on boards such as the Milk-V Duo.
The series introduces the I2S controller driver,
the DAC and ADC codec drivers, corresponding DT bindings,
and DTS updates to wire the components together.
The implementation is based on vendor documentation
and te... | null | null | null | [PATCH v4 0/6] ASoC: sophgo: add CV1800 I2S controllers support | There are 4 TDM controllers on the SoC. Each controller can receive or
transmit data over DMA. The dma it self has 8 channels.
Each channel can be connected only to a specific i2s node. But each
of dma channel can have multiple purposes so in order to save dma
channels the configurations allows to use tx and rx, only r... | {
"author": "\"Anton D. Stavinskii\" <stavinsky@gmail.com>",
"date": "Tue, 20 Jan 2026 23:06:03 +0400",
"is_openbsd": false,
"thread_id": "aZ939evsOs6nCd5I@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | This patch series adds basic audio support for Sophgo CV1800B,
as used on boards such as the Milk-V Duo.
The series introduces the I2S controller driver,
the DAC and ADC codec drivers, corresponding DT bindings,
and DTS updates to wire the components together.
The implementation is based on vendor documentation
and te... | null | null | null | [PATCH v4 0/6] ASoC: sophgo: add CV1800 I2S controllers support | The actual CPU DAI controller. The driver can be used with
simple-audio-card. It respects fixed clock configuration
from simple-audio-card. The card driver can request direction out,
this will be interpreted as mclk out, the clock which can be used
in other CPU or codecs. For example I2S3 generates clock for ADC.
I2S w... | {
"author": "\"Anton D. Stavinskii\" <stavinsky@gmail.com>",
"date": "Tue, 20 Jan 2026 23:06:04 +0400",
"is_openbsd": false,
"thread_id": "aZ939evsOs6nCd5I@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | This patch series adds basic audio support for Sophgo CV1800B,
as used on boards such as the Milk-V Duo.
The series introduces the I2S controller driver,
the DAC and ADC codec drivers, corresponding DT bindings,
and DTS updates to wire the components together.
The implementation is based on vendor documentation
and te... | null | null | null | [PATCH v4 0/6] ASoC: sophgo: add CV1800 I2S controllers support | Document the internal ADC and DAC audio codecs integrated
in the Sophgo CV1800B SoC.
Signed-off-by: Anton D. Stavinskii <stavinsky@gmail.com>
---
.../bindings/sound/sophgo,cv1800b-codecs.yaml | 46 ++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/sophg... | {
"author": "\"Anton D. Stavinskii\" <stavinsky@gmail.com>",
"date": "Tue, 20 Jan 2026 23:06:05 +0400",
"is_openbsd": false,
"thread_id": "aZ939evsOs6nCd5I@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | This patch series adds basic audio support for Sophgo CV1800B,
as used on boards such as the Milk-V Duo.
The series introduces the I2S controller driver,
the DAC and ADC codec drivers, corresponding DT bindings,
and DTS updates to wire the components together.
The implementation is based on vendor documentation
and te... | null | null | null | [PATCH v4 0/6] ASoC: sophgo: add CV1800 I2S controllers support | Codec DAI endpoint for RXADC + basic controls.
THe codec have basic volume control. Which is
imlemented by lookup table for simplicity.
The codec expects set_sysclk callback to
adjust internal mclk divider.
Signed-off-by: Anton D. Stavinskii <stavinsky@gmail.com>
---
sound/soc/sophgo/Kconfig | 12 ++
sou... | {
"author": "\"Anton D. Stavinskii\" <stavinsky@gmail.com>",
"date": "Tue, 20 Jan 2026 23:06:06 +0400",
"is_openbsd": false,
"thread_id": "aZ939evsOs6nCd5I@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | This patch series adds basic audio support for Sophgo CV1800B,
as used on boards such as the Milk-V Duo.
The series introduces the I2S controller driver,
the DAC and ADC codec drivers, corresponding DT bindings,
and DTS updates to wire the components together.
The implementation is based on vendor documentation
and te... | null | null | null | [PATCH v4 0/6] ASoC: sophgo: add CV1800 I2S controllers support | Codec DAI endpoint for TXDAC. The codec does only a few things
- set up decimation
- enable codec and I2S output
- ensures the driver doesn't have dac overwrite enabled. (unmute the
output)
Signed-off-by: Anton D. Stavinskii <stavinsky@gmail.com>
---
sound/soc/sophgo/Kconfig | 11 +-
sound/soc/sophgo/M... | {
"author": "\"Anton D. Stavinskii\" <stavinsky@gmail.com>",
"date": "Tue, 20 Jan 2026 23:06:07 +0400",
"is_openbsd": false,
"thread_id": "aZ939evsOs6nCd5I@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | This patch series adds basic audio support for Sophgo CV1800B,
as used on boards such as the Milk-V Duo.
The series introduces the I2S controller driver,
the DAC and ADC codec drivers, corresponding DT bindings,
and DTS updates to wire the components together.
The implementation is based on vendor documentation
and te... | null | null | null | [PATCH v4 0/6] ASoC: sophgo: add CV1800 I2S controllers support | Introduced I2S nodes and internal dac and adc nodes as well
The new header file provided in order to make DMA channel names
more readable.
Signed-off-by: Anton D. Stavinskii <stavinsky@gmail.com>
---
arch/riscv/boot/dts/sophgo/cv180x-dmamux.h | 57 ++++++++++++++++++++++++++++++
arch/riscv/boot/dts/sophgo/cv180x.dtsi... | {
"author": "\"Anton D. Stavinskii\" <stavinsky@gmail.com>",
"date": "Tue, 20 Jan 2026 23:06:08 +0400",
"is_openbsd": false,
"thread_id": "aZ939evsOs6nCd5I@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | This patch series adds basic audio support for Sophgo CV1800B,
as used on boards such as the Milk-V Duo.
The series introduces the I2S controller driver,
the DAC and ADC codec drivers, corresponding DT bindings,
and DTS updates to wire the components together.
The implementation is based on vendor documentation
and te... | null | null | null | [PATCH v4 0/6] ASoC: sophgo: add CV1800 I2S controllers support | On 20/01/2026 20:06, Anton D. Stavinskii wrote:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Krzysztof Kozlowski <krzk@kernel.org>",
"date": "Tue, 20 Jan 2026 20:21:49 +0100",
"is_openbsd": false,
"thread_id": "aZ939evsOs6nCd5I@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | This patch series adds basic audio support for Sophgo CV1800B,
as used on boards such as the Milk-V Duo.
The series introduces the I2S controller driver,
the DAC and ADC codec drivers, corresponding DT bindings,
and DTS updates to wire the components together.
The implementation is based on vendor documentation
and te... | null | null | null | [PATCH v4 0/6] ASoC: sophgo: add CV1800 I2S controllers support | On Tue, 20 Jan 2026 23:06:05 +0400, Anton D. Stavinskii wrote:
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "\"Rob Herring (Arm)\" <robh@kernel.org>",
"date": "Tue, 20 Jan 2026 20:30:16 -0600",
"is_openbsd": false,
"thread_id": "aZ939evsOs6nCd5I@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | This patch series adds basic audio support for Sophgo CV1800B,
as used on boards such as the Milk-V Duo.
The series introduces the I2S controller driver,
the DAC and ADC codec drivers, corresponding DT bindings,
and DTS updates to wire the components together.
The implementation is based on vendor documentation
and te... | null | null | null | [PATCH v4 0/6] ASoC: sophgo: add CV1800 I2S controllers support | _______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Tue, 27 Jan 2026 12:49:52 +0000",
"is_openbsd": false,
"thread_id": "aZ939evsOs6nCd5I@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | This patch series adds basic audio support for Sophgo CV1800B,
as used on boards such as the Milk-V Duo.
The series introduces the I2S controller driver,
the DAC and ADC codec drivers, corresponding DT bindings,
and DTS updates to wire the components together.
The implementation is based on vendor documentation
and te... | null | null | null | [PATCH v4 0/6] ASoC: sophgo: add CV1800 I2S controllers support | On Tue, Jan 27, 2026 at 12:49:52PM +0400, Mark Brown wrote:
Will fix, thanks.
I'm not sure here. DAC mute feature was not implemented because I don't know how
exactly do that. The public documentation is very weak for my taste.
This call added here to be sure that override flag is
not set (override feature replaces ... | {
"author": "\"Anton D. Stavinskii\" <stavinsky@gmail.com>",
"date": "Tue, 27 Jan 2026 19:11:24 +0400",
"is_openbsd": false,
"thread_id": "aZ939evsOs6nCd5I@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | This patch series adds basic audio support for Sophgo CV1800B,
as used on boards such as the Milk-V Duo.
The series introduces the I2S controller driver,
the DAC and ADC codec drivers, corresponding DT bindings,
and DTS updates to wire the components together.
The implementation is based on vendor documentation
and te... | null | null | null | [PATCH v4 0/6] ASoC: sophgo: add CV1800 I2S controllers support | On Tue, Jan 27, 2026 at 03:13:59PM +0400, Mark Brown wrote:
Sounds good. Will add comments and prepare v5.
Thanks a lot!
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "\"Anton D. Stavinskii\" <stavinsky@gmail.com>",
"date": "Tue, 27 Jan 2026 19:30:27 +0400",
"is_openbsd": false,
"thread_id": "aZ939evsOs6nCd5I@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | This patch series adds basic audio support for Sophgo CV1800B,
as used on boards such as the Milk-V Duo.
The series introduces the I2S controller driver,
the DAC and ADC codec drivers, corresponding DT bindings,
and DTS updates to wire the components together.
The implementation is based on vendor documentation
and te... | null | null | null | [PATCH v4 0/6] ASoC: sophgo: add CV1800 I2S controllers support | On Tue, Jan 27, 2026 at 12:50:34PM +0400, Mark Brown wrote:
Hope everything done correctly here
https://lore.kernel.org/all/20260127-incremental-for-i2s-dvier-v1-2-431b809c632d@gmail.com/
Thank you very much for the review
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.in... | {
"author": "\"Anton D. Stavinskii\" <stavinsky@gmail.com>",
"date": "Tue, 27 Jan 2026 22:51:17 +0400",
"is_openbsd": false,
"thread_id": "aZ939evsOs6nCd5I@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | This patch series adds basic audio support for Sophgo CV1800B,
as used on boards such as the Milk-V Duo.
The series introduces the I2S controller driver,
the DAC and ADC codec drivers, corresponding DT bindings,
and DTS updates to wire the components together.
The implementation is based on vendor documentation
and te... | null | null | null | [PATCH v4 0/6] ASoC: sophgo: add CV1800 I2S controllers support | On Tue, 20 Jan 2026 23:06:02 +0400, Anton D. Stavinskii wrote:
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
Thanks!
[1/6] ASoC: dt-bindings: sophgo,cv1800b: add I2S/TDM controller
commit: ad50e1f63873e5d1f2f421bbd11387a0a1d0ca54
[2/6] ASoC: sophgo: add CV1800B I2S/T... | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Wed, 28 Jan 2026 03:02:21 +0000",
"is_openbsd": false,
"thread_id": "aZ939evsOs6nCd5I@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | This patch series adds basic audio support for Sophgo CV1800B,
as used on boards such as the Milk-V Duo.
The series introduces the I2S controller driver,
the DAC and ADC codec drivers, corresponding DT bindings,
and DTS updates to wire the components together.
The implementation is based on vendor documentation
and te... | null | null | null | [PATCH v4 0/6] ASoC: sophgo: add CV1800 I2S controllers support | On Tue, Jan 20, 2026 at 11:06:08PM +0400, Anton D. Stavinskii wrote:
Hi, Anton,
Can you send a new version with the all device nodes sorted by address?
So I can take them, Thanks.
Regards,
Inochi
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.... | {
"author": "Inochi Amaoto <inochiama@gmail.com>",
"date": "Thu, 26 Feb 2026 06:20:03 +0800",
"is_openbsd": false,
"thread_id": "aZ939evsOs6nCd5I@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | This patch series adds basic audio support for Sophgo CV1800B,
as used on boards such as the Milk-V Duo.
The series introduces the I2S controller driver,
the DAC and ADC codec drivers, corresponding DT bindings,
and DTS updates to wire the components together.
The implementation is based on vendor documentation
and te... | null | null | null | [PATCH v4 0/6] ASoC: sophgo: add CV1800 I2S controllers support | On Tue, Jan 20, 2026 at 11:06:08PM +0400, Anton D. Stavinskii wrote:
This magic number 1 is bind to the RISC-V cores, I think we should add a
macro DMA_CPU_ID into CPU file to route the CPU id to real cores.
Or, just let the borad dts configure which dma is enabled.
Regards,
Inochi
_________________________________... | {
"author": "Inochi Amaoto <inochiama@gmail.com>",
"date": "Thu, 26 Feb 2026 06:32:27 +0800",
"is_openbsd": false,
"thread_id": "aZ939evsOs6nCd5I@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | This is v2 of the series extracting the common shadow stack mmap into a
separate helper for arm64, riscv and x86. Thanks for the review.
Andrew, if you are happy with this, I think taking the patches through
the mm tree makes most sense.
Minor changes since v1:
- Removed #ifdef from the helper function declaration
-... | null | null | null | [PATCH v2 0/5] mm: arch/shstk: Common shadow stack mapping helper and VM_NOHUGEPAGE | arm64, riscv and x86 use a similar pattern for mapping the user shadow
stack (cloned from x86). Extract this into a helper to facilitate code
reuse.
The call to do_mmap() from the new helper uses PROT_READ|PROT_WRITE prot
bits instead of the PROT_READ with an explicit VM_WRITE vm_flag. The
x86 intent was to avoid PROT... | {
"author": "Catalin Marinas <catalin.marinas@arm.com>",
"date": "Wed, 25 Feb 2026 16:13:58 +0000",
"is_openbsd": false,
"thread_id": "aZ9XlUAJvPux4xCQ@kernel.org.mbox.gz"
} |
lkml_critique | linux-riscv | This is v2 of the series extracting the common shadow stack mmap into a
separate helper for arm64, riscv and x86. Thanks for the review.
Andrew, if you are happy with this, I think taking the patches through
the mm tree makes most sense.
Minor changes since v1:
- Removed #ifdef from the helper function declaration
-... | null | null | null | [PATCH v2 0/5] mm: arch/shstk: Common shadow stack mapping helper and VM_NOHUGEPAGE | Replace the arm64 map_shadow_stack() content with a call to
vm_mmap_shadow_stack(). There is no functional change.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: David Hildenbrand (Arm) <david@kernel.org>
Reviewed-by: Mark Brown <broonie@kernel.org>
Cc: Will Deacon <will@kernel.org>
---
arch/ar... | {
"author": "Catalin Marinas <catalin.marinas@arm.com>",
"date": "Wed, 25 Feb 2026 16:13:59 +0000",
"is_openbsd": false,
"thread_id": "aZ9XlUAJvPux4xCQ@kernel.org.mbox.gz"
} |
lkml_critique | linux-riscv | This is v2 of the series extracting the common shadow stack mmap into a
separate helper for arm64, riscv and x86. Thanks for the review.
Andrew, if you are happy with this, I think taking the patches through
the mm tree makes most sense.
Minor changes since v1:
- Removed #ifdef from the helper function declaration
-... | null | null | null | [PATCH v2 0/5] mm: arch/shstk: Common shadow stack mapping helper and VM_NOHUGEPAGE | Replace part of the allocate_shadow_stack() content with a call to
vm_mmap_shadow_stack(). There is no functional change.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Deepak Gupta <debug@rivosinc.com>
Reviewed-by: David Hildenbrand (Arm) <david@kernel.org>
Cc: Paul Walmsley <pjw@kernel.org>
Cc: ... | {
"author": "Catalin Marinas <catalin.marinas@arm.com>",
"date": "Wed, 25 Feb 2026 16:14:00 +0000",
"is_openbsd": false,
"thread_id": "aZ9XlUAJvPux4xCQ@kernel.org.mbox.gz"
} |
lkml_critique | linux-riscv | This is v2 of the series extracting the common shadow stack mmap into a
separate helper for arm64, riscv and x86. Thanks for the review.
Andrew, if you are happy with this, I think taking the patches through
the mm tree makes most sense.
Minor changes since v1:
- Removed #ifdef from the helper function declaration
-... | null | null | null | [PATCH v2 0/5] mm: arch/shstk: Common shadow stack mapping helper and VM_NOHUGEPAGE | The default shadow stack size allocated on first prctl() for the main
thread or subsequently on clone() is either half of RLIMIT_STACK or half
of a thread's stack size (for arm64). Both of these are likely to be
suitable for a THP allocation and the kernel is more aggressive in
creating such mappings. However, it does ... | {
"author": "Catalin Marinas <catalin.marinas@arm.com>",
"date": "Wed, 25 Feb 2026 16:14:02 +0000",
"is_openbsd": false,
"thread_id": "aZ9XlUAJvPux4xCQ@kernel.org.mbox.gz"
} |
lkml_critique | linux-riscv | This is v2 of the series extracting the common shadow stack mmap into a
separate helper for arm64, riscv and x86. Thanks for the review.
Andrew, if you are happy with this, I think taking the patches through
the mm tree makes most sense.
Minor changes since v1:
- Removed #ifdef from the helper function declaration
-... | null | null | null | [PATCH v2 0/5] mm: arch/shstk: Common shadow stack mapping helper and VM_NOHUGEPAGE | Replace part of the x86 alloc_shstk() content with a call to
vm_mmap_shadow_stack(). There is no functional change.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Rick Edgecombe <rick.p.edgecombe@intel.com>
Tested-by: Rick Edgecombe <rick.p.edgecombe@intel.com>
Reviewed-by: David Hildenbrand (Ar... | {
"author": "Catalin Marinas <catalin.marinas@arm.com>",
"date": "Wed, 25 Feb 2026 16:14:01 +0000",
"is_openbsd": false,
"thread_id": "aZ9XlUAJvPux4xCQ@kernel.org.mbox.gz"
} |
lkml_critique | linux-riscv | This is v2 of the series extracting the common shadow stack mmap into a
separate helper for arm64, riscv and x86. Thanks for the review.
Andrew, if you are happy with this, I think taking the patches through
the mm tree makes most sense.
Minor changes since v1:
- Removed #ifdef from the helper function declaration
-... | null | null | null | [PATCH v2 0/5] mm: arch/shstk: Common shadow stack mapping helper and VM_NOHUGEPAGE | On Wed, Feb 25, 2026 at 04:13:57PM +0000, Catalin Marinas wrote:
Reviewed-by: Mike Rapoport (Microsoft) <rppt@kernel.org>
--
Sincerely yours,
Mike.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Mike Rapoport <rppt@kernel.org>",
"date": "Wed, 25 Feb 2026 22:12:05 +0200",
"is_openbsd": false,
"thread_id": "aZ9XlUAJvPux4xCQ@kernel.org.mbox.gz"
} |
lkml_critique | linux-riscv | From: Conor Dooley <conor.dooley@microchip.com>
In 2024 I sent a v7 of adding support for the GPIOs on PolarFire SoC,
which relied on an irqchip driver for a mux sitting between the GPIO
controllers and the main interrupt controller on the chip:
https://lore.kernel.org/all/20240723-flatworm-cornflake-8023212f6584@wend... | null | null | null | [RFC v11 0/4] PolarFire SoC GPIO interrupt support | From: Conor Dooley <conor.dooley@microchip.com>
Add support for interrupts to the PolarFire SoC GPIO driver. Each GPIO
has an independent interrupt that is wired to an interrupt mux that sits
between the controllers and the PLIC. The SoC has more GPIO lines than
connections from the mux to the PLIC, so some GPIOs must... | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Fri, 27 Feb 2026 14:52:27 +0000",
"is_openbsd": false,
"thread_id": "20260227-manhunt-sixtieth-a7928d5b7e98@spud.mbox.gz"
} |
lkml_critique | linux-riscv | From: Conor Dooley <conor.dooley@microchip.com>
In 2024 I sent a v7 of adding support for the GPIOs on PolarFire SoC,
which relied on an irqchip driver for a mux sitting between the GPIO
controllers and the main interrupt controller on the chip:
https://lore.kernel.org/all/20240723-flatworm-cornflake-8023212f6584@wend... | null | null | null | [RFC v11 0/4] PolarFire SoC GPIO interrupt support | From: Conor Dooley <conor.dooley@microchip.com>
On PolarFire SoC there are more GPIO interrupts than there are interrupt
lines available on the PLIC, and a runtime configurable mux is used to
decide which interrupts are assigned direct connections to the PLIC &
which are relegated to sharing a line.
Signed-off-by: Co... | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Fri, 27 Feb 2026 14:52:28 +0000",
"is_openbsd": false,
"thread_id": "20260227-manhunt-sixtieth-a7928d5b7e98@spud.mbox.gz"
} |
lkml_critique | linux-riscv | From: Conor Dooley <conor.dooley@microchip.com>
In 2024 I sent a v7 of adding support for the GPIOs on PolarFire SoC,
which relied on an irqchip driver for a mux sitting between the GPIO
controllers and the main interrupt controller on the chip:
https://lore.kernel.org/all/20240723-flatworm-cornflake-8023212f6584@wend... | null | null | null | [RFC v11 0/4] PolarFire SoC GPIO interrupt support | From: Conor Dooley <conor.dooley@microchip.com>
On PolarFire SoC there are more GPIO interrupts than there are interrupt
lines available on the PLIC, and a runtime configurable mux is used to
decide which interrupts are assigned direct connections to the PLIC &
which are relegated to sharing a line.
Add a driver so t... | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Fri, 27 Feb 2026 14:52:29 +0000",
"is_openbsd": false,
"thread_id": "20260227-manhunt-sixtieth-a7928d5b7e98@spud.mbox.gz"
} |
lkml_critique | linux-riscv | From: Conor Dooley <conor.dooley@microchip.com>
In 2024 I sent a v7 of adding support for the GPIOs on PolarFire SoC,
which relied on an irqchip driver for a mux sitting between the GPIO
controllers and the main interrupt controller on the chip:
https://lore.kernel.org/all/20240723-flatworm-cornflake-8023212f6584@wend... | null | null | null | [RFC v11 0/4] PolarFire SoC GPIO interrupt support | From: Conor Dooley <conor.dooley@microchip.com>
There are 3 GPIO controllers on this SoC, of which:
- GPIO controller 0 has 14 GPIOs
- GPIO controller 1 has 24 GPIOs
- GPIO controller 2 has 32 GPIOs
All GPIOs are capable of generating interrupts, for a total of 70.
There are only 41 IRQs available however, so a confi... | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Fri, 27 Feb 2026 14:52:30 +0000",
"is_openbsd": false,
"thread_id": "20260227-manhunt-sixtieth-a7928d5b7e98@spud.mbox.gz"
} |
lkml_critique | linux-riscv | As the DMA controller on Sophgo CV1800 series SoC only has 8 channels,
the SoC provides a dma multiplexer to reuse the DMA channel. However,
the dma multiplexer also controlls the DMA interrupt multiplexer, which
means that the dma multiplexer needs to know the channel number.
Change the DMA phandle args parsing logic... | null | null | null | [PATCH v4 0/3] riscv: sophgo: allow DMA multiplexer set channel number for DMA controller | The DMA controller on CV1800B needs to use the DMA phandle args
as the channel number instead of hardware handshake number, so
add a new compatible for the DMA controller on CV1800B.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bin... | {
"author": "Inochi Amaoto <inochiama@gmail.com>",
"date": "Wed, 25 Feb 2026 18:40:39 +0800",
"is_openbsd": false,
"thread_id": "20260225104042.1138901-1-inochiama@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | As the DMA controller on Sophgo CV1800 series SoC only has 8 channels,
the SoC provides a dma multiplexer to reuse the DMA channel. However,
the dma multiplexer also controlls the DMA interrupt multiplexer, which
means that the dma multiplexer needs to know the channel number.
Change the DMA phandle args parsing logic... | null | null | null | [PATCH v4 0/3] riscv: sophgo: allow DMA multiplexer set channel number for DMA controller | Change the DMA controller compatible to the sophgo,cv1800b-axi-dma,
which supports setting DMA channel number in DMA phandle args.
Fixes: 514951a81a5e ("riscv: dts: sophgo: cv18xx: add DMA controller")
Reported-by: Anton D. Stavinskii <stavinsky@gmail.com>
Closes: https://github.com/sophgo/linux/issues/9
Signed-off-by... | {
"author": "Inochi Amaoto <inochiama@gmail.com>",
"date": "Wed, 25 Feb 2026 18:40:41 +0800",
"is_openbsd": false,
"thread_id": "20260225104042.1138901-1-inochiama@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | As the DMA controller on Sophgo CV1800 series SoC only has 8 channels,
the SoC provides a dma multiplexer to reuse the DMA channel. However,
the dma multiplexer also controlls the DMA interrupt multiplexer, which
means that the dma multiplexer needs to know the channel number.
Change the DMA phandle args parsing logic... | null | null | null | [PATCH v4 0/3] riscv: sophgo: allow DMA multiplexer set channel number for DMA controller | As the DMA controller on Sophgo CV1800 series SoC only has 8 channels,
the SoC provides a dma multiplexer to reuse the DMA channel. However,
the dma multiplexer also controls the DMA interrupt multiplexer, which
means that the dma multiplexer needs to know the channel number.
Allow the driver to use DMA phandle args a... | {
"author": "Inochi Amaoto <inochiama@gmail.com>",
"date": "Wed, 25 Feb 2026 18:40:40 +0800",
"is_openbsd": false,
"thread_id": "20260225104042.1138901-1-inochiama@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | As the DMA controller on Sophgo CV1800 series SoC only has 8 channels,
the SoC provides a dma multiplexer to reuse the DMA channel. However,
the dma multiplexer also controlls the DMA interrupt multiplexer, which
means that the dma multiplexer needs to know the channel number.
Change the DMA phandle args parsing logic... | null | null | null | [PATCH v4 0/3] riscv: sophgo: allow DMA multiplexer set channel number for DMA controller | On Wed, 25 Feb 2026 18:40:38 +0800, Inochi Amaoto wrote:
Applied to dt/riscv, thanks!
[3/3] riscv: dts: sophgo: cv180x: Allow the DMA multiplexer to set channel number for DMA controller
https://github.com/sophgo/linux/commit/7b159ed9c81cf7e0d0b75666e6548ceface2e1b5
Thanks,
Inochi
___________________________... | {
"author": "Inochi Amaoto <inochiama@gmail.com>",
"date": "Thu, 26 Feb 2026 06:21:07 +0800",
"is_openbsd": false,
"thread_id": "20260225104042.1138901-1-inochiama@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | Add a new driver to support the RISC-V IOMMU PMU. This is an auxiliary
device driver created by the parent RISC-V IOMMU driver.
The RISC-V IOMMU PMU separates the cycle counter from the event counters.
The cycle counter is not associated with iohpmevt0, so a software-defined
cycle event is required for the perf subsys... | null | null | null | [PATCH v2 1/2] drivers/perf: riscv-iommu: add risc-v iommu pmu driver | This series implements support for the RISC-V IOMMU hardware performance
monitor.
The RISC-V IOMMU PMU driver is implemented as an auxiliary device driver
created by the parent RISC-V IOMMU driver. The child driver can obtain
resources and information from the parent device, such as the MMIO base
address and IRQ numbe... | {
"author": "Zong Li <zong.li@sifive.com>",
"date": "Sat, 7 Feb 2026 22:38:34 -0800",
"is_openbsd": false,
"thread_id": "E0900342298E5A5F+1e5c6ddb-3049-4488-9af5-ff3f1eb1544b@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Add a new driver to support the RISC-V IOMMU PMU. This is an auxiliary
device driver created by the parent RISC-V IOMMU driver.
The RISC-V IOMMU PMU separates the cycle counter from the event counters.
The cycle counter is not associated with iohpmevt0, so a software-defined
cycle event is required for the perf subsys... | null | null | null | [PATCH v2 1/2] drivers/perf: riscv-iommu: add risc-v iommu pmu driver | Create an auxiliary device for HPM when the IOMMU supports a
hardware performance monitor.
Suggested-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Zong Li <zong.li@sifive.com>
---
drivers/iommu/riscv/iommu.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/iommu/riscv/... | {
"author": "Zong Li <zong.li@sifive.com>",
"date": "Sat, 7 Feb 2026 22:38:36 -0800",
"is_openbsd": false,
"thread_id": "E0900342298E5A5F+1e5c6ddb-3049-4488-9af5-ff3f1eb1544b@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Add a new driver to support the RISC-V IOMMU PMU. This is an auxiliary
device driver created by the parent RISC-V IOMMU driver.
The RISC-V IOMMU PMU separates the cycle counter from the event counters.
The cycle counter is not associated with iohpmevt0, so a software-defined
cycle event is required for the perf subsys... | null | null | null | [PATCH v2 1/2] drivers/perf: riscv-iommu: add risc-v iommu pmu driver | On 2/8/2026 2:38 PM, Zong Li wrote:
Please do not forget to Cc:
Jingyu Li <joey.li@spacemit.com>
I only provided T100 specific support in the posted series, and the
new approach of the HPM driver in the same series is composed by her.
We'd like to know if there's any comments related to putting IOMMU HPM
driver into... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Mon, 9 Feb 2026 09:40:24 +0800",
"is_openbsd": false,
"thread_id": "E0900342298E5A5F+1e5c6ddb-3049-4488-9af5-ff3f1eb1544b@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Add a new driver to support the RISC-V IOMMU PMU. This is an auxiliary
device driver created by the parent RISC-V IOMMU driver.
The RISC-V IOMMU PMU separates the cycle counter from the event counters.
The cycle counter is not associated with iohpmevt0, so a software-defined
cycle event is required for the perf subsys... | null | null | null | [PATCH v2 1/2] drivers/perf: riscv-iommu: add risc-v iommu pmu driver | On Mon, Feb 9, 2026 at 9:41 AM Lv Zheng <lv.zheng@linux.spacemit.com> wrote:
Sorry for missing Jingyu. I have looped her in this thread.
As you mentioned, it’s not strictly required to place the PMU driver
under the drivers/perf/ directory. I think it would also be ok for us
to place the PMU auxiliary driver under d... | {
"author": "Zong Li <zong.li@sifive.com>",
"date": "Mon, 9 Feb 2026 11:19:48 +0800",
"is_openbsd": false,
"thread_id": "E0900342298E5A5F+1e5c6ddb-3049-4488-9af5-ff3f1eb1544b@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Add a new driver to support the RISC-V IOMMU PMU. This is an auxiliary
device driver created by the parent RISC-V IOMMU driver.
The RISC-V IOMMU PMU separates the cycle counter from the event counters.
The cycle counter is not associated with iohpmevt0, so a software-defined
cycle event is required for the perf subsys... | null | null | null | [PATCH v2 1/2] drivers/perf: riscv-iommu: add risc-v iommu pmu driver | 在 2026/2/9 9:40, Lv Zheng 写道:
When I previously submitted my RISC-V IOMMU PMU series, Will（Will
Deacon<will@kernel.org>） suggested placing the RISC-V IOMMU PMU driver
under drivers/perf/, similar to the ARM implementation. He also
commented: "I'm sure Robin had fun dealing with shared MMIO regions
before" — referr... | {
"author": "yaxing guo <guoyaxing@bosc.ac.cn>",
"date": "Mon, 9 Feb 2026 11:21:32 +0800",
"is_openbsd": false,
"thread_id": "E0900342298E5A5F+1e5c6ddb-3049-4488-9af5-ff3f1eb1544b@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Add a new driver to support the RISC-V IOMMU PMU. This is an auxiliary
device driver created by the parent RISC-V IOMMU driver.
The RISC-V IOMMU PMU separates the cycle counter from the event counters.
The cycle counter is not associated with iohpmevt0, so a software-defined
cycle event is required for the perf subsys... | null | null | null | [PATCH v2 1/2] drivers/perf: riscv-iommu: add risc-v iommu pmu driver | On 2/9/2026 11:21 AM, yaxing guo wrote:
Thanks for the information.
We will also follow this suggestion.
Thanks and best regards
Lv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Fri, 27 Feb 2026 13:54:11 +0800",
"is_openbsd": false,
"thread_id": "E0900342298E5A5F+1e5c6ddb-3049-4488-9af5-ff3f1eb1544b@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | The card detect GPIO depends on support by the base board.
Detecting an SD-card did not work for me with a Milk-V Mars CM Lite
mounted on an Waveshare CM4-IO-BASE-A board.
According to [1] SD_SDIO0_CD_GPIO41 is connected to pin 76 reserved.
The Raspberry Pi Compute Module 4 IO Board documentation marks that pin as
re... | null | null | null | [PATCH 1/1] riscv: dts: starfive: Milk-V Mars CM Lite broken-cd | On 2/4/26 11:16, Heinrich Schuchardt wrote:
The schematic of the Waveshare CM4-IO-BASE-A board is available at
https://files.waveshare.com/upload/a/aa/CM4-IO-BASE-A_V4_SchDoc.pdf
showing pin 76 is not connected.
In https://forums.raspberrypi.com/viewtopic.php?t=291041 the Raspberry
Foundation explicitly wrote that p... | {
"author": "Heinrich Schuchardt <heinrich.schuchardt@canonical.com>",
"date": "Wed, 4 Feb 2026 17:38:54 +0100",
"is_openbsd": false,
"thread_id": "20260226-hummus-quarry-41b06f24b38c@spud.mbox.gz"
} |
lkml_critique | linux-riscv | The card detect GPIO depends on support by the base board.
Detecting an SD-card did not work for me with a Milk-V Mars CM Lite
mounted on an Waveshare CM4-IO-BASE-A board.
According to [1] SD_SDIO0_CD_GPIO41 is connected to pin 76 reserved.
The Raspberry Pi Compute Module 4 IO Board documentation marks that pin as
re... | null | null | null | [PATCH 1/1] riscv: dts: starfive: Milk-V Mars CM Lite broken-cd | Hi,
I think the correct fix will be device tree overlays per-carrier board
and not this one-size-fits-all workaround with the System-on-Module.
Review below:
On 2/4/26 08:38, Heinrich Schuchardt wrote:
+ /* Schematic signal SD_SDIO0_CD_GPIO41 to CM4 connector pin 76*/
+ /* Raspberry Pi CM4 specification pin 76 reser... | {
"author": "E Shattow <e@freeshell.de>",
"date": "Wed, 4 Feb 2026 15:16:36 -0800",
"is_openbsd": false,
"thread_id": "20260226-hummus-quarry-41b06f24b38c@spud.mbox.gz"
} |
lkml_critique | linux-riscv | The card detect GPIO depends on support by the base board.
Detecting an SD-card did not work for me with a Milk-V Mars CM Lite
mounted on an Waveshare CM4-IO-BASE-A board.
According to [1] SD_SDIO0_CD_GPIO41 is connected to pin 76 reserved.
The Raspberry Pi Compute Module 4 IO Board documentation marks that pin as
re... | null | null | null | [PATCH 1/1] riscv: dts: starfive: Milk-V Mars CM Lite broken-cd | On 2/5/26 00:16, E Shattow wrote:
Device-tree overlays would have to be applied by the firmware, typically
U-Boot.
The firmware has no way to determine if it is running on an IO-board
with or without a card detect switch. So the selection of an overlay
will be a manual process. In many cases users will not know ab... | {
"author": "Heinrich Schuchardt <heinrich.schuchardt@canonical.com>",
"date": "Thu, 5 Feb 2026 08:50:01 +0100",
"is_openbsd": false,
"thread_id": "20260226-hummus-quarry-41b06f24b38c@spud.mbox.gz"
} |
lkml_critique | linux-riscv | The card detect GPIO depends on support by the base board.
Detecting an SD-card did not work for me with a Milk-V Mars CM Lite
mounted on an Waveshare CM4-IO-BASE-A board.
According to [1] SD_SDIO0_CD_GPIO41 is connected to pin 76 reserved.
The Raspberry Pi Compute Module 4 IO Board documentation marks that pin as
re... | null | null | null | [PATCH 1/1] riscv: dts: starfive: Milk-V Mars CM Lite broken-cd | On 2/4/26 23:50, Heinrich Schuchardt wrote:
Where should such overlays be developed?
Does the overlay then get committed to Linux upstream for downstream use
by U-Boot via devicetree-rebasing tree? Why is this change necessary, here ?
I would like to see more of the Mars CM and Mars CM Lite devicetree
moved down to... | {
"author": "E Shattow <e@freeshell.de>",
"date": "Thu, 5 Feb 2026 02:41:48 -0800",
"is_openbsd": false,
"thread_id": "20260226-hummus-quarry-41b06f24b38c@spud.mbox.gz"
} |
lkml_critique | linux-riscv | The card detect GPIO depends on support by the base board.
Detecting an SD-card did not work for me with a Milk-V Mars CM Lite
mounted on an Waveshare CM4-IO-BASE-A board.
According to [1] SD_SDIO0_CD_GPIO41 is connected to pin 76 reserved.
The Raspberry Pi Compute Module 4 IO Board documentation marks that pin as
re... | null | null | null | [PATCH 1/1] riscv: dts: starfive: Milk-V Mars CM Lite broken-cd | From: Conor Dooley <conor.dooley@microchip.com>
On Wed, 04 Feb 2026 11:16:02 +0100, Heinrich Schuchardt wrote:
I agree with the stance that the "default value without any overlay
should be one that allows to use the SD-card on all IO-boards,
i.e. 'broken-cd'.", applied to riscv-dt-fixes, thanks!
[1/1] riscv: dts: s... | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Thu, 26 Feb 2026 17:58:44 +0000",
"is_openbsd": false,
"thread_id": "20260226-hummus-quarry-41b06f24b38c@spud.mbox.gz"
} |
lkml_critique | linux-riscv | Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability, but
implement less than 64 address bits. This breaks on platforms where such
a device is assigned an MSI address higher than what's reachable.
Currently, the no_64bit_msi bit is set for these devices, meaning that
only 32-bit MSI addresses are allowed fo... | null | null | null | [PATCH v4 1/4] PCI/MSI: Conservatively generalize no_64bit_msi
into msi_addr_mask | Instead of a 32-bit/64-bit dichotomy, check the MSI address against
msi_addr_mask.
This allows platforms with an MSI doorbell address above the 32-bit
limit to work with devices without full 64-bit MSI address support, as
long as the doorbell is within the addressable range of MSI of the
device.
Reviewed-by: Thomas G... | {
"author": "Vivian Wang <wangruikang@iscas.ac.cn>",
"date": "Thu, 29 Jan 2026 09:56:07 +0800",
"is_openbsd": false,
"thread_id": "20260227164919.GA3897300@bhelgaas.mbox.gz"
} |
lkml_critique | linux-riscv | Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability, but
implement less than 64 address bits. This breaks on platforms where such
a device is assigned an MSI address higher than what's reachable.
Currently, the no_64bit_msi bit is set for these devices, meaning that
only 32-bit MSI addresses are allowed fo... | null | null | null | [PATCH v4 1/4] PCI/MSI: Conservatively generalize no_64bit_msi
into msi_addr_mask | The Sophgo SG2042 is a cursed machine in more ways than one.
The one way relevant to this patch series is that its PCIe controller
has neither INTx nor a low-address MSI doorbell wired up. Instead, the
only usable MSI doorbell is a SoC one at 0x7030010300, which is above
the 32-bit limit.
Currently, the no_64bit_msi ... | {
"author": "Vivian Wang <wangruikang@iscas.ac.cn>",
"date": "Thu, 29 Jan 2026 09:56:05 +0800",
"is_openbsd": false,
"thread_id": "20260227164919.GA3897300@bhelgaas.mbox.gz"
} |
lkml_critique | linux-riscv | Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability, but
implement less than 64 address bits. This breaks on platforms where such
a device is assigned an MSI address higher than what's reachable.
Currently, the no_64bit_msi bit is set for these devices, meaning that
only 32-bit MSI addresses are allowed fo... | null | null | null | [PATCH v4 1/4] PCI/MSI: Conservatively generalize no_64bit_msi
into msi_addr_mask | The code was originally written using no_64bit_msi, which restricts the
device to 32-bit MSI addresses.
Since msi_addr_mask is introduced, use DMA_BIT_MASK(dma_bits) instead of
DMA_BIT_MASK(32) here for msi_addr_mask, describing the restriction more
precisely and allowing these devices to work on platforms with MSI
do... | {
"author": "Vivian Wang <wangruikang@iscas.ac.cn>",
"date": "Thu, 29 Jan 2026 09:56:09 +0800",
"is_openbsd": false,
"thread_id": "20260227164919.GA3897300@bhelgaas.mbox.gz"
} |
lkml_critique | linux-riscv | Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability, but
implement less than 64 address bits. This breaks on platforms where such
a device is assigned an MSI address higher than what's reachable.
Currently, the no_64bit_msi bit is set for these devices, meaning that
only 32-bit MSI addresses are allowed fo... | null | null | null | [PATCH v4 1/4] PCI/MSI: Conservatively generalize no_64bit_msi
into msi_addr_mask | The code was originally written using no_64bit_msi, which restricts the
device to 32-bit MSI addresses.
Since msi_addr_mask is introduced, use DMA_BIT_MASK(dma_bits) instead of
DMA_BIT_MASK(32) here for msi_addr_mask, describing the restriction more
precisely and allowing these devices to work on platforms with MSI
do... | {
"author": "Vivian Wang <wangruikang@iscas.ac.cn>",
"date": "Thu, 29 Jan 2026 09:56:08 +0800",
"is_openbsd": false,
"thread_id": "20260227164919.GA3897300@bhelgaas.mbox.gz"
} |
lkml_critique | linux-riscv | Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability, but
implement less than 64 address bits. This breaks on platforms where such
a device is assigned an MSI address higher than what's reachable.
Currently, the no_64bit_msi bit is set for these devices, meaning that
only 32-bit MSI addresses are allowed fo... | null | null | null | [PATCH v4 1/4] PCI/MSI: Conservatively generalize no_64bit_msi
into msi_addr_mask | On 1/29/26 02:56, Vivian Wang wrote:
Reviewed-by: Christian König <christian.koenig@amd.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "=?UTF-8?Q?Christian_K=C3=B6nig?= <christian.koenig@amd.com>",
"date": "Thu, 29 Jan 2026 09:08:00 +0100",
"is_openbsd": false,
"thread_id": "20260227164919.GA3897300@bhelgaas.mbox.gz"
} |
lkml_critique | linux-riscv | Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability, but
implement less than 64 address bits. This breaks on platforms where such
a device is assigned an MSI address higher than what's reachable.
Currently, the no_64bit_msi bit is set for these devices, meaning that
only 32-bit MSI addresses are allowed fo... | null | null | null | [PATCH v4 1/4] PCI/MSI: Conservatively generalize no_64bit_msi
into msi_addr_mask | On Thu, Jan 29 2026 at 09:56, Vivian Wang wrote:
I'm happy to take the first two right away.
I can pick up the driver specific ones as well if there are no
objections; they both have been looked at by the relevant maintainers
and they obviously depend on the first ones so they have either to go
together or postponed ... | {
"author": "Thomas Gleixner <tglx@kernel.org>",
"date": "Thu, 29 Jan 2026 22:51:12 +0100",
"is_openbsd": false,
"thread_id": "20260227164919.GA3897300@bhelgaas.mbox.gz"
} |
lkml_critique | linux-riscv | Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability, but
implement less than 64 address bits. This breaks on platforms where such
a device is assigned an MSI address higher than what's reachable.
Currently, the no_64bit_msi bit is set for these devices, meaning that
only 32-bit MSI addresses are allowed fo... | null | null | null | [PATCH v4 1/4] PCI/MSI: Conservatively generalize no_64bit_msi
into msi_addr_mask | Hello:
This series was applied to riscv/linux.git (fixes)
by Thomas Gleixner <tglx@kernel.org>:
On Thu, 29 Jan 2026 09:56:05 +0800 you wrote:
Here is the summary with links:
- [v4,1/4] PCI/MSI: Conservatively generalize no_64bit_msi into msi_addr_mask
https://git.kernel.org/riscv/c/386ced19e9a3
- [v4,2/4] PC... | {
"author": "patchwork-bot+linux-riscv@kernel.org",
"date": "Fri, 20 Feb 2026 04:10:40 +0000",
"is_openbsd": false,
"thread_id": "20260227164919.GA3897300@bhelgaas.mbox.gz"
} |
lkml_critique | linux-riscv | Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability, but
implement less than 64 address bits. This breaks on platforms where such
a device is assigned an MSI address higher than what's reachable.
Currently, the no_64bit_msi bit is set for these devices, meaning that
only 32-bit MSI addresses are allowed fo... | null | null | null | [PATCH v4 1/4] PCI/MSI: Conservatively generalize no_64bit_msi
into msi_addr_mask | On 29/01/2026 3:56, Vivian Wang wrote:
Hey Vivian,
We are seeing issues while reloading mlx5 on a PPC64 platform.
We see the following messages in dmesg:
mlx5_core 0000:00:08.0: mlx5_load:1266:(pid 1283): Failed to alloc IRQs
mlx5_core 0000:00:08.0: E-Switch: cleanup
mlx5_core 0000:00:08.0: probe_one:1959:(pid 1283)... | {
"author": "Mark Bloch <mbloch@nvidia.com>",
"date": "Thu, 26 Feb 2026 20:25:35 +0200",
"is_openbsd": false,
"thread_id": "20260227164919.GA3897300@bhelgaas.mbox.gz"
} |
lkml_critique | linux-riscv | Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability, but
implement less than 64 address bits. This breaks on platforms where such
a device is assigned an MSI address higher than what's reachable.
Currently, the no_64bit_msi bit is set for these devices, meaning that
only 32-bit MSI addresses are allowed fo... | null | null | null | [PATCH v4 1/4] PCI/MSI: Conservatively generalize no_64bit_msi
into msi_addr_mask | On 2/27/26 02:25, Mark Bloch wrote:
Mea culpa. There's a fix on the list [1] since last Friday. I'm not sure
why it hasn't moved yet, but please take a look.
Vivian "dramforever" Wang
[1]: https://lore.kernel.org/all/20260220070239.1693303-1-nilay@linux.ibm.com/
_______________________________________________
lin... | {
"author": "Vivian Wang <wangruikang@iscas.ac.cn>",
"date": "Fri, 27 Feb 2026 13:25:03 +0800",
"is_openbsd": false,
"thread_id": "20260227164919.GA3897300@bhelgaas.mbox.gz"
} |
lkml_critique | linux-riscv | Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability, but
implement less than 64 address bits. This breaks on platforms where such
a device is assigned an MSI address higher than what's reachable.
Currently, the no_64bit_msi bit is set for these devices, meaning that
only 32-bit MSI addresses are allowed fo... | null | null | null | [PATCH v4 1/4] PCI/MSI: Conservatively generalize no_64bit_msi
into msi_addr_mask | On 27/02/2026 7:25, Vivian Wang wrote:
Thanks! I've looked at the patch, it seems fine and should fix the issue we
are seeing.
Mark
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Mark Bloch <mbloch@nvidia.com>",
"date": "Fri, 27 Feb 2026 10:16:00 +0200",
"is_openbsd": false,
"thread_id": "20260227164919.GA3897300@bhelgaas.mbox.gz"
} |
lkml_critique | linux-riscv | Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability, but
implement less than 64 address bits. This breaks on platforms where such
a device is assigned an MSI address higher than what's reachable.
Currently, the no_64bit_msi bit is set for these devices, meaning that
only 32-bit MSI addresses are allowed fo... | null | null | null | [PATCH v4 1/4] PCI/MSI: Conservatively generalize no_64bit_msi
into msi_addr_mask | On Fri, Feb 27, 2026 at 01:25:03PM +0800, Vivian Wang wrote:
We needed testing on powerpc and sparc, which has now been done,
thanks to Han Gao (SPARC Enterprise T5220), Nathaniel Roach (SPARC
T5-2), and Venkat Rao Bagalkote (IBM Power System LPAR (pseries)).
It would be ideal to have acks from the powerpc and sparc ... | {
"author": "Bjorn Helgaas <helgaas@kernel.org>",
"date": "Fri, 27 Feb 2026 10:49:19 -0600",
"is_openbsd": false,
"thread_id": "20260227164919.GA3897300@bhelgaas.mbox.gz"
} |
lkml_critique | linux-riscv | Hi All,
This series adds mm_struct parameter to pxx_user_accessible_page() hooks,
which is only used on s390 and does not affect other archs.
I reordered pxx_user_accessible_page() parameters to be consistent with
the traditional order and removed unnecessary brackets in patch #1 - the
only patch that touches the gen... | null | null | null | [PATCH 0/4] mm/pgtable: Support for page table check on s390 | From: Tobias Huschle <huschle@linux.ibm.com>
Unlike other architectures, s390 does not have means to
distinguish kernel vs user page table entries - neither
an entry itself, nor the address could be used for that.
It is only the mm_struct that indicates whether an entry
in question is mapped to a user space. So pass m... | {
"author": "Alexander Gordeev <agordeev@linux.ibm.com>",
"date": "Mon, 23 Feb 2026 12:53:13 +0100",
"is_openbsd": false,
"thread_id": "cover.1771845678.git.agordeev@linux.ibm.com.mbox.gz"
} |
lkml_critique | linux-riscv | Hi All,
This series adds mm_struct parameter to pxx_user_accessible_page() hooks,
which is only used on s390 and does not affect other archs.
I reordered pxx_user_accessible_page() parameters to be consistent with
the traditional order and removed unnecessary brackets in patch #1 - the
only patch that touches the gen... | null | null | null | [PATCH 0/4] mm/pgtable: Support for page table check on s390 | Commit 3a5a8d343e1c ("mm: fix race between __split_huge_pmd_locked()
and GUP-fast") failed to follow the convention and used direct PMD
entry modification instead of set_pmd_bit().
Reviewed-by: Gerald Schaefer <gerald.schaefer@linux.ibm.com>
Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
---
arch/s390/incl... | {
"author": "Alexander Gordeev <agordeev@linux.ibm.com>",
"date": "Mon, 23 Feb 2026 12:53:14 +0100",
"is_openbsd": false,
"thread_id": "cover.1771845678.git.agordeev@linux.ibm.com.mbox.gz"
} |
lkml_critique | linux-riscv | Hi All,
This series adds mm_struct parameter to pxx_user_accessible_page() hooks,
which is only used on s390 and does not affect other archs.
I reordered pxx_user_accessible_page() parameters to be consistent with
the traditional order and removed unnecessary brackets in patch #1 - the
only patch that touches the gen... | null | null | null | [PATCH 0/4] mm/pgtable: Support for page table check on s390 | Reviewed-by: Gerald Schaefer <gerald.schaefer@linux.ibm.com>
Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
---
arch/s390/configs/debug_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/s390/configs/debug_defconfig b/arch/s390/configs/debug_defconfig
index 98fd0a2f51c6..12cdaaefb6db 10064... | {
"author": "Alexander Gordeev <agordeev@linux.ibm.com>",
"date": "Mon, 23 Feb 2026 12:53:16 +0100",
"is_openbsd": false,
"thread_id": "cover.1771845678.git.agordeev@linux.ibm.com.mbox.gz"
} |
lkml_critique | linux-riscv | Hi All,
This series adds mm_struct parameter to pxx_user_accessible_page() hooks,
which is only used on s390 and does not affect other archs.
I reordered pxx_user_accessible_page() parameters to be consistent with
the traditional order and removed unnecessary brackets in patch #1 - the
only patch that touches the gen... | null | null | null | [PATCH 0/4] mm/pgtable: Support for page table check on s390 | From: Tobias Huschle <huschle@linux.ibm.com>
Add page table check hooks into routines that modify user page
tables.
Unlike other architectures s390 does not have means to distinguish
between kernel and user page table entries. Rely on the fact the
page table check infrastructure itself operates on non-init_mm
memory ... | {
"author": "Alexander Gordeev <agordeev@linux.ibm.com>",
"date": "Mon, 23 Feb 2026 12:53:15 +0100",
"is_openbsd": false,
"thread_id": "cover.1771845678.git.agordeev@linux.ibm.com.mbox.gz"
} |
lkml_critique | linux-riscv | Hi All,
This series adds mm_struct parameter to pxx_user_accessible_page() hooks,
which is only used on s390 and does not affect other archs.
I reordered pxx_user_accessible_page() parameters to be consistent with
the traditional order and removed unnecessary brackets in patch #1 - the
only patch that touches the gen... | null | null | null | [PATCH 0/4] mm/pgtable: Support for page table check on s390 | On Mon, 23 Feb 2026 12:53:13 +0100 Alexander Gordeev <agordeev@linux.ibm.com> wrote:
Reviewed-by: Andrew Morton <akpm@linux-foundation.org>
I assume this can go into the s390 tree?
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mai... | {
"author": "Andrew Morton <akpm@linux-foundation.org>",
"date": "Mon, 23 Feb 2026 10:13:35 -0800",
"is_openbsd": false,
"thread_id": "cover.1771845678.git.agordeev@linux.ibm.com.mbox.gz"
} |
lkml_critique | linux-riscv | Hi All,
This series adds mm_struct parameter to pxx_user_accessible_page() hooks,
which is only used on s390 and does not affect other archs.
I reordered pxx_user_accessible_page() parameters to be consistent with
the traditional order and removed unnecessary brackets in patch #1 - the
only patch that touches the gen... | null | null | null | [PATCH 0/4] mm/pgtable: Support for page table check on s390 | On Mon, Feb 23, 2026 at 10:13:35AM -0800, Andrew Morton wrote:
Thank you, Andrew!
I think so.
@Vasily?
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Alexander Gordeev <agordeev@linux.ibm.com>",
"date": "Tue, 24 Feb 2026 07:06:28 +0100",
"is_openbsd": false,
"thread_id": "cover.1771845678.git.agordeev@linux.ibm.com.mbox.gz"
} |
lkml_critique | linux-riscv | Hi All,
This series adds mm_struct parameter to pxx_user_accessible_page() hooks,
which is only used on s390 and does not affect other archs.
I reordered pxx_user_accessible_page() parameters to be consistent with
the traditional order and removed unnecessary brackets in patch #1 - the
only patch that touches the gen... | null | null | null | [PATCH 0/4] mm/pgtable: Support for page table check on s390 | On Tue, Feb 24, 2026 at 07:06:28AM +0100, Alexander Gordeev wrote:
I've picked it up, thank you!
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Vasily Gorbik <gor@linux.ibm.com>",
"date": "Tue, 24 Feb 2026 14:04:57 +0100",
"is_openbsd": false,
"thread_id": "cover.1771845678.git.agordeev@linux.ibm.com.mbox.gz"
} |
lkml_critique | linux-riscv | Hi All,
This series adds mm_struct parameter to pxx_user_accessible_page() hooks,
which is only used on s390 and does not affect other archs.
I reordered pxx_user_accessible_page() parameters to be consistent with
the traditional order and removed unnecessary brackets in patch #1 - the
only patch that touches the gen... | null | null | null | [PATCH 0/4] mm/pgtable: Support for page table check on s390 | On 2/23/26 12:53, Alexander Gordeev wrote:
Acked-by: David Hildenbrand (Arm) <david@kernel.org>
--
Cheers,
David
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "\"David Hildenbrand (Arm)\" <david@kernel.org>",
"date": "Thu, 26 Feb 2026 18:04:04 +0100",
"is_openbsd": false,
"thread_id": "cover.1771845678.git.agordeev@linux.ibm.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: Randolph Lin <randolph@andestech.com>
Add support for Andes Qilai SoC PCIe controller
These patches introduce driver support for the PCIe controller on the
Andes Qilai SoC.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
Changes in v11:
- Make minor adjustments based on the reviewer's suggestions.
- U... | null | null | null | [PATCH v11 0/4] Add support for Andes Qilai SoC PCIe controller | From: Randolph Lin <randolph@andestech.com>
Here add maintainer information for Andes QiLai PCIe driver.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 55af015174a5..02619b84e6ee 100644
--- a/MAINTAINERS
... | {
"author": "Randolph <randolph@andestech.com>",
"date": "Wed, 25 Feb 2026 16:55:04 +0800",
"is_openbsd": false,
"thread_id": "20260225085504.3757601-1-randolph@andestech.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: Randolph Lin <randolph@andestech.com>
Add support for Andes Qilai SoC PCIe controller
These patches introduce driver support for the PCIe controller on the
Andes Qilai SoC.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
Changes in v11:
- Make minor adjustments based on the reviewer's suggestions.
- U... | null | null | null | [PATCH v11 0/4] Add support for Andes Qilai SoC PCIe controller | From: Randolph Lin <randolph@andestech.com>
Add the Andes QiLai PCIe node, which includes 3 Root Complexes.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
arch/riscv/boot/dts/andes/qilai.dtsi | 109 +++++++++++++++++++++++++++
1 file changed, 109 insertions(+)
diff --git a/arch/riscv/boot/dts/andes/qilai.... | {
"author": "Randolph <randolph@andestech.com>",
"date": "Wed, 25 Feb 2026 16:55:02 +0800",
"is_openbsd": false,
"thread_id": "20260225085504.3757601-1-randolph@andestech.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: Randolph Lin <randolph@andestech.com>
Add support for Andes Qilai SoC PCIe controller
These patches introduce driver support for the PCIe controller on the
Andes Qilai SoC.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
Changes in v11:
- Make minor adjustments based on the reviewer's suggestions.
- U... | null | null | null | [PATCH v11 0/4] Add support for Andes Qilai SoC PCIe controller | From: Randolph Lin <randolph@andestech.com>
Add driver support for DesignWare based PCIe controller in Andes
QiLai SoC. The driver only supports the Root Complex mode.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
drivers/pci/controller/dwc/Kconfig | 13 ++
drivers/pci/controller/dwc/Makefile ... | {
"author": "Randolph <randolph@andestech.com>",
"date": "Wed, 25 Feb 2026 16:55:03 +0800",
"is_openbsd": false,
"thread_id": "20260225085504.3757601-1-randolph@andestech.com.mbox.gz"
} |
lkml_critique | linux-riscv | From: Randolph Lin <randolph@andestech.com>
Add support for Andes Qilai SoC PCIe controller
These patches introduce driver support for the PCIe controller on the
Andes Qilai SoC.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
Changes in v11:
- Make minor adjustments based on the reviewer's suggestions.
- U... | null | null | null | [PATCH v11 0/4] Add support for Andes Qilai SoC PCIe controller | From: Randolph Lin <randolph@andestech.com>
Add the Andes QiLai PCIe node, which includes 3 Root Complexes.
Only one example is required in the DTS bindings YAML file.
Signed-off-by: Randolph Lin <randolph@andestech.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
.../bindings/pci/andestech,qilai-pcie.yaml ... | {
"author": "Randolph <randolph@andestech.com>",
"date": "Wed, 25 Feb 2026 16:55:01 +0800",
"is_openbsd": false,
"thread_id": "20260225085504.3757601-1-randolph@andestech.com.mbox.gz"
} |
lkml_critique | linux-riscv | Add initial support for ethernet controller of the Spacemit K3 SoC.
This ethernet controller is almost a standard Synopsys DesignWare
MAC (version 5.40a). This controller require a syscon device to
configure some basic features, like interface type and internal delay.
Change from v4:
- https://lore.kernel.org/netdev/2... | null | null | null | [PATCH net-next v5 0/3] riscv: spacemit: Add ethernet support for K3 | The GMAC IP on Spacemit K3 is almost a standard Synopsys DesignWare
MAC (version 5.40a) with some extra clock.
Add necessary compatible string for this device.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
.../devicetree/bindings/net/snps,dwmac.yaml | 2 +... | {
"author": "Inochi Amaoto <inochiama@gmail.com>",
"date": "Fri, 27 Feb 2026 15:57:15 +0800",
"is_openbsd": false,
"thread_id": "20260227075718.2243818-4-inochiama@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | Add initial support for ethernet controller of the Spacemit K3 SoC.
This ethernet controller is almost a standard Synopsys DesignWare
MAC (version 5.40a). This controller require a syscon device to
configure some basic features, like interface type and internal delay.
Change from v4:
- https://lore.kernel.org/netdev/2... | null | null | null | [PATCH net-next v5 0/3] riscv: spacemit: Add ethernet support for K3 | Add compatible string for 5.40a version that can avoid to define some
platform data in the glue layer.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ... | {
"author": "Inochi Amaoto <inochiama@gmail.com>",
"date": "Fri, 27 Feb 2026 15:57:16 +0800",
"is_openbsd": false,
"thread_id": "20260227075718.2243818-4-inochiama@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | Add initial support for ethernet controller of the Spacemit K3 SoC.
This ethernet controller is almost a standard Synopsys DesignWare
MAC (version 5.40a). This controller require a syscon device to
configure some basic features, like interface type and internal delay.
Change from v4:
- https://lore.kernel.org/netdev/2... | null | null | null | [PATCH net-next v5 0/3] riscv: spacemit: Add ethernet support for K3 | The ethernet controller on Spacemit K3 SoC is Synopsys DesignWare
MAC (version 5.40a), with the following special points:
1. The rate of the tx clock line is auto changed when the mac speed
rate is changed, and no need for changing the input tx clock.
2. This controller require a extra syscon device to configure the... | {
"author": "Inochi Amaoto <inochiama@gmail.com>",
"date": "Fri, 27 Feb 2026 15:57:17 +0800",
"is_openbsd": false,
"thread_id": "20260227075718.2243818-4-inochiama@gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | User-controlled register indices from the ONE_REG ioctl are used to
index into arrays of register values. Sanitize them with
array_index_nospec() to prevent speculative out-of-bounds access.
Signed-off-by: Lukas Gerlach <lukas.gerlach@cispa.de>
---
arch/riscv/kvm/vcpu_onereg.c | 36 ++++++++++++++++++++++++++++-------... | null | null | null | [PATCH 1/4] KVM: riscv: Fix Spectre-v1 in ONE_REG register access | User-controlled indices are used to access AIA CSR registers.
Sanitize them with array_index_nospec() to prevent speculative
out-of-bounds access.
Similar to x86 commit 8c86405f606c ("KVM: x86: Protect
ioapic_read_indirect() from Spectre-v1/L1TF attacks") and arm64
commit 41b87599c743 ("KVM: arm/arm64: vgic: fix possi... | {
"author": "Lukas Gerlach <lukas.gerlach@cispa.de>",
"date": "Thu, 26 Feb 2026 15:18:59 +0100",
"is_openbsd": false,
"thread_id": "20260226-kvm-riscv-spectre-v1-v1-0-5f930ea16691@cispa.de.mbox.gz"
} |
lkml_critique | linux-riscv | User-controlled register indices from the ONE_REG ioctl are used to
index into arrays of register values. Sanitize them with
array_index_nospec() to prevent speculative out-of-bounds access.
Signed-off-by: Lukas Gerlach <lukas.gerlach@cispa.de>
---
arch/riscv/kvm/vcpu_onereg.c | 36 ++++++++++++++++++++++++++++-------... | null | null | null | [PATCH 1/4] KVM: riscv: Fix Spectre-v1 in ONE_REG register access | This series adds array_index_nospec() to RISC-V KVM to prevent
speculative out-of-bounds access to kernel memory.
Similar fixes exist for x86 (ioapic, lapic, PMU) and arm64 (vgic).
Signed-off-by: Lukas Gerlach <lukas.gerlach@cispa.de>
---
Lukas Gerlach (4):
KVM: riscv: Fix Spectre-v1 in ONE_REG register access
... | {
"author": "Lukas Gerlach <lukas.gerlach@cispa.de>",
"date": "Thu, 26 Feb 2026 15:18:57 +0100",
"is_openbsd": false,
"thread_id": "20260226-kvm-riscv-spectre-v1-v1-0-5f930ea16691@cispa.de.mbox.gz"
} |
lkml_critique | linux-riscv | User-controlled register indices from the ONE_REG ioctl are used to
index into arrays of register values. Sanitize them with
array_index_nospec() to prevent speculative out-of-bounds access.
Signed-off-by: Lukas Gerlach <lukas.gerlach@cispa.de>
---
arch/riscv/kvm/vcpu_onereg.c | 36 ++++++++++++++++++++++++++++-------... | null | null | null | [PATCH 1/4] KVM: riscv: Fix Spectre-v1 in ONE_REG register access | User-controlled indices are used to index into floating-point registers.
Sanitize them with array_index_nospec() to prevent speculative
out-of-bounds access.
Signed-off-by: Lukas Gerlach <lukas.gerlach@cispa.de>
---
arch/riscv/kvm/vcpu_fp.c | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
dif... | {
"author": "Lukas Gerlach <lukas.gerlach@cispa.de>",
"date": "Thu, 26 Feb 2026 15:19:00 +0100",
"is_openbsd": false,
"thread_id": "20260226-kvm-riscv-spectre-v1-v1-0-5f930ea16691@cispa.de.mbox.gz"
} |
lkml_critique | linux-riscv | User-controlled register indices from the ONE_REG ioctl are used to
index into arrays of register values. Sanitize them with
array_index_nospec() to prevent speculative out-of-bounds access.
Signed-off-by: Lukas Gerlach <lukas.gerlach@cispa.de>
---
arch/riscv/kvm/vcpu_onereg.c | 36 ++++++++++++++++++++++++++++-------... | null | null | null | [PATCH 1/4] KVM: riscv: Fix Spectre-v1 in ONE_REG register access | Guest-controlled counter indices received via SBI ecalls are used to
index into the PMC array. Sanitize them with array_index_nospec()
to prevent speculative out-of-bounds access.
Similar to x86 commit 13c5183a4e64 ("KVM: x86: Protect MSR-based
index computations in pmu.h from Spectre-v1/L1TF attacks").
Fixes: 8f0153... | {
"author": "Lukas Gerlach <lukas.gerlach@cispa.de>",
"date": "Thu, 26 Feb 2026 15:19:01 +0100",
"is_openbsd": false,
"thread_id": "20260226-kvm-riscv-spectre-v1-v1-0-5f930ea16691@cispa.de.mbox.gz"
} |
lkml_critique | linux-riscv | User-controlled register indices from the ONE_REG ioctl are used to
index into arrays of register values. Sanitize them with
array_index_nospec() to prevent speculative out-of-bounds access.
Signed-off-by: Lukas Gerlach <lukas.gerlach@cispa.de>
---
arch/riscv/kvm/vcpu_onereg.c | 36 ++++++++++++++++++++++++++++-------... | null | null | null | [PATCH 1/4] KVM: riscv: Fix Spectre-v1 in ONE_REG register access | 2026-02-26T15:19:01+01:00, Lukas Gerlach <lukas.gerlach@cispa.de>:
This one also covers a non-speculation bug, since the previous condition
used cidx > RISCV_KVM_MAX_COUNTER. :) I'll send a patch for that.
I noticed a few other places where mis-speculation is possible,
see below; can you explain why they don't need ... | {
"author": "=?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?=\n <radim.krcmar@oss.qualcomm.com>",
"date": "Fri, 27 Feb 2026 13:28:51 +0000",
"is_openbsd": false,
"thread_id": "20260226-kvm-riscv-spectre-v1-v1-0-5f930ea16691@cispa.de.mbox.gz"
} |
lkml_critique | linux-riscv | User-controlled register indices from the ONE_REG ioctl are used to
index into arrays of register values. Sanitize them with
array_index_nospec() to prevent speculative out-of-bounds access.
Signed-off-by: Lukas Gerlach <lukas.gerlach@cispa.de>
---
arch/riscv/kvm/vcpu_onereg.c | 36 ++++++++++++++++++++++++++++-------... | null | null | null | [PATCH 1/4] KVM: riscv: Fix Spectre-v1 in ONE_REG register access | Thanks for the review!
Nice catch, thanks for sending the fix.
They do, I missed those. Will send a v2 incorporating all four sites.
Thanks,
Lukas
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Lukas Gerlach <lukas.gerlach@cispa.de>",
"date": "Fri, 27 Feb 2026 16:12:47 +0100",
"is_openbsd": false,
"thread_id": "20260226-kvm-riscv-spectre-v1-v1-0-5f930ea16691@cispa.de.mbox.gz"
} |
lkml_critique | linux-riscv | The RISC-V SBI Steal-Time Accounting (STA) extension requires the shared
memory physical address to be 64-byte aligned, or set to all-ones to
explicitly disable steal-time accounting.
KVM exposes the SBI STA shared memory configuration to userspace via
KVM_SET_ONE_REG. However, the current implementation of
kvm_sbi_ex... | null | null | null | [PATCH v8 1/3] RISC-V: KVM: Validate SBI STA shmem alignment in kvm_sbi_ext_sta_set_reg() | Move steal time UAPI tests from steal_time_init() into a separate
check_steal_time_uapi() function for better code organization and
maintainability.
Previously, x86 and ARM64 architectures performed UAPI validation
tests within steal_time_init(), mixing initialization logic with
uapi tests.
Changes by architecture:
x... | {
"author": "Jiakai Xu <xujiakai2025@iscas.ac.cn>",
"date": "Thu, 26 Feb 2026 08:32:33 +0000",
"is_openbsd": false,
"thread_id": "20260226083234.634716-1-xujiakai2025@iscas.ac.cn.mbox.gz"
} |
lkml_critique | linux-riscv | The RISC-V SBI Steal-Time Accounting (STA) extension requires the shared
memory physical address to be 64-byte aligned, or set to all-ones to
explicitly disable steal-time accounting.
KVM exposes the SBI STA shared memory configuration to userspace via
KVM_SET_ONE_REG. However, the current implementation of
kvm_sbi_ex... | null | null | null | [PATCH v8 1/3] RISC-V: KVM: Validate SBI STA shmem alignment in kvm_sbi_ext_sta_set_reg() | Add RISC-V KVM selftests to verify the SBI Steal-Time Accounting (STA)
shared memory alignment requirements.
The SBI specification requires the STA shared memory GPA to be 64-byte
aligned, or set to all-ones to explicitly disable steal-time accounting.
This test verifies that KVM enforces the expected behavior when
co... | {
"author": "Jiakai Xu <xujiakai2025@iscas.ac.cn>",
"date": "Thu, 26 Feb 2026 08:32:34 +0000",
"is_openbsd": false,
"thread_id": "20260226083234.634716-1-xujiakai2025@iscas.ac.cn.mbox.gz"
} |
lkml_critique | linux-riscv | The RISC-V SBI Steal-Time Accounting (STA) extension requires the shared
memory physical address to be 64-byte aligned, or set to all-ones to
explicitly disable steal-time accounting.
KVM exposes the SBI STA shared memory configuration to userspace via
KVM_SET_ONE_REG. However, the current implementation of
kvm_sbi_ex... | null | null | null | [PATCH v8 1/3] RISC-V: KVM: Validate SBI STA shmem alignment in kvm_sbi_ext_sta_set_reg() | This series fixes a missing validation in the RISC-V KVM SBI
steal-time accounting (STA) register handling.
Patch 1 validates the configured SBI STA shared memory GPA at
KVM_SET_ONE_REG, enforcing the 64-byte alignment requirement
defined by the SBI specification or allowing INVALID_GPA to explicitly
disable steal-tim... | {
"author": "Jiakai Xu <xujiakai2025@iscas.ac.cn>",
"date": "Thu, 26 Feb 2026 08:32:31 +0000",
"is_openbsd": false,
"thread_id": "20260226083234.634716-1-xujiakai2025@iscas.ac.cn.mbox.gz"
} |
lkml_critique | linux-riscv | The RISC-V SBI Steal-Time Accounting (STA) extension requires the shared
memory physical address to be 64-byte aligned, or set to all-ones to
explicitly disable steal-time accounting.
KVM exposes the SBI STA shared memory configuration to userspace via
KVM_SET_ONE_REG. However, the current implementation of
kvm_sbi_ex... | null | null | null | [PATCH v8 1/3] RISC-V: KVM: Validate SBI STA shmem alignment in kvm_sbi_ext_sta_set_reg() | On Thu, Feb 26, 2026 at 08:32:33AM +0000, Jiakai Xu wrote:
...
We probably get away with adding NR_VCPUS+1 vcpus to a vm which was
created with NR_VCPUS because we don't run it and rlimits happen to
work out, but that's pretty fragile and not a correct use of the APIs.
So, we should also create a throw-away vm,
vm_c... | {
"author": "Andrew Jones <andrew.jones@oss.qualcomm.com>",
"date": "Thu, 26 Feb 2026 13:54:19 -0600",
"is_openbsd": false,
"thread_id": "20260226083234.634716-1-xujiakai2025@iscas.ac.cn.mbox.gz"
} |
lkml_critique | linux-riscv | The RISC-V SBI Steal-Time Accounting (STA) extension requires the shared
memory physical address to be 64-byte aligned, or set to all-ones to
explicitly disable steal-time accounting.
KVM exposes the SBI STA shared memory configuration to userspace via
KVM_SET_ONE_REG. However, the current implementation of
kvm_sbi_ex... | null | null | null | [PATCH v8 1/3] RISC-V: KVM: Validate SBI STA shmem alignment in kvm_sbi_ext_sta_set_reg() | On Thu, Feb 26, 2026 at 08:32:34AM +0000, Jiakai Xu wrote:
Why this #if ? INVALID_GPA is common to all architectures (see
include/linux/kvm_types.h). That's why I suggested putting it in this
shared header.
Thanks,
drew
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infra... | {
"author": "Andrew Jones <andrew.jones@oss.qualcomm.com>",
"date": "Thu, 26 Feb 2026 13:57:00 -0600",
"is_openbsd": false,
"thread_id": "20260226083234.634716-1-xujiakai2025@iscas.ac.cn.mbox.gz"
} |
lkml_critique | linux-riscv | This adds poweroff/reboot support for the SpacemiT P1 PMIC chip, which is
commonly paired with the SpacemiT K1 SoC.
Note: For reliable operation, this driver depends on a this patch that adds
atomic transfer support to the SpacemiT I2C controller driver:
https://lore.kernel.org/spacemit/20251009-k1-i2c-atomic-v4-1-a... | null | null | null | [PATCH v5 0/2] driver: reset: spacemit-p1: add driver for poweroff/reboot | This driver implements poweroff/reboot support for the SpacemiT P1 PMIC
chip, which is commonly paired with the SpacemiT K1 SoC.
The SpacemiT P1 support is implemented as a MFD driver, so the access is
done directly through the regmap interface. Reboot or poweroff is
triggered by setting a specific bit in a control re... | {
"author": "Aurelien Jarno <aurelien@aurel32.net>",
"date": "Mon, 3 Nov 2025 00:01:59 +0100",
"is_openbsd": false,
"thread_id": "20251102230352.914421-1-aurelien@aurel32.net.mbox.gz"
} |
lkml_critique | linux-riscv | This adds poweroff/reboot support for the SpacemiT P1 PMIC chip, which is
commonly paired with the SpacemiT K1 SoC.
Note: For reliable operation, this driver depends on a this patch that adds
atomic transfer support to the SpacemiT I2C controller driver:
https://lore.kernel.org/spacemit/20251009-k1-i2c-atomic-v4-1-a... | null | null | null | [PATCH v5 0/2] driver: reset: spacemit-p1: add driver for poweroff/reboot | Add a "spacemit-p1-reboot" cell for the SpacemiT P1 chip.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
v5: no changes
drivers/mfd/simple-mfd-i2c.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mfd/simple-mfd-i2c.c b/drivers/mfd/simple-mfd-i2c.c
index 0a607a1e3ca1d..542d378cdcd1f 100644
--- ... | {
"author": "Aurelien Jarno <aurelien@aurel32.net>",
"date": "Mon, 3 Nov 2025 00:02:00 +0100",
"is_openbsd": false,
"thread_id": "20251102230352.914421-1-aurelien@aurel32.net.mbox.gz"
} |
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