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values | commit large_stringclasses 234
values | subject large_stringclasses 418
values | critique large_stringlengths 101 1.26M ⌀ | metadata dict |
|---|---|---|---|---|---|---|---|---|
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | Introduces global filter support for RISC-V IOMMU HPM. The global filter
can be seen in SpacemiT T100 which only supports single filter to be
applied to all event counters.
Drivers can program filters in each iohpmevt registers as normal in such a
silicon design, however the underlying hardware filters are wired toget... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Thu, 5 Feb 2026 17:11:02 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | Adds IOATC discovery and HPM support for SpacemiT T100.
SpacemiT T100 supports distributed architecture which allows IOTLBs to be
cached in adjacent to the DMA masters. Such IOTLB controllers are called
as IOATCs. Adds distributed HPM support for IOATCs.
Signed-off-by: Lv Zheng <lv.zheng@linux.spacemit.com>
Signed-of... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Thu, 5 Feb 2026 17:11:12 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On Thu, Feb 05, 2026 at 11:52:57AM +0800, Lv Zheng wrote:
...
You shouldn't need to touch this code at all. I don't see anything to fix
wrt the spec. As I said, if iommu->irqs_count is known to be greater than
one but you're getting zero back from ICVEC even after writing 0xffff to
it first, then ICVEC on your IOMMU i... | {
"author": "Andrew Jones <andrew.jones@oss.qualcomm.com>",
"date": "Thu, 5 Feb 2026 09:04:24 -0600",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On Thu, Feb 05, 2026 at 02:11:48PM +0800, Lv Zheng wrote:
Zong Li's SOB should only be on the patches he authored. Don't put
anybody's SOB on patches they haven't been involved in. See
Documentation/process/submitting-patches.rst
"""
The Signed-off-by: tag indicates that the signer was involved in the
development of t... | {
"author": "Andrew Jones <andrew.jones@oss.qualcomm.com>",
"date": "Thu, 5 Feb 2026 09:23:26 -0600",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On 2/6/2026 2:24 AM, Conor Dooley wrote:
SpacemiT provides RISC-V IOMMU implementation, T100 is the first
generation of the this IP product line, we have plan to develop T200,
T300, etc., with more features introduced to be adoptive to new
RISC-V IOMMU specifications.
Besides, T100 is not only shipped in K3, but also ... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Fri, 6 Feb 2026 09:33:09 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On 2/5/2026 11:04 PM, Andrew Jones wrote:
This patch is an approach trying to give PMIV a standalone wired IRQ#
which is required by pre-silicon spacemit T100 RTLs when it is
configured to report both MSI/WSI caps. However there is no such real
product on the market, I just drop it it in the next version.
Thanks,
Lv
... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Fri, 6 Feb 2026 09:36:59 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On 2/5/2026 11:23 PM, Andrew Jones wrote:
serieswould> at least discuss them in the cover letter, explaining why
you've opted
You can see we have contacted each other in community, and decided to
cooperate in this way to honor his contribution. But final decision is
left for the community to decide:
From Zong Li:
... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Fri, 6 Feb 2026 11:42:39 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On 2/6/2026 2:26 AM, Conor Dooley wrote:
Sure, thanks for the help.
Cheers,
Lv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Fri, 6 Feb 2026 11:44:27 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On 29/01/2026 07:08, Lv Zheng wrote:
What is v1.1 in this patch? Why aren't you following standard process
which allows us to make review easier (try yourself with b4 diff)?
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.i... | {
"author": "Krzysztof Kozlowski <krzk@kernel.org>",
"date": "Fri, 6 Feb 2026 11:44:23 +0100",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On 04/02/2026 10:08, Lv Zheng wrote:
Do not attach (thread) your patchsets to some other threads (unrelated
or older versions). This buries them deep in the mailbox and might
interfere with applying entire sets. See also:
https://elixir.bootlin.com/linux/v6.16-rc2/source/Documentation/process/submitting-patches.rst#L... | {
"author": "Krzysztof Kozlowski <krzk@kernel.org>",
"date": "Fri, 6 Feb 2026 11:44:49 +0100",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On 05/02/2026 10:09, Lv Zheng wrote:
And now also v4 is in the same thread? This is total mess!
How tools are supposed to handle this?
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-ri... | {
"author": "Krzysztof Kozlowski <krzk@kernel.org>",
"date": "Fri, 6 Feb 2026 11:46:06 +0100",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On Fri, Feb 06, 2026 at 11:42:39AM +0800, Lv Zheng wrote:
...
Just do all the communication before posting, allowing that communication
to be summarized in the cover letter and in any appropriate commit
messages so reviewers know what's going on. Also don't forget to CC
anybody previously involved to ensure they have ... | {
"author": "Andrew Jones <andrew.jones@oss.qualcomm.com>",
"date": "Fri, 6 Feb 2026 09:09:43 -0600",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On Fri, Feb 6, 2026 at 11:09 PM Andrew Jones
<andrew.jones@oss.qualcomm.com> wrote:
First of all, I apologize for the delay of the PMU series and any
inconvenience it may have caused. I also really appreciate Andrew for
pointing out the upstream culture and consensus.
My next version (v3 series) is expected to be sen... | {
"author": "Zong Li <zong.li@sifive.com>",
"date": "Sat, 7 Feb 2026 10:11:53 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On 2/6/2026 6:44 PM, Krzysztof Kozlowski wrote:
Got it.
I'm still using an old fashioned upstream way to collect all revisions
into one thread. Will align to the preferred style.
Thanks,
Lv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infrad... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Sat, 7 Feb 2026 11:41:01 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On 2/6/2026 6:46 PM, Krzysztof Kozlowski wrote:
I'm using the tools I was using several years ago.
It's able to handle revisions using one single thread if a "msgid" is
provided via its command line:
# Prepare --in-reply-to argument of git-format-patch
if [ "x$1" != "x" -a "x$1" != "xnone" ]; then
echo "Fou... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Sat, 7 Feb 2026 11:54:03 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On 2/6/2026 6:24 PM, Conor Dooley wrote:
Got it.
Sounds reasonable. Thanks.
Basically, T100 is riscv,iommu compatible, its IOATS part should be able
to work using standard HPM events with standard riscv,iommu HPM
compatible driver. People can now test the real hardware of spacemit
T100 on K3.
https://canonical.com... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Sat, 7 Feb 2026 12:24:30 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | Hi Lv,
On 11:41 Sat 07 Feb , Lv Zheng wrote:
Using b4 will automate this procedure, you can also take a look at
Konstantin's articles, and the b4 doc
https://people.kernel.org/monsieuricon/sending-a-kernel-patch-with-b4-part-1
https://b4.docs.kernel.org/en/latest/
--
Yixun Lan (dlan)
__________________________... | {
"author": "Yixun Lan <dlan@gentoo.org>",
"date": "Sat, 14 Feb 2026 06:21:35 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On 2/14/2026 6:21 AM, Yixun Lan wrote:
Yes, we've tried b4, it really can automate this process a lot.
Thanks,
Lv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Fri, 27 Feb 2026 13:55:34 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Linus,
Please pull these RISC-V updates for v7.0. The primary new feature
here is support for CFI in user processes. This feature has been
tested by a set of RISC-V community participants, including by CPU
IP/hardware vendors and by a major Linux distribution. Other changes
are described in the signed tag.
The cod... | null | null | null | [GIT PULL] RISC-V updates for v7.0 | On Thu, 12 Feb 2026 at 15:39, Paul Walmsley <pjw@kernel.org> wrote:
Hmm. In the meantime, I had pulled the RSEQ time slice extensions
stuff first, so what happened was that these prctl numbers got bumped
up from 79-81 to 80-82.
I note that it looks like linux-next ended up merging things in a
different order, and so ... | {
"author": "Linus Torvalds <torvalds@linux-foundation.org>",
"date": "Thu, 12 Feb 2026 19:35:36 -0800",
"is_openbsd": false,
"thread_id": "aaC1UwUpGebEL5Rt@debug.ba.rivosinc.com.mbox.gz"
} |
lkml_critique | linux-riscv | Linus,
Please pull these RISC-V updates for v7.0. The primary new feature
here is support for CFI in user processes. This feature has been
tested by a set of RISC-V community participants, including by CPU
IP/hardware vendors and by a major Linux distribution. Other changes
are described in the signed tag.
The cod... | null | null | null | [GIT PULL] RISC-V updates for v7.0 | The pull request you sent on Thu, 12 Feb 2026 16:39:48 -0700 (MST):
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/cee73b1e840c154f64ace682cb477c1ae2e29cc4
Thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/prtracker.html
_____________________________________________... | {
"author": "pr-tracker-bot@kernel.org",
"date": "Fri, 13 Feb 2026 03:37:33 +0000",
"is_openbsd": false,
"thread_id": "aaC1UwUpGebEL5Rt@debug.ba.rivosinc.com.mbox.gz"
} |
lkml_critique | linux-riscv | Linus,
Please pull these RISC-V updates for v7.0. The primary new feature
here is support for CFI in user processes. This feature has been
tested by a set of RISC-V community participants, including by CPU
IP/hardware vendors and by a major Linux distribution. Other changes
are described in the signed tag.
The cod... | null | null | null | [GIT PULL] RISC-V updates for v7.0 | On Thu, 12 Feb 2026, Linus Torvalds wrote:
Thanks for the heads-up; shouldn't be a problem.
Will think this through and respond back.
RISC-V didn't invent that term; here are some earlier CFI-related uses:
* ARM (2019): https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Learn%20the%20Architecture/... | {
"author": "Paul Walmsley <pjw@kernel.org>",
"date": "Fri, 13 Feb 2026 17:23:41 -0700 (MST)",
"is_openbsd": false,
"thread_id": "aaC1UwUpGebEL5Rt@debug.ba.rivosinc.com.mbox.gz"
} |
lkml_critique | linux-riscv | Linus,
Please pull these RISC-V updates for v7.0. The primary new feature
here is support for CFI in user processes. This feature has been
tested by a set of RISC-V community participants, including by CPU
IP/hardware vendors and by a major Linux distribution. Other changes
are described in the signed tag.
The cod... | null | null | null | [GIT PULL] RISC-V updates for v7.0 | On Fri, 13 Feb 2026 at 16:23, Paul Walmsley <pjw@kernel.org> wrote:
Oh, ok. "landing pad" makes sense. "lp" didn't.
I absolutely detest the industry practice of making crazy acronyms
that make no sense - and then every company makes their *own* crazy
acronym to make things worse.
Please just write it out. It's a few... | {
"author": "Linus Torvalds <torvalds@linux-foundation.org>",
"date": "Fri, 13 Feb 2026 20:14:31 -0800",
"is_openbsd": false,
"thread_id": "aaC1UwUpGebEL5Rt@debug.ba.rivosinc.com.mbox.gz"
} |
lkml_critique | linux-riscv | Linus,
Please pull these RISC-V updates for v7.0. The primary new feature
here is support for CFI in user processes. This feature has been
tested by a set of RISC-V community participants, including by CPU
IP/hardware vendors and by a major Linux distribution. Other changes
are described in the signed tag.
The cod... | null | null | null | [GIT PULL] RISC-V updates for v7.0 | _______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Mon, 16 Feb 2026 14:20:02 +0000",
"is_openbsd": false,
"thread_id": "aaC1UwUpGebEL5Rt@debug.ba.rivosinc.com.mbox.gz"
} |
lkml_critique | linux-riscv | Linus,
Please pull these RISC-V updates for v7.0. The primary new feature
here is support for CFI in user processes. This feature has been
tested by a set of RISC-V community participants, including by CPU
IP/hardware vendors and by a major Linux distribution. Other changes
are described in the signed tag.
The cod... | null | null | null | [GIT PULL] RISC-V updates for v7.0 | On Sat, Feb 14, 2026 at 5:14 AM Linus Torvalds
<torvalds@linux-foundation.org> wrote:
I clearly remember that the the first time we were presented with the BTI
instruction (at a joint Linaro/Ubuntu conference in Budapest) Arnd Bergman
immediately exclaimed, "so you invented the comefrom instruction!"
The thing is a ... | {
"author": "Linus Walleij <linusw@kernel.org>",
"date": "Mon, 16 Feb 2026 22:54:35 +0100",
"is_openbsd": false,
"thread_id": "aaC1UwUpGebEL5Rt@debug.ba.rivosinc.com.mbox.gz"
} |
lkml_critique | linux-riscv | Linus,
Please pull these RISC-V updates for v7.0. The primary new feature
here is support for CFI in user processes. This feature has been
tested by a set of RISC-V community participants, including by CPU
IP/hardware vendors and by a major Linux distribution. Other changes
are described in the signed tag.
The cod... | null | null | null | [GIT PULL] RISC-V updates for v7.0 | On Mon, 16 Feb 2026 at 06:20, Mark Brown <broonie@kernel.org> wrote:
That makes sense. I was looking at the speculation control ones -
which I honestly think are done much better in that they are a bit
more future-proof and won't need yet another random prctl just because
some architecture comes up with a slight varia... | {
"author": "Linus Torvalds <torvalds@linux-foundation.org>",
"date": "Mon, 16 Feb 2026 13:55:11 -0800",
"is_openbsd": false,
"thread_id": "aaC1UwUpGebEL5Rt@debug.ba.rivosinc.com.mbox.gz"
} |
lkml_critique | linux-riscv | Linus,
Please pull these RISC-V updates for v7.0. The primary new feature
here is support for CFI in user processes. This feature has been
tested by a set of RISC-V community participants, including by CPU
IP/hardware vendors and by a major Linux distribution. Other changes
are described in the signed tag.
The cod... | null | null | null | [GIT PULL] RISC-V updates for v7.0 | On Mon, Feb 16, 2026 at 01:55:11PM -0800, Linus Torvalds wrote:
A little bit of history on this. I was at Intel back when Intel was trying
to enable support for "shadow stack" and "enbranch (branch terminating instr)"
feature. Given no other ISAs at that time had any notion of "shadow stack"
and "indirect branch track... | {
"author": "Deepak Gupta <debug@rivosinc.com>",
"date": "Wed, 18 Feb 2026 11:57:36 -0800",
"is_openbsd": false,
"thread_id": "aaC1UwUpGebEL5Rt@debug.ba.rivosinc.com.mbox.gz"
} |
lkml_critique | linux-riscv | Linus,
Please pull these RISC-V updates for v7.0. The primary new feature
here is support for CFI in user processes. This feature has been
tested by a set of RISC-V community participants, including by CPU
IP/hardware vendors and by a major Linux distribution. Other changes
are described in the signed tag.
The cod... | null | null | null | [GIT PULL] RISC-V updates for v7.0 | On Wed, 2026-02-18 at 11:57 -0800, Deepak Gupta wrote:
Arm already uses PROT_BTI to enable their landing pad like thing. It doesn't
need a prctl AFAIU. Peterz had been suggesting we do a similar PROT for x86 user
IBT. Although an additional prctl might still be required for x86. We'd have to
actually start taking... | {
"author": "\"Edgecombe, Rick P\" <rick.p.edgecombe@intel.com>",
"date": "Wed, 18 Feb 2026 21:58:41 +0000",
"is_openbsd": false,
"thread_id": "aaC1UwUpGebEL5Rt@debug.ba.rivosinc.com.mbox.gz"
} |
lkml_critique | linux-riscv | Linus,
Please pull these RISC-V updates for v7.0. The primary new feature
here is support for CFI in user processes. This feature has been
tested by a set of RISC-V community participants, including by CPU
IP/hardware vendors and by a major Linux distribution. Other changes
are described in the signed tag.
The cod... | null | null | null | [GIT PULL] RISC-V updates for v7.0 | On Thu, Feb 19, 2026 at 12:01:10AM +0000, Mark Brown wrote:
Noted.
Aah this makes sense. This is different from x86 and risc-v. Since BTI is on
per-code page basis, kernel enables if loader (interpreter for executable) and
then likely loader sets PROT_BTI for rest of the user space dependencies.
________________... | {
"author": "Deepak Gupta <debug@rivosinc.com>",
"date": "Wed, 18 Feb 2026 17:28:26 -0800",
"is_openbsd": false,
"thread_id": "aaC1UwUpGebEL5Rt@debug.ba.rivosinc.com.mbox.gz"
} |
lkml_critique | linux-riscv | Linus,
Please pull these RISC-V updates for v7.0. The primary new feature
here is support for CFI in user processes. This feature has been
tested by a set of RISC-V community participants, including by CPU
IP/hardware vendors and by a major Linux distribution. Other changes
are described in the signed tag.
The cod... | null | null | null | [GIT PULL] RISC-V updates for v7.0 | Hi Rick,
Comments inline.
On Wed, Feb 18, 2026 at 09:58:41PM +0000, Edgecombe, Rick P wrote:
x86 doesn't have any equivalent BTI bit in PTEs to mark code pages. IIRC, it
does have mechanism where a bitmap has to be prepared and each entry in bitmap
encodes whether a page is legacy code page (without `endbr64`) or a ... | {
"author": "Deepak Gupta <debug@rivosinc.com>",
"date": "Wed, 18 Feb 2026 17:57:45 -0800",
"is_openbsd": false,
"thread_id": "aaC1UwUpGebEL5Rt@debug.ba.rivosinc.com.mbox.gz"
} |
lkml_critique | linux-riscv | Linus,
Please pull these RISC-V updates for v7.0. The primary new feature
here is support for CFI in user processes. This feature has been
tested by a set of RISC-V community participants, including by CPU
IP/hardware vendors and by a major Linux distribution. Other changes
are described in the signed tag.
The cod... | null | null | null | [GIT PULL] RISC-V updates for v7.0 | On Wed, 2026-02-18 at 17:57 -0800, Deepak Gupta wrote:
This might not be the right thread to get into the gory implementation details,
but at a high level, I had looked at two ways to tie it into the ARM interface.
One worked with the bitmap, and the plumbing to connect it to PROT_BTI was
horrible. The other simply ha... | {
"author": "\"Edgecombe, Rick P\" <rick.p.edgecombe@intel.com>",
"date": "Thu, 19 Feb 2026 17:40:21 +0000",
"is_openbsd": false,
"thread_id": "aaC1UwUpGebEL5Rt@debug.ba.rivosinc.com.mbox.gz"
} |
lkml_critique | linux-riscv | Linus,
Please pull these RISC-V updates for v7.0. The primary new feature
here is support for CFI in user processes. This feature has been
tested by a set of RISC-V community participants, including by CPU
IP/hardware vendors and by a major Linux distribution. Other changes
are described in the signed tag.
The cod... | null | null | null | [GIT PULL] RISC-V updates for v7.0 | Hello:
This pull request was applied to riscv/linux.git (fixes)
by Linus Torvalds <torvalds@linux-foundation.org>:
On Thu, 12 Feb 2026 16:39:48 -0700 (MST) you wrote:
Here is the summary with links:
- [GIT,PULL] RISC-V updates for v7.0
https://git.kernel.org/riscv/c/cee73b1e840c
You are awesome, thank you!
--... | {
"author": "patchwork-bot+linux-riscv@kernel.org",
"date": "Fri, 20 Feb 2026 04:11:01 +0000",
"is_openbsd": false,
"thread_id": "aaC1UwUpGebEL5Rt@debug.ba.rivosinc.com.mbox.gz"
} |
lkml_critique | linux-riscv | Linus,
Please pull these RISC-V updates for v7.0. The primary new feature
here is support for CFI in user processes. This feature has been
tested by a set of RISC-V community participants, including by CPU
IP/hardware vendors and by a major Linux distribution. Other changes
are described in the signed tag.
The cod... | null | null | null | [GIT PULL] RISC-V updates for v7.0 | On Wed, Feb 18, 2026 at 05:57:45PM -0800, Deepak Gupta wrote:
So; all of this is only ever relevant for programs that are mixing CFI
and !CFI code. If a program has no CFI, all good. If a program is all
CFI enabled, also all good.
If it starts mixing things, then you get to be 'creative'.
Now the thing is, if you s... | {
"author": "Peter Zijlstra <peterz@infradead.org>",
"date": "Thu, 26 Feb 2026 14:23:42 +0100",
"is_openbsd": false,
"thread_id": "aaC1UwUpGebEL5Rt@debug.ba.rivosinc.com.mbox.gz"
} |
lkml_critique | linux-riscv | Linus,
Please pull these RISC-V updates for v7.0. The primary new feature
here is support for CFI in user processes. This feature has been
tested by a set of RISC-V community participants, including by CPU
IP/hardware vendors and by a major Linux distribution. Other changes
are described in the signed tag.
The cod... | null | null | null | [GIT PULL] RISC-V updates for v7.0 | Hi Peter,
Responses inline.
On Thu, Feb 26, 2026 at 02:23:42PM +0100, Peter Zijlstra wrote:
IIRC, arm has hardware PTE bit saying this is a guarded page. That can be kept
in ITLB as part of virt addr translation during instruction fetch. So whenever
indir_call --> target happens, if target translation was already in... | {
"author": "Deepak Gupta <debug@rivosinc.com>",
"date": "Thu, 26 Feb 2026 13:04:19 -0800",
"is_openbsd": false,
"thread_id": "aaC1UwUpGebEL5Rt@debug.ba.rivosinc.com.mbox.gz"
} |
lkml_critique | linux-riscv | Add a system error interrupt handler for RISC-V that panics
the system when hardware errors are detected. The implementation includes:
- Add IRQ_SYS_ERROR (23) interrupt definition to CSR header
- Implement sys_error.c module with panic handler
- Register per-CPU interrupt handler for system error interrupts
- Add mod... | null | null | null | [PATCH] riscv: add system error interrupt handler support | _______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Thu, 26 Feb 2026 09:22:09 +0000",
"is_openbsd": false,
"thread_id": "202602270355.h8QSG2vl-lkp@intel.com.mbox.gz"
} |
lkml_critique | linux-riscv | Add a system error interrupt handler for RISC-V that panics
the system when hardware errors are detected. The implementation includes:
- Add IRQ_SYS_ERROR (23) interrupt definition to CSR header
- Implement sys_error.c module with panic handler
- Register per-CPU interrupt handler for system error interrupts
- Add mod... | null | null | null | [PATCH] riscv: add system error interrupt handler support | Hi Rui,
kernel test robot noticed the following build errors:
[auto build test ERROR on linus/master]
[also build test ERROR on tip/smp/core v7.0-rc1 next-20260226]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://gi... | {
"author": "kernel test robot <lkp@intel.com>",
"date": "Fri, 27 Feb 2026 03:09:28 +0800",
"is_openbsd": false,
"thread_id": "202602270355.h8QSG2vl-lkp@intel.com.mbox.gz"
} |
lkml_critique | linux-riscv | Add a system error interrupt handler for RISC-V that panics
the system when hardware errors are detected. The implementation includes:
- Add IRQ_SYS_ERROR (23) interrupt definition to CSR header
- Implement sys_error.c module with panic handler
- Register per-CPU interrupt handler for system error interrupts
- Add mod... | null | null | null | [PATCH] riscv: add system error interrupt handler support | On 2/26/26 5:22 PM, Conor Dooley wrote:
Thanks for the comment.
I checked the latest RISC-V Interrupt Spec (2025-03-12). In that
version, interrupts 16–23 are defined as architectural local interrupts,
and interrupt 23 is tentatively proposed for a “Bus or system error”
type condition. That suggests this interrupt nu... | {
"author": "\"Rui Qi\" <qirui.001@bytedance.com>",
"date": "Fri, 27 Feb 2026 15:54:39 +0800",
"is_openbsd": false,
"thread_id": "202602270355.h8QSG2vl-lkp@intel.com.mbox.gz"
} |
lkml_critique | linux-riscv | Add compatible string for 5.40a version that can avoid to define some
platform data in the glue layer.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ... | null | null | null | [PATCH net-next v4 2/3] net: stmmac: platform: Add snps,dwmac-5.40a IP compatible string | The ethernet controller on Spacemit K3 SoC is Synopsys DesignWare
MAC (version 5.40a), with the following special points:
1. The rate of the tx clock line is auto changed when the mac speed
rate is changed, and no need for changing the input tx clock.
2. This controller require a extra syscon device to configure the... | {
"author": "Inochi Amaoto <inochiama@gmail.com>",
"date": "Fri, 30 Jan 2026 10:27:04 +0800",
"is_openbsd": false,
"thread_id": "aaFOeQ0deTKVW0_N@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | Add compatible string for 5.40a version that can avoid to define some
platform data in the glue layer.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ... | null | null | null | [PATCH net-next v4 2/3] net: stmmac: platform: Add snps,dwmac-5.40a IP compatible string | The GMAC IP on Spacemit K3 is almost a standard Synopsys DesignWare
MAC (version 5.40a) with some extra clock.
Add necessary compatible string for this device.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
.../devicetree/bindings/net/snps,dwmac.yaml | 2 +
.../bindings/net/spacemit,k3-dwmac.yaml |... | {
"author": "Inochi Amaoto <inochiama@gmail.com>",
"date": "Fri, 30 Jan 2026 10:27:02 +0800",
"is_openbsd": false,
"thread_id": "aaFOeQ0deTKVW0_N@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | Add compatible string for 5.40a version that can avoid to define some
platform data in the glue layer.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ... | null | null | null | [PATCH net-next v4 2/3] net: stmmac: platform: Add snps,dwmac-5.40a IP compatible string | Add initial support for ethernet controller of the Spacemit K3 SoC.
This ethernet controller is almost a standard Synopsys DesignWare
MAC (version 5.40a). This controller require a syscon device to
configure some basic features, like interface type and internal delay.
Change from v3:
- https://lore.kernel.org/netdev/2... | {
"author": "Inochi Amaoto <inochiama@gmail.com>",
"date": "Fri, 30 Jan 2026 10:27:01 +0800",
"is_openbsd": false,
"thread_id": "aaFOeQ0deTKVW0_N@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | Add compatible string for 5.40a version that can avoid to define some
platform data in the glue layer.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ... | null | null | null | [PATCH net-next v4 2/3] net: stmmac: platform: Add snps,dwmac-5.40a IP compatible string | On Fri, Jan 30, 2026 at 10:27:02AM +0800, Inochi Amaoto wrote:
If you know what this is in terms of dwmac databook clock terms, it
would be helpful to use it here. I suspect "application clock" would
probably summarise it, that being the clock for the bus interfaces
that dwmac provides to the host.
--
RMK's Patch sy... | {
"author": "\"Russell King (Oracle)\" <linux@armlinux.org.uk>",
"date": "Tue, 3 Feb 2026 17:39:06 +0000",
"is_openbsd": false,
"thread_id": "aaFOeQ0deTKVW0_N@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | Add compatible string for 5.40a version that can avoid to define some
platform data in the glue layer.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ... | null | null | null | [PATCH net-next v4 2/3] net: stmmac: platform: Add snps,dwmac-5.40a IP compatible string | On Fri, Jan 30, 2026 at 10:27:04AM +0800, Inochi Amaoto wrote:
Thanks for updating these.
I would suggest that this is split into two parts - first, this is
renamed and reduced to just controlling CTRL_WAKE_IRQ_EN.
Next, a function hooked into plat_dat->set_phy_intf_sel which sets
the CTRL_PHY_INTF_RGMII and CTRL_P... | {
"author": "\"Russell King (Oracle)\" <linux@armlinux.org.uk>",
"date": "Tue, 3 Feb 2026 17:48:00 +0000",
"is_openbsd": false,
"thread_id": "aaFOeQ0deTKVW0_N@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | Add compatible string for 5.40a version that can avoid to define some
platform data in the glue layer.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ... | null | null | null | [PATCH net-next v4 2/3] net: stmmac: platform: Add snps,dwmac-5.40a IP compatible string | On Tue, Feb 03, 2026 at 05:39:06PM +0000, Russell King (Oracle) wrote:
That's a good point, In fact, I have no dwmac databook now. So if you
think it is fine, I will change this description to the "application
clock". Thanks.
Regards,
Inochi
_______________________________________________
linux-riscv mailing list
li... | {
"author": "Inochi Amaoto <inochiama@gmail.com>",
"date": "Wed, 4 Feb 2026 10:11:36 +0800",
"is_openbsd": false,
"thread_id": "aaFOeQ0deTKVW0_N@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | Add compatible string for 5.40a version that can avoid to define some
platform data in the glue layer.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ... | null | null | null | [PATCH net-next v4 2/3] net: stmmac: platform: Add snps,dwmac-5.40a IP compatible string | On Tue, Feb 03, 2026 at 05:48:00PM +0000, Russell King (Oracle) wrote:
Thanks for your detailed guide, I will try to switch to these helper
apis in the next version.
Regards,
Inochi
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mai... | {
"author": "Inochi Amaoto <inochiama@gmail.com>",
"date": "Wed, 4 Feb 2026 10:14:47 +0800",
"is_openbsd": false,
"thread_id": "aaFOeQ0deTKVW0_N@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | Add compatible string for 5.40a version that can avoid to define some
platform data in the glue layer.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ... | null | null | null | [PATCH net-next v4 2/3] net: stmmac: platform: Add snps,dwmac-5.40a IP compatible string | On Fri, 30 Jan 2026 10:27:02 +0800, Inochi Amaoto wrote:
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "\"Rob Herring (Arm)\" <robh@kernel.org>",
"date": "Mon, 9 Feb 2026 11:55:14 -0600",
"is_openbsd": false,
"thread_id": "aaFOeQ0deTKVW0_N@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | Add compatible string for 5.40a version that can avoid to define some
platform data in the glue layer.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ... | null | null | null | [PATCH net-next v4 2/3] net: stmmac: platform: Add snps,dwmac-5.40a IP compatible string | Quoting Inochi Amaoto (2026-01-30 03:27:01)
Hi Inochi,
Do you have a tree that includes the dt entries?
Otherwise how are we going to test this?
/Emil
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Emil Renner Berthing <emil.renner.berthing@gmail.com>",
"date": "Tue, 17 Feb 2026 10:00:29 -0600",
"is_openbsd": false,
"thread_id": "aaFOeQ0deTKVW0_N@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | Add compatible string for 5.40a version that can avoid to define some
platform data in the glue layer.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ... | null | null | null | [PATCH net-next v4 2/3] net: stmmac: platform: Add snps,dwmac-5.40a IP compatible string | On Tue, Feb 17, 2026 at 10:00:29AM -0600, Emil Renner Berthing wrote:
Yes, I have one, but it is not opened as I was requested.
I will send the DTS patch, once the clock, gpio, and pinctrl
device is available. At least for now, I had no way to post
my DTS patch.
Regards,
Inochi
______________________________________... | {
"author": "Inochi Amaoto <inochiama@gmail.com>",
"date": "Fri, 27 Feb 2026 16:01:07 +0800",
"is_openbsd": false,
"thread_id": "aaFOeQ0deTKVW0_N@inochi.infowork.mbox.gz"
} |
lkml_critique | linux-riscv | kvm_riscv_vcpu_aia_rmw_topei() assumes that the per-vCPU IMSIC state has
been initialized once AIA is reported as available and initialized at
the VM level. This assumption does not always hold.
Under fuzzed ioctl sequences, a guest may access the IMSIC TOPEI CSR
before the vCPU IMSIC state is set up. In this case,
vc... | null | null | null | [PATCH] RISC-V: KVM: Fix null pointer dereference in kvm_riscv_vcpu_aia_rmw_topei() | Hi all,
Just a gentle ping on the patch below, sent about three weeks ago.
This fixes a NULL pointer dereference in the AIA TOPEI RMW path that can
be triggered by fuzzed ioctl sequences before per-vCPU IMSIC state is
initialized.
Any feedback would be appreciated.
Thanks,
Jiakai
_________________________________... | {
"author": "Jiakai Xu <xujiakai2025@iscas.ac.cn>",
"date": "Tue, 24 Feb 2026 00:50:18 +0000",
"is_openbsd": false,
"thread_id": "CAAhSdy2e4UYBRfU_m6RX-pWBBEv+Wu2Sqngg05FEG195odwhNw@mail.gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | kvm_riscv_vcpu_aia_rmw_topei() assumes that the per-vCPU IMSIC state has
been initialized once AIA is reported as available and initialized at
the VM level. This assumption does not always hold.
Under fuzzed ioctl sequences, a guest may access the IMSIC TOPEI CSR
before the vCPU IMSIC state is set up. In this case,
vc... | null | null | null | [PATCH] RISC-V: KVM: Fix null pointer dereference in kvm_riscv_vcpu_aia_rmw_topei() | On Fri, Jan 30, 2026 at 3:46 PM Jiakai Xu <xujiakai2025@iscas.ac.cn> wrote:
This should be part of kvm_riscv_vcpu_aia_imsic_rmw().
Also, Fixes tag should point to:
db8b7e97d6137 ("RISC-V: KVM: Add in-kernel virtualization of AIA IMSIC")
Regards,
Anup
_______________________________________________
linux-riscv mail... | {
"author": "Anup Patel <anup@brainfault.org>",
"date": "Thu, 26 Feb 2026 11:30:00 +0530",
"is_openbsd": false,
"thread_id": "CAAhSdy2e4UYBRfU_m6RX-pWBBEv+Wu2Sqngg05FEG195odwhNw@mail.gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | Currently, kvm_arch_vcpu_load() unconditionally restores guest CSRs,
HGATP, and AIA state. However, when a VCPU is loaded back on the same
physical CPU, and no other KVM VCPU has run on this CPU since it was
last put, the hardware CSRs and AIA registers are still valid.
This patch optimizes the vcpu_load path by skipp... | null | null | null | [PATCH v7] KVM: riscv: Skip CSR restore if VCPU is reloaded on the same core | 2026-02-27T20:10:08+08:00, Jinyu Tang <tjytimi@163.com>:
Reviewed-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com>
Thanks.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "=?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?=\n <radim.krcmar@oss.qualcomm.com>",
"date": "Fri, 27 Feb 2026 14:00:43 +0000",
"is_openbsd": false,
"thread_id": "DGPSROCWMJWD.33FHG4JOPD2V8@oss.qualcomm.com.mbox.gz"
} |
lkml_critique | linux-riscv | The patch (Patch 1 in v1 and v2) fixing hardware voltage constraints was
applied to regulator.git for-next, so is no longer part of this series.
Patch 1, 2 and 3 (previously 2-4) enable flexible power tree
configurations for the SpacemiT P1 PMIC. Hardcoded supply assumptions
are replaced with explicit devicetree prope... | null | null | null | [PATCH v4 0/3] regulator: spacemit-p1: Support board power tree
via DT properties | Add supply properties that match the P1 PMIC's actual hardware topology
where each buck converter has its own VIN pin and LDO groups share
common input pins. Supply names are defined according to the pinout
names in the P1 datasheet.
The existing "vin-supply" is dropped from the binding document as the
updated spacemi... | {
"author": "Guodong Xu <guodong@riscstar.com>",
"date": "Fri, 06 Feb 2026 10:32:02 +0800",
"is_openbsd": false,
"thread_id": "20260206-spacemit-p1-v4-0-8f695d93811e@riscstar.com.mbox.gz"
} |
lkml_critique | linux-riscv | The patch (Patch 1 in v1 and v2) fixing hardware voltage constraints was
applied to regulator.git for-next, so is no longer part of this series.
Patch 1, 2 and 3 (previously 2-4) enable flexible power tree
configurations for the SpacemiT P1 PMIC. Hardcoded supply assumptions
are replaced with explicit devicetree prope... | null | null | null | [PATCH v4 0/3] regulator: spacemit-p1: Support board power tree
via DT properties | Update supply names to match the P1 PMIC's actual hardware pinout where
each buck has an individual VIN pin (vin1-vin6) and LDO groups have
dedicated input pins (aldoin, dldoin1, dldoin2).
This is an ABI change from the original "vin" and "buck5" supplies.
The P1/PMIC regulator has no consumers in the DTS tree yet. Fo... | {
"author": "Guodong Xu <guodong@riscstar.com>",
"date": "Fri, 06 Feb 2026 10:32:03 +0800",
"is_openbsd": false,
"thread_id": "20260206-spacemit-p1-v4-0-8f695d93811e@riscstar.com.mbox.gz"
} |
lkml_critique | linux-riscv | The patch (Patch 1 in v1 and v2) fixing hardware voltage constraints was
applied to regulator.git for-next, so is no longer part of this series.
Patch 1, 2 and 3 (previously 2-4) enable flexible power tree
configurations for the SpacemiT P1 PMIC. Hardcoded supply assumptions
are replaced with explicit devicetree prope... | null | null | null | [PATCH v4 0/3] regulator: spacemit-p1: Support board power tree
via DT properties | Use per-regulator supply names in pmic "spacemit,p1" node to specify
each board's power tree topology and match the updated dt-binding.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v4: No change.
v3: No code change. Updated commit message to be more precise.
v2: Added the pmic supply properties for K1 Milkv Ju... | {
"author": "Guodong Xu <guodong@riscstar.com>",
"date": "Fri, 06 Feb 2026 10:32:04 +0800",
"is_openbsd": false,
"thread_id": "20260206-spacemit-p1-v4-0-8f695d93811e@riscstar.com.mbox.gz"
} |
lkml_critique | linux-riscv | The patch (Patch 1 in v1 and v2) fixing hardware voltage constraints was
applied to regulator.git for-next, so is no longer part of this series.
Patch 1, 2 and 3 (previously 2-4) enable flexible power tree
configurations for the SpacemiT P1 PMIC. Hardcoded supply assumptions
are replaced with explicit devicetree prope... | null | null | null | [PATCH v4 0/3] regulator: spacemit-p1: Support board power tree
via DT properties | _______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Mon, 9 Feb 2026 19:00:18 +0000",
"is_openbsd": false,
"thread_id": "20260206-spacemit-p1-v4-0-8f695d93811e@riscstar.com.mbox.gz"
} |
lkml_critique | linux-riscv | The patch (Patch 1 in v1 and v2) fixing hardware voltage constraints was
applied to regulator.git for-next, so is no longer part of this series.
Patch 1, 2 and 3 (previously 2-4) enable flexible power tree
configurations for the SpacemiT P1 PMIC. Hardcoded supply assumptions
are replaced with explicit devicetree prope... | null | null | null | [PATCH v4 0/3] regulator: spacemit-p1: Support board power tree
via DT properties | On Fri, 06 Feb 2026 10:32:01 +0800, Guodong Xu wrote:
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git for-next
Thanks!
[1/3] dt-bindings: mfd: spacemit,p1: Add individual regulator supply properties
commit: 82ffa9610ba39d3628a9bec968ddc68fe2fe6612
[2/3] regulator: spacemit-... | {
"author": "Mark Brown <broonie@kernel.org>",
"date": "Wed, 25 Feb 2026 19:07:19 +0000",
"is_openbsd": false,
"thread_id": "20260206-spacemit-p1-v4-0-8f695d93811e@riscstar.com.mbox.gz"
} |
lkml_critique | linux-riscv | Currently, kvm_arch_vcpu_load() unconditionally restores guest CSRs and
HGATP. However, when a VCPU is loaded back on the same physical CPU,
and no other KVM VCPU has run on this CPU since it was last put,
the hardware CSRs are still valid.
This patch optimizes the vcpu_load path by skipping the expensive CSR
writes i... | null | null | null | [PATCH v6] KVM: riscv: Skip CSR restore if VCPU is reloaded on the same core | 2026-02-26T20:38:02+08:00, Jinyu Tang <tjytimi@163.com>:
Excluding AIA is disturbing as we're writing only vsiselect, hviprio1,
and hviprio2... It seems to me that it should be fine to optimize the
AIA CSRs too.
Wasn't the issue that you originally didn't track csr_dirty, and the bug
just manifested through IMSICs?
... | {
"author": "=?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?=\n <radim.krcmar@oss.qualcomm.com>",
"date": "Thu, 26 Feb 2026 15:04:43 +0000",
"is_openbsd": false,
"thread_id": "DGOZI4Q6NSDS.7AQVQ7TEK9QH@oss.qualcomm.com.mbox.gz"
} |
lkml_critique | linux-pci | This series can be found on GitHub:
https://github.com/dmatlack/linux/tree/liveupdate/vfio/cdev/v2
This series adds the base support to preserve a VFIO device file across
a Live Update. "Base support" means that this allows userspace to
safely preserve a VFIO device file with LIVEUPDATE_SESSION_PRESERVE_FD
and retr... | null | null | null | [PATCH v2 00/22] vfio/pci: Base Live Update support for VFIO device files | On Thu, 26 Feb 2026 00:28:28 +0000
David Matlack <dmatlack@google.com> wrote:
TBH, without SR-IOV support and some examples of in-kernel PF
preservation in support of vfio-pci VFs, it seems like this only
supports a very niche use case. I expect the majority of vfio-pci
devices are VFs and I don't think we want to pr... | {
"author": "Alex Williamson <alex@shazbot.org>",
"date": "Fri, 27 Feb 2026 09:32:33 -0700",
"is_openbsd": false,
"thread_id": "20260227090449.2a23d06d@shazbot.org.mbox.gz"
} |
lkml_critique | linux-pci | This series can be found on GitHub:
https://github.com/dmatlack/linux/tree/liveupdate/vfio/cdev/v2
This series adds the base support to preserve a VFIO device file across
a Live Update. "Base support" means that this allows userspace to
safely preserve a VFIO device file with LIVEUPDATE_SESSION_PRESERVE_FD
and retr... | null | null | null | [PATCH v2 00/22] vfio/pci: Base Live Update support for VFIO device files | On Fri, Feb 27, 2026 at 7:47 AM Alex Williamson <alex@shazbot.org> wrote:
Would a new VFIO_DEVICE_INFO_CAP be a good way to communicate this
information to userspace?
Yes, I will fix that in v3. | {
"author": "David Matlack <dmatlack@google.com>",
"date": "Fri, 27 Feb 2026 09:07:48 -0800",
"is_openbsd": false,
"thread_id": "20260227090449.2a23d06d@shazbot.org.mbox.gz"
} |
lkml_critique | linux-pci | This series can be found on GitHub:
https://github.com/dmatlack/linux/tree/liveupdate/vfio/cdev/v2
This series adds the base support to preserve a VFIO device file across
a Live Update. "Base support" means that this allows userspace to
safely preserve a VFIO device file with LIVEUPDATE_SESSION_PRESERVE_FD
and retr... | null | null | null | [PATCH v2 00/22] vfio/pci: Base Live Update support for VFIO device files | On Fri, Feb 27, 2026 at 8:32 AM Alex Williamson <alex@shazbot.org> wrote:
The intent is to start by supporting a simple use-case and expand to
more complex scenarios over time, including preserving VFs. Full GPU
passthrough is common at cloud providers so even non-VF preservation
support is valuable.
JasonG recommen... | {
"author": "David Matlack <dmatlack@google.com>",
"date": "Fri, 27 Feb 2026 09:19:28 -0800",
"is_openbsd": false,
"thread_id": "20260227090449.2a23d06d@shazbot.org.mbox.gz"
} |
lkml_critique | linux-pci | Hi,
This series add support for SFPs ports available on the LAN966x PCI
device. In order to have the SFPs supported, additional devices are
needed such as clock controller and I2C.
As a reminder, the LAN966x PCI device driver use a device-tree overlay
to describe devices available on the PCI board. Adding support for... | null | null | null | [PATCH v5 00/28] lan966x pci device: Add support for SFPs | Hi Hervé,
On Fri, 27 Feb 2026 at 14:56, Herve Codina <herve.codina@bootlin.com> wrote:
Thanks, that last change did the trick, finally!
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
things
updated
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyo... | {
"author": "Geert Uytterhoeven <geert@linux-m68k.org>",
"date": "Fri, 27 Feb 2026 17:50:14 +0100",
"is_openbsd": false,
"thread_id": "20260227135428.783983-16-herve.codina@bootlin.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | Some non-CXL NVIDIA GPU devices support non-PASID ATS function when their
RIDs are IOMMU bypassed. This is slightly different than the default ATS
policy which would only enable ATS on demand: when a non-zero PASID line
is enabled in SVA use cases.
Introduce a pci_dev_specific_ats_always_on() quirk function to support... | {
"author": "Nicolin Chen <nicolinc@nvidia.com>",
"date": "Fri, 16 Jan 2026 20:56:41 -0800",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | PCI ATS function is controlled by IOMMU driver calling pci_enable_ats() and
pci_disable_ats() helpers. In general, IOMMU driver only enables ATS, when
a translation channel is enabled on a PASID, typically for an SVA use case.
When a device's RID is IOMMU bypassed and there is no active PASID running
SVA use case, ATS ... | {
"author": "Nicolin Chen <nicolinc@nvidia.com>",
"date": "Fri, 16 Jan 2026 20:56:39 -0800",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | When a device's default substream attaches to an identity domain, the SMMU
driver currently sets the device's STE between two modes:
Mode 1: Cfg=Translate, S1DSS=Bypass, EATS=1
Mode 2: Cfg=bypass (EATS is ignored by HW)
When there is an active PASID (non-default substream), mode 1 is used. And
when there is no PA... | {
"author": "Nicolin Chen <nicolinc@nvidia.com>",
"date": "Fri, 16 Jan 2026 20:56:42 -0800",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Fri, Jan 16, 2026 at 08:56:40PM -0800, Nicolin Chen wrote:
I would add here that this is done to allow optimizing devices running
in IDENTITY translation as there is no point to using ATS to return
the same value as it already has.
This implementation looks OK to me
Thanks,
Jason | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Mon, 19 Jan 2026 13:58:26 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Fri, Jan 16, 2026 at 08:56:41PM -0800, Nicolin Chen wrote:
Not support, require non-PASID ATS.
I've been describing these devices as pre-CXL, in that they have many
CXL like properties, including what motivated the prior patch, but do
not implement the CXL config space.
Require not support
This also looks OK to... | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Mon, 19 Jan 2026 14:00:26 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Fri, Jan 16, 2026 at 08:56:42PM -0800, Nicolin Chen wrote:
It looks right, IDK if Will would prefer a formal ARM_SMMU_FEAT_S1DSS
though.
Jason | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Mon, 19 Jan 2026 16:06:25 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | +Dan. I recalled an offline discussion in which he raised concern on
having the kernel blindly enable ATS for cxl.cache device instead of
creating a knob for admin to configure from userspace (in case
security is viewed more important than functionality, upon allowing
DMA to read data out of CPU caches)... | {
"author": "\"Tian, Kevin\" <kevin.tian@intel.com>",
"date": "Wed, 21 Jan 2026 08:01:36 +0000",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Wed, 21 Jan 2026 08:01:36 +0000
"Tian, Kevin" <kevin.tian@intel.com> wrote:
+CC Linux-cxl
Jonathan | {
"author": "Jonathan Cameron <jonathan.cameron@huawei.com>",
"date": "Wed, 21 Jan 2026 10:03:07 +0000",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Wed, Jan 21, 2026 at 10:03:07AM +0000, Jonathan Cameron wrote:
A cxl.cache device supporting ATS will automatically enable ATS today
if the kernel option to enable translation is set.
Even if the device is marked untrusted by the PCI layer (eg an
external port).
Yes this is effectively a security issue, but it is... | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Wed, 21 Jan 2026 09:03:15 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On 1/21/26 21:03, Jason Gunthorpe wrote:
I don't follow here. The untrusted check is now in pci_ats_supported():
/**
* pci_ats_supported - check if the device can use ATS
* @dev: the PCI device
*
* Returns true if the device supports ATS and is allowed to use it, false
* otherwise.
*/
bool pci_ats_support... | {
"author": "Baolu Lu <baolu.lu@linux.intel.com>",
"date": "Thu, 22 Jan 2026 09:17:27 +0800",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | Jason Gunthorpe wrote:
My contention is that it is a worse or at least different problem in the
CXL case because now you have a new toolkit in an attack that wants to
exfiltrate data from CPU caches.
The current PCI untrusted flag is not fit for purpose in this new age of
PCI device authentication and CXL.cache capa... | {
"author": "<dan.j.williams@intel.com>",
"date": "Wed, 21 Jan 2026 21:44:32 -0800",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On 1/21/26 13:03, Jason Gunthorpe wrote:
I raised my concerns about CXL.cache and virtualization at LPC:
https://lpc.events/event/19/contributions/2173/attachments/1842/3940/LPC_2025_CXL_CACHE.pdf
I expose there some concerns, although I admit some could be due to my
twisted understanding of what CXL specs states... | {
"author": "Alejandro Lucero Palau <alucerop@amd.com>",
"date": "Thu, 22 Jan 2026 10:24:58 +0000",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Wed, Jan 21, 2026 at 09:44:32PM -0800, dan.j.williams@intel.com wrote:
?? I don't see CXL as meaningfully different than PCI in terms of what
data can be accessed with Translated requests. If the IOMMU doesn't
block Translated requests the whole systems is open. CXL doesn't make
it more open.
Ah, I missed that we... | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Thu, 22 Jan 2026 09:14:32 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Thu, Jan 22, 2026 at 09:17:27AM +0800, Baolu Lu wrote:
No, not at all, I forgot about this!
Jason | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Thu, 22 Jan 2026 09:15:19 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Thu, Jan 22, 2026 at 09:14:32AM -0400, Jason Gunthorpe wrote:
pci_ats_always_on() validates against !pci_ats_supported(pdev), so
we ensured that untrusted devices would not be always on.
Perhaps we should highlight in the commit message, as it's a topic?
Nicolin | {
"author": "Nicolin Chen <nicolinc@nvidia.com>",
"date": "Thu, 22 Jan 2026 08:29:10 -0800",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | Jason Gunthorpe wrote:
Right, the game is mostly over in the current case, but CXL.cache still
deserves to be treated carefully. Consider a world where we do have limitations
against requests to HPAs that were never translated for the device. In that
scenario the device can help side channel the contents of HPAs it d... | {
"author": "<dan.j.williams@intel.com>",
"date": "Thu, 22 Jan 2026 11:46:05 -0800",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Fri, Jan 16, 2026 at 08:56:42PM -0800, Nicolin Chen wrote:
Should we still warn if !master->ats_always_on?
Can we avoid the 'bool' parameter if possible, please? They tend to make the
callsites pretty horrible to read and you're already passing the 'struct
device *' so you should have the master in hand?
Were d... | {
"author": "Will Deacon <will@kernel.org>",
"date": "Mon, 26 Jan 2026 12:39:50 +0000",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Mon, Jan 26, 2026 at 12:39:50PM +0000, Will Deacon wrote:
I don't think we need to. The entire design here has a non-valid CD entry
for SSID 0.
The spec is really weird here, on one hand it explicitly says that with
S1DSS the CD entry is ignored.
On the other hand, you are also required to have a CD table pointer... | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Mon, 26 Jan 2026 13:20:20 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Mon, Jan 26, 2026 at 12:39:50PM +0000, Will Deacon wrote:
Hmm, yes. I'll fix this.
Trying to set ats_always_on=false for blocked domain here:
@@ -3260,7 +3277,8 @@ static int arm_smmu_attach_dev_identity(struct iommu_domain *domain,
arm_smmu_attach_dev_ste(domain, old_domain, dev, &ste,
STRTAB_STE_1_S1DSS_B... | {
"author": "Nicolin Chen <nicolinc@nvidia.com>",
"date": "Mon, 26 Jan 2026 10:21:26 -0800",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Mon, Jan 26, 2026 at 01:20:20PM -0400, Jason Gunthorpe wrote:
Hmm, whether we allocate a 2-level cd table would actually depend on
the "1 << cd_table->s1cdmax" v.s. CTXDESC_L2_ENTRIES, right?
If the device supports PASID and s1cdmax is large, we should prepare
a 2-level cd tables, even if only SSID0 is used at thi... | {
"author": "Nicolin Chen <nicolinc@nvidia.com>",
"date": "Mon, 26 Jan 2026 10:40:39 -0800",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On 2026-01-26 5:20 pm, Jason Gunthorpe wrote:
Because it is not possible to enable 0 SubStreams, since that wouldn't
make any sense, hence S1CDMax also acts as the "enable SubStreams"
control (assuming SSIDSIZE > 0 and it does anything at all - note that
strictly we cannot assume this bypass trick is *always* possi... | {
"author": "Robin Murphy <robin.murphy@arm.com>",
"date": "Mon, 26 Jan 2026 18:49:07 +0000",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Mon, Jan 26, 2026 at 06:49:07PM +0000, Robin Murphy wrote:
Yes, I think Nicolin has captured those conditions in computing
it... We don't have a logic to disable bypass in that case though.
Yes
However, taken together:
* S1CDMax is set to substream 0 only
* S1DSS is set such that "does not fetch a CD" for SSI... | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Mon, 26 Jan 2026 15:09:35 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Mon, Jan 26, 2026 at 10:40:39AM -0800, Nicolin Chen wrote:
Yes, this is what arm_smmu_alloc_cd_tables() is doing.
I think will was questioning if this needs to be
arm_smmu_alloc_cd_ptr(master, 0);
To ensure there is some memory under the SSID=0 case, but it seems we
don't need that.
Jason | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Mon, 26 Jan 2026 15:16:57 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | Jason described the flow as "for these secure situations", i.e. not a general
requirement for cxl.cache, but iiuc Dan may instead want userspace policy
opt-in to be default (and with CMA/TSM etc. it gets easier)?
Better to clarity the agreement here as the output decides whether to
continue what this series tries... | {
"author": "\"Tian, Kevin\" <kevin.tian@intel.com>",
"date": "Tue, 27 Jan 2026 08:10:06 +0000",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Mon, Jan 26, 2026 at 03:09:35PM -0400, Jason Gunthorpe wrote:
Right, I think the critical question is whether that setting of S1DSS
(0b01) means that STE.S1ContextPtr is considered "invalid". The spec
doesn't call this out explicitly but the "translation procedure charts"
seem to indicate that it doesn't use the CD... | {
"author": "Will Deacon <will@kernel.org>",
"date": "Tue, 27 Jan 2026 13:10:51 +0000",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On 2026-01-27 1:10 pm, Will Deacon wrote:
No, STE.S1ContextPtr itself is "valid" since S1 is enabled. No CD fetch
will occur for no-SubStreamID transactions that are bypassed by S1DSS,
but the SMMU is permitted to attempt to speculatively fetch CDs for the
enabled SubStreamID(s). Those fetches do not have to reach ... | {
"author": "Robin Murphy <robin.murphy@arm.com>",
"date": "Tue, 27 Jan 2026 13:26:02 +0000",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Tue, Jan 27, 2026 at 01:26:02PM +0000, Robin Murphy wrote:
Argh, I had conflated a transaction using SSID 0 vs a transaction
without a substream at all. So I think this makes sense now...
Thanks,
Will | {
"author": "Will Deacon <will@kernel.org>",
"date": "Tue, 27 Jan 2026 13:50:54 +0000",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Tue, Jan 27, 2026 at 01:50:54PM +0000, Will Deacon wrote:
Yeah, it is bit subtle, but as a SW choice the iommu subsystem
reserves PASID 0/SSID 0 as the "untagged" translation.
Several HW's force this in their implementation (ie AMD)
ARM however includes a "Substream Valid" in the input bus. Linux
doesn't use the ... | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Tue, 27 Jan 2026 10:49:04 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Tue, Jan 27, 2026 at 08:10:06AM +0000, Tian, Kevin wrote:
I think the general strategy has been to push userspace to do security
decisions before binding drivers. So we have a plan for confidential
compute VMs, and if there is interest then we can probably re-use that
plan in all other cases.
Yes.
Yes, ARM too... | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Tue, 27 Jan 2026 11:04:40 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | Jason Gunthorpe wrote:
[..]
Right, if you want to configure a kernel to automatically enable ATS
that is choice. But, as distros get more security concious about devices
for confidential compute, it would be nice to be able to rely on the
same opt-in model for other security concerns like ATS security.
Does this mea... | {
"author": "<dan.j.williams@intel.com>",
"date": "Tue, 27 Jan 2026 16:49:07 -0800",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | make sense
It was made that way by commit 5518f239aff1 ("iommu/vt-d: Move
scalable mode ATS enablement to probe path "). The old policy was
same as AMD side, and changed to current way so domain change
in RID won't affect the ATS requirement for PASIDs.
But I agree BLOCKED is special. Ideally there is no reason to ... | {
"author": "\"Tian, Kevin\" <kevin.tian@intel.com>",
"date": "Wed, 28 Jan 2026 00:57:59 +0000",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Tue, Jan 27, 2026 at 04:49:07PM -0800, dan.j.williams@intel.com wrote:
All of the iommu drivers setup an iommu translation and enable ATS
before any driver is bound.
We would need to do more work in the core to leave the translation
blocked when there is no driver. I don't think it is that difficult
Yes
Jason | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Wed, 28 Jan 2026 09:05:20 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Wed, Jan 28, 2026 at 12:57:59AM +0000, Tian, Kevin wrote:
That's a legimiate thing, but always on is a heavy handed solution.
The driver should track what is going on with the PASID and enable ATS
if required.
Which also solves this:
And is what SMMUv3 is doing already. With an IDENTITY translation on
the RID... | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Wed, 28 Jan 2026 09:11:53 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | yes. at that point the rationale was made purely based on functionality
instead of security.
yes, that should work. In that way the driver binding flow is covered
automatically. | {
"author": "\"Tian, Kevin\" <kevin.tian@intel.com>",
"date": "Thu, 29 Jan 2026 03:28:03 +0000",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Wed, Jan 28, 2026 at 09:05:20AM -0400, Jason Gunthorpe wrote:
Hmm, not sure if we could use group->domain=NULL as "blocked..
Otherwise, I made a draft:
-----------------------------------------------------------------
diff --git a/drivers/base/dd.c b/drivers/base/dd.c
index 349f31bedfa17..8ed15d5ea1f51 100644
--- ... | {
"author": "Nicolin Chen <nicolinc@nvidia.com>",
"date": "Mon, 2 Feb 2026 21:13:50 -0800",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Mon, Feb 02, 2026 at 09:13:50PM -0800, Nicolin Chen wrote:
Definately not, we need to use a proper blocked domain.
We shouldn't need any of these? The dma_configure callback already
gets into the iommu code to validate the domain and restrict VFIO,
no further callbacks should be needed.
When the iommu driver is ... | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Tue, 3 Feb 2026 10:33:48 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Tue, Feb 03, 2026 at 10:33:48AM -0400, Jason Gunthorpe wrote:
Yea, I suspected so.
I was trying to use dev->driver that gets set before dma_configure()
and unset after dma_cleanup(). But looks like we could just keep the
track of group->owner_cnt in iommu_device_use/unuse_default_domain().
Btw, attaching to IOMM... | {
"author": "Nicolin Chen <nicolinc@nvidia.com>",
"date": "Tue, 3 Feb 2026 09:45:17 -0800",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Tue, Feb 03, 2026 at 09:45:17AM -0800, Nicolin Chen wrote:
If require_direct is set then we have to disable this mechanism..
I'm not sure exactly what to do about this as the require_direct comes
from the hypervisor in a CC VM and we probably don't want to give the
hypervisor this kind of escape hatch.
Perhaps we... | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Tue, 3 Feb 2026 13:55:40 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Tue, Feb 03, 2026 at 01:55:40PM -0400, Jason Gunthorpe wrote:
OK. I will put a note in the patch, since it would literally skip
any VM case at this moment.
I just realized a corner case, as iommu_probe_device() may attach
the device to group->domain if it's set:
https://lore.kernel.org/all/9-v5-1b99ae392328+44574-... | {
"author": "Nicolin Chen <nicolinc@nvidia.com>",
"date": "Tue, 3 Feb 2026 10:50:39 -0800",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On 2026-02-03 5:55 pm, Jason Gunthorpe wrote:
No, the point of RMRs in general is that the device can be assumed to
already be accessing them, and that access must be preserved, regardless
of whether an OS driver may or may not take over the device later. In
fact RMRs with the "Remapping Permitted" flag are only st... | {
"author": "Robin Murphy <robin.murphy@arm.com>",
"date": "Tue, 3 Feb 2026 18:59:35 +0000",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Tue, Feb 03, 2026 at 06:59:35PM +0000, Robin Murphy wrote:
I see. Thanks for the input.
Yes. I see that doesn't set require_direct.
Nicolin | {
"author": "Nicolin Chen <nicolinc@nvidia.com>",
"date": "Tue, 3 Feb 2026 11:24:25 -0800",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
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