data_type large_stringclasses 3
values | source large_stringclasses 29
values | code large_stringlengths 98 49.4M | filepath large_stringlengths 5 161 ⌀ | message large_stringclasses 234
values | commit large_stringclasses 234
values | subject large_stringclasses 418
values | critique large_stringlengths 101 1.26M ⌀ | metadata dict |
|---|---|---|---|---|---|---|---|---|
lkml_critique | linux-riscv | This adds poweroff/reboot support for the SpacemiT P1 PMIC chip, which is
commonly paired with the SpacemiT K1 SoC.
Note: For reliable operation, this driver depends on a this patch that adds
atomic transfer support to the SpacemiT I2C controller driver:
https://lore.kernel.org/spacemit/20251009-k1-i2c-atomic-v4-1-a... | null | null | null | [PATCH v5 0/2] driver: reset: spacemit-p1: add driver for poweroff/reboot | On Mon, 03 Nov 2025 00:01:58 +0100, Aurelien Jarno wrote:
Applied, thanks!
[1/2] driver: reset: spacemit-p1: add driver for poweroff/reboot
commit: 28124cc0fb8c7dc01a6834d227351e25d9a92c58
Best regards,
--
Sebastian Reichel <sebastian.reichel@collabora.com>
_______________________________________________
li... | {
"author": "Sebastian Reichel <sebastian.reichel@collabora.com>",
"date": "Mon, 03 Nov 2025 01:48:33 +0100",
"is_openbsd": false,
"thread_id": "20251102230352.914421-1-aurelien@aurel32.net.mbox.gz"
} |
lkml_critique | linux-riscv | This adds poweroff/reboot support for the SpacemiT P1 PMIC chip, which is
commonly paired with the SpacemiT K1 SoC.
Note: For reliable operation, this driver depends on a this patch that adds
atomic transfer support to the SpacemiT I2C controller driver:
https://lore.kernel.org/spacemit/20251009-k1-i2c-atomic-v4-1-a... | null | null | null | [PATCH v5 0/2] driver: reset: spacemit-p1: add driver for poweroff/reboot | On Tue, 04 Nov 2025, Troy Mitchell wrote:
What is the dependency?
--
Lee Jones [李琼斯]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Lee Jones <lee@kernel.org>",
"date": "Wed, 5 Nov 2025 09:34:21 +0000",
"is_openbsd": false,
"thread_id": "20251102230352.914421-1-aurelien@aurel32.net.mbox.gz"
} |
lkml_critique | linux-riscv | This adds poweroff/reboot support for the SpacemiT P1 PMIC chip, which is
commonly paired with the SpacemiT K1 SoC.
Note: For reliable operation, this driver depends on a this patch that adds
atomic transfer support to the SpacemiT I2C controller driver:
https://lore.kernel.org/spacemit/20251009-k1-i2c-atomic-v4-1-a... | null | null | null | [PATCH v5 0/2] driver: reset: spacemit-p1: add driver for poweroff/reboot | On Tue, 04 Nov 2025, Troy Mitchell wrote:
And what is: ^[@kernel.org in your recipients list?
--
Lee Jones [李琼斯]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Lee Jones <lee@kernel.org>",
"date": "Wed, 5 Nov 2025 09:35:44 +0000",
"is_openbsd": false,
"thread_id": "20251102230352.914421-1-aurelien@aurel32.net.mbox.gz"
} |
lkml_critique | linux-riscv | This adds poweroff/reboot support for the SpacemiT P1 PMIC chip, which is
commonly paired with the SpacemiT K1 SoC.
Note: For reliable operation, this driver depends on a this patch that adds
atomic transfer support to the SpacemiT I2C controller driver:
https://lore.kernel.org/spacemit/20251009-k1-i2c-atomic-v4-1-a... | null | null | null | [PATCH v5 0/2] driver: reset: spacemit-p1: add driver for poweroff/reboot | On Wed, Nov 05, 2025 at 09:35:44AM +0000, Lee Jones wrote:
Might have accidentally messed up my email...
- Troy
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Troy Mitchell <troy.mitchell@linux.spacemit.com>",
"date": "Wed, 5 Nov 2025 17:40:29 +0800",
"is_openbsd": false,
"thread_id": "20251102230352.914421-1-aurelien@aurel32.net.mbox.gz"
} |
lkml_critique | linux-riscv | This adds poweroff/reboot support for the SpacemiT P1 PMIC chip, which is
commonly paired with the SpacemiT K1 SoC.
Note: For reliable operation, this driver depends on a this patch that adds
atomic transfer support to the SpacemiT I2C controller driver:
https://lore.kernel.org/spacemit/20251009-k1-i2c-atomic-v4-1-a... | null | null | null | [PATCH v5 0/2] driver: reset: spacemit-p1: add driver for poweroff/reboot | On Wed, Nov 05, 2025 at 09:34:21AM +0000, Lee Jones wrote:
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
dependency is here.
I point it out above.
Without this patch, reboot and shutdown would end up calling the non-atomic i2c_transfer.
- Troy
__________________________... | {
"author": "Troy Mitchell <troy.mitchell@linux.spacemit.com>",
"date": "Wed, 5 Nov 2025 17:42:59 +0800",
"is_openbsd": false,
"thread_id": "20251102230352.914421-1-aurelien@aurel32.net.mbox.gz"
} |
lkml_critique | linux-riscv | This adds poweroff/reboot support for the SpacemiT P1 PMIC chip, which is
commonly paired with the SpacemiT K1 SoC.
Note: For reliable operation, this driver depends on a this patch that adds
atomic transfer support to the SpacemiT I2C controller driver:
https://lore.kernel.org/spacemit/20251009-k1-i2c-atomic-v4-1-a... | null | null | null | [PATCH v5 0/2] driver: reset: spacemit-p1: add driver for poweroff/reboot | On Wed, 05 Nov 2025, Troy Mitchell wrote:
Okay, thanks. I was mostly checking that you weren't referring to the
MFD patch, which doesn't represent a true dependency.
--
Lee Jones [李琼斯]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.o... | {
"author": "Lee Jones <lee@kernel.org>",
"date": "Wed, 5 Nov 2025 10:08:56 +0000",
"is_openbsd": false,
"thread_id": "20251102230352.914421-1-aurelien@aurel32.net.mbox.gz"
} |
lkml_critique | linux-riscv | This adds poweroff/reboot support for the SpacemiT P1 PMIC chip, which is
commonly paired with the SpacemiT K1 SoC.
Note: For reliable operation, this driver depends on a this patch that adds
atomic transfer support to the SpacemiT I2C controller driver:
https://lore.kernel.org/spacemit/20251009-k1-i2c-atomic-v4-1-a... | null | null | null | [PATCH v5 0/2] driver: reset: spacemit-p1: add driver for poweroff/reboot | On Wed, 05 Nov 2025, Lee Jones wrote:
To save Sebastian some trouble, let's keep the reboot patch applied.
I'll hold off on the MFD one, which will ensure that reboot isn't probed.
Let me know when the dep is merged and I'll hoover up the rest of the set.
--
Lee Jones [李琼斯]
______________________________________... | {
"author": "Lee Jones <lee@kernel.org>",
"date": "Wed, 5 Nov 2025 10:11:49 +0000",
"is_openbsd": false,
"thread_id": "20251102230352.914421-1-aurelien@aurel32.net.mbox.gz"
} |
lkml_critique | linux-riscv | This adds poweroff/reboot support for the SpacemiT P1 PMIC chip, which is
commonly paired with the SpacemiT K1 SoC.
Note: For reliable operation, this driver depends on a this patch that adds
atomic transfer support to the SpacemiT I2C controller driver:
https://lore.kernel.org/spacemit/20251009-k1-i2c-atomic-v4-1-a... | null | null | null | [PATCH v5 0/2] driver: reset: spacemit-p1: add driver for poweroff/reboot | On Wed, Nov 05, 2025 at 10:11:49AM +0000, Lee Jones wrote:
Okay. I'll reply this thread when the dependency is merged.
- Troy
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Troy Mitchell <troy.mitchell@linux.spacemit.com>",
"date": "Wed, 5 Nov 2025 21:10:21 +0800",
"is_openbsd": false,
"thread_id": "20251102230352.914421-1-aurelien@aurel32.net.mbox.gz"
} |
lkml_critique | linux-riscv | This adds poweroff/reboot support for the SpacemiT P1 PMIC chip, which is
commonly paired with the SpacemiT K1 SoC.
Note: For reliable operation, this driver depends on a this patch that adds
atomic transfer support to the SpacemiT I2C controller driver:
https://lore.kernel.org/spacemit/20251009-k1-i2c-atomic-v4-1-a... | null | null | null | [PATCH v5 0/2] driver: reset: spacemit-p1: add driver for poweroff/reboot | On 2025-11-05 17:42, Troy Mitchell wrote:
Oh indeed, I have forgotten about this part.
Note however this is not a strong dependency, it is needed to make the
reset or power off reliable. Calling non-atomic i2c_transfer lead to a
successful reset or power off a bit more than half of the time.
Regards
Aurelien
-- ... | {
"author": "Aurelien Jarno <aurelien@aurel32.net>",
"date": "Wed, 5 Nov 2025 23:49:37 +0100",
"is_openbsd": false,
"thread_id": "20251102230352.914421-1-aurelien@aurel32.net.mbox.gz"
} |
lkml_critique | linux-riscv | This adds poweroff/reboot support for the SpacemiT P1 PMIC chip, which is
commonly paired with the SpacemiT K1 SoC.
Note: For reliable operation, this driver depends on a this patch that adds
atomic transfer support to the SpacemiT I2C controller driver:
https://lore.kernel.org/spacemit/20251009-k1-i2c-atomic-v4-1-a... | null | null | null | [PATCH v5 0/2] driver: reset: spacemit-p1: add driver for poweroff/reboot | On Wed, Nov 05, 2025 at 11:49:37PM +0100, Aurelien Jarno wrote:
Oh really? I never had success with the non-atomic transfer.
But however, as Lee pointed out, this patch doesn’t need to do
anything special now.
We only needs to ensure that the MFD part won’t be probed.
- Troy
_______________... | {
"author": "Troy Mitchell <troy.mitchell@linux.spacemit.com>",
"date": "Thu, 6 Nov 2025 09:03:52 +0800",
"is_openbsd": false,
"thread_id": "20251102230352.914421-1-aurelien@aurel32.net.mbox.gz"
} |
lkml_critique | linux-riscv | This adds poweroff/reboot support for the SpacemiT P1 PMIC chip, which is
commonly paired with the SpacemiT K1 SoC.
Note: For reliable operation, this driver depends on a this patch that adds
atomic transfer support to the SpacemiT I2C controller driver:
https://lore.kernel.org/spacemit/20251009-k1-i2c-atomic-v4-1-a... | null | null | null | [PATCH v5 0/2] driver: reset: spacemit-p1: add driver for poweroff/reboot | Hello,
On Mon, 2025-11-03 at 00:02 +0100, Aurelien Jarno wrote:
Perhaps its safe to merge this one now that everything P1 and I2C is
already in linus tip ?
mainline + patch + dts bits enabling i2c8 on the OrangePi RV2 and R2S
allows both to soft reboot as expected.
-Yanko
__________________________________________... | {
"author": "Yanko Kaneti <yaneti@declera.com>",
"date": "Thu, 26 Feb 2026 16:32:58 +0200",
"is_openbsd": false,
"thread_id": "20251102230352.914421-1-aurelien@aurel32.net.mbox.gz"
} |
lkml_critique | linux-riscv | This adds poweroff/reboot support for the SpacemiT P1 PMIC chip, which is
commonly paired with the SpacemiT K1 SoC.
Note: For reliable operation, this driver depends on a this patch that adds
atomic transfer support to the SpacemiT I2C controller driver:
https://lore.kernel.org/spacemit/20251009-k1-i2c-atomic-v4-1-a... | null | null | null | [PATCH v5 0/2] driver: reset: spacemit-p1: add driver for poweroff/reboot | Hi,
On 2026-02-26 16:32, Yanko Kaneti wrote:
Unfortunately, this patchset is still missing:
https://lore.kernel.org/all/20260207-b4-k3-i2c-pio-v7-0-626942d94d91@linux.spacemit.com/
This means the reboots work most of the time, but are not 100% reliable,
and that's the reason why this patch got blocked from merging.... | {
"author": "Aurelien Jarno <aurelien@aurel32.net>",
"date": "Thu, 26 Feb 2026 22:32:32 +0100",
"is_openbsd": false,
"thread_id": "20251102230352.914421-1-aurelien@aurel32.net.mbox.gz"
} |
lkml_critique | linux-riscv | This adds poweroff/reboot support for the SpacemiT P1 PMIC chip, which is
commonly paired with the SpacemiT K1 SoC.
Note: For reliable operation, this driver depends on a this patch that adds
atomic transfer support to the SpacemiT I2C controller driver:
https://lore.kernel.org/spacemit/20251009-k1-i2c-atomic-v4-1-a... | null | null | null | [PATCH v5 0/2] driver: reset: spacemit-p1: add driver for poweroff/reboot | On Thu, 2026-02-26 at 22:32 +0100, Aurelien Jarno wrote:
I see. Thanks. Sounds to me like sometimes working compared to never
working is better , but anyway..
FWIW with this patch and the pio patcheset I get this rcu splat on
reboot (which is still working). Similar splat is there without the pio
patcheset.
..
[ ... | {
"author": "Yanko Kaneti <yaneti@declera.com>",
"date": "Fri, 27 Feb 2026 13:29:53 +0200",
"is_openbsd": false,
"thread_id": "20251102230352.914421-1-aurelien@aurel32.net.mbox.gz"
} |
lkml_critique | linux-riscv | Currently, on GENERIC_IRQ_MULTI_HANDLER or arm64 platforms, the
handle_arch_irq is a pointer which is set during booting, and every
irq processing needs to access it, so it sits in hot code path. We can
use the runtime constant mechanism which was introduced by Linus to
speed up its accessing.
Tested on Sipeed Lichee ... | null | null | null | [PATCH 0/3] use runtime constant to optimize handle_arch_irq access | We will use the runtime constant to optimize the handle_arch_irq
accessing. This is preparation patch.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
include/asm-generic/vmlinux.lds.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/v... | {
"author": "Jisheng Zhang <jszhang@kernel.org>",
"date": "Fri, 20 Feb 2026 17:09:20 +0800",
"is_openbsd": false,
"thread_id": "aZ8JwB2vJ98uab2V@xhacker.mbox.gz"
} |
lkml_critique | linux-riscv | Currently, on GENERIC_IRQ_MULTI_HANDLER or arm64 platforms, the
handle_arch_irq is a pointer which is set during booting, and every
irq processing needs to access it, so it sits in hot code path. We can
use the runtime constant mechanism which was introduced by Linus to
speed up its accessing.
Tested on Sipeed Lichee ... | null | null | null | [PATCH 0/3] use runtime constant to optimize handle_arch_irq access | Currently, on GENERIC_IRQ_MULTI_HANDLER platforms, the handle_arch_irq
is a pointer which is set during booting, and every irq processing needs
to access it, so it sits in hot code path. We can use the
runtime constant mechanism which was introduced by Linus to speed up
its accessing.
Tested on Sipeed Lichee Pi 4A (ri... | {
"author": "Jisheng Zhang <jszhang@kernel.org>",
"date": "Fri, 20 Feb 2026 17:09:21 +0800",
"is_openbsd": false,
"thread_id": "aZ8JwB2vJ98uab2V@xhacker.mbox.gz"
} |
lkml_critique | linux-riscv | Currently, on GENERIC_IRQ_MULTI_HANDLER or arm64 platforms, the
handle_arch_irq is a pointer which is set during booting, and every
irq processing needs to access it, so it sits in hot code path. We can
use the runtime constant mechanism which was introduced by Linus to
speed up its accessing.
Tested on Sipeed Lichee ... | null | null | null | [PATCH 0/3] use runtime constant to optimize handle_arch_irq access | Currently, on arm64 platforms, the handle_arch_irq is a pointer which
is set during booting, and every irq processing needs to access it,
so it sits in hot code path. We can use the runtime constant mechanism
which was introduced by Linus to speed up its accessing.
Tested on Quad CA55 platform, the perf sched benchmar... | {
"author": "Jisheng Zhang <jszhang@kernel.org>",
"date": "Fri, 20 Feb 2026 17:09:22 +0800",
"is_openbsd": false,
"thread_id": "aZ8JwB2vJ98uab2V@xhacker.mbox.gz"
} |
lkml_critique | linux-riscv | Currently, on GENERIC_IRQ_MULTI_HANDLER or arm64 platforms, the
handle_arch_irq is a pointer which is set during booting, and every
irq processing needs to access it, so it sits in hot code path. We can
use the runtime constant mechanism which was introduced by Linus to
speed up its accessing.
Tested on Sipeed Lichee ... | null | null | null | [PATCH 0/3] use runtime constant to optimize handle_arch_irq access | Hi Jisheng,
On Fri, Feb 20, 2026 at 05:09:22PM +0800, Jisheng Zhang wrote:
6.5% is a quite high margin, especially for only one pointer's change.
Maybe it is good to share more info for which compiler you are using,
how you tested and the detailed results.
I played a bit on my juno board on CA73 cores with the comma... | {
"author": "Leo Yan <leo.yan@arm.com>",
"date": "Fri, 20 Feb 2026 12:34:14 +0000",
"is_openbsd": false,
"thread_id": "aZ8JwB2vJ98uab2V@xhacker.mbox.gz"
} |
lkml_critique | linux-riscv | Currently, on GENERIC_IRQ_MULTI_HANDLER or arm64 platforms, the
handle_arch_irq is a pointer which is set during booting, and every
irq processing needs to access it, so it sits in hot code path. We can
use the runtime constant mechanism which was introduced by Linus to
speed up its accessing.
Tested on Sipeed Lichee ... | null | null | null | [PATCH 0/3] use runtime constant to optimize handle_arch_irq access | On Fri, Feb 20, 2026 at 12:34:14PM +0000, Leo Yan wrote:
Hi Leo,
Sure.
aarch64-linux-gnu-gcc version 15.2.0
my kernel defconfig is a minimal arm64 version which disables most
drivers, only keep timer, gic, pll/clk, uart, regulator and i2c controller
The reason is to avoid OS noise as much as possible.
It's also pu... | {
"author": "Jisheng Zhang <jszhang@kernel.org>",
"date": "Fri, 20 Feb 2026 21:16:24 +0800",
"is_openbsd": false,
"thread_id": "aZ8JwB2vJ98uab2V@xhacker.mbox.gz"
} |
lkml_critique | linux-riscv | Currently, on GENERIC_IRQ_MULTI_HANDLER or arm64 platforms, the
handle_arch_irq is a pointer which is set during booting, and every
irq processing needs to access it, so it sits in hot code path. We can
use the runtime constant mechanism which was introduced by Linus to
speed up its accessing.
Tested on Sipeed Lichee ... | null | null | null | [PATCH 0/3] use runtime constant to optimize handle_arch_irq access | On Fri, Feb 20, 2026 at 09:16:24PM +0800, Jisheng Zhang wrote:
BTW: if you remove the abnormal run3 result, you'll find that the
benchmark is improved by ~3.5% on CA73:
(23.159 + 23.702) / 2 = 23.43
(24.258 + 24.224) / 2 = 24.24
(24.24 - 23.43)*100 / 23.43 = ~3.5
_______________________________________________
linux... | {
"author": "Jisheng Zhang <jszhang@kernel.org>",
"date": "Fri, 20 Feb 2026 21:34:14 +0800",
"is_openbsd": false,
"thread_id": "aZ8JwB2vJ98uab2V@xhacker.mbox.gz"
} |
lkml_critique | linux-riscv | Currently, on GENERIC_IRQ_MULTI_HANDLER or arm64 platforms, the
handle_arch_irq is a pointer which is set during booting, and every
irq processing needs to access it, so it sits in hot code path. We can
use the runtime constant mechanism which was introduced by Linus to
speed up its accessing.
Tested on Sipeed Lichee ... | null | null | null | [PATCH 0/3] use runtime constant to optimize handle_arch_irq access | On Fri, Feb 20, 2026 at 09:34:14PM +0800, Jisheng Zhang wrote:
[...]
TBH, I don't think we should subjectively select data. But I agree a
clean test env is important to avoid noise, and I also agree that the
current results already show positive signals.
Thanks,
Leo
_______________________________________________... | {
"author": "Leo Yan <leo.yan@arm.com>",
"date": "Fri, 20 Feb 2026 16:47:38 +0000",
"is_openbsd": false,
"thread_id": "aZ8JwB2vJ98uab2V@xhacker.mbox.gz"
} |
lkml_critique | linux-riscv | Currently, on GENERIC_IRQ_MULTI_HANDLER or arm64 platforms, the
handle_arch_irq is a pointer which is set during booting, and every
irq processing needs to access it, so it sits in hot code path. We can
use the runtime constant mechanism which was introduced by Linus to
speed up its accessing.
Tested on Sipeed Lichee ... | null | null | null | [PATCH 0/3] use runtime constant to optimize handle_arch_irq access | On Fri, Feb 20, 2026 at 04:47:38PM +0000, Leo Yan wrote:
The precondition of this is testing the benchmark properly. And I just
tried perf bench sched in noisy OS, I didn't get the similar abnormal
variance as you got, so I think your run3 result was CA53's result.
This isn't an apple-to-apple comparison.
If possible... | {
"author": "Jisheng Zhang <jszhang@kernel.org>",
"date": "Sat, 21 Feb 2026 08:14:17 +0800",
"is_openbsd": false,
"thread_id": "aZ8JwB2vJ98uab2V@xhacker.mbox.gz"
} |
lkml_critique | linux-riscv | Currently, on GENERIC_IRQ_MULTI_HANDLER or arm64 platforms, the
handle_arch_irq is a pointer which is set during booting, and every
irq processing needs to access it, so it sits in hot code path. We can
use the runtime constant mechanism which was introduced by Linus to
speed up its accessing.
Tested on Sipeed Lichee ... | null | null | null | [PATCH 0/3] use runtime constant to optimize handle_arch_irq access | On Fri, Feb 20 2026 at 17:09, Jisheng Zhang wrote:
The proper solution is to use a static call and update it in
set_handle_irq(). That removes the complete indirect call issue from
the hot path.
Thanks,
tglx
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradea... | {
"author": "Thomas Gleixner <tglx@kernel.org>",
"date": "Sun, 22 Feb 2026 23:06:11 +0100",
"is_openbsd": false,
"thread_id": "aZ8JwB2vJ98uab2V@xhacker.mbox.gz"
} |
lkml_critique | linux-riscv | Currently, on GENERIC_IRQ_MULTI_HANDLER or arm64 platforms, the
handle_arch_irq is a pointer which is set during booting, and every
irq processing needs to access it, so it sits in hot code path. We can
use the runtime constant mechanism which was introduced by Linus to
speed up its accessing.
Tested on Sipeed Lichee ... | null | null | null | [PATCH 0/3] use runtime constant to optimize handle_arch_irq access | On Sat, Feb 21, 2026 at 08:14:17AM +0800, Jisheng Zhang wrote:
[...]
Not true. As said, I tested on CA73. I should say explicitly that I
have hotplugged off CA53 CPUs and run test only on CA73 CPUs.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://li... | {
"author": "Leo Yan <leo.yan@arm.com>",
"date": "Mon, 23 Feb 2026 09:15:47 +0000",
"is_openbsd": false,
"thread_id": "aZ8JwB2vJ98uab2V@xhacker.mbox.gz"
} |
lkml_critique | linux-riscv | Currently, on GENERIC_IRQ_MULTI_HANDLER or arm64 platforms, the
handle_arch_irq is a pointer which is set during booting, and every
irq processing needs to access it, so it sits in hot code path. We can
use the runtime constant mechanism which was introduced by Linus to
speed up its accessing.
Tested on Sipeed Lichee ... | null | null | null | [PATCH 0/3] use runtime constant to optimize handle_arch_irq access | On Fri, Feb 20, 2026 at 05:09:22PM +0800, Jisheng Zhang wrote:
That is a surprisingly large impact. :/
Does this meaningfully actually affect any real workload?
We should treat handle_arch_irq and handle_arch_fiq the same way. Either
both get this, or neither do.
This breaks the default case, since handle_arch_ir... | {
"author": "Mark Rutland <mark.rutland@arm.com>",
"date": "Mon, 23 Feb 2026 12:56:27 +0000",
"is_openbsd": false,
"thread_id": "aZ8JwB2vJ98uab2V@xhacker.mbox.gz"
} |
lkml_critique | linux-riscv | Currently, on GENERIC_IRQ_MULTI_HANDLER or arm64 platforms, the
handle_arch_irq is a pointer which is set during booting, and every
irq processing needs to access it, so it sits in hot code path. We can
use the runtime constant mechanism which was introduced by Linus to
speed up its accessing.
Tested on Sipeed Lichee ... | null | null | null | [PATCH 0/3] use runtime constant to optimize handle_arch_irq access | On Sun, Feb 22, 2026 at 11:06:11PM +0100, Thomas Gleixner wrote:
+ Ard, Mark,
Good idea. The remaining problem is no static call support for current
GENERIC_IRQ_MULTI_HANDLER (or similar, arm64 e.g) platforms.
For arm64, Ard tried to add the static call support[1] in 2021, but
Mark concerned "compiler could easily v... | {
"author": "Jisheng Zhang <jszhang@kernel.org>",
"date": "Mon, 23 Feb 2026 20:41:55 +0800",
"is_openbsd": false,
"thread_id": "aZ8JwB2vJ98uab2V@xhacker.mbox.gz"
} |
lkml_critique | linux-riscv | Currently, on GENERIC_IRQ_MULTI_HANDLER or arm64 platforms, the
handle_arch_irq is a pointer which is set during booting, and every
irq processing needs to access it, so it sits in hot code path. We can
use the runtime constant mechanism which was introduced by Linus to
speed up its accessing.
Tested on Sipeed Lichee ... | null | null | null | [PATCH 0/3] use runtime constant to optimize handle_arch_irq access | On Mon, Feb 23, 2026 at 08:41:55PM +0800, Jisheng Zhang wrote:
There are various reasons for not supporting static calls, and in
general we end up having to have a fall-back path that's *more*
expensive than just loading the pointer.
To be clear, that's ONE specific concern, not the ONLY reason.
As per my other ma... | {
"author": "Mark Rutland <mark.rutland@arm.com>",
"date": "Mon, 23 Feb 2026 13:11:46 +0000",
"is_openbsd": false,
"thread_id": "aZ8JwB2vJ98uab2V@xhacker.mbox.gz"
} |
lkml_critique | linux-riscv | Currently, on GENERIC_IRQ_MULTI_HANDLER or arm64 platforms, the
handle_arch_irq is a pointer which is set during booting, and every
irq processing needs to access it, so it sits in hot code path. We can
use the runtime constant mechanism which was introduced by Linus to
speed up its accessing.
Tested on Sipeed Lichee ... | null | null | null | [PATCH 0/3] use runtime constant to optimize handle_arch_irq access | On Mon, Feb 23, 2026 at 12:56:27PM +0000, Mark Rutland wrote:
all irqs' processing is improved to this extent. The perf sched
bench(an existing and good benchmark to measure IPI) is used to
show how much will be the improvement.
Oops, you're right. If runtime constants is chosen, I will address this
comment. While T... | {
"author": "Jisheng Zhang <jszhang@kernel.org>",
"date": "Mon, 23 Feb 2026 20:58:52 +0800",
"is_openbsd": false,
"thread_id": "aZ8JwB2vJ98uab2V@xhacker.mbox.gz"
} |
lkml_critique | linux-riscv | Currently, on GENERIC_IRQ_MULTI_HANDLER or arm64 platforms, the
handle_arch_irq is a pointer which is set during booting, and every
irq processing needs to access it, so it sits in hot code path. We can
use the runtime constant mechanism which was introduced by Linus to
speed up its accessing.
Tested on Sipeed Lichee ... | null | null | null | [PATCH 0/3] use runtime constant to optimize handle_arch_irq access | On Mon, Feb 23, 2026 at 01:11:46PM +0000, Mark Rutland wrote:
indeed, if arch doesn't support static call, the fall-back addes one
more loading overhead.
This improves generic irq processcing, I think all real workload is affected.
_______________________________________________
linux-riscv mailing list
linux-risc... | {
"author": "Jisheng Zhang <jszhang@kernel.org>",
"date": "Mon, 23 Feb 2026 21:22:44 +0800",
"is_openbsd": false,
"thread_id": "aZ8JwB2vJ98uab2V@xhacker.mbox.gz"
} |
lkml_critique | linux-riscv | Currently, on GENERIC_IRQ_MULTI_HANDLER or arm64 platforms, the
handle_arch_irq is a pointer which is set during booting, and every
irq processing needs to access it, so it sits in hot code path. We can
use the runtime constant mechanism which was introduced by Linus to
speed up its accessing.
Tested on Sipeed Lichee ... | null | null | null | [PATCH 0/3] use runtime constant to optimize handle_arch_irq access | On Mon, Feb 23, 2026 at 09:22:44PM +0800, Jisheng Zhang wrote:
I think you've misunderstood my point.
I'm saying that *even if* arm64 supported static calls, we'd have to
have dynamic fallback paths that are more expensive. For example, where
branch range limitations force indirection via an out-of-line stub,
adding ... | {
"author": "Mark Rutland <mark.rutland@arm.com>",
"date": "Mon, 23 Feb 2026 13:55:32 +0000",
"is_openbsd": false,
"thread_id": "aZ8JwB2vJ98uab2V@xhacker.mbox.gz"
} |
lkml_critique | linux-riscv | Currently, on GENERIC_IRQ_MULTI_HANDLER or arm64 platforms, the
handle_arch_irq is a pointer which is set during booting, and every
irq processing needs to access it, so it sits in hot code path. We can
use the runtime constant mechanism which was introduced by Linus to
speed up its accessing.
Tested on Sipeed Lichee ... | null | null | null | [PATCH 0/3] use runtime constant to optimize handle_arch_irq access | On Fri, Feb 20, 2026 at 5:28 PM Jisheng Zhang <jszhang@kernel.org> wrote:
Thx for the work. It's a visible improvement.
Compared to the original handler pointer approach, this solution
introduces no observable drawbacks. Since the static_call alternative
requires further analysis and consensus, adopting this implement... | {
"author": "Guo Ren <guoren@kernel.org>",
"date": "Tue, 24 Feb 2026 09:40:54 +0800",
"is_openbsd": false,
"thread_id": "aZ8JwB2vJ98uab2V@xhacker.mbox.gz"
} |
lkml_critique | linux-riscv | Currently, on GENERIC_IRQ_MULTI_HANDLER or arm64 platforms, the
handle_arch_irq is a pointer which is set during booting, and every
irq processing needs to access it, so it sits in hot code path. We can
use the runtime constant mechanism which was introduced by Linus to
speed up its accessing.
Tested on Sipeed Lichee ... | null | null | null | [PATCH 0/3] use runtime constant to optimize handle_arch_irq access | On Tue, Feb 24, 2026 at 9:40 AM Guo Ren <guoren@kernel.org> wrote:
Oh, don't forget Mark's suggestion for the uninitialized handler,
which is also suitable for genirq:
"That means that if set_handle_irq() isn't called, an IRQ will result in
a call to that bogus address rather than default_handle_irq(), ..."
Maybe we... | {
"author": "Guo Ren <guoren@kernel.org>",
"date": "Tue, 24 Feb 2026 09:59:11 +0800",
"is_openbsd": false,
"thread_id": "aZ8JwB2vJ98uab2V@xhacker.mbox.gz"
} |
lkml_critique | linux-riscv | Currently, on GENERIC_IRQ_MULTI_HANDLER or arm64 platforms, the
handle_arch_irq is a pointer which is set during booting, and every
irq processing needs to access it, so it sits in hot code path. We can
use the runtime constant mechanism which was introduced by Linus to
speed up its accessing.
Tested on Sipeed Lichee ... | null | null | null | [PATCH 0/3] use runtime constant to optimize handle_arch_irq access | On Fri, Feb 20, 2026 at 5:27 PM Jisheng Zhang <jszhang@kernel.org> wrote:
Reviewed by: Guo Ren (Alibaba Damo Academy) <guoren@kernel.org>
--
Best Regards
Guo Ren
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux... | {
"author": "Guo Ren <guoren@kernel.org>",
"date": "Tue, 24 Feb 2026 10:01:57 +0800",
"is_openbsd": false,
"thread_id": "aZ8JwB2vJ98uab2V@xhacker.mbox.gz"
} |
lkml_critique | linux-riscv | Currently, on GENERIC_IRQ_MULTI_HANDLER or arm64 platforms, the
handle_arch_irq is a pointer which is set during booting, and every
irq processing needs to access it, so it sits in hot code path. We can
use the runtime constant mechanism which was introduced by Linus to
speed up its accessing.
Tested on Sipeed Lichee ... | null | null | null | [PATCH 0/3] use runtime constant to optimize handle_arch_irq access | On Mon, Feb 23, 2026 at 09:15:47AM +0000, Leo Yan wrote:
I tested on quad CA73 platform, I can reproduce the abnormal variance
as you got. This means the series may not alway improve performance
as I expected for *all* CPUs. So I'd like to drop it now.
_______________________________________________
linux-riscv mail... | {
"author": "Jisheng Zhang <jszhang@kernel.org>",
"date": "Wed, 25 Feb 2026 22:40:00 +0800",
"is_openbsd": false,
"thread_id": "aZ8JwB2vJ98uab2V@xhacker.mbox.gz"
} |
lkml_critique | linux-riscv | kvm_riscv_vcpu_aia_rmw_topei() assumes that the per-vCPU IMSIC state has
been initialized once AIA is reported as available and initialized at
the VM level. This assumption does not always hold.
Under fuzzed ioctl sequences, a guest may access the IMSIC TOPEI CSR
before the vCPU IMSIC state is set up. In this case,
vc... | null | null | null | [PATCH v2] RISC-V: KVM: Fix null pointer dereference in kvm_riscv_vcpu_aia_rmw_topei() | On 2/26/2026 4:51 PM, Jiakai Xu wrote:
s/kvm_riscv_vcpu_aia_rmw_topei/kvm_riscv_vcpu_aia_imsic_rmw ?
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Thanks,
Nutty
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-r... | {
"author": "\"Nutty.Liu\" <nutty.liu@hotmail.com>",
"date": "Thu, 26 Feb 2026 17:46:32 +0800",
"is_openbsd": false,
"thread_id": "SE3PR04MB8922DAB758E81D8B16CE44CBF372A@SE3PR04MB8922.apcprd04.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-riscv | Refactor the libunwind support so that whenever a remote target is
available, perf functions using the ELF machine can use that remote
target regardless of what the host/local machine is. Migrate existing
libunwind supported architectures like powerpc, arm64 and loongarch so
that they can work in a cross-architecture w... | null | null | null | [RFC PATCH v1 0/7] perf libunwind multiple remote support | Iterate LIBUNWIND_ARCHS when setting up CONFIG_ and HAVE_ definitions
rather than treating each architecture individually. This sets up the
libunwind build variables and C definitions beyond x86 and
arm/aarch64. The existing naming convention is followed for
compatibility.
Signed-off-by: Ian Rogers <irogers@google.com... | {
"author": "Ian Rogers <irogers@google.com>",
"date": "Tue, 24 Feb 2026 06:29:32 -0800",
"is_openbsd": false,
"thread_id": "CAP-5=fWVU3ktkGAnZQrjQJf+Z5AtQo73BVUhj-nr3H95GdcEJQ@mail.gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | Refactor the libunwind support so that whenever a remote target is
available, perf functions using the ELF machine can use that remote
target regardless of what the host/local machine is. Migrate existing
libunwind supported architectures like powerpc, arm64 and loongarch so
that they can work in a cross-architecture w... | null | null | null | [RFC PATCH v1 0/7] perf libunwind multiple remote support | The separate test files only exist to pass a different #include,
instead have a single source file and pass -include to $(CC) to
include the relevant header file for the architecture being
tested. Generate the rules using a foreach loop. Include tests for all
current libunwind architectures.
Signed-off-by: Ian Rogers ... | {
"author": "Ian Rogers <irogers@google.com>",
"date": "Tue, 24 Feb 2026 06:29:31 -0800",
"is_openbsd": false,
"thread_id": "CAP-5=fWVU3ktkGAnZQrjQJf+Z5AtQo73BVUhj-nr3H95GdcEJQ@mail.gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | Refactor the libunwind support so that whenever a remote target is
available, perf functions using the ELF machine can use that remote
target regardless of what the host/local machine is. Migrate existing
libunwind supported architectures like powerpc, arm64 and loongarch so
that they can work in a cross-architecture w... | null | null | null | [RFC PATCH v1 0/7] perf libunwind multiple remote support | The file was removed in commit e62fae9d9e85 ("perf unwind-libdw: Fix a
cross-arch unwinding bug") but the Build file not updated.
Fixes: commit e62fae9d9e85 ("perf unwind-libdw: Fix a cross-arch unwinding bug")
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/arch/loongarch/util/Build | 1 -
1 file chang... | {
"author": "Ian Rogers <irogers@google.com>",
"date": "Tue, 24 Feb 2026 06:29:33 -0800",
"is_openbsd": false,
"thread_id": "CAP-5=fWVU3ktkGAnZQrjQJf+Z5AtQo73BVUhj-nr3H95GdcEJQ@mail.gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | Refactor the libunwind support so that whenever a remote target is
available, perf functions using the ELF machine can use that remote
target regardless of what the host/local machine is. Migrate existing
libunwind supported architectures like powerpc, arm64 and loongarch so
that they can work in a cross-architecture w... | null | null | null | [RFC PATCH v1 0/7] perf libunwind multiple remote support | Move the libunwind register to perf register mapping functions in
arch/../util/unwind-libunwind.c into a new libunwind-arch
directory. Rename the functions to
__get_perf_regnum_for_unw_regnum_<arch>. Add untested ppc32 and s390
functions. Add a get_perf_regnum_for_unw_regnum function that takes an
ELF machine as well a... | {
"author": "Ian Rogers <irogers@google.com>",
"date": "Tue, 24 Feb 2026 06:29:34 -0800",
"is_openbsd": false,
"thread_id": "CAP-5=fWVU3ktkGAnZQrjQJf+Z5AtQo73BVUhj-nr3H95GdcEJQ@mail.gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | Refactor the libunwind support so that whenever a remote target is
available, perf functions using the ELF machine can use that remote
target regardless of what the host/local machine is. Migrate existing
libunwind supported architectures like powerpc, arm64 and loongarch so
that they can work in a cross-architecture w... | null | null | null | [RFC PATCH v1 0/7] perf libunwind multiple remote support | Flush and finish access are relatively simple calls into libunwind,
move them out struct unwind_libunwind_ops. So that the correct version
can be called, add an e_machine variable to maps. This size regression
will go away when the unwind_libunwind_ops no longer need stashing in
the maps. To set the e_machine up pass i... | {
"author": "Ian Rogers <irogers@google.com>",
"date": "Tue, 24 Feb 2026 06:29:35 -0800",
"is_openbsd": false,
"thread_id": "CAP-5=fWVU3ktkGAnZQrjQJf+Z5AtQo73BVUhj-nr3H95GdcEJQ@mail.gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | Refactor the libunwind support so that whenever a remote target is
available, perf functions using the ELF machine can use that remote
target regardless of what the host/local machine is. Migrate existing
libunwind supported architectures like powerpc, arm64 and loongarch so
that they can work in a cross-architecture w... | null | null | null | [RFC PATCH v1 0/7] perf libunwind multiple remote support | Add a RISC-V implementation for unwinding.
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/util/libunwind-arch/Build | 1 +
.../perf/util/libunwind-arch/libunwind-arch.c | 21 ++
.../perf/util/libunwind-arch/libunwind-arch.h | 22 ++
.../util/libunwind-arch/libunwind-riscv.c | 297 +++++... | {
"author": "Ian Rogers <irogers@google.com>",
"date": "Tue, 24 Feb 2026 06:29:37 -0800",
"is_openbsd": false,
"thread_id": "CAP-5=fWVU3ktkGAnZQrjQJf+Z5AtQo73BVUhj-nr3H95GdcEJQ@mail.gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | Refactor the libunwind support so that whenever a remote target is
available, perf functions using the ELF machine can use that remote
target regardless of what the host/local machine is. Migrate existing
libunwind supported architectures like powerpc, arm64 and loongarch so
that they can work in a cross-architecture w... | null | null | null | [RFC PATCH v1 0/7] perf libunwind multiple remote support | On Tue, Feb 24, 2026 at 06:29:37AM -0800, Ian Rogers wrote:
...
^ copy+paste issue?
Thanks,
drew
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Andrew Jones <andrew.jones@oss.qualcomm.com>",
"date": "Wed, 25 Feb 2026 15:08:54 -0600",
"is_openbsd": false,
"thread_id": "CAP-5=fWVU3ktkGAnZQrjQJf+Z5AtQo73BVUhj-nr3H95GdcEJQ@mail.gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | Refactor the libunwind support so that whenever a remote target is
available, perf functions using the ELF machine can use that remote
target regardless of what the host/local machine is. Migrate existing
libunwind supported architectures like powerpc, arm64 and loongarch so
that they can work in a cross-architecture w... | null | null | null | [RFC PATCH v1 0/7] perf libunwind multiple remote support | On Wed, Feb 25, 2026 at 1:08 PM Andrew Jones
<andrew.jones@oss.qualcomm.com> wrote:
Seems very likely :-) Will fix in v2. I'm still after a way to
generate a compile of libunwind from its github with all the remote
headers built and not just the one for the host I'm on. It seems there
is an Android solution for this, ... | {
"author": "Ian Rogers <irogers@google.com>",
"date": "Wed, 25 Feb 2026 17:34:18 -0800",
"is_openbsd": false,
"thread_id": "CAP-5=fWVU3ktkGAnZQrjQJf+Z5AtQo73BVUhj-nr3H95GdcEJQ@mail.gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | A disconnect status BIT of USB2 PHY need to be cleared, otherwise
it will fail to work properly during next connection when devices
connect to roothub directly.
Fixes: fe4bc1a08638 ("phy: spacemit: support K1 USB2.0 PHY controller")
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
To: Vinod Koul <vkoul@kernel.org>
To: N... | null | null | null | [PATCH v3] phy: k1-usb: add disconnect function support | On Mon, Feb 16, 2026 at 11:26:53PM +0800, Yixun Lan wrote:
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Vladimir Oltean <olteanv@gmail.com>",
"date": "Tue, 17 Feb 2026 00:12:54 +0200",
"is_openbsd": false,
"thread_id": "177220591203.320398.3042297469534840289.b4-ty@kernel.org.mbox.gz"
} |
lkml_critique | linux-riscv | A disconnect status BIT of USB2 PHY need to be cleared, otherwise
it will fail to work properly during next connection when devices
connect to roothub directly.
Fixes: fe4bc1a08638 ("phy: spacemit: support K1 USB2.0 PHY controller")
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
To: Vinod Koul <vkoul@kernel.org>
To: N... | null | null | null | [PATCH v3] phy: k1-usb: add disconnect function support | On Mon, 16 Feb 2026 23:26:53 +0800, Yixun Lan wrote:
Applied, thanks!
[1/1] phy: k1-usb: add disconnect function support
commit: f0cf0a882a02dcf28547f32264f6fd37e9a7b147
Best regards,
--
~Vinod
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://l... | {
"author": "Vinod Koul <vkoul@kernel.org>",
"date": "Fri, 27 Feb 2026 20:55:12 +0530",
"is_openbsd": false,
"thread_id": "177220591203.320398.3042297469534840289.b4-ty@kernel.org.mbox.gz"
} |
lkml_critique | linux-riscv | Guests can control IRQ indices via MMIO. Sanitize them with
array_index_nospec() to prevent speculative out-of-bounds access
to the aplic->irqs[] array.
Similar to arm64 commit 41b87599c743 ("KVM: arm/arm64: vgic: fix possible
spectre-v1 in vgic_get_irq()") and x86 commit 8c86405f606c ("KVM: x86:
Protect ioapic_read_i... | null | null | null | [PATCH] KVM: riscv: Fix Spectre-v1 in APLIC interrupt handling | On 1/16/2026 5:57 PM, Lukas Gerlach wrote:
Seems the above code would be better as follows ?
if (!irq)
continue;
if(aplic->nr_irqs <= irq)
return;
Otherwise,
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Thanks,
Nutty
___... | {
"author": "\"Nutty.Liu\" <nutty.liu@hotmail.com>",
"date": "Mon, 19 Jan 2026 17:59:19 +0800",
"is_openbsd": false,
"thread_id": "CAAhSdy1g7pYoF5uXMx4L9zVkRHd8Fj2SMgsc3MS7sQkh74eELw@mail.gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | Guests can control IRQ indices via MMIO. Sanitize them with
array_index_nospec() to prevent speculative out-of-bounds access
to the aplic->irqs[] array.
Similar to arm64 commit 41b87599c743 ("KVM: arm/arm64: vgic: fix possible
spectre-v1 in vgic_get_irq()") and x86 commit 8c86405f606c ("KVM: x86:
Protect ioapic_read_i... | null | null | null | [PATCH] KVM: riscv: Fix Spectre-v1 in APLIC interrupt handling | On Fri, Jan 16, 2026 at 3:27 PM Lukas Gerlach <lukas.gerlach@cispa.de> wrote:
LGTM.
Reviewed-by: Anup Patel <anup@brainfault.org>
Queued this as fix for Linux-7.0-rcX
Regards,
Anup
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/m... | {
"author": "Anup Patel <anup@brainfault.org>",
"date": "Thu, 26 Feb 2026 11:17:31 +0530",
"is_openbsd": false,
"thread_id": "CAAhSdy1g7pYoF5uXMx4L9zVkRHd8Fj2SMgsc3MS7sQkh74eELw@mail.gmail.com.mbox.gz"
} |
lkml_critique | linux-riscv | The vdso_u_time_data, vdso_u_rng_data, and vdso_u_arch_data arrays
are seen by GCC as single instances (due to their declarations in
include/vdso/datapage.h). When the vdso data pointers are dereferenced
with an offset, GCC thinks there is an access beyond the returned single
instance. These are actually arrays constru... | null | null | null | [PATCH] vdso/datapage: Define vdso data pointers as arrays | On Tue, Feb 24, 2026 at 06:47:20PM -0800, Kees Cook wrote:
I found 2 more places I needed to make "&var" to "var" changes. I'll
send a v2...
--
Kees Cook
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Kees Cook <kees@kernel.org>",
"date": "Wed, 25 Feb 2026 09:24:58 -0800",
"is_openbsd": false,
"thread_id": "202602250924.B0A6F658ED@keescook.mbox.gz"
} |
lkml_critique | linux-riscv | Add a KUnit test for strlen() to verify correctness across
different string lengths and memory alignments. Use vmalloc()
to place the NUL character at the page boundary to ensure
over-reads are detected.
Suggested-by: Kees Cook <kees@kernel.org>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
---
lib/tests/string_ku... | null | null | null | [PATCH v7 1/8] lib/string_kunit: add correctness test for strlen() | This series provides optimized implementations of strnlen(), strchr(),
and strrchr() for the RISC-V architecture. The strnlen() implementation
is derived from the existing optimized strlen(). For strchr() and
strrchr(), the current versions use simple byte-by-byte assembly logic,
which will serve as a baseline for futu... | {
"author": "Feng Jiang <jiangfeng@kylinos.cn>",
"date": "Fri, 30 Jan 2026 10:50:10 +0800",
"is_openbsd": false,
"thread_id": "d0f92b42-529e-493b-9960-581791f29ac3@kylinos.cn.mbox.gz"
} |
lkml_critique | linux-riscv | Add a KUnit test for strlen() to verify correctness across
different string lengths and memory alignments. Use vmalloc()
to place the NUL character at the page boundary to ensure
over-reads are detected.
Suggested-by: Kees Cook <kees@kernel.org>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
---
lib/tests/string_ku... | null | null | null | [PATCH v7 1/8] lib/string_kunit: add correctness test for strlen() | Add a KUnit test for strrchr() to verify correctness across
different string lengths and memory alignments. Use vmalloc()
to place the NUL character at the page boundary to ensure
over-reads are detected.
Suggested-by: Kees Cook <kees@kernel.org>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
---
lib/tests/string_k... | {
"author": "Feng Jiang <jiangfeng@kylinos.cn>",
"date": "Fri, 30 Jan 2026 10:50:13 +0800",
"is_openbsd": false,
"thread_id": "d0f92b42-529e-493b-9960-581791f29ac3@kylinos.cn.mbox.gz"
} |
lkml_critique | linux-riscv | Add a KUnit test for strlen() to verify correctness across
different string lengths and memory alignments. Use vmalloc()
to place the NUL character at the page boundary to ensure
over-reads are detected.
Suggested-by: Kees Cook <kees@kernel.org>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
---
lib/tests/string_ku... | null | null | null | [PATCH v7 1/8] lib/string_kunit: add correctness test for strlen() | Add a KUnit test for strnlen() to verify correctness across
different string lengths and memory alignments. Use vmalloc()
to place the NUL character at the page boundary to ensure
over-reads are detected.
Suggested-by: Andy Shevchenko <andy@kernel.org>
Suggested-by: Kees Cook <kees@kernel.org>
Signed-off-by: Feng Jian... | {
"author": "Feng Jiang <jiangfeng@kylinos.cn>",
"date": "Fri, 30 Jan 2026 10:50:12 +0800",
"is_openbsd": false,
"thread_id": "d0f92b42-529e-493b-9960-581791f29ac3@kylinos.cn.mbox.gz"
} |
lkml_critique | linux-riscv | Add a KUnit test for strlen() to verify correctness across
different string lengths and memory alignments. Use vmalloc()
to place the NUL character at the page boundary to ensure
over-reads are detected.
Suggested-by: Kees Cook <kees@kernel.org>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
---
lib/tests/string_ku... | null | null | null | [PATCH v7 1/8] lib/string_kunit: add correctness test for strlen() | Extend the string benchmarking suite to include strnlen(), strchr(),
and strrchr().
For character search functions strchr() and strrchr(), the benchmark
targets the NUL character. This ensures the entire string is scanned,
providing a consistent measure of full-length processing efficiency
comparable to strlen().
Sug... | {
"author": "Feng Jiang <jiangfeng@kylinos.cn>",
"date": "Fri, 30 Jan 2026 10:50:15 +0800",
"is_openbsd": false,
"thread_id": "d0f92b42-529e-493b-9960-581791f29ac3@kylinos.cn.mbox.gz"
} |
lkml_critique | linux-riscv | Add a KUnit test for strlen() to verify correctness across
different string lengths and memory alignments. Use vmalloc()
to place the NUL character at the page boundary to ensure
over-reads are detected.
Suggested-by: Kees Cook <kees@kernel.org>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
---
lib/tests/string_ku... | null | null | null | [PATCH v7 1/8] lib/string_kunit: add correctness test for strlen() | Add an assembly implementation of strrchr() for RISC-V.
This implementation minimizes instruction count and avoids unnecessary
memory access to the stack. The performance benefits are most visible
on small workloads (1-16 bytes) where the architectural savings in
function overhead outweigh the execution time of the sc... | {
"author": "Feng Jiang <jiangfeng@kylinos.cn>",
"date": "Fri, 30 Jan 2026 10:50:18 +0800",
"is_openbsd": false,
"thread_id": "d0f92b42-529e-493b-9960-581791f29ac3@kylinos.cn.mbox.gz"
} |
lkml_critique | linux-riscv | Add a KUnit test for strlen() to verify correctness across
different string lengths and memory alignments. Use vmalloc()
to place the NUL character at the page boundary to ensure
over-reads are detected.
Suggested-by: Kees Cook <kees@kernel.org>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
---
lib/tests/string_ku... | null | null | null | [PATCH v7 1/8] lib/string_kunit: add correctness test for strlen() | Introduce a benchmarking framework to the string_kunit test suite to
measure the execution efficiency of string functions.
The implementation is inspired by crc_benchmark(), measuring throughput
(MB/s) and latency (ns/call) across a range of string lengths. It
includes a warm-up phase, disables preemption during measu... | {
"author": "Feng Jiang <jiangfeng@kylinos.cn>",
"date": "Fri, 30 Jan 2026 10:50:14 +0800",
"is_openbsd": false,
"thread_id": "d0f92b42-529e-493b-9960-581791f29ac3@kylinos.cn.mbox.gz"
} |
lkml_critique | linux-riscv | Add a KUnit test for strlen() to verify correctness across
different string lengths and memory alignments. Use vmalloc()
to place the NUL character at the page boundary to ensure
over-reads are detected.
Suggested-by: Kees Cook <kees@kernel.org>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
---
lib/tests/string_ku... | null | null | null | [PATCH v7 1/8] lib/string_kunit: add correctness test for strlen() | Add an assembly implementation of strchr() for RISC-V.
By eliminating stack frame management (prologue/epilogue) and optimizing
the function entries, the assembly version provides significant relative
gains for short strings where the fixed overhead of the C function is
most prominent. As string length increases, perf... | {
"author": "Feng Jiang <jiangfeng@kylinos.cn>",
"date": "Fri, 30 Jan 2026 10:50:17 +0800",
"is_openbsd": false,
"thread_id": "d0f92b42-529e-493b-9960-581791f29ac3@kylinos.cn.mbox.gz"
} |
lkml_critique | linux-riscv | Add a KUnit test for strlen() to verify correctness across
different string lengths and memory alignments. Use vmalloc()
to place the NUL character at the page boundary to ensure
over-reads are detected.
Suggested-by: Kees Cook <kees@kernel.org>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
---
lib/tests/string_ku... | null | null | null | [PATCH v7 1/8] lib/string_kunit: add correctness test for strlen() | Add an optimized strnlen() implementation for RISC-V. This version
includes a generic optimization and a Zbb-powered optimization using
the 'orc.b' instruction, derived from the strlen() implementation.
Benchmark results (QEMU TCG, rv64):
Length | Original (MB/s) | Optimized (MB/s) | Improvement
-------|----------... | {
"author": "Feng Jiang <jiangfeng@kylinos.cn>",
"date": "Fri, 30 Jan 2026 10:50:16 +0800",
"is_openbsd": false,
"thread_id": "d0f92b42-529e-493b-9960-581791f29ac3@kylinos.cn.mbox.gz"
} |
lkml_critique | linux-riscv | Add a KUnit test for strlen() to verify correctness across
different string lengths and memory alignments. Use vmalloc()
to place the NUL character at the page boundary to ensure
over-reads are detected.
Suggested-by: Kees Cook <kees@kernel.org>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
---
lib/tests/string_ku... | null | null | null | [PATCH v7 1/8] lib/string_kunit: add correctness test for strlen() | On Fri, Jan 30, 2026 at 10:50:12AM +0800, Feng Jiang wrote:
Reviewed-by: Kees Cook <kees@kernel.org>
--
Kees Cook
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Kees Cook <kees@kernel.org>",
"date": "Fri, 30 Jan 2026 09:34:50 -0800",
"is_openbsd": false,
"thread_id": "d0f92b42-529e-493b-9960-581791f29ac3@kylinos.cn.mbox.gz"
} |
lkml_critique | linux-riscv | Add a KUnit test for strlen() to verify correctness across
different string lengths and memory alignments. Use vmalloc()
to place the NUL character at the page boundary to ensure
over-reads are detected.
Suggested-by: Kees Cook <kees@kernel.org>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
---
lib/tests/string_ku... | null | null | null | [PATCH v7 1/8] lib/string_kunit: add correctness test for strlen() | On Fri, Jan 30, 2026 at 10:50:13AM +0800, Feng Jiang wrote:
Reviewed-by: Kees Cook <kees@kernel.org>
--
Kees Cook
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Kees Cook <kees@kernel.org>",
"date": "Fri, 30 Jan 2026 09:34:58 -0800",
"is_openbsd": false,
"thread_id": "d0f92b42-529e-493b-9960-581791f29ac3@kylinos.cn.mbox.gz"
} |
lkml_critique | linux-riscv | Add a KUnit test for strlen() to verify correctness across
different string lengths and memory alignments. Use vmalloc()
to place the NUL character at the page boundary to ensure
over-reads are detected.
Suggested-by: Kees Cook <kees@kernel.org>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
---
lib/tests/string_ku... | null | null | null | [PATCH v7 1/8] lib/string_kunit: add correctness test for strlen() | On Fri, Jan 30, 2026 at 10:50:11AM +0800, Feng Jiang wrote:
Reviewed-by: Kees Cook <kees@kernel.org>
--
Kees Cook
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Kees Cook <kees@kernel.org>",
"date": "Fri, 30 Jan 2026 09:34:42 -0800",
"is_openbsd": false,
"thread_id": "d0f92b42-529e-493b-9960-581791f29ac3@kylinos.cn.mbox.gz"
} |
lkml_critique | linux-riscv | Add a KUnit test for strlen() to verify correctness across
different string lengths and memory alignments. Use vmalloc()
to place the NUL character at the page boundary to ensure
over-reads are detected.
Suggested-by: Kees Cook <kees@kernel.org>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
---
lib/tests/string_ku... | null | null | null | [PATCH v7 1/8] lib/string_kunit: add correctness test for strlen() | On Fri, Jan 30, 2026 at 10:50:14AM +0800, Feng Jiang wrote:
Reviewed-by: Kees Cook <kees@kernel.org>
--
Kees Cook
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Kees Cook <kees@kernel.org>",
"date": "Fri, 30 Jan 2026 09:35:42 -0800",
"is_openbsd": false,
"thread_id": "d0f92b42-529e-493b-9960-581791f29ac3@kylinos.cn.mbox.gz"
} |
lkml_critique | linux-riscv | Add a KUnit test for strlen() to verify correctness across
different string lengths and memory alignments. Use vmalloc()
to place the NUL character at the page boundary to ensure
over-reads are detected.
Suggested-by: Kees Cook <kees@kernel.org>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
---
lib/tests/string_ku... | null | null | null | [PATCH v7 1/8] lib/string_kunit: add correctness test for strlen() | On Fri, Jan 30, 2026 at 10:50:15AM +0800, Feng Jiang wrote:
Reviewed-by: Kees Cook <kees@kernel.org>
--
Kees Cook
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Kees Cook <kees@kernel.org>",
"date": "Fri, 30 Jan 2026 09:35:52 -0800",
"is_openbsd": false,
"thread_id": "d0f92b42-529e-493b-9960-581791f29ac3@kylinos.cn.mbox.gz"
} |
lkml_critique | linux-riscv | Add a KUnit test for strlen() to verify correctness across
different string lengths and memory alignments. Use vmalloc()
to place the NUL character at the page boundary to ensure
over-reads are detected.
Suggested-by: Kees Cook <kees@kernel.org>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
---
lib/tests/string_ku... | null | null | null | [PATCH v7 1/8] lib/string_kunit: add correctness test for strlen() | On Fri, Jan 30, 2026 at 10:50:10AM +0800, Feng Jiang wrote:
I'm happy with the Kunit elements here, so unless Andy has other
feedback, please feel free to take this via the riscv tree. (Or if riscv
maintainers would prefer, I can take it via string.)
Thanks for working on this!
-Kees
--
Kees Cook
________________... | {
"author": "Kees Cook <kees@kernel.org>",
"date": "Fri, 30 Jan 2026 09:37:36 -0800",
"is_openbsd": false,
"thread_id": "d0f92b42-529e-493b-9960-581791f29ac3@kylinos.cn.mbox.gz"
} |
lkml_critique | linux-riscv | Add a KUnit test for strlen() to verify correctness across
different string lengths and memory alignments. Use vmalloc()
to place the NUL character at the page boundary to ensure
over-reads are detected.
Suggested-by: Kees Cook <kees@kernel.org>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
---
lib/tests/string_ku... | null | null | null | [PATCH v7 1/8] lib/string_kunit: add correctness test for strlen() | On Fri, Jan 30, 2026 at 09:37:36AM -0800, Kees Cook wrote:
I have an impression that I already gave some tag. Why aren't not here?
--
With Best Regards,
Andy Shevchenko
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listi... | {
"author": "Andy Shevchenko <andriy.shevchenko@intel.com>",
"date": "Sat, 31 Jan 2026 11:52:28 +0200",
"is_openbsd": false,
"thread_id": "d0f92b42-529e-493b-9960-581791f29ac3@kylinos.cn.mbox.gz"
} |
lkml_critique | linux-riscv | Add a KUnit test for strlen() to verify correctness across
different string lengths and memory alignments. Use vmalloc()
to place the NUL character at the page boundary to ensure
over-reads are detected.
Suggested-by: Kees Cook <kees@kernel.org>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
---
lib/tests/string_ku... | null | null | null | [PATCH v7 1/8] lib/string_kunit: add correctness test for strlen() | On 2026/1/31 17:52, Andy Shevchenko wrote:
I apologize for the confusion.
In v6, following Kees Cook's suggestion, I introduced a significant change to
the correctness test logic—using vmalloc() and page-boundary alignment to
detect over-reads. Since this part of the code was substantially rewritten,
I felt it was mo... | {
"author": "Feng Jiang <jiangfeng@kylinos.cn>",
"date": "Mon, 2 Feb 2026 09:28:06 +0800",
"is_openbsd": false,
"thread_id": "d0f92b42-529e-493b-9960-581791f29ac3@kylinos.cn.mbox.gz"
} |
lkml_critique | linux-riscv | Add a KUnit test for strlen() to verify correctness across
different string lengths and memory alignments. Use vmalloc()
to place the NUL character at the page boundary to ensure
over-reads are detected.
Suggested-by: Kees Cook <kees@kernel.org>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
---
lib/tests/string_ku... | null | null | null | [PATCH v7 1/8] lib/string_kunit: add correctness test for strlen() | On 2026/1/31 01:37, Kees Cook wrote:
Thank you very much for your review and the previous suggestions for improvement.
I truly appreciate your patience and guidance throughout this process!
--
With Best Regards,
Feng Jiang
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.i... | {
"author": "Feng Jiang <jiangfeng@kylinos.cn>",
"date": "Mon, 2 Feb 2026 11:24:07 +0800",
"is_openbsd": false,
"thread_id": "d0f92b42-529e-493b-9960-581791f29ac3@kylinos.cn.mbox.gz"
} |
lkml_critique | linux-riscv | Add a KUnit test for strlen() to verify correctness across
different string lengths and memory alignments. Use vmalloc()
to place the NUL character at the page boundary to ensure
over-reads are detected.
Suggested-by: Kees Cook <kees@kernel.org>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
---
lib/tests/string_ku... | null | null | null | [PATCH v7 1/8] lib/string_kunit: add correctness test for strlen() | On 2026/1/30 10:50, Feng Jiang wrote:
Hi Palmer,
Just a gentle ping on this v7 series.
Kees is happy for this to go through the riscv tree. I've also followed up
with Andy regarding the tags for v7 on the mailing list.
Is there anything else needed for this series to be picked up?
--
With Best Regards,
Feng Jiang... | {
"author": "Feng Jiang <jiangfeng@kylinos.cn>",
"date": "Thu, 26 Feb 2026 10:33:39 +0800",
"is_openbsd": false,
"thread_id": "d0f92b42-529e-493b-9960-581791f29ac3@kylinos.cn.mbox.gz"
} |
lkml_critique | linux-riscv | Add a KUnit test for strlen() to verify correctness across
different string lengths and memory alignments. Use vmalloc()
to place the NUL character at the page boundary to ensure
over-reads are detected.
Suggested-by: Kees Cook <kees@kernel.org>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
---
lib/tests/string_ku... | null | null | null | [PATCH v7 1/8] lib/string_kunit: add correctness test for strlen() | On 2026/1/30 10:50, Feng Jiang wrote:
Hi Paul,
I'm very sorry, I dropped you from the 'To' list by mistake in v7.
Adding you back now for visibility.
--
With Best Regards,
Feng Jiang
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org... | {
"author": "Feng Jiang <jiangfeng@kylinos.cn>",
"date": "Thu, 26 Feb 2026 14:12:42 +0800",
"is_openbsd": false,
"thread_id": "d0f92b42-529e-493b-9960-581791f29ac3@kylinos.cn.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | From: Jingyu Li <joey.li@spacemit.com>
Enables IOMMU DMA mapping support for RISC-V, so that DMACs can be tested
with translation enabled.
Known Issue:
1. When CONFIG_IOMMU_DMA is enabled, current Linux RISC-V IOMMU is lack
of PCIe support, causing riscv_iommu_fault:522 in dealing with NVMe
PCIe devices... | {
"author": "\"Lv Zheng\" <lv.zheng@spacemit.com>",
"date": "Thu, 29 Jan 2026 14:08:42 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | From: Jingyu Li <joey.li@spacemit.com>
In WSI mode, ICVEC doesn't exist, thus reading it returns 0, which
causes IOMMU driver to fail to find IRQ numbers from device tree
IRQ arrary. The issue is fixed by applying icvec indexes of WSI IRQs.
Signed-off-by: Jingyu Li <joey.li@spacemit.com>
Signed-off-by: Lv Zheng <lv.z... | {
"author": "\"Lv Zheng\" <lv.zheng@spacemit.com>",
"date": "Thu, 29 Jan 2026 14:08:50 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | From: Jingyu Li <joey.li@spacemit.com>
Introduces perf-based HPM driver for RISC-V IOMMU, enabling performance
monitoring capabilities.
Note that the RISC-V IOMMU HPM module uses COUNTER_MAX-1 as a static
counter index of HPMCYCLES, and 0~COUNTER_MAX-2 as the dynamic counter
indexes of other HPMEVENTS in order to cor... | {
"author": "\"Lv Zheng\" <lv.zheng@spacemit.com>",
"date": "Thu, 29 Jan 2026 14:08:58 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | Adds device tree bindings for SpacemiT T100 specific features.
vendor-hpm-events: Allow vendor events to be customized in the device
tree.
global-filter: The feature saves silicon area by reducing filters to
one and use it as a global filter across all events.
This usua... | {
"author": "\"Lv Zheng\" <lv.zheng@spacemit.com>",
"date": "Thu, 29 Jan 2026 14:09:13 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | Adds mechanism to allow vendor events to be registered via device tree.
This is useful to support SpacemiT T100 IOMMU where the maximum 128 event
IDs should be supported by T100 IOATS.
Signed-off-by: Lv Zheng <lv.zheng@spacemit.com>
Signed-off-by: Jingyu Li <joey.li@spacemit.com>
---
drivers/iommu/riscv/iommu-bits.h ... | {
"author": "\"Lv Zheng\" <lv.zheng@spacemit.com>",
"date": "Thu, 29 Jan 2026 14:09:21 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | Introduces global filter support for RISC-V IOMMU HPM. The global filter
can be seen in SpacemiT T100 which only supports single filter to be
applied to all event counters. This silicon design can save the number of
the event bus signals.
Signed-off-by: Lv Zheng <lv.zheng@spacemit.com>
Signed-off-by: Jingyu Li <joey.l... | {
"author": "\"Lv Zheng\" <lv.zheng@spacemit.com>",
"date": "Thu, 29 Jan 2026 14:09:29 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | Adds IOATC discovery and HPM support for SpacemiT T100.
SpacemiT T100 supports distributed architecture which allows IOTLBs to be
cached in adjacent to the DMA masters. Such IOTLBs controllers are called
as IOATC, this patch adds distributed HPM support for IOATCs.
Signed-off-by: Lv Zheng <lv.zheng@spacemit.com>
Sign... | {
"author": "\"Lv Zheng\" <lv.zheng@spacemit.com>",
"date": "Thu, 29 Jan 2026 14:09:37 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | _______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv | {
"author": "Conor Dooley <conor@kernel.org>",
"date": "Thu, 29 Jan 2026 10:08:06 +0000",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | The specification only defines less than 10 standard event types while the
real silicons should have implemented many other event types based on
their micro-architecture. I tried to provide a common mechanism for all
vendor specific event types across different vendors.
It is similar for the global filter, the global ... | {
"author": "=?utf-8?q?=E9=83=91=E5=BE=8B?= <lv.zheng@spacemit.com>",
"date": "Thu, 29 Jan 2026 18:43:03 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On 29/01/2026 4:41 pm, Conor Dooley wrote:
Also, reinventing jevents via devicetree is pretty grim anyway - the PMU
can simply expose an "identifier" attribute that uniquely identifies the
vendor implementation, and perf tooling can match that to a set of event
definitions in userspace, with the added bonus that je... | {
"author": "Robin Murphy <robin.murphy@arm.com>",
"date": "Thu, 29 Jan 2026 17:06:00 +0000",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | Thanks for the idea. It sounds great and I'll give it a try.
Best regards,
Lv
This message and any attachment are confidential and may be privileged or otherwise protected from disclosure. If you are not an intended recipient of this message, please delete it and any attachment from your system and notify the sende... | {
"author": "=?utf-8?q?=E9=83=91=E5=BE=8B?= <lv.zheng@spacemit.com>",
"date": "Fri, 30 Jan 2026 09:30:34 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | I'll give Robin's suggestion a try.
I see. This sounds like a reasonable rule of DT attributes. I'll do similar
stuffs based on compatible.
Thanks and best regards,
Lv
This message and any attachment are confidential and may be privileged or otherwise protected from disclosure. If you are not an intended recipient... | {
"author": "=?utf-8?q?=E9=83=91=E5=BE=8B?= <lv.zheng@spacemit.com>",
"date": "Fri, 30 Jan 2026 09:39:38 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | Includes HPM support for RISC-V IOMMU. The HPM hardware mechanism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
Revisions:
v1
Initial release.
v2 (sent as v1.1)
Split and cleanup DT-bindings.
v3
Refactor using vendor specific compatible.
The tes... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Wed, 4 Feb 2026 17:08:19 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | From: Jingyu Li <joey.li@spacemit.com>
Enables IOMMU DMA mapping support for RISC-V, so that DMACs can be tested
with translation enabled.
Known Possible Issue:
1. When CONFIG_IOMMU_DMA is enabled, on the tested Linux, RISC-V IOMMU is
lack of PCIe support, causing riscv_iommu_fault:522 in dealing with
NVMe PCIe... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Wed, 4 Feb 2026 17:08:39 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | From: Jingyu Li <joey.li@spacemit.com>
In WSI mode, ICVEC doesn't exist, thus reading it returns 0, which
causes IOMMU driver to fail to find IRQ numbers from device tree
IRQ arrary. The issue is fixed by applying icvec indexes of WSI IRQs.
Signed-off-by: Jingyu Li <joey.li@spacemit.com>
Signed-off-by: Lv Zheng <lv.z... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Wed, 4 Feb 2026 17:08:52 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | From: Jingyu Li <joey.li@spacemit.com>
Introduces perf-based HPM driver for RISC-V IOMMU, enabling performance
monitoring capabilities.
Note that the RISC-V IOMMU HPM module uses COUNTER_MAX-1 as a static
counter index of HPMCYCLES, and 0~COUNTER_MAX-2 as the dynamic counter
indexes of other HPMEVENTS in order to cor... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Wed, 4 Feb 2026 17:09:01 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | Adds device tree bindings for SpacemiT T100 specific features by
introducing spacemit,100 compatible. T100 contains distributed IOATCs,
each of which exposes pmiv interrupt.
Signed-off-by: Lv Zheng <lv.zheng@linux.spacemit.com>
Signed-off-by: Jingyu Li <joey.li@spacemit.com>
---
.../bindings/iommu/riscv,iommu.yaml ... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Wed, 4 Feb 2026 17:09:12 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | Adds mechanism to allow vendor events to be registered via userspace
jevents. By default, vendor event identifier matches "riscv,iommu", and
the events are registered as "riscv_iommu_hpm" events.
Signed-off-by: Lv Zheng <lv.zheng@linux.spacemit.com>
Signed-off-by: Jingyu Li <joey.li@spacemit.com>
---
drivers/iommu/ri... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Wed, 4 Feb 2026 17:09:21 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | Introduces global filter support for RISC-V IOMMU HPM. The global filter
can be seen in SpacemiT T100 which only supports single filter to be
applied to all event counters.
Drivers can program filters in each iohpmevt registers as normal in such a
silicon design, however the underlying hardware filters are wired toget... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Wed, 4 Feb 2026 17:09:31 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | Adds IOATC discovery and HPM support for SpacemiT T100.
SpacemiT T100 supports distributed architecture which allows IOTLBs to be
cached in adjacent to the DMA masters. Such IOTLB controllers are called
as IOATCs. Adds distributed HPM support for IOATCs.
Signed-off-by: Lv Zheng <lv.zheng@linux.spacemit.com>
Signed-of... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Wed, 4 Feb 2026 17:09:41 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | Add JSON HPM event aliases for SpacemiT distributed IOMMU (T100) which is
general and compatible for all SpacemiT RISC-V SoCs.
Signed-off-by: Lv Zheng <lv.zheng@linux.spacemit.com>
Signed-off-by: Jingyu Li <joey.li@spacemit.com>
---
MAINTAINERS | 3 +
.../arch/riscv/spacemit/iommu/... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Wed, 4 Feb 2026 17:09:52 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On Wed, Feb 04, 2026 at 05:08:52PM +0800, Lv Zheng wrote:
ICVEC always exists, however it may be hardwired to zero when an
implementation only supports a single vector. But, that has nothing
to do with whether wired interrupts or MSIs are used.
If ICVEC on this IOMMU is always reading as zero, even when 0xf is
writte... | {
"author": "Andrew Jones <andrew.jones@oss.qualcomm.com>",
"date": "Wed, 4 Feb 2026 11:20:03 -0600",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | How does this relate to
https://lore.kernel.org/all/20250115030306.29735-1-zong.li@sifive.com/
Thanks,
drew
On Wed, Feb 04, 2026 at 05:09:01PM +0800, Lv Zheng wrote:
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinf... | {
"author": "Andrew Jones <andrew.jones@oss.qualcomm.com>",
"date": "Wed, 4 Feb 2026 12:39:41 -0600",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On Thu, Feb 5, 2026 at 2:39 AM Andrew Jones
<andrew.jones@oss.qualcomm.com> wrote:
Hi all,
Thanks Andrew for bringing me here, and sorry for the long delay on
the IOMMU PMU driver series.
I’m currently working on the next version to incorporate the feedback
from my earlier series. The main goals are to decouple the ... | {
"author": "Zong Li <zong.li@sifive.com>",
"date": "Thu, 5 Feb 2026 10:11:26 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On 2/5/2026 1:37 AM, Conor Dooley wrote:
T100 is the name of the IOMMU IP developed by SpacemiT, announced in
RISC-V 2024 China Summit:
https://www.bilibili.com/video/BV1DNtCeiEBk/
It's world first server SPEC IOMMU in RISC-V, supports IOTLB placed in
adjacent to the DMA masters and supports PCIe ATS and PRI.
You ca... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Thu, 5 Feb 2026 11:11:51 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On 2/5/2026 1:38 AM, Conor Dooley wrote:
Should this be a big deal?
I've been working as kernel maintainers for 5 years (you can find me in
git log using Lv Zheng <lv.zheng@intel.com>) and given the fact that I'm
also the silicon designer of SpacemiT T100, played an active role in
IOMMU spec community, I'm ready to... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Thu, 5 Feb 2026 11:22:42 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On 2/5/2026 2:39 AM, Andrew Jones wrote:
We developed the driver in 2024 and demonstrated it in China summit. We
didn't notice that a patch is on-going now in the community.
Now it looks our approach solved more issues, and we'll check and update
if there are any community concerns still not addressed in this patch... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Thu, 5 Feb 2026 11:35:01 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On Thu, Feb 5, 2026 at 11:35 AM Lv Zheng <lv.zheng@linux.spacemit.com> wrote:
Perhaps I can first post my next revision to the mailing list (hope it
won't waste the community resource), so that you could have a chance
to review it and see whether that version is architecturally closer to
what the community is looking ... | {
"author": "Zong Li <zong.li@sifive.com>",
"date": "Thu, 5 Feb 2026 11:47:07 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On 2/5/2026 1:20 AM, Andrew Jones wrote:
Indeed.
It looks I can keep icvec returned for WSI and keeps the write-and-read
check logic only for MSI.
Thanks,
Lv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Thu, 5 Feb 2026 11:52:57 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | On 2/5/2026 11:47 AM, Zong Li wrote:
It seems we all composed the RISC-V iommu HPM support by referencing
drivers/perf/arm_smmuv3_pmu.
Robin's comments should all be addressed IMHO.
OK. If we send a next version, we will add your SOB and please help to
review and test.
Thanks in advance,
Lv
_________________... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Thu, 5 Feb 2026 14:11:48 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | Includes HPM support for RISC-V IOMMU. The HPM hardware mechanism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
Revisions:
v1
Initial release.
v2 (sent as v1.1)
Split and cleanup DT-bindings.
v3
1. Refactor using vendor specific compatible.
2. I... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Thu, 5 Feb 2026 17:09:59 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | From: Jingyu Li <joey.li@spacemit.com>
Introduces perf-based HPM driver for RISC-V IOMMU, enabling performance
monitoring capabilities.
Note that the RISC-V IOMMU HPM module uses COUNTER_MAX-1 as a static
counter index of HPMCYCLES, and 0~COUNTER_MAX-2 as the dynamic counter
indexes of other HPMEVENTS in order to cor... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Thu, 5 Feb 2026 17:10:34 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | Adds device tree bindings for SpacemiT T100 specific features by
introducing spacemit,100 compatible. T100 contains distributed IOATCs,
each of which exposes pmiv interrupt.
Signed-off-by: Lv Zheng <lv.zheng@linux.spacemit.com>
Signed-off-by: Jingyu Li <joey.li@spacemit.com>
---
.../bindings/iommu/riscv,iommu.yaml ... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Thu, 5 Feb 2026 17:10:43 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
lkml_critique | linux-riscv | Includes HPM support for RISC-V IOMMU. The HPM hardware mechnism can be
found in the recent announced SpacemiT SoCs (K3, V100), where T100
(SpacemiT distributed IOMMU) is shipped.
The tested result can be found as follows:
root@sdfirm:~# perf stat --timeout 5000 -a -e riscv_iommu_hpm_0/device_dir_walks,config1=0x20... | null | null | null | [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU | Adds mechanism to allow vendor events to be registered via userspace
jevents. By default, vendor event identifier matches "riscv,iommu", and
the events are registered as "riscv_iommu_hpm" events.
Signed-off-by: Lv Zheng <lv.zheng@linux.spacemit.com>
Signed-off-by: Jingyu Li <joey.li@spacemit.com>
---
drivers/iommu/ri... | {
"author": "Lv Zheng <lv.zheng@linux.spacemit.com>",
"date": "Thu, 5 Feb 2026 17:10:53 +0800",
"is_openbsd": false,
"thread_id": "81DC457427F3336D+a6fef8d6-cb0c-4ac0-bb18-49d22ccda4b3@linux.spacemit.com.mbox.gz"
} |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.