data_type large_stringclasses 3
values | source large_stringclasses 29
values | code large_stringlengths 98 49.4M | filepath large_stringlengths 5 161 ⌀ | message large_stringclasses 234
values | commit large_stringclasses 234
values | subject large_stringclasses 418
values | critique large_stringlengths 101 1.26M ⌀ | metadata dict |
|---|---|---|---|---|---|---|---|---|
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Tue, Feb 03, 2026 at 06:59:35PM +0000, Robin Murphy wrote:
This thread has gotten mixed up..
First this series as it is has nothing to do with RMRs.
What the latter part is discussing is a future series to implement
what I think MS calls "boot DMA security". Meaning we don't get into a
position of allowing a devi... | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Tue, 3 Feb 2026 19:16:07 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On 2026-02-03 11:16 pm, Jason Gunthorpe wrote:
I know, but you brought up require_direct so I figured it was worth
clarifying that should not in fact impact ATS decisions, since the
combination a device requiring ATS while *also* requiring an RMR would
be essentially impossible to support given the SMMU architectur... | {
"author": "Robin Murphy <robin.murphy@arm.com>",
"date": "Wed, 4 Feb 2026 12:18:15 +0000",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Wed, Feb 04, 2026 at 12:18:15PM +0000, Robin Murphy wrote:
Splash screens are the most obvious case here where the framebuffer
may be in DMA'able memory and must go through the iommu..
At least we are already shipping products where the GPU has DRAM based
framebuffer, the GPU requires ATS for alot of functions, bu... | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Wed, 4 Feb 2026 09:20:31 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Tue, Feb 03, 2026 at 10:50:39AM -0800, Nicolin Chen wrote:
Just to be clear this is some other project "DMA boot security" and
IDK if we need to do it until the CC patches land for user space
device binding policy, or someone seriously implements DRTM..
Jason | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Wed, 4 Feb 2026 09:21:49 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Tue, Feb 03, 2026 at 01:55:40PM -0400, Jason Gunthorpe wrote:
I found a corner case, which might be another exception here?
Most of dma_configure callback functions don't use default domain
when driver_managed_dma is set. And this breaks MSI on pcieports.
So, I am thinking of doing this:
bool is_pci_bridge = dev... | {
"author": "Nicolin Chen <nicolinc@nvidia.com>",
"date": "Wed, 18 Feb 2026 14:56:35 -0800",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Wed, Feb 18, 2026 at 02:56:35PM -0800, Nicolin Chen wrote:
I don't think this blocking security work needs to be part of this
series. We just need to disable the mechanism for untrusted devices.
The ARM MSI aperture need is some special case here. Those drivers
don't use DMA at all so of course they don't have th... | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Thu, 19 Feb 2026 10:37:37 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Thu, Feb 19, 2026 at 10:37:37AM -0400, Jason Gunthorpe wrote:
Oh, I thought it should be a prerequisite. I'll separate the patch
then.
I see.
The thing is that those driver_managed_dma callbacks don't call
iommu_device_use_default_domain(). So, the iommu core loses the
trigger to switch domain from BLOCKED/empt... | {
"author": "Nicolin Chen <nicolinc@nvidia.com>",
"date": "Thu, 19 Feb 2026 08:53:19 -0800",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Thu, Feb 19, 2026 at 08:53:19AM -0800, Nicolin Chen wrote:
But they don't use DMA API at all so it doesn't matter to them.
Your issue is that BLOCKED breaks MSI on ARM. That is fixed by using
an empty-DMA API domain as default.
What is missing is to bring back the IDENTITY performance optimization
in a secure way... | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Thu, 19 Feb 2026 13:41:39 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Thu, Feb 19, 2026 at 01:41:39PM -0400, Jason Gunthorpe wrote:
Thanks for the hint!
It actually failed in iommu_dma_prepare_msi() due to having an
IOMMU_COOKIE_NONE in the blocking_domain.
My implementation sets group->domain to group->blocking_domain,
and keeps group->default_domain=NULL to retain the EPROBE_DEFE... | {
"author": "Nicolin Chen <nicolinc@nvidia.com>",
"date": "Thu, 19 Feb 2026 20:52:56 -0800",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Thu, Feb 19, 2026 at 08:52:56PM -0800, Nicolin Chen wrote:
The objective of this security step is to keep ATS blocked and
IDENTITY domains disabled until the userspace has "accepted" the
device by binding a driver to it.
The off the cuff suggestion was to just park the device BLOCKED until
a driver is bound. This ... | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Fri, 20 Feb 2026 08:50:44 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On 2026-02-20 12:50 pm, Jason Gunthorpe wrote:
But is that an issue? Until the device has a driver, surely it shouldn't
be expected to send interrupts at all, much less depend on them being
received and understood by Linux? The MSI cookie is only populated once
a driver actually requests some MSI vectors (since it ... | {
"author": "Robin Murphy <robin.murphy@arm.com>",
"date": "Fri, 20 Feb 2026 13:22:49 +0000",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Fri, Feb 20, 2026 at 01:22:49PM +0000, Robin Murphy wrote:
Oh, the issue is the driver_managed_dma flag.
In this mode we do bind a driver but the iommu callbacks at driver
bind are not called anymore because that flag says the driver itself
will call them later.
Things like PCI port driver that never issue DMA a... | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Fri, 20 Feb 2026 09:51:24 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On 2026-02-20 1:51 pm, Jason Gunthorpe wrote:
Or perhaps we handle BUS_NOTIFY_BIND_DRIVER to manage the switch from
BLOCKED to (empty) DMA independently from whether the driver
subsequently claims the DMA domain or not? That said, I wouldn't have
any particular objection to generalising iommu_use_default_domain() i... | {
"author": "Robin Murphy <robin.murphy@arm.com>",
"date": "Fri, 20 Feb 2026 14:45:49 +0000",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Fri, Feb 20, 2026 at 08:50:44AM -0400, Jason Gunthorpe wrote:
Thanks for elaborating. This seems very orthogonal to the issue
that driver_managed_dma skips iommu_device_use_default_domain().
(And I see you discussion with Robin.)
Regarding the empty-DMA domain, I have an idea of accommodating
ARM cases with an IOM... | {
"author": "Nicolin Chen <nicolinc@nvidia.com>",
"date": "Fri, 20 Feb 2026 10:49:09 -0800",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Fri, Feb 20, 2026 at 10:49:09AM -0800, Nicolin Chen wrote:
Yeah, maybe, but also we probably don't need such stringent checks
since no driver will be bound while this domain is setup, so the basic
DMA domain is fine too.
It should be taken to mean "this device never does DMA when attached
to this driver"
Perha... | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Tue, 24 Feb 2026 10:38:16 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Controlled by the IOMMU driver, ATS is usually enabled "on demand", when a
device requests a translation service from its associated IOMMU HW running
on the channel of a given PASID. This is working even when a device has no
translation on its RID, i.e. RID is IOMMU bypassed.
On the other hand, certain PCIe device req... | null | null | null | [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices | On Fri, Feb 20, 2026 at 02:45:49PM +0000, Robin Murphy wrote:
I'm inclined to say we should disable this VFIO feature if CONFIG_IRQ_MSI_IOMMU
is enabled... Better to hard fail then silently loose interrutps.
If that causes problems for people then we should investigate how to
fix the MSI.
It is really hard, but perh... | {
"author": "Jason Gunthorpe <jgg@nvidia.com>",
"date": "Thu, 26 Feb 2026 11:10:08 -0400",
"is_openbsd": false,
"thread_id": "20260226151008.GD5933@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Hex notation matches the spec documents, and is less error prone.
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Link: https://lore.kernel.org/r/20210825160516.GA3576414@bjorn-Precision-5520/
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
include/uapi/linux/pci_regs.h | 44 +++++++++++++++++------------------
... | null | null | null | [PATCH] PCI: Change PCIe capability registers offset to hex | On Thu, Nov 18, 2021 at 04:13:00PM +0200, Baruch Siach wrote:
Applied to pci/misc for v5.17, thanks!
I also converted some other capabilities that had offsets > 8. | {
"author": "Bjorn Helgaas <helgaas@kernel.org>",
"date": "Wed, 15 Dec 2021 15:36:01 -0600",
"is_openbsd": false,
"thread_id": "b167e3f69b49989dd069b32ddc41bc429abb1dba.camel@infradead.org.mbox.gz"
} |
lkml_critique | linux-pci | Hex notation matches the spec documents, and is less error prone.
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Link: https://lore.kernel.org/r/20210825160516.GA3576414@bjorn-Precision-5520/
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
include/uapi/linux/pci_regs.h | 44 +++++++++++++++++------------------
... | null | null | null | [PATCH] PCI: Change PCIe capability registers offset to hex | ...
What you committed in fb82437fdd8cd also changes
PCI_CAP_EXP_ENDPOINT_SIZEOF_V2:
-#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
+#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x32 /* end of v2 EPs w/ link */
That's not actually the same number. Was that intentional? If so it
should ha... | {
"author": "David Woodhouse <dwmw2@infradead.org>",
"date": "Fri, 27 Feb 2026 09:12:39 +0000",
"is_openbsd": false,
"thread_id": "b167e3f69b49989dd069b32ddc41bc429abb1dba.camel@infradead.org.mbox.gz"
} |
lkml_critique | linux-pci | Hex notation matches the spec documents, and is less error prone.
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Link: https://lore.kernel.org/r/20210825160516.GA3576414@bjorn-Precision-5520/
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
include/uapi/linux/pci_regs.h | 44 +++++++++++++++++------------------
... | null | null | null | [PATCH] PCI: Change PCIe capability registers offset to hex | On Fri, Feb 27, 2026 at 09:12:39AM +0000, David Woodhouse wrote:
Ouch. Unintentional and completely my mistake. Did you trip over
something, or find it by inspection? If there's any kind of defect
signature, I'd like to include it in the commit log.
I posted a fix:
https://lore.kernel.org/linux-pci/20260227123653... | {
"author": "Bjorn Helgaas <helgaas@kernel.org>",
"date": "Fri, 27 Feb 2026 06:42:10 -0600",
"is_openbsd": false,
"thread_id": "b167e3f69b49989dd069b32ddc41bc429abb1dba.camel@infradead.org.mbox.gz"
} |
lkml_critique | linux-pci | Hex notation matches the spec documents, and is less error prone.
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Link: https://lore.kernel.org/r/20210825160516.GA3576414@bjorn-Precision-5520/
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
include/uapi/linux/pci_regs.h | 44 +++++++++++++++++------------------
... | null | null | null | [PATCH] PCI: Change PCIe capability registers offset to hex | On Fri, 2026-02-27 at 06:42 -0600, Bjorn Helgaas wrote:
It ended up breaking PCI capabilities in a VMM because the subsequent
ones weren't DWORD-aligned, but nothing I can easily turn into a test
case / signature. | {
"author": "David Woodhouse <dwmw2@infradead.org>",
"date": "Fri, 27 Feb 2026 13:38:56 +0000",
"is_openbsd": false,
"thread_id": "b167e3f69b49989dd069b32ddc41bc429abb1dba.camel@infradead.org.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | Add necessary clocks and reset entries for the PCIe controller
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v6: No changes
v5: No changes
v4: No changes
v3:
- Collected Rb tag
- Preserved sort order (by _onindex, _onbit);
v2:
... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Thu, 19 Feb 2026 23:35:31 +0100",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | Fix a typo in interrupt-names: "ser_cor" should be "serr_cor" (System
Error Correctable).
Also convert interrupt-names, clock-names, and reset-names properties
from "description" to "const" to enable proper validation with
dtbs_check.
Fixes: e7534e790557 ("dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3E ... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Thu, 19 Feb 2026 23:35:32 +0100",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | Extend the existing device tree bindings for Renesas RZ/G3S PCIe
controller to include support for the RZ/G3E (renesas,r9a09g047e57-pcie) PCIe
controller. The RZ/G3E PCIe controller is similar to RZ/G3S but has some key
differences:
- Uses a different device ID
- Supports PCIe Gen3 (8.0 GT/s) link speeds
- Uses a d... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Thu, 19 Feb 2026 23:35:33 +0100",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | Some SoC variants such as RZ/G3E handle configuration reset control
through PCIe AXI registers instead of dedicated reset lines. Make cfg_resets
optional by using devm_reset_control_bulk_get_optional_exclusive() to allow
SoCs to use alternative or complementary reset control mechanisms.
Reviewed-by: Claudiu Beznea <cl... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Thu, 19 Feb 2026 23:35:35 +0100",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | Add optional cfg_pre_init, cfg_post_init, and cfg_deinit callbacks
to handle SoC-specific configuration methods. While RZ/G3S uses the Linux
reset framework with dedicated reset lines, other SoC variants like RZ/G3E
control configuration resets through PCIe AXI registers.
As Linux reset bulk API gracefully handles opt... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Thu, 19 Feb 2026 23:35:36 +0100",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | Program the class code register explicitly during PCIe configuration
initialization. RZ/G3E requires this register to be set, while RZ/G3S
has these values as hardware defaults.
This configuration is harmless for RZ/G3S where these match the hardware
defaults, and necessary for RZ/G3E to properly identify the device a... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Thu, 19 Feb 2026 23:35:37 +0100",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | Extend the link speed configuration to support Gen3 (8.0 GT/s) in addition
to Gen2 (5.0 GT/s). This is required for RZ/G3E PCIe host support, which is
Gen3 capable.
Instead of relying on DT max-link-speed for configuration, read the hardware
capabilities from the PCI_EXP_LNKCAP register to determine the maximum
suppor... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Thu, 19 Feb 2026 23:35:38 +0100",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | Add support for the PCIe controller found in RZ/G3E SoCs to the existing
RZ/G3S PCIe host driver. The RZ/G3E PCIe controller is similar to the
RZ/G3S's, with the following key differences:
- Supports PCIe Gen3 (8.0 GT/s) link speeds alongside Gen2 (5.0 GT/s)
- Uses a different reset control mechanism via AXI registe... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Thu, 19 Feb 2026 23:35:39 +0100",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | The RZ/G3E SoC family features an x2 PCIe IP. Add the PCIe node.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v6: No changes
v5: No changes
v4: No changes
v3: No changes
v2:
- Roerder interrupts and interrupt names to match binding
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 69 +++++++... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Thu, 19 Feb 2026 23:35:40 +0100",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | The RZ/G3E SMARC SoM has a fixed 100 MHz reference clock generator
for PCIe. Model it as a fixed-clock and assign it to the PCIe port.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v6: No changes
v5: No changes
v4: No changes
v3: No changes
v2: No changes
arch/arm64/boot/dts/renesas/rzg3e... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Thu, 19 Feb 2026 23:35:41 +0100",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | The RZ Smarc Crarrier-II board has PCIe slots mounted on it.
Enable PCIe support.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v6: No changes
v5: No changes
v4: No changes
v3:
- Splitted enablement into common carrier dtsi and board dts
v2:
- Removed board-specific dma-ranges.
- Merge... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Thu, 19 Feb 2026 23:35:42 +0100",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with
the existing RZ/G3S PCIe controller, but with several key differences.
This series adds support for the RZ/G3E PCIe controller by extending the existing
RZ/G3S driver and device tree bindings.
Key differences between RZ/G3E and RZ/G3S PCIe... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Thu, 19 Feb 2026 23:35:26 +0100",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | Fix incorrect reset_control_bulk_deassert() call in the probe error
path. When unwinding from a failed pci_host_probe(), the configuration
resets should be asserted to restore the hardware to its initial state,
not deasserted again.
Fixes: 7ef502fb35b2 ("PCI: Add Renesas RZ/G3S host controller driver")
Reviewed-by: Cl... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Thu, 19 Feb 2026 23:35:27 +0100",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | Reorder the reset assertion sequence during suspend from
power_resets -> cfg_resets to cfg_resets -> power_resets.
This change ensures the suspend sequence follows the reverse order
of the probe/init sequence, where power_resets are deasserted first
followed by cfg_resets.
Additionally, this ordering is required for R... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Thu, 19 Feb 2026 23:35:28 +0100",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | The existing inbound window configuration algorithm has two issues that
prevent proper operation on RZ/G3E:
1. Over-mapping: Using roundup_pow_of_two() on the remaining region size
can result in windows that extend beyond the intended memory region.
2. Alignment violation: Addresses are only aligned to 4K regardle... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Thu, 19 Feb 2026 23:35:29 +0100",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | In preparation for adding RZ/G3E support, move the RST_RSM_B register
offset and mask into a SoC-specific data structure. Compared with RZ/G3S,
the RZ/G3E SYSC controls different functionalities for the PCIe controller.
Make SYSC operations conditional on the presence of register offset
information, allowing the drive... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Thu, 19 Feb 2026 23:35:34 +0100",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | On Thu, Feb 19, 2026 at 11:35:32PM +0100, John Madieu wrote:
You have checkpatch warning for the tag.
Best regards,
Krzysztof | {
"author": "Krzysztof Kozlowski <krzk@kernel.org>",
"date": "Fri, 20 Feb 2026 08:27:45 +0100",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | Hi John Madieu,
Thanks for the patch
If it is RZ/G3E register specific, Maybe better to define this mask at top level??
Cheers,
Biju | {
"author": "Biju Das <biju.das.jz@bp.renesas.com>",
"date": "Fri, 20 Feb 2026 08:49:28 +0000",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | Hi, John,
On 2/20/26 00:35, John Madieu wrote:
Currently, all the registers are prefixed with RZG3S. I know these registers are
RZG3E specific but the upcoming SoCs (RZ/V2H, RZ/T2N, RZ/N2H) that will use this
driver, have these registers implemented as well. So, please keep these defines
prefixed with RZG3S to hav... | {
"author": "Claudiu Beznea <claudiu.beznea@tuxon.dev>",
"date": "Thu, 26 Feb 2026 13:23:59 +0200",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | Hi, John,
On 2/20/26 00:35, John Madieu wrote:
checkpatch warning on this line:
WARNING: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#10:
Instead of relying on DT max-link-speed for configuration, read the hardware
Could you please adjust it?
Thank you,
Claudiu | {
"author": "Claudiu Beznea <claudiu.beznea@tuxon.dev>",
"date": "Thu, 26 Feb 2026 13:24:39 +0200",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | Hi, John,
On 2/20/26 00:35, John Madieu wrote:
There is checkpatch warning on this line as follows:
WARNING: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#7:
through PCIe AXI registers instead of dedicated reset lines. Make cfg_resets
Could you please check?
Thank you,
Claudiu | {
"author": "Claudiu Beznea <claudiu.beznea@tuxon.dev>",
"date": "Thu, 26 Feb 2026 13:24:59 +0200",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | Hi, John,
On 2/20/26 00:35, John Madieu wrote:
Some callbacks are implemented for RZ/G3S as well but they fall back to the
reset framework. Could you please adjust this line?
There is a checkpatch warning on this line as follows:
WARNING: Prefer a maximum 75 chars per line (possible unwrapped commit description?)... | {
"author": "Claudiu Beznea <claudiu.beznea@tuxon.dev>",
"date": "Thu, 26 Feb 2026 13:25:48 +0200",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | Hi, John,
On 2/20/26 00:35, John Madieu wrote:
Please drop register word from here ---------------------^
There are 2 blank lines here. Please drop one.
Please drop function from here ---------------------------^
as we may add other data in it at some point.
s/functionalities/info
Other similar functions in t... | {
"author": "Claudiu Beznea <claudiu.beznea@tuxon.dev>",
"date": "Thu, 26 Feb 2026 13:27:10 +0200",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | On 2/20/26 00:35, John Madieu wrote:
Please drop this part as the order may impact the functionality. But with this
fix we now follow the config order from probe, so we should be good now.
With the above addressed:
Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | {
"author": "Claudiu Beznea <claudiu.beznea@tuxon.dev>",
"date": "Thu, 26 Feb 2026 13:30:18 +0200",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | Hi Claudiu,
Thanks for your review.
I'll switch to RZG3S_ prefix and remove the comments in v7.
Noted.
Will go with what you suggest.
Will do.
Noted.
Noted.
Noted.
That's true. Will fix it in v7.
Noted.
Will do.
Regards,
John | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Fri, 27 Feb 2026 11:08:05 +0000",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | Hi Claudiu,
Thanks for the review.
Will address all of the typos you enumerated.
Noted.
Regards,
John | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Fri, 27 Feb 2026 11:15:33 +0000",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | Some peripherals may be left enabled by the bootloader but should be
explicitly disabled by the kernel to ensure a known initial state.
This is particularly important for PCIe which requires proper
initialization sequencing.
Add new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare
module clocks that sh... | null | null | null | [PATCH v6 04/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets | Hi Biju,
Most drivers are using the same approach, defining the class
instead of using hardcoded value, especially since the register
is from specification.
See RCar [1] and Mediatek [2] examples.
[1]: https://elixir.bootlin.com/linux/v6.19.3/source/drivers/pci/controller/pcie-rcar-host.c#L448
[2]: https://elixir.b... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Fri, 27 Feb 2026 14:32:31 +0000",
"is_openbsd": false,
"thread_id": "TY6PR01MB17377BD6AB0D8D3E60E605275FF73A@TY6PR01MB17377.jpnprd01.prod.outlook.com.mbox.gz"
} |
lkml_critique | linux-pci | From: Ionut Nechita <ionut.nechita@windriver.com>
After reverting commit 05703271c3cd ("PCI/IOV: Add PCI rescan-remove
locking when enabling/disabling SR-IOV") and moving the lock to
sriov_numvfs_store(), the path through driver .remove() (e.g. rmmod,
or manual unbind) that calls pci_disable_sriov() directly remains
u... | null | null | null | [PATCH v3 1/1] PCI/IOV: Add reentrant locking in sriov_add_vfs/sriov_del_vfs for complete serialization | From: Ionut Nechita <ionut_n2001@yahoo.com>
From: Ionut Nechita <ionut.nechita@windriver.com>
Hi,
This is v3 of the patch adding owner-tracked reentrant locking for
pci_rescan_remove_lock in sriov_add_vfs() and sriov_del_vfs(), to
serialize VF addition/removal against concurrent hotplug events
(including platform-ge... | {
"author": "ionut.nechita@windriver.com",
"date": "Wed, 25 Feb 2026 22:24:33 +0200",
"is_openbsd": false,
"thread_id": "20260226134052.GA13050@p1gen4-pw042f0m.mbox.gz"
} |
lkml_critique | linux-pci | From: Ionut Nechita <ionut.nechita@windriver.com>
After reverting commit 05703271c3cd ("PCI/IOV: Add PCI rescan-remove
locking when enabling/disabling SR-IOV") and moving the lock to
sriov_numvfs_store(), the path through driver .remove() (e.g. rmmod,
or manual unbind) that calls pci_disable_sriov() directly remains
u... | null | null | null | [PATCH v3 1/1] PCI/IOV: Add reentrant locking in sriov_add_vfs/sriov_del_vfs for complete serialization | Hey Ionut,
On Wed, Feb 25, 2026 at 10:24:33PM +0200, ionut.nechita@windriver.com wrote:
I am reviewing/testing the patch, but I have not given you my Reviewed-by yet.
--
Best Regards, Benjamin Block / Linux on IBM Z Kernel Development
IBM Deutschland Research & Development GmbH / https://www.ibm.... | {
"author": "Benjamin Block <bblock@linux.ibm.com>",
"date": "Thu, 26 Feb 2026 10:36:57 +0100",
"is_openbsd": false,
"thread_id": "20260226134052.GA13050@p1gen4-pw042f0m.mbox.gz"
} |
lkml_critique | linux-pci | From: Ionut Nechita <ionut.nechita@windriver.com>
After reverting commit 05703271c3cd ("PCI/IOV: Add PCI rescan-remove
locking when enabling/disabling SR-IOV") and moving the lock to
sriov_numvfs_store(), the path through driver .remove() (e.g. rmmod,
or manual unbind) that calls pci_disable_sriov() directly remains
u... | null | null | null | [PATCH v3 1/1] PCI/IOV: Add reentrant locking in sriov_add_vfs/sriov_del_vfs for complete serialization | On Wed, Feb 25, 2026 at 10:24:34PM +0200, ionut.nechita@windriver.com wrote:
--8<--
--8<--
^
const *pci_rescan_remove_owner
Minor nitpick: you could declare this `const`; making it clear that this is
not meant to be used to modify the task in any way.
Otherwise... | {
"author": "Benjamin Block <bblock@linux.ibm.com>",
"date": "Thu, 26 Feb 2026 14:40:52 +0100",
"is_openbsd": false,
"thread_id": "20260226134052.GA13050@p1gen4-pw042f0m.mbox.gz"
} |
lkml_critique | linux-pci | Rockchip DWC PCIe driver currently performs synchronous link training for
combo PHYs (PCIe 3.0/2.0 and SATA 3.0) during boot. This process waits for
the link to be fully established, adding several milliseconds to the boot
sequence. To optimize boot time, this change enables asynchronous probing,
allowing link establis... | null | null | null | [PATCH v3] PCI: dw-rockchip: Enable async probe by default | On Thu, Feb 26, 2026 at 03:40:23PM +0530, Anand Moon wrote:
Reviewed-by: Niklas Cassel <cassel@kernel.org> | {
"author": "Niklas Cassel <cassel@kernel.org>",
"date": "Thu, 26 Feb 2026 13:06:58 +0100",
"is_openbsd": false,
"thread_id": "aaA3YuIOK_Q0MPi-@ryzen.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes and the other is for enhancements(current).
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
Disabling L1SS capability based on support-cl... | null | null | null | [PATCH v6 0/9] Enhancements to pcie-tegra194 driver | From: Vidya Sagar <vidyas@nvidia.com>
Currently, the default setting is that CLKREQ signal of a Root Port
is internally overridden to '0' to enable REFCLK to flow out to the slot.
It is observed that one of the PCIe switches (case in point Broadcom PCIe
Gen4 switch) is propagating the CLKREQ signal of the root port to... | {
"author": "Manikanta Maddireddy <mmaddireddy@nvidia.com>",
"date": "Tue, 24 Feb 2026 00:15:30 +0530",
"is_openbsd": false,
"thread_id": "c8ac9a7e-5f37-4e5f-a33a-f1c3e94b4d19@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes and the other is for enhancements(current).
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
Disabling L1SS capability based on support-cl... | null | null | null | [PATCH v6 0/9] Enhancements to pcie-tegra194 driver | From: Vidya Sagar <vidyas@nvidia.com>
The Tegra PCIe Endpoint controller has a single interrupt line that is
shared between multiple interrupt sources:
1. PCIe link state events (link up, hot reset done)
2. Configuration space events (Bus Master Enable changes)
3. DMA completion events
Currently, the interrupt is reg... | {
"author": "Manikanta Maddireddy <mmaddireddy@nvidia.com>",
"date": "Tue, 24 Feb 2026 00:15:32 +0530",
"is_openbsd": false,
"thread_id": "c8ac9a7e-5f37-4e5f-a33a-f1c3e94b4d19@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes and the other is for enhancements(current).
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
Disabling L1SS capability based on support-cl... | null | null | null | [PATCH v6 0/9] Enhancements to pcie-tegra194 driver | From: Vidya Sagar <vidyas@nvidia.com>
Calibrate P2U for endpoint controller to request UPHY PLL rate change to
Gen1 during initialization. This helps to reset stale PLL state from the
previous bad link state.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
-... | {
"author": "Manikanta Maddireddy <mmaddireddy@nvidia.com>",
"date": "Tue, 24 Feb 2026 00:15:31 +0530",
"is_openbsd": false,
"thread_id": "c8ac9a7e-5f37-4e5f-a33a-f1c3e94b4d19@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes and the other is for enhancements(current).
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
Disabling L1SS capability based on support-cl... | null | null | null | [PATCH v6 0/9] Enhancements to pcie-tegra194 driver | From: Vidya Sagar <vidyas@nvidia.com>
Enable DMA interrupt to support Tegra PCIe DMA in both Root port and
Endpoint modes.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V1 -> V6: None
drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++++++++++... | {
"author": "Manikanta Maddireddy <mmaddireddy@nvidia.com>",
"date": "Tue, 24 Feb 2026 00:15:33 +0530",
"is_openbsd": false,
"thread_id": "c8ac9a7e-5f37-4e5f-a33a-f1c3e94b4d19@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes and the other is for enhancements(current).
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
Disabling L1SS capability based on support-cl... | null | null | null | [PATCH v6 0/9] Enhancements to pcie-tegra194 driver | From: Vidya Sagar <vidyas@nvidia.com>
When PCIe link goes down, hardware can retrain the link and try to link up.
To enable this feature, program the APPL_CTRL register with hardware hot
reset with immediate LTSSM enable mode.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddir... | {
"author": "Manikanta Maddireddy <mmaddireddy@nvidia.com>",
"date": "Tue, 24 Feb 2026 00:15:34 +0530",
"is_openbsd": false,
"thread_id": "c8ac9a7e-5f37-4e5f-a33a-f1c3e94b4d19@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes and the other is for enhancements(current).
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
Disabling L1SS capability based on support-cl... | null | null | null | [PATCH v6 0/9] Enhancements to pcie-tegra194 driver | From: Vidya Sagar <vidyas@nvidia.com>
Tegra supports PCIe core clock monitoring for any rate changes that may be
happening because of the link speed changes. This is useful in tracking
any changes in the core clock that are not initiated by the software.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: M... | {
"author": "Manikanta Maddireddy <mmaddireddy@nvidia.com>",
"date": "Tue, 24 Feb 2026 00:15:36 +0530",
"is_openbsd": false,
"thread_id": "c8ac9a7e-5f37-4e5f-a33a-f1c3e94b4d19@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes and the other is for enhancements(current).
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
Disabling L1SS capability based on support-cl... | null | null | null | [PATCH v6 0/9] Enhancements to pcie-tegra194 driver | From: Vidya Sagar <vidyas@nvidia.com>
When Tegra234 is operating in the endpoint mode with L1.2 enabled, PCIe
link goes down during L1.2 exit. This is because Tegra234 is powering up
UPHY PLL immediately without making sure that the REFCLK is stable.
This is causing UPHY PLL to not lock to the correct frequency and le... | {
"author": "Manikanta Maddireddy <mmaddireddy@nvidia.com>",
"date": "Tue, 24 Feb 2026 00:15:35 +0530",
"is_openbsd": false,
"thread_id": "c8ac9a7e-5f37-4e5f-a33a-f1c3e94b4d19@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes and the other is for enhancements(current).
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
Disabling L1SS capability based on support-cl... | null | null | null | [PATCH v6 0/9] Enhancements to pcie-tegra194 driver | From: Vidya Sagar <vidyas@nvidia.com>
Tegra supports PCIe core clock monitoring for any rate changes that may be
happening because of the link speed changes. This is useful in tracking
any changes in the core clock that are not initiated by the software. This
patch adds support to parse the monitor clock info from dev... | {
"author": "Manikanta Maddireddy <mmaddireddy@nvidia.com>",
"date": "Tue, 24 Feb 2026 00:15:37 +0530",
"is_openbsd": false,
"thread_id": "c8ac9a7e-5f37-4e5f-a33a-f1c3e94b4d19@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes and the other is for enhancements(current).
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
Disabling L1SS capability based on support-cl... | null | null | null | [PATCH v6 0/9] Enhancements to pcie-tegra194 driver | For Tegra234, the HW PHY team conducted experiments and determined the
optimal ASPM L1 entrance latency values: 8 us for Root Port mode and
16 us for Endpoint mode. Update the default ASPM L1 entrance latency
configuration accordingly.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V1 -> V6: ... | {
"author": "Manikanta Maddireddy <mmaddireddy@nvidia.com>",
"date": "Tue, 24 Feb 2026 00:15:38 +0530",
"is_openbsd": false,
"thread_id": "c8ac9a7e-5f37-4e5f-a33a-f1c3e94b4d19@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes and the other is for enhancements(current).
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
Disabling L1SS capability based on support-cl... | null | null | null | [PATCH v6 0/9] Enhancements to pcie-tegra194 driver | On 23/02/2026 18:45, Manikanta Maddireddy wrote:
For the series ...
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Thanks
Jon
--
nvpublic | {
"author": "Jon Hunter <jonathanh@nvidia.com>",
"date": "Fri, 27 Feb 2026 16:59:15 +0000",
"is_openbsd": false,
"thread_id": "c8ac9a7e-5f37-4e5f-a33a-f1c3e94b4d19@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | Currently, the steering tag can be used for a CPU on the motherboard; the
ACPI check is in place to query and obtain the supported tph settings. Here
we intend to use the tph info to improve RDMA NIC memory access on a vfio-based
accelerator device via PCIe peer-to-peer. When an applicantion register a
RDMA memory regi... | null | null | null | [RFC 0/2] Retrieve tph from dmabuf for PCIe P2P memory access | On Mon, Feb 09, 2026 at 09:53:10AM -0800, Zhiping Zhang wrote:
you didn't cc the DRM people who really need to look at any changes to
the dmabuf contract.
Jason | {
"author": "Jason Gunthorpe <jgg@ziepe.ca>",
"date": "Mon, 9 Feb 2026 14:13:03 -0400",
"is_openbsd": false,
"thread_id": "20260210194014.2147481-1-zhipingz@meta.com.mbox.gz"
} |
lkml_critique | linux-pci | Currently, the steering tag can be used for a CPU on the motherboard; the
ACPI check is in place to query and obtain the supported tph settings. Here
we intend to use the tph info to improve RDMA NIC memory access on a vfio-based
accelerator device via PCIe peer-to-peer. When an applicantion register a
RDMA memory regi... | null | null | null | [RFC 0/2] Retrieve tph from dmabuf for PCIe P2P memory access | On Mon, Feb 08, 2026 at 10:13:00AM -0800, Jason Gunthor write:
Thanks, let me submit again including the DRM people via the mailing list
dri-devel@lists.freedesktop.org.
Zhiping | {
"author": "Zhiping Zhang <zhipingz@meta.com>",
"date": "Mon, 9 Feb 2026 15:28:24 -0800",
"is_openbsd": false,
"thread_id": "20260210194014.2147481-1-zhipingz@meta.com.mbox.gz"
} |
lkml_critique | linux-pci | Currently, the steering tag can be used for a CPU on the motherboard; the
ACPI check is in place to query and obtain the supported tph settings. Here
we intend to use the tph info to improve RDMA NIC memory access on a vfio-based
accelerator device via PCIe peer-to-peer. When an applicantion register a
RDMA memory regi... | null | null | null | [RFC 0/2] Retrieve tph from dmabuf for PCIe P2P memory access | Currently, the steering tag can be used for a CPU on the motherboard; the
ACPI check is in place to query and obtain the supported tph settings. Here
we intend to use the tph info to improve RDMA NIC memory access on a vfio-based
accelerator device via PCIe peer-to-peer. When an applicantion register a
RDMA memory regi... | {
"author": "Zhiping Zhang <zhipingz@meta.com>",
"date": "Tue, 10 Feb 2026 11:39:53 -0800",
"is_openbsd": false,
"thread_id": "20260210194014.2147481-1-zhipingz@meta.com.mbox.gz"
} |
lkml_critique | linux-pci | Currently, the steering tag can be used for a CPU on the motherboard; the
ACPI check is in place to query and obtain the supported tph settings. Here
we intend to use the tph info to improve RDMA NIC memory access on a vfio-based
accelerator device via PCIe peer-to-peer. When an applicantion register a
RDMA memory regi... | null | null | null | [RFC 0/2] Retrieve tph from dmabuf for PCIe P2P memory access | The patch adds a local function to check and get tph info when available during
dmabuf mr registration. Note the DMAH workflow for CPU still takes precedence in
the process. Currently, it only works with the direct st_mode. Compatibility
with other st_modes will be added in the formal patch set.
Signed-off-by: Zhiping... | {
"author": "Zhiping Zhang <zhipingz@meta.com>",
"date": "Tue, 10 Feb 2026 11:39:55 -0800",
"is_openbsd": false,
"thread_id": "20260210194014.2147481-1-zhipingz@meta.com.mbox.gz"
} |
lkml_critique | linux-pci | Currently, the steering tag can be used for a CPU on the motherboard; the
ACPI check is in place to query and obtain the supported tph settings. Here
we intend to use the tph info to improve RDMA NIC memory access on a vfio-based
accelerator device via PCIe peer-to-peer. When an applicantion register a
RDMA memory regi... | null | null | null | [RFC 0/2] Retrieve tph from dmabuf for PCIe P2P memory access | This RFC patch adds a callback to get the tph info on DMA buffer exporters.
The tph info includes both the steering tag and the process hint (ph).
Signed-off-by: Zhiping Zhang <zhipingz@meta.com>
---
drivers/vfio/pci/vfio_pci_dmabuf.c | 15 ++++++++++++++-
include/linux/dma-buf.h | 30 +++++++++++++++++++++... | {
"author": "Zhiping Zhang <zhipingz@meta.com>",
"date": "Tue, 10 Feb 2026 11:39:54 -0800",
"is_openbsd": false,
"thread_id": "20260210194014.2147481-1-zhipingz@meta.com.mbox.gz"
} |
lkml_critique | linux-pci | Currently, the steering tag can be used for a CPU on the motherboard; the
ACPI check is in place to query and obtain the supported tph settings. Here
we intend to use the tph info to improve RDMA NIC memory access on a vfio-based
accelerator device via PCIe peer-to-peer. When an applicantion register a
RDMA memory regi... | null | null | null | [RFC 0/2] Retrieve tph from dmabuf for PCIe P2P memory access | The subject prefix should be lower case "vfio" to match the subsystem
commit style.
On Tue, Feb 10, 2026 at 11:39:54AM -0800, Zhiping Zhang wrote:
I don't think you can add fields to a uapi struct like this since it
breaks comptibility. Instead, I think you may be able to carve it out of
the "flags" field since it's ... | {
"author": "Keith Busch <kbusch@kernel.org>",
"date": "Thu, 26 Feb 2026 17:56:07 -0700",
"is_openbsd": false,
"thread_id": "20260210194014.2147481-1-zhipingz@meta.com.mbox.gz"
} |
lkml_critique | linux-pci | Currently, the steering tag can be used for a CPU on the motherboard; the
ACPI check is in place to query and obtain the supported tph settings. Here
we intend to use the tph info to improve RDMA NIC memory access on a vfio-based
accelerator device via PCIe peer-to-peer. When an applicantion register a
RDMA memory regi... | null | null | null | [RFC 0/2] Retrieve tph from dmabuf for PCIe P2P memory access | On Tue, Feb 10, 2026 at 11:39:55AM -0800, Zhiping Zhang wrote:
You defined the "get_tph" function to take a pointer to a raw steering
tag value, but you're passing in the steering index to it's table.
But in general, since you're letting the user put whatever they want in
the vfio private area, should there be some v... | {
"author": "Keith Busch <kbusch@kernel.org>",
"date": "Thu, 26 Feb 2026 18:21:28 -0700",
"is_openbsd": false,
"thread_id": "20260210194014.2147481-1-zhipingz@meta.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes(current) and the other is for enhancements.
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
I added below four new patches to fix bugs, c... | null | null | null | [PATCH v6 00/13] Fixes to pcie-tegra194 driver | From: Vidya Sagar <vidyas@nvidia.com>
As per PCIe spec r6.0, sec 5.3.3.2.1, after sending PME_Turn_Off message,
Root port should wait for 1~10 msec for PME_TO_Ack message. Currently,
driver is polling for 10 msec with 1 usec delay which is aggressive.
Change it to 10 msec polling with 100 usec delay. Since this functi... | {
"author": "Manikanta Maddireddy <mmaddireddy@nvidia.com>",
"date": "Tue, 24 Feb 2026 00:11:39 +0530",
"is_openbsd": false,
"thread_id": "dabbc4cd-3a2c-44fd-be93-595ff827f005@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes(current) and the other is for enhancements.
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
I added below four new patches to fix bugs, c... | null | null | null | [PATCH v6 00/13] Fixes to pcie-tegra194 driver | From: Vidya Sagar <vidyas@nvidia.com>
On surprise down, LTSSM state transits from L0 -> Recovery.RcvrLock ->
Recovery.RcvrSpeed -> Gen1 Recovery.RcvrLock -> Detect. Recovery.RcvrLock
and Recovery.RcvrSpeed transit times are 24 msec and 48 msec respectively.
So, the total time taken to transit from L0 to detect state i... | {
"author": "Manikanta Maddireddy <mmaddireddy@nvidia.com>",
"date": "Tue, 24 Feb 2026 00:11:40 +0530",
"is_openbsd": false,
"thread_id": "dabbc4cd-3a2c-44fd-be93-595ff827f005@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes(current) and the other is for enhancements.
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
I added below four new patches to fix bugs, c... | null | null | null | [PATCH v6 00/13] Fixes to pcie-tegra194 driver | From: Vidya Sagar <vidyas@nvidia.com>
As per PCIe CEM spec rev 4.0 ver 1.0 sec 2.3, the PCIe endpoint device
should be in D3 state to assert wake# pin. This takes precedence over PCI
Express Base r4.0 v1.0 September 27-2017, 5.2 Link State Power Management
which states that the device can be put into D0 state before t... | {
"author": "Manikanta Maddireddy <mmaddireddy@nvidia.com>",
"date": "Tue, 24 Feb 2026 00:11:41 +0530",
"is_openbsd": false,
"thread_id": "dabbc4cd-3a2c-44fd-be93-595ff827f005@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes(current) and the other is for enhancements.
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
I added below four new patches to fix bugs, c... | null | null | null | [PATCH v6 00/13] Fixes to pcie-tegra194 driver | The PERST (PERST#) GPIO interrupt is only registered when the controller
is operating in Endpoint mode. In Root Port mode, the PERST GPIO is
configured as an output to control downstream devices, and no interrupt
is registered for it.
Currently, tegra_pcie_dw_stop_link() unconditionally calls disable_irq()
on pex_rst_... | {
"author": "Manikanta Maddireddy <mmaddireddy@nvidia.com>",
"date": "Tue, 24 Feb 2026 00:11:42 +0530",
"is_openbsd": false,
"thread_id": "dabbc4cd-3a2c-44fd-be93-595ff827f005@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes(current) and the other is for enhancements.
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
I added below four new patches to fix bugs, c... | null | null | null | [PATCH v6 00/13] Fixes to pcie-tegra194 driver | From: Vidya Sagar <vidyas@nvidia.com>
The GPIO DT property "nvidia,refclk-select" to select the PCIe reference
clock is optional. Use devm_gpiod_get_optional() to get it.
Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Ma... | {
"author": "Manikanta Maddireddy <mmaddireddy@nvidia.com>",
"date": "Tue, 24 Feb 2026 00:11:43 +0530",
"is_openbsd": false,
"thread_id": "dabbc4cd-3a2c-44fd-be93-595ff827f005@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes(current) and the other is for enhancements.
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
I added below four new patches to fix bugs, c... | null | null | null | [PATCH v6 00/13] Fixes to pcie-tegra194 driver | From: Vidya Sagar <vidyas@nvidia.com>
Disable direct speed change for the endpoint to prevent it from initiating
the speed change post physical layer link up at gen1. This leaves the speed
change ownership with the host.
Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
Signed-off-by:... | {
"author": "Manikanta Maddireddy <mmaddireddy@nvidia.com>",
"date": "Tue, 24 Feb 2026 00:11:44 +0530",
"is_openbsd": false,
"thread_id": "dabbc4cd-3a2c-44fd-be93-595ff827f005@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes(current) and the other is for enhancements.
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
I added below four new patches to fix bugs, c... | null | null | null | [PATCH v6 00/13] Fixes to pcie-tegra194 driver | From: Vidya Sagar <vidyas@nvidia.com>
LTR message should be sent as soon as the root port enables LTR in the
endpoint. Set snoop & no snoop LTR timing and LTR message request before
PCIe links up. This ensures that LTR message is sent upstream as soon as
LTR is enabled.
Fixes: c57247f940e8 ("PCI: tegra: Add support f... | {
"author": "Manikanta Maddireddy <mmaddireddy@nvidia.com>",
"date": "Tue, 24 Feb 2026 00:11:45 +0530",
"is_openbsd": false,
"thread_id": "dabbc4cd-3a2c-44fd-be93-595ff827f005@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes(current) and the other is for enhancements.
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
I added below four new patches to fix bugs, c... | null | null | null | [PATCH v6 00/13] Fixes to pcie-tegra194 driver | From: Vidya Sagar <vidyas@nvidia.com>
PERST# and CLKREQ# pinctrl settings should be applied for both root port
and endpoint mode. Move pinctrl_pm_select_default_state() function call
from root port specific configuration function to probe().
Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegr... | {
"author": "Manikanta Maddireddy <mmaddireddy@nvidia.com>",
"date": "Tue, 24 Feb 2026 00:11:46 +0530",
"is_openbsd": false,
"thread_id": "dabbc4cd-3a2c-44fd-be93-595ff827f005@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes(current) and the other is for enhancements.
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
I added below four new patches to fix bugs, c... | null | null | null | [PATCH v6 00/13] Fixes to pcie-tegra194 driver | From: Vidya Sagar <vidyas@nvidia.com>
Only a Root port initiates the L2 sequence. PCIe link is kept in L2 state
during suspend. If Endpoint mode is enabled and the link is up, the
software cannot proceed with suspend. However, when the PCIe Endpoint
driver is probed, but the PCIe link is not up, Tegra can go into susp... | {
"author": "Manikanta Maddireddy <mmaddireddy@nvidia.com>",
"date": "Tue, 24 Feb 2026 00:11:47 +0530",
"is_openbsd": false,
"thread_id": "dabbc4cd-3a2c-44fd-be93-595ff827f005@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes(current) and the other is for enhancements.
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
I added below four new patches to fix bugs, c... | null | null | null | [PATCH v6 00/13] Fixes to pcie-tegra194 driver | From: Vidya Sagar <vidyas@nvidia.com>
Free up the resources during remove() that were acquired by the DesignWare
driver for the endpoint mode during probe().
Fixes: bb617cbd8151 ("PCI: tegra194: Clean up the exit path for Endpoint mode")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddired... | {
"author": "Manikanta Maddireddy <mmaddireddy@nvidia.com>",
"date": "Tue, 24 Feb 2026 00:11:48 +0530",
"is_openbsd": false,
"thread_id": "dabbc4cd-3a2c-44fd-be93-595ff827f005@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes(current) and the other is for enhancements.
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
I added below four new patches to fix bugs, c... | null | null | null | [PATCH v6 00/13] Fixes to pcie-tegra194 driver | Tegra194 PCIe driver uses custom version number to detect Tegra194 and
Tegra234 IPs. With version detect logic added, version check results
in mismatch warnings.
Use HW version numbers in Tegra194 driver to avoid this kernel warnings.
Fixed version check to enable ecrc for Tegra194.
Existing 490A check is left intact... | {
"author": "Manikanta Maddireddy <mmaddireddy@nvidia.com>",
"date": "Tue, 24 Feb 2026 00:11:49 +0530",
"is_openbsd": false,
"thread_id": "dabbc4cd-3a2c-44fd-be93-595ff827f005@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes(current) and the other is for enhancements.
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
I added below four new patches to fix bugs, c... | null | null | null | [PATCH v6 00/13] Fixes to pcie-tegra194 driver | When PERST# is deasserted twice (assert -> deassert -> assert -> deassert),
a CBB (Control Backbone) timeout occurs at DBI register offset 0x8bc
(PCIE_MISC_CONTROL_1_OFF). This happens because pci_epc_deinit_notify()
and dw_pcie_ep_cleanup() are called before reset_control_deassert() powers
on the controller core.
The... | {
"author": "Manikanta Maddireddy <mmaddireddy@nvidia.com>",
"date": "Tue, 24 Feb 2026 00:11:50 +0530",
"is_openbsd": false,
"thread_id": "dabbc4cd-3a2c-44fd-be93-595ff827f005@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes(current) and the other is for enhancements.
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
I added below four new patches to fix bugs, c... | null | null | null | [PATCH v6 00/13] Fixes to pcie-tegra194 driver | From: Vidya Sagar <vidyas@nvidia.com>
Call pci_epc_deinit_notify() during controller deinitialization to free the
resources allocated by Endpoint function driver. This is safe to call
during PCIe assert sequence because we don't expect Endpoint function
driver to touch hardware in deinit function.
Fixes: 40e2125381dc... | {
"author": "Manikanta Maddireddy <mmaddireddy@nvidia.com>",
"date": "Tue, 24 Feb 2026 00:11:51 +0530",
"is_openbsd": false,
"thread_id": "dabbc4cd-3a2c-44fd-be93-595ff827f005@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes(current) and the other is for enhancements.
I verified these patches on Jetson AGX Orin(Tegra234 SoC).
I added below four new patches to fix bugs, c... | null | null | null | [PATCH v6 00/13] Fixes to pcie-tegra194 driver | On 23/02/2026 18:41, Manikanta Maddireddy wrote:
For the series ...
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Thanks
Jon
--
nvpublic | {
"author": "Jon Hunter <jonathanh@nvidia.com>",
"date": "Fri, 27 Feb 2026 16:59:04 +0000",
"is_openbsd": false,
"thread_id": "dabbc4cd-3a2c-44fd-be93-595ff827f005@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | In pci-epf-vntb, db_count represents the total number of doorbell slots
exposed to the peer, including:
- slot #0 reserved for link events, and
- slot #1 historically unused (kept for compatibility).
Only the remaining slots correspond to actual doorbell bits. The current
db_valid_mask() exposes all slots as valid... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Tue, 24 Feb 2026 22:34:53 +0900",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | Implement .db_vector_count and .db_vector_mask so ntb core/clients can map
doorbell events to per-vector work and avoid the thundering-herd behavior.
pci-epf-vntb reserves two slots in db_count: slot 0 for link events and
slot 1 which is historically unused. Therefore the number of doorbell
vectors is (db_count - 2).
... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Tue, 24 Feb 2026 22:34:54 +0900",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | The NTB .peer_db_set() callback may be invoked from atomic context.
pci-epf-vntb currently calls pci_epc_raise_irq() directly, but
pci_epc_raise_irq() may sleep (it takes epc->lock).
Avoid sleeping in atomic context by coalescing doorbell bits into an
atomic64 pending mask and raising MSIs from a work item. Limit the
... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Tue, 24 Feb 2026 22:34:51 +0900",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | ntb_epf_peer_db_set() uses ffs(db_bits) to select a doorbell to ring.
ffs() returns a 1-based bit index (bit 0 -> 1).
Entry 0 is reserved for link events, so doorbell bit 0 must map to entry
1. However, since the initial commit 812ce2f8d14e ("NTB: Add support for
EPF PCI Non-Transparent Bridge"), the implementation ha... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Tue, 24 Feb 2026 22:34:55 +0900",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | This series fixes doorbell bit/vector handling for the EPF-based NTB
pair (ntb_hw_epf <-> pci-epf-*ntb). Its primary goal is to enable safe
per-db-vector handling in the NTB core and clients (e.g. ntb_transport),
without changing the on-the-wire doorbell mapping.
Background / problem
====================
ntb_hw_epf ... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Tue, 24 Feb 2026 22:34:49 +0900",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | ndev->db_count includes an unused doorbell slot due to the legacy extra
offset in the peer doorbell path. db_valid_mask must cover only the real
doorbell bits and exclude the unused slot.
Set db_valid_mask to BIT_ULL(db_count - 1) - 1.
Fixes: 812ce2f8d14e ("NTB: Add support for EPF PCI Non-Transparent Bridge")
Signed... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Tue, 24 Feb 2026 22:34:56 +0900",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | ntb_db_event() expects the vector number to be relative to the first
doorbell vector starting at 0.
pci-epf-vntb reserves vector 0 for link events and uses higher vector
indices for doorbells. By passing the raw slot index to ntb_db_event(),
it effectively assumes that doorbell 0 maps to vector 1.
However, because th... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Tue, 24 Feb 2026 22:34:52 +0900",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | ntb_db_event() expects the vector number to be relative to the first
doorbell vector starting at 0.
Vector 0 is reserved for link events in the EPF driver, so doorbells
start at vector 1. However, both supported peers (ntb_hw_epf with
pci-epf-ntb, and pci-epf-vntb) have historically skipped vector 1 and
started doorbe... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Tue, 24 Feb 2026 22:34:57 +0900",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | The EPF driver currently stores the incoming doorbell as a vector number
(irq_no + 1) in db_val and db_clear() clears all bits unconditionally.
This breaks db_read()/db_clear() semantics when multiple doorbells are
used.
Store doorbells as a bitmask (BIT_ULL(vector)) and make
db_clear(db_bits) clear only the specified... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Tue, 24 Feb 2026 22:34:58 +0900",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | Implement .db_vector_count and .db_vector_mask so ntb core/clients can
map doorbell events to per-vector work.
Report vectors as 0..(db_count - 2) (skipping the unused slot) and
return BIT_ULL(db_vector) for the corresponding doorbell bit.
Signed-off-by: Koichiro Den <den@valinux.co.jp>
---
drivers/ntb/hw/epf/ntb_hw... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Tue, 24 Feb 2026 22:34:59 +0900",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | On 2/24/26 6:34 AM, Koichiro Den wrote:
I would suggest adding a comment in the code for why this is for future readers.
DJ | {
"author": "Dave Jiang <dave.jiang@intel.com>",
"date": "Wed, 25 Feb 2026 09:47:43 -0700",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | On 2/24/26 6:34 AM, Koichiro Den wrote:
Given that 0 and 1 have specific meanings, maybe create a enum with appropriate naming to make it more clear. Maybe something like this or however you want to name them:
enum EPF_IRQ_SLOT {
EPF_IRQ_LINK = 0,
EPF_IRQ_RESERVED_DB,
EPF_IRQ_DB_START,
};
And then here you can do... | {
"author": "Dave Jiang <dave.jiang@intel.com>",
"date": "Wed, 25 Feb 2026 09:59:46 -0700",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | On 2/24/26 6:34 AM, Koichiro Den wrote:
Again here the bits probably can use a define or enum instead of magic numbers.
DJ | {
"author": "Dave Jiang <dave.jiang@intel.com>",
"date": "Wed, 25 Feb 2026 10:04:42 -0700",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | On Tue, Feb 24, 2026 at 10:34:50PM +0900, Koichiro Den wrote:
Thanks,
Reviewed-by: Frank Li <Frank.Li@nxp.com> | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Wed, 25 Feb 2026 15:34:03 -0500",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | On Tue, Feb 24, 2026 at 10:34:51PM +0900, Koichiro Den wrote:
Can we use thread irq handle()?
Frank | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Wed, 25 Feb 2026 15:36:05 -0500",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | On Tue, Feb 24, 2026 at 10:34:52PM +0900, Koichiro Den wrote:
Reviewed-by: Frank Li <Frank.Li@nxp.com> | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Wed, 25 Feb 2026 15:54:16 -0500",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | On Tue, Feb 24, 2026 at 10:34:53PM +0900, Koichiro Den wrote:
Reviewed-by: Frank Li <Frank.Li@nxp.com> | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Wed, 25 Feb 2026 15:55:39 -0500",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | On Tue, Feb 24, 2026 at 10:34:54PM +0900, Koichiro Den wrote:
return max(ndev->db_count - 2, 0);
Frank | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Wed, 25 Feb 2026 16:02:01 -0500",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.