text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
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< GPIO15, input and output */
GPIO_NUM_16 = 16, /*!< GPIO16, input and output */
GPIO_NUM_17 = 17, /*!< GPIO17, input and output */
GPIO_NUM_18 = 18, /*!< GPIO18, input and output */
GPIO_NUM_19 = 19, /*!< GPIO19, input and output */
GPIO_NUM_20 = 20, /*!< GPIO20, input and output */
G... | 1,399 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef struct gpio_sd_dev_t {
volatile union {
struct {
uint32_t duty: 8;
uint32_t prescale: 8;
uint32_t reserved16: 16;
};
uint32_t val;
} channel[4];
uint32_t ... | 1,401 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct ledc_dev_s {
struct {
struct {
union {
struct {
uint32_t timer_sel: 2;
uint32_t sig_out_en: 1;
uint32_t id... | 1,402 |
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicab... | 1,404 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define GPIO_MATRIX_CONST_ONE_INPUT (0x1E)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x1F)
#ifdef __cplusplus
}
#endif
| 1,405 |
/*
*/
#pragma once
/**
*/
#define I2C_BOD 0x61
#define I2C_BOD_HOSTID 0
#define I2C_BOD_THRESHOLD 0x5
#define I2C_BOD_THRESHOLD_MSB 2
#define I2C_BOD_THRESHOLD_LSB 0
| 1,408 |
/*
*/
#pragma once
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0000)
/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD0_PRESCALE 0x000000FF
#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V)<<... | 1,410 |
.*/
#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR (BIT(9))
#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M (BIT(9))
#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V 0x1
#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S 9
/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
#define LEDC_DUTY_CHNG_END_... | 1,411 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct uhci_dev_s {
union {
struct {
uint32_t tx_rst: 1; /*Write 1 then write 0 to this bit to reset decode state machine.*/
uint32_t rx_rst: 1; /*Wr... | 1,412 |
*/
uint32_t len_eof_en: 1; /*If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_... | 1,412 |
Triggered when there are some errors in EOF in the*/
uint32_t app_ctrl0: 1; /*Soft control int raw bit.*/
uint32_t app_ctrl1: 1; /*Soft control int raw bit.*/
uint32_t reserved9: 23;
};
uint32_t val;
} int_raw;... | 1,412 |
/*
*/
#pragma once
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/*IRAM0 is connected with Cache IBUS0*/
#define SOC_IRAM0_ADDRESS_LOW 0x4037C000
#define SOC_IRAM0_ADDRESS_HIGH 0x403E0000
#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000
#define SOC_IRAM0_CACHE_ADD... | 1,413 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/*
ESP32C3 Root Clock Source
*/
/* With the default value of CK8M_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */
#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!, F
/**
*/
typedef enum {
// For CPU doma... | 1,416 |
< PLL_F160M_CLK is derived from PLL, and has a fixed frequency of 160MHz */
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc... | 1,416 |
< SYSTIMER source clock default choice is XTAL */
} soc_periph_systimer_clk_src_t;
//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
/**
*/
#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_XTAL}
/**
*/
typedef enum {
GPTIMER_CLK_SRC_A... | 1,416 |
< Select APB as the source clock */
RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
} soc_periph_rmt_cl... | 1,416 |
< Select RC_FAST as the source clock */
TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */
} soc_periph_temperature_sensor_clk_src_t;
///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
/**
*/
#d... | 1,416 |
< Select PLL_F160M as the default source clock */
I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
I2S_CLK_SRC_EXTERNAL = -1, ... | 1,416 |
< Select APB as SPI source clock */
SPI_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as SPI source clock */
SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
} soc_periph_spi_clk_src_t;
//////////////////////////////////////////////////SDM///////////////////////////... | 1,416 |
< Select APB as the source clock */
TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
} soc_periph_twai_clk_src_t;
//////////////////////////////////////////////////ADC///////////////////////////////////////////////////////////////////
/**
*/
#define SOC_ADC_DIGI_CLKS {SOC_MO... | 1,416 |
< Select APB as the default clock choice */
} soc_periph_mwdt_clk_src_t;
//////////////////////////////////////////////////LEDC/////////////////////////////////////////////////////////////////
/**
*/
#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_APB, SOC_MOD_CLK_RC_FAST}
/**
*/
typedef enum {
LEDC_AUTO_... | 1,416 |
< PLL_CLK is the output of crystal oscillator frequency multiplier */
CLKOUT_SIG_RC_SLOW = 4, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */
CLKOUT_SIG_PLL_F80M = 13, /*!< From PLL, usually be 80MHz */
CLKOUT_SIG_RC... | 1,416 |
// Copyright 2021 Espressif Systems (Shanghai) Co. Ltd.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by appli... | 1,417 |
When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know how many data is received, then read that amount of data from UAR... | 1,417 |
*/
uint32_t sof_int_raw : 1; /*The raw interrupt bit turns to high level when a SOF frame is received.*/
uint32_t serial_out_recv_pkt_int_raw : 1; /*The raw interrupt bit turns to high level when the Serial Port OUT Endpoint received one packet.*/
uint32_t... | 1,417 |
*/
uint32_t in_token_rec_in_ep1_int_raw : 1; /*The raw interrupt bit turns to high level when an IN token for IN endpoint 1 is received.*/
uint32_t usb_bus_reset_int_raw : 1; /*The raw interrupt bit turns to high level when a USB bus reset is detected.*/
uint32_t ou... | 1,417 |
*/
uint32_t serial_out_recv_pkt_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.*/
uint32_t serial_in_empty_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/
uint3... | 1,417 |
*/
uint32_t usb_bus_reset_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.*/
uint32_t out_ep1_zero_payload_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
uint32... | 1,417 |
*/
uint32_t serial_in_empty_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/
uint32_t pid_err_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.*/
uint32_t crc5_err_int_ena... | 1,417 |
*/
uint32_t out_ep2_zero_payload_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
uint32_t reserved12 : 20; /*reserved*/
};
uint32_t val;
} int_ena;
union {
struct {
uint3... | 1,417 |
*/
uint32_t crc16_err_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.*/
uint32_t stuff_err_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.*/
uint32_t in_token_rec_in_ep1_int_clr : ... | 1,417 |
1’b0: internal PHY, 1’b1: external PHY*/
uint32_t exchg_pins_override : 1; /*Enable software control USB D+ D- exchange*/
uint32_t exchg_pins : 1; /*USB D+ D- exchange*/
uint32_t vrefh : 2; /*Control single-end input h... | 1,417 |
*/
uint32_t pullup_value : 1; /*Control pull up value.*/
uint32_t usb_pad_enable : 1; /*Enable USB pad function.*/
uint32_t reserved15 : 17;
};
uint32_t val;
} conf0;
union {
struct {
... | 1,417 |
*/
uint32_t out_fifo_cnt : 2; /*JTAT out fifo counter.*/
uint32_t out_fifo_empty : 1; /*1: JTAG out fifo is empty.*/
uint32_t out_fifo_full : 1; /*1: JTAG out fifo is full.*/
uint32_t in_fifo_reset ... | 1,417 |
*/
uint32_t in_ep0_rd_addr : 7; /*Read data address of IN endpoint 0.*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} in_ep0_st;
union {
struct {
uint32_t in_ep1_state : 2; /*St... | 1,417 |
*/
uint32_t in_ep3_wr_addr : 7; /*Write data address of IN endpoint 3.*/
uint32_t in_ep3_rd_addr : 7; /*Read data address of IN endpoint 3.*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} in_... | 1,417 |
*/
uint32_t out_ep1_wr_addr : 7; /*Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.*/
uint32_t out_ep1_rd_addr : 7; /*Read data address of OUT en... | 1,417 |
*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} out_ep2_st;
union {
struct {
uint32_t clk_en : 1; /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
... | 1,417 |
/*
*/
#ifndef _SOC_SPI_REG_H_
#define _SOC_SPI_REG_H_
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)
/* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
/*description: User define command enable. An operation will be triggered when the bit is set.
... | 1,418 |
Can be configured in CONF state..*/
#define SPI_USR_ADDR_VALUE 0xFFFFFFFF
#define SPI_USR_ADDR_VALUE_M ((SPI_USR_ADDR_VALUE_V)<<(SPI_USR_ADDR_VALUE_S))
#define SPI_USR_ADDR_VALUE_V 0xFFFFFFFF
#define SPI_USR_ADDR_VALUE_S 0
#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8)
/* SPI_WR_BIT_ORDER : R/W ;bitpo... | 1,418 |
1: output high, 0: output low. C
an be configured in CONF state..*/
#define SPI_WP_POL (BIT(21))
#define SPI_WP_POL_M (BIT(21))
#define SPI_WP_POL_V 0x1
#define SPI_WP_POL_S 21
/* SPI_HOLD_POL : R/W ;bitpos:[20] ;default: 1'b1 ; */
/*description: SPI_HOLD output value when SPI is idle. 1: output high, 0: outpu... | 1,418 |
1: enable 0: disable. C
an be configured in CONF state..*/
#define SPI_FREAD_QUAD (BIT(15))
#define SPI_FREAD_QUAD_M (BIT(15))
#define SPI_FREAD_QUAD_V 0x1
#define SPI_FREAD_QUAD_S 15
/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: In the read operations, read-data phase apply 2 signals.... | 1,418 |
Can be configured in CONF
state..*/
#define SPI_FADDR_QUAD (BIT(6))
#define SPI_FADDR_QUAD_M (BIT(6))
#define SPI_FADDR_QUAD_V 0x1
#define SPI_FADDR_QUAD_S 6
/* SPI_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
s... | 1,418 |
.*/
#define SPI_CLK_EQU_SYSCLK (BIT(31))
#define SPI_CLK_EQU_SYSCLK_M (BIT(31))
#define SPI_CLK_EQU_SYSCLK_V 0x1
#define SPI_CLK_EQU_SYSCLK_S 31
/* SPI_CLKDIV_PRE : R/W ;bitpos:[21:18] ;default: 4'b0 ; */
/*description: In the master mode it is pre-divider of spi_clk. Can be configured in CONF stat
e..*/
#define... | 1,418 |
Can be configured in CONF state..*/
#define SPI_CLKCNT_H 0x0000003F
#define SPI_CLKCNT_H_M ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S))
#define SPI_CLKCNT_H_V 0x3F
#define SPI_CLKCNT_H_S 6
/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
/*description: In the master mode it must be equal to spi_clkcnt_N. In the s... | 1,418 |
Can be configured in CONF sta
te..*/
#define SPI_USR_ADDR (BIT(30))
#define SPI_USR_ADDR_M (BIT(30))
#define SPI_USR_ADDR_V 0x1
#define SPI_USR_ADDR_S 30
/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: This bit enable the dummy phase of an operation. Can be configured in CONF state
..*/
#d... | 1,418 |
Can be configured in
CONF state..*/
#define SPI_USR_DUMMY_IDLE (BIT(26))
#define SPI_USR_DUMMY_IDLE_M (BIT(26))
#define SPI_USR_DUMMY_IDLE_V 0x1
#define SPI_USR_DUMMY_IDLE_S 26
/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: write-data phase only access to high-part of the buffer ... | 1,418 |
1: enable 0: disable. Can be configured in CONF state..*/
#define SPI_SIO (BIT(17))
#define SPI_SIO_M (BIT(17))
#define SPI_SIO_V 0x1
#define SPI_SIO_S 17
/* SPI_USR_CONF_NXT : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
will... | 1,418 |
Can be configured in CO
NF state..*/
#define SPI_FWRITE_DUAL (BIT(12))
#define SPI_FWRITE_DUAL_M (BIT(12))
#define SPI_FWRITE_DUAL_V 0x1
#define SPI_FWRITE_DUAL_S 12
/* SPI_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mod... | 1,418 |
1: enable 0: disable. Can be config
ured in CONF state..*/
#define SPI_CS_HOLD (BIT(6))
#define SPI_CS_HOLD_M (BIT(6))
#define SPI_CS_HOLD_V 0x1
#define SPI_CS_HOLD_S 6
/* SPI_TSCK_I_EDGE : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: In the slave mode, this bit can be used to change the polarity of tsck. ... | 1,418 |
The register value shall be (bit_num-1). Ca
n be configured in CONF state..*/
#define SPI_USR_ADDR_BITLEN 0x0000001F
#define SPI_USR_ADDR_BITLEN_M ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S))
#define SPI_USR_ADDR_BITLEN_V 0x1F
#define SPI_USR_ADDR_BITLEN_S 27
/* SPI_CS_HOLD_TIME : R/W ;bitpos:[26:22] ;defa... | 1,418 |
0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid
in GP-SPI master FD/HD-mode..*/
#define SPI_MST_WFULL_ERR_END_EN (BIT(16))
#define SPI_MST_WFULL_ERR_END_EN_M (BIT(16))
#define SPI_MST_WFULL_ERR_END_EN_V 0x1
#define SPI_MST_WFULL_ERR_END_EN_S 16
/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;... | 1,418 |
0: SPI transfer is not ended when SPI TX AFIFO read empty erro
r is valid in GP-SPI master FD/HD-mode..*/
#define SPI_MST_REMPTY_ERR_END_EN (BIT(27))
#define SPI_MST_REMPTY_ERR_END_EN_M (BIT(27))
#define SPI_MST_REMPTY_ERR_END_EN_V 0x1
#define SPI_MST_REMPTY_ERR_END_EN_S 27
/* SPI_USR_COMMAND_VALUE : R/W ;bitpos... | 1,418 |
Can be configured in CONF state..*/
#define SPI_MS_DATA_BITLEN 0x0003FFFF
#define SPI_MS_DATA_BITLEN_M ((SPI_MS_DATA_BITLEN_V)<<(SPI_MS_DATA_BITLEN_S))
#define SPI_MS_DATA_BITLEN_V 0x3FFFF
#define SPI_MS_DATA_BITLEN_S 0
#define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20)
/* SPI_QUAD_DIN_PIN_SWAP : R/W ;bi... | 1,418 |
Can be c
onfigured in CONF state..*/
#define SPI_CK_IDLE_EDGE (BIT(29))
#define SPI_CK_IDLE_EDGE_M (BIT(29))
#define SPI_CK_IDLE_EDGE_V 0x1
#define SPI_CK_IDLE_EDGE_S 29
/* SPI_SLAVE_CS_POL : R/W ;bitpos:[23] ;default: 1'b0 ; */
/*description: spi slave input cs polarity select. 1: inv 0: not change. Can be con... | 1,418 |
Can be configured in CONF state..*/
#define SPI_CK_DIS (BIT(6))
#define SPI_CK_DIS_M (BIT(6))
#define SPI_CK_DIS_V 0x1
#define SPI_CK_DIS_S 6
/* SPI_CS5_DIS : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
n be configured in CON... | 1,418 |
Ca
n be configured in CONF state..*/
#define SPI_CS2_DIS (BIT(2))
#define SPI_CS2_DIS_M (BIT(2))
#define SPI_CS2_DIS_V 0x1
#define SPI_CS2_DIS_S 2
/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
n be configured i... | 1,418 |
Can be configured in CONF state..*/
#define SPI_DIN3_MODE 0x00000003
#define SPI_DIN3_MODE_M ((SPI_DIN3_MODE_V)<<(SPI_DIN3_MODE_S))
#define SPI_DIN3_MODE_V 0x3
#define SPI_DIN3_MODE_S 6
/* SPI_DIN2_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
/*description: the input signals are delayed by SPI module clock cycle... | 1,418 |
Can be configured in CONF state..*/
#define SPI_DIN0_MODE 0x00000003
#define SPI_DIN0_MODE_M ((SPI_DIN0_MODE_V)<<(SPI_DIN0_MODE_S))
#define SPI_DIN0_MODE_V 0x3
#define SPI_DIN0_MODE_S 0
#define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x28)
/* SPI_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
/*descrip... | 1,418 |
.. Can be configured in CONF state..*/
#define SPI_DIN1_NUM 0x00000003
#define SPI_DIN1_NUM_M ((SPI_DIN1_NUM_V)<<(SPI_DIN1_NUM_S))
#define SPI_DIN1_NUM_V 0x3
#define SPI_DIN1_NUM_S 2
/* SPI_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: the input signals are delayed by SPI module clock cycles, 0... | 1,418 |
Can be co
nfigured in CONF state..*/
#define SPI_DOUT2_MODE (BIT(2))
#define SPI_DOUT2_MODE_M (BIT(2))
#define SPI_DOUT2_MODE_V 0x1
#define SPI_DOUT2_MODE_S 2
/* SPI_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
ed... | 1,418 |
.*/
#define SPI_DMA_AFIFO_RST (BIT(31))
#define SPI_DMA_AFIFO_RST_M (BIT(31))
#define SPI_DMA_AFIFO_RST_V 0x1
#define SPI_DMA_AFIFO_RST_S 31
/* SPI_BUF_AFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
/*description: Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
controlled mode t... | 1,418 |
.*/
#define SPI_DMA_RX_ENA (BIT(27))
#define SPI_DMA_RX_ENA_M (BIT(27))
#define SPI_DMA_RX_ENA_V 0x1
#define SPI_DMA_RX_ENA_S 27
/* SPI_RX_EOF_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
/*description: 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal t
o the value of spi_slv/mst_dma_rd... | 1,418 |
0: spi_dma_infifo_full
_vld is cleared by spi_trans_done..*/
#define SPI_SLV_RX_SEG_TRANS_CLR_EN (BIT(19))
#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M (BIT(19))
#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V 0x1
#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S 19
/* SPI_DMA_SLV_SEG_TRANS_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
/*descri... | 1,418 |
.*/
#define SPI_APP2_INT_ENA (BIT(19))
#define SPI_APP2_INT_ENA_M (BIT(19))
#define SPI_APP2_INT_ENA_V 0x1
#define SPI_APP2_INT_ENA_S 19
/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
/*description: The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
#define SPI_MST_TX_... | 1,418 |
.*/
#define SPI_SLV_CMD_ERR_INT_ENA (BIT(16))
#define SPI_SLV_CMD_ERR_INT_ENA_M (BIT(16))
#define SPI_SLV_CMD_ERR_INT_ENA_V 0x1
#define SPI_SLV_CMD_ERR_INT_ENA_S 16
/* SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
#defi... | 1,418 |
.*/
#define SPI_TRANS_DONE_INT_ENA (BIT(12))
#define SPI_TRANS_DONE_INT_ENA_M (BIT(12))
#define SPI_TRANS_DONE_INT_ENA_V 0x1
#define SPI_TRANS_DONE_INT_ENA_S 12
/* SPI_SLV_WR_BUF_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
#define SPI... | 1,418 |
.*/
#define SPI_SLV_RD_DMA_DONE_INT_ENA (BIT(8))
#define SPI_SLV_RD_DMA_DONE_INT_ENA_M (BIT(8))
#define SPI_SLV_RD_DMA_DONE_INT_ENA_V 0x1
#define SPI_SLV_RD_DMA_DONE_INT_ENA_S 8
/* SPI_SLV_CMDA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: The enable bit for SPI slave CMDA interrupt..*/
#define SPI... | 1,418 |
.*/
#define SPI_SLV_CMD7_INT_ENA (BIT(4))
#define SPI_SLV_CMD7_INT_ENA_M (BIT(4))
#define SPI_SLV_CMD7_INT_ENA_V 0x1
#define SPI_SLV_CMD7_INT_ENA_S 4
/* SPI_SLV_EN_QPI_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: The enable bit for SPI slave En_QPI interrupt..*/
#define SPI_SLV_EN_QPI_INT_ENA (... | 1,418 |
.*/
#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA (BIT(0))
#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M (BIT(0))
#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V 0x1
#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S 0
#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x38)
/* SPI_APP1_INT_CLR : WT ;bitpos:[20] ;default: 1'b0 ;... | 1,418 |
.*/
#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR (BIT(17))
#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M (BIT(17))
#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V 0x1
#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S 17
/* SPI_SLV_CMD_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */
/*description: The clear bit for SPI_SLV... | 1,418 |
.*/
#define SPI_DMA_SEG_TRANS_DONE_INT_CLR (BIT(13))
#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M (BIT(13))
#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V 0x1
#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S 13
/* SPI_TRANS_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
/*description: The clear bit for SPI_TRANS_DONE_INT inter... | 1,418 |
.*/
#define SPI_SLV_WR_DMA_DONE_INT_CLR (BIT(9))
#define SPI_SLV_WR_DMA_DONE_INT_CLR_M (BIT(9))
#define SPI_SLV_WR_DMA_DONE_INT_CLR_V 0x1
#define SPI_SLV_WR_DMA_DONE_INT_CLR_S 9
/* SPI_SLV_RD_DMA_DONE_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
/*description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt..... | 1,418 |
.*/
#define SPI_SLV_CMD8_INT_CLR (BIT(5))
#define SPI_SLV_CMD8_INT_CLR_M (BIT(5))
#define SPI_SLV_CMD8_INT_CLR_V 0x1
#define SPI_SLV_CMD8_INT_CLR_S 5
/* SPI_SLV_CMD7_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
/*description: The clear bit for SPI slave CMD7 interrupt..*/
#define SPI_SLV_CMD7_INT_CLR (BIT(4))
... | 1,418 |
.*/
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR (BIT(1))
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M (BIT(1))
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V 0x1
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S 1
/* SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: The clear bit for SPI_DMA... | 1,418 |
The value is only controlled by applicat
ion..*/
#define SPI_APP2_INT_RAW (BIT(19))
#define SPI_APP2_INT_RAW_M (BIT(19))
#define SPI_APP2_INT_RAW_V 0x1
#define SPI_APP2_INT_RAW_S 19
/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */
/*description: The raw bit for SPI_MST_TX_AFIF... | 1,418 |
1: The slave command value in the
current SPI slave HD mode transmission is not supported. 0: Others..*/
#define SPI_SLV_CMD_ERR_INT_RAW (BIT(16))
#define SPI_SLV_CMD_ERR_INT_RAW_M (BIT(16))
#define SPI_SLV_CMD_ERR_INT_RAW_V 0x1
#define SPI_SLV_CMD_ERR_INT_RAW_S 16
/* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/W/WTC/SS ;... | 1,418 |
1: spi master DMA full-du
plex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And da
ta has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is
not ended or not occurred. .*/
#define SPI_DMA_SEG_TRANS_DONE_INT_RAW (BIT(13))
#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M (BIT(1... | 1,418 |
1: SPI slave mode Rd_BUF tran
smission is ended. 0: Others..*/
#define SPI_SLV_RD_BUF_DONE_INT_RAW (BIT(10))
#define SPI_SLV_RD_BUF_DONE_INT_RAW_M (BIT(10))
#define SPI_SLV_RD_BUF_DONE_INT_RAW_V 0x1
#define SPI_SLV_RD_BUF_DONE_INT_RAW_S 10
/* SPI_SLV_WR_DMA_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[9] ;default: 1'b0 ; ... | 1,418 |
1: SPI slave mode CMDA transmission is
ended. 0: Others..*/
#define SPI_SLV_CMDA_INT_RAW (BIT(7))
#define SPI_SLV_CMDA_INT_RAW_M (BIT(7))
#define SPI_SLV_CMDA_INT_RAW_V 0x1
#define SPI_SLV_CMDA_INT_RAW_S 7
/* SPI_SLV_CMD9_INT_RAW : R/W/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
/*description: The raw bit for SPI sl... | 1,418 |
1: SPI slave mode CMD7 transmission is
ended. 0: Others..*/
#define SPI_SLV_CMD7_INT_RAW (BIT(4))
#define SPI_SLV_CMD7_INT_RAW_M (BIT(4))
#define SPI_SLV_CMD7_INT_RAW_V 0x1
#define SPI_SLV_CMD7_INT_RAW_S 4
/* SPI_SLV_EN_QPI_INT_RAW : R/W/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw bit for SPI ... | 1,418 |
SPI will stop in
master mode and send out all 0 in slave mode. 0: Others. .*/
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW (BIT(1))
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M (BIT(1))
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V 0x1
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S 1
/* SPI_DMA_INFIFO_FULL_ERR_INT_RAW... | 1,418 |
.*/
#define SPI_APP2_INT_ST (BIT(19))
#define SPI_APP2_INT_ST_M (BIT(19))
#define SPI_APP2_INT_ST_V 0x1
#define SPI_APP2_INT_ST_S 19
/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
/*description: The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
#define SPI_MST_TX_AFIFO_... | 1,418 |
.*/
#define SPI_SLV_BUF_ADDR_ERR_INT_ST (BIT(15))
#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M (BIT(15))
#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V 0x1
#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S 15
/* SPI_SEG_MAGIC_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
/*description: The status bit for SPI_SEG_MAGIC_ERR_INT interrupt..... | 1,418 |
.*/
#define SPI_SLV_WR_BUF_DONE_INT_ST (BIT(11))
#define SPI_SLV_WR_BUF_DONE_INT_ST_M (BIT(11))
#define SPI_SLV_WR_BUF_DONE_INT_ST_V 0x1
#define SPI_SLV_WR_BUF_DONE_INT_ST_S 11
/* SPI_SLV_RD_BUF_DONE_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt..... | 1,418 |
.*/
#define SPI_SLV_CMDA_INT_ST (BIT(7))
#define SPI_SLV_CMDA_INT_ST_M (BIT(7))
#define SPI_SLV_CMDA_INT_ST_V 0x1
#define SPI_SLV_CMDA_INT_ST_S 7
/* SPI_SLV_CMD9_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The status bit for SPI slave CMD9 interrupt..*/
#define SPI_SLV_CMD9_INT_ST (BIT(6))
#defi... | 1,418 |
.*/
#define SPI_SLV_EN_QPI_INT_ST (BIT(3))
#define SPI_SLV_EN_QPI_INT_ST_M (BIT(3))
#define SPI_SLV_EN_QPI_INT_ST_V 0x1
#define SPI_SLV_EN_QPI_INT_ST_S 3
/* SPI_SLV_EX_QPI_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: The status bit for SPI slave Ex_QPI interrupt..*/
#define SPI_SLV_EX_QPI_INT_ST ... | 1,418 |
*/
#define SPI_BUF0 0xFFFFFFFF
#define SPI_BUF0_M ((SPI_BUF0_V)<<(SPI_BUF0_S))
#define SPI_BUF0_V 0xFFFFFFFF
#define SPI_BUF0_S 0
#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x9C)
/* SPI_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF1 0xFFFFFFFF
#define S... | 1,418 |
*/
#define SPI_BUF4 0xFFFFFFFF
#define SPI_BUF4_M ((SPI_BUF4_V)<<(SPI_BUF4_S))
#define SPI_BUF4_V 0xFFFFFFFF
#define SPI_BUF4_S 0
#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0xAC)
/* SPI_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF5 0xFFFFFFFF
#define S... | 1,418 |
*/
#define SPI_BUF8 0xFFFFFFFF
#define SPI_BUF8_M ((SPI_BUF8_V)<<(SPI_BUF8_S))
#define SPI_BUF8_V 0xFFFFFFFF
#define SPI_BUF8_S 0
#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xBC)
/* SPI_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF9 0xFFFFFFFF
#define S... | 1,418 |
*/
#define SPI_BUF12 0xFFFFFFFF
#define SPI_BUF12_M ((SPI_BUF12_V)<<(SPI_BUF12_S))
#define SPI_BUF12_V 0xFFFFFFFF
#define SPI_BUF12_S 0
#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xCC)
/* SPI_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF13 0xFFFFFFFF
... | 1,418 |
0: This is not seg-trans mode..*/
#define SPI_USR_CONF (BIT(28))
#define SPI_USR_CONF_M (BIT(28))
#define SPI_USR_CONF_V 0x1
#define SPI_USR_CONF_S 28
/* SPI_SOFT_RESET : WT ;bitpos:[27] ;default: 1'b0 ; */
/*description: Software reset enable, reset the spi clock line cs line and data lines. Can be c
onfigured ... | 1,418 |
0: others.*/
#define SPI_SLV_WRBUF_BITLEN_EN (BIT(11))
#define SPI_SLV_WRBUF_BITLEN_EN_M (BIT(11))
#define SPI_SLV_WRBUF_BITLEN_EN_V 0x1
#define SPI_SLV_WRBUF_BITLEN_EN_S 11
/* SPI_SLV_RDBUF_BITLEN_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-re... | 1,418 |
0: others.*/
#define SPI_SLV_RDDMA_BITLEN_EN (BIT(8))
#define SPI_SLV_RDDMA_BITLEN_EN_M (BIT(8))
#define SPI_SLV_RDDMA_BITLEN_EN_V 0x1
#define SPI_SLV_RDDMA_BITLEN_EN_S 8
/* SPI_RSCK_DATA_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: It saves half a cycle when tsck is the same as rsck. 1: output data ... | 1,418 |
Can be configured in CONF state..*/
#define SPI_CLK_MODE 0x00000003
#define SPI_CLK_MODE_M ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S))
#define SPI_CLK_MODE_V 0x3
#define SPI_CLK_MODE_S 0
#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0xE4)
/* SPI_SLV_LAST_ADDR : R/W/SS ;bitpos:[31:26] ;default: 6'd0 ; */
/*desc... | 1,418 |
.*/
#define SPI_SLV_DATA_BITLEN 0x0003FFFF
#define SPI_SLV_DATA_BITLEN_M ((SPI_SLV_DATA_BITLEN_V)<<(SPI_SLV_DATA_BITLEN_S))
#define SPI_SLV_DATA_BITLEN_V 0x3FFFF
#define SPI_SLV_DATA_BITLEN_S 0
#define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0xE8)
/* SPI_MST_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */... | 1,418 |
.*/
#define SPI_DATE 0x0FFFFFFF
#define SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S))
#define SPI_DATE_V 0xFFFFFFF
#define SPI_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_SPI_REG_H_ */
| 1,418 |
/*
*/
#define DR_REG_SYSTEM_BASE 0x600c0000
#define DR_REG_SENSITIVE_BASE 0x600c1000
#define DR_REG_INTERRUPT_BASE 0x600c2000
#define DR_REG_EXTMEM_BASE 0x600c4000
#define DR_REG_MMU_TABLE 0x600c5000
#define DR_REG_AES... | 1,419 |
/*
*/
#pragma once
#ifndef __ASSEMBLER__
#include
#include "esp_assert.h"
#endif
#include "esp_bit_defs.h"
#include "reg_base.h"
#define PRO_CPU_NUM (0)
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)
#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1... | 1,420 |
__ASSEMBLER__ */
//}}
//Periheral Clock {{
#define APB_CLK_FREQ_ROM ( 40*1000000 )
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader sys... | 1,420 |
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