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#define SOC_DIRAM_IRAM_LOW 0x40380000
#define SOC_DIRAM_IRAM_HIGH 0x403E0000
#define SOC_DIRAM_DRAM_LOW 0x3FC80000
#define SOC_DIRAM_DRAM_HIGH 0x3FCE0000
#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET)
#define MAP_IRAM_TO_DRAM(addr) (ad... | 1,420 |
//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.
//CPU0 Interrupt numbers used in components/riscv/vectors.S. Change it's logic if modifying
#define ETS_T1_WDT_INUM 24
#define ETS_CACHEERR_INUM 25
#define ETS_MEMPROT_ERR_INUM... | 1,420 |
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applic... | 1,421 |
*/
#define I2C_ADDR_BROADCASTING_EN (BIT(14))
#define I2C_ADDR_BROADCASTING_EN_M (BIT(14))
#define I2C_ADDR_BROADCASTING_EN_V 0x1
#define I2C_ADDR_BROADCASTING_EN_S 14
/* I2C_ADDR_10BIT_RW_CHECK_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: .*/
#define I2C_ADDR_10BIT_RW_CHECK_EN (BIT(13))
#define I2... | 1,421 |
*/
#define I2C_ARBITRATION_EN (BIT(9))
#define I2C_ARBITRATION_EN_M (BIT(9))
#define I2C_ARBITRATION_EN_V 0x1
#define I2C_ARBITRATION_EN_S 9
/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: .*/
#define I2C_CLK_EN (BIT(8))
#define I2C_CLK_EN_M (BIT(8))
#define I2C_CLK_EN_V 0x1
#define I2C_CL... | 1,421 |
*/
#define I2C_MS_MODE (BIT(4))
#define I2C_MS_MODE_M (BIT(4))
#define I2C_MS_MODE_V 0x1
#define I2C_MS_MODE_S 4
/* I2C_RX_FULL_ACK_LEVEL : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: .*/
#define I2C_RX_FULL_ACK_LEVEL (BIT(3))
#define I2C_RX_FULL_ACK_LEVEL_M (BIT(3))
#define I2C_RX_FULL_ACK_LEVEL_V 0x... | 1,421 |
*/
#define I2C_SCL_STATE_LAST 0x00000007
#define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S))
#define I2C_SCL_STATE_LAST_V 0x7
#define I2C_SCL_STATE_LAST_S 28
/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
/*description: .*/
#define I2C_SCL_MAIN_STATE_LAST 0x000000... | 1,421 |
*/
#define I2C_RXFIFO_CNT 0x0000003F
#define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S))
#define I2C_RXFIFO_CNT_V 0x3F
#define I2C_RXFIFO_CNT_S 8
/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: .*/
#define I2C_SLAVE_ADDRESSED (BIT(5))
#define I2C_SLAVE_ADDRESSED_M (BIT... | 1,421 |
*/
#define I2C_RESP_REC (BIT(0))
#define I2C_RESP_REC_M (BIT(0))
#define I2C_RESP_REC_V 0x1
#define I2C_RESP_REC_S 0
#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0xC)
/* I2C_TIME_OUT_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: .*/
#define I2C_TIME_OUT_EN (BIT(5))
#define I2C_TIME_OUT_EN_M (B... | 1,421 |
*/
#define I2C_SLAVE_ADDR 0x00007FFF
#define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S))
#define I2C_SLAVE_ADDR_V 0x7FFF
#define I2C_SLAVE_ADDR_S 0
#define I2C_FIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x14)
/* I2C_SLAVE_RW_POINT : RO ;bitpos:[29:22] ;default: 8'b0 ; */
/*description: .*/
#define ... | 1,421 |
*/
#define I2C_RXFIFO_WADDR 0x0000001F
#define I2C_RXFIFO_WADDR_M ((I2C_RXFIFO_WADDR_V)<<(I2C_RXFIFO_WADDR_S))
#define I2C_RXFIFO_WADDR_V 0x1F
#define I2C_RXFIFO_WADDR_S 5
/* I2C_RXFIFO_RADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */
/*description: .*/
#define I2C_RXFIFO_RADDR 0x0000001F
#define I2C_RXFIFO_RADDR_... | 1,421 |
*/
#define I2C_FIFO_ADDR_CFG_EN (BIT(11))
#define I2C_FIFO_ADDR_CFG_EN_M (BIT(11))
#define I2C_FIFO_ADDR_CFG_EN_V 0x1
#define I2C_FIFO_ADDR_CFG_EN_S 11
/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: .*/
#define I2C_NONFIFO_EN (BIT(10))
#define I2C_NONFIFO_EN_M (BIT(10))
#define I2C_NO... | 1,421 |
*/
#define I2C_FIFO_RDATA 0x000000FF
#define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S))
#define I2C_FIFO_RDATA_V 0xFF
#define I2C_FIFO_RDATA_S 0
#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x20)
/* I2C_GENERAL_CALL_INT_RAW : R/SS/WTC ;bitpos:[17] ;default: 1'b0 ; */
/*description: .*/
#... | 1,421 |
*/
#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14))
#define I2C_SCL_MAIN_ST_TO_INT_RAW_M (BIT(14))
#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x1
#define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14
/* I2C_SCL_ST_TO_INT_RAW : R/SS/WTC ;bitpos:[13] ;default: 1'b0 ; */
/*description: .*/
#define I2C_SCL_ST_TO_INT_RAW (BIT(13))
#define... | 1,421 |
*/
#define I2C_NACK_INT_RAW (BIT(10))
#define I2C_NACK_INT_RAW_M (BIT(10))
#define I2C_NACK_INT_RAW_V 0x1
#define I2C_NACK_INT_RAW_S 10
/* I2C_TRANS_START_INT_RAW : R/SS/WTC ;bitpos:[9] ;default: 1'b0 ; */
/*description: .*/
#define I2C_TRANS_START_INT_RAW (BIT(9))
#define I2C_TRANS_START_INT_RAW_M (BIT(9))
#... | 1,421 |
*/
#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5))
#define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5))
#define I2C_ARBITRATION_LOST_INT_RAW_V 0x1
#define I2C_ARBITRATION_LOST_INT_RAW_S 5
/* I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC ;bitpos:[4] ;default: 1'b0 ; */
/*description: .*/
#define I2C_BYTE_TRANS_DONE_INT_RAW (... | 1,421 |
*/
#define I2C_TXFIFO_WM_INT_RAW (BIT(1))
#define I2C_TXFIFO_WM_INT_RAW_M (BIT(1))
#define I2C_TXFIFO_WM_INT_RAW_V 0x1
#define I2C_TXFIFO_WM_INT_RAW_S 1
/* I2C_RXFIFO_WM_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define I2C_RXFIFO_WM_INT_RAW (BIT(0))
#define I2C_RXFIFO_WM_INT_RAW_M ... | 1,421 |
*/
#define I2C_DET_START_INT_CLR (BIT(15))
#define I2C_DET_START_INT_CLR_M (BIT(15))
#define I2C_DET_START_INT_CLR_V 0x1
#define I2C_DET_START_INT_CLR_S 15
/* I2C_SCL_MAIN_ST_TO_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */
/*description: .*/
#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14))
#define I2C_SCL_MAIN_ST... | 1,421 |
*/
#define I2C_NACK_INT_CLR (BIT(10))
#define I2C_NACK_INT_CLR_M (BIT(10))
#define I2C_NACK_INT_CLR_V 0x1
#define I2C_NACK_INT_CLR_S 10
/* I2C_TRANS_START_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
/*description: .*/
#define I2C_TRANS_START_INT_CLR (BIT(9))
#define I2C_TRANS_START_INT_CLR_M (BIT(9))
#define... | 1,421 |
*/
#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5))
#define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5))
#define I2C_ARBITRATION_LOST_INT_CLR_V 0x1
#define I2C_ARBITRATION_LOST_INT_CLR_S 5
/* I2C_BYTE_TRANS_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
/*description: .*/
#define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)... | 1,421 |
*/
#define I2C_TXFIFO_WM_INT_CLR (BIT(1))
#define I2C_TXFIFO_WM_INT_CLR_M (BIT(1))
#define I2C_TXFIFO_WM_INT_CLR_V 0x1
#define I2C_TXFIFO_WM_INT_CLR_S 1
/* I2C_RXFIFO_WM_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define I2C_RXFIFO_WM_INT_CLR (BIT(0))
#define I2C_RXFIFO_WM_INT_CLR_M (BIT(... | 1,421 |
*/
#define I2C_DET_START_INT_ENA (BIT(15))
#define I2C_DET_START_INT_ENA_M (BIT(15))
#define I2C_DET_START_INT_ENA_V 0x1
#define I2C_DET_START_INT_ENA_S 15
/* I2C_SCL_MAIN_ST_TO_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: .*/
#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14))
#define I2C_SCL_MAIN_S... | 1,421 |
*/
#define I2C_NACK_INT_ENA (BIT(10))
#define I2C_NACK_INT_ENA_M (BIT(10))
#define I2C_NACK_INT_ENA_V 0x1
#define I2C_NACK_INT_ENA_S 10
/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: .*/
#define I2C_TRANS_START_INT_ENA (BIT(9))
#define I2C_TRANS_START_INT_ENA_M (BIT(9))
#defin... | 1,421 |
*/
#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5))
#define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5))
#define I2C_ARBITRATION_LOST_INT_ENA_V 0x1
#define I2C_ARBITRATION_LOST_INT_ENA_S 5
/* I2C_BYTE_TRANS_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: .*/
#define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4... | 1,421 |
*/
#define I2C_TXFIFO_WM_INT_ENA (BIT(1))
#define I2C_TXFIFO_WM_INT_ENA_M (BIT(1))
#define I2C_TXFIFO_WM_INT_ENA_V 0x1
#define I2C_TXFIFO_WM_INT_ENA_S 1
/* I2C_RXFIFO_WM_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define I2C_RXFIFO_WM_INT_ENA (BIT(0))
#define I2C_RXFIFO_WM_INT_ENA_M (BIT... | 1,421 |
*/
#define I2C_DET_START_INT_ST (BIT(15))
#define I2C_DET_START_INT_ST_M (BIT(15))
#define I2C_DET_START_INT_ST_V 0x1
#define I2C_DET_START_INT_ST_S 15
/* I2C_SCL_MAIN_ST_TO_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
/*description: .*/
#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14))
#define I2C_SCL_MAIN_ST_TO_IN... | 1,421 |
*/
#define I2C_NACK_INT_ST (BIT(10))
#define I2C_NACK_INT_ST_M (BIT(10))
#define I2C_NACK_INT_ST_V 0x1
#define I2C_NACK_INT_ST_S 10
/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: .*/
#define I2C_TRANS_START_INT_ST (BIT(9))
#define I2C_TRANS_START_INT_ST_M (BIT(9))
#define I2C_TR... | 1,421 |
*/
#define I2C_ARBITRATION_LOST_INT_ST (BIT(5))
#define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5))
#define I2C_ARBITRATION_LOST_INT_ST_V 0x1
#define I2C_ARBITRATION_LOST_INT_ST_S 5
/* I2C_BYTE_TRANS_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: .*/
#define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4))
#def... | 1,421 |
*/
#define I2C_RXFIFO_WM_INT_ST (BIT(0))
#define I2C_RXFIFO_WM_INT_ST_M (BIT(0))
#define I2C_RXFIFO_WM_INT_ST_V 0x1
#define I2C_RXFIFO_WM_INT_ST_S 0
#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x30)
/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */
/*description: .*/
#define I2C_SDA_HOLD_T... | 1,421 |
*/
#define I2C_SCL_HIGH_PERIOD 0x000001FF
#define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S))
#define I2C_SCL_HIGH_PERIOD_V 0x1FF
#define I2C_SCL_HIGH_PERIOD_S 0
#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x40)
/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[8:0] ;defaul... | 1,421 |
*/
#define I2C_SCL_STOP_HOLD_TIME 0x000001FF
#define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S))
#define I2C_SCL_STOP_HOLD_TIME_V 0x1FF
#define I2C_SCL_STOP_HOLD_TIME_S 0
#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x4C)
/* I2C_SCL_STOP_SETUP_TIME : R/W ;bi... | 1,421 |
*/
#define I2C_SDA_FILTER_THRES 0x0000000F
#define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S))
#define I2C_SDA_FILTER_THRES_V 0xF
#define I2C_SDA_FILTER_THRES_S 4
/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: .*/
#define I2C_SCL_FILTER_THRES 0x00... | 1,421 |
*/
#define I2C_SCLK_DIV_B 0x0000003F
#define I2C_SCLK_DIV_B_M ((I2C_SCLK_DIV_B_V)<<(I2C_SCLK_DIV_B_S))
#define I2C_SCLK_DIV_B_V 0x3F
#define I2C_SCLK_DIV_B_S 14
/* I2C_SCLK_DIV_A : R/W ;bitpos:[13:8] ;default: 6'b0 ; */
/*description: .*/
#define I2C_SCLK_DIV_A 0x0000003F
#define I2C_SCLK_DIV_A_M ((I2C_SCLK_D... | 1,421 |
*/
#define I2C_COMMAND0 0x00003FFF
#define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S))
#define I2C_COMMAND0_V 0x3FFF
#define I2C_COMMAND0_S 0
#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x5C)
/* I2C_COMMAND1_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
/*description: .*/
#define I2C_COMMAND1_D... | 1,421 |
*/
#define I2C_COMMAND2 0x00003FFF
#define I2C_COMMAND2_M ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S))
#define I2C_COMMAND2_V 0x3FFF
#define I2C_COMMAND2_S 0
#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x64)
/* I2C_COMMAND3_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
/*description: .*/
#define I2C_COMMAND3_D... | 1,421 |
*/
#define I2C_COMMAND4 0x00003FFF
#define I2C_COMMAND4_M ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S))
#define I2C_COMMAND4_V 0x3FFF
#define I2C_COMMAND4_S 0
#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x6C)
/* I2C_COMMAND5_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
/*description: .*/
#define I2C_COMMAND5_D... | 1,421 |
*/
#define I2C_COMMAND6 0x00003FFF
#define I2C_COMMAND6_M ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S))
#define I2C_COMMAND6_V 0x3FFF
#define I2C_COMMAND6_S 0
#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x74)
/* I2C_COMMAND7_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
/*description: .*/
#define I2C_COMMAND7_D... | 1,421 |
*/
#define I2C_SCL_MAIN_ST_TO_REG 0x0000001F
#define I2C_SCL_MAIN_ST_TO_REG_M ((I2C_SCL_MAIN_ST_TO_REG_V)<<(I2C_SCL_MAIN_ST_TO_REG_S))
#define I2C_SCL_MAIN_ST_TO_REG_V 0x1F
#define I2C_SCL_MAIN_ST_TO_REG_S 0
#define I2C_SCL_SP_CONF_REG(i) (REG_I2C_BASE(i) + 0x80)
/* I2C_SDA_PD_EN : R/W ;bitpos:[7] ;defa... | 1,421 |
*/
#define I2C_SCL_RST_SLV_EN (BIT(0))
#define I2C_SCL_RST_SLV_EN_M (BIT(0))
#define I2C_SCL_RST_SLV_EN_V 0x1
#define I2C_SCL_RST_SLV_EN_S 0
#define I2C_SCL_STRETCH_CONF_REG(i) (REG_I2C_BASE(i) + 0x84)
/* I2C_SLAVE_BYTE_ACK_LVL : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: .*/
#define I2C_SLAVE_... | 1,421 |
*/
#define I2C_SLAVE_SCL_STRETCH_EN (BIT(10))
#define I2C_SLAVE_SCL_STRETCH_EN_M (BIT(10))
#define I2C_SLAVE_SCL_STRETCH_EN_V 0x1
#define I2C_SLAVE_SCL_STRETCH_EN_S 10
/* I2C_STRETCH_PROTECT_NUM : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
/*description: .*/
#define I2C_STRETCH_PROTECT_NUM 0x000003FF
#define I2C_S... | 1,421 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct gdma_dev_s {
struct {
union {
struct {
uint32_t in_done: 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has ... | 1,424 |
*/
uint32_t out_eof: 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.*/
uint32_t in_dscr_err: 1; /*The raw interrupt bit turns to high level when det... | 1,424 |
*/
uint32_t infifo_ovf: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.*/
uint32_t infifo_udf: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.*/
... | 1,424 |
*/
uint32_t in_err_eof: 1; /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/
uint32_t out_done: 1; /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/
uint32_t out_eof: 1; ... | 1,424 |
*/
uint32_t infifo_udf: 1; /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t outfifo_ovf: 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t outfifo_udf: ... | 1,424 |
*/
uint32_t out_eof: 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/
uint32_t in_dscr_err: 1; /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_dscr_err: 1; /*Th... | 1,424 |
*/
uint32_t outfifo_udf: 1; /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t reserved13: 19; /*reserved*/
};
uint32_t val;
} ena;
union {
struct {
uin... | 1,424 |
*/
uint32_t out_dscr_err: 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t in_dscr_empty: 1; /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_t out_total_eof: 1; /*Set this ... | 1,424 |
*/
uint32_t reserved1: 1;
uint32_t arb_pri_dis: 1; /*Set this bit to disable priority arbitration function.*/
uint32_t clk_en: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} misc_conf;
uint32_t date; ... | 1,424 |
*/
uint32_t in_data_burst_en: 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.*/
uint32_t mem_trans_en: 1; /*Set this bit 1 to enable automatic transmitting data from memory to mem... | 1,424 |
*/
uint32_t infifo_empty: 1; /*L1 Rx FIFO empty signal for Rx channel 0.*/
uint32_t infifo_cnt: 6; /*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/
uint32_t reserved8: 15; ... | 1,424 |
*/
uint32_t infifo_pop: 1; /*Set this bit to pop data from DMA FIFO.*/
uint32_t reserved13: 19; /*reserved*/
};
uint32_t val;
} in_pop;
union {
struct {
... | 1,424 |
*/
uint32_t park: 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/
uint32_t reserved25: 7;
};
uint32_t val;
} in_link;
union {
... | 1,424 |
The larger of the value the higher of the priority.*/
uint32_t reserved4: 28;
};
uint32_t val;
} in_pri;
union {
struct {
uint32_t sel: 6; /*This register is used to select perip... | 1,424 |
*/
uint32_t out_loop_test: 1; /*reserved*/
uint32_t out_auto_wrback: 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/
uint32_t out_eof_mode: 1; /... | 1,424 |
*/
uint32_t reserved13: 19; /*reserved*/
};
uint32_t val;
} out_conf1;
union {
struct {
uint32_t outfifo_full: 1; /*L1 Tx FIFO full signal for Tx channel 0.*/
... | 1,424 |
*/
uint32_t outfifo_push: 1; /*Set this bit to push data into DMA FIFO.*/
uint32_t reserved10: 22; /*reserved*/
};
uint32_t val;
} out_push;
union {
struct {
... | 1,424 |
*/
uint32_t reserved24: 8;
};
uint32_t val;
} out_link;
union {
struct {
uint32_t outlink_dscr_addr: 18; /*This register stores the current outlink descriptor's address.*/
... | 1,424 |
The larger of the value the higher of the priority.*/
uint32_t reserved4: 28;
};
uint32_t val;
} out_pri;
union {
struct {
uint32_t sel: 6; /*This register is used to select peri... | 1,424 |
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applic... | 1,426 |
*/
#define UART_WAKEUP_INT_RAW (BIT(19))
#define UART_WAKEUP_INT_RAW_M (BIT(19))
#define UART_WAKEUP_INT_RAW_V 0x1
#define UART_WAKEUP_INT_RAW_S 19
/* UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */
/*description: This interrupt raw bit turns to high level when receiver detects
the configu... | 1,426 |
*/
#define UART_RS485_FRM_ERR_INT_RAW (BIT(16))
#define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16))
#define UART_RS485_FRM_ERR_INT_RAW_V 0x1
#define UART_RS485_FRM_ERR_INT_RAW_S 16
/* UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */
/*description: This interrupt raw bit turns to high level when ... | 1,426 |
*/
#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13))
#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (BIT(13))
#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x1
#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13
/* UART_TX_BRK_DONE_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */
/*description: This interrupt raw bit turns to high leve... | 1,426 |
*/
#define UART_SW_XOFF_INT_RAW (BIT(10))
#define UART_SW_XOFF_INT_RAW_M (BIT(10))
#define UART_SW_XOFF_INT_RAW_V 0x1
#define UART_SW_XOFF_INT_RAW_S 10
/* UART_SW_XON_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
/*description: This interrupt raw bit turns to high level when receiver recevies
Xon char when ua... | 1,426 |
*/
#define UART_BRK_DET_INT_RAW (BIT(7))
#define UART_BRK_DET_INT_RAW_M (BIT(7))
#define UART_BRK_DET_INT_RAW_V 0x1
#define UART_BRK_DET_INT_RAW_S 7
/* UART_CTS_CHG_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
/*description: This interrupt raw bit turns to high level when receiver detects
the edge change of ... | 1,426 |
*/
#define UART_RXFIFO_OVF_INT_RAW (BIT(4))
#define UART_RXFIFO_OVF_INT_RAW_M (BIT(4))
#define UART_RXFIFO_OVF_INT_RAW_V 0x1
#define UART_RXFIFO_OVF_INT_RAW_S 4
/* UART_FRM_ERR_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
/*description: This interrupt raw bit turns to high level when receiver detects
a data ... | 1,426 |
*/
#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1))
#define UART_TXFIFO_EMPTY_INT_RAW_M (BIT(1))
#define UART_TXFIFO_EMPTY_INT_RAW_V 0x1
#define UART_TXFIFO_EMPTY_INT_RAW_S 1
/* UART_RXFIFO_FULL_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
/*description: This interrupt raw bit turns to high level when receiver rece... | 1,426 |
*/
#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18))
#define UART_AT_CMD_CHAR_DET_INT_ST_M (BIT(18))
#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x1
#define UART_AT_CMD_CHAR_DET_INT_ST_S 18
/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
/*description: This is the status bit for rs485_clash_int_raw when rs48... | 1,426 |
*/
#define UART_RS485_PARITY_ERR_INT_ST (BIT(15))
#define UART_RS485_PARITY_ERR_INT_ST_M (BIT(15))
#define UART_RS485_PARITY_ERR_INT_ST_V 0x1
#define UART_RS485_PARITY_ERR_INT_ST_S 15
/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
/*description: This is the status bit for tx_done_int_raw when tx_done_... | 1,426 |
*/
#define UART_TX_BRK_DONE_INT_ST (BIT(12))
#define UART_TX_BRK_DONE_INT_ST_M (BIT(12))
#define UART_TX_BRK_DONE_INT_ST_V 0x1
#define UART_TX_BRK_DONE_INT_ST_S 12
/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
/*description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena
is... | 1,426 |
*/
#define UART_RXFIFO_TOUT_INT_ST (BIT(8))
#define UART_RXFIFO_TOUT_INT_ST_M (BIT(8))
#define UART_RXFIFO_TOUT_INT_ST_V 0x1
#define UART_RXFIFO_TOUT_INT_ST_S 8
/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
#... | 1,426 |
*/
#define UART_RXFIFO_OVF_INT_ST (BIT(4))
#define UART_RXFIFO_OVF_INT_ST_M (BIT(4))
#define UART_RXFIFO_OVF_INT_ST_V 0x1
#define UART_RXFIFO_OVF_INT_ST_S 4
/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.*/
#defi... | 1,426 |
*/
#define UART_RXFIFO_FULL_INT_ST (BIT(0))
#define UART_RXFIFO_FULL_INT_ST_M (BIT(0))
#define UART_RXFIFO_FULL_INT_ST_V 0x1
#define UART_RXFIFO_FULL_INT_ST_S 0
#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xC)
/* UART_WAKEUP_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
/*description: This is the ena... | 1,426 |
*/
#define UART_RS485_FRM_ERR_INT_ENA (BIT(16))
#define UART_RS485_FRM_ERR_INT_ENA_M (BIT(16))
#define UART_RS485_FRM_ERR_INT_ENA_V 0x1
#define UART_RS485_FRM_ERR_INT_ENA_S 16
/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: This is the enable bit for rs485_parity_err_int_st re... | 1,426 |
*/
#define UART_TX_BRK_DONE_INT_ENA (BIT(12))
#define UART_TX_BRK_DONE_INT_ENA_M (BIT(12))
#define UART_TX_BRK_DONE_INT_ENA_V 0x1
#define UART_TX_BRK_DONE_INT_ENA_S 12
/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: This is the enable bit for glitch_det_int_st register.*/
#define UA... | 1,426 |
*/
#define UART_RXFIFO_TOUT_INT_ENA (BIT(8))
#define UART_RXFIFO_TOUT_INT_ENA_M (BIT(8))
#define UART_RXFIFO_TOUT_INT_ENA_V 0x1
#define UART_RXFIFO_TOUT_INT_ENA_S 8
/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: This is the enable bit for brk_det_int_st register.*/
#define UART_BRK_DET... | 1,426 |
*/
#define UART_RXFIFO_OVF_INT_ENA (BIT(4))
#define UART_RXFIFO_OVF_INT_ENA_M (BIT(4))
#define UART_RXFIFO_OVF_INT_ENA_V 0x1
#define UART_RXFIFO_OVF_INT_ENA_S 4
/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: This is the enable bit for frm_err_int_st register.*/
#define UART_FRM_ERR_INT... | 1,426 |
*/
#define UART_RXFIFO_FULL_INT_ENA (BIT(0))
#define UART_RXFIFO_FULL_INT_ENA_M (BIT(0))
#define UART_RXFIFO_FULL_INT_ENA_V 0x1
#define UART_RXFIFO_FULL_INT_ENA_S 0
#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10)
/* UART_WAKEUP_INT_CLR : WT ;bitpos:[19] ;default: 1'b0 ; */
/*description: Set this bi... | 1,426 |
*/
#define UART_RS485_FRM_ERR_INT_CLR (BIT(16))
#define UART_RS485_FRM_ERR_INT_CLR_M (BIT(16))
#define UART_RS485_FRM_ERR_INT_CLR_V 0x1
#define UART_RS485_FRM_ERR_INT_CLR_S 16
/* UART_RS485_PARITY_ERR_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */
/*description: Set this bit to clear the rs485_parity_err_int_raw int... | 1,426 |
.*/
#define UART_TX_BRK_DONE_INT_CLR (BIT(12))
#define UART_TX_BRK_DONE_INT_CLR_M (BIT(12))
#define UART_TX_BRK_DONE_INT_CLR_V 0x1
#define UART_TX_BRK_DONE_INT_CLR_S 12
/* UART_GLITCH_DET_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
/*description: Set this bit to clear the glitch_det_int_raw interrupt.*/
#define U... | 1,426 |
*/
#define UART_RXFIFO_TOUT_INT_CLR (BIT(8))
#define UART_RXFIFO_TOUT_INT_CLR_M (BIT(8))
#define UART_RXFIFO_TOUT_INT_CLR_V 0x1
#define UART_RXFIFO_TOUT_INT_CLR_S 8
/* UART_BRK_DET_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
/*description: Set this bit to clear the brk_det_int_raw interrupt.*/
#define UART_BRK_DET... | 1,426 |
*/
#define UART_RXFIFO_OVF_INT_CLR (BIT(4))
#define UART_RXFIFO_OVF_INT_CLR_M (BIT(4))
#define UART_RXFIFO_OVF_INT_CLR_V 0x1
#define UART_RXFIFO_OVF_INT_CLR_S 4
/* UART_FRM_ERR_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
/*description: Set this bit to clear frm_err_int_raw interrupt.*/
#define UART_FRM_ERR_INT_CLR... | 1,426 |
*/
#define UART_RXFIFO_FULL_INT_CLR (BIT(0))
#define UART_RXFIFO_FULL_INT_CLR_M (BIT(0))
#define UART_RXFIFO_FULL_INT_CLR_V 0x1
#define UART_RXFIFO_FULL_INT_CLR_S 0
#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14)
/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */
/*description: The decimal... | 1,426 |
*/
#define UART_GLITCH_FILT 0x000000FF
#define UART_GLITCH_FILT_M ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S))
#define UART_GLITCH_FILT_V 0xFF
#define UART_GLITCH_FILT_S 0
#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1C)
/* UART_TXD : RO ;bitpos:[31] ;default: 1'h1 ; */
/*description: This bit represe... | 1,426 |
*/
#define UART_TXFIFO_CNT 0x000003FF
#define UART_TXFIFO_CNT_M ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S))
#define UART_TXFIFO_CNT_V 0x3FF
#define UART_TXFIFO_CNT_S 16
/* UART_RXD : RO ;bitpos:[15] ;default: 1'b1 ; */
/*description: This register represent the level value of the internal uart rxd signal.*/
#define... | 1,426 |
*/
#define UART_RXFIFO_CNT 0x000003FF
#define UART_RXFIFO_CNT_M ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S))
#define UART_RXFIFO_CNT_V 0x3FF
#define UART_RXFIFO_CNT_S 0
#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20)
/* UART_MEM_CLK_EN : R/W ;bitpos:[28] ;default: 1'h1 ; */
/*description: UART memory cl... | 1,426 |
1'h0: Support clock only when
application writes registers.*/
#define UART_CLK_EN (BIT(25))
#define UART_CLK_EN_M (BIT(25))
#define UART_CLK_EN_V 0x1
#define UART_CLK_EN_S 25
/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */
/*description: Set this bit to inverse the level value of uart dtr signal.*/
#define... | 1,426 |
*/
#define UART_DSR_INV (BIT(21))
#define UART_DSR_INV_M (BIT(21))
#define UART_DSR_INV_V 0x1
#define UART_DSR_INV_S 21
/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */
/*description: Set this bit to inverse the level value of uart cts signal.*/
#define UART_CTS_INV (BIT(20))
#define UART_CTS_INV_M (BIT(20)... | 1,426 |
*/
#define UART_RXFIFO_RST (BIT(17))
#define UART_RXFIFO_RST_M (BIT(17))
#define UART_RXFIFO_RST_V 0x1
#define UART_RXFIFO_RST_S 17
/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
/*description: Set this bit to enable IrDA protocol.*/
#define UART_IRDA_EN (BIT(16))
#define UART_IRDA_EN_M (BIT(16))
#define ... | 1,426 |
*/
#define UART_IRDA_RX_INV (BIT(13))
#define UART_IRDA_RX_INV_M (BIT(13))
#define UART_IRDA_RX_INV_V 0x1
#define UART_IRDA_RX_INV_S 13
/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: Set this bit to invert the level of IrDA transmitter.*/
#define UART_IRDA_TX_INV (BIT(12))
#define UART_... | 1,426 |
*/
#define UART_IRDA_DPLX (BIT(9))
#define UART_IRDA_DPLX_M (BIT(9))
#define UART_IRDA_DPLX_V 0x1
#define UART_IRDA_DPLX_S 9
/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: Set this bit to enbale transmitter to send NULL when the process
of sending data is done.*/
#define UART_TXD_BRK (BIT(8... | 1,426 |
*/
#define UART_STOP_BIT_NUM 0x00000003
#define UART_STOP_BIT_NUM_M ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S))
#define UART_STOP_BIT_NUM_V 0x3
#define UART_STOP_BIT_NUM_S 4
/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */
/*description: This register is used to set the length of data.*/
#define UART_BIT_... | 1,426 |
*/
#define UART_RX_TOUT_EN (BIT(21))
#define UART_RX_TOUT_EN_M (BIT(21))
#define UART_RX_TOUT_EN_V 0x1
#define UART_RX_TOUT_EN_S 21
/* UART_RX_FLOW_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: This is the flow enable bit for UART receiver.*/
#define UART_RX_FLOW_EN (BIT(20))
#define UART_RX_FLOW_EN_M ... | 1,426 |
*/
#define UART_TXFIFO_EMPTY_THRHD 0x000001FF
#define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S))
#define UART_TXFIFO_EMPTY_THRHD_V 0x1FF
#define UART_TXFIFO_EMPTY_THRHD_S 9
/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[8:0] ;default: 9'h60 ; */
/*description: It will produce rxf... | 1,426 |
It is used in baud rate-detect process.*/
#define UART_HIGHPULSE_MIN_CNT 0x00000FFF
#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S))
#define UART_HIGHPULSE_MIN_CNT_V 0xFFF
#define UART_HIGHPULSE_MIN_CNT_S 0
#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30)
/* ... | 1,426 |
It is cleared by hardware automatically.*/
#define UART_SEND_XON (BIT(4))
#define UART_SEND_XON_M (BIT(4))
#define UART_SEND_XON_V 0x1
#define UART_SEND_XON_S 4
/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: Set this bit to stop the transmitter from sending data.*/
#define UART_FORCE_XOFF... | 1,426 |
It is used with
register sw_xon or sw_xoff.*/
#define UART_SW_FLOW_CON_EN (BIT(0))
#define UART_SW_FLOW_CON_EN_M (BIT(0))
#define UART_SW_FLOW_CON_EN_V 0x1
#define UART_SW_FLOW_CON_EN_S 0
#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38)
/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'h... | 1,426 |
*/
#define UART_XOFF_THRESHOLD 0x000001FF
#define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S))
#define UART_XOFF_THRESHOLD_V 0x1FF
#define UART_XOFF_THRESHOLD_S 0
#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40)
/* UART_XON_CHAR : R/W ;bitpos:[16:9] ;default: 8'h11 ; */... | 1,426 |
It is active when txd_brk is set to 1.*/
#define UART_TX_BRK_NUM 0x000000FF
#define UART_TX_BRK_NUM_M ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S))
#define UART_TX_BRK_NUM_V 0xFF
#define UART_TX_BRK_NUM_S 0
#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x48)
/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;de... | 1,426 |
*/
#define UART_RS485_TX_DLY_NUM 0x0000000F
#define UART_RS485_TX_DLY_NUM_M ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S))
#define UART_RS485_TX_DLY_NUM_V 0xF
#define UART_RS485_TX_DLY_NUM_S 6
/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: This register is used to delay the re... | 1,426 |
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