text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
*/
#define UART_DL1_EN (BIT(2))
#define UART_DL1_EN_M (BIT(2))
#define UART_DL1_EN_V 0x1
#define UART_DL1_EN_S 2
/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: Set this bit to delay the stop bit by 1 bit.*/
#define UART_DL0_EN (BIT(1))
#define UART_DL0_EN_M (BIT(1))
#define UART_DL0_EN_V 0x1... | 1,426 |
*/
#define UART_POST_IDLE_NUM 0x0000FFFF
#define UART_POST_IDLE_NUM_M ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S))
#define UART_POST_IDLE_NUM_V 0xFFFF
#define UART_POST_IDLE_NUM_S 0
#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x58)
/* UART_RX_GAP_TOUT : R/W ;bitpos:[15:0] ;default: 16'd11 ;... | 1,426 |
*/
#define UART_AT_CMD_CHAR 0x000000FF
#define UART_AT_CMD_CHAR_M ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S))
#define UART_AT_CMD_CHAR_V 0xFF
#define UART_AT_CMD_CHAR_S 0
#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60)
/* UART_MEM_FORCE_PU : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: Set ... | 1,426 |
*/
#define UART_RX_TOUT_THRHD 0x000003FF
#define UART_RX_TOUT_THRHD_M ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S))
#define UART_RX_TOUT_THRHD_V 0x3FF
#define UART_RX_TOUT_THRHD_S 16
/* UART_RX_FLOW_THRHD : R/W ;bitpos:[15:7] ;default: 9'h0 ; */
/*description: This register is used to configure the maximum amoun... | 1,426 |
The default number is 128 bytes.*/
#define UART_RX_SIZE 0x00000007
#define UART_RX_SIZE_M ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S))
#define UART_RX_SIZE_V 0x7
#define UART_RX_SIZE_S 1
#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x64)
/* UART_TX_RADDR : RO ;bitpos:[20:11] ;default: 10'h0 ; */
/*descr... | 1,426 |
UART0 is 10'h100. UART1 is 10'h180.*/
#define UART_RX_WADDR 0x000003FF
#define UART_RX_WADDR_M ((UART_RX_WADDR_V)<<(UART_RX_WADDR_S))
#define UART_RX_WADDR_V 0x3FF
#define UART_RX_WADDR_S 11
/* UART_APB_RX_RADDR : RO ;bitpos:[9:0] ;default: 10'h100 ; */
/*description: This register stores the offset address in RX-... | 1,426 |
*/
#define UART_ST_URX_OUT 0x0000000F
#define UART_ST_URX_OUT_M ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S))
#define UART_ST_URX_OUT_V 0xF
#define UART_ST_URX_OUT_S 0
#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x70)
/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */
/*description: This... | 1,426 |
*/
#define UART_RX_RST_CORE (BIT(27))
#define UART_RX_RST_CORE_M (BIT(27))
#define UART_RX_RST_CORE_V 0x1
#define UART_RX_RST_CORE_S 27
/* UART_TX_RST_CORE : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: Write 1 then write 0 to this bit reset UART Tx.*/
#define UART_TX_RST_CORE (BIT(26))
#define UART_TX_RST... | 1,426 |
*/
#define UART_RST_CORE (BIT(23))
#define UART_RST_CORE_M (BIT(23))
#define UART_RST_CORE_V 0x1
#define UART_RST_CORE_S 23
/* UART_SCLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
/*description: Set this bit to enable UART Tx/Rx clock.*/
#define UART_SCLK_EN (BIT(22))
#define UART_SCLK_EN_M (BIT(22))
#define UART_... | 1,426 |
*/
#define UART_SCLK_DIV_A 0x0000003F
#define UART_SCLK_DIV_A_M ((UART_SCLK_DIV_A_V)<<(UART_SCLK_DIV_A_S))
#define UART_SCLK_DIV_A_V 0x3F
#define UART_SCLK_DIV_A_S 6
/* UART_SCLK_DIV_B : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
/*description: The denominator of the frequency divider factor.*/
#define UART_SCLK_DIV_B ... | 1,426 |
*/
#define UART_UPDATE (BIT(31))
#define UART_UPDATE_M (BIT(31))
#define UART_UPDATE_V 0x1
#define UART_UPDATE_S 31
/* UART_HIGH_SPEED : R/W ;bitpos:[30] ;default: 1'b1 ; */
/*description: This bit used to select synchronize mode. 1: Registers are auto
synchronized into UART Core clock and UART core should be keep... | 1,426 |
/*
*/
#pragma once
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
#define SOC_GDMA_TRIG_PERIPH_SPI2 (0)
#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2)
#define SOC_GDMA_TRIG_PERIPH_I2S0 (3)
#define SOC_GDMA_TRIG_PERIPH... | 1,427 |
/*
*/
#pragma once
#include "soc/interrupts.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PERIPH_LEDC_MODULE = 0,
PERIPH_UART0_MODULE,
PERIPH_UART1_MODULE,
PERIPH_USB_DEVICE_MODULE,
PERIPH_I2C0_MODULE,
PERIPH_I2S1_MODULE,
PERIPH_TIMG0_MODULE,
PERIPH_TIMG1_MODULE,
PERI... | 1,428 |
/*
*/
#ifndef __HWCRYPTO_REG_H__
#define __HWCRYPTO_REG_H__
#include "soc.h"
#include "soc/xts_aes_reg.h"
/* registers for RSA acceleration via Multiple Precision Integer ops */
#define RSA_MEM_M_BLOCK_BASE ((DR_REG_RSA_BASE)+0x000)
/* RB & Z use the same memory block, depending on phase of operation */
#d... | 1,429 |
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applic... | 1,430 |
1: close gating 0: open clock gating.*/
#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON (BIT(0))
#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M (BIT(0))
#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V 0x1
#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S 0
#define EXTMEM_ICACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x00C)
/* EXTMEM... | 1,430 |
*/
#define EXTMEM_ICACHE_LOCK_DONE (BIT(2))
#define EXTMEM_ICACHE_LOCK_DONE_M (BIT(2))
#define EXTMEM_ICACHE_LOCK_DONE_V 0x1
#define EXTMEM_ICACHE_LOCK_DONE_S 2
/* EXTMEM_ICACHE_UNLOCK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The bit is used to enable unlock operation. It will be cleared
by hardwar... | 1,430 |
It should be combined with ICACHE_LOCK_SIZE_REG.*/
#define EXTMEM_ICACHE_LOCK_ADDR 0xFFFFFFFF
#define EXTMEM_ICACHE_LOCK_ADDR_M ((EXTMEM_ICACHE_LOCK_ADDR_V)<<(EXTMEM_ICACHE_LOCK_ADDR_S))
#define EXTMEM_ICACHE_LOCK_ADDR_V 0xFFFFFFFF
#define EXTMEM_ICACHE_LOCK_ADDR_S 0
#define EXTMEM_ICACHE_LOCK_SIZE_REG (... | 1,430 |
*/
#define EXTMEM_ICACHE_SYNC_DONE (BIT(1))
#define EXTMEM_ICACHE_SYNC_DONE_M (BIT(1))
#define EXTMEM_ICACHE_SYNC_DONE_V 0x1
#define EXTMEM_ICACHE_SYNC_DONE_S 1
/* EXTMEM_ICACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: The bit is used to enable invalidate operation. It will be cleared
by... | 1,430 |
The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/
#define EXTMEM_ICACHE_SYNC_SIZE 0x007FFFFF
#define EXTMEM_ICACHE_SYNC_SIZE_M ((EXTMEM_ICACHE_SYNC_SIZE_V)<<(EXTMEM_ICACHE_SYNC_SIZE_S))
#define EXTMEM_ICACHE_SYNC_SIZE_V 0x7FFFFF
#define EXTMEM_ICACHE_SYNC_SIZE_S 0
#define... | 1,430 |
It will be cleared
by hardware after preload operation done.*/
#define EXTMEM_ICACHE_PRELOAD_ENA (BIT(0))
#define EXTMEM_ICACHE_PRELOAD_ENA_M (BIT(0))
#define EXTMEM_ICACHE_PRELOAD_ENA_V 0x1
#define EXTMEM_ICACHE_PRELOAD_ENA_S 0
#define EXTMEM_ICACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x038)
/* EXTM... | 1,430 |
The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/
#define EXTMEM_ICACHE_PRELOAD_SIZE 0x0000FFFF
#define EXTMEM_ICACHE_PRELOAD_SIZE_M ((EXTMEM_ICACHE_PRELOAD_SIZE_V)<<(EXTMEM_ICACHE_PRELOAD_SIZE_S))
#define EXTMEM_ICACHE_PRELOAD_SIZE_V 0xFFFF
#define EXTMEM_ICACHE_PRELOA... | 1,430 |
1:
descending 0: ascending.*/
#define EXTMEM_ICACHE_AUTOLOAD_ORDER (BIT(4))
#define EXTMEM_ICACHE_AUTOLOAD_ORDER_M (BIT(4))
#define EXTMEM_ICACHE_AUTOLOAD_ORDER_V 0x1
#define EXTMEM_ICACHE_AUTOLOAD_ORDER_S 4
/* EXTMEM_ICACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b1 ; */
/*description: The bit is used to ind... | 1,430 |
*/
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA (BIT(1))
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_M (BIT(1))
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_V 0x1
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_S 1
/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bits are used to enable the fir... | 1,430 |
It should be combined with icache_autoload_sct0_ena.*/
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE 0x07FFFFFF
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S))
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V 0x7FFFFFF
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_... | 1,430 |
It should be combined with icache_autoload_sct1_ena.*/
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE 0x07FFFFFF
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S))
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V 0x7FFFFFF
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_... | 1,430 |
The register is used to give constraints to ibus access counter.*/
#define EXTMEM_IBUS_TO_FLASH_END_VADDR 0xFFFFFFFF
#define EXTMEM_IBUS_TO_FLASH_END_VADDR_M ((EXTMEM_IBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_END_VADDR_S))
#define EXTMEM_IBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF
#define EXTMEM_IBUS_TO_FLASH_END_... | 1,430 |
The register is used to give constraints to dbus access counter.*/
#define EXTMEM_DBUS_TO_FLASH_END_VADDR 0xFFFFFFFF
#define EXTMEM_DBUS_TO_FLASH_END_VADDR_M ((EXTMEM_DBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_END_VADDR_S))
#define EXTMEM_DBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF
#define EXTMEM_DBUS_TO_FLASH_END_... | 1,430 |
*/
#define EXTMEM_IBUS_ACS_MISS_CNT 0xFFFFFFFF
#define EXTMEM_IBUS_ACS_MISS_CNT_M ((EXTMEM_IBUS_ACS_MISS_CNT_V)<<(EXTMEM_IBUS_ACS_MISS_CNT_S))
#define EXTMEM_IBUS_ACS_MISS_CNT_V 0xFFFFFFFF
#define EXTMEM_IBUS_ACS_MISS_CNT_S 0
#define EXTMEM_IBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x06C)
/* EXTMEM_IBUS_ACS_... | 1,430 |
*/
#define EXTMEM_DBUS_ACS_CNT 0xFFFFFFFF
#define EXTMEM_DBUS_ACS_CNT_M ((EXTMEM_DBUS_ACS_CNT_V)<<(EXTMEM_DBUS_ACS_CNT_S))
#define EXTMEM_DBUS_ACS_CNT_V 0xFFFFFFFF
#define EXTMEM_DBUS_ACS_CNT_S 0
#define EXTMEM_CACHE_ILG_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x078)
/* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W ;bitpos... | 1,430 |
*/
#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA (BIT(5))
#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M (BIT(5))
#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V 0x1
#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S 5
/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The bit is used to enable interr... | 1,430 |
*/
#define EXTMEM_DBUS_CNT_OVF_INT_CLR (BIT(8))
#define EXTMEM_DBUS_CNT_OVF_INT_CLR_M (BIT(8))
#define EXTMEM_DBUS_CNT_OVF_INT_CLR_V 0x1
#define EXTMEM_DBUS_CNT_OVF_INT_CLR_S 8
/* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[7] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt by ibus counter over... | 1,430 |
*/
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(1))
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M (BIT(1))
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x1
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S 1
/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
/*description: The... | 1,430 |
*/
#define EXTMEM_DBUS_ACS_CNT_OVF_ST (BIT(9))
#define EXTMEM_DBUS_ACS_CNT_OVF_ST_M (BIT(9))
#define EXTMEM_DBUS_ACS_CNT_OVF_ST_V 0x1
#define EXTMEM_DBUS_ACS_CNT_OVF_ST_S 9
/* EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by ibus access fla... | 1,430 |
*/
#define EXTMEM_MMU_ENTRY_FAULT_ST (BIT(5))
#define EXTMEM_MMU_ENTRY_FAULT_ST_M (BIT(5))
#define EXTMEM_MMU_ENTRY_FAULT_ST_V 0x1
#define EXTMEM_MMU_ENTRY_FAULT_ST_S 5
/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by preload configura... | 1,430 |
*/
#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA (BIT(4))
#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_M (BIT(4))
#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V 0x1
#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S 4
/* EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: The bit is used to enable ... | 1,430 |
*/
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA (BIT(0))
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_M (BIT(0))
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V 0x1
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S 0
#define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x088)
/* EXTMEM_CORE0_DBUS_... | 1,430 |
*/
#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR (BIT(3))
#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_M (BIT(3))
#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_V 0x1
#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_S 3
/* EXTMEM_CORE0_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
/*description: The bit is use... | 1,430 |
*/
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR (BIT(0))
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_M (BIT(0))
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V 0x1
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S 0
#define EXTMEM_CORE0_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x08C)
/* EXTMEM_CORE0_DBUS_W... | 1,430 |
*/
#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST (BIT(3))
#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_M (BIT(3))
#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_V 0x1
#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_S 3
/* EXTMEM_CORE0_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: The bit is used to indic... | 1,430 |
*/
#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST (BIT(0))
#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_M (BIT(0))
#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V 0x1
#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S 0
#define EXTMEM_CORE0_DBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x090)
/* EXTMEM_CORE0_DBUS_WORLD :... | 1,430 |
*/
#define EXTMEM_CORE0_DBUS_VADDR 0xFFFFFFFF
#define EXTMEM_CORE0_DBUS_VADDR_M ((EXTMEM_CORE0_DBUS_VADDR_V)<<(EXTMEM_CORE0_DBUS_VADDR_S))
#define EXTMEM_CORE0_DBUS_VADDR_V 0xFFFFFFFF
#define EXTMEM_CORE0_DBUS_VADDR_S 0
#define EXTMEM_CORE0_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x098)
/* EXTMEM_CORE0_I... | 1,430 |
*/
#define EXTMEM_CORE0_IBUS_VADDR 0xFFFFFFFF
#define EXTMEM_CORE0_IBUS_VADDR_M ((EXTMEM_CORE0_IBUS_VADDR_V)<<(EXTMEM_CORE0_IBUS_VADDR_S))
#define EXTMEM_CORE0_IBUS_VADDR_V 0xFFFFFFFF
#define EXTMEM_CORE0_IBUS_VADDR_S 0
#define EXTMEM_CACHE_MMU_FAULT_CONTENT_REG (DR_REG_EXTMEM_BASE + 0x0A0)
/* EXTMEM_CACH... | 1,430 |
.*/
#define EXTMEM_CACHE_MMU_FAULT_CONTENT 0x000003FF
#define EXTMEM_CACHE_MMU_FAULT_CONTENT_M ((EXTMEM_CACHE_MMU_FAULT_CONTENT_V)<<(EXTMEM_CACHE_MMU_FAULT_CONTENT_S))
#define EXTMEM_CACHE_MMU_FAULT_CONTENT_V 0x3FF
#define EXTMEM_CACHE_MMU_FAULT_CONTENT_S 0
#define EXTMEM_CACHE_MMU_FAULT_VADDR_REG (DR_REG... | 1,430 |
1: in idle state 0: not in idle state*/
#define EXTMEM_ICACHE_STATE 0x00000FFF
#define EXTMEM_ICACHE_STATE_M ((EXTMEM_ICACHE_STATE_V)<<(EXTMEM_ICACHE_STATE_S))
#define EXTMEM_ICACHE_STATE_V 0xFFF
#define EXTMEM_ICACHE_STATE_S 0
#define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG (DR_REG_EXTMEM_BASE... | 1,430 |
1: close gating 0: open clock gating.*/
#define EXTMEM_CLK_FORCE_ON_CRYPT (BIT(2))
#define EXTMEM_CLK_FORCE_ON_CRYPT_M (BIT(2))
#define EXTMEM_CLK_FORCE_ON_CRYPT_V 0x1
#define EXTMEM_CLK_FORCE_ON_CRYPT_S 2
/* EXTMEM_CLK_FORCE_ON_AUTO_CRYPT : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: The bit is used to cl... | 1,430 |
*/
#define EXTMEM_ICACHE_PRELOAD_INT_CLR (BIT(2))
#define EXTMEM_ICACHE_PRELOAD_INT_CLR_M (BIT(2))
#define EXTMEM_ICACHE_PRELOAD_INT_CLR_V 0x1
#define EXTMEM_ICACHE_PRELOAD_INT_CLR_S 2
/* EXTMEM_ICACHE_PRELOAD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The bit is used to enable the interrupt by i... | 1,430 |
*/
#define EXTMEM_ICACHE_SYNC_INT_CLR (BIT(2))
#define EXTMEM_ICACHE_SYNC_INT_CLR_M (BIT(2))
#define EXTMEM_ICACHE_SYNC_INT_CLR_V 0x1
#define EXTMEM_ICACHE_SYNC_INT_CLR_S 2
/* EXTMEM_ICACHE_SYNC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The bit is used to enable the interrupt by icache sync done... | 1,430 |
bit0/bit2: ibus bit1/bit3: dbus*/
#define EXTMEM_CACHE_MMU_OWNER 0x0000000F
#define EXTMEM_CACHE_MMU_OWNER_M ((EXTMEM_CACHE_MMU_OWNER_V)<<(EXTMEM_CACHE_MMU_OWNER_S))
#define EXTMEM_CACHE_MMU_OWNER_V 0xF
#define EXTMEM_CACHE_MMU_OWNER_S 0
#define EXTMEM_CACHE_CONF_MISC_REG (DR_REG_EXTMEM_BASE + 0x0C8)
/* ... | 1,430 |
*/
#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT (BIT(0))
#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M (BIT(0))
#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V 0x1
#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S 0
#define EXTMEM_ICACHE_FREEZE_REG (DR_REG_EXTMEM_BASE + 0x0CC)
/* ... | 1,430 |
In this case sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/
#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA (BIT(0))
#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_M (BIT(0))
#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V 0x1
#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S... | 1,430 |
*/
#define EXTMEM_CLK_EN (BIT(0))
#define EXTMEM_CLK_EN_M (BIT(0))
#define EXTMEM_CLK_EN_V 0x1
#define EXTMEM_CLK_EN_S 0
#define EXTMEM_DATE_REG (DR_REG_EXTMEM_BASE + 0x3FC)
/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007160 ; */
/*description: Reserved.*/
#define EXTMEM_DATE 0x0FFFFFFF
#define EX... | 1,430 |
/*
*/
#pragma once
/**
*/
#define I2C_SAR_ADC 0X69
#define I2C_SAR_ADC_HOSTID 0
#define ADC_SAR1_ENCAL_GND_ADDR 0x7
#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
#define ADC_SAR2_ENCAL_GND_ADDR 0x7
#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
#define ADC_SAR2_ENCAL_GND_ADDR_... | 1,431 |
/*
*/
#pragma once
#include
#include "soc/ext_mem_defs.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Defined for flash mmap */
#define SOC_MMU_REGIONS_COUNT 1
#define SOC_MMU_PAGES_PER_REGION 128
#define SOC_MMU_IROM0_PAGES_START (CACHE_IROM_MMU_ST... | 1,432 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef struct rmt_dev_t {
volatile uint32_t data_ch[4];
volatile union {
struct {
uint32_t tx_start: 1;
uint32_t mem_rd_rst: 1;
uint32_t mem_rst: 1;
uint3... | 1,433 |
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applic... | 1,436 |
/*
*/
#pragma once
/**
*/
#define I2C_DIG_REG 0x6D
#define I2C_DIG_REG_HOSTID 0
#define I2C_DIG_REG_EXT_RTC_DREG 4
#define I2C_DIG_REG_EXT_RTC_DREG_MSB 4
#define I2C_DIG_REG_EXT_RTC_DREG_LSB 0
#define I2C_DIG_REG_ENX_RTC_DREG 4
#define I2C_DIG_REG_ENX_RTC_DREG_MSB 7
#define I2C_DIG_REG_ENX_RTC_DRE... | 1,437 |
/*
*/
#ifndef _SOC_IO_MUX_REG_H_
#define _SOC_IO_MUX_REG_H_
#include "soc.h"
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
/* Output enable in sleep mode */
#define SLP_OE (BIT(0))
#define SLP_OE_M (BIT(0))
#define SLP_OE_V 1
#define SLP_OE_S 0
/* Pin used for wakeup from sleep */
#define S... | 1,438 |
*/
#define PIN_FUNC_GPIO 1
#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_R... | 1,438 |
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 1,439 |
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applic... | 1,440 |
1: enable 0: disable.*/
#define SPI_MEM_FLASH_READ (BIT(31))
#define SPI_MEM_FLASH_READ_M (BIT(31))
#define SPI_MEM_FLASH_READ_V 0x1
#define SPI_MEM_FLASH_READ_S 31
/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */
/*description: Write flash enable. Write enable command will be sent when the
bit is... | 1,440 |
Read ID command will be sent when the bit is
set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
#define SPI_MEM_FLASH_RDID (BIT(28))
#define SPI_MEM_FLASH_RDID_M (BIT(28))
#define SPI_MEM_FLASH_RDID_V 0x1
#define SPI_MEM_FLASH_RDID_S 28
/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;defau... | 1,440 |
Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
#define SPI_MEM_FLASH_PP (BIT(25))
#define SPI_MEM_FLASH_PP_M (BIT(25))
#define SPI_MEM_FLASH_PP_V 0x1
#define SPI_MEM_FLASH_PP_S 25
/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;de... | 1,440 |
Chip erase operation will be triggered when
the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
#define SPI_MEM_FLASH_CE (BIT(22))
#define SPI_MEM_FLASH_CE_M (BIT(22))
#define SPI_MEM_FLASH_CE_V 0x1
#define SPI_MEM_FLASH_CE_S 22
/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;defaul... | 1,440 |
The bit will be cleared
once the operation done.1: enable 0: disable.*/
#define SPI_MEM_FLASH_HPM (BIT(19))
#define SPI_MEM_FLASH_HPM_M (BIT(19))
#define SPI_MEM_FLASH_HPM_V 0x1
#define SPI_MEM_FLASH_HPM_S 19
/* SPI_MEM_USR : R/W/SC ;bitpos:[18] ;default: 1'b0 ; */
/*description: User define command enable. An ... | 1,440 |
0: idle state
1: preparation state 2: send command state 3: send address state 4: wait state 5: read data state 6:write data state 7: done state 8: read data end state.*/
#define SPI_MEM_SLV_ST 0x0000000F
#define SPI_MEM_SLV_ST_M ((SPI_MEM_SLV_ST_V)<<(SPI_MEM_SLV_ST_S))
#define SPI_MEM_SLV_ST_V 0xF
#define... | 1,440 |
1: enable 0: disable.*/
#define SPI_MEM_FREAD_QIO (BIT(24))
#define SPI_MEM_FREAD_QIO_M (BIT(24))
#define SPI_MEM_FREAD_QIO_V 0x1
#define SPI_MEM_FREAD_QIO_S 24
/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
/*description: In the read operations address phase and read-data phase apply
2 signals. 1: e... | 1,440 |
1: enable 0: disable.*/
#define SPI_MEM_FREAD_QUAD (BIT(20))
#define SPI_MEM_FREAD_QUAD_M (BIT(20))
#define SPI_MEM_FREAD_QUAD_V 0x1
#define SPI_MEM_FREAD_QUAD_S 20
/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
/*description: The bit is used to set MOSI line polarity 1: high 0 low*/
#define SPI_MEM_D_P... | 1,440 |
1: enable 0: disable.*/
#define SPI_MEM_FREAD_DUAL (BIT(14))
#define SPI_MEM_FREAD_DUAL_M (BIT(14))
#define SPI_MEM_FREAD_DUAL_V 0x1
#define SPI_MEM_FREAD_DUAL_S 14
/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
/*description: This bit enable the bits: spi_mem_fread_qio spi_mem_fread_dio
spi_mem_... | 1,440 |
*/
#define SPI_MEM_FDUMMY_OUT (BIT(3))
#define SPI_MEM_FDUMMY_OUT_M (BIT(3))
#define SPI_MEM_FDUMMY_OUT_V 0x1
#define SPI_MEM_FDUMMY_OUT_S 3
#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0x00C)
/* SPI_MEM_RXFIFO_WFULL_ERR : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: 1: SPI0 RX FIFO write ful... | 1,440 |
0: SPI clock is off when CS inactive 1:
SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
#define SPI_MEM_CLK_MODE 0x00000003
#define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
#define SPI_MEM_CLK_MODE_V 0x3
#defi... | 1,440 |
*/
#define SPI_MEM_CS_HOLD_TIME 0x0000001F
#define SPI_MEM_CS_HOLD_TIME_M ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S))
#define SPI_MEM_CS_HOLD_TIME_V 0x1F
#define SPI_MEM_CS_HOLD_TIME_S 5
/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */
/*description: (cycles-1) of prepare phase by spi clock... | 1,440 |
So spi_mem_clk
frequency is system/(spi_mem_clkcnt_N+1)*/
#define SPI_MEM_CLKCNT_N 0x000000FF
#define SPI_MEM_CLKCNT_N_M ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S))
#define SPI_MEM_CLKCNT_N_V 0xFF
#define SPI_MEM_CLKCNT_N_S 16
/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
/*description: In the mas... | 1,440 |
*/
#define SPI_MEM_USR_COMMAND (BIT(31))
#define SPI_MEM_USR_COMMAND_M (BIT(31))
#define SPI_MEM_USR_COMMAND_V 0x1
#define SPI_MEM_USR_COMMAND_S 31
/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: This bit enable the address phase of an operation.*/
#define SPI_MEM_USR_ADDR (BIT(30))
#defi... | 1,440 |
*/
#define SPI_MEM_USR_MOSI (BIT(27))
#define SPI_MEM_USR_MOSI_M (BIT(27))
#define SPI_MEM_USR_MOSI_V 0x1
#define SPI_MEM_USR_MOSI_S 27
/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: spi clock is disable in dummy phase when the bit is enable.*/
#define SPI_MEM_USR_DUMMY_IDLE (BIT(2... | 1,440 |
*/
#define SPI_MEM_FWRITE_QIO (BIT(15))
#define SPI_MEM_FWRITE_QIO_M (BIT(15))
#define SPI_MEM_FWRITE_QIO_V 0x1
#define SPI_MEM_FWRITE_QIO_S 15
/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: In the write operations address phase and read-data phase apply 2 signals.*/
#define SPI_MEM_FWR... | 1,440 |
*/
#define SPI_MEM_CK_OUT_EDGE (BIT(9))
#define SPI_MEM_CK_OUT_EDGE_M (BIT(9))
#define SPI_MEM_CK_OUT_EDGE_V 0x1
#define SPI_MEM_CK_OUT_EDGE_S 9
/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/
#define SPI_MEM_CS_SETUP ... | 1,440 |
The register
value shall be (cycle_num-1).*/
#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003F
#define SPI_MEM_USR_DUMMY_CYCLELEN_M ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S))
#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x3F
#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0
#define SPI_MEM_USER2_REG(i) (... | 1,440 |
The register value shall be (bit_num-1).*/
#define SPI_MEM_USR_MOSI_DBITLEN 0x000003FF
#define SPI_MEM_USR_MOSI_DBITLEN_M ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S))
#define SPI_MEM_USR_MOSI_DBITLEN_V 0x3FF
#define SPI_MEM_USR_MOSI_DBITLEN_S 0
#define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI_ME... | 1,440 |
*/
#define SPI_MEM_STATUS 0x0000FFFF
#define SPI_MEM_STATUS_M ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S))
#define SPI_MEM_STATUS_V 0xFFFF
#define SPI_MEM_STATUS_S 0
#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x034)
/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: spi cs... | 1,440 |
*/
#define SPI_MEM_SLV_ST_TRANS_END (BIT(5))
#define SPI_MEM_SLV_ST_TRANS_END_M (BIT(5))
#define SPI_MEM_SLV_ST_TRANS_END_V 0x1
#define SPI_MEM_SLV_ST_TRANS_END_S 5
/* SPI_MEM_CSPI_ST_TRANS_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is used to enable the interrupt of SPI0 cspi_st contr... | 1,440 |
*/
#define SPI_MEM_TRANS_END_INT_ENA (BIT(2))
#define SPI_MEM_TRANS_END_INT_ENA_M (BIT(2))
#define SPI_MEM_TRANS_END_INT_ENA_V 0x1
#define SPI_MEM_TRANS_END_INT_ENA_S 2
/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: SPI_CS1 pin enable 1: disable SPI_CS1 0: SPI_CS1 pin is active
to select... | 1,440 |
*/
#define SPI_MEM_TX_CRC_DATA 0xFFFFFFFF
#define SPI_MEM_TX_CRC_DATA_M ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S))
#define SPI_MEM_TX_CRC_DATA_V 0xFFFFFFFF
#define SPI_MEM_TX_CRC_DATA_S 0
#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x03C)
/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;defa... | 1,440 |
1: enable 0: disable. The
bit is the same with spi_mem_fread_qio.*/
#define SPI_MEM_FDIN_QUAD (BIT(6))
#define SPI_MEM_FDIN_QUAD_M (BIT(6))
#define SPI_MEM_FDIN_QUAD_V 0x1
#define SPI_MEM_FDIN_QUAD_S 6
/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: For SPI1 address phase apply 2 sign... | 1,440 |
*/
#define SPI_MEM_FDIN_DUAL (BIT(3))
#define SPI_MEM_FDIN_DUAL_M (BIT(3))
#define SPI_MEM_FDIN_DUAL_V 0x1
#define SPI_MEM_FDIN_DUAL_S 3
/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: For SPI0 cache read flash for user define command 1: enable 0:disable.*/
#define SPI_MEM_C... | 1,440 |
*/
#define SPI_MEM_CSPI_LOCK_DELAY_TIME 0x0000001F
#define SPI_MEM_CSPI_LOCK_DELAY_TIME_M ((SPI_MEM_CSPI_LOCK_DELAY_TIME_V)<<(SPI_MEM_CSPI_LOCK_DELAY_TIME_S))
#define SPI_MEM_CSPI_LOCK_DELAY_TIME_V 0x1F
#define SPI_MEM_CSPI_LOCK_DELAY_TIME_S 7
/* SPI_MEM_EM_ST : RO ;bitpos:[6:4] ;default: 3'h0 ; */
/*description: T... | 1,440 |
*/
#define SPI_MEM_WAITI_DUMMY_CYCLELEN 0x0000003F
#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S))
#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V 0x3F
#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S 10
/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[9:2] ;default: 8'h05 ; */
/*descrip... | 1,440 |
*/
#define SPI_MEM_SUS_TIMEOUT_CNT 0x0000007F
#define SPI_MEM_SUS_TIMEOUT_CNT_M ((SPI_MEM_SUS_TIMEOUT_CNT_V)<<(SPI_MEM_SUS_TIMEOUT_CNT_S))
#define SPI_MEM_SUS_TIMEOUT_CNT_V 0x7F
#define SPI_MEM_SUS_TIMEOUT_CNT_S 25
/* SPI_MEM_PES_END_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: 1: Both WIP and SUS/SUS1/... | 1,440 |
0: Read one byte when check flash SUS/SUS1/SUS2 status bit*/
#define SPI_MEM_FMEM_RD_SUS_2B (BIT(22))
#define SPI_MEM_FMEM_RD_SUS_2B_M (BIT(22))
#define SPI_MEM_FMEM_RD_SUS_2B_V 0x1
#define SPI_MEM_FMEM_RD_SUS_2B_S 22
/* SPI_MEM_PESR_END_MSK : R/W ;bitpos:[21:6] ;default: 16'h80 ; */
/*description: The mask valu... | 1,440 |
If this bit is 0 application should send PER after PES is done.*/
#define SPI_MEM_PES_PER_EN (BIT(4))
#define SPI_MEM_PES_PER_EN_M (BIT(4))
#define SPI_MEM_PES_PER_EN_V 0x1
#define SPI_MEM_PES_PER_EN_S 4
/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: Set this bit to enable SPI1... | 1,440 |
The bit will be cleared once the operation done.1: enable 0: disable.*/
#define SPI_MEM_FLASH_PES (BIT(1))
#define SPI_MEM_FLASH_PES_M (BIT(1))
#define SPI_MEM_FLASH_PES_V 0x1
#define SPI_MEM_FLASH_PES_S 1
/* SPI_MEM_FLASH_PER : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
/*description: program erase resume bit progra... | 1,440 |
*/
#define SPI_MEM_FLASH_PES_COMMAND 0x000000FF
#define SPI_MEM_FLASH_PES_COMMAND_M ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S))
#define SPI_MEM_FLASH_PES_COMMAND_V 0xFF
#define SPI_MEM_FLASH_PES_COMMAND_S 8
/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[7:0] ;default: 8'h7a ; */
/*description: Progr... | 1,440 |
1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0]
#define SPI_MEM_FLASH_PES_DLY_128 (BIT(6))
#define SPI_MEM_FLASH_PES_DLY_128_M (BIT(6))
#define SPI_MEM_FLASH_PES_DLY_128_V 0x1
#define SPI_MEM_FLASH_PES_DLY_128_S 6
/* SPI_MEM_FLASH_PER_DLY_128 : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: Valid when SPI_MEM_FL... | 1,440 |
0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/
#define SPI_MEM_FLASH_RES_DLY_128 (BIT(3))
#define SPI_MEM_FLASH_RES_DLY_128_M (BIT(3))
#define SPI_MEM_FLASH_RES_DLY_128_V 0x1
#define SPI_MEM_FLASH_RES_DLY_128_S 3
/* SPI_MEM_FLASH_HPM_DLY_128 : R/W ;bitpos:[2] ;defaul... | 1,440 |
*/
#define SPI_MEM_FLASH_SUS (BIT(0))
#define SPI_MEM_FLASH_SUS_M (BIT(0))
#define SPI_MEM_FLASH_SUS_V 0x1
#define SPI_MEM_FLASH_SUS_S 0
#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x0A8)
/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
/*description: add extra dummy s... | 1,440 |
*/
#define SPI_MEM_TIMING_CLK_ENA (BIT(0))
#define SPI_MEM_TIMING_CLK_ENA_M (BIT(0))
#define SPI_MEM_TIMING_CLK_ENA_V 0x1
#define SPI_MEM_TIMING_CLK_ENA_S 0
#define SPI_MEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0AC)
/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
/*description: the input s... | 1,440 |
..*/
#define SPI_MEM_DIN3_NUM 0x00000003
#define SPI_MEM_DIN3_NUM_M ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S))
#define SPI_MEM_DIN3_NUM_V 0x3
#define SPI_MEM_DIN3_NUM_S 6
/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
/*description: the input signals are delayed by system clock cycles 0: delayed
by... | 1,440 |
..*/
#define SPI_MEM_DIN0_NUM 0x00000003
#define SPI_MEM_DIN0_NUM_M ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S))
#define SPI_MEM_DIN0_NUM_V 0x3
#define SPI_MEM_DIN0_NUM_S 0
#define SPI_MEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0B4)
/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
/*descript... | 1,440 |
*/
#define SPI_MEM_MST_ST_END_INT_ENA (BIT(4))
#define SPI_MEM_MST_ST_END_INT_ENA_M (BIT(4))
#define SPI_MEM_MST_ST_END_INT_ENA_V 0x1
#define SPI_MEM_MST_ST_END_INT_ENA_S 4
/* SPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
#defi... | 1,440 |
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