text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
0:even 1:odd*/
#define UART_PARITY (BIT(0))
#define UART_PARITY_M (BIT(0))
#define UART_PARITY_V 0x1
#define UART_PARITY_S 0
#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
/* UART_RX_TOUT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: This is the enble bit for uart receiver's timeout func... | 1,560 |
receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/
#define UART_RX_FLOW_THRHD 0x0000007F
#define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S))
#define UART_RX_FLOW_THRHD_V 0x7F
#define UART_RX_FLOW_THRHD_S 16
/... | 1,560 |
the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/
#define UART_RXFIFO_FULL_THRHD 0x0000007F
#define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S))
#define UART_RXFIFO_FULL_THRHD_V 0x7F
#define UART_RXFIFO_FULL_THRHD_S 0
#define UART_LOWPULSE_REG(i) (REG_UART... | 1,560 |
*/
#define UART_HIGHPULSE_MIN_CNT 0x000FFFFF
#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S))
#define UART_HIGHPULSE_MIN_CNT_V 0xFFFFF
#define UART_HIGHPULSE_MIN_CNT_S 0
#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30)
/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;... | 1,560 |
it is cleared by hardware automatically.*/
#define UART_SEND_XON (BIT(4))
#define UART_SEND_XON_M (BIT(4))
#define UART_SEND_XON_V 0x1
#define UART_SEND_XON_S 4
/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: Set this bit to set ctsn to enable the transmitter to go on sending data.*/
#defin... | 1,560 |
it is used with
register sw_xon or sw_xoff .*/
#define UART_SW_FLOW_CON_EN (BIT(0))
#define UART_SW_FLOW_CON_EN_M (BIT(0))
#define UART_SW_FLOW_CON_EN_V 0x1
#define UART_SW_FLOW_CON_EN_S 0
#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38)
/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'... | 1,560 |
*/
#define UART_XON_CHAR 0x000000FF
#define UART_XON_CHAR_M ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S))
#define UART_XON_CHAR_V 0xFF
#define UART_XON_CHAR_S 16
/* UART_XOFF_THRESHOLD : R/W ;bitpos:[15:8] ;default: 8'he0 ; */
/*description: When the data amount in receiver's fifo is less than this register
value. it wil... | 1,560 |
it is active when txd_brk is set to 1.*/
#define UART_TX_BRK_NUM 0x000000FF
#define UART_TX_BRK_NUM_M ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S))
#define UART_TX_BRK_NUM_V 0xFF
#define UART_TX_BRK_NUM_S 20
/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */
/*description: This register is used to confi... | 1,560 |
*/
#define UART_RS485_TX_DLY_NUM 0x0000000F
#define UART_RS485_TX_DLY_NUM_M ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S))
#define UART_RS485_TX_DLY_NUM_V 0xF
#define UART_RS485_TX_DLY_NUM_S 6
/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: This register is used to delay the re... | 1,560 |
*/
#define UART_RS485TX_RX_EN (BIT(3))
#define UART_RS485TX_RX_EN_M (BIT(3))
#define UART_RS485TX_RX_EN_V 0x1
#define UART_RS485TX_RX_EN_S 3
/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set this bit to delay the stop bit by 1 bit.*/
#define UART_DL1_EN (BIT(2))
#define UART_DL1_EN_M (BIT(2)... | 1,560 |
when the the duration is less than this register value it will not take the next data received as at_cmd char.*/
#define UART_PRE_IDLE_NUM 0x00FFFFFF
#define UART_PRE_IDLE_NUM_M ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S))
#define UART_PRE_IDLE_NUM_V 0xFFFFFF
#define UART_PRE_IDLE_NUM_S 0
#define UART_AT_CMD_PO... | 1,560 |
when the duration time is less than this register value it will not take the datas as continous at_cmd chars.*/
#define UART_RX_GAP_TOUT 0x00FFFFFF
#define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S))
#define UART_RX_GAP_TOUT_V 0xFFFFFF
#define UART_RX_GAP_TOUT_S 0
#define UART_AT_CMD_CHAR_REG(... | 1,560 |
*/
#define UART_TX_MEM_EMPTY_THRHD 0x00000007
#define UART_TX_MEM_EMPTY_THRHD_M ((UART_TX_MEM_EMPTY_THRHD_V)<<(UART_TX_MEM_EMPTY_THRHD_S))
#define UART_TX_MEM_EMPTY_THRHD_V 0x7
#define UART_TX_MEM_EMPTY_THRHD_S 28
/* UART_RX_MEM_FULL_THRHD : R/W ;bitpos:[27:25] ;default: 3'h0 ; */
/*description: refer to the rxfifo... | 1,560 |
*/
#define UART_XON_THRESHOLD_H2 0x00000003
#define UART_XON_THRESHOLD_H2_M ((UART_XON_THRESHOLD_H2_V)<<(UART_XON_THRESHOLD_H2_S))
#define UART_XON_THRESHOLD_H2_V 0x3
#define UART_XON_THRESHOLD_H2_S 21
/* UART_RX_TOUT_THRHD_H3 : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
/*description: refer to the rx_tout_thrhd's des... | 1,560 |
the default byte num is 128.*/
#define UART_TX_SIZE 0x0000000F
#define UART_TX_SIZE_M ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S))
#define UART_TX_SIZE_V 0xF
#define UART_TX_SIZE_S 7
/* UART_RX_SIZE : R/W ;bitpos:[6:3] ;default: 4'h1 ; */
/*description: This register is used to configure the amount of mem allocated
to rec... | 1,560 |
*/
#define UART_TX_MEM_CNT 0x00000007
#define UART_TX_MEM_CNT_M ((UART_TX_MEM_CNT_V)<<(UART_TX_MEM_CNT_S))
#define UART_TX_MEM_CNT_V 0x7
#define UART_TX_MEM_CNT_S 3
/* UART_RX_MEM_CNT : RO ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: refer to the rxfifo_cnt's describtion.*/
#define UART_RX_MEM_CNT 0x00000007
#... | 1,560 |
it is used
in boudrate-detect process.*/
#define UART_NEGEDGE_MIN_CNT 0x000FFFFF
#define UART_NEGEDGE_MIN_CNT_M ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S))
#define UART_NEGEDGE_MIN_CNT_V 0xFFFFF
#define UART_NEGEDGE_MIN_CNT_S 0
#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x78)
/* UART_DATE : R... | 1,560 |
/*
*/
// ESP32 doesn't feature General DMA peripheral.
// We keep this file here only for consistency's sake.
| 1,561 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PERIPH_LEDC_MODULE = 0,
PERIPH_UART0_MODULE,
PERIPH_UART1_MODULE,
PERIPH_UART2_MODULE,
PERIPH_I2C0_MODULE,
PERIPH_I2C1_MODULE,
PERIPH_I2S0_MODULE,
PERIPH_I2S1_MODULE,
PERIPH_TIMG0_MODULE,
PERIPH_TIMG1_MO... | 1,562 |
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 1,563 |
/*
*/
#pragma once
#include
#include "soc/dport_reg.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Defined for flash mmap */
#define SOC_MMU_REGIONS_COUNT 4
#define SOC_MMU_PAGES_PER_REGION 64
#define SOC_MMU_IROM0_PAGES_START 64
#define SOC_MMU_IR... | 1,564 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef struct rmt_dev_t {
volatile uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access.
Note that in some circumstances, data read from the ... | 1,565 |
*/
uint32_t carrier_en: 1; /*This is the carrier modulation enable control bit for channel0-7.*/
uint32_t carrier_out_lv: 1; /*This bit is used to configure the way carrier wave is modulated for channel0-7.1'b1:transmit on low output level 1'b0:transmit on ... | 1,565 |
*/
uint32_t mem_rd_rst: 1; /*Set this bit to reset read ram address for channel0-7 by transmitter access.*/
uint32_t apb_mem_rst: 1; /*Set this bit to reset W/R ram address for channel0-7 by apb fifo access (using fifo is discouraged, please see the note ab... | 1,565 |
*/
uint32_t ref_always_on: 1; /*This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/
uint32_t idle_out_lv: 1; /*This bit configures the output signal's level for channel0-7 in IDLE state.*/
uint32_t idle_out_en: 1; ... | 1,565 |
*/
uint32_t ch0_err: 1; /*The interrupt raw bit for channel 0 turns to high level when channel 0 detects some errors.*/
uint32_t ch1_tx_end: 1; /*The interrupt raw bit for channel 1 turns to high level when the transmit process is done.*/
ui... | 1,565 |
*/
uint32_t ch3_tx_end: 1; /*The interrupt raw bit for channel 3 turns to high level when the transmit process is done.*/
uint32_t ch3_rx_end: 1; /*The interrupt raw bit for channel 3 turns to high level when the receive process is done.*/
uint... | 1,565 |
*/
uint32_t ch5_rx_end: 1; /*The interrupt raw bit for channel 5 turns to high level when the receive process is done.*/
uint32_t ch5_err: 1; /*The interrupt raw bit for channel 5 turns to high level when channel 5 detects some errors.*/
uin... | 1,565 |
*/
uint32_t ch7_err: 1; /*The interrupt raw bit for channel 7 turns to high level when channel 7 detects some errors.*/
uint32_t ch0_tx_thr_event: 1; /*The interrupt raw bit for channel 0 turns to high level when transmitter in channel0 have send data more t... | 1,565 |
*/
uint32_t ch4_tx_thr_event: 1; /*The interrupt raw bit for channel 4 turns to high level when transmitter in channel4 have send data more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old data with new data.*/
uint32_t ch5_tx_thr_event: 1; ... | 1,565 |
*/
};
uint32_t val;
} int_raw;
volatile union {
struct {
uint32_t ch0_tx_end: 1; /*The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.*/
uint32_t ch0_rx_end: 1; /*The inte... | 1,565 |
*/
uint32_t ch2_tx_end: 1; /*The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw when mt_ch2_tx_end_int_ena is set to 1.*/
uint32_t ch2_rx_end: 1; /*The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw when rmt_ch2_rx_end_int_ena i... | 1,565 |
*/
uint32_t ch4_rx_end: 1; /*The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw when rmt_ch4_rx_end_int_ena is set to 1.*/
uint32_t ch4_err: 1; /*The interrupt state bit for channel 4's rmt_ch4_err_int_raw when rmt_ch4_err_int_ena is s... | 1,565 |
*/
uint32_t ch6_err: 1; /*The interrupt state bit for channel 6's rmt_ch6_err_int_raw when rmt_ch6_err_int_ena is set to 1.*/
uint32_t ch7_tx_end: 1; /*The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw when mt_ch7_tx_end_int_ena is set ... | 1,565 |
*/
uint32_t ch2_tx_thr_event: 1; /*The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw when mt_ch2_tx_thr_event_int_ena is set to 1.*/
uint32_t ch3_tx_thr_event: 1; /*The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw when mt_ch3... | 1,565 |
*/
};
uint32_t val;
} int_st;
volatile union {
struct {
uint32_t ch0_tx_end: 1; /*Set this bit to enable rmt_ch0_tx_end_int_st.*/
uint32_t ch0_rx_end: 1; /*Set this bit to enable rmt_ch0_rx_end_int_st.*/
uint32_t... | 1,565 |
*/
uint32_t ch3_tx_end: 1; /*Set this bit to enable rmt_ch3_tx_end_int_st.*/
uint32_t ch3_rx_end: 1; /*Set this bit to enable rmt_ch3_rx_end_int_st.*/
uint32_t ch3_err: 1; /*Set this bit to enable rmt_ch3_err_int_st.*/
... | 1,565 |
*/
uint32_t ch6_rx_end: 1; /*Set this bit to enable rmt_ch6_rx_end_int_st.*/
uint32_t ch6_err: 1; /*Set this bit to enable rmt_ch6_err_int_st.*/
uint32_t ch7_tx_end: 1; /*Set this bit to enable rmt_ch7_tx_end_int_st.*/
... | 1,565 |
*/
uint32_t ch5_tx_thr_event: 1; /*Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/
uint32_t ch6_tx_thr_event: 1; /*Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/
uint32_t ch7_tx_thr_event: 1; /*Set this bit to enable rmt_ch7_tx_t... | 1,565 |
*/
uint32_t ch2_tx_end: 1; /*Set this bit to clear the rmt_ch2_rx_end_int_raw..*/
uint32_t ch2_rx_end: 1; /*Set this bit to clear the rmt_ch2_tx_end_int_raw.*/
uint32_t ch2_err: 1; /*Set this bit to clear the rmt_ch2_err... | 1,565 |
.*/
uint32_t ch5_rx_end: 1; /*Set this bit to clear the rmt_ch5_tx_end_int_raw.*/
uint32_t ch5_err: 1; /*Set this bit to clear the rmt_ch5_err_int_raw.*/
uint32_t ch6_tx_end: 1; /*Set this bit to clear the rmt_ch6_rx_end... | 1,565 |
*/
uint32_t ch1_tx_thr_event: 1; /*Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/
uint32_t ch2_tx_thr_event: 1; /*Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/
uint32_t ch3_tx_thr_event: 1; /*Set t... | 1,565 |
*/
uint32_t high: 16; /*This register is used to configure carrier wave's high level value for channel0-7.*/
};
uint32_t val;
} carrier_duty_ch[8];
volatile union {
struct {
uint32_t limit: 9; /*When channel0-7 sen... | 1,565 |
*/
} rmt_dev_t;
extern rmt_dev_t RMT;
#ifdef __cplusplus
}
#endif
| 1,565 |
/**
*/
#pragma once
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + i*0x1000)
#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000)
/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: When set timer 0 time-base counter i... | 1,566 |
*/
#define TIMG_T0_DIVIDER 0x0000FFFF
#define TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S))
#define TIMG_T0_DIVIDER_V 0xFFFF
#define TIMG_T0_DIVIDER_S 13
/* TIMG_T0_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
/*description: When set edge type interrupt will be generated during alarm*/
#define... | 1,566 |
*/
#define TIMG_T0_LO 0xFFFFFFFF
#define TIMG_T0_LO_M ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S))
#define TIMG_T0_LO_V 0xFFFFFFFF
#define TIMG_T0_LO_S 0
#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008)
/* TIMG_T0_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Register to store timer 0 time-base count... | 1,566 |
When cleared timer
1 time-base counter decrement.*/
#define TIMG_T1_INCREASE (BIT(30))
#define TIMG_T1_INCREASE_M (BIT(30))
#define TIMG_T1_INCREASE_V 0x1
#define TIMG_T1_INCREASE_S 30
/* TIMG_T1_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
/*description: When set timer 1 auto-reload at alarming is enabled*... | 1,566 |
*/
#define TIMG_T1_LO 0xFFFFFFFF
#define TIMG_T1_LO_M ((TIMG_T1_LO_V)<<(TIMG_T1_LO_S))
#define TIMG_T1_LO_V 0xFFFFFFFF
#define TIMG_T1_LO_S 0
#define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x002c)
/* TIMG_T1_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Register to store timer 1 time-base count... | 1,566 |
0: off 1: interrupt 2: reset CPU 3: reset system*/
#define TIMG_WDT_STG0 0x00000003
#define TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S))
#define TIMG_WDT_STG0_V 0x3
#define TIMG_WDT_STG0_S 29
/* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 1'd0 ; */
/*description: Stage 1 configuration. 0: off 1: in... | 1,566 |
0: 100ns 1: 200ns 2: 300ns
3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/
#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007
#define TIMG_WDT_CPU_RESET_LENGTH_M ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S))
#define TIMG_WDT_CPU_RESET_LENGTH_V 0x7
#define TIMG_WDT_CPU_RESET_LENGTH_S 18
/* TIMG_WDT... | 1,566 |
Period = 12.5ns * value stored in this register*/
#define TIMG_WDT_CLK_PRESCALE 0x0000FFFF
#define TIMG_WDT_CLK_PRESCALE_M ((TIMG_WDT_CLK_PRESCALE_V)<<(TIMG_WDT_CLK_PRESCALE_S))
#define TIMG_WDT_CLK_PRESCALE_V 0xFFFF
#define TIMG_WDT_CLK_PRESCALE_S 16
#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x... | 1,566 |
/*
*/
#ifndef _SOC_APB_CTRL_REG_H_
#define _SOC_APB_CTRL_REG_H_
#warning "apb_ctrl_reg is deprecated due to duplicated with syscon_reg, please use syscon_reg instead, they are same"
#include "soc.h"
#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0)
/* APB_CTRL_QUICK_CLK_CHNG : R/W ;bitpos:[13] ;... | 1,567 |
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applic... | 1,569 |
/*
*/
#pragma once
/**
*/
#define I2C_APLL 0X6D
#define I2C_APLL_HOSTID 3
#define I2C_APLL_IR_CAL_DELAY 0
#define I2C_APLL_IR_CAL_DELAY_MSB 3
#define I2C_APLL_IR_CAL_DELAY_LSB 0
#define I2C_APLL_IR_CAL_RSTB 0
#define I2C_APLL_IR_CAL_RSTB_MSB 4
#define I2C_APLL_IR_CAL_RSTB_LS... | 1,570 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
typedef struct emac_mac_dev_s {
volatile union {
struct {
uint32_t pltf : 2; /*These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs o... | 1,572 |
*/
uint32_t deferralcheck : 1; /*Deferral Check.*/
uint32_t backofflimit : 2; /*The Back-Off limit determines the random integer number (r) of slot time delays (512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. Th... | 1,572 |
When a collision occurs on the MII interface the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset the MAC attempts retries based on the settings of the BL field (Bits [6:5]). This bit is applicable only in the hal... | 1,572 |
This bit is read only with default value of 1'b1 in the full-duplex-mode.*/
uint32_t loopback : 1; /*When this bit is set the MAC operates in the loopback mode MII. The MII Receive clock input (CLK_RX) is required for the loopback to work properly because the transmit clock is not looped-back intern... | 1,572 |
In the 10/100 Mbps-only operations the bit is always 1.*/
uint32_t disablecrs : 1; /*When set high this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during... | 1,572 |
*/
uint32_t reserved21 : 1;
uint32_t jabber : 1; /*When this bit is set the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16 383 bytes. When this bit is reset the MAC cuts off the transmitter if the application sends out more than 2 048 bytes of data ... | 1,572 |
When Bit[20] (JE) is not set the MAC considers all received frames of size more than 2K bytes as Giant frames. When this bit is reset and Bit[20] (JE) is not set the MAC considers all received frames of size more than 1 518 bytes (1 522 bytes for tagged) as Giant frames. When Bit[20] is set setting this bit has no e... | 1,572 |
If Bit[30] is set to 1 the MAC replaces the content of the MAC Address 1 registers in the SA field of all transmitted frames.*/
uint32_t reserved31 : 1;
};
uint32_t val;
} gmacconfig;
volatile union {
struct {
uint32_t pmode : 1; /*When this bit is set the Addr... | 1,572 |
*/
uint32_t dbf : 1; /*When this bit is set the AFM(Address Filtering Module) module blocks all incoming broadcast frames. In addition it overrides all other filter settings. When this bit is reset the AFM module passes all received broadcast Frames.*/
uint32_t pcf : 2; /*These bits control... | 1,572 |
Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001.*/
uint32_t saif : 1; /*When this bit is set the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Addre... | 1,572 |
The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset the Receiver module passes only those frames to the Application that pass the SA or DA address Filter.*/
};
uint32_t val;
} gmacff;
uint32_t reserved_1008;... | 1,572 |
Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed there is no change in the functionality of this bit even when the PHY is not Present.*/
uint32_t miiwrite : 1; /*When set this bit indicates to the PHY that this is a Write operation using the MII Data re... | 1,572 |
*/
uint32_t reserved16 : 16;
};
uint32_t val;
} emacmiidata;
volatile union {
struct {
uint32_t fcbba : 1; /*This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFCE bit is set. In the ful... | 1,572 |
*/
uint32_t tfce : 1; /*In the full-duplex mode when this bit is set the MAC enables the flow control operation to transmit Pause frames. When this bit is reset the flow control operation in the MAC is disabled and the MAC does not transmit any Pause frames. In the half-duplex mode when this bit is set... | 1,572 |
*/
uint32_t plt : 2; /*This field configures the threshold of the Pause timer automatic retransmission of the Pause frame.The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example if PT = 100H (256 slot-times) and PLT = 01 then a second Pause frame is automat... | 1,572 |
When this bit is reset normal operation with automatic Zero-Quanta Pause frame generation is enabled.*/
uint32_t reserved8 : 8;
uint32_t pause_time : 16; /*This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be do... | 1,572 |
MACRFFCS[0] represents the status of small FIFO Write controller.*/
uint32_t reserved3 : 1;
uint32_t mtlrfwcas : 1; /*When high this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO.*/
uint32_t mtlrfrcs : 2; /*This fiel... | 1,572 |
*/
uint32_t mactfcs : 2; /*This field indicates the state of the MAC Transmit Frame Controller module: 2'b00: IDLE state. 2'b01: Waiting for status of previous frame or IFG or backoff period to be over. 2'b10: Generating and transmitting a Pause frame (in the full-duplex mode). 2'b11: Transferring inp... | 1,572 |
*/
uint32_t reserved23 : 1;
uint32_t mtltfnes : 1; /*When high this bit indicates that the MTL Tx FIFO is not empty and some data is left for Transmission.*/
uint32_t mtltsffs : 1; /*When high this bit indicates that the MTL TxStatus FIFO is full. Therefore the MTL cannot accept a... | 1,572 |
This bit must only be set when MGKPKTEN GLBLUCAST or RWKPKTEN bit is set high.*/
uint32_t mgkpkten : 1; /*When set enables generation of a power management event because of magic packet reception.*/
uint32_t rwkpkten : 1; /*When set enables generation of a power management event because of r... | 1,572 |
*/
uint32_t reserved29 : 2;
uint32_t rwkfiltrst : 1; /*When this bit is set it resets the RWKPTR register to 3’b000.*/
};
uint32_t val;
} pmt_csr;
volatile union {
struct {
uint32_t tlpien : 1; /*When set this bit indicates that the MAC Transmitter h... | 1,572 |
This bit is cleared by a read into this register.*/
uint32_t reserved4 : 4;
uint32_t tlpist : 1; /*When set this bit indicates that the MAC is transmitting the LPI pattern on the MII interface.*/
uint32_t rlpist : 1; /*When set this bit indicates that the MAC is receiving the LPI ... | 1,572 |
If the LPITXA and LPIEN bits are set to 1 the MAC enters the LPI mode only after all outstanding frames and pending frames have been transmitted. The MAC comes out of the LPI mode when the application sends any frame.When this bit is 0 the LPIEN bit directly controls behavior of the MAC when it is entering or coming ... | 1,572 |
The default value of the LPI_LS_Timer is 1000 (1 sec) as defined in the IEEE standard.*/
uint32_t reserved26 : 6;
};
uint32_t val;
} gmaclpitimerscontrol;
volatile union {
struct {
uint32_t reserved0 : 1;
uint32_t reserved1 : 1;
uint32_t r... | 1,572 |
This bit is cleared on reading Bit[0] of Register (LPI Control and Status Register).*/
uint32_t reserved11 : 1;
uint32_t reserved12 : 20;
};
uint32_t val;
} emacints;
volatile union {
struct {
uint32_t reserved0 : 1;
uint32_t reserved1 : 1... | 1,572 |
The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames.*/
uint32_t reserved16 : 15;
uint32_t address_enable0 : 1; /*This bit is always set to 1.*/
};
uint32_t val;
} emacaddr0high;
uint32_t emaca... | 1,572 |
Bit[28]: EMACADDR1 High [7:0]. Bit[27]: EMACADDR1 Low [31:24]. Bit[24]: EMACADDR1 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/
uint32_t source_address : 1; /*When this bit is set the EMACADDR1[47:0] is used to compare... | 1,572 |
*/
uint32_t reserved16 : 8;
uint32_t mask_byte_control2 : 6; /*These bits are mask control bits for comparison of each of the EMACADDR2 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR2 registers. Each bit controls the maski... | 1,572 |
*/
};
uint32_t val;
} emacaddr2high;
uint32_t emacaddr2low; /*This field contains the lower 32 bits of the third 6-byte MAC address. The content of this field is undefined so the register needs to be configured after the initialization process.*/
volatile union {
struct {
... | 1,572 |
*/
uint32_t source_address3 : 1; /*When this bit is set the EMACADDR3[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR3[47:0] is used to compare with the DA fields of the received frame.*/
uint32_t address_enable3 : 1; /*When this bit... | 1,572 |
When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR4 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR4 High [15:8]. Bit[28]: EMACADDR4 High [7:0]. Bit[27]: EMACADDR4 Low [31:24]. Bit[24]: EMACADDR4 Low [7:0].You can fi... | 1,572 |
The content of this field is undefined so the register needs to be configured after the initialization process.*/
volatile union {
struct {
uint32_t mac_address5_hi : 16; /*This field contains the upper 16 bits Bits[47:32] of the sixth 6-byte MAC address.*/
uint32_t reserved16 : 8... | 1,572 |
When this bit is reset the EMACADDR5[47:0] is used to compare with the DA fields of the received frame.*/
uint32_t address_enable5 : 1; /*When this bit is set the address filter module uses the sixth MAC address for perfect filtering. When this bit is reset the address filter module ignores the addre... | 1,572 |
Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR6 High [15:8]. Bit[28]: EMACADDR6 High [7:0]. Bit[27]: EMACADDR6 Low [31:24]. Bit[24]: EMACADDR6 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/
uint32... | 1,572 |
*/
volatile union {
struct {
uint32_t mac_address7_hi : 16; /*This field contains the upper 16 bits Bits[47:32] of the eighth 6-byte MAC Address.*/
uint32_t reserved16 : 8;
uint32_t mask_byte_control7 : 6; /*These bits are mask control bits for comparison of each of the ... | 1,572 |
*/
uint32_t address_enable7 : 1; /*When this bit is set the address filter module uses the eighth MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering.*/
};
uint32_t val;
} emacaddr7high;
uint32_t emacaddr7low; /*T... | 1,572 |
1'b1: Full-duplex mode.*/
uint32_t link_speed : 2; /*This bit indicates the current speed of the link: 2'b00: 2.5 MHz. 2'b01: 25 MHz. 2'b10: 125 MHz.*/
uint32_t reserved3 : 1;
uint32_t jabber_timeout : 1; /*This bit indicates whether there is jabber timeout error (1'b1) in the ... | 1,572 |
When this bit is cleared the watchdog timeout for a received frame is controlled by the setting of Bit[23] (WD) and Bit[20] (JE) in EMACCONFIG_REG.*/
uint32_t reserved17 : 15;
};
uint32_t val;
} emacwdogto;
} emac_mac_dev_t;
extern emac_mac_dev_t EMAC_MAC;
#ifdef __cplusplus
}
#endif... | 1,572 |
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 1,573 |
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 1,574 |
/*
*/
#pragma once
#define ADC1_GPIO36_CHANNEL 0
#define ADC1_CHANNEL_0_GPIO_NUM 36
#define ADC1_GPIO37_CHANNEL 1
#define ADC1_CHANNEL_1_GPIO_NUM 37
#define ADC1_GPIO38_CHANNEL 2
#define ADC1_CHANNEL_2_GPIO_NUM 38
#define ADC1_GPIO39_CHANNEL 3
#define ADC1_CHANNEL_3_GPIO_NUM 39
#define ADC1_GPIO3... | 1,575 |
/*
*/
#pragma once
#define DAC_GPIO25_CHANNEL DAC_CHAN_0
#define DAC_CHAN0_GPIO_NUM 25
#define DAC_CHANNEL_1_GPIO_NUM DAC_CHAN0_GPIO_NUM //`DAC_CHANNEL_1_GPIO_NUM` is defined for DAC legacy driver, indicating the first DAC channel.
#define DAC_GPIO26_CHANNEL DAC_CHAN_1
#define DAC_CHAN1_GP... | 1,576 |
/*
*/
/*
*/
#pragma once
#ifdef __has_include
# if __has_include("sdkconfig.h")
# include "sdkconfig.h"
# define SOC_CAPS_ECO_VER CONFIG_ESP32_REV_MIN_FULL
# endif
#endif
#if __DOXYGEN__ && !defined(SOC_CAPS_ECO_VER)
#define SOC_CAPS_ECO_VER SOC_CAPS_ECO_VER_MAX
#endif
#ifndef SOC_CAPS_ECO_VER
#wa... | 1,577 |
#define SOC_CPU_BREAKPOINTS_NUM 2
#define SOC_CPU_WATCHPOINTS_NUM 2
#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 64 // bytes
/* DAC CAPS */
#define SOC_DAC_CHAN_NUM 2
#define SOC_DAC_RESOLUTION 8 // DAC resolution ratio 8 bit
#define SOC_DAC_DMA_16BIT_ALIGN 1 ... | 1,577 |
= 200
# define SOC_TWAI_BRP_MAX 256
# define SOC_TWAI_BRP_DIV_SUPPORTED 1
#else
# define SOC_TWAI_BRP_MAX 128
#endif
#define SOC_TWAI_CLK_SUPPORT_APB 1
#define SOC_TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT 1
/* UART CAPS */
// ESP32 have 3 UART.
#define SOC_UART_NUM (3)
... | 1,577 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.