text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
bit0 is used to choose test only once(1) or continue(0)*/
uint32_t reserved3: 1;
uint32_t test_addr: 2; /*The two bits represent ahb bus address bit[20:19]*/
uint32_t reserved6: 26;
};
uint32_t val;
} ahb_test;
uint32_t dma_in_dscr;... | 1,545 |
*/
uint32_t tx_db_esc_en: 1; /*Set this bit to enable 0xdb char decode when DMA receives data.*/
uint32_t tx_11_esc_en: 1; /*Set this bit to enable flow control char 0x11 decode when DMA receives data.*/
uint32_t tx_13_esc_en: 1; ... | 1,545 |
when DMA takes more time than this register value to receive a data it will produce uhci_tx_hung_int interrupt.*/
uint32_t txfifo_timeout_shift: 3; /*The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift)*/
uint32_t txfifo_timeout_ena: 1; /*... | 1,545 |
*/
uint32_t seper_esc_char0: 8; /*This register stores the first char used to replace separator char in data.*/
uint32_t seper_esc_char1: 8; /*This register stores the second char used to replace separator char in data . 0xdc 0xdb replace 0xc0 by default.*/
... | 1,545 |
*/
uint32_t seq1_char1: 8; /*This register stores the second char used to replace the reg_esc_seq1 in data.*/
uint32_t reserved24: 8;
};
uint32_t val;
} esc_conf2;
union {
struct {
uint32_t seq2: 8; /... | 1,545 |
/*
*/
#ifndef _SOC_RTC_IO_CHANNEL_H
#define _SOC_RTC_IO_CHANNEL_H
//RTC GPIO channels
#define RTCIO_GPIO36_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 36
#define RTCIO_GPIO37_CHANNEL 1 //RTCIO_CHANNEL_1
#define RTCIO_CHANNEL_1_GPIO_NUM 37
#define RTCIO_GPIO38_CHANNEL ... | 1,546 |
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 1,547 |
/*
*/
#ifndef _CACHE_MEMORY_H_
#define _CACHE_MEMORY_H_
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x400D0000
#define SOC_IRAM0_CACHE_ADDRESS_HIGH 0x40400000
#define SOC_IRAM1_CACHE_ADDRESS_LOW 0x40400000
#define SOC_IRAM1_CACHE_ADDRESS_HIGH ... | 1,548 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/*
ESP32 Root Clock Source
*/
/* With the default value of CK8M_DFREQ = 172, RC_FAST clock frequency is 8.5 MHz +/- 7% */
#define SOC_CLK_RC_FAST_FREQ_APPROX 8500000 /*!, F
/**
*/
typedef enum {
// For CPU domain
... | 1,550 |
< PLL_F160M_CLK is derived from PLL, and has a fixed frequency of 160MHz */
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 8MHz rc ... | 1,550 |
< Indication of the end of the available module clock sources */
} soc_module_clk_t;
//////////////////////////////////////////////////SYSTIMER///////////////////////////////////////////////////////////////
/**
*/
typedef enum {
SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL *... | 1,550 |
< Timer group source clock default choice is APB */
} soc_periph_tg_clk_src_legacy_t;
//////////////////////////////////////////////////LCD///////////////////////////////////////////////////////////////////
/**
*/
#define SOC_LCD_CLKS {SOC_MOD_CLK_PLL_F160M}
/**
*/
typedef enum {
LCD_CLK_SRC_PLL160M = SOC_MOD_... | 1,550 |
< RMT source clock is APB CLK */
RMT_BASECLK_REF = SOC_MOD_CLK_REF_TICK, /*!< RMT source clock is REF_TICK */
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_APB, /*!< RMT source clock default choice is APB */
} soc_periph_rmt_clk_src_legacy_t;
///////////////////////////////////////////////////UART////////////////////////... | 1,550 |
< Select PLL_F160M as the source clock */
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
} soc_periph_mcpwm_timer_clk_src_t;
/**
*/
#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_APB}
/**
*/
typedef enum {
MCPWM_CAPTURE_CLK_SRC_APB = SOC_MOD_CLK_APB, ... | 1,550 |
< Select PLL_F160M as the default source clock */
I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
I2S_CLK_SRC_APLL = SOC_MOD_CLK_APLL, /*!< Select APLL as the source clock */
} soc_periph_i2s_clk_src_t;
///////////////////////////... | 1,550 |
< Select APB as the source clock */
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
} soc_periph_sdm_clk_src_t;
////////////////////////////////////////////////////DAC/////////////////////////////////////////////////////////////////
/**
*/
#define SOC_DAC_DIGI_CLKS {SOC_MOD_... | 1,550 |
< Select APB as the source clock */
TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
} soc_periph_twai_clk_src_t;
//////////////////////////////////////////////////ADC///////////////////////////////////////////////////////////////////
/**
*/
#define SOC_ADC_DIGI_CLKS {SOC_MO... | 1,550 |
< Select APB as the source clock */
MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
} soc_periph_mwdt_clk_src_t;
//////////////////////////////////////////////////LEDC/////////////////////////////////////////////////////////////////
/**
*/
#define SOC_LEDC_CLKS {SOC_MOD_CLK... | 1,550 |
< Select PLL_160M as the default choice */
SDMMC_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as the source clock */
} soc_periph_sdmmc_clk_src_t;
//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
typedef enum {
CLKOUT_SIG_I2S... | 1,550 |
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 1,551 |
The bit will be cleared once the operation done. 1: enable 0: disable.*/
#define SPI_FLASH_READ (BIT(31))
#define SPI_FLASH_READ_M (BIT(31))
#define SPI_FLASH_READ_V 0x1
#define SPI_FLASH_READ_S 31
/* SPI_FLASH_WREN : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: Write flash enable. Write enable command wil... | 1,551 |
The bit will be cleared once the operation done. 1: enable 0: disable.*/
#define SPI_FLASH_RDID (BIT(28))
#define SPI_FLASH_RDID_M (BIT(28))
#define SPI_FLASH_RDID_V 0x1
#define SPI_FLASH_RDID_S 28
/* SPI_FLASH_RDSR : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: Read status register-1. Read status operatio... | 1,551 |
Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
#define SPI_FLASH_PP (BIT(25))
#define SPI_FLASH_PP_M (BIT(25))
#define SPI_FLASH_PP_V 0x1
#define SPI_FLASH_PP_S 25
/* SPI_FLASH_SE : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*desc... | 1,551 |
Chip erase operation will be triggered when
the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
#define SPI_FLASH_CE (BIT(22))
#define SPI_FLASH_CE_M (BIT(22))
#define SPI_FLASH_CE_V 0x1
#define SPI_FLASH_CE_S 22
/* SPI_FLASH_DP : R/W ;bitpos:[21] ;default: 1'b0 ; */
/*descript... | 1,551 |
The bit will be cleared
once the operation done.1: enable 0: disable.*/
#define SPI_FLASH_HPM (BIT(19))
#define SPI_FLASH_HPM_M (BIT(19))
#define SPI_FLASH_HPM_V 0x1
#define SPI_FLASH_HPM_S 19
/* SPI_USR : R/W ;bitpos:[18] ;default: 1'b0 ; */
/*description: User define command enable. An operation will be trigg... | 1,551 |
The bit will be cleared once the operation done.1: enable 0: disable.*/
#define SPI_FLASH_PER (BIT(16))
#define SPI_FLASH_PER_M (BIT(16))
#define SPI_FLASH_PER_V 0x1
#define SPI_FLASH_PER_S 16
#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4)
//The CSV actually is wrong here. It indicates that the lower 8 ... | 1,551 |
1: enable 0: disable.*/
#define SPI_FREAD_QIO (BIT(24))
#define SPI_FREAD_QIO_M (BIT(24))
#define SPI_FREAD_QIO_V 0x1
#define SPI_FREAD_QIO_S 24
/* SPI_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
/*description: In the read operations address phase and read-data phase apply
2 signals. 1: enable 0: disable.*/
... | 1,551 |
1: enable 0: disable.*/
#define SPI_FREAD_QUAD (BIT(20))
#define SPI_FREAD_QUAD_M (BIT(20))
#define SPI_FREAD_QUAD_V 0x1
#define SPI_FREAD_QUAD_S 20
/* SPI_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */
/*description: The Device ID is read out to SPI_RD_STATUS register, this bit
combine with spi_flash_res bit. ... | 1,551 |
1: enable 0: disable.*/
#define SPI_WAIT_FLASH_IDLE_EN (BIT(12))
#define SPI_WAIT_FLASH_IDLE_EN_M (BIT(12))
#define SPI_WAIT_FLASH_IDLE_EN_V 0x1
#define SPI_WAIT_FLASH_IDLE_EN_S 12
/* SPI_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: For SPI1 enable crc32 when writing encrypted data to flash.
1... | 1,551 |
*/
#define SPI_CS_HOLD_DELAY_RES 0x00000FFF
#define SPI_CS_HOLD_DELAY_RES_M ((SPI_CS_HOLD_DELAY_RES_V)<<(SPI_CS_HOLD_DELAY_RES_S))
#define SPI_CS_HOLD_DELAY_RES_V 0xFFF
#define SPI_CS_HOLD_DELAY_RES_S 16
#define SPI_RD_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10)
/* SPI_STATUS_EXT : R/W ;bitpos:[31:24] ;default... | 1,551 |
*/
#define SPI_STATUS 0x0000FFFF
#define SPI_STATUS_M ((SPI_STATUS_V)<<(SPI_STATUS_S))
#define SPI_STATUS_V 0xFFFF
#define SPI_STATUS_S 0
#define SPI_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x14)
/* SPI_CS_DELAY_NUM : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
/*description: spi_cs signal is delayed by system clock ... | 1,551 |
0: zero 1: if spi_ck_out_edge
or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/
#define SPI_MOSI_DELAY_MODE 0x00000003
#define SPI_MOSI_DELAY_MODE_M ((SPI_MOSI_DELA... | 1,551 |
*/
#define SPI_CK_OUT_HIGH_MODE 0x0000000F
#define SPI_CK_OUT_HIGH_MODE_M ((SPI_CK_OUT_HIGH_MODE_V)<<(SPI_CK_OUT_HIGH_MODE_S))
#define SPI_CK_OUT_HIGH_MODE_V 0xF
#define SPI_CK_OUT_HIGH_MODE_S 12
/* SPI_CK_OUT_LOW_MODE : R/W ;bitpos:[11:8] ;default: 4'h0 ; */
/*description: modify spi clock duty ratio when the valu... | 1,551 |
*/
#define SPI_SETUP_TIME 0x0000000F
#define SPI_SETUP_TIME_M ((SPI_SETUP_TIME_V)<<(SPI_SETUP_TIME_S))
#define SPI_SETUP_TIME_V 0xF
#define SPI_SETUP_TIME_S 0
#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0x18)
/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */
/*description: In the master mode 1:... | 1,551 |
In
the slave mode it must be 0.*/
#define SPI_CLKCNT_H 0x0000003F
#define SPI_CLKCNT_H_M ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S))
#define SPI_CLKCNT_H_V 0x3F
#define SPI_CLKCNT_H_S 6
/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
/*description: In the master mode it must be equal to spi_clkcnt_N. In the slav... | 1,551 |
*/
#define SPI_USR_DUMMY (BIT(29))
#define SPI_USR_DUMMY_M (BIT(29))
#define SPI_USR_DUMMY_V 0x1
#define SPI_USR_DUMMY_S 29
/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: This bit enable the read-data phase of an operation.*/
#define SPI_USR_MISO (BIT(28))
#define SPI_USR_MISO_M (BIT(28))
#... | 1,551 |
1: enable 0: disable.*/
#define SPI_USR_MOSI_HIGHPART (BIT(25))
#define SPI_USR_MOSI_HIGHPART_M (BIT(25))
#define SPI_USR_MOSI_HIGHPART_V 0x1
#define SPI_USR_MOSI_HIGHPART_S 25
/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: read-data phase only access to high-part of the buffer spi... | 1,551 |
*/
#define SPI_USR_ADDR_HOLD (BIT(21))
#define SPI_USR_ADDR_HOLD_M (BIT(21))
#define SPI_USR_ADDR_HOLD_V 0x1
#define SPI_USR_ADDR_HOLD_S 21
/* SPI_USR_DUMMY_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.*/
#define SPI_USR_DUMMY_HOLD... | 1,551 |
1: enable 0: disable.*/
#define SPI_SIO (BIT(16))
#define SPI_SIO_M (BIT(16))
#define SPI_SIO_V 0x1
#define SPI_SIO_S 16
/* SPI_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: In the write operations address phase and read-data phase apply 4 signals.*/
#define SPI_FWRITE_QIO (BIT(15))
#define SPI... | 1,551 |
*/
#define SPI_CK_OUT_EDGE (BIT(7))
#define SPI_CK_OUT_EDGE_M (BIT(7))
#define SPI_CK_OUT_EDGE_V 0x1
#define SPI_CK_OUT_EDGE_S 7
/* SPI_CK_I_EDGE : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: In the slave mode the bit is same as spi_ck_out_edge in master
mode. It is combined with spi_miso_delay_mode bits.... | 1,551 |
1: enable 0: disable.*/
#define SPI_DOUTDIN (BIT(0))
#define SPI_DOUTDIN_M (BIT(0))
#define SPI_DOUTDIN_V 0x1
#define SPI_DOUTDIN_S 0
#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x20)
/* SPI_USR_ADDR_BITLEN : RO ;bitpos:[31:26] ;default: 6'd23 ; */
/*description: The length in bits of address phase. The ... | 1,551 |
The register value shall be (bit_num-1)*/
#define SPI_USR_COMMAND_BITLEN 0x0000000F
#define SPI_USR_COMMAND_BITLEN_M ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S))
#define SPI_USR_COMMAND_BITLEN_V 0xF
#define SPI_USR_COMMAND_BITLEN_S 28
/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
/... | 1,551 |
The register value shall be (bit_num-1).*/
#define SPI_USR_MISO_DBITLEN 0x00FFFFFF
#define SPI_USR_MISO_DBITLEN_M ((SPI_USR_MISO_DBITLEN_V)<<(SPI_USR_MISO_DBITLEN_S))
#define SPI_USR_MISO_DBITLEN_V 0xFFFFFF
#define SPI_USR_MISO_DBITLEN_S 0
#define SPI_SLV_WR_STATUS_REG(i) (REG_SPI_BASE(i) + 0x30)
/* SPI_... | 1,551 |
*/
#define SPI_MASTER_CK_SEL 0x00000007
#define SPI_MASTER_CK_SEL_M ((SPI_MASTER_CK_SEL_V)<<(SPI_MASTER_CK_SEL_S))
#define SPI_MASTER_CK_SEL_V 0x07
#define SPI_MASTER_CK_SEL_S 11
/* SPI_MASTER_CS_POL : R/W ;bitpos:[8:6] ;default: 3'b0 ; */
/*description: In the master mode the bits are the polarity of spi cs line
... | 1,551 |
*/
#define SPI_SYNC_RESET (BIT(31))
#define SPI_SYNC_RESET_M (BIT(31))
#define SPI_SYNC_RESET_V 0x1
#define SPI_SYNC_RESET_S 31
/* SPI_SLAVE_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: 1: slave mode 0: master mode.*/
#define SPI_SLAVE_MODE (BIT(30))
#define SPI_SLAVE_MODE_M (BIT(30))
#define SPI_SL... | 1,551 |
0: slave mode
commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/
#define SPI_SLV_CMD_DEFINE (BIT(27))
#define SPI_SLV_CMD_DEFINE_M (BIT(27))
#define SPI_SLV_CMD_DEFINE_V 0x1
#define SPI_SLV_CMD_DEFINE_S 27
/* SPI_TRANS_CNT : RO ;bitpos:[26:23] ;default: 4'b0 ; */
/*description: The oper... | 1,551 |
*/
#define SPI_CS_I_MODE 0x00000003
#define SPI_CS_I_MODE_M ((SPI_CS_I_MODE_V)<<(SPI_CS_I_MODE_S))
#define SPI_CS_I_MODE_V 0x3
#define SPI_CS_I_MODE_S 10
/* SPI_INT_EN : R/W ;bitpos:[9:5] ;default: 5'b1_0000 ; */
/*description: Interrupt enable bits for the below 5 sources*/
#define SPI_INT_EN 0x0000001F
#define S... | 1,551 |
*/
#define SPI_SLV_RD_STA_DONE (BIT(2))
#define SPI_SLV_RD_STA_DONE_M (BIT(2))
#define SPI_SLV_RD_STA_DONE_V 0x1
#define SPI_SLV_RD_STA_DONE_S 2
/* SPI_SLV_WR_BUF_DONE : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The interrupt raw bit for the completion of write-buffer operation
in the slave mode.*/
#defin... | 1,551 |
*/
#define SPI_SLV_STATUS_FAST_EN (BIT(26))
#define SPI_SLV_STATUS_FAST_EN_M (BIT(26))
#define SPI_SLV_STATUS_FAST_EN_V 0x1
#define SPI_SLV_STATUS_FAST_EN_S 26
/* SPI_SLV_STATUS_READBACK : R/W ;bitpos:[25] ;default: 1'b1 ; */
/*description: In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read
register ... | 1,551 |
The register value shall be (bit_num-1).*/
#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F
#define SPI_SLV_WR_ADDR_BITLEN_M ((SPI_SLV_WR_ADDR_BITLEN_V)<<(SPI_SLV_WR_ADDR_BITLEN_S))
#define SPI_SLV_WR_ADDR_BITLEN_V 0x3F
#define SPI_SLV_WR_ADDR_BITLEN_S 4
/* SPI_SLV_WRSTA_DUMMY_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*d... | 1,551 |
*/
#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1))
#define SPI_SLV_WRBUF_DUMMY_EN_M (BIT(1))
#define SPI_SLV_WRBUF_DUMMY_EN_V 0x1
#define SPI_SLV_WRBUF_DUMMY_EN_S 1
/* SPI_SLV_RDBUF_DUMMY_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: In the slave mode it is the enable bit of dummy phase for read-buffer
operation... | 1,551 |
The register value shall be (cycle_num-1).*/
#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0x000000FF
#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_M ((SPI_SLV_RDBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDBUF_DUMMY_CYCLELEN_S))
#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_V 0xFF
#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16
/* SPI_SLV_WRSTA_DUMMY_CYCLE... | 1,551 |
*/
#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF
#define SPI_SLV_WRSTA_CMD_VALUE_M ((SPI_SLV_WRSTA_CMD_VALUE_V)<<(SPI_SLV_WRSTA_CMD_VALUE_S))
#define SPI_SLV_WRSTA_CMD_VALUE_V 0xFF
#define SPI_SLV_WRSTA_CMD_VALUE_S 24
/* SPI_SLV_RDSTA_CMD_VALUE : R/W ;bitpos:[23:16] ;default: 8'b0 ; */
/*description: In the slave mode... | 1,551 |
*/
#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF
#define SPI_SLV_RDBUF_CMD_VALUE_M ((SPI_SLV_RDBUF_CMD_VALUE_V)<<(SPI_SLV_RDBUF_CMD_VALUE_S))
#define SPI_SLV_RDBUF_CMD_VALUE_V 0xFF
#define SPI_SLV_RDBUF_CMD_VALUE_S 0
#define SPI_SLV_WRBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x48)
/* SPI_SLV_WRBUF_DBITLEN : R/W ;b... | 1,551 |
*/
#define SPI_CACHE_FLASH_PES_EN (BIT(3))
#define SPI_CACHE_FLASH_PES_EN_M (BIT(3))
#define SPI_CACHE_FLASH_PES_EN_V 0x1
#define SPI_CACHE_FLASH_PES_EN_S 3
/* SPI_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: For SPI0 cache read flash for user define command 1: enable 0:disable.*/
#d... | 1,551 |
The register value shall be (bit_num-1).*/
#define SPI_SRAM_ADDR_BITLEN 0x0000003F
#define SPI_SRAM_ADDR_BITLEN_M ((SPI_SRAM_ADDR_BITLEN_V)<<(SPI_SRAM_ADDR_BITLEN_S))
#define SPI_SRAM_ADDR_BITLEN_V 0x3F
#define SPI_SRAM_ADDR_BITLEN_S 22
/* SPI_SRAM_DUMMY_CYCLELEN : R/W ;bitpos:[21:14] ;default: 8'b1 ; */
/*descrip... | 1,551 |
*/
#define SPI_CACHE_SRAM_USR_RCMD (BIT(5))
#define SPI_CACHE_SRAM_USR_RCMD_M (BIT(5))
#define SPI_CACHE_SRAM_USR_RCMD_V 0x1
#define SPI_CACHE_SRAM_USR_RCMD_S 5
/* SPI_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: For SPI0 In the spi sram mode it is the enable bit of dummy
phase for read... | 1,551 |
SRAM IO mode reset operation
will be triggered when the bit is set. The bit will be cleared once the operation done*/
#define SPI_SRAM_RSTIO (BIT(4))
#define SPI_SRAM_RSTIO_M (BIT(4))
#define SPI_SRAM_RSTIO_V 0x1
#define SPI_SRAM_RSTIO_S 4
/* SPI_SRAM_QIO : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: For S... | 1,551 |
The register value shall be (bit_num-1).*/
#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F
#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S))
#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF
#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28
/* SPI_... | 1,551 |
The register value shall be (bit_num-1).*/
#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F
#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S))
#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF
#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28
/* SPI_... | 1,551 |
*/
#define SPI_TX_CRC_DATA 0xFFFFFFFF
#define SPI_TX_CRC_DATA_M ((SPI_TX_CRC_DATA_V)<<(SPI_TX_CRC_DATA_S))
#define SPI_TX_CRC_DATA_V 0xFFFFFFFF
#define SPI_TX_CRC_DATA_S 0
#define SPI_EXT0_REG(i) (REG_SPI_BASE(i) + 0xF0)
/* SPI_T_PP_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */
/*description: page program de... | 1,551 |
*/
#define SPI_T_ERASE_ENA (BIT(31))
#define SPI_T_ERASE_ENA_M (BIT(31))
#define SPI_T_ERASE_ENA_V 0x1
#define SPI_T_ERASE_ENA_S 31
/* SPI_T_ERASE_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd15 ; */
/*description: erase flash delay time shift.*/
#define SPI_T_ERASE_SHIFT 0x0000000F
#define SPI_T_ERASE_SHIFT_M ((SPI_... | 1,551 |
The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ¡°idle¡± phase 2: hold at ¡°prepare¡± phase.*/
#define SPI_INT_HOLD_ENA 0x00000003
#define SPI_INT_HOLD_ENA_M ((SPI_INT_HOLD_ENA_V)<<(SPI_INT_HOLD_ENA_S))
#define SPI_INT_HOLD_ENA_V 0x3
#define SPI_INT_HOLD_ENA_S 0
#define ... | 1,551 |
*/
#define SPI_DMA_RX_STOP (BIT(14))
#define SPI_DMA_RX_STOP_M (BIT(14))
#define SPI_DMA_RX_STOP_V 0x1
#define SPI_DMA_RX_STOP_S 14
/* SPI_OUT_DATA_BURST_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: spi dma read data from memory in burst mode.*/
#define SPI_OUT_DATA_BURST_EN (BIT(12))
#define SPI_OUT_D... | 1,551 |
1: when dma pop all data from
fifo 0:when ahb push all data to fifo.*/
#define SPI_OUT_EOF_MODE (BIT(9))
#define SPI_OUT_EOF_MODE_M (BIT(9))
#define SPI_OUT_EOF_MODE_V 0x1
#define SPI_OUT_EOF_MODE_S 9
/* SPI_OUT_AUTO_WRBACK : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: when the link is empty jump to nex... | 1,551 |
*/
#define SPI_AHBM_RST (BIT(5))
#define SPI_AHBM_RST_M (BIT(5))
#define SPI_AHBM_RST_V 0x1
#define SPI_AHBM_RST_S 5
/* SPI_AHBM_FIFO_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: reset spi dma ahb master fifo pointer.*/
#define SPI_AHBM_FIFO_RST (BIT(4))
#define SPI_AHBM_FIFO_RST_M (BIT(4))
#define SP... | 1,551 |
*/
#define SPI_OUTLINK_RESTART (BIT(30))
#define SPI_OUTLINK_RESTART_M (BIT(30))
#define SPI_OUTLINK_RESTART_V 0x1
#define SPI_OUTLINK_RESTART_S 30
/* SPI_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: Set the bit to start to use outlink descriptor.*/
#define SPI_OUTLINK_START (BIT(29))
#defin... | 1,551 |
*/
#define SPI_INLINK_RESTART (BIT(30))
#define SPI_INLINK_RESTART_M (BIT(30))
#define SPI_INLINK_RESTART_V 0x1
#define SPI_INLINK_RESTART_S 30
/* SPI_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: Set the bit to start to use inlink descriptor.*/
#define SPI_INLINK_START (BIT(29))
#define SPI_I... | 1,551 |
*/
#define SPI_INLINK_ADDR 0x000FFFFF
#define SPI_INLINK_ADDR_M ((SPI_INLINK_ADDR_V)<<(SPI_INLINK_ADDR_S))
#define SPI_INLINK_ADDR_V 0xFFFFF
#define SPI_INLINK_ADDR_S 0
#define SPI_DMA_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10C)
/* SPI_DMA_TX_EN : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: spi dma writ... | 1,551 |
*/
#define SPI_OUT_EOF_INT_ENA (BIT(7))
#define SPI_OUT_EOF_INT_ENA_M (BIT(7))
#define SPI_OUT_EOF_INT_ENA_V 0x1
#define SPI_OUT_EOF_INT_ENA_S 7
/* SPI_OUT_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: The enable bit for completing usage of a outlink descriptor .*/
#define SPI_OUT_DONE_INT_ENA ... | 1,551 |
*/
#define SPI_IN_DONE_INT_ENA (BIT(3))
#define SPI_IN_DONE_INT_ENA_M (BIT(3))
#define SPI_IN_DONE_INT_ENA_V 0x1
#define SPI_IN_DONE_INT_ENA_S 3
/* SPI_INLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: The enable bit for inlink descriptor error.*/
#define SPI_INLINK_DSCR_ERROR_INT_ENA ... | 1,551 |
*/
#define SPI_OUT_TOTAL_EOF_INT_RAW (BIT(8))
#define SPI_OUT_TOTAL_EOF_INT_RAW_M (BIT(8))
#define SPI_OUT_TOTAL_EOF_INT_RAW_V 0x1
#define SPI_OUT_TOTAL_EOF_INT_RAW_S 8
/* SPI_OUT_EOF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: The raw bit for sending a packet to host done.*/
#define SPI_OUT_EOF_INT... | 1,551 |
*/
#define SPI_IN_ERR_EOF_INT_RAW (BIT(4))
#define SPI_IN_ERR_EOF_INT_RAW_M (BIT(4))
#define SPI_IN_ERR_EOF_INT_RAW_V 0x1
#define SPI_IN_ERR_EOF_INT_RAW_S 4
/* SPI_IN_DONE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw bit for completing usage of a inlink descriptor.*/
#define SPI_IN_DONE_INT_R... | 1,551 |
*/
#define SPI_INLINK_DSCR_EMPTY_INT_RAW (BIT(0))
#define SPI_INLINK_DSCR_EMPTY_INT_RAW_M (BIT(0))
#define SPI_INLINK_DSCR_EMPTY_INT_RAW_V 0x1
#define SPI_INLINK_DSCR_EMPTY_INT_RAW_S 0
#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x118)
/* SPI_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
... | 1,551 |
*/
#define SPI_IN_SUC_EOF_INT_ST (BIT(5))
#define SPI_IN_SUC_EOF_INT_ST_M (BIT(5))
#define SPI_IN_SUC_EOF_INT_ST_V 0x1
#define SPI_IN_SUC_EOF_INT_ST_S 5
/* SPI_IN_ERR_EOF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: The status bit for receiving error.*/
#define SPI_IN_ERR_EOF_INT_ST (BIT(4))
#define ... | 1,551 |
*/
#define SPI_OUTLINK_DSCR_ERROR_INT_ST (BIT(1))
#define SPI_OUTLINK_DSCR_ERROR_INT_ST_M (BIT(1))
#define SPI_OUTLINK_DSCR_ERROR_INT_ST_V 0x1
#define SPI_OUTLINK_DSCR_ERROR_INT_ST_S 1
/* SPI_INLINK_DSCR_EMPTY_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The status bit for lack of enough inlink descri... | 1,551 |
*/
#define SPI_OUT_EOF_INT_CLR (BIT(7))
#define SPI_OUT_EOF_INT_CLR_M (BIT(7))
#define SPI_OUT_EOF_INT_CLR_V 0x1
#define SPI_OUT_EOF_INT_CLR_S 7
/* SPI_OUT_DONE_INT_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: The clear bit for completing usage of a outlink descriptor.*/
#define SPI_OUT_DONE_INT_CLR (B... | 1,551 |
*/
#define SPI_IN_DONE_INT_CLR (BIT(3))
#define SPI_IN_DONE_INT_CLR_M (BIT(3))
#define SPI_IN_DONE_INT_CLR_V 0x1
#define SPI_IN_DONE_INT_CLR_S 3
/* SPI_INLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: The clear bit for inlink descriptor error.*/
#define SPI_INLINK_DSCR_ERROR_INT_CLR (... | 1,551 |
*/
#define SPI_DMA_IN_ERR_EOF_DES_ADDR 0xFFFFFFFF
#define SPI_DMA_IN_ERR_EOF_DES_ADDR_M ((SPI_DMA_IN_ERR_EOF_DES_ADDR_V)<<(SPI_DMA_IN_ERR_EOF_DES_ADDR_S))
#define SPI_DMA_IN_ERR_EOF_DES_ADDR_V 0xFFFFFFFF
#define SPI_DMA_IN_ERR_EOF_DES_ADDR_S 0
#define SPI_IN_SUC_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x12... | 1,551 |
*/
#define SPI_DMA_INLINK_DSCR_BF0 0xFFFFFFFF
#define SPI_DMA_INLINK_DSCR_BF0_M ((SPI_DMA_INLINK_DSCR_BF0_V)<<(SPI_DMA_INLINK_DSCR_BF0_S))
#define SPI_DMA_INLINK_DSCR_BF0_V 0xFFFFFFFF
#define SPI_DMA_INLINK_DSCR_BF0_S 0
#define SPI_INLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x130)
/* SPI_DMA_INLINK_DSCR_BF... | 1,551 |
*/
#define SPI_DMA_OUT_EOF_DES_ADDR 0xFFFFFFFF
#define SPI_DMA_OUT_EOF_DES_ADDR_M ((SPI_DMA_OUT_EOF_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_DES_ADDR_S))
#define SPI_DMA_OUT_EOF_DES_ADDR_V 0xFFFFFFFF
#define SPI_DMA_OUT_EOF_DES_ADDR_S 0
#define SPI_OUTLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x13C)
/* SPI_DMA_OUTLINK_DSC... | 1,551 |
*/
#define SPI_DMA_OUTLINK_DSCR_BF1 0xFFFFFFFF
#define SPI_DMA_OUTLINK_DSCR_BF1_M ((SPI_DMA_OUTLINK_DSCR_BF1_V)<<(SPI_DMA_OUTLINK_DSCR_BF1_S))
#define SPI_DMA_OUTLINK_DSCR_BF1_V 0xFFFFFFFF
#define SPI_DMA_OUTLINK_DSCR_BF1_S 0
#define SPI_DMA_RSTATUS_REG(i) (REG_SPI_BASE(i) + 0x148)
/* SPI_DMA_OUT_STATUS :... | 1,551 |
*/
#define SPI_DATE 0x0FFFFFFF
#define SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S))
#define SPI_DATE_V 0xFFFFFFF
#define SPI_DATE_S 0
#endif /*__SPI_REG_H__ */
| 1,551 |
/*
*/
#define DR_REG_DPORT_BASE 0x3ff00000
#define DR_REG_AES_BASE 0x3ff01000
#define DR_REG_RSA_BASE 0x3ff02000
#define DR_REG_SHA_BASE 0x3ff03000
#define DR_REG_FLASH_MMU_TABLE_PRO 0x3ff10000
#define DR_REG_FLA... | 1,552 |
/*
*/
#pragma once
#ifndef __ASSEMBLER__
#include
#include "esp_assert.h"
#include "soc/soc_caps.h"
#include "soc/interrupts.h"
#endif
#include "esp_bit_defs.h"
#include "reg_base.h"
#define PRO_CPU_NUM (0)
#define APP_CPU_NUM (1)
#define SOC_MAX_CONTIGUOUS_RAM_SIZE 0x400000 ///= DR_REG_DPORT_BASE) && (_r) > (_... | 1,553 |
__ASSEMBLER__ */
//}}
//Periheral Clock {{
#define APB_CLK_FREQ_ROM ( 26*1000000 )
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader... | 1,553 |
#define SOC_DIRAM_IRAM_LOW 0x400A0000
#define SOC_DIRAM_IRAM_HIGH 0x400C0000
#define SOC_DIRAM_DRAM_LOW 0x3FFE0000
#define SOC_DIRAM_DRAM_HIGH 0x40000000
// Byte order of D/IRAM regions is reversed between accessing as DRAM or IRAM
#define SOC_DIRAM_INVERTED 1
// Region of memory accessible via DMA. See ... | 1,553 |
h
/
*/
//CPU0 Interrupt number reserved, not touch this.
#define ETS_WMAC_INUM 0
#define ETS_BT_HOST_INUM 1
#define ETS_WBB_INUM 4
#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
#define ETS_FRC1_INUM ... | 1,553 |
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 1,554 |
*/
#define I2C_CLK_EN (BIT(8))
#define I2C_CLK_EN_M (BIT(8))
#define I2C_CLK_EN_V 0x1
#define I2C_CLK_EN_S 8
/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */
/*description: This bit is used to control the storage mode for received datas.
1: receive data from most significant bit 0: receive data from le... | 1,554 |
*/
#define I2C_MS_MODE (BIT(4))
#define I2C_MS_MODE_M (BIT(4))
#define I2C_MS_MODE_V 0x1
#define I2C_MS_MODE_S 4
/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set this bit to sample data in SCL low level. clear this bit
to sample data in SCL high level.*/
#define I2C_SAMPLE_SCL_LEVEL... | 1,554 |
3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/
#define I2C_SCL_STATE_LAST 0x00000007
#define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S))
#define I2C_SCL_STATE_LAST_V 0x7
#define I2C_SCL_STATE_LAST_S 28
/* I2C_SCL_MA... | 1,554 |
*/
#define I2C_RXFIFO_CNT 0x0000003F
#define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S))
#define I2C_RXFIFO_CNT_V 0x3F
#define I2C_RXFIFO_CNT_S 8
/* I2C_BYTE_TRANS : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: This register changes to high level when one byte is transferred.*/
#define I2C_BYTE_T... | 1,554 |
*/
#define I2C_ARB_LOST (BIT(3))
#define I2C_ARB_LOST_M (BIT(3))
#define I2C_ARB_LOST_V 0x1
#define I2C_ARB_LOST_S 3
/* I2C_TIME_OUT : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: when I2C takes more than time_out_reg clocks to receive a data
then this register changes to high level.*/
#define I2C_TIME_OUT (... | 1,554 |
*/
#define I2C_TIME_OUT_REG 0x000FFFFF
#define I2C_TIME_OUT_REG_M ((I2C_TIME_OUT_REG_V)<<(I2C_TIME_OUT_REG_S))
#define I2C_TIME_OUT_REG_V 0xFFFFF
#define I2C_TIME_OUT_REG_S 0
#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0010)
/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description:... | 1,554 |
*/
#define I2C_TXFIFO_END_ADDR 0x0000001F
#define I2C_TXFIFO_END_ADDR_M ((I2C_TXFIFO_END_ADDR_V)<<(I2C_TXFIFO_END_ADDR_S))
#define I2C_TXFIFO_END_ADDR_V 0x1F
#define I2C_TXFIFO_END_ADDR_S 15
/* I2C_TXFIFO_START_ADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */
/*description: This is the offset address of the first sen... | 1,554 |
*/
#define I2C_RXFIFO_START_ADDR 0x0000001F
#define I2C_RXFIFO_START_ADDR_M ((I2C_RXFIFO_START_ADDR_V)<<(I2C_RXFIFO_START_ADDR_S))
#define I2C_RXFIFO_START_ADDR_V 0x1F
#define I2C_RXFIFO_START_ADDR_S 0
#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x0018)
/* I2C_NONFIFO_TX_THRES : R/W ;bitpos:[25:20] ;d... | 1,554 |
*/
#define I2C_TX_FIFO_RST (BIT(13))
#define I2C_TX_FIFO_RST_M (BIT(13))
#define I2C_TX_FIFO_RST_V 0x1
#define I2C_TX_FIFO_RST_S 13
/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: Set this bit to reset rx fifo when using apb fifo access.*/
#define I2C_RX_FIFO_RST (BIT(12))
#define I2C_RX_F... | 1,554 |
when
I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/
#define I2C_TX_SEND_EMPTY_INT_RAW (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_RAW_M (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_RAW_V 0x1
#define I2C_TX_SEND_EMPTY_INT_RAW_S 12
/* I2C_RX_REC_FULL_INT_RAW : RO ;bitpos:[11] ;defa... | 1,554 |
when
I2C sends the START bit it will produce trans_start_int interrupt.*/
#define I2C_TRANS_START_INT_RAW (BIT(9))
#define I2C_TRANS_START_INT_RAW_M (BIT(9))
#define I2C_TRANS_START_INT_RAW_V 0x1
#define I2C_TRANS_START_INT_RAW_S 9
/* I2C_TIME_OUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: The ra... | 1,554 |
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