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when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/
#define I2C_MASTER_TRAN_COMP_INT_RAW (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1
#define I2C_MASTER_TRAN_COMP_INT_RAW_S 6
/* I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:... | 1,554 |
when
I2C deals with the END command it will produce end_detect_int interrupt.*/
#define I2C_END_DETECT_INT_RAW (BIT(3))
#define I2C_END_DETECT_INT_RAW_M (BIT(3))
#define I2C_END_DETECT_INT_RAW_V 0x1
#define I2C_END_DETECT_INT_RAW_S 3
/* I2C_RXFIFO_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: ... | 1,554 |
*/
#define I2C_RXFIFO_FULL_INT_RAW (BIT(0))
#define I2C_RXFIFO_FULL_INT_RAW_M (BIT(0))
#define I2C_RXFIFO_FULL_INT_RAW_V 0x1
#define I2C_RXFIFO_FULL_INT_RAW_S 0
#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x0024)
/* I2C_TX_SEND_EMPTY_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
/*description: Set this ... | 1,554 |
*/
#define I2C_TRANS_START_INT_CLR (BIT(9))
#define I2C_TRANS_START_INT_CLR_M (BIT(9))
#define I2C_TRANS_START_INT_CLR_V 0x1
#define I2C_TRANS_START_INT_CLR_S 9
/* I2C_TIME_OUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
/*description: Set this bit to clear the time_out_int interrupt.*/
#define I2C_TIME_OUT_INT_CL... | 1,554 |
*/
#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5))
#define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5))
#define I2C_ARBITRATION_LOST_INT_CLR_V 0x1
#define I2C_ARBITRATION_LOST_INT_CLR_S 5
/* I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
/*description: Set this bit to clear the slave_tran_comp_int interr... | 1,554 |
*/
#define I2C_TXFIFO_EMPTY_INT_CLR (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_CLR_M (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_CLR_V 0x1
#define I2C_TXFIFO_EMPTY_INT_CLR_S 1
/* I2C_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to clear the rxfifo_full_int interrupt.*/
#define I2C_RXFIF... | 1,554 |
*/
#define I2C_ACK_ERR_INT_ENA (BIT(10))
#define I2C_ACK_ERR_INT_ENA_M (BIT(10))
#define I2C_ACK_ERR_INT_ENA_V 0x1
#define I2C_ACK_ERR_INT_ENA_S 10
/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: The enable bit for trans_start_int interrupt.*/
#define I2C_TRANS_START_INT_ENA (BIT(9)... | 1,554 |
*/
#define I2C_MASTER_TRAN_COMP_INT_ENA (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1
#define I2C_MASTER_TRAN_COMP_INT_ENA_S 6
/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: The enable bit for arbitration_lost_int interrupt.... | 1,554 |
*/
#define I2C_RXFIFO_OVF_INT_ENA (BIT(2))
#define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2))
#define I2C_RXFIFO_OVF_INT_ENA_V 0x1
#define I2C_RXFIFO_OVF_INT_ENA_S 2
/* I2C_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The enable bit for txfifo_empty_int interrupt.*/
#define I2C_TXFIFO_EMPTY_INT_... | 1,554 |
*/
#define I2C_RX_REC_FULL_INT_ST (BIT(11))
#define I2C_RX_REC_FULL_INT_ST_M (BIT(11))
#define I2C_RX_REC_FULL_INT_ST_V 0x1
#define I2C_RX_REC_FULL_INT_ST_S 11
/* I2C_ACK_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: The masked interrupt status for ack_err_int interrupt.*/
#define I2C_ACK_ERR_INT_... | 1,554 |
*/
#define I2C_TRANS_COMPLETE_INT_ST (BIT(7))
#define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7))
#define I2C_TRANS_COMPLETE_INT_ST_V 0x1
#define I2C_TRANS_COMPLETE_INT_ST_S 7
/* I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The masked interrupt status for master_tran_comp_int interrupt.*... | 1,554 |
*/
#define I2C_END_DETECT_INT_ST (BIT(3))
#define I2C_END_DETECT_INT_ST_M (BIT(3))
#define I2C_END_DETECT_INT_ST_V 0x1
#define I2C_END_DETECT_INT_ST_S 3
/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: The masked interrupt status for rxfifo_ovf_int interrupt.*/
#define I2C_RXFIFO_OVF_INT... | 1,554 |
*/
#define I2C_SDA_HOLD_TIME 0x000003FF
#define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S))
#define I2C_SDA_HOLD_TIME_V 0x3FF
#define I2C_SDA_HOLD_TIME_S 0
#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x0034)
/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
/*desc... | 1,554 |
*/
#define I2C_SCL_START_HOLD_TIME 0x000003FF
#define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S))
#define I2C_SCL_START_HOLD_TIME_V 0x3FF
#define I2C_SCL_START_HOLD_TIME_S 0
#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x0044)
/* I2C_SCL_RSTART_SETUP_TIME... | 1,554 |
*/
#define I2C_SCL_STOP_SETUP_TIME 0x000003FF
#define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S))
#define I2C_SCL_STOP_SETUP_TIME_V 0x3FF
#define I2C_SCL_STOP_SETUP_TIME_S 0
#define I2C_SCL_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0050)
/* I2C_SCL_FILTER_EN : R/W ;bi... | 1,554 |
*/
#define I2C_SDA_FILTER_EN (BIT(3))
#define I2C_SDA_FILTER_EN_M (BIT(3))
#define I2C_SDA_FILTER_EN_V 0x1
#define I2C_SDA_FILTER_EN_S 3
/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: When input SCL's pulse width is smaller than this register value
I2C ignores this pulse.*/
#define... | 1,554 |
4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND0 0x00003FFF
#define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S))
#define I2C_COMMAND0_V 0x3FFF
#define I2C_COMMAND0_S 0
#def... | 1,554 |
*/
#define I2C_COMMAND1 0x00003FFF
#define I2C_COMMAND1_M ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S))
#define I2C_COMMAND1_V 0x3FFF
#define I2C_COMMAND1_S 0
#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x0060)
/* I2C_COMMAND2_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command2 is done in I2C ... | 1,554 |
*/
#define I2C_COMMAND3_DONE (BIT(31))
#define I2C_COMMAND3_DONE_M (BIT(31))
#define I2C_COMMAND3_DONE_V 0x1
#define I2C_COMMAND3_DONE_S 31
/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command3. It consists of three part. op_code
is the command 0: RSTART 1: WRI... | 1,554 |
It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND4 0x00003FFF
#define I2C_COMMAND4_M ((I2C_... | 1,554 |
ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND5 0x00003FFF
#define I2C_COMMAND5_M ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S))
#define I2C_COMMAND5_V 0x3FFF
#define I2C_COMMAND5_S 0
#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x0070)
/* I2C_COMMAND6_DONE : R/W ;bitpos... | 1,554 |
*/
#define I2C_COMMAND7_DONE (BIT(31))
#define I2C_COMMAND7_DONE_M (BIT(31))
#define I2C_COMMAND7_DONE_V 0x1
#define I2C_COMMAND7_DONE_S 31
/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command7. It consists of three part. op_code
is the command 0: RSTART 1: WRI... | 1,554 |
It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND8 0x00003FFF
#define I2C_COMMAND8_M ((I2C_... | 1,554 |
ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND9 0x00003FFF
#define I2C_COMMAND9_M ((I2C_COMMAND9_V)<<(I2C_COMMAND9_S))
#define I2C_COMMAND9_V 0x3FFF
#define I2C_COMMAND9_S 0
#define I2C_COMD10_REG(i) (REG_I2C_BASE(i) + 0x0080)
/* I2C_COMMAND10_DONE : R/W ;bitp... | 1,554 |
*/
#define I2C_COMMAND11_DONE (BIT(31))
#define I2C_COMMAND11_DONE_M (BIT(31))
#define I2C_COMMAND11_DONE_V 0x1
#define I2C_COMMAND11_DONE_S 31
/* I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command11. It consists of three part.
op_code is the command 0: RSTART ... | 1,554 |
It consists of three part.
op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND12 0x00003FFF
#define I2C_COMMAND12_M ((I2... | 1,554 |
ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND13 0x00003FFF
#define I2C_COMMAND13_M ((I2C_COMMAND13_V)<<(I2C_COMMAND13_S))
#define I2C_COMMAND13_V 0x3FFF
#define I2C_COMMAND13_S 0
#define I2C_COMD14_REG(i) (REG_I2C_BASE(i) + 0x0090)
/* I2C_COMMAND14_DONE : R/W... | 1,554 |
*/
#define I2C_COMMAND15_DONE (BIT(31))
#define I2C_COMMAND15_DONE_M (BIT(31))
#define I2C_COMMAND15_DONE_V 0x1
#define I2C_COMMAND15_DONE_S 31
/* I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command15. It consists of three part.
op_code is the command 0: RSTART ... | 1,554 |
*/
#define RTC_IO_PDAC1_DAC 0x000000FF
#define RTC_IO_PDAC1_DAC_M ((RTC_IO_PDAC1_DAC_V)<<(RTC_IO_PDAC1_DAC_S))
#define RTC_IO_PDAC1_DAC_V 0xFF
#define RTC_IO_PDAC1_DAC_S 19
/* RTC_IO_PDAC1_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */
/*description: Power on DAC1. Usually we need to tristate PDAC1 if we power
on... | 1,555 |
Usually we need to tristate PDAC1 if we power
on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/
#define RTC_IO_PDAC1_DAC_XPD_FORCE (BIT(10))
#define RTC_IO_PDAC1_DAC_XPD_FORCE_M (BIT(10))
#define RTC_IO_PDAC1_DAC_XPD_FORCE_V 0x1
#define RTC_IO_PDAC1_DAC_XPD_FORCE_S 10
#define RTC_IO_PAD_DAC2_REG (DR_REG_RTCI... | 1,555 |
*/
#define RTC_IO_PDAC2_DAC 0x000000FF
#define RTC_IO_PDAC2_DAC_M ((RTC_IO_PDAC2_DAC_V)<<(RTC_IO_PDAC2_DAC_S))
#define RTC_IO_PDAC2_DAC_V 0xFF
#define RTC_IO_PDAC2_DAC_S 19
/* RTC_IO_PDAC2_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */
/*description: Power on DAC2. Usually we need to tristate PDAC1 if we power
on... | 1,555 |
Usually we need to tristate PDAC2 if we power
on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/
#define RTC_IO_PDAC2_DAC_XPD_FORCE (BIT(10))
#define RTC_IO_PDAC2_DAC_XPD_FORCE_M (BIT(10))
#define RTC_IO_PDAC2_DAC_XPD_FORCE_V 0x1
#define RTC_IO_PDAC2_DAC_XPD_FORCE_S 10
#define RTC_IO_XTAL_32K_PAD_REG (DR_REG_... | 1,555 |
*/
#define RTC_IO_DAC_XTAL_32K 0x00000003
#define RTC_IO_DAC_XTAL_32K_M ((RTC_IO_DAC_XTAL_32K_V)<<(RTC_IO_DAC_XTAL_32K_S))
#define RTC_IO_DAC_XTAL_32K_V 0x3
#define RTC_IO_DAC_XTAL_32K_S 20
/* RTC_IO_XPD_XTAL_32K : R/W ;bitpos:[19] ;default: 1'd0 ; */
/*description: Power up 32kHz crystal oscillator*/
#define RTC_I... | 1,555 |
*/
#define RTC_IO_DRES_XTAL_32K 0x00000003
#define RTC_IO_DRES_XTAL_32K_M ((RTC_IO_DRES_XTAL_32K_V)<<(RTC_IO_DRES_XTAL_32K_S))
#define RTC_IO_DRES_XTAL_32K_V 0x3
#define RTC_IO_DRES_XTAL_32K_S 3
/* RTC_IO_DBIAS_XTAL_32K : R/W ;bitpos:[2:1] ;default: 2'b00 ; */
/*description: 32K XTAL self-bias reference control.*/
... | 1,555 |
*/
#define RTC_IO_TOUCH_DREFL 0x00000003
#define RTC_IO_TOUCH_DREFL_M ((RTC_IO_TOUCH_DREFL_V)<<(RTC_IO_TOUCH_DREFL_S))
#define RTC_IO_TOUCH_DREFL_V 0x3
#define RTC_IO_TOUCH_DREFL_S 27
/* RTC_IO_TOUCH_DRANGE : R/W ;bitpos:[26:25] ;default: 2'b11 ; */
/*description: touch sensor saw wave voltage range.*/
#define RTC_... | 1,555 |
3-bit for each touch panel default 100.*/
#define RTC_IO_TOUCH_PAD0_DAC 0x00000007
#define RTC_IO_TOUCH_PAD0_DAC_M ((RTC_IO_TOUCH_PAD0_DAC_V)<<(RTC_IO_TOUCH_PAD0_DAC_S))
#define RTC_IO_TOUCH_PAD0_DAC_V 0x7
#define RTC_IO_TOUCH_PAD0_DAC_S 23
/* RTC_IO_TOUCH_PAD0_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*descr... | 1,555 |
3-bit for each touch panel default 100.*/
#define RTC_IO_TOUCH_PAD1_DAC 0x00000007
#define RTC_IO_TOUCH_PAD1_DAC_M ((RTC_IO_TOUCH_PAD1_DAC_V)<<(RTC_IO_TOUCH_PAD1_DAC_S))
#define RTC_IO_TOUCH_PAD1_DAC_V 0x7
#define RTC_IO_TOUCH_PAD1_DAC_S 23
/* RTC_IO_TOUCH_PAD1_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*descr... | 1,555 |
GPIO0*/
#define RTC_IO_TOUCH_PAD1_TO_GPIO (BIT(12))
#define RTC_IO_TOUCH_PAD1_TO_GPIO_M (BIT(12))
#define RTC_IO_TOUCH_PAD1_TO_GPIO_V 0x1
#define RTC_IO_TOUCH_PAD1_TO_GPIO_S 12
#define RTC_IO_TOUCH_PAD2_REG (DR_REG_RTCIO_BASE + 0x9c)
/* RTC_IO_TOUCH_PAD2_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
/*descr... | 1,555 |
3-bit for each touch panel default 100.*/
#define RTC_IO_TOUCH_PAD2_DAC 0x00000007
#define RTC_IO_TOUCH_PAD2_DAC_M ((RTC_IO_TOUCH_PAD2_DAC_V)<<(RTC_IO_TOUCH_PAD2_DAC_S))
#define RTC_IO_TOUCH_PAD2_DAC_V 0x7
#define RTC_IO_TOUCH_PAD2_DAC_S 23
/* RTC_IO_TOUCH_PAD2_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*descr... | 1,555 |
GPIO2*/
#define RTC_IO_TOUCH_PAD2_TO_GPIO (BIT(12))
#define RTC_IO_TOUCH_PAD2_TO_GPIO_M (BIT(12))
#define RTC_IO_TOUCH_PAD2_TO_GPIO_V 0x1
#define RTC_IO_TOUCH_PAD2_TO_GPIO_S 12
#define RTC_IO_TOUCH_PAD3_REG (DR_REG_RTCIO_BASE + 0xa0)
/* RTC_IO_TOUCH_PAD3_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
/*descr... | 1,555 |
3-bit for each touch panel default 100.*/
#define RTC_IO_TOUCH_PAD3_DAC 0x00000007
#define RTC_IO_TOUCH_PAD3_DAC_M ((RTC_IO_TOUCH_PAD3_DAC_V)<<(RTC_IO_TOUCH_PAD3_DAC_S))
#define RTC_IO_TOUCH_PAD3_DAC_V 0x7
#define RTC_IO_TOUCH_PAD3_DAC_S 23
/* RTC_IO_TOUCH_PAD3_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*descr... | 1,555 |
MTDO*/
#define RTC_IO_TOUCH_PAD3_TO_GPIO (BIT(12))
#define RTC_IO_TOUCH_PAD3_TO_GPIO_M (BIT(12))
#define RTC_IO_TOUCH_PAD3_TO_GPIO_V 0x1
#define RTC_IO_TOUCH_PAD3_TO_GPIO_S 12
#define RTC_IO_TOUCH_PAD4_REG (DR_REG_RTCIO_BASE + 0xa4)
/* RTC_IO_TOUCH_PAD4_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
/*descri... | 1,555 |
3-bit for each touch panel default 100.*/
#define RTC_IO_TOUCH_PAD4_DAC 0x00000007
#define RTC_IO_TOUCH_PAD4_DAC_M ((RTC_IO_TOUCH_PAD4_DAC_V)<<(RTC_IO_TOUCH_PAD4_DAC_S))
#define RTC_IO_TOUCH_PAD4_DAC_V 0x7
#define RTC_IO_TOUCH_PAD4_DAC_S 23
/* RTC_IO_TOUCH_PAD4_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*descr... | 1,555 |
MTCK*/
#define RTC_IO_TOUCH_PAD4_TO_GPIO (BIT(12))
#define RTC_IO_TOUCH_PAD4_TO_GPIO_M (BIT(12))
#define RTC_IO_TOUCH_PAD4_TO_GPIO_V 0x1
#define RTC_IO_TOUCH_PAD4_TO_GPIO_S 12
#define RTC_IO_TOUCH_PAD5_REG (DR_REG_RTCIO_BASE + 0xa8)
/* RTC_IO_TOUCH_PAD5_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
/*descri... | 1,555 |
3-bit for each touch panel default 100.*/
#define RTC_IO_TOUCH_PAD5_DAC 0x00000007
#define RTC_IO_TOUCH_PAD5_DAC_M ((RTC_IO_TOUCH_PAD5_DAC_V)<<(RTC_IO_TOUCH_PAD5_DAC_S))
#define RTC_IO_TOUCH_PAD5_DAC_V 0x7
#define RTC_IO_TOUCH_PAD5_DAC_S 23
/* RTC_IO_TOUCH_PAD5_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*descr... | 1,555 |
MTDI*/
#define RTC_IO_TOUCH_PAD5_TO_GPIO (BIT(12))
#define RTC_IO_TOUCH_PAD5_TO_GPIO_M (BIT(12))
#define RTC_IO_TOUCH_PAD5_TO_GPIO_V 0x1
#define RTC_IO_TOUCH_PAD5_TO_GPIO_S 12
#define RTC_IO_TOUCH_PAD6_REG (DR_REG_RTCIO_BASE + 0xac)
/* RTC_IO_TOUCH_PAD6_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
/*descri... | 1,555 |
3-bit for each touch panel default 100.*/
#define RTC_IO_TOUCH_PAD6_DAC 0x00000007
#define RTC_IO_TOUCH_PAD6_DAC_M ((RTC_IO_TOUCH_PAD6_DAC_V)<<(RTC_IO_TOUCH_PAD6_DAC_S))
#define RTC_IO_TOUCH_PAD6_DAC_V 0x7
#define RTC_IO_TOUCH_PAD6_DAC_S 23
/* RTC_IO_TOUCH_PAD6_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*descr... | 1,555 |
MTMS*/
#define RTC_IO_TOUCH_PAD6_TO_GPIO (BIT(12))
#define RTC_IO_TOUCH_PAD6_TO_GPIO_M (BIT(12))
#define RTC_IO_TOUCH_PAD6_TO_GPIO_V 0x1
#define RTC_IO_TOUCH_PAD6_TO_GPIO_S 12
#define RTC_IO_TOUCH_PAD7_REG (DR_REG_RTCIO_BASE + 0xb0)
/* RTC_IO_TOUCH_PAD7_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
/*descri... | 1,555 |
3-bit for each touch panel default 100.*/
#define RTC_IO_TOUCH_PAD7_DAC 0x00000007
#define RTC_IO_TOUCH_PAD7_DAC_M ((RTC_IO_TOUCH_PAD7_DAC_V)<<(RTC_IO_TOUCH_PAD7_DAC_S))
#define RTC_IO_TOUCH_PAD7_DAC_V 0x7
#define RTC_IO_TOUCH_PAD7_DAC_S 23
/* RTC_IO_TOUCH_PAD7_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*descr... | 1,555 |
GPIO27*/
#define RTC_IO_TOUCH_PAD7_TO_GPIO (BIT(12))
#define RTC_IO_TOUCH_PAD7_TO_GPIO_M (BIT(12))
#define RTC_IO_TOUCH_PAD7_TO_GPIO_V 0x1
#define RTC_IO_TOUCH_PAD7_TO_GPIO_S 12
#define RTC_IO_TOUCH_PAD8_REG (DR_REG_RTCIO_BASE + 0xb4)
/* RTC_IO_TOUCH_PAD8_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
/*de... | 1,555 |
*/
#define RTC_IO_TOUCH_PAD8_TIE_OPT (BIT(21))
#define RTC_IO_TOUCH_PAD8_TIE_OPT_M (BIT(21))
#define RTC_IO_TOUCH_PAD8_TIE_OPT_V 0x1
#define RTC_IO_TOUCH_PAD8_TIE_OPT_S 21
/* RTC_IO_TOUCH_PAD8_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
/*description: touch sensor power on.*/
#define RTC_IO_TOUCH_PAD8_XPD (BIT(20))... | 1,555 |
*/
#define RTC_IO_TOUCH_PAD9_START (BIT(22))
#define RTC_IO_TOUCH_PAD9_START_M (BIT(22))
#define RTC_IO_TOUCH_PAD9_START_V 0x1
#define RTC_IO_TOUCH_PAD9_START_S 22
/* RTC_IO_TOUCH_PAD9_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
/*description: default touch sensor tie option. 0: tie low 1: tie high.*/
#define R... | 1,555 |
..Ò17Ó select GPIO17*/
#define RTC_IO_EXT_WAKEUP0_SEL 0x0000001F
#define RTC_IO_EXT_WAKEUP0_SEL_M ((RTC_IO_EXT_WAKEUP0_SEL_V)<<(RTC_IO_EXT_WAKEUP0_SEL_S))
#define RTC_IO_EXT_WAKEUP0_SEL_V 0x1F
#define RTC_IO_EXT_WAKEUP0_SEL_S 27
#define RTC_IO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0xc0)
/* RTC_IO_XTL_EXT_C... | 1,555 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef struct pcnt_dev_t {
volatile struct {
union {
struct {
uint32_t filter_thres: 10; /*This register is used to filter pulse whose width is smaller than this value for unit0.*/
u... | 1,556 |
*/
uint32_t ch0_neg_mode: 2; /*This register is used to control the mode of channel0's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
uint32_t ch0_pos_mode: 2; /*This ... | 1,556 |
2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
uint32_t ch1_pos_mode: 2; /*This register is used to control the mode of channel1's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease... | 1,556 |
*/
uint32_t cnt_thres1: 16; /*This register is used to configure thres1 value for unit0.*/
};
uint32_t val;
} conf1;
union {
struct {
uint32_t cnt_h_lim: 16; /*This register is used to configure thr_h_lim value fo... | 1,556 |
*/
uint32_t cnt_thr_event_u2: 1; /*This is the interrupt raw bit for channel2 event.*/
uint32_t cnt_thr_event_u3: 1; /*This is the interrupt raw bit for channel3 event.*/
uint32_t cnt_thr_event_u4: 1; /*This is the interrupt raw bit for channel4 event.*/... | 1,556 |
*/
uint32_t cnt_thr_event_u3: 1; /*This is the interrupt status bit for channel3 event.*/
uint32_t cnt_thr_event_u4: 1; /*This is the interrupt status bit for channel4 event.*/
uint32_t cnt_thr_event_u5: 1; /*This is the interrupt status bit for ch... | 1,556 |
*/
uint32_t cnt_thr_event_u3: 1; /*This is the interrupt enable bit for channel3 event.*/
uint32_t cnt_thr_event_u4: 1; /*This is the interrupt enable bit for channel4 event.*/
uint32_t cnt_thr_event_u5: 1; /*This is the interrupt enable bit for chann... | 1,556 |
*/
uint32_t cnt_thr_event_u4: 1; /*Set this bit to clear channel4 event interrupt.*/
uint32_t cnt_thr_event_u5: 1; /*Set this bit to clear channel5 event interrupt.*/
uint32_t cnt_thr_event_u6: 1; /*Set this bit to clear channel6 event interrupt.*/
... | 1,556 |
*/
uint32_t cnt_pause_u0: 1; /*Set this bit to pause unit0's counter.*/
uint32_t cnt_rst_u1: 1; /*Set this bit to clear unit1's counter.*/
uint32_t cnt_pause_u1: 1; /*Set this bit to pause unit1's counter.*/
uint32_t cnt_rst_u2:... | 1,556 |
*/
uint32_t cnt_rst_u6: 1; /*Set this bit to clear unit6's counter.*/
uint32_t cnt_pause_u6: 1; /*Set this bit to pause unit6's counter.*/
uint32_t cnt_rst_u7: 1; /*Set this bit to clear unit7's counter.*/
uint32_t cnt_pause_u... | 1,556 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
typedef struct emac_ext_dev_s {
volatile union {
struct {
uint32_t div_num : 4;
uint32_t h_div_num : 4;
uint32_t dly_num : 2;
uint32_t reserved10 : 22;
};
uint32_t val;
... | 1,558 |
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 1,559 |
Boot_sel_dig[7:1]: {U0RXD SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3} . vsdio_boot_sel: MTDI. boot_sel_chip[5:0]: {GPIO0 U0TXD GPIO2 GPIO4 MTDO GPIO5} */
uint32_t reserved16:16;
};
uint32_t val;
} strap;
uint32_t in; /*GPIO0~31... | 1,559 |
if GPIO_FUNC0_OUT_SEL is 256 or GPIO_FUNC0_OEN_SEL is 1 using GPIO_ENABLE_DATA[x] for the enable value else using the signal enable*/
};
uint32_t val;
} func_out_sel_cfg[40];
} gpio_dev_t;
extern gpio_dev_t GPIO;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_GPIO_STRUCT_H_ */
| 1,559 |
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 1,560 |
*/
#define UART_RXFIFO_RD_BYTE 0x000000FF
#define UART_RXFIFO_RD_BYTE_M ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S))
#define UART_RXFIFO_RD_BYTE_V 0xFF
#define UART_RXFIFO_RD_BYTE_S 0
#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)
/* UART_AT_CMD_CHAR_DET_INT_RAW : RO ;bitpos:[18] ;default: 1'b... | 1,560 |
*/
#define UART_RS485_FRM_ERR_INT_RAW (BIT(16))
#define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16))
#define UART_RS485_FRM_ERR_INT_RAW_V 0x1
#define UART_RS485_FRM_ERR_INT_RAW_S 16
/* UART_RS485_PARITY_ERR_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
/*description: This interrupt raw bit turns to high level when rs485 ... | 1,560 |
*/
#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13))
#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (BIT(13))
#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x1
#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13
/* UART_TX_BRK_DONE_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
/*description: This interrupt raw bit turns to high level when... | 1,560 |
*/
#define UART_SW_XOFF_INT_RAW (BIT(10))
#define UART_SW_XOFF_INT_RAW_M (BIT(10))
#define UART_SW_XOFF_INT_RAW_V 0x1
#define UART_SW_XOFF_INT_RAW_S 10
/* UART_SW_XON_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: This interrupt raw bit turns to high level when receiver receives
xoff char with uart_sw... | 1,560 |
*/
#define UART_BRK_DET_INT_RAW (BIT(7))
#define UART_BRK_DET_INT_RAW_M (BIT(7))
#define UART_BRK_DET_INT_RAW_V 0x1
#define UART_BRK_DET_INT_RAW_S 7
/* UART_CTS_CHG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: This interrupt raw bit turns to high level when receiver detects
the edge change of ctsn s... | 1,560 |
*/
#define UART_FRM_ERR_INT_RAW (BIT(3))
#define UART_FRM_ERR_INT_RAW_M (BIT(3))
#define UART_FRM_ERR_INT_RAW_V 0x1
#define UART_FRM_ERR_INT_RAW_S 3
/* UART_PARITY_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: This interrupt raw bit turns to high level when receiver detects
the parity error of da... | 1,560 |
*/
#define UART_RXFIFO_FULL_INT_RAW (BIT(0))
#define UART_RXFIFO_FULL_INT_RAW_M (BIT(0))
#define UART_RXFIFO_FULL_INT_RAW_V 0x1
#define UART_RXFIFO_FULL_INT_RAW_S 0
#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8)
/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
/*description: This ... | 1,560 |
*/
#define UART_RS485_FRM_ERR_INT_ST (BIT(16))
#define UART_RS485_FRM_ERR_INT_ST_M (BIT(16))
#define UART_RS485_FRM_ERR_INT_ST_V 0x1
#define UART_RS485_FRM_ERR_INT_ST_S 16
/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
/*description: This is the status bit for rs485_parity_err_int_raw when rs... | 1,560 |
*/
#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13))
#define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13))
#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x1
#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13
/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
/*description: This is the status bit for tx_brk_done_int_raw when ... | 1,560 |
*/
#define UART_SW_XON_INT_ST (BIT(9))
#define UART_SW_XON_INT_ST_M (BIT(9))
#define UART_SW_XON_INT_ST_V 0x1
#define UART_SW_XON_INT_ST_S 9
/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena
is set to 1.*/
#define ... | 1,560 |
*/
#define UART_DSR_CHG_INT_ST (BIT(5))
#define UART_DSR_CHG_INT_ST_M (BIT(5))
#define UART_DSR_CHG_INT_ST_V 0x1
#define UART_DSR_CHG_INT_ST_S 5
/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena
is set to 1.*/
#define... | 1,560 |
*/
#define UART_TXFIFO_EMPTY_INT_ST (BIT(1))
#define UART_TXFIFO_EMPTY_INT_ST_M (BIT(1))
#define UART_TXFIFO_EMPTY_INT_ST_V 0x1
#define UART_TXFIFO_EMPTY_INT_ST_S 1
/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena
... | 1,560 |
*/
#define UART_RS485_CLASH_INT_ENA (BIT(17))
#define UART_RS485_CLASH_INT_ENA_M (BIT(17))
#define UART_RS485_CLASH_INT_ENA_V 0x1
#define UART_RS485_CLASH_INT_ENA_S 17
/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: This is the enable bit for rs485_parity_err_int_st register.*/
#... | 1,560 |
*/
#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13))
#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (BIT(13))
#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x1
#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13
/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: This is the enable bit for tx_brk_done_int_st ... | 1,560 |
*/
#define UART_SW_XON_INT_ENA (BIT(9))
#define UART_SW_XON_INT_ENA_M (BIT(9))
#define UART_SW_XON_INT_ENA_V 0x1
#define UART_SW_XON_INT_ENA_S 9
/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: This is the enable bit for rxfifo_tout_int_st register.*/
#define UART_RXFIFO_TOUT_INT_ENA... | 1,560 |
*/
#define UART_DSR_CHG_INT_ENA (BIT(5))
#define UART_DSR_CHG_INT_ENA_M (BIT(5))
#define UART_DSR_CHG_INT_ENA_V 0x1
#define UART_DSR_CHG_INT_ENA_S 5
/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: This is the enable bit for rxfifo_ovf_int_st register.*/
#define UART_RXFIFO_OVF_INT_EN... | 1,560 |
*/
#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1))
#define UART_TXFIFO_EMPTY_INT_ENA_M (BIT(1))
#define UART_TXFIFO_EMPTY_INT_ENA_V 0x1
#define UART_TXFIFO_EMPTY_INT_ENA_S 1
/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: This is the enable bit for rxfifo_full_int_st register.*/
#define ... | 1,560 |
*/
#define UART_RS485_CLASH_INT_CLR (BIT(17))
#define UART_RS485_CLASH_INT_CLR_M (BIT(17))
#define UART_RS485_CLASH_INT_CLR_V 0x1
#define UART_RS485_CLASH_INT_CLR_S 17
/* UART_RS485_FRM_ERR_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
/*description: Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
#def... | 1,560 |
*/
#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13))
#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (BIT(13))
#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x1
#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13
/* UART_TX_BRK_DONE_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
/*description: Set this bit to clear the tx_brk_done_int_raw i... | 1,560 |
*/
#define UART_SW_XON_INT_CLR (BIT(9))
#define UART_SW_XON_INT_CLR_M (BIT(9))
#define UART_SW_XON_INT_CLR_V 0x1
#define UART_SW_XON_INT_CLR_S 9
/* UART_RXFIFO_TOUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
/*description: Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
#define UART_RXFIFO_TOUT_INT_CLR... | 1,560 |
*/
#define UART_DSR_CHG_INT_CLR (BIT(5))
#define UART_DSR_CHG_INT_CLR_M (BIT(5))
#define UART_DSR_CHG_INT_CLR_V 0x1
#define UART_DSR_CHG_INT_CLR_S 5
/* UART_RXFIFO_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
/*description: Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
#define UART_RXFIFO_OVF_INT_CLR (... | 1,560 |
*/
#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1))
#define UART_TXFIFO_EMPTY_INT_CLR_M (BIT(1))
#define UART_TXFIFO_EMPTY_INT_CLR_V 0x1
#define UART_TXFIFO_EMPTY_INT_CLR_S 1
/* UART_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to clear the rxfifo_full_int_raw interrupt.*/
#define ... | 1,560 |
*/
#define UART_CLKDIV 0x000FFFFF
#define UART_CLKDIV_M ((UART_CLKDIV_V)<<(UART_CLKDIV_S))
#define UART_CLKDIV_V 0xFFFFF
#define UART_CLKDIV_S 0
#define UART_AUTOBAUD_REG(i) (REG_UART_BASE(i) + 0x18)
/* UART_GLITCH_FILT : R/W ;bitpos:[15:8] ;default: 8'h10 ; */
/*description: when input pulse width is low... | 1,560 |
*/
#define UART_TXD (BIT(31))
#define UART_TXD_M (BIT(31))
#define UART_TXD_V 0x1
#define UART_TXD_S 31
/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b0 ; */
/*description: This register represent the level value of the internal uart cts signal.*/
#define UART_RTSN (BIT(30))
#define UART_RTSN_M (BIT(30))
#define UAR... | 1,560 |
tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/
#define UART_TXFIFO_CNT 0x000000FF
#define UART_TXFIFO_CNT_M ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S))
#define UART_TXFIFO_CNT_V 0xFF
#define UART_TXFIFO_CNT_S 16
/* UART_RXD : RO ;bitpos:[15] ;default: 1'b0 ; */
/*des... | 1,560 |
0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/
#define UART_ST_URX_OUT 0x0000000F
#define UART_ST_URX_OUT_M ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S))
#define UART_ST_URX_OUT_V 0xF
#define UART_ST_URX_OU... | 1,560 |
receiver stops storing data int fifo when data is wrong.
0.receiver stores the data even if the received data is wrong.*/
#define UART_ERR_WR_MASK (BIT(26))
#define UART_ERR_WR_MASK_M (BIT(26))
#define UART_ERR_WR_MASK_V 0x1
#define UART_ERR_WR_MASK_S 26
/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */
/*des... | 1,560 |
*/
#define UART_TXD_INV (BIT(22))
#define UART_TXD_INV_M (BIT(22))
#define UART_TXD_INV_V 0x1
#define UART_TXD_INV_S 22
/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */
/*description: Set this bit to inverse the level value of uart dsr signal.*/
#define UART_DSR_INV (BIT(21))
#define UART_DSR_INV_M (BIT(21)... | 1,560 |
*/
#define UART_TXFIFO_RST (BIT(18))
#define UART_TXFIFO_RST_M (BIT(18))
#define UART_TXFIFO_RST_V 0x1
#define UART_TXFIFO_RST_S 18
/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */
/*description: Set this bit to reset uart receiver's fifo.*/
#define UART_RXFIFO_RST (BIT(17))
#define UART_RXFIFO_RST_M (BI... | 1,560 |
*/
#define UART_LOOPBACK (BIT(14))
#define UART_LOOPBACK_M (BIT(14))
#define UART_LOOPBACK_V 0x1
#define UART_LOOPBACK_S 14
/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: Set this bit to inverse the level value of irda receiver's level.*/
#define UART_IRDA_RX_INV (BIT(13))
#define UART_I... | 1,560 |
*/
#define UART_IRDA_TX_EN (BIT(10))
#define UART_IRDA_TX_EN_M (BIT(10))
#define UART_IRDA_TX_EN_V 0x1
#define UART_IRDA_TX_EN_S 10
/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: Set this bit to enable irda loopback mode.*/
#define UART_IRDA_DPLX (BIT(9))
#define UART_IRDA_DPLX_M (BIT(9))
... | 1,560 |
*/
#define UART_SW_RTS (BIT(6))
#define UART_SW_RTS_M (BIT(6))
#define UART_SW_RTS_V 0x1
#define UART_SW_RTS_S 6
/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */
/*description: This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/
#define UART_STOP_BIT_NUM 0x00000003
#defin... | 1,560 |
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