text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
*/
#define I2C_MST_I2C1_STATUS 0x000000FFU
#define I2C_MST_I2C1_STATUS_M (I2C_MST_I2C1_STATUS_V << I2C_MST_I2C1_STATUS_S)
#define I2C_MST_I2C1_STATUS_V 0x000000FFU
#define I2C_MST_I2C1_STATUS_S 24
#define I2C_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10)
/* I2C_MST_BURST_CTRL : R/W; bitpos: [31:0]; def... | 1,890 |
*/
#define I2C_MST_I2C_MST0_BURST_ERR_FLAG (BIT(1))
#define I2C_MST_I2C_MST0_BURST_ERR_FLAG_M (I2C_MST_I2C_MST0_BURST_ERR_FLAG_V << I2C_MST_I2C_MST0_BURST_ERR_FLAG_S)
#define I2C_MST_I2C_MST0_BURST_ERR_FLAG_V 0x00000001U
#define I2C_MST_I2C_MST0_BURST_ERR_FLAG_S 1
/* I2C_MST_I2C_MST1_BURST_ERR_FLAG : RO; bitpos: ... | 1,890 |
*/
#define I2C_MST_ANA_CONF0 0x00FFFFFFU
#define I2C_MST_ANA_CONF0_M (I2C_MST_ANA_CONF0_V << I2C_MST_ANA_CONF0_S)
#define I2C_MST_ANA_CONF0_V 0x00FFFFFFU
#define I2C_MST_ANA_CONF0_S 0
/* I2C_MST_ANA_STATUS0 : RO; bitpos: [31:24]; default: 0;*/
/* description: .*/
#define I2C_MST_ANA_STATUS0 0x000000FFU
#define... | 1,890 |
*/
#define I2C_MST_ANA_CONF2 0x00FFFFFFU
#define I2C_MST_ANA_CONF2_M (I2C_MST_ANA_CONF2_V << I2C_MST_ANA_CONF2_S)
#define I2C_MST_ANA_CONF2_V 0x00FFFFFFU
#define I2C_MST_ANA_CONF2_S 0
/* I2C_MST_ANA_STATUS2 : RO; bitpos: [31:24]; default: 0;*/
/* description: .*/
#define I2C_MST_ANA_STATUS2 0x000000FFU
#define... | 1,890 |
*/
#define I2C_MST_I2C1_SCL_PULSE_DUR 0x0000003FU
#define I2C_MST_I2C1_SCL_PULSE_DUR_M (I2C_MST_I2C1_SCL_PULSE_DUR_V << I2C_MST_I2C1_SCL_PULSE_DUR_S)
#define I2C_MST_I2C1_SCL_PULSE_DUR_V 0x0000003FU
#define I2C_MST_I2C1_SCL_PULSE_DUR_S 0
/* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;*/
/* descr... | 1,890 |
*/
#define I2C_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001FU
#define I2C_MST_HW_I2C_SDA_SIDE_GUARD_M (I2C_MST_HW_I2C_SDA_SIDE_GUARD_V << I2C_MST_HW_I2C_SDA_SIDE_GUARD_S)
#define I2C_MST_HW_I2C_SDA_SIDE_GUARD_V 0x0000001FU
#define I2C_MST_HW_I2C_SDA_SIDE_GUARD_S 6
/* I2C_MST_ARBITER_DIS : R/W; bitpos: [11]; default: 0;*/
... | 1,890 |
*/
#define I2C_MST_CLK_EN (BIT(28))
#define I2C_MST_CLK_EN_M (I2C_MST_CLK_EN_V << I2C_MST_CLK_EN_S)
#define I2C_MST_CLK_EN_V 0x00000001U
#define I2C_MST_CLK_EN_S 28
#ifdef __cplusplus
}
#endif
| 1,890 |
/*
*/
#pragma once
#define ANA_CMPR0_EXT_REF_GPIO 10 /*!< The GPIO that can be used as external reference voltage */
#define ANA_CMPR0_SRC_GPIO 11 /*!< The GPIO that used for inputting the source signal to compare */
| 1,893 |
/*
*/
#pragma once
#include
#include "soc/soc_caps.h"
#include "soc/regdma.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
*/
#define INT_MTX_RETENTION_LINK_LEN 1
extern const regdma_entries_config_t intr_matrix_regs_retention[INT_MTX_RETENTION_LINK_LEN];
/**
*/
#define HP_SYSTEM_RETENTION_LINK_LEN 1
extern co... | 1,895 |
/**
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5
#ifdef __cplusplus
}
#endif
| 1,902 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of config0 register
*/
typedef union {
struct {
uint32_t reserved_0:9;
/** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1;
*/
uint32_t wdt_pause_in_slp:1;
/** ... | 1,903 |
/*
*/
#pragma once
#include "soc/soc.h"
#include "esp32h2/rom/cache.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef union {
struct {
uint32_t cat0 : 2;
uint32_t cat1 : 2;
uint32_t cat2 : 2;
uint32_t res0 : 8;
uint32_t splitaddr : 8;
uin... | 1,905 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: memory type */
/** Group: Control/Status registers */
/** Type of set_start register
*/
typedef union {
struct {
/** set_start : WT; bitpos: [0]; default: 0;
*/
uint32_t set_start:1;
uint32_t reserv... | 1,906 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of clk_en register
*/
typedef union {
struct {
uint32_t reserved_0:24;
/** rng_ck_en : R/W; bitpos: [24]; default: 1;
*/
uint32_t rng_ck_en:1;
/** otp_dbg_ck_en... | 1,907 |
/*
*/
#ifndef _SOC_SPI_PINS_H_
#define _SOC_SPI_PINS_H_
#define SPI_FUNC_NUM 0
#define SPI_IOMUX_PIN_NUM_HD 18
#define SPI_IOMUX_PIN_NUM_CS 15
#define SPI_IOMUX_PIN_NUM_MOSI 20
#define SPI_IOMUX_PIN_NUM_CLK 19
#define SPI_IOMUX_PIN_NUM_MISO 16
#define SPI_IOMUX_PIN_NUM_WP 17
#define SPI2_FUN... | 1,908 |
/*
*/
#pragma once
/**
*/
#define I2C_BBPLL 0x66
#define I2C_BBPLL_HOSTID 0
#define I2C_BBPLL_OC_REF_DIV 2
#define I2C_BBPLL_OC_REF_DIV_MSB 3
#define I2C_BBPLL_OC_REF_DIV_LSB 0
#define I2C_BBPLL_OC_DIV 3
#define I2C_BBPLL_OC_DIV_MSB 5
#define I2C_BBPLL_OC_DIV_LSB 0
#define... | 1,909 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** TRACE_MEM_START_ADDR_REG register
*/
#define TRACE_MEM_START_ADDR_REG (DR_REG_TRACE_BASE + 0x0)
/** TRACE_MEM_STAET_ADDR : R/W; bitpos: [31:0]; default: 0;
*/
#define TRACE_MEM_STAET_ADDR 0xFFFFFFFFU
#define TRACE_MEM_... | 1,910 |
/*
*/
/*
*/
#pragma once
#include "soc/gpio_pins.h"
#include "soc/spi_pins.h"
| 1,912 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** I2S_INT_RAW_REG register
*/
#define I2S_INT_RAW_REG (DR_REG_I2S_BASE + 0xc)
/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
*/
#define I2S_RX_DONE_INT_RAW (BIT(0))
#define I2S_RX_DONE_INT_RAW_M (I2S_RX_D... | 1,914 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define XTS_AES_PLAIN_MEM(i) (REG_SPI_MEM_BASE(i) + 0x300)
/* XTS_AES_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: This field is only used to generate include file in c case. This field is useles
s. P... | 1,915 |
0: flash(default), 1: psram(reserved). Only default value can be
used..*/
#define XTS_AES_DESTINATION (BIT(0))
#define XTS_AES_DESTINATION_M (BIT(0))
#define XTS_AES_DESTINATION_V 0x1
#define XTS_AES_DESTINATION_S 0
#define XTS_AES_PHYSICAL_ADDRESS_REG(i) (REG_SPI_MEM_BASE(i) + 0x348)
/* XTS_AES_PHYSIC... | 1,915 |
This actio
n should only be asserted when manual encryption status is 0. After this action,
manual encryption status becomes 1. After calculation is done, manual encryptio
n status becomes 2..*/
#define XTS_AES_TRIGGER (BIT(0))
#define XTS_AES_TRIGGER_M (BIT(0))
#define XTS_AES_TRIGGER_V 0x1
#define XTS_AES_TRIG... | 1,915 |
After this action, manual encryption status wi
ll become 0..*/
#define XTS_AES_DESTROY (BIT(0))
#define XTS_AES_DESTROY_M (BIT(0))
#define XTS_AES_DESTROY_V 0x1
#define XTS_AES_DESTROY_S 0
#define XTS_AES_STATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x358)
/* XTS_AES_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */... | 1,915 |
0: Controlled by efuse bits..*/
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER (BIT(4))
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_M (BIT(4))
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_V 0x1
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_S 4
/* XTS_AES_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description:... | 1,915 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECC_MULT_INT_RAW_REG register
*/
#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
*/
#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0))
#define ECC... | 1,916 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: key register */
/** Type of key_0 register
*/
typedef union {
struct {
/** key_0 : R/W; bitpos: [31:0]; default: 0;
*/
uint32_t key_0:32;
};
uint32_t val;
} aes_key_0_reg_t;
/** Type of key_1 regist... | 1,917 |
/*
*/
#pragma once
#define PMU_ICG_APB_ENA_CAN0 18
#define PMU_ICG_APB_ENA_CAN1 19
#define PMU_ICG_APB_ENA_GDMA 1
#define PMU_ICG_APB_ENA_I2C 13
#define PMU_ICG_APB_ENA_I2S ... | 1,920 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Data Memory */
/** Group: Configuration registers */
/** Type of conf register
*/
typedef union {
struct {
/** work_mode : R/W; bitpos: [0]; default: 0;
*/
uint32_t work_mode:1;
/** ecc_curve : R/W;... | 1,921 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of region_filter_en register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [1:0]; default: 1;
*/
uint32_t region_filter_en:2;
uint32_t rese... | 1,924 |
/*
*/
#pragma once
#include "esp_bit_defs.h"
/* Analog function control register */
// I2C_MST_ANA_CONF0_REG
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define I2C_MST_BBPLL_CAL_DONE (BIT(24))
// I2C_MST_ANA_CONF1_REG
#define ANA_CONFIG_S (8)
#define ... | 1,926 |
/**
*/
#pragma once
#include
#include "modem/reg_base.h"
#ifdef __cplusplus
extern "C" {
#endif
#define MODEM_SYSCON_TEST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x0)
/* MODEM_SYSCON_CLK_EN : R/W; bitpos: [0]; default: 0; */
/* description: .*/
#define MODEM_SYSCON_CLK_EN (BIT(0))
#define MODEM_SYSCON_CLK_EN_M (MO... | 1,931 |
*/
#define MODEM_SYSCON_CLK_ZB_MAC_EN (BIT(23))
#define MODEM_SYSCON_CLK_ZB_MAC_EN_M (MODEM_SYSCON_CLK_ZB_MAC_EN_V << MODEM_SYSCON_CLK_ZB_MAC_EN_S)
#define MODEM_SYSCON_CLK_ZB_MAC_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_ZB_MAC_EN_S 23
/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN : R/W; bitpos: [24]; default: 0; */
/* d... | 1,931 |
*/
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN (BIT(26))
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S)
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S 26
/* MODEM_SYSCON_CLK_MODEM_SEC_APB_E... | 1,931 |
*/
#define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN (BIT(29))
#define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_M (MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_V << MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_S)
#define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_S 29
/* MODEM_SYSCON_CLK_BLE_TIMER_EN : ... | 1,931 |
*/
#define MODEM_SYSCON_CLK_ETM_FO (BIT(22))
#define MODEM_SYSCON_CLK_ETM_FO_M (MODEM_SYSCON_CLK_ETM_FO_V << MODEM_SYSCON_CLK_ETM_FO_S)
#define MODEM_SYSCON_CLK_ETM_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_ETM_FO_S 22
/* MODEM_SYSCON_CLK_ZB_FO : R/W; bitpos: [24]; default: 0; */
/* description: .*/
#define MODEM... | 1,931 |
*/
#define MODEM_SYSCON_CLK_DATA_DUMP_FO (BIT(31))
#define MODEM_SYSCON_CLK_DATA_DUMP_FO_M (MODEM_SYSCON_CLK_DATA_DUMP_FO_V << MODEM_SYSCON_CLK_DATA_DUMP_FO_S)
#define MODEM_SYSCON_CLK_DATA_DUMP_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_DATA_DUMP_FO_S 31
#define MODEM_SYSCON_MODEM_RST_CONF_REG (DR_REG_MODEM_SYSC... | 1,931 |
*/
#define MODEM_SYSCON_RST_BTMAC (BIT(16))
#define MODEM_SYSCON_RST_BTMAC_M (MODEM_SYSCON_RST_BTMAC_V << MODEM_SYSCON_RST_BTMAC_S)
#define MODEM_SYSCON_RST_BTMAC_V 0x00000001U
#define MODEM_SYSCON_RST_BTMAC_S 16
/* MODEM_SYSCON_RST_BTBB_APB : R/W; bitpos: [17]; default: 0; */
/* description: .*/
#define MODEM_SY... | 1,931 |
*/
#define MODEM_SYSCON_RST_ZBMAC (BIT(24))
#define MODEM_SYSCON_RST_ZBMAC_M (MODEM_SYSCON_RST_ZBMAC_V << MODEM_SYSCON_RST_ZBMAC_S)
#define MODEM_SYSCON_RST_ZBMAC_V 0x00000001U
#define MODEM_SYSCON_RST_ZBMAC_S 24
/* MODEM_SYSCON_RST_MODEM_ECB : R/W; bitpos: [25]; default: 0; */
/* description: .*/
#define MODEM_S... | 1,931 |
*/
#define MODEM_SYSCON_RST_MODEM_SEC (BIT(29))
#define MODEM_SYSCON_RST_MODEM_SEC_M (MODEM_SYSCON_RST_MODEM_SEC_V << MODEM_SYSCON_RST_MODEM_SEC_S)
#define MODEM_SYSCON_RST_MODEM_SEC_V 0x00000001U
#define MODEM_SYSCON_RST_MODEM_SEC_S 29
/* MODEM_SYSCON_RST_BLE_TIMER : R/W; bitpos: [30]; default: 0; */
/* descript... | 1,931 |
*/
#define MODEM_SYSCON_CLK_FE_16M_EN (BIT(12))
#define MODEM_SYSCON_CLK_FE_16M_EN_M (MODEM_SYSCON_CLK_FE_16M_EN_V << MODEM_SYSCON_CLK_FE_16M_EN_S)
#define MODEM_SYSCON_CLK_FE_16M_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_16M_EN_S 12
/* MODEM_SYSCON_CLK_FE_32M_EN : R/W; bitpos: [13]; default: 0; */
/* descript... | 1,931 |
*/
#define MODEM_SYSCON_CLK_FE_APB_EN (BIT(16))
#define MODEM_SYSCON_CLK_FE_APB_EN_M (MODEM_SYSCON_CLK_FE_APB_EN_V << MODEM_SYSCON_CLK_FE_APB_EN_S)
#define MODEM_SYSCON_CLK_FE_APB_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_APB_EN_S 16
/* MODEM_SYSCON_CLK_BT_APB_EN : R/W; bitpos: [17]; default: 0; */
/* descript... | 1,931 |
*/
#define MODEM_SYSCON_CLK_FE_FO (BIT(16))
#define MODEM_SYSCON_CLK_FE_FO_M (MODEM_SYSCON_CLK_FE_FO_V << MODEM_SYSCON_CLK_FE_FO_S)
#define MODEM_SYSCON_CLK_FE_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_FO_S 16
/* MODEM_SYSCON_CLK_BT_FO : R/W; bitpos: [18]; default: 0; */
/* description: .*/
#define MODEM_SYSCO... | 1,931 |
*/
#define MODEM_SYSCON_MODEM_MEM_RA 0x00000003U
#define MODEM_SYSCON_MODEM_MEM_RA_M (MODEM_SYSCON_MODEM_MEM_RA_V << MODEM_SYSCON_MODEM_MEM_RA_S)
#define MODEM_SYSCON_MODEM_MEM_RA_V 0x00000003U
#define MODEM_SYSCON_MODEM_MEM_RA_S 6
#define MODEM_SYSCON_DATE_REG (DR_REG_MODEM_SYSCON_BASE + 0x1c)
/* MODEM_SYSCON_D... | 1,931 |
/*
*/
#pragma once
#define DR_REG_MODEM_SYSCON_BASE 0x600A5400
#define DR_REG_MODEM_LPCON_BASE 0x600AD000
| 1,932 |
/**
*/
#pragma once
#include
#include "modem/reg_base.h"
#ifdef __cplusplus
extern "C" {
#endif
#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0)
/* MODEM_LPCON_CLK_EN : R/W; bitpos: [0]; default: 0; */
/* description: .*/
#define MODEM_LPCON_CLK_EN (BIT(0))
#define MODEM_LPCON_CLK_EN_M (MODEM_L... | 1,933 |
*/
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2))
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S)
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x00000001U
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2
/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/... | 1,933 |
*/
#define MODEM_LPCON_CLK_COEX_EN (BIT(1))
#define MODEM_LPCON_CLK_COEX_EN_M (MODEM_LPCON_CLK_COEX_EN_V << MODEM_LPCON_CLK_COEX_EN_S)
#define MODEM_LPCON_CLK_COEX_EN_V 0x00000001U
#define MODEM_LPCON_CLK_COEX_EN_S 1
/* MODEM_LPCON_CLK_I2C_MST_EN : R/W; bitpos: [2]; default: 0; */
/* description: .*/
#define MODE... | 1,933 |
*/
#define MODEM_LPCON_CLK_COEX_FO (BIT(1))
#define MODEM_LPCON_CLK_COEX_FO_M (MODEM_LPCON_CLK_COEX_FO_V << MODEM_LPCON_CLK_COEX_FO_S)
#define MODEM_LPCON_CLK_COEX_FO_V 0x00000001U
#define MODEM_LPCON_CLK_COEX_FO_S 1
/* MODEM_LPCON_CLK_I2C_MST_FO : R/W; bitpos: [2]; default: 0; */
/* description: .*/
#define MODE... | 1,933 |
*/
#define MODEM_LPCON_PWR_TICK_TARGET 0x0000003FU
#define MODEM_LPCON_PWR_TICK_TARGET_M (MODEM_LPCON_PWR_TICK_TARGET_V << MODEM_LPCON_PWR_TICK_TARGET_S)
#define MODEM_LPCON_PWR_TICK_TARGET_V 0x0000003FU
#define MODEM_LPCON_PWR_TICK_TARGET_S 0
#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14)
/* ... | 1,933 |
*/
#define MODEM_LPCON_AGC_MEM_FORCE_PU (BIT(2))
#define MODEM_LPCON_AGC_MEM_FORCE_PU_M (MODEM_LPCON_AGC_MEM_FORCE_PU_V << MODEM_LPCON_AGC_MEM_FORCE_PU_S)
#define MODEM_LPCON_AGC_MEM_FORCE_PU_V 0x00000001U
#define MODEM_LPCON_AGC_MEM_FORCE_PU_S 2
/* MODEM_LPCON_AGC_MEM_FORCE_PD : R/W; bitpos: [3]; default: 0; */
... | 1,933 |
*/
#define MODEM_LPCON_PBUS_MEM_FORCE_PD (BIT(5))
#define MODEM_LPCON_PBUS_MEM_FORCE_PD_M (MODEM_LPCON_PBUS_MEM_FORCE_PD_V << MODEM_LPCON_PBUS_MEM_FORCE_PD_S)
#define MODEM_LPCON_PBUS_MEM_FORCE_PD_V 0x00000001U
#define MODEM_LPCON_PBUS_MEM_FORCE_PD_S 5
/* MODEM_LPCON_I2C_MST_MEM_FORCE_PU : R/W; bitpos: [8]; defau... | 1,933 |
*/
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU (BIT(10))
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_M (MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V << MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S)
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V 0x00000001U
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S 10
/* MODEM_LPCON_CHAN_FREQ_MEM_... | 1,933 |
*/
#define MODEM_LPCON_MODEM_PWR_MEM_WA 0x00000007U
#define MODEM_LPCON_MODEM_PWR_MEM_WA_M (MODEM_LPCON_MODEM_PWR_MEM_WA_V << MODEM_LPCON_MODEM_PWR_MEM_WA_S)
#define MODEM_LPCON_MODEM_PWR_MEM_WA_V 0x00000007U
#define MODEM_LPCON_MODEM_PWR_MEM_WA_S 15
/* MODEM_LPCON_MODEM_PWR_MEM_RA : R/W; bitpos: [19:18]; default... | 1,933 |
*/
#define MODEM_LPCON_DATE 0x0FFFFFFFU
#define MODEM_LPCON_DATE_M (MODEM_LPCON_DATE_V << MODEM_LPCON_DATE_S)
#define MODEM_LPCON_DATE_V 0x0FFFFFFFU
#define MODEM_LPCON_DATE_S 0
#ifdef __cplusplus
}
#endif
| 1,933 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef union {
struct {
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} modem_syscon_test_conf_reg_t;
typedef union {
struct {
uint32_t reserved_0:21;
uint32_t clk_etm_en:1;
ui... | 1,934 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef union {
struct {
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} modem_lpcon_test_conf_reg_t;
typedef union {
struct {
uint32_t clk_coex_lp_sel_osc_slow:1;
uint32_t clk_coex_lp_... | 1,935 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C"
{
#endif
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
typedef enum {
ETS_WIFI_MAC_INTR_SOURCE,
ETS_WIFI_MAC_NMI_SOURCE,
ETS_WIFI_PWR_INTR_SOURCE,
ETS_WIFI_BB_INTR_SOURCE,
ETS_BT_MAC_INTR_SOURC... | 1,936 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Control/Configuration Registers */
/** Type of mode register
*/
typedef union {
struct {
/** mode : R/W; bitpos: [2:0]; default: 0;
*/
uint32_t mode:3;
uint32_t reserved_3:29;
};
uint32_t val... | 1,937 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of tar0_low register
*/
typedef union {
struct {
/** main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0;
*/
uint32_t main_timer_tar_low0:32;
};
uint32_t val;
} lp_ti... | 1,942 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration registers */
/** Type of log_setting register
*/
typedef union {
struct {
/** log_mode : R/W; bitpos: [3:0]; default: 0;
*/
uint32_t log_mode:4;
/** log_mem_loop_enable : R/W; bitpos: [... | 1,948 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of store0 register
*/
typedef union {
struct {
/** lp_aon_store0 : R/W; bitpos: [31:0]; default: 0;
*/
uint32_t lp_aon_store0:32;
};
uint32_t val;
} lp_aon_store0_reg_t... | 1,952 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** GPIO_STRAP_REG register
*/
#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0)
/** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0;
*/
#define GPIO_STRAPPING 0x0000FFFFU
#define GPIO_STRAPPING_M (GPIO_STRAPPING_V link.
*... | 1,953 |
*/
#define GPIO_FUNC7_OUT_SEL 0x000001FFU
#define GPIO_FUNC7_OUT_SEL_M (GPIO_FUNC7_OUT_SEL_V link.
*/
#define GPIO_FUNC8_OUT_SEL 0x000001FFU
#define GPIO_FUNC8_OUT_SEL_M (GPIO_FUNC8_OUT_SEL_V link.
*/
#define GPIO_FUNC9_OUT_SEL 0x000001FFU
#define GPIO_FUNC9_OUT_SEL_M (GPIO_FUNC9_OUT_SEL_V link.
*/
#de... | 1,953 |
*/
#define GPIO_FUNC17_OUT_SEL 0x000001FFU
#define GPIO_FUNC17_OUT_SEL_M (GPIO_FUNC17_OUT_SEL_V link.
*/
#define GPIO_FUNC18_OUT_SEL 0x000001FFU
#define GPIO_FUNC18_OUT_SEL_M (GPIO_FUNC18_OUT_SEL_V link.
*/
#define GPIO_FUNC19_OUT_SEL 0x000001FFU
#define GPIO_FUNC19_OUT_SEL_M (GPIO_FUNC19_OUT_SEL_V link... | 1,953 |
*/
#define GPIO_FUNC27_OUT_SEL 0x000001FFU
#define GPIO_FUNC27_OUT_SEL_M (GPIO_FUNC27_OUT_SEL_V link.
*/
#define GPIO_FUNC28_OUT_SEL 0x000001FFU
#define GPIO_FUNC28_OUT_SEL_M (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S)
#define GPIO_FUNC28_OUT_SEL_V 0x000001FFU
#define GPIO_FUNC28_OUT_SEL_S 0
/** GPIO_... | 1,953 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** SPI_CMD_REG register
*/
#define SPI_CMD_REG (DR_REG_SPI_BASE + 0x0)
/** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0;
*/
#define SPI_CONF_BITLEN 0x0003FFFFU
#define SPI_CONF_BITLEN_M (SPI_CONF_BITLEN_V link.
*/
... | 1,955 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of gpion register
*/
typedef union {
struct {
/** gpion_mcu_oe : R/W; bitpos: [0]; default: 0;
*/
uint32_t gpion_mcu_oe:1;
/** gpion_slp_sel : R/W; bitpos: [1]; de... | 1,956 |
/*
*/
#pragma once
#define DR_REG_UART0_BASE 0x60000000
#define DR_REG_UART1_BASE 0x60001000
#define DR_REG_MSPI0_BASE 0x60002000
#define DR_REG_MSPI1_BASE 0x60003000
#define DR_REG_I2C_BASE 0x60... | 1,957 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** I2C_SCL_LOW_PERIOD_REG register
*/
#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0)
/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0;
*/
#define I2C_SCL_LOW_PERIOD 0x000001FFU
#define I2C_SCL_LOW_PERIOD_M ... | 1,958 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Interrupt Registers */
/** Type of cpu_intr_from_cpu_n register
*/
typedef union {
struct {
/** cpu_intr_from_cpu_n : R/W; bitpos: [0]; default: 0;
*/
uint32_t cpu_intr_from_cpu_n:1;
uint32_t reserve... | 1,961 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_TEE_M0_MODE_CTRL_REG register
*/
#define LP_TEE_M0_MODE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x0)
/** LP_TEE_M0_MODE : R/W; bitpos: [1:0]; default: 3;
*/
#define LP_TEE_M0_MODE 0x00000003U
#define LP_TEE_M0_MODE_M (LP_TE... | 1,968 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Interrupt registers */
/** Type of int_raw register
*/
typedef union {
struct {
/** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
*/
uint32_t calc_done_int_raw:1;
... | 1,969 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of lp_clk_conf register
*/
typedef union {
struct {
/** slow_clk_sel : R/W; bitpos: [1:0]; default: 0;
*/
uint32_t slow_clk_sel:2;
/** fast_clk_sel : R/W; bitpos: [3:2]... | 1,971 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of gpion register
*/
typedef union {
struct {
/** gpion_mcu_oe : R/W; bitpos: [0]; default: 0;
*/
uint32_t gpion_mcu_oe:1;
/** gpion_slp_sel : R/W; bitpos: [1]; de... | 1,972 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LPPERI_CLK_EN_REG register
*/
#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0)
/** LPPERI_RNG_CK_EN : R/W; bitpos: [24]; default: 1;
*/
#define LPPERI_RNG_CK_EN (BIT(24))
#define LPPERI_RNG_CK_EN_M (LPPERI_RNG_CK_... | 1,973 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of regdma_conf register
*/
typedef union {
struct {
/** flow_err : RO; bitpos: [2:0]; default: 0;
*/
uint32_t flow_err:3;
/** start : WT; bitpos: [3]; default: 0;
... | 1,974 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of out register
*/
typedef union {
struct {
/** out_data_orig : R/W/WTC; bitpos: [6:0]; default: 0;
*/
uint32_t out_data_orig:7;
uint32_t reserved_7:25;
};
... | 1,975 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
/* Output enable in sleep mode */
#define SLP_OE (BIT(0))
#define SLP_OE_M (BIT(0))
#define SLP_OE_V 1
#define SLP_OE_S 0
/* Pin used for wakeup from sleep... | 1,978 |
csv
#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_P (REG_IO_MUX_BASE + 0x0)
#define FUNC_XTAL_32K_P_GPIO0 1
#define FUNC_XTAL_32K_P_GPIO0_0 0
#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_N (REG_IO_MUX_BASE + 0x4)
#define FUNC_XT... | 1,978 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** SHA_MODE_REG register
*/
#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
*/
#define SHA_MODE 0x00000007U
#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S)
#define SHA_MODE_V 0x... | 1,979 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** MEM_MONITOR_LOG_SETTING_REG register
*/
#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [3:0]; default: 0;
*/
#define MEM_MONITOR_LOG_MODE 0x0000000FU
#define... | 1,981 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** PAU_REGDMA_CONF_REG register
*/
#define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0)
/** PAU_FLOW_ERR : RO; bitpos: [2:0]; default: 0;
*/
#define PAU_FLOW_ERR 0x00000007U
#define PAU_FLOW_ERR_M (PAU_FLOW_ERR_V << PAU_F... | 1,984 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_ANA_BOD_MODE0_CNTL_REG register
*/
#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_ANA_BASE + 0x0)
/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0;
*/
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA (BIT(6... | 1,985 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Tee mode control register */
/** Type of m0_mode_ctrl register
*/
typedef union {
struct {
/** m0_mode : R/W; bitpos: [1:0]; default: 3;
*/
uint32_t m0_mode:2;
/** m0_lock : R/W; bitpos: [2]; default... | 1,988 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** INTPRI_CPU_INTR_FROM_CPU_0_REG register
*/
#define INTPRI_CPU_INTR_FROM_CPU_0_REG (DR_REG_INTPRI_BASE + 0x90)
/** INTPRI_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
*/
#define INTPRI_CPU_INTR_FROM_CPU_0 (BIT(0)... | 1,993 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory configuration registers */
/** Type of mem_start_addr register
*/
typedef union {
struct {
/** mem_start_addr : R/W; bitpos: [31:0]; default: 0;
*/
uint32_t mem_start_addr:32;
};
uint32_t val;... | 1,994 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Tee mode control register */
/** Type of mn_mode_ctrl register
*/
typedef union {
struct {
/** mn_mode : R/W; bitpos: [1:0]; default: 0;
*/
uint32_t mn_mode:2;
/** mn_lock : R/W; bitpos: [2]; default... | 2,005 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of bod_mode0_cntl register
*/
typedef union {
struct {
uint32_t reserved_0:6;
/** bod_mode0_close_flash_ena : R/W; bitpos: [6]; default: 0;
*/
uint32_t bod_mode0_close_... | 2,006 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of config0 register
*/
typedef union {
struct {
/** wdt_chip_reset_width : R/W; bitpos: [7:0]; default: 20;
*/
uint32_t wdt_chip_reset_width:8;
/** wdt_chip_reset_en : ... | 2,010 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of clk_en register
*/
typedef union {
struct {
uint32_t reserved_0:24;
/** rng_ck_en : R/W; bitpos: [24]; default: 1;
*/
uint32_t rng_ck_en:1;
/** otp_dbg_ck_en... | 2,011 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** I2S_INT_RAW_REG register
*/
#define I2S_INT_RAW_REG (DR_REG_I2S_BASE + 0xc)
/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
*/
#define I2S_RX_DONE_INT_RAW (BIT(0))
#define I2S_RX_DONE_INT_RAW_M (I2S_RX_D... | 2,014 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECC_MULT_INT_RAW_REG register
*/
#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
*/
#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0))
#define ECC... | 2,015 |
/*
*/
#pragma once
#define PMU_ICG_APB_ENA_CAN0 18
#define PMU_ICG_APB_ENA_CAN1 19
#define PMU_ICG_APB_ENA_GDMA 1
#define PMU_ICG_APB_ENA_I2C 13
#define PMU_ICG_APB_ENA_I2S 4
#define PMU_ICG_APB_ENA_INTMTX ... | 2,017 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Data Memory */
/** Group: Configuration registers */
/** Type of conf register
*/
typedef union {
struct {
/** work_mode : R/W; bitpos: [1:0]; default: 0;
*/
uint32_t work_mode:2;
/** ecc_curve : R/... | 2,018 |
/**
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of region_filter_en register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [3:0]; default: 1;
*/
uint32_t region_filter_en:4;
uint32_t rese... | 2,022 |
/*
*/
#pragma once
#define EXT_ADC_START_IDX 0
#define LEDC_LS_SIG_OUT0_IDX 0
#define LEDC_LS_SIG_OUT1_IDX 1
#define LEDC_LS_SIG_OUT2_IDX 2
#define LEDC_LS_SIG_OUT3_IDX 3
#define LEDC_LS_SIG_OUT4_IDX ... | 2,025 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C"
{
#endif
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
typedef enum {
ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/
ETS_WIFI_MAC_NMI_SOURCE, /**< interru... | 2,027 |
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,028 |
*/
#define PERI_BACKUP_TO_MEM (BIT(30))
#define PERI_BACKUP_TO_MEM_M (BIT(30))
#define PERI_BACKUP_TO_MEM_V 0x1
#define PERI_BACKUP_TO_MEM_S 30
/* PERI_BACKUP_START : WT ;bitpos:[29] ;default: 1'b0 ; */
/*description: .*/
#define PERI_BACKUP_START (BIT(29))
#define PERI_BACKUP_START_M (BIT(29))
#define PERI_B... | 2,028 |
*/
#define PERI_BACKUP_BURST_LIMIT 0x0000001F
#define PERI_BACKUP_BURST_LIMIT_M ((PERI_BACKUP_BURST_LIMIT_V)<<(PERI_BACKUP_BURST_LIMIT_S))
#define PERI_BACKUP_BURST_LIMIT_V 0x1F
#define PERI_BACKUP_BURST_LIMIT_S 4
/* PERI_BACKUP_ADDR_MAP_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: .*/
#define PERI_B... | 2,028 |
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