text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
*/
#define PERI_BACKUP_MEM_START_ADDR 0xFFFFFFFF
#define PERI_BACKUP_MEM_START_ADDR_M ((PERI_BACKUP_MEM_START_ADDR_V)<<(PERI_BACKUP_MEM_START_ADDR_S))
#define PERI_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF
#define PERI_BACKUP_MEM_START_ADDR_S 0
#define PERI_BACKUP_REG_MAP0_REG (DR_REG_PERI_BACKUP_BASE + 0xC)
/... | 2,028 |
*/
#define PERI_BACKUP_MAP2 0xFFFFFFFF
#define PERI_BACKUP_MAP2_M ((PERI_BACKUP_MAP2_V)<<(PERI_BACKUP_MAP2_S))
#define PERI_BACKUP_MAP2_V 0xFFFFFFFF
#define PERI_BACKUP_MAP2_S 0
#define PERI_BACKUP_REG_MAP3_REG (DR_REG_PERI_BACKUP_BASE + 0x18)
/* PERI_BACKUP_MAP3 : R/W ;bitpos:[31:0] ;default: 32'd0 ; *... | 2,028 |
*/
#define PERI_BACKUP_ERR_INT_ST (BIT(1))
#define PERI_BACKUP_ERR_INT_ST_M (BIT(1))
#define PERI_BACKUP_ERR_INT_ST_V 0x1
#define PERI_BACKUP_ERR_INT_ST_S 1
/* PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */
/*description: .*/
#define PERI_BACKUP_DONE_INT_ST (BIT(0))
#define PERI_BACKUP_DONE_INT_S... | 2,028 |
*/
#define PERI_BACKUP_ERR_INT_CLR (BIT(1))
#define PERI_BACKUP_ERR_INT_CLR_M (BIT(1))
#define PERI_BACKUP_ERR_INT_CLR_V 0x1
#define PERI_BACKUP_ERR_INT_CLR_S 1
/* PERI_BACKUP_DONE_INT_CLR : WT ;bitpos:[0] ;default: 1'd0 ; */
/*description: .*/
#define PERI_BACKUP_DONE_INT_CLR (BIT(0))
#define PERI_BACKUP_DONE... | 2,028 |
/*
*/
#pragma once
//Touch channels
/* Note: T0 is an internal channel that does not have a corresponding external GPIO. */
#define TOUCH_PAD_GPIO1_CHANNEL TOUCH_PAD_NUM1
#define TOUCH_PAD_NUM1_GPIO_NUM 1
#define TOUCH_PAD_GPIO2_CHANNEL TOUCH_PAD_NUM2
#define TOUCH_PAD_NUM2_GPIO_NUM 2
#define TOU... | 2,029 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */
GPIO_NUM_0 = 0, /*!< GPIO0, input and output */
GPIO_NUM_1 = 1, /*!< GPIO1, input and output */
GPIO_NUM_2 = 2, /*!< GPIO2, input and output */... | 2,032 |
< GPIO15, input and output */
GPIO_NUM_16 = 16, /*!< GPIO16, input and output */
GPIO_NUM_17 = 17, /*!< GPIO17, input and output */
GPIO_NUM_18 = 18, /*!< GPIO18, input and output */
GPIO_NUM_19 = 19, /*!< GPIO19, input and output */
GPIO_NUM_20 = 20, /*!< GPIO20, input and output */
G... | 2,032 |
< GPIO37, input and output */
GPIO_NUM_38 = 38, /*!< GPIO38, input and output */
GPIO_NUM_39 = 39, /*!< GPIO39, input and output */
GPIO_NUM_40 = 40, /*!< GPIO40, input and output */
GPIO_NUM_41 = 41, /*!< GPIO41, input and output */
GPIO_NUM_42 = 42, /*!< GPIO42, input and output */
G... | 2,032 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef struct gpio_sd_dev_t {
volatile union {
struct {
uint32_t duty : 8;
uint32_t prescale : 8;
uint32_t reserved16 : 16;
... | 2,034 |
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,035 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define TRACEMEM_MUX_BLK0_NUM 22
#define TRACEMEM_MUX_BLK1_NUM 26
#if (TRACEMEM_MUX_BLK0_NUM 29)
#error Invalid TRAX block 0 num!
#endif
#if (TRACEMEM_MUX_BLK1_NUM 29)
#error Invalid TRAX block 1 num!
#endif
#if TRACEME... | 2,036 |
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,038 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define GPIO_MATRIX_CONST_ONE_INPUT (0x38)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C)
#ifdef __cplusplus
}
#endif
| 2,039 |
/*
*/
#pragma once
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "interrupt_reg.h"
#include "system_reg.h"
#include "sensitive_reg.h"
#include "soc.h"
#define DPORT_DATE_REG SYSTEM_DATE_REG
#ifndef __ASSEMBLER__
#include "dport_access.h"
#endif
#ifdef __cplusplus
}
#endif
| 2,041 |
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,042 |
// Registers defined in rtc_cntl_reg.h, rtc_io_reg.h, sens_reg.h, and rtc_i2c_reg.h are usable with these macros.
// Read from rtc_reg[low_bit + bit_width - 1 : low_bit] into R0, bit_width <= 16
#define READ_RTC_REG(rtc_reg, low_bit, bit_width) \
REG_RD (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_w... | 2,042 |
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,044 |
*/
uint32_t reserved1 : 31;
};
uint32_t val;
} ext_mem_writeback_bypass;
union {
struct {
uint32_t flash_ace0_attr : 9;
uint32_t reserved9 : 23;
};
uint32_t val;
} flash... | 2,044 |
0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
uint32_t sram_page_size : 2; /*Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
uint32_t reserved22 : 10; /*reserved*/
};
... | 2,044 |
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 2,045 |
/*
*/
#pragma once
/**
*/
#define I2C_BOD 0x61
#define I2C_BOD_HOSTID 1
#define I2C_BOD_THRESHOLD 0x5
#define I2C_BOD_THRESHOLD_MSB 2
#define I2C_BOD_THRESHOLD_LSB 0
| 2,046 |
/*
*/
#pragma once
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0)
/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: .*/
#define GPIO_SD0_PRESCALE 0x000000FF
#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V)<... | 2,048 |
*/
#define GPIO_SD1_IN 0x000000FF
#define GPIO_SD1_IN_M ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S))
#define GPIO_SD1_IN_V 0xFF
#define GPIO_SD1_IN_S 0
#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x8)
/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: .*/
#define GPIO_SD2_PRESCA... | 2,048 |
*/
#define GPIO_SD3_IN 0x000000FF
#define GPIO_SD3_IN_M ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S))
#define GPIO_SD3_IN_V 0xFF
#define GPIO_SD3_IN_S 0
#define GPIO_SIGMADELTA4_REG (DR_REG_GPIO_SD_BASE + 0x10)
/* GPIO_SD4_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: .*/
#define GPIO_SD4_PRESC... | 2,048 |
*/
#define GPIO_SD5_IN 0x000000FF
#define GPIO_SD5_IN_M ((GPIO_SD5_IN_V)<<(GPIO_SD5_IN_S))
#define GPIO_SD5_IN_V 0xFF
#define GPIO_SD5_IN_S 0
#define GPIO_SIGMADELTA6_REG (DR_REG_GPIO_SD_BASE + 0x18)
/* GPIO_SD6_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: .*/
#define GPIO_SD6_PRESC... | 2,048 |
*/
#define GPIO_SD7_IN 0x000000FF
#define GPIO_SD7_IN_M ((GPIO_SD7_IN_V)<<(GPIO_SD7_IN_S))
#define GPIO_SD7_IN_V 0xFF
#define GPIO_SD7_IN_S 0
#define GPIO_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x20)
/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: .*/
#define GPIO_SD_CLK_EN ... | 2,048 |
*/
#define GPIO_SD_DATE 0x0FFFFFFF
#define GPIO_SD_DATE_M ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S))
#define GPIO_SD_DATE_V 0xFFFFFFF
#define GPIO_SD_DATE_S 0
#ifdef __cplusplus
}
#endif
| 2,048 |
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,050 |
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,051 |
/*
*/
#pragma once
//RTC GPIO channels
#define RTCIO_GPIO0_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 0
#define RTCIO_GPIO1_CHANNEL 1 //RTCIO_CHANNEL_1
#define RTCIO_CHANNEL_1_GPIO_NUM 1
#define RTCIO_GPIO2_CHANNEL 2 //RTCIO_CHANNEL_2
#define RTCIO_CHANNEL_2_GP... | 2,052 |
/*
*/
#pragma once
/*
Note: These macros are deprecated. When connecting USB OTG to an external FSLS
PHY, the FSLS Serial Interface signals can be routed to any GPIO via the GPIO
matrix. Thus, these macros are meaningless.
Todo: Remove in IDF v6.0 (IDF-9029)
*/
#define USBPHY_VP_NUM 42
#define USBPHY_VM_NUM 41
#def... | 2,053 |
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 2,054 |
/*
*/
#pragma once
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/*IRAM0 is connected with Cache IBUS0*/
#define SOC_IRAM0_ADDRESS_LOW 0x40370000
#define SOC_IRAM0_ADDRESS_HIGH 0x403E0000
#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000
#define SOC_IRAM0_CACHE_ADD... | 2,055 |
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,056 |
*/
#define GPIO_BT_SEL 0xFFFFFFFF
#define GPIO_BT_SEL_M ((GPIO_BT_SEL_V)<<(GPIO_BT_SEL_S))
#define GPIO_BT_SEL_V 0xFFFFFFFF
#define GPIO_BT_SEL_S 0
#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4)
/* GPIO_OUT_DATA : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define GPIO_OUT_DATA 0xFFFFF... | 2,056 |
*/
#define GPIO_OUT1_DATA 0x003FFFFF
#define GPIO_OUT1_DATA_M ((GPIO_OUT1_DATA_V)<<(GPIO_OUT1_DATA_S))
#define GPIO_OUT1_DATA_V 0x3FFFFF
#define GPIO_OUT1_DATA_S 0
#define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x14)
/* GPIO_OUT1_W1TS : WO ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: .*/
#define G... | 2,056 |
*/
#define GPIO_ENABLE_DATA 0xFFFFFFFF
#define GPIO_ENABLE_DATA_M ((GPIO_ENABLE_DATA_V)<<(GPIO_ENABLE_DATA_S))
#define GPIO_ENABLE_DATA_V 0xFFFFFFFF
#define GPIO_ENABLE_DATA_S 0
#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24)
/* GPIO_ENABLE_W1TS : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*descript... | 2,056 |
*/
#define GPIO_ENABLE1_W1TS 0x003FFFFF
#define GPIO_ENABLE1_W1TS_M ((GPIO_ENABLE1_W1TS_V)<<(GPIO_ENABLE1_W1TS_S))
#define GPIO_ENABLE1_W1TS_V 0x3FFFFF
#define GPIO_ENABLE1_W1TS_S 0
#define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x34)
/* GPIO_ENABLE1_W1TC : WO ;bitpos:[21:0] ;default: 22'h0 ; */
/*de... | 2,056 |
*/
#define GPIO_IN1_DATA 0x003FFFFF
#define GPIO_IN1_DATA_M ((GPIO_IN1_DATA_V)<<(GPIO_IN1_DATA_S))
#define GPIO_IN1_DATA_V 0x3FFFFF
#define GPIO_IN1_DATA_S 0
#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44)
/* GPIO_STATUS_INT : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define GPIO_STA... | 2,056 |
*/
#define GPIO_STATUS1_INT 0x003FFFFF
#define GPIO_STATUS1_INT_M ((GPIO_STATUS1_INT_V)<<(GPIO_STATUS1_INT_S))
#define GPIO_STATUS1_INT_V 0x3FFFFF
#define GPIO_STATUS1_INT_S 0
#define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x54)
/* GPIO_STATUS1_W1TS : WO ;bitpos:[21:0] ;default: 22'h0 ; */
/*descript... | 2,056 |
*/
#define GPIO_PROCPU_NMI_INT 0xFFFFFFFF
#define GPIO_PROCPU_NMI_INT_M ((GPIO_PROCPU_NMI_INT_V)<<(GPIO_PROCPU_NMI_INT_S))
#define GPIO_PROCPU_NMI_INT_V 0xFFFFFFFF
#define GPIO_PROCPU_NMI_INT_S 0
#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64)
/* GPIO_SDIO_INT : RO ;bitpos:[31:0] ;default: 32'h0 ... | 2,056 |
*/
#define GPIO_PIN0_INT_ENA 0x0000001F
#define GPIO_PIN0_INT_ENA_M ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S))
#define GPIO_PIN0_INT_ENA_V 0x1F
#define GPIO_PIN0_INT_ENA_S 13
/* GPIO_PIN0_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN0_CONFIG 0x00000003
#define GPIO_PI... | 2,056 |
*/
#define GPIO_PIN0_SYNC1_BYPASS 0x00000003
#define GPIO_PIN0_SYNC1_BYPASS_M ((GPIO_PIN0_SYNC1_BYPASS_V)<<(GPIO_PIN0_SYNC1_BYPASS_S))
#define GPIO_PIN0_SYNC1_BYPASS_V 0x3
#define GPIO_PIN0_SYNC1_BYPASS_S 3
/* GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: .*/
#define GPIO_PIN0_PAD_DRIV... | 2,056 |
*/
#define GPIO_PIN1_CONFIG 0x00000003
#define GPIO_PIN1_CONFIG_M ((GPIO_PIN1_CONFIG_V)<<(GPIO_PIN1_CONFIG_S))
#define GPIO_PIN1_CONFIG_V 0x3
#define GPIO_PIN1_CONFIG_S 11
/* GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
/*description: .*/
#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10))
#define GPIO... | 2,056 |
*/
#define GPIO_PIN1_PAD_DRIVER (BIT(2))
#define GPIO_PIN1_PAD_DRIVER_M (BIT(2))
#define GPIO_PIN1_PAD_DRIVER_V 0x1
#define GPIO_PIN1_PAD_DRIVER_S 2
/* GPIO_PIN1_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN1_SYNC2_BYPASS 0x00000003
#define GPIO_PIN1_SYNC2_BYPASS_M (... | 2,056 |
*/
#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10))
#define GPIO_PIN2_WAKEUP_ENABLE_V 0x1
#define GPIO_PIN2_WAKEUP_ENABLE_S 10
/* GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
/*description: .*/
#define GPIO_PIN2_INT_TYPE 0x00000007
#define GPIO_PIN2_INT_TYPE_M... | 2,056 |
*/
#define GPIO_PIN2_SYNC2_BYPASS 0x00000003
#define GPIO_PIN2_SYNC2_BYPASS_M ((GPIO_PIN2_SYNC2_BYPASS_V)<<(GPIO_PIN2_SYNC2_BYPASS_S))
#define GPIO_PIN2_SYNC2_BYPASS_V 0x3
#define GPIO_PIN2_SYNC2_BYPASS_S 0
#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80)
/* GPIO_PIN3_INT_ENA : R/W ;bitpos:[17:13] ;defau... | 2,056 |
*/
#define GPIO_PIN3_INT_TYPE 0x00000007
#define GPIO_PIN3_INT_TYPE_M ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S))
#define GPIO_PIN3_INT_TYPE_V 0x7
#define GPIO_PIN3_INT_TYPE_S 7
/* GPIO_PIN3_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN3_SYNC1_BYPASS 0x00000003
#... | 2,056 |
*/
#define GPIO_PIN4_INT_ENA 0x0000001F
#define GPIO_PIN4_INT_ENA_M ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S))
#define GPIO_PIN4_INT_ENA_V 0x1F
#define GPIO_PIN4_INT_ENA_S 13
/* GPIO_PIN4_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN4_CONFIG 0x00000003
#define GPIO_PI... | 2,056 |
*/
#define GPIO_PIN4_SYNC1_BYPASS 0x00000003
#define GPIO_PIN4_SYNC1_BYPASS_M ((GPIO_PIN4_SYNC1_BYPASS_V)<<(GPIO_PIN4_SYNC1_BYPASS_S))
#define GPIO_PIN4_SYNC1_BYPASS_V 0x3
#define GPIO_PIN4_SYNC1_BYPASS_S 3
/* GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: .*/
#define GPIO_PIN4_PAD_DRIV... | 2,056 |
*/
#define GPIO_PIN5_CONFIG 0x00000003
#define GPIO_PIN5_CONFIG_M ((GPIO_PIN5_CONFIG_V)<<(GPIO_PIN5_CONFIG_S))
#define GPIO_PIN5_CONFIG_V 0x3
#define GPIO_PIN5_CONFIG_S 11
/* GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
/*description: .*/
#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10))
#define GPIO... | 2,056 |
*/
#define GPIO_PIN5_PAD_DRIVER (BIT(2))
#define GPIO_PIN5_PAD_DRIVER_M (BIT(2))
#define GPIO_PIN5_PAD_DRIVER_V 0x1
#define GPIO_PIN5_PAD_DRIVER_S 2
/* GPIO_PIN5_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN5_SYNC2_BYPASS 0x00000003
#define GPIO_PIN5_SYNC2_BYPASS_M (... | 2,056 |
*/
#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10))
#define GPIO_PIN6_WAKEUP_ENABLE_V 0x1
#define GPIO_PIN6_WAKEUP_ENABLE_S 10
/* GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
/*description: .*/
#define GPIO_PIN6_INT_TYPE 0x00000007
#define GPIO_PIN6_INT_TYPE_M... | 2,056 |
*/
#define GPIO_PIN6_SYNC2_BYPASS 0x00000003
#define GPIO_PIN6_SYNC2_BYPASS_M ((GPIO_PIN6_SYNC2_BYPASS_V)<<(GPIO_PIN6_SYNC2_BYPASS_S))
#define GPIO_PIN6_SYNC2_BYPASS_V 0x3
#define GPIO_PIN6_SYNC2_BYPASS_S 0
#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90)
/* GPIO_PIN7_INT_ENA : R/W ;bitpos:[17:13] ;defau... | 2,056 |
*/
#define GPIO_PIN7_INT_TYPE 0x00000007
#define GPIO_PIN7_INT_TYPE_M ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S))
#define GPIO_PIN7_INT_TYPE_V 0x7
#define GPIO_PIN7_INT_TYPE_S 7
/* GPIO_PIN7_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN7_SYNC1_BYPASS 0x00000003
#... | 2,056 |
*/
#define GPIO_PIN8_INT_ENA 0x0000001F
#define GPIO_PIN8_INT_ENA_M ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S))
#define GPIO_PIN8_INT_ENA_V 0x1F
#define GPIO_PIN8_INT_ENA_S 13
/* GPIO_PIN8_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN8_CONFIG 0x00000003
#define GPIO_PI... | 2,056 |
*/
#define GPIO_PIN8_SYNC1_BYPASS 0x00000003
#define GPIO_PIN8_SYNC1_BYPASS_M ((GPIO_PIN8_SYNC1_BYPASS_V)<<(GPIO_PIN8_SYNC1_BYPASS_S))
#define GPIO_PIN8_SYNC1_BYPASS_V 0x3
#define GPIO_PIN8_SYNC1_BYPASS_S 3
/* GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: .*/
#define GPIO_PIN8_PAD_DRIV... | 2,056 |
*/
#define GPIO_PIN9_CONFIG 0x00000003
#define GPIO_PIN9_CONFIG_M ((GPIO_PIN9_CONFIG_V)<<(GPIO_PIN9_CONFIG_S))
#define GPIO_PIN9_CONFIG_V 0x3
#define GPIO_PIN9_CONFIG_S 11
/* GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
/*description: .*/
#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10))
#define GPIO... | 2,056 |
*/
#define GPIO_PIN9_PAD_DRIVER (BIT(2))
#define GPIO_PIN9_PAD_DRIVER_M (BIT(2))
#define GPIO_PIN9_PAD_DRIVER_V 0x1
#define GPIO_PIN9_PAD_DRIVER_S 2
/* GPIO_PIN9_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN9_SYNC2_BYPASS 0x00000003
#define GPIO_PIN9_SYNC2_BYPASS_M (... | 2,056 |
*/
#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10))
#define GPIO_PIN10_WAKEUP_ENABLE_V 0x1
#define GPIO_PIN10_WAKEUP_ENABLE_S 10
/* GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
/*description: .*/
#define GPIO_PIN10_INT_TYPE 0x00000007
#define GPIO_PIN10_INT... | 2,056 |
*/
#define GPIO_PIN10_SYNC2_BYPASS 0x00000003
#define GPIO_PIN10_SYNC2_BYPASS_M ((GPIO_PIN10_SYNC2_BYPASS_V)<<(GPIO_PIN10_SYNC2_BYPASS_S))
#define GPIO_PIN10_SYNC2_BYPASS_V 0x3
#define GPIO_PIN10_SYNC2_BYPASS_S 0
#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xA0)
/* GPIO_PIN11_INT_ENA : R/W ;bitpos:[17:13... | 2,056 |
*/
#define GPIO_PIN11_INT_TYPE 0x00000007
#define GPIO_PIN11_INT_TYPE_M ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S))
#define GPIO_PIN11_INT_TYPE_V 0x7
#define GPIO_PIN11_INT_TYPE_S 7
/* GPIO_PIN11_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN11_SYNC1_BYPASS 0x00... | 2,056 |
*/
#define GPIO_PIN12_INT_ENA 0x0000001F
#define GPIO_PIN12_INT_ENA_M ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S))
#define GPIO_PIN12_INT_ENA_V 0x1F
#define GPIO_PIN12_INT_ENA_S 13
/* GPIO_PIN12_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN12_CONFIG 0x00000003
#define... | 2,056 |
*/
#define GPIO_PIN12_SYNC1_BYPASS 0x00000003
#define GPIO_PIN12_SYNC1_BYPASS_M ((GPIO_PIN12_SYNC1_BYPASS_V)<<(GPIO_PIN12_SYNC1_BYPASS_S))
#define GPIO_PIN12_SYNC1_BYPASS_V 0x3
#define GPIO_PIN12_SYNC1_BYPASS_S 3
/* GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: .*/
#define GPIO_PIN12_... | 2,056 |
*/
#define GPIO_PIN13_CONFIG 0x00000003
#define GPIO_PIN13_CONFIG_M ((GPIO_PIN13_CONFIG_V)<<(GPIO_PIN13_CONFIG_S))
#define GPIO_PIN13_CONFIG_V 0x3
#define GPIO_PIN13_CONFIG_S 11
/* GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
/*description: .*/
#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10))
#def... | 2,056 |
*/
#define GPIO_PIN13_PAD_DRIVER (BIT(2))
#define GPIO_PIN13_PAD_DRIVER_M (BIT(2))
#define GPIO_PIN13_PAD_DRIVER_V 0x1
#define GPIO_PIN13_PAD_DRIVER_S 2
/* GPIO_PIN13_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN13_SYNC2_BYPASS 0x00000003
#define GPIO_PIN13_SYNC2_BYPA... | 2,056 |
*/
#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10))
#define GPIO_PIN14_WAKEUP_ENABLE_V 0x1
#define GPIO_PIN14_WAKEUP_ENABLE_S 10
/* GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
/*description: .*/
#define GPIO_PIN14_INT_TYPE 0x00000007
#define GPIO_PIN14_INT... | 2,056 |
*/
#define GPIO_PIN14_SYNC2_BYPASS 0x00000003
#define GPIO_PIN14_SYNC2_BYPASS_M ((GPIO_PIN14_SYNC2_BYPASS_V)<<(GPIO_PIN14_SYNC2_BYPASS_S))
#define GPIO_PIN14_SYNC2_BYPASS_V 0x3
#define GPIO_PIN14_SYNC2_BYPASS_S 0
#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xB0)
/* GPIO_PIN15_INT_ENA : R/W ;bitpos:[17:13... | 2,056 |
*/
#define GPIO_PIN15_INT_TYPE 0x00000007
#define GPIO_PIN15_INT_TYPE_M ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S))
#define GPIO_PIN15_INT_TYPE_V 0x7
#define GPIO_PIN15_INT_TYPE_S 7
/* GPIO_PIN15_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN15_SYNC1_BYPASS 0x00... | 2,056 |
*/
#define GPIO_PIN16_INT_ENA 0x0000001F
#define GPIO_PIN16_INT_ENA_M ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S))
#define GPIO_PIN16_INT_ENA_V 0x1F
#define GPIO_PIN16_INT_ENA_S 13
/* GPIO_PIN16_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN16_CONFIG 0x00000003
#define... | 2,056 |
*/
#define GPIO_PIN16_SYNC1_BYPASS 0x00000003
#define GPIO_PIN16_SYNC1_BYPASS_M ((GPIO_PIN16_SYNC1_BYPASS_V)<<(GPIO_PIN16_SYNC1_BYPASS_S))
#define GPIO_PIN16_SYNC1_BYPASS_V 0x3
#define GPIO_PIN16_SYNC1_BYPASS_S 3
/* GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: .*/
#define GPIO_PIN16_... | 2,056 |
*/
#define GPIO_PIN17_CONFIG 0x00000003
#define GPIO_PIN17_CONFIG_M ((GPIO_PIN17_CONFIG_V)<<(GPIO_PIN17_CONFIG_S))
#define GPIO_PIN17_CONFIG_V 0x3
#define GPIO_PIN17_CONFIG_S 11
/* GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
/*description: .*/
#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10))
#def... | 2,056 |
*/
#define GPIO_PIN17_PAD_DRIVER (BIT(2))
#define GPIO_PIN17_PAD_DRIVER_M (BIT(2))
#define GPIO_PIN17_PAD_DRIVER_V 0x1
#define GPIO_PIN17_PAD_DRIVER_S 2
/* GPIO_PIN17_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN17_SYNC2_BYPASS 0x00000003
#define GPIO_PIN17_SYNC2_BYPA... | 2,056 |
*/
#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN18_WAKEUP_ENABLE_M (BIT(10))
#define GPIO_PIN18_WAKEUP_ENABLE_V 0x1
#define GPIO_PIN18_WAKEUP_ENABLE_S 10
/* GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
/*description: .*/
#define GPIO_PIN18_INT_TYPE 0x00000007
#define GPIO_PIN18_INT... | 2,056 |
*/
#define GPIO_PIN18_SYNC2_BYPASS 0x00000003
#define GPIO_PIN18_SYNC2_BYPASS_M ((GPIO_PIN18_SYNC2_BYPASS_V)<<(GPIO_PIN18_SYNC2_BYPASS_S))
#define GPIO_PIN18_SYNC2_BYPASS_V 0x3
#define GPIO_PIN18_SYNC2_BYPASS_S 0
#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xC0)
/* GPIO_PIN19_INT_ENA : R/W ;bitpos:[17:13... | 2,056 |
*/
#define GPIO_PIN19_INT_TYPE 0x00000007
#define GPIO_PIN19_INT_TYPE_M ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S))
#define GPIO_PIN19_INT_TYPE_V 0x7
#define GPIO_PIN19_INT_TYPE_S 7
/* GPIO_PIN19_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN19_SYNC1_BYPASS 0x00... | 2,056 |
*/
#define GPIO_PIN20_INT_ENA 0x0000001F
#define GPIO_PIN20_INT_ENA_M ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S))
#define GPIO_PIN20_INT_ENA_V 0x1F
#define GPIO_PIN20_INT_ENA_S 13
/* GPIO_PIN20_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN20_CONFIG 0x00000003
#define... | 2,056 |
*/
#define GPIO_PIN20_SYNC1_BYPASS 0x00000003
#define GPIO_PIN20_SYNC1_BYPASS_M ((GPIO_PIN20_SYNC1_BYPASS_V)<<(GPIO_PIN20_SYNC1_BYPASS_S))
#define GPIO_PIN20_SYNC1_BYPASS_V 0x3
#define GPIO_PIN20_SYNC1_BYPASS_S 3
/* GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: .*/
#define GPIO_PIN20_... | 2,056 |
*/
#define GPIO_PIN21_CONFIG 0x00000003
#define GPIO_PIN21_CONFIG_M ((GPIO_PIN21_CONFIG_V)<<(GPIO_PIN21_CONFIG_S))
#define GPIO_PIN21_CONFIG_V 0x3
#define GPIO_PIN21_CONFIG_S 11
/* GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
/*description: .*/
#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10))
#def... | 2,056 |
*/
#define GPIO_PIN21_PAD_DRIVER (BIT(2))
#define GPIO_PIN21_PAD_DRIVER_M (BIT(2))
#define GPIO_PIN21_PAD_DRIVER_V 0x1
#define GPIO_PIN21_PAD_DRIVER_S 2
/* GPIO_PIN21_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN21_SYNC2_BYPASS 0x00000003
#define GPIO_PIN21_SYNC2_BYPA... | 2,056 |
*/
#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN22_WAKEUP_ENABLE_M (BIT(10))
#define GPIO_PIN22_WAKEUP_ENABLE_V 0x1
#define GPIO_PIN22_WAKEUP_ENABLE_S 10
/* GPIO_PIN22_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
/*description: .*/
#define GPIO_PIN22_INT_TYPE 0x00000007
#define GPIO_PIN22_INT... | 2,056 |
*/
#define GPIO_PIN22_SYNC2_BYPASS 0x00000003
#define GPIO_PIN22_SYNC2_BYPASS_M ((GPIO_PIN22_SYNC2_BYPASS_V)<<(GPIO_PIN22_SYNC2_BYPASS_S))
#define GPIO_PIN22_SYNC2_BYPASS_V 0x3
#define GPIO_PIN22_SYNC2_BYPASS_S 0
#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xD0)
/* GPIO_PIN23_INT_ENA : R/W ;bitpos:[17:13... | 2,056 |
*/
#define GPIO_PIN23_INT_TYPE 0x00000007
#define GPIO_PIN23_INT_TYPE_M ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S))
#define GPIO_PIN23_INT_TYPE_V 0x7
#define GPIO_PIN23_INT_TYPE_S 7
/* GPIO_PIN23_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN23_SYNC1_BYPASS 0x00... | 2,056 |
*/
#define GPIO_PIN24_INT_ENA 0x0000001F
#define GPIO_PIN24_INT_ENA_M ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S))
#define GPIO_PIN24_INT_ENA_V 0x1F
#define GPIO_PIN24_INT_ENA_S 13
/* GPIO_PIN24_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN24_CONFIG 0x00000003
#define... | 2,056 |
*/
#define GPIO_PIN24_SYNC1_BYPASS 0x00000003
#define GPIO_PIN24_SYNC1_BYPASS_M ((GPIO_PIN24_SYNC1_BYPASS_V)<<(GPIO_PIN24_SYNC1_BYPASS_S))
#define GPIO_PIN24_SYNC1_BYPASS_V 0x3
#define GPIO_PIN24_SYNC1_BYPASS_S 3
/* GPIO_PIN24_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: .*/
#define GPIO_PIN24_... | 2,056 |
*/
#define GPIO_PIN25_CONFIG 0x00000003
#define GPIO_PIN25_CONFIG_M ((GPIO_PIN25_CONFIG_V)<<(GPIO_PIN25_CONFIG_S))
#define GPIO_PIN25_CONFIG_V 0x3
#define GPIO_PIN25_CONFIG_S 11
/* GPIO_PIN25_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
/*description: .*/
#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10))
#def... | 2,056 |
*/
#define GPIO_PIN25_PAD_DRIVER (BIT(2))
#define GPIO_PIN25_PAD_DRIVER_M (BIT(2))
#define GPIO_PIN25_PAD_DRIVER_V 0x1
#define GPIO_PIN25_PAD_DRIVER_S 2
/* GPIO_PIN25_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN25_SYNC2_BYPASS 0x00000003
#define GPIO_PIN25_SYNC2_BYPA... | 2,056 |
*/
#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN26_WAKEUP_ENABLE_M (BIT(10))
#define GPIO_PIN26_WAKEUP_ENABLE_V 0x1
#define GPIO_PIN26_WAKEUP_ENABLE_S 10
/* GPIO_PIN26_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
/*description: .*/
#define GPIO_PIN26_INT_TYPE 0x00000007
#define GPIO_PIN26_INT... | 2,056 |
*/
#define GPIO_PIN26_SYNC2_BYPASS 0x00000003
#define GPIO_PIN26_SYNC2_BYPASS_M ((GPIO_PIN26_SYNC2_BYPASS_V)<<(GPIO_PIN26_SYNC2_BYPASS_S))
#define GPIO_PIN26_SYNC2_BYPASS_V 0x3
#define GPIO_PIN26_SYNC2_BYPASS_S 0
#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0xE0)
/* GPIO_PIN27_INT_ENA : R/W ;bitpos:[17:13... | 2,056 |
*/
#define GPIO_PIN27_INT_TYPE 0x00000007
#define GPIO_PIN27_INT_TYPE_M ((GPIO_PIN27_INT_TYPE_V)<<(GPIO_PIN27_INT_TYPE_S))
#define GPIO_PIN27_INT_TYPE_V 0x7
#define GPIO_PIN27_INT_TYPE_S 7
/* GPIO_PIN27_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN27_SYNC1_BYPASS 0x00... | 2,056 |
*/
#define GPIO_PIN28_INT_ENA 0x0000001F
#define GPIO_PIN28_INT_ENA_M ((GPIO_PIN28_INT_ENA_V)<<(GPIO_PIN28_INT_ENA_S))
#define GPIO_PIN28_INT_ENA_V 0x1F
#define GPIO_PIN28_INT_ENA_S 13
/* GPIO_PIN28_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN28_CONFIG 0x00000003
#define... | 2,056 |
*/
#define GPIO_PIN28_SYNC1_BYPASS 0x00000003
#define GPIO_PIN28_SYNC1_BYPASS_M ((GPIO_PIN28_SYNC1_BYPASS_V)<<(GPIO_PIN28_SYNC1_BYPASS_S))
#define GPIO_PIN28_SYNC1_BYPASS_V 0x3
#define GPIO_PIN28_SYNC1_BYPASS_S 3
/* GPIO_PIN28_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: .*/
#define GPIO_PIN28_... | 2,056 |
*/
#define GPIO_PIN29_CONFIG 0x00000003
#define GPIO_PIN29_CONFIG_M ((GPIO_PIN29_CONFIG_V)<<(GPIO_PIN29_CONFIG_S))
#define GPIO_PIN29_CONFIG_V 0x3
#define GPIO_PIN29_CONFIG_S 11
/* GPIO_PIN29_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
/*description: .*/
#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10))
#def... | 2,056 |
*/
#define GPIO_PIN29_PAD_DRIVER (BIT(2))
#define GPIO_PIN29_PAD_DRIVER_M (BIT(2))
#define GPIO_PIN29_PAD_DRIVER_V 0x1
#define GPIO_PIN29_PAD_DRIVER_S 2
/* GPIO_PIN29_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN29_SYNC2_BYPASS 0x00000003
#define GPIO_PIN29_SYNC2_BYPA... | 2,056 |
*/
#define GPIO_PIN30_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN30_WAKEUP_ENABLE_M (BIT(10))
#define GPIO_PIN30_WAKEUP_ENABLE_V 0x1
#define GPIO_PIN30_WAKEUP_ENABLE_S 10
/* GPIO_PIN30_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
/*description: .*/
#define GPIO_PIN30_INT_TYPE 0x00000007
#define GPIO_PIN30_INT... | 2,056 |
*/
#define GPIO_PIN30_SYNC2_BYPASS 0x00000003
#define GPIO_PIN30_SYNC2_BYPASS_M ((GPIO_PIN30_SYNC2_BYPASS_V)<<(GPIO_PIN30_SYNC2_BYPASS_S))
#define GPIO_PIN30_SYNC2_BYPASS_V 0x3
#define GPIO_PIN30_SYNC2_BYPASS_S 0
#define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0xF0)
/* GPIO_PIN31_INT_ENA : R/W ;bitpos:[17:13... | 2,056 |
*/
#define GPIO_PIN31_INT_TYPE 0x00000007
#define GPIO_PIN31_INT_TYPE_M ((GPIO_PIN31_INT_TYPE_V)<<(GPIO_PIN31_INT_TYPE_S))
#define GPIO_PIN31_INT_TYPE_V 0x7
#define GPIO_PIN31_INT_TYPE_S 7
/* GPIO_PIN31_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN31_SYNC1_BYPASS 0x00... | 2,056 |
*/
#define GPIO_PIN32_INT_ENA 0x0000001F
#define GPIO_PIN32_INT_ENA_M ((GPIO_PIN32_INT_ENA_V)<<(GPIO_PIN32_INT_ENA_S))
#define GPIO_PIN32_INT_ENA_V 0x1F
#define GPIO_PIN32_INT_ENA_S 13
/* GPIO_PIN32_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
/*description: .*/
#define GPIO_PIN32_CONFIG 0x00000003
#define... | 2,056 |
*/
#define GPIO_PIN32_SYNC1_BYPASS 0x00000003
#define GPIO_PIN32_SYNC1_BYPASS_M ((GPIO_PIN32_SYNC1_BYPASS_V)<<(GPIO_PIN32_SYNC1_BYPASS_S))
#define GPIO_PIN32_SYNC1_BYPASS_V 0x3
#define GPIO_PIN32_SYNC1_BYPASS_S 3
/* GPIO_PIN32_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: .*/
#define GPIO_PIN32_... | 2,056 |
*/
#define GPIO_PIN33_CONFIG 0x00000003
#define GPIO_PIN33_CONFIG_M ((GPIO_PIN33_CONFIG_V)<<(GPIO_PIN33_CONFIG_S))
#define GPIO_PIN33_CONFIG_V 0x3
#define GPIO_PIN33_CONFIG_S 11
/* GPIO_PIN33_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
/*description: .*/
#define GPIO_PIN33_WAKEUP_ENABLE (BIT(10))
#def... | 2,056 |
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