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So spi_clk frequency is system/
(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state..*/
#define SPI_CLKCNT_N 0x0000003F
#define SPI_CLKCNT_N_M ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S))
#define SPI_CLKCNT_N_V 0x3F
#define SPI_CLKCNT_N_S 12
/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */
/*des... | 2,060 |
Can be configured in CONF sta
te..*/
#define SPI_USR_COMMAND (BIT(31))
#define SPI_USR_COMMAND_M (BIT(31))
#define SPI_USR_COMMAND_V 0x1
#define SPI_USR_COMMAND_S 31
/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: This bit enable the address phase of an operation. Can be configured in CONF ... | 2,060 |
Can be configured in CONF
state..*/
#define SPI_USR_MOSI (BIT(27))
#define SPI_USR_MOSI_M (BIT(27))
#define SPI_USR_MOSI_V 0x1
#define SPI_USR_MOSI_S 27
/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: spi clock is disable in dummy phase when the bit is enable. Can be configured in
CO... | 2,060 |
Can be configured in CONF state..*/
#define SPI_USR_MISO_HIGHPART (BIT(24))
#define SPI_USR_MISO_HIGHPART_M (BIT(24))
#define SPI_USR_MISO_HIGHPART_V 0x1
#define SPI_USR_MISO_HIGHPART_S 24
/* SPI_SIO : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: Set the bit to enable 3-line half duplex communication mosi... | 2,060 |
Can be configured in CO
NF state..*/
#define SPI_FWRITE_OCT (BIT(14))
#define SPI_FWRITE_OCT_M (BIT(14))
#define SPI_FWRITE_OCT_V 0x1
#define SPI_FWRITE_OCT_S 14
/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: In the write operations read-data phase apply 4 signals. Can be configured in ... | 2,060 |
0: rsck
= !spi_ck_i. 1:rsck = spi_ck_i..*/
#define SPI_RSCK_I_EDGE (BIT(8))
#define SPI_RSCK_I_EDGE_M (BIT(8))
#define SPI_RSCK_I_EDGE_V 0x1
#define SPI_RSCK_I_EDGE_S 8
/* SPI_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b1 ; */
/*description: spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can ... | 2,060 |
1: spi controller is in OPI mode (all in 8-b-m). 0: others
. Can be configured in CONF state..*/
#define SPI_OPI_MODE (BIT(4))
#define SPI_OPI_MODE_M (BIT(4))
#define SPI_OPI_MODE_V 0x1
#define SPI_OPI_MODE_S 4
/* SPI_QPI_MODE : R/W/SS/SC ;bitpos:[3] ;default: 1'b0 ; */
/*description: Both for master mode and sl... | 2,060 |
The register value shall be (bit_num-1). Ca
n be configured in CONF state..*/
#define SPI_USR_ADDR_BITLEN 0x0000001F
#define SPI_USR_ADDR_BITLEN_M ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S))
#define SPI_USR_ADDR_BITLEN_V 0x1F
#define SPI_USR_ADDR_BITLEN_S 27
/* SPI_CS_HOLD_TIME : R/W ;bitpos:[26:22] ;defa... | 2,060 |
0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid
in GP-SPI master FD/HD-mode..*/
#define SPI_MST_WFULL_ERR_END_EN (BIT(16))
#define SPI_MST_WFULL_ERR_END_EN_M (BIT(16))
#define SPI_MST_WFULL_ERR_END_EN_V 0x1
#define SPI_MST_WFULL_ERR_END_EN_S 16
/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;... | 2,060 |
0: SPI transfer is not ended when SPI TX AFIFO read empty erro
r is valid in GP-SPI master FD/HD-mode..*/
#define SPI_MST_REMPTY_ERR_END_EN (BIT(27))
#define SPI_MST_REMPTY_ERR_END_EN_M (BIT(27))
#define SPI_MST_REMPTY_ERR_END_EN_V 0x1
#define SPI_MST_REMPTY_ERR_END_EN_S 27
/* SPI_USR_COMMAND_VALUE : R/W ;bitpos... | 2,060 |
Can be configured in CONF state..*/
#define SPI_MS_DATA_BITLEN 0x0003FFFF
#define SPI_MS_DATA_BITLEN_M ((SPI_MS_DATA_BITLEN_V)<<(SPI_MS_DATA_BITLEN_S))
#define SPI_MS_DATA_BITLEN_V 0x3FFFF
#define SPI_MS_DATA_BITLEN_S 0
#define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20)
/* SPI_QUAD_DIN_PIN_SWAP : R/W ;bi... | 2,060 |
Can be c
onfigured in CONF state..*/
#define SPI_CK_IDLE_EDGE (BIT(29))
#define SPI_CK_IDLE_EDGE_M (BIT(29))
#define SPI_CK_IDLE_EDGE_V 0x1
#define SPI_CK_IDLE_EDGE_S 29
/* SPI_DQS_IDLE_EDGE : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: The default value of spi_dqs. Can be configured in CONF state..*/
#d... | 2,060 |
.*/
#define SPI_CMD_DTR_EN (BIT(19))
#define SPI_CMD_DTR_EN_M (BIT(19))
#define SPI_CMD_DTR_EN_V 0x1
#define SPI_CMD_DTR_EN_S 19
/* SPI_ADDR_DTR_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
/*description: 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2
/4/8-bm. 0: SPI clk and data ... | 2,060 |
0: SPI master D
TR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. .*/
#define SPI_CLK_DATA_DTR_EN (BIT(16))
#define SPI_CLK_DATA_DTR_EN_M (BIT(16))
#define SPI_CLK_DATA_DTR_EN_V 0x1
#define SPI_CLK_DATA_DTR_EN_S 16
/* SPI_MASTER_CS_POL : R/W ;bitpos:[12:7] ;default: 6'b0 ; */
/*des... | 2,060 |
Ca
n be configured in CONF state..*/
#define SPI_CS5_DIS (BIT(5))
#define SPI_CS5_DIS_M (BIT(5))
#define SPI_CS5_DIS_V 0x1
#define SPI_CS5_DIS_S 5
/* SPI_CS4_DIS : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
n be configured i... | 2,060 |
Ca
n be configured in CONF state..*/
#define SPI_CS1_DIS (BIT(1))
#define SPI_CS1_DIS_M (BIT(1))
#define SPI_CS1_DIS_V 0x1
#define SPI_CS1_DIS_S 1
/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
n be configured i... | 2,060 |
Can be configured in CONF state..*/
#define SPI_DIN7_MODE 0x00000003
#define SPI_DIN7_MODE_M ((SPI_DIN7_MODE_V)<<(SPI_DIN7_MODE_S))
#define SPI_DIN7_MODE_V 0x3
#define SPI_DIN7_MODE_S 14
/* SPI_DIN6_MODE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
/*description: the input signals are delayed by SPI module clock cy... | 2,060 |
Can be configured in CONF state..*/
#define SPI_DIN4_MODE 0x00000003
#define SPI_DIN4_MODE_M ((SPI_DIN4_MODE_V)<<(SPI_DIN4_MODE_S))
#define SPI_DIN4_MODE_V 0x3
#define SPI_DIN4_MODE_S 8
/* SPI_DIN3_MODE : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
/*description: the input signals are delayed by SPI module clock cycle... | 2,060 |
Can be configured in CONF state..*/
#define SPI_DIN1_MODE 0x00000003
#define SPI_DIN1_MODE_M ((SPI_DIN1_MODE_V)<<(SPI_DIN1_MODE_S))
#define SPI_DIN1_MODE_V 0x3
#define SPI_DIN1_MODE_S 2
/* SPI_DIN0_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: the input signals are delayed by SPI module clock cycle... | 2,060 |
.. Can be configured in CONF state..*/
#define SPI_DIN6_NUM 0x00000003
#define SPI_DIN6_NUM_M ((SPI_DIN6_NUM_V)<<(SPI_DIN6_NUM_S))
#define SPI_DIN6_NUM_V 0x3
#define SPI_DIN6_NUM_S 12
/* SPI_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
/*description: the input signals are delayed by SPI module clock cycles... | 2,060 |
.. Can be configured in CONF state..*/
#define SPI_DIN3_NUM 0x00000003
#define SPI_DIN3_NUM_M ((SPI_DIN3_NUM_V)<<(SPI_DIN3_NUM_S))
#define SPI_DIN3_NUM_V 0x3
#define SPI_DIN3_NUM_S 6
/* SPI_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
/*description: the input signals are delayed by SPI module clock cycles, 0... | 2,060 |
.. Can be configured in CONF state..*/
#define SPI_DIN0_NUM 0x00000003
#define SPI_DIN0_NUM_M ((SPI_DIN0_NUM_V)<<(SPI_DIN0_NUM_S))
#define SPI_DIN0_NUM_V 0x3
#define SPI_DIN0_NUM_S 0
#define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x2C)
/* SPI_D_DQS_MODE : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*descript... | 2,060 |
Can be co
nfigured in CONF state..*/
#define SPI_DOUT6_MODE (BIT(6))
#define SPI_DOUT6_MODE_M (BIT(6))
#define SPI_DOUT6_MODE_V 0x1
#define SPI_DOUT6_MODE_S 6
/* SPI_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
ed... | 2,060 |
Can be co
nfigured in CONF state..*/
#define SPI_DOUT3_MODE (BIT(3))
#define SPI_DOUT3_MODE_M (BIT(3))
#define SPI_DOUT3_MODE_V 0x1
#define SPI_DOUT3_MODE_S 3
/* SPI_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
ed... | 2,060 |
Can be co
nfigured in CONF state..*/
#define SPI_DOUT0_MODE (BIT(0))
#define SPI_DOUT0_MODE_M (BIT(0))
#define SPI_DOUT0_MODE_V 0x1
#define SPI_DOUT0_MODE_S 0
#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x30)
/* SPI_DMA_AFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */
/*description: Set this bit to r... | 2,060 |
.*/
#define SPI_RX_AFIFO_RST (BIT(29))
#define SPI_RX_AFIFO_RST_M (BIT(29))
#define SPI_RX_AFIFO_RST_V 0x1
#define SPI_RX_AFIFO_RST_S 29
/* SPI_DMA_TX_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: Set this bit to enable SPI DMA controlled send data mode..*/
#define SPI_DMA_TX_ENA (BIT(28))
#define ... | 2,060 |
.*/
#define SPI_RX_EOF_EN (BIT(21))
#define SPI_RX_EOF_EN_M (BIT(21))
#define SPI_RX_EOF_EN_V 0x1
#define SPI_RX_EOF_EN_S 21
/* SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_e
mpty_vld is cleared by ... | 2,060 |
1: enable. 0: disable..*/
#define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18))
#define SPI_DMA_SLV_SEG_TRANS_EN_M (BIT(18))
#define SPI_DMA_SLV_SEG_TRANS_EN_V 0x1
#define SPI_DMA_SLV_SEG_TRANS_EN_S 18
/* SPI_DMA_INFIFO_FULL : RO ;bitpos:[1] ;default: 1'b1 ; */
/*description: Records the status of DMA RX FIFO. 1: DMA RX FI... | 2,060 |
.*/
#define SPI_APP1_INT_ENA (BIT(20))
#define SPI_APP1_INT_ENA_M (BIT(20))
#define SPI_APP1_INT_ENA_V 0x1
#define SPI_APP1_INT_ENA_S 20
/* SPI_APP2_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
/*description: The enable bit for SPI_APP2_INT interrupt..*/
#define SPI_APP2_INT_ENA (BIT(19))
#define SPI_APP2_IN... | 2,060 |
.*/
#define SPI_SLV_CMD_ERR_INT_ENA (BIT(16))
#define SPI_SLV_CMD_ERR_INT_ENA_M (BIT(16))
#define SPI_SLV_CMD_ERR_INT_ENA_V 0x1
#define SPI_SLV_CMD_ERR_INT_ENA_S 16
/* SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
#defi... | 2,060 |
.*/
#define SPI_TRANS_DONE_INT_ENA (BIT(12))
#define SPI_TRANS_DONE_INT_ENA_M (BIT(12))
#define SPI_TRANS_DONE_INT_ENA_V 0x1
#define SPI_TRANS_DONE_INT_ENA_S 12
/* SPI_SLV_WR_BUF_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
#define SPI... | 2,060 |
.*/
#define SPI_SLV_RD_DMA_DONE_INT_ENA (BIT(8))
#define SPI_SLV_RD_DMA_DONE_INT_ENA_M (BIT(8))
#define SPI_SLV_RD_DMA_DONE_INT_ENA_V 0x1
#define SPI_SLV_RD_DMA_DONE_INT_ENA_S 8
/* SPI_SLV_CMDA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: The enable bit for SPI slave CMDA interrupt..*/
#define SPI... | 2,060 |
.*/
#define SPI_SLV_CMD7_INT_ENA (BIT(4))
#define SPI_SLV_CMD7_INT_ENA_M (BIT(4))
#define SPI_SLV_CMD7_INT_ENA_V 0x1
#define SPI_SLV_CMD7_INT_ENA_S 4
/* SPI_SLV_EN_QPI_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: The enable bit for SPI slave En_QPI interrupt..*/
#define SPI_SLV_EN_QPI_INT_ENA (... | 2,060 |
.*/
#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA (BIT(0))
#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M (BIT(0))
#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V 0x1
#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S 0
#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x38)
/* SPI_APP1_INT_CLR : WT ;bitpos:[20] ;default: 1'b0 ;... | 2,060 |
.*/
#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR (BIT(17))
#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M (BIT(17))
#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V 0x1
#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S 17
/* SPI_SLV_CMD_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */
/*description: The clear bit for SPI_SLV... | 2,060 |
.*/
#define SPI_DMA_SEG_TRANS_DONE_INT_CLR (BIT(13))
#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M (BIT(13))
#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V 0x1
#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S 13
/* SPI_TRANS_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
/*description: The clear bit for SPI_TRANS_DONE_INT inter... | 2,060 |
.*/
#define SPI_SLV_WR_DMA_DONE_INT_CLR (BIT(9))
#define SPI_SLV_WR_DMA_DONE_INT_CLR_M (BIT(9))
#define SPI_SLV_WR_DMA_DONE_INT_CLR_V 0x1
#define SPI_SLV_WR_DMA_DONE_INT_CLR_S 9
/* SPI_SLV_RD_DMA_DONE_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
/*description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt..... | 2,060 |
.*/
#define SPI_SLV_CMD8_INT_CLR (BIT(5))
#define SPI_SLV_CMD8_INT_CLR_M (BIT(5))
#define SPI_SLV_CMD8_INT_CLR_V 0x1
#define SPI_SLV_CMD8_INT_CLR_S 5
/* SPI_SLV_CMD7_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
/*description: The clear bit for SPI slave CMD7 interrupt..*/
#define SPI_SLV_CMD7_INT_CLR (BIT(4))
... | 2,060 |
.*/
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR (BIT(1))
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M (BIT(1))
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V 0x1
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S 1
/* SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: The clear bit for SPI_DMA... | 2,060 |
The value is only controlled by software
..*/
#define SPI_APP2_INT_RAW (BIT(19))
#define SPI_APP2_INT_RAW_M (BIT(19))
#define SPI_APP2_INT_RAW_V 0x1
#define SPI_APP2_INT_RAW_S 19
/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */
/*description: The raw bit for SPI_MST_TX_AFIFO_REM... | 2,060 |
1: The slave command value in the
current SPI slave HD mode transmission is not supported. 0: Others..*/
#define SPI_SLV_CMD_ERR_INT_RAW (BIT(16))
#define SPI_SLV_CMD_ERR_INT_RAW_M (BIT(16))
#define SPI_SLV_CMD_ERR_INT_RAW_V 0x1
#define SPI_SLV_CMD_ERR_INT_RAW_S 16
/* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS ;bi... | 2,060 |
1: spi master DMA full-du
plex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And da
ta has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is
not ended or not occurred. .*/
#define SPI_DMA_SEG_TRANS_DONE_INT_RAW (BIT(13))
#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M (BIT(1... | 2,060 |
1: SPI slave mode Rd_BUF tran
smission is ended. 0: Others..*/
#define SPI_SLV_RD_BUF_DONE_INT_RAW (BIT(10))
#define SPI_SLV_RD_BUF_DONE_INT_RAW_M (BIT(10))
#define SPI_SLV_RD_BUF_DONE_INT_RAW_V 0x1
#define SPI_SLV_RD_BUF_DONE_INT_RAW_S 10
/* SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */... | 2,060 |
1: SPI slave mode CMDA transmission is
ended. 0: Others..*/
#define SPI_SLV_CMDA_INT_RAW (BIT(7))
#define SPI_SLV_CMDA_INT_RAW_M (BIT(7))
#define SPI_SLV_CMDA_INT_RAW_V 0x1
#define SPI_SLV_CMDA_INT_RAW_S 7
/* SPI_SLV_CMD9_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
/*description: The raw bit for SPI slav... | 2,060 |
1: SPI slave mode CMD7 transmission is
ended. 0: Others..*/
#define SPI_SLV_CMD7_INT_RAW (BIT(4))
#define SPI_SLV_CMD7_INT_RAW_M (BIT(4))
#define SPI_SLV_CMD7_INT_RAW_V 0x1
#define SPI_SLV_CMD7_INT_RAW_S 4
/* SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw bit for SPI sl... | 2,060 |
SPI will stop in
master mode and send out all 0 in slave mode. 0: Others. .*/
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW (BIT(1))
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M (BIT(1))
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V 0x1
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S 1
/* SPI_DMA_INFIFO_FULL_ERR_INT_RAW... | 2,060 |
.*/
#define SPI_APP2_INT_ST (BIT(19))
#define SPI_APP2_INT_ST_M (BIT(19))
#define SPI_APP2_INT_ST_V 0x1
#define SPI_APP2_INT_ST_S 19
/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
/*description: The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
#define SPI_MST_TX_AFIFO_... | 2,060 |
.*/
#define SPI_SLV_BUF_ADDR_ERR_INT_ST (BIT(15))
#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M (BIT(15))
#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V 0x1
#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S 15
/* SPI_SEG_MAGIC_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
/*description: The status bit for SPI_SEG_MAGIC_ERR_INT interrupt..... | 2,060 |
.*/
#define SPI_SLV_WR_BUF_DONE_INT_ST (BIT(11))
#define SPI_SLV_WR_BUF_DONE_INT_ST_M (BIT(11))
#define SPI_SLV_WR_BUF_DONE_INT_ST_V 0x1
#define SPI_SLV_WR_BUF_DONE_INT_ST_S 11
/* SPI_SLV_RD_BUF_DONE_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt..... | 2,060 |
.*/
#define SPI_SLV_CMDA_INT_ST (BIT(7))
#define SPI_SLV_CMDA_INT_ST_M (BIT(7))
#define SPI_SLV_CMDA_INT_ST_V 0x1
#define SPI_SLV_CMDA_INT_ST_S 7
/* SPI_SLV_CMD9_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The status bit for SPI slave CMD9 interrupt..*/
#define SPI_SLV_CMD9_INT_ST (BIT(6))
#defi... | 2,060 |
.*/
#define SPI_SLV_EN_QPI_INT_ST (BIT(3))
#define SPI_SLV_EN_QPI_INT_ST_M (BIT(3))
#define SPI_SLV_EN_QPI_INT_ST_V 0x1
#define SPI_SLV_EN_QPI_INT_ST_S 3
/* SPI_SLV_EX_QPI_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: The status bit for SPI slave Ex_QPI interrupt..*/
#define SPI_SLV_EX_QPI_INT_ST ... | 2,060 |
.*/
#define SPI_APP1_INT_SET (BIT(20))
#define SPI_APP1_INT_SET_M (BIT(20))
#define SPI_APP1_INT_SET_V 0x1
#define SPI_APP1_INT_SET_S 20
/* SPI_APP2_INT_SET : WT ;bitpos:[19] ;default: 1'b0 ; */
/*description: The software set bit for SPI_APP2_INT interrupt..*/
#define SPI_APP2_INT_SET (BIT(19))
#define SPI_AP... | 2,060 |
.*/
#define SPI_SLV_CMD_ERR_INT_SET (BIT(16))
#define SPI_SLV_CMD_ERR_INT_SET_M (BIT(16))
#define SPI_SLV_CMD_ERR_INT_SET_V 0x1
#define SPI_SLV_CMD_ERR_INT_SET_S 16
/* SPI_SLV_BUF_ADDR_ERR_INT_SET : WT ;bitpos:[15] ;default: 1'b0 ; */
/*description: The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
... | 2,060 |
.*/
#define SPI_TRANS_DONE_INT_SET (BIT(12))
#define SPI_TRANS_DONE_INT_SET_M (BIT(12))
#define SPI_TRANS_DONE_INT_SET_V 0x1
#define SPI_TRANS_DONE_INT_SET_S 12
/* SPI_SLV_WR_BUF_DONE_INT_SET : WT ;bitpos:[11] ;default: 1'b0 ; */
/*description: The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
#defin... | 2,060 |
.*/
#define SPI_SLV_RD_DMA_DONE_INT_SET (BIT(8))
#define SPI_SLV_RD_DMA_DONE_INT_SET_M (BIT(8))
#define SPI_SLV_RD_DMA_DONE_INT_SET_V 0x1
#define SPI_SLV_RD_DMA_DONE_INT_SET_S 8
/* SPI_SLV_CMDA_INT_SET : WT ;bitpos:[7] ;default: 1'b0 ; */
/*description: The software set bit for SPI slave CMDA interrupt..*/
#defin... | 2,060 |
.*/
#define SPI_SLV_CMD7_INT_SET (BIT(4))
#define SPI_SLV_CMD7_INT_SET_M (BIT(4))
#define SPI_SLV_CMD7_INT_SET_V 0x1
#define SPI_SLV_CMD7_INT_SET_S 4
/* SPI_SLV_EN_QPI_INT_SET : WT ;bitpos:[3] ;default: 1'b0 ; */
/*description: The software set bit for SPI slave En_QPI interrupt..*/
#define SPI_SLV_EN_QPI_INT_SET... | 2,060 |
.*/
#define SPI_DMA_INFIFO_FULL_ERR_INT_SET (BIT(0))
#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M (BIT(0))
#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V 0x1
#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S 0
#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x98)
/* SPI_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*desc... | 2,060 |
*/
#define SPI_BUF3 0xFFFFFFFF
#define SPI_BUF3_M ((SPI_BUF3_V)<<(SPI_BUF3_S))
#define SPI_BUF3_V 0xFFFFFFFF
#define SPI_BUF3_S 0
#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0xA8)
/* SPI_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF4 0xFFFFFFFF
#define S... | 2,060 |
*/
#define SPI_BUF7 0xFFFFFFFF
#define SPI_BUF7_M ((SPI_BUF7_V)<<(SPI_BUF7_S))
#define SPI_BUF7_V 0xFFFFFFFF
#define SPI_BUF7_S 0
#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xB8)
/* SPI_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF8 0xFFFFFFFF
#define S... | 2,060 |
*/
#define SPI_BUF11 0xFFFFFFFF
#define SPI_BUF11_M ((SPI_BUF11_V)<<(SPI_BUF11_S))
#define SPI_BUF11_V 0xFFFFFFFF
#define SPI_BUF11_S 0
#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xC8)
/* SPI_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF12 0xFFFFFFFF
... | 2,060 |
*/
#define SPI_BUF15 0xFFFFFFFF
#define SPI_BUF15_M ((SPI_BUF15_V)<<(SPI_BUF15_S))
#define SPI_BUF15_V 0xFFFFFFFF
#define SPI_BUF15_S 0
#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0xE0)
/* SPI_USR_CONF : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: 1: Enable the DMA CONF phase of current seg-tran... | 2,060 |
.*/
#define SPI_DMA_SEG_MAGIC_VALUE 0x0000000F
#define SPI_DMA_SEG_MAGIC_VALUE_M ((SPI_DMA_SEG_MAGIC_VALUE_V)<<(SPI_DMA_SEG_MAGIC_VALUE_S))
#define SPI_DMA_SEG_MAGIC_VALUE_V 0xF
#define SPI_DMA_SEG_MAGIC_VALUE_S 22
/* SPI_SLV_WRBUF_BITLEN_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: 1: SPI_SLV_DATA_BI... | 2,060 |
0: others.*/
#define SPI_SLV_WRDMA_BITLEN_EN (BIT(9))
#define SPI_SLV_WRDMA_BITLEN_EN_M (BIT(9))
#define SPI_SLV_WRDMA_BITLEN_EN_V 0x1
#define SPI_SLV_WRDMA_BITLEN_EN_S 9
/* SPI_SLV_RDDMA_BITLEN_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-s... | 2,060 |
0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]..*/
#define SPI_CLK_MODE_13 (BIT(2))
#define SPI_CLK_MODE_13_M (BIT(2))
#define SPI_CLK_MODE_13_V 0x1
#define SPI_CLK_MODE_13_S 2
/* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: SPI clock mode bits. 0: SPI clock is off when... | 2,060 |
.*/
#define SPI_SLV_LAST_COMMAND 0x000000FF
#define SPI_SLV_LAST_COMMAND_M ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S))
#define SPI_SLV_LAST_COMMAND_V 0xFF
#define SPI_SLV_LAST_COMMAND_S 18
/* SPI_SLV_DATA_BITLEN : R/W/SS ;bitpos:[17:0] ;default: 18'd0 ; */
/*description: The transferred data bit length i... | 2,060 |
.*/
#define SPI_MST_CLK_ACTIVE (BIT(1))
#define SPI_MST_CLK_ACTIVE_M (BIT(1))
#define SPI_MST_CLK_ACTIVE_V 0x1
#define SPI_MST_CLK_ACTIVE_S 1
/* SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to enable clk gate.*/
#define SPI_CLK_EN (BIT(0))
#define SPI_CLK_EN_M (BIT(0))
#define ... | 2,060 |
/*
*/
#define DR_REG_UART_BASE 0x60000000
#define DR_REG_SPI1_BASE 0x60002000
#define DR_REG_SPI0_BASE 0x60003000
#define DR_REG_GPIO_BASE 0x60004000
#define DR_REG_GPIO_SD_BASE 0x60004f00
#define DR_REG_FE2... | 2,061 |
/*
*/
#pragma once
#ifndef __ASSEMBLER__
#include
#include "esp_assert.h"
#endif
#include "esp_bit_defs.h"
#include "reg_base.h"
#define PRO_CPU_NUM (0)
#define APP_CPU_NUM (1)
#define PRO_CPUID (0xcdcd)
#define APP_CPUID (0xabab)
/* Cache configuration */
#define DR_REG_MMU_TABLE 0x6... | 2,062 |
(DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
//Convenient way to replace the register ops when ulp riscv projects
//consume this file
#ifndef ULP_RISCV_REGISTER_OPS
//Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (a... | 2,062 |
__ASSEMBLER__ */
//}}
#endif /* !ULP_RISCV_REGISTER_OPS */
//Periheral Clock {{
#define APB_CLK_FREQ_ROM (40*1000000)
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in ... | 2,062 |
#define SOC_DIRAM_IRAM_LOW 0x40378000
#define SOC_DIRAM_IRAM_HIGH 0x403E0000
#define SOC_DIRAM_DRAM_LOW 0x3FC88000
#define SOC_DIRAM_DRAM_HIGH 0x3FCF0000
#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET)
#define MAP_IRAM_TO_DRAM(addr) (ad... | 2,062 |
#define SOC_MEM_INTERNAL_LOW 0x3FC88000
#define SOC_MEM_INTERNAL_HIGH 0x403E0000
// Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x3fceb710
#define SOC_ROM_STACK_SIZE 0x2000
//interrupt cpu using table, Please see the core-isa.h
... | 2,062 |
#define ETS_FRC_TIMER2_INUM 10 /* use edge*/
#define ETS_GPIO_INUM 4
//Other interrupt number should be managed by the user
//Invalid interrupt for number interrupt matrix
#define ETS_INVALID_INUM 6
// Interrupt number for the Interrupt watchdog
#define ETS_INT_WDT_INUM ... | 2,062 |
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,064 |
*/
#define RTC_GPIO_OUT_DATA_W1TS 0x003FFFFF
#define RTC_GPIO_OUT_DATA_W1TS_M ((RTC_GPIO_OUT_DATA_W1TS_V)<<(RTC_GPIO_OUT_DATA_W1TS_S))
#define RTC_GPIO_OUT_DATA_W1TS_V 0x3FFFFF
#define RTC_GPIO_OUT_DATA_W1TS_S 10
#define RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x8)
/* RTC_GPIO_OUT_DATA_W1TC : WO ;bit... | 2,064 |
*/
#define RTC_GPIO_ENABLE_W1TS 0x003FFFFF
#define RTC_GPIO_ENABLE_W1TS_M ((RTC_GPIO_ENABLE_W1TS_V)<<(RTC_GPIO_ENABLE_W1TS_S))
#define RTC_GPIO_ENABLE_W1TS_V 0x3FFFFF
#define RTC_GPIO_ENABLE_W1TS_S 10
#define RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x14)
/* RTC_GPIO_ENABLE_W1TC : WO ;bitpos:[31:10... | 2,064 |
*/
#define RTC_GPIO_STATUS_INT_W1TS 0x003FFFFF
#define RTC_GPIO_STATUS_INT_W1TS_M ((RTC_GPIO_STATUS_INT_W1TS_V)<<(RTC_GPIO_STATUS_INT_W1TS_S))
#define RTC_GPIO_STATUS_INT_W1TS_V 0x3FFFFF
#define RTC_GPIO_STATUS_INT_W1TS_S 10
#define RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x20)
/* RTC_GPIO_STATUS_... | 2,064 |
*/
#define RTC_GPIO_PIN0_WAKEUP_ENABLE (BIT(10))
#define RTC_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10))
#define RTC_GPIO_PIN0_WAKEUP_ENABLE_V 0x1
#define RTC_GPIO_PIN0_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: risin... | 2,064 |
*/
#define RTC_GPIO_PIN1_WAKEUP_ENABLE (BIT(10))
#define RTC_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10))
#define RTC_GPIO_PIN1_WAKEUP_ENABLE_V 0x1
#define RTC_GPIO_PIN1_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: risin... | 2,064 |
*/
#define RTC_GPIO_PIN2_WAKEUP_ENABLE (BIT(10))
#define RTC_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10))
#define RTC_GPIO_PIN2_WAKEUP_ENABLE_V 0x1
#define RTC_GPIO_PIN2_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: risin... | 2,064 |
*/
#define RTC_GPIO_PIN3_WAKEUP_ENABLE (BIT(10))
#define RTC_GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10))
#define RTC_GPIO_PIN3_WAKEUP_ENABLE_V 0x1
#define RTC_GPIO_PIN3_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: risin... | 2,064 |
*/
#define RTC_GPIO_PIN4_WAKEUP_ENABLE (BIT(10))
#define RTC_GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10))
#define RTC_GPIO_PIN4_WAKEUP_ENABLE_V 0x1
#define RTC_GPIO_PIN4_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: risin... | 2,064 |
*/
#define RTC_GPIO_PIN5_WAKEUP_ENABLE (BIT(10))
#define RTC_GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10))
#define RTC_GPIO_PIN5_WAKEUP_ENABLE_V 0x1
#define RTC_GPIO_PIN5_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: risin... | 2,064 |
*/
#define RTC_GPIO_PIN6_WAKEUP_ENABLE (BIT(10))
#define RTC_GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10))
#define RTC_GPIO_PIN6_WAKEUP_ENABLE_V 0x1
#define RTC_GPIO_PIN6_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: risin... | 2,064 |
*/
#define RTC_GPIO_PIN7_WAKEUP_ENABLE (BIT(10))
#define RTC_GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10))
#define RTC_GPIO_PIN7_WAKEUP_ENABLE_V 0x1
#define RTC_GPIO_PIN7_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: risin... | 2,064 |
*/
#define RTC_GPIO_PIN8_WAKEUP_ENABLE (BIT(10))
#define RTC_GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10))
#define RTC_GPIO_PIN8_WAKEUP_ENABLE_V 0x1
#define RTC_GPIO_PIN8_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: risin... | 2,064 |
*/
#define RTC_GPIO_PIN9_WAKEUP_ENABLE (BIT(10))
#define RTC_GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10))
#define RTC_GPIO_PIN9_WAKEUP_ENABLE_V 0x1
#define RTC_GPIO_PIN9_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: risin... | 2,064 |
*/
#define RTC_GPIO_PIN10_WAKEUP_ENABLE (BIT(10))
#define RTC_GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10))
#define RTC_GPIO_PIN10_WAKEUP_ENABLE_V 0x1
#define RTC_GPIO_PIN10_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: ... | 2,064 |
*/
#define RTC_GPIO_PIN11_WAKEUP_ENABLE (BIT(10))
#define RTC_GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10))
#define RTC_GPIO_PIN11_WAKEUP_ENABLE_V 0x1
#define RTC_GPIO_PIN11_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: ... | 2,064 |
*/
#define RTC_GPIO_PIN12_WAKEUP_ENABLE (BIT(10))
#define RTC_GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10))
#define RTC_GPIO_PIN12_WAKEUP_ENABLE_V 0x1
#define RTC_GPIO_PIN12_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: ... | 2,064 |
*/
#define RTC_GPIO_PIN13_WAKEUP_ENABLE (BIT(10))
#define RTC_GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10))
#define RTC_GPIO_PIN13_WAKEUP_ENABLE_V 0x1
#define RTC_GPIO_PIN13_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: ... | 2,064 |
*/
#define RTC_GPIO_PIN14_WAKEUP_ENABLE (BIT(10))
#define RTC_GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10))
#define RTC_GPIO_PIN14_WAKEUP_ENABLE_V 0x1
#define RTC_GPIO_PIN14_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: ... | 2,064 |
*/
#define RTC_GPIO_PIN15_WAKEUP_ENABLE (BIT(10))
#define RTC_GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10))
#define RTC_GPIO_PIN15_WAKEUP_ENABLE_V 0x1
#define RTC_GPIO_PIN15_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: ... | 2,064 |
*/
#define RTC_GPIO_PIN16_WAKEUP_ENABLE (BIT(10))
#define RTC_GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10))
#define RTC_GPIO_PIN16_WAKEUP_ENABLE_V 0x1
#define RTC_GPIO_PIN16_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: ... | 2,064 |
*/
#define RTC_GPIO_PIN17_WAKEUP_ENABLE (BIT(10))
#define RTC_GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10))
#define RTC_GPIO_PIN17_WAKEUP_ENABLE_V 0x1
#define RTC_GPIO_PIN17_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: ... | 2,064 |
*/
#define RTC_GPIO_PIN18_WAKEUP_ENABLE (BIT(10))
#define RTC_GPIO_PIN18_WAKEUP_ENABLE_M (BIT(10))
#define RTC_GPIO_PIN18_WAKEUP_ENABLE_V 0x1
#define RTC_GPIO_PIN18_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: ... | 2,064 |
*/
#define RTC_GPIO_PIN19_WAKEUP_ENABLE (BIT(10))
#define RTC_GPIO_PIN19_WAKEUP_ENABLE_M (BIT(10))
#define RTC_GPIO_PIN19_WAKEUP_ENABLE_V 0x1
#define RTC_GPIO_PIN19_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: ... | 2,064 |
*/
#define RTC_GPIO_PIN20_WAKEUP_ENABLE (BIT(10))
#define RTC_GPIO_PIN20_WAKEUP_ENABLE_M (BIT(10))
#define RTC_GPIO_PIN20_WAKEUP_ENABLE_V 0x1
#define RTC_GPIO_PIN20_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: ... | 2,064 |
*/
#define RTC_GPIO_PIN21_WAKEUP_ENABLE (BIT(10))
#define RTC_GPIO_PIN21_WAKEUP_ENABLE_M (BIT(10))
#define RTC_GPIO_PIN21_WAKEUP_ENABLE_V 0x1
#define RTC_GPIO_PIN21_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: ... | 2,064 |
*/
#define RTC_IO_DEBUG_12M_NO_GATING (BIT(25))
#define RTC_IO_DEBUG_12M_NO_GATING_M (BIT(25))
#define RTC_IO_DEBUG_12M_NO_GATING_V 0x1
#define RTC_IO_DEBUG_12M_NO_GATING_S 25
/* RTC_IO_DEBUG_SEL4 : R/W ;bitpos:[24:20] ;default: 5'd0 ; */
/*description: .*/
#define RTC_IO_DEBUG_SEL4 0x0000001F
#define RTC_IO_D... | 2,064 |
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