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*/
#define RTC_IO_DEBUG_SEL1 0x0000001F
#define RTC_IO_DEBUG_SEL1_M ((RTC_IO_DEBUG_SEL1_V)<<(RTC_IO_DEBUG_SEL1_S))
#define RTC_IO_DEBUG_SEL1_V 0x1F
#define RTC_IO_DEBUG_SEL1_S 5
/* RTC_IO_DEBUG_SEL0 : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: .*/
#define RTC_IO_DEBUG_SEL0 0x0000001F
#define RTC_IO_D... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD0_RUE (BIT(27))
#define RTC_IO_TOUCH_PAD0_RUE_M (BIT(27))
#define RTC_IO_TOUCH_PAD0_RUE_V 0x1
#define RTC_IO_TOUCH_PAD0_RUE_S 27
/* RTC_IO_TOUCH_PAD0_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*description: TOUCH_START.*/
#define RTC_IO_TOUCH_PAD0_START (BIT(22))
#define RTC_IO_TO... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD0_MUX_SEL (BIT(19))
#define RTC_IO_TOUCH_PAD0_MUX_SEL_M (BIT(19))
#define RTC_IO_TOUCH_PAD0_MUX_SEL_V 0x1
#define RTC_IO_TOUCH_PAD0_MUX_SEL_S 19
/* RTC_IO_TOUCH_PAD0_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
/*description: function sel.*/
#define RTC_IO_TOUCH_PAD0_FUN_SEL 0x0... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD0_SLP_OE (BIT(14))
#define RTC_IO_TOUCH_PAD0_SLP_OE_M (BIT(14))
#define RTC_IO_TOUCH_PAD0_SLP_OE_V 0x1
#define RTC_IO_TOUCH_PAD0_SLP_OE_S 14
/* RTC_IO_TOUCH_PAD0_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
/*description: input enable in work mode.*/
#define RTC_IO_TOUCH_PAD0_FUN_IE ... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD1_RUE (BIT(27))
#define RTC_IO_TOUCH_PAD1_RUE_M (BIT(27))
#define RTC_IO_TOUCH_PAD1_RUE_V 0x1
#define RTC_IO_TOUCH_PAD1_RUE_S 27
/* RTC_IO_TOUCH_PAD1_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*description: TOUCH_START.*/
#define RTC_IO_TOUCH_PAD1_START (BIT(22))
#define RTC_IO_TO... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD1_MUX_SEL (BIT(19))
#define RTC_IO_TOUCH_PAD1_MUX_SEL_M (BIT(19))
#define RTC_IO_TOUCH_PAD1_MUX_SEL_V 0x1
#define RTC_IO_TOUCH_PAD1_MUX_SEL_S 19
/* RTC_IO_TOUCH_PAD1_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
/*description: function sel.*/
#define RTC_IO_TOUCH_PAD1_FUN_SEL 0x0... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD1_SLP_OE (BIT(14))
#define RTC_IO_TOUCH_PAD1_SLP_OE_M (BIT(14))
#define RTC_IO_TOUCH_PAD1_SLP_OE_V 0x1
#define RTC_IO_TOUCH_PAD1_SLP_OE_S 14
/* RTC_IO_TOUCH_PAD1_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
/*description: input enable in work mode.*/
#define RTC_IO_TOUCH_PAD1_FUN_IE ... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD2_RUE (BIT(27))
#define RTC_IO_TOUCH_PAD2_RUE_M (BIT(27))
#define RTC_IO_TOUCH_PAD2_RUE_V 0x1
#define RTC_IO_TOUCH_PAD2_RUE_S 27
/* RTC_IO_TOUCH_PAD2_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*description: TOUCH_START.*/
#define RTC_IO_TOUCH_PAD2_START (BIT(22))
#define RTC_IO_TO... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD2_MUX_SEL (BIT(19))
#define RTC_IO_TOUCH_PAD2_MUX_SEL_M (BIT(19))
#define RTC_IO_TOUCH_PAD2_MUX_SEL_V 0x1
#define RTC_IO_TOUCH_PAD2_MUX_SEL_S 19
/* RTC_IO_TOUCH_PAD2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
/*description: function sel.*/
#define RTC_IO_TOUCH_PAD2_FUN_SEL 0x0... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD2_SLP_OE (BIT(14))
#define RTC_IO_TOUCH_PAD2_SLP_OE_M (BIT(14))
#define RTC_IO_TOUCH_PAD2_SLP_OE_V 0x1
#define RTC_IO_TOUCH_PAD2_SLP_OE_S 14
/* RTC_IO_TOUCH_PAD2_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
/*description: input enable in work mode.*/
#define RTC_IO_TOUCH_PAD2_FUN_IE ... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD3_RUE (BIT(27))
#define RTC_IO_TOUCH_PAD3_RUE_M (BIT(27))
#define RTC_IO_TOUCH_PAD3_RUE_V 0x1
#define RTC_IO_TOUCH_PAD3_RUE_S 27
/* RTC_IO_TOUCH_PAD3_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*description: TOUCH_START.*/
#define RTC_IO_TOUCH_PAD3_START (BIT(22))
#define RTC_IO_TO... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD3_MUX_SEL (BIT(19))
#define RTC_IO_TOUCH_PAD3_MUX_SEL_M (BIT(19))
#define RTC_IO_TOUCH_PAD3_MUX_SEL_V 0x1
#define RTC_IO_TOUCH_PAD3_MUX_SEL_S 19
/* RTC_IO_TOUCH_PAD3_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
/*description: function sel.*/
#define RTC_IO_TOUCH_PAD3_FUN_SEL 0x0... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD3_SLP_OE (BIT(14))
#define RTC_IO_TOUCH_PAD3_SLP_OE_M (BIT(14))
#define RTC_IO_TOUCH_PAD3_SLP_OE_V 0x1
#define RTC_IO_TOUCH_PAD3_SLP_OE_S 14
/* RTC_IO_TOUCH_PAD3_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
/*description: input enable in work mode.*/
#define RTC_IO_TOUCH_PAD3_FUN_IE ... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD4_RUE (BIT(27))
#define RTC_IO_TOUCH_PAD4_RUE_M (BIT(27))
#define RTC_IO_TOUCH_PAD4_RUE_V 0x1
#define RTC_IO_TOUCH_PAD4_RUE_S 27
/* RTC_IO_TOUCH_PAD4_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*description: TOUCH_START.*/
#define RTC_IO_TOUCH_PAD4_START (BIT(22))
#define RTC_IO_TO... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD4_MUX_SEL (BIT(19))
#define RTC_IO_TOUCH_PAD4_MUX_SEL_M (BIT(19))
#define RTC_IO_TOUCH_PAD4_MUX_SEL_V 0x1
#define RTC_IO_TOUCH_PAD4_MUX_SEL_S 19
/* RTC_IO_TOUCH_PAD4_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
/*description: function sel.*/
#define RTC_IO_TOUCH_PAD4_FUN_SEL 0x0... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD4_SLP_OE (BIT(14))
#define RTC_IO_TOUCH_PAD4_SLP_OE_M (BIT(14))
#define RTC_IO_TOUCH_PAD4_SLP_OE_V 0x1
#define RTC_IO_TOUCH_PAD4_SLP_OE_S 14
/* RTC_IO_TOUCH_PAD4_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
/*description: input enable in work mode.*/
#define RTC_IO_TOUCH_PAD4_FUN_IE ... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD5_RUE (BIT(27))
#define RTC_IO_TOUCH_PAD5_RUE_M (BIT(27))
#define RTC_IO_TOUCH_PAD5_RUE_V 0x1
#define RTC_IO_TOUCH_PAD5_RUE_S 27
/* RTC_IO_TOUCH_PAD5_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*description: TOUCH_START.*/
#define RTC_IO_TOUCH_PAD5_START (BIT(22))
#define RTC_IO_TO... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD5_MUX_SEL (BIT(19))
#define RTC_IO_TOUCH_PAD5_MUX_SEL_M (BIT(19))
#define RTC_IO_TOUCH_PAD5_MUX_SEL_V 0x1
#define RTC_IO_TOUCH_PAD5_MUX_SEL_S 19
/* RTC_IO_TOUCH_PAD5_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
/*description: function sel.*/
#define RTC_IO_TOUCH_PAD5_FUN_SEL 0x0... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD5_SLP_OE (BIT(14))
#define RTC_IO_TOUCH_PAD5_SLP_OE_M (BIT(14))
#define RTC_IO_TOUCH_PAD5_SLP_OE_V 0x1
#define RTC_IO_TOUCH_PAD5_SLP_OE_S 14
/* RTC_IO_TOUCH_PAD5_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
/*description: input enable in work mode.*/
#define RTC_IO_TOUCH_PAD5_FUN_IE ... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD6_RUE (BIT(27))
#define RTC_IO_TOUCH_PAD6_RUE_M (BIT(27))
#define RTC_IO_TOUCH_PAD6_RUE_V 0x1
#define RTC_IO_TOUCH_PAD6_RUE_S 27
/* RTC_IO_TOUCH_PAD6_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*description: TOUCH_START.*/
#define RTC_IO_TOUCH_PAD6_START (BIT(22))
#define RTC_IO_TO... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD6_MUX_SEL (BIT(19))
#define RTC_IO_TOUCH_PAD6_MUX_SEL_M (BIT(19))
#define RTC_IO_TOUCH_PAD6_MUX_SEL_V 0x1
#define RTC_IO_TOUCH_PAD6_MUX_SEL_S 19
/* RTC_IO_TOUCH_PAD6_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
/*description: function sel.*/
#define RTC_IO_TOUCH_PAD6_FUN_SEL 0x0... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD6_SLP_OE (BIT(14))
#define RTC_IO_TOUCH_PAD6_SLP_OE_M (BIT(14))
#define RTC_IO_TOUCH_PAD6_SLP_OE_V 0x1
#define RTC_IO_TOUCH_PAD6_SLP_OE_S 14
/* RTC_IO_TOUCH_PAD6_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
/*description: input enable in work mode.*/
#define RTC_IO_TOUCH_PAD6_FUN_IE ... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD7_RUE (BIT(27))
#define RTC_IO_TOUCH_PAD7_RUE_M (BIT(27))
#define RTC_IO_TOUCH_PAD7_RUE_V 0x1
#define RTC_IO_TOUCH_PAD7_RUE_S 27
/* RTC_IO_TOUCH_PAD7_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*description: TOUCH_START.*/
#define RTC_IO_TOUCH_PAD7_START (BIT(22))
#define RTC_IO_TO... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD7_MUX_SEL (BIT(19))
#define RTC_IO_TOUCH_PAD7_MUX_SEL_M (BIT(19))
#define RTC_IO_TOUCH_PAD7_MUX_SEL_V 0x1
#define RTC_IO_TOUCH_PAD7_MUX_SEL_S 19
/* RTC_IO_TOUCH_PAD7_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
/*description: function sel.*/
#define RTC_IO_TOUCH_PAD7_FUN_SEL 0x0... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD7_SLP_OE (BIT(14))
#define RTC_IO_TOUCH_PAD7_SLP_OE_M (BIT(14))
#define RTC_IO_TOUCH_PAD7_SLP_OE_V 0x1
#define RTC_IO_TOUCH_PAD7_SLP_OE_S 14
/* RTC_IO_TOUCH_PAD7_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
/*description: input enable in work mode.*/
#define RTC_IO_TOUCH_PAD7_FUN_IE ... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD8_RUE (BIT(27))
#define RTC_IO_TOUCH_PAD8_RUE_M (BIT(27))
#define RTC_IO_TOUCH_PAD8_RUE_V 0x1
#define RTC_IO_TOUCH_PAD8_RUE_S 27
/* RTC_IO_TOUCH_PAD8_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*description: TOUCH_START.*/
#define RTC_IO_TOUCH_PAD8_START (BIT(22))
#define RTC_IO_TO... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD8_MUX_SEL (BIT(19))
#define RTC_IO_TOUCH_PAD8_MUX_SEL_M (BIT(19))
#define RTC_IO_TOUCH_PAD8_MUX_SEL_V 0x1
#define RTC_IO_TOUCH_PAD8_MUX_SEL_S 19
/* RTC_IO_TOUCH_PAD8_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
/*description: function sel.*/
#define RTC_IO_TOUCH_PAD8_FUN_SEL 0x0... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD8_SLP_OE (BIT(14))
#define RTC_IO_TOUCH_PAD8_SLP_OE_M (BIT(14))
#define RTC_IO_TOUCH_PAD8_SLP_OE_V 0x1
#define RTC_IO_TOUCH_PAD8_SLP_OE_S 14
/* RTC_IO_TOUCH_PAD8_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
/*description: input enable in work mode.*/
#define RTC_IO_TOUCH_PAD8_FUN_IE ... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD9_RUE (BIT(27))
#define RTC_IO_TOUCH_PAD9_RUE_M (BIT(27))
#define RTC_IO_TOUCH_PAD9_RUE_V 0x1
#define RTC_IO_TOUCH_PAD9_RUE_S 27
/* RTC_IO_TOUCH_PAD9_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*description: TOUCH_START.*/
#define RTC_IO_TOUCH_PAD9_START (BIT(22))
#define RTC_IO_TO... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD9_MUX_SEL (BIT(19))
#define RTC_IO_TOUCH_PAD9_MUX_SEL_M (BIT(19))
#define RTC_IO_TOUCH_PAD9_MUX_SEL_V 0x1
#define RTC_IO_TOUCH_PAD9_MUX_SEL_S 19
/* RTC_IO_TOUCH_PAD9_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
/*description: function sel.*/
#define RTC_IO_TOUCH_PAD9_FUN_SEL 0x0... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD9_SLP_OE (BIT(14))
#define RTC_IO_TOUCH_PAD9_SLP_OE_M (BIT(14))
#define RTC_IO_TOUCH_PAD9_SLP_OE_V 0x1
#define RTC_IO_TOUCH_PAD9_SLP_OE_S 14
/* RTC_IO_TOUCH_PAD9_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
/*description: input enable in work mode.*/
#define RTC_IO_TOUCH_PAD9_FUN_IE ... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD10_RUE (BIT(27))
#define RTC_IO_TOUCH_PAD10_RUE_M (BIT(27))
#define RTC_IO_TOUCH_PAD10_RUE_V 0x1
#define RTC_IO_TOUCH_PAD10_RUE_S 27
/* RTC_IO_TOUCH_PAD10_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*description: TOUCH_START.*/
#define RTC_IO_TOUCH_PAD10_START (BIT(22))
#define RTC... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD10_MUX_SEL (BIT(19))
#define RTC_IO_TOUCH_PAD10_MUX_SEL_M (BIT(19))
#define RTC_IO_TOUCH_PAD10_MUX_SEL_V 0x1
#define RTC_IO_TOUCH_PAD10_MUX_SEL_S 19
/* RTC_IO_TOUCH_PAD10_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
/*description: function sel.*/
#define RTC_IO_TOUCH_PAD10_FUN_SEL ... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD10_SLP_OE (BIT(14))
#define RTC_IO_TOUCH_PAD10_SLP_OE_M (BIT(14))
#define RTC_IO_TOUCH_PAD10_SLP_OE_V 0x1
#define RTC_IO_TOUCH_PAD10_SLP_OE_S 14
/* RTC_IO_TOUCH_PAD10_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
/*description: input enable in work mode.*/
#define RTC_IO_TOUCH_PAD10_FUN... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD11_RUE (BIT(27))
#define RTC_IO_TOUCH_PAD11_RUE_M (BIT(27))
#define RTC_IO_TOUCH_PAD11_RUE_V 0x1
#define RTC_IO_TOUCH_PAD11_RUE_S 27
/* RTC_IO_TOUCH_PAD11_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*description: TOUCH_START.*/
#define RTC_IO_TOUCH_PAD11_START (BIT(22))
#define RTC... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD11_MUX_SEL (BIT(19))
#define RTC_IO_TOUCH_PAD11_MUX_SEL_M (BIT(19))
#define RTC_IO_TOUCH_PAD11_MUX_SEL_V 0x1
#define RTC_IO_TOUCH_PAD11_MUX_SEL_S 19
/* RTC_IO_TOUCH_PAD11_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
/*description: function sel.*/
#define RTC_IO_TOUCH_PAD11_FUN_SEL ... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD11_SLP_OE (BIT(14))
#define RTC_IO_TOUCH_PAD11_SLP_OE_M (BIT(14))
#define RTC_IO_TOUCH_PAD11_SLP_OE_V 0x1
#define RTC_IO_TOUCH_PAD11_SLP_OE_S 14
/* RTC_IO_TOUCH_PAD11_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
/*description: input enable in work mode.*/
#define RTC_IO_TOUCH_PAD11_FUN... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD12_RUE (BIT(27))
#define RTC_IO_TOUCH_PAD12_RUE_M (BIT(27))
#define RTC_IO_TOUCH_PAD12_RUE_V 0x1
#define RTC_IO_TOUCH_PAD12_RUE_S 27
/* RTC_IO_TOUCH_PAD12_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*description: TOUCH_START.*/
#define RTC_IO_TOUCH_PAD12_START (BIT(22))
#define RTC... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD12_MUX_SEL (BIT(19))
#define RTC_IO_TOUCH_PAD12_MUX_SEL_M (BIT(19))
#define RTC_IO_TOUCH_PAD12_MUX_SEL_V 0x1
#define RTC_IO_TOUCH_PAD12_MUX_SEL_S 19
/* RTC_IO_TOUCH_PAD12_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
/*description: function sel.*/
#define RTC_IO_TOUCH_PAD12_FUN_SEL ... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD12_SLP_OE (BIT(14))
#define RTC_IO_TOUCH_PAD12_SLP_OE_M (BIT(14))
#define RTC_IO_TOUCH_PAD12_SLP_OE_V 0x1
#define RTC_IO_TOUCH_PAD12_SLP_OE_S 14
/* RTC_IO_TOUCH_PAD12_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
/*description: input enable in work mode.*/
#define RTC_IO_TOUCH_PAD12_FUN... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD13_RUE (BIT(27))
#define RTC_IO_TOUCH_PAD13_RUE_M (BIT(27))
#define RTC_IO_TOUCH_PAD13_RUE_V 0x1
#define RTC_IO_TOUCH_PAD13_RUE_S 27
/* RTC_IO_TOUCH_PAD13_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*description: TOUCH_START.*/
#define RTC_IO_TOUCH_PAD13_START (BIT(22))
#define RTC... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD13_MUX_SEL (BIT(19))
#define RTC_IO_TOUCH_PAD13_MUX_SEL_M (BIT(19))
#define RTC_IO_TOUCH_PAD13_MUX_SEL_V 0x1
#define RTC_IO_TOUCH_PAD13_MUX_SEL_S 19
/* RTC_IO_TOUCH_PAD13_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
/*description: function sel.*/
#define RTC_IO_TOUCH_PAD13_FUN_SEL ... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD13_SLP_OE (BIT(14))
#define RTC_IO_TOUCH_PAD13_SLP_OE_M (BIT(14))
#define RTC_IO_TOUCH_PAD13_SLP_OE_V 0x1
#define RTC_IO_TOUCH_PAD13_SLP_OE_S 14
/* RTC_IO_TOUCH_PAD13_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
/*description: input enable in work mode.*/
#define RTC_IO_TOUCH_PAD13_FUN... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD14_RUE (BIT(27))
#define RTC_IO_TOUCH_PAD14_RUE_M (BIT(27))
#define RTC_IO_TOUCH_PAD14_RUE_V 0x1
#define RTC_IO_TOUCH_PAD14_RUE_S 27
/* RTC_IO_TOUCH_PAD14_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*description: TOUCH_START.*/
#define RTC_IO_TOUCH_PAD14_START (BIT(22))
#define RTC... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD14_MUX_SEL (BIT(19))
#define RTC_IO_TOUCH_PAD14_MUX_SEL_M (BIT(19))
#define RTC_IO_TOUCH_PAD14_MUX_SEL_V 0x1
#define RTC_IO_TOUCH_PAD14_MUX_SEL_S 19
/* RTC_IO_TOUCH_PAD14_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
/*description: function sel.*/
#define RTC_IO_TOUCH_PAD14_FUN_SEL ... | 2,064 |
*/
#define RTC_IO_TOUCH_PAD14_SLP_OE (BIT(14))
#define RTC_IO_TOUCH_PAD14_SLP_OE_M (BIT(14))
#define RTC_IO_TOUCH_PAD14_SLP_OE_V 0x1
#define RTC_IO_TOUCH_PAD14_SLP_OE_S 14
/* RTC_IO_TOUCH_PAD14_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
/*description: input enable in work mode.*/
#define RTC_IO_TOUCH_PAD14_FUN... | 2,064 |
*/
#define RTC_IO_X32P_RUE (BIT(27))
#define RTC_IO_X32P_RUE_M (BIT(27))
#define RTC_IO_X32P_RUE_V 0x1
#define RTC_IO_X32P_RUE_S 27
/* RTC_IO_X32P_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
/*description: 1: use RTC GPIO,0: use digital GPIO.*/
#define RTC_IO_X32P_MUX_SEL (BIT(19))
#define RTC_IO_X32P_MUX_S... | 2,064 |
*/
#define RTC_IO_X32P_SLP_IE (BIT(15))
#define RTC_IO_X32P_SLP_IE_M (BIT(15))
#define RTC_IO_X32P_SLP_IE_V 0x1
#define RTC_IO_X32P_SLP_IE_S 15
/* RTC_IO_X32P_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
/*description: output enable in sleep mode.*/
#define RTC_IO_X32P_SLP_OE (BIT(14))
#define RTC_IO_X32P_SLP... | 2,064 |
*/
#define RTC_IO_X32N_RDE (BIT(28))
#define RTC_IO_X32N_RDE_M (BIT(28))
#define RTC_IO_X32N_RDE_V 0x1
#define RTC_IO_X32N_RDE_S 28
/* RTC_IO_X32N_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
/*description: RUE.*/
#define RTC_IO_X32N_RUE (BIT(27))
#define RTC_IO_X32N_RUE_M (BIT(27))
#define RTC_IO_X32N_RUE_V 0... | 2,064 |
*/
#define RTC_IO_X32N_SLP_SEL (BIT(16))
#define RTC_IO_X32N_SLP_SEL_M (BIT(16))
#define RTC_IO_X32N_SLP_SEL_V 0x1
#define RTC_IO_X32N_SLP_SEL_S 16
/* RTC_IO_X32N_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
/*description: input enable in sleep mode.*/
#define RTC_IO_X32N_SLP_IE (BIT(15))
#define RTC_IO_X32N_... | 2,064 |
*/
#define RTC_IO_PDAC1_DRV 0x00000003
#define RTC_IO_PDAC1_DRV_M ((RTC_IO_PDAC1_DRV_V)<<(RTC_IO_PDAC1_DRV_S))
#define RTC_IO_PDAC1_DRV_V 0x3
#define RTC_IO_PDAC1_DRV_S 29
/* RTC_IO_PDAC1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
/*description: PDAC1_RDE.*/
#define RTC_IO_PDAC1_RDE (BIT(28))
#define RTC_IO_PD... | 2,064 |
*/
#define RTC_IO_PDAC1_FUN_SEL 0x00000003
#define RTC_IO_PDAC1_FUN_SEL_M ((RTC_IO_PDAC1_FUN_SEL_V)<<(RTC_IO_PDAC1_FUN_SEL_S))
#define RTC_IO_PDAC1_FUN_SEL_V 0x3
#define RTC_IO_PDAC1_FUN_SEL_S 17
/* RTC_IO_PDAC1_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
/*description: 1: enable sleep mode during sleep,0: no ... | 2,064 |
*/
#define RTC_IO_PDAC1_FUN_IE (BIT(13))
#define RTC_IO_PDAC1_FUN_IE_M (BIT(13))
#define RTC_IO_PDAC1_FUN_IE_V 0x1
#define RTC_IO_PDAC1_FUN_IE_S 13
/* RTC_IO_PDAC1_DAC_XPD_FORCE : R/W ;bitpos:[12] ;default: 1'd0 ; */
/*description: 1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC,0: use SAR ADC FSM to control
PD... | 2,064 |
*/
#define RTC_IO_PDAC2_DRV 0x00000003
#define RTC_IO_PDAC2_DRV_M ((RTC_IO_PDAC2_DRV_V)<<(RTC_IO_PDAC2_DRV_S))
#define RTC_IO_PDAC2_DRV_V 0x3
#define RTC_IO_PDAC2_DRV_S 29
/* RTC_IO_PDAC2_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
/*description: PDAC2_RDE.*/
#define RTC_IO_PDAC2_RDE (BIT(28))
#define RTC_IO_PD... | 2,064 |
*/
#define RTC_IO_PDAC2_FUN_SEL 0x00000003
#define RTC_IO_PDAC2_FUN_SEL_M ((RTC_IO_PDAC2_FUN_SEL_V)<<(RTC_IO_PDAC2_FUN_SEL_S))
#define RTC_IO_PDAC2_FUN_SEL_V 0x3
#define RTC_IO_PDAC2_FUN_SEL_S 17
/* RTC_IO_PDAC2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
/*description: 1: enable sleep mode during sleep,0: no ... | 2,064 |
*/
#define RTC_IO_PDAC2_FUN_IE (BIT(13))
#define RTC_IO_PDAC2_FUN_IE_M (BIT(13))
#define RTC_IO_PDAC2_FUN_IE_V 0x1
#define RTC_IO_PDAC2_FUN_IE_S 13
/* RTC_IO_PDAC2_DAC_XPD_FORCE : R/W ;bitpos:[12] ;default: 1'd0 ; */
/*description: 1: use reg_pdac2_xpd_dac to control PDAC2_XPD_DAC,0: use SAR ADC FSM to control
PD... | 2,064 |
*/
#define RTC_IO_PAD19_DRV 0x00000003
#define RTC_IO_PAD19_DRV_M ((RTC_IO_PAD19_DRV_V)<<(RTC_IO_PAD19_DRV_S))
#define RTC_IO_PAD19_DRV_V 0x3
#define RTC_IO_PAD19_DRV_S 29
/* RTC_IO_PAD19_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
/*description: RDE.*/
#define RTC_IO_PAD19_RDE (BIT(28))
#define RTC_IO_PAD19_RD... | 2,064 |
*/
#define RTC_IO_PAD19_SLP_SEL (BIT(16))
#define RTC_IO_PAD19_SLP_SEL_M (BIT(16))
#define RTC_IO_PAD19_SLP_SEL_V 0x1
#define RTC_IO_PAD19_SLP_SEL_S 16
/* RTC_IO_PAD19_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
/*description: input enable in sleep mode.*/
#define RTC_IO_PAD19_SLP_IE (BIT(15))
#define RTC_IO... | 2,064 |
*/
#define RTC_IO_PAD20_DRV 0x00000003
#define RTC_IO_PAD20_DRV_M ((RTC_IO_PAD20_DRV_V)<<(RTC_IO_PAD20_DRV_S))
#define RTC_IO_PAD20_DRV_V 0x3
#define RTC_IO_PAD20_DRV_S 29
/* RTC_IO_PAD20_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
/*description: RDE.*/
#define RTC_IO_PAD20_RDE (BIT(28))
#define RTC_IO_PAD20_RD... | 2,064 |
*/
#define RTC_IO_PAD20_SLP_SEL (BIT(16))
#define RTC_IO_PAD20_SLP_SEL_M (BIT(16))
#define RTC_IO_PAD20_SLP_SEL_V 0x1
#define RTC_IO_PAD20_SLP_SEL_S 16
/* RTC_IO_PAD20_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
/*description: input enable in sleep mode.*/
#define RTC_IO_PAD20_SLP_IE (BIT(15))
#define RTC_IO... | 2,064 |
*/
#define RTC_IO_PAD21_DRV 0x00000003
#define RTC_IO_PAD21_DRV_M ((RTC_IO_PAD21_DRV_V)<<(RTC_IO_PAD21_DRV_S))
#define RTC_IO_PAD21_DRV_V 0x3
#define RTC_IO_PAD21_DRV_S 29
/* RTC_IO_PAD21_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
/*description: RDE.*/
#define RTC_IO_PAD21_RDE (BIT(28))
#define RTC_IO_PAD21_RD... | 2,064 |
*/
#define RTC_IO_PAD21_SLP_SEL (BIT(16))
#define RTC_IO_PAD21_SLP_SEL_M (BIT(16))
#define RTC_IO_PAD21_SLP_SEL_V 0x1
#define RTC_IO_PAD21_SLP_SEL_S 16
/* RTC_IO_PAD21_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
/*description: input enable in sleep mode.*/
#define RTC_IO_PAD21_SLP_IE (BIT(15))
#define RTC_IO... | 2,064 |
*/
#define RTC_IO_EXT_WAKEUP0_SEL 0x0000001F
#define RTC_IO_EXT_WAKEUP0_SEL_M ((RTC_IO_EXT_WAKEUP0_SEL_V)<<(RTC_IO_EXT_WAKEUP0_SEL_S))
#define RTC_IO_EXT_WAKEUP0_SEL_V 0x1F
#define RTC_IO_EXT_WAKEUP0_SEL_S 27
#define RTC_IO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0xE0)
/* RTC_IO_XTL_EXT_CTR_SEL : R/W ;bitp... | 2,064 |
*/
#define RTC_IO_SAR_I2C_SCL_SEL 0x00000003
#define RTC_IO_SAR_I2C_SCL_SEL_M ((RTC_IO_SAR_I2C_SCL_SEL_V)<<(RTC_IO_SAR_I2C_SCL_SEL_S))
#define RTC_IO_SAR_I2C_SCL_SEL_V 0x3
#define RTC_IO_SAR_I2C_SCL_SEL_S 28
/* RTC_IO_SAR_DEBUG_BIT_SEL : R/W ;bitpos:[27:23] ;default: 5'h0 ; */
/*description: .*/
#define RTC_IO_SA... | 2,064 |
*/
#define RTC_IO_DATE 0x0FFFFFFF
#define RTC_IO_DATE_M ((RTC_IO_DATE_V)<<(RTC_IO_DATE_S))
#define RTC_IO_DATE_V 0xFFFFFFF
#define RTC_IO_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_RTC_IO_REG_H_ */
| 2,064 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of un_conf0 register
*/
typedef union {
struct {
/** filter_thres_un : R/W; bitpos: [9:0]; default: 16;
*/
uint32_t filter_thres_un: 10;
/** filter_en_un : R/W; bit... | 2,066 |
/*
*/
#ifndef _SOC_GDMA_STRUCT_H_
#define _SOC_GDMA_STRUCT_H_
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct gdma_dev_s {
struct {
struct {
union {
struct {
uint32_t in_rst : 1; /*This bit is used to res... | 2,069 |
*/
uint32_t in_check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/
uint32_t in_ext_mem_bk_size : 2; /*Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reser... | 2,069 |
*/
uint32_t in_err_eof : 1; /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.*/
uint32_t in_dscr_err ... | 2,069 |
*/
uint32_t infifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. */
uint32_t infifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is ov... | 2,069 |
*/
uint32_t in_dscr_err : 1; /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_t in_dscr_empty : 1; /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_t infifo_f... | 2,069 |
*/
uint32_t in_suc_eof : 1; /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/
uint32_t in_err_eof : 1; /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/
uint32_t in_dscr_err ... | 2,069 |
*/
uint32_t infifo_udf_l3 : 1; /*The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} int_ena;
union {
... | 2,069 |
*/
uint32_t infifo_ovf_l1 : 1; /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t infifo_udf_l1 : 1; /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t infifo_ovf_l3 ... | 2,069 |
*/
uint32_t infifo_empty_l2 : 1; /*L2 Rx FIFO empty signal for Rx channel 0.*/
uint32_t infifo_full_l3 : 1; /*L3 Rx FIFO full signal for Rx channel 0.*/
uint32_t infifo_empty_l3 : 1; /*L3 Rx FIFO empty sig... | 2,069 |
*/
uint32_t infifo_pop : 1; /*Set this bit to pop data from DMA FIFO.*/
uint32_t reserved13 : 19; /*reserved*/
};
uint32_t val;
} pop;
union {
struct {
... | 2,069 |
*/
uint32_t park : 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/
uint32_t reserved25 : 7;
};
uint32_t val;
} link;
unio... | 2,069 |
*/
uint32_t reserved12 : 20;
};
uint32_t val;
} wight;
uint32_t reserved_40;
union {
struct {
uint32_t rx_pri : 4; /*The priority of Rx channel 0.... | 2,069 |
*/
uint32_t out_loop_test : 1; /*reserved*/
uint32_t out_auto_wrback : 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/
uint32_t out_eof_mode :... | 2,069 |
*/
uint32_t out_ext_mem_bk_size : 2; /*Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/
uint32_t reserved15 : 17; /*reserved*/
};
uint32_t val;
... | 2,069 |
*/
uint32_t out_total_eof : 1; /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/
uint32_t outfifo_ovf_l1 : 1; /*This ra... | 2,069 |
*/
uint32_t out_eof : 1; /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_total_eof... | 2,069 |
*/
uint32_t out_eof : 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_total_eof ... | 2,069 |
*/
uint32_t out_eof : 1; /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_total_eof : ... | 2,069 |
*/
uint32_t outfifo_empty_l1 : 1; /*L1 Tx FIFO empty signal for Tx channel 0.*/
uint32_t outfifo_full_l2 : 1; /*L2 Tx FIFO full signal for Tx channel 0.*/
uint32_t outfifo_empty_l2 : 1; /*L2 Tx FIFO empty sig... | 2,069 |
*/
uint32_t out_remain_under_1b_l3 : 1; /*reserved*/
uint32_t out_remain_under_2b_l3 : 1; /*reserved*/
uint32_t out_remain_under_3b_l3 : 1; /*reserved*/
uint32_t out_remain_under_4b_l3 : 1; /*rese... | 2,069 |
*/
uint32_t stop : 1; /*Set this bit to stop dealing with the outlink descriptors.*/
uint32_t start : 1; /*Set this bit to start dealing with the outlink descriptors.*/
uint32_t restart ... | 2,069 |
*/
uint32_t reserved12 : 20;
};
uint32_t val;
} wight;
uint32_t reserved_a0;
union {
struct {
uint32_t tx_pri : 4; /*The priority of Tx channel 0.... | 2,069 |
0: A gate-clock will be used when accessing the RAM in DMA.*/
uint32_t reserved7 : 25;
};
uint32_t val;
} pd_conf;
union {
struct {
uint32_t ahbm_rst_inter : 1; /*Set this bit, then clear this bit to reset the internal ah... | 2,069 |
1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes.*/
uint32_t reserved7 : 25;
};
uint32_t val;
} in;
union {
struct {
uint32_t out_size : ... | 2,069 |
*/
uint32_t extmem_reject_peri_num : 6; /*This register indicate reject accessing from which peripheral.*/
uint32_t reserved12 : 20;
};
uint32_t val;
} extmem_reject_st;
union {
struct {
uint32_t extmem_reject ... | 2,069 |
*/
uint32_t reserved1 : 31; /*reserved*/
};
uint32_t val;
} extmem_reject_int_ena;
union {
struct {
uint32_t extmem_reject : 1; /*Set this bit to clear the EXTMEM_REJECT_INT interrupt.*/
uint32_t reserved1 ... | 2,069 |
/*
*/
#ifndef _SOC_GPIO_STRUCT_H_
#define _SOC_GPIO_STRUCT_H_
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct gpio_dev_s {
uint32_t bt_select;
uint32_t out;
uint32_t out_w1ts;
uint32_t out_w1tc;
union {
struct {
uint32_t data ... | 2,070 |
/*
*/
#pragma once
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
#define SOC_GDMA_TRIG_PERIPH_SPI2 (0)
#define SOC_GDMA_TRIG_PERIPH_SPI3 (1)
#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2)
#define SOC_GDMA_TRIG_PERIPH... | 2,072 |
/*
*/
#pragma once
#include "soc/interrupts.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PERIPH_LEDC_MODULE = 0,
PERIPH_UART0_MODULE,
PERIPH_UART1_MODULE,
PERIPH_UART2_MODULE,
PERIPH_USB_MODULE,
PERIPH_I2C0_MODULE,
PERIPH_I2C1_MODULE,
PERIPH_I2S0_MODULE,
PERIPH_I2S1_... | 2,073 |
/*
*/
#pragma once
#include "soc.h"
/* registers for RSA acceleration via Multiple Precision Integer ops */
#define RSA_MEM_M_BLOCK_BASE ((DR_REG_RSA_BASE)+0x000)
/* RB & Z use the same memory block, depending on phase of operation */
#define RSA_MEM_RB_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200)
#define ... | 2,074 |
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,075 |
0: 32KB, 1: 64KB.*/
#define EXTMEM_DCACHE_SIZE_MODE (BIT(2))
#define EXTMEM_DCACHE_SIZE_MODE_M (BIT(2))
#define EXTMEM_DCACHE_SIZE_MODE_V 0x1
#define EXTMEM_DCACHE_SIZE_MODE_S 2
/* EXTMEM_DCACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to activate the data cache. 0: disable, 1: ... | 2,075 |
*/
#define EXTMEM_DCACHE_SHUT_CORE0_BUS (BIT(0))
#define EXTMEM_DCACHE_SHUT_CORE0_BUS_M (BIT(0))
#define EXTMEM_DCACHE_SHUT_CORE0_BUS_V 0x1
#define EXTMEM_DCACHE_SHUT_CORE0_BUS_S 0
#define EXTMEM_DCACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x8)
/* EXTMEM_DCACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;de... | 2,075 |
1: close gating, 0:
open clock gating..*/
#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON (BIT(0))
#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_M (BIT(0))
#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_V 0x1
#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_S 0
#define EXTMEM_DCACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0xC)
/* EXTMEM... | 2,075 |
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