text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
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*/
#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF
#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S))
#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF
#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S 0
#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_REG ... | 2,075 |
*/
#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE 0x0000FFFF
#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S))
#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V 0xFFFF
#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S 16
/* EXTMEM_DCACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:... | 2,075 |
It will be cleared by hardware after
unlock operation done..*/
#define EXTMEM_DCACHE_UNLOCK_ENA (BIT(1))
#define EXTMEM_DCACHE_UNLOCK_ENA_M (BIT(1))
#define EXTMEM_DCACHE_UNLOCK_ENA_V 0x1
#define EXTMEM_DCACHE_UNLOCK_ENA_S 1
/* EXTMEM_DCACHE_LOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit ... | 2,075 |
The bits are the
counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG..*/
#define EXTMEM_DCACHE_LOCK_SIZE 0x0000FFFF
#define EXTMEM_DCACHE_LOCK_SIZE_M ((EXTMEM_DCACHE_LOCK_SIZE_V)<<(EXTMEM_DCACHE_LOCK_SIZE_S))
#define EXTMEM_DCACHE_LOCK_SIZE_V 0xFFFF
#define EXTMEM_DCACHE_LOCK_SIZE_S 0
#define... | 2,075 |
It will be cleared by hardware af
ter writeback operation done..*/
#define EXTMEM_DCACHE_WRITEBACK_ENA (BIT(1))
#define EXTMEM_DCACHE_WRITEBACK_ENA_M (BIT(1))
#define EXTMEM_DCACHE_WRITEBACK_ENA_V 0x1
#define EXTMEM_DCACHE_WRITEBACK_ENA_S 1
/* EXTMEM_DCACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*... | 2,075 |
The bits are the
counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG..*/
#define EXTMEM_DCACHE_SYNC_SIZE 0x007FFFFF
#define EXTMEM_DCACHE_SYNC_SIZE_M ((EXTMEM_DCACHE_SYNC_SIZE_V)<<(EXTMEM_DCACHE_SYNC_SIZE_S))
#define EXTMEM_DCACHE_SYNC_SIZE_V 0x7FFFFF
#define EXTMEM_DCACHE_SYNC_SIZE_S 0
#defi... | 2,075 |
I
t should be combined with DCACHE_OCCUPY_SIZE_REG..*/
#define EXTMEM_DCACHE_OCCUPY_ADDR 0xFFFFFFFF
#define EXTMEM_DCACHE_OCCUPY_ADDR_M ((EXTMEM_DCACHE_OCCUPY_ADDR_V)<<(EXTMEM_DCACHE_OCCUPY_ADDR_S))
#define EXTMEM_DCACHE_OCCUPY_ADDR_V 0xFFFFFFFF
#define EXTMEM_DCACHE_OCCUPY_ADDR_S 0
#define EXTMEM_DCACHE_OCCUPY... | 2,075 |
1: descending,
0: ascending..*/
#define EXTMEM_DCACHE_PRELOAD_ORDER (BIT(2))
#define EXTMEM_DCACHE_PRELOAD_ORDER_M (BIT(2))
#define EXTMEM_DCACHE_PRELOAD_ORDER_V 0x1
#define EXTMEM_DCACHE_PRELOAD_ORDER_S 2
/* EXTMEM_DCACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b1 ; */
/*description: The bit is used to indica... | 2,075 |
It should be combined with DCACHE_PRELOAD_SIZE_REG..*/
#define EXTMEM_DCACHE_PRELOAD_ADDR 0xFFFFFFFF
#define EXTMEM_DCACHE_PRELOAD_ADDR_M ((EXTMEM_DCACHE_PRELOAD_ADDR_V)<<(EXTMEM_DCACHE_PRELOAD_ADDR_S))
#define EXTMEM_DCACHE_PRELOAD_ADDR_V 0xFFFFFFFF
#define EXTMEM_DCACHE_PRELOAD_ADDR_S 0
#define EXTMEM_DCACHE_... | 2,075 |
.*/
#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR (BIT(9))
#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_M (BIT(9))
#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_V 0x1
#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_S 9
/* EXTMEM_DCACHE_AUTOLOAD_SIZE : R/W ;bitpos:[8:7] ;default: 2'h0 ; */
/*description: The bits are used ... | 2,075 |
1: descending, 0: asce
nding..*/
#define EXTMEM_DCACHE_AUTOLOAD_ORDER (BIT(4))
#define EXTMEM_DCACHE_AUTOLOAD_ORDER_M (BIT(4))
#define EXTMEM_DCACHE_AUTOLOAD_ORDER_V 0x1
#define EXTMEM_DCACHE_AUTOLOAD_ORDER_S 4
/* EXTMEM_DCACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b1 ; */
/*description: The bit is used to ... | 2,075 |
.*/
#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA (BIT(1))
#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_M (BIT(1))
#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_V 0x1
#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_S 1
/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bits are used to enable the ... | 2,075 |
It should be combined with dcache_autoload_sct0_ena..*/
#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE 0x07FFFFFF
#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S))
#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V 0x7FFFFFF
#define EXTMEM_DCACHE_AUTOLOAD_SC... | 2,075 |
It should be combined with dcache_autoload_sct1_ena..*/
#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE 0x07FFFFFF
#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S))
#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V 0x7FFFFFF
#define EXTMEM_DCACHE_AUTOLOAD_SC... | 2,075 |
0: 4-way, 1: 8-way.*/
#define EXTMEM_ICACHE_WAY_MODE (BIT(1))
#define EXTMEM_ICACHE_WAY_MODE_M (BIT(1))
#define EXTMEM_ICACHE_WAY_MODE_V 0x1
#define EXTMEM_ICACHE_WAY_MODE_S 1
/* EXTMEM_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to activate the data cache. 0: disable, 1: en... | 2,075 |
*/
#define EXTMEM_ICACHE_SHUT_CORE0_BUS (BIT(0))
#define EXTMEM_ICACHE_SHUT_CORE0_BUS_M (BIT(0))
#define EXTMEM_ICACHE_SHUT_CORE0_BUS_V 0x1
#define EXTMEM_ICACHE_SHUT_CORE0_BUS_S 0
#define EXTMEM_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x68)
/* EXTMEM_ICACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;d... | 2,075 |
1: close gating, 0:
open clock gating..*/
#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON (BIT(0))
#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M (BIT(0))
#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V 0x1
#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S 0
#define EXTMEM_ICACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x6C)
/* EXTM... | 2,075 |
*/
#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF
#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S))
#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF
#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S 0
#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_REG ... | 2,075 |
*/
#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE 0x0000FFFF
#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S))
#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V 0xFFFF
#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S 16
/* EXTMEM_ICACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:... | 2,075 |
It will be cleared by hardware after
unlock operation done..*/
#define EXTMEM_ICACHE_UNLOCK_ENA (BIT(1))
#define EXTMEM_ICACHE_UNLOCK_ENA_M (BIT(1))
#define EXTMEM_ICACHE_UNLOCK_ENA_V 0x1
#define EXTMEM_ICACHE_UNLOCK_ENA_S 1
/* EXTMEM_ICACHE_LOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit ... | 2,075 |
The bits are the
counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG..*/
#define EXTMEM_ICACHE_LOCK_SIZE 0x0000FFFF
#define EXTMEM_ICACHE_LOCK_SIZE_M ((EXTMEM_ICACHE_LOCK_SIZE_V)<<(EXTMEM_ICACHE_LOCK_SIZE_S))
#define EXTMEM_ICACHE_LOCK_SIZE_V 0xFFFF
#define EXTMEM_ICACHE_LOCK_SIZE_S 0
#define... | 2,075 |
I
t should be combined with ICACHE_SYNC_SIZE_REG..*/
#define EXTMEM_ICACHE_SYNC_ADDR 0xFFFFFFFF
#define EXTMEM_ICACHE_SYNC_ADDR_M ((EXTMEM_ICACHE_SYNC_ADDR_V)<<(EXTMEM_ICACHE_SYNC_ADDR_S))
#define EXTMEM_ICACHE_SYNC_ADDR_V 0xFFFFFFFF
#define EXTMEM_ICACHE_SYNC_ADDR_S 0
#define EXTMEM_ICACHE_SYNC_SIZE_REG ... | 2,075 |
1: descending,
0: ascending..*/
#define EXTMEM_ICACHE_PRELOAD_ORDER (BIT(2))
#define EXTMEM_ICACHE_PRELOAD_ORDER_M (BIT(2))
#define EXTMEM_ICACHE_PRELOAD_ORDER_V 0x1
#define EXTMEM_ICACHE_PRELOAD_ORDER_S 2
/* EXTMEM_ICACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b1 ; */
/*description: The bit is used to indica... | 2,075 |
It should be combined with ICACHE_PRELOAD_SIZE_REG..*/
#define EXTMEM_ICACHE_PRELOAD_ADDR 0xFFFFFFFF
#define EXTMEM_ICACHE_PRELOAD_ADDR_M ((EXTMEM_ICACHE_PRELOAD_ADDR_V)<<(EXTMEM_ICACHE_PRELOAD_ADDR_S))
#define EXTMEM_ICACHE_PRELOAD_ADDR_V 0xFFFFFFFF
#define EXTMEM_ICACHE_PRELOAD_ADDR_S 0
#define EXTMEM_ICACHE_... | 2,075 |
.*/
#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR (BIT(9))
#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_M (BIT(9))
#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_V 0x1
#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_S 9
/* EXTMEM_ICACHE_AUTOLOAD_SIZE : R/W ;bitpos:[8:7] ;default: 2'h0 ; */
/*description: The bits are used ... | 2,075 |
1: descending, 0: asce
nding..*/
#define EXTMEM_ICACHE_AUTOLOAD_ORDER (BIT(4))
#define EXTMEM_ICACHE_AUTOLOAD_ORDER_M (BIT(4))
#define EXTMEM_ICACHE_AUTOLOAD_ORDER_V 0x1
#define EXTMEM_ICACHE_AUTOLOAD_ORDER_S 4
/* EXTMEM_ICACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b1 ; */
/*description: The bit is used to ... | 2,075 |
.*/
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA (BIT(1))
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_M (BIT(1))
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_V 0x1
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_S 1
/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bits are used to enable the ... | 2,075 |
It should be combined with icache_autoload_sct0_ena..*/
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE 0x07FFFFFF
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S))
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V 0x7FFFFFF
#define EXTMEM_ICACHE_AUTOLOAD_SC... | 2,075 |
It should be combined with icache_autoload_sct1_ena..*/
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE 0x07FFFFFF
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S))
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V 0x7FFFFFF
#define EXTMEM_ICACHE_AUTOLOAD_SC... | 2,075 |
The register is used to give constraints to ibus access counter..*/
#define EXTMEM_IBUS_TO_FLASH_END_VADDR 0xFFFFFFFF
#define EXTMEM_IBUS_TO_FLASH_END_VADDR_M ((EXTMEM_IBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_END_VADDR_S))
#define EXTMEM_IBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF
#define EXTMEM_IBUS_TO_FLASH_E... | 2,075 |
The register is used to give constraints to dbus access counter..*/
#define EXTMEM_DBUS_TO_FLASH_END_VADDR 0xFFFFFFFF
#define EXTMEM_DBUS_TO_FLASH_END_VADDR_M ((EXTMEM_DBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_END_VADDR_S))
#define EXTMEM_DBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF
#define EXTMEM_DBUS_TO_FLASH_E... | 2,075 |
.*/
#define EXTMEM_IBUS_ACS_MISS_CNT 0xFFFFFFFF
#define EXTMEM_IBUS_ACS_MISS_CNT_M ((EXTMEM_IBUS_ACS_MISS_CNT_V)<<(EXTMEM_IBUS_ACS_MISS_CNT_S))
#define EXTMEM_IBUS_ACS_MISS_CNT_V 0xFFFFFFFF
#define EXTMEM_IBUS_ACS_MISS_CNT_S 0
#define EXTMEM_IBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xCC)
/* EXTMEM_IBUS_AC... | 2,075 |
.*/
#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT 0xFFFFFFFF
#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_M ((EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_V)<<(EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_S))
#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_V 0xFFFFFFFF
#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_S 0
#define EXTMEM_DBUS_ACS_CNT_REG (DR... | 2,075 |
.*/
#define EXTMEM_IBUS_CNT_OVF_INT_ENA (BIT(7))
#define EXTMEM_IBUS_CNT_OVF_INT_ENA_M (BIT(7))
#define EXTMEM_IBUS_CNT_OVF_INT_ENA_V 0x1
#define EXTMEM_IBUS_CNT_OVF_INT_ENA_S 7
/* EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt by dcache t... | 2,075 |
.*/
#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA (BIT(4))
#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_M (BIT(4))
#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_V 0x1
#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_S 4
/* EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: The bit is used t... | 2,075 |
.*/
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(1))
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_M (BIT(1))
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x1
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S 1
/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: ... | 2,075 |
.*/
#define EXTMEM_IBUS_CNT_OVF_INT_CLR (BIT(7))
#define EXTMEM_IBUS_CNT_OVF_INT_CLR_M (BIT(7))
#define EXTMEM_IBUS_CNT_OVF_INT_CLR_V 0x1
#define EXTMEM_IBUS_CNT_OVF_INT_CLR_S 7
/* EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR : WOD ;bitpos:[6] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt by dcache tr... | 2,075 |
.*/
#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR (BIT(4))
#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_M (BIT(4))
#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_V 0x1
#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_S 4
/* EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */
/*description: The bit is used t... | 2,075 |
.*/
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(1))
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M (BIT(1))
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x1
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S 1
/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
/*description: ... | 2,075 |
.*/
#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST (BIT(10))
#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_M (BIT(10))
#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V 0x1
#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S 10
/* EXTMEM_DBUS_ACS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: The bit is ... | 2,075 |
.*/
#define EXTMEM_IBUS_ACS_CNT_OVF_ST (BIT(7))
#define EXTMEM_IBUS_ACS_CNT_OVF_ST_M (BIT(7))
#define EXTMEM_IBUS_ACS_CNT_OVF_ST_V 0x1
#define EXTMEM_IBUS_ACS_CNT_OVF_ST_S 7
/* EXTMEM_DCACHE_OCCUPY_EXC_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by dcache trying to... | 2,075 |
.*/
#define EXTMEM_DCACHE_WRITE_FLASH_ST (BIT(4))
#define EXTMEM_DCACHE_WRITE_FLASH_ST_M (BIT(4))
#define EXTMEM_DCACHE_WRITE_FLASH_ST_V 0x1
#define EXTMEM_DCACHE_WRITE_FLASH_ST_S 4
/* EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by pr... | 2,075 |
.*/
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST (BIT(1))
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_M (BIT(1))
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V 0x1
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S 1
/* EXTMEM_ICACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to indicat... | 2,075 |
.*/
#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA (BIT(3))
#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_M (BIT(3))
#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_V 0x1
#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_S 3
/* EXTMEM_CORE0_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: The bit is ... | 2,075 |
.*/
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA (BIT(0))
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_M (BIT(0))
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V 0x1
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S 0
#define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0xEC)
/* EXTMEM_CORE0_DBU... | 2,075 |
.*/
#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR (BIT(2))
#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_M (BIT(2))
#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V 0x1
#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S 2
/* EXTMEM_CORE0_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
/*description: The bit is used to clear int... | 2,075 |
.*/
#define EXTMEM_CORE0_DBUS_REJECT_ST (BIT(4))
#define EXTMEM_CORE0_DBUS_REJECT_ST_M (BIT(4))
#define EXTMEM_CORE0_DBUS_REJECT_ST_V 0x1
#define EXTMEM_CORE0_DBUS_REJECT_ST_S 4
/* EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by cpu ... | 2,075 |
*/
#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST (BIT(1))
#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_M (BIT(1))
#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V 0x1
#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S 1
/* EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to indicate interr... | 2,075 |
.*/
#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA (BIT(3))
#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_M (BIT(3))
#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_V 0x1
#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_S 3
/* EXTMEM_CORE1_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: The bit is ... | 2,075 |
.*/
#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA (BIT(0))
#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_M (BIT(0))
#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_V 0x1
#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_S 0
#define EXTMEM_CORE1_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0xF8)
/* EXTMEM_CORE1_DBU... | 2,075 |
.*/
#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR (BIT(2))
#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_M (BIT(2))
#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_V 0x1
#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_S 2
/* EXTMEM_CORE1_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
/*description: The bit is used to clear int... | 2,075 |
.*/
#define EXTMEM_CORE1_DBUS_REJECT_ST (BIT(4))
#define EXTMEM_CORE1_DBUS_REJECT_ST_M (BIT(4))
#define EXTMEM_CORE1_DBUS_REJECT_ST_V 0x1
#define EXTMEM_CORE1_DBUS_REJECT_ST_S 4
/* EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by cpu ... | 2,075 |
*/
#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST (BIT(1))
#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_M (BIT(1))
#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_V 0x1
#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_S 1
/* EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to indicate interr... | 2,075 |
0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/
#define EXTMEM_CORE0_DBUS_ATTR 0x00000007
#define EXTMEM_CORE0_DBUS_ATTR_M ((EXTMEM_CORE0_DBUS_ATTR_V)<<(EXTMEM_CORE0_DBUS_ATTR_S))
#define EXTMEM_CORE0_DBUS_ATTR_V 0x7
#define EXTMEM_CORE0_DBUS_ATTR_S 3
/* EXTMEM_CORE0_DBUS_TAG_ATTR : RO ;bitpos:[2... | 2,075 |
.*/
#define EXTMEM_CORE0_DBUS_VADDR 0xFFFFFFFF
#define EXTMEM_CORE0_DBUS_VADDR_M ((EXTMEM_CORE0_DBUS_VADDR_V)<<(EXTMEM_CORE0_DBUS_VADDR_S))
#define EXTMEM_CORE0_DBUS_VADDR_V 0xFFFFFFFF
#define EXTMEM_CORE0_DBUS_VADDR_S 0
#define EXTMEM_CORE0_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x108)
/* EXTMEM_CORE... | 2,075 |
0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/
#define EXTMEM_CORE0_IBUS_TAG_ATTR 0x00000007
#define EXTMEM_CORE0_IBUS_TAG_ATTR_M ((EXTMEM_CORE0_IBUS_TAG_ATTR_V)<<(EXTMEM_CORE0_IBUS_TAG_ATTR_S))
#define EXTMEM_CORE0_IBUS_TAG_ATTR_V 0x7
#define EXTMEM_CORE0_IBUS_TAG_ATTR_S 0
#define EXTMEM_CORE0... | 2,075 |
0: WORLD0, 1: WORLD1.*/
#define EXTMEM_CORE1_DBUS_WORLD (BIT(6))
#define EXTMEM_CORE1_DBUS_WORLD_M (BIT(6))
#define EXTMEM_CORE1_DBUS_WORLD_V 0x1
#define EXTMEM_CORE1_DBUS_WORLD_S 6
/* EXTMEM_CORE1_DBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */
/*description: The bits are used to indicate the attribute of CPU ... | 2,075 |
.*/
#define EXTMEM_CORE1_DBUS_VADDR 0xFFFFFFFF
#define EXTMEM_CORE1_DBUS_VADDR_M ((EXTMEM_CORE1_DBUS_VADDR_V)<<(EXTMEM_CORE1_DBUS_VADDR_S))
#define EXTMEM_CORE1_DBUS_VADDR_V 0xFFFFFFFF
#define EXTMEM_CORE1_DBUS_VADDR_S 0
#define EXTMEM_CORE1_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x118)
/* EXTMEM_CORE... | 2,075 |
0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/
#define EXTMEM_CORE1_IBUS_TAG_ATTR 0x00000007
#define EXTMEM_CORE1_IBUS_TAG_ATTR_M ((EXTMEM_CORE1_IBUS_TAG_ATTR_V)<<(EXTMEM_CORE1_IBUS_TAG_ATTR_S))
#define EXTMEM_CORE1_IBUS_TAG_ATTR_V 0x7
#define EXTMEM_CORE1_IBUS_TAG_ATTR_S 0
#define EXTMEM_CORE1... | 2,075 |
0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss
evict recovery address, 5: load miss evict recovery address, 6: external dma tx,
7: external dma rx. The most significant bit is used to indicate this operation
occurs in which one icache. .*/
#define EXTMEM_CACHE_MMU_FAULT_CODE 0x0000000F
#defin... | 2,075 |
..*/
#define EXTMEM_CACHE_MMU_FAULT_VADDR 0xFFFFFFFF
#define EXTMEM_CACHE_MMU_FAULT_VADDR_M ((EXTMEM_CACHE_MMU_FAULT_VADDR_V)<<(EXTMEM_CACHE_MMU_FAULT_VADDR_S))
#define EXTMEM_CACHE_MMU_FAULT_VADDR_V 0xFFFFFFFF
#define EXTMEM_CACHE_MMU_FAULT_VADDR_S 0
#define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EX... | 2,075 |
*/
#define EXTMEM_CACHE_MMU_MEM_FORCE_PU (BIT(2))
#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_M (BIT(2))
#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_V 0x1
#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_S 2
/* EXTMEM_CACHE_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The bit is used to power mmu memory down, 0... | 2,075 |
1:
in idle state, 0: not in idle state.*/
#define EXTMEM_DCACHE_STATE 0x00000FFF
#define EXTMEM_DCACHE_STATE_M ((EXTMEM_DCACHE_STATE_V)<<(EXTMEM_DCACHE_STATE_S))
#define EXTMEM_DCACHE_STATE_V 0xFFF
#define EXTMEM_DCACHE_STATE_S 12
/* EXTMEM_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h001 ; */
/*description: ... | 2,075 |
.*/
#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT (BIT(0))
#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M (BIT(0))
#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V 0x1
#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S 0
#define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG (DR_REG_EXTMEM_BASE + 0x138)
/* EXTMEM_CLK_FORCE_ON_... | 2,075 |
1: close gating, 0:
open clock gating..*/
#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT (BIT(0))
#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_M (BIT(0))
#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V 0x1
#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S 0
#define EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_REG (DR_REG_EXTMEM_BASE +... | 2,075 |
.*/
#define EXTMEM_DCACHE_PRELOAD_INT_ENA (BIT(4))
#define EXTMEM_DCACHE_PRELOAD_INT_ENA_M (BIT(4))
#define EXTMEM_DCACHE_PRELOAD_INT_ENA_V 0x1
#define EXTMEM_DCACHE_PRELOAD_INT_ENA_S 4
/* EXTMEM_DCACHE_PRELOAD_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The bit is used to indicate the interrupt by... | 2,075 |
.*/
#define EXTMEM_ICACHE_PRELOAD_INT_ENA (BIT(1))
#define EXTMEM_ICACHE_PRELOAD_INT_ENA_M (BIT(1))
#define EXTMEM_ICACHE_PRELOAD_INT_ENA_V 0x1
#define EXTMEM_ICACHE_PRELOAD_INT_ENA_S 1
/* EXTMEM_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to indicate the interrupt by... | 2,075 |
.*/
#define EXTMEM_DCACHE_SYNC_INT_ENA (BIT(4))
#define EXTMEM_DCACHE_SYNC_INT_ENA_M (BIT(4))
#define EXTMEM_DCACHE_SYNC_INT_ENA_V 0x1
#define EXTMEM_DCACHE_SYNC_INT_ENA_S 4
/* EXTMEM_DCACHE_SYNC_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The bit is used to indicate the interrupt by dcache sync do... | 2,075 |
.*/
#define EXTMEM_ICACHE_SYNC_INT_ST (BIT(0))
#define EXTMEM_ICACHE_SYNC_INT_ST_M (BIT(0))
#define EXTMEM_ICACHE_SYNC_INT_ST_V 0x1
#define EXTMEM_ICACHE_SYNC_INT_ST_S 0
#define EXTMEM_CACHE_MMU_OWNER_REG (DR_REG_EXTMEM_BASE + 0x148)
/* EXTMEM_CACHE_MMU_OWNER : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
/*... | 2,075 |
.*/
#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT (BIT(1))
#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M (BIT(1))
#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V 0x1
#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S 1
/* EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W ;bitpos:[0] ;default: 1'b1 ; */... | 2,075 |
*/
#define EXTMEM_DCACHE_FREEZE_MODE (BIT(1))
#define EXTMEM_DCACHE_FREEZE_MODE_M (BIT(1))
#define EXTMEM_DCACHE_FREEZE_MODE_V 0x1
#define EXTMEM_DCACHE_FREEZE_MODE_S 1
/* EXTMEM_DCACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to enable dcache freeze mode.*/
#define EXTMEM_D... | 2,075 |
*/
#define EXTMEM_ICACHE_FREEZE_MODE (BIT(1))
#define EXTMEM_ICACHE_FREEZE_MODE_M (BIT(1))
#define EXTMEM_ICACHE_FREEZE_MODE_V 0x1
#define EXTMEM_ICACHE_FREEZE_MODE_S 1
/* EXTMEM_ICACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to enable icache freeze mode.*/
#define EXTMEM_I... | 2,075 |
In this case, sy
nc/lock/occupy operation can not interrupt miss-work. This feature does not work
during invalidateAll operation..*/
#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA (BIT(0))
#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_M (BIT(0))
#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_V 0x1
#define EXTMEM_DCACHE_ATOMIC_OP... | 2,075 |
This bit should be onehot with
the others fields inside this register..*/
#define EXTMEM_DCACHE_TAG_OBJECT (BIT(1))
#define EXTMEM_DCACHE_TAG_OBJECT_M (BIT(1))
#define EXTMEM_DCACHE_TAG_OBJECT_V 0x1
#define EXTMEM_DCACHE_TAG_OBJECT_S 1
/* EXTMEM_ICACHE_TAG_OBJECT : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*descripti... | 2,075 |
.*/
#define EXTMEM_CACHE_VADDR 0xFFFFFFFF
#define EXTMEM_CACHE_VADDR_M ((EXTMEM_CACHE_VADDR_V)<<(EXTMEM_CACHE_VADDR_S))
#define EXTMEM_CACHE_VADDR_V 0xFFFFFFFF
#define EXTMEM_CACHE_VADDR_S 0
#define EXTMEM_CACHE_TAG_CONTENT_REG (DR_REG_EXTMEM_BASE + 0x18C)
/* EXTMEM_CACHE_TAG_CONTENT : R/W ;bitpos:[31:0... | 2,075 |
/*
*/
#pragma once
/**
*/
#define I2C_SAR_ADC 0X69
#define I2C_SAR_ADC_HOSTID 1
#define ADC_SAR1_ENCAL_GND_ADDR 0x7
#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
#define ADC_SAR2_ENCAL_GND_ADDR 0x7
#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
#define ADC_SAR2_ENCAL_GND_ADDR_... | 2,076 |
/*
*/
#pragma once
#include
#include "soc/ext_mem_defs.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Defined for flash mmap */
#define SOC_MMU_REGIONS_COUNT 2
#define SOC_MMU_PAGES_PER_REGION 256
#define SOC_MMU_IROM0_PAGES_START (CACHE_IROM_MMU_ST... | 2,077 |
/*
*/
#ifndef _SOC_APB_CTRL_REG_H_
#define _SOC_APB_CTRL_REG_H_
#warning "apb_ctrl_reg is deprecated due to duplicated with syscon_reg, please use syscon_reg instead, they are same"
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0)
/* APB_... | 2,081 |
*/
#define APB_CTRL_PRE_DIV_CNT 0x000003FF
#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S))
#define APB_CTRL_PRE_DIV_CNT_V 0x3FF
#define APB_CTRL_PRE_DIV_CNT_S 0
#define APB_CTRL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x4)
/* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;def... | 2,081 |
*/
#define APB_CTRL_CLK_XTAL_OEN (BIT(10))
#define APB_CTRL_CLK_XTAL_OEN_M (BIT(10))
#define APB_CTRL_CLK_XTAL_OEN_V 0x1
#define APB_CTRL_CLK_XTAL_OEN_S 10
/* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
/*description: .*/
#define APB_CTRL_CLK40X_BB_OEN (BIT(9))
#define APB_CTRL_CLK40X_BB_OEN_M... | 2,081 |
*/
#define APB_CTRL_CLK160_OEN (BIT(5))
#define APB_CTRL_CLK160_OEN_M (BIT(5))
#define APB_CTRL_CLK160_OEN_V 0x1
#define APB_CTRL_CLK160_OEN_S 5
/* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: .*/
#define APB_CTRL_CLK80_OEN (BIT(4))
#define APB_CTRL_CLK80_OEN_M (BIT(4))
#define APB_... | 2,081 |
*/
#define APB_CTRL_CLK20_OEN (BIT(0))
#define APB_CTRL_CLK20_OEN_M (BIT(0))
#define APB_CTRL_CLK20_OEN_V 0x1
#define APB_CTRL_CLK20_OEN_S 0
#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_APB_CTRL_BASE + 0xC)
/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define APB_CTRL... | 2,081 |
*/
#define APB_CTRL_WIFI_CLK_EN 0xFFFFFFFF
#define APB_CTRL_WIFI_CLK_EN_M ((APB_CTRL_WIFI_CLK_EN_V)<<(APB_CTRL_WIFI_CLK_EN_S))
#define APB_CTRL_WIFI_CLK_EN_V 0xFFFFFFFF
#define APB_CTRL_WIFI_CLK_EN_S 0
#define APB_CTRL_WIFI_RST_EN_REG (DR_REG_APB_CTRL_BASE + 0x18)
/* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:... | 2,081 |
*/
#define APB_CTRL_EXT_MEM_PMS_LOCK (BIT(0))
#define APB_CTRL_EXT_MEM_PMS_LOCK_M (BIT(0))
#define APB_CTRL_EXT_MEM_PMS_LOCK_V 0x1
#define APB_CTRL_EXT_MEM_PMS_LOCK_S 0
#define APB_CTRL_EXT_MEM_WRITEBACK_BYPASS_REG (DR_REG_APB_CTRL_BASE + 0x24)
/* APB_CTRL_WRITEBACK_BYPASS : R/W ;bitpos:[0] ;default: 1'... | 2,081 |
*/
#define APB_CTRL_FLASH_ACE1_ATTR 0x000001FF
#define APB_CTRL_FLASH_ACE1_ATTR_M ((APB_CTRL_FLASH_ACE1_ATTR_V)<<(APB_CTRL_FLASH_ACE1_ATTR_S))
#define APB_CTRL_FLASH_ACE1_ATTR_V 0x1FF
#define APB_CTRL_FLASH_ACE1_ATTR_S 0
#define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x30)
/* APB_CTRL_FLAS... | 2,081 |
*/
#define APB_CTRL_FLASH_ACE0_ADDR_S 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE0_ADDR_S_M ((APB_CTRL_FLASH_ACE0_ADDR_S_V)<<(APB_CTRL_FLASH_ACE0_ADDR_S_S))
#define APB_CTRL_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE0_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x3C)... | 2,081 |
*/
#define APB_CTRL_FLASH_ACE3_ADDR_S 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE3_ADDR_S_M ((APB_CTRL_FLASH_ACE3_ADDR_S_V)<<(APB_CTRL_FLASH_ACE3_ADDR_S_S))
#define APB_CTRL_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE3_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x48)... | 2,081 |
*/
#define APB_CTRL_FLASH_ACE2_SIZE 0x0000FFFF
#define APB_CTRL_FLASH_ACE2_SIZE_M ((APB_CTRL_FLASH_ACE2_SIZE_V)<<(APB_CTRL_FLASH_ACE2_SIZE_S))
#define APB_CTRL_FLASH_ACE2_SIZE_V 0xFFFF
#define APB_CTRL_FLASH_ACE2_SIZE_S 0
#define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x54)
/* APB_CTRL_FLA... | 2,081 |
*/
#define APB_CTRL_SRAM_ACE1_ATTR 0x000001FF
#define APB_CTRL_SRAM_ACE1_ATTR_M ((APB_CTRL_SRAM_ACE1_ATTR_V)<<(APB_CTRL_SRAM_ACE1_ATTR_S))
#define APB_CTRL_SRAM_ACE1_ATTR_V 0x1FF
#define APB_CTRL_SRAM_ACE1_ATTR_S 0
#define APB_CTRL_SRAM_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x60)
/* APB_CTRL_SRAM_ACE2_A... | 2,081 |
*/
#define APB_CTRL_SRAM_ACE0_ADDR_S 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE0_ADDR_S_M ((APB_CTRL_SRAM_ACE0_ADDR_S_V)<<(APB_CTRL_SRAM_ACE0_ADDR_S_S))
#define APB_CTRL_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE0_ADDR_S_S 0
#define APB_CTRL_SRAM_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x6C)
/* APB... | 2,081 |
*/
#define APB_CTRL_SRAM_ACE3_ADDR_S 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE3_ADDR_S_M ((APB_CTRL_SRAM_ACE3_ADDR_S_V)<<(APB_CTRL_SRAM_ACE3_ADDR_S_S))
#define APB_CTRL_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE3_ADDR_S_S 0
#define APB_CTRL_SRAM_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x78)
/* APB... | 2,081 |
*/
#define APB_CTRL_SRAM_ACE2_SIZE 0x0000FFFF
#define APB_CTRL_SRAM_ACE2_SIZE_M ((APB_CTRL_SRAM_ACE2_SIZE_V)<<(APB_CTRL_SRAM_ACE2_SIZE_S))
#define APB_CTRL_SRAM_ACE2_SIZE_V 0xFFFF
#define APB_CTRL_SRAM_ACE2_SIZE_S 0
#define APB_CTRL_SRAM_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x84)
/* APB_CTRL_SRAM_ACE3_... | 2,081 |
*/
#define APB_CTRL_SPI_MEM_REJECT_CLR (BIT(1))
#define APB_CTRL_SPI_MEM_REJECT_CLR_M (BIT(1))
#define APB_CTRL_SPI_MEM_REJECT_CLR_V 0x1
#define APB_CTRL_SPI_MEM_REJECT_CLR_S 1
/* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define APB_CTRL_SPI_MEM_REJECT_INT (BIT(0))
#d... | 2,081 |
*/
#define APB_CTRL_SDIO_WIN_ACCESS_EN (BIT(0))
#define APB_CTRL_SDIO_WIN_ACCESS_EN_M (BIT(0))
#define APB_CTRL_SDIO_WIN_ACCESS_EN_V 0x1
#define APB_CTRL_SDIO_WIN_ACCESS_EN_S 0
#define APB_CTRL_REDCY_SIG0_REG (DR_REG_APB_CTRL_BASE + 0x94)
/* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*d... | 2,081 |
*/
#define APB_CTRL_REDCY_SIG1 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG1_M ((APB_CTRL_REDCY_SIG1_V)<<(APB_CTRL_REDCY_SIG1_S))
#define APB_CTRL_REDCY_SIG1_V 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG1_S 0
#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_APB_CTRL_BASE + 0x9C)
/* APB_CTRL_FREQ_MEM_FORCE_PD : R/W ;bit... | 2,081 |
*/
#define APB_CTRL_DC_MEM_FORCE_PU (BIT(4))
#define APB_CTRL_DC_MEM_FORCE_PU_M (BIT(4))
#define APB_CTRL_DC_MEM_FORCE_PU_V 0x1
#define APB_CTRL_DC_MEM_FORCE_PU_S 4
/* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: .*/
#define APB_CTRL_PBUS_MEM_FORCE_PD (BIT(3))
#define APB_CTR... | 2,081 |
*/
#define APB_CTRL_AGC_MEM_FORCE_PU (BIT(0))
#define APB_CTRL_AGC_MEM_FORCE_PU_M (BIT(0))
#define APB_CTRL_AGC_MEM_FORCE_PU_V 0x1
#define APB_CTRL_AGC_MEM_FORCE_PU_S 0
#define APB_CTRL_SPI_MEM_ECC_CTRL_REG (DR_REG_APB_CTRL_BASE + 0xA0)
/* APB_CTRL_SRAM_PAGE_SIZE : R/W ;bitpos:[21:20] ;default: 2'd2 ; *... | 2,081 |
*/
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON 0x000007FF
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_M ((APB_CTRL_SRAM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_SRAM_CLKGATE_FORCE_ON_S))
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_V 0x7FF
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_S 3
/* APB_CTRL_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;def... | 2,081 |
*/
#define APB_CTRL_ROM_POWER_DOWN 0x00000007
#define APB_CTRL_ROM_POWER_DOWN_M ((APB_CTRL_ROM_POWER_DOWN_V)<<(APB_CTRL_ROM_POWER_DOWN_S))
#define APB_CTRL_ROM_POWER_DOWN_V 0x7
#define APB_CTRL_ROM_POWER_DOWN_S 0
#define APB_CTRL_MEM_POWER_UP_REG (DR_REG_APB_CTRL_BASE + 0xB0)
/* APB_CTRL_SRAM_POWER_UP :... | 2,081 |
*/
#define APB_CTRL_NOBYPASS_CPU_ISO_RST (BIT(27))
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_M (BIT(27))
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_V 0x1
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_S 27
/* APB_CTRL_RETENTION_CPU_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
/*description: .*/
#define APB_CTRL_RETENTION_CP... | 2,081 |
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