text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
*/
#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS (BIT(18))
#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_M (BIT(18))
#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_V 0x1
#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_S 18
/* RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS : WO ;bitpos:[17] ;default: 1'b0 ; */
/*description: enable cocpu ... | 2,145 |
*/
#define RTC_CNTL_SARADC2_INT_ENA_W1TS (BIT(14))
#define RTC_CNTL_SARADC2_INT_ENA_W1TS_M (BIT(14))
#define RTC_CNTL_SARADC2_INT_ENA_W1TS_V 0x1
#define RTC_CNTL_SARADC2_INT_ENA_W1TS_S 14
/* RTC_CNTL_COCPU_INT_ENA_W1TS : WO ;bitpos:[13] ;default: 1'b0 ; */
/*description: enable riscV cocpu interrupt.*/
#define RT... | 2,145 |
*/
#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS (BIT(10))
#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M (BIT(10))
#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V 0x1
#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S 10
/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */
/*description: enable brown out interrupt.... | 2,145 |
*/
#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS (BIT(6))
#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_M (BIT(6))
#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_V 0x1
#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_S 6
/* RTC_CNTL_ULP_CP_INT_ENA_W1TS : WO ;bitpos:[5] ;default: 1'b0 ; */
/*description: enable ULP-coprocessor interrupt.... | 2,145 |
*/
#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS (BIT(2))
#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_M (BIT(2))
#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_V 0x1
#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_S 2
/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */
/*description: enable sleep reject interrupt.*/
... | 2,145 |
*/
#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC (BIT(20))
#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_M (BIT(20))
#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V 0x1
#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S 20
/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TC : WO ;bitpos:[19] ;def... | 2,145 |
*/
#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC (BIT(17))
#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_M (BIT(17))
#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_V 0x1
#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_S 17
/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC : WO ;bitpos:[16] ;default: 1'b0 ; */
/*description: enable xtal32k_dead in... | 2,145 |
*/
#define RTC_CNTL_COCPU_INT_ENA_W1TC (BIT(13))
#define RTC_CNTL_COCPU_INT_ENA_W1TC_M (BIT(13))
#define RTC_CNTL_COCPU_INT_ENA_W1TC_V 0x1
#define RTC_CNTL_COCPU_INT_ENA_W1TC_S 13
/* RTC_CNTL_TSENS_INT_ENA_W1TC : WO ;bitpos:[12] ;default: 1'b0 ; */
/*description: enable tsens interrupt.*/
#define RTC_CNTL_TSENS_I... | 2,145 |
*/
#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC (BIT(9))
#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M (BIT(9))
#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V 0x1
#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S 9
/* RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC : WO ;bitpos:[8] ;default: 1'b0 ; */
/*description: enable touch inactive interru... | 2,145 |
*/
#define RTC_CNTL_ULP_CP_INT_ENA_W1TC (BIT(5))
#define RTC_CNTL_ULP_CP_INT_ENA_W1TC_M (BIT(5))
#define RTC_CNTL_ULP_CP_INT_ENA_W1TC_V 0x1
#define RTC_CNTL_ULP_CP_INT_ENA_W1TC_S 5
/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC : WO ;bitpos:[4] ;default: 1'b0 ; */
/*description: enable touch scan done interrupt.*/
#def... | 2,145 |
*/
#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC (BIT(1))
#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M (BIT(1))
#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V 0x1
#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S 1
/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: enable sleep wakeup interrupt... | 2,145 |
*/
#define RTC_CNTL_RETENTION_EN (BIT(24))
#define RTC_CNTL_RETENTION_EN_M (BIT(24))
#define RTC_CNTL_RETENTION_EN_V 0x1
#define RTC_CNTL_RETENTION_EN_S 24
/* RTC_CNTL_RETENTION_CLKOFF_WAIT : R/W ;bitpos:[23:20] ;default: 4'd3 ; */
/*description: .*/
#define RTC_CNTL_RETENTION_CLKOFF_WAIT 0x0000000F
#define RT... | 2,145 |
*/
#define RTC_CNTL_RETENTION_TARGET 0x00000003
#define RTC_CNTL_RETENTION_TARGET_M ((RTC_CNTL_RETENTION_TARGET_V)<<(RTC_CNTL_RETENTION_TARGET_S))
#define RTC_CNTL_RETENTION_TARGET_V 0x3
#define RTC_CNTL_RETENTION_TARGET_S 14
/* RTC_CNTL_RETENTION_TAG_MODE : R/W ;bitpos:[13:10] ;default: 4'd0 ; */
/*description: ... | 2,145 |
*/
#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL (BIT(30))
#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_M (BIT(30))
#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V 0x1
#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S 30
/* RTC_CNTL_POWER_GLITCH_FORCE_PU : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: .*/
#define RTC_CNTL_POWER_GLI... | 2,145 |
*/
#define RTC_CNTL_FIB_SEL 0x00000007
#define RTC_CNTL_FIB_SEL_M ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S))
#define RTC_CNTL_FIB_SEL_V 0x7
#define RTC_CNTL_FIB_SEL_S 0
#define RTC_CNTL_FIB_GLITCH_RST BIT(0)
#define RTC_CNTL_FIB_BOD_RST BIT(1)
#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
#define RTC_CNTL_TOUCH_D... | 2,145 |
*/
#define RTC_CNTL_TOUCH_PAD2_DAC 0x00000007
#define RTC_CNTL_TOUCH_PAD2_DAC_M ((RTC_CNTL_TOUCH_PAD2_DAC_V)<<(RTC_CNTL_TOUCH_PAD2_DAC_S))
#define RTC_CNTL_TOUCH_PAD2_DAC_V 0x7
#define RTC_CNTL_TOUCH_PAD2_DAC_S 23
/* RTC_CNTL_TOUCH_PAD3_DAC : R/W ;bitpos:[22:20] ;default: 3'd0 ; */
/*description: .*/
#define RTC_... | 2,145 |
*/
#define RTC_CNTL_TOUCH_PAD6_DAC 0x00000007
#define RTC_CNTL_TOUCH_PAD6_DAC_M ((RTC_CNTL_TOUCH_PAD6_DAC_V)<<(RTC_CNTL_TOUCH_PAD6_DAC_S))
#define RTC_CNTL_TOUCH_PAD6_DAC_V 0x7
#define RTC_CNTL_TOUCH_PAD6_DAC_S 11
/* RTC_CNTL_TOUCH_PAD7_DAC : R/W ;bitpos:[10:8] ;default: 3'd0 ; */
/*description: .*/
#define RTC_C... | 2,145 |
*/
#define RTC_CNTL_TOUCH_PAD10_DAC 0x00000007
#define RTC_CNTL_TOUCH_PAD10_DAC_M ((RTC_CNTL_TOUCH_PAD10_DAC_V)<<(RTC_CNTL_TOUCH_PAD10_DAC_S))
#define RTC_CNTL_TOUCH_PAD10_DAC_V 0x7
#define RTC_CNTL_TOUCH_PAD10_DAC_S 29
/* RTC_CNTL_TOUCH_PAD11_DAC : R/W ;bitpos:[28:26] ;default: 3'd0 ; */
/*description: .*/
#defi... | 2,145 |
*/
#define RTC_CNTL_TOUCH_PAD14_DAC 0x00000007
#define RTC_CNTL_TOUCH_PAD14_DAC_M ((RTC_CNTL_TOUCH_PAD14_DAC_V)<<(RTC_CNTL_TOUCH_PAD14_DAC_S))
#define RTC_CNTL_TOUCH_PAD14_DAC_V 0x7
#define RTC_CNTL_TOUCH_PAD14_DAC_S 17
#define RTC_CNTL_COCPU_DISABLE_REG (DR_REG_RTCCNTL_BASE + 0x154)
/* RTC_CNTL_DISABLE... | 2,145 |
*/
#define RTC_CNTL_SLAVE_PD 0x0000003F
#define RTC_CNTL_SLAVE_PD_M ((RTC_CNTL_SLAVE_V)<<(RTC_CNTL_SLAVE_S))
#define RTC_CNTL_SLAVE_PD_V 0x3F
#define RTC_CNTL_SLAVE_PD_S 13
#ifdef __cplusplus
}
#endif
#endif /*_SOC_RTC_CNTL_REG_H_ */
| 2,145 |
uint32_t pktcnt: 10; // Note: Width depends on OTG_PACKET_COUNT_WIDTH (see databook).
uint32_t pid: 2;
uint32_t dopng: 1;
};
uint32_t val;
} usb_dwc_hctsiz_reg_t;
typedef union {
struct {
uint32_t dmaaddr;
};
uint32_t val;
} usb_dwc_hcdma_reg_t;
typedef union {
... | 2,146 |
uint32_t pktcnt: 10; // Note: Width depends on OTG_PACKET_COUNT_WIDTH (see databook).
uint32_t mc: 2;
uint32_t reserved: 1;
};
uint32_t val;
} usb_dwc_dieptsiz_reg_t;
typedef union {
struct {
uint32_t dmaddr;
};
uint32_t val;
} usb_dwc_diepdma_reg_t;
typedef uni... | 2,146 |
uint32_t pktcnt: 10; // Note: Width depends on OTG_PACKET_COUNT_WIDTH (see databook).
uint32_t rxdpid: 2;
uint32_t reserved_31: 1;
};
uint32_t val;
} usb_dwc_doeptsiz_reg_t;
typedef union {
struct {
uint32_t dmaaddr;
};
uint32_t val;
} usb_dwc_doepdma_reg_t;
typ... | 2,146 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
/* USB_SERIAL_JTAG_RDWR_BYTE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DE... | 2,147 |
.*/
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x1
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2
/* USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO ;bitpos:[1] ;default: 1'b1 ; */
/*des... | 2,147 |
.*/
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11))
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (BIT(11))
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x1
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS ;bitpo... | 2,147 |
.*/
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8))
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (BIT(8))
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x1
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8
/* USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'... | 2,147 |
.*/
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5))
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (BIT(5))
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x1
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5
/* USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
/*description: The raw interrupt bit t... | 2,147 |
.*/
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x1
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2
/* USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; *... | 2,147 |
.*/
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11))
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (BIT(11))
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x1
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO ;bitpos:[10] ;def... | 2,147 |
.*/
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8))
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (BIT(8))
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x1
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8
/* USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
/*d... | 2,147 |
.*/
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5))
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (BIT(5))
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x1
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5
/* USB_SERIAL_JTAG_PID_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for t... | 2,147 |
.*/
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x1
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2
/* USB_SERIAL_JTAG_SOF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*descrip... | 2,147 |
.*/
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11))
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (BIT(11))
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x1
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W ;bitpos:[10... | 2,147 |
.*/
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8))
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (BIT(8))
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x1
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8
/* USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; ... | 2,147 |
.*/
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5))
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (BIT(5))
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x1
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5
/* USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The interrupt enable bit for... | 2,147 |
.*/
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x1
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2
/* USB_SERIAL_JTAG_SOF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*d... | 2,147 |
.*/
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11))
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (BIT(11))
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x1
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT ;bitpos:[10]... | 2,147 |
.*/
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8))
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (BIT(8))
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x1
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8
/* USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; *... | 2,147 |
.*/
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5))
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (BIT(5))
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x1
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5
/* USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
/*description: Set this bit to clear the USB... | 2,147 |
.*/
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x1
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2
/* USB_SERIAL_JTAG_SOF_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
/*de... | 2,147 |
.*/
#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN (BIT(16))
#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (BIT(16))
#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x1
#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 16
/* USB_SERIAL_JTAG_PHY_TX_EDGE_SEL : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: 0: TX output at ... | 2,147 |
.*/
#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12))
#define USB_SERIAL_JTAG_DM_PULLDOWN_M (BIT(12))
#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x1
#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12
/* USB_SERIAL_JTAG_DM_PULLUP : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: Control USB D- pull up..*/
#define USB_SERIAL_JTAG... | 2,147 |
*/
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8))
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (BIT(8))
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x1
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8
/* USB_SERIAL_JTAG_VREF_OVERRIDE : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: Enable software control inp... | 2,147 |
*/
#define USB_SERIAL_JTAG_VREFH 0x00000003
#define USB_SERIAL_JTAG_VREFH_M ((USB_DEVICE_VREFH_V)<<(USB_DEVICE_VREFH_S))
#define USB_SERIAL_JTAG_VREFH_V 0x3
#define USB_SERIAL_JTAG_VREFH_S 3
/* USB_SERIAL_JTAG_EXCHG_PINS : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: USB D+ D- exchange.*/
#define USB_SERIAL... | 2,147 |
*/
#define USB_SERIAL_JTAG_TEST_RX_DM (BIT(6))
#define USB_SERIAL_JTAG_TEST_RX_DM_M (BIT(6))
#define USB_SERIAL_JTAG_TEST_RX_DM_V 0x1
#define USB_SERIAL_JTAG_TEST_RX_DM_S 6
/* USB_SERIAL_JTAG_TEST_RX_DP : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: USB D+ rx value in test.*/
#define USB_SERIAL_JTAG_TEST_RX_... | 2,147 |
*/
#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2))
#define USB_SERIAL_JTAG_TEST_TX_DP_M (BIT(2))
#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x1
#define USB_SERIAL_JTAG_TEST_TX_DP_S 2
/* USB_SERIAL_JTAG_TEST_USB_OE : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: USB pad oen in test.*/
#define USB_SERIAL_JTAG_TEST_USB_O... | 2,147 |
.*/
#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8))
#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (BIT(8))
#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x1
#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8
/* USB_SERIAL_JTAG_OUT_FIFO_FULL : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: 1: JTAG out fifo is full..*/
#define USB_SE... | 2,147 |
.*/
#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3))
#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (BIT(3))
#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x1
#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3
/* USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO ;bitpos:[2] ;default: 1'b1 ; */
/*description: 1: JTAG in fifo is empty..*/
#define USB_SERIAL... | 2,147 |
.*/
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FF
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M ((USB_DEVICE_SOF_FRAME_INDEX_V)<<(USB_DEVICE_SOF_FRAME_INDEX_S))
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x7FF
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0
#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_... | 2,147 |
.*/
#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003
#define USB_SERIAL_JTAG_IN_EP0_STATE_M ((USB_DEVICE_IN_EP0_STATE_V)<<(USB_DEVICE_IN_EP0_STATE_S))
#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x3
#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0
#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0... | 2,147 |
.*/
#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003
#define USB_SERIAL_JTAG_IN_EP1_STATE_M ((USB_DEVICE_IN_EP1_STATE_V)<<(USB_DEVICE_IN_EP1_STATE_S))
#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x3
#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0
#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0... | 2,147 |
.*/
#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003
#define USB_SERIAL_JTAG_IN_EP2_STATE_M ((USB_DEVICE_IN_EP2_STATE_V)<<(USB_DEVICE_IN_EP2_STATE_S))
#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x3
#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0
#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0... | 2,147 |
.*/
#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003
#define USB_SERIAL_JTAG_IN_EP3_STATE_M ((USB_DEVICE_IN_EP3_STATE_V)<<(USB_DEVICE_IN_EP3_STATE_S))
#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x3
#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0
#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + ... | 2,147 |
.*/
#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003
#define USB_SERIAL_JTAG_OUT_EP0_STATE_M ((USB_DEVICE_OUT_EP0_STATE_V)<<(USB_DEVICE_OUT_EP0_STATE_S))
#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x3
#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0
#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_B... | 2,147 |
When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is
detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1..*/
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M ((USB_DEVICE_OUT_EP1_WR_ADDR_V)<<(USB_DEVICE_OUT_EP1_WR_ADDR_S))
#define USB_SERIAL_JTAG_OUT_... | 2,147 |
When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is
detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2..*/
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M ((USB_DEVICE_OUT_EP2_WR_ADDR_V)<<(USB_DEVICE_OUT_EP2_WR_ADDR_S))
#define USB_SERIAL_JTAG_OUT_... | 2,147 |
.*/
#define USB_SERIAL_JTAG_CLK_EN (BIT(0))
#define USB_SERIAL_JTAG_CLK_EN_M (BIT(0))
#define USB_SERIAL_JTAG_CLK_EN_V 0x1
#define USB_SERIAL_JTAG_CLK_EN_S 0
#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
/* USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
... | 2,147 |
.*/
#define USB_SERIAL_JTAG_DATE 0xFFFFFFFF
#define USB_SERIAL_JTAG_DATE_M ((USB_DEVICE_DATE_V)<<(USB_DEVICE_DATE_S))
#define USB_SERIAL_JTAG_DATE_V 0xFFFFFFFF
#define USB_SERIAL_JTAG_DATE_S 0
#ifdef __cplusplus
}
#endif
| 2,147 |
/*
*/
#pragma once
#include "esp_bit_defs.h"
/* Analog function control register */
#define I2C_MST_ANA_CONF0_REG 0x6000E040
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define I2C_MST_BBPLL_CAL_DONE (BIT(24))
#define ANA_CONFIG_REG 0x6000E044
#define A... | 2,148 |
/*
*/
#ifndef _SOC_GDMA_REG_H_
#define _SOC_GDMA_REG_H_
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define GDMA_IN_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x0)
/* GDMA_MEM_TRANS_EN_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: Set this bit 1 to enable automatic transmitting data from memo... | 2,150 |
.*/
#define GDMA_INDSCR_BURST_EN_CH0 (BIT(2))
#define GDMA_INDSCR_BURST_EN_CH0_M (BIT(2))
#define GDMA_INDSCR_BURST_EN_CH0_V 0x1
#define GDMA_INDSCR_BURST_EN_CH0_S 2
/* GDMA_IN_LOOP_TEST_CH0 : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: reserved.*/
#define GDMA_IN_LOOP_TEST_CH0 (BIT(1))
#define GDMA_IN... | 2,150 |
.*/
#define GDMA_IN_CHECK_OWNER_CH0 (BIT(12))
#define GDMA_IN_CHECK_OWNER_CH0_M (BIT(12))
#define GDMA_IN_CHECK_OWNER_CH0_V 0x1
#define GDMA_IN_CHECK_OWNER_CH0_S 12
/* GDMA_DMA_INFIFO_FULL_THRS_CH0 : R/W ;bitpos:[11:0] ;default: 12'hc ; */
/*description: This register is used to generate the INFIFO_FULL_WM_INT in... | 2,150 |
.*/
#define GDMA_INFIFO_OVF_L3_CH0_INT_RAW (BIT(8))
#define GDMA_INFIFO_OVF_L3_CH0_INT_RAW_M (BIT(8))
#define GDMA_INFIFO_OVF_L3_CH0_INT_RAW_V 0x1
#define GDMA_INFIFO_OVF_L3_CH0_INT_RAW_S 8
/* GDMA_INFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
/*description: This raw interrupt bit turns to... | 2,150 |
.*/
#define GDMA_INFIFO_FULL_WM_CH0_INT_RAW (BIT(5))
#define GDMA_INFIFO_FULL_WM_CH0_INT_RAW_M (BIT(5))
#define GDMA_INFIFO_FULL_WM_CH0_INT_RAW_V 0x1
#define GDMA_INFIFO_FULL_WM_CH0_INT_RAW_S 5
/* GDMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
/*description: The raw interrupt bit turns ... | 2,150 |
For other peripherals, thi
s raw interrupt is reserved..*/
#define GDMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2))
#define GDMA_IN_ERR_EOF_CH0_INT_RAW_M (BIT(2))
#define GDMA_IN_ERR_EOF_CH0_INT_RAW_V 0x1
#define GDMA_IN_ERR_EOF_CH0_INT_RAW_S 2
/* GDMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
/*desc... | 2,150 |
.*/
#define GDMA_IN_DONE_CH0_INT_RAW (BIT(0))
#define GDMA_IN_DONE_CH0_INT_RAW_M (BIT(0))
#define GDMA_IN_DONE_CH0_INT_RAW_V 0x1
#define GDMA_IN_DONE_CH0_INT_RAW_S 0
#define GDMA_IN_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0xC)
/* GDMA_INFIFO_UDF_L3_CH0_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
/*descriptio... | 2,150 |
.*/
#define GDMA_INFIFO_UDF_L1_CH0_INT_ST (BIT(7))
#define GDMA_INFIFO_UDF_L1_CH0_INT_ST_M (BIT(7))
#define GDMA_INFIFO_UDF_L1_CH0_INT_ST_V 0x1
#define GDMA_INFIFO_UDF_L1_CH0_INT_ST_S 7
/* GDMA_INFIFO_OVF_L1_CH0_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the INFIFO... | 2,150 |
.*/
#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(4))
#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_M (BIT(4))
#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x1
#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S 4
/* GDMA_IN_DSCR_ERR_CH0_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the IN_DSCR_... | 2,150 |
*/
#define GDMA_IN_SUC_EOF_CH0_INT_ST (BIT(1))
#define GDMA_IN_SUC_EOF_CH0_INT_ST_M (BIT(1))
#define GDMA_IN_SUC_EOF_CH0_INT_ST_V 0x1
#define GDMA_IN_SUC_EOF_CH0_INT_ST_S 1
/* GDMA_IN_DONE_CH0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt.... | 2,150 |
.*/
#define GDMA_INFIFO_OVF_L3_CH0_INT_ENA (BIT(8))
#define GDMA_INFIFO_OVF_L3_CH0_INT_ENA_M (BIT(8))
#define GDMA_INFIFO_OVF_L3_CH0_INT_ENA_V 0x1
#define GDMA_INFIFO_OVF_L3_CH0_INT_ENA_S 8
/* GDMA_INFIFO_UDF_L1_CH0_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the INFI... | 2,150 |
.*/
#define GDMA_INFIFO_FULL_WM_CH0_INT_ENA (BIT(5))
#define GDMA_INFIFO_FULL_WM_CH0_INT_ENA_M (BIT(5))
#define GDMA_INFIFO_FULL_WM_CH0_INT_ENA_V 0x1
#define GDMA_INFIFO_FULL_WM_CH0_INT_ENA_S 5
/* GDMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the ... | 2,150 |
.*/
#define GDMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2))
#define GDMA_IN_ERR_EOF_CH0_INT_ENA_M (BIT(2))
#define GDMA_IN_ERR_EOF_CH0_INT_ENA_V 0x1
#define GDMA_IN_ERR_EOF_CH0_INT_ENA_S 2
/* GDMA_IN_SUC_EOF_CH0_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT i... | 2,150 |
.*/
#define GDMA_INFIFO_UDF_L3_CH0_INT_CLR (BIT(9))
#define GDMA_INFIFO_UDF_L3_CH0_INT_CLR_M (BIT(9))
#define GDMA_INFIFO_UDF_L3_CH0_INT_CLR_V 0x1
#define GDMA_INFIFO_UDF_L3_CH0_INT_CLR_S 9
/* GDMA_INFIFO_OVF_L3_CH0_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
/*description: Set this bit to clear the INFIFO_OVF_L... | 2,150 |
.*/
#define GDMA_INFIFO_OVF_L1_CH0_INT_CLR (BIT(6))
#define GDMA_INFIFO_OVF_L1_CH0_INT_CLR_M (BIT(6))
#define GDMA_INFIFO_OVF_L1_CH0_INT_CLR_V 0x1
#define GDMA_INFIFO_OVF_L1_CH0_INT_CLR_S 6
/* GDMA_DMA_INFIFO_FULL_WM_CH0_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
/*description: Set this bit to clear the INFIFO_... | 2,150 |
.*/
#define GDMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(3))
#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_M (BIT(3))
#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x1
#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_S 3
/* GDMA_IN_ERR_EOF_CH0_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set this bit to clear the IN_ERR_EOF_CH_INT inter... | 2,150 |
*/
#define GDMA_IN_BUF_HUNGRY_CH0 (BIT(28))
#define GDMA_IN_BUF_HUNGRY_CH0_M (BIT(28))
#define GDMA_IN_BUF_HUNGRY_CH0_V 0x1
#define GDMA_IN_BUF_HUNGRY_CH0_S 28
/* GDMA_IN_REMAIN_UNDER_4B_L3_CH0 : RO ;bitpos:[27] ;default: 1'b1 ; */
/*description: reserved.*/
#define GDMA_IN_REMAIN_UNDER_4B_L3_CH0 (BIT(27))
#de... | 2,150 |
*/
#define GDMA_IN_REMAIN_UNDER_1B_L3_CH0 (BIT(24))
#define GDMA_IN_REMAIN_UNDER_1B_L3_CH0_M (BIT(24))
#define GDMA_IN_REMAIN_UNDER_1B_L3_CH0_V 0x1
#define GDMA_IN_REMAIN_UNDER_1B_L3_CH0_S 24
/* GDMA_INFIFO_CNT_L3_CH0 : RO ;bitpos:[23:19] ;default: 5'b0 ; */
/*description: The register stores the byte number of t... | 2,150 |
.*/
#define GDMA_INFIFO_CNT_L1_CH0 0x0000003F
#define GDMA_INFIFO_CNT_L1_CH0_M ((GDMA_INFIFO_CNT_L1_CH0_V)<<(GDMA_INFIFO_CNT_L1_CH0_S))
#define GDMA_INFIFO_CNT_L1_CH0_V 0x3F
#define GDMA_INFIFO_CNT_L1_CH0_S 6
/* GDMA_INFIFO_EMPTY_L3_CH0 : RO ;bitpos:[5] ;default: 1'b1 ; */
/*description: L3 Rx FIFO empty signal f... | 2,150 |
.*/
#define GDMA_INFIFO_FULL_L2_CH0 (BIT(2))
#define GDMA_INFIFO_FULL_L2_CH0_M (BIT(2))
#define GDMA_INFIFO_FULL_L2_CH0_V 0x1
#define GDMA_INFIFO_FULL_L2_CH0_S 2
/* GDMA_INFIFO_EMPTY_L1_CH0 : RO ;bitpos:[1] ;default: 1'b1 ; */
/*description: L1 Rx FIFO empty signal for Rx channel 0..*/
#define GDMA_INFIFO_EMPTY_L... | 2,150 |
.*/
#define GDMA_INFIFO_RDATA_CH0 0x00000FFF
#define GDMA_INFIFO_RDATA_CH0_M ((GDMA_INFIFO_RDATA_CH0_V)<<(GDMA_INFIFO_RDATA_CH0_S))
#define GDMA_INFIFO_RDATA_CH0_V 0xFFF
#define GDMA_INFIFO_RDATA_CH0_S 0
#define GDMA_IN_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x20)
/* GDMA_INLINK_PARK_CH0 : RO ;bitpos:[24] ;de... | 2,150 |
.*/
#define GDMA_INLINK_START_CH0 (BIT(22))
#define GDMA_INLINK_START_CH0_M (BIT(22))
#define GDMA_INLINK_START_CH0_V 0x1
#define GDMA_INLINK_START_CH0_S 22
/* GDMA_INLINK_STOP_CH0 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
/*description: Set this bit to stop dealing with the inlink descriptors..*/
#define GDMA_IN... | 2,150 |
.*/
#define GDMA_INLINK_ADDR_CH0 0x000FFFFF
#define GDMA_INLINK_ADDR_CH0_M ((GDMA_INLINK_ADDR_CH0_V)<<(GDMA_INLINK_ADDR_CH0_S))
#define GDMA_INLINK_ADDR_CH0_V 0xFFFFF
#define GDMA_INLINK_ADDR_CH0_S 0
#define GDMA_IN_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x24)
/* GDMA_IN_STATE_CH0 : RO ;bitpos:[22:20] ;defau... | 2,150 |
.*/
#define GDMA_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFF
#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH0_V)<<(GDMA_IN_SUC_EOF_DES_ADDR_CH0_S))
#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFF
#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_S 0
#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA... | 2,150 |
.*/
#define GDMA_INLINK_DSCR_CH0 0xFFFFFFFF
#define GDMA_INLINK_DSCR_CH0_M ((GDMA_INLINK_DSCR_CH0_V)<<(GDMA_INLINK_DSCR_CH0_S))
#define GDMA_INLINK_DSCR_CH0_V 0xFFFFFFFF
#define GDMA_INLINK_DSCR_CH0_S 0
#define GDMA_IN_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0x34)
/* GDMA_INLINK_DSCR_BF0_CH0 : RO ;bitpos:[... | 2,150 |
.*/
#define GDMA_RX_WEIGHT_CH0 0x0000000F
#define GDMA_RX_WEIGHT_CH0_M ((GDMA_RX_WEIGHT_CH0_V)<<(GDMA_RX_WEIGHT_CH0_S))
#define GDMA_RX_WEIGHT_CH0_V 0xF
#define GDMA_RX_WEIGHT_CH0_S 8
#define GDMA_IN_PRI_CH0_REG (DR_REG_GDMA_BASE + 0x44)
/* GDMA_RX_PRI_CH0 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*desc... | 2,150 |
.*/
#define GDMA_OUT_DATA_BURST_EN_CH0 (BIT(5))
#define GDMA_OUT_DATA_BURST_EN_CH0_M (BIT(5))
#define GDMA_OUT_DATA_BURST_EN_CH0_V 0x1
#define GDMA_OUT_DATA_BURST_EN_CH0_S 5
/* GDMA_OUTDSCR_BURST_EN_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: Set this bit to 1 to enable INCR burst transfer for Tx ch... | 2,150 |
.*/
#define GDMA_OUT_AUTO_WRBACK_CH0 (BIT(2))
#define GDMA_OUT_AUTO_WRBACK_CH0_M (BIT(2))
#define GDMA_OUT_AUTO_WRBACK_CH0_V 0x1
#define GDMA_OUT_AUTO_WRBACK_CH0_S 2
/* GDMA_OUT_LOOP_TEST_CH0 : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: reserved.*/
#define GDMA_OUT_LOOP_TEST_CH0 (BIT(1))
#define GDMA_O... | 2,150 |
.*/
#define GDMA_OUT_CHECK_OWNER_CH0 (BIT(12))
#define GDMA_OUT_CHECK_OWNER_CH0_M (BIT(12))
#define GDMA_OUT_CHECK_OWNER_CH0_V 0x1
#define GDMA_OUT_CHECK_OWNER_CH0_S 12
#define GDMA_OUT_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x68)
/* GDMA_OUTFIFO_UDF_L3_CH0_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; *... | 2,150 |
.*/
#define GDMA_OUTFIFO_UDF_L1_CH0_INT_RAW (BIT(5))
#define GDMA_OUTFIFO_UDF_L1_CH0_INT_RAW_M (BIT(5))
#define GDMA_OUTFIFO_UDF_L1_CH0_INT_RAW_V 0x1
#define GDMA_OUTFIFO_UDF_L1_CH0_INT_RAW_S 5
/* GDMA_OUTFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
/*description: This raw interrupt bit tur... | 2,150 |
.*/
#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(2))
#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_M (BIT(2))
#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x1
#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S 2
/* GDMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
/*description: The raw interrupt bit turns to high level ... | 2,150 |
.*/
#define GDMA_OUTFIFO_UDF_L3_CH0_INT_ST (BIT(7))
#define GDMA_OUTFIFO_UDF_L3_CH0_INT_ST_M (BIT(7))
#define GDMA_OUTFIFO_UDF_L3_CH0_INT_ST_V 0x1
#define GDMA_OUTFIFO_UDF_L3_CH0_INT_ST_S 7
/* GDMA_OUTFIFO_OVF_L3_CH0_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the O... | 2,150 |
.*/
#define GDMA_OUTFIFO_OVF_L1_CH0_INT_ST (BIT(4))
#define GDMA_OUTFIFO_OVF_L1_CH0_INT_ST_M (BIT(4))
#define GDMA_OUTFIFO_OVF_L1_CH0_INT_ST_V 0x1
#define GDMA_OUTFIFO_OVF_L1_CH0_INT_ST_S 4
/* GDMA_OUT_TOTAL_EOF_CH0_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the OU... | 2,150 |
.*/
#define GDMA_OUT_EOF_CH0_INT_ST (BIT(1))
#define GDMA_OUT_EOF_CH0_INT_ST_M (BIT(1))
#define GDMA_OUT_EOF_CH0_INT_ST_V 0x1
#define GDMA_OUT_EOF_CH0_INT_ST_S 1
/* GDMA_OUT_DONE_CH0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt..*/
#defi... | 2,150 |
.*/
#define GDMA_OUTFIFO_OVF_L3_CH0_INT_ENA (BIT(6))
#define GDMA_OUTFIFO_OVF_L3_CH0_INT_ENA_M (BIT(6))
#define GDMA_OUTFIFO_OVF_L3_CH0_INT_ENA_V 0x1
#define GDMA_OUTFIFO_OVF_L3_CH0_INT_ENA_S 6
/* GDMA_OUTFIFO_UDF_L1_CH0_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the... | 2,150 |
.*/
#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(3))
#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (BIT(3))
#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x1
#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 3
/* GDMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the OUT_D... | 2,150 |
.*/
#define GDMA_OUTFIFO_UDF_L3_CH0_INT_CLR (BIT(7))
#define GDMA_OUTFIFO_UDF_L3_CH0_INT_CLR_M (BIT(7))
#define GDMA_OUTFIFO_UDF_L3_CH0_INT_CLR_V 0x1
#define GDMA_OUTFIFO_UDF_L3_CH0_INT_CLR_S 7
/* GDMA_OUTFIFO_OVF_L3_CH0_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
/*description: Set this bit to clear the OUTFIFO... | 2,150 |
.*/
#define GDMA_OUTFIFO_OVF_L1_CH0_INT_CLR (BIT(4))
#define GDMA_OUTFIFO_OVF_L1_CH0_INT_CLR_M (BIT(4))
#define GDMA_OUTFIFO_OVF_L1_CH0_INT_CLR_V 0x1
#define GDMA_OUTFIFO_OVF_L1_CH0_INT_CLR_S 4
/* GDMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
/*description: Set this bit to clear the OUT_TOTA... | 2,150 |
.*/
#define GDMA_OUT_EOF_CH0_INT_CLR (BIT(1))
#define GDMA_OUT_EOF_CH0_INT_CLR_M (BIT(1))
#define GDMA_OUT_EOF_CH0_INT_CLR_V 0x1
#define GDMA_OUT_EOF_CH0_INT_CLR_S 1
/* GDMA_OUT_DONE_CH0_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt..*/
#define GDM... | 2,150 |
*/
#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH0 (BIT(24))
#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH0_M (BIT(24))
#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH0_V 0x1
#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH0_S 24
/* GDMA_OUT_REMAIN_UNDER_1B_L3_CH0 : RO ;bitpos:[23] ;default: 1'b1 ; */
/*description: reserved.*/
#define GDMA_OUT_R... | 2,150 |
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