text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
.*/
#define GDMA_OUTFIFO_CNT_L2_CH0 0x0000007F
#define GDMA_OUTFIFO_CNT_L2_CH0_M ((GDMA_OUTFIFO_CNT_L2_CH0_V)<<(GDMA_OUTFIFO_CNT_L2_CH0_S))
#define GDMA_OUTFIFO_CNT_L2_CH0_V 0x7F
#define GDMA_OUTFIFO_CNT_L2_CH0_S 11
/* GDMA_OUTFIFO_CNT_L1_CH0 : RO ;bitpos:[10:6] ;default: 5'b0 ; */
/*description: The register sto... | 2,150 |
.*/
#define GDMA_OUTFIFO_FULL_L3_CH0 (BIT(4))
#define GDMA_OUTFIFO_FULL_L3_CH0_M (BIT(4))
#define GDMA_OUTFIFO_FULL_L3_CH0_V 0x1
#define GDMA_OUTFIFO_FULL_L3_CH0_S 4
/* GDMA_OUTFIFO_EMPTY_L2_CH0 : RO ;bitpos:[3] ;default: 1'b1 ; */
/*description: L2 Tx FIFO empty signal for Tx channel 0..*/
#define GDMA_OUTFIFO_E... | 2,150 |
.*/
#define GDMA_OUTFIFO_FULL_L1_CH0 (BIT(0))
#define GDMA_OUTFIFO_FULL_L1_CH0_M (BIT(0))
#define GDMA_OUTFIFO_FULL_L1_CH0_V 0x1
#define GDMA_OUTFIFO_FULL_L1_CH0_S 0
#define GDMA_OUT_PUSH_CH0_REG (DR_REG_GDMA_BASE + 0x7C)
/* GDMA_OUTFIFO_PUSH_CH0 : R/W/SC ;bitpos:[9] ;default: 1'h0 ; */
/*description: S... | 2,150 |
0: the outlink descriptor's F
SM is working..*/
#define GDMA_OUTLINK_PARK_CH0 (BIT(23))
#define GDMA_OUTLINK_PARK_CH0_M (BIT(23))
#define GDMA_OUTLINK_PARK_CH0_V 0x1
#define GDMA_OUTLINK_PARK_CH0_S 23
/* GDMA_OUTLINK_RESTART_CH0 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
/*description: Set this bit to restart a ... | 2,150 |
.*/
#define GDMA_OUTLINK_ADDR_CH0 0x000FFFFF
#define GDMA_OUTLINK_ADDR_CH0_M ((GDMA_OUTLINK_ADDR_CH0_V)<<(GDMA_OUTLINK_ADDR_CH0_S))
#define GDMA_OUTLINK_ADDR_CH0_V 0xFFFFF
#define GDMA_OUTLINK_ADDR_CH0_S 0
#define GDMA_OUT_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x84)
/* GDMA_OUT_STATE_CH0 : RO ;bitpos:[22:20... | 2,150 |
.*/
#define GDMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFF
#define GDMA_OUTLINK_DSCR_ADDR_CH0_M ((GDMA_OUTLINK_DSCR_ADDR_CH0_V)<<(GDMA_OUTLINK_DSCR_ADDR_CH0_S))
#define GDMA_OUTLINK_DSCR_ADDR_CH0_V 0x3FFFF
#define GDMA_OUTLINK_DSCR_ADDR_CH0_S 0
#define GDMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x88)
/* G... | 2,150 |
.*/
#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0 0xFFFFFFFF
#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_M ((GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V)<<(GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S))
#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V 0xFFFFFFFF
#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0
#define GDMA_OUT_DSCR_CH0_REG (DR_REG_GDMA_BASE... | 2,150 |
.*/
#define GDMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFF
#define GDMA_OUTLINK_DSCR_BF1_CH0_M ((GDMA_OUTLINK_DSCR_BF1_CH0_V)<<(GDMA_OUTLINK_DSCR_BF1_CH0_S))
#define GDMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFF
#define GDMA_OUTLINK_DSCR_BF1_CH0_S 0
#define GDMA_OUT_WIGHT_CH0_REG (DR_REG_GDMA_BASE + 0x9C)
/* GDMA_TX_WEI... | 2,150 |
0:SPI2. 1: SPI3. 2:
UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT.; 7: AE
S. 8: SHA. 9: ADC_DAC..*/
#define GDMA_PERI_OUT_SEL_CH0 0x0000003F
#define GDMA_PERI_OUT_SEL_CH0_M ((GDMA_PERI_OUT_SEL_CH0_V)<<(GDMA_PERI_OUT_SEL_CH0_S))
#define GDMA_PERI_OUT_SEL_CH0_V 0x3F
#define GDMA_PERI_OUT_... | 2,150 |
.*/
#define GDMA_INDSCR_BURST_EN_CH1 (BIT(2))
#define GDMA_INDSCR_BURST_EN_CH1_M (BIT(2))
#define GDMA_INDSCR_BURST_EN_CH1_V 0x1
#define GDMA_INDSCR_BURST_EN_CH1_S 2
/* GDMA_IN_LOOP_TEST_CH1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: reserved.*/
#define GDMA_IN_LOOP_TEST_CH1 (BIT(1))
#define GDMA_IN... | 2,150 |
.*/
#define GDMA_IN_CHECK_OWNER_CH1 (BIT(12))
#define GDMA_IN_CHECK_OWNER_CH1_M (BIT(12))
#define GDMA_IN_CHECK_OWNER_CH1_V 0x1
#define GDMA_IN_CHECK_OWNER_CH1_S 12
/* GDMA_DMA_INFIFO_FULL_THRS_CH1 : R/W ;bitpos:[11:0] ;default: 12'hc ; */
/*description: This register is used to generate the INFIFO_FULL_WM_INT in... | 2,150 |
.*/
#define GDMA_INFIFO_OVF_L3_CH1_INT_RAW (BIT(8))
#define GDMA_INFIFO_OVF_L3_CH1_INT_RAW_M (BIT(8))
#define GDMA_INFIFO_OVF_L3_CH1_INT_RAW_V 0x1
#define GDMA_INFIFO_OVF_L3_CH1_INT_RAW_S 8
/* GDMA_INFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
/*description: This raw interrupt bit turns to... | 2,150 |
.*/
#define GDMA_INFIFO_FULL_WM_CH1_INT_RAW (BIT(5))
#define GDMA_INFIFO_FULL_WM_CH1_INT_RAW_M (BIT(5))
#define GDMA_INFIFO_FULL_WM_CH1_INT_RAW_V 0x1
#define GDMA_INFIFO_FULL_WM_CH1_INT_RAW_S 5
/* GDMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
/*description: The raw interrupt bit turns ... | 2,150 |
For other peripherals, thi
s raw interrupt is reserved..*/
#define GDMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2))
#define GDMA_IN_ERR_EOF_CH1_INT_RAW_M (BIT(2))
#define GDMA_IN_ERR_EOF_CH1_INT_RAW_V 0x1
#define GDMA_IN_ERR_EOF_CH1_INT_RAW_S 2
/* GDMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
/*desc... | 2,150 |
.*/
#define GDMA_IN_DONE_CH1_INT_RAW (BIT(0))
#define GDMA_IN_DONE_CH1_INT_RAW_M (BIT(0))
#define GDMA_IN_DONE_CH1_INT_RAW_V 0x1
#define GDMA_IN_DONE_CH1_INT_RAW_S 0
#define GDMA_IN_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0xCC)
/* GDMA_INFIFO_UDF_L3_CH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
/*descripti... | 2,150 |
.*/
#define GDMA_INFIFO_UDF_L1_CH1_INT_ST (BIT(7))
#define GDMA_INFIFO_UDF_L1_CH1_INT_ST_M (BIT(7))
#define GDMA_INFIFO_UDF_L1_CH1_INT_ST_V 0x1
#define GDMA_INFIFO_UDF_L1_CH1_INT_ST_S 7
/* GDMA_INFIFO_OVF_L1_CH1_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the INFIFO... | 2,150 |
.*/
#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST (BIT(4))
#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_M (BIT(4))
#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_V 0x1
#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_S 4
/* GDMA_IN_DSCR_ERR_CH1_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the IN_DSCR_... | 2,150 |
*/
#define GDMA_IN_SUC_EOF_CH1_INT_ST (BIT(1))
#define GDMA_IN_SUC_EOF_CH1_INT_ST_M (BIT(1))
#define GDMA_IN_SUC_EOF_CH1_INT_ST_V 0x1
#define GDMA_IN_SUC_EOF_CH1_INT_ST_S 1
/* GDMA_IN_DONE_CH1_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt.... | 2,150 |
.*/
#define GDMA_INFIFO_OVF_L3_CH1_INT_ENA (BIT(8))
#define GDMA_INFIFO_OVF_L3_CH1_INT_ENA_M (BIT(8))
#define GDMA_INFIFO_OVF_L3_CH1_INT_ENA_V 0x1
#define GDMA_INFIFO_OVF_L3_CH1_INT_ENA_S 8
/* GDMA_INFIFO_UDF_L1_CH1_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the INFI... | 2,150 |
.*/
#define GDMA_INFIFO_FULL_WM_CH1_INT_ENA (BIT(5))
#define GDMA_INFIFO_FULL_WM_CH1_INT_ENA_M (BIT(5))
#define GDMA_INFIFO_FULL_WM_CH1_INT_ENA_V 0x1
#define GDMA_INFIFO_FULL_WM_CH1_INT_ENA_S 5
/* GDMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the ... | 2,150 |
.*/
#define GDMA_IN_ERR_EOF_CH1_INT_ENA (BIT(2))
#define GDMA_IN_ERR_EOF_CH1_INT_ENA_M (BIT(2))
#define GDMA_IN_ERR_EOF_CH1_INT_ENA_V 0x1
#define GDMA_IN_ERR_EOF_CH1_INT_ENA_S 2
/* GDMA_IN_SUC_EOF_CH1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT i... | 2,150 |
.*/
#define GDMA_INFIFO_UDF_L3_CH1_INT_CLR (BIT(9))
#define GDMA_INFIFO_UDF_L3_CH1_INT_CLR_M (BIT(9))
#define GDMA_INFIFO_UDF_L3_CH1_INT_CLR_V 0x1
#define GDMA_INFIFO_UDF_L3_CH1_INT_CLR_S 9
/* GDMA_INFIFO_OVF_L3_CH1_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
/*description: Set this bit to clear the INFIFO_OVF_L... | 2,150 |
.*/
#define GDMA_INFIFO_OVF_L1_CH1_INT_CLR (BIT(6))
#define GDMA_INFIFO_OVF_L1_CH1_INT_CLR_M (BIT(6))
#define GDMA_INFIFO_OVF_L1_CH1_INT_CLR_V 0x1
#define GDMA_INFIFO_OVF_L1_CH1_INT_CLR_S 6
/* GDMA_DMA_INFIFO_FULL_WM_CH1_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
/*description: Set this bit to clear the INFIFO_... | 2,150 |
.*/
#define GDMA_IN_DSCR_ERR_CH1_INT_CLR (BIT(3))
#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_M (BIT(3))
#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_V 0x1
#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_S 3
/* GDMA_IN_ERR_EOF_CH1_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set this bit to clear the IN_ERR_EOF_CH_INT inter... | 2,150 |
*/
#define GDMA_IN_BUF_HUNGRY_CH1 (BIT(28))
#define GDMA_IN_BUF_HUNGRY_CH1_M (BIT(28))
#define GDMA_IN_BUF_HUNGRY_CH1_V 0x1
#define GDMA_IN_BUF_HUNGRY_CH1_S 28
/* GDMA_IN_REMAIN_UNDER_4B_L3_CH1 : RO ;bitpos:[27] ;default: 1'b1 ; */
/*description: reserved.*/
#define GDMA_IN_REMAIN_UNDER_4B_L3_CH1 (BIT(27))
#de... | 2,150 |
*/
#define GDMA_IN_REMAIN_UNDER_1B_L3_CH1 (BIT(24))
#define GDMA_IN_REMAIN_UNDER_1B_L3_CH1_M (BIT(24))
#define GDMA_IN_REMAIN_UNDER_1B_L3_CH1_V 0x1
#define GDMA_IN_REMAIN_UNDER_1B_L3_CH1_S 24
/* GDMA_INFIFO_CNT_L3_CH1 : RO ;bitpos:[23:19] ;default: 5'b0 ; */
/*description: The register stores the byte number of t... | 2,150 |
.*/
#define GDMA_INFIFO_CNT_L1_CH1 0x0000003F
#define GDMA_INFIFO_CNT_L1_CH1_M ((GDMA_INFIFO_CNT_L1_CH1_V)<<(GDMA_INFIFO_CNT_L1_CH1_S))
#define GDMA_INFIFO_CNT_L1_CH1_V 0x3F
#define GDMA_INFIFO_CNT_L1_CH1_S 6
/* GDMA_INFIFO_EMPTY_L3_CH1 : RO ;bitpos:[5] ;default: 1'b1 ; */
/*description: L3 Rx FIFO empty signal f... | 2,150 |
.*/
#define GDMA_INFIFO_FULL_L2_CH1 (BIT(2))
#define GDMA_INFIFO_FULL_L2_CH1_M (BIT(2))
#define GDMA_INFIFO_FULL_L2_CH1_V 0x1
#define GDMA_INFIFO_FULL_L2_CH1_S 2
/* GDMA_INFIFO_EMPTY_L1_CH1 : RO ;bitpos:[1] ;default: 1'b1 ; */
/*description: L1 Rx FIFO empty signal for Rx channel 1..*/
#define GDMA_INFIFO_EMPTY_L... | 2,150 |
.*/
#define GDMA_INFIFO_RDATA_CH1 0x00000FFF
#define GDMA_INFIFO_RDATA_CH1_M ((GDMA_INFIFO_RDATA_CH1_V)<<(GDMA_INFIFO_RDATA_CH1_S))
#define GDMA_INFIFO_RDATA_CH1_V 0xFFF
#define GDMA_INFIFO_RDATA_CH1_S 0
#define GDMA_IN_LINK_CH1_REG (DR_REG_GDMA_BASE + 0xE0)
/* GDMA_INLINK_PARK_CH1 : RO ;bitpos:[24] ;de... | 2,150 |
.*/
#define GDMA_INLINK_START_CH1 (BIT(22))
#define GDMA_INLINK_START_CH1_M (BIT(22))
#define GDMA_INLINK_START_CH1_V 0x1
#define GDMA_INLINK_START_CH1_S 22
/* GDMA_INLINK_STOP_CH1 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
/*description: Set this bit to stop dealing with the inlink descriptors..*/
#define GDMA_IN... | 2,150 |
.*/
#define GDMA_INLINK_ADDR_CH1 0x000FFFFF
#define GDMA_INLINK_ADDR_CH1_M ((GDMA_INLINK_ADDR_CH1_V)<<(GDMA_INLINK_ADDR_CH1_S))
#define GDMA_INLINK_ADDR_CH1_V 0xFFFFF
#define GDMA_INLINK_ADDR_CH1_S 0
#define GDMA_IN_STATE_CH1_REG (DR_REG_GDMA_BASE + 0xE4)
/* GDMA_IN_STATE_CH1 : RO ;bitpos:[22:20] ;defau... | 2,150 |
.*/
#define GDMA_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFF
#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH1_V)<<(GDMA_IN_SUC_EOF_DES_ADDR_CH1_S))
#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFF
#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_S 0
#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA... | 2,150 |
.*/
#define GDMA_INLINK_DSCR_CH1 0xFFFFFFFF
#define GDMA_INLINK_DSCR_CH1_M ((GDMA_INLINK_DSCR_CH1_V)<<(GDMA_INLINK_DSCR_CH1_S))
#define GDMA_INLINK_DSCR_CH1_V 0xFFFFFFFF
#define GDMA_INLINK_DSCR_CH1_S 0
#define GDMA_IN_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0xF4)
/* GDMA_INLINK_DSCR_BF0_CH1 : RO ;bitpos:[... | 2,150 |
.*/
#define GDMA_RX_WEIGHT_CH1 0x0000000F
#define GDMA_RX_WEIGHT_CH1_M ((GDMA_RX_WEIGHT_CH1_V)<<(GDMA_RX_WEIGHT_CH1_S))
#define GDMA_RX_WEIGHT_CH1_V 0xF
#define GDMA_RX_WEIGHT_CH1_S 8
#define GDMA_IN_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x104)
/* GDMA_RX_PRI_CH1 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*des... | 2,150 |
.*/
#define GDMA_OUT_DATA_BURST_EN_CH1 (BIT(5))
#define GDMA_OUT_DATA_BURST_EN_CH1_M (BIT(5))
#define GDMA_OUT_DATA_BURST_EN_CH1_V 0x1
#define GDMA_OUT_DATA_BURST_EN_CH1_S 5
/* GDMA_OUTDSCR_BURST_EN_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: Set this bit to 1 to enable INCR burst transfer for Tx ch... | 2,150 |
.*/
#define GDMA_OUT_AUTO_WRBACK_CH1 (BIT(2))
#define GDMA_OUT_AUTO_WRBACK_CH1_M (BIT(2))
#define GDMA_OUT_AUTO_WRBACK_CH1_V 0x1
#define GDMA_OUT_AUTO_WRBACK_CH1_S 2
/* GDMA_OUT_LOOP_TEST_CH1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: reserved.*/
#define GDMA_OUT_LOOP_TEST_CH1 (BIT(1))
#define GDMA_O... | 2,150 |
.*/
#define GDMA_OUT_CHECK_OWNER_CH1 (BIT(12))
#define GDMA_OUT_CHECK_OWNER_CH1_M (BIT(12))
#define GDMA_OUT_CHECK_OWNER_CH1_V 0x1
#define GDMA_OUT_CHECK_OWNER_CH1_S 12
#define GDMA_OUT_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x128)
/* GDMA_OUTFIFO_UDF_L3_CH1_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; ... | 2,150 |
.*/
#define GDMA_OUTFIFO_UDF_L1_CH1_INT_RAW (BIT(5))
#define GDMA_OUTFIFO_UDF_L1_CH1_INT_RAW_M (BIT(5))
#define GDMA_OUTFIFO_UDF_L1_CH1_INT_RAW_V 0x1
#define GDMA_OUTFIFO_UDF_L1_CH1_INT_RAW_S 5
/* GDMA_OUTFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
/*description: This raw interrupt bit tur... | 2,150 |
.*/
#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(2))
#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_M (BIT(2))
#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x1
#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_S 2
/* GDMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
/*description: The raw interrupt bit turns to high level ... | 2,150 |
.*/
#define GDMA_OUTFIFO_UDF_L3_CH1_INT_ST (BIT(7))
#define GDMA_OUTFIFO_UDF_L3_CH1_INT_ST_M (BIT(7))
#define GDMA_OUTFIFO_UDF_L3_CH1_INT_ST_V 0x1
#define GDMA_OUTFIFO_UDF_L3_CH1_INT_ST_S 7
/* GDMA_OUTFIFO_OVF_L3_CH1_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the O... | 2,150 |
.*/
#define GDMA_OUTFIFO_OVF_L1_CH1_INT_ST (BIT(4))
#define GDMA_OUTFIFO_OVF_L1_CH1_INT_ST_M (BIT(4))
#define GDMA_OUTFIFO_OVF_L1_CH1_INT_ST_V 0x1
#define GDMA_OUTFIFO_OVF_L1_CH1_INT_ST_S 4
/* GDMA_OUT_TOTAL_EOF_CH1_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the OU... | 2,150 |
.*/
#define GDMA_OUT_EOF_CH1_INT_ST (BIT(1))
#define GDMA_OUT_EOF_CH1_INT_ST_M (BIT(1))
#define GDMA_OUT_EOF_CH1_INT_ST_V 0x1
#define GDMA_OUT_EOF_CH1_INT_ST_S 1
/* GDMA_OUT_DONE_CH1_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt..*/
#defi... | 2,150 |
.*/
#define GDMA_OUTFIFO_OVF_L3_CH1_INT_ENA (BIT(6))
#define GDMA_OUTFIFO_OVF_L3_CH1_INT_ENA_M (BIT(6))
#define GDMA_OUTFIFO_OVF_L3_CH1_INT_ENA_V 0x1
#define GDMA_OUTFIFO_OVF_L3_CH1_INT_ENA_S 6
/* GDMA_OUTFIFO_UDF_L1_CH1_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the... | 2,150 |
.*/
#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(3))
#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_M (BIT(3))
#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x1
#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_S 3
/* GDMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the OUT_D... | 2,150 |
.*/
#define GDMA_OUTFIFO_UDF_L3_CH1_INT_CLR (BIT(7))
#define GDMA_OUTFIFO_UDF_L3_CH1_INT_CLR_M (BIT(7))
#define GDMA_OUTFIFO_UDF_L3_CH1_INT_CLR_V 0x1
#define GDMA_OUTFIFO_UDF_L3_CH1_INT_CLR_S 7
/* GDMA_OUTFIFO_OVF_L3_CH1_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
/*description: Set this bit to clear the OUTFIFO... | 2,150 |
.*/
#define GDMA_OUTFIFO_OVF_L1_CH1_INT_CLR (BIT(4))
#define GDMA_OUTFIFO_OVF_L1_CH1_INT_CLR_M (BIT(4))
#define GDMA_OUTFIFO_OVF_L1_CH1_INT_CLR_V 0x1
#define GDMA_OUTFIFO_OVF_L1_CH1_INT_CLR_S 4
/* GDMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
/*description: Set this bit to clear the OUT_TOTA... | 2,150 |
.*/
#define GDMA_OUT_EOF_CH1_INT_CLR (BIT(1))
#define GDMA_OUT_EOF_CH1_INT_CLR_M (BIT(1))
#define GDMA_OUT_EOF_CH1_INT_CLR_V 0x1
#define GDMA_OUT_EOF_CH1_INT_CLR_S 1
/* GDMA_OUT_DONE_CH1_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt..*/
#define GDM... | 2,150 |
*/
#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH1 (BIT(24))
#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH1_M (BIT(24))
#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH1_V 0x1
#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH1_S 24
/* GDMA_OUT_REMAIN_UNDER_1B_L3_CH1 : RO ;bitpos:[23] ;default: 1'b1 ; */
/*description: reserved.*/
#define GDMA_OUT_R... | 2,150 |
.*/
#define GDMA_OUTFIFO_CNT_L2_CH1 0x0000007F
#define GDMA_OUTFIFO_CNT_L2_CH1_M ((GDMA_OUTFIFO_CNT_L2_CH1_V)<<(GDMA_OUTFIFO_CNT_L2_CH1_S))
#define GDMA_OUTFIFO_CNT_L2_CH1_V 0x7F
#define GDMA_OUTFIFO_CNT_L2_CH1_S 11
/* GDMA_OUTFIFO_CNT_L1_CH1 : RO ;bitpos:[10:6] ;default: 5'b0 ; */
/*description: The register sto... | 2,150 |
.*/
#define GDMA_OUTFIFO_FULL_L3_CH1 (BIT(4))
#define GDMA_OUTFIFO_FULL_L3_CH1_M (BIT(4))
#define GDMA_OUTFIFO_FULL_L3_CH1_V 0x1
#define GDMA_OUTFIFO_FULL_L3_CH1_S 4
/* GDMA_OUTFIFO_EMPTY_L2_CH1 : RO ;bitpos:[3] ;default: 1'b1 ; */
/*description: L2 Tx FIFO empty signal for Tx channel 1..*/
#define GDMA_OUTFIFO_E... | 2,150 |
.*/
#define GDMA_OUTFIFO_FULL_L1_CH1 (BIT(0))
#define GDMA_OUTFIFO_FULL_L1_CH1_M (BIT(0))
#define GDMA_OUTFIFO_FULL_L1_CH1_V 0x1
#define GDMA_OUTFIFO_FULL_L1_CH1_S 0
#define GDMA_OUT_PUSH_CH1_REG (DR_REG_GDMA_BASE + 0x13C)
/* GDMA_OUTFIFO_PUSH_CH1 : R/W/SC ;bitpos:[9] ;default: 1'h0 ; */
/*description: ... | 2,150 |
0: the outlink descriptor's F
SM is working..*/
#define GDMA_OUTLINK_PARK_CH1 (BIT(23))
#define GDMA_OUTLINK_PARK_CH1_M (BIT(23))
#define GDMA_OUTLINK_PARK_CH1_V 0x1
#define GDMA_OUTLINK_PARK_CH1_S 23
/* GDMA_OUTLINK_RESTART_CH1 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
/*description: Set this bit to restart a ... | 2,150 |
.*/
#define GDMA_OUTLINK_ADDR_CH1 0x000FFFFF
#define GDMA_OUTLINK_ADDR_CH1_M ((GDMA_OUTLINK_ADDR_CH1_V)<<(GDMA_OUTLINK_ADDR_CH1_S))
#define GDMA_OUTLINK_ADDR_CH1_V 0xFFFFF
#define GDMA_OUTLINK_ADDR_CH1_S 0
#define GDMA_OUT_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x144)
/* GDMA_OUT_STATE_CH1 : RO ;bitpos:[22:2... | 2,150 |
.*/
#define GDMA_OUTLINK_DSCR_ADDR_CH1 0x0003FFFF
#define GDMA_OUTLINK_DSCR_ADDR_CH1_M ((GDMA_OUTLINK_DSCR_ADDR_CH1_V)<<(GDMA_OUTLINK_DSCR_ADDR_CH1_S))
#define GDMA_OUTLINK_DSCR_ADDR_CH1_V 0x3FFFF
#define GDMA_OUTLINK_DSCR_ADDR_CH1_S 0
#define GDMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x148)
/* ... | 2,150 |
.*/
#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1 0xFFFFFFFF
#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_M ((GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V)<<(GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S))
#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V 0xFFFFFFFF
#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0
#define GDMA_OUT_DSCR_CH1_REG (DR_REG_GDMA_BASE... | 2,150 |
.*/
#define GDMA_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFF
#define GDMA_OUTLINK_DSCR_BF1_CH1_M ((GDMA_OUTLINK_DSCR_BF1_CH1_V)<<(GDMA_OUTLINK_DSCR_BF1_CH1_S))
#define GDMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFF
#define GDMA_OUTLINK_DSCR_BF1_CH1_S 0
#define GDMA_OUT_WIGHT_CH1_REG (DR_REG_GDMA_BASE + 0x15C)
/* GDMA_TX_WE... | 2,150 |
0:SPI2. 1: SPI3. 2:
UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT.; 7: AE
S. 8: SHA. 9: ADC_DAC..*/
#define GDMA_PERI_OUT_SEL_CH1 0x0000003F
#define GDMA_PERI_OUT_SEL_CH1_M ((GDMA_PERI_OUT_SEL_CH1_V)<<(GDMA_PERI_OUT_SEL_CH1_S))
#define GDMA_PERI_OUT_SEL_CH1_V 0x3F
#define GDMA_PERI_OUT_... | 2,150 |
.*/
#define GDMA_INDSCR_BURST_EN_CH2 (BIT(2))
#define GDMA_INDSCR_BURST_EN_CH2_M (BIT(2))
#define GDMA_INDSCR_BURST_EN_CH2_V 0x1
#define GDMA_INDSCR_BURST_EN_CH2_S 2
/* GDMA_IN_LOOP_TEST_CH2 : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: reserved.*/
#define GDMA_IN_LOOP_TEST_CH2 (BIT(1))
#define GDMA_IN... | 2,150 |
.*/
#define GDMA_IN_CHECK_OWNER_CH2 (BIT(12))
#define GDMA_IN_CHECK_OWNER_CH2_M (BIT(12))
#define GDMA_IN_CHECK_OWNER_CH2_V 0x1
#define GDMA_IN_CHECK_OWNER_CH2_S 12
/* GDMA_DMA_INFIFO_FULL_THRS_CH2 : R/W ;bitpos:[11:0] ;default: 12'hc ; */
/*description: This register is used to generate the INFIFO_FULL_WM_INT in... | 2,150 |
.*/
#define GDMA_INFIFO_OVF_L3_CH2_INT_RAW (BIT(8))
#define GDMA_INFIFO_OVF_L3_CH2_INT_RAW_M (BIT(8))
#define GDMA_INFIFO_OVF_L3_CH2_INT_RAW_V 0x1
#define GDMA_INFIFO_OVF_L3_CH2_INT_RAW_S 8
/* GDMA_INFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
/*description: This raw interrupt bit turns to... | 2,150 |
.*/
#define GDMA_INFIFO_FULL_WM_CH2_INT_RAW (BIT(5))
#define GDMA_INFIFO_FULL_WM_CH2_INT_RAW_M (BIT(5))
#define GDMA_INFIFO_FULL_WM_CH2_INT_RAW_V 0x1
#define GDMA_INFIFO_FULL_WM_CH2_INT_RAW_S 5
/* GDMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
/*description: The raw interrupt bit turns ... | 2,150 |
For other peripherals, thi
s raw interrupt is reserved..*/
#define GDMA_IN_ERR_EOF_CH2_INT_RAW (BIT(2))
#define GDMA_IN_ERR_EOF_CH2_INT_RAW_M (BIT(2))
#define GDMA_IN_ERR_EOF_CH2_INT_RAW_V 0x1
#define GDMA_IN_ERR_EOF_CH2_INT_RAW_S 2
/* GDMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
/*desc... | 2,150 |
.*/
#define GDMA_IN_DONE_CH2_INT_RAW (BIT(0))
#define GDMA_IN_DONE_CH2_INT_RAW_M (BIT(0))
#define GDMA_IN_DONE_CH2_INT_RAW_V 0x1
#define GDMA_IN_DONE_CH2_INT_RAW_S 0
#define GDMA_IN_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x18C)
/* GDMA_INFIFO_UDF_L3_CH2_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
/*descript... | 2,150 |
.*/
#define GDMA_INFIFO_UDF_L1_CH2_INT_ST (BIT(7))
#define GDMA_INFIFO_UDF_L1_CH2_INT_ST_M (BIT(7))
#define GDMA_INFIFO_UDF_L1_CH2_INT_ST_V 0x1
#define GDMA_INFIFO_UDF_L1_CH2_INT_ST_S 7
/* GDMA_INFIFO_OVF_L1_CH2_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the INFIFO... | 2,150 |
.*/
#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST (BIT(4))
#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_M (BIT(4))
#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_V 0x1
#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_S 4
/* GDMA_IN_DSCR_ERR_CH2_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the IN_DSCR_... | 2,150 |
*/
#define GDMA_IN_SUC_EOF_CH2_INT_ST (BIT(1))
#define GDMA_IN_SUC_EOF_CH2_INT_ST_M (BIT(1))
#define GDMA_IN_SUC_EOF_CH2_INT_ST_V 0x1
#define GDMA_IN_SUC_EOF_CH2_INT_ST_S 1
/* GDMA_IN_DONE_CH2_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt.... | 2,150 |
.*/
#define GDMA_INFIFO_OVF_L3_CH2_INT_ENA (BIT(8))
#define GDMA_INFIFO_OVF_L3_CH2_INT_ENA_M (BIT(8))
#define GDMA_INFIFO_OVF_L3_CH2_INT_ENA_V 0x1
#define GDMA_INFIFO_OVF_L3_CH2_INT_ENA_S 8
/* GDMA_INFIFO_UDF_L1_CH2_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the INFI... | 2,150 |
.*/
#define GDMA_INFIFO_FULL_WM_CH2_INT_ENA (BIT(5))
#define GDMA_INFIFO_FULL_WM_CH2_INT_ENA_M (BIT(5))
#define GDMA_INFIFO_FULL_WM_CH2_INT_ENA_V 0x1
#define GDMA_INFIFO_FULL_WM_CH2_INT_ENA_S 5
/* GDMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the ... | 2,150 |
.*/
#define GDMA_IN_ERR_EOF_CH2_INT_ENA (BIT(2))
#define GDMA_IN_ERR_EOF_CH2_INT_ENA_M (BIT(2))
#define GDMA_IN_ERR_EOF_CH2_INT_ENA_V 0x1
#define GDMA_IN_ERR_EOF_CH2_INT_ENA_S 2
/* GDMA_IN_SUC_EOF_CH2_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT i... | 2,150 |
.*/
#define GDMA_INFIFO_UDF_L3_CH2_INT_CLR (BIT(9))
#define GDMA_INFIFO_UDF_L3_CH2_INT_CLR_M (BIT(9))
#define GDMA_INFIFO_UDF_L3_CH2_INT_CLR_V 0x1
#define GDMA_INFIFO_UDF_L3_CH2_INT_CLR_S 9
/* GDMA_INFIFO_OVF_L3_CH2_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
/*description: Set this bit to clear the INFIFO_OVF_L... | 2,150 |
.*/
#define GDMA_INFIFO_OVF_L1_CH2_INT_CLR (BIT(6))
#define GDMA_INFIFO_OVF_L1_CH2_INT_CLR_M (BIT(6))
#define GDMA_INFIFO_OVF_L1_CH2_INT_CLR_V 0x1
#define GDMA_INFIFO_OVF_L1_CH2_INT_CLR_S 6
/* GDMA_DMA_INFIFO_FULL_WM_CH2_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
/*description: Set this bit to clear the INFIFO_... | 2,150 |
.*/
#define GDMA_IN_DSCR_ERR_CH2_INT_CLR (BIT(3))
#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_M (BIT(3))
#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_V 0x1
#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_S 3
/* GDMA_IN_ERR_EOF_CH2_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set this bit to clear the IN_ERR_EOF_CH_INT inter... | 2,150 |
*/
#define GDMA_IN_BUF_HUNGRY_CH2 (BIT(28))
#define GDMA_IN_BUF_HUNGRY_CH2_M (BIT(28))
#define GDMA_IN_BUF_HUNGRY_CH2_V 0x1
#define GDMA_IN_BUF_HUNGRY_CH2_S 28
/* GDMA_IN_REMAIN_UNDER_4B_L3_CH2 : RO ;bitpos:[27] ;default: 1'b1 ; */
/*description: reserved.*/
#define GDMA_IN_REMAIN_UNDER_4B_L3_CH2 (BIT(27))
#de... | 2,150 |
*/
#define GDMA_IN_REMAIN_UNDER_1B_L3_CH2 (BIT(24))
#define GDMA_IN_REMAIN_UNDER_1B_L3_CH2_M (BIT(24))
#define GDMA_IN_REMAIN_UNDER_1B_L3_CH2_V 0x1
#define GDMA_IN_REMAIN_UNDER_1B_L3_CH2_S 24
/* GDMA_INFIFO_CNT_L3_CH2 : RO ;bitpos:[23:19] ;default: 5'b0 ; */
/*description: The register stores the byte number of t... | 2,150 |
.*/
#define GDMA_INFIFO_CNT_L1_CH2 0x0000003F
#define GDMA_INFIFO_CNT_L1_CH2_M ((GDMA_INFIFO_CNT_L1_CH2_V)<<(GDMA_INFIFO_CNT_L1_CH2_S))
#define GDMA_INFIFO_CNT_L1_CH2_V 0x3F
#define GDMA_INFIFO_CNT_L1_CH2_S 6
/* GDMA_INFIFO_EMPTY_L3_CH2 : RO ;bitpos:[5] ;default: 1'b1 ; */
/*description: L3 Rx FIFO empty signal f... | 2,150 |
.*/
#define GDMA_INFIFO_FULL_L2_CH2 (BIT(2))
#define GDMA_INFIFO_FULL_L2_CH2_M (BIT(2))
#define GDMA_INFIFO_FULL_L2_CH2_V 0x1
#define GDMA_INFIFO_FULL_L2_CH2_S 2
/* GDMA_INFIFO_EMPTY_L1_CH2 : RO ;bitpos:[1] ;default: 1'b1 ; */
/*description: L1 Rx FIFO empty signal for Rx channel 2..*/
#define GDMA_INFIFO_EMPTY_L... | 2,150 |
.*/
#define GDMA_INFIFO_RDATA_CH2 0x00000FFF
#define GDMA_INFIFO_RDATA_CH2_M ((GDMA_INFIFO_RDATA_CH2_V)<<(GDMA_INFIFO_RDATA_CH2_S))
#define GDMA_INFIFO_RDATA_CH2_V 0xFFF
#define GDMA_INFIFO_RDATA_CH2_S 0
#define GDMA_IN_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x1A0)
/* GDMA_INLINK_PARK_CH2 : RO ;bitpos:[24] ;d... | 2,150 |
.*/
#define GDMA_INLINK_START_CH2 (BIT(22))
#define GDMA_INLINK_START_CH2_M (BIT(22))
#define GDMA_INLINK_START_CH2_V 0x1
#define GDMA_INLINK_START_CH2_S 22
/* GDMA_INLINK_STOP_CH2 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
/*description: Set this bit to stop dealing with the inlink descriptors..*/
#define GDMA_IN... | 2,150 |
.*/
#define GDMA_INLINK_ADDR_CH2 0x000FFFFF
#define GDMA_INLINK_ADDR_CH2_M ((GDMA_INLINK_ADDR_CH2_V)<<(GDMA_INLINK_ADDR_CH2_S))
#define GDMA_INLINK_ADDR_CH2_V 0xFFFFF
#define GDMA_INLINK_ADDR_CH2_S 0
#define GDMA_IN_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x1A4)
/* GDMA_IN_STATE_CH2 : RO ;bitpos:[22:20] ;defa... | 2,150 |
.*/
#define GDMA_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFF
#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH2_V)<<(GDMA_IN_SUC_EOF_DES_ADDR_CH2_S))
#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFF
#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_S 0
#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA... | 2,150 |
.*/
#define GDMA_INLINK_DSCR_CH2 0xFFFFFFFF
#define GDMA_INLINK_DSCR_CH2_M ((GDMA_INLINK_DSCR_CH2_V)<<(GDMA_INLINK_DSCR_CH2_S))
#define GDMA_INLINK_DSCR_CH2_V 0xFFFFFFFF
#define GDMA_INLINK_DSCR_CH2_S 0
#define GDMA_IN_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x1B4)
/* GDMA_INLINK_DSCR_BF0_CH2 : RO ;bitpos:... | 2,150 |
.*/
#define GDMA_RX_WEIGHT_CH2 0x0000000F
#define GDMA_RX_WEIGHT_CH2_M ((GDMA_RX_WEIGHT_CH2_V)<<(GDMA_RX_WEIGHT_CH2_S))
#define GDMA_RX_WEIGHT_CH2_V 0xF
#define GDMA_RX_WEIGHT_CH2_S 8
#define GDMA_IN_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x1C4)
/* GDMA_RX_PRI_CH2 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*des... | 2,150 |
.*/
#define GDMA_OUT_DATA_BURST_EN_CH2 (BIT(5))
#define GDMA_OUT_DATA_BURST_EN_CH2_M (BIT(5))
#define GDMA_OUT_DATA_BURST_EN_CH2_V 0x1
#define GDMA_OUT_DATA_BURST_EN_CH2_S 5
/* GDMA_OUTDSCR_BURST_EN_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: Set this bit to 1 to enable INCR burst transfer for Tx ch... | 2,150 |
.*/
#define GDMA_OUT_AUTO_WRBACK_CH2 (BIT(2))
#define GDMA_OUT_AUTO_WRBACK_CH2_M (BIT(2))
#define GDMA_OUT_AUTO_WRBACK_CH2_V 0x1
#define GDMA_OUT_AUTO_WRBACK_CH2_S 2
/* GDMA_OUT_LOOP_TEST_CH2 : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: reserved.*/
#define GDMA_OUT_LOOP_TEST_CH2 (BIT(1))
#define GDMA_O... | 2,150 |
.*/
#define GDMA_OUT_CHECK_OWNER_CH2 (BIT(12))
#define GDMA_OUT_CHECK_OWNER_CH2_M (BIT(12))
#define GDMA_OUT_CHECK_OWNER_CH2_V 0x1
#define GDMA_OUT_CHECK_OWNER_CH2_S 12
#define GDMA_OUT_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x1E8)
/* GDMA_OUTFIFO_UDF_L3_CH2_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; ... | 2,150 |
.*/
#define GDMA_OUTFIFO_UDF_L1_CH2_INT_RAW (BIT(5))
#define GDMA_OUTFIFO_UDF_L1_CH2_INT_RAW_M (BIT(5))
#define GDMA_OUTFIFO_UDF_L1_CH2_INT_RAW_V 0x1
#define GDMA_OUTFIFO_UDF_L1_CH2_INT_RAW_S 5
/* GDMA_OUTFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
/*description: This raw interrupt bit tur... | 2,150 |
.*/
#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW (BIT(2))
#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_M (BIT(2))
#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_V 0x1
#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_S 2
/* GDMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
/*description: The raw interrupt bit turns to high level ... | 2,150 |
.*/
#define GDMA_OUTFIFO_UDF_L3_CH2_INT_ST (BIT(7))
#define GDMA_OUTFIFO_UDF_L3_CH2_INT_ST_M (BIT(7))
#define GDMA_OUTFIFO_UDF_L3_CH2_INT_ST_V 0x1
#define GDMA_OUTFIFO_UDF_L3_CH2_INT_ST_S 7
/* GDMA_OUTFIFO_OVF_L3_CH2_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the O... | 2,150 |
.*/
#define GDMA_OUTFIFO_OVF_L1_CH2_INT_ST (BIT(4))
#define GDMA_OUTFIFO_OVF_L1_CH2_INT_ST_M (BIT(4))
#define GDMA_OUTFIFO_OVF_L1_CH2_INT_ST_V 0x1
#define GDMA_OUTFIFO_OVF_L1_CH2_INT_ST_S 4
/* GDMA_OUT_TOTAL_EOF_CH2_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the OU... | 2,150 |
.*/
#define GDMA_OUT_EOF_CH2_INT_ST (BIT(1))
#define GDMA_OUT_EOF_CH2_INT_ST_M (BIT(1))
#define GDMA_OUT_EOF_CH2_INT_ST_V 0x1
#define GDMA_OUT_EOF_CH2_INT_ST_S 1
/* GDMA_OUT_DONE_CH2_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt..*/
#defi... | 2,150 |
.*/
#define GDMA_OUTFIFO_OVF_L3_CH2_INT_ENA (BIT(6))
#define GDMA_OUTFIFO_OVF_L3_CH2_INT_ENA_M (BIT(6))
#define GDMA_OUTFIFO_OVF_L3_CH2_INT_ENA_V 0x1
#define GDMA_OUTFIFO_OVF_L3_CH2_INT_ENA_S 6
/* GDMA_OUTFIFO_UDF_L1_CH2_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the... | 2,150 |
.*/
#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA (BIT(3))
#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_M (BIT(3))
#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_V 0x1
#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_S 3
/* GDMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the OUT_D... | 2,150 |
.*/
#define GDMA_OUTFIFO_UDF_L3_CH2_INT_CLR (BIT(7))
#define GDMA_OUTFIFO_UDF_L3_CH2_INT_CLR_M (BIT(7))
#define GDMA_OUTFIFO_UDF_L3_CH2_INT_CLR_V 0x1
#define GDMA_OUTFIFO_UDF_L3_CH2_INT_CLR_S 7
/* GDMA_OUTFIFO_OVF_L3_CH2_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
/*description: Set this bit to clear the OUTFIFO... | 2,150 |
.*/
#define GDMA_OUTFIFO_OVF_L1_CH2_INT_CLR (BIT(4))
#define GDMA_OUTFIFO_OVF_L1_CH2_INT_CLR_M (BIT(4))
#define GDMA_OUTFIFO_OVF_L1_CH2_INT_CLR_V 0x1
#define GDMA_OUTFIFO_OVF_L1_CH2_INT_CLR_S 4
/* GDMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
/*description: Set this bit to clear the OUT_TOTA... | 2,150 |
.*/
#define GDMA_OUT_EOF_CH2_INT_CLR (BIT(1))
#define GDMA_OUT_EOF_CH2_INT_CLR_M (BIT(1))
#define GDMA_OUT_EOF_CH2_INT_CLR_V 0x1
#define GDMA_OUT_EOF_CH2_INT_CLR_S 1
/* GDMA_OUT_DONE_CH2_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt..*/
#define GDM... | 2,150 |
*/
#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH2 (BIT(24))
#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH2_M (BIT(24))
#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH2_V 0x1
#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH2_S 24
/* GDMA_OUT_REMAIN_UNDER_1B_L3_CH2 : RO ;bitpos:[23] ;default: 1'b1 ; */
/*description: reserved.*/
#define GDMA_OUT_R... | 2,150 |
.*/
#define GDMA_OUTFIFO_CNT_L2_CH2 0x0000007F
#define GDMA_OUTFIFO_CNT_L2_CH2_M ((GDMA_OUTFIFO_CNT_L2_CH2_V)<<(GDMA_OUTFIFO_CNT_L2_CH2_S))
#define GDMA_OUTFIFO_CNT_L2_CH2_V 0x7F
#define GDMA_OUTFIFO_CNT_L2_CH2_S 11
/* GDMA_OUTFIFO_CNT_L1_CH2 : RO ;bitpos:[10:6] ;default: 5'b0 ; */
/*description: The register sto... | 2,150 |
.*/
#define GDMA_OUTFIFO_FULL_L3_CH2 (BIT(4))
#define GDMA_OUTFIFO_FULL_L3_CH2_M (BIT(4))
#define GDMA_OUTFIFO_FULL_L3_CH2_V 0x1
#define GDMA_OUTFIFO_FULL_L3_CH2_S 4
/* GDMA_OUTFIFO_EMPTY_L2_CH2 : RO ;bitpos:[3] ;default: 1'b1 ; */
/*description: L2 Tx FIFO empty signal for Tx channel 2..*/
#define GDMA_OUTFIFO_E... | 2,150 |
.*/
#define GDMA_OUTFIFO_FULL_L1_CH2 (BIT(0))
#define GDMA_OUTFIFO_FULL_L1_CH2_M (BIT(0))
#define GDMA_OUTFIFO_FULL_L1_CH2_V 0x1
#define GDMA_OUTFIFO_FULL_L1_CH2_S 0
#define GDMA_OUT_PUSH_CH2_REG (DR_REG_GDMA_BASE + 0x1FC)
/* GDMA_OUTFIFO_PUSH_CH2 : R/W/SC ;bitpos:[9] ;default: 1'h0 ; */
/*description: ... | 2,150 |
0: the outlink descriptor's F
SM is working..*/
#define GDMA_OUTLINK_PARK_CH2 (BIT(23))
#define GDMA_OUTLINK_PARK_CH2_M (BIT(23))
#define GDMA_OUTLINK_PARK_CH2_V 0x1
#define GDMA_OUTLINK_PARK_CH2_S 23
/* GDMA_OUTLINK_RESTART_CH2 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
/*description: Set this bit to restart a ... | 2,150 |
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