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*/
#define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19))
#define RTC_CNTL_GLITCH_DET_INT_ST_M (BIT(19))
#define RTC_CNTL_GLITCH_DET_INT_ST_V 0x1
#define RTC_CNTL_GLITCH_DET_INT_ST_S 19
/* RTC_CNTL_TOUCH_TIMEOUT_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
/*description: Touch timeout interrupt state.*/
#define RTC_CNTL_TO... | 2,145 |
*/
#define RTC_CNTL_SWD_INT_ST (BIT(15))
#define RTC_CNTL_SWD_INT_ST_M (BIT(15))
#define RTC_CNTL_SWD_INT_ST_V 0x1
#define RTC_CNTL_SWD_INT_ST_S 15
/* RTC_CNTL_SARADC2_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
/*description: saradc2 interrupt state.*/
#define RTC_CNTL_SARADC2_INT_ST (BIT(14))
#define RTC_CN... | 2,145 |
*/
#define RTC_CNTL_SARADC1_INT_ST (BIT(11))
#define RTC_CNTL_SARADC1_INT_ST_M (BIT(11))
#define RTC_CNTL_SARADC1_INT_ST_V 0x1
#define RTC_CNTL_SARADC1_INT_ST_S 11
/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: RTC main timer interrupt state.*/
#define RTC_CNTL_MAIN_TIMER_INT_S... | 2,145 |
*/
#define RTC_CNTL_TOUCH_ACTIVE_INT_ST (BIT(7))
#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_M (BIT(7))
#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_V 0x1
#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_S 7
/* RTC_CNTL_TOUCH_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: touch done interrupt state.*/
#define RTC_CNTL_TOUC... | 2,145 |
*/
#define RTC_CNTL_WDT_INT_ST (BIT(3))
#define RTC_CNTL_WDT_INT_ST_M (BIT(3))
#define RTC_CNTL_WDT_INT_ST_V 0x1
#define RTC_CNTL_WDT_INT_ST_S 3
/* RTC_CNTL_SDIO_IDLE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: SDIO idle interrupt state.*/
#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2))
#define RTC_C... | 2,145 |
*/
#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR (BIT(20))
#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M (BIT(20))
#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V 0x1
#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S 20
/* RTC_CNTL_GLITCH_DET_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
/*descrip... | 2,145 |
*/
#define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16))
#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M (BIT(16))
#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V 0x1
#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S 16
/* RTC_CNTL_SWD_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
/*description: Clear super watch dog interrupt state.*/
#define ... | 2,145 |
*/
#define RTC_CNTL_TSENS_INT_CLR (BIT(12))
#define RTC_CNTL_TSENS_INT_CLR_M (BIT(12))
#define RTC_CNTL_TSENS_INT_CLR_V 0x1
#define RTC_CNTL_TSENS_INT_CLR_S 12
/* RTC_CNTL_SARADC1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
/*description: Clear saradc1 interrupt state.*/
#define RTC_CNTL_SARADC1_INT_CLR (BIT... | 2,145 |
*/
#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR (BIT(8))
#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_M (BIT(8))
#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_V 0x1
#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_S 8
/* RTC_CNTL_TOUCH_ACTIVE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
/*description: Clear touch active interrupt state.*... | 2,145 |
*/
#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR (BIT(4))
#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_M (BIT(4))
#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_V 0x1
#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_S 4
/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
/*description: Clear RTC WDT interrupt state.*/
#define ... | 2,145 |
*/
#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0))
#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0))
#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1
#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0
#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x50)
/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */
/*descripti... | 2,145 |
*/
#define RTC_CNTL_SCRATCH3 0xFFFFFFFF
#define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S))
#define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF
#define RTC_CNTL_SCRATCH3_S 0
#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60)
/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1... | 2,145 |
*/
#define RTC_CNTL_WDT_STATE 0x00000007
#define RTC_CNTL_WDT_STATE_M ((RTC_CNTL_WDT_STATE_V)<<(RTC_CNTL_WDT_STATE_S))
#define RTC_CNTL_WDT_STATE_V 0x7
#define RTC_CNTL_WDT_STATE_S 20
/* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */
/*description: DAC_XTAL_32K.*/
#define RTC_CNTL_DAC_XTAL_32K ... | 2,145 |
*/
#define RTC_CNTL_DGM_XTAL_32K 0x00000007
#define RTC_CNTL_DGM_XTAL_32K_M ((RTC_CNTL_DGM_XTAL_32K_V)<<(RTC_CNTL_DGM_XTAL_32K_S))
#define RTC_CNTL_DGM_XTAL_32K_V 0x7
#define RTC_CNTL_DGM_XTAL_32K_S 10
/* RTC_CNTL_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: 0: single-end buffer 1: different... | 2,145 |
*/
#define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6))
#define RTC_CNTL_XTAL32K_AUTO_RETURN_M (BIT(6))
#define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x1
#define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6
/* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: xtal 32k restart xtal when xtal is dead.*/
#def... | 2,145 |
*/
#define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2))
#define RTC_CNTL_XTAL32K_WDT_RESET_M (BIT(2))
#define RTC_CNTL_XTAL32K_WDT_RESET_V 0x1
#define RTC_CNTL_XTAL32K_WDT_RESET_S 2
/* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: xtal 32k watch dog clock force on.*/
#define RTC_CNTL_XTA... | 2,145 |
*/
#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30))
#define RTC_CNTL_EXT_WAKEUP0_LV_M (BIT(30))
#define RTC_CNTL_EXT_WAKEUP0_LV_V 0x1
#define RTC_CNTL_EXT_WAKEUP0_LV_S 30
/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[29] ;default: 1'd0 ; */
/*description: enable filter for gpio wakeup event.*/
#define RTC_CNTL_GPIO_WAKE... | 2,145 |
*/
#define RTC_CNTL_SLEEP_REJECT_ENA 0x0003FFFF
#define RTC_CNTL_SLEEP_REJECT_ENA_M ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S))
#define RTC_CNTL_SLEEP_REJECT_ENA_V 0x3FFFF
#define RTC_CNTL_SLEEP_REJECT_ENA_S 12
#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6C)
/* RTC_C... | 2,145 |
*/
#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF
#define RTC_CNTL_SDIO_ACT_DNUM_M ((RTC_CNTL_SDIO_ACT_DNUM_V)<<(RTC_CNTL_SDIO_ACT_DNUM_S))
#define RTC_CNTL_SDIO_ACT_DNUM_V 0x3FF
#define RTC_CNTL_SDIO_ACT_DNUM_S 22
#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74)
/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;... | 2,145 |
*/
#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING (BIT(27))
#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M (BIT(27))
#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V 0x1
#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S 27
/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */
/*description: CK8M force power up.*/
#define... | 2,145 |
*/
#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16))
#define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16))
#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1
#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16
/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */
/*description: XTAL force no gating during sleep.*/
#define... | 2,145 |
*/
#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9))
#define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9))
#define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1
#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9
/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */
/*description: enable CK_XTAL_32K for digital core (no relationship with RTC... | 2,145 |
00: div128.*/
#define RTC_CNTL_CK8M_DIV 0x00000003
#define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S))
#define RTC_CNTL_CK8M_DIV_V 0x3
#define RTC_CNTL_CK8M_DIV_S 4
/* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: used to sync reg_ck8m_div_sel bus. Clear vl... | 2,145 |
*/
#define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31))
#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M (BIT(31))
#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V 0x1
#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S 31
/* RTC_CNTL_ANA_CLK_DIV : R/W ;bitpos:[30:23] ;default: 8'd0 ; */
/*description: .*/
#define RTC_CNTL_ANA_CLK_DIV 0x000000FF
#defin... | 2,145 |
Only active when reg_sdio_force = 1.*/
#define RTC_CNTL_DREFH_SDIO 0x00000003
#define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S))
#define RTC_CNTL_DREFH_SDIO_V 0x3
#define RTC_CNTL_DREFH_SDIO_S 29
/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b01 ; */
/*description: SW opt... | 2,145 |
*/
#define RTC_CNTL_REG1P8_READY (BIT(24))
#define RTC_CNTL_REG1P8_READY_M (BIT(24))
#define RTC_CNTL_REG1P8_READY_V 0x1
#define RTC_CNTL_REG1P8_READY_S 24
/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */
/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1.*/
#define RTC_CNTL_S... | 2,145 |
*/
#define RTC_CNTL_SDIO_ENCURLIM (BIT(20))
#define RTC_CNTL_SDIO_ENCURLIM_M (BIT(20))
#define RTC_CNTL_SDIO_ENCURLIM_V 0x1
#define RTC_CNTL_SDIO_ENCURLIM_S 20
/* RTC_CNTL_SDIO_MODECURLIM : R/W ;bitpos:[19] ;default: 1'd0 ; */
/*description: select current limit mode.*/
#define RTC_CNTL_SDIO_MODECURLIM (BIT(19... | 2,145 |
0: no res.*/
#define RTC_CNTL_SDIO_INITI 0x00000003
#define RTC_CNTL_SDIO_INITI_M ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S))
#define RTC_CNTL_SDIO_INITI_V 0x3
#define RTC_CNTL_SDIO_INITI_S 13
/* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */
/*description: ability to prevent LDO from overs... | 2,145 |
*/
#define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FF
#define RTC_CNTL_SDIO_TIMER_TARGET_M ((RTC_CNTL_SDIO_TIMER_TARGET_V)<<(RTC_CNTL_SDIO_TIMER_TARGET_S))
#define RTC_CNTL_SDIO_TIMER_TARGET_V 0xFF
#define RTC_CNTL_SDIO_TIMER_TARGET_S 0
#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x80)
/* RTC_CNTL_... | 2,145 |
*/
#define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F
#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S))
#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0xF
#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18
/* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*desc... | 2,145 |
*/
#define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14))
#define RTC_CNTL_PD_CUR_DEEP_SLP_M (BIT(14))
#define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x1
#define RTC_CNTL_PD_CUR_DEEP_SLP_S 14
/* RTC_CNTL_BIAS_BUF_MONITOR : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: .*/
#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13))
#define RTC_... | 2,145 |
*/
#define RTC_CNTL_BIAS_BUF_IDLE (BIT(10))
#define RTC_CNTL_BIAS_BUF_IDLE_M (BIT(10))
#define RTC_CNTL_BIAS_BUF_IDLE_V 0x1
#define RTC_CNTL_BIAS_BUF_IDLE_S 10
#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x84)
/* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */
/*description: .*/
#defi... | 2,145 |
*/
#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28))
#define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28))
#define RTC_CNTL_DBOOST_FORCE_PD_V 0x1
#define RTC_CNTL_DBOOST_FORCE_PD_S 28
/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
*/
#define RTC_CNTL_DIG_DBIAS_0V85 0
#define RTC_CNTL_DIG_DBIAS_0V... | 2,145 |
*/
#define RTC_CNTL_PAD_FORCE_HOLD (BIT(21))
#define RTC_CNTL_PAD_FORCE_HOLD_M (BIT(21))
#define RTC_CNTL_PAD_FORCE_HOLD_V 0x1
#define RTC_CNTL_PAD_FORCE_HOLD_S 21
/* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
/*description: enable power down rtc_peri in sleep .*/
#define RTC_CNTL_PD_EN (BIT(20))
#d... | 2,145 |
*/
#define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11))
#define RTC_CNTL_SLOWMEM_FORCE_LPU_M (BIT(11))
#define RTC_CNTL_SLOWMEM_FORCE_LPU_V 0x1
#define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11
/* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: RTC memory force PD.*/
#define RTC_CNTL_SLOWMEM_FORCE_... | 2,145 |
*/
#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7))
#define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(7))
#define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1
#define RTC_CNTL_FASTMEM_FORCE_LPD_S 7
/* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: 1: Fast RTC memory PD following CPU.*/
#define RTC_CNTL_FAS... | 2,145 |
*/
#define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3))
#define RTC_CNTL_SLOWMEM_FORCE_ISO_M (BIT(3))
#define RTC_CNTL_SLOWMEM_FORCE_ISO_V 0x1
#define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3
/* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: RTC memory force no ISO.*/
#define RTC_CNTL_SLOWMEM_FORC... | 2,145 |
*/
#define RTC_CNTL_DG_VDD_DRV_B_MONITOR 0x000000FF
#define RTC_CNTL_DG_VDD_DRV_B_MONITOR_M ((RTC_CNTL_DG_VDD_DRV_B_MONITOR_V)<<(RTC_CNTL_DG_VDD_DRV_B_MONITOR_S))
#define RTC_CNTL_DG_VDD_DRV_B_MONITOR_V 0xFF
#define RTC_CNTL_DG_VDD_DRV_B_MONITOR_S 20
/* RTC_CNTL_DG_VDD_DRV_B_SLP : R/W ;bitpos:[19:12] ;default: 8'... | 2,145 |
*/
#define RTC_CNTL_REGULATOR_DRV_B_MONITOR 0x0000003F
#define RTC_CNTL_REGULATOR_DRV_B_MONITOR_M ((RTC_CNTL_REGULATOR_DRV_B_MONITOR_V)<<(RTC_CNTL_REGULATOR_DRV_B_MONITOR_S))
#define RTC_CNTL_REGULATOR_DRV_B_MONITOR_V 0x3F
#define RTC_CNTL_REGULATOR_DRV_B_MONITOR_S 0
#define RTC_CNTL_DIG_PWC_REG (DR_REG... | 2,145 |
*/
#define RTC_CNTL_DG_PERI_PD_EN (BIT(28))
#define RTC_CNTL_DG_PERI_PD_EN_M (BIT(28))
#define RTC_CNTL_DG_PERI_PD_EN_V 0x1
#define RTC_CNTL_DG_PERI_PD_EN_S 28
/* RTC_CNTL_CPU_TOP_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */
/*description: digital dcdc force power up.*/
#define RTC_CNTL_CPU_TOP_FORCE_PU (BI... | 2,145 |
*/
#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19))
#define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19))
#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1
#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19
/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */
/*description: wifi force power up.*/
#define RTC_CNTL_WIFI_FORCE_PU (BIT(... | 2,145 |
*/
#define RTC_CNTL_DG_PERI_FORCE_PD (BIT(13))
#define RTC_CNTL_DG_PERI_FORCE_PD_M (BIT(13))
#define RTC_CNTL_DG_PERI_FORCE_PD_V 0x1
#define RTC_CNTL_DG_PERI_FORCE_PD_S 13
/* RTC_CNTL_BT_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */
/*description: internal SRAM 2 force power up.*/
#define RTC_CNTL_BT_FORCE_PU ... | 2,145 |
*/
#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3))
#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3))
#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1
#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3
#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x94)
/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */
/*... | 2,145 |
*/
#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28))
#define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28))
#define RTC_CNTL_WIFI_FORCE_ISO_V 0x1
#define RTC_CNTL_WIFI_FORCE_ISO_S 28
/* RTC_CNTL_CPU_TOP_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */
/*description: internal SRAM 4 force no ISO.*/
#define RTC_CNTL_CPU_TOP_FORCE_N... | 2,145 |
*/
#define RTC_CNTL_DG_PERI_FORCE_ISO (BIT(24))
#define RTC_CNTL_DG_PERI_FORCE_ISO_M (BIT(24))
#define RTC_CNTL_DG_PERI_FORCE_ISO_V 0x1
#define RTC_CNTL_DG_PERI_FORCE_ISO_S 24
/* RTC_CNTL_BT_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */
/*description: internal SRAM 2 force no ISO.*/
#define RTC_CNTL_BT_FORCE... | 2,145 |
*/
#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14))
#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14))
#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1
#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14
/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */
/*description: digital pad force ISO.*/
#define RTC_CNTL_DG_PA... | 2,145 |
*/
#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10))
#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10))
#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1
#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10
/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */
/*description: read only register to indicate digital pad auto-ho... | 2,145 |
*/
#define RTC_CNTL_WDT_EN (BIT(31))
#define RTC_CNTL_WDT_EN_M (BIT(31))
#define RTC_CNTL_WDT_EN_V 0x1
#define RTC_CNTL_WDT_EN_S 31
/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */
/*description: 1: interrupt stage en.*/
#define RTC_CNTL_WDT_STG0 0x00000007
#define RTC_CNTL_WDT_STG0_M ((RTC_CNTL... | 2,145 |
*/
#define RTC_CNTL_WDT_STG3 0x00000007
#define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S))
#define RTC_CNTL_WDT_STG3_V 0x7
#define RTC_CNTL_WDT_STG3_S 19
/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */
/*description: CPU reset counter length.*/
#define RTC_CNTL_... | 2,145 |
*/
#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12))
#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(12))
#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1
#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12
/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */
/*description: enable WDT reset PRO CPU.*/
#define RTC_... | 2,145 |
*/
#define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8))
#define RTC_CNTL_WDT_CHIP_RESET_EN_M (BIT(8))
#define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x1
#define RTC_CNTL_WDT_CHIP_RESET_EN_S 8
/* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[7:0] ;default: 8'd20 ; */
/*description: chip reset siginal pulse width.*/
#define RTC_CNTL_W... | 2,145 |
*/
#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF
#define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S))
#define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF
#define RTC_CNTL_WDT_STG1_HOLD_S 0
#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0xA4)
/* RTC_CNTL_WDT_STG2_HOLD : R... | 2,145 |
*/
#define RTC_CNTL_WDT_FEED (BIT(31))
#define RTC_CNTL_WDT_FEED_M (BIT(31))
#define RTC_CNTL_WDT_FEED_V 0x1
#define RTC_CNTL_WDT_FEED_S 31
#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xB0)
/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
/*description: .*/
#define RTC_C... | 2,145 |
*/
#define RTC_CNTL_SWD_FEED (BIT(29))
#define RTC_CNTL_SWD_FEED_M (BIT(29))
#define RTC_CNTL_SWD_FEED_V 0x1
#define RTC_CNTL_SWD_FEED_S 29
/* RTC_CNTL_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
/*description: reset swd reset flag.*/
#define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28))
#define RTC_CNTL_SWD_... | 2,145 |
*/
#define RTC_CNTL_SWD_FEED_INT (BIT(1))
#define RTC_CNTL_SWD_FEED_INT_M (BIT(1))
#define RTC_CNTL_SWD_FEED_INT_V 0x1
#define RTC_CNTL_SWD_FEED_INT_S 1
/* RTC_CNTL_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: swd reset flag.*/
#define RTC_CNTL_SWD_RESET_FLAG (BIT(0))
#define RTC_CNTL_SWD... | 2,145 |
*/
#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F
#define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S))
#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F
#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20
#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xC0)
/* RTC_C... | 2,145 |
*/
#define RTC_CNTL_SCRATCH6 0xFFFFFFFF
#define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S))
#define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF
#define RTC_CNTL_SCRATCH6_S 0
#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xCC)
/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */
/*de... | 2,145 |
*/
#define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27))
#define RTC_CNTL_MAIN_STATE_IN_IDLE_M (BIT(27))
#define RTC_CNTL_MAIN_STATE_IN_IDLE_V 0x1
#define RTC_CNTL_MAIN_STATE_IN_IDLE_S 27
/* RTC_CNTL_MAIN_STATE_IN_SLP : RO ;bitpos:[26] ;default: 1'b0 ; */
/*description: rtc main state machine is in sleep state.*/
#define... | 2,145 |
*/
#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23))
#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M (BIT(23))
#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V 0x1
#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S 23
/* RTC_CNTL_IN_LOW_POWER_STATE : RO ;bitpos:[22] ;default: 1'b0 ; */
/*description: rtc main state machine is in the state... | 2,145 |
*/
#define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19))
#define RTC_CNTL_RDY_FOR_WAKEUP_M (BIT(19))
#define RTC_CNTL_RDY_FOR_WAKEUP_V 0x1
#define RTC_CNTL_RDY_FOR_WAKEUP_S 19
/* RTC_CNTL_MAIN_STATE_PLL_ON : RO ;bitpos:[18] ;default: 1'b0 ; */
/*description: rtc main state machine is in states that pll should be running.*/
#... | 2,145 |
*/
#define RTC_CNTL_COCPU_STATE_SLP (BIT(15))
#define RTC_CNTL_COCPU_STATE_SLP_M (BIT(15))
#define RTC_CNTL_COCPU_STATE_SLP_V 0x1
#define RTC_CNTL_COCPU_STATE_SLP_S 15
/* RTC_CNTL_COCPU_STATE_SWITCH : RO ;bitpos:[14] ;default: 1'b0 ; */
/*description: ulp/cocpu is about to working. Switch rtc main state.*/
#defin... | 2,145 |
*/
#define RTC_CNTL_TOUCH_STATE_SLP (BIT(11))
#define RTC_CNTL_TOUCH_STATE_SLP_M (BIT(11))
#define RTC_CNTL_TOUCH_STATE_SLP_V 0x1
#define RTC_CNTL_TOUCH_STATE_SLP_S 11
/* RTC_CNTL_TOUCH_STATE_SWITCH : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: touch is about to working. Switch rtc main state.*/
#define RT... | 2,145 |
*/
#define RTC_CNTL_DIG_ISO (BIT(7))
#define RTC_CNTL_DIG_ISO_M (BIT(7))
#define RTC_CNTL_DIG_ISO_V 0x1
#define RTC_CNTL_DIG_ISO_S 7
/* RTC_CNTL_XPD_WIFI : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: wifi wrap power down.*/
#define RTC_CNTL_XPD_WIFI (BIT(6))
#define RTC_CNTL_XPD_WIFI_M (BIT(6))
#define ... | 2,145 |
*/
#define RTC_CNTL_XPD_DIG_DCDC (BIT(2))
#define RTC_CNTL_XPD_DIG_DCDC_M (BIT(2))
#define RTC_CNTL_XPD_DIG_DCDC_V 0x1
#define RTC_CNTL_XPD_DIG_DCDC_S 2
/* RTC_CNTL_XPD_ROM0 : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: rom0 power down.*/
#define RTC_CNTL_XPD_ROM0 (BIT(0))
#define RTC_CNTL_XPD_ROM0_M (B... | 2,145 |
*/
#define RTC_CNTL_PAD20_HOLD (BIT(20))
#define RTC_CNTL_PAD20_HOLD_M (BIT(20))
#define RTC_CNTL_PAD20_HOLD_V 0x1
#define RTC_CNTL_PAD20_HOLD_S 20
/* RTC_CNTL_PAD19_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */
/*description: .*/
#define RTC_CNTL_PAD19_HOLD (BIT(19))
#define RTC_CNTL_PAD19_HOLD_M (BIT(19))
#de... | 2,145 |
*/
#define RTC_CNTL_X32P_HOLD (BIT(15))
#define RTC_CNTL_X32P_HOLD_M (BIT(15))
#define RTC_CNTL_X32P_HOLD_V 0x1
#define RTC_CNTL_X32P_HOLD_S 15
/* RTC_CNTL_TOUCH_PAD14_HOLD : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: .*/
#define RTC_CNTL_TOUCH_PAD14_HOLD (BIT(14))
#define RTC_CNTL_TOUCH_PAD14_HOLD_M ... | 2,145 |
*/
#define RTC_CNTL_TOUCH_PAD11_HOLD (BIT(11))
#define RTC_CNTL_TOUCH_PAD11_HOLD_M (BIT(11))
#define RTC_CNTL_TOUCH_PAD11_HOLD_V 0x1
#define RTC_CNTL_TOUCH_PAD11_HOLD_S 11
/* RTC_CNTL_TOUCH_PAD10_HOLD : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: .*/
#define RTC_CNTL_TOUCH_PAD10_HOLD (BIT(10))
#define ... | 2,145 |
*/
#define RTC_CNTL_TOUCH_PAD7_HOLD (BIT(7))
#define RTC_CNTL_TOUCH_PAD7_HOLD_M (BIT(7))
#define RTC_CNTL_TOUCH_PAD7_HOLD_V 0x1
#define RTC_CNTL_TOUCH_PAD7_HOLD_S 7
/* RTC_CNTL_TOUCH_PAD6_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: .*/
#define RTC_CNTL_TOUCH_PAD6_HOLD (BIT(6))
#define RTC_CNTL_TO... | 2,145 |
*/
#define RTC_CNTL_TOUCH_PAD3_HOLD (BIT(3))
#define RTC_CNTL_TOUCH_PAD3_HOLD_M (BIT(3))
#define RTC_CNTL_TOUCH_PAD3_HOLD_V 0x1
#define RTC_CNTL_TOUCH_PAD3_HOLD_S 3
/* RTC_CNTL_TOUCH_PAD2_HOLD : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define RTC_CNTL_TOUCH_PAD2_HOLD (BIT(2))
#define RTC_CNTL_TO... | 2,145 |
*/
#define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF
#define RTC_CNTL_DIG_PAD_HOLD_M ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S))
#define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF
#define RTC_CNTL_DIG_PAD_HOLD_S 0
#define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xE0)
/* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR... | 2,145 |
*/
#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x003FFFFF
#define RTC_CNTL_EXT_WAKEUP1_STATUS_M ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S))
#define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x3FFFFF
#define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0
#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xE8)
/*... | 2,145 |
*/
#define RTC_CNTL_BROWN_OUT_ANA_RST_EN (BIT(28))
#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M (BIT(28))
#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V 0x1
#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S 28
/* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: 1: 4-pos reset.*/
#define RTC_CNTL_BROWN_... | 2,145 |
*/
#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15))
#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15))
#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1
#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15
/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: enable close flash when brown out happ... | 2,145 |
*/
#define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF
#define RTC_CNTL_TIMER_VALUE1_LOW_M ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S))
#define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF
#define RTC_CNTL_TIMER_VALUE1_LOW_S 0
#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0xF0)
/* RTC_CNTL... | 2,145 |
*/
#define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F
#define RTC_CNTL_XTAL32K_STABLE_THRES_M ((RTC_CNTL_XTAL32K_STABLE_THRES_V)<<(RTC_CNTL_XTAL32K_STABLE_THRES_S))
#define RTC_CNTL_XTAL32K_STABLE_THRES_V 0xF
#define RTC_CNTL_XTAL32K_STABLE_THRES_S 28
/* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: ... | 2,145 |
*/
#define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F
#define RTC_CNTL_XTAL32K_RETURN_WAIT_M ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S))
#define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0xF
#define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0
#define RTC_CNTL_ULP_CP_TIMER_REG (DR_REG_RTCCNTL_BASE + 0xFC... | 2,145 |
*/
#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA (BIT(29))
#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_M (BIT(29))
#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V 0x1
#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S 29
/* RTC_CNTL_ULP_CP_PC_INIT : R/W ;bitpos:[10:0] ;default: 11'b0 ; */
/*description: ULP-coprocessor PC initial address... | 2,145 |
*/
#define RTC_CNTL_ULP_CP_FORCE_START_TOP (BIT(30))
#define RTC_CNTL_ULP_CP_FORCE_START_TOP_M (BIT(30))
#define RTC_CNTL_ULP_CP_FORCE_START_TOP_V 0x1
#define RTC_CNTL_ULP_CP_FORCE_START_TOP_S 30
/* RTC_CNTL_ULP_CP_RESET : R/W ;bitpos:[29] ;default: 1'd0 ; */
/*description: ulp coprocessor clk software reset.*/
#... | 2,145 |
*/
#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE 0x000007FF
#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_M ((RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V)<<(RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S))
#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V 0x7FF
#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S 11
/* RTC_CNTL_ULP_CP_MEM_ADDR_INIT : R/W ;bitpos:[10:0] ;default... | 2,145 |
*/
#define RTC_CNTL_COCPU_SW_INT_TRIGGER (BIT(26))
#define RTC_CNTL_COCPU_SW_INT_TRIGGER_M (BIT(26))
#define RTC_CNTL_COCPU_SW_INT_TRIGGER_V 0x1
#define RTC_CNTL_COCPU_SW_INT_TRIGGER_S 26
/* RTC_CNTL_COCPU_DONE : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: done signal used by riscv to control timer. .*/
#... | 2,145 |
*/
#define RTC_CNTL_COCPU_SHUT_RESET_EN (BIT(22))
#define RTC_CNTL_COCPU_SHUT_RESET_EN_M (BIT(22))
#define RTC_CNTL_COCPU_SHUT_RESET_EN_V 0x1
#define RTC_CNTL_COCPU_SHUT_RESET_EN_S 22
/* RTC_CNTL_COCPU_SHUT_2_CLK_DIS : R/W ;bitpos:[21:14] ;default: 8'd40 ; */
/*description: time from shut cocpu to disable clk.*/
... | 2,145 |
*/
#define RTC_CNTL_COCPU_START_2_RESET_DIS 0x0000003F
#define RTC_CNTL_COCPU_START_2_RESET_DIS_M ((RTC_CNTL_COCPU_START_2_RESET_DIS_V)<<(RTC_CNTL_COCPU_START_2_RESET_DIS_S))
#define RTC_CNTL_COCPU_START_2_RESET_DIS_V 0x3F
#define RTC_CNTL_COCPU_START_2_RESET_DIS_S 1
/* RTC_CNTL_COCPU_CLK_FO : R/W ;bitpos:[0] ;de... | 2,145 |
*/
#define RTC_CNTL_TOUCH_SLEEP_CYCLES 0x0000FFFF
#define RTC_CNTL_TOUCH_SLEEP_CYCLES_M ((RTC_CNTL_TOUCH_SLEEP_CYCLES_V)<<(RTC_CNTL_TOUCH_SLEEP_CYCLES_S))
#define RTC_CNTL_TOUCH_SLEEP_CYCLES_V 0xFFFF
#define RTC_CNTL_TOUCH_SLEEP_CYCLES_S 0
#define RTC_CNTL_TOUCH_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x10C)
/... | 2,145 |
*/
#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE 0x00000003
#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_M ((RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V)<<(RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S))
#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V 0x3
#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S 27
/* RTC_CNTL_TOUCH_SLP_CYC_DIV : R/W ;bitpos:[26:25] ... | 2,145 |
*/
#define RTC_CNTL_TOUCH_START_FORCE (BIT(16))
#define RTC_CNTL_TOUCH_START_FORCE_M (BIT(16))
#define RTC_CNTL_TOUCH_START_FORCE_V 0x1
#define RTC_CNTL_TOUCH_START_FORCE_S 16
/* RTC_CNTL_TOUCH_START_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: 1: start touch fsm.*/
#define RTC_CNTL_TOUCH_START_EN ... | 2,145 |
*/
#define RTC_CNTL_TOUCH_DBIAS (BIT(12))
#define RTC_CNTL_TOUCH_DBIAS_M (BIT(12))
#define RTC_CNTL_TOUCH_DBIAS_V 0x1
#define RTC_CNTL_TOUCH_DBIAS_S 12
/* RTC_CNTL_TOUCH_REFC : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
/*description: TOUCH pad0 reference cap.*/
#define RTC_CNTL_TOUCH_REFC 0x00000007
#define RTC_C... | 2,145 |
*/
#define RTC_CNTL_TOUCH_DREFL 0x00000003
#define RTC_CNTL_TOUCH_DREFL_M ((RTC_CNTL_TOUCH_DREFL_V)<<(RTC_CNTL_TOUCH_DREFL_S))
#define RTC_CNTL_TOUCH_DREFL_V 0x3
#define RTC_CNTL_TOUCH_DREFL_S 4
/* RTC_CNTL_TOUCH_DRANGE : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
/*description: TOUCH_DRANGE.*/
#define RTC_CNTL_TOUCH... | 2,145 |
*/
#define RTC_CNTL_TOUCH_BUFDRV 0x00000007
#define RTC_CNTL_TOUCH_BUFDRV_M ((RTC_CNTL_TOUCH_BUFDRV_V)<<(RTC_CNTL_TOUCH_BUFDRV_S))
#define RTC_CNTL_TOUCH_BUFDRV_V 0x7
#define RTC_CNTL_TOUCH_BUFDRV_S 25
/* RTC_CNTL_TOUCH_SCAN_PAD_MAP : R/W ;bitpos:[24:10] ;default: 15'h0 ; */
/*description: touch scan mode pad ena... | 2,145 |
*/
#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION (BIT(8))
#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_M (BIT(8))
#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V 0x1
#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S 8
/* RTC_CNTL_TOUCH_DENOISE_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: touch pad0 will be used to ... | 2,145 |
*/
#define RTC_CNTL_TOUCH_SLP_PAD 0x0000001F
#define RTC_CNTL_TOUCH_SLP_PAD_M ((RTC_CNTL_TOUCH_SLP_PAD_V)<<(RTC_CNTL_TOUCH_SLP_PAD_S))
#define RTC_CNTL_TOUCH_SLP_PAD_V 0x1F
#define RTC_CNTL_TOUCH_SLP_PAD_S 27
/* RTC_CNTL_TOUCH_SLP_APPROACH_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: sleep pad approac... | 2,145 |
*/
#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME 0x000000FF
#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_M ((RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V)<<(RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S))
#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V 0xFF
#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S 24
/* RTC_CNTL_TOUCH_SLP_CHANNEL_CLR : WO ... | 2,145 |
1: IIR ? 2: IIR 1/8 3: Jitter.*/
#define RTC_CNTL_TOUCH_FILTER_MODE 0x00000007
#define RTC_CNTL_TOUCH_FILTER_MODE_M ((RTC_CNTL_TOUCH_FILTER_MODE_V)<<(RTC_CNTL_TOUCH_FILTER_MODE_S))
#define RTC_CNTL_TOUCH_FILTER_MODE_V 0x7
#define RTC_CNTL_TOUCH_FILTER_MODE_S 28
/* RTC_CNTL_TOUCH_DEBOUNCE : R/W ;bitpos:[27:25] ;d... | 2,145 |
*/
#define RTC_CNTL_TOUCH_JITTER_STEP 0x0000000F
#define RTC_CNTL_TOUCH_JITTER_STEP_M ((RTC_CNTL_TOUCH_JITTER_STEP_V)<<(RTC_CNTL_TOUCH_JITTER_STEP_S))
#define RTC_CNTL_TOUCH_JITTER_STEP_V 0xF
#define RTC_CNTL_TOUCH_JITTER_STEP_S 11
/* RTC_CNTL_TOUCH_SMOOTH_LVL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */
/*descriptio... | 2,145 |
*/
#define RTC_CNTL_SW_HW_USB_PHY_SEL (BIT(20))
#define RTC_CNTL_SW_HW_USB_PHY_SEL_M (BIT(20))
#define RTC_CNTL_SW_HW_USB_PHY_SEL_V 0x1
#define RTC_CNTL_SW_HW_USB_PHY_SEL_S 20
/* RTC_CNTL_SW_USB_PHY_SEL : R/W ;bitpos:[19] ;default: 1'b0 ; */
/*description: .*/
#define RTC_CNTL_SW_USB_PHY_SEL (BIT(19))
#define ... | 2,145 |
*/
#define RTC_CNTL_USB_TX_EN_OVERRIDE (BIT(16))
#define RTC_CNTL_USB_TX_EN_OVERRIDE_M (BIT(16))
#define RTC_CNTL_USB_TX_EN_OVERRIDE_V 0x1
#define RTC_CNTL_USB_TX_EN_OVERRIDE_S 16
/* RTC_CNTL_USB_TX_EN : R/W ;bitpos:[15] ;default: 1'd0 ; */
/*description: .*/
#define RTC_CNTL_USB_TX_EN (BIT(15))
#define RTC_CN... | 2,145 |
*/
#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE (BIT(11))
#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_M (BIT(11))
#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V 0x1
#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S 11
/* RTC_CNTL_USB_PULLUP_VALUE : R/W ;bitpos:[10] ;default: 1'd0 ; */
/*description: .*/
#define RTC_CNTL_USB_PULLUP... | 2,145 |
*/
#define RTC_CNTL_USB_DP_PULLDOWN (BIT(7))
#define RTC_CNTL_USB_DP_PULLDOWN_M (BIT(7))
#define RTC_CNTL_USB_DP_PULLDOWN_V 0x1
#define RTC_CNTL_USB_DP_PULLDOWN_S 7
/* RTC_CNTL_USB_DP_PULLUP : R/W ;bitpos:[6] ;default: 1'd0 ; */
/*description: .*/
#define RTC_CNTL_USB_DP_PULLUP (BIT(6))
#define RTC_CNTL_USB_DP... | 2,145 |
*/
#define RTC_CNTL_USB_VREFL 0x00000003
#define RTC_CNTL_USB_VREFL_M ((RTC_CNTL_USB_VREFL_V)<<(RTC_CNTL_USB_VREFL_S))
#define RTC_CNTL_USB_VREFL_V 0x3
#define RTC_CNTL_USB_VREFL_S 2
/* RTC_CNTL_USB_VREFH : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
/*description: .*/
#define RTC_CNTL_USB_VREFH 0x00000003
#define R... | 2,145 |
*/
#define RTC_CNTL_REJECT_CAUSE 0x0003FFFF
#define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S))
#define RTC_CNTL_REJECT_CAUSE_V 0x3FFFF
#define RTC_CNTL_REJECT_CAUSE_S 0
#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x12C)
/* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;b... | 2,145 |
*/
#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFF
#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S))
#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0xFFFFFF
#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8
#define RTC_CNTL_INT_ENA_W1TS_REG (DR_... | 2,145 |
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