text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
*/
#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC (BIT(0))
#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_M (BIT(0))
#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_V 0x1
#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_S 0
#define SENS_SAR_DEBUG_CONF_REG (DR_REG_SENS_BASE + 0x114)
/* SENS_DEBUG_BIT_SEL : R/W ;bitpos:[4:0... | 2,137 |
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,138 |
0: 32KB, 1: 64KB*/
uint32_t dcache_blocksize_mode : 2; /*The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 bytes*/
uint32_t reserved5 : 27;
};
uint32_t val;
} dcache_ctrl;
union {
struct {
u... | 2,138 |
*/
uint32_t dcache_prelock_sct1_en : 1; /*The bit is used to enable the second section of prelock function.*/
uint32_t reserved2 : 30;
};
uint32_t val;
} dcache_prelock_ctrl;
uint32_t dcache_prelock_sct0_addr;
uint32_t dcache_prelock_... | 2,138 |
It will be cleared by hardware after unlock operation done.*/
uint32_t dcache_lock_done : 1; /*The bit is used to indicate unlock/lock operation is finished.*/
uint32_t reserved3 : 29;
};
uint32_t val;
} dcache_lock_ctrl;
uint32_t ... | 2,138 |
It will be cleared by hardware after writeback operation done.*/
uint32_t dcache_clean_ena : 1; /*The bit is used to enable clean operation. It will be cleared by hardware after clean operation done.*/
uint32_t dcache_sync_done : 1; /*The bit is used to indicat... | 2,138 |
It will be cleared by hardware after issuing Auot-Invalidate Operation.*/
uint32_t dcache_occupy_done : 1; /*The bit is used to indicate occupy operation is finished.*/
uint32_t reserved2 : 30;
};
uint32_t val;
} dcache_occupy_ctrl;
... | 2,138 |
*/
uint32_t dcache_preload_order : 1; /*The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.*/
uint32_t reserved3 : 29;
};
uint32_t val;
} dcache_preload_ctrl;
uint32_t dcache_preload_addr;
u... | 2,138 |
It is combined with dcache_autoload_done. 1: enable, 0: disable. */
uint32_t dcache_autoload_done : 1; /*The bit is used to indicate autoload operation is finished.*/
uint32_t dcache_autoload_order : 1; /*The bits are used to configure the direction of autoload. 1: desc... | 2,138 |
It should be combined with dcache_autoload_sct0_ena.*/
uint32_t reserved27 : 5;
};
uint32_t val;
} dcache_autoload_sct0_size;
uint32_t dcache_autoload_sct1_addr;
union {
struct {
uint32_t dcache_autoload_sct1_size : 27; /*The bit... | 2,138 |
0: 16 bytes, 1: 32 bytes*/
uint32_t reserved4 : 28;
};
uint32_t val;
} icache_ctrl;
union {
struct {
uint32_t icache_shut_core0_bus : 1; /*The bit is used to disable core0 ibus, 0: enable, 1: disable*/
uint32_t icache... | 2,138 |
*/
uint32_t icache_prelock_sct1_en : 1; /*The bit is used to enable the second section of prelock function.*/
uint32_t reserved2 : 30;
};
uint32_t val;
} icache_prelock_ctrl;
uint32_t icache_prelock_sct0_addr;
uint32_t icache_prelock_... | 2,138 |
It will be cleared by hardware after unlock operation done.*/
uint32_t icache_lock_done : 1; /*The bit is used to indicate unlock/lock operation is finished.*/
uint32_t reserved3 : 29;
};
uint32_t val;
} icache_lock_ctrl;
uint32_t ... | 2,138 |
*/
uint32_t reserved2 : 30;
};
uint32_t val;
} icache_sync_ctrl;
uint32_t icache_sync_addr;
union {
struct {
uint32_t icache_sync_size : 23; /*The bits are used to configure the length for sync operations. The bits are t... | 2,138 |
The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/
uint32_t reserved16 : 16;
};
uint32_t val;
} icache_preload_size;
union {
struct {
uint32_t icache_autoload_sct0_ena : 1; /*The bits are ... | 2,138 |
0/3: cache miss, 1: cache hit, 2: both cache miss and hit.*/
uint32_t icache_autoload_size : 2; /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/
uint32_t icache_autoload_buffer_clear : 1; /*The bit is used to clear autoload ... | 2,138 |
It should be combined with icache_autoload_sct1_ena.*/
uint32_t reserved27 : 5;
};
uint32_t val;
} icache_autoload_sct1_size;
uint32_t ibus_to_flash_start_vaddr;
uint32_t ibus_to_flash_end_vaddr;
uint32_t dbus_to_flash_start_vaddr;
uint32_t dbus_to_... | 2,138 |
*/
uint32_t icache_preload_op_fault : 1; /*The bit is used to enable interrupt by preload configurations fault.*/
uint32_t dcache_sync_op_fault : 1; /*The bit is used to enable interrupt by sync configurations fault.*/
uint32_t dcache_preload_op_fault : ... | 2,138 |
*/
uint32_t reserved9 : 23;
};
uint32_t val;
} cache_ilg_int_ena;
union {
struct {
uint32_t icache_sync_op_fault : 1; /*The bit is used to clear interrupt by sync configurations fault.*/
uint32_t icache_preload_op_fa... | 2,138 |
*/
uint32_t ibus_cnt_ovf : 1; /*The bit is used to clear interrupt by ibus counter overflow.*/
uint32_t dbus_cnt_ovf : 1; /*The bit is used to clear interrupt by dbus counter overflow.*/
uint32_t reserved9 : 23;
... | 2,138 |
*/
uint32_t mmu_entry_fault_st : 1; /*The bit is used to indicate interrupt by mmu entry fault.*/
uint32_t dcache_occupy_exc_st : 1; /*The bit is used to indicate interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/
... | 2,138 |
*/
uint32_t reserved12 : 20;
};
uint32_t val;
} cache_ilg_int_st;
union {
struct {
uint32_t core0_ibus_acs_msk_ic : 1; /*The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which inclu... | 2,138 |
*/
uint32_t core0_ibus_wr_ic : 1; /*The bit is used to clear interrupt by ibus trying to write icache*/
uint32_t core0_ibus_reject : 1; /*The bit is used to clear interrupt by authentication fail.*/
uint32_t core0_dbus_acs_msk_dc : 1; /*Th... | 2,138 |
*/
uint32_t core0_dbus_acs_msk_dcache_st : 1; /*The bit is used to indicate interrupt by cpu access dcache while the core0_dbus is disabled or dcache is disabled which include speculative access.*/
uint32_t core0_dbus_reject_st : 1; /*The bit is used to indicate interrupt by au... | 2,138 |
*/
uint32_t core1_dbus_reject : 1; /*The bit is used to enable interrupt by authentication fail.*/
uint32_t reserved5 : 27;
};
uint32_t val;
} core1_acs_cache_int_ena;
union {
struct {
uint32_t core1_ibus_acs_msk_... | 2,138 |
*/
uint32_t reserved5 : 27;
};
uint32_t val;
} core1_acs_cache_int_clr;
union {
struct {
uint32_t core1_ibus_acs_msk_icache_st : 1; /*The bit is used to indicate interrupt by cpu access icache while the core1_ibus is disabled or icach... | 2,138 |
0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
uint32_t core0_dbus_attr : 3; /*The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
uint32_t core0_dbus_world ... | 2,138 |
0: invalidate, 1: execute-able, 2: read-able*/
uint32_t core0_ibus_world : 1; /*The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1*/
uint32_t reserved7 : 25;
};
uint32_t val;
} core0... | 2,138 |
0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
uint32_t core1_ibus_attr : 3; /*The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able*/
uint32_t core1_ibus_world : 1;... | 2,138 |
The most significant bit is used to indicate this operation occurs in which one icache. */
uint32_t reserved20 : 12;
};
uint32_t val;
} cache_mmu_fault_content;
uint32_t cache_mmu_fault_vaddr;
union {
struct {
uint32_t cache_flash_wrap_a... | 2,138 |
1: in idle state, 0: not in idle state*/
uint32_t dcache_state : 12; /*The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state, 0: not in idle state*/
uint32_t reserved24 : 8;
};
uint32_t val;
... | 2,138 |
*/
uint32_t clk_force_on_crypt : 1; /*The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating.*/
uint32_t reserved3 : 29;
};
uint32_t val;
} cache_encrypt_decrypt_clk_force... | 2,138 |
*/
uint32_t dcache_preload_iena : 1; /*The bit is used to enable the interrupt by dcache pre-load done.*/
uint32_t dcache_preload_iclr : 1; /*The bit is used to clear the interrupt by dcache pre-load done.*/
uint32_t reserved6 : 26;
... | 2,138 |
*/
uint32_t dcache_sync_iclr : 1; /*The bit is used to clear the interrupt by dcache sync done.*/
uint32_t reserved6 : 26;
};
uint32_t val;
} cache_sync_int_ctrl;
union {
struct {
uint32_t cache_mmu_owner ... | 2,138 |
In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/
uint32_t reserved1 : 31;
};
uint32_t val;
} icache_atomic_operate_ena;
union {
struct {
uint32_t dcache_atomic_opera... | 2,138 |
*/
uint32_t reserved1 : 31;
};
uint32_t val;
} clock_gate;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
union {
struct {
uin... | 2,138 |
., 7: way7.*/
uint32_t reserved3 : 29; /*Reserved*/
};
uint32_t val;
} cache_tag_way_object;
uint32_t cache_vaddr;
uint32_t cache_tag_content;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
u... | 2,138 |
*/
uint32_t reserved28 : 4;
};
uint32_t val;
} date;
} extmem_dev_t;
extern extmem_dev_t EXTMEM;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_EXTMEM_STRUCT_H_ */
| 2,138 |
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,139 |
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,140 |
/*
*/
#pragma once
/**
*/
#define I2C_ULP 0x61
#define I2C_ULP_HOSTID 1
#define I2C_ULP_IR_RESETB 0
#define I2C_ULP_IR_RESETB_MSB 0
#define I2C_ULP_IR_RESETB_LSB 0
#define I2C_ULP_O_DONE_FLAG 3
#define I2C_ULP_O_DONE_FLAG_MSB 0
#define I2C_ULP_O_DONE_FLAG_LSB 0
#define I2C_ULP_BG_O_DONE_FLAG 3
#define I2C_ULP_B... | 2,141 |
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,143 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct i2s_dev_s {
uint32_t reserved_0;
uint32_t reserved_4;
uint32_t reserved_8;
union {
struct {
uint32_t rx_done : 1; /*The raw interrupt status bit for the i2s_rx_d... | 2,144 |
0: low addr with low addr value.*/
uint32_t rx_update : 1; /*Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.*/
uint32_t rx_mono_fst_vld : 1; /*1: The first c... | 2,144 |
*/
uint32_t rx_left_align : 1; /*1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/
uint32_t rx_24_fill_en : 1; /*1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/
uint32_t rx_ws_idle_pol : ... | 2,144 |
1: The down sampling rate is 128. 0: down sampling rate is 64.*/
uint32_t reserved23 : 9; /*Reserve*/
};
uint32_t val;
} rx_conf;
union {
struct {
uint32_t tx_reset : 1; /*Set this bit to reset transmitter*/
... | 2,144 |
0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/
uint32_t tx_big_endian : 1; /*I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.*/
uint32_t tx_update : 1; /*Set 1 ... | 2,144 |
*/
uint32_t tx_stop_en : 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/
uint32_t reserved14 : 1; /* Reserved*/
uint32_t tx_left_align : 1; /*1: I2S TX left alignment mode. 0: ... | 2,144 |
0: Disable.*/
uint32_t reserved21 : 3; /*Reserved*/
uint32_t tx_chan_mod : 3; /*I2S transmitter channel mode configuration bits.*/
uint32_t sig_loopback : 1; /*Enable signal loop back mode with transmitter module and ... | 2,144 |
23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.*/
uint32_t rx_half_sample_bits : 6; /*I2S Rx half sample bits -1.*/
uint32_t rx_tdm_chan_bits : 5; /*The Rx bit number for each channel minus 1in TDM mode.*/
... | 2,144 |
15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.*/
uint32_t tx_half_sample_bits : 6; /* I2S Tx half sample bits -1.*/
uint32_t tx_tdm_chan_bits : 5; /*The Tx bit nu... | 2,144 |
*/
uint32_t rx_clk_sel : 2; /*Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
uint32_t mclk_sel : 1; /* 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. */
... | 2,144 |
0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
uint32_t clk_en : 1; /*Set this bit to enable clk gate*/
uint32_t reserved30 : 2; /* Reserved*/
};
uint32_t val;
} tx_clkm_conf;
union {
struct {
... | 2,144 |
*/
uint32_t tx_clkm_div_y : 9; /*For b a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). */
uint32_t tx_clkm_div_x : 9; /*For b a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. */
uint32_t tx_clkm_div_yn1 : 1; /*For b ... | 2,144 |
0: Disable, just input 0 in this channel.*/
uint32_t rx_tdm_chan1_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
uint32_t rx_tdm_chan2_en : 1; /*1: Enable the valid data input of I2S RX ... | 2,144 |
0: Disable, just input 0 in this channel.*/
uint32_t rx_tdm_chan7_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
uint32_t rx_tdm_chan8_en : 1; /*1: Enable the valid data input of I2S RX ... | 2,144 |
*/
uint32_t rx_tdm_chan13_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
uint32_t rx_tdm_chan14_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this ... | 2,144 |
0: Disable, just output 0 in this channel.*/
uint32_t tx_tdm_chan2_en : 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 0 in this channel.*/
uint32_t tx_tdm_chan3_en : 1; /*1: Enable the valid data output of I2S TX TDM... | 2,144 |
*/
uint32_t tx_tdm_chan8_en : 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 0 in this channel.*/
uint32_t tx_tdm_chan9_en : 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 0 in t... | 2,144 |
0: Disable, just output 0 in this channel.*/
uint32_t tx_tdm_chan15_en : 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 0 in this channel.*/
uint32_t tx_tdm_tot_chan_num : 4; /*The total channel number of I2S TX TDM mode.*... | 2,144 |
0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved6 : 2;
uint32_t rx_sd2_in_dm : 2; /*The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
u... | 2,144 |
3: not used.*/
uint32_t reserved22 : 2; /* Reserved*/
uint32_t rx_ws_in_dm : 2; /*The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved26 : ... | 2,144 |
0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved6 : 10; /* Reserved*/
uint32_t tx_ws_out_dm : 2; /*The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.... | 2,144 |
0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved30 : 2; /* Reserved*/
};
uint32_t val;
} tx_timing;
union {
struct {
uint32_t fifo_timeout : 8; /*the i2s_tx_hung_int interrupt or ... | 2,144 |
It will trigger in_suc_eof interrupt in the configured DMA RX channel.*/
uint32_t reserved12 : 20; /* Reserved*/
};
uint32_t val;
} rx_eof_num;
uint32_t conf_single_data; /*the right channel or left channel put out constant value ... | 2,144 |
/*
*/
#ifndef _SOC_RTC_CNTL_REG_H_
#define _SOC_RTC_CNTL_REG_H_
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG to write-enable the wdt registers */
#define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A
#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_... | 2,145 |
*/
#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29))
#define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29))
#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1
#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29
/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */
/*description: .*/
#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28))
... | 2,145 |
*/
#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25))
#define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25))
#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1
#define RTC_CNTL_ANALOG_FORCE_ISO_S 25
/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */
/*description: .*/
#define RTC_CNTL_PLL_FORCE_ISO (BIT(24))
#define RTC_CN... | 2,145 |
*/
#define RTC_CNTL_XTL_FORCE_PU (BIT(13))
#define RTC_CNTL_XTL_FORCE_PU_M (BIT(13))
#define RTC_CNTL_XTL_FORCE_PU_V 0x1
#define RTC_CNTL_XTL_FORCE_PU_S 13
/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: crystall force power down.*/
#define RTC_CNTL_XTL_FORCE_PD (BIT(12))
#define... | 2,145 |
*/
#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9))
#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9))
#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1
#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9
/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: BB_PLL _I2C force power down.*/
#define RTC_CNTL_BBPL... | 2,145 |
*/
#define RTC_CNTL_SW_PROCPU_RST (BIT(5))
#define RTC_CNTL_SW_PROCPU_RST_M (BIT(5))
#define RTC_CNTL_SW_PROCPU_RST_V 0x1
#define RTC_CNTL_SW_PROCPU_RST_S 5
/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */
/*description: APP CPU SW reset.*/
#define RTC_CNTL_SW_APPCPU_RST (BIT(4))
#define RTC_CNTL... | 2,145 |
*/
#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003
#define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S))
#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3
#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0
#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4)
/* RTC_... | 2,145 |
*/
#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF
#define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S))
#define RTC_CNTL_SLP_VAL_HI_V 0xFFFF
#define RTC_CNTL_SLP_VAL_HI_S 0
#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xC)
/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default:... | 2,145 |
*/
#define RTC_CNTL_TIMER_SYS_STALL (BIT(27))
#define RTC_CNTL_TIMER_SYS_STALL_M (BIT(27))
#define RTC_CNTL_TIMER_SYS_STALL_V 0x1
#define RTC_CNTL_TIMER_SYS_STALL_S 27
#define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x10)
/* RTC_CNTL_TIMER_VALUE0_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*desc... | 2,145 |
*/
#define RTC_CNTL_SLEEP_EN (BIT(31))
#define RTC_CNTL_SLEEP_EN_M (BIT(31))
#define RTC_CNTL_SLEEP_EN_V 0x1
#define RTC_CNTL_SLEEP_EN_S 31
/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */
/*description: leep reject bit.*/
#define RTC_CNTL_SLP_REJECT (BIT(30))
#define RTC_CNTL_SLP_REJECT_M (BIT(3... | 2,145 |
*/
#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22))
#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22))
#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1
#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22
/* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
/*description: clear rtc sleep reject cause.*/
#define RTC_CNTL_... | 2,145 |
*/
#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF
#define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S))
#define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF
#define RTC_CNTL_XTL_BUF_WAIT_S 14
/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */
/*description: CK8M wait cycles in slow_clk_rt... | 2,145 |
*/
#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF
#define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S))
#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF
#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24
/* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W ;bitpos:[23:15] ;default: 9'h10 ; */
/*d... | 2,145 |
*/
#define RTC_CNTL_BT_WAIT_TIMER 0x000001FF
#define RTC_CNTL_BT_WAIT_TIMER_M ((RTC_CNTL_BT_WAIT_TIMER_V)<<(RTC_CNTL_BT_WAIT_TIMER_S))
#define RTC_CNTL_BT_WAIT_TIMER_V 0x1FF
#define RTC_CNTL_BT_WAIT_TIMER_S 16
/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */
/*description: .*/
#define RTC_C... | 2,145 |
*/
#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F
#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S))
#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F
#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25
/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;def... | 2,145 |
*/
#define RTC_CNTL_MIN_SLP_VAL 0x000000FF
#define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S))
#define RTC_CNTL_MIN_SLP_VAL_V 0xFF
#define RTC_CNTL_MIN_SLP_VAL_S 8
#define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x30)
/* RTC_CNTL_DG_PERI_POWERUP_TIMER : R/W ;bitpos:[31... | 2,145 |
*/
#define RTC_CNTL_CPU_TOP_POWERUP_TIMER 0x0000007F
#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_M ((RTC_CNTL_CPU_TOP_POWERUP_TIMER_V)<<(RTC_CNTL_CPU_TOP_POWERUP_TIMER_S))
#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_V 0x7F
#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_S 9
/* RTC_CNTL_CPU_TOP_WAIT_TIMER : R/W ;bitpos:[8:0] ;defaul... | 2,145 |
*/
#define RTC_CNTL_RFRX_PBUS_PU (BIT(28))
#define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28))
#define RTC_CNTL_RFRX_PBUS_PU_V 0x1
#define RTC_CNTL_RFRX_PBUS_PU_S 28
/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */
/*description: 1: TXRF_I2C power up.*/
#define RTC_CNTL_TXRF_I2C_PU (BIT(27))
#define RTC_CN... | 2,145 |
*/
#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR (BIT(24))
#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_M (BIT(24))
#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_V 0x1
#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_S 24
/* RTC_CNTL_ANALOG_TOP_ISO_SLEEP : R/W ;bitpos:[23] ;default: 1'b0 ; */
/*description: PLLA force power down.*/
#defin... | 2,145 |
*/
#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19))
#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (BIT(19))
#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x1
#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19
/* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b1 ; */
/*description: .*/
#define RTC_CNTL_I2C_RESE... | 2,145 |
*/
#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR (BIT(23))
#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_M (BIT(23))
#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_V 0x1
#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_S 23
/* RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
/*description: .*/
#defin... | 2,145 |
*/
#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET (BIT(19))
#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_M (BIT(19))
#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_V 0x1
#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_S 19
/* RTC_CNTL_APPCPU_OCD_HALT_ON_RESET : R/W ;bitpos:[18] ;default: 1'b0 ; */
/*description: APPCPU OcdHaltOnRes... | 2,145 |
*/
#define RTC_CNTL_RESET_FLAG_APPCPU (BIT(15))
#define RTC_CNTL_RESET_FLAG_APPCPU_M (BIT(15))
#define RTC_CNTL_RESET_FLAG_APPCPU_V 0x1
#define RTC_CNTL_RESET_FLAG_APPCPU_S 15
/* RTC_CNTL_RESET_FLAG_PROCPU : RO ;bitpos:[14] ;default: 1'b0 ; */
/*description: PRO CPU reset_flag.*/
#define RTC_CNTL_RESET_FLAG_PROCP... | 2,145 |
*/
#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F
#define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S))
#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F
#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6
/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */
/*descrip... | 2,145 |
*/
#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA (BIT(20))
#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M (BIT(20))
#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V 0x1
#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 20
/* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
/*descri... | 2,145 |
*/
#define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16))
#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M (BIT(16))
#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V 0x1
#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S 16
/* RTC_CNTL_SWD_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: enable super watch dog interrupt.*/
#define RTC_... | 2,145 |
*/
#define RTC_CNTL_TSENS_INT_ENA (BIT(12))
#define RTC_CNTL_TSENS_INT_ENA_M (BIT(12))
#define RTC_CNTL_TSENS_INT_ENA_V 0x1
#define RTC_CNTL_TSENS_INT_ENA_S 12
/* RTC_CNTL_SARADC1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: enable saradc1 interrupt.*/
#define RTC_CNTL_SARADC1_INT_ENA (BIT(11)... | 2,145 |
*/
#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA (BIT(8))
#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_M (BIT(8))
#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_V 0x1
#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_S 8
/* RTC_CNTL_TOUCH_ACTIVE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: enable touch active interrupt.*/
#d... | 2,145 |
*/
#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA (BIT(4))
#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_M (BIT(4))
#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_V 0x1
#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_S 4
/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: enable RTC WDT interrupt.*/
#define RTC_... | 2,145 |
*/
#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0))
#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0))
#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1
#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0
#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x44)
/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW : R/W ;bitpos:[20] ;defa... | 2,145 |
*/
#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW (BIT(18))
#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_M (BIT(18))
#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_V 0x1
#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_S 18
/* RTC_CNTL_COCPU_TRAP_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
/*description: cocpu trap interrupt raw.*/
#define RT... | 2,145 |
*/
#define RTC_CNTL_SARADC2_INT_RAW (BIT(14))
#define RTC_CNTL_SARADC2_INT_RAW_M (BIT(14))
#define RTC_CNTL_SARADC2_INT_RAW_V 0x1
#define RTC_CNTL_SARADC2_INT_RAW_S 14
/* RTC_CNTL_COCPU_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
/*description: riscV cocpu interrupt raw.*/
#define RTC_CNTL_COCPU_INT_RAW (BIT... | 2,145 |
*/
#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10))
#define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(10))
#define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1
#define RTC_CNTL_MAIN_TIMER_INT_RAW_S 10
/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: brown out interrupt raw.*/
#define RTC_CNTL_BROWN_OU... | 2,145 |
*/
#define RTC_CNTL_TOUCH_DONE_INT_RAW (BIT(6))
#define RTC_CNTL_TOUCH_DONE_INT_RAW_M (BIT(6))
#define RTC_CNTL_TOUCH_DONE_INT_RAW_V 0x1
#define RTC_CNTL_TOUCH_DONE_INT_RAW_S 6
/* RTC_CNTL_ULP_CP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: ULP-coprocessor interrupt raw.*/
#define RTC_CNTL_ULP_CP_I... | 2,145 |
*/
#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2))
#define RTC_CNTL_SDIO_IDLE_INT_RAW_M (BIT(2))
#define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x1
#define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2
/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: sleep reject interrupt raw.*/
#define RTC_CNTL_SLP_REJECT_... | 2,145 |
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