text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
0:SPI2. 1: SPI3. 2:
UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT.; 7: AE
S. 8: SHA. 9: ADC_DAC..*/
#define GDMA_PERI_OUT_SEL_CH4 0x0000003F
#define GDMA_PERI_OUT_SEL_CH4_M ((GDMA_PERI_OUT_SEL_CH4_V)<<(GDMA_PERI_OUT_SEL_CH4_S))
#define GDMA_PERI_OUT_SEL_CH4_V 0x3F
#define GDMA_PERI_OUT_... | 2,150 |
0: A gate-clock will be used when accessing the RAM in DMA..*/
#define GDMA_DMA_RAM_CLK_FO (BIT(6))
#define GDMA_DMA_RAM_CLK_FO_M (BIT(6))
#define GDMA_DMA_RAM_CLK_FO_V 0x1
#define GDMA_DMA_RAM_CLK_FO_S 6
/* GDMA_DMA_RAM_FORCE_PU : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: .*/
#define GDMA_DMA_RAM_FORCE... | 2,150 |
.*/
#define GDMA_ARB_PRI_DIS (BIT(2))
#define GDMA_ARB_PRI_DIS_M (BIT(2))
#define GDMA_ARB_PRI_DIS_V 0x1
#define GDMA_ARB_PRI_DIS_S 2
/* GDMA_AHBM_RST_EXTER : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: Set this bit, then clear this bit to reset the external ahb FSM..*/
#define GDMA_AHBM_RST_EXTER (BIT(... | 2,150 |
5:56 bytes. 6: 64 byte
s. 7: 72 bytes. 8: 80 bytes..*/
#define GDMA_IN_SIZE_CH0 0x0000007F
#define GDMA_IN_SIZE_CH0_M ((GDMA_IN_SIZE_CH0_V)<<(GDMA_IN_SIZE_CH0_S))
#define GDMA_IN_SIZE_CH0_V 0x7F
#define GDMA_IN_SIZE_CH0_S 0
#define GDMA_OUT_SRAM_SIZE_CH0_REG (DR_REG_GDMA_BASE + 0x3D0)
/* GDMA_OUT_SIZE_... | 2,150 |
2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 byte
s. 7: 72 bytes. 8: 80 bytes..*/
#define GDMA_IN_SIZE_CH1 0x0000007F
#define GDMA_IN_SIZE_CH1_M ((GDMA_IN_SIZE_CH1_V)<<(GDMA_IN_SIZE_CH1_S))
#define GDMA_IN_SIZE_CH1_V 0x7F
#define GDMA_IN_SIZE_CH1_S 0
#define GDMA_OUT_SRAM_SIZE_CH1_REG (DR_RE... | 2,150 |
0:16
bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 byte
s. 7: 72 bytes. 8: 80 bytes..*/
#define GDMA_IN_SIZE_CH2 0x0000007F
#define GDMA_IN_SIZE_CH2_M ((GDMA_IN_SIZE_CH2_V)<<(GDMA_IN_SIZE_CH2_S))
#define GDMA_IN_SIZE_CH2_V 0x7F
#define GDMA_IN_SIZE_CH2_S 0
#define GDMA_OUT_SRAM_SIZ... | 2,150 |
0:16
bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 byte
s. 7: 72 bytes. 8: 80 bytes..*/
#define GDMA_IN_SIZE_CH3 0x0000007F
#define GDMA_IN_SIZE_CH3_M ((GDMA_IN_SIZE_CH3_V)<<(GDMA_IN_SIZE_CH3_S))
#define GDMA_IN_SIZE_CH3_V 0x7F
#define GDMA_IN_SIZE_CH3_S 0
#define GDMA_OUT_SRAM_SIZ... | 2,150 |
0:16
bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 byte
s. 7: 72 bytes. 8: 80 bytes..*/
#define GDMA_IN_SIZE_CH4 0x0000007F
#define GDMA_IN_SIZE_CH4_M ((GDMA_IN_SIZE_CH4_V)<<(GDMA_IN_SIZE_CH4_S))
#define GDMA_IN_SIZE_CH4_V 0x7F
#define GDMA_IN_SIZE_CH4_S 0
#define GDMA_OUT_SRAM_SIZ... | 2,150 |
.*/
#define GDMA_EXTMEM_REJECT_ADDR 0xFFFFFFFF
#define GDMA_EXTMEM_REJECT_ADDR_M ((GDMA_EXTMEM_REJECT_ADDR_V)<<(GDMA_EXTMEM_REJECT_ADDR_S))
#define GDMA_EXTMEM_REJECT_ADDR_V 0xFFFFFFFF
#define GDMA_EXTMEM_REJECT_ADDR_S 0
#define GDMA_EXTMEM_REJECT_ST_REG (DR_REG_GDMA_BASE + 0x3F8)
/* GDMA_EXTMEM_REJECT_... | 2,150 |
Bit 0: if this bit is 1, the rejected accessing is READ. B
it 1: if this bit is 1, the rejected accessing is WRITE..*/
#define GDMA_EXTMEM_REJECT_ATTR 0x00000003
#define GDMA_EXTMEM_REJECT_ATTR_M ((GDMA_EXTMEM_REJECT_ATTR_V)<<(GDMA_EXTMEM_REJECT_ATTR_S))
#define GDMA_EXTMEM_REJECT_ATTR_V 0x3
#define GDMA_EXTMEM_R... | 2,150 |
.*/
#define GDMA_EXTMEM_REJECT_INT_ST (BIT(0))
#define GDMA_EXTMEM_REJECT_INT_ST_M (BIT(0))
#define GDMA_EXTMEM_REJECT_INT_ST_V 0x1
#define GDMA_EXTMEM_REJECT_INT_ST_S 0
#define GDMA_EXTMEM_REJECT_INT_ENA_REG (DR_REG_GDMA_BASE + 0x404)
/* GDMA_EXTMEM_REJECT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
... | 2,150 |
.*/
#define GDMA_DATE 0xFFFFFFFF
#define GDMA_DATE_M ((GDMA_DATE_V)<<(GDMA_DATE_S))
#define GDMA_DATE_V 0xFFFFFFFF
#define GDMA_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_GDMA_REG_H_ */
| 2,150 |
/**
*/
#ifndef _SOC_SYSCON_REG_H_
#define _SOC_SYSCON_REG_H_
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x0)
/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: .*/
#define SYSCON_RST_TICK_CNT (BIT(12))
#define SY... | 2,151 |
*/
#define SYSCON_TICK_ENABLE (BIT(16))
#define SYSCON_TICK_ENABLE_M (BIT(16))
#define SYSCON_TICK_ENABLE_V 0x1
#define SYSCON_TICK_ENABLE_S 16
/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
/*description: .*/
#define SYSCON_CK8M_TICK_NUM 0x000000FF
#define SYSCON_CK8M_TICK_NUM_M ((SYSCON_CK... | 2,151 |
*/
#define SYSCON_CLK40X_BB_OEN (BIT(9))
#define SYSCON_CLK40X_BB_OEN_M (BIT(9))
#define SYSCON_CLK40X_BB_OEN_V 0x1
#define SYSCON_CLK40X_BB_OEN_S 9
/* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
/*description: .*/
#define SYSCON_CLK_DAC_CPU_OEN (BIT(8))
#define SYSCON_CLK_DAC_CPU_OEN_M (BIT(... | 2,151 |
*/
#define SYSCON_CLK80_OEN (BIT(4))
#define SYSCON_CLK80_OEN_M (BIT(4))
#define SYSCON_CLK80_OEN_V 0x1
#define SYSCON_CLK80_OEN_S 4
/* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: .*/
#define SYSCON_CLK_BB_OEN (BIT(3))
#define SYSCON_CLK_BB_OEN_M (BIT(3))
#define SYSCON_CLK_BB_OEN_V... | 2,151 |
*/
#define SYSCON_WIFI_BB_CFG 0xFFFFFFFF
#define SYSCON_WIFI_BB_CFG_M ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S))
#define SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF
#define SYSCON_WIFI_BB_CFG_S 0
#define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x10)
/* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default... | 2,151 |
*/
#define SYSCON_WIFI_RST 0xFFFFFFFF
#define SYSCON_WIFI_RST_M ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S))
#define SYSCON_WIFI_RST_V 0xFFFFFFFF
#define SYSCON_WIFI_RST_S 0
#define SYSTEM_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG
/* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
/*description: *... | 2,151 |
*/
#define SYSCON_PERI_IO_SWAP 0x000000FF
#define SYSCON_PERI_IO_SWAP_M ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S))
#define SYSCON_PERI_IO_SWAP_V 0xFF
#define SYSCON_PERI_IO_SWAP_S 0
#define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x20)
/* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;defa... | 2,151 |
*/
#define SYSCON_FLASH_ACE0_ATTR 0x000001FF
#define SYSCON_FLASH_ACE0_ATTR_M ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S))
#define SYSCON_FLASH_ACE0_ATTR_V 0x1FF
#define SYSCON_FLASH_ACE0_ATTR_S 0
#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x2C)
/* SYSCON_FLASH_ACE1_ATTR : R/W ... | 2,151 |
*/
#define SYSCON_FLASH_ACE3_ATTR 0x000001FF
#define SYSCON_FLASH_ACE3_ATTR_M ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S))
#define SYSCON_FLASH_ACE3_ATTR_V 0x1FF
#define SYSCON_FLASH_ACE3_ATTR_S 0
#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x38)
/* SYSCON_FLASH_ACE0_ADDR_S : R/... | 2,151 |
*/
#define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFF
#define SYSCON_FLASH_ACE2_ADDR_S_M ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S))
#define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE2_ADDR_S_S 0
#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x44)
/* SYSCON_FLASH... | 2,151 |
*/
#define SYSCON_FLASH_ACE1_SIZE 0x0000FFFF
#define SYSCON_FLASH_ACE1_SIZE_M ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S))
#define SYSCON_FLASH_ACE1_SIZE_V 0xFFFF
#define SYSCON_FLASH_ACE1_SIZE_S 0
#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x50)
/* SYSCON_FLASH_ACE2_SIZE : R/W... | 2,151 |
*/
#define SYSCON_SRAM_ACE0_ATTR 0x000001FF
#define SYSCON_SRAM_ACE0_ATTR_M ((SYSCON_SRAM_ACE0_ATTR_V)<<(SYSCON_SRAM_ACE0_ATTR_S))
#define SYSCON_SRAM_ACE0_ATTR_V 0x1FF
#define SYSCON_SRAM_ACE0_ATTR_S 0
#define SYSCON_SRAM_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x5C)
/* SYSCON_SRAM_ACE1_ATTR : R/W ;bitpos:... | 2,151 |
*/
#define SYSCON_SRAM_ACE3_ATTR 0x000001FF
#define SYSCON_SRAM_ACE3_ATTR_M ((SYSCON_SRAM_ACE3_ATTR_V)<<(SYSCON_SRAM_ACE3_ATTR_S))
#define SYSCON_SRAM_ACE3_ATTR_V 0x1FF
#define SYSCON_SRAM_ACE3_ATTR_S 0
#define SYSCON_SRAM_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x68)
/* SYSCON_SRAM_ACE0_ADDR_S : R/W ;bitpo... | 2,151 |
*/
#define SYSCON_SRAM_ACE2_ADDR_S 0xFFFFFFFF
#define SYSCON_SRAM_ACE2_ADDR_S_M ((SYSCON_SRAM_ACE2_ADDR_S_V)<<(SYSCON_SRAM_ACE2_ADDR_S_S))
#define SYSCON_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF
#define SYSCON_SRAM_ACE2_ADDR_S_S 0
#define SYSCON_SRAM_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x74)
/* SYSCON_SRAM_ACE3_AD... | 2,151 |
*/
#define SYSCON_SRAM_ACE1_SIZE 0x0000FFFF
#define SYSCON_SRAM_ACE1_SIZE_M ((SYSCON_SRAM_ACE1_SIZE_V)<<(SYSCON_SRAM_ACE1_SIZE_S))
#define SYSCON_SRAM_ACE1_SIZE_V 0xFFFF
#define SYSCON_SRAM_ACE1_SIZE_S 0
#define SYSCON_SRAM_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x80)
/* SYSCON_SRAM_ACE2_SIZE : R/W ;bitpos... | 2,151 |
*/
#define SYSCON_SPI_MEM_REJECT_CDE 0x0000001F
#define SYSCON_SPI_MEM_REJECT_CDE_M ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S))
#define SYSCON_SPI_MEM_REJECT_CDE_V 0x1F
#define SYSCON_SPI_MEM_REJECT_CDE_S 2
/* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
/*description: .*/
#d... | 2,151 |
*/
#define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0))
#define SYSCON_SDIO_WIN_ACCESS_EN_M (BIT(0))
#define SYSCON_SDIO_WIN_ACCESS_EN_V 0x1
#define SYSCON_SDIO_WIN_ACCESS_EN_S 0
#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x94)
/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: .*... | 2,151 |
*/
#define SYSCON_REDCY_SIG1 0x7FFFFFFF
#define SYSCON_REDCY_SIG1_M ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S))
#define SYSCON_REDCY_SIG1_V 0x7FFFFFFF
#define SYSCON_REDCY_SIG1_S 0
#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x9C)
/* SYSCON_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: ... | 2,151 |
*/
#define SYSCON_DC_MEM_FORCE_PU (BIT(4))
#define SYSCON_DC_MEM_FORCE_PU_M (BIT(4))
#define SYSCON_DC_MEM_FORCE_PU_V 0x1
#define SYSCON_DC_MEM_FORCE_PU_S 4
/* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: .*/
#define SYSCON_PBUS_MEM_FORCE_PD (BIT(3))
#define SYSCON_PBUS_MEM_FOR... | 2,151 |
0: 256 bytes. 1: 512 bytes. 2:
1024 bytes. 3: 2048 bytes..*/
#define SYSCON_SRAM_PAGE_SIZE 0x00000003
#define SYSCON_SRAM_PAGE_SIZE_M ((SYSCON_SRAM_PAGE_SIZE_V)<<(SYSCON_SRAM_PAGE_SIZE_S))
#define SYSCON_SRAM_PAGE_SIZE_V 0x3
#define SYSCON_SRAM_PAGE_SIZE_S 20
/* SYSCON_FLASH_PAGE_SIZE : R/W ;bitpos:[19:18] ;defa... | 2,151 |
*/
#define SYSCON_ROM_CLKGATE_FORCE_ON 0x00000007
#define SYSCON_ROM_CLKGATE_FORCE_ON_M ((SYSCON_ROM_CLKGATE_FORCE_ON_V)<<(SYSCON_ROM_CLKGATE_FORCE_ON_S))
#define SYSCON_ROM_CLKGATE_FORCE_ON_V 0x7
#define SYSCON_ROM_CLKGATE_FORCE_ON_S 0
#define SYSCON_MEM_POWER_DOWN_REG (DR_REG_SYSCON_BASE + 0xAC)
/* SY... | 2,151 |
*/
#define SYSCON_SRAM_POWER_UP 0x000007FF
#define SYSCON_SRAM_POWER_UP_M ((SYSCON_SRAM_POWER_UP_V)<<(SYSCON_SRAM_POWER_UP_S))
#define SYSCON_SRAM_POWER_UP_V 0x7FF
#define SYSCON_SRAM_POWER_UP_S 3
/* SYSCON_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
/*description: .*/
#define SYSCON_ROM_POWER_UP 0x0... | 2,151 |
*/
#define SYSCON_RETENTION_TAG_LINK_ADDR 0x07FFFFFF
#define SYSCON_RETENTION_TAG_LINK_ADDR_M ((SYSCON_RETENTION_TAG_LINK_ADDR_V)<<(SYSCON_RETENTION_TAG_LINK_ADDR_S))
#define SYSCON_RETENTION_TAG_LINK_ADDR_V 0x7FFFFFF
#define SYSCON_RETENTION_TAG_LINK_ADDR_S 0
#define SYSCON_RETENTION_CTRL2_REG (DR_REG_... | 2,151 |
*/
#define SYSCON_RET_ICACHE_VLD_SIZE 0x000000FF
#define SYSCON_RET_ICACHE_VLD_SIZE_M ((SYSCON_RET_ICACHE_VLD_SIZE_V)<<(SYSCON_RET_ICACHE_VLD_SIZE_S))
#define SYSCON_RET_ICACHE_VLD_SIZE_V 0xFF
#define SYSCON_RET_ICACHE_VLD_SIZE_S 13
/* SYSCON_RET_ICACHE_SIZE : R/W ;bitpos:[11:4] ;default: 8'hff ; */
/*description... | 2,151 |
*/
#define SYSCON_RET_DCACHE_VLD_SIZE 0x000001FF
#define SYSCON_RET_DCACHE_VLD_SIZE_M ((SYSCON_RET_DCACHE_VLD_SIZE_V)<<(SYSCON_RET_DCACHE_VLD_SIZE_S))
#define SYSCON_RET_DCACHE_VLD_SIZE_V 0x1FF
#define SYSCON_RET_DCACHE_VLD_SIZE_S 13
/* SYSCON_RET_DCACHE_SIZE : R/W ;bitpos:[12:4] ;default: 9'h1ff ; */
/*descripti... | 2,151 |
*/
#define SYSCON_RETENTION_DISABLE (BIT(0))
#define SYSCON_RETENTION_DISABLE_M (BIT(0))
#define SYSCON_RETENTION_DISABLE_V 0x1
#define SYSCON_RETENTION_DISABLE_S 0
#define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC)
/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101150 ; */
/*description: Version ... | 2,151 |
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,152 |
*/
#define HOST_GPIO_SDIO_INT0 0xFFFFFFFF
#define HOST_GPIO_SDIO_INT0_M ((HOST_GPIO_SDIO_INT0_V)<<(HOST_GPIO_SDIO_INT0_S))
#define HOST_GPIO_SDIO_INT0_V 0xFFFFFFFF
#define HOST_GPIO_SDIO_INT0_S 0
#define HOST_SLCHOST_GPIO_STATUS1_REG (DR_REG_SLCHOST_BASE + 0x38)
/* HOST_GPIO_SDIO_INT1 : RO ;bitpos:[21:0... | 2,152 |
*/
#define HOST_GPIO_SDIO_IN1 0x003FFFFF
#define HOST_GPIO_SDIO_IN1_M ((HOST_GPIO_SDIO_IN1_V)<<(HOST_GPIO_SDIO_IN1_S))
#define HOST_GPIO_SDIO_IN1_V 0x3FFFFF
#define HOST_GPIO_SDIO_IN1_S 0
#define HOST_SLC0HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x44)
/* HOST_SLC0_RX_PF_EOF : RO ;bitpos:[31:28] ;defa... | 2,152 |
*/
#define HOST_SLC0_TOKEN0 0x00000FFF
#define HOST_SLC0_TOKEN0_M ((HOST_SLC0_TOKEN0_V)<<(HOST_SLC0_TOKEN0_S))
#define HOST_SLC0_TOKEN0_V 0xFFF
#define HOST_SLC0_TOKEN0_S 0
#define HOST_SLC0_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x48)
/* HOST_SLC0_PF_DATA : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*descript... | 2,152 |
*/
#define HOST_SLC0_RX_NEW_PACKET_INT_RAW (BIT(23))
#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_M (BIT(23))
#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_V 0x1
#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_S 23
/* HOST_SLC0_EXT_BIT3_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_EXT_BIT3_INT_... | 2,152 |
*/
#define HOST_SLC0_EXT_BIT0_INT_RAW (BIT(19))
#define HOST_SLC0_EXT_BIT0_INT_RAW_M (BIT(19))
#define HOST_SLC0_EXT_BIT0_INT_RAW_V 0x1
#define HOST_SLC0_EXT_BIT0_INT_RAW_S 19
/* HOST_SLC0_RX_PF_VALID_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_RX_PF_VALID_INT_RAW (BIT(18... | 2,152 |
*/
#define HOST_SLC0HOST_TX_START_INT_RAW (BIT(15))
#define HOST_SLC0HOST_TX_START_INT_RAW_M (BIT(15))
#define HOST_SLC0HOST_TX_START_INT_RAW_V 0x1
#define HOST_SLC0HOST_TX_START_INT_RAW_S 15
/* HOST_SLC0HOST_RX_START_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0HOST_RX_START_... | 2,152 |
*/
#define HOST_SLC0_TOKEN1_0TO1_INT_RAW (BIT(11))
#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_M (BIT(11))
#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_V 0x1
#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_S 11
/* HOST_SLC0_TOKEN0_0TO1_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_TOKEN0_0TO1_INT_RA... | 2,152 |
*/
#define HOST_SLC0_TOHOST_BIT7_INT_RAW (BIT(7))
#define HOST_SLC0_TOHOST_BIT7_INT_RAW_M (BIT(7))
#define HOST_SLC0_TOHOST_BIT7_INT_RAW_V 0x1
#define HOST_SLC0_TOHOST_BIT7_INT_RAW_S 7
/* HOST_SLC0_TOHOST_BIT6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_TOHOST_BIT6_INT_RAW ... | 2,152 |
*/
#define HOST_SLC0_TOHOST_BIT3_INT_RAW (BIT(3))
#define HOST_SLC0_TOHOST_BIT3_INT_RAW_M (BIT(3))
#define HOST_SLC0_TOHOST_BIT3_INT_RAW_V 0x1
#define HOST_SLC0_TOHOST_BIT3_INT_RAW_S 3
/* HOST_SLC0_TOHOST_BIT2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_TOHOST_BIT2_INT_RAW ... | 2,152 |
*/
#define HOST_GPIO_SDIO_INT_ST (BIT(25))
#define HOST_GPIO_SDIO_INT_ST_M (BIT(25))
#define HOST_GPIO_SDIO_INT_ST_V 0x1
#define HOST_GPIO_SDIO_INT_ST_S 25
/* HOST_SLC0_HOST_RD_RETRY_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_HOST_RD_RETRY_INT_ST (BIT(24))
#define HOST_SL... | 2,152 |
*/
#define HOST_SLC0_EXT_BIT2_INT_ST (BIT(21))
#define HOST_SLC0_EXT_BIT2_INT_ST_M (BIT(21))
#define HOST_SLC0_EXT_BIT2_INT_ST_V 0x1
#define HOST_SLC0_EXT_BIT2_INT_ST_S 21
/* HOST_SLC0_EXT_BIT1_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_EXT_BIT1_INT_ST (BIT(20))
#define H... | 2,152 |
*/
#define HOST_SLC0_TX_OVF_INT_ST (BIT(17))
#define HOST_SLC0_TX_OVF_INT_ST_M (BIT(17))
#define HOST_SLC0_TX_OVF_INT_ST_V 0x1
#define HOST_SLC0_TX_OVF_INT_ST_S 17
/* HOST_SLC0_RX_UDF_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_RX_UDF_INT_ST (BIT(16))
#define HOST_SLC0_RX_... | 2,152 |
*/
#define HOST_SLC0HOST_RX_EOF_INT_ST (BIT(13))
#define HOST_SLC0HOST_RX_EOF_INT_ST_M (BIT(13))
#define HOST_SLC0HOST_RX_EOF_INT_ST_V 0x1
#define HOST_SLC0HOST_RX_EOF_INT_ST_S 13
/* HOST_SLC0HOST_RX_SOF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0HOST_RX_SOF_INT_ST (BIT(12... | 2,152 |
*/
#define HOST_SLC0_TOKEN1_1TO0_INT_ST (BIT(9))
#define HOST_SLC0_TOKEN1_1TO0_INT_ST_M (BIT(9))
#define HOST_SLC0_TOKEN1_1TO0_INT_ST_V 0x1
#define HOST_SLC0_TOKEN1_1TO0_INT_ST_S 9
/* HOST_SLC0_TOKEN0_1TO0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_TOKEN0_1TO0_INT_ST (BIT(... | 2,152 |
*/
#define HOST_SLC0_TOHOST_BIT5_INT_ST (BIT(5))
#define HOST_SLC0_TOHOST_BIT5_INT_ST_M (BIT(5))
#define HOST_SLC0_TOHOST_BIT5_INT_ST_V 0x1
#define HOST_SLC0_TOHOST_BIT5_INT_ST_S 5
/* HOST_SLC0_TOHOST_BIT4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_TOHOST_BIT4_INT_ST (BIT(... | 2,152 |
*/
#define HOST_SLC0_TOHOST_BIT1_INT_ST (BIT(1))
#define HOST_SLC0_TOHOST_BIT1_INT_ST_M (BIT(1))
#define HOST_SLC0_TOHOST_BIT1_INT_ST_V 0x1
#define HOST_SLC0_TOHOST_BIT1_INT_ST_S 1
/* HOST_SLC0_TOHOST_BIT0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_TOHOST_BIT0_INT_ST (BIT(... | 2,152 |
*/
#define HOST_SLCHOST_STATE3 0x000000FF
#define HOST_SLCHOST_STATE3_M ((HOST_SLCHOST_STATE3_V)<<(HOST_SLCHOST_STATE3_S))
#define HOST_SLCHOST_STATE3_V 0xFF
#define HOST_SLCHOST_STATE3_S 24
/* HOST_SLCHOST_STATE2 : RO ;bitpos:[23:16] ;default: 8'h0 ; */
/*description: .*/
#define HOST_SLCHOST_STATE2 0x000000F... | 2,152 |
*/
#define HOST_SLCHOST_STATE7 0x000000FF
#define HOST_SLCHOST_STATE7_M ((HOST_SLCHOST_STATE7_V)<<(HOST_SLCHOST_STATE7_S))
#define HOST_SLCHOST_STATE7_V 0xFF
#define HOST_SLCHOST_STATE7_S 24
/* HOST_SLCHOST_STATE6 : RO ;bitpos:[23:16] ;default: 8'h0 ; */
/*description: .*/
#define HOST_SLCHOST_STATE6 0x000000F... | 2,152 |
*/
#define HOST_SLCHOST_CONF3 0x000000FF
#define HOST_SLCHOST_CONF3_M ((HOST_SLCHOST_CONF3_V)<<(HOST_SLCHOST_CONF3_S))
#define HOST_SLCHOST_CONF3_V 0xFF
#define HOST_SLCHOST_CONF3_S 24
/* HOST_SLCHOST_CONF2 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
/*description: .*/
#define HOST_SLCHOST_CONF2 0x000000FF
#defi... | 2,152 |
*/
#define HOST_SLCHOST_CONF7 0x000000FF
#define HOST_SLCHOST_CONF7_M ((HOST_SLCHOST_CONF7_V)<<(HOST_SLCHOST_CONF7_S))
#define HOST_SLCHOST_CONF7_V 0xFF
#define HOST_SLCHOST_CONF7_S 24
/* HOST_SLCHOST_CONF6 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
/*description: .*/
#define HOST_SLCHOST_CONF6 0x000000FF
#defi... | 2,152 |
*/
#define HOST_SLCHOST_CONF11 0x000000FF
#define HOST_SLCHOST_CONF11_M ((HOST_SLCHOST_CONF11_V)<<(HOST_SLCHOST_CONF11_S))
#define HOST_SLCHOST_CONF11_V 0xFF
#define HOST_SLCHOST_CONF11_S 24
/* HOST_SLCHOST_CONF10 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
/*description: .*/
#define HOST_SLCHOST_CONF10 0x000000... | 2,152 |
*/
#define HOST_SLCHOST_CONF15 0x000000FF
#define HOST_SLCHOST_CONF15_M ((HOST_SLCHOST_CONF15_V)<<(HOST_SLCHOST_CONF15_S))
#define HOST_SLCHOST_CONF15_V 0xFF
#define HOST_SLCHOST_CONF15_S 24
/* HOST_SLCHOST_CONF14 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
/*description: .*/
#define HOST_SLCHOST_CONF14 0x000000... | 2,152 |
*/
#define HOST_SLCHOST_CONF19 0x000000FF
#define HOST_SLCHOST_CONF19_M ((HOST_SLCHOST_CONF19_V)<<(HOST_SLCHOST_CONF19_S))
#define HOST_SLCHOST_CONF19_V 0xFF
#define HOST_SLCHOST_CONF19_S 24
/* HOST_SLCHOST_CONF18 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
/*description: .*/
#define HOST_SLCHOST_CONF18 0x000000... | 2,152 |
*/
#define HOST_SLCHOST_CONF23 0x000000FF
#define HOST_SLCHOST_CONF23_M ((HOST_SLCHOST_CONF23_V)<<(HOST_SLCHOST_CONF23_S))
#define HOST_SLCHOST_CONF23_V 0xFF
#define HOST_SLCHOST_CONF23_S 24
/* HOST_SLCHOST_CONF22 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
/*description: .*/
#define HOST_SLCHOST_CONF22 0x000000... | 2,152 |
*/
#define HOST_SLCHOST_WIN_CMD 0x0000FFFF
#define HOST_SLCHOST_WIN_CMD_M ((HOST_SLCHOST_WIN_CMD_V)<<(HOST_SLCHOST_WIN_CMD_S))
#define HOST_SLCHOST_WIN_CMD_V 0xFFFF
#define HOST_SLCHOST_WIN_CMD_S 0
#define HOST_SLCHOST_CONF_W6_REG (DR_REG_SLCHOST_BASE + 0x88)
/* HOST_SLCHOST_CONF27 : R/W ;bitpos:[31:24]... | 2,152 |
*/
#define HOST_SLCHOST_CONF24 0x000000FF
#define HOST_SLCHOST_CONF24_M ((HOST_SLCHOST_CONF24_V)<<(HOST_SLCHOST_CONF24_S))
#define HOST_SLCHOST_CONF24_V 0xFF
#define HOST_SLCHOST_CONF24_S 0
#define HOST_SLCHOST_CONF_W7_REG (DR_REG_SLCHOST_BASE + 0x8C)
/* HOST_SLCHOST_CONF31 : R/W ;bitpos:[31:24] ;defaul... | 2,152 |
*/
#define HOST_SLCHOST_CONF28 0x000000FF
#define HOST_SLCHOST_CONF28_M ((HOST_SLCHOST_CONF28_V)<<(HOST_SLCHOST_CONF28_S))
#define HOST_SLCHOST_CONF28_V 0xFF
#define HOST_SLCHOST_CONF28_S 0
#define HOST_SLCHOST_PKT_LEN0_REG (DR_REG_SLCHOST_BASE + 0x90)
/* HOST_HOSTSLC0_LEN0_CHECK : RO ;bitpos:[31:20] ;d... | 2,152 |
*/
#define HOST_HOSTSLC0_LEN1_CHECK 0x00000FFF
#define HOST_HOSTSLC0_LEN1_CHECK_M ((HOST_HOSTSLC0_LEN1_CHECK_V)<<(HOST_HOSTSLC0_LEN1_CHECK_S))
#define HOST_HOSTSLC0_LEN1_CHECK_V 0xFFF
#define HOST_HOSTSLC0_LEN1_CHECK_S 20
/* HOST_HOSTSLC0_LEN1 : RO ;bitpos:[19:0] ;default: 20'h0 ; */
/*description: .*/
#define HO... | 2,152 |
*/
#define HOST_SLCHOST_CONF35 0x000000FF
#define HOST_SLCHOST_CONF35_M ((HOST_SLCHOST_CONF35_V)<<(HOST_SLCHOST_CONF35_S))
#define HOST_SLCHOST_CONF35_V 0xFF
#define HOST_SLCHOST_CONF35_S 24
/* HOST_SLCHOST_CONF34 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
/*description: .*/
#define HOST_SLCHOST_CONF34 0x000000... | 2,152 |
*/
#define HOST_SLCHOST_CONF39 0x000000FF
#define HOST_SLCHOST_CONF39_M ((HOST_SLCHOST_CONF39_V)<<(HOST_SLCHOST_CONF39_S))
#define HOST_SLCHOST_CONF39_V 0xFF
#define HOST_SLCHOST_CONF39_S 24
/* HOST_SLCHOST_CONF38 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
/*description: .*/
#define HOST_SLCHOST_CONF38 0x000000... | 2,152 |
*/
#define HOST_SLCHOST_CONF43 0x000000FF
#define HOST_SLCHOST_CONF43_M ((HOST_SLCHOST_CONF43_V)<<(HOST_SLCHOST_CONF43_S))
#define HOST_SLCHOST_CONF43_V 0xFF
#define HOST_SLCHOST_CONF43_S 24
/* HOST_SLCHOST_CONF42 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
/*description: .*/
#define HOST_SLCHOST_CONF42 0x000000... | 2,152 |
*/
#define HOST_SLCHOST_CONF47 0x000000FF
#define HOST_SLCHOST_CONF47_M ((HOST_SLCHOST_CONF47_V)<<(HOST_SLCHOST_CONF47_S))
#define HOST_SLCHOST_CONF47_V 0xFF
#define HOST_SLCHOST_CONF47_S 24
/* HOST_SLCHOST_CONF46 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
/*description: .*/
#define HOST_SLCHOST_CONF46 0x000000... | 2,152 |
*/
#define HOST_SLCHOST_CONF51 0x000000FF
#define HOST_SLCHOST_CONF51_M ((HOST_SLCHOST_CONF51_V)<<(HOST_SLCHOST_CONF51_S))
#define HOST_SLCHOST_CONF51_V 0xFF
#define HOST_SLCHOST_CONF51_S 24
/* HOST_SLCHOST_CONF50 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
/*description: .*/
#define HOST_SLCHOST_CONF50 0x000000... | 2,152 |
*/
#define HOST_SLCHOST_CONF55 0x000000FF
#define HOST_SLCHOST_CONF55_M ((HOST_SLCHOST_CONF55_V)<<(HOST_SLCHOST_CONF55_S))
#define HOST_SLCHOST_CONF55_V 0xFF
#define HOST_SLCHOST_CONF55_S 24
/* HOST_SLCHOST_CONF54 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
/*description: .*/
#define HOST_SLCHOST_CONF54 0x000000... | 2,152 |
*/
#define HOST_SLCHOST_CONF59 0x000000FF
#define HOST_SLCHOST_CONF59_M ((HOST_SLCHOST_CONF59_V)<<(HOST_SLCHOST_CONF59_S))
#define HOST_SLCHOST_CONF59_V 0xFF
#define HOST_SLCHOST_CONF59_S 24
/* HOST_SLCHOST_CONF58 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
/*description: .*/
#define HOST_SLCHOST_CONF58 0x000000... | 2,152 |
*/
#define HOST_SLCHOST_CONF63 0x000000FF
#define HOST_SLCHOST_CONF63_M ((HOST_SLCHOST_CONF63_V)<<(HOST_SLCHOST_CONF63_S))
#define HOST_SLCHOST_CONF63_V 0xFF
#define HOST_SLCHOST_CONF63_S 24
/* HOST_SLCHOST_CONF62 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
/*description: .*/
#define HOST_SLCHOST_CONF62 0x000000... | 2,152 |
*/
#define HOST_SLCHOST_CHECK_SUM0 0xFFFFFFFF
#define HOST_SLCHOST_CHECK_SUM0_M ((HOST_SLCHOST_CHECK_SUM0_V)<<(HOST_SLCHOST_CHECK_SUM0_S))
#define HOST_SLCHOST_CHECK_SUM0_V 0xFFFFFFFF
#define HOST_SLCHOST_CHECK_SUM0_S 0
#define HOST_SLCHOST_CHECK_SUM1_REG (DR_REG_SLCHOST_BASE + 0xC0)
/* HOST_SLCHOST_CHE... | 2,152 |
*/
#define HOST_SLC0HOST_TOKEN0_WD 0x00000FFF
#define HOST_SLC0HOST_TOKEN0_WD_M ((HOST_SLC0HOST_TOKEN0_WD_V)<<(HOST_SLC0HOST_TOKEN0_WD_S))
#define HOST_SLC0HOST_TOKEN0_WD_V 0xFFF
#define HOST_SLC0HOST_TOKEN0_WD_S 0
#define HOST_SLCHOST_TOKEN_CON_REG (DR_REG_SLCHOST_BASE + 0xD0)
/* HOST_SLC0HOST_LEN_WR :... | 2,152 |
*/
#define HOST_SLC0HOST_TOKEN1_DEC (BIT(1))
#define HOST_SLC0HOST_TOKEN1_DEC_M (BIT(1))
#define HOST_SLC0HOST_TOKEN1_DEC_V 0x1
#define HOST_SLC0HOST_TOKEN1_DEC_S 1
/* HOST_SLC0HOST_TOKEN0_DEC : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0HOST_TOKEN0_DEC (BIT(0))
#define HOST_SLC0HOS... | 2,152 |
*/
#define HOST_SLC0_RX_NEW_PACKET_INT_CLR (BIT(23))
#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_M (BIT(23))
#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_V 0x1
#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_S 23
/* HOST_SLC0_EXT_BIT3_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_EXT_BIT3_INT_... | 2,152 |
*/
#define HOST_SLC0_EXT_BIT0_INT_CLR (BIT(19))
#define HOST_SLC0_EXT_BIT0_INT_CLR_M (BIT(19))
#define HOST_SLC0_EXT_BIT0_INT_CLR_V 0x1
#define HOST_SLC0_EXT_BIT0_INT_CLR_S 19
/* HOST_SLC0_RX_PF_VALID_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_RX_PF_VALID_INT_CLR (BIT(18... | 2,152 |
*/
#define HOST_SLC0HOST_TX_START_INT_CLR (BIT(15))
#define HOST_SLC0HOST_TX_START_INT_CLR_M (BIT(15))
#define HOST_SLC0HOST_TX_START_INT_CLR_V 0x1
#define HOST_SLC0HOST_TX_START_INT_CLR_S 15
/* HOST_SLC0HOST_RX_START_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0HOST_RX_START_... | 2,152 |
*/
#define HOST_SLC0_TOKEN1_0TO1_INT_CLR (BIT(11))
#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_M (BIT(11))
#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_V 0x1
#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_S 11
/* HOST_SLC0_TOKEN0_0TO1_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_TOKEN0_0TO1_INT_CL... | 2,152 |
*/
#define HOST_SLC0_TOHOST_BIT7_INT_CLR (BIT(7))
#define HOST_SLC0_TOHOST_BIT7_INT_CLR_M (BIT(7))
#define HOST_SLC0_TOHOST_BIT7_INT_CLR_V 0x1
#define HOST_SLC0_TOHOST_BIT7_INT_CLR_S 7
/* HOST_SLC0_TOHOST_BIT6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_TOHOST_BIT6_INT_CLR ... | 2,152 |
*/
#define HOST_SLC0_TOHOST_BIT3_INT_CLR (BIT(3))
#define HOST_SLC0_TOHOST_BIT3_INT_CLR_M (BIT(3))
#define HOST_SLC0_TOHOST_BIT3_INT_CLR_V 0x1
#define HOST_SLC0_TOHOST_BIT3_INT_CLR_S 3
/* HOST_SLC0_TOHOST_BIT2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_TOHOST_BIT2_INT_CLR ... | 2,152 |
*/
#define HOST_FN1_GPIO_SDIO_INT_ENA (BIT(25))
#define HOST_FN1_GPIO_SDIO_INT_ENA_M (BIT(25))
#define HOST_FN1_GPIO_SDIO_INT_ENA_V 0x1
#define HOST_FN1_GPIO_SDIO_INT_ENA_S 25
/* HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: .*/
#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_E... | 2,152 |
*/
#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA (BIT(21))
#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_M (BIT(21))
#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_V 0x1
#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_S 21
/* HOST_FN1_SLC0_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: .*/
#define HOST_FN1_SLC0_EXT_BIT1... | 2,152 |
*/
#define HOST_FN1_SLC0_TX_OVF_INT_ENA (BIT(17))
#define HOST_FN1_SLC0_TX_OVF_INT_ENA_M (BIT(17))
#define HOST_FN1_SLC0_TX_OVF_INT_ENA_V 0x1
#define HOST_FN1_SLC0_TX_OVF_INT_ENA_S 17
/* HOST_FN1_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: .*/
#define HOST_FN1_SLC0_RX_UDF_INT_ENA ... | 2,152 |
*/
#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA (BIT(13))
#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_M (BIT(13))
#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V 0x1
#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S 13
/* HOST_FN1_SLC0HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: .*/
#define HOST_FN1_SLC... | 2,152 |
*/
#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9))
#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_M (BIT(9))
#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V 0x1
#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S 9
/* HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: .*/
#define HOST_FN1_SL... | 2,152 |
*/
#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA (BIT(5))
#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_M (BIT(5))
#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V 0x1
#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S 5
/* HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: .*/
#define HOST_FN1_SL... | 2,152 |
*/
#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA (BIT(1))
#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_M (BIT(1))
#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V 0x1
#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S 1
/* HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define HOST_FN1_SL... | 2,152 |
*/
#define HOST_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23))
#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_M (BIT(23))
#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_V 0x1
#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_S 23
/* HOST_SLC0_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_EXT_BIT3_INT... | 2,152 |
*/
#define HOST_SLC0_EXT_BIT0_INT_ENA (BIT(19))
#define HOST_SLC0_EXT_BIT0_INT_ENA_M (BIT(19))
#define HOST_SLC0_EXT_BIT0_INT_ENA_V 0x1
#define HOST_SLC0_EXT_BIT0_INT_ENA_S 19
/* HOST_SLC0_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_RX_PF_VALID_INT_ENA (BIT(1... | 2,152 |
*/
#define HOST_SLC0HOST_TX_START_INT_ENA (BIT(15))
#define HOST_SLC0HOST_TX_START_INT_ENA_M (BIT(15))
#define HOST_SLC0HOST_TX_START_INT_ENA_V 0x1
#define HOST_SLC0HOST_TX_START_INT_ENA_S 15
/* HOST_SLC0HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0HOST_RX_START... | 2,152 |
*/
#define HOST_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11))
#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_M (BIT(11))
#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_V 0x1
#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_S 11
/* HOST_SLC0_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_TOKEN0_0TO1_INT_E... | 2,152 |
*/
#define HOST_SLC0_TOHOST_BIT7_INT_ENA (BIT(7))
#define HOST_SLC0_TOHOST_BIT7_INT_ENA_M (BIT(7))
#define HOST_SLC0_TOHOST_BIT7_INT_ENA_V 0x1
#define HOST_SLC0_TOHOST_BIT7_INT_ENA_S 7
/* HOST_SLC0_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_TOHOST_BIT6_INT_ENA ... | 2,152 |
*/
#define HOST_SLC0_TOHOST_BIT3_INT_ENA (BIT(3))
#define HOST_SLC0_TOHOST_BIT3_INT_ENA_M (BIT(3))
#define HOST_SLC0_TOHOST_BIT3_INT_ENA_V 0x1
#define HOST_SLC0_TOHOST_BIT3_INT_ENA_S 3
/* HOST_SLC0_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_TOHOST_BIT2_INT_ENA ... | 2,152 |
*/
#define HOST_SLC0HOST_RX_INFOR 0x000FFFFF
#define HOST_SLC0HOST_RX_INFOR_M ((HOST_SLC0HOST_RX_INFOR_V)<<(HOST_SLC0HOST_RX_INFOR_S))
#define HOST_SLC0HOST_RX_INFOR_V 0xFFFFF
#define HOST_SLC0HOST_RX_INFOR_S 0
#define HOST_SLC0HOST_LEN_WD_REG (DR_REG_SLCHOST_BASE + 0xFC)
/* HOST_SLC0HOST_LEN_WD : R/W ;... | 2,152 |
*/
#define HOST_SLC_APBWIN_BUS (BIT(30))
#define HOST_SLC_APBWIN_BUS_M (BIT(30))
#define HOST_SLC_APBWIN_BUS_V 0x1
#define HOST_SLC_APBWIN_BUS_S 30
/* HOST_SLC_APBWIN_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC_APBWIN_START (BIT(29))
#define HOST_SLC_APBWIN_START_M (BIT(29... | 2,152 |
*/
#define HOST_SLC_APBWIN_RDATA 0xFFFFFFFF
#define HOST_SLC_APBWIN_RDATA_M ((HOST_SLC_APBWIN_RDATA_V)<<(HOST_SLC_APBWIN_RDATA_S))
#define HOST_SLC_APBWIN_RDATA_V 0xFFFFFFFF
#define HOST_SLC_APBWIN_RDATA_S 0
#define HOST_SLCHOST_RDCLR0_REG (DR_REG_SLCHOST_BASE + 0x10C)
/* HOST_SLCHOST_SLC0_BIT6_CLRADDR ... | 2,152 |
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