text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
*/
#define SPI_SLV_CMDA_INT_ST (BIT(15))
#define SPI_SLV_CMDA_INT_ST_M (BIT(15))
#define SPI_SLV_CMDA_INT_ST_V 0x1
#define SPI_SLV_CMDA_INT_ST_S 15
/* SPI_SLV_CMD9_INT_ST : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: The status bit for SPI slave CMD9 interrupt.*/
#define SPI_SLV_CMD9_INT_ST (BIT(14))
#defi... | 2,180 |
*/
#define SPI_SLV_CMD6_INT_ST (BIT(11))
#define SPI_SLV_CMD6_INT_ST_M (BIT(11))
#define SPI_SLV_CMD6_INT_ST_V 0x1
#define SPI_SLV_CMD6_INT_ST_S 11
/* SPI_OUTFIFO_EMPTY_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: The status bit for outfifo empty error.*/
#define SPI_OUTFIFO_EMPTY_ERR_INT_ST (BI... | 2,180 |
*/
#define SPI_OUT_EOF_INT_ST (BIT(7))
#define SPI_OUT_EOF_INT_ST_M (BIT(7))
#define SPI_OUT_EOF_INT_ST_V 0x1
#define SPI_OUT_EOF_INT_ST_S 7
/* SPI_OUT_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The status bit for completing usage of a outlink descriptor.*/
#define SPI_OUT_DONE_INT_ST (BIT(6))... | 2,180 |
*/
#define SPI_IN_DONE_INT_ST (BIT(3))
#define SPI_IN_DONE_INT_ST_M (BIT(3))
#define SPI_IN_DONE_INT_ST_V 0x1
#define SPI_IN_DONE_INT_ST_S 3
/* SPI_INLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: The status bit for inlink descriptor error.*/
#define SPI_INLINK_DSCR_ERROR_INT_ST (BIT(2)... | 2,180 |
*/
#define SPI_SLV_CMDA_INT_CLR (BIT(15))
#define SPI_SLV_CMDA_INT_CLR_M (BIT(15))
#define SPI_SLV_CMDA_INT_CLR_V 0x1
#define SPI_SLV_CMDA_INT_CLR_S 15
/* SPI_SLV_CMD9_INT_CLR : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: The clear bit for SPI slave CMD9 interrupt.*/
#define SPI_SLV_CMD9_INT_CLR (BIT(14))
... | 2,180 |
*/
#define SPI_SLV_CMD6_INT_CLR (BIT(11))
#define SPI_SLV_CMD6_INT_CLR_M (BIT(11))
#define SPI_SLV_CMD6_INT_CLR_V 0x1
#define SPI_SLV_CMD6_INT_CLR_S 11
/* SPI_OUTFIFO_EMPTY_ERR_INT_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: 1: Clear spi_dma_outfifo_empty_err signal. 0: not valid. Can
be changed by C... | 2,180 |
*/
#define SPI_OUT_TOTAL_EOF_INT_CLR (BIT(8))
#define SPI_OUT_TOTAL_EOF_INT_CLR_M (BIT(8))
#define SPI_OUT_TOTAL_EOF_INT_CLR_V 0x1
#define SPI_OUT_TOTAL_EOF_INT_CLR_S 8
/* SPI_OUT_EOF_INT_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: The clear bit for sending a packet to host done. Can be configured
in ... | 2,180 |
Can be configured in CONF state.*/
#define SPI_IN_ERR_EOF_INT_CLR (BIT(4))
#define SPI_IN_ERR_EOF_INT_CLR_M (BIT(4))
#define SPI_IN_ERR_EOF_INT_CLR_V 0x1
#define SPI_IN_ERR_EOF_INT_CLR_S 4
/* SPI_IN_DONE_INT_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: The clear bit for completing usage of a inlink des... | 2,180 |
*/
#define SPI_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1))
#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_M (BIT(1))
#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_V 0x1
#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_S 1
/* SPI_INLINK_DSCR_EMPTY_INT_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The clear bit for lack of enough inlink d... | 2,180 |
*/
#define SPI_DMA_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF
#define SPI_DMA_IN_SUC_EOF_DES_ADDR_M ((SPI_DMA_IN_SUC_EOF_DES_ADDR_V)<<(SPI_DMA_IN_SUC_EOF_DES_ADDR_S))
#define SPI_DMA_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF
#define SPI_DMA_IN_SUC_EOF_DES_ADDR_S 0
#define SPI_INLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x070)
/* SP... | 2,180 |
*/
#define SPI_DMA_INLINK_DSCR_BF1 0xFFFFFFFF
#define SPI_DMA_INLINK_DSCR_BF1_M ((SPI_DMA_INLINK_DSCR_BF1_V)<<(SPI_DMA_INLINK_DSCR_BF1_S))
#define SPI_DMA_INLINK_DSCR_BF1_V 0xFFFFFFFF
#define SPI_DMA_INLINK_DSCR_BF1_S 0
#define SPI_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x07C)
/* SPI_DMA_OUT_EOF_B... | 2,180 |
*/
#define SPI_DMA_OUTLINK_DSCR 0xFFFFFFFF
#define SPI_DMA_OUTLINK_DSCR_M ((SPI_DMA_OUTLINK_DSCR_V)<<(SPI_DMA_OUTLINK_DSCR_S))
#define SPI_DMA_OUTLINK_DSCR_V 0xFFFFFFFF
#define SPI_DMA_OUTLINK_DSCR_S 0
#define SPI_OUTLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x088)
/* SPI_DMA_OUTLINK_DSCR_BF0 : RO ;bitpos:[... | 2,180 |
*/
#define SPI_DMA_OUTFIFO_EMPTY (BIT(31))
#define SPI_DMA_OUTFIFO_EMPTY_M (BIT(31))
#define SPI_DMA_OUTFIFO_EMPTY_V 0x1
#define SPI_DMA_OUTFIFO_EMPTY_S 31
/* SPI_DMA_OUTFIFO_FULL : RO ;bitpos:[30] ;default: 1'b0 ; */
/*description: SPI dma outfifo is full.*/
#define SPI_DMA_OUTFIFO_FULL (BIT(30))
#define SPI_DMA_... | 2,180 |
*/
#define SPI_DMA_OUTDSCR_STATE 0x00000003
#define SPI_DMA_OUTDSCR_STATE_M ((SPI_DMA_OUTDSCR_STATE_V)<<(SPI_DMA_OUTDSCR_STATE_S))
#define SPI_DMA_OUTDSCR_STATE_V 0x3
#define SPI_DMA_OUTDSCR_STATE_S 18
/* SPI_DMA_OUTDSCR_ADDR : RO ;bitpos:[17:0] ;default: 18'b0 ; */
/*description: SPI dma out descriptor address.*/
... | 2,180 |
*/
#define SPI_DMA_INFIFO_CNT 0x0000007F
#define SPI_DMA_INFIFO_CNT_M ((SPI_DMA_INFIFO_CNT_V)<<(SPI_DMA_INFIFO_CNT_S))
#define SPI_DMA_INFIFO_CNT_V 0x7F
#define SPI_DMA_INFIFO_CNT_S 23
/* SPI_DMA_IN_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */
/*description: SPI dma in data state.*/
#define SPI_DMA_IN_STATE 0x00... | 2,180 |
v. 0: disable it. Can be configured in CONF state.*/
#define SPI_TIMING_CLK_ENA (BIT(24))
#define SPI_TIMING_CLK_ENA_M (BIT(24))
#define SPI_TIMING_CLK_ENA_V 0x1
#define SPI_TIMING_CLK_ENA_S 24
/* SPI_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
/*description: the input signals are delayed by system clock c... | 2,180 |
Can be configured in CONF state.*/
#define SPI_DIN5_MODE 0x00000007
#define SPI_DIN5_MODE_M ((SPI_DIN5_MODE_V)<<(SPI_DIN5_MODE_S))
#define SPI_DIN5_MODE_V 0x7
#define SPI_DIN5_MODE_S 15
/* SPI_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
/*description: the input signals are delayed by system clock cycles 0... | 2,180 |
Can be configured in CONF state.*/
#define SPI_DIN2_MODE 0x00000007
#define SPI_DIN2_MODE_M ((SPI_DIN2_MODE_V)<<(SPI_DIN2_MODE_S))
#define SPI_DIN2_MODE_V 0x7
#define SPI_DIN2_MODE_S 6
/* SPI_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
/*description: the input signals are delayed by system clock cycles 0: i... | 2,180 |
.. Can be configured in CONF state.*/
#define SPI_DIN7_NUM 0x00000003
#define SPI_DIN7_NUM_M ((SPI_DIN7_NUM_V)<<(SPI_DIN7_NUM_S))
#define SPI_DIN7_NUM_V 0x3
#define SPI_DIN7_NUM_S 14
/* SPI_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
/*description: the input signals are delayed by system clock cycles 0: de... | 2,180 |
.. Can be configured in CONF state.*/
#define SPI_DIN4_NUM 0x00000003
#define SPI_DIN4_NUM_M ((SPI_DIN4_NUM_V)<<(SPI_DIN4_NUM_S))
#define SPI_DIN4_NUM_V 0x3
#define SPI_DIN4_NUM_S 8
/* SPI_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
/*description: the input signals are delayed by system clock cycles 0: delay... | 2,180 |
.. Can be configured in CONF state.*/
#define SPI_DIN1_NUM 0x00000003
#define SPI_DIN1_NUM_M ((SPI_DIN1_NUM_V)<<(SPI_DIN1_NUM_S))
#define SPI_DIN1_NUM_V 0x3
#define SPI_DIN1_NUM_S 2
/* SPI_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
/*description: the input signals are delayed by system clock cycles 0: delay... | 2,180 |
Can be configured in CONF state.*/
#define SPI_DOUT6_MODE 0x00000007
#define SPI_DOUT6_MODE_M ((SPI_DOUT6_MODE_V)<<(SPI_DOUT6_MODE_S))
#define SPI_DOUT6_MODE_V 0x7
#define SPI_DOUT6_MODE_S 18
/* SPI_DOUT5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
/*description: the output signals are delayed by system clock c... | 2,180 |
Can be configured in CONF state.*/
#define SPI_DOUT3_MODE 0x00000007
#define SPI_DOUT3_MODE_M ((SPI_DOUT3_MODE_V)<<(SPI_DOUT3_MODE_S))
#define SPI_DOUT3_MODE_V 0x7
#define SPI_DOUT3_MODE_S 9
/* SPI_DOUT2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
/*description: the output signals are delayed by system clock cycl... | 2,180 |
Can be configured in CONF state.*/
#define SPI_DOUT0_MODE 0x00000007
#define SPI_DOUT0_MODE_M ((SPI_DOUT0_MODE_V)<<(SPI_DOUT0_MODE_S))
#define SPI_DOUT0_MODE_V 0x7
#define SPI_DOUT0_MODE_S 0
#define SPI_DOUT_NUM_REG(i) (REG_SPI_BASE(i) + 0x0EC)
/* SPI_DOUT7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
/... | 2,180 |
.. Can be configured in CONF state.*/
#define SPI_DOUT5_NUM 0x00000003
#define SPI_DOUT5_NUM_M ((SPI_DOUT5_NUM_V)<<(SPI_DOUT5_NUM_S))
#define SPI_DOUT5_NUM_V 0x3
#define SPI_DOUT5_NUM_S 10
/* SPI_DOUT4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
/*description: the output signals are delayed by system clock cycles ... | 2,180 |
.. Can be configured in CONF state.*/
#define SPI_DOUT2_NUM 0x00000003
#define SPI_DOUT2_NUM_M ((SPI_DOUT2_NUM_V)<<(SPI_DOUT2_NUM_S))
#define SPI_DOUT2_NUM_V 0x3
#define SPI_DOUT2_NUM_S 4
/* SPI_DOUT1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
/*description: the output signals are delayed by system clock cycles 0... | 2,180 |
0: Disable. Can be
configured in CONF state.*/
#define SPI_LCD_MODE_EN (BIT(31))
#define SPI_LCD_MODE_EN_M (BIT(31))
#define SPI_LCD_MODE_EN_V 0x1
#define SPI_LCD_MODE_EN_S 31
/* SPI_LCD_VT_HEIGHT : R/W ;bitpos:[30:21] ;default: 10'd0 ; */
/*description: It is the vertical total height of a frame. Can be configur... | 2,180 |
*/
#define SPI_LCD_HB_FRONT 0x000007FF
#define SPI_LCD_HB_FRONT_M ((SPI_LCD_HB_FRONT_V)<<(SPI_LCD_HB_FRONT_S))
#define SPI_LCD_HB_FRONT_V 0x7FF
#define SPI_LCD_HB_FRONT_S 0
#define SPI_LCD_CTRL1_REG(i) (REG_SPI_BASE(i) + 0x0F4)
/* SPI_LCD_HT_WIDTH : R/W ;bitpos:[31:20] ;default: 12'd0 ; */
/*description: ... | 2,180 |
Can be configured
in CONF state.*/
#define SPI_LCD_VB_FRONT 0x000000FF
#define SPI_LCD_VB_FRONT_M ((SPI_LCD_VB_FRONT_V)<<(SPI_LCD_VB_FRONT_S))
#define SPI_LCD_VB_FRONT_V 0xFF
#define SPI_LCD_VB_FRONT_S 0
#define SPI_LCD_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x0F8)
/* SPI_LCD_HSYNC_POSITION : R/W ;bitpos:[31:2... | 2,180 |
Can be
configured in CONF state.*/
#define SPI_LCD_HSYNC_WIDTH 0x0000007F
#define SPI_LCD_HSYNC_WIDTH_M ((SPI_LCD_HSYNC_WIDTH_V)<<(SPI_LCD_HSYNC_WIDTH_S))
#define SPI_LCD_HSYNC_WIDTH_V 0x7F
#define SPI_LCD_HSYNC_WIDTH_S 16
/* SPI_VSYNC_IDLE_POL : R/W ;bitpos:[7] ;default: 1'd0 ; */
/*description: It is the idle v... | 2,180 |
0: spi_hsync pulse is valid only in active region lines in seg-trans.*/
#define SPI_HS_BLANK_EN (BIT(16))
#define SPI_HS_BLANK_EN_M (BIT(16))
#define SPI_HS_BLANK_EN_V 0x1
#define SPI_HS_BLANK_EN_S 16
/* SPI_DE_IDLE_POL : R/W ;bitpos:[15] ;default: 1'd0 ; */
/*description: It is the idle value of spi_de.*/
#define... | 2,180 |
Can be configured in CONF state.*/
#define SPI_D_HSYNC_MODE 0x00000007
#define SPI_D_HSYNC_MODE_M ((SPI_D_HSYNC_MODE_V)<<(SPI_D_HSYNC_MODE_S))
#define SPI_D_HSYNC_MODE_V 0x7
#define SPI_D_HSYNC_MODE_S 9
/* SPI_D_DE_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
/*description: the output spi_de is delayed by system c... | 2,180 |
Can be configured in CONF state.*/
#define SPI_D_DQS_MODE 0x00000007
#define SPI_D_DQS_MODE_M ((SPI_D_DQS_MODE_V)<<(SPI_D_DQS_MODE_S))
#define SPI_D_DQS_MODE_V 0x7
#define SPI_D_DQS_MODE_S 0
#define SPI_LCD_D_NUM_REG(i) (REG_SPI_BASE(i) + 0x100)
/* SPI_D_VSYNC_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
... | 2,180 |
.. Can be configured in CONF state.*/
#define SPI_D_DE_NUM 0x00000003
#define SPI_D_DE_NUM_M ((SPI_D_DE_NUM_V)<<(SPI_D_DE_NUM_S))
#define SPI_D_DE_NUM_V 0x3
#define SPI_D_DE_NUM_S 4
/* SPI_D_CD_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
/*description: the output spi_cd is delayed by system clock cycles 0: delayed... | 2,180 |
*/
#define SPI_DATE 0x0FFFFFFF
#define SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S))
#define SPI_DATE_V 0xFFFFFFF
#define SPI_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_SPI_REG_H_ */
| 2,180 |
/*
*/
#define DR_REG_SYSTEM_BASE 0x3f4c0000
#define DR_REG_SENSITIVE_BASE 0x3f4c1000
#define DR_REG_INTERRUPT_BASE 0x3f4c2000
#define DR_REG_DMA_COPY_BASE 0x3f4c3000
#define DR_REG_EXTMEM_BASE 0x61800000
#define DR_REG_MMU... | 2,181 |
/*
*/
#pragma once
#ifndef __ASSEMBLER__
#include
#include "esp_assert.h"
#endif
#include "esp_bit_defs.h"
#include "reg_base.h"
#define PRO_CPU_NUM (0)
#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3
#de... | 2,182 |
__ASSEMBLER__ */
//}}
#endif /* !ULP_RISCV_REGISTER_OPS */
//Periheral Clock {{
#define APB_CLK_FREQ_ROM ( 40*1000000 )
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency ... | 2,182 |
#define SOC_DIRAM_IRAM_LOW 0x40020000
#define SOC_DIRAM_IRAM_HIGH 0x40070000
#define SOC_DIRAM_DRAM_LOW 0x3FFB0000
#define SOC_DIRAM_DRAM_HIGH 0x40000000
#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET)
#define MAP_IRAM_TO_DRAM(addr) (ad... | 2,182 |
h
/
*/
//CPU0 Interrupt number reserved, not touch this.
#define ETS_WMAC_INUM 0
#define ETS_BT_HOST_INUM 1
#define ETS_WBB_INUM 4
#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
#define ETS_FRC1_INUM ... | 2,182 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of un_conf0 register
*/
typedef union {
struct {
/** filter_thres_un : R/W; bitpos: [9:0]; default: 16;
*/
uint32_t filter_thres_un: 10;
/** filter_en_un : R/W; bit... | 2,186 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct gpio_dev_s {
uint32_t bt_select; /**/
uint32_t out; /**/
uint32_t out_w1ts; /**/
uint32_t out_w1tc; ... | 2,188 |
/*
*/
// ESP32-S2 doesn't feature General DMA peripheral.
// We keep this file here only for consistency's sake.
| 2,190 |
/*
*/
#pragma once
#include "soc/interrupts.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PERIPH_LEDC_MODULE = 0,
PERIPH_UART0_MODULE,
PERIPH_UART1_MODULE,
PERIPH_USB_MODULE,
PERIPH_I2C0_MODULE,
PERIPH_I2C1_MODULE,
PERIPH_I2S0_MODULE,
PERIPH_TIMG0_MODULE,
PERIPH_TIMG1... | 2,191 |
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,193 |
It will be cleared
by hardware after lock operation done.*/
#define EXTMEM_PRO_DCACHE_LOCK_ENA (BIT(24))
#define EXTMEM_PRO_DCACHE_LOCK_ENA_M (BIT(24))
#define EXTMEM_PRO_DCACHE_LOCK_ENA_V 0x1
#define EXTMEM_PRO_DCACHE_LOCK_ENA_S 24
/* EXTMEM_PRO_DCACHE_UNLOCK_DONE : RO ;bitpos:[23] ;default: 1'b0 ; */
/*descript... | 2,193 |
*/
#define EXTMEM_PRO_DCACHE_PRELOAD_DONE (BIT(21))
#define EXTMEM_PRO_DCACHE_PRELOAD_DONE_M (BIT(21))
#define EXTMEM_PRO_DCACHE_PRELOAD_DONE_V 0x1
#define EXTMEM_PRO_DCACHE_PRELOAD_DONE_S 21
/* EXTMEM_PRO_DCACHE_PRELOAD_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: The bit is used to enable preload ope... | 2,193 |
It is combined with pre_dcache_autoload_done. 1: enable 0: disable.*/
#define EXTMEM_PRO_DCACHE_AUTOLOAD_ENA (BIT(18))
#define EXTMEM_PRO_DCACHE_AUTOLOAD_ENA_M (BIT(18))
#define EXTMEM_PRO_DCACHE_AUTOLOAD_ENA_V 0x1
#define EXTMEM_PRO_DCACHE_AUTOLOAD_ENA_S 18
/* EXTMEM_PRO_DCACHE_LOCK1_EN : R/W ;bitpos:[15] ;defa... | 2,193 |
*/
#define EXTMEM_PRO_DCACHE_CLEAN_DONE (BIT(13))
#define EXTMEM_PRO_DCACHE_CLEAN_DONE_M (BIT(13))
#define EXTMEM_PRO_DCACHE_CLEAN_DONE_V 0x1
#define EXTMEM_PRO_DCACHE_CLEAN_DONE_S 13
/* EXTMEM_PRO_DCACHE_CLEAN_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: The bit is used to enable clean operation. It w... | 2,193 |
It will be cleared
by hardware after flush operation done.*/
#define EXTMEM_PRO_DCACHE_FLUSH_ENA (BIT(10))
#define EXTMEM_PRO_DCACHE_FLUSH_ENA_M (BIT(10))
#define EXTMEM_PRO_DCACHE_FLUSH_ENA_V 0x1
#define EXTMEM_PRO_DCACHE_FLUSH_ENA_S 10
/* EXTMEM_PRO_DCACHE_INVALIDATE_DONE : RO ;bitpos:[9] ;default: 1'b0 ; */
/*... | 2,193 |
0: 16 bytes 1: 32 bytes*/
#define EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE (BIT(3))
#define EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE_M (BIT(3))
#define EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE_V 0x1
#define EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE_S 3
/* EXTMEM_PRO_DCACHE_SETSIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: The bit ... | 2,193 |
1:
close gating 0: open clock gating.*/
#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON (BIT(0))
#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON_M (BIT(0))
#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON_V 0x1
#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON_S 0
#define EXTMEM_PRO_DCACHE_LOCK0_ADDR_REG (DR_REG_EXTMEM_BASE ... | 2,193 |
The manual operations will be issued if the address is validate. The auto operations will be issued if the address is invalidate. It should be combined with PRO_DCACHE_MEM_SYNC1.*/
#define EXTMEM_PRO_DCACHE_MEMSYNC_ADDR 0xFFFFFFFF
#define EXTMEM_PRO_DCACHE_MEMSYNC_ADDR_M ((EXTMEM_PRO_DCACHE_MEMSYNC_ADDR_V)<<(EXTMEM_... | 2,193 |
It should be combined with PRO_DCACHE_PRELOAD_SIZE_REG.*/
#define EXTMEM_PRO_DCACHE_PRELOAD_ADDR 0xFFFFFFFF
#define EXTMEM_PRO_DCACHE_PRELOAD_ADDR_M ((EXTMEM_PRO_DCACHE_PRELOAD_ADDR_V)<<(EXTMEM_PRO_DCACHE_PRELOAD_ADDR_S))
#define EXTMEM_PRO_DCACHE_PRELOAD_ADDR_V 0xFFFFFFFF
#define EXTMEM_PRO_DCACHE_PRELOAD_ADDR_S ... | 2,193 |
.*/
#define EXTMEM_PRO_DCACHE_PRELOAD_SIZE 0x000003FF
#define EXTMEM_PRO_DCACHE_PRELOAD_SIZE_M ((EXTMEM_PRO_DCACHE_PRELOAD_SIZE_V)<<(EXTMEM_PRO_DCACHE_PRELOAD_SIZE_S))
#define EXTMEM_PRO_DCACHE_PRELOAD_SIZE_V 0x3FF
#define EXTMEM_PRO_DCACHE_PRELOAD_SIZE_S 0
#define EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_REG (DR_R... | 2,193 |
*/
#define EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE 0x00000003
#define EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_M ((EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_V)<<(EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_S))
#define EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_V 0x3
#define EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_S 6
/* EXTMEM_PRO_DCACHE_AUTOLOAD_RQST : R/W ;bitpos:[5:4] ... | 2,193 |
*/
#define EXTMEM_PRO_DCACHE_AUTOLOAD_STEP 0x00000003
#define EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_M ((EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_V)<<(EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_S))
#define EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_V 0x3
#define EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_S 1
/* EXTMEM_PRO_DCACHE_AUTOLOAD_MODE : R/W ;bitpos:[0] ;d... | 2,193 |
It should be combined with pro_dcache_autoload_sct0_ena.*/
#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE 0x00FFFFFF
#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_S))
#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_V 0xFFFFFF
#define EXTME... | 2,193 |
It should be combined with pro_dcache_autoload_sct1_ena.*/
#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE 0x00FFFFFF
#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_S))
#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_V 0xFFFFFF
#define EXTME... | 2,193 |
*/
#define EXTMEM_PRO_ICACHE_UNLOCK_DONE (BIT(23))
#define EXTMEM_PRO_ICACHE_UNLOCK_DONE_M (BIT(23))
#define EXTMEM_PRO_ICACHE_UNLOCK_DONE_V 0x1
#define EXTMEM_PRO_ICACHE_UNLOCK_DONE_S 23
/* EXTMEM_PRO_ICACHE_UNLOCK_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: The bit is used to enable unlock operation... | 2,193 |
It will be cleared
by hardware after preload operation done.*/
#define EXTMEM_PRO_ICACHE_PRELOAD_ENA (BIT(20))
#define EXTMEM_PRO_ICACHE_PRELOAD_ENA_M (BIT(20))
#define EXTMEM_PRO_ICACHE_PRELOAD_ENA_V 0x1
#define EXTMEM_PRO_ICACHE_PRELOAD_ENA_S 20
/* EXTMEM_PRO_ICACHE_AUTOLOAD_DONE : RO ;bitpos:[19] ;default: 1'b... | 2,193 |
*/
#define EXTMEM_PRO_ICACHE_LOCK1_EN (BIT(15))
#define EXTMEM_PRO_ICACHE_LOCK1_EN_M (BIT(15))
#define EXTMEM_PRO_ICACHE_LOCK1_EN_V 0x1
#define EXTMEM_PRO_ICACHE_LOCK1_EN_S 15
/* EXTMEM_PRO_ICACHE_LOCK0_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: The bit is used to enable pre-lock operation which is co... | 2,193 |
It will be cleared
by hardware after invalidate operation done.*/
#define EXTMEM_PRO_ICACHE_INVALIDATE_ENA (BIT(8))
#define EXTMEM_PRO_ICACHE_INVALIDATE_ENA_M (BIT(8))
#define EXTMEM_PRO_ICACHE_INVALIDATE_ENA_V 0x1
#define EXTMEM_PRO_ICACHE_INVALIDATE_ENA_S 8
/* EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE : R/W ;bitpos:[3] ... | 2,193 |
0: disable 1: enable*/
#define EXTMEM_PRO_ICACHE_ENABLE (BIT(0))
#define EXTMEM_PRO_ICACHE_ENABLE_M (BIT(0))
#define EXTMEM_PRO_ICACHE_ENABLE_V 0x1
#define EXTMEM_PRO_ICACHE_ENABLE_S 0
#define EXTMEM_PRO_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x044)
/* EXTMEM_PRO_ICACHE_MASK_BUS2 : R/W ;bitpos:[2] ;defa... | 2,193 |
1:
close gating 0: open clock gating.*/
#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON (BIT(0))
#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON_M (BIT(0))
#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON_V 0x1
#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON_S 0
#define EXTMEM_PRO_ICACHE_LOCK0_ADDR_REG (DR_REG_EXTMEM_BASE ... | 2,193 |
The manual operations will be issued if the address is validate. The auto operations will be issued if the address is invalidate. It should be combined with PRO_ICACHE_MEM_SYNC1.*/
#define EXTMEM_PRO_ICACHE_MEMSYNC_ADDR 0xFFFFFFFF
#define EXTMEM_PRO_ICACHE_MEMSYNC_ADDR_M ((EXTMEM_PRO_ICACHE_MEMSYNC_ADDR_V)<<(EXTMEM_... | 2,193 |
It should be combined with PRO_ICACHE_PRELOAD_SIZE_REG.*/
#define EXTMEM_PRO_ICACHE_PRELOAD_ADDR 0xFFFFFFFF
#define EXTMEM_PRO_ICACHE_PRELOAD_ADDR_M ((EXTMEM_PRO_ICACHE_PRELOAD_ADDR_V)<<(EXTMEM_PRO_ICACHE_PRELOAD_ADDR_S))
#define EXTMEM_PRO_ICACHE_PRELOAD_ADDR_V 0xFFFFFFFF
#define EXTMEM_PRO_ICACHE_PRELOAD_ADDR_S ... | 2,193 |
.*/
#define EXTMEM_PRO_ICACHE_PRELOAD_SIZE 0x000003FF
#define EXTMEM_PRO_ICACHE_PRELOAD_SIZE_M ((EXTMEM_PRO_ICACHE_PRELOAD_SIZE_V)<<(EXTMEM_PRO_ICACHE_PRELOAD_SIZE_S))
#define EXTMEM_PRO_ICACHE_PRELOAD_SIZE_V 0x3FF
#define EXTMEM_PRO_ICACHE_PRELOAD_SIZE_S 0
#define EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_REG (DR_R... | 2,193 |
*/
#define EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE 0x00000003
#define EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_M ((EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_V)<<(EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_S))
#define EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_V 0x3
#define EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_S 6
/* EXTMEM_PRO_ICACHE_AUTOLOAD_RQST : R/W ;bitpos:[5:4] ... | 2,193 |
*/
#define EXTMEM_PRO_ICACHE_AUTOLOAD_STEP 0x00000003
#define EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_M ((EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_V)<<(EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_S))
#define EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_V 0x3
#define EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_S 1
/* EXTMEM_PRO_ICACHE_AUTOLOAD_MODE : R/W ;bitpos:[0] ;d... | 2,193 |
It should be combined with pro_icache_autoload_sct0_ena.*/
#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE 0x00FFFFFF
#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_S))
#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_V 0xFFFFFF
#define EXTME... | 2,193 |
It should be combined with pro_icache_autoload_sct1_ena.*/
#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE 0x00FFFFFF
#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_S))
#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_V 0xFFFFFF
#define EXTME... | 2,193 |
*/
#define EXTMEM_IC_PRELOAD_MISS_CNT 0x0000FFFF
#define EXTMEM_IC_PRELOAD_MISS_CNT_M ((EXTMEM_IC_PRELOAD_MISS_CNT_V)<<(EXTMEM_IC_PRELOAD_MISS_CNT_S))
#define EXTMEM_IC_PRELOAD_MISS_CNT_V 0xFFFF
#define EXTMEM_IC_PRELOAD_MISS_CNT_S 0
#define EXTMEM_IBUS2_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0x088)
/* EXT... | 2,193 |
*/
#define EXTMEM_IBUS0_ABANDON_CNT 0x0000FFFF
#define EXTMEM_IBUS0_ABANDON_CNT_M ((EXTMEM_IBUS0_ABANDON_CNT_V)<<(EXTMEM_IBUS0_ABANDON_CNT_S))
#define EXTMEM_IBUS0_ABANDON_CNT_V 0xFFFF
#define EXTMEM_IBUS0_ABANDON_CNT_S 0
#define EXTMEM_IBUS2_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x094)
/* EXTMEM_IBUS2_A... | 2,193 |
*/
#define EXTMEM_IBUS0_ACS_MISS_CNT 0xFFFFFFFF
#define EXTMEM_IBUS0_ACS_MISS_CNT_M ((EXTMEM_IBUS0_ACS_MISS_CNT_V)<<(EXTMEM_IBUS0_ACS_MISS_CNT_S))
#define EXTMEM_IBUS0_ACS_MISS_CNT_V 0xFFFFFFFF
#define EXTMEM_IBUS0_ACS_MISS_CNT_S 0
#define EXTMEM_IBUS2_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0A0)
/* EXTMEM_IB... | 2,193 |
*/
#define EXTMEM_IBUS0_ACS_CNT 0xFFFFFFFF
#define EXTMEM_IBUS0_ACS_CNT_M ((EXTMEM_IBUS0_ACS_CNT_V)<<(EXTMEM_IBUS0_ACS_CNT_S))
#define EXTMEM_IBUS0_ACS_CNT_V 0xFFFFFFFF
#define EXTMEM_IBUS0_ACS_CNT_S 0
#define EXTMEM_DC_PRELOAD_CNT_REG (DR_REG_EXTMEM_BASE + 0x0AC)
/* EXTMEM_DC_PRELOAD_CNT : RO ;bitpos:[15... | 2,193 |
*/
#define EXTMEM_DC_PRELOAD_MISS_CNT 0x0000FFFF
#define EXTMEM_DC_PRELOAD_MISS_CNT_M ((EXTMEM_DC_PRELOAD_MISS_CNT_V)<<(EXTMEM_DC_PRELOAD_MISS_CNT_S))
#define EXTMEM_DC_PRELOAD_MISS_CNT_V 0xFFFF
#define EXTMEM_DC_PRELOAD_MISS_CNT_S 0
#define EXTMEM_DBUS2_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0x0B8)
/* EXT... | 2,193 |
*/
#define EXTMEM_DBUS0_ABANDON_CNT 0x0000FFFF
#define EXTMEM_DBUS0_ABANDON_CNT_M ((EXTMEM_DBUS0_ABANDON_CNT_V)<<(EXTMEM_DBUS0_ABANDON_CNT_S))
#define EXTMEM_DBUS0_ABANDON_CNT_V 0xFFFF
#define EXTMEM_DBUS0_ABANDON_CNT_S 0
#define EXTMEM_DBUS2_ACS_WB_CNT_REG (DR_REG_EXTMEM_BASE + 0x0C4)
/* EXTMEM_DBUS2_ACS... | 2,193 |
*/
#define EXTMEM_DBUS0_ACS_WB_CNT 0x000FFFFF
#define EXTMEM_DBUS0_ACS_WB_CNT_M ((EXTMEM_DBUS0_ACS_WB_CNT_V)<<(EXTMEM_DBUS0_ACS_WB_CNT_S))
#define EXTMEM_DBUS0_ACS_WB_CNT_V 0xFFFFF
#define EXTMEM_DBUS0_ACS_WB_CNT_S 0
#define EXTMEM_DBUS2_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0D0)
/* EXTMEM_DBUS2_ACS_MI... | 2,193 |
*/
#define EXTMEM_DBUS0_ACS_MISS_CNT 0xFFFFFFFF
#define EXTMEM_DBUS0_ACS_MISS_CNT_M ((EXTMEM_DBUS0_ACS_MISS_CNT_V)<<(EXTMEM_DBUS0_ACS_MISS_CNT_S))
#define EXTMEM_DBUS0_ACS_MISS_CNT_V 0xFFFFFFFF
#define EXTMEM_DBUS0_ACS_MISS_CNT_S 0
#define EXTMEM_DBUS2_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0DC)
/* EXTMEM_DB... | 2,193 |
*/
#define EXTMEM_DBUS0_ACS_CNT 0xFFFFFFFF
#define EXTMEM_DBUS0_ACS_CNT_M ((EXTMEM_DBUS0_ACS_CNT_V)<<(EXTMEM_DBUS0_ACS_CNT_S))
#define EXTMEM_DBUS0_ACS_CNT_V 0xFFFFFFFF
#define EXTMEM_DBUS0_ACS_CNT_S 0
#define EXTMEM_CACHE_DBG_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x0E8)
/* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/... | 2,193 |
*/
#define EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA (BIT(17))
#define EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA_M (BIT(17))
#define EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA_V 0x1
#define EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA_S 17
/* EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: The bit is us... | 2,193 |
*/
#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA (BIT(14))
#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_M (BIT(14))
#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_V 0x1
#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_S 14
/* EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: The bit is used to... | 2,193 |
*/
#define EXTMEM_DBUS_CNT_OVF_INT_ENA (BIT(11))
#define EXTMEM_DBUS_CNT_OVF_INT_ENA_M (BIT(11))
#define EXTMEM_DBUS_CNT_OVF_INT_ENA_V 0x1
#define EXTMEM_DBUS_CNT_OVF_INT_ENA_S 11
/* EXTMEM_DBUS_ACS_MSK_DC_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt by cpu acces... | 2,193 |
*/
#define EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA (BIT(8))
#define EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA_M (BIT(8))
#define EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA_V 0x1
#define EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA_S 8
/* EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: The bit is used t... | 2,193 |
*/
#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA (BIT(5))
#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA_M (BIT(5))
#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA_V 0x1
#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA_S 5
/* EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is us... | 2,193 |
*/
#define EXTMEM_IBUS_ACS_MSK_IC_INT_ENA (BIT(2))
#define EXTMEM_IBUS_ACS_MSK_IC_INT_ENA_M (BIT(2))
#define EXTMEM_IBUS_ACS_MSK_IC_INT_ENA_V 0x1
#define EXTMEM_IBUS_ACS_MSK_IC_INT_ENA_S 2
/* EXTMEM_CACHE_DBG_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: The bit is used to activate the cache track functio... | 2,193 |
*/
#define EXTMEM_DCACHE_SET_ILG_INT_CLR (BIT(12))
#define EXTMEM_DCACHE_SET_ILG_INT_CLR_M (BIT(12))
#define EXTMEM_DCACHE_SET_ILG_INT_CLR_V 0x1
#define EXTMEM_DCACHE_SET_ILG_INT_CLR_S 12
/* EXTMEM_DCACHE_REJECT_INT_CLR : WOD ;bitpos:[11] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt by auth... | 2,193 |
*/
#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR (BIT(9))
#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR_M (BIT(9))
#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR_V 0x1
#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR_S 9
/* EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR : WOD ;bitpos:[8] ;default: 1'b0 ; */
/*description: The bit is us... | 2,193 |
*/
#define EXTMEM_DBUS_ACS_MSK_DC_INT_CLR (BIT(6))
#define EXTMEM_DBUS_ACS_MSK_DC_INT_CLR_M (BIT(6))
#define EXTMEM_DBUS_ACS_MSK_DC_INT_CLR_V 0x1
#define EXTMEM_DBUS_ACS_MSK_DC_INT_CLR_S 6
/* EXTMEM_ICACHE_SET_ILG_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt by ill... | 2,193 |
*/
#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR (BIT(3))
#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR_M (BIT(3))
#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR_V 0x1
#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR_S 3
/* EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
/*description: The bit is us... | 2,193 |
*/
#define EXTMEM_IBUS_ACS_MSK_IC_INT_CLR (BIT(0))
#define EXTMEM_IBUS_ACS_MSK_IC_INT_CLR_M (BIT(0))
#define EXTMEM_IBUS_ACS_MSK_IC_INT_CLR_V 0x1
#define EXTMEM_IBUS_ACS_MSK_IC_INT_CLR_S 0
#define EXTMEM_CACHE_DBG_STATUS0_REG (DR_REG_EXTMEM_BASE + 0x0F0)
/* EXTMEM_ICACHE_SET_LOCK_ILG_ST : RO ;bitpos:[24] ... | 2,193 |
*/
#define EXTMEM_ICACHE_SET_PRELOAD_ILG_ST (BIT(22))
#define EXTMEM_ICACHE_SET_PRELOAD_ILG_ST_M (BIT(22))
#define EXTMEM_ICACHE_SET_PRELOAD_ILG_ST_V 0x1
#define EXTMEM_ICACHE_SET_PRELOAD_ILG_ST_S 22
/* EXTMEM_ICACHE_REJECT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrup... | 2,193 |
*/
#define EXTMEM_IC_SYNC_SIZE_FAULT_ST (BIT(19))
#define EXTMEM_IC_SYNC_SIZE_FAULT_ST_M (BIT(19))
#define EXTMEM_IC_SYNC_SIZE_FAULT_ST_V 0x1
#define EXTMEM_IC_SYNC_SIZE_FAULT_ST_S 19
/* EXTMEM_IC_PRELOAD_CNT_OVF_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by pre-lo... | 2,193 |
*/
#define EXTMEM_IBUS2_ABANDON_CNT_OVF_ST (BIT(14))
#define EXTMEM_IBUS2_ABANDON_CNT_OVF_ST_M (BIT(14))
#define EXTMEM_IBUS2_ABANDON_CNT_OVF_ST_V 0x1
#define EXTMEM_IBUS2_ABANDON_CNT_OVF_ST_S 14
/* EXTMEM_IBUS1_ABANDON_CNT_OVF_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
/*description: The bit is used to indicate inte... | 2,193 |
*/
#define EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST (BIT(10))
#define EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST_M (BIT(10))
#define EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST_V 0x1
#define EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST_S 10
/* EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: The bit is used to indicate ... | 2,193 |
*/
#define EXTMEM_IBUS2_ACS_CNT_OVF_ST (BIT(6))
#define EXTMEM_IBUS2_ACS_CNT_OVF_ST_M (BIT(6))
#define EXTMEM_IBUS2_ACS_CNT_OVF_ST_V 0x1
#define EXTMEM_IBUS2_ACS_CNT_OVF_ST_S 6
/* EXTMEM_IBUS1_ACS_CNT_OVF_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by ibus1 counter o... | 2,193 |
*/
#define EXTMEM_IBUS2_ACS_MSK_ICACHE_ST (BIT(2))
#define EXTMEM_IBUS2_ACS_MSK_ICACHE_ST_M (BIT(2))
#define EXTMEM_IBUS2_ACS_MSK_ICACHE_ST_V 0x1
#define EXTMEM_IBUS2_ACS_MSK_ICACHE_ST_S 2
/* EXTMEM_IBUS1_ACS_MSK_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by ... | 2,193 |
*/
#define EXTMEM_MMU_ENTRY_FAULT_ST (BIT(30))
#define EXTMEM_MMU_ENTRY_FAULT_ST_M (BIT(30))
#define EXTMEM_MMU_ENTRY_FAULT_ST_V 0x1
#define EXTMEM_MMU_ENTRY_FAULT_ST_S 30
/* EXTMEM_DCACHE_SET_LOCK_ILG_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by illegal writing l... | 2,193 |
*/
#define EXTMEM_DCACHE_SET_PRELOAD_ILG_ST (BIT(27))
#define EXTMEM_DCACHE_SET_PRELOAD_ILG_ST_M (BIT(27))
#define EXTMEM_DCACHE_SET_PRELOAD_ILG_ST_V 0x1
#define EXTMEM_DCACHE_SET_PRELOAD_ILG_ST_S 27
/* EXTMEM_DCACHE_REJECT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrup... | 2,193 |
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