text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
*/
#define HOST_GPIO_SDIO_INT_ENA1 (BIT(25))
#define HOST_GPIO_SDIO_INT_ENA1_M (BIT(25))
#define HOST_GPIO_SDIO_INT_ENA1_V 0x1
#define HOST_GPIO_SDIO_INT_ENA1_S 25
/* HOST_SLC0_HOST_RD_RETRY_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1 (BIT(24))
#d... | 2,152 |
*/
#define HOST_SLC0_EXT_BIT2_INT_ENA1 (BIT(21))
#define HOST_SLC0_EXT_BIT2_INT_ENA1_M (BIT(21))
#define HOST_SLC0_EXT_BIT2_INT_ENA1_V 0x1
#define HOST_SLC0_EXT_BIT2_INT_ENA1_S 21
/* HOST_SLC0_EXT_BIT1_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_EXT_BIT1_INT_ENA1 (BIT(2... | 2,152 |
*/
#define HOST_SLC0_TX_OVF_INT_ENA1 (BIT(17))
#define HOST_SLC0_TX_OVF_INT_ENA1_M (BIT(17))
#define HOST_SLC0_TX_OVF_INT_ENA1_V 0x1
#define HOST_SLC0_TX_OVF_INT_ENA1_S 17
/* HOST_SLC0_RX_UDF_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_RX_UDF_INT_ENA1 (BIT(16))
#define ... | 2,152 |
*/
#define HOST_SLC0HOST_RX_EOF_INT_ENA1 (BIT(13))
#define HOST_SLC0HOST_RX_EOF_INT_ENA1_M (BIT(13))
#define HOST_SLC0HOST_RX_EOF_INT_ENA1_V 0x1
#define HOST_SLC0HOST_RX_EOF_INT_ENA1_S 13
/* HOST_SLC0HOST_RX_SOF_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0HOST_RX_SOF_INT_EN... | 2,152 |
*/
#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(9))
#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_M (BIT(9))
#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x1
#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_S 9
/* HOST_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_TOKEN0_1TO0_INT_... | 2,152 |
*/
#define HOST_SLC0_TOHOST_BIT5_INT_ENA1 (BIT(5))
#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_M (BIT(5))
#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_V 0x1
#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_S 5
/* HOST_SLC0_TOHOST_BIT4_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_TOHOST_BIT4_INT_... | 2,152 |
*/
#define HOST_SLC0_TOHOST_BIT1_INT_ENA1 (BIT(1))
#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_M (BIT(1))
#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_V 0x1
#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_S 1
/* HOST_SLC0_TOHOST_BIT0_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SLC0_TOHOST_BIT0_INT_... | 2,152 |
*/
#define HOST_HSPEED_CON_EN (BIT(27))
#define HOST_HSPEED_CON_EN_M (BIT(27))
#define HOST_HSPEED_CON_EN_V 0x1
#define HOST_HSPEED_CON_EN_S 27
/* HOST_SDIO_PAD_PULLUP : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: .*/
#define HOST_SDIO_PAD_PULLUP (BIT(26))
#define HOST_SDIO_PAD_PULLUP_M (BIT(26))
#def... | 2,152 |
*/
#define HOST_FRC_NEG_SAMP 0x0000001F
#define HOST_FRC_NEG_SAMP_M ((HOST_FRC_NEG_SAMP_V)<<(HOST_FRC_NEG_SAMP_S))
#define HOST_FRC_NEG_SAMP_V 0x1F
#define HOST_FRC_NEG_SAMP_S 10
/* HOST_FRC_SDIO20 : R/W ;bitpos:[9:5] ;default: 5'b0 ; */
/*description: .*/
#define HOST_FRC_SDIO20 0x0000001F
#define HOST_FRC_SD... | 2,152 |
*/
#define HOST_SDIO_NEG_SAMP 0x0000001F
#define HOST_SDIO_NEG_SAMP_M ((HOST_SDIO_NEG_SAMP_V)<<(HOST_SDIO_NEG_SAMP_S))
#define HOST_SDIO_NEG_SAMP_V 0x1F
#define HOST_SDIO_NEG_SAMP_S 5
/* HOST_SDIO20_MODE : RO ;bitpos:[4:0] ;default: 5'b0 ; */
/*description: .*/
#define HOST_SDIO20_MODE 0x0000001F
#define HOST_... | 2,152 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C"
{
#endif
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
typedef enum {
ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/
ETS_WIFI_MAC_NMI_SOURCE, /**< interru... | 2,153 |
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 2,154 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */
GPIO_NUM_0 = 0, /*!< GPIO0, input and output */
GPIO_NUM_1 = 1, /*!< GPIO1, input and output */
GPIO_NUM_2 = 2, /*!< GPIO2, input and output */... | 2,156 |
< GPIO15, input and output */
GPIO_NUM_16 = 16, /*!< GPIO16, input and output */
GPIO_NUM_17 = 17, /*!< GPIO17, input and output */
GPIO_NUM_18 = 18, /*!< GPIO18, input and output */
GPIO_NUM_19 = 19, /*!< GPIO19, input and output */
GPIO_NUM_20 = 20, /*!< GPIO20, input and output */
G... | 2,156 |
< GPIO37, input and output */
GPIO_NUM_38 = 38, /*!< GPIO38, input and output */
GPIO_NUM_39 = 39, /*!< GPIO39, input and output */
GPIO_NUM_40 = 40, /*!< GPIO40, input and output */
GPIO_NUM_41 = 41, /*!< GPIO41, input and output */
GPIO_NUM_42 = 42, /*!< GPIO42, input and output */
G... | 2,156 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef struct gpio_sd_dev_t {
volatile union {
struct {
uint32_t duty: 8;
uint32_t prescale: 8;
uint32_t reserved16: 16;
};
uint32_t val;
} channel[8];
volatile ... | 2,158 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct ledc_dev_s {
struct {
struct {
union {
struct {
uint32_t timer_sel: 2; /*There are four high speed timers the two bits are used to select one of them... | 2,159 |
when software configure LED_PWM internal registers it controls the register clock.*/
};
uint32_t val;
} conf;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
ui... | 2,159 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define TRACEMEM_MUX_BLK0_NUM 19
#define TRACEMEM_MUX_BLK1_NUM 20
#define TRACEMEM_BLK_NUM2ADDR(_n_) (0x3FFB8000UL + 0x4000UL*((_n_)-4))
#define TRACEMEM_BLK0_ADDR TRACEMEM_BLK_NUM2ADDR(TR... | 2,160 |
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 2,162 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define GPIO_MATRIX_CONST_ONE_INPUT (0x38)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C)
#ifdef __cplusplus
}
#endif
| 2,163 |
/*
*/
#ifndef _SOC_DPORT_REG_H_
#define _SOC_DPORT_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "interrupt_reg.h"
#include "system_reg.h"
#include "sensitive_reg.h"
#include "soc.h"
#define DPORT_DATE_REG SYSTEM_DATE_REG
#ifndef __ASSEMBLER__
#include "dport_access.h"
#endif
#ifdef __cplusplus
}
#endif
... | 2,165 |
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,166 |
// Registers defined in rtc_cntl_reg.h, rtc_io_reg.h, sens_reg.h, and rtc_i2c_reg.h are usable with these macros.
// Read from rtc_reg[low_bit + bit_width - 1 : low_bit] into R0, bit_width <= 16
#define READ_RTC_REG(rtc_reg, low_bit, bit_width) \
REG_RD (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_w... | 2,166 |
/*
*/
#pragma once
/**
*/
#define I2C_BOD 0x61
#define I2C_BOD_HOSTID 1
#define I2C_BOD_THRESHOLD 0x5
#define I2C_BOD_THRESHOLD_MSB 2
#define I2C_BOD_THRESHOLD_LSB 0
| 2,168 |
/*
*/
#pragma once
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0000)
/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD0_PRESCALE 0x000000FF
#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V)<<... | 2,169 |
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,170 |
0x007FFFFF:0xffffffff)
#define FRC_TIMER_COUNT_S 0
#define FRC_TIMER_CTRL_REG(i) (REG_FRC_TIMER_BASE(i) + 0x8)
#define FRC_TIMER_INT_STATUS (BIT(8)) // interrupt status (RO)
#define FRC_TIMER_ENABLE (BIT(7)) // enable timer
#define FRC_TIMER_AUTOLOAD ... | 2,170 |
/*
*/
#ifndef _SOC_RTC_GPIO_CHANNEL_H
#define _SOC_RTC_GPIO_CHANNEL_H
//RTC GPIO channels
#define RTCIO_GPIO0_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 0
#define RTCIO_GPIO1_CHANNEL 1 //RTCIO_CHANNEL_1
#define RTCIO_CHANNEL_1_GPIO_NUM 1
#define RTCIO_GPIO2_CHANNEL ... | 2,173 |
/*
*/
#pragma once
/*
Note: These macros are deprecated. When connecting USB OTG to an external FSLS
PHY, the FSLS Serial Interface signals can be routed to any GPIO via the GPIO
matrix. Thus, these macros are meaningless.
Todo: Remove in IDF v6.0 (IDF-9029)
*/
#define USBPHY_VP_NUM 33
#define USBPHY_VM_NUM 34
#def... | 2,174 |
/*
*/
#ifndef _CACHE_MEMORY_H_
#define _CACHE_MEMORY_H_
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/*IRAM0 is connected with Cache IBUS0*/
#define SOC_IRAM0_ADDRESS_LOW 0x40000000
#define SOC_IRAM0_ADDRESS_HIGH 0x40400000
#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x40080000
#define SOC_IR... | 2,176 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/*
ESP32S2 Root Clock Source
*/
/* With the default value of CK8M_DFREQ = 172, RC_FAST clock frequency is 8.5 MHz +/- 7% */
#define SOC_CLK_RC_FAST_FREQ_APPROX 8500000 /*!, F
/**
*/
typedef enum {
// For CPU domai... | 2,179 |
< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 8MHz rc oscillator, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST_D256, /*!< RC_FAST_D256_CLK ... | 2,179 |
< Indication of the end of the available module clock sources */
} soc_module_clk_t;
//////////////////////////////////////////////////SYSTIMER///////////////////////////////////////////////////////////////
/**
*/
typedef enum {
SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL *... | 2,179 |
< Timer group source clock is APB */
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group source clock is XTAL */
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_APB, /*!< Timer group source clock default choice is APB */
} soc_periph_tg_clk_src_legacy_t;
//////////////////////////////////////////////////LCD/////////... | 2,179 |
< Select REF_TICK as the source clock */
RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
} soc_periph_rmt_clk_src_t;
/**
*/
typedef enum {
RMT_BASECLK_APB = SOC_MOD_CLK_APB, /*!< RMT source clock is APB CLK */
RMT_BASECLK_REF = SOC_MOD_CLK_REF_TICK, /*!< RMT sour... | 2,179 |
< UART source clock is APB CLK */
UART_SCLK_REF_TICK = SOC_MOD_CLK_REF_TICK, /*!< UART source clock is REF_TICK */
UART_SCLK_DEFAULT = SOC_MOD_CLK_APB, /*!< UART source clock default choice is APB */
} soc_periph_uart_clk_src_legacy_t;
///////////////////////////////////////////////////// I2S ///////////... | 2,179 |
< Select APB as SPI source clock */
SPI_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select XTAL as SPI source clock */
} soc_periph_spi_clk_src_t;
//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
/**
*/
#define SOC_SDM_CLKS {SOC_MOD_CLK_APB}
/*... | 2,179 |
< Select APB as the source clock */
DAC_DIGI_CLK_SRC_APLL = SOC_MOD_CLK_APLL, /*!< Select APLL as the source clock */
DAC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default source clock */
} soc_periph_dac_digi_clk_src_t;
/**
*/
#define SOC_DAC_COSINE_CLKS {SOC_MOD_CLK_RTC_FAST}
... | 2,179 |
< Select APB as the source clock */
ADC_DIGI_CLK_SRC_APLL = SOC_MOD_CLK_APLL, /*!< Select APLL as the source clock */
ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
} soc_periph_adc_digi_clk_src_t;
/**
*/
#define SOC_ADC_RTC_CLKS {SOC_MOD_CLK_RC_FAST}
/**... | 2,179 |
< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/
LEDC_USE_APB_CLK = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_US... | 2,179 |
< Main crystal oscillator clock */
CLKOUT_SIG_APLL = 6, /*!< Divided by PLL, frequency is configurable */
CLKOUT_SIG_REF_TICK = 12, /*!< Divided by APB clock, usually be 1MHz */
CLKOUT_SIG_PLL_F80M = 13, /*!< From PLL, usually be 80MHz */
CLKOUT_SIG_RC_FAST = 14, /*!< RC fast clock, about ... | 2,179 |
/*
*/
#ifndef _SOC_SPI_REG_H_
#define _SOC_SPI_REG_H_
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x000)
/* SPI_USR : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: User define command enable. An operation will be triggered when
the bit is set. T... | 2,180 |
Can be configured in CONF state.*/
#define SPI_USR_ADDR_VALUE 0xFFFFFFFF
#define SPI_USR_ADDR_VALUE_M ((SPI_USR_ADDR_VALUE_V)<<(SPI_USR_ADDR_VALUE_S))
#define SPI_USR_ADDR_VALUE_V 0xFFFFFFFF
#define SPI_USR_ADDR_VALUE_S 0
#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x008)
/* SPI_WR_BIT_ORDER : R/W ;bitpos... | 2,180 |
1: output high
0: output low. Can be configured in CONF state.*/
#define SPI_WP_REG (BIT(21))
#define SPI_WP_REG_M (BIT(21))
#define SPI_WP_REG_V 0x1
#define SPI_WP_REG_S 21
/* SPI_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
/*description: The bit is used to set MOSI line polarity 1: high 0 low. Can
be con... | 2,180 |
1: enable
0: disable. Can be configured in CONF state.*/
#define SPI_FREAD_QUAD (BIT(15))
#define SPI_FREAD_QUAD_M (BIT(15))
#define SPI_FREAD_QUAD_V 0x1
#define SPI_FREAD_QUAD_S 15
/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: In the read operations read-data phase apply 2 signals. 1:... | 2,180 |
Can
be configured in CONF state.*/
#define SPI_FCMD_DUAL (BIT(8))
#define SPI_FCMD_DUAL_M (BIT(8))
#define SPI_FCMD_DUAL_V 0x1
#define SPI_FCMD_DUAL_S 8
/* SPI_FADDR_OCT : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: Apply 8 signals during addr phase 1:enable 0: disable. Can be
configured in CONF state.*/
... | 2,180 |
Can be configured in CONF state.*/
#define SPI_DUMMY_OUT (BIT(3))
#define SPI_DUMMY_OUT_M (BIT(3))
#define SPI_DUMMY_OUT_V 0x1
#define SPI_DUMMY_OUT_S 3
/* SPI_EXT_HOLD_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set the bit to hold spi. The bit is combined with spi_usr_prep_hold
spi_usr_cmd_hold spi_... | 2,180 |
Can be configured in CONF state.*/
#define SPI_W16_17_WR_ENA (BIT(4))
#define SPI_W16_17_WR_ENA_M (BIT(4))
#define SPI_W16_17_WR_ENA_V 0x1
#define SPI_W16_17_WR_ENA_S 4
/* SPI_RSCK_DATA_OUT : R/W ;bitpos:[3] ;default: 1'h0 ; */
/*description: It saves half a cycle when tsck is the same as rsck. 1: output
data at ... | 2,180 |
Can be configured in CONF state.*/
#define SPI_CLK_MODE 0x00000003
#define SPI_CLK_MODE_M ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S))
#define SPI_CLK_MODE_V 0x3
#define SPI_CLK_MODE_S 0
#define SPI_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x010)
/* SPI_CS_DELAY_NUM : R/W ;bitpos:[30:29] ;default: 2'h0 ; */
/*description... | 2,180 |
Can be configured in CONF state.*/
#define SPI_CS_HOLD_TIME 0x00001FFF
#define SPI_CS_HOLD_TIME_M ((SPI_CS_HOLD_TIME_V)<<(SPI_CS_HOLD_TIME_S))
#define SPI_CS_HOLD_TIME_V 0x1FFF
#define SPI_CS_HOLD_TIME_S 13
/* SPI_CS_SETUP_TIME : R/W ;bitpos:[12:0] ;default: 13'h0 ; */
/*description: (cycles+1) of prepare phase by... | 2,180 |
Can be configured
in CONF state.*/
#define SPI_CLKDIV_PRE 0x00001FFF
#define SPI_CLKDIV_PRE_M ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S))
#define SPI_CLKDIV_PRE_V 0x1FFF
#define SPI_CLKDIV_PRE_S 18
/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */
/*description: In the master mode it is the divider of spi_c... | 2,180 |
In the slave
mode it must be 0. Can be configured in CONF state.*/
#define SPI_CLKCNT_L 0x0000003F
#define SPI_CLKCNT_L_M ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S))
#define SPI_CLKCNT_L_V 0x3F
#define SPI_CLKCNT_L_S 0
#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x018)
/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;def... | 2,180 |
*/
#define SPI_USR_DUMMY (BIT(29))
#define SPI_USR_DUMMY_M (BIT(29))
#define SPI_USR_DUMMY_V 0x1
#define SPI_USR_DUMMY_S 29
/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: This bit enable the read-data phase of an operation. Can be configured
in CONF state.*/
#define SPI_USR_MISO (BIT(28))
#... | 2,180 |
1: enable 0: disable. Can be configured in CONF state.*/
#define SPI_USR_MOSI_HIGHPART (BIT(25))
#define SPI_USR_MOSI_HIGHPART_M (BIT(25))
#define SPI_USR_MOSI_HIGHPART_V 0x1
#define SPI_USR_MOSI_HIGHPART_S 25
/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: read-data phase only acc... | 2,180 |
Can be configured in CONF state.*/
#define SPI_USR_CMD_HOLD (BIT(22))
#define SPI_USR_CMD_HOLD_M (BIT(22))
#define SPI_USR_CMD_HOLD_V 0x1
#define SPI_USR_CMD_HOLD_S 22
/* SPI_USR_ADDR_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */
/*description: spi is hold at address state the bit are combined with spi_usr_hold_pol
... | 2,180 |
*/
#define SPI_USR_DIN_HOLD (BIT(19))
#define SPI_USR_DIN_HOLD_M (BIT(19))
#define SPI_USR_DIN_HOLD_V 0x1
#define SPI_USR_DIN_HOLD_S 19
/* SPI_USR_DOUT_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */
/*description: spi is hold at data out state the bit are combined with spi_usr_hold_pol
bit. Can be configured in CONF ... | 2,180 |
1: enable 0: disable. Can be configured in CONF state.*/
#define SPI_SIO (BIT(16))
#define SPI_SIO_M (BIT(16))
#define SPI_SIO_V 0x1
#define SPI_SIO_S 16
/* SPI_USR_CONF_NXT : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: 1: Enable the DMA CONF phase of next seg-trans operation which
means seg-trans will c... | 2,180 |
Can
be configured in CONF state.*/
#define SPI_FWRITE_QUAD (BIT(13))
#define SPI_FWRITE_QUAD_M (BIT(13))
#define SPI_FWRITE_QUAD_V 0x1
#define SPI_FWRITE_QUAD_S 13
/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: In the write operations read-data phase apply 2 signals. Can
be configured i... | 2,180 |
Can be configured in CONF state.*/
#define SPI_CK_OUT_EDGE (BIT(9))
#define SPI_CK_OUT_EDGE_M (BIT(9))
#define SPI_CK_OUT_EDGE_V 0x1
#define SPI_CK_OUT_EDGE_S 9
/* SPI_RSCK_I_EDGE : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: In the slave mode this bit can be used to change the polarity
of rsck. 0: rsck =... | 2,180 |
0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/
#define SPI_TSCK_I_EDGE (BIT(5))
#define SPI_TSCK_I_EDGE_M (BIT(5))
#define SPI_TSCK_I_EDGE_V 0x1
#define SPI_TSCK_I_EDGE_S 5
/* SPI_OPI_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: Just for master mode. 1: spi controller is in OPI mode (all in
8-b-m). 0: oth... | 2,180 |
The register value shall
be (bit_num-1). Can be configured in CONF state.*/
#define SPI_USR_ADDR_BITLEN 0x0000001F
#define SPI_USR_ADDR_BITLEN_M ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S))
#define SPI_USR_ADDR_BITLEN_V 0x1F
#define SPI_USR_ADDR_BITLEN_S 27
/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;def... | 2,180 |
Can be configured in CONF state.*/
#define SPI_USR_COMMAND_VALUE 0x0000FFFF
#define SPI_USR_COMMAND_VALUE_M ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S))
#define SPI_USR_COMMAND_VALUE_V 0xFFFF
#define SPI_USR_COMMAND_VALUE_S 0
#define SPI_MOSI_DLEN_REG(i) (REG_SPI_BASE(i) + 0x024)
/* SPI_USR_MOS... | 2,180 |
Can be configured in CONF state.*/
#define SPI_QUAD_DIN_PIN_SWAP (BIT(31))
#define SPI_QUAD_DIN_PIN_SWAP_M (BIT(31))
#define SPI_QUAD_DIN_PIN_SWAP_V 0x1
#define SPI_QUAD_DIN_PIN_SWAP_S 31
/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: spi cs line keep low when the bit is set. Can be c... | 2,180 |
spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_CMD
state. 0: spi_cd = spi_cd_idle_edge. Can be configured in CONF state.*/
#define SPI_CD_CMD_SET (BIT(25))
#define SPI_CD_CMD_SET_M (BIT(25))
#define SPI_CD_CMD_SET_V 0x1
#define SPI_CD_CMD_SET_S 25
/* SPI_DQS_IDLE_EDGE : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*de... | 2,180 |
Can be configured in CONF state.*/
#define SPI_CD_ADDR_SET (BIT(22))
#define SPI_CD_ADDR_SET_M (BIT(22))
#define SPI_CD_ADDR_SET_V 0x1
#define SPI_CD_ADDR_SET_S 22
/* SPI_CD_DUMMY_SET : R/W ;bitpos:[21] ;default: 1'b0 ; */
/*description: 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DUMMY
state. 0: sp... | 2,180 |
Can be configured in CONF state.*/
#define SPI_CMD_DTR_EN (BIT(19))
#define SPI_CMD_DTR_EN_M (BIT(19))
#define SPI_CMD_DTR_EN_V 0x1
#define SPI_CMD_DTR_EN_S 19
/* SPI_ADDR_DTR_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
/*description: 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode including
master 1/2/... | 2,180 |
Can be configured in CONF state.*/
#define SPI_MASTER_CS_POL 0x0000003F
#define SPI_MASTER_CS_POL_M ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S))
#define SPI_MASTER_CS_POL_V 0x3F
#define SPI_MASTER_CS_POL_S 7
/* SPI_CK_DIS : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: 1: spi clk out disable 0: spi clk ou... | 2,180 |
Can be configured in CONF state.*/
#define SPI_CS2_DIS (BIT(2))
#define SPI_CS2_DIS_M (BIT(2))
#define SPI_CS2_DIS_V 0x1
#define SPI_CS2_DIS_S 2
/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: SPI CS1 pin enable 1: disable CS1 0: spi_cs1 signal is from/to
CS1 pin. Can be configured in CONF s... | 2,180 |
1: slave mode 0: master mode.*/
#define SPI_SLAVE_MODE (BIT(30))
#define SPI_SLAVE_MODE_M (BIT(30))
#define SPI_SLAVE_MODE_V 0x1
#define SPI_SLAVE_MODE_S 30
/* SPI_TRANS_DONE_AUTO_CLR_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: spi_trans_done auto clear enable clear it 3 apb cycles after
the pos edg... | 2,180 |
Can be
configured in CONF state.*/
#define SPI_SEG_MAGIC_ERR_INT_EN (BIT(11))
#define SPI_SEG_MAGIC_ERR_INT_EN_M (BIT(11))
#define SPI_SEG_MAGIC_ERR_INT_EN_V 0x1
#define SPI_SEG_MAGIC_ERR_INT_EN_S 11
/* SPI_INT_DMA_SEG_TRANS_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: spi_dma_seg_trans_done Interrupt... | 2,180 |
Can be
configured in CONF state.*/
#define SPI_INT_WR_DMA_DONE_EN (BIT(8))
#define SPI_INT_WR_DMA_DONE_EN_M (BIT(8))
#define SPI_INT_WR_DMA_DONE_EN_V 0x1
#define SPI_INT_WR_DMA_DONE_EN_S 8
/* SPI_INT_RD_DMA_DONE_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: spi_slv_rd_dma Interrupt enable. 1: enable 0: ... | 2,180 |
*/
#define SPI_INT_RD_BUF_DONE_EN (BIT(5))
#define SPI_INT_RD_BUF_DONE_EN_M (BIT(5))
#define SPI_INT_RD_BUF_DONE_EN_V 0x1
#define SPI_INT_RD_BUF_DONE_EN_S 5
/* SPI_TRANS_DONE : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The interrupt raw bit for the completion of any operation in
both the master mode and t... | 2,180 |
Can not be changed by CONF_buf.*/
#define SPI_SLV_WR_DMA_DONE (BIT(15))
#define SPI_SLV_WR_DMA_DONE_M (BIT(15))
#define SPI_SLV_WR_DMA_DONE_V 0x1
#define SPI_SLV_WR_DMA_DONE_S 15
/* SPI_SLV_CMD_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */
/*description: 1: The command value of the last SPI transfer is not supported
... | 2,180 |
0: spi slave QPI mode is supported.*/
#define SPI_SLV_NO_QPI_EN (BIT(12))
#define SPI_SLV_NO_QPI_EN_M (BIT(12))
#define SPI_SLV_NO_QPI_EN_V 0x1
#define SPI_SLV_NO_QPI_EN_S 12
/* SPI_SLV_CMD_ERR_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: 1: Clear spi_slv_cmd_err. 0: not valid. Can be changed by CONF... | 2,180 |
*/
#define SPI_CONF_BASE_BITLEN 0x0000007F
#define SPI_CONF_BASE_BITLEN_M ((SPI_CONF_BASE_BITLEN_V)<<(SPI_CONF_BASE_BITLEN_S))
#define SPI_CONF_BASE_BITLEN_V 0x7F
#define SPI_CONF_BASE_BITLEN_S 25
/* SPI_SLV_WR_BUF_DONE : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: The interrupt raw bit for the completion o... | 2,180 |
Can not be changed by CONF_buf.*/
#define SPI_SLV_RD_BUF_DONE (BIT(24))
#define SPI_SLV_RD_BUF_DONE_M (BIT(24))
#define SPI_SLV_RD_BUF_DONE_V 0x1
#define SPI_SLV_RD_BUF_DONE_S 24
/* SPI_SLV_DMA_RD_BYTELEN : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
/*description: In the slave mode it is the length in bytes for read... | 2,180 |
Can not be changed by CONF_buf.*/
#define SPI_SLV_RD_DMA_DONE (BIT(30))
#define SPI_SLV_RD_DMA_DONE_M (BIT(30))
#define SPI_SLV_RD_DMA_DONE_V 0x1
#define SPI_SLV_RD_DMA_DONE_S 30
/* SPI_DMA_SEG_MAGIC_VALUE : R/W ;bitpos:[27:24] ;default: 4'd10 ; */
/*description: The magic value of BM table in master DMA seg-tran... | 2,180 |
0: others*/
#define SPI_SLV_RDBUF_BYTELEN_EN (BIT(22))
#define SPI_SLV_RDBUF_BYTELEN_EN_M (BIT(22))
#define SPI_SLV_RDBUF_BYTELEN_EN_V 0x1
#define SPI_SLV_RDBUF_BYTELEN_EN_S 22
/* SPI_SLV_WRDMA_BYTELEN_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
/*description: 1: spi_slv_data_bytelen stores data byte length of maste... | 2,180 |
In half-duplex mode this value is controlled by bits [23:20].*/
#define SPI_SLV_DATA_BYTELEN 0x000FFFFF
#define SPI_SLV_DATA_BYTELEN_M ((SPI_SLV_DATA_BYTELEN_V)<<(SPI_SLV_DATA_BYTELEN_S))
#define SPI_SLV_DATA_BYTELEN_V 0xFFFFF
#define SPI_SLV_DATA_BYTELEN_S 0
#define SPI_FSM_REG(i) (REG_SPI_BASE(i) + 0x... | 2,180 |
*/
#define SPI_ST 0x0000000F
#define SPI_ST_M ((SPI_ST_V)<<(SPI_ST_S))
#define SPI_ST_V 0xF
#define SPI_ST_S 0
#define SPI_HOLD_REG(i) (REG_SPI_BASE(i) + 0x048)
/* SPI_DMA_SEG_TRANS_DONE : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: 1: spi master DMA full-duplex/half-duplex seg-trans ends or
slav... | 2,180 |
It can be used
to hold spi state machine with spi_ext_hold_en and other usr hold signals. Can be configured in CONF state.*/
#define SPI_HOLD_OUT_EN (BIT(3))
#define SPI_HOLD_OUT_EN_M (BIT(3))
#define SPI_HOLD_OUT_EN_V 0x1
#define SPI_HOLD_OUT_EN_S 3
/* SPI_HOLD_VAL_REG : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*des... | 2,180 |
2 or more
end seg-trans signals will induce error in DMA RX.*/
#define SPI_DMA_SEG_TRANS_CLR (BIT(28))
#define SPI_DMA_SEG_TRANS_CLR_M (BIT(28))
#define SPI_DMA_SEG_TRANS_CLR_V 0x1
#define SPI_DMA_SEG_TRANS_CLR_S 28
/* SPI_EXT_MEM_BK_SIZE : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
/*description: Select the externa... | 2,180 |
0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/
#define SPI_RX_EOF_EN (BIT(21))
#define SPI_RX_EOF_EN_M (BIT(21))
#define SPI_RX_EOF_EN_V 0x1
#define SPI_RX_EOF_EN_S 21
/* SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: 1:... | 2,180 |
1: enable. 0: disable.*/
#define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18))
#define SPI_DMA_SLV_SEG_TRANS_EN_M (BIT(18))
#define SPI_DMA_SLV_SEG_TRANS_EN_V 0x1
#define SPI_DMA_SLV_SEG_TRANS_EN_S 18
/* SPI_SLV_LAST_SEG_POP_CLR : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: 1: Clear spi_slv_seg_frt_pop_mask. 0 : othe... | 2,180 |
*/
#define SPI_DMA_RX_STOP (BIT(14))
#define SPI_DMA_RX_STOP_M (BIT(14))
#define SPI_DMA_RX_STOP_V 0x1
#define SPI_DMA_RX_STOP_S 14
/* SPI_MEM_TRANS_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: */
#define SPI_MEM_TRANS_EN (BIT(13))
#define SPI_MEM_TRANS_EN_M (BIT(13))
#define SPI_MEM_TRANS_EN_V 0x1
#... | 2,180 |
*/
#define SPI_OUTDSCR_BURST_EN (BIT(10))
#define SPI_OUTDSCR_BURST_EN_M (BIT(10))
#define SPI_OUTDSCR_BURST_EN_V 0x1
#define SPI_OUTDSCR_BURST_EN_S 10
/* SPI_OUT_EOF_MODE : R/W ;bitpos:[9] ;default: 1'b1 ; */
/*description: out eof flag generation mode . 1: when dma pop all data from
fifo 0:when ahb push all dat... | 2,180 |
*/
#define SPI_IN_LOOP_TEST (BIT(6))
#define SPI_IN_LOOP_TEST_M (BIT(6))
#define SPI_IN_LOOP_TEST_V 0x1
#define SPI_IN_LOOP_TEST_S 6
/* SPI_AHBM_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: Reset spi dma ahb master.*/
#define SPI_AHBM_RST (BIT(5))
#define SPI_AHBM_RST_M (BIT(5))
#define SPI_AHBM_RST_V... | 2,180 |
*/
#define SPI_DMA_TX_ENA (BIT(31))
#define SPI_DMA_TX_ENA_M (BIT(31))
#define SPI_DMA_TX_ENA_V 0x1
#define SPI_DMA_TX_ENA_S 31
/* SPI_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: Set the bit to mount on new outlink descriptors.*/
#define SPI_OUTLINK_RESTART (BIT(30))
#define SPI_OUTLINK_R... | 2,180 |
*/
#define SPI_OUTLINK_ADDR 0x000FFFFF
#define SPI_OUTLINK_ADDR_M ((SPI_OUTLINK_ADDR_V)<<(SPI_OUTLINK_ADDR_S))
#define SPI_OUTLINK_ADDR_V 0xFFFFF
#define SPI_OUTLINK_ADDR_S 0
#define SPI_DMA_IN_LINK_REG(i) (REG_SPI_BASE(i) + 0x054)
/* SPI_DMA_RX_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: sp... | 2,180 |
*/
#define SPI_INLINK_STOP (BIT(28))
#define SPI_INLINK_STOP_M (BIT(28))
#define SPI_INLINK_STOP_V 0x1
#define SPI_INLINK_STOP_S 28
/* SPI_INLINK_AUTO_RET : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: when the bit is set the inlink descriptor returns to the first
link node when a packet is error.*/
#defin... | 2,180 |
*/
#define SPI_SLV_CMD9_INT_ENA (BIT(14))
#define SPI_SLV_CMD9_INT_ENA_M (BIT(14))
#define SPI_SLV_CMD9_INT_ENA_V 0x1
#define SPI_SLV_CMD9_INT_ENA_S 14
/* SPI_SLV_CMD8_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: The enable bit for SPI slave CMD8 interrupt.*/
#define SPI_SLV_CMD8_INT_ENA (BIT(13))... | 2,180 |
*/
#define SPI_OUTFIFO_EMPTY_ERR_INT_ENA (BIT(10))
#define SPI_OUTFIFO_EMPTY_ERR_INT_ENA_M (BIT(10))
#define SPI_OUTFIFO_EMPTY_ERR_INT_ENA_V 0x1
#define SPI_OUTFIFO_EMPTY_ERR_INT_ENA_S 10
/* SPI_INFIFO_FULL_ERR_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: The enable bit for infifo full error interru... | 2,180 |
*/
#define SPI_OUT_EOF_INT_ENA (BIT(7))
#define SPI_OUT_EOF_INT_ENA_M (BIT(7))
#define SPI_OUT_EOF_INT_ENA_V 0x1
#define SPI_OUT_EOF_INT_ENA_S 7
/* SPI_OUT_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: The enable bit for completing usage of a outlink descriptor .
Can be configured in CONF state... | 2,180 |
Can
be configured in CONF state.*/
#define SPI_IN_DONE_INT_ENA (BIT(3))
#define SPI_IN_DONE_INT_ENA_M (BIT(3))
#define SPI_IN_DONE_INT_ENA_V 0x1
#define SPI_IN_DONE_INT_ENA_S 3
/* SPI_INLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: The enable bit for inlink descriptor error. Can be ... | 2,180 |
Can be
configured in CONF state.*/
#define SPI_INLINK_DSCR_EMPTY_INT_ENA (BIT(0))
#define SPI_INLINK_DSCR_EMPTY_INT_ENA_M (BIT(0))
#define SPI_INLINK_DSCR_EMPTY_INT_ENA_V 0x1
#define SPI_INLINK_DSCR_EMPTY_INT_ENA_S 0
#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x05C)
/* SPI_SLV_CMDA_INT_RAW : R/W ... | 2,180 |
*/
#define SPI_SLV_CMD7_INT_RAW (BIT(12))
#define SPI_SLV_CMD7_INT_RAW_M (BIT(12))
#define SPI_SLV_CMD7_INT_RAW_V 0x1
#define SPI_SLV_CMD7_INT_RAW_S 12
/* SPI_SLV_CMD6_INT_RAW : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: The raw bit for SPI slave CMD6 interrupt.*/
#define SPI_SLV_CMD6_INT_RAW (BIT(11))
#d... | 2,180 |
0: Others. Can not be changed by CONF_buf.*/
#define SPI_INFIFO_FULL_ERR_INT_RAW (BIT(9))
#define SPI_INFIFO_FULL_ERR_INT_RAW_M (BIT(9))
#define SPI_INFIFO_FULL_ERR_INT_RAW_V 0x1
#define SPI_INFIFO_FULL_ERR_INT_RAW_S 9
/* SPI_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: The raw bit f... | 2,180 |
Can
be configured in CONF state.*/
#define SPI_OUT_DONE_INT_RAW (BIT(6))
#define SPI_OUT_DONE_INT_RAW_M (BIT(6))
#define SPI_OUT_DONE_INT_RAW_V 0x1
#define SPI_OUT_DONE_INT_RAW_S 6
/* SPI_IN_SUC_EOF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: The raw bit for completing receiving all the packets fr... | 2,180 |
Can be configured in CONF state.*/
#define SPI_INLINK_DSCR_ERROR_INT_RAW (BIT(2))
#define SPI_INLINK_DSCR_ERROR_INT_RAW_M (BIT(2))
#define SPI_INLINK_DSCR_ERROR_INT_RAW_V 0x1
#define SPI_INLINK_DSCR_ERROR_INT_RAW_S 2
/* SPI_OUTLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: The raw bit ... | 2,180 |
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