text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
*/
#define EXTMEM_DC_PRELOAD_SIZE_FAULT_ST (BIT(24))
#define EXTMEM_DC_PRELOAD_SIZE_FAULT_ST_M (BIT(24))
#define EXTMEM_DC_PRELOAD_SIZE_FAULT_ST_V 0x1
#define EXTMEM_DC_PRELOAD_SIZE_FAULT_ST_S 24
/* EXTMEM_DC_SYNC_SIZE_FAULT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
/*description: The bit is used to indicate interru... | 2,193 |
*/
#define EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST (BIT(21))
#define EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST_M (BIT(21))
#define EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST_V 0x1
#define EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST_S 21
/* EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
/*description: The bit is used to... | 2,193 |
*/
#define EXTMEM_DBUS1_ABANDON_CNT_OVF_ST (BIT(17))
#define EXTMEM_DBUS1_ABANDON_CNT_OVF_ST_M (BIT(17))
#define EXTMEM_DBUS1_ABANDON_CNT_OVF_ST_V 0x1
#define EXTMEM_DBUS1_ABANDON_CNT_OVF_ST_S 17
/* EXTMEM_DBUS0_ABANDON_CNT_OVF_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
/*description: The bit is used to indicate inte... | 2,193 |
*/
#define EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST (BIT(13))
#define EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST_M (BIT(13))
#define EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST_V 0x1
#define EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST_S 13
/* EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt... | 2,193 |
*/
#define EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST (BIT(9))
#define EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST_M (BIT(9))
#define EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST_V 0x1
#define EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST_S 9
/* EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: The bit is used to indicate int... | 2,193 |
*/
#define EXTMEM_DBUS1_ACS_CNT_OVF_ST (BIT(5))
#define EXTMEM_DBUS1_ACS_CNT_OVF_ST_M (BIT(5))
#define EXTMEM_DBUS1_ACS_CNT_OVF_ST_V 0x1
#define EXTMEM_DBUS1_ACS_CNT_OVF_ST_S 5
/* EXTMEM_DBUS0_ACS_CNT_OVF_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by dbus0 counter o... | 2,193 |
*/
#define EXTMEM_DBUS1_ACS_MSK_DCACHE_ST (BIT(1))
#define EXTMEM_DBUS1_ACS_MSK_DCACHE_ST_M (BIT(1))
#define EXTMEM_DBUS1_ACS_MSK_DCACHE_ST_V 0x1
#define EXTMEM_DBUS1_ACS_MSK_DCACHE_ST_S 1
/* EXTMEM_DBUS0_ACS_MSK_DCACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by ... | 2,193 |
*/
#define EXTMEM_PRO_DCACHE_ACS_CNT_CLR (BIT(0))
#define EXTMEM_PRO_DCACHE_ACS_CNT_CLR_M (BIT(0))
#define EXTMEM_PRO_DCACHE_ACS_CNT_CLR_V 0x1
#define EXTMEM_PRO_DCACHE_ACS_CNT_CLR_S 0
#define EXTMEM_PRO_DCACHE_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x0FC)
/* EXTMEM_PRO_DCACHE_CPU_ATTR : RO ;bitpos:[5:3] ;de... | 2,193 |
*/
#define EXTMEM_PRO_DCACHE_CPU_VADDR 0xFFFFFFFF
#define EXTMEM_PRO_DCACHE_CPU_VADDR_M ((EXTMEM_PRO_DCACHE_CPU_VADDR_V)<<(EXTMEM_PRO_DCACHE_CPU_VADDR_S))
#define EXTMEM_PRO_DCACHE_CPU_VADDR_V 0xFFFFFFFF
#define EXTMEM_PRO_DCACHE_CPU_VADDR_S 0
#define EXTMEM_PRO_ICACHE_REJECT_ST_REG (DR_REG_EXTMEM_BASE + ... | 2,193 |
*/
#define EXTMEM_PRO_ICACHE_TAG_ATTR 0x00000007
#define EXTMEM_PRO_ICACHE_TAG_ATTR_M ((EXTMEM_PRO_ICACHE_TAG_ATTR_V)<<(EXTMEM_PRO_ICACHE_TAG_ATTR_S))
#define EXTMEM_PRO_ICACHE_TAG_ATTR_V 0x7
#define EXTMEM_PRO_ICACHE_TAG_ATTR_S 0
#define EXTMEM_PRO_ICACHE_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x108)
/* ... | 2,193 |
0: default 1: cpu miss 2: preload miss 3: flush 4: cpu miss evict recovery address 5: load miss evict recovery address 6: external dma tx 7: external dma rx*/
#define EXTMEM_PRO_CACHE_MMU_FAULT_CODE 0x00000007
#define EXTMEM_PRO_CACHE_MMU_FAULT_CODE_M ((EXTMEM_PRO_CACHE_MMU_FAULT_CODE_V)<<(EXTMEM_PRO_CACHE_MM... | 2,193 |
.*/
#define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR 0xFFFFFFFF
#define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_M ((EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_V)<<(EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_S))
#define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_V 0xFFFFFFFF
#define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_S 0
#define EXTMEM_PRO_CACHE_WRAP_AROUND_CTR... | 2,193 |
1: in idle state 0: not in idle state*/
#define EXTMEM_PRO_DCACHE_STATE 0x00000FFF
#define EXTMEM_PRO_DCACHE_STATE_M ((EXTMEM_PRO_DCACHE_STATE_V)<<(EXTMEM_PRO_DCACHE_STATE_S))
#define EXTMEM_PRO_DCACHE_STATE_V 0xFFF
#define EXTMEM_PRO_DCACHE_STATE_S 12
/* EXTMEM_PRO_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'... | 2,193 |
*/
#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT (BIT(0))
#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M (BIT(0))
#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V 0x1
#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S 0
#define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG (DR_REG_EXTMEM_BASE + 0x124)
/* EXTMEM_CLK_FORCE_ON_AUT... | 2,193 |
1: close
gating 0: open clock gating.*/
#define EXTMEM_CLK_FORCE_ON_DB_ENCRYPT (BIT(0))
#define EXTMEM_CLK_FORCE_ON_DB_ENCRYPT_M (BIT(0))
#define EXTMEM_CLK_FORCE_ON_DB_ENCRYPT_V 0x1
#define EXTMEM_CLK_FORCE_ON_DB_ENCRYPT_S 0
#define EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x128)
/* ... | 2,193 |
*/
#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA (BIT(4))
#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA_M (BIT(4))
#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA_V 0x1
#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA_S 4
/* EXTMEM_PRO_DCACHE_PRELOAD_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The bit is used to indicate... | 2,193 |
*/
#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA (BIT(1))
#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA_M (BIT(1))
#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA_V 0x1
#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA_S 1
/* EXTMEM_PRO_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to indicate... | 2,193 |
*/
#define EXTMEM_PRO_DCACHE_SYNC_INT_ENA (BIT(4))
#define EXTMEM_PRO_DCACHE_SYNC_INT_ENA_M (BIT(4))
#define EXTMEM_PRO_DCACHE_SYNC_INT_ENA_V 0x1
#define EXTMEM_PRO_DCACHE_SYNC_INT_ENA_S 4
/* EXTMEM_PRO_DCACHE_SYNC_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The bit is used to indicate the interrupt ... | 2,193 |
*/
#define EXTMEM_PRO_ICACHE_SYNC_INT_ENA (BIT(1))
#define EXTMEM_PRO_ICACHE_SYNC_INT_ENA_M (BIT(1))
#define EXTMEM_PRO_ICACHE_SYNC_INT_ENA_V 0x1
#define EXTMEM_PRO_ICACHE_SYNC_INT_ENA_S 1
/* EXTMEM_PRO_ICACHE_SYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to indicate the interrupt ... | 2,193 |
*/
#define EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT (BIT(0))
#define EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M (BIT(0))
#define EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V 0x1
#define EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S 0
#define EXTMEM_CLOCK_GATE_REG (DR_REG_EXTMEM_BASE... | 2,193 |
/*
*/
#pragma once
/**
*/
#define I2C_SAR_ADC 0X69
#define I2C_SAR_ADC_HOSTID 1
#define ADC_SAR1_ENCAL_GND_ADDR 0x7
#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
#define ADC_SAR2_ENCAL_GND_ADDR 0x7
#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
#define ADC_SAR2_ENCAL_GND_ADDR_... | 2,194 |
/*
*/
#pragma once
#include
#include "soc/ext_mem_defs.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Defined for flash mmap */
#define SOC_MMU_REGIONS_COUNT 6
#define SOC_MMU_PAGES_PER_REGION 64
#define SOC_MMU_IROM0_PAGES_START (PRO_CACHE_IBUS0_MM... | 2,195 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/*
Configuration Set ID: 1
*/
/* 3.1 Basic Config Parameters */
#define OTG_MODE 0
#define OTG_ARCHITECTURE 2
#define OTG_SINGLE_POINT 1
#define OTG_ENABLE_LPM 0
#define OTG_EN_DED_TX_FIFO 1
#define OTG_EN_DESC_DMA... | 2,199 |
6 Additional Configuration Options Parameters */
#define OTG_TRANS_COUNT_WIDTH 16
#define OTG_PACKET_COUNT_WIDTH 7
#define OTG_RM_OPT_FEATURES 1
#define OTG_EN_PWROPT 1
#define OTG_SYNC_RESET_TYPE 0
#define OTG_EN_IDDIG_FILTER 1
#define OTG_EN_VBUSVALID_FILTER 1
#def... | 2,199 |
10 UTMI-To-UTMI Bridge Component Parameters */
#define U2UB_EN 0
#ifdef __cplusplus
}
#endif
| 2,199 |
/** Copyright 2020 Espressif Systems (Shanghai) PTE LTD
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** USB_WRAP_OTG_CONF_REG register
*/
#define USB_WRAP_OTG_CONF_REG (DR_REG_USB_WRAP_BASE + 0x0)
/** USB_WRAP_SRP_SESSEND_OVERRIDE : R/W; bitpos: [0]; default: 0;
*/
#define... | 2,200 |
/*
*/
#pragma once
//+Terminology+
//| |
//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
//| ... | 2,201 |
/*
*/
#pragma once
/**
*/
#define I2C_APLL 0X6D
#define I2C_APLL_HOSTID 1
#define I2C_APLL_IR_CAL_DELAY 0
#define I2C_APLL_IR_CAL_DELAY_MSB 3
#define I2C_APLL_IR_CAL_DELAY_LSB 0
#define I2C_APLL_IR_CAL_RSTB 0
#define I2C_APLL_IR_CAL_RSTB_MSB 4
#define I2C_APLL_IR_CAL_RSTB_LS... | 2,202 |
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,204 |
/*
*/
#ifndef _SOC_SPI_MEM_REG_H_
#define _SOC_SPI_MEM_REG_H_
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x000)
/* SPI_MEM_FLASH_READ : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: Read flash enable. Read flash operation will be triggere... | 2,205 |
Write disable command will be sent when
the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
#define SPI_MEM_FLASH_WRDI (BIT(29))
#define SPI_MEM_FLASH_WRDI_M (BIT(29))
#define SPI_MEM_FLASH_WRDI_V 0x1
#define SPI_MEM_FLASH_WRDI_S 29
/* SPI_MEM_FLASH_RDID : R/W ;bitpos:[28] ;de... | 2,205 |
Write status operation will
be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
#define SPI_MEM_FLASH_WRSR (BIT(26))
#define SPI_MEM_FLASH_WRSR_M (BIT(26))
#define SPI_MEM_FLASH_WRSR_V 0x1
#define SPI_MEM_FLASH_WRSR_S 26
/* SPI_MEM_FLASH_PP : R/W ;bitpos:[2... | 2,205 |
Block erase operation will be triggered
when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
#define SPI_MEM_FLASH_BE (BIT(23))
#define SPI_MEM_FLASH_BE_M (BIT(23))
#define SPI_MEM_FLASH_BE_V 0x1
#define SPI_MEM_FLASH_BE_S 23
/* SPI_MEM_FLASH_CE : R/W ;bitpos:[22] ;default... | 2,205 |
The bit will be cleared once the operation done.1: enable 0: disable.*/
#define SPI_MEM_FLASH_RES (BIT(20))
#define SPI_MEM_FLASH_RES_M (BIT(20))
#define SPI_MEM_FLASH_RES_V 0x1
#define SPI_MEM_FLASH_RES_S 20
/* SPI_MEM_FLASH_HPM : R/W ;bitpos:[19] ;default: 1'b0 ; */
/*description: Drive Flash into high performan... | 2,205 |
The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.*/
#define SPI_MEM_FLASH_PE (BIT(17))
#define SPI_MEM_FLASH_PE_M (BIT(17))
#define SPI_MEM_FLASH_PE_V 0x1
#define SPI_MEM_FLASH_PE_S 17
#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x004)
... | 2,205 |
*/
#define SPI_MEM_FREAD_QIO (BIT(24))
#define SPI_MEM_FREAD_QIO_M (BIT(24))
#define SPI_MEM_FREAD_QIO_V 0x1
#define SPI_MEM_FREAD_QIO_S 24
/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
/*description: In the read operations address phase and read-data phase apply
2 signals. 1: enable 0: disable.*/
#d... | 2,205 |
1: enable 0: disable.*/
#define SPI_MEM_FREAD_QUAD (BIT(20))
#define SPI_MEM_FREAD_QUAD_M (BIT(20))
#define SPI_MEM_FREAD_QUAD_V 0x1
#define SPI_MEM_FREAD_QUAD_S 20
/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
/*description: The bit is used to set MOSI line polarity 1: high 0 low*/
#define SPI_MEM_D_P... | 2,205 |
1: enable 0: disable.*/
#define SPI_MEM_FREAD_DUAL (BIT(14))
#define SPI_MEM_FREAD_DUAL_M (BIT(14))
#define SPI_MEM_FREAD_DUAL_V 0x1
#define SPI_MEM_FREAD_DUAL_S 14
/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
/*description: This bit enable the bits: spi_mem_fread_qio spi_mem_fread_dio
spi_mem_... | 2,205 |
*/
#define SPI_MEM_FDUMMY_OUT (BIT(3))
#define SPI_MEM_FDUMMY_OUT_M (BIT(3))
#define SPI_MEM_FDUMMY_OUT_V 0x1
#define SPI_MEM_FDUMMY_OUT_S 3
#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0x00C)
/* SPI_MEM_CS_DLY_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: The bit is used to select the... | 2,205 |
*/
#define SPI_MEM_CS_HOLD_DLY 0x00000FFF
#define SPI_MEM_CS_HOLD_DLY_M ((SPI_MEM_CS_HOLD_DLY_V)<<(SPI_MEM_CS_HOLD_DLY_S))
#define SPI_MEM_CS_HOLD_DLY_V 0xFFF
#define SPI_MEM_CS_HOLD_DLY_S 14
/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[13:2] ;default: 12'hfff ; */
/*description: Delay cycles of resume Flash when resu... | 2,205 |
*/
#define SPI_MEM_SYNC_RESET (BIT(31))
#define SPI_MEM_SYNC_RESET_M (BIT(31))
#define SPI_MEM_SYNC_RESET_V 0x1
#define SPI_MEM_SYNC_RESET_S 31
/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[25:13] ;default: 13'h1 ; */
/*description: Spi cs signal is delayed to inactive by spi clock this bits are
combined with spi_mem_cs_... | 2,205 |
So spi_mem_clk
frequency is system/(spi_mem_clkcnt_N+1)*/
#define SPI_MEM_CLKCNT_N 0x000000FF
#define SPI_MEM_CLKCNT_N_M ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S))
#define SPI_MEM_CLKCNT_N_V 0xFF
#define SPI_MEM_CLKCNT_N_S 16
/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
/*description: In the mas... | 2,205 |
*/
#define SPI_MEM_USR_COMMAND (BIT(31))
#define SPI_MEM_USR_COMMAND_M (BIT(31))
#define SPI_MEM_USR_COMMAND_V 0x1
#define SPI_MEM_USR_COMMAND_S 31
/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: This bit enable the address phase of an operation.*/
#define SPI_MEM_USR_ADDR (BIT(30))
#defi... | 2,205 |
*/
#define SPI_MEM_USR_MOSI (BIT(27))
#define SPI_MEM_USR_MOSI_M (BIT(27))
#define SPI_MEM_USR_MOSI_V 0x1
#define SPI_MEM_USR_MOSI_S 27
/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: spi clock is disable in dummy phase when the bit is enable.*/
#define SPI_MEM_USR_DUMMY_IDLE (BIT(2... | 2,205 |
*/
#define SPI_MEM_FWRITE_QIO (BIT(15))
#define SPI_MEM_FWRITE_QIO_M (BIT(15))
#define SPI_MEM_FWRITE_QIO_V 0x1
#define SPI_MEM_FWRITE_QIO_S 15
/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: In the write operations address phase and read-data phase apply 2 signals.*/
#define SPI_MEM_FWR... | 2,205 |
*/
#define SPI_MEM_CK_OUT_EDGE (BIT(9))
#define SPI_MEM_CK_OUT_EDGE_M (BIT(9))
#define SPI_MEM_CK_OUT_EDGE_V 0x1
#define SPI_MEM_CK_OUT_EDGE_S 9
/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/
#define SPI_MEM_CS_SETUP ... | 2,205 |
The register
value shall be (cycle_num-1).*/
#define SPI_MEM_USR_DUMMY_CYCLELEN 0x000000FF
#define SPI_MEM_USR_DUMMY_CYCLELEN_M ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S))
#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0xFF
#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0
#define SPI_MEM_USER2_REG(i) (... | 2,205 |
The register value shall be (bit_num-1).*/
#define SPI_MEM_USR_MOSI_DBITLEN 0x000007FF
#define SPI_MEM_USR_MOSI_DBITLEN_M ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S))
#define SPI_MEM_USR_MOSI_DBITLEN_V 0x7FF
#define SPI_MEM_USR_MOSI_DBITLEN_S 0
#define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI_ME... | 2,205 |
*/
#define SPI_MEM_STATUS 0x0000FFFF
#define SPI_MEM_STATUS_M ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S))
#define SPI_MEM_STATUS_V 0xFFFF
#define SPI_MEM_STATUS_S 0
#define SPI_MEM_EXT_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x030)
/* SPI_MEM_EXT_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: The r... | 2,205 |
*/
#define SPI_MEM_SSUB_PIN (BIT(8))
#define SPI_MEM_SSUB_PIN_M (BIT(8))
#define SPI_MEM_SSUB_PIN_V 0x1
#define SPI_MEM_SSUB_PIN_S 8
/* SPI_MEM_FSUB_PIN : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: For SPI0 flash is connected to SUBPINs.*/
#define SPI_MEM_FSUB_PIN (BIT(7))
#define SPI_MEM_FSUB_PIN_M (BI... | 2,205 |
*/
#define SPI_MEM_TRANS_END (BIT(3))
#define SPI_MEM_TRANS_END_M (BIT(3))
#define SPI_MEM_TRANS_END_V 0x1
#define SPI_MEM_TRANS_END_S 3
/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: SPI CS1 pin enable 1: disable CS1 0: spi_mem_cs1 signal is from/to CS1 pin*/
#define SPI_MEM_CS1_DIS (BI... | 2,205 |
1: enable 0: disable.
The bit is the same with spi_mem_fread_qio.*/
#define SPI_MEM_FADDR_QUAD (BIT(8))
#define SPI_MEM_FADDR_QUAD_M (BIT(8))
#define SPI_MEM_FADDR_QUAD_V 0x1
#define SPI_MEM_FADDR_QUAD_S 8
/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: For SPI0 flash dout phase apply... | 2,205 |
The bit is the same with spi_mem_fread_dio.*/
#define SPI_MEM_FADDR_DUAL (BIT(5))
#define SPI_MEM_FADDR_DUAL_M (BIT(5))
#define SPI_MEM_FADDR_DUAL_V 0x1
#define SPI_MEM_FADDR_DUAL_S 5
/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: For SPI0 flash dout phase apply 2 signals. 1: enable ... | 2,205 |
*/
#define SPI_MEM_CACHE_FLASH_USR_CMD (BIT(2))
#define SPI_MEM_CACHE_FLASH_USR_CMD_M (BIT(2))
#define SPI_MEM_CACHE_FLASH_USR_CMD_V 0x1
#define SPI_MEM_CACHE_FLASH_USR_CMD_S 2
/* SPI_MEM_CACHE_USR_CMD_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: For SPI0 cache read flash with 4 bytes command 1: e... | 2,205 |
The register value shall be (bit_num-1).*/
#define SPI_MEM_SRAM_WDUMMY_CYCLELEN 0x000000FF
#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S))
#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V 0xFF
#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S 22
/* SPI_MEM_SRAM_OCT : R/W ;bit... | 2,205 |
The register value shall be (bit_num-1).*/
#define SPI_MEM_SRAM_ADDR_BITLEN 0x0000003F
#define SPI_MEM_SRAM_ADDR_BITLEN_M ((SPI_MEM_SRAM_ADDR_BITLEN_V)<<(SPI_MEM_SRAM_ADDR_BITLEN_S))
#define SPI_MEM_SRAM_ADDR_BITLEN_V 0x3F
#define SPI_MEM_SRAM_ADDR_BITLEN_S 14
/* SPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W ;bitpos:[13:6] ;... | 2,205 |
*/
#define SPI_MEM_USR_RD_SRAM_DUMMY (BIT(4))
#define SPI_MEM_USR_RD_SRAM_DUMMY_M (BIT(4))
#define SPI_MEM_USR_RD_SRAM_DUMMY_V 0x1
#define SPI_MEM_USR_RD_SRAM_DUMMY_S 4
/* SPI_MEM_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: For SPI0 In the spi sram mode it is the enable bit of dummy
ph... | 2,205 |
*/
#define SPI_MEM_CACHE_USR_SCMD_4BYTE (BIT(0))
#define SPI_MEM_CACHE_USR_SCMD_4BYTE_M (BIT(0))
#define SPI_MEM_CACHE_USR_SCMD_4BYTE_V 0x1
#define SPI_MEM_CACHE_USR_SCMD_4BYTE_S 0
#define SPI_MEM_SRAM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x044)
/* SPI_MEM_SDUMMY_OUT : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*... | 2,205 |
1: enable 0: disable.*/
#define SPI_MEM_SDOUT_OCT (BIT(19))
#define SPI_MEM_SDOUT_OCT_M (BIT(19))
#define SPI_MEM_SDOUT_OCT_V 0x1
#define SPI_MEM_SDOUT_OCT_S 19
/* SPI_MEM_SDIN_OCT : R/W ;bitpos:[18] ;default: 1'b0 ; */
/*description: For SPI0 sram din phase apply 8 signals. 1: enable 0: disable.*/
#define SPI_ME... | 2,205 |
1: enable 0: disable.
The bit is the same with spi_mem_usr_sram_qio.*/
#define SPI_MEM_SDOUT_QUAD (BIT(15))
#define SPI_MEM_SDOUT_QUAD_M (BIT(15))
#define SPI_MEM_SDOUT_QUAD_V 0x1
#define SPI_MEM_SDOUT_QUAD_S 15
/* SPI_MEM_SDIN_QUAD : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: For SPI0 sram din phase ap... | 2,205 |
The bit is the same with spi_mem_usr_sram_dio.*/
#define SPI_MEM_SADDR_DUAL (BIT(12))
#define SPI_MEM_SADDR_DUAL_M (BIT(12))
#define SPI_MEM_SADDR_DUAL_V 0x1
#define SPI_MEM_SADDR_DUAL_S 12
/* SPI_MEM_SDOUT_DUAL : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: For SPI0 sram dout phase apply 2 signals. 1: en... | 2,205 |
*/
#define SPI_MEM_SWB_MODE 0x000000FF
#define SPI_MEM_SWB_MODE_M ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S))
#define SPI_MEM_SWB_MODE_V 0xFF
#define SPI_MEM_SWB_MODE_S 2
/* SPI_MEM_SCLK_MODE : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1:
SPI cl... | 2,205 |
*/
#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF
#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S))
#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF
#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0
#define SPI_MEM_SRAM_DWR_CM... | 2,205 |
*/
#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF
#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S))
#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF
#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0
#define SPI_MEM_SRAM_CLK_RE... | 2,205 |
*/
#define SPI_MEM_SCLKCNT_H 0x000000FF
#define SPI_MEM_SCLKCNT_H_M ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S))
#define SPI_MEM_SCLKCNT_H_V 0xFF
#define SPI_MEM_SCLKCNT_H_S 8
/* SPI_MEM_SCLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
/*description: For SPI0 sram interface it must be equal to spi_mem_clkcnt_N.... | 2,205 |
1: enable 0: disable.*/
#define SPI_MEM_WAITI_EN (BIT(0))
#define SPI_MEM_WAITI_EN_M (BIT(0))
#define SPI_MEM_WAITI_EN_V 0x1
#define SPI_MEM_WAITI_EN_S 0
#define SPI_MEM_FLASH_SUS_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x09C)
/* SPI_MEM_FLASH_PES : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: program er... | 2,205 |
*/
#define SPI_MEM_FLASH_PES_COMMAND 0x000000FF
#define SPI_MEM_FLASH_PES_COMMAND_M ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S))
#define SPI_MEM_FLASH_PES_COMMAND_V 0xFF
#define SPI_MEM_FLASH_PES_COMMAND_S 9
/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[8:1] ;default: 8'h7a ; */
/*description: Progr... | 2,205 |
*/
#define SPI_MEM_FLASH_SUS (BIT(0))
#define SPI_MEM_FLASH_SUS_M (BIT(0))
#define SPI_MEM_FLASH_SUS_V 0x1
#define SPI_MEM_FLASH_SUS_S 0
#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x0A8)
/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
/*description: add extra dummy s... | 2,205 |
*/
#define SPI_MEM_TIMING_CLK_ENA (BIT(0))
#define SPI_MEM_TIMING_CLK_ENA_M (BIT(0))
#define SPI_MEM_TIMING_CLK_ENA_V 0x1
#define SPI_MEM_TIMING_CLK_ENA_S 0
#define SPI_MEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0AC)
/* SPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
/*description: the input... | 2,205 |
..*/
#define SPI_MEM_DINS_NUM 0x00000003
#define SPI_MEM_DINS_NUM_M ((SPI_MEM_DINS_NUM_V)<<(SPI_MEM_DINS_NUM_S))
#define SPI_MEM_DINS_NUM_V 0x3
#define SPI_MEM_DINS_NUM_S 16
/* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
/*description: the input signals are delayed by system clock cycles 0: delayed
... | 2,205 |
..*/
#define SPI_MEM_DIN5_NUM 0x00000003
#define SPI_MEM_DIN5_NUM_M ((SPI_MEM_DIN5_NUM_V)<<(SPI_MEM_DIN5_NUM_S))
#define SPI_MEM_DIN5_NUM_V 0x3
#define SPI_MEM_DIN5_NUM_S 10
/* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
/*description: the input signals are delayed by system clock cycles 0: delayed
b... | 2,205 |
..*/
#define SPI_MEM_DIN2_NUM 0x00000003
#define SPI_MEM_DIN2_NUM_M ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S))
#define SPI_MEM_DIN2_NUM_V 0x3
#define SPI_MEM_DIN2_NUM_S 4
/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
/*description: the input signals are delayed by system clock cycles 0: delayed
by... | 2,205 |
..*/
#define SPI_MEM_DOUTS_NUM 0x00000003
#define SPI_MEM_DOUTS_NUM_M ((SPI_MEM_DOUTS_NUM_V)<<(SPI_MEM_DOUTS_NUM_S))
#define SPI_MEM_DOUTS_NUM_V 0x3
#define SPI_MEM_DOUTS_NUM_S 16
/* SPI_MEM_DOUT7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
/*description: the output signals are delayed by system clock cycles 0: ... | 2,205 |
..*/
#define SPI_MEM_DOUT5_NUM 0x00000003
#define SPI_MEM_DOUT5_NUM_M ((SPI_MEM_DOUT5_NUM_V)<<(SPI_MEM_DOUT5_NUM_S))
#define SPI_MEM_DOUT5_NUM_V 0x3
#define SPI_MEM_DOUT5_NUM_S 10
/* SPI_MEM_DOUT4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
/*description: the output signals are delayed by system clock cycles 0: de... | 2,205 |
..*/
#define SPI_MEM_DOUT2_NUM 0x00000003
#define SPI_MEM_DOUT2_NUM_M ((SPI_MEM_DOUT2_NUM_V)<<(SPI_MEM_DOUT2_NUM_S))
#define SPI_MEM_DOUT2_NUM_V 0x3
#define SPI_MEM_DOUT2_NUM_S 4
/* SPI_MEM_DOUT1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
/*description: the output signals are delayed by system clock cycles 0: del... | 2,205 |
*/
#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000003
#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S))
#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x3
#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2
/* SPI_MEM_SPI_SMEM... | 2,205 |
..*/
#define SPI_MEM_SPI_SMEM_DIN7_NUM 0x00000003
#define SPI_MEM_SPI_SMEM_DIN7_NUM_M ((SPI_MEM_SPI_SMEM_DIN7_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN7_NUM_S))
#define SPI_MEM_SPI_SMEM_DIN7_NUM_V 0x3
#define SPI_MEM_SPI_SMEM_DIN7_NUM_S 14
/* SPI_MEM_SPI_SMEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
/*description: th... | 2,205 |
..*/
#define SPI_MEM_SPI_SMEM_DIN4_NUM 0x00000003
#define SPI_MEM_SPI_SMEM_DIN4_NUM_M ((SPI_MEM_SPI_SMEM_DIN4_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN4_NUM_S))
#define SPI_MEM_SPI_SMEM_DIN4_NUM_V 0x3
#define SPI_MEM_SPI_SMEM_DIN4_NUM_S 8
/* SPI_MEM_SPI_SMEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
/*description: the i... | 2,205 |
..*/
#define SPI_MEM_SPI_SMEM_DIN1_NUM 0x00000003
#define SPI_MEM_SPI_SMEM_DIN1_NUM_M ((SPI_MEM_SPI_SMEM_DIN1_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN1_NUM_S))
#define SPI_MEM_SPI_SMEM_DIN1_NUM_V 0x3
#define SPI_MEM_SPI_SMEM_DIN1_NUM_S 2
/* SPI_MEM_SPI_SMEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
/*description: the i... | 2,205 |
..*/
#define SPI_MEM_SPI_SMEM_DOUT3_NUM 0x00000003
#define SPI_MEM_SPI_SMEM_DOUT3_NUM_M ((SPI_MEM_SPI_SMEM_DOUT3_NUM_V)<<(SPI_MEM_SPI_SMEM_DOUT3_NUM_S))
#define SPI_MEM_SPI_SMEM_DOUT3_NUM_V 0x3
#define SPI_MEM_SPI_SMEM_DOUT3_NUM_S 6
/* SPI_MEM_SPI_SMEM_DOUT2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
/*description... | 2,205 |
..*/
#define SPI_MEM_SPI_SMEM_DOUT0_NUM 0x00000003
#define SPI_MEM_SPI_SMEM_DOUT0_NUM_M ((SPI_MEM_SPI_SMEM_DOUT0_NUM_V)<<(SPI_MEM_SPI_SMEM_DOUT0_NUM_S))
#define SPI_MEM_SPI_SMEM_DOUT0_NUM_V 0x3
#define SPI_MEM_SPI_SMEM_DOUT0_NUM_S 0
#define SPI_MEM_SPI_SMEM_AC_REG(i) (REG_SPI_MEM_BASE(i) + 0x0D0)
/* SPI_M... | 2,205 |
1: enable 0: disable.*/
#define SPI_MEM_SPI_SMEM_CS_HOLD (BIT(1))
#define SPI_MEM_SPI_SMEM_CS_HOLD_M (BIT(1))
#define SPI_MEM_SPI_SMEM_CS_HOLD_V 0x1
#define SPI_MEM_SPI_SMEM_CS_HOLD_S 1
/* SPI_MEM_SPI_SMEM_CS_SETUP : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: For spi0 spi cs is enable when spi is in prepa... | 2,205 |
*/
#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP (BIT(21))
#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_M (BIT(21))
#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_V 0x1
#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_S 21
/* SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:13] ;default: 8'b0 ; */
/*description: The delay number of data strobe whi... | 2,205 |
*/
#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS (BIT(4))
#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_M (BIT(4))
#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_V 0x1
#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_S 4
/* SPI_MEM_SPI_FMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: Set the bit to reorder tx data of the word in spi... | 2,205 |
*/
#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE 0x00000003
#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_M ((SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_V)<<(SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_S))
#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_V 0x3
#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_S 22
/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP : R... | 2,205 |
*/
#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN 0x000000FF
#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S))
#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V 0xFF
#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S 5
/* SPI_MEM_SPI_SMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: ... | 2,205 |
*/
#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP (BIT(2))
#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_M (BIT(2))
#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_V 0x1
#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_S 2
/* SPI_MEM_SPI_SMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: Set the bit to enable variable dummy cycle in sp... | 2,205 |
*/
#define SPI_MEM_DATE 0x0FFFFFFF
#define SPI_MEM_DATE_M ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S))
#define SPI_MEM_DATE_V 0xFFFFFFF
#define SPI_MEM_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_SPI_MEM_REG_H_ */
| 2,205 |
/*
*/
#pragma once
#define ADC1_GPIO1_CHANNEL 0
#define ADC1_CHANNEL_0_GPIO_NUM 1
#define ADC1_GPIO2_CHANNEL 1
#define ADC1_CHANNEL_1_GPIO_NUM 2
#define ADC1_GPIO3_CHANNEL 2
#define ADC1_CHANNEL_2_GPIO_NUM 3
#define ADC1_GPIO4_CHANNEL 3
#define ADC1_CHANNEL_3_GPIO_NUM 4
#define ADC1_GPIO5_CHA... | 2,207 |
/*
*/
#pragma once
#define DAC_GPIO17_CHANNEL DAC_CHAN_0
#define DAC_CHAN0_GPIO_NUM 17
#define DAC_CHANNEL_1_GPIO_NUM DAC_CHAN0_GPIO_NUM //`DAC_CHANNEL_1_GPIO_NUM` is defined for DAC legacy driver, indicating the first DAC channel.
#define DAC_GPIO18_CHANNEL DAC_CHAN_1
#define DAC_CHAN1_GPI... | 2,209 |
/*
*/
/*
*/
#pragma once
/* COMMON CAPS */
#define SOC_ADC_SUPPORTED 1
#define SOC_DAC_SUPPORTED 1
#define SOC_UART_SUPPORTED 1
#define SOC_TWAI_SUPPORTED 1
#define SOC_CP_DMA_SUPPORTED 1
#define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_GPTIMER_... | 2,210 |
< SAR ADC Module*/
#define SOC_ADC_RTC_CTRL_SUPPORTED 1
#define SOC_ADC_DIG_CTRL_SUPPORTED 1
#define SOC_ADC_ARBITER_SUPPORTED 1
#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
#define SOC_ADC_DIG_IIR_FILTER_UNIT_BINDED 1 //ADC filter is binded with the ADC unit
#define... | 2,210 |
< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval<= 4095 */
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
/*!< RTC */
#define SOC_ADC_RTC_MIN_BITWIDTH (13)
#define SOC_ADC_RTC_MAX_BITWIDTH (13)
/*!<... | 2,210 |
// On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
// Force hold is a new function of ESP32-S2
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// 0~46 valid except 22~25
#define SOC_GPIO_VALID_GPIO_MASK ... | 2,210 |
< 8 inward channels on each CPU core */
#define SOC_DEDIC_GPIO_ALLOW_REG_ACCESS (1) /*!< Allow access dedicated GPIO channel by register */
#define SOC_DEDIC_GPIO_HAS_INTERRUPT (1) /*!< Dedicated GPIO has its own interrupt source */
#define SOC_DEDIC_GPIO_OUT_AUTO_ENABLE (1) /*!< Dedicated GPIO output attribution i... | 2,210 |
< Intel 8080 LCD is supported */
#define SOC_LCD_I80_BUSES (1U) /*!< Only I2S0 has LCD mode */
#define SOC_LCD_I80_BUS_WIDTH (24) /*!< Intel 8080 bus width */
/* LEDC CAPS */
#define SOC_LEDC_HAS_TIMER_SPECIFIC_MUX (1)
#define SOC_LEDC_SUPPORT_APB_CLOCK (1)
#define SOC_LEDC_SUPPORT_REF_TICK ... | 2,210 |
< One RMT group */
#define SOC_RMT_TX_CANDIDATES_PER_GROUP 4 /*!< Number of channels that capable of Transmit in each group */
#define SOC_RMT_RX_CANDIDATES_PER_GROUP 4 /*!< Number of channels that capable of Receive in each group */
#define SOC_RMT_CHANNELS_PER_GROUP 4 /*!< Total 4 channels *... | 2,210 |
< Support set REF_TICK as the RMT clock source */
#define SOC_RMT_SUPPORT_APB 1 /*!< Support set APB as the RMT clock source */
#define SOC_RMT_CHANNEL_CLK_INDEPENDENT 1 /*!< Can select different source clock for each channel */
/* RTCIO CAPS */
#define SOC_RTCIO_PIN_COUNT 22
#define SOC_RT... | 2,210 |
= 2)
// Peripheral supports output given level during its "dummy phase"
// Only SPI1 supports this feature
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_SPI_SUPPORT_OCT 1
#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_4... | 2,210 |
<Hardware version of touch sensor */
#define SOC_TOUCH_SENSOR_NUM (15) /*!<15 Touch channels */
#define SOC_TOUCH_PROXIMITY_CHANNEL_NUM (3) /*!<Support touch proximity channel number. */
#define SOC_TOUCH_SAMPLER_NUM (1U) /*!< The sampler number in total, each sampler can be ... | 2,210 |
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