text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
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< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
/* SPIRAM CAPS */
#define SOC_SPIRAM_SUPPORTED 1
#define SOC_SPIRAM_XIP_SUPPORTED 1
/* USB CAPS */
#define SOC_USB_OTG_PERIPH_NUM (1U)
/* SHA CAPS */
/* Max amount of bytes... | 2,210 |
<Compatible to the old version of IDF */
#define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
#define SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP (1) /*!<Supports waking up from touch pad trigger */
#define SOC_PM_SUPPORT_WIFI_PD (1)
#define SOC_PM_SUPPORT_RTC_PERIPH_PD (1)
#define S... | 2,210 |
< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (1) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
/* Temperature Sensor CAPS */
#define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1)
/* WI-FI CAPS */
#define SOC_WIFI_HW_TSF (1) /*!< Support... | 2,210 |
0: external XTAL_32K 1: CLK from RTC pad X32P_C*/
uint32_t reserved24: 6;
uint32_t ctr_lv: 1; /*0: power down XTAL at high level 1: power down XTAL at low level*/
uint32_t ctr_en: 1;
};
uint32_t val;
} ext_xtl_co... | 2,211 |
Clear vld before set reg_ck8m_div_sel then set vld to actually switch the clk*/
uint32_t ck8m_div: 2; /*CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.*/
uint32_t enb_ck8m: 1; /*disable CK8M and CK8M_D256_OUT*/
u... | 2,211 |
0: XTAL div 4 1: CK8M*/
uint32_t ana_clk_rtc_sel: 2;
};
uint32_t val;
} clk_conf;
union {
struct {
uint32_t reserved0: 22;
uint32_t rtc_ana_clk_div_vld: 1; /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div ... | 2,211 |
0: no res 1: 6k 2: 4k 3: 2k*/
uint32_t sdio_en_initi: 1; /*0 to set init[1:0]=0*/
uint32_t sdio_dcurlim: 3; /*tune current limit threshold when tieh = 0. About 800mA/(8+d)*/
uint32_t sdio_modecurlim: 1; /*select current limit m... | 2,211 |
Only active when reg_sdio_force = 1*/
uint32_t drefh_sdio: 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
uint32_t xpd_sdio: 1;
};
uint32_t val;
} sdio_conf;
union {
struct {
uint32_t reserved0: ... | 2,211 |
Switch rtc main state*/
uint32_t rtc_touch_state_slp: 1; /*touch is in sleep state*/
uint32_t rtc_touch_state_done: 1; /*touch is done*/
uint32_t rtc_cocpu_state_start: 1; /*ulp/cocpu should start to work*/
uint32_t rtc_cocpu_state_switch... | 2,211 |
*/
uint32_t cocpu_sw_int_trigger: 1; /*trigger cocpu register interrupt*/
uint32_t reserved27: 5;
};
uint32_t val;
} cocpu_ctrl;
union {
struct {
uint32_t touch_sleep_cycles:16; /*sleep cycles for timer*/
... | 2,211 |
1: IIR ? 2: IIR 1/8 3: Jitter*/
uint32_t touch_filter_en: 1; /*touch filter enable*/
};
uint32_t val;
} touch_filter_ctrl;
union {
struct {
uint32_t usb_vrefh: 2;
uint32_t usb_vrefl: 2;
uint32_t ... | 2,211 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct spi_mem_dev_s {
union {
struct {
uint32_t reserved0: 17; /*reserved*/
uint32_t flash_pe: 1; /*In user mode it is set to indicate ... | 2,212 |
The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_dp: 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_... | 2,212 |
Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
uint32_t flash_wrsr: 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleare... | 2,212 |
*/
uint32_t flash_wren: 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_t flash_read: 1; /*Read flash enable. Read flash operat... | 2,212 |
Active low.*/
uint32_t tx_crc_en: 1; /*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
uint32_t reserved12: 1; /*reserved*/
uint32_t fastrd_mode: 1; /*This bit ena... | 2,212 |
1: enable 0: disable.*/
uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/
uint32_t wrsr_2b: 1; /*two bytes data will be written to status register when it is set. 1: enable 0: disa... | 2,212 |
*/
uint32_t cs_hold_dly_res:12; /*Delay cycles of resume Flash when resume Flash from standby mode is enable by spi clock.*/
uint32_t cs_hold_dly: 12; /*SPI fsm is delayed to idle by spi clock cycles.*/
uint32_t cs_dly_num: 2; ... | 2,212 |
*/
uint32_t cs_hold_time: 13; /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
uint32_t reserved26: 5; /*reserved*/
uint32_t sync_reset: 1; /*The FSM... | 2,212 |
1: enable 0: disable.*/
uint32_t cs_setup: 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/
uint32_t reserved8: 1; /*reserved*/
uint32_t ck_out_edge: 1; /*the bit combi... | 2,212 |
1: enable 0: disable.*/
uint32_t usr_mosi_highpart: 1; /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/
uint32_t usr_dummy_idle: 1; /*spi clock is disable in dummy phase when the bit is enable.... | 2,212 |
The register value shall be (cycle_num-1).*/
uint32_t reserved8: 18; /*reserved*/
uint32_t usr_addr_bitlen: 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/
};
uint32_t val;
} user1;
u... | 2,212 |
The register value shall be (bit_num-1).*/
uint32_t reserved11: 21; /*reserved*/
};
uint32_t val;
} miso_dlen;
union {
struct {
uint32_t status: 16; /*The value is stored when set spi_mem_flash_rdsr bit an... | 2,212 |
*/
uint32_t trans_end_en: 1; /*The bit is used to enable the intterrupt of SPI transmitting done.*/
uint32_t cs_pol: 2; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_mem_cs ^ spi_mem_master_... | 2,212 |
*/
union {
struct {
uint32_t req_en: 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/
uint32_t usr_cmd_4byte: 1; /*For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/
uint32_t flash... | 2,212 |
1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
uint32_t fdout_quad: 1; /*For SPI0 flash dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
uint32_t faddr_quad: 1; /*For S... | 2,212 |
*/
uint32_t usr_rd_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.*/
uint32_t cache_sram_usr_rcmd: 1; /*For SPI0 In the spi sram mode cache read sram for user define command.*/
uint32_t... | 2,212 |
The register value shall be (bit_num-1).*/
uint32_t reserved30: 2; /*reserved*/
};
uint32_t val;
} cache_sctrl;
union {
struct {
uint32_t sclk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS ina... | 2,212 |
1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
uint32_t scmd_dual: 1; /*For SPI0 sram cmd phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
uint32_t sdin_quad: 1; /*For... | 2,212 |
1: enable 0: disable.*/
uint32_t sdout_oct: 1; /*For SPI0 sram dout phase apply 8 signals. 1: enable 0: disable.*/
uint32_t saddr_oct: 1; /*For SPI0 sram address phase apply 4 signals. 1: enable 0: disable.*/
uint32_t scmd_... | 2,212 |
The register value shall be (bit_num-1).*/
};
uint32_t val;
} sram_drd_cmd;
union {
struct {
uint32_t usr_wr_cmd_value: 16; /*For SPI0 When cache mode is enable it is the write command value of command phase for sram.*/
uint32_t reserved16: ... | 2,212 |
So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
uint32_t reserved24: 7; /*reserved*/
uint32_t equ_sysclk: 1; /*For SPI0 sram interface 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/
};
... | 2,212 |
1: enable 0: disable.*/
uint32_t waiti_dummy: 1; /*The dummy phase enable when auto wait flash idle*/
uint32_t waiti_cmd: 8; /*The command to auto wait idle*/
uint32_t waiti_dummy_cyclelen: 8; /*The dummy cycl... | 2,212 |
*/
uint32_t flash_pes_command: 8; /*Program/Erase suspend command.*/
uint32_t reserved17: 15;
};
uint32_t val;
} flash_sus_ctrl;
union {
struct {
uint32_t flash_sus: 1; /*The status of flash suspe... | 2,212 |
..*/
uint32_t din1_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din2_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle ... | 2,212 |
..*/
uint32_t din7_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dins_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle ... | 2,212 |
..*/
uint32_t dout1_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout2_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle... | 2,212 |
..*/
uint32_t dout7_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t douts_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle... | 2,212 |
..*/
uint32_t spi_smem_din1_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_din2_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle ... | 2,212 |
..*/
uint32_t spi_smem_din7_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_dins_num: 3; /*the input signals are delayed by system clock cycles 0: input without delaye... | 2,212 |
..*/
uint32_t spi_smem_dout1_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_dout2_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle... | 2,212 |
1: enable 0: disable.*/
uint32_t spi_smem_cs_hold: 1; /*For spi0 spi cs keep low when spi is in done phase. 1: enable 0: disable.*/
uint32_t spi_smem_cs_setup_time:13; /*For spi0 (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem... | 2,212 |
*/
uint32_t spi_fmem_ddr_cmd_dis: 1; /*the bit is used to disable dual edge in command phase when ddr mode.*/
uint32_t spi_fmem_outminbytelen: 8; /*It is the minimum output data length in the panda device.*/
uint32_t spi_fmem_usr_ddr_dqs_thd: 8; ... | 2,212 |
*/
uint32_t spi_smem_ddr_rdat_swp: 1; /*Set the bit to reorder rx data of the word in spi ddr mode.*/
uint32_t spi_smem_ddr_wdat_swp: 1; /*Set the bit to reorder tx data of the word in spi ddr mode.*/
uint32_t spi_smem_ddr_cmd_dis: 1; ... | 2,212 |
1: Enable. 0: Disable.*/
uint32_t reserved1: 31; /*reserved*/
};
uint32_t val;
} clock_gate;
union {
struct {
uint32_t spi01_clk_sel: 2; /*When the digital system clock selects PLL clock and the frequency of PL... | 2,212 |
*/
uint32_t reserved28: 4; /*reserved*/
};
uint32_t val;
} date;
} spi_mem_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "invalid spi_mem_dev_t size");
#endif
extern spi_mem_dev_t SPIMEM0;
extern spi_mem_dev_t SPIMEM1;
#ifdef __cp... | 2,212 |
/*
*/
#ifndef _DPORT_ACCESS_H_
#define _DPORT_ACCESS_H_
#include
#ifdef __cplusplus
extern "C" {
#endif
// ESP32S2 is single core and does not have DPORT bug, so these macros are all same as the non-DPORT versions
#define DPORT_INTERRUPT_DISABLE()
#define DPORT_INTERRUPT_RESTORE()
/**
*/
void esp_dport_access_... | 2,213 |
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,214 |
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,216 |
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,217 |
0: XPD HALL is controlled by FSM in ULP-coprocessor*/
uint32_t hall_phase: 1; /*Reverse phase of hall sensor*/
uint32_t hall_phase_force: 1; /*1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor*/
};
... | 2,219 |
/*
*/
// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32S2.
#ifndef _SOC_UART_CHANNEL_H
#define _SOC_UART_CHANNEL_H
//UART channels
#define UART_GPIO43_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 43
#define UART_GPIO44_DIRECT_CHANNEL UART_NUM_0
#define UA... | 2,220 |
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** SYSTEM TIMER REGISTER */
/** Type of conf register
*/
typedef union {
struct {
/** clk_fo : R/W; bitpos: [0]; default: 0;
*/
uint32_t clk_fo: 1;
uint32_t ... | 2,221 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
/* Register Layout */
/* The TWAI peripheral's registers are 8bits, however the ESP32-S2 can only access
*/
typedef volatile struct twai_dev_s {
//Configuration and Control Registers
union {
struct {
uint32_t rm: 1... | 2,222 |
2 Release Receive Buffer */
uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */
uint32_t srr: 1; /* CMR.4 Self Reception Request */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} command_reg; ... | 2,222 |
8 Miss Status */
uint32_t reserved9: 23; /* Internal Reserved */
};
uint32_t val;
} status_reg; /* Address 0x0008 */
union {
struct {
uint32_t ri: 1; /* IR.0 Receive Interrupt */
uint32_t ti... | 2,222 |
0 Receive Interrupt Enable */
uint32_t tie: 1; /* IER.1 Transmit Interrupt Enable */
uint32_t eie: 1; /* IER.2 Error Interrupt Enable */
uint32_t doie: 1; /* IER.3 Data Overrun Interrupt Enable */
uint32_t reserved4:... | 2,222 |
7 Sampling*/
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} bus_timing_1_reg; /* Address 0x001C */
uint32_t reserved_20; /* Address 0x0020 (Output control not supported) */
uint32_t reserved_24; ... | 2,222 |
8 CLKOUT enable/disable */
uint32_t reserved9: 23; /* Internal Reserved */
};
uint32_t val;
} clock_divider_reg; /* Address 0x007C */
} twai_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes");... | 2,222 |
/*
*/
#pragma once
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** RMT_CH0DATA_REG register
*/
#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0)
/** RMT_CH0_DATA : RO; bitpos: [31:0]; default: 0;
*/
#define RMT_CH0_DATA 0xFFFFFFFFU
#define RMT_CH0_DATA_M (RMT_CH0_DATA_V 1, this field can be set to ... | 2,224 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct apb_saradc_dev_s {
union {
struct {
uint32_t start_force: 1;
uint32_t start: 1;
uint32_t reserved2: 1;
uint32_t work_... | 2,225 |
// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,227 |
#define ASSIST_DEBUG_BASE DR_REG_ASSIST_DEBUG_BASE
#define ASSIST_DEBUG_INTERRUPT_ENA ((ASSIST_DEBUG_BASE) +0x00)
#define ASSIST_DEBUG_INTERRUPT_RAW ((ASSIST_DEBUG_BASE) +0x04)
#define ASSIST_DEBUG_INTERRUPT_RLS ((ASSIST_DEBUG_BASE) +0x08)
#define ASSIST_DEBUG_INTERRUPT_CLR ... | 2,228 |
.20] : Loopback status.
** CINTLEVEL [27..24]: CINTLEVEL.
*/
#define DPORT_RECORD_PDEBUGINST_SZ_M ((DPORT_RECORD_PDEBUGINST_SZ_V)>DPORT_RECORD_PDEBUGINST_SZ_S) & DPORT_RECORD_PDEBUGINST_SZ_V)
#define DPORT_RECORD_PDEBUGINST_ISRC_M ((DPORT_RECORD_PDEBUGINST_ISRC_V)>DPORT_RECORD_PDEBUGINST_ISR... | 2,228 |
See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_CTL 0x04 /* Control transfer bubble */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ICM 0x08 /* I-cache miss (incl uncached miss) */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DCM 0x0C /* D-ca... | 2,228 |
*/
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLB 0x18 /* HW ITLB refill. The refill address and data are available on
DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG and DPORT_PRO_CPU_RECORD_PDEBUGL... | 2,228 |
The address and load data (before the conditional store) are available on the LS signals*/
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WXSR2LB 0x28 /* WSR/XSR to LBEGIN */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WSR2MMID 0x2C /* WSR to MMID */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWXSR 0x30 /* ... | 2,228 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/* USB IN EP Register block type */
typedef struct usb_in_ep_reg {
volatile uint32_t diepctl;
uint32_t reserved;
volatile uint32_t diepint;
uint32_t reserved1;
volatile uint32_t dieptsiz;
volatile uint32_t diepdma;
vola... | 2,230 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct rtc_i2c_dev_s {
union {
struct {
uint32_t period: 20; /*time period that scl = 0*/
uint32_t reserved20: 12;
};
uint32_t val;
} scl_low;
union ... | 2,231 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct spi_dev_s {
union {
struct {
uint32_t conf_bitlen:23; /*Define the spi_clk cycles of SPI_CONF state. Can be configured in CONF state.*/
uint32_t reserved23: 1; ... | 2,232 |
The bit is combined with spi_usr_prep_hold spi_usr_cmd_hold spi_usr_addr_hold spi_usr_dummy_hold spi_usr_din_hold spi_usr_dout_hold and spi_usr_hold_pol. Can be configured in CONF state.*/
uint32_t dummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi contro... | 2,232 |
*/
uint32_t fcmd_quad: 1; /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t fcmd_oct: 1; /*Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
... | 2,232 |
Can be configured in CONF state.*/
uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high 0 low. Can be configured in CONF state.*/
uint32_t reserved20: 1; /*reserved*/
uint32_t wp: 1; /... | 2,232 |
0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/
uint32_t clk_mode_13: 1; /*{CPOL CPHA} 1: support spi clk mode 1 and 3 first edg... | 2,232 |
Can be configured in CONF state.*/
uint32_t cs_hold_time: 13; /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.*/
uint32_t cs_delay_mode: 3; /*spi_cs signal is delayed by spi_clk . 0: zero 1:... | 2,232 |
Can be configured in CONF state.*/
uint32_t clkcnt_h: 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/
uint32_t clkcnt_n: 6; /*In the master mode it is the divider o... | 2,232 |
*/
uint32_t reserved1: 2; /*reserved*/
uint32_t qpi_mode: 1; /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/
uint32_t opi_mode: 1; /*Just for ... | 2,232 |
0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/
uint32_t ck_out_edge: 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/
uint32_t rd_byte_order: 1; /*In read-data (MISO) phase 1: big-endian 0: l... | 2,232 |
0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/
uint32_t sio: 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configure... | 2,232 |
Can be configured in CONF state.*/
uint32_t usr_addr_hold: 1; /*spi is hold at address state the bit are combined with spi_usr_hold_pol bit. Can be configured in CONF state.*/
uint32_t usr_cmd_hold: 1; /*spi is hold at command state the bit are combined wi... | 2,232 |
Can be configured in CONF state.*/
uint32_t usr_mosi: 1; /*This bit enable the write-data phase of an operation. Can be configured in CONF state.*/
uint32_t usr_miso: 1; /*This bit enable the read-data phase of an operation. Can be configured in C... | 2,232 |
*/
uint32_t reserved8: 19; /*reserved*/
uint32_t usr_addr_bitlen: 5; /*The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
};
uint32_t val;
} user1;
union {
struct ... | 2,232 |
The register value shall be (bit_num-1). Can be configured in CONF state.*/
uint32_t reserved23: 9; /*reserved*/
};
uint32_t val;
} miso_dlen;
union {
struct {
uint32_t cs0_dis: 1; /*SPI CS0 pin enable 1: disable CS... | 2,232 |
Can be configured in CONF state.*/
uint32_t ck_dis: 1; /*1: spi clk out disable 0: spi clk out enable. Can be configured in CONF state.*/
uint32_t master_cs_pol: 6; /*In the master mode the bits are the polarity of spi cs line the value is equival... | 2,232 |
Can be configured in CONF state.*/
uint32_t cd_data_set: 1; /*1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DOUT or SPI_DIN state. 0: spi_cd = spi_cd_idle_edge. Can be configured in CONF state.*/
uint32_t cd_dummy_set: 1; /*1: spi_cd = !spi_c... | 2,232 |
0: spi_cd = spi_cd_idle_edge. Can be configured in CONF state.*/
uint32_t cd_idle_edge: 1; /*The default value of spi_cd. Can be configured in CONF state.*/
uint32_t reserved27: 2; /*reserved*/
uint32_t ck_idle_edge: 1; ... | 2,232 |
Can not be changed by CONF_buf.*/
uint32_t int_rd_buf_done_en: 1; /*spi_slv_rd_buf Interrupt enable. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t int_wr_buf_done_en: 1; /*spi_slv_wr_buf Interrupt enable. 1: enable 0: disable. Can be configured i... | 2,232 |
0: Others. Can be configured in CONF state.*/
uint32_t reserved12: 11; /*reserved*/
uint32_t trans_cnt: 4; /*The operations counter in both the master mode and the slave mode.*/
uint32_t reserved27: 1; /*reserved*/
... | 2,232 |
0: not valid. Can be changed by CONF_buf.*/
uint32_t cmd_err_clr: 1; /*1: Clear spi_slv_cmd_err. 0: not valid. Can be changed by CONF_buf.*/
uint32_t no_qpi_en: 1; /*1: spi slave QPI mode is not supported. 0: spi slave QPI mode is supported.*/
... | 2,232 |
*/
uint32_t last_addr: 8; /*In the slave mode it is the value of address.*/
};
uint32_t val;
} slave1;
union {
struct {
uint32_t reserved0: 24; /*reserved*/
uint32_t wr_buf_done: 1; /*Th... | 2,232 |
Can not be changed by CONF_buf.*/
uint32_t seg_magic_err: 1; /*1: The recent magic value in CONF buffer is not right in master DMA seg-trans mode. 0: others.*/
uint32_t reserved26: 6; /*reserved*/
};
uint32_t val;
} slv_rdbuf_dlen;
... | 2,232 |
0: others*/
uint32_t wrbuf_bytelen_en: 1; /*1: spi_slv_data_bytelen stores data byte length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others*/
uint32_t dma_seg_magic_value: 4; /*The magic value of BM table in master DMA seg-trans.*/
... | 2,232 |
*/
uint32_t reserved4: 8; /*reserved*/
uint32_t mst_dma_rd_bytelen:20; /*Define the master DMA read byte length in non seg-trans or seg-trans mode. Invalid when spi_rx_eof_en is 0. Can be configured in CONF state..*/
};
uint32_t val;
} fsm... | 2,232 |
Can be configured in CONF state.*/
uint32_t hold_out_time: 3; /*set the hold cycles of output spi_hold signal when spi_hold_out_en is enable. Can be configured in CONF state.*/
uint32_t dma_seg_trans_done: 1; /*1: spi master DMA full-duplex/half-duplex seg-tran... | 2,232 |
*/
uint32_t ahbm_rst: 1; /*Reset spi dma ahb master.*/
uint32_t in_loop_test: 1; /*Set bit to test in link.*/
uint32_t out_loop_test: 1; /*Set bit to test out link.*/
uint32_t out_auto_wrback: 1; ... | 2,232 |
*/
uint32_t dma_tx_stop: 1; /*spi dma write data stop when in continue tx/rx mode.*/
uint32_t dma_continue: 1; /*spi dma continue tx/rx data.*/
uint32_t last_seg_pop_clr: 1; /*1: Clear spi_slv_seg_frt_pop_mask. 0 : others*/
... | 2,232 |
0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/
uint32_t infifo_full_clr: 1; /*1:Clear spi_dma_infifo_full_vld. 0: Do not control it.*/
uint32_t outfifo_empty_clr: 1; /*1:Clear spi_dma_outfifo_empty_vld. ... | 2,232 |
*/
uint32_t start: 1; /*Set the bit to start to use outlink descriptor.*/
uint32_t restart: 1; /*Set the bit to mount on new outlink descriptors.*/
uint32_t dma_tx_ena: 1; /*spi dma write data status bit.*/
... | 2,232 |
*/
uint32_t dma_rx_ena: 1; /*spi dma read data status bit.*/
};
uint32_t val;
} dma_in_link;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The enable bit for lack of enough inlink descriptors. Can be configured in CONF stat... | 2,232 |
Can be configured in CONF state.*/
uint32_t out_done: 1; /*The enable bit for completing usage of a outlink descriptor . Can be configured in CONF state.*/
uint32_t out_eof: 1; /*The enable bit for sending a packet to host done. Can be configured... | 2,232 |
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