repo_id
stringlengths 5
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stringlengths 4
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stringlengths 590
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tactcomplabs/xbgas-binutils-gdb
| 1,482
|
gas/testsuite/gas/arm/branch-reloc.s
|
@ Check that non-local branches with and without mode switching
@ produce the right relocations with appropriate in-place addends.
.syntax unified
.text
.arm
.global arm_glob_sym1
.global arm_glob_sym2
.global thumb_glob_sym1
.global thumb_glob_sym2
nop
.type arm_glob_sym1, %function
arm_glob_sym1:
bl thumb_glob_sym1
bl thumb_glob_sym2
bl thumb_sym1
bl arm_glob_sym1
bl arm_glob_sym2
bl arm_sym1
blx thumb_glob_sym1
blx thumb_glob_sym2
blx thumb_sym1
blx arm_glob_sym1
blx arm_glob_sym2
blx arm_sym1
nop
bx lr
.type arm_sym1, %function
arm_sym1:
nop
bx lr
.thumb
.thumb_func
.type thumb_sym1, %function
thumb_sym1:
bx lr
.type thumb_glob_sym1, %function
.thumb_func
.thumb
thumb_glob_sym1:
bx lr
.section foo,"ax"
@ Add some space to avoid confusing objdump output: as we are
@ producing a relocatable file, objdump may match an address to
@ the wrong symbol (as symbols in different sections may have the same
@ address in the object file).
.space 0x100
.type thumb_glob_sym2, %function
.thumb_func
.thumb
thumb_glob_sym2:
bl arm_glob_sym1
bl arm_glob_sym2
bl arm_sym2
bl thumb_glob_sym1
bl thumb_glob_sym2
bl thumb_sym2
blx arm_glob_sym1
blx arm_glob_sym2
blx arm_sym2
blx thumb_glob_sym1
blx thumb_glob_sym2
blx thumb_sym2
nop
bx lr
.type thumb_sym2, %function
thumb_sym2:
nop
bx lr
.arm
.type arm_sym2, %function
arm_sym2:
bx lr
.global arm_glob_sym2
.type arm_glob_sym2, %function
arm_glob_sym2:
bx lr
|
tactcomplabs/xbgas-binutils-gdb
| 1,606
|
gas/testsuite/gas/arm/mve-vcvt-bad.s
|
.macro cond1
.irp cond, eq, ne, gt, ge, lt, le
it \cond
vcvt\().f16.s16 q0, q1, #1
.endr
.endm
.syntax unified
.thumb
vcvt.f16.s16 q0, q1, #0
vcvt.f16.s16 q0, q1, #17
vcvt.f16.u16 q0, q1, #0
vcvt.f16.u16 q0, q1, #17
vcvt.s16.f16 q0, q1, #0
vcvt.s16.f16 q0, q1, #17
vcvt.u16.f16 q0, q1, #0
vcvt.u16.f16 q0, q1, #17
vcvt.f32.s32 q0, q1, #0
vcvt.f32.s32 q0, q1, #33
vcvt.f32.u32 q0, q1, #0
vcvt.f32.u32 q0, q1, #33
vcvt.s32.f32 q0, q1, #0
vcvt.s32.f32 q0, q1, #33
vcvt.u32.f32 q0, q1, #0
vcvt.u32.f32 q0, q1, #33
vcvt.f64.s64 q0, q1, #1
vcvt.f64.u64 q0, q1, #1
vcvt.s64.f64 q0, q1, #1
vcvt.u64.f64 q0, q1, #1
cond1
it eq
vcvteq.f16.s16 q0, q1, #1
vcvteq.f16.s16 q0, q1, #1
vpst
vcvteq.f16.s16 q0, q1, #1
vcvtt.f16.s16 q0, q1, #1
vpst
vcvt.f16.s16 q0, q1, #1
.macro cond2
.irp cond, eq, ne, gt, ge, lt, le
it \cond
vcvt\().f16.s16 q0, q1
.endr
.endm
cond2
vcvt.f64.s64 q0, q1
vcvt.f64.u64 q0, q1
vcvt.s64.f64 q0, q1
vcvt.u64.f64 q0, q1
it eq
vcvteq.u32.f32 q0, q1
vcvteq.u32.f32 q0, q1
vpst
vcvteq.u32.f32 q0, q1
vcvtt.u32.f32 q0, q1
vpst
vcvt.u32.f32 q0, q1
.macro cond3 mnem
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\mnem\().f16.f32 q0, q1
.endr
.endm
cond3 vcvtb
vcvtb.f16.f64 q0, q1
vcvtb.f64.f16 q0, q1
vcvtb.f32.f64 q0, q1
vcvtb.f64.f32 q0, q1
it eq
vcvtbeq.f16.f32 q0, q1
vcvtbeq.f16.f32 q0, q1
vpst
vcvtbeq.f16.f32 q0, q1
vcvtbt.f16.f32 q0, q1
vpst
vcvtb.f16.f32 q0, q1
cond3 vcvtt
vcvtt.f16.f64 q0, q1
vcvtt.f64.f16 q0, q1
vcvtt.f32.f64 q0, q1
vcvtt.f64.f32 q0, q1
it eq
vcvtteq.f16.f32 q0, q1
vcvtteq.f16.f32 q0, q1
vpst
vcvtteq.f16.f32 q0, q1
vcvttt.f16.f32 q0, q1
vpst
vcvtt.f16.f32 q0, q1
|
tactcomplabs/xbgas-binutils-gdb
| 1,079
|
gas/testsuite/gas/arm/neon-addressing-bad.s
|
.syntax unified
VLD1.8 {d0}, 1f
1:
VLD1.8 {D0}, R0
VLD1.8 {Q1}, R0
VLD1.8 {D0}, [PC]
VLD1.8 {D0}, [PC, #0]
VST1.8 {D0}, R0
VST1.8 {Q1}, R0
VST1.8 {D0}, [PC]
VST1.8 {D0}, [PC, #0]
VST1.8 {D0[]}, [R0]
VST2.8 {D0[], D2[]}, [R0]
VST3.16 {D0[], D1[], D2[]}, [R0]
VST4.32 {D0[], D1[], D2[], D3[]}, [R0]
VLD1.8 {Q0}, [R0, #8]
VLD1.8 {Q0}, [R0, #8]!
VLD1.8 {Q0}, [R0, R1]
VLD1.8 {Q0}, [R0, R1]!
.thumb
VLD1.8 {d0}, 2f
2:
VLD1.8 {D0}, R0
VLD1.8 {Q1}, R0
VLD1.8 {D0}, [PC]
VLD1.8 {D0}, [PC, #0]
VST1.8 {D0}, R0
VST1.8 {Q1}, R0
VST1.8 {D0}, [PC]
VST1.8 {D0}, [PC, #0]
VSHL.I8 d0, d0, #7
VSHL.I8 d0, d0, #8
VSHL.I16 d0, d0, #15
VSHL.I16 d0, d0, #16
VSHL.I32 d0, d0, #31
VSHL.I32 d0, d0, #32
VSHL.I64 d0, d0, #63
VSHL.I64 d0, d0, #64
VQSHL.S8 d0, d0, #7
VQSHL.S8 d0, d0, #8
VQSHL.S16 d0, d0, #15
VQSHL.S16 d0, d0, #16
VQSHL.S32 d0, d0, #31
VQSHL.S32 d0, d0, #32
VQSHL.S64 d0, d0, #63
VQSHL.S64 d0, d0, #64
VQSHLU.S8 d0, d0, #7
VQSHLU.S8 d0, d0, #8
VQSHLU.S16 d0, d0, #15
VQSHLU.S16 d0, d0, #16
VQSHLU.S32 d0, d0, #31
VQSHLU.S32 d0, d0, #32
VQSHLU.S64 d0, d0, #63
VQSHLU.S64 d0, d0, #64
|
tactcomplabs/xbgas-binutils-gdb
| 4,907
|
gas/testsuite/gas/arm/armv8-2-fp16-simd.s
|
.macro f16_dq_ifsu reg0 reg1 reg2
.irp op, vabd.f16, vmax.f16, vmin.f16
\op d\reg0, d\reg1, d\reg2
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_q_ifsu reg0 reg1 reg2
.irp op, vabdq.f16, vmaxq.f16, vminq.f16
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_dq_abs_neg reg0 reg1
.irp op, vabs.f16, vneg.f16
\op d\reg0, d\reg1
\op q\reg0, q\reg1
.endr
.endm
.macro f16_q_abs_neg reg0 reg1
.irp op, vabsq.f16, vnegq.f16
\op q\reg0, q\reg1
.endr
.endm
.macro f16_dq_fcmp reg0 reg1 reg2
.irp op, vacge.f16, vacgt.f16, vaclt.f16, vacle.f16, vceq.f16, vcge.f16, vcgt.f16, vcle.f16, vclt.f16
\op d\reg0, d\reg1, d\reg2
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_dq_fcmp_imm0 reg0 reg1
.irp op, vceq.f16, vcge.f16, vcgt.f16, vcle.f16, vclt.f16
\op d\reg0, d\reg1, #0
\op q\reg0, q\reg1, #0
.endr
.endm
.macro f16_q_fcmp reg0 reg1 reg2
.irp op, vacgeq.f16, vacgtq.f16, vacltq.f16, vacleq.f16, vceqq.f16, vcgeq.f16, vcgtq.f16, vcleq.f16, vcltq.f16
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_dq_addsub reg0 reg1 reg2
.irp op, vadd.f16, vsub.f16
\op d\reg0, d\reg1, d\reg2
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_q_addsub reg0 reg1 reg2
.irp op, vaddq.f16, vsubq.f16
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_dq_vmaxnm reg0 reg1 reg2
.irp op, vmaxnm.f16, vminnm.f16
\op d\reg0, d\reg1, d\reg2
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_dq_fmac reg0 reg1 reg2
.irp op, vfma.f16, vfms.f16
\op d\reg0, d\reg1, d\reg2
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_dq_fmacmaybe reg0 reg1 reg2
.irp op, vmla.f16, vmls.f16
\op d\reg0, d\reg1, d\reg2
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_dq_vrint reg0 reg1
.irp op, vrintz.f16, vrintx.f16, vrinta.f16, vrintn.f16, vrintp.f16, vrintm.f16
\op d\reg0, d\reg1
\op q\reg0, q\reg1
.endr
.endm
.macro f16_dq_recip reg0 reg1
.irp op, vrecpe.f16, vrsqrte.f16
\op d\reg0, d\reg1
\op q\reg0, q\reg1
.endr
.endm
.macro f16_q_recip reg0 reg1
.irp op, vrecpeq.f16, vrsqrteq.f16
\op q\reg0, q\reg1
.endr
.endm
.macro f16_dq_step reg0 reg1 reg2
.irp op, vrecps.f16, vrsqrts.f16
\op d\reg0, d\reg1, d\reg2
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_q_step reg0 reg1 reg2
.irp op, vrecpsq.f16, vrsqrtsq.f16
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_dq_cvt reg0 reg1
.irp op, vcvta.s16.f16, vcvtm.s16.f16, vcvtn.s16.f16, vcvtp.s16.f16, vcvta.u16.f16, vcvtm.u16.f16, vcvtn.u16.f16, vcvtp.u16.f16,
\op d\reg0, d\reg1
\op q\reg0, q\reg1
.endr
.endm
.macro f16_dq_cvtz reg0 reg1
.irp op, vcvt.s16.f16, vcvt.u16.f16, vcvt.f16.s16, vcvt.f16.u16,
\op d\reg0, d\reg1
\op q\reg0, q\reg1
.endr
.endm
.macro f16_dq_cvtz_fixed reg0 reg1 imm
.irp op, vcvt.s16.f16, vcvt.u16.f16, vcvt.f16.s16, vcvt.f16.u16,
\op d\reg0, d\reg1, #\imm
\op q\reg0, q\reg1, #\imm
.endr
.endm
.macro f16_dq op reg0 reg1 reg2
\op d\reg0, d\reg1, d\reg2
\op q\reg0, q\reg1, q\reg2
.endm
.macro f16_d op reg0 reg1 reg2
\op d\reg0, d\reg1, d\reg2
.endm
.macro f16_q op reg0 reg1 reg2
\op q\reg0, q\reg1, q\reg2
.endm
.macro f16_dq_2 op reg0 reg1
\op d\reg0, d\reg1
\op q\reg0, q\reg1
.endm
.macro f16_d_2 op reg0 reg1
\op d\reg0, d\reg1
.endm
.macro f16_q_2 op reg0 reg1
\op q\reg0, q\reg1
.endm
func:
# neon_dyadic_if_su
f16_dq_ifsu 2 4 14
f16_q_ifsu 0 8 14
f16_d vabd.f16 1 3 15
f16_d vabd.f16 0 1 8
# neon_abs_neg
f16_dq_abs_neg 0 8
f16_q_abs_neg 2 6
f16_d_2 vabs.f16 7 3
f16_d_2 vneg.f16 9 1
# neon_fcmp
f16_dq_fcmp 2 4 14
f16_q_fcmp 0 8 14
# neon_addsub_if_i
f16_dq_addsub 2 4 14
f16_q_addsub 0 8 14
# neon_vmaxnm
f16_dq_vmaxnm 2 4 14
# neon_fmac
f16_dq_fmac 2 4 14
# neon_mac_maybe_scalar
f16_dq_fmacmaybe 2 4 14
# vrint
f16_dq_vrint 4 14
# neon_dyadic_if_i_d
f16_d vpadd.f16 4 8 14
# neon_recip_est
f16_dq_recip 4 8
f16_q_recip 0 10
# neon_step
f16_dq_step 8 10 12
f16_q_step 2 0 4
# neon_dyadic_if_su_d
f16_d vpmax.f16 4 8 14
f16_d vpmin.f16 10 8 2
# neon_mul
f16_d vmul.f16 4 8 14
f16_d vmul.f16 7 0 1
f16_q vmul.f16 2 8 0
# neon_cvt
f16_dq_cvt 6 12
# neon_cvtz
f16_dq_cvtz 14, 0
# neon_cvtz_fixed
f16_dq_cvtz_fixed 14, 0, 3
# neon_fcmp_imm0
f16_dq_fcmp_imm0 14, 2
.macro f16_d_by_scalar op reg0 reg1 reg2 idx
\op d\reg0, d\reg1, d\reg2[\idx]
.endm
.macro f16_q_by_scalar op reg0 reg1 reg2 idx
\op q\reg0, q\reg1, d\reg2[\idx]
.endm
.macro f16_dq_fmacmaybe_by_scalar reg0 reg1 reg2 idx
.irp op, vmla.f16, vmls.f16
\op d\reg0, d\reg1, d\reg2[\idx]
\op q\reg0, q\reg1, d\reg2[\idx]
.endr
.endm
# neon_mul (by scalar)
f16_d_by_scalar vmul.f16 7 0 1 0
f16_d_by_scalar vmul.f16 4 8 6 2
f16_q_by_scalar vmul.f16 2 8 0 1
f16_q_by_scalar vmul.f16 2 8 7 3
# neon_mac_maybe_scalar (by scalar)
f16_dq_fmacmaybe_by_scalar 2 4 1 0
f16_dq_fmacmaybe_by_scalar 1 8 7 3
|
tactcomplabs/xbgas-binutils-gdb
| 1,202
|
gas/testsuite/gas/arm/vfma1.s
|
.eabi_attribute Tag_Advanced_SIMD_arch, 2
.eabi_attribute Tag_VFP_arch, 6
@VMLA
.inst 0xee000a00 @ VFP vmla.f32 s0,s0,s0
.inst 0xee000b00 @ VFP vmla.f64 d0,d0,d0
.inst 0xf2000d10 @ NEON vmla.f32 d0,d0,d0
.inst 0xf2000d50 @ NEON vmla.f32 q0,q0,q0
@VFMA new
.inst 0xeea00a00 @ VFP vfma.f32 s0,s0,s0
.inst 0xeea00b00 @ VFP vfma.f64 d0,d0,d0
.inst 0xf2000c10 @ NEON vfma.f32 d0,d0,d0
.inst 0xf2000c50 @ NEON vfma.f32 q0,q0,q0
@VMLS
.inst 0xee000a40 @ VFP vmls.F32 s0,s0,s0
.inst 0xee000b40 @ VFP vmls.F64 d0,d0,d0
.inst 0xf2200d10 @ NEON vmls.F32 d0,d0,d0
.inst 0xf2200d50 @ NEON vmls.F32 q0,q0,q0
@VFMS new
.inst 0xeea00a40 @ VFP vfms.F32 s0,s0,s0
.inst 0xeea00b40 @ VFP vfms.F64 d0,d0,d0
.inst 0xf2200c10 @ NEON vfms.F32 d0,d0,d0
.inst 0xf2200c50 @ NEON vfms.F32 q0,q0,q0
@VNMLA
.inst 0xee100a40 @ VFP vnmla.F32 s0,s0,s0
.inst 0xee100b40 @ VFP vnmla.F64 d0,d0,d0
@VFNMA new
.inst 0xee900a40 @ VFP vfnma.F32 s0,s0,s0
.inst 0xee900b40 @ VFP vfnma.F64 d0,d0,d0
@VNMLS
.inst 0xee100a00 @ VFP vnmls.F32 s0,s0,s0
.inst 0xee100b00 @ VFP vnmls.F64 d0,d0,d0
@VFNMS new
.inst 0xee900a00 @ VFP vfnms.F32 s0,s0,s0
.inst 0xee900b00 @ VFP vfnms.F64 d0,d0,d0
|
tactcomplabs/xbgas-binutils-gdb
| 3,646
|
gas/testsuite/gas/arm/inst.s
|
@ Test file for ARM/GAS -- basic instructions
.text
.align
mov r0, #0
mov r1, r2
mov r3, r4, lsl #3
mov r5, r6, lsr r7
mov r8, r9, asr r10
mov r11, r12, asl r13
mov r14, r15, rrx
moval a2, a3
moveq a3, a4
movne v1, v2
movlt v3, v4
movge v5, v6
movle v7, v8
movgt ip, sp
movcc r1, r2
movcs r1, r3
movmi r3, r6
movpl wr, sb
movvs r1, r8
movvc SB, r1, lsr #31
movhi r8, pc
movls PC, lr
movhs r9, r8
movul r1, r3
movs r0, r8
movuls r0, WR
add r0, r1, #10
add r2, r3, r4
add r5, r6, r7, asl #5
add r1, r2, r3, lsl r1
and r0, r1, #10
and r2, r3, r4
and r5, r6, r7, asl #5
and r1, r2, r3, lsl r1
eor r0, r1, #10
eor r2, r3, r4
eor r5, r6, r7, asl #5
eor r1, r2, r3, lsl r1
sub r0, r1, #10
sub r2, r3, r4
sub r5, r6, r7, asl #5
sub r1, r2, r3, lsl r1
adc r0, r1, #10
adc r2, r3, r4
adc r5, r6, r7, asl #5
adc r1, r2, r3, lsl r1
sbc r0, r1, #10
sbc r2, r3, r4
sbc r5, r6, r7, asl #5
sbc r1, r2, r3, lsl r1
rsb r0, r1, #10
rsb r2, r3, r4
rsb r5, r6, r7, asl #5
rsb r1, r2, r3, lsl r1
rsc r0, r1, #10
rsc r2, r3, r4
rsc r5, r6, r7, asl #5
rsc r1, r2, r3, lsl r1
orr r0, r1, #10
orr r2, r3, r4
orr r5, r6, r7, asl #5
orr r1, r2, r3, lsl r1
bic r0, r1, #10
bic r2, r3, r4
bic r5, r6, r7, asl #5
bic r1, r2, r3, lsl r1
mvn r0, #10
mvn r2, r4
mvn r5, r7, asl #5
mvn r1, r3, lsl r1
tst r0, #10
tst r2, r4
tst r5, r7, asl #5
tst r1, r3, lsl r1
teq r0, #10
teq r2, r4
teq r5, r7, asl #5
teq r1, r3, lsl r1
cmp r0, #10
cmp r2, r4
cmp r5, r7, asl #5
cmp r1, r3, lsl r1
cmn r0, #10
cmn r2, r4
cmn r5, r7, asl #5
cmn r1, r3, lsl r1
teqp r0, #10
teqp r2, r4
teqp r5, r7, asl #5
teqp r1, r3, lsl r1
cmnp r0, #10
cmnp r2, r4
cmnp r5, r7, asl #5
cmnp r1, r3, lsl r1
cmpp r0, #10
cmpp r2, r4
cmpp r5, r7, asl #5
cmpp r1, r3, lsl r1
tstp r0, #10
tstp r2, r4
tstp r5, r7, asl #5
tstp r1, r3, lsl r1
mul r0, r1, r2
muls r1, r2, r3
mulne r0, r1, r0
mullss r9, r8, r7
mla r1, r9, sl, fp
mlas r3, r4, r9, IP
mlalt r9, r8, r7, SP
mlages r4, r1, r3, LR
ldr r0, [r1]
ldr r1, [r1, r2]
ldr r2, [r3, r4]!
ldr r2, [r2, #32]
ldr r2, [r3, r4, lsr #8]
ldreq r4, [r5, r4, asl #9]!
ldrne r4, [r5], #6
ldrt r1, [r2], r3
ldr r2, [r4], r5, lsr #8
foo:
ldr r0, foo
ldrb r3, [r4]
ldrnebt r5, [r8]
str r0, [r1]
str r1, [r1, r2]
str r3, [r4, r3]!
str r2, [r2, #32]
str r2, [r3, r4, lsr #8]
streq r4, [r5, r4, asl #9]!
strne r4, [r5], #6
str r1, [r2], r3
strt r2, [r4], r5, lsr #8
str r1, bar
bar:
stralb r1, [r7]
strbt r2, [r0]
ldmia r0, {r1}
ldmeqib r2, {r3, r4, r5}
ldmalda r3, {r0-r15}^
ldmdb FP!, {r0-r8, SL}
ldmed r1, {r0, r1, r2}|0xf0
ldmfd r2, {r3, r4}+{r5, r6, r7, r8}
ldmea r3, 3
ldmfa r4, {r8, r9}^
stmia r0, {r1}
stmeqib r2, {r3, r4, r5}
stmalda r3, {r0-r15}^
stmdb r11!, {r0-r8, r10}
stmed r1, {r0, r1, r2}
stmfd r2, {r3, r4}
stmea r3, 3
stmfa r4, {r8, r9}^
swi 0x123456
swihs 0x33
bl _wombat
blpl hohum
b _wibble
ble testerfunc
mov r1, r2, lsl #2
mov r1, r2, lsl #0
mov r1, r2, lsl #31
mov r1, r2, lsl r3
mov r1, r2, lsr #2
mov r1, r2, lsr #31
mov r1, r2, lsr #32
mov r1, r2, lsr r3
mov r1, r2, asr #2
mov r1, r2, asr #31
mov r1, r2, asr #32
mov r1, r2, asr r3
mov r1, r2, ror #2
mov r1, r2, ror #31
mov r1, r2, ror r3
mov r1, r2, rrx
mov r1, r2, LSL #2
mov r1, r2, LSL #0
mov r1, r2, LSL #31
mov r1, r2, LSL r3
mov r1, r2, LSR #2
mov r1, r2, LSR #31
mov r1, r2, LSR #32
mov r1, r2, LSR r3
mov r1, r2, ASR #2
mov r1, r2, ASR #31
mov r1, r2, ASR #32
mov r1, r2, ASR r3
mov r1, r2, ROR #2
mov r1, r2, ROR #31
mov r1, r2, ROR r3
mov r1, r2, RRX
ldralt r1, [r2], r3
|
tactcomplabs/xbgas-binutils-gdb
| 1,159
|
gas/testsuite/gas/arm/mve-vaddsub.s
|
.syntax unified
.thumb
.macro all_qqq op
.irp op1, q0, q1, q2, q4, q7
.irp op2, q0, q1, q2, q4, q7
.irp op3, q0, q1, q2, q4, q7
\op \op1, \op2, \op3
.endr
.endr
.endr
.endm
.macro all_qqr op
.irp op1, q0, q1, q2, q4, q7
.irp op2, q0, q1, q2, q4, q7
.irp op3, r0, r1, r2, r4, r7, r8, r10, r12, r14
\op \op1, \op2, \op3
.endr
.endr
.endr
.endm
all_qqq vadd.i8
all_qqq vadd.i16
all_qqq vadd.i32
all_qqq vadd.f16
all_qqq vadd.f32
vpstt
vaddt.i8 q0, q1, q2
vaddt.i16 q1, q2, q4
vpstee
vaddt.i32 q2, q4, q5
vadde.f16 q0, q4, q6
vadde.f32 q4, q5, q7
all_qqq vsub.i8
all_qqq vsub.i16
all_qqq vsub.i32
all_qqq vsub.f16
all_qqq vsub.f32
vpste
vsubt.i8 q0, q1, q2
vsube.i16 q1, q2, q4
vpstte
vsubt.i32 q2, q7, q5
vsubt.f16 q1, q4, q6
vsube.f32 q4, q5, q7
all_qqr vadd.i8
all_qqr vadd.i16
all_qqr vadd.i32
all_qqr vadd.f16
all_qqr vadd.f32
vpstt
vaddt.i8 q0, q1, r10
vaddt.i16 q1, q2, r12
vpstee
vaddt.i32 q2, q4, r5
vadde.f16 q5, q4, r6
vadde.f32 q4, q5, r7
all_qqr vsub.i8
all_qqr vsub.i16
all_qqr vsub.i32
all_qqr vsub.f16
all_qqr vsub.f32
vpste
vsubt.i8 q0, q1, r10
vsube.i16 q1, q2, r11
vpstte
vsubt.i32 q2, q0, r5
vsubt.f16 q1, q4, r6
vsube.f32 q4, q5, r7
|
tactcomplabs/xbgas-binutils-gdb
| 1,179
|
gas/testsuite/gas/arm/cde-mve.s
|
.syntax unified
vcx1 p0, q0, #0
vcx1 p0, q0, #2048
vcx1 p0, q0, #1920
vcx1 p0, q0, #64
vcx1 p0, q0, #63
vcx1 p7, q0, #0
vcx1 p0, q7, #0
vcx1a p0, q0, #0
vcx1a p0, q0, #2048
vcx1a p0, q0, #1920
vcx1a p0, q0, #64
vcx1a p0, q0, #63
vcx1a p7, q0, #0
vcx1a p0, q7, #0
vptt.i8 eq, q0, q0
vcx1t p0, q0, #0
vcx1at p0, q0, #0
vcx2 p0, q0, q0, #0
vcx2 p0, q0, q0, #64
vcx2 p0, q0, q0, #60
vcx2 p0, q0, q0, #2
vcx2 p0, q0, q0, #1
vcx2 p7, q0, q0, #0
vcx2 p0, q7, q0, #0
vcx2 p0, q0, q7, #0
vcx2a p0, q0, q0, #0
vcx2a p0, q0, q0, #64
vcx2a p0, q0, q0, #60
vcx2a p0, q0, q0, #2
vcx2a p0, q0, q0, #1
vcx2a p7, q0, q0, #0
vcx2a p0, q7, q0, #0
vcx2a p0, q0, q7, #0
vptt.i8 eq, q0, q0
vcx2t p0, q0, q0, #0
vcx2at p0, q0, q0, #0
vcx3 p0, q0, q0, q0, #0
vcx3 p0, q0, q0, q0, #8
vcx3 p0, q0, q0, q0, #6
vcx3 p0, q0, q0, q0, #1
vcx3 p7, q0, q0, q0, #0
vcx3 p0, q7, q0, q0, #0
vcx3 p0, q0, q7, q0, #0
vcx3 p0, q0, q0, q7, #0
vcx3a p0, q0, q0, q0, #0
vcx3a p0, q0, q0, q0, #8
vcx3a p0, q0, q0, q0, #6
vcx3a p0, q0, q0, q0, #1
vcx3a p7, q0, q0, q0, #0
vcx3a p0, q7, q0, q0, #0
vcx3a p0, q0, q7, q0, #0
vcx3a p0, q0, q0, q7, #0
vptt.i8 eq, q0, q0
vcx3t p0, q0, q0, q0, #0
vcx3at p0, q0, q0, q0, #0
|
tactcomplabs/xbgas-binutils-gdb
| 1,725
|
gas/testsuite/gas/arm/mve-vqdmladh.s
|
.syntax unified
.thumb
.irp data, s8, s16
.irp op1, q0, q1, q2, q4, q7
.irp op2, q0, q1, q2, q4, q7
.irp op3, q0, q1, q2, q4, q7
vqdmladh.\data \op1, \op2, \op3
vqdmladhx.\data \op1, \op2, \op3
vqrdmladh.\data \op1, \op2, \op3
vqrdmladhx.\data \op1, \op2, \op3
.endr
.endr
.endr
.endr
.irp op2, q1, q2, q4, q7
.irp op3, q1, q2, q4, q7
vqdmladh.s32 q0, \op2, \op3
vqdmladhx.s32 q0, \op2, \op3
vqrdmladh.s32 q0, \op2, \op3
vqrdmladhx.s32 q0, \op2, \op3
.endr
.endr
.irp op2, q0, q2, q4, q7
.irp op3, q0, q2, q4, q7
vqdmladh.s32 q1, \op2, \op3
vqdmladhx.s32 q1, \op2, \op3
vqrdmladh.s32 q1, \op2, \op3
vqrdmladhx.s32 q1, \op2, \op3
.endr
.endr
.irp op2, q0, q1, q4, q7
.irp op3, q0, q1, q4, q7
vqdmladh.s32 q2, \op2, \op3
vqdmladhx.s32 q2, \op2, \op3
vqrdmladh.s32 q2, \op2, \op3
vqrdmladhx.s32 q2, \op2, \op3
.endr
.endr
.irp op2, q0, q1, q4, q7
.irp op3, q0, q1, q4, q7
vqdmladh.s32 q2, \op2, \op3
vqdmladhx.s32 q2, \op2, \op3
vqrdmladh.s32 q2, \op2, \op3
vqrdmladhx.s32 q2, \op2, \op3
.endr
.endr
.irp op2, q0, q1, q2, q7
.irp op3, q0, q1, q2, q7
vqdmladh.s32 q4, \op2, \op3
vqdmladhx.s32 q4, \op2, \op3
vqrdmladh.s32 q4, \op2, \op3
vqrdmladhx.s32 q4, \op2, \op3
.endr
.endr
.irp op2, q0, q1, q2, q4
.irp op3, q0, q1, q2, q4
vqdmladh.s32 q7, \op2, \op3
vqdmladhx.s32 q7, \op2, \op3
vqrdmladh.s32 q7, \op2, \op3
vqrdmladhx.s32 q7, \op2, \op3
.endr
.endr
vpstete
vqdmladht.s8 q0, q1, q2
vqdmladhe.s8 q0, q1, q2
vqdmladhxt.s16 q0, q1, q2
vqdmladhxe.s16 q0, q1, q2
vpstete
vqrdmladht.s32 q0, q1, q2
vqrdmladhe.s32 q0, q1, q2
vqrdmladhxt.s16 q0, q1, q2
vqrdmladhxe.s16 q0, q1, q2
vqdmladh.s32 q0, q0, q0
vqrdmladh.s32 q0, q0, q0
vqdmladh.s32 q0, q0, q1
vqrdmladh.s32 q1, q1, q2
vqdmladh.s32 q2, q3, q2
vqrdmladh.s32 q3, q4, q3
|
tactcomplabs/xbgas-binutils-gdb
| 1,687
|
gas/testsuite/gas/arm/armv8-ar+simd.s
|
.syntax unified
.arch_extension simd
.arm
vmaxnm.f32 d0, d0, d0
vmaxnm.f32 d16, d16, d16
vmaxnm.f32 d15, d15, d15
vmaxnm.f32 d31, d31, d31
vmaxnm.f32 q0, q0, q0
vmaxnm.f32 q8, q8, q8
vmaxnm.f32 q7, q7, q7
vmaxnm.f32 q15, q15, q15
vminnm.f32 d0, d0, d0
vminnm.f32 d16, d16, d16
vminnm.f32 d15, d15, d15
vminnm.f32 d31, d31, d31
vminnm.f32 q0, q0, q0
vminnm.f32 q8, q8, q8
vminnm.f32 q7, q7, q7
vminnm.f32 q15, q15, q15
vcvta.s32.f32 d0, d0
vcvtn.s32.f32 d16, d16
vcvtp.u32.f32 d15, d15
vcvtm.u32.f32 d31, d31
vcvta.s32.f32 q0, q0
vcvtn.s32.f32 q8, q8
vcvtp.u32.f32 q7, q7
vcvtm.u32.f32 q15, q15
vrinta.f32 d0, d0
vrintn.f32 d16, d16
vrintm.f32 d15, d15
vrintp.f32 d31, d31
vrintx.f32 d0, d31
vrintz.f32 d16, d15
vrinta.f32 q0, q0
vrintn.f32 q8, q8
vrintm.f32 q7, q7
vrintp.f32 q15, q15
vrintx.f32 q0, q15
vrintz.f32 q8, q7
.thumb
vmaxnm.f32 d0, d0, d0
vmaxnm.f32 d16, d16, d16
vmaxnm.f32 d15, d15, d15
vmaxnm.f32 d31, d31, d31
vmaxnm.f32 q0, q0, q0
vmaxnm.f32 q8, q8, q8
vmaxnm.f32 q7, q7, q7
vmaxnm.f32 q15, q15, q15
vminnm.f32 d0, d0, d0
vminnm.f32 d16, d16, d16
vminnm.f32 d15, d15, d15
vminnm.f32 d31, d31, d31
vminnm.f32 q0, q0, q0
vminnm.f32 q8, q8, q8
vminnm.f32 q7, q7, q7
vminnm.f32 q15, q15, q15
vcvta.s32.f32 d0, d0
vcvtn.s32.f32 d16, d16
vcvtp.u32.f32 d15, d15
vcvtm.u32.f32 d31, d31
vcvta.s32.f32 q0, q0
vcvtn.s32.f32 q8, q8
vcvtp.u32.f32 q7, q7
vcvtm.u32.f32 q15, q15
vrinta.f32 d0, d0
vrintn.f32 d16, d16
vrintm.f32 d15, d15
vrintp.f32 d31, d31
vrintx.f32 d0, d31
vrintz.f32 d16, d15
vrinta.f32 q0, q0
vrintn.f32 q8, q8
vrintm.f32 q7, q7
vrintp.f32 q15, q15
vrintx.f32 q0, q15
vrintz.f32 q8, q7
|
tactcomplabs/xbgas-binutils-gdb
| 4,056
|
gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s
|
@ LDC group relocation tests that are supposed to fail during encoding.
.text
@ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L
.macro ldctest load store cst
\load 0, c0, [r0, #:pc_g0:(f + \cst)]
\load 0, c0, [r0, #:pc_g1:(f + \cst)]
\load 0, c0, [r0, #:pc_g2:(f + \cst)]
\load 0, c0, [r0, #:sb_g0:(f + \cst)]
\load 0, c0, [r0, #:sb_g1:(f + \cst)]
\load 0, c0, [r0, #:sb_g2:(f + \cst)]
\store 0, c0, [r0, #:pc_g0:(f + \cst)]
\store 0, c0, [r0, #:pc_g1:(f + \cst)]
\store 0, c0, [r0, #:pc_g2:(f + \cst)]
\store 0, c0, [r0, #:sb_g0:(f + \cst)]
\store 0, c0, [r0, #:sb_g1:(f + \cst)]
\store 0, c0, [r0, #:sb_g2:(f + \cst)]
\load 0, c0, [r0, #:pc_g0:(f - \cst)]
\load 0, c0, [r0, #:pc_g1:(f - \cst)]
\load 0, c0, [r0, #:pc_g2:(f - \cst)]
\load 0, c0, [r0, #:sb_g0:(f - \cst)]
\load 0, c0, [r0, #:sb_g1:(f - \cst)]
\load 0, c0, [r0, #:sb_g2:(f - \cst)]
\store 0, c0, [r0, #:pc_g0:(f - \cst)]
\store 0, c0, [r0, #:pc_g1:(f - \cst)]
\store 0, c0, [r0, #:pc_g2:(f - \cst)]
\store 0, c0, [r0, #:sb_g0:(f - \cst)]
\store 0, c0, [r0, #:sb_g1:(f - \cst)]
\store 0, c0, [r0, #:sb_g2:(f - \cst)]
.endm
ldctest ldc stc 0x1
ldctest ldcl stcl 0x1
ldctest ldc2 stc2 0x1
ldctest ldc2l stc2l 0x1
ldctest ldc stc 0x808
ldctest ldcl stcl 0x808
ldctest ldc2 stc2 0x808
ldctest ldc2l stc2l 0x808
@ LDFS/STFS/LDFD/STFD/LDFE/STFE/LDFP/STFP
.fpu fpa
.macro fpa_test load store cst
\load f0, [r0, #:pc_g0:(f + \cst)]
\load f0, [r0, #:pc_g1:(f + \cst)]
\load f0, [r0, #:pc_g2:(f + \cst)]
\load f0, [r0, #:sb_g0:(f + \cst)]
\load f0, [r0, #:sb_g1:(f + \cst)]
\load f0, [r0, #:sb_g2:(f + \cst)]
\store f0, [r0, #:pc_g0:(f + \cst)]
\store f0, [r0, #:pc_g1:(f + \cst)]
\store f0, [r0, #:pc_g2:(f + \cst)]
\store f0, [r0, #:sb_g0:(f + \cst)]
\store f0, [r0, #:sb_g1:(f + \cst)]
\store f0, [r0, #:sb_g2:(f + \cst)]
\load f0, [r0, #:pc_g0:(f - \cst)]
\load f0, [r0, #:pc_g1:(f - \cst)]
\load f0, [r0, #:pc_g2:(f - \cst)]
\load f0, [r0, #:sb_g0:(f - \cst)]
\load f0, [r0, #:sb_g1:(f - \cst)]
\load f0, [r0, #:sb_g2:(f - \cst)]
\store f0, [r0, #:pc_g0:(f - \cst)]
\store f0, [r0, #:pc_g1:(f - \cst)]
\store f0, [r0, #:pc_g2:(f - \cst)]
\store f0, [r0, #:sb_g0:(f - \cst)]
\store f0, [r0, #:sb_g1:(f - \cst)]
\store f0, [r0, #:sb_g2:(f - \cst)]
.endm
fpa_test ldfs stfs 0x1
fpa_test ldfd stfd 0x1
fpa_test ldfe stfe 0x1
fpa_test ldfp stfp 0x1
fpa_test ldfs stfs 0x808
fpa_test ldfd stfd 0x808
fpa_test ldfe stfe 0x808
fpa_test ldfp stfp 0x808
@ FLDS/FSTS
.fpu vfp
.macro vfp_test load store reg cst
\load \reg, [r0, #:pc_g0:(f + \cst)]
\load \reg, [r0, #:pc_g1:(f + \cst)]
\load \reg, [r0, #:pc_g2:(f + \cst)]
\load \reg, [r0, #:sb_g0:(f + \cst)]
\load \reg, [r0, #:sb_g1:(f + \cst)]
\load \reg, [r0, #:sb_g2:(f + \cst)]
\store \reg, [r0, #:pc_g0:(f + \cst)]
\store \reg, [r0, #:pc_g1:(f + \cst)]
\store \reg, [r0, #:pc_g2:(f + \cst)]
\store \reg, [r0, #:sb_g0:(f + \cst)]
\store \reg, [r0, #:sb_g1:(f + \cst)]
\store \reg, [r0, #:sb_g2:(f + \cst)]
\load \reg, [r0, #:pc_g0:(f - \cst)]
\load \reg, [r0, #:pc_g1:(f - \cst)]
\load \reg, [r0, #:pc_g2:(f - \cst)]
\load \reg, [r0, #:sb_g0:(f - \cst)]
\load \reg, [r0, #:sb_g1:(f - \cst)]
\load \reg, [r0, #:sb_g2:(f - \cst)]
\store \reg, [r0, #:pc_g0:(f - \cst)]
\store \reg, [r0, #:pc_g1:(f - \cst)]
\store \reg, [r0, #:pc_g2:(f - \cst)]
\store \reg, [r0, #:sb_g0:(f - \cst)]
\store \reg, [r0, #:sb_g1:(f - \cst)]
\store \reg, [r0, #:sb_g2:(f - \cst)]
.endm
vfp_test flds fsts s0 0x1
vfp_test flds fsts s0 0x808
@ FLDD/FSTD
vfp_test fldd fstd d0 0x1
vfp_test fldd fstd d0 0x808
@ VLDR/VSTR
vfp_test vldr vstr d0 0x1
vfp_test vldr vstr d0 0x808
@ CFLDRS/CFLDRD/CFLDR32/CFLDR64/CFSTRS/CFSTRD/CFSTR32/CFSTR64
.cpu ep9312
vfp_test cfldrs cfstrs mvf0 0x1
vfp_test cfldrd cfstrd mvd0 0x1
vfp_test cfldr32 cfstr32 mvfx0 0x1
vfp_test cfldr64 cfstr64 mvdx0 0x1
vfp_test cfldrs cfstrs mvf0 0x808
vfp_test cfldrd cfstrd mvd0 0x808
vfp_test cfldr32 cfstr32 mvfx0 0x808
vfp_test cfldr64 cfstr64 mvdx0 0x808
|
tactcomplabs/xbgas-binutils-gdb
| 2,348
|
gas/testsuite/gas/arm/armv8-2-fp16-scalar-bad.s
|
.macro f16_sss_arithmetic reg0, reg1, reg2
.irp op, vdiv, vfma, vfms, vfnma, vfnms, vmla, vmls, vmul, vnmla, vnmls, vnmul, vsub
.irp cond, eq.f16, ne.f16, ge.f16, lt.f16, gt.f16, le.f16
\op\cond s\reg0, s\reg1, s\reg2
.endr
.endr
.endm
.macro f16_ss_arithmetic reg0, reg1
.irp op, vabs, vadd, vsqrt, vneg
.irp cond, eq.f16, ne.f16, ge.f16, lt.f16, gt.f16, le.f16
\op\cond s\reg0, s\reg1
.endr
.endr
.endm
.macro f16_si_cmp reg0, imm
.irp op, vcmp, vcmpe
.irp cond, eq.f16, ne.f16, ge.f16, lt.f16, gt.f16, le.f16
\op\cond s\reg0, \imm
.endr
.endr
.endm
.macro f16_ss_cmp reg0, reg1
.irp op, vcmp, vcmpe
.irp cond, eq.f16, ne.f16, ge.f16, lt.f16, gt.f16, le.f16
\op\cond s\reg0, s\reg1
.endr
.endr
.endm
.macro f16_ss_cvt reg0, reg1
.irp cond, eq, ne, ge, lt, gt, le
.irp mode, .s32.f16, .u32.f16, .f16.s32, .f16.u32
vcvt\cond\mode s\reg0, s\reg1
.endr
.endr
.endm
.macro f16_ssi_cvt_imm32 reg0, reg1, imm
.irp cond, eq, ne, ge, lt, gt, le
.irp mode, .s32.f16, .u32.f16, .f16.s32, .f16.u32
vcvt\cond\mode s\reg0, s\reg1, \imm
.endr
.endr
.endm
.macro f16_ss_cvt_r reg0, reg1
.irp cond, eq, ne, ge, lt, gt, le
.irp mode, .s32.f16, .u32.f16
vcvtr\cond\mode s\reg0, s\reg1
.endr
.endr
.endm
.macro f16_ss_vrint reg0, reg1
.irp op, vrintr, vrintx, vrintz
.irp cond, eq.f16, ne.f16, ge.f16, lt.f16, gt.f16, le.f16
\op\cond s\reg0, s\reg1
.endr
.endr
.endm
.macro f16_ss_mov reg0, reg1
.irp op, vins, vmovx
.irp cond, eq.f16, ne.f16, ge.f16, lt.f16, gt.f16, le.f16
\op\cond s\reg0, s\reg1
.endr
.endr
.endm
.macro t_f16_ss_mov reg0, reg1
.irp op, vins, vmovx
.irp cond, eq, ne, ge, lt, gt, le
.irp mode, .f16
it \cond
\op\cond\mode s\reg0, s\reg1
.endr
.endr
.endr
.endm
.text
@ invalied immediate range
vldr.16 s6, [pc, #-511]
vldr.16 s6, [pc, #111]
vldr.16 s3, [pc, #511]
@ invalid immediate range
vcvt.s32.f16 s11, s11, #33
vcvt.u32.f16 s11, s11, #0
vcvt.f16.s32 s12, s12, #34
vcvt.f16.u32 s12, s12, #-1
@ armv8.2 fp16 scalar instruction cannot be conditional
f16_sss_arithmetic 0, 1, 2
f16_ss_arithmetic 0, 1
f16_si_cmp 2, #0.0
f16_ss_cmp 0, 1
f16_ss_cvt 1, 8
f16_ssi_cvt_imm32 2, 2, #29
f16_ss_cvt_r 0, 10
f16_ss_vrint 3, 11
f16_ss_mov 0, 1
.syntax unified
.thumb
t_f16_ss_mov 0, 1
|
tactcomplabs/xbgas-binutils-gdb
| 1,892
|
gas/testsuite/gas/arm/neon-omit.s
|
@ test omitted optional arguments
.text
.arm
.syntax unified
vabd.u8 q1,q3
vhadd.s32 q14, q3
vrhadd.s32 q1,q2
vhsub.s32 q5,q7
vshl.u16 q3,q4
vqshl.u32 q5,q6
vand.64 q7,q8
veor.64 q7,q8
vceq.i16 q5,#0
vceq.i16 q5,q5
vclt.s16 q5,#0
vabs.s16 q5,q6
vneg.s16 d7,d8
vabs.f d7,d8
vneg.f q9,q10
vpmax.s32 d1,d3
vpmin.s32 d5,d7
vpmax.f32 d1,d3
vpmin.f32 d5,d7
vqdmulh.s16 q1,q3
vqrdmulh.s32 d5,d7
vqdmulh.s16 q1,d5[3]
vqadd.s16 q1,q3
vqadd.s32 d5,d7
vmla.i32 q1,q2
vpadd.i16 d3,d4
vmls.s32 q3,q4
vacge.f q1,q2
vacgt.f q3,q4
vacle.f q5,q6
vaclt.f q7,q8
vcge.u32 q7,q8
vcgt.u32 q7,q8
vcle.u32 q7,q8
vclt.u32 q7,q8
vaddw.u32 q1,d2
vsubw.s32 q3,d4
vtst.i32 q2,q3
vrecps.f d1,d2
vshr.s16 q1,#4
vrshr.s8 q2,#5
vsra.u16 q3,#6
vrsra.u16 q4,#6
vsli.16 q2,#5
vqshlu.s64 d15,#63
vext.8 d5,d6,#3
@ Also test three-argument forms without omitted arguments
vabd.u8 q1,q2,q3
vhadd.s32 q14,q9,q3
vrhadd.s32 q1,q5,q2
vhsub.s32 q5,q8,q7
vshl.u16 q3,q4,q5
vqshl.u32 q5,q6,q1
vand.64 q7,q8,q6
veor.64 q7,q8,q6
vceq.i16 q5,q3,#0
vceq.i16 q5,q3,q5
vclt.s16 q5,q3,#0
vpmax.s32 d1,d3,d16
vpmin.s32 d5,d7,d20
vpmax.f32 d1,d3,d7
vpmin.f32 d5,d12,d7
vqdmulh.s16 q1,q3,q8
vqrdmulh.s32 d5,d7,d9
vqdmulh.s16 q1,q6,d5[3]
vqadd.s16 q1,q11,q3
vqadd.s32 d5,d7,d31
vmla.i32 q1,q2,q9
vpadd.i16 d3,d26,d4
vmls.s32 q3,q4,q5
vacge.f q1,q4,q2
vacgt.f q3,q1,q4
vacle.f q5,q9,q6
vaclt.f q7,q1,q8
vcge.u32 q7,q8,q3
vcgt.u32 q7,q8,q3
vcle.u32 q7,q8,q3
vclt.u32 q7,q8,q3
vaddw.u32 q1,q5,d2
vsubw.s32 q3,q1,d4
vtst.i32 q2,q11,q3
vrecps.f d1,d30,d2
vshr.s16 q1,q13,#4
vrshr.s8 q2,q9,#5
vsra.u16 q3,q1,#6
vrsra.u16 q15,q4,#6
vsli.16 q2,q3,#5
vqshlu.s64 d15,d23,#63
vext.8 d5,d18,d6,#3
@ Also test VMOV with omitted suffix:
vmov d0[0], r0
vmov r0, d0[0]
@ PR 11136 - this used to crash the assembler.
vmul.f32 q0,q1,q2
|
tactcomplabs/xbgas-binutils-gdb
| 1,028
|
gas/testsuite/gas/arm/req.s
|
.text
.global test_dot_req_and_unreq
test_dot_req_and_unreq:
# Check that builtin register alias 'r0' works.
add r0, r0, r0
# Create an alias for r0.
foo .req r0
# Check that it works.
add foo, foo, foo
# Now remove the alias.
.unreq foo
# And make sure that it no longer works.
add foo, foo, foo
# Attempt to remove the builtin alias for r0.
.unreq r0
# That is ignored, so this should still work.
add r0, r0, r0
# Now attempt to re-alias foo. There used to be a bug whereby the
# first creation of an alias called foo would also create an alias
# called FOO, but the .unreq of foo would not delete FOO. Thus a
# second attempt at aliasing foo (to something different than
# before) would fail because the assembler would complain that FOO
# already existed.
foo .req r1
add foo, foo, foo
# Check that the upper case alias was also recreated.
add FOO, FOO, FOO
# Check that a second attempt to alias foo, using a mixed case
# version of the name, will fail.
Foo .req r2
|
tactcomplabs/xbgas-binutils-gdb
| 11,472
|
gas/testsuite/gas/arm/cde-warnings.s
|
.syntax unified
# cx1{a}
# Immediate out of range.
# Each register out of range.
# r13 => constrained unpredictable
# itblock => constrained unpredictable
# Error given when using coprocessor number not enabled on command line.
# Too many arguments
# Too little arguments
# r15 instead of APSR_nzcv
cx1 p0, r0, #8192
cx1a p0, r0, #8192
cx1 p0, r0, #-1
cx1a p0, r0, #-1
cx1 p8, r0, #0
cx1a p8, r0, #0
cx1 p0, r16, #0
cx1a p0, r16, #0
cx1 p0, r13, #0
cx1a p0, r13, #0
itttt ne
cx1 p0, r0, #0
cx1ne p0, r0, #0
cx1a p0, r0, #0
cx1aeq p0, r0, #0
cx1 p1, r0, #0
cx1a p1, r0, #0
cx1 p0, r0, r0, #0
cx1a p0, r0, r0, #0
cx1 p0, #0
cx1a p0, #0
cx1 p0, r15, #0
cx1a p0, r15, #0
# cx1d{a}
# Immediate out of range.
# Each register out of range.
# APSR_nzcv disallowed as destination register.
# rd<odd> => constrained unpredictable
# r< N > 10 > => constrained unpredictable
# IT block => constrained unpredictable
#
# Error given when using coprocessor number not enabled on command line.
# Disallow non-incrementing values in destination.
# Too many arguments
# Too little arguments
cx1d p0, r0, r1, #8192
cx1da p0, r0, r1, #8192
cx1d p0, r0, r1, #-1
cx1da p0, r0, r1, #-1
cx1d p8, r0, r1, #0
cx1da p8, r0, r1, #0
cx1d p0, r16, r17, #0
cx1da p0, r16, r17, #0
cx1d p0, APSR_nzcv, r15, #0
cx1da p0, APSR_nzcv, r15, #0
cx1d p0, r9, r10, #0
cx1da p0, r9, r10, #0
cx1d p0, r13, r14, #0
cx1da p0, r13, r14, #0
itttt ne
cx1d p0, r0, r1, #0
cx1da p0, r0, r1, #0
cx1dne p0, r0, r1, #0
cx1daeq p0, r0, r1, #0
cx1d p1, r0, r1, #0
cx1da p1, r0, r1, #0
cx1d p0, r0, r2, #0
cx1da p0, r0, r2, #0
cx1d p0, r0, r1, r0, #0
cx1da p0, r0, r1, r0, #0
cx1d p0, r0, #0
cx1da p0, r0, #0
# cx2{a}
# Immediate out of range.
# Each register out of range.
# rd13 => constrained unpredictable
# rn13 => constrained unpredictable
# IT block => constrained unpredictable
#
# Error given when using coprocessor number not enabled on command line.
# Too many arguments
# Too little arguments.
# r15 instead of APSR_nzcv
cx2 p0, r0, r0, #512
cx2a p0, r0, r0, #512
cx2 p0, r0, r0, #-1
cx2a p0, r0, r0, #-1
cx2 p8, r0, r0, #0
cx2a p8, r0, r0, #0
cx2 p0, r16, r0, #0
cx2a p0, r16, r0, #0
cx2 p0, r0, r16, #0
cx2a p0, r0, r16, #0
cx2 p0, r13, r0, #0
cx2a p0, r13, r0, #0
cx2 p0, r0, r13, #0
cx2a p0, r0, r13, #0
itttt ne
cx2 p0, r0, r0, #0
cx2a p0, r0, r0, #0
cx2ne p0, r0, r0, #0
cx2aeq p0, r0, r0, #0
cx2 p1, r0, r0, #0
cx2a p1, r0, r0, #0
cx2 p0, r0, r0, r0, #0
cx2a p0, r0, r0, r0, #0
cx2 p0, r0, #0
cx2a p0, r0, #0
cx2 p0, r0, r15, #0
cx2a p0, r0, r15, #0
cx2 p0, r15, r0, #0
cx2a p0, r15, r0, #0
# cx2d{a}
# Immediate out of range.
# Each register out of range.
# APSR_nzcv disallowed as destination register.
# rd<odd> => constrained unpredictable
# rd< N > 10 > => constrained unpredictable
# rn13 => constrained unpredictable
# IT block => constrained unpredictable
#
# Error given when using coprocessor number not enabled on command line.
# Disallow non-incrementing values in destination.
# Too many arguments
# Too little arguments
cx2d p0, r0, r1, r0, #512
cx2da p0, r0, r1, r0, #512
cx2d p0, r0, r1, r0, #-1
cx2da p0, r0, r1, r0, #-1
cx2d p8, r0, r1, r0, #0
cx2da p8, r0, r1, r0, #0
cx2d p0, r16, r17, r0, #0
cx2da p0, r16, r17, r0, #0
cx2d p0, r0, r1, r16, #0
cx2da p0, r0, r1, r16, #0
cx2d p0, APSR_nzcv, r15, r0, #0
cx2da p0, APSR_nzcv, r15, r0, #0
cx2d p0, r9, r10, r0, #0
cx2da p0, r9, r10, r0, #0
cx2d p0, r12, r13, r0, #0
cx2da p0, r12, r13, r0, #0
cx2d p0, r0, r1, r13, #0
cx2da p0, r0, r1, r13, #0
cx2d p0, r0, r1, r15, #0
cx2da p0, r0, r1, r15, #0
itttt ne
cx2d p0, r0, r1, r0, #0
cx2da p0, r0, r1, r0, #0
cx2dne p0, r0, r1, r0, #0
cx2daeq p0, r0, r1, r0, #0
cx2d p1, r0, r1, r0, #0
cx2da p1, r0, r1, r0, #0
cx2d p0, r0, r2, r0, #0
cx2da p0, r0, r2, r0, #0
cx2d p0, r0, r1, r0, r0, #0
cx2da p0, r0, r1, r0, r0, #0
cx2d p0, r0, r0, #0
cx2da p0, r0, r0, #0
# cx2{a}
# Immediate out of range.
# Each register out of range.
# rd13 => constrained unpredictable
# rn13 => constrained unpredictable
# rm13 => constrained unpredictable
# IT block => constrained unpredictable
#
# Error given when using coprocessor number not enabled on command line.
# Too many arguments
# Too little arguments.
# r15 instead of APSR_nzcv
cx3 p0, r0, r0, r0, #64
cx3a p0, r0, r0, r0, #64
cx3 p0, r0, r0, r0, #-1
cx3a p0, r0, r0, r0, #-1
cx3 p8, r0, r0, r0, #0
cx3a p8, r0, r0, r0, #0
cx3 p0, r16, r0, r0, #0
cx3a p0, r16, r0, r0, #0
cx3 p0, r0, r16, r0, #0
cx3a p0, r0, r16, r0, #0
cx3 p0, r0, r0, r16, #0
cx3a p0, r0, r0, r16, #0
cx3 p0, r13, r0, r0, #0
cx3a p0, r13, r0, r0, #0
cx3 p0, r0, r13, r0, #0
cx3a p0, r0, r13, r0, #0
cx3 p0, r0, r0, r13, #0
cx3a p0, r0, r0, r13, #0
itttt ne
cx3 p0, r0, r0, r0, #0
cx3a p0, r0, r0, r0, #0
cx3ne p0, r0, r0, r0, #0
cx3aeq p0, r0, r0, r0, #0
cx3 p1, r0, r0, r0, #0
cx3a p1, r0, r0, r0, #0
cx3 p0, r0, r0, r0, r0, #0
cx3a p0, r0, r0, r0, r0, #0
cx3 p0, r0, r0, #0
cx3a p0, r0, r0, #0
cx3 p0, r15, r0, r0, #0
cx3a p0, r15, r0, r0, #0
cx3 p0, r0, r15, r0, #0
cx3a p0, r0, r15, r0, #0
cx3 p0, r0, r0, r15, #0
cx3a p0, r0, r0, r15, #0
# cx3d{a}
# Immediate out of range.
# Each register out of range.
# APSR_nzcv disallowed as destination register.
# rd<odd> => constrained unpredictable
# rd< N > 10 > => constrained unpredictable
# rn13 => constrained unpredictable
# rm13 => constrained unpredictable
# rn15 disallowed (pattern matches APSR_nzcv)
# rm15 disallowed (pattern matches APSR_nzcv)
# IT block => constrained unpredictable
#
# Error given when using coprocessor number not enabled on command line.
# Disallow non-incrementing values in destination.
# Too many arguments
# Too little arguments
cx3d p0, r0, r1, r0, r0, #64
cx3da p0, r0, r1, r0, r0, #64
cx3d p0, r0, r1, r0, r0, #-1
cx3da p0, r0, r1, r0, r0, #-1
cx3d p8, r0, r1, r0, r0, #0
cx3da p8, r0, r1, r0, r0, #0
cx3d p0, r16, r17, r0, r0, #0
cx3da p0, r16, r17, r0, r0, #0
cx3d p0, r0, r1, r16, r0, #0
cx3da p0, r0, r1, r16, r0, #0
cx3d p0, r0, r1, r0, r16, #0
cx3da p0, r0, r1, r0, r16, #0
cx3d p0, APSR_nzcv, r15, r0, r0, #0
cx3da p0, APSR_nzcv, r15, r0, r0, #0
cx3d p0, r9, r10, r0, r0, #0
cx3da p0, r9, r10, r0, r0, #0
cx3d p0, r12, r13, r0, r0, #0
cx3da p0, r12, r13, r0, r0, #0
cx3d p0, r0, r1, r13, r0, #0
cx3da p0, r0, r1, r13, r0, #0
cx3d p0, r0, r1, r0, r13, #0
cx3da p0, r0, r1, r0, r13, #0
cx3d p0, r0, r1, r15, r0, #0
cx3da p0, r0, r1, r15, r0, #0
cx3d p0, r0, r1, r0, r15, #0
cx3da p0, r0, r1, r0, r15, #0
itttt ne
cx3d p0, r0, r1, r0, r0, #0
cx3da p0, r0, r1, r0, r0, #0
cx3dne p0, r0, r1, r0, r0, #0
cx3daeq p0, r0, r1, r0, r0, #0
cx3d p1, r0, r1, r0, r0, #0
cx3da p1, r0, r1, r0, r0, #0
cx3d p0, r0, r2, r0, r0, #0
cx3da p0, r0, r2, r0, r0, #0
cx3d p0, r0, r1, r0, r0, r0, #0
cx3da p0, r0, r1, r0, r0, r0, #0
cx3d p0, r0, r0, r0, #0
cx3da p0, r0, r0, r0, #0
# vcx1{a}
# Immediate out of range.
# Each register out of range.
# IT block => constrained unpredictable
#
# Error given when using coprocessor number not enabled on command line.
# Too many arguments
# Too little arguments
vcx1 p0, q0, #4096
vcx1a p0, q0, #4096
vcx1 p0, q0, #-1
vcx1a p0, q0, #-1
vcx1 p8, q0, #0
vcx1a p8, q0, #0
vcx1 p0, q8, #0
vcx1a p0, q8, #0
itttt ne
vcx1 p0, q0, #0
vcx1ne p0, q0, #0
vcx1a p0, q0, #0
vcx1ane p0, q0, #0
vcx1 p1, q0, #0
vcx1a p1, q0, #0
vcx1 p0, q0, q0, #0
vcx1a p0, q0, q0, #0
vcx1 p0, #0
vcx1a p0, #0
vcx1 p0, d0, #2048
vcx1a p0, d0, #2048
vcx1 p0, d0, #-1
vcx1a p0, d0, #-1
vcx1 p8, d0, #0
vcx1a p8, d0, #0
vcx1 p0, d16, #0
vcx1a p0, d16, #0
itttt ne
vcx1 p0, d0, #0
vcx1ne p0, d0, #0
vcx1a p0, d0, #0
vcx1ane p0, d0, #0
vcx1 p1, d0, #0
vcx1a p1, d0, #0
vcx1 p0, d0, d0, #0
vcx1a p0, d0, d0, #0
vcx1 p0, #0
vcx1a p0, #0
vcx1 p0, s0, #2048
vcx1a p0, s0, #2048
vcx1 p0, s0, #-1
vcx1a p0, s0, #-1
vcx1 p8, s0, #0
vcx1a p8, s0, #0
vcx1 p0, s32, #0
vcx1a p0, s32, #0
itttt ne
vcx1 p0, s0, #0
vcx1ne p0, s0, #0
vcx1a p0, s0, #0
vcx1ane p0, s0, #0
vcx1 p1, s0, #0
vcx1a p1, s0, #0
vcx1 p0, s0, s0, #0
vcx1a p0, s0, s0, #0
vcx1 p0, #0
vcx1a p0, #0
# vcx2{a}
# Immediate out of range.
# Each register out of range.
# IT block => constrained unpredictable
#
# Error given when using coprocessor number not enabled on command line.
# Too many arguments
# Too little arguments
vcx2 p0, q0, q0, #128
vcx2a p0, q0, q0, #128
vcx2 p0, q0, q0, #-1
vcx2a p0, q0, q0, #-1
vcx2 p8, q0, q0, #0
vcx2a p8, q0, q0, #0
vcx2 p0, q8, q0, #0
vcx2a p0, q8, q0, #0
vcx2 p0, q0, q8, #0
vcx2a p0, q0, q8, #0
itttt ne
vcx2 p0, q0, q0, #0
vcx2ne p0, q0, q0, #0
vcx2a p0, q0, q0, #0
vcx2ane p0, q0, q0, #0
vcx2 p1, q0, q0, #0
vcx2a p1, q0, q0, #0
vcx2 p0, q0, q0, q0, #0
vcx2a p0, q0, q0, q0, #0
vcx2 p0, q0, #0
vcx2a p0, q0, #0
vcx2 p0, d0, d0, #64
vcx2a p0, d0, d0, #64
vcx2 p0, d0, d0, #-1
vcx2a p0, d0, d0, #-1
vcx2 p8, d0, d0, #0
vcx2a p8, d0, d0, #0
vcx2 p0, d16, d0, #0
vcx2a p0, d16, d0, #0
vcx2 p0, d0, d16, #0
vcx2a p0, d0, d16, #0
itttt ne
vcx2 p0, d0, d0, #0
vcx2ne p0, d0, d0, #0
vcx2a p0, d0, d0, #0
vcx2ane p0, d0, d0, #0
vcx2 p1, d0, d0, #0
vcx2a p1, d0, d0, #0
vcx2 p0, d0, d0, d0, #0
vcx2a p0, d0, d0, d0, #0
vcx2 p0, d0, #0
vcx2a p0, d0, #0
vcx2 p0, s0, s0, #64
vcx2a p0, s0, s0, #64
vcx2 p0, s0, s0, #-1
vcx2a p0, s0, s0, #-1
vcx2 p8, s0, s0, #0
vcx2a p8, s0, s0, #0
vcx2 p0, s32, s0, #0
vcx2a p0, s32, s0, #0
vcx2 p0, s0, s32, #0
vcx2a p0, s0, s32, #0
itttt ne
vcx2 p0, s0, s0, #0
vcx2ne p0, s0, s0, #0
vcx2a p0, s0, s0, #0
vcx2ane p0, s0, s0, #0
vcx2 p1, s0, s0, #0
vcx2a p1, s0, s0, #0
vcx2 p0, s0, s0, s0, #0
vcx2a p0, s0, s0, s0, #0
vcx2 p0, s0, #0
vcx2a p0, s0, #0
# vcx3{a}
# Immediate out of range.
# Each register out of range.
# IT block => constrained unpredictable
#
# Error given when using coprocessor number not enabled on command line.
# Too many arguments
# Too little arguments
vcx3 p0, q0, q0, q0, #16
vcx3a p0, q0, q0, q0, #16
vcx3 p0, q0, q0, q0, #-1
vcx3a p0, q0, q0, q0, #-1
vcx3 p8, q0, q0, q0, #0
vcx3a p8, q0, q0, q0, #0
vcx3 p0, q8, q0, q0, #0
vcx3a p0, q8, q0, q0, #0
vcx3 p0, q8, q0, q0, #0
vcx3a p0, q0, q8, q0, #0
vcx3 p0, q0, q0, q8, #0
vcx3a p0, q0, q0, q8, #0
itttt ne
vcx3 p0, q0, q0, q0, #0
vcx3ne p0, q0, q0, q0, #0
vcx3a p0, q0, q0, q0, #0
vcx3ane p0, q0, q0, q0, #0
vcx3 p1, q0, q0, q0, #0
vcx3a p1, q0, q0, q0, #0
vcx3 p0, q0, q0, q0, q0, #0
vcx3a p0, q0, q0, q0, q0, #0
vcx3 p0, q0, q0, #0
vcx3a p0, q0, q0, #0
vcx3 p0, d0, d0, d0, #8
vcx3a p0, d0, d0, d0, #8
vcx3 p0, d0, d0, d0, #-1
vcx3a p0, d0, d0, d0, #-1
vcx3 p8, d0, d0, d0, #0
vcx3a p8, d0, d0, d0, #0
vcx3 p0, d16, d0, d0, #0
vcx3a p0, d16, d0, d0, #0
vcx3 p0, d0, d16, d0, #0
vcx3a p0, d0, d16, d0, #0
vcx3 p0, d0, d0, d16, #0
vcx3a p0, d0, d0, d16, #0
itttt ne
vcx3 p0, d0, d0, d0, #0
vcx3ne p0, d0, d0, d0, #0
vcx3a p0, d0, d0, d0, #0
vcx3ane p0, d0, d0, d0, #0
vcx3 p1, d0, d0, d0, #0
vcx3a p1, d0, d0, d0, #0
vcx3 p0, d0, d0, d0, d0, #0
vcx3a p0, d0, d0, d0, d0, #0
vcx3 p0, d0, d0, #0
vcx3a p0, d0, d0, #0
vcx3 p0, s0, s0, s0, #8
vcx3a p0, s0, s0, s0, #8
vcx3 p0, s0, s0, s0, #-1
vcx3a p0, s0, s0, s0, #-1
vcx3 p8, s0, s0, s0, #0
vcx3a p8, s0, s0, s0, #0
vcx3 p0, s32, s0, s0, #0
vcx3a p0, s32, s0, s0, #0
vcx3 p0, s0, s32, s0, #0
vcx3a p0, s0, s32, s0, #0
vcx3 p0, s0, s0, s32, #0
vcx3a p0, s0, s0, s32, #0
itttt ne
vcx3 p0, s0, s0, s0, #0
vcx3ne p0, s0, s0, s0, #0
vcx3a p0, s0, s0, s0, #0
vcx3ane p0, s0, s0, s0, #0
vcx3 p1, s0, s0, s0, #0
vcx3a p1, s0, s0, s0, #0
vcx3 p0, s0, s0, s0, s0, #0
vcx3a p0, s0, s0, s0, s0, #0
vcx3 p0, s0, s0, #0
vcx3a p0, s0, s0, #0
|
tactcomplabs/xbgas-binutils-gdb
| 1,435
|
gas/testsuite/gas/arm/mve-vrmlaldavh.s
|
.syntax unified
.thumb
.irp op1, r0, r2, r4, r8, r10, r12, r14
.irp op2, r1, r3, r5, r7, r9, r11
.irp op3, q0, q1, q2, q4, q7
.irp op4, q0, q1, q2, q4, q7
.irp data, s32, u32
vrmlaldavh.\data \op1, \op2, \op3, \op4
vrmlaldavha.\data \op1, \op2, \op3, \op4
vrmlalvh.\data \op1, \op2, \op3, \op4
vrmlalvha.\data \op1, \op2, \op3, \op4
.endr
vrmlaldavhx.s32 \op1, \op2, \op3, \op4
vrmlaldavhax.s32 \op1, \op2, \op3, \op4
.endr
.endr
.endr
.endr
.irp op1, r0, r2, r4, r8, r10, r12, r14
.irp op2, r1, r3, r5, r7, r9, r11
.irp op3, q0, q1, q2, q4, q7
.irp op4, q0, q1, q2, q4, q7
vrmlsldavh.s32 \op1, \op2, \op3, \op4
vrmlsldavha.s32 \op1, \op2, \op3, \op4
vrmlsldavhx.s32 \op1, \op2, \op3, \op4
vrmlsldavhax.s32 \op1, \op2, \op3, \op4
.endr
.endr
.endr
.endr
vpstete
vrmlaldavht.s32 r0, r1, q2, q3
vrmlaldavhe.u32 lr, r11, q7, q7
vrmlaldavhat.s32 lr, r11, q7, q7
vrmlaldavhae.u32 r0, r1, q2, q3
vpstete
vrmlaldavhxt.s32 r0, r1, q2, q3
vrmlaldavhxe.s32 r4, r7, q0, q5
vrmlaldavhaxt.s32 r0, r1, q2, q3
vrmlaldavhaxe.s32 lr, r11, q7, q7
vpstete
vrmlalvht.s32 r0, r1, q2, q3
vrmlalvhe.s32 lr, r11, q7, q7
vrmlalvhat.s32 r0, r1, q2, q3
vrmlalvhae.s32 lr, r11, q7, q7
vpstete
vrmlsldavht.s32 r0, r1, q2, q3
vrmlsldavhe.s32 lr, r11, q7, q7
vrmlsldavhat.s32 r0, r1, q2, q3
vrmlsldavhae.s32 lr, r11, q7, q7
vpstete
vrmlsldavhxt.s32 r0, r1, q2, q3
vrmlsldavhxe.s32 lr, r11, q7, q7
vrmlsldavhaxt.s32 r0, r1, q2, q3
vrmlsldavhaxe.s32 lr, r11, q7, q7
|
tactcomplabs/xbgas-binutils-gdb
| 1,115
|
gas/testsuite/gas/arm/mve-vqdmull.s
|
.syntax unified
.thumb
.irp op1, q0, q1, q2, q4, q7
.irp op2, q0, q1, q2, q4, q7
.irp op3, r0, r1, r2, r4, r7, r8, r10, r12, r14
vqdmullt.s16 \op1, \op2, \op3
vqdmullb.s16 \op1, \op2, \op3
.endr
.endr
.endr
.irp op2, q1, q2, q4, q7
.irp op3, r0, r2, r4, r7, r8, r10, r12, r14
vqdmullt.s32 q0, \op2, \op3
vqdmullb.s32 q0, \op2, \op3
.endr
.endr
.irp op2, q0, q2, q4, q7
.irp op3, r0, r2, r4, r7, r8, r10, r12, r14
vqdmullt.s32 q1, \op2, \op3
vqdmullb.s32 q1, \op2, \op3
.endr
.endr
.irp op2, q0, q1, q4, q7
.irp op3, r0, r2, r4, r7, r8, r10, r12, r14
vqdmullt.s32 q2, \op2, \op3
vqdmullb.s32 q2, \op2, \op3
.endr
.endr
.irp op2, q0, q1, q2, q7
.irp op3, r0, r2, r4, r7, r8, r10, r12, r14
vqdmullt.s32 q4, \op2, \op3
vqdmullb.s32 q4, \op2, \op3
.endr
.endr
.irp op2, q0, q1, q2, q4
.irp op3, r0, r2, r4, r7, r8, r10, r12, r14
vqdmullt.s32 q7, \op2, \op3
vqdmullb.s32 q7, \op2, \op3
.endr
.endr
vpstete
vqdmulltt.s16 q0, q1, q2
vqdmullte.s32 q0, q1, q2
vqdmullbt.s16 q0, q1, q2
vqdmullbe.s32 q0, q1, q2
vpstete
vqdmulltt.s16 q7, q7, lr
vqdmullte.s32 q7, q6, r0
vqdmullbt.s16 q0, q1, r2
vqdmullbe.s32 q5, q7, r14
|
tactcomplabs/xbgas-binutils-gdb
| 3,702
|
gas/testsuite/gas/cris/branch.s
|
;
; Test that branches work: 8- and 16-bit all insns, relaxing to
; 32-bit, forward and backward. No need to check the border
; cases for *all* insns.
;
.text
start_original:
nop
startm32: ; start start2 start3
nop
.space 32750-(256-21*2+20)-(21*2+10*2+21*4)-12,0
startm16:
nop
; The size of a bunch of short branches is start2-start = 42,
; so make the threshold be dependent of the size of that block,
; for the next block; half of them will be relaxed.
.space 256-21*2-20,0
start:
nop
ba start
bcc start
bcs start
beq start
bwf start
bext start
bext start ; leftover, used to be never-implemented "bir"
bge start
bgt start
bhi start
bhs start
ble start
blo start
bls start
blt start
bmi start
bne start
bpl start
bvc start
bvs start
start2:
nop
ba startm16
bcc startm16
bcs startm16
beq startm16
bwf startm16
bext startm16
bext startm16
bge startm16
bgt startm16
bhi startm16
bhs startm16
ble startm16
blo startm16
bls startm16
blt startm16
bmi startm16
bne startm16
bpl startm16
bvc startm16
bvs startm16
start3:
; Ok, once more to make sure *all* 16-bit variants get ok for
; backward references.
nop
ba startm16
bcc startm16
bcs startm16
beq startm16
bwf startm16
bext startm16
bext startm16
bge startm16
bgt startm16
bhi startm16
bhs startm16
ble startm16
blo startm16
bls startm16
blt startm16
bmi startm16
bne startm16
bpl startm16
bvc startm16
bvs startm16
;
; Now check that dynamically relaxing some of these branches
; from 16-bit to 32-bit works.
;
start4:
nop
ba startm32
bcc startm32
bcs startm32
beq startm32
bwf startm32
bext startm32
bext startm32
bge startm32
bgt startm32
bhi startm32
bhs startm32
ble startm32
blo startm32
bls startm32
blt startm32
bmi startm32
bne startm32
bpl startm32
bvc startm32
bvs startm32
;
; Again, so all insns get to be tested for 32-bit relaxing.
;
start5:
nop
ba startm32
bcc startm32
bcs startm32
beq startm32
bwf startm32
bext startm32
bext startm32
bge startm32
bgt startm32
bhi startm32
bhs startm32
ble startm32
blo startm32
bls startm32
blt startm32
bmi startm32
bne startm32
bpl startm32
bvc startm32
bvs startm32
;
; Now test forward references. Symmetrically as above.
;
; All to 32-bit:
start6:
nop
ba endp32
bcc endp32
bcs endp32
beq endp32
bwf endp32
bext endp32
bext endp32
bge endp32
bgt endp32
bhi endp32
bhs endp32
ble endp32
blo endp32
bls endp32
blt endp32
bmi endp32
bne endp32
bpl endp32
bvc endp32
bvs endp32
;
; Some get relaxed:
;
start7:
nop
ba endp32
bcc endp32
bcs endp32
beq endp32
bwf endp32
bext endp32
bext endp32
bge endp32
bgt endp32
bhi endp32
bhs endp32
ble endp32
blo endp32
bls endp32
blt endp32
bmi endp32
bne endp32
bpl endp32
bvc endp32
bvs endp32
;
; All to 16-bit:
;
start8:
nop
ba endp16
bcc endp16
bcs endp16
beq endp16
bwf endp16
bext endp16
bext endp16
bge endp16
bgt endp16
bhi endp16
bhs endp16
ble endp16
blo endp16
bls endp16
blt endp16
bmi endp16
bne endp16
bpl endp16
bvc endp16
bvs endp16
;
; Some relaxing:
;
start9:
nop
ba endp16
bcc endp16
bcs endp16
beq endp16
bwf endp16
bext endp16
bext endp16
bge endp16
bgt endp16
bhi endp16
bhs endp16
ble endp16
blo endp16
bls endp16
blt endp16
bmi endp16
bne endp16
bpl endp16
bvc endp16
bvs endp16
;
; And all the short ones, forward.
;
start10:
ba end
bcc end
bcs end
beq end
bwf end
bext end
bext end
bge end
bgt end
bhi end
bhs end
ble end
blo end
bls end
blt end
bmi end
bne end
bpl end
bvc end
bvs end
nop
end:
nop
.space 256-21*2-20,0
endp16:
nop
.space 32750-(256-21*2+20)-(21*2+10*2+21*4)-12,0
endp32:
nop
|
tactcomplabs/xbgas-binutils-gdb
| 1,091
|
gas/testsuite/gas/cris/tls-err-2.s
|
; Like tls-err-1.s but for PIC TLS suffixes.
; { dg-do assemble }
; { dg-options "--pic --no-underscore --em=criself" }
.syntax no_register_prefix
.text
start:
move.b extsym:GDGOTREL16,r4 ; { dg-error "PIC relocation size does not match" "" { xfail *-*-* } }
move.b extsym12:GDGOTREL,r5 ; { dg-error "PIC relocation size does not match" }
move.w extsym2:GDGOTREL,r5 ; { dg-error "PIC relocation size does not match" }
move.d extsym3:GDGOTREL16,r6 ; { dg-error "PIC relocation size does not match" }
move extsym4:GDGOTREL16,srp ; { dg-error "PIC relocation size does not match" }
move.b extsym5:TPOFFGOT16,r4 ; { dg-error "PIC relocation size does not match" "" { xfail *-*-* } }
move.b extsym15:TPOFFGOT,r7 ; { dg-error "PIC relocation size does not match" }
move.w extsym6:DTPREL,r5 ; { dg-error "PIC relocation size does not match" }
move.d extsym7:DTPREL16,r6 ; { dg-error "PIC relocation size does not match" }
move.d extsym7:TPOFFGOT16,r6 ; { dg-error "PIC relocation size does not match" }
move extsym8:TPOFFGOT16,srp ; { dg-error "PIC relocation size does not match" }
|
tactcomplabs/xbgas-binutils-gdb
| 1,486
|
gas/testsuite/gas/cris/rd-pcrel2.s
|
; Test border-cases for relaxation of pc-relative expressions.
.macro relaxcode
.endm
.text
.syntax no_register_prefix
; Region of relaxation is after insn, same segment
z:
move.d [pc-(x1-x+128-4)],r8 ; 4
move.d [pc-(x2-x+129-8)],r8 ; 6
move.d [pc+x3-x+127-14],r8 ; 4
move.d [pc+x4-x+128-18],r8 ; 6
move.d [pc-(x5-x+32768-26)],r8 ; 6
move.d [pc-(x6-x+32769-32)],r8 ; 8
move.d [pc+x7-x+32767-40],r8 ; 6
move.d [pc+x8-x+32768-46],r8 ; 8
.p2align 1
; Region of relaxation is around insn, same segment
x:
move.d [pc-(x1-x+128-4)],r8 ; 4
x1:
move.d [pc-(x2-x+129-8)],r8 ; 6
x2:
move.d [pc+x3-x+127-14],r8 ; 4
x3:
move.d [pc+x4-x+128-18],r8 ; 6
x4:
move.d [pc-(x5-x+32768-26)],r8 ; 6
x5:
move.d [pc-(x6-x+32769-32)],r8 ; 8
x6:
move.d [pc+x7-x+32767-40],r8 ; 6
x7:
move.d [pc+x8-x+32768-46],r8 ; 8
x8:
; Region of relaxation is before insn, same segment.
move.d [pc-(x1-x+128-4)],r8 ; 4
move.d [pc-(x2-x+129-8)],r8 ; 6
move.d [pc+x3-x+127-14],r8 ; 4
move.d [pc+x4-x+128-18],r8 ; 6
move.d [pc-(x5-x+32768-26)],r8 ; 6
move.d [pc-(x6-x+32769-32)],r8 ; 8
move.d [pc+x7-x+32767-40],r8 ; 6
move.d [pc+x8-x+32768-46],r8 ; 8
; Region of relaxation is in other segment.
.section .text.other
y:
move.d [pc-(x1-x+128-4)],r8 ; 4
move.d [pc-(x2-x+129-8)],r8 ; 6
move.d [pc+x3-x+127-14],r8 ; 4
move.d [pc+x4-x+128-18],r8 ; 6
move.d [pc-(x5-x+32768-26)],r8 ; 6
move.d [pc-(x6-x+32769-32)],r8 ; 8
move.d [pc+x7-x+32767-40],r8 ; 6
move.d [pc+x8-x+32768-46],r8 ; 8
|
tactcomplabs/xbgas-binutils-gdb
| 2,171
|
gas/testsuite/gas/cris/brokw-3.s
|
; Tests the broken-word function, one more word than fits in a
; single branch.
.syntax no_register_prefix
start: moveq 0,r0
; Take the opportunity to (rudimentally) test case-recognition,
; as the diassembler gets overly confused by the table.
subs.b 87,r0
bound.b 41,r0
adds.w [pc+r0.w],pc
sym2:
.word sym1 - sym2
.word sym3 - sym2
.word sym4 - sym2
.word sym5 - sym2
.word sym6 - sym2
.word sym7 - sym2
.word sym8 - sym2
.word sym9 - sym2
.word sym10 - sym2
.word sym11 - sym2
.word sym12 - sym2
.word sym13 - sym2
.word sym14 - sym2
.word sym15 - sym2
.word sym16 - sym2
.word sym17 - sym2
.word sym18 - sym2
.word sym19 - sym2
.word sym20 - sym2
.word sym21 - sym2
.word sym22 - sym2
.word sym23 - sym2
.word sym24 - sym2
.word sym25 - sym2
.word sym26 - sym2
.word sym27 - sym2
.word sym28 - sym2
.word sym29 - sym2
.word sym30 - sym2
.word sym31 - sym2
.word sym32 - sym2
.word sym33 - sym2
.word sym34 - sym2
.word sym35 - sym2
.word sym36 - sym2
.word sym37 - sym2
.word sym38 - sym2
.word sym39 - sym2
.word sym40 - sym2
.word sym41 - sym2
.word sym42 - sym2
.word sym43 - sym2
.space 16, 0
moveq 1,r0
; Medium-range branch around secondary jump table inserted here :
; ba next_label
; nop
; .skip 2,0
; Secondary jump table inserted here :
; jump sym1
; jump sym3
; ...
next_label:
moveq 2,r0
.space 32768, 0
sym1: moveq -3,r0
sym3: moveq 3,r0
sym4: moveq 4,r0
sym5: moveq 5,r0
sym6: moveq 6,r0
sym7: moveq 7,r0
sym8: moveq 8,r0
sym9: moveq 9,r0
sym10: moveq 10,r0
sym11: moveq 11,r0
sym12: moveq 12,r0
sym13: moveq 13,r0
sym14: moveq 14,r0
sym15: moveq 15,r0
sym16: moveq 16,r0
sym17: moveq 17,r0
sym18: moveq 18,r0
sym19: moveq 19,r0
sym20: moveq 20,r0
sym21: moveq 21,r0
sym22: moveq 22,r0
sym23: moveq 23,r0
sym24: moveq 24,r0
sym25: moveq 25,r0
sym26: moveq 26,r0
sym27: moveq 27,r0
sym28: moveq 28,r0
sym29: moveq 29,r0
sym30: moveq 30,r0
sym31: moveq 31,r0
sym32: moveq -32,r0
sym33: moveq -31,r0
sym34: moveq -30,r0
sym35: moveq -29,r0
sym36: moveq -28,r0
sym37: moveq -27,r0
sym38: moveq -26,r0
sym39: moveq -25,r0
sym40: moveq -24,r0
sym41: moveq -23,r0
sym42: moveq -22,r0
sym43: moveq -21,r0
|
tactcomplabs/xbgas-binutils-gdb
| 2,809
|
gas/testsuite/gas/cris/binop-segref.s
|
; This used to be part of the binop test; differences broke when the
; broken-dot-word handling was broke and were moved here.
.text
.syntax no_register_prefix
.byte 56,43,42 ; Make sure we don't start at zero.
; Some differences we want to see computed right, giving the right
; size of the operands.
;
.globl back_ref_text_zero
back_ref_text_zero:
.space 42,0
.globl back_ref_text_fortytwo
back_ref_text_fortytwo:
.space 32767-42,0
.globl back_ref_text_three2767
back_ref_text_three2767:
.space 327767-32767,0
.globl back_ref_text_three27767
back_ref_text_three27767:
.data
.globl back_ref_data_zero
back_ref_data_zero:
.space 42,0
.globl back_ref_data_fortytwo
back_ref_data_fortytwo:
.space 32767-42,0
.globl back_ref_data_three2767
back_ref_data_three2767:
.space 327767-32767,0
.globl back_ref_data_three27767
back_ref_data_three27767:
.text
add.b back_ref_data_fortytwo-back_ref_data_zero,r5
add.b forw_ref_data_fortytwo-forw_ref_data_zero,r5
add.b back_ref_text_fortytwo-back_ref_text_zero,r5
add.b forw_ref_text_fortytwo-forw_ref_text_zero,r5
add.w back_ref_data_fortytwo-back_ref_data_zero,r5
add.w forw_ref_data_fortytwo-forw_ref_data_zero,r5
add.w back_ref_text_fortytwo-back_ref_text_zero,r5
add.w forw_ref_text_fortytwo-forw_ref_text_zero,r5
add.w back_ref_data_three2767-back_ref_data_zero,r5
add.w forw_ref_data_three2767-forw_ref_data_zero,r5
add.w back_ref_text_three2767-back_ref_text_zero,r5
add.w forw_ref_text_three2767-forw_ref_text_zero,r5
add.d back_ref_data_fortytwo-back_ref_data_zero,r5
add.d forw_ref_data_fortytwo-forw_ref_data_zero,r5
add.d back_ref_text_fortytwo-back_ref_text_zero,r5
add.d forw_ref_text_fortytwo-forw_ref_text_zero,r5
add.d back_ref_data_three2767-back_ref_data_zero,r5
add.d forw_ref_data_three2767-forw_ref_data_zero,r5
add.d back_ref_text_three2767-back_ref_text_zero,r5
add.d forw_ref_text_three2767-forw_ref_text_zero,r5
add.d back_ref_data_three27767-back_ref_data_zero,r5
add.d forw_ref_data_three27767-forw_ref_data_zero,r5
add.d back_ref_text_three27767-back_ref_text_zero,r5
add.d forw_ref_text_three27767-forw_ref_text_zero,r5
.text
; Don't have references to addresses immediately after the
; tested code (I'm superstitious).
.byte 56,43,42
.globl forw_ref_text_zero
forw_ref_text_zero:
.space 42,0
.globl forw_ref_text_fortytwo
forw_ref_text_fortytwo:
.space 32767-42
.globl forw_ref_text_three2767
forw_ref_text_three2767:
.space 327767-32767,0
.globl forw_ref_text_three27767
forw_ref_text_three27767:
.data
.globl forw_ref_data_zero
forw_ref_data_zero:
.space 42,0
.globl forw_ref_data_fortytwo
forw_ref_data_fortytwo:
.globl forw_ref_data_three2767
.space 32767-42
forw_ref_data_three2767:
.space 327767-32767,0
.globl forw_ref_data_three27767
forw_ref_data_three27767:
|
tactcomplabs/xbgas-binutils-gdb
| 2,005
|
gas/testsuite/gas/cris/bwtest-err-1.s
|
; File bwtest-err-1.s
; { dg-do assemble { target cris-*-* } }
; A variant of exbwtest.s. This is an example of invalid use of the broken-
; dot-word function. The nearest label occurs about 32 kbytes after the primary
; jump table so the secondary jump table can't be reached by word displace-
; ments and the broken words overflow.
; main()
; {
; byte i;
;
; for (i=0; i <= 3; i++) {
; result[i] = funct(i);
; }
; }
;
; Register use : r1 - i
; r2 - result address
.text
.syntax no_register_prefix
.word 0
main: move.d stack,sp
moveq 0,r1
move.d result,r2
for1: cmpq 3,r1
bgt endfor1
move.d r1,r0
jsr funct
move.w r0,[r2+r1.w]
ba for1
addq 1,r1
endfor1:
end: ba end
nop
; uword funct(i)
; byte i;
; {
; switch (i) {
; case 0 : return 0x1111;
; case 1 : return 0x2222;
; case 2 : return 0x3333;
; case 3 : return 0x4444;
; }
; }
;
; Parameters : r0 - i
;
; Register use : r1 - pjt address
funct: push r1
move.d pjt,r1
adds.w [r1+r0.w],pc
pjt: .word near1 - pjt
.word near2 - pjt
.word far1 - pjt
.word far2 - pjt
; Note that the line-number of the source-location of the error
; seems slightly off from the user perspective, but it's the
; best I could get without major changes in BW-handling. Not
; sure it it's worth fixing. May need adjustments if
; BW-handling changes. Four errors from four .words are what's
; expected.
.space 32760,0xFF; { dg-error "Adjusted signed \.word \(.*\) overflow.*" }
near1: move.w 0x1111,r0
ba ret1
nop
near2: move.w 0x2222,r0
ba ret1
nop
far1: move.w 0x3333,r0
ba ret1
nop
far2: move.w 0x4444,r0
ret1: pop r1
ret
result: .space 4 * 2 ; static uword result[4];
.space 4
stack:
|
tactcomplabs/xbgas-binutils-gdb
| 1,176
|
gas/testsuite/gas/cris/pic-err-1.s
|
; Check that invalid PIC reloc and instruction size combinations are
; recognized. Note that sizes of byte operands are not error-checked for
; not being in 16-bit range, so no error is recognized for a 16-bit operand.
; { dg-do assemble { target cris-*-* } }
; { dg-options "--pic --no-underscore --em=criself" }
.syntax no_register_prefix
.text
start:
move.b extsym:GOTPLT16,r4 ; { dg-error "PIC relocation size does not match" "" { xfail *-*-* } }
move.b extsym12:GOTPLT,r5 ; { dg-error "PIC relocation size does not match" }
move.w extsym2:GOTPLT,r5 ; { dg-error "PIC relocation size does not match" }
move.d extsym3:GOTPLT16,r6 ; { dg-error "PIC relocation size does not match" }
move extsym4:GOTPLT16,srp ; { dg-error "PIC relocation size does not match" }
move.b extsym5:GOT16,r4 ; { dg-error "PIC relocation size does not match" "" { xfail *-*-* } }
move.b extsym15:GOT,r7 ; { dg-error "PIC relocation size does not match" }
move.w extsym6:GOT,r5 ; { dg-error "PIC relocation size does not match" }
move.d extsym7:GOT16,r6 ; { dg-error "PIC relocation size does not match" }
move extsym8:GOT16,srp ; { dg-error "PIC relocation size does not match" }
|
tactcomplabs/xbgas-binutils-gdb
| 1,944
|
gas/testsuite/gas/cris/brokw-3b.s
|
; Tests the broken-word function with a real switch table. CRISv32 version.
start: moveq 0,r0
subs.b 87,r0
bound.b 41,r0
lapc sym2,acr
addi r0.w,acr
adds.w [acr],acr
jump acr
nop
sym2:
.word sym1 - .
.word sym3 - .
.word sym4 - .
.word sym5 - .
.word sym6 - .
.word sym7 - .
.word sym8 - .
.word sym9 - .
.word sym10 - .
.word sym11 - .
.word sym12 - .
.word sym13 - .
.word sym14 - .
.word sym15 - .
.word sym16 - .
.word sym17 - .
.word sym18 - .
.word sym19 - .
.word sym20 - .
.word sym21 - .
.word sym22 - .
.word sym23 - .
.word sym24 - .
.word sym25 - .
.word sym26 - .
.word sym27 - .
.word sym28 - .
.word sym29 - .
.word sym30 - .
.word sym31 - .
.word sym32 - .
.word sym33 - .
.word sym34 - .
.word sym35 - .
.word sym36 - .
.word sym37 - .
.word sym38 - .
.word sym39 - .
.word sym40 - .
.word sym41 - .
.word sym42 - .
.word sym43 - .
.space 16, 0
moveq 1,r0
; Medium-range branch around secondary jump table inserted here :
; ba next_label
; nop
; .skip 2,0
; Secondary jump table inserted here :
; ba sym1
; nop
; ba sym3
; nop
; ...
next_label:
moveq 2,r0
.space 32768, 0
sym1: moveq -3,r0
sym3: moveq 3,r0
sym4: moveq 4,r0
sym5: moveq 5,r0
sym6: moveq 6,r0
sym7: moveq 7,r0
sym8: moveq 8,r0
sym9: moveq 9,r0
sym10: moveq 10,r0
sym11: moveq 11,r0
sym12: moveq 12,r0
sym13: moveq 13,r0
sym14: moveq 14,r0
sym15: moveq 15,r0
sym16: moveq 16,r0
sym17: moveq 17,r0
sym18: moveq 18,r0
sym19: moveq 19,r0
sym20: moveq 20,r0
sym21: moveq 21,r0
sym22: moveq 22,r0
sym23: moveq 23,r0
sym24: moveq 24,r0
sym25: moveq 25,r0
sym26: moveq 26,r0
sym27: moveq 27,r0
sym28: moveq 28,r0
sym29: moveq 29,r0
sym30: moveq 30,r0
sym31: moveq 31,r0
sym32: moveq -32,r0
sym33: moveq -31,r0
sym34: moveq -30,r0
sym35: moveq -29,r0
sym36: moveq -28,r0
sym37: moveq -27,r0
sym38: moveq -26,r0
sym39: moveq -25,r0
sym40: moveq -24,r0
sym41: moveq -23,r0
sym42: moveq -22,r0
sym43: moveq -21,r0
|
tactcomplabs/xbgas-binutils-gdb
| 1,260
|
gas/testsuite/gas/cris/mulbug-err-1.s
|
; Test error message for mul insns at locations likely to trig
; a hardware bug.
; { dg-do assemble { target cris-*-* } }
; { dg-options "--em=criself" }
; First, .text isn't dword-aligned by default.
.text
muls.w $r1,$r4 ; { dg-error "align" }
nop
muls.b $r1,$r4 ; { dg-error "align" }
mulu.d $r1,$r4 ; { dg-error "align" }
; Neither are other code sections, aligned to word.
.section .text.1,"ax",@progbits
.p2align 1
muls.w $r1,$r4 ; { dg-error "align" }
nop
mulu.b $r1,$r4 ; { dg-error "align" }
muls.d $r1,$r4 ; { dg-error "align" }
; Now, a section aligned to dword. Errors for certain relative
; positions only.
.section .text.2,"ax",@progbits
.p2align 2
mulu.w $r1,$r4
nop
muls.d $r1,$r4
mulu.w $r1,$r4 ; { dg-error "align" }
; For good measure, a cache-line-aligned section.
.section .text.3,"ax",@progbits
.p2align 5
muls.w $r1,$r4
mulu.d $r4,$r1
mulu.b $r1,$r4
.rept 12
nop
.endr
mulu.b $r1,$r4 ; { dg-error "align" }
mulu.b $r1,$r4
; Last, make sure typical alignment use by a fixed gcc passes.
.section .text.4,"ax",@progbits
.align 1
moveq 0,$r13
moveq 1,$r13
.p2alignw 5,0x050f,2
muls.d $r1,$r4
.rept 12
moveq 2,$r13
.endr
.p2alignw 5,0x050f,2
muls.w $r1,$r4
.p2alignw 5,0x050f,2
muls.b $r4,$r1
|
tactcomplabs/xbgas-binutils-gdb
| 11,537
|
gas/testsuite/gas/cris/unop.s
|
; @OC@ test
; Generic unary operations supporting all sizes and their various
; addressing modes.
; Some fairly big pseudorandom numbers we don't want to compute
; as differences in actual data or code.
.set const_int_32, 0x1b94452b
.set const_int_m32, -3513208907
.set two701867, 2701867
; Other constants that are not differences
.set forty2, 42
.set mforty2, -42
.set three2767, 32767
.set six5535, 65535
.text
.syntax no_register_prefix
notstart:
.dword 0
start:
;;;;;;;;;;;;;;;;;
;
; r
@OC@.b r3
@OC@.w r5
@OC@.d r10
@OC@ r7
@OC@ r6
;;;;;;;;;;;;;;;;;
;
; [r]
@OC@.b [r0]
@OC@.w [r5]
@OC@.d [r10]
@OC@ [r0]
@OC@ [r3]
;;;;;;;;;;;;;;;;;
;
; [r+]
@OC@.b [r0+]
@OC@.w [r5+]
@OC@.d [r10+]
@OC@ [r4+]
@OC@ [r1+]
;;;;;;;;;;;;;;;;;
;
; [r+X]
; [r+r.b]
@OC@.b [r2+r0.b]
@OC@.w [r2+r5.b]
@OC@.d [r2+r10.b]
@OC@ [r11+r13.b]
@OC@ [r2+r10.b]
; [r+[r].b]
@OC@.b [r2+[r0].b]
@OC@.w [r2+[r5].b]
@OC@.d [r2+[r10].b]
@OC@ [r12+[r5].b]
@OC@ [r13+[r10].b]
; [r+[r+].b]
@OC@.b [r2+[r0+].b]
@OC@.w [r2+[r5+].b]
@OC@.d [r2+[r10+].b]
@OC@ [r2+[r13+].b]
@OC@ [r12+[r0+].b]
; [r+r.w]
@OC@.b [r2+r0.w]
@OC@.w [r2+r5.w]
@OC@.d [r2+r10.w]
@OC@ [r5+r11.w]
@OC@ [r1+r1.w]
; [r+[r].w]
@OC@.b [r2+[r0].w]
@OC@.w [r2+[r5].w]
@OC@.d [r2+[r10].w]
@OC@ [r0+[r0].w]
@OC@ [r2+[r7].w]
; [r+[r+].w]
@OC@.b [r2+[r0+].w]
@OC@.w [r2+[r5+].w]
@OC@.d [r2+[r10+].w]
@OC@ [r2+[r3+].w]
@OC@ [r7+[r8+].w]
; [r+r.d]
@OC@.b [r2+r0.d]
@OC@.w [r2+r5.d]
@OC@.d [r2+r10.d]
@OC@ [r2+r5.d]
@OC@ [r3+r10.d]
; [r+[r].d]
@OC@.b [r2+[r0].d]
@OC@.w [r2+[r5].d]
@OC@.d [r2+[r10].d]
@OC@ [r5+[r2].d]
@OC@ [r12+[r10].d]
; [r+[r+].d]
@OC@.b [r2+[r0+].d]
@OC@.w [r2+[r5+].d]
@OC@.d [r2+[r10+].d]
@OC@ [r1+[r5+].d]
@OC@ [r2+[r10+].d]
; [r+const]
; Note that I forgot 16-bit offsets and 32-bit offsets here and later.
; Maybe add them later if it feels necessary.
@OC@.b [r2+0]
@OC@.b [r2+1]
@OC@.b [r2+127]
@OC@.b [r2+128]
@OC@.b [r2+-1]
@OC@.b [r2+-127]
@OC@.b [r2+-128]
@OC@.b [r2+255]
@OC@.b [r2+42]
@OC@.b [r2+-42]
@OC@.b [r2-42]
@OC@.b [r2+forty2]
@OC@.b [r2+mforty2]
@OC@.b [r2+-forty2]
@OC@.b [r2+-mforty2]
@OC@.b [r2-forty2]
@OC@.b [r2-mforty2]
@OC@.b [r2+externalsym]
; Note that I missed 32-bit offsets (except -32769) here and later.
; Maybe add them later if it feels necessary.
@OC@.w [r2+0]
@OC@.w [r2+1]
@OC@.w [r2+127]
@OC@.w [r2+128]
@OC@.w [r2+-1]
@OC@.w [r2-1]
@OC@.w [r2+-127]
@OC@.w [r2+-128]
@OC@.w [r2+-129]
@OC@.w [r2-127]
@OC@.w [r2-128]
@OC@.w [r2-129]
@OC@.w [r2+255]
@OC@.w [r2+-255]
@OC@.w [r2-255]
@OC@.w [r2+256]
@OC@.w [r2-256]
@OC@.w [r2+-8856]
@OC@.w [r2-8856]
@OC@.w [r2+8856]
@OC@.w [r2+42]
@OC@.w [r2+-42]
@OC@.w [r2-42]
@OC@.w [r2+forty2]
@OC@.w [r2+mforty2]
@OC@.w [r2+-forty2]
@OC@.w [r2-forty2]
@OC@.w [r2+-mforty2]
@OC@.w [r2+three2767]
@OC@.w [r2+three2767+1]
@OC@.w [r2+three2767+2]
@OC@.w [r2+-three2767]
@OC@.w [r2+-(three2767+1)]
@OC@.w [r2+-(three2767+2)]
@OC@.w [r2-three2767]
@OC@.w [r2-(three2767+1)]
@OC@.w [r2-(three2767+2)]
@OC@.w [r2+six5535]
@OC@.w [r2+externalsym]
@OC@.d [r2+0]
@OC@.d [r2+1]
@OC@.d [r2+127]
@OC@.d [r2+128]
@OC@.d [r2+-1]
@OC@.d [r2-1]
@OC@.d [r2+-127]
@OC@.d [r2+-128]
@OC@.d [r2-127]
@OC@.d [r2-128]
@OC@.d [r2+255]
@OC@.d [r2+-255]
@OC@.d [r2-255]
@OC@.d [r2+256]
@OC@.d [r2-256]
@OC@.d [r2-8856]
@OC@.d [r2+-256]
@OC@.d [r2+-8856]
@OC@.d [r2+8856]
@OC@.d [r2+2781868]
@OC@.d [r2+-2701867]
@OC@.d [r2+0x9ec0ceac]
@OC@.d [r2+-0x7ec0cead]
@OC@.d [r2-0x7ec0cead]
@OC@.d [r2+const_int_m32]
@OC@.d [r2+const_int_32]
@OC@.d [r2+42]
@OC@.d [r2-42]
@OC@.d [r2+-42]
@OC@.d [r2+forty2]
@OC@.d [r2+mforty2]
@OC@.d [r2-forty2]
@OC@.d [r2-mforty2]
@OC@.d [r2+-forty2]
@OC@.d [r2+-mforty2]
@OC@.d [r2+three2767]
@OC@.d [r2+three2767+1]
@OC@.d [r2+three2767+2]
@OC@.d [r2+-three2767]
@OC@.d [r2+-(three2767+1)]
@OC@.d [r2+-(three2767+2)]
@OC@.d [r2-three2767]
@OC@.d [r2-(three2767+1)]
@OC@.d [r2-(three2767+2)]
@OC@.d [r2+six5535]
@OC@.d [r2+six5535+1]
@OC@.d [r2+two701867]
@OC@.d [r2+-two701867]
@OC@.d [r2-two701867]
@OC@.d [r2+externalsym]
@OC@ [r2+0]
@OC@ [r2+1]
@OC@ [r2+127]
@OC@ [r2+128]
@OC@ [r2+-1]
@OC@ [r2-1]
@OC@ [r2+-127]
@OC@ [r2+-128]
@OC@ [r2-127]
@OC@ [r2-128]
@OC@ [r2+255]
@OC@ [r2+-255]
@OC@ [r2-255]
@OC@ [r2+256]
@OC@ [r2-256]
@OC@ [r2-8856]
@OC@ [r2+-256]
@OC@ [r2+-8856]
@OC@ [r2+8856]
@OC@ [r2+2781868]
@OC@ [r2+-2701867]
@OC@ [r2+0x9ec0ceac]
@OC@ [r2+-0x7ec0cead]
@OC@ [r2-0x7ec0cead]
@OC@ [r2+const_int_m32]
@OC@ [r2+const_int_32]
@OC@ [r2+42]
@OC@ [r2-42]
@OC@ [r2+-42]
@OC@ [r2+forty2]
@OC@ [r2+mforty2]
@OC@ [r2-forty2]
@OC@ [r2-mforty2]
@OC@ [r2+-forty2]
@OC@ [r2+-mforty2]
@OC@ [r2+three2767]
@OC@ [r2+three2767+1]
@OC@ [r2+three2767+2]
@OC@ [r2+-three2767]
@OC@ [r2+-(three2767+1)]
@OC@ [r2+-(three2767+2)]
@OC@ [r2-three2767]
@OC@ [r2-(three2767+1)]
@OC@ [r2-(three2767+2)]
@OC@ [r2+six5535]
@OC@ [r2+six5535+1]
@OC@ [r2+two701867]
@OC@ [r2+-two701867]
@OC@ [r2-two701867]
@OC@ [r2+externalsym]
@OC@ [r2+0]
@OC@ [r2+1]
@OC@ [r2+127]
@OC@ [r2+128]
@OC@ [r2+-1]
@OC@ [r2-1]
@OC@ [r2+-127]
@OC@ [r2+-128]
@OC@ [r2-127]
@OC@ [r2-128]
@OC@ [r2+255]
@OC@ [r2+-255]
@OC@ [r2-255]
@OC@ [r2+256]
@OC@ [r2-256]
@OC@ [r2-8856]
@OC@ [r2+-256]
@OC@ [r2+-8856]
@OC@ [r2+8856]
@OC@ [r2+2781868]
@OC@ [r2+-2701867]
@OC@ [r2+0x9ec0ceac]
@OC@ [r2+-0x7ec0cead]
@OC@ [r2-0x7ec0cead]
@OC@ [r2+const_int_m32]
@OC@ [r2+const_int_32]
@OC@ [r2+42]
@OC@ [r2-42]
@OC@ [r2+-42]
@OC@ [r2+forty2]
@OC@ [r2+mforty2]
@OC@ [r2-forty2]
@OC@ [r2-mforty2]
@OC@ [r2+-forty2]
@OC@ [r2+-mforty2]
@OC@ [r2+three2767]
@OC@ [r2+three2767+1]
@OC@ [r2+three2767+2]
@OC@ [r2+-three2767]
@OC@ [r2+-(three2767+1)]
@OC@ [r2+-(three2767+2)]
@OC@ [r2-three2767]
@OC@ [r2-(three2767+1)]
@OC@ [r2-(three2767+2)]
@OC@ [r2+six5535]
@OC@ [r2+six5535+1]
@OC@ [r2+two701867]
@OC@ [r2+-two701867]
@OC@ [r2-two701867]
@OC@ [r2+externalsym]
;;;;;;;;;;;;;;;;;
;
; [r=r+X],r
; [r=r+r.b],r
@OC@.b [r12=r2+r0.b]
@OC@.w [r12=r2+r5.b]
@OC@.d [r12=r2+r10.b]
@OC@ [r1=r2+r3.b]
@OC@ [r12=r2+r10.b]
; [r=r+[r].b],r
@OC@.b [r12=r2+[r0].b]
@OC@.w [r12=r2+[r5].b]
@OC@.d [r12=r2+[r10].b]
@OC@ [r0=r2+[r5].b]
@OC@ [r3=r2+[r10].b]
; [r=r+[r+].b],r
@OC@.b [r12=r2+[r0+].b]
@OC@.w [r12=r2+[r5+].b]
@OC@.d [r12=r2+[r10+].b]
@OC@.w [r12=r2+[r5+].b]
@OC@.d [r12=r2+[r10+].b]
@OC@ [r5=r2+[r4+].b]
@OC@ [r2=r4+[r7+].b]
; [r=r+r.w],r
@OC@.b [r12=r2+r0.w]
@OC@.w [r12=r2+r5.w]
@OC@.d [r12=r2+r10.w]
@OC@ [r12=r12+r5.w]
@OC@ [r1=r3+r10.w]
; [r=r+[r].w],r
@OC@.b [r12=r2+[r0].w]
@OC@.w [r12=r2+[r5].w]
@OC@.d [r12=r2+[r10].w]
@OC@ [r12=r2+[r5].w]
@OC@ [r12=r7+[r10].w]
; [r=r+[r+].w],r
@OC@.b [r12=r2+[r0+].w]
@OC@.w [r12=r2+[r5+].w]
@OC@.d [r12=r2+[r10+].w]
@OC@.w [r12=r2+[r5+].w]
@OC@.d [r12=r2+[r10+].w]
@OC@ [r12=r6+[r7+].w]
@OC@ [r12=r3+[r1+].w]
; [r=r+r.d],r
@OC@.b [r12=r2+r0.d]
@OC@.w [r12=r2+r5.d]
@OC@.d [r12=r2+r10.d]
@OC@ [r4=r2+r5.d]
@OC@ [r12=r2+r10.d]
; [r=r+[r].d],r
@OC@.b [r12=r2+[r0].d]
@OC@.w [r12=r2+[r5].d]
@OC@.d [r12=r2+[r10].d]
@OC@ [r12=r3+[r5].d]
@OC@ [r12=r4+[r10].d]
; [r=r+[r+].d],r
@OC@.b [r12=r2+[r0+].d]
@OC@.w [r12=r2+[r5+].d]
@OC@.d [r12=r2+[r10+].d]
@OC@.w [r12=r2+[r5+].d]
@OC@.d [r12=r2+[r10+].d]
@OC@ [r12=r8+[r5+].d]
@OC@ [r12=r9+[r10+].d]
; [r=r+const],r
@OC@.b [r12=r2+0]
@OC@.b [r12=r2+1]
@OC@.b [r12=r2+127]
@OC@.b [r12=r2+128]
@OC@.b [r12=r2+-1]
@OC@.b [r12=r2+-127]
@OC@.b [r12=r2+-128]
@OC@.b [r12=r2+255]
@OC@.b [r12=r2+42]
@OC@.b [r12=r2+-42]
@OC@.b [r12=r2-42]
@OC@.b [r12=r2+forty2]
@OC@.b [r12=r2+mforty2]
@OC@.b [r12=r2+-forty2]
@OC@.b [r12=r2+-mforty2]
@OC@.b [r12=r2-forty2]
@OC@.b [r12=r2-mforty2]
@OC@.b [r12=r2+externalsym]
@OC@.w [r12=r2+0]
@OC@.w [r12=r2+1]
@OC@.w [r12=r2+127]
@OC@.w [r12=r2+128]
@OC@.w [r12=r2+-1]
@OC@.w [r12=r2-1]
@OC@.w [r12=r2+-127]
@OC@.w [r12=r2+-128]
@OC@.w [r12=r2+-129]
@OC@.w [r12=r2-127]
@OC@.w [r12=r2-128]
@OC@.w [r12=r2-129]
@OC@.w [r12=r2+255]
@OC@.w [r12=r2+-255]
@OC@.w [r12=r2-255]
@OC@.w [r12=r2+256]
@OC@.w [r12=r2-256]
@OC@.w [r12=r2+-8856]
@OC@.w [r12=r2-8856]
@OC@.w [r12=r2+8856]
@OC@.w [r12=r2+42]
@OC@.w [r12=r2+-42]
@OC@.w [r12=r2-42]
@OC@.w [r12=r2+forty2]
@OC@.w [r12=r2+mforty2]
@OC@.w [r12=r2+-forty2]
@OC@.w [r12=r2-forty2]
@OC@.w [r12=r2+-mforty2]
@OC@.w [r12=r2+three2767]
@OC@.w [r12=r2+three2767+1]
@OC@.w [r12=r2+three2767+2]
@OC@.w [r12=r2+-three2767]
@OC@.w [r12=r2+-(three2767+1)]
@OC@.w [r12=r2+-(three2767+2)]
@OC@.w [r12=r2-three2767]
@OC@.w [r12=r2-(three2767+1)]
@OC@.w [r12=r2-(three2767+2)]
@OC@.w [r12=r2+six5535]
@OC@.w [r12=r2+externalsym]
@OC@.d [r12=r2+0]
@OC@.d [r12=r2+1]
@OC@.d [r12=r2+127]
@OC@.d [r12=r2+128]
@OC@.d [r12=r2+-1]
@OC@.d [r12=r2-1]
@OC@.d [r12=r2+-127]
@OC@.d [r12=r2+-128]
@OC@.d [r12=r2-127]
@OC@.d [r12=r2-128]
@OC@.d [r12=r2+255]
@OC@.d [r12=r2+-255]
@OC@.d [r12=r2-255]
@OC@.d [r12=r2+256]
@OC@.d [r12=r2-256]
@OC@.d [r12=r2-8856]
@OC@.d [r12=r2+-256]
@OC@.d [r12=r2+-8856]
@OC@.d [r12=r2+8856]
@OC@.d [r12=r2+2781868]
@OC@.d [r12=r2+-2701867]
@OC@.d [r12=r2+0x9ec0ceac]
@OC@.d [r12=r2+-0x7ec0cead]
@OC@.d [r12=r2-0x7ec0cead]
@OC@.d [r12=r2+const_int_m32]
@OC@.d [r12=r2+const_int_32]
@OC@.d [r12=r2+42]
@OC@.d [r12=r2-42]
@OC@.d [r12=r2+-42]
@OC@.d [r12=r2+forty2]
@OC@.d [r12=r2+mforty2]
@OC@.d [r12=r2-forty2]
@OC@.d [r12=r2-mforty2]
@OC@.d [r12=r2+-forty2]
@OC@.d [r12=r2+-mforty2]
@OC@.d [r12=r2+three2767]
@OC@.d [r12=r2+three2767+1]
@OC@.d [r12=r2+three2767+2]
@OC@.d [r12=r2+-three2767]
@OC@.d [r12=r2+-(three2767+1)]
@OC@.d [r12=r2+-(three2767+2)]
@OC@.d [r12=r2-three2767]
@OC@.d [r12=r2-(three2767+1)]
@OC@.d [r12=r2-(three2767+2)]
@OC@.d [r12=r2+six5535]
@OC@.d [r12=r2+six5535+1]
@OC@.d [r12=r2+two701867]
@OC@.d [r12=r2+-two701867]
@OC@.d [r12=r2-two701867]
@OC@.d [r12=r2+externalsym]
@OC@ [r12=r2+0]
@OC@ [r12=r2+1]
@OC@ [r12=r2+127]
@OC@ [r12=r2+128]
@OC@ [r12=r2+-1]
@OC@ [r12=r2-1]
@OC@ [r12=r2+-127]
@OC@ [r12=r2+-128]
@OC@ [r12=r2-127]
@OC@ [r12=r2-128]
@OC@ [r12=r2+255]
@OC@ [r12=r2+-255]
@OC@ [r12=r2-255]
@OC@ [r12=r2+256]
@OC@ [r12=r2-256]
@OC@ [r12=r2-8856]
@OC@ [r12=r2+-256]
@OC@ [r12=r2+-8856]
@OC@ [r12=r2+8856]
@OC@ [r12=r2+2781868]
@OC@ [r12=r2+-2701867]
@OC@ [r12=r2+0x9ec0ceac]
@OC@ [r12=r2+-0x7ec0cead]
@OC@ [r12=r2-0x7ec0cead]
@OC@ [r12=r2+const_int_m32]
@OC@ [r12=r2+const_int_32]
@OC@ [r12=r2+42]
@OC@ [r12=r2-42]
@OC@ [r12=r2+-42]
@OC@ [r12=r2+forty2]
@OC@ [r12=r2+mforty2]
@OC@ [r12=r2-forty2]
@OC@ [r12=r2-mforty2]
@OC@ [r12=r2+-forty2]
@OC@ [r12=r2+-mforty2]
@OC@ [r12=r2+three2767]
@OC@ [r12=r2+three2767+1]
@OC@ [r12=r2+three2767+2]
@OC@ [r12=r2+-three2767]
@OC@ [r12=r2+-(three2767+1)]
@OC@ [r12=r2+-(three2767+2)]
@OC@ [r12=r2-three2767]
@OC@ [r12=r2-(three2767+1)]
@OC@ [r12=r2-(three2767+2)]
@OC@ [r12=r2+six5535]
@OC@ [r12=r2+six5535+1]
@OC@ [r12=r2+two701867]
@OC@ [r12=r2+-two701867]
@OC@ [r12=r2-two701867]
@OC@ [r12=r2+externalsym]
;;;;;;;;;;;;;;;;;;;
;
; [[r(+)]],r
@OC@.b [[r3]]
@OC@.w [[r2]]
@OC@.d [[r3]]
@OC@ [[r2]]
@OC@ [[r3]]
@OC@.b [[r9+]]
@OC@.w [[r3+]]
@OC@.d [[r1+]]
@OC@ [[r3+]]
@OC@ [[r1+]]
@OC@.b [externalsym]
@OC@.w [externalsym]
@OC@.d [externalsym]
@OC@ [externalsym]
@OC@.b [notstart]
@OC@.w [notstart]
@OC@.d [notstart]
@OC@ [notstart]
end:
|
tactcomplabs/xbgas-binutils-gdb
| 4,273
|
gas/testsuite/gas/cris/range-err-1.s
|
; Test error cases for constant ranges.
; { dg-do assemble { target cris-*-* } }
.set two701867, 2701867
.set mtwo701867, -2701867
.set const_int_32, 0x1b94452b
.set const_int_m32, -3513208907
.set three2767, 32767
.text
.syntax no_register_prefix
start:
moveq 32,r0 ; { dg-error "Immediate value not in 6 bit range: 32" }
moveq 63,r0 ; { dg-error "Immediate value not in 6 bit range: 63" }
moveq 0x20,r0 ; { dg-error "Immediate value not in 6 bit range: 32" }
moveq 0x3f,r0 ; { dg-error "Immediate value not in 6 bit range: 63" }
moveq -33,r0 ; { dg-error "Immediate value not in 6 bit range: -33" }
addq 64,r0 ; { dg-error "Immediate value not in 6 bit unsigned range: 64" }
addq -1,r0 ; { dg-error "Immediate value not in 6 bit unsigned range: -1" }
subq 64,r0 ; { dg-error "Immediate value not in 6 bit unsigned range: 64" }
subq -1,r0 ; { dg-error "Immediate value not in 6 bit unsigned range: -1" }
break 16 ; { dg-error "Immediate value not in 4 bit unsigned range: 16" }
movs.b 256,r0 ; { dg-error "Immediate value not in 8 bit range: 256" }
movs.b 255,r0 ; { dg-error "Immediate value not in 8 bit range: 255" "" { xfail *-*-* } }
movs.b -129,r0 ; { dg-error "Immediate value not in 8 bit range: -129" }
movs.b 128,r0 ; { dg-error "Immediate value not in 8 bit range: 128" "" { xfail *-*-* } }
movs.b -32769,r0 ; { dg-error "Immediate value not in (8|16) bit range: -32769" }
movs.b 0xffffffff,r0 ; { dg-error "Immediate value not in (8|16) bit range: (4294967295|-1)" }
movs.w 32768,r0 ; { dg-error "Immediate value not in 16 bit range: 32768" "" { xfail *-*-* } }
movs.w 0x8000,r0 ; { dg-error "Immediate value not in 16 bit range: 32768" "" { xfail *-*-* } }
movs.w 65535,r0 ; { dg-error "Immediate value not in 16 bit range: 65535" "" { xfail *-*-* } }
movs.w 0xffff,r0 ; { dg-error "Immediate value not in 16 bit range: 65535" "" { xfail *-*-* } }
movs.w -32769,r0 ; { dg-error "Immediate value not in 16 bit range: -32769" }
movs.w 65536,r0 ; { dg-error "Immediate value not in 16 bit range: 65536" }
movs.w -32769,r0 ; { dg-error "Immediate value not in 16 bit range: -32769" }
movs.w 0xffffffff,r0 ; { dg-error "Immediate value not in 16 bit range: (4294967295|-1)" }
movu.b 256,r0 ; { dg-error "Immediate value not in 8 bit range: 256" }
movu.b 0x100,r0 ; { dg-error "Immediate value not in 8 bit range: 256" }
movu.b -1,r0 ; { dg-error "Immediate value not in 8 bit unsigned range: -1" "" { xfail *-*-* } }
movu.b -127,r0 ; { dg-error "Immediate value not in 8 bit unsigned range: -127" "" { xfail *-*-* } }
movu.b -129,r0 ; { dg-error "Immediate value not in 8 bit range: -129" }
movu.b -128,r0 ; { dg-error "Immediate value not in 8 bit unsigned range: -128" "" { xfail *-*-* } }
movu.w 65536,r0 ; { dg-error "Immediate value not in 16 bit range: 65536" }
movu.w -32769,r0 ; { dg-error "Immediate value not in 16 bit range: -32769" }
movu.w -1,r0 ; { dg-error "Immediate value not in 16 bit unsigned range: -1" "" { xfail *-*-* } }
movu.w 0xffffffff,r0 ; { dg-error "Immediate value not in 16 bit (unsigned )?range: (4294967295|-1)" }
add.b -129,r5 ; { dg-error "Immediate value not in 8 bit range: -129" }
add.b -255,r5 ; { dg-error "Immediate value not in 8 bit range: -255" }
add.b 256,r5 ; { dg-error "Immediate value not in 8 bit range: 256" }
add.b -8856,r5 ; { dg-error "Immediate value not in 8 bit range: -8856" }
add.b 8856,r5 ; { dg-error "Immediate value not in 8 bit range: 8856" }
add.w two701867,r13 ; { dg-error "Immediate value not in 16 bit range: 2701867" }
add.w mtwo701867,r13 ; { dg-error "Immediate value not in 16 bit range: -2701867" }
add.w 2781868,r13 ; { dg-error "Immediate value not in 16 bit range: 2781868" }
add.w -2701867,r13 ; { dg-error "Immediate value not in 16 bit range: -2701867" }
add.w 0x9ec0ceac,r13 ; { dg-error "Immediate value not in 16 bit range: (2663435948|-1631531348)" }
add.w -0x7ec0cead,r13 ; { dg-error "Immediate value not in 16 bit range: -2126565037" }
add.w const_int_m32,r13 ; { dg-error "Immediate value not in 16 bit range: (-3513208907|781758389)" }
add.w const_int_32,r13 ; { dg-error "Immediate value not in 16 bit range: 462701867" }
add.w -(three2767+2),r5 ; { dg-error "Immediate value not in 16 bit range: -32769" }
|
tactcomplabs/xbgas-binutils-gdb
| 2,621
|
gas/testsuite/gas/cris/prefix.s
|
; See that prefix insns are assembled right.
.text
.syntax no_register_prefix
start:
;
; bdap (8-bit signed offset).
;
bdap 0,r0
move.b [r5],r4
bdap 0,r3
move.w [r6+],r4
bdap -1,r1
move.b [r5],r4
bdap -1,r0
move.w [r6+],r4
bdap -128,r1
move.b [r5],r4
bdap -128,r7
move.w [r6+],r4
bdap 127,r1
move.b [r5],r4
bdap 127,r11
move.w [r6],r4
;
; bdap.S [],r
;
bdap.b 0,r4
move.d [r7+],r9
bdap.b 1,r5
move.b [r5],r4
bdap.b -1,r6
move.d [r7+],r9
bdap.b -128,r6
move.d [r7],r9
bdap.b 127,r6
move.w [r6+],r4
bdap.w 0,r4
move.d [r7+],r9
bdap.w 1,r5
move.b [r5],r4
bdap.w -1,r6
move.d [r7+],r9
bdap.w -128,r6
move.d [r7],r9
bdap.w 127,r6
move.w [r6+],r4
bdap.w -129,r6
move.d [r7],r9
bdap.w 128,r6
move.d [r7],r9
bdap.w -32768,r6
move.b [r5],r4
bdap.w 32767,r6
move.w [r5+],r5
bdap.d 0,r4
move.d [r7+],r9
bdap.d 1,r5
move.b [r5],r4
bdap.d -1,r6
move.d [r7+],r9
bdap.d -128,r6
move.d [r7],r9
bdap.d 127,r6
move.w [r6+],r4
bdap.d -129,r6
move.d [r7],r9
bdap.d 128,r6
move.d [r7],r9
bdap.d -32768,r6
move.b [r5],r4
bdap.d 32767,r6
move.w [r5+],r5
bdap.d -32769,r6
move.w [r6+],r4
bdap.d 32768,r6
move.w [r6],r4
bdap.d -327680,r6
move.b [r5],r4
bdap.d 21474805,r6
move.w [r5+],r5
bdap.d -2147483648,r6
move.d [r7],r9
bdap.d 2147483647,r6
move.b [r5],r4
bdap.d external_symbol,r6
move.w [r5+],r5
bdap.b [r0],r2
move.d [r6+],r4
bdap.w [r0],r2
move.b [r5],r4
bdap.d [r0],r2
move.d [r6+],r4
bdap.b [r10],r2
move.d [r6+],r4
bdap.w [r10],r2
move.b [r5],r4
bdap.d [r10],r2
move.d [r6+],r4
bdap.b [r2+],r2
move.w [r6],r4
bdap.w [r11+],r2
move.w [r5+],r5
bdap.d [r10+],r2
move.w [r6],r4
;
; BIAP.m (like addi).
;
biap.b r3,r0
move.b [r5],r4
biap.w r5,r3
move.w [r6+],r4
biap.d r13,r13
move.b [r5],r4
biap.b r6,r6
move.w [r6+],r4
biap.w r13,r13
move.b [r5],r4
biap.d r11,r12
move.w [r6+],r4
biap.w r5,r4
move.b [r5],r4
biap.b r3,r3
move.w [r6+],r4
biap.d r5,r5
move.w [r5+],r5
;
; DIP []
;
dip 0
move.d [r7+],r9
dip 1
move.b [r5],r4
dip -1
move.d [r7+],r9
dip -128
move.d [r7],r9
dip 127
move.w [r6+],r4
dip -129
move.d [r7],r9
dip 128
move.d [r7],r9
dip -32768
move.b [r5],r4
dip 32767
move.w [r5+],r5
dip -32769
move.w [r6+],r4
dip 32768
move.w [r6],r4
dip -327680
move.b [r5],r4
dip 21474805
move.w [r5+],r5
dip -2147483648
move.d [r7],r9
dip 2147483647
move.b [r5],r4
dip external_symbol
move.w [r5+],r5
dip [r10]
move.d [r6+],r4
dip [r11]
move.d [r7],r4
dip [r2+]
move.w [r6],r4
dip [r11+]
move.w [r5+],r5
end:
|
tactcomplabs/xbgas-binutils-gdb
| 1,246
|
gas/testsuite/gas/cris/regprefix-err-1.s
|
; Test that we get errors when we require a register prefix.
; { dg-do assemble }
.syntax register_prefix
start:
; Some simple tests that we indeed require a register prefix, and some
; that should not be flagged as syntax errors.
push srp ; { dg-error "(Illegal|Invalid) operands" }
push r3 ; { dg-error "(Illegal|Invalid) operands" }
move.d $r7,r8 ; { dg-error "(Illegal|Invalid) operands" }
move.d r8,[$r11] ; { dg-error "(Illegal|Invalid) operands" }
move.d $r8,[$r11+]
move.d $r8,[$r10+$r9.b]
move.d $r7,[$r10+[$r1].d]
move.d $r7,[$r10+[$r3+].w]
move $r8,srp ; { dg-error "(Illegal|Invalid) operands" }
move ccr,$r13 ; { dg-error "(Illegal|Invalid) operands" }
movem r4,[$r12+] ; { dg-error "(Illegal|Invalid) operands" }
; Here we have no ambiguity; r10 can only be a symbol when we reuire a
; prefix. It does not just miss a size specifier, e.g. as in [r12+r10.d].
move.d $r13,[$r12+r10]
.syntax no_register_prefix
; Perhaps in this one we should backtrack and retry r10 as a symbol, but
; the ambiguity is closer to a programming error, so we should catch it as
; such.
move.d $r13,[$r12+r10] ; { dg-error "(Illegal|Invalid) operands" }
move.d r13,[r12+r16] ; No register named r16 so must be a symbol.
nop
|
tactcomplabs/xbgas-binutils-gdb
| 1,264
|
gas/testsuite/gas/cris/rd-v32s-4.s
|
; Check special registers specified as pN.
.text
here:
move $r3,$p0
move $r5,$p1
move $r6,$p2
move $r7,$p3
move $r8,$p4
move $r9,$p5
move $r5,$p6
move $r6,$p7
move $r7,$p8
move $r2,$p9
move $r4,$p10
move $r0,$p11
move $r6,$p12
move $r10,$p13
move $r12,$p14
move $r13,$p15
move $p0,$r3
move $p1,$r5
move $p2,$r6
move $p3,$r7
move $p4,$r8
move $p5,$r9
move $p6,$r5
move $p7,$r6
move $p8,$r7
move $p9,$r2
move $p10,$r4
move $p11,$r0
move $p12,$r6
move $p13,$r10
move $p14,$r12
move $p15,$r13
move 3,$p0
move 5,$p1
move 6,$p2
move 7,$p3
move 8,$p4
move 9,$p5
move 10,$p6
move 101,$p7
move 120,$p8
move 13,$p9
move 4,$p10
move 0,$p11
move 6,$p12
move 10,$p13
move 12,$p14
move 13,$p15
move $p0,[$r3]
move $p1,[$r5]
move $p2,[$r6]
move $p3,[$r7]
move $p4,[$r8]
move $p5,[$r9]
move $p6,[$r5]
move $p7,[$r6]
move $p8,[$r7]
move $p9,[$r2]
move $p10,[$r4]
move $p11,[$r0]
move $p12,[$r6]
move $p13,[$r10]
move $p14,[$r12]
move $p15,[$r13]
move [$r3],$p0
move [$r5],$p1
move [$r6],$p2
move [$r7],$p3
move [$r8],$p4
move [$r9],$p5
move [$r5],$p6
move [$r6],$p7
move [$r7],$p8
move [$r2],$p9
move [$r4],$p10
move [$r0],$p11
move [$r6],$p12
move [$r10],$p13
move [$r12],$p14
move [$r13],$p15
|
tactcomplabs/xbgas-binutils-gdb
| 1,330
|
gas/testsuite/gas/cris/ccr.s
|
; Flag settings; clearf, setf
.text
.syntax no_register_prefix
start:
nop ; So we get it tested too -- and it makes the
; size of the code a 32-bit multiple, so
; the end of disassembly does not show zeros.
ax
setf deixnzvc ; old names
clearf deixnzvc ; old names
ei
di
setf dxnc ; old names
clearf dxnc ; old names
setf ; empty list
clearf ; empty list
; For each flag. Note that the disassembly will show macros for
; some.
setf c
clearf c
setf v
clearf v
setf z
clearf z
setf n
clearf n
setf x
clearf x
setf i
clearf i
setf e
clearf e
setf d
clearf d
; Two from same group, and switch order.
clearf vc
setf vc
clearf ix
setf ix
clearf cv
setf cv
clearf xi
setf xi
; Two from different groups, and switch order.
clearf in
setf in
clearf ni
setf ni
; Four in same group, and switch order.
clearf nvxc
setf nvxc
clearf vncx
setf vncx
clearf dxei
setf dxei
clearf xide
setf xide
; Four in different groups, and switch order.
clearf exnv
setf exnv
clearf xvne
setf xvne
; FIXME: Put tests for new flag-names here, (not above.
; The new names in ETRAX 100, just some assortment of the above.
setf mbixnzvc
clearf bmixnzvc
setf b
clearf b
setf m
clearf m
clearf mxbi
setf dxbi
clearf ximb
setf ximb
clearf bxnv
setf bxnv
clearf xvnb
setf xvnb
end:
|
tactcomplabs/xbgas-binutils-gdb
| 2,085
|
gas/testsuite/gas/cris/pushpop.s
|
; Check the push and pop builtin "macros".
.text
.syntax no_register_prefix
start:
push r1
push r0
push r4
; Check that there is no recognition of invalid offsets.
move.b r5,[sp=sp-8]
move.w r5,[sp=sp-8]
move.d r5,[sp=sp-8]
move.b r5,[sp=sp-5]
move.w r5,[sp=sp-5]
move.d r5,[sp=sp-5]
move.w r5,[sp=sp-4]
move.b r3,[sp=sp-4]
move.d r5,[sp=sp-3]
move.w r11,[sp=sp-3]
move.b r5,[sp=sp-3]
move.d r5,[sp=sp-2]
move.b r5,[sp=sp-2]
move.d r5,[sp=sp-1]
move.w r5,[sp=sp-1]
move.d r5,[sp=sp+0]
move.b r5,[sp=sp+0]
move.w r5,[sp=sp+0]
move.d r5,[sp=sp+1]
move.w r5,[sp=sp+1]
move.b r5,[sp=sp+1]
move.d r5,[sp=sp+2]
move.w r5,[sp=sp+2]
move.b r5,[sp=sp+2]
move.d r5,[sp=sp+3]
move.w r5,[sp=sp+3]
move.b r5,[sp=sp+3]
move.d r5,[sp=sp+4]
move.w r5,[sp=sp+4]
move.b r5,[sp=sp+4]
move.d r5,[sp=sp+5]
move.w r5,[sp=sp+5]
move.b r5,[sp=sp+5]
move.d r1,[sp=sp+8]
move.w r9,[sp=sp+8]
move.b r13,[sp=sp+8]
;
; All these will have postincrement on the "real" instruction
; (e.g. "move.d [sp+],r6") which is the actual insn recognized as
; pop; it is *not* e.g. "move.d [sp=sp+4],r6".
; Here we make sure that neither the combination nor the second
; is interpreted as a pop.
;
move.b [sp=sp+8],r5
move.w [sp=sp+8],r5
move.d [sp=sp+8],r5
move.b [sp=sp+5],r5
move.w [sp=sp+5],r5
move.d [sp=sp+5],r5
move.d [sp=sp+4],r5
move.w [sp=sp+4],r5
move.b [sp=sp+4],r3
move.d [sp=sp+3],r5
move.w [sp=sp+3],r11
move.b [sp=sp+3],r5
move.d [sp=sp+2],r5
move.w [sp=sp+2],r5
move.b [sp=sp+2],r5
move.d [sp=sp+1],r5
move.w [sp=sp+1],r5
move.b [sp=sp+1],r5
move.d [sp=sp-0],r5
move.w [sp=sp-0],r5
move.b [sp=sp-0],r5
move.d [sp=sp-1],r5
move.w [sp=sp-1],r5
move.b [sp=sp-1],r5
move.d [sp=sp-2],r5
move.w [sp=sp-2],r5
move.b [sp=sp-2],r5
move.d [sp=sp-3],r5
move.w [sp=sp-3],r5
move.b [sp=sp-3],r5
move.d [sp=sp-4],r5
move.w [sp=sp-4],r5
move.b [sp=sp-4],r5
move.d [sp=sp-5],r5
move.w [sp=sp-5],r5
move.b [sp=sp-5],r5
move.d [sp=sp-8],r5
move.w [sp=sp-8],r5
move.b [sp=sp-8],r5
push r0
pop r2
pop r3
push r13
end:
|
tactcomplabs/xbgas-binutils-gdb
| 17,891
|
gas/testsuite/gas/cris/binop.s
|
; @OC@ test
; Generic binary operations supporting all sizes and their various
; addressing modes.
; Some fairly big pseudorandom numbers we don't want to compute
; as differences in actual data or code.
.set const_int_32, 0x1b94452b
.set const_int_m32, -3513208907
.set two701867, 2701867
; Other constants that are not differences
.set forty2, 42
.set mforty2, -42
.set three2767, 32767
.set six5535, 65535
.text
.syntax no_register_prefix
notstart:
.dword 0
start:
;;;;;;;;;;;;;;;;;
;
; r,r
@OC@.b r3,r5
@OC@.w r5,r13
@OC@.d r10,r1
;;;;;;;;;;;;;;;;;
;
; [r],r
@OC@.b [r0],r5
@OC@.w [r5],r13
@OC@.d [r10],r1
@OC@ r13,[r5]
@OC@ r1,[r10]
;;;;;;;;;;;;;;;;;
;
; [r+],r
@OC@.b [r0+],r5
@OC@.w [r5+],r13
@OC@.d [r10+],r1
@OC@ r13,[r5+]
@OC@ r4,[r10+]
;;;;;;;;;;;;;;;;;
;
; const,r
@OC@.b 0,r5
@OC@.b 1,r5
@OC@.b 127,r5
@OC@.b 128,r5
@OC@.b -1,r5
@OC@.b -127,r5
@OC@.b -128,r5
@OC@.b 255,r5
@OC@.b 42,r5
@OC@.b -42,r5
@OC@.b forty2,r5
@OC@.b mforty2,r5
@OC@.b -forty2,r5
@OC@.b -mforty2,r5
@OC@.b externalsym,r5
@OC@.w 0,r13
@OC@.w 1,r13
@OC@.w 127,r13
@OC@.w 128,r13
@OC@.w -1,r13
@OC@.w -127,r13
@OC@.w -128,r13
@OC@.w -129,r13
@OC@.w 255,r13
@OC@.w -255,r13
@OC@.w 256,r13
@OC@.w -8856,r13
@OC@.w 8856,r13
@OC@.w 42,r13
@OC@.w -42,r13
@OC@.w forty2,r13
@OC@.w mforty2,r13
@OC@.w -forty2,r5
@OC@.w -mforty2,r5
@OC@.w three2767,r5
@OC@.w three2767+1,r5
@OC@.w three2767+2,r13
@OC@.w -three2767,r13
@OC@.w -(three2767+1),r13
@OC@.w six5535,r5
@OC@.w externalsym,r5
@OC@.d 0,r1
@OC@.d 1,r1
@OC@.d 127,r1
@OC@.d 128,r1
@OC@.d -1,r1
@OC@.d -127,r1
@OC@.d -128,r1
@OC@.d 255,r1
@OC@.d -255,r1
@OC@.d 256,r1
@OC@.d -8856,r1
@OC@.d 8856,r1
@OC@.d 2781868,r1
@OC@.d -2701867,r1
@OC@.d 0x9ec0ceac,r1
@OC@.d -0x7ec0cead,r1
@OC@.d const_int_m32,r1
@OC@.d const_int_32,r1
@OC@.d 42,r13
@OC@.d -42,r5
@OC@.d forty2,r5
@OC@.d mforty2,r5
@OC@.d -forty2,r5
@OC@.d -mforty2,r5
@OC@.d three2767,r5
@OC@.d three2767+1,r5
@OC@.d three2767+2,r5
@OC@.d -three2767,r5
@OC@.d -(three2767+1),r13
@OC@.d -(three2767+2),r13
@OC@.d six5535,r5
@OC@.d six5535+1,r13
@OC@.d two701867,r5
@OC@.d -two701867,r5
@OC@.d externalsym,r5
;;;;;;;;;;;;;;;;;
;
; [r+X],r
; [r+r.b],r
@OC@.b [r2+r0.b],r5
@OC@.w [r2+r5.b],r13
@OC@.d [r2+r10.b],r1
@OC@ r13,[r2+r5.b]
@OC@ r3,[r2+r10.b]
; [r+[r].b],r
@OC@.b [r2+[r0].b],r5
@OC@.w [r2+[r5].b],r13
@OC@.d [r2+[r10].b],r1
@OC@ r13,[r2+[r5].b]
@OC@ r2,[r2+[r10].b]
; [r+[r+].b],r
@OC@.b [r2+[r0+].b],r5
@OC@.w [r2+[r5+].b],r13
@OC@.d [r2+[r10+].b],r1
@OC@.w [r2+[r5+].b],r13
@OC@.d [r2+[r10+].b],r1
@OC@ r0,[r2+[r5+].b]
@OC@ r12,[r2+[r10+].b]
; [r+r.w],r
@OC@.b [r2+r0.w],r5
@OC@.w [r2+r5.w],r13
@OC@.d [r2+r10.w],r1
; [r+[r].w],r
@OC@.b [r2+[r0].w],r5
@OC@.w [r2+[r5].w],r13
@OC@.d [r2+[r10].w],r1
@OC@ r2,[r2+[r5].w]
@OC@ r6,[r2+[r10].w]
; [r+[r+].w],r
@OC@.b [r2+[r0+].w],r5
@OC@.w [r2+[r5+].w],r13
@OC@.d [r2+[r10+].w],r1
@OC@.w [r2+[r5+].w],r13
@OC@.d [r2+[r10+].w],r1
@OC@ r7,[r2+[r5+].w]
@OC@ r8,[r2+[r10+].w]
; [r+r.d],r
@OC@.b [r2+r0.d],r5
@OC@.w [r2+r5.d],r13
@OC@.d [r2+r10.d],r1
@OC@ r12,[r2+r5.d]
@OC@ r9,[r2+r10.d]
; [r+[r].d],r
@OC@.b [r2+[r0].d],r5
@OC@.w [r2+[r5].d],r13
@OC@.d [r2+[r10].d],r1
@OC@ r13,[r2+[r5].d]
@OC@ r8,[r2+[r10].d]
; [r+[r+].d],r
@OC@.b [r2+[r0+].d],r5
@OC@.w [r2+[r5+].d],r13
@OC@.d [r2+[r10+].d],r1
@OC@.w [r2+[r5+].d],r13
@OC@.d [r2+[r10+].d],r1
@OC@ r0,[r2+[r5+].d]
@OC@ r5,[r2+[r10+].d]
; [r+const],r
; Note that I forgot 16-bit offsets and 32-bit offsets here and later.
; Maybe add them later if it feels necessary.
@OC@.b [r2+0],r5
@OC@.b [r2+1],r5
@OC@.b [r2+127],r5
@OC@.b [r2+128],r5
@OC@.b [r2+-1],r5
@OC@.b [r2+-127],r5
@OC@.b [r2+-128],r5
@OC@.b [r2+255],r5
@OC@.b [r2+42],r5
@OC@.b [r2+-42],r5
@OC@.b [r2-42],r5
@OC@.b [r2+forty2],r5
@OC@.b [r2+mforty2],r5
@OC@.b [r2+-forty2],r5
@OC@.b [r2+-mforty2],r5
@OC@.b [r2-forty2],r5
@OC@.b [r2-mforty2],r5
@OC@.b [r2+externalsym],r5
; Note that I missed 32-bit offsets (except -32769) here and later.
; Maybe add them later if it feels necessary.
@OC@.w [r2+0],r13
@OC@.w [r2+1],r13
@OC@.w [r2+127],r13
@OC@.w [r2+128],r13
@OC@.w [r2+-1],r13
@OC@.w [r2-1],r13
@OC@.w [r2+-127],r13
@OC@.w [r2+-128],r13
@OC@.w [r2+-129],r13
@OC@.w [r2-127],r13
@OC@.w [r2-128],r13
@OC@.w [r2-129],r13
@OC@.w [r2+255],r13
@OC@.w [r2+-255],r13
@OC@.w [r2-255],r13
@OC@.w [r2+256],r13
@OC@.w [r2-256],r13
@OC@.w [r2+-8856],r13
@OC@.w [r2-8856],r13
@OC@.w [r2+8856],r13
@OC@.w [r2+42],r13
@OC@.w [r2+-42],r13
@OC@.w [r2-42],r13
@OC@.w [r2+forty2],r13
@OC@.w [r2+mforty2],r13
@OC@.w [r2+-forty2],r5
@OC@.w [r2-forty2],r5
@OC@.w [r2+-mforty2],r5
@OC@.w [r2+three2767],r5
@OC@.w [r2+three2767+1],r5
@OC@.w [r2+three2767+2],r13
@OC@.w [r2+-three2767],r13
@OC@.w [r2+-(three2767+1)],r13
@OC@.w [r2+-(three2767+2)],r5
@OC@.w [r2-three2767],r13
@OC@.w [r2-(three2767+1)],r13
@OC@.w [r2-(three2767+2)],r5
@OC@.w [r2+six5535],r5
@OC@.w [r2+externalsym],r5
@OC@.d [r2+0],r1
@OC@.d [r2+1],r1
@OC@.d [r2+127],r1
@OC@.d [r2+128],r1
@OC@.d [r2+-1],r1
@OC@.d [r2-1],r1
@OC@.d [r2+-127],r1
@OC@.d [r2+-128],r1
@OC@.d [r2-127],r1
@OC@.d [r2-128],r1
@OC@.d [r2+255],r1
@OC@.d [r2+-255],r1
@OC@.d [r2-255],r1
@OC@.d [r2+256],r1
@OC@.d [r2-256],r1
@OC@.d [r2-8856],r1
@OC@.d [r2+-256],r1
@OC@.d [r2+-8856],r1
@OC@.d [r2+8856],r1
@OC@.d [r2+2781868],r1
@OC@.d [r2+-2701867],r1
@OC@.d [r2+0x9ec0ceac],r1
@OC@.d [r2+-0x7ec0cead],r1
@OC@.d [r2-0x7ec0cead],r1
@OC@.d [r2+const_int_m32],r1
@OC@.d [r2+const_int_32],r1
@OC@.d [r2+42],r13
@OC@.d [r2-42],r5
@OC@.d [r2+-42],r5
@OC@.d [r2+forty2],r5
@OC@.d [r2+mforty2],r5
@OC@.d [r2-forty2],r5
@OC@.d [r2-mforty2],r5
@OC@.d [r2+-forty2],r5
@OC@.d [r2+-mforty2],r5
@OC@.d [r2+three2767],r5
@OC@.d [r2+three2767+1],r5
@OC@.d [r2+three2767+2],r5
@OC@.d [r2+-three2767],r5
@OC@.d [r2+-(three2767+1)],r13
@OC@.d [r2+-(three2767+2)],r13
@OC@.d [r2-three2767],r5
@OC@.d [r2-(three2767+1)],r13
@OC@.d [r2-(three2767+2)],r13
@OC@.d [r2+six5535],r5
@OC@.d [r2+six5535+1],r13
@OC@.d [r2+two701867],r5
@OC@.d [r2+-two701867],r5
@OC@.d [r2-two701867],r5
@OC@.d [r2+externalsym],r5
@OC@ r1,[r2+0]
@OC@ r1,[r2+1]
@OC@ r1,[r2+127]
@OC@ r1,[r2+128]
@OC@ r1,[r2+-1]
@OC@ r1,[r2-1]
@OC@ r1,[r2+-127]
@OC@ r1,[r2+-128]
@OC@ r1,[r2-127]
@OC@ r1,[r2-128]
@OC@ r1,[r2+255]
@OC@ r1,[r2+-255]
@OC@ r1,[r2-255]
@OC@ r1,[r2+256]
@OC@ r1,[r2-256]
@OC@ r1,[r2-8856]
@OC@ r1,[r2+-256]
@OC@ r1,[r2+-8856]
@OC@ r1,[r2+8856]
@OC@ r1,[r2+2781868]
@OC@ r1,[r2+-2701867]
@OC@ r1,[r2+0x9ec0ceac]
@OC@ r1,[r2+-0x7ec0cead]
@OC@ r1,[r2-0x7ec0cead]
@OC@ r1,[r2+const_int_m32]
@OC@ r1,[r2+const_int_32]
@OC@ r13,[r2+42]
@OC@ r5,[r2-42]
@OC@ r5,[r2+-42]
@OC@ r5,[r2+forty2]
@OC@ r5,[r2+mforty2]
@OC@ r5,[r2-forty2]
@OC@ r5,[r2-mforty2]
@OC@ r5,[r2+-forty2]
@OC@ r5,[r2+-mforty2]
@OC@ r5,[r2+three2767]
@OC@ r5,[r2+three2767+1]
@OC@ r5,[r2+three2767+2]
@OC@ r5,[r2+-three2767]
@OC@ r13,[r2+-(three2767+1)]
@OC@ r13,[r2+-(three2767+2)]
@OC@ r5,[r2-three2767]
@OC@ r13,[r2-(three2767+1)]
@OC@ r13,[r2-(three2767+2)]
@OC@ r5,[r2+six5535]
@OC@ r13,[r2+six5535+1]
@OC@ r5,[r2+two701867]
@OC@ r5,[r2+-two701867]
@OC@ r5,[r2-two701867]
@OC@ r5,[r2+externalsym]
;;;;;;;;;;;;;;;;;
;
; [r+X],r,r
; [r+r.b],r,r
@OC@.b [r2+r0.b],r5,r8
@OC@.w [r2+r5.b],r13,r8
@OC@.d [r2+r10.b],r1,r8
; [r+[r].b],r,r
@OC@.b [r2+[r0].b],r5,r8
@OC@.w [r2+[r5].b],r13,r8
@OC@.d [r2+[r10].b],r1,r8
; [r+[r+].b],r,r
@OC@.b [r2+[r0+].b],r5,r8
@OC@.w [r2+[r5+].b],r13,r8
@OC@.d [r2+[r10+].b],r1,r8
@OC@.w [r2+[r5+].b],r13,r8
@OC@.d [r2+[r10+].b],r1,r8
; [r+r.w],r,r
@OC@.b [r2+r0.w],r5,r8
@OC@.w [r2+r5.w],r13,r8
@OC@.d [r2+r10.w],r1,r8
; [r+[r].w],r,r
@OC@.b [r2+[r0].w],r5,r8
@OC@.w [r2+[r5].w],r13,r8
@OC@.d [r2+[r10].w],r1,r8
; [r+[r+].w],r,r
@OC@.b [r2+[r0+].w],r5,r8
@OC@.w [r2+[r5+].w],r13,r8
@OC@.d [r2+[r10+].w],r1,r8
@OC@.w [r2+[r5+].w],r13,r8
@OC@.d [r2+[r10+].w],r1,r8
; [r+r.d],r,r
@OC@.b [r2+r0.d],r5,r8
@OC@.w [r2+r5.d],r13,r8
@OC@.d [r2+r10.d],r1,r8
; [r+[r].d],r,r
@OC@.b [r2+[r0].d],r5,r8
@OC@.w [r2+[r5].d],r13,r8
@OC@.d [r2+[r10].d],r1,r8
; [r+[r+].d],r,r
@OC@.b [r2+[r0+].d],r5,r8
@OC@.w [r2+[r5+].d],r13,r8
@OC@.d [r2+[r10+].d],r1,r8
@OC@.w [r2+[r5+].d],r13,r8
@OC@.d [r2+[r10+].d],r1,r8
; [r+const],r,r
@OC@.b [r2+0],r5,r8
@OC@.b [r2+1],r5,r8
@OC@.b [r2+127],r5,r8
@OC@.b [r2+128],r5,r8
@OC@.b [r2+-1],r5,r8
@OC@.b [r2+-127],r5,r8
@OC@.b [r2+-128],r5,r8
@OC@.b [r2+255],r5,r8
@OC@.b [r2+42],r5,r8
@OC@.b [r2+-42],r5,r8
@OC@.b [r2-42],r5,r8
@OC@.b [r2+forty2],r5,r8
@OC@.b [r2+mforty2],r5,r8
@OC@.b [r2+-forty2],r5,r8
@OC@.b [r2+-mforty2],r5,r8
@OC@.b [r2-forty2],r5,r8
@OC@.b [r2-mforty2],r5,r8
@OC@.b [r2+externalsym],r5,r8
@OC@.w [r2+0],r13,r8
@OC@.w [r2+1],r13,r8
@OC@.w [r2+127],r13,r8
@OC@.w [r2+128],r13,r8
@OC@.w [r2+-1],r13,r8
@OC@.w [r2-1],r13,r8
@OC@.w [r2+-127],r13,r8
@OC@.w [r2+-128],r13,r8
@OC@.w [r2+-129],r13,r8
@OC@.w [r2-127],r13,r8
@OC@.w [r2-128],r13,r8
@OC@.w [r2-129],r13,r8
@OC@.w [r2+255],r13,r8
@OC@.w [r2+-255],r13,r8
@OC@.w [r2-255],r13,r8
@OC@.w [r2+256],r13,r8
@OC@.w [r2-256],r13,r8
@OC@.w [r2+-8856],r13,r8
@OC@.w [r2-8856],r13,r8
@OC@.w [r2+8856],r13,r8
@OC@.w [r2+42],r13,r8
@OC@.w [r2+-42],r13,r8
@OC@.w [r2-42],r13,r8
@OC@.w [r2+forty2],r13,r8
@OC@.w [r2+mforty2],r13,r8
@OC@.w [r2+-forty2],r5,r8
@OC@.w [r2-forty2],r5,r8
@OC@.w [r2+-mforty2],r5,r8
@OC@.w [r2+three2767],r5,r8
@OC@.w [r2+three2767+1],r5,r8
@OC@.w [r2+three2767+2],r13,r8
@OC@.w [r2+-three2767],r13,r8
@OC@.w [r2+-(three2767+1)],r13,r8
@OC@.w [r2+-(three2767+2)],r5,r8
@OC@.w [r2-three2767],r13,r8
@OC@.w [r2-(three2767+1)],r13,r8
@OC@.w [r2-(three2767+2)],r5,r8
@OC@.w [r2+six5535],r5,r8
@OC@.w [r2+externalsym],r5,r8
@OC@.d [r2+0],r1,r8
@OC@.d [r2+1],r1,r8
@OC@.d [r2+127],r1,r8
@OC@.d [r2+128],r1,r8
@OC@.d [r2+-1],r1,r8
@OC@.d [r2-1],r1,r8
@OC@.d [r2+-127],r1,r8
@OC@.d [r2+-128],r1,r8
@OC@.d [r2-127],r1,r8
@OC@.d [r2-128],r1,r8
@OC@.d [r2+255],r1,r8
@OC@.d [r2+-255],r1,r8
@OC@.d [r2-255],r1,r8
@OC@.d [r2+256],r1,r8
@OC@.d [r2-256],r1,r8
@OC@.d [r2-8856],r1,r8
@OC@.d [r2+-256],r1,r8
@OC@.d [r2+-8856],r1,r8
@OC@.d [r2+8856],r1,r8
@OC@.d [r2+2781868],r1,r8
@OC@.d [r2+-2701867],r1,r8
@OC@.d [r2+0x9ec0ceac],r1,r8
@OC@.d [r2+-0x7ec0cead],r1,r8
@OC@.d [r2-0x7ec0cead],r1,r8
@OC@.d [r2+const_int_m32],r1,r8
@OC@.d [r2+const_int_32],r1,r8
@OC@.d [r2+42],r13,r8
@OC@.d [r2-42],r5,r8
@OC@.d [r2+-42],r5,r8
@OC@.d [r2+forty2],r5,r8
@OC@.d [r2+mforty2],r5,r8
@OC@.d [r2-forty2],r5,r8
@OC@.d [r2-mforty2],r5,r8
@OC@.d [r2+-forty2],r5,r8
@OC@.d [r2+-mforty2],r5,r8
@OC@.d [r2+three2767],r5,r8
@OC@.d [r2+three2767+1],r5,r8
@OC@.d [r2+three2767+2],r5,r8
@OC@.d [r2+-three2767],r5,r8
@OC@.d [r2+-(three2767+1)],r13,r8
@OC@.d [r2+-(three2767+2)],r13,r8
@OC@.d [r2-three2767],r5,r8
@OC@.d [r2-(three2767+1)],r13,r8
@OC@.d [r2-(three2767+2)],r13,r8
@OC@.d [r2+six5535],r5,r8
@OC@.d [r2+six5535+1],r13,r8
@OC@.d [r2+two701867],r5,r8
@OC@.d [r2+-two701867],r5,r8
@OC@.d [r2-two701867],r5,r8
@OC@.d [r2+externalsym],r5,r8
;;;;;;;;;;;;;;;;;
;
; [r=r+X],r
; [r=r+r.b],r
@OC@.b [r12=r2+r0.b],r5
@OC@.w [r12=r2+r5.b],r13
@OC@.d [r12=r2+r10.b],r1
@OC@ r13,[r12=r2+r5.b]
@OC@ r1,[r12=r2+r10.b]
; [r=r+[r].b],r
@OC@.b [r12=r2+[r0].b],r5
@OC@.w [r12=r2+[r5].b],r13
@OC@.d [r12=r2+[r10].b],r1
@OC@ r4,[r12=r2+[r5].b]
@OC@ r6,[r12=r2+[r10].b]
; [r=r+[r+].b],r
@OC@.b [r12=r2+[r0+].b],r5
@OC@.w [r12=r2+[r5+].b],r13
@OC@.d [r12=r2+[r10+].b],r1
@OC@.w [r12=r2+[r5+].b],r13
@OC@.d [r12=r2+[r10+].b],r1
@OC@ r3,[r12=r2+[r5+].b]
@OC@ r2,[r12=r2+[r10+].b]
; [r=r+r.w],r
@OC@.b [r12=r2+r0.w],r5
@OC@.w [r12=r2+r5.w],r13
@OC@.d [r12=r2+r10.w],r1
@OC@ r5,[r12=r2+r5.w]
@OC@ r8,[r12=r2+r10.w]
; [r=r+[r].w],r
@OC@.b [r12=r2+[r0].w],r5
@OC@.w [r12=r2+[r5].w],r13
@OC@.d [r12=r2+[r10].w],r1
@OC@ r4,[r12=r2+[r5].w]
@OC@ r3,[r12=r2+[r10].w]
; [r=r+[r+].w],r
@OC@.b [r12=r2+[r0+].w],r5
@OC@.w [r12=r2+[r5+].w],r13
@OC@.d [r12=r2+[r10+].w],r1
@OC@.w [r12=r2+[r5+].w],r13
@OC@.d [r12=r2+[r10+].w],r1
@OC@ r2,[r12=r2+[r5+].w]
@OC@ r7,[r12=r2+[r10+].w]
; [r=r+r.d],r
@OC@.b [r12=r2+r0.d],r5
@OC@.w [r12=r2+r5.d],r13
@OC@.d [r12=r2+r10.d],r1
@OC@ r4,[r12=r2+r5.d]
@OC@ r8,[r12=r2+r10.d]
; [r=r+[r].d],r
@OC@.b [r12=r2+[r0].d],r5
@OC@.w [r12=r2+[r5].d],r13
@OC@.d [r12=r2+[r10].d],r1
@OC@ r2,[r12=r2+[r5].d]
@OC@ r0,[r12=r2+[r10].d]
; [r=r+[r+].d],r
@OC@.b [r12=r2+[r0+].d],r5
@OC@.w [r12=r2+[r5+].d],r13
@OC@.d [r12=r2+[r10+].d],r1
@OC@.w [r12=r2+[r5+].d],r13
@OC@.d [r12=r2+[r10+].d],r1
@OC@ r3,[r12=r2+[r5+].d]
@OC@ r2,[r12=r2+[r10+].d]
; [r=r+const],r
@OC@.b [r12=r2+0],r5
@OC@.b [r12=r2+1],r5
@OC@.b [r12=r2+127],r5
@OC@.b [r12=r2+128],r5
@OC@.b [r12=r2+-1],r5
@OC@.b [r12=r2+-127],r5
@OC@.b [r12=r2+-128],r5
@OC@.b [r12=r2+255],r5
@OC@.b [r12=r2+42],r5
@OC@.b [r12=r2+-42],r5
@OC@.b [r12=r2-42],r5
@OC@.b [r12=r2+forty2],r5
@OC@.b [r12=r2+mforty2],r5
@OC@.b [r12=r2+-forty2],r5
@OC@.b [r12=r2+-mforty2],r5
@OC@.b [r12=r2-forty2],r5
@OC@.b [r12=r2-mforty2],r5
@OC@.b [r12=r2+externalsym],r5
@OC@.w [r12=r2+0],r13
@OC@.w [r12=r2+1],r13
@OC@.w [r12=r2+127],r13
@OC@.w [r12=r2+128],r13
@OC@.w [r12=r2+-1],r13
@OC@.w [r12=r2-1],r13
@OC@.w [r12=r2+-127],r13
@OC@.w [r12=r2+-128],r13
@OC@.w [r12=r2+-129],r13
@OC@.w [r12=r2-127],r13
@OC@.w [r12=r2-128],r13
@OC@.w [r12=r2-129],r13
@OC@.w [r12=r2+255],r13
@OC@.w [r12=r2+-255],r13
@OC@.w [r12=r2-255],r13
@OC@.w [r12=r2+256],r13
@OC@.w [r12=r2-256],r13
@OC@.w [r12=r2+-8856],r13
@OC@.w [r12=r2-8856],r13
@OC@.w [r12=r2+8856],r13
@OC@.w [r12=r2+42],r13
@OC@.w [r12=r2+-42],r13
@OC@.w [r12=r2-42],r13
@OC@.w [r12=r2+forty2],r13
@OC@.w [r12=r2+mforty2],r13
@OC@.w [r12=r2+-forty2],r5
@OC@.w [r12=r2-forty2],r5
@OC@.w [r12=r2+-mforty2],r5
@OC@.w [r12=r2+three2767],r5
@OC@.w [r12=r2+three2767+1],r5
@OC@.w [r12=r2+three2767+2],r13
@OC@.w [r12=r2+-three2767],r13
@OC@.w [r12=r2+-(three2767+1)],r13
@OC@.w [r12=r2+-(three2767+2)],r5
@OC@.w [r12=r2-three2767],r13
@OC@.w [r12=r2-(three2767+1)],r13
@OC@.w [r12=r2-(three2767+2)],r5
@OC@.w [r12=r2+six5535],r5
@OC@.w [r12=r2+externalsym],r5
@OC@.d [r12=r2+0],r1
@OC@.d [r12=r2+1],r1
@OC@.d [r12=r2+127],r1
@OC@.d [r12=r2+128],r1
@OC@.d [r12=r2+-1],r1
@OC@.d [r12=r2-1],r1
@OC@.d [r12=r2+-127],r1
@OC@.d [r12=r2+-128],r1
@OC@.d [r12=r2-127],r1
@OC@.d [r12=r2-128],r1
@OC@.d [r12=r2+255],r1
@OC@.d [r12=r2+-255],r1
@OC@.d [r12=r2-255],r1
@OC@.d [r12=r2+256],r1
@OC@.d [r12=r2-256],r1
@OC@.d [r12=r2-8856],r1
@OC@.d [r12=r2+-256],r1
@OC@.d [r12=r2+-8856],r1
@OC@.d [r12=r2+8856],r1
@OC@.d [r12=r2+2781868],r1
@OC@.d [r12=r2+-2701867],r1
@OC@.d [r12=r2+0x9ec0ceac],r1
@OC@.d [r12=r2+-0x7ec0cead],r1
@OC@.d [r12=r2-0x7ec0cead],r1
@OC@.d [r12=r2+const_int_m32],r1
@OC@.d [r12=r2+const_int_32],r1
@OC@.d [r12=r2+42],r13
@OC@.d [r12=r2-42],r5
@OC@.d [r12=r2+-42],r5
@OC@.d [r12=r2+forty2],r5
@OC@.d [r12=r2+mforty2],r5
@OC@.d [r12=r2-forty2],r5
@OC@.d [r12=r2-mforty2],r5
@OC@.d [r12=r2+-forty2],r5
@OC@.d [r12=r2+-mforty2],r5
@OC@.d [r12=r2+three2767],r5
@OC@.d [r12=r2+three2767+1],r5
@OC@.d [r12=r2+three2767+2],r5
@OC@.d [r12=r2+-three2767],r5
@OC@.d [r12=r2+-(three2767+1)],r13
@OC@.d [r12=r2+-(three2767+2)],r13
@OC@.d [r12=r2-three2767],r5
@OC@.d [r12=r2-(three2767+1)],r13
@OC@.d [r12=r2-(three2767+2)],r13
@OC@.d [r12=r2+six5535],r5
@OC@.d [r12=r2+six5535+1],r13
@OC@.d [r12=r2+two701867],r5
@OC@.d [r12=r2+-two701867],r5
@OC@.d [r12=r2-two701867],r5
@OC@.d [r12=r2+externalsym],r5
@OC@ r1,[r12=r2+0]
@OC@ r1,[r12=r2+1]
@OC@ r1,[r12=r2+127]
@OC@ r1,[r12=r2+128]
@OC@ r1,[r12=r2+-1]
@OC@ r1,[r12=r2-1]
@OC@ r1,[r12=r2+-127]
@OC@ r1,[r12=r2+-128]
@OC@ r1,[r12=r2-127]
@OC@ r1,[r12=r2-128]
@OC@ r1,[r12=r2+255]
@OC@ r1,[r12=r2+-255]
@OC@ r1,[r12=r2-255]
@OC@ r1,[r12=r2+256]
@OC@ r1,[r12=r2-256]
@OC@ r1,[r12=r2-8856]
@OC@ r1,[r12=r2+-256]
@OC@ r1,[r12=r2+-8856]
@OC@ r1,[r12=r2+8856]
@OC@ r1,[r12=r2+2781868]
@OC@ r1,[r12=r2+-2701867]
@OC@ r1,[r12=r2+0x9ec0ceac]
@OC@ r1,[r12=r2+-0x7ec0cead]
@OC@ r1,[r12=r2-0x7ec0cead]
@OC@ r1,[r12=r2+const_int_m32]
@OC@ r1,[r12=r2+const_int_32]
@OC@ r13,[r12=r2+42]
@OC@ r5,[r12=r2-42]
@OC@ r5,[r12=r2+-42]
@OC@ r5,[r12=r2+forty2]
@OC@ r5,[r12=r2+mforty2]
@OC@ r5,[r12=r2-forty2]
@OC@ r5,[r12=r2-mforty2]
@OC@ r5,[r12=r2+-forty2]
@OC@ r5,[r12=r2+-mforty2]
@OC@ r5,[r12=r2+three2767]
@OC@ r5,[r12=r2+three2767+1]
@OC@ r5,[r12=r2+three2767+2]
@OC@ r5,[r12=r2+-three2767]
@OC@ r13,[r12=r2+-(three2767+1)]
@OC@ r13,[r12=r2+-(three2767+2)]
@OC@ r5,[r12=r2-three2767]
@OC@ r13,[r12=r2-(three2767+1)]
@OC@ r13,[r12=r2-(three2767+2)]
@OC@ r5,[r12=r2+six5535]
@OC@ r13,[r12=r2+six5535+1]
@OC@ r5,[r12=r2+two701867]
@OC@ r5,[r12=r2+-two701867]
@OC@ r5,[r12=r2-two701867]
@OC@ r5,[r12=r2+externalsym]
;;;;;;;;;;;;;;;;;;;
;
; [[r(+)]],r
@OC@.b [[r3]],r5
@OC@.w [[r2]],r4
@OC@.d [[r3]],r7
@OC@ r4,[[r2]]
@OC@ r7,[[r3]]
@OC@.b [[r9+]],r7
@OC@.w [[r3+]],r5
@OC@.d [[r1+]],r6
@OC@ r5,[[r3+]]
@OC@ r6,[[r1+]]
@OC@.b [externalsym],r5
@OC@.w [externalsym],r4
@OC@.d [externalsym],r7
@OC@ r4,[externalsym]
@OC@ r7,[externalsym]
@OC@.b [notstart],r5
@OC@.w [notstart],r4
@OC@.d [notstart],r7
@OC@ r3,[notstart]
@OC@ r7,[notstart]
;;;;;;;;;;;;;;;;;;;
;
; [[r(+)]],r,r
@OC@.b [[r3]],r5,r12
@OC@.w [[r2]],r4,r9
@OC@.d [[r3]],r7,r9
@OC@.b [[r9+]],r7,r10
@OC@.w [[r3+]],r5,r9
@OC@.d [[r1+]],r6,r9
@OC@.b [externalsym],r5,r7
@OC@.w [externalsym],r4,r9
@OC@.d [externalsym],r7,r9
@OC@.b [notstart],r5,r9
@OC@.w [notstart],r4,r12
@OC@.d [notstart],r7,r9
end:
|
tactcomplabs/xbgas-binutils-gdb
| 2,570
|
gas/testsuite/gas/cris/operand-err-1.s
|
; Error cases for invalid operands.
; { dg-do assemble { target cris-*-* } }
.text
.syntax no_register_prefix
start:
add.w r3,r4,r5 ; { dg-error "(Illegal|Invalid) operands" }
add.w 42,r4,r5 ; { dg-error "(Illegal|Invalid) operands" }
add.w [r3],r4,r5 ; Not an error: [r3] implies [r3+0].
add.w r3,[r3],r4 ; { dg-error "(Illegal|Invalid) operands" }
add.w r3,[r3] ; { dg-error "(Illegal|Invalid) operands" }
test.w [r3],r4,r5 ; { dg-error "(Illegal|Invalid) operands" }
test.d [r3],r4 ; { dg-error "(Illegal|Invalid) operands" }
move.d [r3],r4,r5 ; { dg-error "(Illegal|Invalid) operands" }
; These two could be seen useful in extreme cases, but those
; would be shadowed by not flagging erroneous use of
; e.g. "test.d $r3" for CRISv32. If you really need it, use
; e.g. "test.d [$pc+] @ .dword whatever".
test.d whatever ; { dg-error "(Illegal|Invalid) operands" "" }
test.d 42 ; { dg-error "(Illegal|Invalid) operands" "" }
clear.d whatever ; { dg-error "(Illegal|Invalid) operands" }
clear.d 42 ; { dg-error "(Illegal|Invalid) operands" }
addi r5,r3 ; { dg-error "(Illegal|Invalid) operands" }
; These two are valid instructions, though not recognized by
; the assembler since they're obscure and generally useless.
ba [external_symbol] ; { dg-error "(Illegal|Invalid) operands|(B|b)ad expression" }
ba [r3] ; { dg-error "(Illegal|Invalid) operands|(B|b)ad expression" }
lsl r3,r5 ; { dg-error "(Illegal|Invalid) operands" }
xor.d r5,r6 ; { dg-error "(Illegal|Invalid) operands" }
; Addressing modes
test.d [r3+r4] ; { dg-error "(Illegal|Invalid) operands" }
test.d [r3=r2+[r4]] ; { dg-error "(Illegal|Invalid) operands" }
test.d [r3=r2+[r4].w ; { dg-error "(Illegal|Invalid) operands" }
test.d [r3=r2] ; { dg-error "(Illegal|Invalid) operands" }
test.d [r3=r2+] ; { dg-error "(Illegal|Invalid) operands|(B|b)ad expression" }
test.d [r3++] ; { dg-error "(Illegal|Invalid) operands|(B|b)ad expression" }
; I think these should be valid; a dip with "postincrement" on
; the insn that follows.
test.d [r3=external_symbol] ; { dg-error "(Illegal|Invalid) operands" }
test.d [r3=[r4]] ; { dg-error "(Illegal|Invalid) operands" }
test.d [r3=[r4+]] ; { dg-error "(Illegal|Invalid) operands" }
test.d [[r3+r4.b]] ; { dg-error "(Illegal|Invalid) operands" }
test.d [r3=external+[r5]] ; { dg-error "(Illegal|Invalid) operands" }
test.d [r3=[r5]+external] ; { dg-error "(Illegal|Invalid) operands" }
test.d [r3+[r3+r5.d]] ; { dg-error "(Illegal|Invalid) operands" }
test.d [r3+[r3+external]] ; { dg-error "(Illegal|Invalid) operands" }
|
tactcomplabs/xbgas-binutils-gdb
| 1,217
|
gas/testsuite/gas/cris/fragtest.s
|
; File fragtest.s
;
; Tests frag handling
ba l1 ; 2, 254 = 0xFE
nop
.space 124,0
ba l2 ; 2, 226 = 0xE2
nop
.space 124,0
l1:
.space 100,0
l2:
ba l3 ; 4, 256 = 0x0100
nop
.space 124,0
ba l4 ; 4, 1126 = 0x0466
nop
.space 124,0
l3:
.space 1000,0
l4:
ba l5 ; 4, 264 = 0x0108
nop
.space 124,0
ba l6 ; 12, 33126 = 0x00008844
nop
.space 124,0
l5:
.space 33000,0
l6:
; A circular case
l7:
.space 124,0
ba l8 ; 2, 254 = 0xFE
nop
.space 126,0
ba l7 ; 2, -256 = 0x01
nop
.space 122,0
l8:
l9:
.space 124,0
ba l10 ; 4, 258 = 0x0102
nop
.space 126,0
ba l9 ; 4, -260 = 0xFEFC
nop
.space 124,0
l10:
l11:
.space 126,0
ba l12 ; 4, 256 = 0x0100
nop
.space 126,0
ba l11 ; 4, -262 = 0xFEFA
nop
.space 122,0
l12:
|
tactcomplabs/xbgas-binutils-gdb
| 5,260
|
gas/testsuite/gas/cris/v32-err-1.s
|
; { dg-do assemble }
; { dg-options "--march=v0_v10" }
; Check that valid v32-specific mnemonics and operands are not
; recognized for v10. (Also used elsewhere to check that valid
; v32-specific insns and operands are recognized at assembly and
; disassembly for v32.)
.text
here:
move.d [$acr],$r3 ; No error - $acr treated as a symbol.
move.d [$r5+],$acr ; { dg-error "(Illegal|Invalid) operands" }
move.d $acr,$r7 ; No error - $acr treated as a symbol.
move.d $r8,$acr ; { dg-error "(Illegal|Invalid) operands" }
move $acr,$srp ; No error - $acr treated as a symbol.
addc $r0,$r0 ; { dg-error "Unknown opcode" }
addc $acr,$acr ; { dg-error "Unknown opcode" }
addc $r6,$r1 ; { dg-error "Unknown opcode" }
addc [$r3],$r1 ; { dg-error "Unknown opcode" }
addc [$r0],$r0 ; { dg-error "Unknown opcode" }
addc [$acr],$acr ; { dg-error "Unknown opcode" }
addc [$acr],$r1 ; { dg-error "Unknown opcode" }
addc [$r3+],$r1 ; { dg-error "Unknown opcode" }
addi $r8.w,$r2,$acr ; { dg-error "(Illegal|Invalid) operands" }
addi $r0.b,$r0,$acr ; { dg-error "(Illegal|Invalid) operands" }
addi $acr.d,$acr,$acr ; { dg-error "(Illegal|Invalid) operands" }
addo.d [$r3],$r7,$acr ; { dg-error "Unknown opcode" }
addo.d [$r13+],$r7,$acr ; { dg-error "Unknown opcode" }
addo.d [$r3],$acr,$acr ; { dg-error "Unknown opcode" }
addo.b [$r0],$r0,$acr ; { dg-error "Unknown opcode" }
addo.d [$acr],$acr,$acr ; { dg-error "Unknown opcode" }
addo.b -1,$acr,$acr ; { dg-error "Unknown opcode" }
addo.w -1,$acr,$acr ; { dg-error "Unknown opcode" }
addo.d -1,$acr,$acr ; { dg-error "Unknown opcode" }
addo.b extsym1,$r3,$acr ; { dg-error "Unknown opcode" }
addo.w extsym2,$r3,$acr ; { dg-error "Unknown opcode" }
addo.d extsym3,$r3,$acr ; { dg-error "Unknown opcode" }
addo.b 127,$acr,$acr ; { dg-error "Unknown opcode" }
addo.w 32767,$acr,$acr ; { dg-error "Unknown opcode" }
addo.d 0xffffff,$acr,$acr ; { dg-error "Unknown opcode" }
addo.b -128,$acr,$acr ; { dg-error "Unknown opcode" }
addo.w -32768,$acr,$acr ; { dg-error "Unknown opcode" }
addo.d 0xffffffff,$acr,$acr ; { dg-error "Unknown opcode" }
lapc .,$r0 ; { dg-error "Unknown opcode" }
lapc .+30,$r4 ; { dg-error "Unknown opcode" }
lapc .+30,$acr ; { dg-error "Unknown opcode" }
lapc extsym4,$acr ; { dg-error "Unknown opcode" }
lapc extsym5,$r4 ; { dg-error "Unknown opcode" }
lapc here,$r4 ; { dg-error "Unknown opcode" }
addoq -1,$acr,$acr ; { dg-error "Unknown opcode" }
addoq 0,$r0,$acr ; { dg-error "Unknown opcode" }
addoq 127,$r4,$acr ; { dg-error "Unknown opcode" }
addoq extsym6,$r4,$acr ; { dg-error "Unknown opcode" }
bas 0xffffffff,$srp ; { dg-error "Unknown opcode" }
bas extsym7,$bz ; { dg-error "Unknown opcode" }
bas here,$erp ; { dg-error "Unknown opcode" }
basc 0xffffffff,$srp ; { dg-error "Unknown opcode" }
.dword 0
basc extsym8,$bz ; { dg-error "Unknown opcode" }
.dword 0
basc here,$erp ; { dg-error "Unknown opcode" }
.dword 0
bsb . ; { dg-error "Unknown opcode" }
nop
bsb here ; { dg-error "Unknown opcode" }
nop
bsr extsym9 ; { dg-error "Unknown opcode" }
bsr here ; { dg-error "Unknown opcode" }
bsrc 0xffffffff ; { dg-error "Unknown opcode" }
.dword 0
bsrc extsym10 ; { dg-error "Unknown opcode" }
.dword 0
bsrc here ; { dg-error "Unknown opcode" }
.dword 0
fidxd [$r0] ; { dg-error "Unknown opcode" }
fidxd [$acr] ; { dg-error "Unknown opcode" }
fidxi [$r0] ; { dg-error "Unknown opcode" }
fidxi [$acr] ; { dg-error "Unknown opcode" }
ftagd [$r0] ; { dg-error "Unknown opcode" }
ftagd [$acr] ; { dg-error "Unknown opcode" }
ftagi [$r0] ; { dg-error "Unknown opcode" }
ftagi [$acr] ; { dg-error "Unknown opcode" }
jas $r0,$bz ; { dg-error "Unknown opcode" }
jas $acr,$usp ; { dg-error "Unknown opcode" }
jas extsym9,$bz ; { dg-error "Unknown opcode" }
jas here,$srp ; { dg-error "Unknown opcode" }
jasc $r0,$bz ; { dg-error "Unknown opcode" }
.dword 0
jasc $acr,$usp ; { dg-error "Unknown opcode" }
.dword 0
jasc 0xffffffff,$srp ; { dg-error "Unknown opcode" }
.dword 0
jasc extsym11,$bz ; { dg-error "Unknown opcode" }
.dword 0
jasc here,$erp ; { dg-error "Unknown opcode" }
.dword 0
jump $srp ; No error - $srp treated as a symbol.
jump $bz ; No error - $bz treated as a symbol.
mcp $p0,$r0 ; { dg-error "Unknown opcode" }
mcp $mof,$acr ; { dg-error "Unknown opcode" }
mcp $srp,$r2 ; { dg-error "Unknown opcode" }
move $s0,$r0 ; { dg-error "(Illegal|Invalid) operands" }
move $s15,$acr ; { dg-error "(Illegal|Invalid) operands" }
move $s5,$r3 ; { dg-error "(Illegal|Invalid) operands" }
move $r0,$s0 ; { dg-error "(Illegal|Invalid) operands" }
move $acr,$s15 ; { dg-error "(Illegal|Invalid) operands" }
move $r4,$s10 ; { dg-error "(Illegal|Invalid) operands" }
rfe ; { dg-error "Unknown opcode" }
rfg ; { dg-error "Unknown opcode" }
rete ; { dg-error "Unknown opcode" }
retn ; { dg-error "Unknown opcode" }
ssb $r0 ; { dg-error "Unknown opcode" }
ssb $acr ; { dg-error "Unknown opcode" }
ssb $r10 ; { dg-error "Unknown opcode" }
sfe ; { dg-error "Unknown opcode" }
halt ; { dg-error "Unknown opcode" }
rfn ; { dg-error "Unknown opcode" }
|
tactcomplabs/xbgas-binutils-gdb
| 1,381
|
gas/testsuite/gas/ia64/reloc-bad.s
|
.psr abi64
.global esym
.section .rodata, "a", @progbits
.text
_start:
adds r1 = @gprel(esym), r0
adds r1 = @ltoff(esym), r0
.xdata4 .rodata, @ltoff(esym)
.xdata8 .rodata, @ltoff(esym)
adds r1 = @pltoff(esym), r0
.xdata4 .rodata, @pltoff(esym)
adds r1 = @fptr(esym), r0
mov r2 = @fptr(esym)
adds r1 = @pcrel(esym), r0
adds r1 = @ltoff(@fptr(esym)), r0
adds r1 = @segrel(esym), r0
mov r2 = @segrel(esym)
movl r3 = @segrel(esym)
adds r1 = @secrel(esym), r0
mov r2 = @secrel(esym)
movl r3 = @secrel(esym)
adds r1 = @ltv(esym), r0
mov r2 = @ltv(esym)
movl r3 = @ltv(esym)
adds r1 = @iplt(esym), r0
mov r2 = @iplt(esym)
movl r3 = @iplt(esym)
.xdata4 .rodata, @iplt(esym)
.xdata8 .rodata, @iplt(esym)
adds r1 = @ltoffx(esym), r0
.xdata4 .rodata, @tprel(esym)
adds r1 = @ltoff(@tprel(esym)), r0
movl r3 = @ltoff(@tprel(esym))
.xdata4 .rodata, @ltoff(@tprel(esym))
.xdata8 .rodata, @ltoff(@tprel(esym))
adds r1 = @dtpmod(esym), r0
mov r2 = @dtpmod(esym)
movl r3 = @dtpmod(esym)
.xdata4 .rodata, @dtpmod(esym)
adds r1 = @ltoff(@dtpmod(esym)), r0
movl r3 = @ltoff(@dtpmod(esym))
.xdata4 .rodata, @ltoff(@tprel(esym))
.xdata8 .rodata, @ltoff(@tprel(esym))
adds r1 = @ltoff(@dtprel(esym)), r0
movl r3 = @ltoff(@dtprel(esym))
.xdata4 .rodata, @ltoff(@dtprel(esym))
.xdata8 .rodata, @ltoff(@dtprel(esym))
|
tactcomplabs/xbgas-binutils-gdb
| 22,687
|
gas/testsuite/gas/ia64/opc-m.s
|
.text
.type _start,@function
_start:
ld1 r4 = [r5]
ld1 r4 = [r5], r6
ld1 r4 = [r5], -256
ld1.nt1 r4 = [r5]
ld1.nt1 r4 = [r5], r6
ld1.nt1 r4 = [r5], -243
ld1.nta r4 = [r5]
ld1.nta r4 = [r5], r6
ld1.nta r4 = [r5], -230
ld1.s r4 = [r5]
ld1.s r4 = [r5], r6
ld1.s r4 = [r5], -217
ld1.s.nt1 r4 = [r5]
ld1.s.nt1 r4 = [r5], r6
ld1.s.nt1 r4 = [r5], -204
ld1.s.nta r4 = [r5]
ld1.s.nta r4 = [r5], r6
ld1.s.nta r4 = [r5], -191
ld1.a r4 = [r5]
ld1.a r4 = [r5], r6
ld1.a r4 = [r5], -178
ld1.a.nt1 r4 = [r5]
ld1.a.nt1 r4 = [r5], r6
ld1.a.nt1 r4 = [r5], -165
ld1.a.nta r4 = [r5]
ld1.a.nta r4 = [r5], r6
ld1.a.nta r4 = [r5], -152
ld1.sa r4 = [r5]
ld1.sa r4 = [r5], r6
ld1.sa r4 = [r5], -139
ld1.sa.nt1 r4 = [r5]
ld1.sa.nt1 r4 = [r5], r6
ld1.sa.nt1 r4 = [r5], -126
ld1.sa.nta r4 = [r5]
ld1.sa.nta r4 = [r5], r6
ld1.sa.nta r4 = [r5], -113
ld1.c.clr r4 = [r5]
ld1.c.clr r4 = [r5], r6
ld1.c.clr r4 = [r5], -100
ld1.c.clr.nt1 r4 = [r5]
ld1.c.clr.nt1 r4 = [r5], r6
ld1.c.clr.nt1 r4 = [r5], -87
ld1.c.clr.nta r4 = [r5]
ld1.c.clr.nta r4 = [r5], r6
ld1.c.clr.nta r4 = [r5], -74
ld1.c.nc r4 = [r5]
ld1.c.nc r4 = [r5], r6
ld1.c.nc r4 = [r5], -61
ld1.c.nc.nt1 r4 = [r5]
ld1.c.nc.nt1 r4 = [r5], r6
ld1.c.nc.nt1 r4 = [r5], -48
ld1.c.nc.nta r4 = [r5]
ld1.c.nc.nta r4 = [r5], r6
ld1.c.nc.nta r4 = [r5], -35
ld1.bias r4 = [r5]
ld1.bias r4 = [r5], r6
ld1.bias r4 = [r5], -22
ld1.bias.nt1 r4 = [r5]
ld1.bias.nt1 r4 = [r5], r6
ld1.bias.nt1 r4 = [r5], -9
ld1.bias.nta r4 = [r5]
ld1.bias.nta r4 = [r5], r6
ld1.bias.nta r4 = [r5], 4
ld1.acq r4 = [r5]
ld1.acq r4 = [r5], r6
ld1.acq r4 = [r5], 17
ld1.acq.nt1 r4 = [r5]
ld1.acq.nt1 r4 = [r5], r6
ld1.acq.nt1 r4 = [r5], 30
ld1.acq.nta r4 = [r5]
ld1.acq.nta r4 = [r5], r6
ld1.acq.nta r4 = [r5], 43
ld1.c.clr.acq r4 = [r5]
ld1.c.clr.acq r4 = [r5], r6
ld1.c.clr.acq r4 = [r5], 56
ld1.c.clr.acq.nt1 r4 = [r5]
ld1.c.clr.acq.nt1 r4 = [r5], r6
ld1.c.clr.acq.nt1 r4 = [r5], 69
ld1.c.clr.acq.nta r4 = [r5]
ld1.c.clr.acq.nta r4 = [r5], r6
ld1.c.clr.acq.nta r4 = [r5], 82
ld2 r4 = [r5]
ld2 r4 = [r5], r6
ld2 r4 = [r5], 95
ld2.nt1 r4 = [r5]
ld2.nt1 r4 = [r5], r6
ld2.nt1 r4 = [r5], 108
ld2.nta r4 = [r5]
ld2.nta r4 = [r5], r6
ld2.nta r4 = [r5], 121
ld2.s r4 = [r5]
ld2.s r4 = [r5], r6
ld2.s r4 = [r5], 134
ld2.s.nt1 r4 = [r5]
ld2.s.nt1 r4 = [r5], r6
ld2.s.nt1 r4 = [r5], 147
ld2.s.nta r4 = [r5]
ld2.s.nta r4 = [r5], r6
ld2.s.nta r4 = [r5], 160
ld2.a r4 = [r5]
ld2.a r4 = [r5], r6
ld2.a r4 = [r5], 173
ld2.a.nt1 r4 = [r5]
ld2.a.nt1 r4 = [r5], r6
ld2.a.nt1 r4 = [r5], 186
ld2.a.nta r4 = [r5]
ld2.a.nta r4 = [r5], r6
ld2.a.nta r4 = [r5], 199
ld2.sa r4 = [r5]
ld2.sa r4 = [r5], r6
ld2.sa r4 = [r5], 212
ld2.sa.nt1 r4 = [r5]
ld2.sa.nt1 r4 = [r5], r6
ld2.sa.nt1 r4 = [r5], 225
ld2.sa.nta r4 = [r5]
ld2.sa.nta r4 = [r5], r6
ld2.sa.nta r4 = [r5], 238
ld2.c.clr r4 = [r5]
ld2.c.clr r4 = [r5], r6
ld2.c.clr r4 = [r5], 251
ld2.c.clr.nt1 r4 = [r5]
ld2.c.clr.nt1 r4 = [r5], r6
ld2.c.clr.nt1 r4 = [r5], -248
ld2.c.clr.nta r4 = [r5]
ld2.c.clr.nta r4 = [r5], r6
ld2.c.clr.nta r4 = [r5], -235
ld2.c.nc r4 = [r5]
ld2.c.nc r4 = [r5], r6
ld2.c.nc r4 = [r5], -222
ld2.c.nc.nt1 r4 = [r5]
ld2.c.nc.nt1 r4 = [r5], r6
ld2.c.nc.nt1 r4 = [r5], -209
ld2.c.nc.nta r4 = [r5]
ld2.c.nc.nta r4 = [r5], r6
ld2.c.nc.nta r4 = [r5], -196
ld2.bias r4 = [r5]
ld2.bias r4 = [r5], r6
ld2.bias r4 = [r5], -183
ld2.bias.nt1 r4 = [r5]
ld2.bias.nt1 r4 = [r5], r6
ld2.bias.nt1 r4 = [r5], -170
ld2.bias.nta r4 = [r5]
ld2.bias.nta r4 = [r5], r6
ld2.bias.nta r4 = [r5], -157
ld2.acq r4 = [r5]
ld2.acq r4 = [r5], r6
ld2.acq r4 = [r5], -144
ld2.acq.nt1 r4 = [r5]
ld2.acq.nt1 r4 = [r5], r6
ld2.acq.nt1 r4 = [r5], -131
ld2.acq.nta r4 = [r5]
ld2.acq.nta r4 = [r5], r6
ld2.acq.nta r4 = [r5], -118
ld2.c.clr.acq r4 = [r5]
ld2.c.clr.acq r4 = [r5], r6
ld2.c.clr.acq r4 = [r5], -105
ld2.c.clr.acq.nt1 r4 = [r5]
ld2.c.clr.acq.nt1 r4 = [r5], r6
ld2.c.clr.acq.nt1 r4 = [r5], -92
ld2.c.clr.acq.nta r4 = [r5]
ld2.c.clr.acq.nta r4 = [r5], r6
ld2.c.clr.acq.nta r4 = [r5], -79
ld4 r4 = [r5]
ld4 r4 = [r5], r6
ld4 r4 = [r5], -66
ld4.nt1 r4 = [r5]
ld4.nt1 r4 = [r5], r6
ld4.nt1 r4 = [r5], -53
ld4.nta r4 = [r5]
ld4.nta r4 = [r5], r6
ld4.nta r4 = [r5], -40
ld4.s r4 = [r5]
ld4.s r4 = [r5], r6
ld4.s r4 = [r5], -27
ld4.s.nt1 r4 = [r5]
ld4.s.nt1 r4 = [r5], r6
ld4.s.nt1 r4 = [r5], -14
ld4.s.nta r4 = [r5]
ld4.s.nta r4 = [r5], r6
ld4.s.nta r4 = [r5], -1
ld4.a r4 = [r5]
ld4.a r4 = [r5], r6
ld4.a r4 = [r5], 12
ld4.a.nt1 r4 = [r5]
ld4.a.nt1 r4 = [r5], r6
ld4.a.nt1 r4 = [r5], 25
ld4.a.nta r4 = [r5]
ld4.a.nta r4 = [r5], r6
ld4.a.nta r4 = [r5], 38
ld4.sa r4 = [r5]
ld4.sa r4 = [r5], r6
ld4.sa r4 = [r5], 51
ld4.sa.nt1 r4 = [r5]
ld4.sa.nt1 r4 = [r5], r6
ld4.sa.nt1 r4 = [r5], 64
ld4.sa.nta r4 = [r5]
ld4.sa.nta r4 = [r5], r6
ld4.sa.nta r4 = [r5], 77
ld4.c.clr r4 = [r5]
ld4.c.clr r4 = [r5], r6
ld4.c.clr r4 = [r5], 90
ld4.c.clr.nt1 r4 = [r5]
ld4.c.clr.nt1 r4 = [r5], r6
ld4.c.clr.nt1 r4 = [r5], 103
ld4.c.clr.nta r4 = [r5]
ld4.c.clr.nta r4 = [r5], r6
ld4.c.clr.nta r4 = [r5], 116
ld4.c.nc r4 = [r5]
ld4.c.nc r4 = [r5], r6
ld4.c.nc r4 = [r5], 129
ld4.c.nc.nt1 r4 = [r5]
ld4.c.nc.nt1 r4 = [r5], r6
ld4.c.nc.nt1 r4 = [r5], 142
ld4.c.nc.nta r4 = [r5]
ld4.c.nc.nta r4 = [r5], r6
ld4.c.nc.nta r4 = [r5], 155
ld4.bias r4 = [r5]
ld4.bias r4 = [r5], r6
ld4.bias r4 = [r5], 168
ld4.bias.nt1 r4 = [r5]
ld4.bias.nt1 r4 = [r5], r6
ld4.bias.nt1 r4 = [r5], 181
ld4.bias.nta r4 = [r5]
ld4.bias.nta r4 = [r5], r6
ld4.bias.nta r4 = [r5], 194
ld4.acq r4 = [r5]
ld4.acq r4 = [r5], r6
ld4.acq r4 = [r5], 207
ld4.acq.nt1 r4 = [r5]
ld4.acq.nt1 r4 = [r5], r6
ld4.acq.nt1 r4 = [r5], 220
ld4.acq.nta r4 = [r5]
ld4.acq.nta r4 = [r5], r6
ld4.acq.nta r4 = [r5], 233
ld4.c.clr.acq r4 = [r5]
ld4.c.clr.acq r4 = [r5], r6
ld4.c.clr.acq r4 = [r5], 246
ld4.c.clr.acq.nt1 r4 = [r5]
ld4.c.clr.acq.nt1 r4 = [r5], r6
ld4.c.clr.acq.nt1 r4 = [r5], -253
ld4.c.clr.acq.nta r4 = [r5]
ld4.c.clr.acq.nta r4 = [r5], r6
ld4.c.clr.acq.nta r4 = [r5], -240
ld8 r4 = [r5]
ld8 r4 = [r5], r6
ld8 r4 = [r5], -227
ld8.nt1 r4 = [r5]
ld8.nt1 r4 = [r5], r6
ld8.nt1 r4 = [r5], -214
ld8.nta r4 = [r5]
ld8.nta r4 = [r5], r6
ld8.nta r4 = [r5], -201
ld8.s r4 = [r5]
ld8.s r4 = [r5], r6
ld8.s r4 = [r5], -188
ld8.s.nt1 r4 = [r5]
ld8.s.nt1 r4 = [r5], r6
ld8.s.nt1 r4 = [r5], -175
ld8.s.nta r4 = [r5]
ld8.s.nta r4 = [r5], r6
ld8.s.nta r4 = [r5], -162
ld8.a r4 = [r5]
ld8.a r4 = [r5], r6
ld8.a r4 = [r5], -149
ld8.a.nt1 r4 = [r5]
ld8.a.nt1 r4 = [r5], r6
ld8.a.nt1 r4 = [r5], -136
ld8.a.nta r4 = [r5]
ld8.a.nta r4 = [r5], r6
ld8.a.nta r4 = [r5], -123
ld8.sa r4 = [r5]
ld8.sa r4 = [r5], r6
ld8.sa r4 = [r5], -110
ld8.sa.nt1 r4 = [r5]
ld8.sa.nt1 r4 = [r5], r6
ld8.sa.nt1 r4 = [r5], -97
ld8.sa.nta r4 = [r5]
ld8.sa.nta r4 = [r5], r6
ld8.sa.nta r4 = [r5], -84
ld8.c.clr r4 = [r5]
ld8.c.clr r4 = [r5], r6
ld8.c.clr r4 = [r5], -71
ld8.c.clr.nt1 r4 = [r5]
ld8.c.clr.nt1 r4 = [r5], r6
ld8.c.clr.nt1 r4 = [r5], -58
ld8.c.clr.nta r4 = [r5]
ld8.c.clr.nta r4 = [r5], r6
ld8.c.clr.nta r4 = [r5], -45
ld8.c.nc r4 = [r5]
ld8.c.nc r4 = [r5], r6
ld8.c.nc r4 = [r5], -32
ld8.c.nc.nt1 r4 = [r5]
ld8.c.nc.nt1 r4 = [r5], r6
ld8.c.nc.nt1 r4 = [r5], -19
ld8.c.nc.nta r4 = [r5]
ld8.c.nc.nta r4 = [r5], r6
ld8.c.nc.nta r4 = [r5], -6
ld8.bias r4 = [r5]
ld8.bias r4 = [r5], r6
ld8.bias r4 = [r5], 7
ld8.bias.nt1 r4 = [r5]
ld8.bias.nt1 r4 = [r5], r6
ld8.bias.nt1 r4 = [r5], 20
ld8.bias.nta r4 = [r5]
ld8.bias.nta r4 = [r5], r6
ld8.bias.nta r4 = [r5], 33
ld8.acq r4 = [r5]
ld8.acq r4 = [r5], r6
ld8.acq r4 = [r5], 46
ld8.acq.nt1 r4 = [r5]
ld8.acq.nt1 r4 = [r5], r6
ld8.acq.nt1 r4 = [r5], 59
ld8.acq.nta r4 = [r5]
ld8.acq.nta r4 = [r5], r6
ld8.acq.nta r4 = [r5], 72
ld8.c.clr.acq r4 = [r5]
ld8.c.clr.acq r4 = [r5], r6
ld8.c.clr.acq r4 = [r5], 85
ld8.c.clr.acq.nt1 r4 = [r5]
ld8.c.clr.acq.nt1 r4 = [r5], r6
ld8.c.clr.acq.nt1 r4 = [r5], 98
ld8.c.clr.acq.nta r4 = [r5]
ld8.c.clr.acq.nta r4 = [r5], r6
ld8.c.clr.acq.nta r4 = [r5], 111
ld8.fill r4 = [r5]
ld8.fill r4 = [r5], r6
ld8.fill r4 = [r5], 124
ld8.fill.nt1 r4 = [r5]
ld8.fill.nt1 r4 = [r5], r6
ld8.fill.nt1 r4 = [r5], 137
ld8.fill.nta r4 = [r5]
ld8.fill.nta r4 = [r5], r6
ld8.fill.nta r4 = [r5], 150
st1 [r4] = r5
st1 [r4] = r5, 163
st1.nta [r4] = r5
st1.nta [r4] = r5, 176
st2 [r4] = r5
st2 [r4] = r5, 189
st2.nta [r4] = r5
st2.nta [r4] = r5, 202
st4 [r4] = r5
st4 [r4] = r5, 215
st4.nta [r4] = r5
st4.nta [r4] = r5, 228
st8 [r4] = r5
st8 [r4] = r5, 241
st8.nta [r4] = r5
st8.nta [r4] = r5, 254
st1.rel [r4] = r5
st1.rel [r4] = r5, -245
st1.rel.nta [r4] = r5
st1.rel.nta [r4] = r5, -232
st2.rel [r4] = r5
st2.rel [r4] = r5, -219
st2.rel.nta [r4] = r5
st2.rel.nta [r4] = r5, -206
st4.rel [r4] = r5
st4.rel [r4] = r5, -193
st4.rel.nta [r4] = r5
st4.rel.nta [r4] = r5, -180
st8.rel [r4] = r5
st8.rel [r4] = r5, -167
st8.rel.nta [r4] = r5
st8.rel.nta [r4] = r5, -154
st8.spill [r4] = r5
st8.spill [r4] = r5, -141
st8.spill.nta [r4] = r5
st8.spill.nta [r4] = r5, -128
ldfs f4 = [r5]
ldfs f4 = [r5], r6
ldfs f4 = [r5], -115
ldfs.nt1 f4 = [r5]
ldfs.nt1 f4 = [r5], r6
ldfs.nt1 f4 = [r5], -102
ldfs.nta f4 = [r5]
ldfs.nta f4 = [r5], r6
ldfs.nta f4 = [r5], -89
ldfs.s f4 = [r5]
ldfs.s f4 = [r5], r6
ldfs.s f4 = [r5], -76
ldfs.s.nt1 f4 = [r5]
ldfs.s.nt1 f4 = [r5], r6
ldfs.s.nt1 f4 = [r5], -63
ldfs.s.nta f4 = [r5]
ldfs.s.nta f4 = [r5], r6
ldfs.s.nta f4 = [r5], -50
ldfs.a f4 = [r5]
ldfs.a f4 = [r5], r6
ldfs.a f4 = [r5], -37
ldfs.a.nt1 f4 = [r5]
ldfs.a.nt1 f4 = [r5], r6
ldfs.a.nt1 f4 = [r5], -24
ldfs.a.nta f4 = [r5]
ldfs.a.nta f4 = [r5], r6
ldfs.a.nta f4 = [r5], -11
ldfs.sa f4 = [r5]
ldfs.sa f4 = [r5], r6
ldfs.sa f4 = [r5], 2
ldfs.sa.nt1 f4 = [r5]
ldfs.sa.nt1 f4 = [r5], r6
ldfs.sa.nt1 f4 = [r5], 15
ldfs.sa.nta f4 = [r5]
ldfs.sa.nta f4 = [r5], r6
ldfs.sa.nta f4 = [r5], 28
ldfs.c.clr f4 = [r5]
ldfs.c.clr f4 = [r5], r6
ldfs.c.clr f4 = [r5], 41
ldfs.c.clr.nt1 f4 = [r5]
ldfs.c.clr.nt1 f4 = [r5], r6
ldfs.c.clr.nt1 f4 = [r5], 54
ldfs.c.clr.nta f4 = [r5]
ldfs.c.clr.nta f4 = [r5], r6
ldfs.c.clr.nta f4 = [r5], 67
ldfs.c.nc f4 = [r5]
ldfs.c.nc f4 = [r5], r6
ldfs.c.nc f4 = [r5], 80
ldfs.c.nc.nt1 f4 = [r5]
ldfs.c.nc.nt1 f4 = [r5], r6
ldfs.c.nc.nt1 f4 = [r5], 93
ldfs.c.nc.nta f4 = [r5]
ldfs.c.nc.nta f4 = [r5], r6
ldfs.c.nc.nta f4 = [r5], 106
ldfd f4 = [r5]
ldfd f4 = [r5], r6
ldfd f4 = [r5], 119
ldfd.nt1 f4 = [r5]
ldfd.nt1 f4 = [r5], r6
ldfd.nt1 f4 = [r5], 132
ldfd.nta f4 = [r5]
ldfd.nta f4 = [r5], r6
ldfd.nta f4 = [r5], 145
ldfd.s f4 = [r5]
ldfd.s f4 = [r5], r6
ldfd.s f4 = [r5], 158
ldfd.s.nt1 f4 = [r5]
ldfd.s.nt1 f4 = [r5], r6
ldfd.s.nt1 f4 = [r5], 171
ldfd.s.nta f4 = [r5]
ldfd.s.nta f4 = [r5], r6
ldfd.s.nta f4 = [r5], 184
ldfd.a f4 = [r5]
ldfd.a f4 = [r5], r6
ldfd.a f4 = [r5], 197
ldfd.a.nt1 f4 = [r5]
ldfd.a.nt1 f4 = [r5], r6
ldfd.a.nt1 f4 = [r5], 210
ldfd.a.nta f4 = [r5]
ldfd.a.nta f4 = [r5], r6
ldfd.a.nta f4 = [r5], 223
ldfd.sa f4 = [r5]
ldfd.sa f4 = [r5], r6
ldfd.sa f4 = [r5], 236
ldfd.sa.nt1 f4 = [r5]
ldfd.sa.nt1 f4 = [r5], r6
ldfd.sa.nt1 f4 = [r5], 249
ldfd.sa.nta f4 = [r5]
ldfd.sa.nta f4 = [r5], r6
ldfd.sa.nta f4 = [r5], -250
ldfd.c.clr f4 = [r5]
ldfd.c.clr f4 = [r5], r6
ldfd.c.clr f4 = [r5], -237
ldfd.c.clr.nt1 f4 = [r5]
ldfd.c.clr.nt1 f4 = [r5], r6
ldfd.c.clr.nt1 f4 = [r5], -224
ldfd.c.clr.nta f4 = [r5]
ldfd.c.clr.nta f4 = [r5], r6
ldfd.c.clr.nta f4 = [r5], -211
ldfd.c.nc f4 = [r5]
ldfd.c.nc f4 = [r5], r6
ldfd.c.nc f4 = [r5], -198
ldfd.c.nc.nt1 f4 = [r5]
ldfd.c.nc.nt1 f4 = [r5], r6
ldfd.c.nc.nt1 f4 = [r5], -185
ldfd.c.nc.nta f4 = [r5]
ldfd.c.nc.nta f4 = [r5], r6
ldfd.c.nc.nta f4 = [r5], -172
ldf8 f4 = [r5]
ldf8 f4 = [r5], r6
ldf8 f4 = [r5], -159
ldf8.nt1 f4 = [r5]
ldf8.nt1 f4 = [r5], r6
ldf8.nt1 f4 = [r5], -146
ldf8.nta f4 = [r5]
ldf8.nta f4 = [r5], r6
ldf8.nta f4 = [r5], -133
ldf8.s f4 = [r5]
ldf8.s f4 = [r5], r6
ldf8.s f4 = [r5], -120
ldf8.s.nt1 f4 = [r5]
ldf8.s.nt1 f4 = [r5], r6
ldf8.s.nt1 f4 = [r5], -107
ldf8.s.nta f4 = [r5]
ldf8.s.nta f4 = [r5], r6
ldf8.s.nta f4 = [r5], -94
ldf8.a f4 = [r5]
ldf8.a f4 = [r5], r6
ldf8.a f4 = [r5], -81
ldf8.a.nt1 f4 = [r5]
ldf8.a.nt1 f4 = [r5], r6
ldf8.a.nt1 f4 = [r5], -68
ldf8.a.nta f4 = [r5]
ldf8.a.nta f4 = [r5], r6
ldf8.a.nta f4 = [r5], -55
ldf8.sa f4 = [r5]
ldf8.sa f4 = [r5], r6
ldf8.sa f4 = [r5], -42
ldf8.sa.nt1 f4 = [r5]
ldf8.sa.nt1 f4 = [r5], r6
ldf8.sa.nt1 f4 = [r5], -29
ldf8.sa.nta f4 = [r5]
ldf8.sa.nta f4 = [r5], r6
ldf8.sa.nta f4 = [r5], -16
ldf8.c.clr f4 = [r5]
ldf8.c.clr f4 = [r5], r6
ldf8.c.clr f4 = [r5], -3
ldf8.c.clr.nt1 f4 = [r5]
ldf8.c.clr.nt1 f4 = [r5], r6
ldf8.c.clr.nt1 f4 = [r5], 10
ldf8.c.clr.nta f4 = [r5]
ldf8.c.clr.nta f4 = [r5], r6
ldf8.c.clr.nta f4 = [r5], 23
ldf8.c.nc f4 = [r5]
ldf8.c.nc f4 = [r5], r6
ldf8.c.nc f4 = [r5], 36
ldf8.c.nc.nt1 f4 = [r5]
ldf8.c.nc.nt1 f4 = [r5], r6
ldf8.c.nc.nt1 f4 = [r5], 49
ldf8.c.nc.nta f4 = [r5]
ldf8.c.nc.nta f4 = [r5], r6
ldf8.c.nc.nta f4 = [r5], 62
ldfe f4 = [r5]
ldfe f4 = [r5], r6
ldfe f4 = [r5], 75
ldfe.nt1 f4 = [r5]
ldfe.nt1 f4 = [r5], r6
ldfe.nt1 f4 = [r5], 88
ldfe.nta f4 = [r5]
ldfe.nta f4 = [r5], r6
ldfe.nta f4 = [r5], 101
ldfe.s f4 = [r5]
ldfe.s f4 = [r5], r6
ldfe.s f4 = [r5], 114
ldfe.s.nt1 f4 = [r5]
ldfe.s.nt1 f4 = [r5], r6
ldfe.s.nt1 f4 = [r5], 127
ldfe.s.nta f4 = [r5]
ldfe.s.nta f4 = [r5], r6
ldfe.s.nta f4 = [r5], 140
ldfe.a f4 = [r5]
ldfe.a f4 = [r5], r6
ldfe.a f4 = [r5], 153
ldfe.a.nt1 f4 = [r5]
ldfe.a.nt1 f4 = [r5], r6
ldfe.a.nt1 f4 = [r5], 166
ldfe.a.nta f4 = [r5]
ldfe.a.nta f4 = [r5], r6
ldfe.a.nta f4 = [r5], 179
ldfe.sa f4 = [r5]
ldfe.sa f4 = [r5], r6
ldfe.sa f4 = [r5], 192
ldfe.sa.nt1 f4 = [r5]
ldfe.sa.nt1 f4 = [r5], r6
ldfe.sa.nt1 f4 = [r5], 205
ldfe.sa.nta f4 = [r5]
ldfe.sa.nta f4 = [r5], r6
ldfe.sa.nta f4 = [r5], 218
ldfe.c.clr f4 = [r5]
ldfe.c.clr f4 = [r5], r6
ldfe.c.clr f4 = [r5], 231
ldfe.c.clr.nt1 f4 = [r5]
ldfe.c.clr.nt1 f4 = [r5], r6
ldfe.c.clr.nt1 f4 = [r5], 244
ldfe.c.clr.nta f4 = [r5]
ldfe.c.clr.nta f4 = [r5], r6
ldfe.c.clr.nta f4 = [r5], -255
ldfe.c.nc f4 = [r5]
ldfe.c.nc f4 = [r5], r6
ldfe.c.nc f4 = [r5], -242
ldfe.c.nc.nt1 f4 = [r5]
ldfe.c.nc.nt1 f4 = [r5], r6
ldfe.c.nc.nt1 f4 = [r5], -229
ldfe.c.nc.nta f4 = [r5]
ldfe.c.nc.nta f4 = [r5], r6
ldfe.c.nc.nta f4 = [r5], -216
ldf.fill f4 = [r5]
ldf.fill f4 = [r5], r6
ldf.fill f4 = [r5], -203
ldf.fill.nt1 f4 = [r5]
ldf.fill.nt1 f4 = [r5], r6
ldf.fill.nt1 f4 = [r5], -190
ldf.fill.nta f4 = [r5]
ldf.fill.nta f4 = [r5], r6
ldf.fill.nta f4 = [r5], -177
stfs [r4] = f5
stfs [r4] = f5, -164
stfs.nta [r4] = f5
stfs.nta [r4] = f5, -151
stfd [r4] = f5
stfd [r4] = f5, -138
stfd.nta [r4] = f5
stfd.nta [r4] = f5, -125
stf8 [r4] = f5
stf8 [r4] = f5, -112
stf8.nta [r4] = f5
stf8.nta [r4] = f5, -99
stfe [r4] = f5
stfe [r4] = f5, -86
stfe.nta [r4] = f5
stfe.nta [r4] = f5, -73
stf.spill [r4] = f5
stf.spill [r4] = f5, -60
stf.spill.nta [r4] = f5
stf.spill.nta [r4] = f5, -47
ldfps f4, f5 = [r5]
ldfps f4, f5 = [r5], 8
ldfps.nt1 f4, f5 = [r5]
ldfps.nt1 f4, f5 = [r5], 8
ldfps.nta f4, f5 = [r5]
ldfps.nta f4, f5 = [r5], 8
ldfps.s f4, f5 = [r5]
ldfps.s f4, f5 = [r5], 8
ldfps.s.nt1 f4, f5 = [r5]
ldfps.s.nt1 f4, f5 = [r5], 8
ldfps.s.nta f4, f5 = [r5]
ldfps.s.nta f4, f5 = [r5], 8
ldfps.a f4, f5 = [r5]
ldfps.a f4, f5 = [r5], 8
ldfps.a.nt1 f4, f5 = [r5]
ldfps.a.nt1 f4, f5 = [r5], 8
ldfps.a.nta f4, f5 = [r5]
ldfps.a.nta f4, f5 = [r5], 8
ldfps.sa f4, f5 = [r5]
ldfps.sa f4, f5 = [r5], 8
ldfps.sa.nt1 f4, f5 = [r5]
ldfps.sa.nt1 f4, f5 = [r5], 8
ldfps.sa.nta f4, f5 = [r5]
ldfps.sa.nta f4, f5 = [r5], 8
ldfps.c.clr f4, f5 = [r5]
ldfps.c.clr f4, f5 = [r5], 8
ldfps.c.clr.nt1 f4, f5 = [r5]
ldfps.c.clr.nt1 f4, f5 = [r5], 8
ldfps.c.clr.nta f4, f5 = [r5]
ldfps.c.clr.nta f4, f5 = [r5], 8
ldfps.c.nc f4, f5 = [r5]
ldfps.c.nc f4, f5 = [r5], 8
ldfps.c.nc.nt1 f4, f5 = [r5]
ldfps.c.nc.nt1 f4, f5 = [r5], 8
ldfps.c.nc.nta f4, f5 = [r5]
ldfps.c.nc.nta f4, f5 = [r5], 8
ldfpd f4, f5 = [r5]
ldfpd f4, f5 = [r5], 16
ldfpd.nt1 f4, f5 = [r5]
ldfpd.nt1 f4, f5 = [r5], 16
ldfpd.nta f4, f5 = [r5]
ldfpd.nta f4, f5 = [r5], 16
ldfpd.s f4, f5 = [r5]
ldfpd.s f4, f5 = [r5], 16
ldfpd.s.nt1 f4, f5 = [r5]
ldfpd.s.nt1 f4, f5 = [r5], 16
ldfpd.s.nta f4, f5 = [r5]
ldfpd.s.nta f4, f5 = [r5], 16
ldfpd.a f4, f5 = [r5]
ldfpd.a f4, f5 = [r5], 16
ldfpd.a.nt1 f4, f5 = [r5]
ldfpd.a.nt1 f4, f5 = [r5], 16
ldfpd.a.nta f4, f5 = [r5]
ldfpd.a.nta f4, f5 = [r5], 16
ldfpd.sa f4, f5 = [r5]
ldfpd.sa f4, f5 = [r5], 16
ldfpd.sa.nt1 f4, f5 = [r5]
ldfpd.sa.nt1 f4, f5 = [r5], 16
ldfpd.sa.nta f4, f5 = [r5]
ldfpd.sa.nta f4, f5 = [r5], 16
ldfpd.c.clr f4, f5 = [r5]
ldfpd.c.clr f4, f5 = [r5], 16
ldfpd.c.clr.nt1 f4, f5 = [r5]
ldfpd.c.clr.nt1 f4, f5 = [r5], 16
ldfpd.c.clr.nta f4, f5 = [r5]
ldfpd.c.clr.nta f4, f5 = [r5], 16
ldfpd.c.nc f4, f5 = [r5]
ldfpd.c.nc f4, f5 = [r5], 16
ldfpd.c.nc.nt1 f4, f5 = [r5]
ldfpd.c.nc.nt1 f4, f5 = [r5], 16
ldfpd.c.nc.nta f4, f5 = [r5]
ldfpd.c.nc.nta f4, f5 = [r5], 16
ldfp8 f4, f5 = [r5]
ldfp8 f4, f5 = [r5], 16
ldfp8.nt1 f4, f5 = [r5]
ldfp8.nt1 f4, f5 = [r5], 16
ldfp8.nta f4, f5 = [r5]
ldfp8.nta f4, f5 = [r5], 16
ldfp8.s f4, f5 = [r5]
ldfp8.s f4, f5 = [r5], 16
ldfp8.s.nt1 f4, f5 = [r5]
ldfp8.s.nt1 f4, f5 = [r5], 16
ldfp8.s.nta f4, f5 = [r5]
ldfp8.s.nta f4, f5 = [r5], 16
ldfp8.a f4, f5 = [r5]
ldfp8.a f4, f5 = [r5], 16
ldfp8.a.nt1 f4, f5 = [r5]
ldfp8.a.nt1 f4, f5 = [r5], 16
ldfp8.a.nta f4, f5 = [r5]
ldfp8.a.nta f4, f5 = [r5], 16
ldfp8.sa f4, f5 = [r5]
ldfp8.sa f4, f5 = [r5], 16
ldfp8.sa.nt1 f4, f5 = [r5]
ldfp8.sa.nt1 f4, f5 = [r5], 16
ldfp8.sa.nta f4, f5 = [r5]
ldfp8.sa.nta f4, f5 = [r5], 16
ldfp8.c.clr f4, f5 = [r5]
ldfp8.c.clr f4, f5 = [r5], 16
ldfp8.c.clr.nt1 f4, f5 = [r5]
ldfp8.c.clr.nt1 f4, f5 = [r5], 16
ldfp8.c.clr.nta f4, f5 = [r5]
ldfp8.c.clr.nta f4, f5 = [r5], 16
ldfp8.c.nc f4, f5 = [r5]
ldfp8.c.nc f4, f5 = [r5], 16
ldfp8.c.nc.nt1 f4, f5 = [r5]
ldfp8.c.nc.nt1 f4, f5 = [r5], 16
ldfp8.c.nc.nta f4, f5 = [r5]
ldfp8.c.nc.nta f4, f5 = [r5], 16
lfetch [r4]
lfetch [r4], r5
lfetch [r4], -34
lfetch.nt1 [r4]
lfetch.nt1 [r4], r5
lfetch.nt1 [r4], -21
lfetch.nt2 [r4]
lfetch.nt2 [r4], r5
lfetch.nt2 [r4], -8
lfetch.nta [r4]
lfetch.nta [r4], r5
lfetch.nta [r4], 5
lfetch.fault [r4]
lfetch.fault [r4], r5
lfetch.fault [r4], 18
lfetch.fault.nt1 [r4]
lfetch.fault.nt1 [r4], r5
lfetch.fault.nt1 [r4], 31
lfetch.fault.nt2 [r4]
lfetch.fault.nt2 [r4], r5
lfetch.fault.nt2 [r4], 44
lfetch.fault.nta [r4]
lfetch.fault.nta [r4], r5
lfetch.fault.nta [r4], 57
lfetch.excl [r4]
lfetch.excl [r4], r5
lfetch.excl [r4], 70
lfetch.excl.nt1 [r4]
lfetch.excl.nt1 [r4], r5
lfetch.excl.nt1 [r4], 83
lfetch.excl.nt2 [r4]
lfetch.excl.nt2 [r4], r5
lfetch.excl.nt2 [r4], 96
lfetch.excl.nta [r4]
lfetch.excl.nta [r4], r5
lfetch.excl.nta [r4], 109
lfetch.fault.excl [r4]
lfetch.fault.excl [r4], r5
lfetch.fault.excl [r4], 122
lfetch.fault.excl.nt1 [r4]
lfetch.fault.excl.nt1 [r4], r5
lfetch.fault.excl.nt1 [r4], 135
lfetch.fault.excl.nt2 [r4]
lfetch.fault.excl.nt2 [r4], r5
lfetch.fault.excl.nt2 [r4], 148
lfetch.fault.excl.nta [r4]
lfetch.fault.excl.nta [r4], r5
lfetch.fault.excl.nta [r4], 161
cmpxchg1.acq r4 = [r5], r6, ar.ccv
cmpxchg1.acq.nt1 r4 = [r5], r6, ar.ccv
cmpxchg1.acq.nta r4 = [r5], r6, ar.ccv
cmpxchg1.rel r4 = [r5], r6, ar.ccv
cmpxchg1.rel.nt1 r4 = [r5], r6, ar.ccv
cmpxchg1.rel.nta r4 = [r5], r6, ar.ccv
cmpxchg2.acq r4 = [r5], r6, ar.ccv
cmpxchg2.acq.nt1 r4 = [r5], r6, ar.ccv
cmpxchg2.acq.nta r4 = [r5], r6, ar.ccv
cmpxchg2.rel r4 = [r5], r6, ar.ccv
cmpxchg2.rel.nt1 r4 = [r5], r6, ar.ccv
cmpxchg2.rel.nta r4 = [r5], r6, ar.ccv
cmpxchg4.acq r4 = [r5], r6, ar.ccv
cmpxchg4.acq.nt1 r4 = [r5], r6, ar.ccv
cmpxchg4.acq.nta r4 = [r5], r6, ar.ccv
cmpxchg4.rel r4 = [r5], r6, ar.ccv
cmpxchg4.rel.nt1 r4 = [r5], r6, ar.ccv
cmpxchg4.rel.nta r4 = [r5], r6, ar.ccv
cmpxchg8.acq r4 = [r5], r6, ar.ccv
cmpxchg8.acq.nt1 r4 = [r5], r6, ar.ccv
cmpxchg8.acq.nta r4 = [r5], r6, ar.ccv
cmpxchg8.rel r4 = [r5], r6, ar.ccv
cmpxchg8.rel.nt1 r4 = [r5], r6, ar.ccv
cmpxchg8.rel.nta r4 = [r5], r6, ar.ccv
xchg1 r4 = [r5], r6
xchg1.nt1 r4 = [r5], r6
xchg1.nta r4 = [r5], r6
xchg2 r4 = [r5], r6
xchg2.nt1 r4 = [r5], r6
xchg2.nta r4 = [r5], r6
xchg4 r4 = [r5], r6
xchg4.nt1 r4 = [r5], r6
xchg4.nta r4 = [r5], r6
xchg8 r4 = [r5], r6
xchg8.nt1 r4 = [r5], r6
xchg8.nta r4 = [r5], r6
fetchadd4.acq r4 = [r5], -16
fetchadd4.acq.nt1 r4 = [r5], -8
fetchadd4.acq.nta r4 = [r5], -4
fetchadd8.acq r4 = [r5], -1
fetchadd8.acq.nt1 r4 = [r5], 1
fetchadd8.acq.nta r4 = [r5], 4
fetchadd4.rel r4 = [r5], 8
fetchadd4.rel.nt1 r4 = [r5], 16
fetchadd4.rel.nta r4 = [r5], -16
fetchadd8.rel r4 = [r5], -8
fetchadd8.rel.nt1 r4 = [r5], -4
fetchadd8.rel.nta r4 = [r5], -1
setf.sig f4 = r5
setf.exp f4 = r5
setf.s f4 = r5
setf.d f4 = r5
getf.sig r4 = f5
getf.exp r4 = f5
getf.s r4 = f5
getf.d r4 = f5
chk.s.m r4, _start
chk.s f4, _start
chk.a.nc r4, _start
chk.a.clr r4, _start
chk.a.nc f4, _start
chk.a.clr f4, _start
invala
fwb
mf
mf.a
srlz.d
srlz.i
sync.i
nop.m 0
nop.i 0;;
{ .mii; alloc r4 = ar.pfs, 2, 10, 16, 16;; }
{ .mii; flushrs;; }
{ .mii; loadrs }
invala.e r4
invala.e f4
fc r4
ptc.e r4
break.m 0
break.m 0x1ffff
nop.m 0
nop.m 0x1ffff
probe.r r4 = r5, r6
probe.w r4 = r5, r6
probe.r r4 = r5, 0
probe.w r4 = r5, 1
probe.r.fault r3, 2
probe.w.fault r3, 3
probe.rw.fault r3, 0
{ .mmi; itc.d r8;; nop.m 0x0; nop.i 0x0;; }
itc.i r9;;
sum 0x1234
rum 0x5aaaaa
ssm 0xffffff
rsm 0x400000
ptc.l r4, r5
{ .mmi; ptc.g r4, r5;; nop.m 0x0; nop.i 0x0 }
{ .mmi; ptc.ga r4, r5;; nop.m 0x0; nop.i 0x0 }
ptr.d r4, r5
ptr.i r4, r5
thash r4 = r5
ttag r4 = r5
tpa r4 = r5
tak r4 = r5
# instructions added by SDM2.1:
hint.m 0
hint.m @pause
hint.m 0x1ffff
cmp8xchg16.acq r4 = [r5], r6, ar25, ar.ccv
cmp8xchg16.acq.nt1 r4 = [r5], r6, ar.csd, ar.ccv
cmp8xchg16.acq.nta r4 = [r5], r6, ar.csd, ar.ccv
cmp8xchg16.rel r4 = [r5], r6, ar.csd, ar.ccv
cmp8xchg16.rel.nt1 r4 = [r5], r6, ar.csd, ar.ccv
cmp8xchg16.rel.nta r4 = [r5], r6, ar.csd, ar.ccv
fc.i r4
ld16 r4, ar25 = [r5]
ld16.nt1 r4, ar.csd = [r5]
ld16.nta r4, ar.csd = [r5]
ld16.acq r4, ar25 = [r5]
ld16.acq.nt1 r4, ar.csd = [r5]
ld16.acq.nta r4, ar.csd = [r5]
st16 [r4] = r5, ar25
st16.nta [r4] = r5, ar.csd
st16.rel [r4] = r5, ar.csd
st16.rel.nta [r4] = r5, ar.csd
|
tactcomplabs/xbgas-binutils-gdb
| 1,741
|
gas/testsuite/gas/ia64/unwind-bad.s
|
.text
.proc full1
full1:
.prologue
.spill 0
.save.g 0
nop 0
.save.g 0x10
nop 0
.save.g -1
nop 0
.save.g 0x3
nop 0
.save.g 0x4
nop 0
.save.g 0x1
nop 0
.save.f 0
nop 0
.save.f 0x100000
nop 0
.save.f -1
nop 0
.save.f 0x3
nop 0
.save.f 0x4
nop 0
.save.f 0x1
nop 0
.save.b 0
nop 0
.save.b 0x20
nop 0
.save.b -1
nop 0
.save.b 0x3
nop 0
.save.b 0x4
nop 0
.save.b 0x1
nop 0
.spillreg r4, r0
nop 0
.spillreg r3, r2
nop 0
.spillreg r8, r9
nop 0
.spillreg b6, r10
nop 0
.spillreg f2, f0
nop 0
.spillreg f3, f1
nop 0
.spillreg f6, f7
nop 0
.spillreg f4, r11
nop 0
.spillreg f5, b0
nop 0
.spillreg.p p0, r4, r3
nop 0
.spillreg.p p1, r4, r0
nop 0
.spillreg.p p1, f16, f0
nop 0
.restorereg.p p0, r4
nop 0
.body
br.ret.sptk rp
.endp full1
.proc full2
full2:
.prologue
.spill 0
.save.gf 0, 0
nop 0
.save.gf 0x10, 0
nop 0
.save.gf 0, 0x100000
nop 0
.save.gf ~0, 0
nop 0
.save.gf 0, ~0
nop 0
.save.gf 1, 1
nop 0
.save.gf 2, 0
nop 0
.save.gf 1, 0
nop 0
.save.gf 0, 1
nop 0
.body
.label_state 1
.restore sp, 1
nop.x 0
.copy_state 2
br.ret.sptk rp
.endp full2
.proc full3
full3:
.prologue
.spill 0
.save.g 0x10, r16
nop 0
.save.g 0x01, r0
nop 0
.save.g 0x06, r127
nop 0
nop 0
.save.b 0x20, r16
nop 0
.save.b 0x01, r0
nop 0
.save.b 0x18, r127
nop 0
nop 0
.body
br.ret.sptk rp
.endp full3
.proc simple1
simple1:
.prologue 0x10, r2
br.ret.sptk rp
.endp simple1
.proc simple2
simple2:
.prologue 0, r2
br.ret.sptk rp
.endp simple2
.proc simple3
simple3:
.prologue -1, r2
.vframe r0
br.ret.sptk rp
.endp simple3
.proc simple4
simple4:
.prologue 0x1, r0
br.ret.sptk rp
.endp simple4
.proc simple5
simple5:
.prologue 0xc, r127
br.ret.sptk rp
.endp simple5
|
tactcomplabs/xbgas-binutils-gdb
| 1,260
|
gas/testsuite/gas/ia64/xdata.s
|
// Note that most of the section names used here aren't legal as operands
// to either .section or .xdata/.xreal/.xstring (quoted strings aren't in
// general), but since generic code accepts them for .section we also test
// this here for our target specific directives. This could be viewed as a
// shortcut of a pair of .section/.secalias for each of them.
.section .xdata1, "a", @progbits
.section ".xdata2", "a", @progbits
.section ",xdata3", "a", @progbits
.section ".xdata,4", "a", @progbits
.section "\".xdata5\"", "a", @progbits
.section ".xreal\\1", "a", @progbits
.section ".xreal+2", "a", @progbits
.section ".xreal(3)", "a", @progbits
.section ".xreal[4]", "a", @progbits
.section ".xstr<1>", "a", @progbits
.section ".xstr{2}", "a", @progbits
.text
.xdata1 .xdata1, 1
.xdata2 ".xdata2", 2
.xdata4 ",xdata3", 3
.xdata8 ".xdata,4", 4
.xdata16 "\".xdata5\"", @iplt(_start)
.xdata2.ua ".xdata2", 2
.xdata4.ua ",xdata3", 3
.xdata8.ua ".xdata,4", 4
.xdata16.ua "\".xdata5\"", @iplt(_start)
.xreal4 ".xreal\\1", 1
.xreal8 ".xreal+2", 2
.xreal10 ".xreal(3)", 3
.xreal16 ".xreal[4]", 4
.xreal4.ua ".xreal\\1", 1
.xreal8.ua ".xreal+2", 2
.xreal10.ua ".xreal(3)", 3
.xreal16.ua ".xreal[4]", 4
.xstring ".xstr<1>", "abc"
.xstringz ".xstr{2}", "xyz"
|
tactcomplabs/xbgas-binutils-gdb
| 9,948
|
gas/testsuite/gas/ia64/opc-a.s
|
.text
.type _start,@function
_start:
add r101 = r102, r103
(p1) add r104 = r105, r106
add r107 = r108, r109, 1
(p2) add r110 = r111, r112, 1
adds r20 = 0, r10
(p1) adds r21 = 1, r10
adds r22 = -1, r10
adds r23 = -0x2000, r10
(p2) adds r24 = 0x1FFF, r10
addl r30 = 0, r1
addl r31 = 1, r1
(p1) addl r32 = -1, r1
addl r33 = -0x2000, r1
addl r34 = 0x1FFF, r1
addl r35 = -0x200000, r1
addl r36 = 0x1FFFFF, r1
add r11 = 0, r10
add r12 = 0x1234, r10
add r13 = 0x1234, r1
add r14 = 0x12345, r1
addp4 r20 = r3, r10
(p1) addp4 r21 = 1, r10
addp4 r22 = -1, r10
sub r101 = r102, r103
(p2) sub r110 = r111, r112, 1
sub r120 = 0, r3
sub r121 = 1, r3
sub r122 = -1, r3
sub r123 = -128, r3
sub r124 = 127, r3
and r8 = r9, r10
(p3) and r11 = -128, r12
(p4) or r8 = r9, r10
or r11 = -128, r12
xor r8 = r9, r10
xor r11 = -128, r12
andcm r8 = r9, r10
andcm r11 = -128, r12
shladd r8 = r30, 1, r31
shladd r9 = r30, 2, r31
shladd r10 = r30, 3, r31
shladd r11 = r30, 4, r31
shladdp4 r8 = r30, 1, r31
shladdp4 r9 = r30, 2, r31
shladdp4 r10 = r30, 3, r31
shladdp4 r11 = r30, 4, r31
padd1 r10 = r30, r31
padd1.sss r11 = r30, r31
padd1.uus r12 = r30, r31
padd1.uuu r13 = r30, r31
padd2 r14 = r30, r31
padd2.sss r15 = r30, r31
padd2.uus r16 = r30, r31
padd2.uuu r17 = r30, r31
padd4 r18 = r30, r31
psub1 r10 = r30, r31
psub1.sss r11 = r30, r31
psub1.uus r12 = r30, r31
psub1.uuu r13 = r30, r31
psub2 r14 = r30, r31
psub2.sss r15 = r30, r31
psub2.uus r16 = r30, r31
psub2.uuu r17 = r30, r31
psub4 r18 = r30, r31
pavg1 r10 = r30, r31
pavg1.raz r10 = r30, r31
pavg2 r10 = r30, r31
pavg2.raz r10 = r30, r31
pavgsub1 r10 = r30, r31
pavgsub2 r10 = r30, r31
pcmp1.eq r10 = r30, r31
pcmp2.eq r10 = r30, r31
pcmp4.eq r10 = r30, r31
pcmp1.gt r10 = r30, r31
pcmp2.gt r10 = r30, r31
pcmp4.gt r10 = r30, r31
pshladd2 r10 = r11, 1, r12
pshladd2 r10 = r11, 3, r12
pshradd2 r10 = r11, 1, r12
pshradd2 r10 = r11, 2, r12
cmp.eq p2, p3 = r3, r4
cmp.eq p2, p3 = 3, r4
cmp.ne p2, p3 = r3, r4
cmp.ne p2, p3 = 3, r4
cmp.lt p2, p3 = r3, r4
cmp.lt p2, p3 = 3, r4
cmp.le p2, p3 = r3, r4
cmp.le p2, p3 = 3, r4
cmp.gt p2, p3 = r3, r4
cmp.gt p2, p3 = 3, r4
cmp.ge p2, p3 = r3, r4
cmp.ge p2, p3 = 3, r4
cmp.ltu p2, p3 = r3, r4
cmp.ltu p2, p3 = 3, r4
cmp.leu p2, p3 = r3, r4
cmp.leu p2, p3 = 3, r4
cmp.gtu p2, p3 = r3, r4
cmp.gtu p2, p3 = 3, r4
cmp.geu p2, p3 = r3, r4
cmp.geu p2, p3 = 3, r4
cmp.eq.unc p2, p3 = r3, r4
cmp.eq.unc p2, p3 = 3, r4
cmp.ne.unc p2, p3 = r3, r4
cmp.ne.unc p2, p3 = 3, r4
cmp.lt.unc p2, p3 = r3, r4
cmp.lt.unc p2, p3 = 3, r4
cmp.le.unc p2, p3 = r3, r4
cmp.le.unc p2, p3 = 3, r4
cmp.gt.unc p2, p3 = r3, r4
cmp.gt.unc p2, p3 = 3, r4
cmp.ge.unc p2, p3 = r3, r4
cmp.ge.unc p2, p3 = 3, r4
cmp.ltu.unc p2, p3 = r3, r4
cmp.ltu.unc p2, p3 = 3, r4
cmp.leu.unc p2, p3 = r3, r4
cmp.leu.unc p2, p3 = 3, r4
cmp.gtu.unc p2, p3 = r3, r4
cmp.gtu.unc p2, p3 = 3, r4
cmp.geu.unc p2, p3 = r3, r4
cmp.geu.unc p2, p3 = 3, r4
cmp.eq.and p2, p3 = r3, r4
cmp.eq.and p2, p3 = 3, r4
cmp.eq.or p2, p3 = r3, r4
cmp.eq.or p2, p3 = 3, r4
cmp.eq.or.andcm p2, p3 = r3, r4
cmp.eq.or.andcm p2, p3 = 3, r4
cmp.eq.orcm p2, p3 = r3, r4
cmp.eq.orcm p2, p3 = 3, r4
cmp.eq.andcm p2, p3 = r3, r4
cmp.eq.andcm p2, p3 = 3, r4
cmp.eq.and.orcm p2, p3 = r3, r4
cmp.eq.and.orcm p2, p3 = 3, r4
cmp.ne.and p2, p3 = r3, r4
cmp.ne.and p2, p3 = 3, r4
cmp.ne.or p2, p3 = r3, r4
cmp.ne.or p2, p3 = 3, r4
cmp.ne.or.andcm p2, p3 = r3, r4
cmp.ne.or.andcm p2, p3 = 3, r4
cmp.ne.orcm p2, p3 = r3, r4
cmp.ne.orcm p2, p3 = 3, r4
cmp.ne.andcm p2, p3 = r3, r4
cmp.ne.andcm p2, p3 = 3, r4
cmp.ne.and.orcm p2, p3 = r3, r4
cmp.ne.and.orcm p2, p3 = 3, r4
cmp.eq.and p2, p3 = r0, r4
cmp.eq.and p2, p3 = r4, r0
cmp.eq.or p2, p3 = r0, r4
cmp.eq.or p2, p3 = r4, r0
cmp.eq.or.andcm p2, p3 = r0, r4
cmp.eq.or.andcm p2, p3 = r4, r0
cmp.eq.orcm p2, p3 = r0, r4
cmp.eq.orcm p2, p3 = r4, r0
cmp.eq.andcm p2, p3 = r0, r4
cmp.eq.andcm p2, p3 = r4, r0
cmp.eq.and.orcm p2, p3 = r0, r4
cmp.eq.and.orcm p2, p3 = r4, r0
cmp.ne.and p2, p3 = r0, r4
cmp.ne.and p2, p3 = r4, r0
cmp.ne.or p2, p3 = r0, r4
cmp.ne.or p2, p3 = r4, r0
cmp.ne.or.andcm p2, p3 = r0, r4
cmp.ne.or.andcm p2, p3 = r4, r0
cmp.ne.orcm p2, p3 = r0, r4
cmp.ne.orcm p2, p3 = r4, r0
cmp.ne.andcm p2, p3 = r0, r4
cmp.ne.andcm p2, p3 = r4, r0
cmp.ne.and.orcm p2, p3 = r0, r4
cmp.ne.and.orcm p2, p3 = r4, r0
cmp.lt.and p2, p3 = r0, r4
cmp.lt.and p2, p3 = r4, r0
cmp.lt.or p2, p3 = r0, r4
cmp.lt.or p2, p3 = r4, r0
cmp.lt.or.andcm p2, p3 = r0, r4
cmp.lt.or.andcm p2, p3 = r4, r0
cmp.lt.orcm p2, p3 = r0, r4
cmp.lt.orcm p2, p3 = r4, r0
cmp.lt.andcm p2, p3 = r0, r4
cmp.lt.andcm p2, p3 = r4, r0
cmp.lt.and.orcm p2, p3 = r0, r4
cmp.lt.and.orcm p2, p3 = r4, r0
cmp.le.and p2, p3 = r0, r4
cmp.le.and p2, p3 = r4, r0
cmp.le.or p2, p3 = r0, r4
cmp.le.or p2, p3 = r4, r0
cmp.le.or.andcm p2, p3 = r0, r4
cmp.le.or.andcm p2, p3 = r4, r0
cmp.le.orcm p2, p3 = r0, r4
cmp.le.orcm p2, p3 = r4, r0
cmp.le.andcm p2, p3 = r0, r4
cmp.le.andcm p2, p3 = r4, r0
cmp.le.and.orcm p2, p3 = r0, r4
cmp.le.and.orcm p2, p3 = r4, r0
cmp.gt.and p2, p3 = r0, r4
cmp.gt.and p2, p3 = r4, r0
cmp.gt.or p2, p3 = r0, r4
cmp.gt.or p2, p3 = r4, r0
cmp.gt.or.andcm p2, p3 = r0, r4
cmp.gt.or.andcm p2, p3 = r4, r0
cmp.gt.orcm p2, p3 = r0, r4
cmp.gt.orcm p2, p3 = r4, r0
cmp.gt.andcm p2, p3 = r0, r4
cmp.gt.andcm p2, p3 = r4, r0
cmp.gt.and.orcm p2, p3 = r0, r4
cmp.gt.and.orcm p2, p3 = r4, r0
cmp.ge.and p2, p3 = r0, r4
cmp.ge.and p2, p3 = r4, r0
cmp.ge.or p2, p3 = r0, r4
cmp.ge.or p2, p3 = r4, r0
cmp.ge.or.andcm p2, p3 = r0, r4
cmp.ge.or.andcm p2, p3 = r4, r0
cmp.ge.orcm p2, p3 = r0, r4
cmp.ge.orcm p2, p3 = r4, r0
cmp.ge.andcm p2, p3 = r0, r4
cmp.ge.andcm p2, p3 = r4, r0
cmp.ge.and.orcm p2, p3 = r0, r4
cmp.ge.and.orcm p2, p3 = r4, r0
cmp4.eq p2, p3 = r3, r4
cmp4.eq p2, p3 = 3, r4
cmp4.ne p2, p3 = r3, r4
cmp4.ne p2, p3 = 3, r4
cmp4.lt p2, p3 = r3, r4
cmp4.lt p2, p3 = 3, r4
cmp4.le p2, p3 = r3, r4
cmp4.le p2, p3 = 3, r4
cmp4.gt p2, p3 = r3, r4
cmp4.gt p2, p3 = 3, r4
cmp4.ge p2, p3 = r3, r4
cmp4.ge p2, p3 = 3, r4
cmp4.ltu p2, p3 = r3, r4
cmp4.ltu p2, p3 = 3, r4
cmp4.leu p2, p3 = r3, r4
cmp4.leu p2, p3 = 3, r4
cmp4.gtu p2, p3 = r3, r4
cmp4.gtu p2, p3 = 3, r4
cmp4.geu p2, p3 = r3, r4
cmp4.geu p2, p3 = 3, r4
cmp4.eq.unc p2, p3 = r3, r4
cmp4.eq.unc p2, p3 = 3, r4
cmp4.ne.unc p2, p3 = r3, r4
cmp4.ne.unc p2, p3 = 3, r4
cmp4.lt.unc p2, p3 = r3, r4
cmp4.lt.unc p2, p3 = 3, r4
cmp4.le.unc p2, p3 = r3, r4
cmp4.le.unc p2, p3 = 3, r4
cmp4.gt.unc p2, p3 = r3, r4
cmp4.gt.unc p2, p3 = 3, r4
cmp4.ge.unc p2, p3 = r3, r4
cmp4.ge.unc p2, p3 = 3, r4
cmp4.ltu.unc p2, p3 = r3, r4
cmp4.ltu.unc p2, p3 = 3, r4
cmp4.leu.unc p2, p3 = r3, r4
cmp4.leu.unc p2, p3 = 3, r4
cmp4.gtu.unc p2, p3 = r3, r4
cmp4.gtu.unc p2, p3 = 3, r4
cmp4.geu.unc p2, p3 = r3, r4
cmp4.geu.unc p2, p3 = 3, r4
cmp4.eq.and p2, p3 = r3, r4
cmp4.eq.and p2, p3 = 3, r4
cmp4.eq.or p2, p3 = r3, r4
cmp4.eq.or p2, p3 = 3, r4
cmp4.eq.or.andcm p2, p3 = r3, r4
cmp4.eq.or.andcm p2, p3 = 3, r4
cmp4.eq.orcm p2, p3 = r3, r4
cmp4.eq.orcm p2, p3 = 3, r4
cmp4.eq.andcm p2, p3 = r3, r4
cmp4.eq.andcm p2, p3 = 3, r4
cmp4.eq.and.orcm p2, p3 = r3, r4
cmp4.eq.and.orcm p2, p3 = 3, r4
cmp4.ne.and p2, p3 = r3, r4
cmp4.ne.and p2, p3 = 3, r4
cmp4.ne.or p2, p3 = r3, r4
cmp4.ne.or p2, p3 = 3, r4
cmp4.ne.or.andcm p2, p3 = r3, r4
cmp4.ne.or.andcm p2, p3 = 3, r4
cmp4.ne.orcm p2, p3 = r3, r4
cmp4.ne.orcm p2, p3 = 3, r4
cmp4.ne.andcm p2, p3 = r3, r4
cmp4.ne.andcm p2, p3 = 3, r4
cmp4.ne.and.orcm p2, p3 = r3, r4
cmp4.ne.and.orcm p2, p3 = 3, r4
cmp4.eq.and p2, p3 = r0, r4
cmp4.eq.and p2, p3 = r4, r0
cmp4.eq.or p2, p3 = r0, r4
cmp4.eq.or p2, p3 = r4, r0
cmp4.eq.or.andcm p2, p3 = r0, r4
cmp4.eq.or.andcm p2, p3 = r4, r0
cmp4.eq.orcm p2, p3 = r0, r4
cmp4.eq.orcm p2, p3 = r4, r0
cmp4.eq.andcm p2, p3 = r0, r4
cmp4.eq.andcm p2, p3 = r4, r0
cmp4.eq.and.orcm p2, p3 = r0, r4
cmp4.eq.and.orcm p2, p3 = r4, r0
cmp4.ne.and p2, p3 = r0, r4
cmp4.ne.and p2, p3 = r4, r0
cmp4.ne.or p2, p3 = r0, r4
cmp4.ne.or p2, p3 = r4, r0
cmp4.ne.or.andcm p2, p3 = r0, r4
cmp4.ne.or.andcm p2, p3 = r4, r0
cmp4.ne.orcm p2, p3 = r0, r4
cmp4.ne.orcm p2, p3 = r4, r0
cmp4.ne.andcm p2, p3 = r0, r4
cmp4.ne.andcm p2, p3 = r4, r0
cmp4.ne.and.orcm p2, p3 = r0, r4
cmp4.ne.and.orcm p2, p3 = r4, r0
cmp4.lt.and p2, p3 = r0, r4
cmp4.lt.and p2, p3 = r4, r0
cmp4.lt.or p2, p3 = r0, r4
cmp4.lt.or p2, p3 = r4, r0
cmp4.lt.or.andcm p2, p3 = r0, r4
cmp4.lt.or.andcm p2, p3 = r4, r0
cmp4.lt.orcm p2, p3 = r0, r4
cmp4.lt.orcm p2, p3 = r4, r0
cmp4.lt.andcm p2, p3 = r0, r4
cmp4.lt.andcm p2, p3 = r4, r0
cmp4.lt.and.orcm p2, p3 = r0, r4
cmp4.lt.and.orcm p2, p3 = r4, r0
cmp4.le.and p2, p3 = r0, r4
cmp4.le.and p2, p3 = r4, r0
cmp4.le.or p2, p3 = r0, r4
cmp4.le.or p2, p3 = r4, r0
cmp4.le.or.andcm p2, p3 = r0, r4
cmp4.le.or.andcm p2, p3 = r4, r0
cmp4.le.orcm p2, p3 = r0, r4
cmp4.le.orcm p2, p3 = r4, r0
cmp4.le.andcm p2, p3 = r0, r4
cmp4.le.andcm p2, p3 = r4, r0
cmp4.le.and.orcm p2, p3 = r0, r4
cmp4.le.and.orcm p2, p3 = r4, r0
cmp4.gt.and p2, p3 = r0, r4
cmp4.gt.and p2, p3 = r4, r0
cmp4.gt.or p2, p3 = r0, r4
cmp4.gt.or p2, p3 = r4, r0
cmp4.gt.or.andcm p2, p3 = r0, r4
cmp4.gt.or.andcm p2, p3 = r4, r0
cmp4.gt.orcm p2, p3 = r0, r4
cmp4.gt.orcm p2, p3 = r4, r0
cmp4.gt.andcm p2, p3 = r0, r4
cmp4.gt.andcm p2, p3 = r4, r0
cmp4.gt.and.orcm p2, p3 = r0, r4
cmp4.gt.and.orcm p2, p3 = r4, r0
cmp4.ge.and p2, p3 = r0, r4
cmp4.ge.and p2, p3 = r4, r0
cmp4.ge.or p2, p3 = r0, r4
cmp4.ge.or p2, p3 = r4, r0
cmp4.ge.or.andcm p2, p3 = r0, r4
cmp4.ge.or.andcm p2, p3 = r4, r0
cmp4.ge.orcm p2, p3 = r0, r4
cmp4.ge.orcm p2, p3 = r4, r0
cmp4.ge.andcm p2, p3 = r0, r4
cmp4.ge.andcm p2, p3 = r4, r0
cmp4.ge.and.orcm p2, p3 = r0, r4
cmp4.ge.and.orcm p2, p3 = r4, r0
nop.i 0; nop.i 0
|
tactcomplabs/xbgas-binutils-gdb
| 4,746
|
gas/testsuite/gas/ia64/opc-i.s
|
.text
.type _start,@function
_start:
pmpyshr2 r4 = r5, r6, 0
pmpyshr2.u r4 = r5, r6, 16
pmpy2.r r4 = r5, r6
pmpy2.l r4 = r5, r6
mix1.r r4 = r5, r6
mix2.r r4 = r5, r6
mix4.r r4 = r5, r6
mix1.l r4 = r5, r6
mix2.l r4 = r5, r6
mix4.l r4 = r5, r6
pack2.uss r4 = r5, r6
pack2.sss r4 = r5, r6
pack4.sss r4 = r5, r6
unpack1.h r4 = r5, r6
unpack2.h r4 = r5, r6
unpack4.h r4 = r5, r6
unpack1.l r4 = r5, r6
unpack2.l r4 = r5, r6
unpack4.l r4 = r5, r6
pmin1.u r4 = r5, r6
pmax1.u r4 = r5, r6
pmin2 r4 = r5, r6
pmax2 r4 = r5, r6
psad1 r4 = r5, r6
mux1 r4 = r5, @rev
mux1 r4 = r5, @mix
mux1 r4 = r5, @shuf
mux1 r4 = r5, @alt
mux1 r4 = r5, @brcst
mux2 r4 = r5, 0
mux2 r4 = r5, 0xff
mux2 r4 = r5, 0xaa
pshr2 r4 = r5, r6
pshr2 r4 = r5, 0
pshr2 r4 = r5, 8
pshr2 r4 = r5, 31
pshr4 r4 = r5, r6
pshr4 r4 = r5, 0
pshr4 r4 = r5, 8
pshr4 r4 = r5, 31
pshr2.u r4 = r5, r6
pshr2.u r4 = r5, 0
pshr2.u r4 = r5, 8
pshr2.u r4 = r5, 31
pshr4.u r4 = r5, r6
pshr4.u r4 = r5, 0
pshr4.u r4 = r5, 8
pshr4.u r4 = r5, 31
shr r4 = r5, r6
shr.u r4 = r5, r6
pshl2 r4 = r5, r6
pshl2 r4 = r5, 0
pshl2 r4 = r5, 8
pshl2 r4 = r5, 31
pshl4 r4 = r5, r6
pshl4 r4 = r5, 0
pshl4 r4 = r5, 8
pshl4 r4 = r5, 31
shl r4 = r5, r6
popcnt r4 = r5
shrp r4 = r5, r6, 0
shrp r4 = r5, r6, 12
shrp r4 = r5, r6, 63
extr r4 = r5, 0, 16
extr r4 = r5, 0, 63
extr r4 = r5, 10, 40
extr.u r4 = r5, 0, 16
extr.u r4 = r5, 0, 63
extr.u r4 = r5, 10, 40
dep.z r4 = r5, 0, 16
dep.z r4 = r5, 0, 63
dep.z r4 = r5, 10, 40
dep.z r4 = 0, 0, 16
dep.z r4 = 127, 0, 63
dep.z r4 = -128, 5, 50
dep.z r4 = 0x55, 10, 40
dep r4 = 0, r5, 0, 16
dep r4 = -1, r5, 0, 63
// Insert padding NOPs to force the same template selection as IAS.
nop.m 0
nop.f 0
dep r4 = r5, r6, 10, 7
movl r4 = 0
movl r4 = 0xffffffffffffffff
movl r4 = 0x1234567890abcdef
break.i 0
break.i 0x1fffff
nop.i 0
nop.i 0x1fffff
chk.s.i r4, _start
mov r4 = b0
mov b0 = r4
mov pr = r4, 0
mov pr = r4, 0x1234
mov pr = r4, 0x1ffff
mov pr.rot = 0
// ??? This was originally 0x3ffffff, but that generates an assembler warning
// that the testsuite infrastructure isn't set up to ignore.
mov pr.rot = 0x3ff0000
mov pr.rot = -0x4000000
zxt1 r4 = r5
zxt2 r4 = r5
zxt4 r4 = r5
sxt1 r4 = r5
sxt2 r4 = r5
sxt4 r4 = r5
czx1.l r4 = r5
czx2.l r4 = r5
czx1.r r4 = r5
czx2.r r4 = r5
tbit.z p2, p3 = r4, 0
tbit.z.unc p2, p3 = r4, 1
tbit.z.and p2, p3 = r4, 2
tbit.z.or p2, p3 = r4, 3
tbit.z.or.andcm p2, p3 = r4, 4
tbit.z.orcm p2, p3 = r4, 5
tbit.z.andcm p2, p3 = r4, 6
tbit.z.and.orcm p2, p3 = r4, 7
tbit.nz p2, p3 = r4, 8
tbit.nz.unc p2, p3 = r4, 9
tbit.nz.and p2, p3 = r4, 10
tbit.nz.or p2, p3 = r4, 11
tbit.nz.or.andcm p2, p3 = r4, 12
tbit.nz.orcm p2, p3 = r4, 13
tbit.nz.andcm p2, p3 = r4, 14
tbit.nz.and.orcm p2, p3 = r4, 15
tnat.z p2, p3 = r4
tnat.z.unc p2, p3 = r4
tnat.z.and p2, p3 = r4
tnat.z.or p2, p3 = r4
tnat.z.or.andcm p2, p3 = r4
tnat.z.orcm p2, p3 = r4
tnat.z.andcm p2, p3 = r4
tnat.z.and.orcm p2, p3 = r4
tnat.nz p2, p3 = r4
tnat.nz.unc p2, p3 = r4
tnat.nz.and p2, p3 = r4
tnat.nz.or p2, p3 = r4
tnat.nz.or.andcm p2, p3 = r4
tnat.nz.orcm p2, p3 = r4
tnat.nz.andcm p2, p3 = r4
tnat.nz.and.orcm p2, p3 = r4
mov b3 = r4, .L1
mov.imp b3 = r4, .L1
.space 240
.L1:
mov.sptk b3 = r4, .L2
mov.sptk.imp b3 = r4, .L2
.space 240
.L2:
mov.dptk b3 = r4, .L3
mov.dptk.imp b3 = r4, .L3
.space 240
.L3:
mov.ret b3 = r4, .L4
mov.ret.imp b3 = r4, .L4
.space 240
.L4:
mov.ret.sptk b3 = r4, .L5
mov.ret.sptk.imp b3 = r4, .L5
.space 240
.L5:
mov.ret.dptk b3 = r4, .L6
mov.ret.dptk.imp b3 = r4, .L6
.space 240
.L6:
# instructions added by SDM2.1:
hint @pause
hint.i 0
hint.i @pause
hint.i 0x1fffff
(p7) hint @pause
(p7) hint.i 0
(p7) hint.i @pause
(p7) hint.i 0x1fffff
(p7) hint @pause
(p7) hint.i 0
(p7) hint.i @pause
(p7) hint.i 0x1fffff
# instructions added by SDM2.2:
tf.z p2, p3 = 39
tf.z.unc p2, p3 = 39
tf.z.and p2, p3 = 39
tf.z.or p2, p3 = 39
tf.z.or.andcm p2, p3 = 39
tf.z.orcm p2, p3 = 39
tf.z.andcm p2, p3 = 39
tf.z.and.orcm p2, p3 = 39
tf.nz p2, p3 = 39
tf.nz.unc p2, p3 = 39
tf.nz.and p2, p3 = 39
tf.nz.or p2, p3 = 39
tf.nz.or.andcm p2, p3 = 39
tf.nz.orcm p2, p3 = 39
tf.nz.andcm p2, p3 = 39
tf.nz.and.orcm p2, p3 = 39
(p7) tf.z p2, p3 = 39
(p7) tf.z.unc p2, p3 = 39
(p7) tf.z.and p2, p3 = 39
(p7) tf.z.or p2, p3 = 39
(p7) tf.z.or.andcm p2, p3 = 39
(p7) tf.z.orcm p2, p3 = 39
(p7) tf.z.andcm p2, p3 = 39
(p7) tf.z.and.orcm p2, p3 = 39
(p7) tf.nz p2, p3 = 39
(p7) tf.nz.unc p2, p3 = 39
(p7) tf.nz.and p2, p3 = 39
(p7) tf.nz.or p2, p3 = 39
(p7) tf.nz.or.andcm p2, p3 = 39
(p7) tf.nz.orcm p2, p3 = 39
(p7) tf.nz.andcm p2, p3 = 39
(p7) tf.nz.and.orcm p2, p3 = 39
|
tactcomplabs/xbgas-binutils-gdb
| 29,325
|
gas/testsuite/gas/ia64/psn.s
|
lfetch.count [r2], 1, 64
lfetch.count.d0 [r22], 5, -64
lfetch.count.nt1 [r23], 9, 1024-64
lfetch.count.d1 [r122], 12, -1024
lfetch.count.nt2 [r5], 16, 0x80
lfetch.count.d2 [r15], 20, -0x100
lfetch.count.nta [r125], 24, 512
lfetch.count.d3 [r8], 29, 960
lfetch.count.d4 [r18], 34, -0x400
lfetch.count.d5 [r127], 62, 0x3bf
lfetch.count.d6 [r10], 63, -0x3ff
lfetch.count.d7 [r96], 64, 0
tf.z p1,p2 = 32;;
tf.nz p7,p2 = @clz;;
tf.z.unc p3,p2 = @clz
tf.nz p3,p4 = @mpy
tf.z.and p5,p4 = @datahints
tf.nz.and p5,p6 = 35
tf.nz.andcm p5,p6 = 35
tf.z.or p7,p6 = 63
tf.nz.or p5,p6 = 35
tf.z.or.andcm p7,p6 = @mpy
tf.nz.or.andcm p7,p6 = @datahints
tf.z.and.orcm p7,p6 = @clz
tf.nz.and.orcm p7,p6 = @mpy
{ .mib
tf.nz.unc p6,p0=33
nop.b 0 ;;
}
lfetch.d4 [r18]
{ .mmi
lfetch.fault.excl.d7 [r19] ;;
lfetch.count [r14], 2, 128
sxt4 r8=r10
}
{ .mmi
lfetch.count.d4 [r11], 64, 256;;
lfetch.excl.d5 [r17]
nop.i 0
}
{ .mmi
lfetch.fault.d6 [r16] ;;
mov dahr7=7
clz r3=r9 ;;
}
mov dahr6=6
mpy4 r2=r9,r8
mpyshl4 r2=r9,r8
{ .mmi
mov dahr5=5 ;;
mov dahr4=4
nop.i 0 ;;
}
{ .mib
mov dahr3=3
add r8=r2,r3
nop.b 0 ;;
}
{ .mmi
mov dahr2=2 ;;
mov dahr1=1
nop.i 0 ;;
}
{ .mib
mov dahr0=0
nop.i 0
}
mov r12 = dahr[r5]
mov r122 = dahr[r55]
st1 [ r65 ] = r93
st1.d1 [ r65 ] = r93
st1.nt1 [ r65 ] = r93
st1.d2 [ r65 ] = r93
st1.nt2 [ r65 ] = r93
st1.nta [ r65 ] = r93
st1.d3 [ r65 ] = r93
st1.d4 [ r65 ] = r93
st1.d5 [ r65 ] = r93
st1.d6 [ r65 ] = r93
st1.d7 [ r65 ] = r93
st2 [ r65 ] = r93
st2.d1 [ r65 ] = r93
st2.nt1 [ r65 ] = r93
st2.d2 [ r65 ] = r93
st2.nt2 [ r65 ] = r93
st2.nta [ r65 ] = r93
st2.d3 [ r65 ] = r93
st2.d4 [ r65 ] = r93
st2.d5 [ r65 ] = r93
st2.d6 [ r65 ] = r93
st2.d7 [ r65 ] = r93
st4 [ r65 ] = r93
st4.d1 [ r65 ] = r93
st4.nt1 [ r65 ] = r93
st4.d2 [ r65 ] = r93
st4.nt2 [ r65 ] = r93
st4.nta [ r65 ] = r93
st4.d3 [ r65 ] = r93
st4.d4 [ r65 ] = r93
st4.d5 [ r65 ] = r93
st4.d6 [ r65 ] = r93
st4.d7 [ r65 ] = r93
st8 [ r65 ] = r93
st8.d1 [ r65 ] = r93
st8.nt1 [ r65 ] = r93
st8.d2 [ r65 ] = r93
st8.nt2 [ r65 ] = r93
st8.nta [ r65 ] = r93
st8.d3 [ r65 ] = r93
st8.d4 [ r65 ] = r93
st8.d5 [ r65 ] = r93
st8.d6 [ r65 ] = r93
st8.d7 [ r65 ] = r93
st16 [ r65 ] = r93
st16 [ r65 ] = r93
st16.d1 [ r65 ] = r93
st16.nt1 [ r65 ] = r93
st16.d2 [ r65 ] = r93
st16.nt2 [ r65 ] = r93
st16.nta [ r65 ] = r93
st16.d3 [ r65 ] = r93
st16.d4 [ r65 ] = r93
st16.d5 [ r65 ] = r93
st16.d6 [ r65 ] = r93
st16.d7 [ r65 ] = r93
st16.nta [ r65 ] = r93
st16.d3 [ r65 ] = r93
st16.d4 [ r65 ] = r93
st16.d5 [ r65 ] = r93
st16.d6 [ r65 ] = r93
st16.d7 [ r65 ] = r93
st1.rel [ r65 ] = r93
st1.rel.d1 [ r65 ] = r93
st1.rel.nt1 [ r65 ] = r93
st1.rel.d2 [ r65 ] = r93
st1.rel.nt2 [ r65 ] = r93
st1.rel.nta [ r65 ] = r93
st1.rel.d3 [ r65 ] = r93
st1.rel.d4 [ r65 ] = r93
st1.rel.d5 [ r65 ] = r93
st1.rel.d6 [ r65 ] = r93
st1.rel.d7 [ r65 ] = r93
st2.rel [ r65 ] = r93
st2.rel.d1 [ r65 ] = r93
st2.rel.nt1 [ r65 ] = r93
st2.rel.d2 [ r65 ] = r93
st2.rel.nt2 [ r65 ] = r93
st2.rel.nta [ r65 ] = r93
st2.rel.d3 [ r65 ] = r93
st2.rel.d4 [ r65 ] = r93
st2.rel.d5 [ r65 ] = r93
st2.rel.d6 [ r65 ] = r93
st2.rel.d7 [ r65 ] = r93
st4.rel [ r65 ] = r93
st4.rel.d1 [ r65 ] = r93
st4.rel.nt1 [ r65 ] = r93
st4.rel.d2 [ r65 ] = r93
st4.rel.nt2 [ r65 ] = r93
st4.rel.nta [ r65 ] = r93
st4.rel.d3 [ r65 ] = r93
st4.rel.d4 [ r65 ] = r93
st4.rel.d5 [ r65 ] = r93
st4.rel.d6 [ r65 ] = r93
st4.rel.d7 [ r65 ] = r93
st8.rel [ r65 ] = r93
st8.rel.d1 [ r65 ] = r93
st8.rel.nt1 [ r65 ] = r93
st8.rel.d2 [ r65 ] = r93
st8.rel.nt2 [ r65 ] = r93
st8.rel.nta [ r65 ] = r93
st8.rel.d3 [ r65 ] = r93
st8.rel.d4 [ r65 ] = r93
st8.rel.d5 [ r65 ] = r93
st8.rel.d6 [ r65 ] = r93
st8.rel.d7 [ r65 ] = r93
st16.rel [ r65 ] = r93
st16.rel [ r65 ] = r93, ar.csd
st16.rel.d1 [ r65 ] = r93
st16.rel.d1 [ r65 ] = r93, ar.csd
st16.rel.nt1 [ r65 ] = r93
st16.rel.nt1 [ r65 ] = r93, ar.csd
st16.rel.d2 [ r65 ] = r93
st16.rel.d2 [ r65 ] = r93, ar.csd
st16.rel.nt2 [ r65 ] = r93
st16.rel.nt2 [ r65 ] = r93, ar.csd
st16.rel.nta [ r65 ] = r93
st16.rel.d3 [ r65 ] = r93
st16.rel.d4 [ r65 ] = r93
st16.rel.d5 [ r65 ] = r93
st16.rel.d6 [ r65 ] = r93
st16.rel.d7 [ r65 ] = r93
st16.rel.nta [ r65 ] = r93, ar.csd
st16.rel.d3 [ r65 ] = r93, ar.csd
st16.rel.d4 [ r65 ] = r93, ar.csd
st16.rel.d5 [ r65 ] = r93, ar.csd
st16.rel.d6 [ r65 ] = r93, ar.csd
st16.rel.d7 [ r65 ] = r93, ar.csd
st8.spill [ r65 ] = r93
st8.spill.d1 [ r65 ] = r93
st8.spill.nt1 [ r65 ] = r93
st8.spill.d2 [ r65 ] = r93
st8.spill.nt2 [ r65 ] = r93
st8.spill.nta [ r65 ] = r93
st8.spill.d3 [ r65 ] = r93
st8.spill.d4 [ r65 ] = r93
st8.spill.d5 [ r65 ] = r93
st8.spill.d6 [ r65 ] = r93
st8.spill.d7 [ r65 ] = r93
lfetch [ r60 ]
lfetch.d1 [ r60 ]
lfetch.nt1 [ r60 ]
lfetch.d2 [ r60 ]
lfetch.nt2 [ r60 ]
lfetch.nta [ r60 ]
lfetch.d3 [ r60 ]
lfetch.d4 [ r60 ]
lfetch.d5 [ r60 ]
lfetch.d6 [ r60 ]
lfetch.d7 [ r60 ]
stfs [ r60 ] = f90
stfs.d1 [ r60 ] = f90
stfs.nt1 [ r60 ] = f90
stfs.d2 [ r60 ] = f90
stfs.nt2 [ r60 ] = f90
stfs.nta [ r60 ] = f90
stfs.d3 [ r60 ] = f90
stfs.d4 [ r60 ] = f90
stfs.d5 [ r60 ] = f90
stfs.d6 [ r60 ] = f90
stfs.d7 [ r60 ] = f90
stfd [ r60 ] = f90
stfd.d1 [ r60 ] = f90
stfd.nt1 [ r60 ] = f90
stfd.d2 [ r60 ] = f90
stfd.nt2 [ r60 ] = f90
stfd.nta [ r60 ] = f90
stfd.d3 [ r60 ] = f90
stfd.d4 [ r60 ] = f90
stfd.d5 [ r60 ] = f90
stfd.d6 [ r60 ] = f90
stfd.d7 [ r60 ] = f90
stf8 [ r60 ] = f90
stf8.d1 [ r60 ] = f90
stf8.nt1 [ r60 ] = f90
stf8.d2 [ r60 ] = f90
stf8.nt2 [ r60 ] = f90
stf8.nta [ r60 ] = f90
stf8.d3 [ r60 ] = f90
stf8.d4 [ r60 ] = f90
stf8.d5 [ r60 ] = f90
stf8.d6 [ r60 ] = f90
stf8.d7 [ r60 ] = f90
stfe [ r60 ] = f90
stfe.d1 [ r60 ] = f90
stfe.nt1 [ r60 ] = f90
stfe.d2 [ r60 ] = f90
stfe.nt2 [ r60 ] = f90
stfe.nta [ r60 ] = f90
stfe.d3 [ r60 ] = f90
stfe.d4 [ r60 ] = f90
stfe.d5 [ r60 ] = f90
stfe.d6 [ r60 ] = f90
stfe.d7 [ r60 ] = f90
stf.spill [ r60 ] = f90
stf.spill.d1 [ r60 ] = f90
stf.spill.nt1 [ r60 ] = f90
stf.spill.d2 [ r60 ] = f90
stf.spill.nt2 [ r60 ] = f90
stf.spill.nta [ r60 ] = f90
stf.spill.d3 [ r60 ] = f90
stf.spill.d4 [ r60 ] = f90
stf.spill.d5 [ r60 ] = f90
stf.spill.d6 [ r60 ] = f90
stf.spill.d7 [ r60 ] = f90
/* Floating-point load. */
ldfs f121 = [ r125 ]
ldfs.nt1 f121 = [ r125 ]
ldfs.d1 f121 = [ r125 ]
ldfs.d2 f121 = [ r125 ]
ldfs.nt2 f121 = [ r125 ]
ldfs.nta f121 = [ r125 ]
ldfs.d3 f121 = [ r125 ]
ldfs.d4 f121 = [ r125 ]
ldfs.d5 f121 = [ r125 ]
ldfs.d6 f121 = [ r125 ]
ldfs.d7 f121 = [ r125 ]
ldfd f121 = [ r125 ]
ldfd.nt1 f121 = [ r125 ]
ldfd.d1 f121 = [ r125 ]
ldfd.d2 f121 = [ r125 ]
ldfd.nt2 f121 = [ r125 ]
ldfd.nta f121 = [ r125 ]
ldfd.d3 f121 = [ r125 ]
ldfd.d4 f121 = [ r125 ]
ldfd.d5 f121 = [ r125 ]
ldfd.d6 f121 = [ r125 ]
ldfd.d7 f121 = [ r125 ]
ldf8 f121 = [ r125 ]
ldf8.nt1 f121 = [ r125 ]
ldf8.d1 f121 = [ r125 ]
ldf8.d2 f121 = [ r125 ]
ldf8.nt2 f121 = [ r125 ]
ldf8.nta f121 = [ r125 ]
ldf8.d3 f121 = [ r125 ]
ldf8.d4 f121 = [ r125 ]
ldf8.d5 f121 = [ r125 ]
ldf8.d6 f121 = [ r125 ]
ldf8.d7 f121 = [ r125 ]
ldfe f121 = [ r125 ]
ldfe.nt1 f121 = [ r125 ]
ldfe.d1 f121 = [ r125 ]
ldfe.d2 f121 = [ r125 ]
ldfe.nt2 f121 = [ r125 ]
ldfe.nta f121 = [ r125 ]
ldfe.d3 f121 = [ r125 ]
ldfe.d4 f121 = [ r125 ]
ldfe.d5 f121 = [ r125 ]
ldfe.d6 f121 = [ r125 ]
ldfe.d7 f121 = [ r125 ]
ldfs.s f121 = [ r125 ]
ldfs.s.nt1 f121 = [ r125 ]
ldfs.s.d1 f121 = [ r125 ]
ldfs.s.d2 f121 = [ r125 ]
ldfs.s.nt2 f121 = [ r125 ]
ldfs.s.nta f121 = [ r125 ]
ldfs.s.d3 f121 = [ r125 ]
ldfs.s.d4 f121 = [ r125 ]
ldfs.s.d5 f121 = [ r125 ]
ldfs.s.d6 f121 = [ r125 ]
ldfs.s.d7 f121 = [ r125 ]
ldfd.s f121 = [ r125 ]
ldfd.s.nt1 f121 = [ r125 ]
ldfd.s.d1 f121 = [ r125 ]
ldfd.s.d2 f121 = [ r125 ]
ldfd.s.nt2 f121 = [ r125 ]
ldfd.s.nta f121 = [ r125 ]
ldfd.s.d3 f121 = [ r125 ]
ldfd.s.d4 f121 = [ r125 ]
ldfd.s.d5 f121 = [ r125 ]
ldfd.s.d6 f121 = [ r125 ]
ldfd.s.d7 f121 = [ r125 ]
ldf8.s f121 = [ r125 ]
ldf8.s.nt1 f121 = [ r125 ]
ldf8.s.d1 f121 = [ r125 ]
ldf8.s.d2 f121 = [ r125 ]
ldf8.s.nt2 f121 = [ r125 ]
ldf8.s.nta f121 = [ r125 ]
ldf8.s.d3 f121 = [ r125 ]
ldf8.s.d4 f121 = [ r125 ]
ldf8.s.d5 f121 = [ r125 ]
ldf8.s.d6 f121 = [ r125 ]
ldf8.s.d7 f121 = [ r125 ]
ldfe.s f121 = [ r125 ]
ldfe.s.nt1 f121 = [ r125 ]
ldfe.s.d1 f121 = [ r125 ]
ldfe.s.d2 f121 = [ r125 ]
ldfe.s.nt2 f121 = [ r125 ]
ldfe.s.nta f121 = [ r125 ]
ldfe.s.d3 f121 = [ r125 ]
ldfe.s.d4 f121 = [ r125 ]
ldfe.s.d5 f121 = [ r125 ]
ldfe.s.d6 f121 = [ r125 ]
ldfe.s.d7 f121 = [ r125 ]
ldfs.a f121 = [ r125 ]
ldfs.a.nt1 f121 = [ r125 ]
ldfs.a.d1 f121 = [ r125 ]
ldfs.a.d2 f121 = [ r125 ]
ldfs.a.nt2 f121 = [ r125 ]
ldfs.a.nta f121 = [ r125 ]
ldfs.a.d3 f121 = [ r125 ]
ldfs.a.d4 f121 = [ r125 ]
ldfs.a.d5 f121 = [ r125 ]
ldfs.a.d6 f121 = [ r125 ]
ldfs.a.d7 f121 = [ r125 ]
ldfd.a f121 = [ r125 ]
ldfd.a.nt1 f121 = [ r125 ]
ldfd.a.d1 f121 = [ r125 ]
ldfd.a.d2 f121 = [ r125 ]
ldfd.a.nt2 f121 = [ r125 ]
ldfd.a.nta f121 = [ r125 ]
ldfd.a.d3 f121 = [ r125 ]
ldfd.a.d4 f121 = [ r125 ]
ldfd.a.d5 f121 = [ r125 ]
ldfd.a.d6 f121 = [ r125 ]
ldfd.a.d7 f121 = [ r125 ]
ldf8.a f121 = [ r125 ]
ldf8.a.nt1 f121 = [ r125 ]
ldf8.a.d1 f121 = [ r125 ]
ldf8.a.d2 f121 = [ r125 ]
ldf8.a.nt2 f121 = [ r125 ]
ldf8.a.nta f121 = [ r125 ]
ldf8.a.d3 f121 = [ r125 ]
ldf8.a.d4 f121 = [ r125 ]
ldf8.a.d5 f121 = [ r125 ]
ldf8.a.d6 f121 = [ r125 ]
ldf8.a.d7 f121 = [ r125 ]
ldfe.a f121 = [ r125 ]
ldfe.a.nt1 f121 = [ r125 ]
ldfe.a.d1 f121 = [ r125 ]
ldfe.a.d2 f121 = [ r125 ]
ldfe.a.nt2 f121 = [ r125 ]
ldfe.a.nta f121 = [ r125 ]
ldfe.a.d3 f121 = [ r125 ]
ldfe.a.d4 f121 = [ r125 ]
ldfe.a.d5 f121 = [ r125 ]
ldfe.a.d6 f121 = [ r125 ]
ldfe.a.d7 f121 = [ r125 ]
ldfs.sa f121 = [ r125 ]
ldfs.sa.nt1 f121 = [ r125 ]
ldfs.sa.d1 f121 = [ r125 ]
ldfs.sa.d2 f121 = [ r125 ]
ldfs.sa.nt2 f121 = [ r125 ]
ldfs.sa.nta f121 = [ r125 ]
ldfs.sa.d3 f121 = [ r125 ]
ldfs.sa.d4 f121 = [ r125 ]
ldfs.sa.d5 f121 = [ r125 ]
ldfs.sa.d6 f121 = [ r125 ]
ldfs.sa.d7 f121 = [ r125 ]
ldfd.sa f121 = [ r125 ]
ldfd.sa.nt1 f121 = [ r125 ]
ldfd.sa.d1 f121 = [ r125 ]
ldfd.sa.d2 f121 = [ r125 ]
ldfd.sa.nt2 f121 = [ r125 ]
ldfd.sa.nta f121 = [ r125 ]
ldfd.sa.d3 f121 = [ r125 ]
ldfd.sa.d4 f121 = [ r125 ]
ldfd.sa.d5 f121 = [ r125 ]
ldfd.sa.d6 f121 = [ r125 ]
ldfd.sa.d7 f121 = [ r125 ]
ldf8.sa f121 = [ r125 ]
ldf8.sa.nt1 f121 = [ r125 ]
ldf8.sa.d1 f121 = [ r125 ]
ldf8.sa.d2 f121 = [ r125 ]
ldf8.sa.nt2 f121 = [ r125 ]
ldf8.sa.nta f121 = [ r125 ]
ldf8.sa.d3 f121 = [ r125 ]
ldf8.sa.d4 f121 = [ r125 ]
ldf8.sa.d5 f121 = [ r125 ]
ldf8.sa.d6 f121 = [ r125 ]
ldf8.sa.d7 f121 = [ r125 ]
ldfe.sa f121 = [ r125 ]
ldfe.sa.nt1 f121 = [ r125 ]
ldfe.sa.d1 f121 = [ r125 ]
ldfe.sa.d2 f121 = [ r125 ]
ldfe.sa.nt2 f121 = [ r125 ]
ldfe.sa.nta f121 = [ r125 ]
ldfe.sa.d3 f121 = [ r125 ]
ldfe.sa.d4 f121 = [ r125 ]
ldfe.sa.d5 f121 = [ r125 ]
ldfe.sa.d6 f121 = [ r125 ]
ldfe.sa.d7 f121 = [ r125 ]
ldf.fill f121 = [ r125 ]
ldf.fill.nt1 f121 = [ r125 ]
ldf.fill.d1 f121 = [ r125 ]
ldf.fill.d2 f121 = [ r125 ]
ldf.fill.nt2 f121 = [ r125 ]
ldf.fill.nta f121 = [ r125 ]
ldf.fill.d3 f121 = [ r125 ]
ldf.fill.d4 f121 = [ r125 ]
ldf.fill.d5 f121 = [ r125 ]
ldf.fill.d6 f121 = [ r125 ]
ldf.fill.d7 f121 = [ r125 ]
ldfs.c.clr f121 = [ r125 ]
ldfs.c.clr.nt1 f121 = [ r125 ]
ldfs.c.clr.d1 f121 = [ r125 ]
ldfs.c.clr.d2 f121 = [ r125 ]
ldfs.c.clr.nt2 f121 = [ r125 ]
ldfs.c.clr.nta f121 = [ r125 ]
ldfs.c.clr.d3 f121 = [ r125 ]
ldfs.c.clr.d4 f121 = [ r125 ]
ldfs.c.clr.d5 f121 = [ r125 ]
ldfs.c.clr.d6 f121 = [ r125 ]
ldfs.c.clr.d7 f121 = [ r125 ]
ldfd.c.clr f121 = [ r125 ]
ldfd.c.clr.nt1 f121 = [ r125 ]
ldfd.c.clr.d1 f121 = [ r125 ]
ldfd.c.clr.d2 f121 = [ r125 ]
ldfd.c.clr.nt2 f121 = [ r125 ]
ldfd.c.clr.nta f121 = [ r125 ]
ldfd.c.clr.d3 f121 = [ r125 ]
ldfd.c.clr.d4 f121 = [ r125 ]
ldfd.c.clr.d5 f121 = [ r125 ]
ldfd.c.clr.d6 f121 = [ r125 ]
ldfd.c.clr.d7 f121 = [ r125 ]
ldf8.c.clr f121 = [ r125 ]
ldf8.c.clr.nt1 f121 = [ r125 ]
ldf8.c.clr.d1 f121 = [ r125 ]
ldf8.c.clr.d2 f121 = [ r125 ]
ldf8.c.clr.nt2 f121 = [ r125 ]
ldf8.c.clr.nta f121 = [ r125 ]
ldf8.c.clr.d3 f121 = [ r125 ]
ldf8.c.clr.d4 f121 = [ r125 ]
ldf8.c.clr.d5 f121 = [ r125 ]
ldf8.c.clr.d6 f121 = [ r125 ]
ldf8.c.clr.d7 f121 = [ r125 ]
ldfe.c.clr f121 = [ r125 ]
ldfe.c.clr.nt1 f121 = [ r125 ]
ldfe.c.clr.d1 f121 = [ r125 ]
ldfe.c.clr.d2 f121 = [ r125 ]
ldfe.c.clr.nt2 f121 = [ r125 ]
ldfe.c.clr.nta f121 = [ r125 ]
ldfe.c.clr.d3 f121 = [ r125 ]
ldfe.c.clr.d4 f121 = [ r125 ]
ldfe.c.clr.d5 f121 = [ r125 ]
ldfe.c.clr.d6 f121 = [ r125 ]
ldfe.c.clr.d7 f121 = [ r125 ]
ldfs.c.nc f121 = [ r125 ]
ldfs.c.nc.nt1 f121 = [ r125 ]
ldfs.c.nc.d1 f121 = [ r125 ]
ldfs.c.nc.d2 f121 = [ r125 ]
ldfs.c.nc.nt2 f121 = [ r125 ]
ldfs.c.nc.nta f121 = [ r125 ]
ldfs.c.nc.d3 f121 = [ r125 ]
ldfs.c.nc.d4 f121 = [ r125 ]
ldfs.c.nc.d5 f121 = [ r125 ]
ldfs.c.nc.d6 f121 = [ r125 ]
ldfs.c.nc.d7 f121 = [ r125 ]
ldfd.c.nc f121 = [ r125 ]
ldfd.c.nc.nt1 f121 = [ r125 ]
ldfd.c.nc.d1 f121 = [ r125 ]
ldfd.c.nc.d2 f121 = [ r125 ]
ldfd.c.nc.nt2 f121 = [ r125 ]
ldfd.c.nc.nta f121 = [ r125 ]
ldfd.c.nc.d3 f121 = [ r125 ]
ldfd.c.nc.d4 f121 = [ r125 ]
ldfd.c.nc.d5 f121 = [ r125 ]
ldfd.c.nc.d6 f121 = [ r125 ]
ldfd.c.nc.d7 f121 = [ r125 ]
ldf8.c.nc f121 = [ r125 ]
ldf8.c.nc.nt1 f121 = [ r125 ]
ldf8.c.nc.d1 f121 = [ r125 ]
ldf8.c.nc.d2 f121 = [ r125 ]
ldf8.c.nc.nt2 f121 = [ r125 ]
ldf8.c.nc.nta f121 = [ r125 ]
ldf8.c.nc.d3 f121 = [ r125 ]
ldf8.c.nc.d4 f121 = [ r125 ]
ldf8.c.nc.d5 f121 = [ r125 ]
ldf8.c.nc.d6 f121 = [ r125 ]
ldf8.c.nc.d7 f121 = [ r125 ]
ldfe.c.nc f121 = [ r125 ]
ldfe.c.nc.nt1 f121 = [ r125 ]
ldfe.c.nc.d1 f121 = [ r125 ]
ldfe.c.nc.d2 f121 = [ r125 ]
ldfe.c.nc.nt2 f121 = [ r125 ]
ldfe.c.nc.nta f121 = [ r125 ]
ldfe.c.nc.d3 f121 = [ r125 ]
ldfe.c.nc.d4 f121 = [ r125 ]
ldfe.c.nc.d5 f121 = [ r125 ]
ldfe.c.nc.d6 f121 = [ r125 ]
ldfe.c.nc.d7 f121 = [ r125 ]
ld1 r120 = [ r20 ]
ld1.nt1 r120 = [ r20 ]
ld1.d1 r120 = [ r20 ]
ld1.d2 r120 = [ r20 ]
ld1.nt2 r120 = [ r20 ]
ld1.nta r120 = [ r20 ]
ld1.d3 r120 = [ r20 ]
ld1.d4 r120 = [ r20 ]
ld1.d5 r120 = [ r20 ]
ld1.d6 r120 = [ r20 ]
ld1.d7 r120 = [ r20 ]
ld2 r120 = [ r20 ]
ld2.nt1 r120 = [ r20 ]
ld2.d1 r120 = [ r20 ]
ld2.d2 r120 = [ r20 ]
ld2.nt2 r120 = [ r20 ]
ld2.nta r120 = [ r20 ]
ld2.d3 r120 = [ r20 ]
ld2.d4 r120 = [ r20 ]
ld2.d5 r120 = [ r20 ]
ld2.d6 r120 = [ r20 ]
ld2.d7 r120 = [ r20 ]
ld4 r120 = [ r20 ]
ld4.nt1 r120 = [ r20 ]
ld4.d1 r120 = [ r20 ]
ld4.d2 r120 = [ r20 ]
ld4.nt2 r120 = [ r20 ]
ld4.nta r120 = [ r20 ]
ld4.d3 r120 = [ r20 ]
ld4.d4 r120 = [ r20 ]
ld4.d5 r120 = [ r20 ]
ld4.d6 r120 = [ r20 ]
ld4.d7 r120 = [ r20 ]
ld8 r120 = [ r20 ]
ld8.nt1 r120 = [ r20 ]
ld8.d1 r120 = [ r20 ]
ld8.d2 r120 = [ r20 ]
ld8.nt2 r120 = [ r20 ]
ld8.nta r120 = [ r20 ]
ld8.d3 r120 = [ r20 ]
ld8.d4 r120 = [ r20 ]
ld8.d5 r120 = [ r20 ]
ld8.d6 r120 = [ r20 ]
ld8.d7 r120 = [ r20 ]
ld1.s r120 = [ r20 ]
ld1.s.nt1 r120 = [ r20 ]
ld1.s.d1 r120 = [ r20 ]
ld1.s.d2 r120 = [ r20 ]
ld1.s.nt2 r120 = [ r20 ]
ld1.s.nta r120 = [ r20 ]
ld1.s.d3 r120 = [ r20 ]
ld1.s.d4 r120 = [ r20 ]
ld1.s.d5 r120 = [ r20 ]
ld1.s.d6 r120 = [ r20 ]
ld1.s.d7 r120 = [ r20 ]
ld2.s r120 = [ r20 ]
ld2.s.nt1 r120 = [ r20 ]
ld2.s.d1 r120 = [ r20 ]
ld2.s.d2 r120 = [ r20 ]
ld2.s.nt2 r120 = [ r20 ]
ld2.s.nta r120 = [ r20 ]
ld2.s.d3 r120 = [ r20 ]
ld2.s.d4 r120 = [ r20 ]
ld2.s.d5 r120 = [ r20 ]
ld2.s.d6 r120 = [ r20 ]
ld2.s.d7 r120 = [ r20 ]
ld4.s r120 = [ r20 ]
ld4.s.nt1 r120 = [ r20 ]
ld4.s.d1 r120 = [ r20 ]
ld4.s.d2 r120 = [ r20 ]
ld4.s.nt2 r120 = [ r20 ]
ld4.s.nta r120 = [ r20 ]
ld4.s.d3 r120 = [ r20 ]
ld4.s.d4 r120 = [ r20 ]
ld4.s.d5 r120 = [ r20 ]
ld4.s.d6 r120 = [ r20 ]
ld4.s.d7 r120 = [ r20 ]
ld8.s r120 = [ r20 ]
ld8.s.nt1 r120 = [ r20 ]
ld8.s.d1 r120 = [ r20 ]
ld8.s.d2 r120 = [ r20 ]
ld8.s.nt2 r120 = [ r20 ]
ld8.s.nta r120 = [ r20 ]
ld8.s.d3 r120 = [ r20 ]
ld8.s.d4 r120 = [ r20 ]
ld8.s.d5 r120 = [ r20 ]
ld8.s.d6 r120 = [ r20 ]
ld8.s.d7 r120 = [ r20 ]
ld1.a r120 = [ r20 ]
ld1.a.nt1 r120 = [ r20 ]
ld1.a.d1 r120 = [ r20 ]
ld1.a.d2 r120 = [ r20 ]
ld1.a.nt2 r120 = [ r20 ]
ld1.a.nta r120 = [ r20 ]
ld1.a.d3 r120 = [ r20 ]
ld1.a.d4 r120 = [ r20 ]
ld1.a.d5 r120 = [ r20 ]
ld1.a.d6 r120 = [ r20 ]
ld1.a.d7 r120 = [ r20 ]
ld2.a r120 = [ r20 ]
ld2.a.nt1 r120 = [ r20 ]
ld2.a.d1 r120 = [ r20 ]
ld2.a.nt2 r120 = [ r20 ]
ld2.a.nta r120 = [ r20 ]
ld2.a.d3 r120 = [ r20 ]
ld2.a.d4 r120 = [ r20 ]
ld2.a.d5 r120 = [ r20 ]
ld2.a.d6 r120 = [ r20 ]
ld2.a.d7 r120 = [ r20 ]
ld4.a r120 = [ r20 ]
ld4.a.nt1 r120 = [ r20 ]
ld4.a.d1 r120 = [ r20 ]
ld4.a.d2 r120 = [ r20 ]
ld4.a.nt2 r120 = [ r20 ]
ld4.a.nta r120 = [ r20 ]
ld4.a.d3 r120 = [ r20 ]
ld4.a.d4 r120 = [ r20 ]
ld4.a.d5 r120 = [ r20 ]
ld4.a.d6 r120 = [ r20 ]
ld4.a.d7 r120 = [ r20 ]
ld8.a r120 = [ r20 ]
ld8.a.nt1 r120 = [ r20 ]
ld8.a.d1 r120 = [ r20 ]
ld8.a.d2 r120 = [ r20 ]
ld8.a.nt2 r120 = [ r20 ]
ld8.a.nta r120 = [ r20 ]
ld8.a.d3 r120 = [ r20 ]
ld8.a.d5 r120 = [ r20 ]
ld8.a.d6 r120 = [ r20 ]
ld8.a.d7 r120 = [ r20 ]
ld1.sa r120 = [ r20 ]
ld1.sa.nt1 r120 = [ r20 ]
ld1.sa.d1 r120 = [ r20 ]
ld1.sa.d2 r120 = [ r20 ]
ld1.sa.nt2 r120 = [ r20 ]
ld1.sa.nta r120 = [ r20 ]
ld1.sa.d3 r120 = [ r20 ]
ld1.sa.d4 r120 = [ r20 ]
ld1.sa.d5 r120 = [ r20 ]
ld1.sa.d6 r120 = [ r20 ]
ld1.sa.d7 r120 = [ r20 ]
ld2.sa r120 = [ r20 ]
ld2.sa.nt1 r120 = [ r20 ]
ld2.sa.d1 r120 = [ r20 ]
ld2.sa.d2 r120 = [ r20 ]
ld2.sa.nt2 r120 = [ r20 ]
ld2.sa.nta r120 = [ r20 ]
ld2.sa.d3 r120 = [ r20 ]
ld2.sa.d4 r120 = [ r20 ]
ld2.sa.d5 r120 = [ r20 ]
ld2.sa.d6 r120 = [ r20 ]
ld2.sa.d7 r120 = [ r20 ]
ld4.sa.nt1 r120 = [ r20 ]
ld4.sa.d1 r120 = [ r20 ]
ld4.sa.d2 r120 = [ r20 ]
ld4.sa.nt2 r120 = [ r20 ]
ld4.sa.nta r120 = [ r20 ]
ld4.sa.d3 r120 = [ r20 ]
ld4.sa.d4 r120 = [ r20 ]
ld4.sa.d5 r120 = [ r20 ]
ld4.sa.d6 r120 = [ r20 ]
ld4.sa.d7 r120 = [ r20 ]
ld8.sa r120 = [ r20 ]
ld8.sa.nt1 r120 = [ r20 ]
ld8.sa.d1 r120 = [ r20 ]
ld8.sa.d2 r120 = [ r20 ]
ld8.sa.nt2 r120 = [ r20 ]
ld8.sa.nta r120 = [ r20 ]
ld8.sa.d3 r120 = [ r20 ]
ld8.sa.d4 r120 = [ r20 ]
ld8.sa.d5 r120 = [ r20 ]
ld8.sa.d6 r120 = [ r20 ]
ld8.sa.d7 r120 = [ r20 ]
ld1.bias r120 = [ r20 ]
ld1.bias.nt1 r120 = [ r20 ]
ld1.bias.d1 r120 = [ r20 ]
ld1.bias.d2 r120 = [ r20 ]
ld1.bias.nt2 r120 = [ r20 ]
ld1.bias.nta r120 = [ r20 ]
ld1.bias.d3 r120 = [ r20 ]
ld1.bias.d4 r120 = [ r20 ]
ld1.bias.d5 r120 = [ r20 ]
ld1.bias.d6 r120 = [ r20 ]
ld1.bias.d7 r120 = [ r20 ]
ld2.bias r120 = [ r20 ]
ld2.bias.nt1 r120 = [ r20 ]
ld2.bias.d1 r120 = [ r20 ]
ld2.bias.d2 r120 = [ r20 ]
ld2.bias.nt2 r120 = [ r20 ]
ld2.bias.nta r120 = [ r20 ]
ld2.bias.d3 r120 = [ r20 ]
ld2.bias.d4 r120 = [ r20 ]
ld2.bias.d5 r120 = [ r20 ]
ld2.bias.d6 r120 = [ r20 ]
ld2.bias.d7 r120 = [ r20 ]
ld4.bias r120 = [ r20 ]
ld4.bias.nt1 r120 = [ r20 ]
ld4.bias.d1 r120 = [ r20 ]
ld4.bias.d2 r120 = [ r20 ]
ld4.bias.nt2 r120 = [ r20 ]
ld4.bias.nta r120 = [ r20 ]
ld4.bias.d3 r120 = [ r20 ]
ld4.bias.d4 r120 = [ r20 ]
ld4.bias.d5 r120 = [ r20 ]
ld4.bias.d6 r120 = [ r20 ]
ld4.bias.d7 r120 = [ r20 ]
ld8.bias r120 = [ r20 ]
ld8.bias.nt1 r120 = [ r20 ]
ld8.bias.d1 r120 = [ r20 ]
ld8.bias.d2 r120 = [ r20 ]
ld8.bias.nt2 r120 = [ r20 ]
ld8.bias.nta r120 = [ r20 ]
ld8.bias.d3 r120 = [ r20 ]
ld8.bias.d4 r120 = [ r20 ]
ld8.bias.d5 r120 = [ r20 ]
ld8.bias.d6 r120 = [ r20 ]
ld8.bias.d7 r120 = [ r20 ]
ld1.acq r120 = [ r20 ]
ld1.acq.nt1 r120 = [ r20 ]
ld1.acq.d1 r120 = [ r20 ]
ld1.acq.d2 r120 = [ r20 ]
ld1.acq.nt2 r120 = [ r20 ]
ld1.acq.nta r120 = [ r20 ]
ld1.acq.d3 r120 = [ r20 ]
ld1.acq.d4 r120 = [ r20 ]
ld1.acq.d5 r120 = [ r20 ]
ld1.acq.d6 r120 = [ r20 ]
ld2.acq r120 = [ r20 ]
ld2.acq.nt1 r120 = [ r20 ]
ld2.acq.d1 r120 = [ r20 ]
ld2.acq.d2 r120 = [ r20 ]
ld2.acq.nt2 r120 = [ r20 ]
ld2.acq.nta r120 = [ r20 ]
ld2.acq.d3 r120 = [ r20 ]
ld2.acq.d4 r120 = [ r20 ]
ld2.acq.d5 r120 = [ r20 ]
ld2.acq.d6 r120 = [ r20 ]
ld2.acq.d7 r120 = [ r20 ]
ld4.acq r120 = [ r20 ]
ld4.acq.nt1 r120 = [ r20 ]
ld4.acq.d1 r120 = [ r20 ]
ld4.acq.d2 r120 = [ r20 ]
ld4.acq.nt2 r120 = [ r20 ]
ld4.acq.nta r120 = [ r20 ]
ld4.acq.d3 r120 = [ r20 ]
ld4.acq.d4 r120 = [ r20 ]
ld4.acq.d5 r120 = [ r20 ]
ld4.acq.d6 r120 = [ r20 ]
ld4.acq.d7 r120 = [ r20 ]
ld8.acq r120 = [ r20 ]
ld8.acq.nt1 r120 = [ r20 ]
ld8.acq.d1 r120 = [ r20 ]
ld8.acq.d2 r120 = [ r20 ]
ld8.acq.nt2 r120 = [ r20 ]
ld8.acq.nta r120 = [ r20 ]
ld8.acq.d3 r120 = [ r20 ]
ld8.acq.d4 r120 = [ r20 ]
ld8.acq.d5 r120 = [ r20 ]
ld8.acq.d6 r120 = [ r20 ]
ld8.acq.d7 r120 = [ r20 ]
ld8.fill r120 = [ r20 ]
ld8.fill.nt1 r120 = [ r20 ]
ld8.fill.d1 r120 = [ r20 ]
ld8.fill.d2 r120 = [ r20 ]
ld8.fill.nt2 r120 = [ r20 ]
ld8.fill.nta r120 = [ r20 ]
ld8.fill.d3 r120 = [ r20 ]
ld8.fill.d4 r120 = [ r20 ]
ld8.fill.d5 r120 = [ r20 ]
ld8.fill.d6 r120 = [ r20 ]
ld8.fill.d7 r120 = [ r20 ]
ld1.c.clr r120 = [ r20 ]
ld1.c.clr.nt1 r120 = [ r20 ]
ld1.c.clr.d1 r120 = [ r20 ]
ld1.c.clr.d2 r120 = [ r20 ]
ld1.c.clr.nt2 r120 = [ r20 ]
ld1.c.clr.nta r120 = [ r20 ]
ld1.c.clr.d3 r120 = [ r20 ]
ld1.c.clr.d4 r120 = [ r20 ]
ld1.c.clr.d5 r120 = [ r20 ]
ld1.c.clr.d6 r120 = [ r20 ]
ld1.c.clr.d7 r120 = [ r20 ]
ld2.c.clr r120 = [ r20 ]
ld2.c.clr.nt1 r120 = [ r20 ]
ld2.c.clr.d1 r120 = [ r20 ]
ld2.c.clr.d2 r120 = [ r20 ]
ld2.c.clr.nt2 r120 = [ r20 ]
ld2.c.clr.nta r120 = [ r20 ]
ld2.c.clr.d3 r120 = [ r20 ]
ld2.c.clr.d4 r120 = [ r20 ]
ld2.c.clr.d5 r120 = [ r20 ]
ld2.c.clr.d6 r120 = [ r20 ]
ld2.c.clr.d7 r120 = [ r20 ]
ld4.c.clr r120 = [ r20 ]
ld4.c.clr.nt1 r120 = [ r20 ]
ld4.c.clr.d1 r120 = [ r20 ]
ld4.c.clr.d2 r120 = [ r20 ]
ld4.c.clr.nt2 r120 = [ r20 ]
ld4.c.clr.nta r120 = [ r20 ]
ld4.c.clr.d3 r120 = [ r20 ]
ld4.c.clr.d4 r120 = [ r20 ]
ld4.c.clr.d5 r120 = [ r20 ]
ld4.c.clr.d6 r120 = [ r20 ]
ld4.c.clr.d7 r120 = [ r20 ]
ld8.c.clr r120 = [ r20 ]
ld8.c.clr.nt1 r120 = [ r20 ]
ld8.c.clr.d1 r120 = [ r20 ]
ld8.c.clr.d2 r120 = [ r20 ]
ld8.c.clr.nt2 r120 = [ r20 ]
ld8.c.clr.nta r120 = [ r20 ]
ld8.c.clr.d3 r120 = [ r20 ]
ld8.c.clr.d4 r120 = [ r20 ]
ld8.c.clr.d5 r120 = [ r20 ]
ld8.c.clr.d6 r120 = [ r20 ]
ld8.c.clr.d7 r120 = [ r20 ]
ld1.c.nc r120 = [ r20 ]
ld1.c.nc.nt1 r120 = [ r20 ]
ld1.c.nc.d1 r120 = [ r20 ]
ld1.c.nc.d2 r120 = [ r20 ]
ld1.c.nc.nt2 r120 = [ r20 ]
ld1.c.nc.nta r120 = [ r20 ]
ld1.c.nc.d3 r120 = [ r20 ]
ld1.c.nc.d4 r120 = [ r20 ]
ld1.c.nc.d5 r120 = [ r20 ]
ld1.c.nc.d7 r120 = [ r20 ]
ld2.c.nc r120 = [ r20 ]
ld2.c.nc.nt1 r120 = [ r20 ]
ld2.c.nc.d1 r120 = [ r20 ]
ld2.c.nc.d2 r120 = [ r20 ]
ld2.c.nc.nt2 r120 = [ r20 ]
ld2.c.nc.nta r120 = [ r20 ]
ld2.c.nc.d3 r120 = [ r20 ]
ld2.c.nc.d4 r120 = [ r20 ]
ld2.c.nc.d5 r120 = [ r20 ]
ld2.c.nc.d6 r120 = [ r20 ]
ld2.c.nc.d7 r120 = [ r20 ]
ld4.c.nc r120 = [ r20 ]
ld4.c.nc.nt1 r120 = [ r20 ]
ld4.c.nc.d1 r120 = [ r20 ]
ld4.c.nc.d2 r120 = [ r20 ]
ld4.c.nc.nt2 r120 = [ r20 ]
ld4.c.nc.nta r120 = [ r20 ]
ld4.c.nc.d3 r120 = [ r20 ]
ld4.c.nc.d4 r120 = [ r20 ]
ld4.c.nc.d5 r120 = [ r20 ]
ld4.c.nc.d6 r120 = [ r20 ]
ld4.c.nc.d7 r120 = [ r20 ]
ld8.c.nc r120 = [ r20 ]
ld8.c.nc.nt1 r120 = [ r20 ]
ld8.c.nc.d1 r120 = [ r20 ]
ld8.c.nc.d2 r120 = [ r20 ]
ld8.c.nc.nt2 r120 = [ r20 ]
ld8.c.nc.nta r120 = [ r20 ]
ld8.c.nc.d3 r120 = [ r20 ]
ld8.c.nc.d4 r120 = [ r20 ]
ld8.c.nc.d5 r120 = [ r20 ]
ld8.c.nc.d6 r120 = [ r20 ]
ld8.c.nc.d7 r120 = [ r20 ]
ld1.c.clr.acq r120 = [ r20 ]
ld1.c.clr.acq.nt1 r120 = [ r20 ]
ld1.c.clr.acq.d1 r120 = [ r20 ]
ld1.c.clr.acq.d2 r120 = [ r20 ]
ld1.c.clr.acq.nt2 r120 = [ r20 ]
ld1.c.clr.acq.nta r120 = [ r20 ]
ld1.c.clr.acq.d3 r120 = [ r20 ]
ld1.c.clr.acq.d4 r120 = [ r20 ]
ld1.c.clr.acq.d5 r120 = [ r20 ]
ld1.c.clr.acq.d6 r120 = [ r20 ]
ld1.c.clr.acq.d7 r120 = [ r20 ]
ld2.c.clr.acq r120 = [ r20 ]
ld2.c.clr.acq.nt1 r120 = [ r20 ]
ld2.c.clr.acq.d1 r120 = [ r20 ]
ld2.c.clr.acq.d2 r120 = [ r20 ]
ld2.c.clr.acq.nt2 r120 = [ r20 ]
ld2.c.clr.acq.d3 r120 = [ r20 ]
ld2.c.clr.acq.d4 r120 = [ r20 ]
ld2.c.clr.acq.d5 r120 = [ r20 ]
ld2.c.clr.acq.d6 r120 = [ r20 ]
ld2.c.clr.acq.d7 r120 = [ r20 ]
ld4.c.clr.acq r120 = [ r20 ]
ld4.c.clr.acq.nt1 r120 = [ r20 ]
ld4.c.clr.acq.d1 r120 = [ r20 ]
ld4.c.clr.acq.d2 r120 = [ r20 ]
ld4.c.clr.acq.nt2 r120 = [ r20 ]
ld4.c.clr.acq.nta r120 = [ r20 ]
ld4.c.clr.acq.d3 r120 = [ r20 ]
ld4.c.clr.acq.d4 r120 = [ r20 ]
ld4.c.clr.acq.d5 r120 = [ r20 ]
ld4.c.clr.acq.d6 r120 = [ r20 ]
ld4.c.clr.acq.d7 r120 = [ r20 ]
ld8.c.clr.acq r120 = [ r20 ]
ld8.c.clr.acq.nt1 r120 = [ r20 ]
ld8.c.clr.acq.d1 r120 = [ r20 ]
ld8.c.clr.acq.d2 r120 = [ r20 ]
ld8.c.clr.acq.nt2 r120 = [ r20 ]
ld8.c.clr.acq.nta r120 = [ r20 ]
ld8.c.clr.acq.d3 r120 = [ r20 ]
ld8.c.clr.acq.d4 r120 = [ r20 ]
ld8.c.clr.acq.d5 r120 = [ r20 ]
ld8.c.clr.acq.d6 r120 = [ r20 ]
ld8.c.clr.acq.d7 r120 = [ r20 ]
ld16 r120 = [ r20 ]
ld16 r120 = [ r20 ]
ld16.nt1 r120 = [ r20 ]
ld16.d1 r120 = [ r20 ]
ld16.d2 r120 = [ r20 ]
ld16.nt2 r120 = [ r20 ]
ld16.nt1 r120 = [ r20 ]
ld16.d1 r120 = [ r20 ]
ld16.d2 r120 = [ r20 ]
ld16.nt2 r120 = [ r20 ]
ld16.nta r120 = [ r20 ]
ld16.d3 r120 = [ r20 ]
ld16.d4 r120 = [ r20 ]
ld16.d5 r120 = [ r20 ]
ld16.d6 r120 = [ r20 ]
ld16.d7 r120 = [ r20 ]
ld16.nta r120 = [ r20 ]
ld16.d3 r120 = [ r20 ]
ld16.d4 r120 = [ r20 ]
ld16.d5 r120 = [ r20 ]
ld16.d6 r120 = [ r20 ]
ld16.d7 r120 = [ r20 ]
ld16.acq r120 = [ r20 ]
ld16.acq r120, ar.csd = [ r20 ]
ld16.acq.nt1 r120 = [ r20 ]
ld16.acq.d1 r120 = [ r20 ]
ld16.acq.d2 r120, ar.csd = [ r20 ]
ld16.acq.nt2 r120 = [ r20 ]
ld16.acq.nt1 r120 = [ r20 ]
ld16.acq.d1 r120 = [ r20 ]
ld16.acq.d2 r120 = [ r20 ]
ld16.acq.nt2 r120 = [ r20 ]
ld16.acq.nta r120 = [ r20 ]
ld16.acq.d3 r120 = [ r20 ]
ld16.acq.d4 r120 = [ r20 ]
ld16.acq.d5 r120 = [ r20 ]
ld16.acq.d6 r120 = [ r20 ]
ld16.acq.d7 r120 = [ r20 ]
ld16.acq.nta r120, ar.csd = [ r20 ]
ld16.acq.d3 r120 = [ r20 ]
ld16.acq.d4 r120 = [ r20 ]
ld16.acq.d5 r120 = [ r20 ]
ld16.acq.d6 r120 = [ r20 ]
ld16.acq.d7 r120 = [ r20 ]
/* Pseudo-op that generates ldxmov relocation. */
ld8.mov r120 = [ r20 ], AAAAA
AAAAA:
|
tactcomplabs/xbgas-binutils-gdb
| 1,704
|
gas/testsuite/gas/ia64/reloc.s
|
.global esym
.section .rodata.4, "a", @progbits
.section .rodata.8, "a", @progbits
.text
_start:
adds r1 = esym, r0
mov r2 = esym
movl r3 = esym
.xdata4 .rodata.4, esym
.xdata8 .rodata.8, esym
mov r2 = @gprel(esym)
movl r3 = @gprel(esym)
.xdata4 .rodata.4, @gprel(esym)
.xdata8 .rodata.8, @gprel(esym)
mov r2 = @ltoff(esym)
movl r3 = @ltoff(esym)
mov r2 = @pltoff(esym)
movl r3 = @pltoff(esym)
.xdata8 .rodata.8, @pltoff(esym)
movl r3 = @fptr(esym)
.xdata4 .rodata.4, @fptr(esym)
.xdata8 .rodata.8, @fptr(esym)
brl.call.sptk b1 = esym
br.call.sptk b2 = esym
chk.s r0, esym
fchkf esym
.xdata4 .rodata.4, @pcrel(esym)
.xdata8 .rodata.8, @pcrel(esym)
mov r2 = @ltoff(@fptr(esym))
movl r3 = @ltoff(@fptr(esym))
.xdata4 .rodata.4, @ltoff(@fptr(esym))
.xdata8 .rodata.8, @ltoff(@fptr(esym))
.xdata4 .rodata.4, @segrel(esym)
.xdata8 .rodata.8, @segrel(esym)
.xdata4 .rodata.4, @secrel(esym)
.xdata8 .rodata.8, @secrel(esym)
// REL32 only in executables
// REL64 only in executables
.xdata4 .rodata.4, @ltv(esym)
.xdata8 .rodata.8, @ltv(esym)
//todo PCREL21BI
mov r2 = @pcrel(esym)
movl r3 = @pcrel(esym)
.xdata16 .rodata.8, @iplt(esym)
// COPY only in executables
//todo movl r3 = -esym
mov r2 = @ltoffx(esym)
ld8.mov r3 = [r2], esym
adds r1 = @tprel(esym), r0
mov r2 = @tprel(esym)
movl r3 = @tprel(esym)
.xdata8 .rodata.8, @tprel(esym)
mov r2 = @ltoff(@tprel(esym))
.xdata8 .rodata.8, @dtpmod(esym)
mov r2 = @ltoff(@dtpmod(esym))
adds r1 = @dtprel(esym), r0
mov r2 = @dtprel(esym)
movl r3 = @dtprel(esym)
.xdata4 .rodata.4, @dtprel(esym)
.xdata8 .rodata.8, @dtprel(esym)
mov r2 = @ltoff(@dtprel(esym))
|
tactcomplabs/xbgas-binutils-gdb
| 13,085
|
gas/testsuite/gas/ia64/opc-f.s
|
.text
.type _start,@function
_start:
fma f4 = f5, f6, f7
fma.s0 f4 = f5, f6, f7
fma.s1 f4 = f5, f6, f7
fma.s2 f4 = f5, f6, f7
fma.s3 f4 = f5, f6, f7
fma.s f4 = f5, f6, f7
fma.s.s0 f4 = f5, f6, f7
fma.s.s1 f4 = f5, f6, f7
fma.s.s2 f4 = f5, f6, f7
fma.s.s3 f4 = f5, f6, f7
fma.d f4 = f5, f6, f7
fma.d.s0 f4 = f5, f6, f7
fma.d.s1 f4 = f5, f6, f7
fma.d.s2 f4 = f5, f6, f7
fma.d.s3 f4 = f5, f6, f7
fpma f4 = f5, f6, f7
fpma.s0 f4 = f5, f6, f7
fpma.s1 f4 = f5, f6, f7
fpma.s2 f4 = f5, f6, f7
fpma.s3 f4 = f5, f6, f7
fms f4 = f5, f6, f7
fms.s0 f4 = f5, f6, f7
fms.s1 f4 = f5, f6, f7
fms.s2 f4 = f5, f6, f7
fms.s3 f4 = f5, f6, f7
fms.s f4 = f5, f6, f7
fms.s.s0 f4 = f5, f6, f7
fms.s.s1 f4 = f5, f6, f7
fms.s.s2 f4 = f5, f6, f7
fms.s.s3 f4 = f5, f6, f7
fms.d f4 = f5, f6, f7
fms.d.s0 f4 = f5, f6, f7
fms.d.s1 f4 = f5, f6, f7
fms.d.s2 f4 = f5, f6, f7
fms.d.s3 f4 = f5, f6, f7
fpms f4 = f5, f6, f7
fpms.s0 f4 = f5, f6, f7
fpms.s1 f4 = f5, f6, f7
fpms.s2 f4 = f5, f6, f7
fpms.s3 f4 = f5, f6, f7
fnma f4 = f5, f6, f7
fnma.s0 f4 = f5, f6, f7
fnma.s1 f4 = f5, f6, f7
fnma.s2 f4 = f5, f6, f7
fnma.s3 f4 = f5, f6, f7
fnma.s f4 = f5, f6, f7
fnma.s.s0 f4 = f5, f6, f7
fnma.s.s1 f4 = f5, f6, f7
fnma.s.s2 f4 = f5, f6, f7
fnma.s.s3 f4 = f5, f6, f7
fnma.d f4 = f5, f6, f7
fnma.d.s0 f4 = f5, f6, f7
fnma.d.s1 f4 = f5, f6, f7
fnma.d.s2 f4 = f5, f6, f7
fnma.d.s3 f4 = f5, f6, f7
fpnma f4 = f5, f6, f7
fpnma.s0 f4 = f5, f6, f7
fpnma.s1 f4 = f5, f6, f7
fpnma.s2 f4 = f5, f6, f7
fpnma.s3 f4 = f5, f6, f7
fmpy f4 = f5, f6
fmpy.s0 f4 = f5, f6
fmpy.s1 f4 = f5, f6
fmpy.s2 f4 = f5, f6
fmpy.s3 f4 = f5, f6
fmpy.s f4 = f5, f6
fmpy.s.s0 f4 = f5, f6
fmpy.s.s1 f4 = f5, f6
fmpy.s.s2 f4 = f5, f6
fmpy.s.s3 f4 = f5, f6
fmpy.d f4 = f5, f6
fmpy.d.s0 f4 = f5, f6
fmpy.d.s1 f4 = f5, f6
fmpy.d.s2 f4 = f5, f6
fmpy.d.s3 f4 = f5, f6
fpmpy f4 = f5, f6
fpmpy.s0 f4 = f5, f6
fpmpy.s1 f4 = f5, f6
fpmpy.s2 f4 = f5, f6
fpmpy.s3 f4 = f5, f6
fadd f4 = f5, f6
fadd.s0 f4 = f5, f6
fadd.s1 f4 = f5, f6
fadd.s2 f4 = f5, f6
fadd.s3 f4 = f5, f6
fadd.s f4 = f5, f6
fadd.s.s0 f4 = f5, f6
fadd.s.s1 f4 = f5, f6
fadd.s.s2 f4 = f5, f6
fadd.s.s3 f4 = f5, f6
fadd.d f4 = f5, f6
fadd.d.s0 f4 = f5, f6
fadd.d.s1 f4 = f5, f6
fadd.d.s2 f4 = f5, f6
fadd.d.s3 f4 = f5, f6
fsub f4 = f5, f6
fsub.s0 f4 = f5, f6
fsub.s1 f4 = f5, f6
fsub.s2 f4 = f5, f6
fsub.s3 f4 = f5, f6
fsub.s f4 = f5, f6
fsub.s.s0 f4 = f5, f6
fsub.s.s1 f4 = f5, f6
fsub.s.s2 f4 = f5, f6
fsub.s.s3 f4 = f5, f6
fsub.d f4 = f5, f6
fsub.d.s0 f4 = f5, f6
fsub.d.s1 f4 = f5, f6
fsub.d.s2 f4 = f5, f6
fsub.d.s3 f4 = f5, f6
fnmpy f4 = f5, f6
fnmpy.s0 f4 = f5, f6
fnmpy.s1 f4 = f5, f6
fnmpy.s2 f4 = f5, f6
fnmpy.s3 f4 = f5, f6
fnmpy.s f4 = f5, f6
fnmpy.s.s0 f4 = f5, f6
fnmpy.s.s1 f4 = f5, f6
fnmpy.s.s2 f4 = f5, f6
fnmpy.s.s3 f4 = f5, f6
fnmpy.d f4 = f5, f6
fnmpy.d.s0 f4 = f5, f6
fnmpy.d.s1 f4 = f5, f6
fnmpy.d.s2 f4 = f5, f6
fnmpy.d.s3 f4 = f5, f6
fpnmpy f4 = f5, f6
fpnmpy.s0 f4 = f5, f6
fpnmpy.s1 f4 = f5, f6
fpnmpy.s2 f4 = f5, f6
fpnmpy.s3 f4 = f5, f6
fnorm f4 = f5
fnorm.s0 f4 = f5
fnorm.s1 f4 = f5
fnorm.s2 f4 = f5
fnorm.s3 f4 = f5
fnorm.s f4 = f5
fnorm.s.s0 f4 = f5
fnorm.s.s1 f4 = f5
fnorm.s.s2 f4 = f5
fnorm.s.s3 f4 = f5
fnorm.d f4 = f5
fnorm.d.s0 f4 = f5
fnorm.d.s1 f4 = f5
fnorm.d.s2 f4 = f5
fnorm.d.s3 f4 = f5
xma.l f4 = f5, f6, f7
xma.lu f4 = f5, f6, f7
xma.h f4 = f5, f6, f7
xma.hu f4 = f5, f6, f7
xmpy.l f4 = f5, f6
xmpy.lu f4 = f5, f6
xmpy.h f4 = f5, f6
xmpy.hu f4 = f5, f6
fselect f4 = f5, f6, f7
fcmp.eq p3, p4 = f4, f5
fcmp.eq.s0 p3, p4 = f4, f5
fcmp.eq.s1 p3, p4 = f4, f5
fcmp.eq.s2 p3, p4 = f4, f5
fcmp.eq.s3 p3, p4 = f4, f5
fcmp.eq.unc p3, p4 = f4, f5
fcmp.eq.unc.s0 p3, p4 = f4, f5
fcmp.eq.unc.s1 p3, p4 = f4, f5
fcmp.eq.unc.s2 p3, p4 = f4, f5
fcmp.eq.unc.s3 p3, p4 = f4, f5
fcmp.lt p3, p4 = f4, f5
fcmp.lt.s0 p3, p4 = f4, f5
fcmp.lt.s1 p3, p4 = f4, f5
fcmp.lt.s2 p3, p4 = f4, f5
fcmp.lt.s3 p3, p4 = f4, f5
fcmp.lt.unc p3, p4 = f4, f5
fcmp.lt.unc.s0 p3, p4 = f4, f5
fcmp.lt.unc.s1 p3, p4 = f4, f5
fcmp.lt.unc.s2 p3, p4 = f4, f5
fcmp.lt.unc.s3 p3, p4 = f4, f5
fcmp.le p3, p4 = f4, f5
fcmp.le.s0 p3, p4 = f4, f5
fcmp.le.s1 p3, p4 = f4, f5
fcmp.le.s2 p3, p4 = f4, f5
fcmp.le.s3 p3, p4 = f4, f5
fcmp.le.unc p3, p4 = f4, f5
fcmp.le.unc.s0 p3, p4 = f4, f5
fcmp.le.unc.s1 p3, p4 = f4, f5
fcmp.le.unc.s2 p3, p4 = f4, f5
fcmp.le.unc.s3 p3, p4 = f4, f5
fcmp.unord p3, p4 = f4, f5
fcmp.unord.s0 p3, p4 = f4, f5
fcmp.unord.s1 p3, p4 = f4, f5
fcmp.unord.s2 p3, p4 = f4, f5
fcmp.unord.s3 p3, p4 = f4, f5
fcmp.unord.unc p3, p4 = f4, f5
fcmp.unord.unc.s0 p3, p4 = f4, f5
fcmp.unord.unc.s1 p3, p4 = f4, f5
fcmp.unord.unc.s2 p3, p4 = f4, f5
fcmp.unord.unc.s3 p3, p4 = f4, f5
fcmp.gt p3, p4 = f4, f5
fcmp.gt.s0 p3, p4 = f4, f5
fcmp.gt.s1 p3, p4 = f4, f5
fcmp.gt.s2 p3, p4 = f4, f5
fcmp.gt.s3 p3, p4 = f4, f5
fcmp.gt.unc p3, p4 = f4, f5
fcmp.gt.unc.s0 p3, p4 = f4, f5
fcmp.gt.unc.s1 p3, p4 = f4, f5
fcmp.gt.unc.s2 p3, p4 = f4, f5
fcmp.gt.unc.s3 p3, p4 = f4, f5
fcmp.ge p3, p4 = f4, f5
fcmp.ge.s0 p3, p4 = f4, f5
fcmp.ge.s1 p3, p4 = f4, f5
fcmp.ge.s2 p3, p4 = f4, f5
fcmp.ge.s3 p3, p4 = f4, f5
fcmp.ge.unc p3, p4 = f4, f5
fcmp.ge.unc.s0 p3, p4 = f4, f5
fcmp.ge.unc.s1 p3, p4 = f4, f5
fcmp.ge.unc.s2 p3, p4 = f4, f5
fcmp.ge.unc.s3 p3, p4 = f4, f5
fcmp.neq p3, p4 = f4, f5
fcmp.neq.s0 p3, p4 = f4, f5
fcmp.neq.s1 p3, p4 = f4, f5
fcmp.neq.s2 p3, p4 = f4, f5
fcmp.neq.s3 p3, p4 = f4, f5
fcmp.neq.unc p3, p4 = f4, f5
fcmp.neq.unc.s0 p3, p4 = f4, f5
fcmp.neq.unc.s1 p3, p4 = f4, f5
fcmp.neq.unc.s2 p3, p4 = f4, f5
fcmp.neq.unc.s3 p3, p4 = f4, f5
fcmp.nlt p3, p4 = f4, f5
fcmp.nlt.s0 p3, p4 = f4, f5
fcmp.nlt.s1 p3, p4 = f4, f5
fcmp.nlt.s2 p3, p4 = f4, f5
fcmp.nlt.s3 p3, p4 = f4, f5
fcmp.nlt.unc p3, p4 = f4, f5
fcmp.nlt.unc.s0 p3, p4 = f4, f5
fcmp.nlt.unc.s1 p3, p4 = f4, f5
fcmp.nlt.unc.s2 p3, p4 = f4, f5
fcmp.nlt.unc.s3 p3, p4 = f4, f5
fcmp.nle p3, p4 = f4, f5
fcmp.nle.s0 p3, p4 = f4, f5
fcmp.nle.s1 p3, p4 = f4, f5
fcmp.nle.s2 p3, p4 = f4, f5
fcmp.nle.s3 p3, p4 = f4, f5
fcmp.nle.unc p3, p4 = f4, f5
fcmp.nle.unc.s0 p3, p4 = f4, f5
fcmp.nle.unc.s1 p3, p4 = f4, f5
fcmp.nle.unc.s2 p3, p4 = f4, f5
fcmp.nle.unc.s3 p3, p4 = f4, f5
fcmp.ngt p3, p4 = f4, f5
fcmp.ngt.s0 p3, p4 = f4, f5
fcmp.ngt.s1 p3, p4 = f4, f5
fcmp.ngt.s2 p3, p4 = f4, f5
fcmp.ngt.s3 p3, p4 = f4, f5
fcmp.ngt.unc p3, p4 = f4, f5
fcmp.ngt.unc.s0 p3, p4 = f4, f5
fcmp.ngt.unc.s1 p3, p4 = f4, f5
fcmp.ngt.unc.s2 p3, p4 = f4, f5
fcmp.ngt.unc.s3 p3, p4 = f4, f5
fcmp.nge p3, p4 = f4, f5
fcmp.nge.s0 p3, p4 = f4, f5
fcmp.nge.s1 p3, p4 = f4, f5
fcmp.nge.s2 p3, p4 = f4, f5
fcmp.nge.s3 p3, p4 = f4, f5
fcmp.nge.unc p3, p4 = f4, f5
fcmp.nge.unc.s0 p3, p4 = f4, f5
fcmp.nge.unc.s1 p3, p4 = f4, f5
fcmp.nge.unc.s2 p3, p4 = f4, f5
fcmp.nge.unc.s3 p3, p4 = f4, f5
fcmp.ord p3, p4 = f4, f5
fcmp.ord.s0 p3, p4 = f4, f5
fcmp.ord.s1 p3, p4 = f4, f5
fcmp.ord.s2 p3, p4 = f4, f5
fcmp.ord.s3 p3, p4 = f4, f5
fcmp.ord.unc p3, p4 = f4, f5
fcmp.ord.unc.s0 p3, p4 = f4, f5
fcmp.ord.unc.s1 p3, p4 = f4, f5
fcmp.ord.unc.s2 p3, p4 = f4, f5
fcmp.ord.unc.s3 p3, p4 = f4, f5
fclass.m p3, p4 = f4, @nat
fclass.nm p3, p4 = f4, @nat
fclass.m p3, p4 = f4, @qnan
fclass.nm p3, p4 = f4, @qnan
fclass.m p3, p4 = f4, @snan
fclass.nm p3, p4 = f4, @snan
fclass.m p3, p4 = f4, @pos
fclass.nm p3, p4 = f4, @pos
fclass.m p3, p4 = f4, @neg
fclass.nm p3, p4 = f4, @neg
fclass.m p3, p4 = f4, @unorm
fclass.nm p3, p4 = f4, @unorm
fclass.m p3, p4 = f4, @norm
fclass.nm p3, p4 = f4, @norm
fclass.m p3, p4 = f4, @inf
fclass.nm p3, p4 = f4, @inf
fclass.m p3, p4 = f4, 0x1ff
fclass.nm p3, p4 = f4, 0x1ff
fclass.m.unc p3, p4 = f4, @nat
fclass.nm.unc p3, p4 = f4, @nat
fclass.m.unc p3, p4 = f4, @qnan
fclass.nm.unc p3, p4 = f4, @qnan
fclass.m.unc p3, p4 = f4, @snan
fclass.nm.unc p3, p4 = f4, @snan
fclass.m.unc p3, p4 = f4, @pos
fclass.nm.unc p3, p4 = f4, @pos
fclass.m.unc p3, p4 = f4, @neg
fclass.nm.unc p3, p4 = f4, @neg
fclass.m.unc p3, p4 = f4, @unorm
fclass.nm.unc p3, p4 = f4, @unorm
fclass.m.unc p3, p4 = f4, @norm
fclass.nm.unc p3, p4 = f4, @norm
fclass.m.unc p3, p4 = f4, @inf
fclass.nm.unc p3, p4 = f4, @inf
fclass.m.unc p3, p4 = f4, 0x1ff
fclass.nm.unc p3, p4 = f4, 0x1ff
frcpa f4, p5 = f6, f7
frcpa.s0 f4, p5 = f6, f7
frcpa.s1 f4, p5 = f6, f7
frcpa.s2 f4, p5 = f6, f7
frcpa.s3 f4, p5 = f6, f7
fprcpa f4, p5 = f6, f7
fprcpa.s0 f4, p5 = f6, f7
fprcpa.s1 f4, p5 = f6, f7
fprcpa.s2 f4, p5 = f6, f7
fprcpa.s3 f4, p5 = f6, f7
frsqrta f4, p5 = f6
frsqrta.s0 f4, p5 = f6
frsqrta.s1 f4, p5 = f6
frsqrta.s2 f4, p5 = f6
frsqrta.s3 f4, p5 = f6
fprsqrta f4, p5 = f6
fprsqrta.s0 f4, p5 = f6
fprsqrta.s1 f4, p5 = f6
fprsqrta.s2 f4, p5 = f6
fprsqrta.s3 f4, p5 = f6
fmin f4 = f5, f6
fmin.s0 f4 = f5, f6
fmin.s1 f4 = f5, f6
fmin.s2 f4 = f5, f6
fmin.s3 f4 = f5, f6
fmax f4 = f5, f6
fmax.s0 f4 = f5, f6
fmax.s1 f4 = f5, f6
fmax.s2 f4 = f5, f6
fmax.s3 f4 = f5, f6
famin f4 = f5, f6
famin.s0 f4 = f5, f6
famin.s1 f4 = f5, f6
famin.s2 f4 = f5, f6
famin.s3 f4 = f5, f6
famax f4 = f5, f6
famax.s0 f4 = f5, f6
famax.s1 f4 = f5, f6
famax.s2 f4 = f5, f6
famax.s3 f4 = f5, f6
fpmin f4 = f5, f6
fpmin.s0 f4 = f5, f6
fpmin.s1 f4 = f5, f6
fpmin.s2 f4 = f5, f6
fpmin.s3 f4 = f5, f6
fpmax f4 = f5, f6
fpmax.s0 f4 = f5, f6
fpmax.s1 f4 = f5, f6
fpmax.s2 f4 = f5, f6
fpmax.s3 f4 = f5, f6
fpamin f4 = f5, f6
fpamin.s0 f4 = f5, f6
fpamin.s1 f4 = f5, f6
fpamin.s2 f4 = f5, f6
fpamin.s3 f4 = f5, f6
fpamax f4 = f5, f6
fpamax.s0 f4 = f5, f6
fpamax.s1 f4 = f5, f6
fpamax.s2 f4 = f5, f6
fpamax.s3 f4 = f5, f6
fpcmp.eq f3 = f4, f5
fpcmp.eq.s0 f3 = f4, f5
fpcmp.eq.s1 f3 = f4, f5
fpcmp.eq.s2 f3 = f4, f5
fpcmp.eq.s3 f3 = f4, f5
fpcmp.lt f3 = f4, f5
fpcmp.lt.s0 f3 = f4, f5
fpcmp.lt.s1 f3 = f4, f5
fpcmp.lt.s2 f3 = f4, f5
fpcmp.lt.s3 f3 = f4, f5
fpcmp.le f3 = f4, f5
fpcmp.le.s0 f3 = f4, f5
fpcmp.le.s1 f3 = f4, f5
fpcmp.le.s2 f3 = f4, f5
fpcmp.le.s3 f3 = f4, f5
fpcmp.unord f3 = f4, f5
fpcmp.unord.s0 f3 = f4, f5
fpcmp.unord.s1 f3 = f4, f5
fpcmp.unord.s2 f3 = f4, f5
fpcmp.unord.s3 f3 = f4, f5
fpcmp.gt f3 = f4, f5
fpcmp.gt.s0 f3 = f4, f5
fpcmp.gt.s1 f3 = f4, f5
fpcmp.gt.s2 f3 = f4, f5
fpcmp.gt.s3 f3 = f4, f5
fpcmp.ge f3 = f4, f5
fpcmp.ge.s0 f3 = f4, f5
fpcmp.ge.s1 f3 = f4, f5
fpcmp.ge.s2 f3 = f4, f5
fpcmp.ge.s3 f3 = f4, f5
fpcmp.neq f3 = f4, f5
fpcmp.neq.s0 f3 = f4, f5
fpcmp.neq.s1 f3 = f4, f5
fpcmp.neq.s2 f3 = f4, f5
fpcmp.neq.s3 f3 = f4, f5
fpcmp.nlt f3 = f4, f5
fpcmp.nlt.s0 f3 = f4, f5
fpcmp.nlt.s1 f3 = f4, f5
fpcmp.nlt.s2 f3 = f4, f5
fpcmp.nlt.s3 f3 = f4, f5
fpcmp.nle f3 = f4, f5
fpcmp.nle.s0 f3 = f4, f5
fpcmp.nle.s1 f3 = f4, f5
fpcmp.nle.s2 f3 = f4, f5
fpcmp.nle.s3 f3 = f4, f5
fpcmp.ngt f3 = f4, f5
fpcmp.ngt.s0 f3 = f4, f5
fpcmp.ngt.s1 f3 = f4, f5
fpcmp.ngt.s2 f3 = f4, f5
fpcmp.ngt.s3 f3 = f4, f5
fpcmp.nge f3 = f4, f5
fpcmp.nge.s0 f3 = f4, f5
fpcmp.nge.s1 f3 = f4, f5
fpcmp.nge.s2 f3 = f4, f5
fpcmp.nge.s3 f3 = f4, f5
fpcmp.ord f3 = f4, f5
fpcmp.ord.s0 f3 = f4, f5
fpcmp.ord.s1 f3 = f4, f5
fpcmp.ord.s2 f3 = f4, f5
fpcmp.ord.s3 f3 = f4, f5
fmerge.s f4 = f5, f6
fmerge.ns f4 = f5, f6
fmerge.se f4 = f5, f6
fmix.lr f4 = f5, f6
fmix.r f4 = f5, f6
fmix.l f4 = f5, f6
fsxt.l f4 = f5, f6
fpack f4 = f5, f6
fswap f4 = f5, f6
fswap.nl f4 = f5, f6
fswap.nr f4 = f5, f6
fand f4 = f5, f6
fandcm f4 = f5, f6
for f4 = f5, f6
fxor f4 = f5, f6
fpmerge.s f4 = f5, f6
fpmerge.ns f4 = f5, f6
fpmerge.se f4 = f5, f6
fabs f4 = f5
fneg f4 = f5
fnegabs f4 = f5
fpabs f4 = f5
fpneg f4 = f5
fpnegabs f4 = f5
fcvt.fx f4 = f5
fcvt.fx.s0 f4 = f5
fcvt.fx.s1 f4 = f5
fcvt.fx.s2 f4 = f5
fcvt.fx.s3 f4 = f5
fcvt.fx.trunc f4 = f5
fcvt.fx.trunc.s0 f4 = f5
fcvt.fx.trunc.s1 f4 = f5
fcvt.fx.trunc.s2 f4 = f5
fcvt.fx.trunc.s3 f4 = f5
fcvt.fxu f4 = f5
fcvt.fxu.s0 f4 = f5
fcvt.fxu.s1 f4 = f5
fcvt.fxu.s2 f4 = f5
fcvt.fxu.s3 f4 = f5
fcvt.fxu.trunc f4 = f5
fcvt.fxu.trunc.s0 f4 = f5
fcvt.fxu.trunc.s1 f4 = f5
fcvt.fxu.trunc.s2 f4 = f5
fcvt.fxu.trunc.s3 f4 = f5
fpcvt.fx f4 = f5
fpcvt.fx.s0 f4 = f5
fpcvt.fx.s1 f4 = f5
fpcvt.fx.s2 f4 = f5
fpcvt.fx.s3 f4 = f5
fpcvt.fx.trunc f4 = f5
fpcvt.fx.trunc.s0 f4 = f5
fpcvt.fx.trunc.s1 f4 = f5
fpcvt.fx.trunc.s2 f4 = f5
fpcvt.fx.trunc.s3 f4 = f5
fpcvt.fxu f4 = f5
fpcvt.fxu.s0 f4 = f5
fpcvt.fxu.s1 f4 = f5
fpcvt.fxu.s2 f4 = f5
fpcvt.fxu.s3 f4 = f5
fpcvt.fxu.trunc f4 = f5
fpcvt.fxu.trunc.s0 f4 = f5
fpcvt.fxu.trunc.s1 f4 = f5
fpcvt.fxu.trunc.s2 f4 = f5
fpcvt.fxu.trunc.s3 f4 = f5
fcvt.xf f4 = f5
fcvt.xuf f4 = f5
fsetc 0, 0
fsetc 0x3f, 0x3f
fsetc.s0 0, 0
fsetc.s0 0x3f, 0x3f
fsetc.s1 0, 0
fsetc.s1 0x3f, 0x3f
fsetc.s2 0, 0
fsetc.s2 0x3f, 0x3f
fsetc.s3 0, 0
fsetc.s3 0x3f, 0x3f
fclrf
fclrf.s0
fclrf.s1
fclrf.s2
fclrf.s3
fchkf _start
fchkf.s0 _start
fchkf.s1 _start
fchkf.s2 _start
fchkf.s3 _start
break.f 0
nop.f 0;;
# instructions added by SDM2.1:
hint.f 0
hint.f @pause
hint.f 0x1ffff
|
tactcomplabs/xbgas-binutils-gdb
| 3,699
|
gas/testsuite/gas/ia64/unwind-ok.s
|
.text
.proc personality
personality:
br.ret.sptk rp
.endp personality
.proc full1
full1:
.prologue
.spill 0
.save.g 0x1
nop 0
.save.f 0x1
nop 0
.save.b 0x01
nop 0
.save.g 0x8
nop 0
.save.f 0x8
nop 0
.save.b 0x10
nop 0
.altrp b7
nop 0
.unwabi @svr4, 0
nop 0
.body
.spillreg r4, r2
nop 0
.spillreg.p p1, r7, r127
nop 0
.spillsp b1, 0x08
nop 0
.spillsp.p p2, b5, 0x10
nop 0
.spillpsp f2, 0x18
nop 0
.spillpsp.p p4, f5, 0x20
nop 0
.restorereg f16
nop 0
.restorereg.p p8, f31
nop 0
.spillreg ar.bsp, r16
nop 0
.spillreg ar.bspstore, r17
nop 0
.spillreg ar.fpsr, r18
nop 0
.spillreg ar.lc, r19
nop 0
.spillreg ar.pfs, r20
nop 0
.spillreg ar.rnat, r21
nop 0
.spillreg ar.unat, r22
nop 0
.spillreg psp, r23
nop 0
.spillreg pr, r24
nop 0
.spillreg rp, r25
nop 0
.spillreg @priunat, r26
nop 0
.label_state 1
nop 0
.restore sp
nop.x 0
.copy_state 1
br.ret.sptk rp
.personality personality
.handlerdata
data4 -1
data4 0
.endp full1
.proc full2
full2:
.prologue 0xb, r8
.spill 0
.save.gf 0x1, 0x00001
nop 0
nop 0
.save.b 0x11, r32
nop 0
nop 0
.save.gf 0x8, 0x80000
nop 0
nop 0
.spillreg f31, f127
nop 0
.spillreg.p p63, f16, f32
nop 0
.spillsp f5, 0x20
nop 0
.spillsp.p p31, f2, 0x18
nop 0
.spillpsp b5, 0x10
nop 0
.spillpsp.p p15, b1, 0x08
nop 0
.restorereg r7
nop 0
.restorereg.p p7, r4
nop 0
.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
.body
.label_state 32
nop 0
.restore sp, 32
nop.x 0
.copy_state 32
br.ret.sptk rp
.endp full2
.proc full3
full3:
.prologue
.spill 0
.save.g 0x3, r32
nop 0
nop 0
.save.b 0x03, r34
nop 0
nop 0
.save.g 0xc, r124
nop 0
nop 0
.save.b 0x18, r126
nop 0
nop 0
nop.x 0
nop.x 0
nop.x 0
nop.x 0
nop.x 0
nop.x 0
nop.x 0
nop.x 0
.body
nop.x 0
nop.x 0
nop.x 0
nop.x 0
nop.x 0
nop.x 0
nop.x 0
nop.x 0
nop.x 0
nop.x 0
br.ret.sptk rp
.endp full3
.proc fframe
fframe:
.prologue
.fframe 0
nop 0
.body
br.ret.sptk rp
.endp fframe
.proc vframe
vframe:
.prologue
.vframe r16
nop 0
.save ar.bsp, r17
nop 0
.save ar.bspstore, r18
nop 0
.save ar.fpsr, r19
nop 0
.save ar.lc, r20
nop 0
.save ar.pfs, r21
nop 0
.save ar.rnat, r22
nop 0
.save ar.unat, r23
nop 0
.save pr, r24
nop 0
.save @priunat, r25
nop 0
.save rp, r26
nop 0
.body
br.ret.sptk rp
.endp vframe
.proc vframesp
vframesp:
.prologue
.vframesp 0
nop 0
.savesp ar.bsp, 0x08
nop 0
.savesp ar.bspstore, 0x10
nop 0
.savesp ar.fpsr, 0x18
nop 0
.savesp ar.lc, 0x20
nop 0
.savesp ar.pfs, 0x28
nop 0
.savesp ar.rnat, 0x30
nop 0
.savesp ar.unat, 0x38
nop 0
.savesp pr, 0x40
nop 0
.savesp @priunat, 0x48
nop 0
.savesp rp, 0x50
nop 0
.body
br.ret.sptk rp
.endp vframesp
.proc psp
psp:
.prologue
.vframesp 0
nop 0
.savepsp ar.bsp, 0x08
nop 0
.savepsp ar.bspstore, 0x10
nop 0
.savepsp ar.fpsr, 0x18
nop 0
.savepsp ar.lc, 0x20
nop 0
.savepsp ar.pfs, 0x28
nop 0
.savepsp ar.rnat, 0x30
nop 0
.savepsp ar.unat, 0x38
nop 0
.savepsp pr, 0x40
nop 0
.savepsp @priunat, 0x48
nop 0
.savepsp rp, 0x50
nop 0
.body
br.ret.sptk rp
.endp psp
.proc simple
simple:
.unwentry
br.ret.sptk rp
.endp simple
|
tactcomplabs/xbgas-binutils-gdb
| 2,474
|
gas/testsuite/gas/ia64/invalid-ar.s
|
// AR 0 to AR 47 can be accessed only by M unit.
mov.i r1 = ar0
mov.i r1 = ar1
mov.i r1 = ar2
mov.i r1 = ar3
mov.i r1 = ar4
mov.i r1 = ar5
mov.i r1 = ar6
mov.i r1 = ar7
mov.i r1 = ar8
mov.i r1 = ar9
mov.i r1 = ar10
mov.i r1 = ar11
mov.i r1 = ar12
mov.i r1 = ar13
mov.i r1 = ar14
mov.i r1 = ar15
mov.i r1 = ar16
mov.i r1 = ar17
mov.i r1 = ar18
mov.i r1 = ar19
mov.i r1 = ar20
mov.i r1 = ar21
mov.i r1 = ar22
mov.i r1 = ar23
mov.i r1 = ar24
mov.i r1 = ar25
mov.i r1 = ar26
mov.i r1 = ar27
mov.i r1 = ar28
mov.i r1 = ar29
mov.i r1 = ar30
mov.i r1 = ar31
mov.i r1 = ar32
mov.i r1 = ar33
mov.i r1 = ar34
mov.i r1 = ar35
mov.i r1 = ar36
mov.i r1 = ar37
mov.i r1 = ar38
mov.i r1 = ar39
mov.i r1 = ar40
mov.i r1 = ar41
mov.i r1 = ar42
mov.i r1 = ar43
mov.i r1 = ar44
mov.i r1 = ar45
mov.i r1 = ar46
mov.i r1 = ar47
// AR 48 to 63 can be accessed by I or M units.
// AR 64 to AR 111 can be accessed only by I unit.
mov.m r1 = ar64
mov.m r1 = ar65
mov.m r1 = ar66
mov.m r1 = ar67
mov.m r1 = ar68
mov.m r1 = ar69
mov.m r1 = ar70
mov.m r1 = ar71
mov.m r1 = ar72
mov.m r1 = ar73
mov.m r1 = ar74
mov.m r1 = ar75
mov.m r1 = ar76
mov.m r1 = ar77
mov.m r1 = ar78
mov.m r1 = ar79
mov.m r1 = ar80
mov.m r1 = ar81
mov.m r1 = ar82
mov.m r1 = ar83
mov.m r1 = ar84
mov.m r1 = ar85
mov.m r1 = ar86
mov.m r1 = ar87
mov.m r1 = ar88
mov.m r1 = ar89
mov.m r1 = ar90
mov.m r1 = ar91
mov.m r1 = ar92
mov.m r1 = ar93
mov.m r1 = ar94
mov.m r1 = ar95
mov.m r1 = ar96
mov.m r1 = ar97
mov.m r1 = ar98
mov.m r1 = ar99
mov.m r1 = ar100
mov.m r1 = ar101
mov.m r1 = ar102
mov.m r1 = ar103
mov.m r1 = ar104
mov.m r1 = ar105
mov.m r1 = ar106
mov.m r1 = ar107
mov.m r1 = ar108
mov.m r1 = ar109
mov.m r1 = ar110
mov.m r1 = ar111
// AR 112 to 127 can be accessed by I or M units.
// AR K0 to AR ITC can be accessed only by M unit.
mov.i r1 = ar.k0
mov.i r1 = ar.k1
mov.i r1 = ar.k2
mov.i r1 = ar.k3
mov.i r1 = ar.k4
mov.i r1 = ar.k5
mov.i r1 = ar.k6
mov.i r1 = ar.k7
mov.i r1 = ar.rsc
mov.i r1 = ar.bsp
mov.i r1 = ar.bspstore
mov.i r1 = ar.rnat
mov.i r1 = ar.fcr
mov.i r1 = ar.eflag
mov.i r1 = ar.csd
mov.i r1 = ar.ssd
mov.i r1 = ar.cflg
mov.i r1 = ar.fsr
mov.i r1 = ar.fir
mov.i r1 = ar.fdr
mov.i r1 = ar.ccv
mov.i r1 = ar.unat
mov.i r1 = ar.fpsr
mov.i r1 = ar.itc
mov.i r1 = ar.ruc
// AR PFS, LC and EC can be accessed only by I unit.
mov.m r1 = ar.pfs
mov.m r1 = ar.lc
mov.m r1 = ar.ec
|
tactcomplabs/xbgas-binutils-gdb
| 7,828
|
gas/testsuite/gas/ia64/dv-waw-err.s
|
//
// Detect WAW violations. Cases taken from DV tables.
//
.text
.explicit
// AR[BSP]
mov ar.bsp = r0
mov ar.bsp = r1
;;
// AR[BSPSTORE]
mov ar.bspstore = r2
mov ar.bspstore = r3
;;
// AR[CCV]
mov ar.ccv = r4
mov ar.ccv = r4
;;
// AR[EC]
br.wtop.sptk L
mov ar.ec = r0
;;
// AR[FPSR].sf0.controls
mov ar.fpsr = r0
fsetc.s0 0x7f, 0x0f
;;
// AR[FPSR].sf1.controls
mov ar.fpsr = r0
fsetc.s1 0x7f, 0x0f
;;
// AR[FPSR].sf2.controls
mov ar.fpsr = r0
fsetc.s2 0x7f, 0x0f
;;
// AR[FPSR].sf3.controls
mov ar.fpsr = r0
fsetc.s3 0x7f, 0x0f
;;
// AR[FPSR].sf0.flags
fcmp.eq.s0 p1, p2 = f3, f4
fcmp.eq.s0 p3, p4 = f3, f4 // no DV here
;;
fcmp.eq.s0 p1, p2 = f3, f4
fclrf.s0
;;
// AR[FPSR].sf1.flags
fcmp.eq.s1 p1, p2 = f3, f4
fcmp.eq.s1 p3, p4 = f3, f4 // no DV here
;;
fcmp.eq.s1 p1, p2 = f3, f4
fclrf.s1
;;
// AR[FPSR].sf2.flags
fcmp.eq.s2 p1, p2 = f3, f4
fcmp.eq.s2 p3, p4 = f3, f4 // no DV here
;;
fcmp.eq.s2 p1, p2 = f3, f4
fclrf.s2
;;
// AR[FPSR].sf3.flags
fcmp.eq.s3 p1, p2 = f3, f4
fcmp.eq.s3 p3, p4 = f3, f4 // no DV here
;;
fcmp.eq.s3 p1, p2 = f3, f4
fclrf.s3
;;
// AR[FPSR].traps/rv plus all controls/flags
mov ar.fpsr = r0
mov ar.fpsr = r0
;;
// AR[ITC]
mov ar.itc = r1
mov ar.itc = r1
;;
// AR[RUC]
mov ar.ruc = r1
mov ar.ruc = r1
;;
// AR[K]
mov ar.k2 = r3
mov ar.k2 = r3
;;
// AR[LC]
br.cloop.sptk L
mov ar.lc = r0
;;
// AR[PFS]
mov ar.pfs = r0
br.call.sptk b0 = L
;;
// AR[RNAT] (see also AR[BSPSTORE])
mov ar.rnat = r8
mov ar.rnat = r8
;;
// AR[RSC]
mov ar.rsc = r10
mov ar.rsc = r10
;;
// AR[UNAT]
mov ar.unat = r12
st8.spill [r0] = r1
;;
// AR%
mov ar48 = r0
mov ar48 = r0
;;
// BR%
mov b1 = r0
mov b1 = r1
;;
// CFM (and others)
br.wtop.sptk L
br.wtop.sptk L
;;
// CR[CMCV]
mov cr.cmcv = r1
mov cr.cmcv = r2
;;
// CR[DCR]
mov cr.dcr = r3
mov cr.dcr = r3
;;
// CR[EOI] (and InService)
mov cr.eoi = r0
mov cr.eoi = r0
;;
srlz.d
// CR[GPTA]
mov cr.gpta = r6
mov cr.gpta = r7
;;
// CR[IFA]
mov cr.ifa = r9
mov cr.ifa = r10
;;
// CR[IFS]
mov cr.ifs = r11
cover
;;
// CR[IHA]
mov cr.iha = r13
mov cr.iha = r14
;;
// CR[IIB%]
mov cr.iib0 = r15
mov cr.iib0 = r16
;;
mov cr.iib1 = r15
mov cr.iib1 = r16
;;
// CR[IIM]
mov cr.iim = r15
mov cr.iim = r16
;;
// CR[IIP]
mov cr.iip = r17
mov cr.iip = r17
;;
// CR[IIPA]
mov cr.iipa = r19
mov cr.iipa = r20
;;
// CR[IPSR]
mov cr.ipsr = r21
mov cr.ipsr = r22
;;
// CR[IRR%] (and others)
mov r2 = cr.ivr
mov r3 = cr.ivr
;;
// CR[ISR]
mov cr.isr = r24
mov cr.isr = r25
;;
// CR[ITIR]
mov cr.itir = r26
mov cr.itir = r27
;;
// CR[ITM]
mov cr.itm = r28
mov cr.itm = r29
;;
// CR[ITV]
mov cr.itv = r0
mov cr.itv = r1
;;
// CR[IVA]
mov cr.iva = r0
mov cr.iva = r1
;;
// CR[IVR] (no explicit writers)
// CR[LID]
mov cr.lid = r0
mov cr.lid = r1
;;
// CR[LRR%]
mov cr.lrr0 = r0
mov cr.lrr1 = r0 // no DV here
;;
mov cr.lrr0 = r0
mov cr.lrr0 = r0
;;
// CR[PMV]
mov cr.pmv = r0
mov cr.pmv = r1
;;
// CR[PTA]
mov cr.pta = r0
mov cr.pta = r1
;;
// CR[TPR]
mov cr.tpr = r0
mov cr.tpr = r1
;;
// DBR#
mov dbr[r1] = r1
mov dbr[r1] = r2
;;
srlz.d
// DTC
ptc.e r0
ptc.e r1 // no DVs here
;;
ptc.e r0 // (and others)
itc.i r0
;;
srlz.d
// DTC_LIMIT
ptc.g r0, r1 // NOTE: GAS automatically emits stops after
ptc.ga r2, r3 // ptc.g/ptc.ga, so this conflict is no
;; // longer possible in GAS-generated assembly
srlz.d
// DTR
itr.d dtr[r0] = r1 // (and others)
ptr.d r2, r3
;;
srlz.d
// FR%
mov f3 = f2
ldfs.c.clr f3 = [r1]
;;
// GR%
mov r2 = r0
ld8.c.clr r2 = [r1]
;;
// IBR#
mov ibr[r0] = r2
mov ibr[r1] = r2
;;
// InService
mov cr.eoi = r0
mov r1 = cr.ivr
;;
srlz.d
// ITC
ptc.e r0
itc.i r1
;;
srlz.i
;;
// ITR
itr.i itr[r0] = r1
ptr.i r2, r3
;;
srlz.i
;;
// PKR#
.reg.val r1, 0x1
.reg.val r2, ~0x1
mov pkr[r1] = r1
mov pkr[r2] = r1 // no DV here
;;
mov pkr[r1] = r1
mov pkr[r1] = r1
;;
// PMC#
mov pmc[r3] = r1
mov pmc[r4] = r1
;;
// PMD#
mov pmd[r3] = r1
mov pmd[r4] = r1
;;
// PR%, 1 - 15
cmp.eq p1, p0 = r0, r1
cmp.eq p1, p0 = r2, r3
;;
fcmp.eq p1, p2 = f2, f3
fcmp.eq p1, p3 = f2, f3
;;
cmp.eq.and p1, p2 = r0, r1
cmp.eq.or p1, p3 = r2, r3
;;
cmp.eq.or p1, p3 = r2, r3
cmp.eq.and p1, p2 = r0, r1
;;
cmp.eq.and p1, p2 = r0, r1
cmp.eq.and p1, p3 = r2, r3 // no DV here
;;
cmp.eq.or p1, p2 = r0, r1
cmp.eq.or p1, p3 = r2, r3 // no DV here
;;
// PR63
br.wtop.sptk L
br.wtop.sptk L
;;
cmp.eq p63, p0 = r0, r1
cmp.eq p63, p0 = r2, r3
;;
fcmp.eq p63, p2 = f2, f3
fcmp.eq p63, p3 = f2, f3
;;
cmp.eq.and p63, p2 = r0, r1
cmp.eq.or p63, p3 = r2, r3
;;
cmp.eq.or p63, p3 = r2, r3
cmp.eq.and p63, p2 = r0, r1
;;
cmp.eq.and p63, p2 = r0, r1
cmp.eq.and p63, p3 = r2, r3 // no DV here
;;
cmp.eq.or p63, p2 = r0, r1
cmp.eq.or p63, p3 = r2, r3 // no DV here
;;
// PSR.ac
rum (1<<3)
rum (1<<3)
;;
// PSR.be
rum (1<<1)
rum (1<<1)
;;
// PSR.bn
bsw.0 // GAS automatically emits a stop after bsw.n
bsw.0 // so this conflict is avoided
;;
// PSR.cpl
epc
br.ret.sptk b0
;;
// PSR.da (rfi is the only writer)
// PSR.db (and others)
mov psr.l = r0
mov psr.l = r1
;;
srlz.d
// PSR.dd (rfi is the only writer)
// PSR.dfh
ssm (1<<19)
ssm (1<<19)
;;
srlz.d
// PSR.dfl
ssm (1<<18)
ssm (1<<18)
;;
srlz.d
// PSR.di
rsm (1<<22)
rsm (1<<22)
;;
// PSR.dt
rsm (1<<17)
rsm (1<<17)
;;
// PSR.ed (rfi is the only writer)
// PSR.i
ssm (1<<14)
ssm (1<<14)
;;
// PSR.ia (no DV semantics)
// PSR.ic
ssm (1<<13)
ssm (1<<13)
;;
// PSR.id (rfi is the only writer)
// PSR.is (br.ia and rfi are the only writers)
// PSR.it (rfi is the only writer)
// PSR.lp (see PSR.db)
// PSR.mc (rfi is the only writer)
// PSR.mfh
mov f32 = f33
mov r10 = psr
;;
ssm (1<<5)
ssm (1<<5)
;;
ssm (1<<5)
mov psr.um = r10
;;
rum (1<<5)
rum (1<<5)
;;
mov f32 = f33
mov f34 = f35 // no DV here
;;
// PSR.mfl
mov f2 = f3
mov r10 = psr
;;
ssm (1<<4)
ssm (1<<4)
;;
ssm (1<<4)
mov psr.um = r10
;;
rum (1<<4)
rum (1<<4)
;;
mov f2 = f3
mov f4 = f5 // no DV here
;;
// PSR.pk
rsm (1<<15)
rsm (1<<15)
;;
// PSR.pp
rsm (1<<21)
rsm (1<<21)
;;
// PSR.ri (no DV semantics)
// PSR.rt (see PSR.db)
// PSR.si
rsm (1<<23)
ssm (1<<23)
;;
// PSR.sp
ssm (1<<20)
rsm (1<<20)
;;
srlz.d
// PSR.ss (rfi is the only writer)
// PSR.tb (see PSR.db)
// PSR.up
rsm (1<<2)
rsm (1<<2)
;;
rum (1<<2)
mov psr.um = r0
;;
// RR#
mov rr[r2] = r1
mov rr[r2] = r3
;;
// PR, additional cases (or.andcm and and.orcm interaction)
cmp.eq.or.andcm p6, p7 = 1, r32
cmp.eq.or.andcm p6, p7 = 5, r36 // no DV here
;;
cmp.eq.and.orcm p6, p7 = 1, r32
cmp.eq.and.orcm p6, p7 = 5, r36 // no DV here
;;
cmp.eq.or.andcm p63, p7 = 1, r32
cmp.eq.or.andcm p63, p7 = 5, r36 // no DV here
;;
cmp.eq.or.andcm p6, p63 = 1, r32
cmp.eq.or.andcm p6, p63 = 5, r36 // no DV here
;;
cmp.eq.and.orcm p63, p7 = 1, r32
cmp.eq.and.orcm p63, p7 = 5, r36 // no DV here
;;
cmp.eq.and.orcm p6, p63 = 1, r32
cmp.eq.and.orcm p6, p63 = 5, r36 // no DV here
;;
cmp.eq.or.andcm p6, p7 = 1, r32
cmp.eq.and.orcm p6, p7 = 5, r36
;;
cmp.eq.or.andcm p63, p7 = 1, r32
cmp.eq.and.orcm p63, p7 = 5, r36
;;
cmp.eq.or.andcm p6, p63 = 1, r32
cmp.eq.and.orcm p6, p63 = 5, r36
;;
// PR%, 16 - 62
cmp.eq p21, p0 = r0, r1
cmp.eq p21, p0 = r2, r3
;;
fcmp.eq p21, p22 = f2, f3
fcmp.eq p21, p23 = f2, f3
;;
cmp.eq.and p21, p22 = r0, r1
cmp.eq.or p21, p23 = r2, r3
;;
cmp.eq.or p21, p23 = r2, r3
cmp.eq.and p21, p22 = r0, r1
;;
cmp.eq.and p21, p22 = r0, r1
cmp.eq.and p21, p23 = r2, r3 // no DV here
;;
cmp.eq.or p21, p22 = r0, r1
cmp.eq.or p21, p23 = r2, r3 // no DV here
;;
// RSE
L:
|
tactcomplabs/xbgas-binutils-gdb
| 1,153
|
gas/testsuite/gas/ia64/tls.s
|
.section ".tdata", "awT", @progbits
.align 16
.global x#, y#, z#, a#, b#, c#
.protected a#, b#, c#
.type x#,@object
.size x#,4
x: data4 1
.type y#,@object
.size y#,4
y: data4 2
.type z#,@object
.size z#,4
z: data4 3
.align 8
.type a#,@object
.size a#,8
a: data8 4
.type b#,@object
.size b#,8
b: data8 5
.type c#,@object
.size c#,1
c: data1 6
.text
.align 16
.global foo#
.proc foo#
foo:
.prologue
alloc r36 = ar.pfs, 0, 5, 3, 0
.body
addl loc0 = @ltoff(@tprel(x)), gp;;
ld8 loc0 = [loc0];;
add loc1 = loc0, r13;;
mov r2 = r13;;
addl loc1 = @tprel(y), r2;;
mov loc0 = gp
addl out0 = @ltoff(@dtpmod(z)), gp
addl out1 = @ltoff(@dtprel(z)), gp;;
ld8 out0 = [out0]
ld8 out1 = [out1]
br.call.sptk.many b0 = __tls_get_addr;;
mov gp = loc0;;
addl out0 = @ltoff(@dtpmod(a)), gp
addl out1 = @dtprel(a), r0;;
ld8 out0 = [out0]
br.call.sptk.many b0 = __tls_get_addr;;
mov gp = loc0;;
addl out0 = @ltoff(@dtpmod(b)), gp
mov out1 = r0;;
ld8 out0 = [out0]
br.call.sptk.many b0 = __tls_get_addr;;
mov gp = loc0
mov r2 = ret0;;
addl loc1 = @dtprel(b), r2
addl loc2 = @dtprel(c), r2
br.ret.sptk.many b0
.endp foo#
|
tactcomplabs/xbgas-binutils-gdb
| 18,157
|
gas/testsuite/gas/ia64/opc-b.s
|
.L0:
{ .bbb; nop.b 0
(p2) br.cond.sptk .L1
br.cond.sptk .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.sptk.clr .L1
br.cond.sptk.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.sptk.few .L1
br.cond.sptk.few .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.sptk.few.clr .L1
br.cond.sptk.few.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.sptk.many .L1
br.cond.sptk.many .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.sptk.many.clr .L1
br.cond.sptk.many.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.spnt .L1
br.cond.spnt .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.spnt.clr .L1
br.cond.spnt.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.spnt.few .L1
br.cond.spnt.few .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.spnt.few.clr .L1
br.cond.spnt.few.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.spnt.many .L1
br.cond.spnt.many .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.spnt.many.clr .L1
br.cond.spnt.many.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dptk .L1
br.cond.dptk .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dptk.clr .L1
br.cond.dptk.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dptk.few .L1
br.cond.dptk.few .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dptk.few.clr .L1
br.cond.dptk.few.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dptk.many .L1
br.cond.dptk.many .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dptk.many.clr .L1
br.cond.dptk.many.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dpnt .L1
br.cond.dpnt .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dpnt.clr .L1
br.cond.dpnt.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dpnt.few .L1
br.cond.dpnt.few .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dpnt.few.clr .L1
br.cond.dpnt.few.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dpnt.many .L1
br.cond.dpnt.many .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dpnt.many.clr .L1
br.cond.dpnt.many.clr .L0
;; }
{ .bbb; (p2) br.wexit.sptk .L1 ;; }
{ .bbb; br.wexit.sptk .L1 ;; }
{ .bbb; (p2) br.wexit.sptk.clr .L1 ;; }
{ .bbb; br.wexit.sptk.clr .L1 ;; }
{ .bbb; (p2) br.wexit.sptk.few .L1 ;; }
{ .bbb; br.wexit.sptk.few .L1 ;; }
{ .bbb; (p2) br.wexit.sptk.few.clr .L1 ;; }
{ .bbb; br.wexit.sptk.few.clr .L1 ;; }
{ .bbb; (p2) br.wexit.sptk.many .L1 ;; }
{ .bbb; br.wexit.sptk.many .L1 ;; }
{ .bbb; (p2) br.wexit.sptk.many.clr .L1 ;; }
{ .bbb; br.wexit.sptk.many.clr .L1 ;; }
{ .bbb; (p2) br.wexit.spnt .L1 ;; }
{ .bbb; br.wexit.spnt .L1 ;; }
{ .bbb; (p2) br.wexit.spnt.clr .L1 ;; }
{ .bbb; br.wexit.spnt.clr .L1 ;; }
{ .bbb; (p2) br.wexit.spnt.few .L1 ;; }
{ .bbb; br.wexit.spnt.few .L1 ;; }
{ .bbb; (p2) br.wexit.spnt.few.clr .L1 ;; }
{ .bbb; br.wexit.spnt.few.clr .L1 ;; }
{ .bbb; (p2) br.wexit.spnt.many .L1 ;; }
{ .bbb; br.wexit.spnt.many .L1 ;; }
{ .bbb; (p2) br.wexit.spnt.many.clr .L1 ;; }
{ .bbb; br.wexit.spnt.many.clr .L1 ;; }
{ .bbb; (p2) br.wexit.dptk .L1 ;; }
{ .bbb; br.wexit.dptk .L1 ;; }
{ .bbb; (p2) br.wexit.dptk.clr .L1 ;; }
{ .bbb; br.wexit.dptk.clr .L1 ;; }
{ .bbb; (p2) br.wexit.dptk.few .L1 ;; }
{ .bbb; br.wexit.dptk.few .L1 ;; }
{ .bbb; (p2) br.wexit.dptk.few.clr .L1 ;; }
{ .bbb; br.wexit.dptk.few.clr .L1 ;; }
{ .bbb; (p2) br.wexit.dptk.many .L1 ;; }
{ .bbb; br.wexit.dptk.many .L1 ;; }
{ .bbb; (p2) br.wexit.dptk.many.clr .L1 ;; }
{ .bbb; br.wexit.dptk.many.clr .L1 ;; }
{ .bbb; (p2) br.wexit.dpnt .L1 ;; }
{ .bbb; br.wexit.dpnt .L1 ;; }
{ .bbb; (p2) br.wexit.dpnt.clr .L1 ;; }
{ .bbb; br.wexit.dpnt.clr .L1 ;; }
{ .bbb; (p2) br.wexit.dpnt.few .L1 ;; }
{ .bbb; br.wexit.dpnt.few .L1 ;; }
{ .bbb; (p2) br.wexit.dpnt.few.clr .L1 ;; }
{ .bbb; br.wexit.dpnt.few.clr .L1 ;; }
{ .bbb; (p2) br.wexit.dpnt.many .L1 ;; }
{ .bbb; br.wexit.dpnt.many .L1 ;; }
{ .bbb; (p2) br.wexit.dpnt.many.clr .L1 ;; }
{ .bbb; br.wexit.dpnt.many.clr .L1 ;; }
{ .bbb; (p2) br.wtop.sptk .L1 ;; }
{ .bbb; br.wtop.sptk .L1 ;; }
{ .bbb; (p2) br.wtop.sptk.clr .L1 ;; }
{ .bbb; br.wtop.sptk.clr .L1 ;; }
{ .bbb; (p2) br.wtop.sptk.few .L1 ;; }
{ .bbb; br.wtop.sptk.few .L1 ;; }
{ .bbb; (p2) br.wtop.sptk.few.clr .L1 ;; }
{ .bbb; br.wtop.sptk.few.clr .L1 ;; }
{ .bbb; (p2) br.wtop.sptk.many .L1 ;; }
{ .bbb; br.wtop.sptk.many .L1 ;; }
{ .bbb; (p2) br.wtop.sptk.many.clr .L1 ;; }
{ .bbb; br.wtop.sptk.many.clr .L1 ;; }
{ .bbb; (p2) br.wtop.spnt .L1 ;; }
{ .bbb; br.wtop.spnt .L1 ;; }
{ .bbb; (p2) br.wtop.spnt.clr .L1 ;; }
{ .bbb; br.wtop.spnt.clr .L1 ;; }
{ .bbb; (p2) br.wtop.spnt.few .L1 ;; }
{ .bbb; br.wtop.spnt.few .L1 ;; }
{ .bbb; (p2) br.wtop.spnt.few.clr .L1 ;; }
{ .bbb; br.wtop.spnt.few.clr .L1 ;; }
{ .bbb; (p2) br.wtop.spnt.many .L1 ;; }
{ .bbb; br.wtop.spnt.many .L1 ;; }
{ .bbb; (p2) br.wtop.spnt.many.clr .L1 ;; }
{ .bbb; br.wtop.spnt.many.clr .L1 ;; }
{ .bbb; (p2) br.wtop.dptk .L1 ;; }
{ .bbb; br.wtop.dptk .L1 ;; }
{ .bbb; (p2) br.wtop.dptk.clr .L1 ;; }
{ .bbb; br.wtop.dptk.clr .L1 ;; }
{ .bbb; (p2) br.wtop.dptk.few .L1 ;; }
{ .bbb; br.wtop.dptk.few .L1 ;; }
{ .bbb; (p2) br.wtop.dptk.few.clr .L1 ;; }
{ .bbb; br.wtop.dptk.few.clr .L1 ;; }
{ .bbb; (p2) br.wtop.dptk.many .L1 ;; }
{ .bbb; br.wtop.dptk.many .L1 ;; }
{ .bbb; (p2) br.wtop.dptk.many.clr .L1 ;; }
{ .bbb; br.wtop.dptk.many.clr .L1 ;; }
{ .bbb; (p2) br.wtop.dpnt .L1 ;; }
{ .bbb; br.wtop.dpnt .L1 ;; }
{ .bbb; (p2) br.wtop.dpnt.clr .L1 ;; }
{ .bbb; br.wtop.dpnt.clr .L1 ;; }
{ .bbb; (p2) br.wtop.dpnt.few .L1 ;; }
{ .bbb; br.wtop.dpnt.few .L1 ;; }
{ .bbb; (p2) br.wtop.dpnt.few.clr .L1 ;; }
{ .bbb; br.wtop.dpnt.few.clr .L1 ;; }
{ .bbb; (p2) br.wtop.dpnt.many .L1 ;; }
{ .bbb; br.wtop.dpnt.many .L1 ;; }
{ .bbb; (p2) br.wtop.dpnt.many.clr .L1 ;; }
{ .bbb; br.wtop.dpnt.many.clr .L1 ;; }
{ .bbb; br.cloop.sptk .L1 ;; }
{ .bbb; br.cloop.sptk.clr .L1 ;; }
{ .bbb; br.cloop.sptk.few .L1 ;; }
{ .bbb; br.cloop.sptk.few.clr .L1 ;; }
{ .bbb; br.cloop.sptk.many .L1 ;; }
{ .bbb; br.cloop.sptk.many.clr .L1 ;; }
{ .bbb; br.cloop.spnt .L1 ;; }
{ .bbb; br.cloop.spnt.clr .L1 ;; }
{ .bbb; br.cloop.spnt.few .L1 ;; }
{ .bbb; br.cloop.spnt.few.clr .L1 ;; }
{ .bbb; br.cloop.spnt.many .L1 ;; }
{ .bbb; br.cloop.spnt.many.clr .L1 ;; }
{ .bbb; br.cloop.dptk .L1 ;; }
{ .bbb; br.cloop.dptk.clr .L1 ;; }
{ .bbb; br.cloop.dptk.few .L1 ;; }
{ .bbb; br.cloop.dptk.few.clr .L1 ;; }
{ .bbb; br.cloop.dptk.many .L1 ;; }
{ .bbb; br.cloop.dptk.many.clr .L1 ;; }
{ .bbb; br.cloop.dpnt .L1 ;; }
{ .bbb; br.cloop.dpnt.clr .L1 ;; }
{ .bbb; br.cloop.dpnt.few .L1 ;; }
{ .bbb; br.cloop.dpnt.few.clr .L1 ;; }
{ .bbb; br.cloop.dpnt.many .L1 ;; }
{ .bbb; br.cloop.dpnt.many.clr .L1 ;; }
{ .bbb; br.cexit.sptk .L1 ;; }
{ .bbb; br.cexit.sptk.clr .L1 ;; }
{ .bbb; br.cexit.sptk.few .L1 ;; }
{ .bbb; br.cexit.sptk.few.clr .L1 ;; }
{ .bbb; br.cexit.sptk.many .L1 ;; }
{ .bbb; br.cexit.sptk.many.clr .L1 ;; }
{ .bbb; br.cexit.spnt .L1 ;; }
{ .bbb; br.cexit.spnt.clr .L1 ;; }
{ .bbb; br.cexit.spnt.few .L1 ;; }
{ .bbb; br.cexit.spnt.few.clr .L1 ;; }
{ .bbb; br.cexit.spnt.many .L1 ;; }
{ .bbb; br.cexit.spnt.many.clr .L1 ;; }
{ .bbb; br.cexit.dptk .L1 ;; }
{ .bbb; br.cexit.dptk.clr .L1 ;; }
{ .bbb; br.cexit.dptk.few .L1 ;; }
{ .bbb; br.cexit.dptk.few.clr .L1 ;; }
{ .bbb; br.cexit.dptk.many .L1 ;; }
{ .bbb; br.cexit.dptk.many.clr .L1 ;; }
{ .bbb; br.cexit.dpnt .L1 ;; }
{ .bbb; br.cexit.dpnt.clr .L1 ;; }
{ .bbb; br.cexit.dpnt.few .L1 ;; }
{ .bbb; br.cexit.dpnt.few.clr .L1 ;; }
{ .bbb; br.cexit.dpnt.many .L1 ;; }
{ .bbb; br.cexit.dpnt.many.clr .L1 ;; }
{ .bbb; br.ctop.sptk .L1 ;; }
{ .bbb; br.ctop.sptk.clr .L1 ;; }
{ .bbb; br.ctop.sptk.few .L1 ;; }
{ .bbb; br.ctop.sptk.few.clr .L1 ;; }
{ .bbb; br.ctop.sptk.many .L1 ;; }
{ .bbb; br.ctop.sptk.many.clr .L1 ;; }
{ .bbb; br.ctop.spnt .L1 ;; }
{ .bbb; br.ctop.spnt.clr .L1 ;; }
{ .bbb; br.ctop.spnt.few .L1 ;; }
{ .bbb; br.ctop.spnt.few.clr .L1 ;; }
{ .bbb; br.ctop.spnt.many .L1 ;; }
{ .bbb; br.ctop.spnt.many.clr .L1 ;; }
{ .bbb; br.ctop.dptk .L1 ;; }
{ .bbb; br.ctop.dptk.clr .L1 ;; }
{ .bbb; br.ctop.dptk.few .L1 ;; }
{ .bbb; br.ctop.dptk.few.clr .L1 ;; }
{ .bbb; br.ctop.dptk.many .L1 ;; }
{ .bbb; br.ctop.dptk.many.clr .L1 ;; }
{ .bbb; br.ctop.dpnt .L1 ;; }
{ .bbb; br.ctop.dpnt.clr .L1 ;; }
{ .bbb; br.ctop.dpnt.few .L1 ;; }
{ .bbb; br.ctop.dpnt.few.clr .L1 ;; }
{ .bbb; br.ctop.dpnt.many .L1 ;; }
{ .bbb; br.ctop.dpnt.many.clr .L1 ;; }
{ .bbb; nop.b 0
(p2) br.call.sptk b0 = .L1
br.call.sptk b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.sptk.clr b0 = .L1
br.call.sptk.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.sptk.few b0 = .L1
br.call.sptk.few b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.sptk.few.clr b0 = .L1
br.call.sptk.few.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.sptk.many b0 = .L1
br.call.sptk.many b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.sptk.many.clr b0 = .L1
br.call.sptk.many.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.spnt b0 = .L1
br.call.spnt b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.spnt.clr b0 = .L1
br.call.spnt.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.spnt.few b0 = .L1
br.call.spnt.few b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.spnt.few.clr b0 = .L1
br.call.spnt.few.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.spnt.many b0 = .L1
br.call.spnt.many b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.spnt.many.clr b0 = .L1
br.call.spnt.many.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dptk b0 = .L1
br.call.dptk b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dptk.clr b0 = .L1
br.call.dptk.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dptk.few b0 = .L1
br.call.dptk.few b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dptk.few.clr b0 = .L1
br.call.dptk.few.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dptk.many b0 = .L1
br.call.dptk.many b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dptk.many.clr b0 = .L1
br.call.dptk.many.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dpnt b0 = .L1
br.call.dpnt b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dpnt.clr b0 = .L1
br.call.dpnt.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dpnt.few b0 = .L1
br.call.dpnt.few b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dpnt.few.clr b0 = .L1
br.call.dpnt.few.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dpnt.many b0 = .L1
br.call.dpnt.many b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dpnt.many.clr b0 = .L1
br.call.dpnt.many.clr b0 = .L0
;; }
{ .bbb; nop.b 0;
(p2) br.cond.sptk b2
br.cond.sptk b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.sptk.clr b2
br.cond.sptk.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.sptk.few b2
br.cond.sptk.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.sptk.few.clr b2
br.cond.sptk.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.sptk.many b2
br.cond.sptk.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.sptk.many.clr b2
br.cond.sptk.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.spnt b2
br.cond.spnt b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.spnt.clr b2
br.cond.spnt.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.spnt.few b2
br.cond.spnt.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.spnt.few.clr b2
br.cond.spnt.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.spnt.many b2
br.cond.spnt.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.spnt.many.clr b2
br.cond.spnt.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dptk b2
br.cond.dptk b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dptk.clr b2
br.cond.dptk.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dptk.few b2
br.cond.dptk.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dptk.few.clr b2
br.cond.dptk.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dptk.many b2
br.cond.dptk.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dptk.many.clr b2
br.cond.dptk.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dpnt b2
br.cond.dpnt b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dpnt.clr b2
br.cond.dpnt.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dpnt.few b2
br.cond.dpnt.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dpnt.few.clr b2
br.cond.dpnt.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dpnt.many b2
br.cond.dpnt.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dpnt.many.clr b2
br.cond.dpnt.many.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.sptk b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.sptk.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.sptk.few b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.sptk.few.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.sptk.many b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.sptk.many.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.spnt b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.spnt.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.spnt.few b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.spnt.few.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.spnt.many b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.spnt.many.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dptk b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dptk.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dptk.few b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dptk.few.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dptk.many b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dptk.many.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dpnt b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dpnt.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dpnt.few b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dpnt.few.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dpnt.many b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dpnt.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.sptk b2
br.ret.sptk b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.sptk.clr b2
br.ret.sptk.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.sptk.few b2
br.ret.sptk.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.sptk.few.clr b2
br.ret.sptk.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.sptk.many b2
br.ret.sptk.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.sptk.many.clr b2
br.ret.sptk.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.spnt b2
br.ret.spnt b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.spnt.clr b2
br.ret.spnt.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.spnt.few b2
br.ret.spnt.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.spnt.few.clr b2
br.ret.spnt.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.spnt.many b2
br.ret.spnt.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.spnt.many.clr b2
br.ret.spnt.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dptk b2
br.ret.dptk b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dptk.clr b2
br.ret.dptk.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dptk.few b2
br.ret.dptk.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dptk.few.clr b2
br.ret.dptk.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dptk.many b2
br.ret.dptk.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dptk.many.clr b2
br.ret.dptk.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dpnt b2
br.ret.dpnt b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dpnt.clr b2
br.ret.dpnt.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dpnt.few b2
br.ret.dpnt.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dpnt.few.clr b2
br.ret.dpnt.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dpnt.many b2
br.ret.dpnt.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dpnt.many.clr b2
br.ret.dpnt.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.sptk b0 = b2
br.call.sptk b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.sptk.clr b0 = b2
br.call.sptk.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.sptk.few b0 = b2
br.call.sptk.few b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.sptk.few.clr b0 = b2
br.call.sptk.few.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.sptk.many b0 = b2
br.call.sptk.many b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.sptk.many.clr b0 = b2
br.call.sptk.many.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.spnt b0 = b2
br.call.spnt b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.spnt.clr b0 = b2
br.call.spnt.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.spnt.few b0 = b2
br.call.spnt.few b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.spnt.few.clr b0 = b2
br.call.spnt.few.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.spnt.many b0 = b2
br.call.spnt.many b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.spnt.many.clr b0 = b2
br.call.spnt.many.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dptk b0 = b2
br.call.dptk b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dptk.clr b0 = b2
br.call.dptk.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dptk.few b0 = b2
br.call.dptk.few b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dptk.few.clr b0 = b2
br.call.dptk.few.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dptk.many b0 = b2
br.call.dptk.many b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dptk.many.clr b0 = b2
br.call.dptk.many.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dpnt b0 = b2
br.call.dpnt b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dpnt.clr b0 = b2
br.call.dpnt.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dpnt.few b0 = b2
br.call.dpnt.few b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dpnt.few.clr b0 = b2
br.call.dpnt.few.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dpnt.many b0 = b2
br.call.dpnt.many b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dpnt.many.clr b0 = b2
br.call.dpnt.many.clr b0 = b2
;; }
{ .bbb; break.b 0; nop.b 0
brp.sptk .L0, .L2
;; }
{ .bbb; break.b 0; nop.b 0
brp.sptk.imp .L0, .L2
;; }
.L2:
{ .bbb; break.b 0; nop.b 0
brp.loop .L0, .L3
;; }
{ .bbb; break.b 0; nop.b 0
brp.loop.imp .L0, .L3
;; }
.L3:
{ .bbb; break.b 0; nop.b 0
brp.dptk .L0, .L4
;; }
{ .bbb; break.b 0; nop.b 0
brp.dptk.imp .L0, .L4
;; }
.L4:
{ .bbb; break.b 0; nop.b 0
brp.exit .L0, .L5
;; }
{ .bbb; break.b 0; nop.b 0
brp.exit.imp .L0, .L5
;; }
.L5:
{ .bbb; break.b 0; nop.b 0
brp.sptk b3, .L6
;; }
{ .bbb; break.b 0; nop.b 0
brp.sptk.imp b3, .L6
;; }
.L6:
{ .bbb; break.b 0; nop.b 0
brp.dptk b3, .L7
;; }
{ .bbb; break.b 0; nop.b 0
brp.dptk.imp b3, .L7
;; }
.L7:
{ .bbb; break.b 0; nop.b 0
brp.ret.sptk b3, .L8
;; }
{ .bbb; break.b 0; nop.b 0
brp.ret.sptk.imp b3, .L8
;; }
.L8:
{ .bbb; break.b 0; nop.b 0
brp.ret.dptk b3, .L9
;; }
{ .bbb; break.b 0; nop.b 0
brp.ret.dptk.imp b3, .L9
;; }
.L9:
.space 5888
{ .bbb; nop.b 0; nop.b 0; cover ;; }
{ .bbb; nop.b 0; nop.b 0; clrrrb ;; }
{ .bbb; nop.b 0; nop.b 0; clrrrb.pr ;; }
{ .bbb; nop.b 0; nop.b 0; rfi ;; }
{ .bbb; nop.b 0; nop.b 0; bsw.0 ;; }
{ .bbb; nop.b 0; nop.b 0; bsw.1 ;; }
{ .bbb; nop.b 0; nop.b 0; epc ;; }
.L1:
# instructions added by SDM2.1:
break.b 0x1ffff
hint.b @pause
hint.b 0x1ffff
nop.b 0x1ffff
# instructions added by SDM2.2:
vmsw.0
vmsw.1
|
tactcomplabs/xbgas-binutils-gdb
| 7,884
|
gas/testsuite/gas/ia64/dv-raw-err.s
|
//
// Detect RAW violations. Cases taken from DV tables.
// This test is by no means complete but tries to hit the things that are
// likely to be missed.
//
.text
.explicit
// AR[BSP]
mov ar.bspstore = r0
mov r1 = ar.bsp
;;
// AR[BSPSTORE]
mov ar.bspstore = r2
mov r3 = ar.bspstore
;;
// AR[CCV]
mov ar.ccv = r4
cmpxchg8.acq r5 = [r6],r7,ar.ccv
;;
// AR[EC]
br.wtop.sptk L
mov r8 = ar.ec
;;
// AR[FPSR].sf0.controls
fsetc.s0 0x7f, 0x0f
fpcmp.eq.s0 f2 = f3, f4
;;
// AR[FPSR].sf1.controls
fsetc.s1 0x7f, 0x0f
fpcmp.eq.s1 f2 = f3, f4
;;
// AR[FPSR].sf2.controls
fsetc.s2 0x7f, 0x0f
fpcmp.eq.s2 f2 = f3, f4
;;
// AR[FPSR].sf3.controls
fsetc.s3 0x7f, 0x0f
fpcmp.eq.s3 f2 = f3, f4
;;
// AR[FPSR].sf0.flags
fpcmp.eq.s0 f2 = f3, f4
fchkf.s0 L
;;
// AR[FPSR].sf1.flags
fpcmp.eq.s1 f2 = f3, f4
fchkf.s1 L
;;
// AR[FPSR].sf2.flags
fpcmp.eq.s2 f2 = f3, f4
fchkf.s2 L
;;
// AR[FPSR].sf3.flags
fpcmp.eq.s3 f2 = f3, f4
fchkf.s3 L
;;
// AR[FPSR].traps/rv
mov ar.fpsr = r0
fcmp.eq.s3 p1, p2 = f5, f6
;;
// AR[ITC]
mov ar.itc = r1
mov r2 = ar.itc
;;
// AR[RUC]
mov ar.ruc = r1
mov r2 = ar.ruc
;;
// AR[K]
mov ar.k1 = r3
br.ia.sptk b0
;;
// AR[LC]
br.cloop.sptk L
mov r4 = ar.lc
;;
// AR[PFS]
mov ar.pfs = r5
epc
// AR[RNAT]
mov ar.bspstore = r8
mov r9 = ar.rnat
;;
// AR[RSC]
mov ar.rsc = r10
mov r11 = ar.rnat
;;
// AR[UNAT]
mov ar.unat = r12
ld8.fill r13 = [r14]
;;
// AR%
// BR%
mov b0 = r0
mov r2 = b0
;;
// CFM
br.wtop.sptk L
fadd f2 = f1, f32 // read from rotating register region
;;
// CR[CMCV]
mov cr.cmcv = r1
mov r2 = cr.cmcv
;;
// CR[DCR]
mov cr.dcr = r3
ld8.s r4 = [r5]
;;
// CR[EOI]
// CR[GPTA]
mov cr.gpta = r6
thash r7 = r8
;;
srlz.d
// CR[IFA]
mov cr.ifa = r9
itc.i r10
;;
// CR[IFS]
mov cr.ifs = r11
mov r12 = cr.ifs
;;
// CR[IHA]
mov cr.iha = r13
mov r14 = cr.iha
;;
// CR[IIB%]
mov cr.iib0 = r15
mov r16 = cr.iib0
;;
mov cr.iib1 = r15
mov r16 = cr.iib1
;;
// CR[IIM]
mov cr.iim = r15
mov r16 = cr.iim
;;
// CR[IIP]
mov cr.iip = r17
rfi
;;
// CR[IIPA]
mov cr.iipa = r19
mov r20 = cr.iipa
;;
// CR[IPSR]
mov cr.ipsr = r21
rfi
;;
// CR[IRR%]
mov r22 = cr.ivr
mov r23 = cr.irr0
;;
// CR[ISR]
mov cr.isr = r24
mov r25 = cr.isr
;;
// CR[ITIR]
mov cr.itir = r26
itc.d r27
;;
// CR[ITM]
mov cr.itm = r28
mov r29 = cr.itm
;;
// CR[ITV]
mov cr.itv = r0
mov r1 = cr.itv
;;
// CR[IVR] (all writes are implicit in other resource usage)
// CR[IVA]
mov cr.iva = r0
mov r1 = cr.iva
;;
// CR[LID]
mov cr.lid = r0
mov r1 = cr.lid
;;
srlz.d
// CR[LRR%]
mov cr.lrr0 = r0
mov r1 = cr.lrr0
;;
// CR[PMV]
mov cr.pmv = r0
mov r1 = cr.pmv
;;
// CR[PTA]
mov cr.pta = r0
thash r1 = r2
;;
// CR[TPR]
mov cr.tpr = r0
mov r1 = cr.ivr // data
;;
srlz.d
mov cr.tpr = r2
mov psr.l = r3 // other
;;
srlz.d
// DBR#
mov dbr[r0] = r1
mov r2 = dbr[r3]
;;
srlz.d
mov dbr[r4] = r5
probe.r r6 = r7, r8
;;
srlz.d
// DTC
ptc.e r0
fc r1
;;
srlz.d
itr.i itr[r2] = r3
ptc.e r4
;;
// DTC_LIMIT/ITC_LIMIT
ptc.g r0, r1 // NOTE: GAS automatically emits stops after
ptc.ga r2, r3 // ptc.g/ptc.ga, so this conflict is no
;; // longer possible in GAS-generated assembly
srlz.d
// DTR
itr.d dtr[r0] = r1
tak r2 = r3
;;
srlz.d
ptr.d r4, r5
tpa r6 = r7
;;
srlz.d
// FR%
ldfs.c.clr f2 = [r1]
mov f3 = f2 // no DV here
;;
mov f4 = f5
mov f6 = f4
;;
// GR%
ld8.c.clr r1 = [r1] // no DV here
mov r2 = r0
;;
mov r3 = r4
mov r5 = r3
;;
// IBR#
mov ibr[r0] = r1
mov r2 = ibr[r3]
;;
// InService
mov cr.eoi = r0
mov r1 = cr.ivr
;;
srlz.d
mov r2 = cr.ivr
mov r3 = cr.ivr // several DVs
;;
mov cr.eoi = r4
mov cr.eoi = r5
;;
// ITC
ptc.e r0
epc
;;
srlz.i
;;
// ITC_LIMIT (see DTC_LIMIT)
// ITR
itr.i itr[r0] = r1
epc
;;
srlz.i
;;
// PKR#
mov pkr[r0] = r1
probe.r r2 = r3, r4
;;
srlz.d
mov pkr[r5] = r6
mov r7 = pkr[r8]
;;
srlz.d
// PMC#
mov pmc[r0] = r1
mov r2 = pmc[r3]
;;
srlz.d
mov pmc[r4] = r5
mov r6 = pmd[r7]
;;
srlz.d
// PMD#
mov pmd[r0] = r1
mov r2 = pmd[r3]
;;
// PR%, 1 - 15
cmp.eq p1, p2 = r0, r1 // pr-writer/pr-reader-nobr-nomovpr
(p1) add r2 = r3, r4
;;
mov pr = r5, 0xffff // mov-to-pr-allreg/pr-reader-nobr-nomovpr
(p2) add r6 = r7, r8
;;
fcmp.eq p5, p6 = f2, f3 // pr-writer-fp/pr-reader-br
(p5) br.cond.sptk b0
;;
cmp.eq p7, p8 = r11, r12
(p7) br.cond.sptk b1 // no DV here
;;
// PR63
br.wtop.sptk L
(p63) add r3 = r1, r2
;;
fcmp.eq p62, p63 = f2, f3
(p63) add r3 = r4, r5
;;
cmp.eq p62, p63 = r6, r7 // no DV here
(p63) br.cond.sptk b0
;;
// PSR.ac
rum (1<<3)
ld8 r2 = [r1]
;;
// PSR.be
rum (1<<1)
ld8 r2 = [r1]
;;
// PSR.bn
bsw.0
mov r1 = r15 // no DV here, since gr < 16
;;
bsw.1 // GAS automatically emits a stop after bsw.n
mov r1 = r16 // so this conflict is avoided
;;
// PSR.cpl
epc
st8 [r0] = r1
;;
epc
mov r2 = ar.itc
;;
epc
mov ar.itc = r3
;;
epc
mov r2 = ar.ruc
;;
epc
mov ar.ruc = r3
;;
epc
mov ar.rsc = r4
;;
epc
mov ar.k0 = r5
;;
epc
mov r6 = pmd[r7]
;;
epc
mov ar.bsp = r8 // no DV here
;;
epc
mov r9 = ar.bsp // no DV here
;;
epc
mov cr.ifa = r10 // any mov-to/from-cr is a DV
;;
epc
mov r11 = cr.eoi // any mov-to/from-cr is a DV
;;
// PSR.da (rfi is the only writer)
// PSR.db (also ac,be,dt,pk)
mov psr.l = r0
ld8 r1 = [r2]
;;
srlz.d
// PSR.dd (rfi is the only writer)
// PSR.dfh
mov psr.l = r0
mov f64 = f65
;;
srlz.d
// PSR.dfl
mov psr.l = r0
mov f3 = f4
;;
srlz.d
// PSR.di
rsm (1<<22)
mov r1 = psr
;;
// PSR.dt
rsm (1<<17)
ld8 r1 = [r1]
;;
// PSR.ed (rfi is the only writer)
// PSR.i
ssm (1<<14)
mov r1 = psr
;;
// PSR.ia (no DV semantics)
// PSR.ic
ssm (1<<13)
mov r1 = psr
;;
srlz.d
rsm (1<<13)
mov r1 = cr.itir
;;
srlz.d
rsm (1<<13)
mov r1 = cr.irr0 // no DV here
;;
srlz.d
// PSR.id (rfi is the only writer)
// PSR.is (br.ia and rfi are the only writers)
// PSR.it (rfi is the only writer)
// PSR.lp
mov psr.l = r0
br.ret.sptk b0
;;
// PSR.mc (rfi is the only writer)
// PSR.mfh
mov f32 = f33
mov r1 = psr
;;
// PSR.mfl
mov f2 = f3
mov r1 = psr
;;
// PSR.pk
rsm (1<<15)
ld8 r1 = [r1]
;;
rsm (1<<15)
mov r2 = psr
;;
// PSR.pp
rsm (1<<21)
mov r1 = psr
;;
// PSR.ri (no DV semantics)
// PSR.rt
mov psr.l = r0
flushrs
;;
srlz.d
// PSR.si
rsm (1<<23)
mov r1 = ar.itc
;;
rsm (1<<23)
mov r1 = ar.ruc
;;
ssm (1<<23)
mov r1 = ar.ec // no DV here
;;
// PSR.sp
ssm (1<<20)
mov r1 = pmd[r1]
;;
ssm (1<<20)
rum 0xff
;;
ssm (1<<20)
mov r1 = rr[r1]
;;
// PSR.ss (rfi is the only writer)
// PSR.tb
mov psr.l = r0
chk.s r0, L
;;
// PSR.up
rsm (1<<2)
mov r1 = psr.um
;;
srlz.d
// RR#
mov rr[r0] = r1
ld8 r2 = [r0] // data
;;
mov rr[r4] = r5
mov r6 = rr[r7] // impliedf
;;
srlz.d
;;
// RSE
// GR%, additional cases
// addl
mov r2 = r32
addl r3 = 12345, r2 // impliedf, IA64_OPND_R3_2
;;
// postinc
ld8 r2 = [r32], 8
mov r8 = r32 // impliedf
;;
// PR%, 16 - 62
cmp.eq p21, p22 = r0, r1 // pr-writer/pr-reader-nobr-nomovpr
(p21) add r2 = r3, r4
;;
mov pr = r5, 0x1ffff // mov-to-pr-allreg/pr-reader-nobr-nomovpr
(p22) add r6 = r7, r8
;;
mov pr.rot = 0xffff0000 // mov-to-pr-rotreg/pr-reader-nobr-nomovpr
(p23) add r9 = r10, r11
;;
fcmp.eq p25, p26 = f2, f3 // pr-writer-fp/pr-reader-br
(p25) br.cond.sptk b0
;;
cmp.eq p27, p28 = r11, r12
(p27) br.cond.sptk b1 // no DV here
;;
// postinc
st8 [r6] = r8, 16
add r7 = 8, r6 // impliedf
;;
ldfd f14 = [r6], 16
add r7 = 8, r6 // impliedf
;;
stfd [r6] = f14, 16
add r7 = r8, r6
;;
add r6 = 8, r7
ld8 r8 = [r6], 16 // impliedf, WAW
;;
add r6 = 8, r7
ldfd f14 = [r6], 16 // impliedf, WAW
;;
L:
br.ret.sptk rp
// PSR.vm. New in SDM 2.2
vmsw.0
ld8 r2 = [r1]
;;
|
tactcomplabs/xbgas-binutils-gdb
| 39,967
|
gas/testsuite/gas/ia64/regs.s
|
.text
.type _start,@function
_start:
// Fixed and stacked integer registers.
{ .mii; mov r1 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r2 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r3 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r4 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r5 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r6 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r7 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r8 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r9 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r10 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r11 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r12 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r13 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r14 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r15 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r16 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r17 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r18 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r19 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r20 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r21 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r22 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r23 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r24 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r25 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r26 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r27 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r28 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r29 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r30 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r31 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r32 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r33 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r34 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r35 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r36 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r37 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r38 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r39 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r40 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r41 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r42 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r43 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r44 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r45 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r46 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r47 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r48 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r49 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r50 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r51 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r52 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r53 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r54 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r55 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r56 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r57 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r58 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r59 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r60 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r61 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r62 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r63 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r64 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r65 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r66 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r67 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r68 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r69 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r70 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r71 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r72 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r73 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r74 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r75 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r76 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r77 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r78 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r79 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r80 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r81 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r82 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r83 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r84 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r85 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r86 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r87 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r88 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r89 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r90 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r91 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r92 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r93 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r94 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r95 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r96 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r97 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r98 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r99 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r100 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r101 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r102 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r103 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r104 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r105 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r106 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r107 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r108 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r109 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r110 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r111 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r112 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r113 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r114 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r115 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r116 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r117 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r118 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r119 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r120 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r121 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r122 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r123 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r124 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r125 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r126 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r127 = r0; nop.i 0; nop.i 0;; }
// Alternate names for input registers
.regstk 96, 0, 0, 0
{ .mii; mov in0 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in1 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in2 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in3 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in4 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in5 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in6 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in7 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in8 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in9 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in10 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in11 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in12 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in13 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in14 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in15 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in16 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in17 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in18 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in19 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in20 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in21 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in22 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in23 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in24 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in25 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in26 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in27 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in28 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in29 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in30 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in31 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in32 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in33 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in34 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in35 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in36 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in37 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in38 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in39 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in40 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in41 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in42 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in43 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in44 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in45 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in46 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in47 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in48 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in49 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in50 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in51 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in52 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in53 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in54 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in55 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in56 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in57 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in58 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in59 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in60 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in61 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in62 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in63 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in64 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in65 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in66 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in67 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in68 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in69 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in70 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in71 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in72 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in73 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in74 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in75 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in76 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in77 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in78 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in79 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in80 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in81 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in82 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in83 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in84 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in85 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in86 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in87 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in88 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in89 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in90 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in91 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in92 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in93 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in94 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in95 = r0; nop.i 0; nop.i 0;; }
// Alternate names for output registers
.regstk 0, 0, 96, 0
{ .mii; mov out0 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out1 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out2 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out3 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out4 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out5 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out6 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out7 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out8 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out9 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out10 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out11 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out12 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out13 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out14 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out15 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out16 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out17 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out18 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out19 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out20 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out21 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out22 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out23 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out24 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out25 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out26 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out27 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out28 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out29 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out30 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out31 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out32 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out33 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out34 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out35 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out36 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out37 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out38 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out39 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out40 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out41 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out42 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out43 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out44 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out45 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out46 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out47 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out48 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out49 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out50 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out51 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out52 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out53 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out54 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out55 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out56 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out57 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out58 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out59 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out60 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out61 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out62 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out63 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out64 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out65 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out66 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out67 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out68 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out69 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out70 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out71 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out72 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out73 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out74 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out75 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out76 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out77 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out78 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out79 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out80 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out81 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out82 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out83 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out84 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out85 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out86 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out87 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out88 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out89 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out90 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out91 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out92 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out93 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out94 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out95 = r0; nop.i 0; nop.i 0;; }
// Alternate names for local registers
.regstk 0, 96, 0, 0
{ .mii; mov loc0 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc1 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc2 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc3 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc4 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc5 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc6 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc7 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc8 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc9 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc10 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc11 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc12 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc13 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc14 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc15 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc16 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc17 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc18 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc19 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc20 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc21 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc22 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc23 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc24 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc25 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc26 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc27 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc28 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc29 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc30 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc31 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc32 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc33 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc34 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc35 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc36 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc37 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc38 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc39 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc40 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc41 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc42 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc43 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc44 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc45 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc46 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc47 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc48 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc49 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc50 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc51 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc52 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc53 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc54 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc55 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc56 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc57 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc58 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc59 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc60 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc61 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc62 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc63 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc64 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc65 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc66 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc67 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc68 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc69 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc70 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc71 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc72 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc73 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc74 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc75 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc76 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc77 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc78 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc79 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc80 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc81 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc82 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc83 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc84 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc85 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc86 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc87 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc88 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc89 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc90 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc91 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc92 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc93 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc94 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc95 = r0; nop.i 0; nop.i 0;; }
// Return value registers
{ .mii; mov ret0 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov ret1 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov ret2 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov ret3 = r0; nop.i 0; nop.i 0;; }
{ .mii;
mov gp = r0
mov sp = r0
mov tp = r0;; }
// Floating point registers
{ .mfi; mov f2 = f0 ;; }
{ .mfi; mov f3 = f0 ;; }
{ .mfi; mov f4 = f0 ;; }
{ .mfi; mov f5 = f0 ;; }
{ .mfi; mov f6 = f0 ;; }
{ .mfi; mov f7 = f0 ;; }
{ .mfi; mov f8 = f0 ;; }
{ .mfi; mov f9 = f0 ;; }
{ .mfi; mov f10 = f0 ;; }
{ .mfi; mov f11 = f0 ;; }
{ .mfi; mov f12 = f0 ;; }
{ .mfi; mov f13 = f0 ;; }
{ .mfi; mov f14 = f0 ;; }
{ .mfi; mov f15 = f0 ;; }
{ .mfi; mov f16 = f0 ;; }
{ .mfi; mov f17 = f0 ;; }
{ .mfi; mov f18 = f0 ;; }
{ .mfi; mov f19 = f0 ;; }
{ .mfi; mov f20 = f0 ;; }
{ .mfi; mov f21 = f0 ;; }
{ .mfi; mov f22 = f0 ;; }
{ .mfi; mov f23 = f0 ;; }
{ .mfi; mov f24 = f0 ;; }
{ .mfi; mov f25 = f0 ;; }
{ .mfi; mov f26 = f0 ;; }
{ .mfi; mov f27 = f0 ;; }
{ .mfi; mov f28 = f0 ;; }
{ .mfi; mov f29 = f0 ;; }
{ .mfi; mov f30 = f0 ;; }
{ .mfi; mov f31 = f0 ;; }
{ .mfi; mov f32 = f0 ;; }
{ .mfi; mov f33 = f0 ;; }
{ .mfi; mov f34 = f0 ;; }
{ .mfi; mov f35 = f0 ;; }
{ .mfi; mov f36 = f0 ;; }
{ .mfi; mov f37 = f0 ;; }
{ .mfi; mov f38 = f0 ;; }
{ .mfi; mov f39 = f0 ;; }
{ .mfi; mov f40 = f0 ;; }
{ .mfi; mov f41 = f0 ;; }
{ .mfi; mov f42 = f0 ;; }
{ .mfi; mov f43 = f0 ;; }
{ .mfi; mov f44 = f0 ;; }
{ .mfi; mov f45 = f0 ;; }
{ .mfi; mov f46 = f0 ;; }
{ .mfi; mov f47 = f0 ;; }
{ .mfi; mov f48 = f0 ;; }
{ .mfi; mov f49 = f0 ;; }
{ .mfi; mov f50 = f0 ;; }
{ .mfi; mov f51 = f0 ;; }
{ .mfi; mov f52 = f0 ;; }
{ .mfi; mov f53 = f0 ;; }
{ .mfi; mov f54 = f0 ;; }
{ .mfi; mov f55 = f0 ;; }
{ .mfi; mov f56 = f0 ;; }
{ .mfi; mov f57 = f0 ;; }
{ .mfi; mov f58 = f0 ;; }
{ .mfi; mov f59 = f0 ;; }
{ .mfi; mov f60 = f0 ;; }
{ .mfi; mov f61 = f0 ;; }
{ .mfi; mov f62 = f0 ;; }
{ .mfi; mov f63 = f0 ;; }
{ .mfi; mov f64 = f0 ;; }
{ .mfi; mov f65 = f0 ;; }
{ .mfi; mov f66 = f0 ;; }
{ .mfi; mov f67 = f0 ;; }
{ .mfi; mov f68 = f0 ;; }
{ .mfi; mov f69 = f0 ;; }
{ .mfi; mov f70 = f0 ;; }
{ .mfi; mov f71 = f0 ;; }
{ .mfi; mov f72 = f0 ;; }
{ .mfi; mov f73 = f0 ;; }
{ .mfi; mov f74 = f0 ;; }
{ .mfi; mov f75 = f0 ;; }
{ .mfi; mov f76 = f0 ;; }
{ .mfi; mov f77 = f0 ;; }
{ .mfi; mov f78 = f0 ;; }
{ .mfi; mov f79 = f0 ;; }
{ .mfi; mov f80 = f0 ;; }
{ .mfi; mov f81 = f0 ;; }
{ .mfi; mov f82 = f0 ;; }
{ .mfi; mov f83 = f0 ;; }
{ .mfi; mov f84 = f0 ;; }
{ .mfi; mov f85 = f0 ;; }
{ .mfi; mov f86 = f0 ;; }
{ .mfi; mov f87 = f0 ;; }
{ .mfi; mov f88 = f0 ;; }
{ .mfi; mov f89 = f0 ;; }
{ .mfi; mov f90 = f0 ;; }
{ .mfi; mov f91 = f0 ;; }
{ .mfi; mov f92 = f0 ;; }
{ .mfi; mov f93 = f0 ;; }
{ .mfi; mov f94 = f0 ;; }
{ .mfi; mov f95 = f0 ;; }
{ .mfi; mov f96 = f0 ;; }
{ .mfi; mov f97 = f0 ;; }
{ .mfi; mov f98 = f0 ;; }
{ .mfi; mov f99 = f0 ;; }
{ .mfi; mov f100 = f0 ;; }
{ .mfi; mov f101 = f0 ;; }
{ .mfi; mov f102 = f0 ;; }
{ .mfi; mov f103 = f0 ;; }
{ .mfi; mov f104 = f0 ;; }
{ .mfi; mov f105 = f0 ;; }
{ .mfi; mov f106 = f0 ;; }
{ .mfi; mov f107 = f0 ;; }
{ .mfi; mov f108 = f0 ;; }
{ .mfi; mov f109 = f0 ;; }
{ .mfi; mov f110 = f0 ;; }
{ .mfi; mov f111 = f0 ;; }
{ .mfi; mov f112 = f0 ;; }
{ .mfi; mov f113 = f0 ;; }
{ .mfi; mov f114 = f0 ;; }
{ .mfi; mov f115 = f0 ;; }
{ .mfi; mov f116 = f0 ;; }
{ .mfi; mov f117 = f0 ;; }
{ .mfi; mov f118 = f0 ;; }
{ .mfi; mov f119 = f0 ;; }
{ .mfi; mov f120 = f0 ;; }
{ .mfi; mov f121 = f0 ;; }
{ .mfi; mov f122 = f0 ;; }
{ .mfi; mov f123 = f0 ;; }
{ .mfi; mov f124 = f0 ;; }
{ .mfi; mov f125 = f0 ;; }
{ .mfi; mov f126 = f0 ;; }
{ .mfi; mov f127 = f0 ;; }
// Floating point argument registers
{ .mfi; mov farg0 = f1 ;; }
{ .mfi; mov farg1 = f1 ;; }
{ .mfi; mov farg2 = f1 ;; }
{ .mfi; mov farg3 = f1 ;; }
{ .mfi; mov farg4 = f1 ;; }
{ .mfi; mov farg5 = f1 ;; }
{ .mfi; mov farg6 = f1 ;; }
{ .mfi; mov farg7 = f1 ;; }
// Floating point return value registers
{ .mfi; mov fret0 = f1 ;; }
{ .mfi; mov fret1 = f1 ;; }
{ .mfi; mov fret2 = f1 ;; }
{ .mfi; mov fret3 = f1 ;; }
{ .mfi; mov fret4 = f1 ;; }
{ .mfi; mov fret5 = f1 ;; }
{ .mfi; mov fret6 = f1 ;; }
{ .mfi; mov fret7 = f1 ;; }
// Predicate registers
{ .mii; (p0) mov r1 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p1) mov r2 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p2) mov r3 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p3) mov r4 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p4) mov r5 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p5) mov r6 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p6) mov r7 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p7) mov r8 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p8) mov r9 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p9) mov r10 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p10) mov r11 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p11) mov r12 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p12) mov r13 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p13) mov r14 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p14) mov r15 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p15) mov r16 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p16) mov r17 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p17) mov r18 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p18) mov r19 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p19) mov r20 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p20) mov r21 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p21) mov r22 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p22) mov r23 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p23) mov r24 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p24) mov r25 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p25) mov r26 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p26) mov r27 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p27) mov r28 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p28) mov r29 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p29) mov r30 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p30) mov r31 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p31) mov r32 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p32) mov r33 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p33) mov r34 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p34) mov r35 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p35) mov r36 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p36) mov r37 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p37) mov r38 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p38) mov r39 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p39) mov r40 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p40) mov r41 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p41) mov r42 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p42) mov r43 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p43) mov r44 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p44) mov r45 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p45) mov r46 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p46) mov r47 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p47) mov r48 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p48) mov r49 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p49) mov r50 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p50) mov r51 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p51) mov r52 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p52) mov r53 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p53) mov r54 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p54) mov r55 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p55) mov r56 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p56) mov r57 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p57) mov r58 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p58) mov r59 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p59) mov r60 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p60) mov r61 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p61) mov r62 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p62) mov r63 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p63) mov r64 = r0; nop.i 0; nop.i 0;; }
// Predicates as a unit
{ .mmi; nop.m 0; mov r1 = pr ;; }
// mov r2 = pr.rot
// Branch registers.
{ .mmi; mov b0 = r0;; }
{ .mmi; mov b1 = r0;; }
{ .mmi; mov b2 = r0;; }
{ .mmi; mov b3 = r0;; }
{ .mmi; mov b4 = r0;; }
{ .mmi; mov b5 = r0;; }
{ .mmi; mov b6 = r0;; }
{ .mmi; mov b7 = r0;; }
{ .mmi; mov rp = r0;; }
// Application registers
{ .mmi; nop.m 0; mov r1 = ar0 ;; }
{ .mmi; nop.m 0; mov r1 = ar1 ;; }
{ .mmi; nop.m 0; mov r1 = ar2 ;; }
{ .mmi; nop.m 0; mov r1 = ar3 ;; }
{ .mmi; nop.m 0; mov r1 = ar4 ;; }
{ .mmi; nop.m 0; mov r1 = ar5 ;; }
{ .mmi; nop.m 0; mov r1 = ar6 ;; }
{ .mmi; nop.m 0; mov r1 = ar7 ;; }
// { .mmi; nop.m 0; mov r1 = ar8 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar9 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar10 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar11 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar12 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar13 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar14 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar15 ;; } // reserved
{ .mmi; nop.m 0; mov r1 = ar16 ;; }
{ .mmi; nop.m 0; mov r1 = ar17 ;; }
{ .mmi; nop.m 0; mov r1 = ar18 ;; }
{ .mmi; nop.m 0; mov r1 = ar19 ;; }
// { .mmi; nop.m 0; mov r1 = ar20 ;; } // reserved
{ .mmi; nop.m 0; mov r1 = ar21 ;; }
// { .mmi; nop.m 0; mov r1 = ar22 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar23 ;; } // reserved
{ .mmi; nop.m 0; mov r1 = ar24 ;; }
{ .mmi; nop.m 0; mov r1 = ar25 ;; }
{ .mmi; nop.m 0; mov r1 = ar26 ;; }
{ .mmi; nop.m 0; mov r1 = ar27 ;; }
{ .mmi; nop.m 0; mov r1 = ar28 ;; }
{ .mmi; nop.m 0; mov r1 = ar29 ;; }
{ .mmi; nop.m 0; mov r1 = ar30 ;; }
// { .mmi; nop.m 0; mov r1 = ar31 ;; } // reserved
{ .mmi; nop.m 0; mov r1 = ar32 ;; }
// { .mmi; nop.m 0; mov r1 = ar33 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar34 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar35 ;; } // reserved
{ .mmi; nop.m 0; mov r1 = ar36 ;; }
// { .mmi; nop.m 0; mov r1 = ar37 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar38 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar39 ;; } // reserved
{ .mmi; nop.m 0; mov r1 = ar40 ;; }
// { .mmi; nop.m 0; mov r1 = ar41 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar42 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar43 ;; } // reserved
{ .mmi; nop.m 0; mov r1 = ar44 ;; }
{ .mmi; nop.m 0; mov r1 = ar45 ;; }
// { .mmi; nop.m 0; mov r1 = ar46 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar47 ;; } // reserved
{ .mmi; nop.m 0; mov r1 = ar48 ;; }
{ .mmi; nop.m 0; mov r1 = ar49 ;; }
{ .mmi; nop.m 0; mov r1 = ar50 ;; }
{ .mmi; nop.m 0; mov r1 = ar51 ;; }
{ .mmi; nop.m 0; mov r1 = ar52 ;; }
{ .mmi; nop.m 0; mov r1 = ar53 ;; }
{ .mmi; nop.m 0; mov r1 = ar54 ;; }
{ .mmi; nop.m 0; mov r1 = ar55 ;; }
{ .mmi; nop.m 0; mov r1 = ar56 ;; }
{ .mmi; nop.m 0; mov r1 = ar57 ;; }
{ .mmi; nop.m 0; mov r1 = ar58 ;; }
{ .mmi; nop.m 0; mov r1 = ar59 ;; }
{ .mmi; nop.m 0; mov r1 = ar60 ;; }
{ .mmi; nop.m 0; mov r1 = ar61 ;; }
{ .mmi; nop.m 0; mov r1 = ar62 ;; }
{ .mmi; nop.m 0; mov r1 = ar63 ;; }
{ .mmi; nop.m 0; mov r1 = ar64 ;; }
{ .mmi; nop.m 0; mov r1 = ar65 ;; }
{ .mmi; nop.m 0; mov r1 = ar66 ;; }
// { .mmi; nop.m 0; mov r1 = ar67 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar68 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar69 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar70 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar71 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar72 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar73 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar74 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar75 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar76 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar77 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar78 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar79 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar80 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar81 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar82 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar83 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar84 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar85 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar86 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar87 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar88 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar89 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar90 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar91 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar92 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar93 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar94 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar95 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar96 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar97 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar98 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar99 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar100 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar101 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar102 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar103 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar104 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar105 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar106 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar107 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar108 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar109 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar110 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar111 ;; } // reserved
{ .mmi; nop.m 0; mov r1 = ar112 ;; }
{ .mmi; nop.m 0; mov r1 = ar113 ;; }
{ .mmi; nop.m 0; mov r1 = ar114 ;; }
{ .mmi; nop.m 0; mov r1 = ar115 ;; }
{ .mmi; nop.m 0; mov r1 = ar116 ;; }
{ .mmi; nop.m 0; mov r1 = ar117 ;; }
{ .mmi; nop.m 0; mov r1 = ar118 ;; }
{ .mmi; nop.m 0; mov r1 = ar119 ;; }
{ .mmi; nop.m 0; mov r1 = ar120 ;; }
{ .mmi; nop.m 0; mov r1 = ar121 ;; }
{ .mmi; nop.m 0; mov r1 = ar122 ;; }
{ .mmi; nop.m 0; mov r1 = ar123 ;; }
{ .mmi; nop.m 0; mov r1 = ar124 ;; }
{ .mmi; nop.m 0; mov r1 = ar125 ;; }
{ .mmi; nop.m 0; mov r1 = ar126 ;; }
{ .mmi; nop.m 0; mov r1 = ar127 ;; }
// Application registers by name
{ .mmi; nop.m 0; mov r1 = ar.k0 ;;}
{ .mmi; nop.m 0; mov r1 = ar.k1 ;;}
{ .mmi; nop.m 0; mov r1 = ar.k2 ;;}
{ .mmi; nop.m 0; mov r1 = ar.k3 ;;}
{ .mmi; nop.m 0; mov r1 = ar.k4 ;;}
{ .mmi; nop.m 0; mov r1 = ar.k5 ;;}
{ .mmi; nop.m 0; mov r1 = ar.k6 ;;}
{ .mmi; nop.m 0; mov r1 = ar.k7 ;;}
{ .mmi; nop.m 0; mov r1 = ar.rsc ;; }
{ .mmi; nop.m 0; mov r1 = ar.bsp ;; }
{ .mmi; nop.m 0; mov r1 = ar.bspstore ;; }
{ .mmi; nop.m 0; mov r1 = ar.rnat ;; }
{ .mmi; nop.m 0; mov r1 = ar.ccv ;; }
{ .mmi; nop.m 0; mov r1 = ar.unat ;; }
{ .mmi; nop.m 0; mov r1 = ar.fpsr ;; }
{ .mmi; nop.m 0; mov r1 = ar.itc ;; }
{ .mmi; nop.m 0; mov r1 = ar.ruc ;; }
{ .mmi; nop.m 0; mov r1 = ar.pfs ;; }
{ .mmi; nop.m 0; mov r1 = ar.lc ;; }
{ .mmi; nop.m 0; mov r1 = ar.ec ;; }
// Control registers
{ .mfb; mov r1 = cr0 ;; }
{ .mfb; mov r1 = cr1 ;; }
{ .mfb; mov r1 = cr2 ;; }
// { .mfb; mov r1 = cr3 ;; } // reserved
// { .mfb; mov r1 = cr4 ;; } // reserved
// { .mfb; mov r1 = cr5 ;; } // reserved
// { .mfb; mov r1 = cr6 ;; } // reserved
// { .mfb; mov r1 = cr7 ;; } // reserved
{ .mfb; mov r1 = cr8 ;; }
{ .mfb; mov r1 = cr9 ;; }
// { .mfb; mov r1 = cr10 ;; } // reserved
// { .mfb; mov r1 = cr11 ;; } // reserved
// { .mfb; mov r1 = cr12 ;; } // reserved
// { .mfb; mov r1 = cr13 ;; } // reserved
// { .mfb; mov r1 = cr14 ;; } // reserved
// { .mfb; mov r1 = cr15 ;; } // reserved
{ .mfb; mov r1 = cr16 ;; }
{ .mfb; mov r1 = cr17 ;; }
// { .mfb; mov r1 = cr18 ;; } // reserved
{ .mfb; mov r1 = cr19 ;; }
{ .mfb; mov r1 = cr20 ;; }
{ .mfb; mov r1 = cr21 ;; }
{ .mfb; mov r1 = cr22 ;; }
{ .mfb; mov r1 = cr23 ;; }
{ .mfb; mov r1 = cr24 ;; }
{ .mfb; mov r1 = cr25 ;; }
// { .mfb; mov r1 = cr26 ;; } // reserved
// { .mfb; mov r1 = cr27 ;; } // reserved
// { .mfb; mov r1 = cr28 ;; } // reserved
// { .mfb; mov r1 = cr29 ;; } // reserved
// { .mfb; mov r1 = cr30 ;; } // reserved
// { .mfb; mov r1 = cr31 ;; } // reserved
// { .mfb; mov r1 = cr32 ;; } // reserved
// { .mfb; mov r1 = cr33 ;; } // reserved
// { .mfb; mov r1 = cr34 ;; } // reserved
// { .mfb; mov r1 = cr35 ;; } // reserved
// { .mfb; mov r1 = cr36 ;; } // reserved
// { .mfb; mov r1 = cr37 ;; } // reserved
// { .mfb; mov r1 = cr38 ;; } // reserved
// { .mfb; mov r1 = cr39 ;; } // reserved
// { .mfb; mov r1 = cr40 ;; } // reserved
// { .mfb; mov r1 = cr41 ;; } // reserved
// { .mfb; mov r1 = cr42 ;; } // reserved
// { .mfb; mov r1 = cr43 ;; } // reserved
// { .mfb; mov r1 = cr44 ;; } // reserved
// { .mfb; mov r1 = cr45 ;; } // reserved
// { .mfb; mov r1 = cr46 ;; } // reserved
// { .mfb; mov r1 = cr47 ;; } // reserved
// { .mfb; mov r1 = cr48 ;; } // reserved
// { .mfb; mov r1 = cr49 ;; } // reserved
// { .mfb; mov r1 = cr50 ;; } // reserved
// { .mfb; mov r1 = cr51 ;; } // reserved
// { .mfb; mov r1 = cr52 ;; } // reserved
// { .mfb; mov r1 = cr53 ;; } // reserved
// { .mfb; mov r1 = cr54 ;; } // reserved
// { .mfb; mov r1 = cr55 ;; } // reserved
// { .mfb; mov r1 = cr56 ;; } // reserved
// { .mfb; mov r1 = cr57 ;; } // reserved
// { .mfb; mov r1 = cr58 ;; } // reserved
// { .mfb; mov r1 = cr59 ;; } // reserved
// { .mfb; mov r1 = cr60 ;; } // reserved
// { .mfb; mov r1 = cr61 ;; } // reserved
// { .mfb; mov r1 = cr62 ;; } // reserved
// { .mfb; mov r1 = cr63 ;; } // reserved
{ .mfb; mov r1 = cr64 ;; }
{ .mfb; mov r1 = cr65 ;; }
{ .mfb; mov r1 = cr66 ;; }
{ .mfb; mov r1 = cr67 ;; }
{ .mfb; mov r1 = cr68 ;; }
{ .mfb; mov r1 = cr69 ;; }
{ .mfb; mov r1 = cr70 ;; }
{ .mfb; mov r1 = cr71 ;; }
{ .mfb; mov r1 = cr72 ;; }
{ .mfb; mov r1 = cr73 ;; }
{ .mfb; mov r1 = cr74 ;; }
// { .mfb; mov r1 = cr75 ;; } // reserved
// { .mfb; mov r1 = cr76 ;; } // reserved
// { .mfb; mov r1 = cr77 ;; } // reserved
// { .mfb; mov r1 = cr78 ;; } // reserved
// { .mfb; mov r1 = cr79 ;; } // reserved
{ .mfb; mov r1 = cr80 ;; }
{ .mfb; mov r1 = cr81 ;; }
// { .mfb; mov r1 = cr82 ;; } // reserved
// { .mfb; mov r1 = cr83 ;; } // reserved
// { .mfb; mov r1 = cr84 ;; } // reserved
// { .mfb; mov r1 = cr85 ;; } // reserved
// { .mfb; mov r1 = cr86 ;; } // reserved
// { .mfb; mov r1 = cr87 ;; } // reserved
// { .mfb; mov r1 = cr88 ;; } // reserved
// { .mfb; mov r1 = cr89 ;; } // reserved
// { .mfb; mov r1 = cr90 ;; } // reserved
// { .mfb; mov r1 = cr91 ;; } // reserved
// { .mfb; mov r1 = cr92 ;; } // reserved
// { .mfb; mov r1 = cr93 ;; } // reserved
// { .mfb; mov r1 = cr94 ;; } // reserved
// { .mfb; mov r1 = cr95 ;; } // reserved
// { .mfb; mov r1 = cr96 ;; } // reserved
// { .mfb; mov r1 = cr97 ;; } // reserved
// { .mfb; mov r1 = cr98 ;; } // reserved
// { .mfb; mov r1 = cr99 ;; } // reserved
// { .mfb; mov r1 = cr100 ;; } // reserved
// { .mfb; mov r1 = cr101 ;; } // reserved
// { .mfb; mov r1 = cr102 ;; } // reserved
// { .mfb; mov r1 = cr103 ;; } // reserved
// { .mfb; mov r1 = cr104 ;; } // reserved
// { .mfb; mov r1 = cr105 ;; } // reserved
// { .mfb; mov r1 = cr106 ;; } // reserved
// { .mfb; mov r1 = cr107 ;; } // reserved
// { .mfb; mov r1 = cr108 ;; } // reserved
// { .mfb; mov r1 = cr109 ;; } // reserved
// { .mfb; mov r1 = cr110 ;; } // reserved
// { .mfb; mov r1 = cr111 ;; } // reserved
// { .mfb; mov r1 = cr112 ;; } // reserved
// { .mfb; mov r1 = cr113 ;; } // reserved
// { .mfb; mov r1 = cr114 ;; } // reserved
// { .mfb; mov r1 = cr115 ;; } // reserved
// { .mfb; mov r1 = cr116 ;; } // reserved
// { .mfb; mov r1 = cr117 ;; } // reserved
// { .mfb; mov r1 = cr118 ;; } // reserved
// { .mfb; mov r1 = cr119 ;; } // reserved
// { .mfb; mov r1 = cr120 ;; } // reserved
// { .mfb; mov r1 = cr121 ;; } // reserved
// { .mfb; mov r1 = cr122 ;; } // reserved
// { .mfb; mov r1 = cr123 ;; } // reserved
// { .mfb; mov r1 = cr124 ;; } // reserved
// { .mfb; mov r1 = cr125 ;; } // reserved
// { .mfb; mov r1 = cr126 ;; } // reserved
// { .mfb; mov r1 = cr127 ;; } // reserved
// Control registers by name
{ .mfb; mov r1 = cr.dcr ;; }
{ .mfb; mov r1 = cr.itm ;; }
{ .mfb; mov r1 = cr.iva ;; }
{ .mfb; mov r1 = cr.pta ;; }
{ .mfb; mov r1 = cr.ipsr ;; }
{ .mfb; mov r1 = cr.isr ;; }
{ .mfb; mov r1 = cr.iip ;; }
{ .mfb; mov r1 = cr.iipa ;; }
{ .mfb; mov r1 = cr.ifs ;; }
{ .mfb; mov r1 = cr.iim ;; }
{ .mfb; mov r1 = cr.iha ;; }
{ .mfb; mov r1 = cr.iib0 ;; }
{ .mfb; mov r1 = cr.iib1 ;; }
{ .mfb; mov r1 = cr.lid ;; }
{ .mfb; mov r1 = cr.ivr ;; }
{ .mfb; mov r1 = cr.tpr ;; }
{ .mfb; mov r1 = cr.eoi ;; }
{ .mfb; mov r1 = cr.irr0 ;; }
{ .mfb; mov r1 = cr.irr1 ;; }
{ .mfb; mov r1 = cr.irr2 ;; }
{ .mfb; mov r1 = cr.irr3 ;; }
{ .mfb; mov r1 = cr.itv ;; }
{ .mfb; mov r1 = cr.pmv ;; }
{ .mfb; mov r1 = cr.lrr0 ;; }
{ .mfb; mov r1 = cr.lrr1 ;; }
{ .mfb; mov r1 = cr.cmcv ;; }
// Other registers
{ .mfb; mov r1 = psr ;; }
// { .mfb; mov r1 = psr.l ;; }
{ .mfb; mov r1 = psr.um ;; }
{ .mmi; mov r1 = ip ;; }
// Indirect register files
{ .mmi
mov r1 = pmc[r3]
mov r2 = pmc[r4]
nop.i 0;; }
{ .mmi
mov r1 = pmd[r3]
mov r2 = pmd[r4]
nop.i 0;; }
{ .mmi
mov r1 = pkr[r3]
mov r2 = pkr[r4]
nop.i 0;; }
{ .mmi
mov r1 = rr[r3]
mov r2 = rr[r4]
nop.i 0;; }
{ .mmi
mov r1 = ibr[r3]
mov r2 = ibr[r4]
nop.i 0;; }
{ .mmi
mov r1 = dbr[r3]
mov r2 = dbr[r4]
nop.i 0;; }
{ .mmi
mov r1 = CPUID[r3]
mov r2 = CPUID[r4]
nop.i 0;; }
{ .mmi
mov r1 = cpuid[r3]
mov r2 = cpuid[r4]
nop.i 0;; }
|
tactcomplabs/xbgas-binutils-gdb
| 2,451
|
gas/testsuite/gas/loongarch/fix_op.s
|
clo.w $r4,$r5
clz.w $r4,$r5
cto.w $r4,$r5
ctz.w $r4,$r5
clo.d $r4,$r5
clz.d $r4,$r5
cto.d $r4,$r5
ctz.d $r4,$r5
revb.2h $r4,$r5
revb.4h $r4,$r5
revb.2w $r4,$r5
revb.d $r4,$r5
revh.2w $r4,$r5
revh.d $r4,$r5
bitrev.4b $r4,$r5
bitrev.8b $r4,$r5
bitrev.w $r4,$r5
bitrev.d $r4,$r5
ext.w.h $r4,$r5
ext.w.b $r4,$r5
move $r4,$r5
rdtimel.w $r4,$r5
rdtimeh.w $r4,$r5
rdtime.d $r4,$r5
cpucfg $r4,$r5
asrtle.d $r5,$r6
asrtgt.d $r5,$r6
alsl.w $r4,$r5,$r6,1
alsl.w $r4,$r5,$r6,4
alsl.wu $r4,$r5,$r6,1
alsl.wu $r4,$r5,$r6,4
bytepick.w $r4,$r5,$r6,0
bytepick.w $r4,$r5,$r6,3
bytepick.d $r4,$r5,$r6,0
bytepick.d $r4,$r5,$r6,7
add.w $r4,$r5,$r6
add.d $r4,$r5,$r6
sub.w $r4,$r5,$r6
sub.d $r4,$r5,$r6
slt $r4,$r5,$r6
sltu $r4,$r5,$r6
maskeqz $r4,$r5,$r6
masknez $r4,$r5,$r6
nor $r4,$r5,$r6
and $r4,$r5,$r6
or $r4,$r5,$r6
xor $r4,$r5,$r6
orn $r4,$r5,$r6
andn $r4,$r5,$r6
sll.w $r4,$r5,$r6
srl.w $r4,$r5,$r6
sra.w $r4,$r5,$r6
sll.d $r4,$r5,$r6
srl.d $r4,$r5,$r6
sra.d $r4,$r5,$r6
rotr.w $r4,$r5,$r6
rotr.d $r4,$r5,$r6
mul.w $r4,$r5,$r6
mulh.w $r4,$r5,$r6
mulh.wu $r4,$r5,$r6
mul.d $r4,$r5,$r6
mulh.d $r4,$r5,$r6
mulh.du $r4,$r5,$r6
mulw.d.w $r4,$r5,$r6
mulw.d.wu $r4,$r5,$r6
div.w $r4,$r5,$r6
mod.w $r4,$r5,$r6
div.wu $r4,$r5,$r6
mod.wu $r4,$r5,$r6
div.d $r4,$r5,$r6
mod.d $r4,$r5,$r6
div.du $r4,$r5,$r6
mod.du $r4,$r5,$r6
crc.w.b.w $r4,$r5,$r6
crc.w.h.w $r4,$r5,$r6
crc.w.w.w $r4,$r5,$r6
crc.w.d.w $r4,$r5,$r6
crcc.w.b.w $r4,$r5,$r6
crcc.w.h.w $r4,$r5,$r6
crcc.w.w.w $r4,$r5,$r6
crcc.w.d.w $r4,$r5,$r6
break 0
break 0x7fff
dbcl 0
dbcl 0x7fff
alsl.d $r4,$r5,$r6,1
alsl.d $r4,$r5,$r6,4
slli.w $r4,$r5,0
slli.w $r4,$r5,1
slli.w $r4,$r5,0x1f
slli.d $r4,$r5,0
slli.d $r4,$r5,1
slli.d $r4,$r5,0x3f
srli.w $r4,$r5,0
srli.w $r4,$r5,1
srli.w $r4,$r5,0x1f
srli.d $r4,$r5,0
srli.d $r4,$r5,1
srli.d $r4,$r5,0x3f
srai.w $r4,$r5,0
srai.w $r4,$r5,1
srai.w $r4,$r5,0x1f
srai.d $r4,$r5,0
srai.d $r4,$r5,1
srai.d $r4,$r5,0x3f
rotri.w $r4,$r5,0
rotri.w $r4,$r5,1
rotri.w $r4,$r5,0x1f
rotri.d $r4,$r5,0
rotri.d $r4,$r5,1
rotri.d $r4,$r5,0x3f
bstrins.w $r4,$r5,0,0
bstrins.w $r4,$r5,2,1
bstrins.w $r4,$r5,31,0
bstrpick.w $r4,$r5,0,0
bstrpick.w $r4,$r5,2,1
bstrpick.w $r4,$r5,31,0
bstrins.d $r4,$r5,0,0
bstrins.d $r4,$r5,31,1
bstrins.d $r4,$r5,32,0
bstrins.d $r4,$r5,63,0
bstrpick.d $r4,$r5,0,0
bstrpick.d $r4,$r5,31,1
bstrpick.d $r4,$r5,32,0
bstrpick.d $r4,$r5,63,0
|
tactcomplabs/xbgas-binutils-gdb
| 3,572
|
gas/testsuite/gas/loongarch/load_store_op.s
|
ll.w $r4,$r5,0
ll.w $r4,$r5,0x3ffc
sc.w $r4,$r5,0
sc.w $r4,$r5,0x3ffc
ll.d $r4,$r5,0
ll.d $r4,$r5,0x3ffc
sc.d $r4,$r5,0
sc.d $r4,$r5,0x3ffc
ldptr.w $r4,$r5,0
ldptr.w $r4,$r5,0x3ffc
stptr.w $r4,$r5,0
stptr.w $r4,$r5,0x3ffc
ldptr.d $r4,$r5,0
ldptr.d $r4,$r5,0x3ffc
stptr.d $r4,$r5,0
stptr.d $r4,$r5,0x3ffc
ld.b $r4,$r5,0
ld.b $r4,$r5,0x7ff
ld.b $r4,$r5,-0x7ff
ld.h $r4,$r5,0
ld.h $r4,$r5,0x7ff
ld.h $r4,$r5,-0x7ff
ld.w $r4,$r5,0
ld.w $r4,$r5,0x7ff
ld.w $r4,$r5,-0x7ff
ld.d $r4,$r5,0
ld.d $r4,$r5,0x7ff
ld.d $r4,$r5,-0x7ff
st.b $r4,$r5,0
st.b $r4,$r5,0x7ff
st.b $r4,$r5,-0x7ff
st.h $r4,$r5,0
st.h $r4,$r5,0x7ff
st.h $r4,$r5,-0x7ff
st.w $r4,$r5,0
st.w $r4,$r5,0x7ff
st.w $r4,$r5,-0x7ff
st.d $r4,$r5,0
st.d $r4,$r5,0x7ff
st.d $r4,$r5,-0x7ff
ld.bu $r4,$r5,0
ld.bu $r4,$r5,0x7ff
ld.bu $r4,$r5,-0x7ff
ld.hu $r4,$r5,0
ld.hu $r4,$r5,0x7ff
ld.hu $r4,$r5,-0x7ff
ld.wu $r4,$r5,0
ld.wu $r4,$r5,0x7ff
ld.wu $r4,$r5,-0x7ff
preld 0,$r5,0
preld 31,$r5,0x7ff
preld 31,$r5,-0x7ff
fld.s $f0,$r5,0
fld.s $f0,$r5,0x7ff
fld.s $f0,$r5,-0x7ff
fst.s $f0,$r5,0
fst.s $f0,$r5,0x7ff
fst.s $f0,$r5,-0x7ff
fld.d $f0,$r5,0
fld.d $f0,$r5,0x7ff
fld.d $f0,$r5,-0x7ff
fst.d $f0,$r5,0
fst.d $f0,$r5,0x7ff
fst.d $f0,$r5,-0x7ff
ldx.b $r4,$r5,$r6
ldx.h $r4,$r5,$r6
ldx.w $r4,$r5,$r6
ldx.d $r4,$r5,$r6
stx.b $r4,$r5,$r6
stx.h $r4,$r5,$r6
stx.w $r4,$r5,$r6
stx.d $r4,$r5,$r6
ldx.bu $r4,$r5,$r6
ldx.hu $r4,$r5,$r6
ldx.wu $r4,$r5,$r6
preldx 0,$r5,$r6
preldx 31,$r5,$r6
dbar 0
dbar 0x7fff
ibar 0
ibar 0x7fff
amswap.w $r4,$r5,$r6,0
amswap.w $r4,$r6,$r5
amswap.d $r4,$r5,$r6,0
amswap.d $r4,$r6,$r5
amadd.w $r4,$r5,$r6,0
amadd.w $r4,$r6,$r5
amadd.d $r4,$r5,$r6,0
amadd.d $r4,$r6,$r5
amand.w $r4,$r5,$r6,0
amand.w $r4,$r6,$r5
amand.d $r4,$r5,$r6,0
amand.d $r4,$r6,$r5
amor.w $r4,$r5,$r6,0
amor.w $r4,$r6,$r5
amor.d $r4,$r5,$r6,0
amor.d $r4,$r6,$r5
amxor.w $r4,$r5,$r6,0
amxor.w $r4,$r6,$r5
amxor.d $r4,$r5,$r6,0
amxor.d $r4,$r6,$r5
ammax.w $r4,$r5,$r6,0
ammax.w $r4,$r6,$r5
ammax.d $r4,$r5,$r6,0
ammax.d $r4,$r6,$r5
ammin.w $r4,$r5,$r6,0
ammin.w $r4,$r6,$r5
ammin.d $r4,$r5,$r6,0
ammin.d $r4,$r6,$r5
ammax.wu $r4,$r5,$r6,0
ammax.wu $r4,$r6,$r5
ammax.du $r4,$r5,$r6,0
ammax.du $r4,$r6,$r5
ammin.wu $r4,$r5,$r6,0
ammin.wu $r4,$r6,$r5
ammin.du $r4,$r5,$r6,0
ammin.du $r4,$r6,$r5
amswap_db.w $r4,$r5,$r6,0
amswap_db.w $r4,$r6,$r5
amswap_db.d $r4,$r5,$r6,0
amswap_db.d $r4,$r6,$r5
amadd_db.w $r4,$r5,$r6,0
amadd_db.w $r4,$r6,$r5
amadd_db.d $r4,$r5,$r6,0
amadd_db.d $r4,$r6,$r5
amand_db.w $r4,$r5,$r6,0
amand_db.w $r4,$r6,$r5
amand_db.d $r4,$r5,$r6,0
amand_db.d $r4,$r6,$r5
amor_db.w $r4,$r5,$r6,0
amor_db.w $r4,$r6,$r5
amor_db.d $r4,$r5,$r6,0
amor_db.d $r4,$r6,$r5
amxor_db.w $r4,$r5,$r6,0
amxor_db.w $r4,$r6,$r5
amxor_db.d $r4,$r5,$r6,0
amxor_db.d $r4,$r6,$r5
ammax_db.w $r4,$r5,$r6,0
ammax_db.w $r4,$r6,$r5
ammax_db.d $r4,$r5,$r6,0
ammax_db.d $r4,$r6,$r5
ammin_db.w $r4,$r5,$r6,0
ammin_db.w $r4,$r6,$r5
ammin_db.d $r4,$r5,$r6,0
ammin_db.d $r4,$r6,$r5
ammax_db.wu $r4,$r5,$r6,0
ammax_db.wu $r4,$r6,$r5
ammax_db.du $r4,$r5,$r6,0
ammax_db.du $r4,$r6,$r5
ammin_db.wu $r4,$r5,$r6,0
ammin_db.wu $r4,$r6,$r5
ammin_db.du $r4,$r5,$r6,0
ammin_db.du $r4,$r6,$r5
ldgt.b $r4,$r5,$r6
ldgt.h $r4,$r5,$r6
ldgt.w $r4,$r5,$r6
ldgt.d $r4,$r5,$r6
ldle.b $r4,$r5,$r6
ldle.h $r4,$r5,$r6
ldle.w $r4,$r5,$r6
ldle.d $r4,$r5,$r6
stgt.b $r4,$r5,$r6
stgt.h $r4,$r5,$r6
stgt.w $r4,$r5,$r6
stgt.d $r4,$r5,$r6
stle.b $r4,$r5,$r6
stle.h $r4,$r5,$r6
stle.w $r4,$r5,$r6
stle.d $r4,$r5,$r6
|
tactcomplabs/xbgas-binutils-gdb
| 1,600
|
gas/testsuite/gas/loongarch/4opt_op.s
|
fmadd.s $f0,$f1,$f2,$f3
fmadd.d $f0,$f1,$f2,$f3
fmsub.s $f0,$f1,$f2,$f3
fmsub.d $f0,$f1,$f2,$f3
fnmadd.s $f0,$f1,$f2,$f3
fnmadd.d $f0,$f1,$f2,$f3
fnmsub.s $f0,$f1,$f2,$f3
fnmsub.d $f0,$f1,$f2,$f3
fcmp.caf.s $fcc0,$f1,$f2
fcmp.saf.s $fcc0,$f1,$f2
fcmp.clt.s $fcc0,$f1,$f2
fcmp.slt.s $fcc0,$f1,$f2
fcmp.sgt.s $fcc0,$f2,$f1
fcmp.ceq.s $fcc0,$f1,$f2
fcmp.seq.s $fcc0,$f1,$f2
fcmp.cle.s $fcc0,$f1,$f2
fcmp.sle.s $fcc0,$f1,$f2
fcmp.sge.s $fcc0,$f2,$f1
fcmp.cun.s $fcc0,$f1,$f2
fcmp.sun.s $fcc0,$f1,$f2
fcmp.cult.s $fcc0,$f1,$f2
fcmp.cugt.s $fcc0,$f2,$f1
fcmp.sult.s $fcc0,$f1,$f2
fcmp.cueq.s $fcc0,$f1,$f2
fcmp.sueq.s $fcc0,$f1,$f2
fcmp.cule.s $fcc0,$f1,$f2
fcmp.cuge.s $fcc0,$f2,$f1
fcmp.sule.s $fcc0,$f1,$f2
fcmp.cne.s $fcc0,$f1,$f2
fcmp.sne.s $fcc0,$f1,$f2
fcmp.cor.s $fcc0,$f1,$f2
fcmp.sor.s $fcc0,$f1,$f2
fcmp.cune.s $fcc0,$f1,$f2
fcmp.sune.s $fcc0,$f1,$f2
fcmp.caf.d $fcc0,$f1,$f2
fcmp.saf.d $fcc0,$f1,$f2
fcmp.clt.d $fcc0,$f1,$f2
fcmp.slt.d $fcc0,$f1,$f2
fcmp.sgt.d $fcc0,$f2,$f1
fcmp.ceq.d $fcc0,$f1,$f2
fcmp.seq.d $fcc0,$f1,$f2
fcmp.cle.d $fcc0,$f1,$f2
fcmp.sle.d $fcc0,$f1,$f2
fcmp.sge.d $fcc0,$f2,$f1
fcmp.cun.d $fcc0,$f1,$f2
fcmp.sun.d $fcc0,$f1,$f2
fcmp.cult.d $fcc0,$f1,$f2
fcmp.cugt.d $fcc0,$f2,$f1
fcmp.sult.d $fcc0,$f1,$f2
fcmp.cueq.d $fcc0,$f1,$f2
fcmp.sueq.d $fcc0,$f1,$f2
fcmp.cule.d $fcc0,$f1,$f2
fcmp.cuge.d $fcc0,$f2,$f1
fcmp.sule.d $fcc0,$f1,$f2
fcmp.cne.d $fcc0,$f1,$f2
fcmp.sne.d $fcc0,$f1,$f2
fcmp.cor.d $fcc0,$f1,$f2
fcmp.sor.d $fcc0,$f1,$f2
fcmp.cune.d $fcc0,$f1,$f2
fcmp.sune.d $fcc0,$f1,$f2
fsel $f0,$f1,$f2,$fcc0
|
tactcomplabs/xbgas-binutils-gdb
| 1,496
|
gas/testsuite/gas/loongarch/float_op.s
|
fadd.s $f0,$f1,$f2
fadd.d $f0,$f1,$f2
fsub.s $f0,$f1,$f2
fsub.d $f0,$f1,$f2
fmul.s $f0,$f1,$f2
fmul.d $f0,$f1,$f2
fdiv.s $f0,$f1,$f2
fdiv.d $f0,$f1,$f2
fmax.s $f0,$f1,$f2
fmax.d $f0,$f1,$f2
fmin.s $f0,$f1,$f2
fmin.d $f0,$f1,$f2
fmaxa.s $f0,$f1,$f2
fmaxa.d $f0,$f1,$f2
fmina.s $f0,$f1,$f2
fmina.d $f0,$f1,$f2
fscaleb.s $f0,$f1,$f2
fscaleb.d $f0,$f1,$f2
fcopysign.s $f0,$f1,$f2
fcopysign.d $f0,$f1,$f2
fabs.s $f0,$f1
fabs.d $f0,$f1
fneg.s $f0,$f1
fneg.d $f0,$f1
flogb.s $f0,$f1
flogb.d $f0,$f1
fclass.s $f0,$f1
fclass.d $f0,$f1
fsqrt.s $f0,$f1
fsqrt.d $f0,$f1
frecip.s $f0,$f1
frecip.d $f0,$f1
frsqrt.s $f0,$f1
frsqrt.d $f0,$f1
fmov.s $f0,$f1
fmov.d $f0,$f1
movgr2fr.w $f0,$r5
movgr2fr.d $f0,$r5
movgr2frh.w $f0,$r5
movfr2gr.s $r4,$f1
movfr2gr.d $r4,$f1
movfrh2gr.s $r4,$f1
movgr2fcsr $r4,$r5
movfcsr2gr $r4,$r5
movfr2cf $fcc0,$f1
movcf2fr $f0,$fcc5
movgr2cf $fcc0,$r5
movcf2gr $r4,$fcc5
fcvt.s.d $f0,$f1
fcvt.d.s $f0,$f1
ftintrm.w.s $f0,$f1
ftintrm.w.d $f0,$f1
ftintrm.l.s $f0,$f1
ftintrm.l.d $f0,$f1
ftintrp.w.s $f0,$f1
ftintrp.w.d $f0,$f1
ftintrp.l.s $f0,$f1
ftintrp.l.d $f0,$f1
ftintrz.w.s $f0,$f1
ftintrz.w.d $f0,$f1
ftintrz.l.s $f0,$f1
ftintrz.l.d $f0,$f1
ftintrne.w.s $f0,$f1
ftintrne.w.d $f0,$f1
ftintrne.l.s $f0,$f1
ftintrne.l.d $f0,$f1
ftint.w.s $f0,$f1
ftint.w.d $f0,$f1
ftint.l.s $f0,$f1
ftint.l.d $f0,$f1
ffint.s.w $f0,$f1
ffint.s.l $f0,$f1
ffint.d.w $f0,$f1
ffint.d.l $f0,$f1
frint.s $f0,$f1
frint.d $f0,$f1
|
tactcomplabs/xbgas-binutils-gdb
| 3,479
|
gas/testsuite/gas/s390/zarch-arch13.s
|
.text
foo:
ncrk %r6,%r9,%r11
ncgrk %r6,%r9,%r11
mvcrl 4000(%r6),4000(%r9)
nnrk %r6,%r9,%r11
nngrk %r6,%r9,%r11
nork %r6,%r9,%r11
nogrk %r6,%r9,%r11
nxrk %r6,%r9,%r11
nxgrk %r6,%r9,%r11
ocrk %r6,%r9,%r11
ocgrk %r6,%r9,%r11
popcnt %r6,%r9
popcnt %r6,%r9,13
selr %r6,%r9,%r11,13
selro %r6,%r9,%r11
selrh %r6,%r9,%r11
selrp %r6,%r9,%r11
selrnle %r6,%r9,%r11
selrl %r6,%r9,%r11
selrm %r6,%r9,%r11
selrnhe %r6,%r9,%r11
selrlh %r6,%r9,%r11
selrne %r6,%r9,%r11
selrnz %r6,%r9,%r11
selre %r6,%r9,%r11
selrz %r6,%r9,%r11
selrnlh %r6,%r9,%r11
selrhe %r6,%r9,%r11
selrnl %r6,%r9,%r11
selrnm %r6,%r9,%r11
selrle %r6,%r9,%r11
selrnh %r6,%r9,%r11
selrnp %r6,%r9,%r11
selrno %r6,%r9,%r11
selgr %r6,%r9,%r11,13
selgro %r6,%r9,%r11
selgrh %r6,%r9,%r11
selgrp %r6,%r9,%r11
selgrnle %r6,%r9,%r11
selgrl %r6,%r9,%r11
selgrm %r6,%r9,%r11
selgrnhe %r6,%r9,%r11
selgrlh %r6,%r9,%r11
selgrne %r6,%r9,%r11
selgrnz %r6,%r9,%r11
selgre %r6,%r9,%r11
selgrz %r6,%r9,%r11
selgrnlh %r6,%r9,%r11
selgrhe %r6,%r9,%r11
selgrnl %r6,%r9,%r11
selgrnm %r6,%r9,%r11
selgrle %r6,%r9,%r11
selgrnh %r6,%r9,%r11
selgrnp %r6,%r9,%r11
selgrno %r6,%r9,%r11
selfhr %r6,%r9,%r11,13
selfhro %r6,%r9,%r11
selfhrh %r6,%r9,%r11
selfhrp %r6,%r9,%r11
selfhrnle %r6,%r9,%r11
selfhrl %r6,%r9,%r11
selfhrm %r6,%r9,%r11
selfhrnhe %r6,%r9,%r11
selfhrlh %r6,%r9,%r11
selfhrne %r6,%r9,%r11
selfhrnz %r6,%r9,%r11
selfhre %r6,%r9,%r11
selfhrz %r6,%r9,%r11
selfhrnlh %r6,%r9,%r11
selfhrhe %r6,%r9,%r11
selfhrnl %r6,%r9,%r11
selfhrnm %r6,%r9,%r11
selfhrle %r6,%r9,%r11
selfhrnh %r6,%r9,%r11
selfhrnp %r6,%r9,%r11
selfhrno %r6,%r9,%r11
vlbr %v15,4000(%r6,%r9),13
vlbrh %v15,4000(%r6,%r9)
vlbrf %v15,4000(%r6,%r9)
vlbrg %v15,4000(%r6,%r9)
vlbrq %v15,4000(%r6,%r9)
vler %v15,4000(%r6,%r9),13
vlerh %v15,4000(%r6,%r9)
vlerf %v15,4000(%r6,%r9)
vlerg %v15,4000(%r6,%r9)
vllebrz %v15,4000(%r6,%r9),13
vllebrzh %v15,4000(%r6,%r9)
vllebrzf %v15,4000(%r6,%r9)
ldrv %v15,4000(%r6,%r9)
vllebrzg %v15,4000(%r6,%r9)
lerv %v15,4000(%r6,%r9)
vllebrze %v15,4000(%r6,%r9)
vlebrh %v15,4000(%r6,%r9),13
vlebrf %v15,4000(%r6,%r9),13
vlebrg %v15,4000(%r6,%r9),13
vlbrrep %v15,4000(%r6,%r9),13
vlbrreph %v15,4000(%r6,%r9)
vlbrrepf %v15,4000(%r6,%r9)
vlbrrepg %v15,4000(%r6,%r9)
vstbr %v15,4000(%r6,%r9),13
vstbrh %v15,4000(%r6,%r9)
vstbrf %v15,4000(%r6,%r9)
vstbrg %v15,4000(%r6,%r9)
vstbrq %v15,4000(%r6,%r9)
vster %v15,4000(%r6,%r9),13
vsterh %v15,4000(%r6,%r9)
vsterf %v15,4000(%r6,%r9)
vsterg %v15,4000(%r6,%r9)
vstebrh %v15,4000(%r6,%r9),13
vstebrf %v15,4000(%r6,%r9),13
sterv %v15,4000(%r6,%r9)
vstebrg %v15,4000(%r6,%r9),13
stdrv %v15,4000(%r6,%r9)
vsld %v15,%v17,%v20,253
vsrd %v15,%v17,%v20,253
vstrs %v15,%v17,%v20,%v24,13
vstrs %v15,%v17,%v20,%v24,13,12
vstrsb %v15,%v17,%v20,%v24
vstrsb %v15,%v17,%v20,%v24,13
vstrsh %v15,%v17,%v20,%v24
vstrsh %v15,%v17,%v20,%v24,13
vstrsf %v15,%v17,%v20,%v24
vstrsf %v15,%v17,%v20,%v24,13
vstrszb %v15,%v17,%v20,%v24
vstrszh %v15,%v17,%v20,%v24
vstrszf %v15,%v17,%v20,%v24
vcfps %v15,%v17,13,12,11
vcefb %v15,%v17,13,12
wcefb %v15,%v17,13,12
vcfpl %v15,%v17,13,12,11
vcelfb %v15,%v17,13,12
wcelfb %v15,%v17,13,12
vcsfp %v15,%v17,13,12,11
vcfeb %v15,%v17,13,12
wcfeb %v15,%v17,13,12
vclfp %v15,%v17,13,12,11
vclfeb %v15,%v17,13,12
wclfeb %v15,%v17,13,12
dfltcc %r6,%r9,%r11
sortl %r6,%r9
vcvb %r6,%v15,13
vcvb %r6,%v15,13,12
vcvbg %r6,%v15,13
vcvbg %r6,%v15,13,12
kdsa %r6,%r9
|
tactcomplabs/xbgas-binutils-gdb
| 1,288
|
gas/testsuite/gas/s390/zarch-z9-109.s
|
.text
foo:
afi %r6,-2147483648
agfi %r6,-2147483648
alfi %r6,4294967295
algfi %r6,4294967295
nihf %r6,4294967295
nilf %r6,4294967295
cfi %r6,-2147483648
cgfi %r6,-2147483648
clfi %r6,4294967295
clgfi %r6,4294967295
xihf %r6,4294967295
xilf %r6,4294967295
iihf %r6,4294967295
iilf %r6,4294967295
flogr %r6,%r9
lt %r6,-524288(%r5,%r10)
ltg %r6,-524288(%r5,%r10)
lbr %r6,%r9
lgbr %r6,%r9
lhr %r6,%r9
lghr %r6,%r9
lgfi %r6,-2147483648
llc %r6,-524288(%r5,%r10)
llcr %r6,%r9
llgcr %r6,%r9
llh %r6,-524288(%r5,%r10)
llhr %r6,%r9
llghr %r6,%r9
llihf %r6,4294967295
llilf %r6,4294967295
oihf %r6,4294967295
oilf %r6,4294967295
slfi %r6,4294967295
slgfi %r6,4294967295
stfle 4095(%r5)
stckf 4095(%r5)
mvcos 4095(%r5),4095(%r10),%r6
lptea %r6,%r9,%r5,15
sske %r6,%r9,15
sske %r6,%r9
cu24 %r6,%r8,15
cu24 %r6,%r8
cu21 %r6,%r8,15
cu21 %r6,%r8
cu42 %r6,%r8
cu41 %r6,%r8
cu12 %r6,%r8,15
cu12 %r6,%r8
cu14 %r6,%r8,15
cu14 %r6,%r8
myr %f6,%f9,%f5
myhr %f6,%f9,%f5
mylr %f6,%f9,%f5
my %f5,%f9,4095(%r5,%r10)
myh %f6,%f9,4095(%r5,%r10)
myl %f6,%f9,4095(%r5,%r10)
mayr %f6,%f9,%f5
mayhr %f6,%f9,%f5
maylr %f6,%f9,%f5
may %f6,%f9,4095(%r5,%r10)
mayh %f6,%f9,4095(%r5,%r10)
mayl %f6,%f9,4095(%r5,%r10)
srstu %r6,%r7
trtr 4095(23,%r5),3333(%r10)
|
tactcomplabs/xbgas-binutils-gdb
| 1,207
|
gas/testsuite/gas/s390/zarch-zEC12.s
|
.text
foo:
etnd %r6
ntstg %r6,-5555(%r7,%r8)
tabort 4000(%r6)
tbegin 4000(%r6),65000
tbeginc 4000(%r6),65000
tend
bpp 10,.,4000(%r6)
bprp 10,.,.+24
niai 10,13
lat %r6,-5555(%r7,%r8)
lgat %r6,-5555(%r7,%r8)
lfhat %r6,-5555(%r7,%r8)
llgfat %r6,-5555(%r7,%r8)
llgtat %r6,-5555(%r7,%r8)
clt %r6,10,-5555(%r7)
clth %r6,-5555(%r7)
cltnle %r6,-5555(%r7)
cltl %r6,-5555(%r7)
cltnhe %r6,-5555(%r7)
cltlh %r6,-5555(%r7)
cltne %r6,-5555(%r7)
clte %r6,-5555(%r7)
cltnlh %r6,-5555(%r7)
clthe %r6,-5555(%r7)
cltnl %r6,-5555(%r7)
cltle %r6,-5555(%r7)
cltnh %r6,-5555(%r7)
clgt %r6,10,-5555(%r7)
clgth %r6,-5555(%r7)
clgtnle %r6,-5555(%r7)
clgtl %r6,-5555(%r7)
clgtnhe %r6,-5555(%r7)
clgtlh %r6,-5555(%r7)
clgtne %r6,-5555(%r7)
clgte %r6,-5555(%r7)
clgtnlh %r6,-5555(%r7)
clgthe %r6,-5555(%r7)
clgtnl %r6,-5555(%r7)
clgtle %r6,-5555(%r7)
clgtnh %r6,-5555(%r7)
risbgn %r6,%r7,12,13,14
risbgn %r6,%r7,12,188,14
risbgnz %r6,%r7,12,20,14
cdzt %f6,4000(16,%r8),13
cxzt %f4,4000(34,%r8),13
czdt %f6,4000(16,%r8),13
czxt %f4,4000(34,%r8),13
ppa %r5,%r6,12
crdte %r5,%r6,%r9
crdte %r5,%r6,%r9,1
bprp 10,bar,bar
bprp 10,bar@PLT,bar@PLT
bpp 10,bar@PLT,0
bpp 10,baz,0
bar:
|
tactcomplabs/xbgas-binutils-gdb
| 3,296
|
gas/testsuite/gas/s390/zarch-z990.s
|
.text
foo:
ag %r6,-524288(%r5,%r10)
agf %r6,-524288(%r5,%r10)
ahy %r6,-524288(%r5,%r10)
alc %r6,-524288(%r5,%r10)
alcg %r6,-524288(%r5,%r10)
alg %r6,-524288(%r5,%r10)
algf %r6,-524288(%r5,%r10)
aly %r6,-524288(%r5,%r10)
ay %r6,-524288(%r5,%r10)
bctg %r6,-524288(%r5)
bxhg %r6,%r9,-524288(%r5)
bxleg %r6,%r9,-524288(%r5)
cdsg %r6,%r8,-524288(%r5)
cdsy %r6,%r8,-524288(%r5)
cg %r6,-524288(%r5,%r10)
cgf %r6,-524288(%r5,%r10)
chy %r6,-524288(%r5,%r10)
clg %r6,-524288(%r5,%r10)
clgf %r6,-524288(%r5,%r10)
cliy -524288(%r5),255
clmh %r6,15,-524288(%r5)
clmy %r6,15,-524288(%r5)
cly %r6,-524288(%r5,%r10)
csg %r6,%r9,-524288(%r5)
cspg %r6,%r9
csy %r6,%r9,-524288(%r5)
cvbg %r6,-524288(%r5,%r10)
cvby %r6,-524288(%r5,%r10)
cvdg %r6,-524288(%r5,%r10)
cvdy %r6,-524288(%r5,%r10)
cy %r6,-524288(%r5,%r10)
dl %r6,-524288(%r5,%r10)
dlg %r6,-524288(%r5,%r10)
dsg %r6,-524288(%r5,%r10)
dsgf %r6,-524288(%r5,%r10)
icmh %r6,15,-524288(%r5)
icmy %r6,15,-524288(%r5)
icy %r6,-524288(%r5,%r10)
idte %r6,%r9,%r11
idte %r6,%r9,%r11,13
lamy %a6,%a9,-524288(%r5)
lay %r6,-524288(%r5,%r10)
lb %r6,-524288(%r5,%r10)
lctlg %c6,%c9,-524288(%r5)
ldy %f6,-524288(%r5,%r10)
ley %f6,-524288(%r5,%r10)
lg %r6,-524288(%r5,%r10)
lgb %r6,-524288(%r5,%r10)
lgf %r6,-524288(%r5,%r10)
lgh %r6,-524288(%r5,%r10)
lhy %r6,-524288(%r5,%r10)
llgc %r6,-524288(%r5,%r10)
llgf %r6,-524288(%r5,%r10)
llgh %r6,-524288(%r5,%r10)
llgt %r6,-524288(%r5,%r10)
lmg %r6,%r9,-524288(%r5)
lmh %r6,%r9,-524288(%r5)
lmy %r6,%r9,-524288(%r5)
lpq %r6,-524288(%r5,%r10)
lrag %r6,-524288(%r5,%r10)
lray %r6,-524288(%r5,%r10)
lrv %r6,-524288(%r5,%r10)
lrvg %r6,-524288(%r5,%r10)
lrvh %r6,-524288(%r5,%r10)
ly %r6,-524288(%r5,%r10)
mad %f6,%f9,4095(%r5,%r10)
madr %f6,%f9,%f5
mae %f6,%f9,4095(%r5,%r10)
maer %f6,%f9,%f5
ml %r6,-524288(%r5,%r10)
mlg %r6,-524288(%r5,%r10)
msd %f6,%f9,4095(%r5,%r10)
msdr %f6,%f9,%f5
mse %f6,%f9,4095(%r5,%r10)
mser %f6,%f9,%f5
msg %r6,-524288(%r5,%r10)
msgf %r6,-524288(%r5,%r10)
msy %r6,-524288(%r5,%r10)
mvclu %r6,%r8,-524288(%r5)
mviy -524288(%r5),255
ng %r6,-524288(%r5,%r10)
niy -524288(%r5),255
ny %r6,-524288(%r5,%r10)
og %r6,-524288(%r5,%r10)
oiy -524288(%r5),255
oy %r6,-524288(%r5,%r10)
rll %r6,%r9,-524288(%r5)
rllg %r6,%r9,-524288(%r5)
sg %r6,-524288(%r5,%r10)
sgf %r6,-524288(%r5,%r10)
shy %r6,-524288(%r5,%r10)
slag %r6,%r9,-524288(%r5)
slb %r6,-524288(%r5,%r10)
slbg %r6,-524288(%r5,%r10)
slg %r6,-524288(%r5,%r10)
slgf %r6,-524288(%r5,%r10)
sllg %r6,%r9,-524288(%r5)
sly %r6,-524288(%r5,%r10)
srag %r6,%r9,-524288(%r5)
srlg %r6,%r9,-524288(%r5)
stamy %a6,%a9,-524288(%r5)
stcmh %r6,15,-524288(%r5)
stcmy %r6,15,-524288(%r5)
stctg %c6,%c9,-524288(%r5)
stcy %r6,-524288(%r5,%r10)
stdy %f6,-524288(%r5,%r10)
stey %f6,-524288(%r5,%r10)
stg %r6,-524288(%r5,%r10)
sthy %r6,-524288(%r5,%r10)
stmg %r6,%r9,-524288(%r5)
stmh %r6,%r9,-524288(%r5)
stmy %r6,%r9,-524288(%r5)
stpq %r6,-524288(%r5,%r10)
strv %r6,-524288(%r5,%r10)
strvg %r6,-524288(%r5,%r10)
strvh %r6,-524288(%r5,%r10)
sty %r6,-524288(%r5,%r10)
sy %r6,-524288(%r5,%r10)
tmy -524288(%r5),255
tracg %r6,%r9,-524288(%r5)
xg %r6,-524288(%r5,%r10)
xiy -524288(%r5),255
xy %r6,-524288(%r5,%r10)
epair %r6
esair %r6
pti %r6,%r5
ssair %r6
|
tactcomplabs/xbgas-binutils-gdb
| 8,392
|
gas/testsuite/gas/s390/esa-g5.s
|
.text
foo:
a %r6,4095(%r5,%r10)
ad %f6,4095(%r5,%r10)
adb %f6,4095(%r5,%r10)
adbr %f6,%f9
adr %f6,%f9
ae %f6,4095(%r5,%r10)
aeb %f6,4095(%r5,%r10)
aebr %f6,%f9
aer %f6,%f9
ah %r6,4095(%r5,%r10)
ahi %r6,-32767
al %r6,4095(%r5,%r10)
alr %r6,%r9
ap 4095(6,%r5),4095(9,%r10)
ar %r6,%r9
au %f6,4095(%r5,%r10)
aur %f6,%f9
aw %f6,4095(%r5,%r10)
awr %f6,%f9
axbr %f4,%f8
axr %f4,%f8
b 4095(%r5,%r10)
bakr %r6,%r9
bal %r6,4095(%r5,%r10)
balr %r6,%r9
bas %r6,4095(%r5,%r10)
basr %r6,%r9
bassm %r6,%r9
bc 6,4095(%r5,%r10)
bcr 6,%r9
bct %r6,4095(%r5,%r10)
bctr %r6,%r9
be 4095(%r5,%r10)
ber %r9
bh 4095(%r5,%r10)
bhe 4095(%r5,%r10)
bher %r9
bhr %r9
bl 4095(%r5,%r10)
ble 4095(%r5,%r10)
bler %r9
blh 4095(%r5,%r10)
blhr %r9
blr %r9
bm 4095(%r5,%r10)
bmr %r9
bne 4095(%r5,%r10)
bner %r9
bnh 4095(%r5,%r10)
bnhe 4095(%r5,%r10)
bnher %r9
bnhr %r9
bnl 4095(%r5,%r10)
bnle 4095(%r5,%r10)
bnler %r9
bnlh 4095(%r5,%r10)
bnlhr %r9
bnlr %r9
bnm 4095(%r5,%r10)
bnmr %r9
bno 4095(%r5,%r10)
bnor %r9
bnp 4095(%r5,%r10)
bnpr %r9
bnz 4095(%r5,%r10)
bnzr %r9
bo 4095(%r5,%r10)
bor %r9
bp 4095(%r5,%r10)
bpr %r9
br %r9
bras %r9,.
jas %r6,.
brc 6,.
brct 6,.
jct %r6,.
brxh %r6,%r9,.
jxh %r6,%r9,.
brxle %r6,%r9,.
jxle %r6,%r9,.
bsa %r6,%r9
bsg %r6,%r9
bsm %r6,%r9
bxh %r6,%r9,4095(%r5)
bxle %r6,%r9,4095(%r5)
bz 4095(%r5,%r10)
bzr %r9
c %r6,4095(%r5,%r10)
cd %f6,4095(%r5,%r10)
cdb %f6,4095(%r5,%r10)
cdbr %f6,%f9
cdfbr %f6,%r9
cdfr %f6,%r9
cdr %f6,%f9
cds %r6,%r8,4095(%r5)
ce %f6,4095(%r5,%r10)
ceb %f6,4095(%r5,%r10)
cebr %f6,%f9
cefbr %f6,%r9
cefr %f6,%r9
cer %f6,%f9
cfc 4095(%r5)
cfdbr %r6,5,%f9
cfebr %r6,5,%f9
cfxbr %r5,5,%f8
cfdr %r6,9,%f5
cfer %r6,9,%f5
cfxr %r5,9,%f4
ch %r6,4095(%r5,%r10)
chi %r6,-32767
cksm %r6,%r9
cl %r6,4095(%r5,%r10)
clc 4095(256,%r5),4095(%r10)
clcl %r6,%r9
clcle %r6,%r9,4095(%r5)
cli 4095(%r5),255
clm %r6,10,4095(%r5)
clr %r6,%r9
clst %r6,%r9
cmpsc %r6,%r9
cp 4095(6,%r5),4095(9,%r10)
cpya %a6,%a9
cr %r6,%r9
cs %r6,%r9,4095(%r5)
csch
csp %r6,%r9
cuse %r6,%r8
cutfu %r6,%r8
cuutf %r6,%r8
cvb %r6,4095(%r5,%r10)
cvd %r6,4095(%r5,%r10)
cxbr %f5,%f8
cxfbr %f5,%r9
cxfr %f5,%r9
cxr %f5,%f9
d %r6,4095(%r5,%r10)
dd %f6,4095(%r5,%r10)
ddb %f6,4095(%r5,%r10)
ddbr %f6,%f9
ddr %f6,%f9
de %f6,4095(%r5,%r10)
deb %f6,4095(%r5,%r10)
debr %f6,%f9
der %f6,%f9
diag %r6,%r9,4095(%r5)
didbr %f6,%r9,%r5,10
diebr %f6,%r9,%r5,10
dp 4095(6,%r5),4095(9,%r10)
dr %r6,%r9
dxbr %f5,%f8
dxr %f5,%f8
ear %r6,%a9
ed 4095(256,%r5),4095(%r10)
edmk 4095(256,%r5),4095(%r10)
efpc %r6,%r9
efpc %r6
epar %r6
ereg %r6,%r9
esar %r6
esta %r6,%r9
ex %r6,4095(%r5,%r10)
fidbr %f6,5,%f9
fidr %f6,%f9
fiebr %f6,5,%f9
fier %f6,%f9
fixbr %f5,5,%f8
fixr %f5,%f8
hdr %f6,%f9
her %f6,%f9
hsch
iac %r6
ic %r6,4095(%r5,%r10)
icm %r6,10,4095(%r5)
ipk
ipm %r6
ipte %r6,%r9
iske %r6,%r9
ivsk %r6,%r9
j .
je .
jh .
jhe .
jl .
jle .
jlh .
jm .
jne .
jnh .
jnhe .
jnl .
jnle .
jnlh .
jnm .
jno .
jnp .
jnz .
jo .
jp .
jz .
jnop .
bro .
brh .
brp .
brnle .
brl .
brm .
brnhe .
brlh .
brne .
brnz .
bre .
brz .
brnlh .
brhe .
brnl .
brnm .
brle .
brnh .
brnp .
brno .
bru .
kdb %f6,4095(%r5,%r10)
kdbr %f6,%f9
keb %f6,4095(%r5,%r10)
kebr %f6,%f9
kxbr %f6,%f9
l %r6,4095(%r5,%r10)
la %r6,4095(%r5,%r10)
lae %r6,4095(%r5,%r10)
lam %a6,%a9,4095(%r5)
lasp 4095(%r5),4095(%r10)
lcdbr %f6,%f9
lcdr %f6,%f9
lcebr %f6,%f9
lcer %f6,%f9
lcr %r6,%r9
lctl %c6,%c9,4095(%r5)
lcxbr %f5,%f8
lcxr %f5,%f8
ld %f6,4095(%r5,%r10)
lde %f6,4095(%r5,%r10)
ldeb %f6,4095(%r5,%r10)
ldebr %f6,%f9
lder %f6,%f9
ldr %f6,%f9
ldxbr %f5,%f8
ldxr %f6,%f8
le %f6,4095(%r5,%r10)
ledbr %f6,%f9
ledr %f6,%f9
ler %f6,%f9
lexbr %f5,%f8
lexr %f6,%f8
lfpc 4095(%r5)
lh %r6,4095(%r5,%r10)
lhi %r6,-32767
lm %r6,%r9,4095(%r5)
lndbr %f6,%f9
lndr %f6,%f9
lnebr %f6,%f9
lner %f6,%f9
lnr %r6,%r9
lnxbr %f5,%f8
lnxr %f5,%f8
lpdbr %f6,%f9
lpdr %f6,%f9
lpebr %f6,%f9
lper %f6,%f9
lpr %r6,%r9
lpsw 4095(%r5)
lpxbr %f5,%f8
lpxr %f5,%f8
lr %r6,%r9
lra %r6,4095(%r5,%r10)
lrdr %f7,%f8
lrer %f6,%f9
ltdbr %f6,%f9
ltdr %f6,%f9
ltebr %f6,%f9
lter %f6,%f9
ltr %r6,%r9
ltxbr %f5,%f8
ltxr %f5,%f8
lura %r6,%r9
lxd %f5,4095(%r5,%r10)
lxdb %f5,4095(%r5,%r10)
lxdbr %f5,%f9
lxdr %f5,%f9
lxe %f5,4095(%r5,%r10)
lxeb %f5,4095(%r5,%r10)
lxebr %f5,%f9
lxer %f5,%f9
lxr %f5,%f8
lzdr %f6
lzer %f6
lzxr %f5
m %r6,4095(%r5,%r10)
madb %f6,%f9,4095(%r5,%r10)
madbr %f6,%f9,%f5
maeb %f6,%f9,4095(%r5,%r10)
maebr %f6,%f9,%f5
mc 4095(%r5),255
md %f6,4095(%r5,%r10)
mdb %f6,4095(%r5,%r10)
mdbr %f6,%f9
mde %f6,4095(%r5,%r10)
mdeb %f6,4095(%r5,%r10)
mdebr %f6,%f9
mder %f6,%f9
mdr %f6,%f9
me %f6,4095(%r5,%r10)
mee %f6,4095(%r5,%r10)
meeb %f6,4095(%r5,%r10)
meebr %f6,%f9
meer %f6,%f9
mer %f6,%f9
mh %r6,4095(%r5,%r10)
mhi %r6,-32767
mp 4095(6,%r5),4095(9,%r10)
mr %r6,%r9
ms %r6,4095(%r5,%r10)
msch 4095(%r5)
msdb %f6,%f9,4095(%r5,%r10)
msdbr %f6,%f9,%f5
mseb %f6,%f9,4095(%r5,%r10)
msebr %f6,%f9,%f5
msr %r6,%r9
msta %r6
mvc 4095(256,%r5),4095(%r10)
mvcdk 4095(%r5),4095(%r10)
mvcin 4095(256,%r5),4095(%r10)
mvck 4095(%r6,%r5),4095(%r10),%r9
mvcl %r6,%r9
mvcle %r6,%r8,4095(%r5)
mvclu %r6,%r8,4095(%r5)
mvcp 4095(%r6,%r5),4095(%r10),%r9
mvcs 4095(%r6,%r5),4095(%r10),%r9
mvcsk 4095(%r5),4095(%r10)
mvi 4095(%r5),255
mvn 4095(256,%r5),4095(%r10)
mvo 4095(6,%r5),4095(9,%r10)
mvpg %r6,%r9
mvst %r6,%r9
mvz 4095(256,%r5),4095(%r10)
mxbr %f5,%f8
mxd %f5,4095(%r5,%r10)
mxdb %f5,4095(%r5,%r10)
mxdbr %f5,%f9
mxdr %f5,%f9
mxr %f5,%f8
n %r6,4095(%r5,%r10)
nc 4095(256,%r5),4095(%r10)
ni 4095(%r5),255
nop 4095(%r5,%r10)
nopr %r9
nr %r6,%r9
o %r6,4095(%r5,%r10)
oc 4095(256,%r5),4095(%r10)
oi 4095(%r5),255
or %r6,%r9
pack 4095(6,%r5),4095(9,%r10)
palb
pc 4095(%r5)
pgin %r6,%r9
pgout %r6,%r9
pka 4095(%r5),4095(32,%r10)
pku 4095(%r5),4095(256,%r10)
plo %r6,4095(%r5),%r9,4095(%r10)
pr
pt %r6,%r9
ptlb
rchp
rp 4095(%r5)
rrbe %r6,%r9
rsch
s %r6,4095(%r5,%r10)
sac 4095(%r5)
sacf 4095(%r5)
sal
sar %a6,%r9
schm
sck 4095(%r5)
sckc 4095(%r5)
sckpf
sd %f6,4095(%r5,%r10)
sdb %f6,4095(%r5,%r10)
sdbr %f6,%f9
sdr %f6,%f9
se %f6,4095(%r5,%r10)
seb %f6,4095(%r5,%r10)
sebr %f6,%f9
ser %f6,%f9
sfpc %r6,%r9
sfpc %r6
sh %r6,4095(%r5,%r10)
sie 4095(%r5)
siga 4095(%r5)
sigp %r6,%r9,4095(%r5)
sl %r6,4095(%r5,%r10)
sla %r6,4095(%r5)
slda %r6,4095(%r5)
sldl %r6,4095(%r5)
sll %r6,4095(%r5)
slr %r6,%r9
sp 4095(6,%r5),4095(9,%r10)
spka 4095(%r5)
spm %r6
spt 4095(%r5)
spx 4095(%r5)
sqdb %f6,4095(%r5,%r10)
sqdbr %f6,%f9
sqdr %f6,%f9
sqe %f6,4095(%r5,%r10)
sqd %f6,4095(%r5,%r10)
sqeb %f6,4095(%r5,%r10)
sqebr %f6,%f9
sqer %f6,%f9
sqxbr %f5,%f8
sqxr %f5,%f8
sr %r6,%r9
sra %r6,4095(%r5)
srda %r6,4095(%r5)
srdl %r6,4095(%r5)
srl %r6,4095(%r5)
srnm 4095(%r5)
srp 4095(16,%r5),4095(%r10),10
srst %r6,%r9
ssar %r6
ssch 4095(%r5)
sske %r6,%r9
ssm 4095(%r5)
st %r6,4095(%r5,%r10)
stam %a6,%a9,4095(%r5)
stap 4095(%r5)
stc %r6,4095(%r5,%r10)
stck 4095(%r5)
stckc 4095(%r5)
stcke 4095(%r5)
stcm %r6,10,4095(%r5)
stcps 4095(%r5)
stcrw 4095(%r5)
stctl %c6,%c9,4095(%r5)
std %f6,4095(%r5,%r10)
ste %f6,4095(%r5,%r10)
stfpc 4095(%r5)
sth %r6,4095(%r5,%r10)
stidp 4095(%r5)
stm %r6,%r9,4095(%r5)
stnsm 4095(%r5),255
stosm 4095(%r5),255
stpt 4095(%r5)
stpx 4095(%r5)
stsch 4095(%r5)
stsi 4095(%r5)
stura %r6,%r9
su %f6,4095(%r5,%r10)
sur %f6,%f9
svc 255
sw %f6,4095(%r5,%r10)
swr %f6,%f9
sxbr %f5,%f8
sxr %f5,%f8
tar %a6,%r9
tb %r6,%r9
tbdr %r6,5,%r9
tbedr %r6,5,%r9
tcdb %f6,4095(%r5,%r10)
tceb %f6,4095(%r5,%r10)
tcxb %f5,4095(%r5,%r10)
thder %f6,%f9
thdr %f6,%f9
tm 4095(%r5),255
tmh %r6,65535
tml %r6,65535
tmlh %r6,65535
tmll %r6,65535
tp 4095(6,%r5)
tpi 4095(%r5)
tprot 4095(%r5),4095(%r10)
tr 4095(256,%r5),4095(%r10)
trace %r6,%r9,4095(%r5)
trap2
trap4 4095(%r5)
tre %r6,%r9
troo %r6,%r9
trot %r6,%r9
trt 4095(256,%r5),4095(%r10)
trto %r6,%r9
trtt %r6,%r9
ts 4095(%r5)
tsch 4095(%r5)
unpk 4095(6,%r5),4095(9,%r10)
unpka 4095(256,%r5),4095(%r10)
unpku 4095(256,%r5),4095(%r10)
upt
x %r6,4095(%r5,%r10)
xc 4095(256,%r5),4095(%r10)
xi 4095(%r5),255
xr %r6,%r9
xsch
zap 4095(6,%r5),4095(9,%r10)
ipte %r6,%r9,%r11
ipte %r6,%r9,%r11,13
|
tactcomplabs/xbgas-binutils-gdb
| 2,724
|
gas/testsuite/gas/s390/zarch-z900.s
|
.text
foo:
ag %r9,4095(%r5,%r10)
agf %r9,4095(%r5,%r10)
agfr %r9,%r6
aghi %r9,-32767
agr %r9,%r6
alcg %r9,4095(%r5,%r10)
alcgr %r9,%r6
alg %r9,4095(%r5,%r10)
algf %r9,4095(%r5,%r10)
algfr %r9,%r6
algr %r9,%r6
bctg %r9,4095(%r5,%r10)
bctgr %r9,%r6
brctg %r9,.
jctg %r6,.
brxhg %r9,%r6,.
jxhg %r6,%r9,.
brxlg %r9,%r6,.
jxleg %r6,%r9,.
bxhg %r9,%r6,4095(%r5)
bxleg %r9,%r6,4095(%r5)
cdgbr %f9,%r6
cdgr %f9,%r6
cdsg %r8,%r6,4095(%r5)
cegbr %f9,%r6
cegr %f9,%r6
cg %r9,4095(%r5,%r10)
cgdbr %r6,15,%f5
cgdr %r6,15,%f5
cgebr %r6,15,%f5
cger %r6,15,%f5
cgf %r9,4095(%r5,%r10)
cgfr %r9,%r6
cghi %r9,-32767
cgr %r9,%r6
cgxbr %r6,15,%f4
cgxr %r6,15,%f4
clg %r9,4095(%r5,%r10)
clgf %r9,4095(%r5,%r10)
clgfr %r9,%r6
clgr %r9,%r6
clmh %r9,10,4095(%r5)
csg %r9,%r6,4095(%r5)
cvbg %r9,4095(%r5,%r10)
cvdg %r9,4095(%r5,%r10)
cxgbr %f8,%r6
cxgr %f8,%r6
dlg %r8,4095(%r5,%r10)
dlgr %r8,%r6
dsg %r8,4095(%r5,%r10)
dsgf %r8,4095(%r5,%r10)
dsgfr %r8,%r6
dsgr %r8,%r6
eregg %r9,%r6
esea %r9
icmh %r9,10,4095(%r5)
iihh %r9,65535
iihl %r9,65535
iilh %r9,65535
iill %r9,65535
lcgfr %r9,%r6
lcgr %r9,%r6
lctlg %c9,%c6,4095(%r5)
lg %r9,4095(%r5,%r10)
lgf %r9,4095(%r5,%r10)
lgfr %r9,%r6
lgh %r9,4095(%r5,%r10)
lghi %r9,-32767
lgr %r9,%r6
llgc %r9,4095(%r5,%r10)
llgf %r9,4095(%r5,%r10)
llgfr %r9,%r6
llgh %r9,4095(%r5,%r10)
llgt %r9,4095(%r5,%r10)
llgtr %r9,%r6
llihh %r9,65535
llihl %r9,65535
llilh %r9,65535
llill %r9,65535
lmd %r9,%r6,4095(%r5),4095(%r10)
lmg %r9,%r6,4095(%r5)
lmh %r9,%r6,4095(%r5)
lngfr %r9,%r6
lngr %r9,%r6
lpgfr %r9,%r6
lpgr %r9,%r6
lpq %r8,4095(%r5,%r10)
lpswe 4095(%r5)
lrag %r9,4095(%r5,%r10)
lrvg %r9,4095(%r5,%r10)
lrvgr %r9,%r6
ltgfr %r9,%r6
ltgr %r9,%r6
lurag %r9,%r6
mghi %r9,-32767
mlg %r8,4095(%r5,%r10)
mlgr %r8,%r6
msg %r9,4095(%r5,%r10)
msgf %r9,4095(%r5,%r10)
msgfr %r9,%r6
msgr %r9,%r6
ng %r9,4095(%r5,%r10)
ngr %r9,%r6
nihh %r9,65535
nihl %r9,65535
nilh %r9,65535
nill %r9,65535
og %r9,4095(%r5,%r10)
ogr %r9,%r6
oihh %r9,65535
oihl %r9,65535
oilh %r9,65535
oill %r9,65535
rllg %r9,%r6,4095(%r5)
sam64
sg %r9,4095(%r5,%r10)
sgf %r9,4095(%r5,%r10)
sgfr %r9,%r6
sgr %r9,%r6
slag %r9,%r6,4095(%r5)
slbg %r9,4095(%r5,%r10)
slbgr %r9,%r6
slg %r9,4095(%r5,%r10)
slgf %r9,4095(%r5,%r10)
slgfr %r9,%r6
slgr %r9,%r6
sllg %r9,%r6,4095(%r5)
srag %r9,%r6,4095(%r5)
srlg %r9,%r6,4095(%r5)
stcmh %r9,10,4095(%r5)
stctg %c9,%c6,4095(%r5)
stg %r9,4095(%r5,%r10)
stmg %r9,%r6,4095(%r5)
stmh %r9,%r6,4095(%r5)
stpq %r9,4095(%r5,%r10)
strag 4095(%r5),4095(%r9)
strvg %r9,4095(%r5,%r10)
sturg %r9,%r6
tmhh %r9,65535
tmhl %r9,65535
tracg %r9,%r6,4095(%r5)
xg %r9,4095(%r5,%r10)
xgr %r9,%r6
|
tactcomplabs/xbgas-binutils-gdb
| 4,787
|
gas/testsuite/gas/s390/zarch-arch12.s
|
.text
foo:
vbperm %v15,%v17,%v20
vllezlf %v15,4000(%r6,%r9)
vmsl %v15,%v17,%v20,%v24,13,12
vmslg %v15,%v17,%v20,%v24,13
vnx %v15,%v17,%v20
vnn %v15,%v17,%v20
voc %v15,%v17,%v20
vpopctb %v15,%v17
vpopcth %v15,%v17
vpopctf %v15,%v17
vpopctg %v15,%v17
vfasb %v15,%v17,%v20
wfasb %v15,%v17,%v20
wfaxb %v15,%v17,%v20
wfcsb %v15,%v17
wfcxb %v15,%v17
wfksb %v15,%v17
wfkxb %v15,%v17
vfcesb %v15,%v17,%v20
vfcesbs %v15,%v17,%v20
wfcesb %v15,%v17,%v20
wfcesbs %v15,%v17,%v20
wfcexb %v15,%v17,%v20
wfcexbs %v15,%v17,%v20
vfkesb %v15,%v17,%v20
vfkesbs %v15,%v17,%v20
wfkesb %v15,%v17,%v20
wfkesbs %v15,%v17,%v20
vfkedb %v15,%v17,%v20
vfkedbs %v15,%v17,%v20
wfkedb %v15,%v17,%v20
wfkedbs %v15,%v17,%v20
wfkexb %v15,%v17,%v20
wfkexbs %v15,%v17,%v20
vfchsb %v15,%v17,%v20
vfchsbs %v15,%v17,%v20
wfchsb %v15,%v17,%v20
wfchsbs %v15,%v17,%v20
wfchxb %v15,%v17,%v20
wfchxbs %v15,%v17,%v20
vfkhsb %v15,%v17,%v20
vfkhsbs %v15,%v17,%v20
wfkhsb %v15,%v17,%v20
wfkhsbs %v15,%v17,%v20
vfkhdb %v15,%v17,%v20
vfkhdbs %v15,%v17,%v20
wfkhdb %v15,%v17,%v20
wfkhdbs %v15,%v17,%v20
wfkhxb %v15,%v17,%v20
wfkhxbs %v15,%v17,%v20
vfchesb %v15,%v17,%v20
vfchesbs %v15,%v17,%v20
wfchesb %v15,%v17,%v20
wfchesbs %v15,%v17,%v20
wfchexb %v15,%v17,%v20
wfchexbs %v15,%v17,%v20
vfkhesb %v15,%v17,%v20
vfkhesbs %v15,%v17,%v20
wfkhesb %v15,%v17,%v20
wfkhesbs %v15,%v17,%v20
vfkhedb %v15,%v17,%v20
vfkhedbs %v15,%v17,%v20
wfkhedb %v15,%v17,%v20
wfkhedbs %v15,%v17,%v20
wfkhexb %v15,%v17,%v20
wfkhexbs %v15,%v17,%v20
vfdsb %v15,%v17,%v20
wfdsb %v15,%v17,%v20
wfdxb %v15,%v17,%v20
vfisb %v15,%v17,13,12
wfisb %v15,%v17,13,12
wfixb %v15,%v17,13,12
vfll %v15,%v17,13,12
vflls %v15,%v17
wflls %v15,%v17
wflld %v15,%v17
vflr %v15,%v17,13,12,11
vflrd %v15,%v17,13,12
wflrd %v15,%v17,13,12
wflrx %v15,%v17,13,12
vfmax %v15,%v17,%v20,13,12,11
vfmaxsb %v15,%v17,%v20,13
vfmaxdb %v15,%v17,%v20,13
wfmaxsb %v15,%v17,%v20,13
wfmaxdb %v15,%v17,%v20,13
wfmaxxb %v15,%v17,%v20,13
vfmin %v15,%v17,%v20,13,12,11
vfminsb %v15,%v17,%v20,13
vfmindb %v15,%v17,%v20,13
wfminsb %v15,%v17,%v20,13
wfmindb %v15,%v17,%v20,13
wfminxb %v15,%v17,%v20,13
vfmsb %v15,%v17,%v20
wfmsb %v15,%v17,%v20
wfmxb %v15,%v17,%v20
vfmasb %v15,%v17,%v20,%v24
wfmasb %v15,%v17,%v20,%v24
wfmaxb %v15,%v17,%v20,%v24
vfmssb %v15,%v17,%v20,%v24
wfmssb %v15,%v17,%v20,%v24
wfmsxb %v15,%v17,%v20,%v24
vfnma %v15,%v17,%v20,%v24,13,12
vfnmasb %v15,%v17,%v20,%v24
wfnmasb %v15,%v17,%v20,%v24
vfnmadb %v15,%v17,%v20,%v24
wfnmadb %v15,%v17,%v20,%v24
wfnmaxb %v15,%v17,%v20,%v24
vfnms %v15,%v17,%v20,%v24,13,12
vfnmssb %v15,%v17,%v20,%v24
wfnmssb %v15,%v17,%v20,%v24
vfnmsdb %v15,%v17,%v20,%v24
wfnmsdb %v15,%v17,%v20,%v24
wfnmsxb %v15,%v17,%v20,%v24
vfpsosb %v15,%v17,13
wfpsosb %v15,%v17,13
vflcsb %v15,%v17
wflcsb %v15,%v17
vflnsb %v15,%v17
wflnsb %v15,%v17
vflpsb %v15,%v17
wflpsb %v15,%v17
wfpsoxb %v15,%v17,13
wflcxb %v15,%v17
wflnxb %v15,%v17
wflpxb %v15,%v17
vfsqsb %v15,%v17
wfsqsb %v15,%v17
wfsqxb %v15,%v17
vfssb %v15,%v17,%v20
wfssb %v15,%v17,%v20
wfsxb %v15,%v17,%v20
vftcisb %v15,%v17,4093
wftcisb %v15,%v17,4093
wftcixb %v15,%v17,4093
agh %r6,-10000(%r9,%r11)
bic 13,-10000(%r6,%r9)
bi -10000(%r6,%r9)
bio -10000(%r6,%r9)
bih -10000(%r6,%r9)
bip -10000(%r6,%r9)
binle -10000(%r6,%r9)
bil -10000(%r6,%r9)
bim -10000(%r6,%r9)
binhe -10000(%r6,%r9)
bilh -10000(%r6,%r9)
bine -10000(%r6,%r9)
binz -10000(%r6,%r9)
bie -10000(%r6,%r9)
biz -10000(%r6,%r9)
binlh -10000(%r6,%r9)
bihe -10000(%r6,%r9)
binl -10000(%r6,%r9)
binm -10000(%r6,%r9)
bile -10000(%r6,%r9)
binh -10000(%r6,%r9)
binp -10000(%r6,%r9)
bino -10000(%r6,%r9)
mgrk %r6,%r9,%r11
mg %r6,-10000(%r9,%r11)
mgh %r6,-10000(%r9,%r11)
msrkc %r6,%r9,%r11
msgrkc %r6,%r9,%r11
msc %r6,-10000(%r9,%r11)
msgc %r6,-10000(%r9,%r11)
sgh %r6,-10000(%r9,%r11)
vlrlr %v15,%r6,4000(%r9)
vlrl %v15,4000(%r6),253
vstrlr %v15,%r6,4000(%r9)
vstrl %v15,4000(%r6),253
vap %v15,%v17,%v20,253,12
vcp %v15,%v17,13
vcvb %r6,%v15,13
vcvbg %r6,%v15,13
vcvd %v15,%r6,253,12
vcvdg %v15,%r6,253,12
vdp %v15,%v17,%v20,253,12
vlip %v15,65533,12
vmp %v15,%v17,%v20,253,12
vmsp %v15,%v17,%v20,253,12
vpkz %v15,4000(%r6),253
vpsop %v15,%v17,253,252,11
vrp %v15,%v17,%v20,253,12
vsdp %v15,%v17,%v20,253,12
vsrp %v15,%v17,253,252,11
vsp %v15,%v17,%v20,253,12
vtp %v15
vupkz %v15,4000(%r6),253
lgg %r6,-10000(%r9,%r11)
llgfsg %r6,-10000(%r9,%r11)
lgsc %r6,-10000(%r9,%r11)
stgsc %r6,-10000(%r9,%r11)
kma %r6,%r9,%r11
prno %r6,%r9
tpei %r6,%r9
irbm %r6,%r9
vl %v15,4000(%r6,%r9)
vl %v15,4000(%r6,%r9),13
vlm %v15,%v17,4000(%r6)
vlm %v15,%v17,4000(%r6),13
vst %v15,4000(%r6,%r9)
vst %v15,4000(%r6,%r9),13
vstm %v15,%v17,4000(%r6)
vstm %v15,%v17,4000(%r6),13
|
tactcomplabs/xbgas-binutils-gdb
| 1,329
|
gas/testsuite/gas/s390/zarch-z9-ec.s
|
.text
foo:
lpdfr %f6,%f2
lndfr %f6,%f2
cpsdr %f6,%f1,%f2
lcdfr %f6,%f2
ldgr %f6,%r2
lgdr %r2,%f6
adtr %f6,%f2,%f4
axtr %f8,%f9,%f4
cdtr %f6,%f2
cxtr %f1,%f0
kdtr %f6,%f2
kxtr %f6,%f2
cedtr %f6,%f2
cextr %f1,%f0
cdgtr %f6,%r2
cxgtr %f1,%r2
cdstr %f6,%r2
cxstr %f6,%r2
cdutr %f6,%r2
cxutr %f1,%r2
cgdtr %r2,1,%f6
cgxtr %r2,1,%f1
csdtr %r6,%f3,13
csxtr %r6,%f1,13
cudtr %r2,%f6
cuxtr %r2,%f1
ddtr %f6,%f2,%f4
dxtr %f1,%f0,%f4
eedtr %r2,%f6
eextr %r2,%f1
esdtr %r2,%f6
esxtr %r2,%f1
iedtr %f6,%f2,%r4
iextr %f1,%f0,%r4
ltdtr %f6,%f2
ltxtr %f5,%f4
fidtr %f6,1,%f2,3
fixtr %f5,1,%f4,3
lfas 3(%r1)
ldetr %f6,%f2,1
lxdtr %f4,%f2,1
ledtr %f6,1,%f2,3
ldxtr %f6,1,%f4,3
mdtr %f6,%f2,%f4
mxtr %f9,%f8,%f4
qadtr %f6,%f2,%f4,1
qaxtr %f9,%f8,%f4,1
rrdtr %f6,%f2,%r4,1
rrxtr %f9,%f8,%r4,1
srnmt 3(%r1)
sfasr %r2
sldt %f6,%f2,3(%r1,%r4)
slxt %f5,%f4,3(%r1,%r4)
srdt %f6,%f2,3(%r1,%r4)
srxt %f5,%f4,3(%r1,%r4)
sdtr %f6,%f2,%f4
sxtr %f5,%f1,%f4
tdcet %f6,3(%r1,%r2)
tdcdt %f6,3(%r1,%r2)
tdcxt %f5,3(%r1,%r2)
tdget %f6,3(%r1,%r2)
tdgdt %f6,3(%r1,%r2)
tdgxt %f5,3(%r1,%r2)
pfpo
ectg 10(%r1),20(%r2),%r3
csst 10(%r1),20(%r2),%r3
/* The following .data section is 4 byte aligned.
So we get 2 additional bytes of 07 07 wherefor
we have to provide an instruction. */
bcr 0,%r7
|
tactcomplabs/xbgas-binutils-gdb
| 7,642
|
gas/testsuite/gas/s390/zarch-z10.s
|
.text
foo:
asi 5555(%r6),-42
agsi 5555(%r6),-42
alsi 5555(%r6),-42
algsi 5555(%r6),-42
crl %r6,.
cgrl %r6,.
cgfrl %r6,.
crb %r6,%r7,10,1111(%r8)
crbh %r6,%r7,1111(%r8)
crbnle %r6,%r7,1111(%r8)
crbl %r6,%r7,1111(%r8)
crbnhe %r6,%r7,1111(%r8)
crblh %r6,%r7,1111(%r8)
crbne %r6,%r7,1111(%r8)
crbe %r6,%r7,1111(%r8)
crbnlh %r6,%r7,1111(%r8)
crbhe %r6,%r7,1111(%r8)
crbnl %r6,%r7,1111(%r8)
crble %r6,%r7,1111(%r8)
crbnh %r6,%r7,1111(%r8)
cgrb %r6,%r7,10,1111(%r8)
cgrbh %r6,%r7,1111(%r8)
cgrbnle %r6,%r7,1111(%r8)
cgrbl %r6,%r7,1111(%r8)
cgrbnhe %r6,%r7,1111(%r8)
cgrblh %r6,%r7,1111(%r8)
cgrbne %r6,%r7,1111(%r8)
cgrbe %r6,%r7,1111(%r8)
cgrbnlh %r6,%r7,1111(%r8)
cgrbhe %r6,%r7,1111(%r8)
cgrbnl %r6,%r7,1111(%r8)
cgrble %r6,%r7,1111(%r8)
cgrbnh %r6,%r7,1111(%r8)
crj %r6,%r7,10,.
crjh %r6,%r7,.
crjnle %r6,%r7,.
crjl %r6,%r7,.
crjnhe %r6,%r7,.
crjlh %r6,%r7,.
crjne %r6,%r7,.
crje %r6,%r7,.
crjnlh %r6,%r7,.
crjhe %r6,%r7,.
crjnl %r6,%r7,.
crjle %r6,%r7,.
crjnh %r6,%r7,.
cgrj %r6,%r7,10,.
cgrjh %r6,%r7,.
cgrjnle %r6,%r7,.
cgrjl %r6,%r7,.
cgrjnhe %r6,%r7,.
cgrjlh %r6,%r7,.
cgrjne %r6,%r7,.
cgrje %r6,%r7,.
cgrjnlh %r6,%r7,.
cgrjhe %r6,%r7,.
cgrjnl %r6,%r7,.
cgrjle %r6,%r7,.
cgrjnh %r6,%r7,.
cib %r6,-42,10,1111(%r7)
cibh %r6,-42,1111(%r7)
cibnle %r6,-42,1111(%r7)
cibl %r6,-42,1111(%r7)
cibnhe %r6,-42,1111(%r7)
ciblh %r6,-42,1111(%r7)
cibne %r6,-42,1111(%r7)
cibe %r6,-42,1111(%r7)
cibnlh %r6,-42,1111(%r7)
cibhe %r6,-42,1111(%r7)
cibnl %r6,-42,1111(%r7)
cible %r6,-42,1111(%r7)
cibnh %r6,-42,1111(%r7)
cgib %r6,-42,10,1111(%r7)
cgibh %r6,-42,1111(%r7)
cgibnle %r6,-42,1111(%r7)
cgibl %r6,-42,1111(%r7)
cgibnhe %r6,-42,1111(%r7)
cgiblh %r6,-42,1111(%r7)
cgibne %r6,-42,1111(%r7)
cgibe %r6,-42,1111(%r7)
cgibnlh %r6,-42,1111(%r7)
cgibhe %r6,-42,1111(%r7)
cgibnl %r6,-42,1111(%r7)
cgible %r6,-42,1111(%r7)
cgibnh %r6,-42,1111(%r7)
cij %r6,-42,10,.
cijh %r6,-42,.
cijnle %r6,-42,.
cijl %r6,-42,.
cijnhe %r6,-42,.
cijlh %r6,-42,.
cijne %r6,-42,.
cije %r6,-42,.
cijnlh %r6,-42,.
cijhe %r6,-42,.
cijnl %r6,-42,.
cijle %r6,-42,.
cijnh %r6,-42,.
cgij %r6,-42,10,.
cgijh %r6,-42,.
cgijnle %r6,-42,.
cgijl %r6,-42,.
cgijnhe %r6,-42,.
cgijlh %r6,-42,.
cgijne %r6,-42,.
cgije %r6,-42,.
cgijnlh %r6,-42,.
cgijhe %r6,-42,.
cgijnl %r6,-42,.
cgijle %r6,-42,.
cgijnh %r6,-42,.
crt %r6,%r7,10
crth %r6,%r7
crtnle %r6,%r7
crtl %r6,%r7
crtnhe %r6,%r7
crtlh %r6,%r7
crtne %r6,%r7
crte %r6,%r7
crtnlh %r6,%r7
crthe %r6,%r7
crtnl %r6,%r7
crtle %r6,%r7
crtnh %r6,%r7
cgrt %r6,%r7,10
cgrth %r6,%r7
cgrtnle %r6,%r7
cgrtl %r6,%r7
cgrtnhe %r6,%r7
cgrtlh %r6,%r7
cgrtne %r6,%r7
cgrte %r6,%r7
cgrtnlh %r6,%r7
cgrthe %r6,%r7
cgrtnl %r6,%r7
cgrtle %r6,%r7
cgrtnh %r6,%r7
cit %r6,-30000,10
cith %r6,-30000
citnle %r6,-30000
citl %r6,-30000
citnhe %r6,-30000
citlh %r6,-30000
citne %r6,-30000
cite %r6,-30000
citnlh %r6,-30000
cithe %r6,-30000
citnl %r6,-30000
citle %r6,-30000
citnh %r6,-30000
cgit %r6,-30000,10
cgith %r6,-30000
cgitnle %r6,-30000
cgitl %r6,-30000
cgitnhe %r6,-30000
cgitlh %r6,-30000
cgitne %r6,-30000
cgite %r6,-30000
cgitnlh %r6,-30000
cgithe %r6,-30000
cgitnl %r6,-30000
cgitle %r6,-30000
cgitnh %r6,-30000
cgh %r6,5555(%r7,%r8)
chhsi 1111(%r6),-30000
chsi 1111(%r6),-30000
cghsi 1111(%r6),-30000
chrl %r6,.
cghrl %r6,.
clhhsi 1111(%r6),40000
clfhsi 1111(%r6),40000
clghsi 1111(%r6),40000
clrl %r6,.
clgrl %r6,.
clgfrl %r6,.
clhrl %r6,.
clghrl %r6,.
clrb %r6,%r7,10,1111(%r8)
clrbh %r6,%r7,1111(%r8)
clrbnle %r6,%r7,1111(%r8)
clrbl %r6,%r7,1111(%r8)
clrbnhe %r6,%r7,1111(%r8)
clrblh %r6,%r7,1111(%r8)
clrbne %r6,%r7,1111(%r8)
clrbe %r6,%r7,1111(%r8)
clrbnlh %r6,%r7,1111(%r8)
clrbhe %r6,%r7,1111(%r8)
clrbnl %r6,%r7,1111(%r8)
clrble %r6,%r7,1111(%r8)
clrbnh %r6,%r7,1111(%r8)
clgrb %r6,%r7,10,1111(%r8)
clgrbh %r6,%r7,1111(%r8)
clgrbnle %r6,%r7,1111(%r8)
clgrbl %r6,%r7,1111(%r8)
clgrbnhe %r6,%r7,1111(%r8)
clgrblh %r6,%r7,1111(%r8)
clgrbne %r6,%r7,1111(%r8)
clgrbe %r6,%r7,1111(%r8)
clgrbnlh %r6,%r7,1111(%r8)
clgrbhe %r6,%r7,1111(%r8)
clgrbnl %r6,%r7,1111(%r8)
clgrble %r6,%r7,1111(%r8)
clgrbnh %r6,%r7,1111(%r8)
clrj %r6,%r7,10,.
clrjh %r6,%r7,.
clrjnle %r6,%r7,.
clrjl %r6,%r7,.
clrjnhe %r6,%r7,.
clrjlh %r6,%r7,.
clrjne %r6,%r7,.
clrje %r6,%r7,.
clrjnlh %r6,%r7,.
clrjhe %r6,%r7,.
clrjnl %r6,%r7,.
clrjle %r6,%r7,.
clrjnh %r6,%r7,.
clgrj %r6,%r7,10,.
clgrjh %r6,%r7,.
clgrjnle %r6,%r7,.
clgrjl %r6,%r7,.
clgrjnhe %r6,%r7,.
clgrjlh %r6,%r7,.
clgrjne %r6,%r7,.
clgrje %r6,%r7,.
clgrjnlh %r6,%r7,.
clgrjhe %r6,%r7,.
clgrjnl %r6,%r7,.
clgrjle %r6,%r7,.
clgrjnh %r6,%r7,.
clib %r6,200,10,1111(%r7)
clibh %r6,200,1111(%r7)
clibnle %r6,200,1111(%r7)
clibl %r6,200,1111(%r7)
clibnhe %r6,200,1111(%r7)
cliblh %r6,200,1111(%r7)
clibne %r6,200,1111(%r7)
clibe %r6,200,1111(%r7)
clibnlh %r6,200,1111(%r7)
clibhe %r6,200,1111(%r7)
clibnl %r6,200,1111(%r7)
clible %r6,200,1111(%r7)
clibnh %r6,200,1111(%r7)
clgib %r6,200,10,1111(%r7)
clgibh %r6,200,1111(%r7)
clgibnle %r6,200,1111(%r7)
clgibl %r6,200,1111(%r7)
clgibnhe %r6,200,1111(%r7)
clgiblh %r6,200,1111(%r7)
clgibne %r6,200,1111(%r7)
clgibe %r6,200,1111(%r7)
clgibnlh %r6,200,1111(%r7)
clgibhe %r6,200,1111(%r7)
clgibnl %r6,200,1111(%r7)
clgible %r6,200,1111(%r7)
clgibnh %r6,200,1111(%r7)
clij %r6,200,10,.
clijh %r6,200,.
clijnle %r6,200,.
clijl %r6,200,.
clijnhe %r6,200,.
clijlh %r6,200,.
clijne %r6,200,.
clije %r6,200,.
clijnlh %r6,200,.
clijhe %r6,200,.
clijnl %r6,200,.
clijle %r6,200,.
clijnh %r6,200,.
clgij %r6,200,10,.
clgijh %r6,200,.
clgijnle %r6,200,.
clgijl %r6,200,.
clgijnhe %r6,200,.
clgijlh %r6,200,.
clgijne %r6,200,.
clgije %r6,200,.
clgijnlh %r6,200,.
clgijhe %r6,200,.
clgijnl %r6,200,.
clgijle %r6,200,.
clgijnh %r6,200,.
clrt %r6,%r7,10
clrth %r6,%r7
clrtnle %r6,%r7
clrtl %r6,%r7
clrtnhe %r6,%r7
clrtlh %r6,%r7
clrtne %r6,%r7
clrte %r6,%r7
clrtnlh %r6,%r7
clrthe %r6,%r7
clrtnl %r6,%r7
clrtle %r6,%r7
clrtnh %r6,%r7
clgrt %r6,%r7,10
clgrth %r6,%r7
clgrtnle %r6,%r7
clgrtl %r6,%r7
clgrtnhe %r6,%r7
clgrtlh %r6,%r7
clgrtne %r6,%r7
clgrte %r6,%r7
clgrtnlh %r6,%r7
clgrthe %r6,%r7
clgrtnl %r6,%r7
clgrtle %r6,%r7
clgrtnh %r6,%r7
clfit %r6,30000,10
clfith %r6,30000
clfitnle %r6,30000
clfitl %r6,30000
clfitnhe %r6,30000
clfitlh %r6,30000
clfitne %r6,30000
clfite %r6,30000
clfitnlh %r6,30000
clfithe %r6,30000
clfitnl %r6,30000
clfitle %r6,30000
clfitnh %r6,30000
clgit %r6,30000,10
clgith %r6,30000
clgitnle %r6,30000
clgitl %r6,30000
clgitnhe %r6,30000
clgitlh %r6,30000
clgitne %r6,30000
clgite %r6,30000
clgitnlh %r6,30000
clgithe %r6,30000
clgitnl %r6,30000
clgitle %r6,30000
clgitnh %r6,30000
ecag %r6,%r7,1111(%r8)
lrl %r6,.
lgrl %r6,.
lgfrl %r6,.
laey %r6,5555(%r7,%r8)
ltgf %r6,5555(%r7,%r8)
lhrl %r6,.
lghrl %r6,.
llgfrl %r6,.
llhrl %r6,.
llghrl %r6,.
mvhhi 1111(%r6),-30000
mvhi 1111(%r6),-30000
mvghi 1111(%r6),-30000
mfy %r6,5555(%r7,%r8)
mhy %r6,5555(%r7,%r8)
msfi %r6,-100000
msgfi %r6,-100000
pfd 10,5555(%r6,%r7)
pfdrl 10,.
rnsbg %r6,%r7,210,220,230
rxsbg %r6,%r7,210,220,230
rosbg %r6,%r7,210,220,230
risbg %r6,%r7,210,20,230
risbg %r6,%r7,210,188,230
risbgz %r6,%r7,210,20,230
strl %r6,.
stgrl %r6,.
sthrl %r6,.
exrl %r6,.
mc 3333(%r6),238
ptf %r6
pfmf %r6,%r7
trte %r6,%r7,10
trte %r6,%r7
trtre %r6,%r7,10
trtre %r6,%r7
ecpga %r6,%r7
ecctr %r6,%r7
epctr %r6,%r7
lcctl 3333(%r6)
lpctl 3333(%r6)
lsctl 3333(%r6)
qctri 3333(%r6)
qsi 3333(%r6)
scctr %r6,%r7
spctr %r6,%r7
lpp 3333(%r6)
|
tactcomplabs/xbgas-binutils-gdb
| 5,178
|
gas/testsuite/gas/s390/zarch-z196.s
|
.text
foo:
ahhhr %r6,%r7,%r8
ahhlr %r6,%r7,%r8
aih %r6,-65000
alhhhr %r6,%r7,%r8
alhhlr %r6,%r7,%r8
alsih %r6,65000
alsihn %r6,65000
brcth %r6,.
chhr %r6,%r7
chlr %r6,%r7
chf %r6,5555(%r7,%r8)
cih %r6,65000
clhhr %r6,%r7
clhlr %r6,%r7
clhf %r6,5555(%r7,%r8)
clih %r6,650000
clih %r9,4000000000
lbh %r6,-5555(%r7,%r8)
lhh %r6,-5555(%r7,%r8)
lfh %r6,-5555(%r7,%r8)
llch %r6,-5555(%r7,%r8)
llhh %r6,-5555(%r7,%r8)
risbhg %r6,%r7,12,13,14
risblg %r6,%r7,12,13,14
stch %r6,-5555(%r7,%r8)
sthh %r6,-5555(%r7,%r8)
stfh %r6,-5555(%r7,%r8)
shhhr %r6,%r7,%r8
shhlr %r6,%r7,%r8
slhhhr %r6,%r7,%r8
slhhlr %r6,%r7,%r8
laa %r6,%r7,-5555(%r8)
laag %r6,%r7,-5555(%r8)
laal %r6,%r7,-5555(%r8)
laalg %r6,%r7,-5555(%r8)
lan %r6,%r7,-5555(%r8)
lang %r6,%r7,-5555(%r8)
lax %r6,%r7,-5555(%r8)
laxg %r6,%r7,-5555(%r8)
lao %r6,%r7,-5555(%r8)
laog %r6,%r7,-5555(%r8)
lpd %r6,2222(%r7),1111(%r8)
lpdg %r6,2222(%r7),1111(%r8)
locro %r6,%r7
locrh %r6,%r7
locrp %r6,%r7
locrnle %r6,%r7
locrl %r6,%r7
locrm %r6,%r7
locrnhe %r6,%r7
locrlh %r6,%r7
locrne %r6,%r7
locrnz %r6,%r7
locre %r6,%r7
locrz %r6,%r7
locrnlh %r6,%r7
locrhe %r6,%r7
locrnl %r6,%r7
locrnm %r6,%r7
locrle %r6,%r7
locrnh %r6,%r7
locrnp %r6,%r7
locrno %r6,%r7
locr %r6,%r7,8
locgro %r6,%r7
locgrh %r6,%r7
locgrp %r6,%r7
locgrnle %r6,%r7
locgrl %r6,%r7
locgrm %r6,%r7
locgrnhe %r6,%r7
locgrlh %r6,%r7
locgrne %r6,%r7
locgrnz %r6,%r7
locgre %r6,%r7
locgrz %r6,%r7
locgrnlh %r6,%r7
locgrhe %r6,%r7
locgrnl %r6,%r7
locgrnm %r6,%r7
locgrle %r6,%r7
locgrnh %r6,%r7
locgrnp %r6,%r7
locgrno %r6,%r7
locgr %r6,%r7,8
loco %r6,-5555(%r7)
loch %r6,-5555(%r7)
locp %r6,-5555(%r7)
locnle %r6,-5555(%r7)
locl %r6,-5555(%r7)
locm %r6,-5555(%r7)
locnhe %r6,-5555(%r7)
loclh %r6,-5555(%r7)
locne %r6,-5555(%r7)
locnz %r6,-5555(%r7)
loce %r6,-5555(%r7)
locz %r6,-5555(%r7)
locnlh %r6,-5555(%r7)
loche %r6,-5555(%r7)
locnl %r6,-5555(%r7)
locnm %r6,-5555(%r7)
locle %r6,-5555(%r7)
locnh %r6,-5555(%r7)
locnp %r6,-5555(%r7)
locno %r6,-5555(%r7)
loc %r6,-5555(%r7),8
locgo %r6,-5555(%r7)
locgh %r6,-5555(%r7)
locgp %r6,-5555(%r7)
locgnle %r6,-5555(%r7)
locgl %r6,-5555(%r7)
locgm %r6,-5555(%r7)
locgnhe %r6,-5555(%r7)
locglh %r6,-5555(%r7)
locgne %r6,-5555(%r7)
locgnz %r6,-5555(%r7)
locge %r6,-5555(%r7)
locgz %r6,-5555(%r7)
locgnlh %r6,-5555(%r7)
locghe %r6,-5555(%r7)
locgnl %r6,-5555(%r7)
locgnm %r6,-5555(%r7)
locgle %r6,-5555(%r7)
locgnh %r6,-5555(%r7)
locgnp %r6,-5555(%r7)
locgno %r6,-5555(%r7)
locg %r6,-5555(%r7),8
stoco %r6,-5555(%r7)
stoch %r6,-5555(%r7)
stocp %r6,-5555(%r7)
stocnle %r6,-5555(%r7)
stocl %r6,-5555(%r7)
stocm %r6,-5555(%r7)
stocnhe %r6,-5555(%r7)
stoclh %r6,-5555(%r7)
stocne %r6,-5555(%r7)
stocnz %r6,-5555(%r7)
stoce %r6,-5555(%r7)
stocz %r6,-5555(%r7)
stocnlh %r6,-5555(%r7)
stoche %r6,-5555(%r7)
stocnl %r6,-5555(%r7)
stocnm %r6,-5555(%r7)
stocle %r6,-5555(%r7)
stocnh %r6,-5555(%r7)
stocnp %r6,-5555(%r7)
stocno %r6,-5555(%r7)
stoc %r6,-5555(%r7),8
stocgo %r6,-5555(%r7)
stocgh %r6,-5555(%r7)
stocgp %r6,-5555(%r7)
stocgnle %r6,-5555(%r7)
stocgl %r6,-5555(%r7)
stocgm %r6,-5555(%r7)
stocgnhe %r6,-5555(%r7)
stocglh %r6,-5555(%r7)
stocgne %r6,-5555(%r7)
stocgnz %r6,-5555(%r7)
stocge %r6,-5555(%r7)
stocgz %r6,-5555(%r7)
stocgnlh %r6,-5555(%r7)
stocghe %r6,-5555(%r7)
stocgnl %r6,-5555(%r7)
stocgnm %r6,-5555(%r7)
stocgle %r6,-5555(%r7)
stocgnh %r6,-5555(%r7)
stocgnp %r6,-5555(%r7)
stocgno %r6,-5555(%r7)
stocg %r6,-5555(%r7),8
ark %r6,%r7,%r8
agrk %r6,%r7,%r8
ahik %r6,%r7,-32000
aghik %r6,%r7,-32000
alrk %r6,%r7,%r8
algrk %r6,%r7,%r8
alhsik %r6,%r7,-32000
alghsik %r6,%r7,-32000
nrk %r6,%r7,%r8
ngrk %r6,%r7,%r8
xrk %r6,%r7,%r8
xgrk %r6,%r7,%r8
ork %r6,%r7,%r8
ogrk %r6,%r7,%r8
slak %r6,%r7,-5555(%r8)
sllk %r6,%r7,-5555(%r8)
srak %r6,%r7,-5555(%r8)
srlk %r6,%r7,-5555(%r8)
srk %r6,%r7,%r8
sgrk %r6,%r7,%r8
slrk %r6,%r7,%r8
slgrk %r6,%r7,%r8
popcnt %r6,%r7
rrbm %r6,%r7
cefbra %f5,3,%r9,7
cdfbra %f5,3,%r9,7
cxfbra %f5,3,%r9,7
cegbra %f5,3,%r9,7
cdgbra %f5,3,%r9,7
cxgbra %f5,3,%r9,7
celfbr %f5,3,%r9,7
cdlfbr %f5,3,%r9,7
cxlfbr %f5,3,%r9,7
celgbr %f5,3,%r9,7
cdlgbr %f5,3,%r9,7
cxlgbr %f5,3,%r9,7
cfebra %r5,3,%f9,7
cfdbra %r5,3,%f9,7
cfxbra %r5,3,%f8,7
cgebra %r5,3,%f9,7
cgdbra %r5,3,%f9,7
cgxbra %r5,3,%f8,7
clfebr %r5,3,%f9,7
clfdbr %r5,3,%f9,7
clfxbr %r5,3,%f8,7
clgebr %r5,3,%f9,7
clgdbr %r5,3,%f9,7
clgxbr %r5,3,%f8,7
fiebra %f5,3,%f9,7
fidbra %f5,3,%f9,7
fixbra %f5,3,%f8,7
ledbra %f5,3,%f9,7
ldxbra %f5,3,%f8,7
lexbra %f5,3,%f8,7
adtra %f3,%f5,%f9,7
axtra %f1,%f4,%f5,7
cdgtra %f5,3,%r9,7
cdftr %f5,3,%r9,7
cxftr %f5,3,%r9,7
cxgtra %f5,3,%r9,7
cdlgtr %f5,3,%r9,7
cxlgtr %f5,3,%r9,7
cdlftr %f5,3,%r9,7
cxlftr %f5,3,%r9,7
cgdtra %r5,3,%f9,7
cgxtra %r5,3,%f8,7
cfdtr %r5,3,%f9,7
cfxtr %r5,3,%f9,7
clgdtr %r5,3,%f9,7
clgxtr %r5,3,%f8,7
clfdtr %r5,3,%f9,7
clfxtr %r5,3,%f8,7
ddtra %f3,%f5,%f9,7
dxtra %f1,%f4,%f5,7
mdtra %f3,%f5,%f9,7
mxtra %f1,%f4,%f5,7
sdtra %f3,%f5,%f9,7
sxtra %f1,%f4,%f5,7
srnmb 4000(%r7)
kmf %r5,%r6
kmo %r5,%r6
pcc
kmctr %r5,%r6,%r9
pckmo
|
tactcomplabs/xbgas-binutils-gdb
| 15,787
|
gas/testsuite/gas/s390/zarch-z13.s
|
.text
foo:
lcbb %r6,4000(%r9,%r11),13
vgef %v15,4000(%r6,%r9),13
vgeg %v15,4000(%r6,%r9),13
vgbm %v15,65533
vzero %v15
vone %v15
vgm %v15,253,252,11
vgmb %v15,253,252
vgmh %v15,253,252
vgmf %v15,253,252
vgmg %v15,253,252
vlr %v15,%v17
vlrep %v15,4000(%r6,%r9),13
vlrepb %v15,4000(%r6,%r9)
vlreph %v15,4000(%r6,%r9)
vlrepf %v15,4000(%r6,%r9)
vlrepg %v15,4000(%r6,%r9)
vleb %v15,4000(%r6,%r9),13
vleh %v15,4000(%r6,%r9),13
vlef %v15,4000(%r6,%r9),13
vleg %v15,4000(%r6,%r9),13
vleib %v15,-32765,12
vleih %v15,-32765,12
vleif %v15,-32765,12
vleig %v15,-32765,12
vlgv %r6,%v15,4000(%r9),13
vlgvb %r6,%v15,4000(%r9)
vlgvh %r6,%v15,4000(%r9)
vlgvf %r6,%v15,4000(%r9)
vlgvg %r6,%v15,4000(%r9)
vllez %v15,4000(%r6,%r9),13
vllezb %v15,4000(%r6,%r9)
vllezh %v15,4000(%r6,%r9)
vllezf %v15,4000(%r6,%r9)
vllezg %v15,4000(%r6,%r9)
vlbb %v15,4000(%r6,%r9),13
vlvg %v15,%r6,4000(%r9),13
vlvgb %v15,%r6,4000(%r9)
vlvgh %v15,%r6,4000(%r9)
vlvgf %v15,%r6,4000(%r9)
vlvgg %v15,%r6,4000(%r9)
vlvgp %v15,%r6,%r9
vll %v15,%r6,4000(%r9)
vmrh %v15,%v17,%v20,13
vmrhb %v15,%v17,%v20
vmrhh %v15,%v17,%v20
vmrhf %v15,%v17,%v20
vmrhg %v15,%v17,%v20
vmrl %v15,%v17,%v20,13
vmrlb %v15,%v17,%v20
vmrlh %v15,%v17,%v20
vmrlf %v15,%v17,%v20
vmrlg %v15,%v17,%v20
vpk %v15,%v17,%v20,13
vpkh %v15,%v17,%v20
vpkf %v15,%v17,%v20
vpkg %v15,%v17,%v20
vpks %v15,%v17,%v20,13,12
vpksh %v15,%v17,%v20
vpksf %v15,%v17,%v20
vpksg %v15,%v17,%v20
vpkshs %v15,%v17,%v20
vpksfs %v15,%v17,%v20
vpksgs %v15,%v17,%v20
vpkls %v15,%v17,%v20,13,12
vpklsh %v15,%v17,%v20
vpklsf %v15,%v17,%v20
vpklsg %v15,%v17,%v20
vpklshs %v15,%v17,%v20
vpklsfs %v15,%v17,%v20
vpklsgs %v15,%v17,%v20
vperm %v15,%v17,%v20,%v24
vpdi %v15,%v17,%v20,13
vrep %v15,%v17,65533,12
vrepb %v15,%v17,65533
vreph %v15,%v17,65533
vrepf %v15,%v17,65533
vrepg %v15,%v17,65533
vrepi %v15,-32765,12
vrepib %v15,-32765
vrepih %v15,-32765
vrepif %v15,-32765
vrepig %v15,-32765
vscef %v15,4000(%r6,%r9),13
vsceg %v15,4000(%r6,%r9),13
vsel %v15,%v17,%v20,%v24
vseg %v15,%v17,13
vsegb %v15,%v17
vsegh %v15,%v17
vsegf %v15,%v17
vsteb %v15,4000(%r6,%r9),13
vsteh %v15,4000(%r6,%r9),13
vstef %v15,4000(%r6,%r9),13
vsteg %v15,4000(%r6,%r9),13
vstl %v15,%r6,4000(%r9)
vuph %v15,%v17,13
vuphb %v15,%v17
vuphh %v15,%v17
vuphf %v15,%v17
vuplh %v15,%v17,13
vuplhb %v15,%v17
vuplhh %v15,%v17
vuplhf %v15,%v17
vupl %v15,%v17,13
vuplb %v15,%v17
vuplhw %v15,%v17
vuplf %v15,%v17
vupll %v15,%v17,13
vupllb %v15,%v17
vupllh %v15,%v17
vupllf %v15,%v17
va %v15,%v17,%v20,13
vab %v15,%v17,%v20
vah %v15,%v17,%v20
vaf %v15,%v17,%v20
vag %v15,%v17,%v20
vaq %v15,%v17,%v20
vacc %v15,%v17,%v20,13
vaccb %v15,%v17,%v20
vacch %v15,%v17,%v20
vaccf %v15,%v17,%v20
vaccg %v15,%v17,%v20
vaccq %v15,%v17,%v20
vac %v15,%v17,%v20,%v24,13
vacq %v15,%v17,%v20,%v24
vaccc %v15,%v17,%v20,%v24,13
vacccq %v15,%v17,%v20,%v24
vn %v15,%v17,%v20
vnc %v15,%v17,%v20
vavg %v15,%v17,%v20,13
vavgb %v15,%v17,%v20
vavgh %v15,%v17,%v20
vavgf %v15,%v17,%v20
vavgg %v15,%v17,%v20
vavgl %v15,%v17,%v20,13
vavglb %v15,%v17,%v20
vavglh %v15,%v17,%v20
vavglf %v15,%v17,%v20
vavglg %v15,%v17,%v20
vcksm %v15,%v17,%v20
vec %v15,%v17,13
vecb %v15,%v17
vech %v15,%v17
vecf %v15,%v17
vecg %v15,%v17
vecl %v15,%v17,13
veclb %v15,%v17
veclh %v15,%v17
veclf %v15,%v17
veclg %v15,%v17
vceq %v15,%v17,%v20,13,12
vceqb %v15,%v17,%v20
vceqh %v15,%v17,%v20
vceqf %v15,%v17,%v20
vceqg %v15,%v17,%v20
vceqbs %v15,%v17,%v20
vceqhs %v15,%v17,%v20
vceqfs %v15,%v17,%v20
vceqgs %v15,%v17,%v20
vch %v15,%v17,%v20,13,12
vchb %v15,%v17,%v20
vchh %v15,%v17,%v20
vchf %v15,%v17,%v20
vchg %v15,%v17,%v20
vchbs %v15,%v17,%v20
vchhs %v15,%v17,%v20
vchfs %v15,%v17,%v20
vchgs %v15,%v17,%v20
vchl %v15,%v17,%v20,13,12
vchlb %v15,%v17,%v20
vchlh %v15,%v17,%v20
vchlf %v15,%v17,%v20
vchlg %v15,%v17,%v20
vchlbs %v15,%v17,%v20
vchlhs %v15,%v17,%v20
vchlfs %v15,%v17,%v20
vchlgs %v15,%v17,%v20
vclz %v15,%v17,13
vclzb %v15,%v17
vclzh %v15,%v17
vclzf %v15,%v17
vclzg %v15,%v17
vctz %v15,%v17,13
vctzb %v15,%v17
vctzh %v15,%v17
vctzf %v15,%v17
vctzg %v15,%v17
vx %v15,%v17,%v20
vgfm %v15,%v17,%v20,13
vgfmb %v15,%v17,%v20
vgfmh %v15,%v17,%v20
vgfmf %v15,%v17,%v20
vgfmg %v15,%v17,%v20
vgfma %v15,%v17,%v20,%v24,13
vgfmab %v15,%v17,%v20,%v24
vgfmah %v15,%v17,%v20,%v24
vgfmaf %v15,%v17,%v20,%v24
vgfmag %v15,%v17,%v20,%v24
vlc %v15,%v17,13
vlcb %v15,%v17
vlch %v15,%v17
vlcf %v15,%v17
vlcg %v15,%v17
vlp %v15,%v17,13
vlpb %v15,%v17
vlph %v15,%v17
vlpf %v15,%v17
vlpg %v15,%v17
vmx %v15,%v17,%v20,13
vmxb %v15,%v17,%v20
vmxh %v15,%v17,%v20
vmxf %v15,%v17,%v20
vmxg %v15,%v17,%v20
vmxl %v15,%v17,%v20,13
vmxlb %v15,%v17,%v20
vmxlh %v15,%v17,%v20
vmxlf %v15,%v17,%v20
vmxlg %v15,%v17,%v20
vmn %v15,%v17,%v20,13
vmnb %v15,%v17,%v20
vmnh %v15,%v17,%v20
vmnf %v15,%v17,%v20
vmng %v15,%v17,%v20
vmnl %v15,%v17,%v20,13
vmnlb %v15,%v17,%v20
vmnlh %v15,%v17,%v20
vmnlf %v15,%v17,%v20
vmnlg %v15,%v17,%v20
vmal %v15,%v17,%v20,%v24,13
vmalb %v15,%v17,%v20,%v24
vmalhw %v15,%v17,%v20,%v24
vmalf %v15,%v17,%v20,%v24
vmah %v15,%v17,%v20,%v24,13
vmahb %v15,%v17,%v20,%v24
vmahh %v15,%v17,%v20,%v24
vmahf %v15,%v17,%v20,%v24
vmalh %v15,%v17,%v20,%v24,13
vmalhb %v15,%v17,%v20,%v24
vmalhh %v15,%v17,%v20,%v24
vmalhf %v15,%v17,%v20,%v24
vmae %v15,%v17,%v20,%v24,13
vmaeb %v15,%v17,%v20,%v24
vmaeh %v15,%v17,%v20,%v24
vmaef %v15,%v17,%v20,%v24
vmale %v15,%v17,%v20,%v24,13
vmaleb %v15,%v17,%v20,%v24
vmaleh %v15,%v17,%v20,%v24
vmalef %v15,%v17,%v20,%v24
vmao %v15,%v17,%v20,%v24,13
vmaob %v15,%v17,%v20,%v24
vmaoh %v15,%v17,%v20,%v24
vmaof %v15,%v17,%v20,%v24
vmalo %v15,%v17,%v20,%v24,13
vmalob %v15,%v17,%v20,%v24
vmaloh %v15,%v17,%v20,%v24
vmalof %v15,%v17,%v20,%v24
vmh %v15,%v17,%v20,13
vmhb %v15,%v17,%v20
vmhh %v15,%v17,%v20
vmhf %v15,%v17,%v20
vmlh %v15,%v17,%v20,13
vmlhb %v15,%v17,%v20
vmlhh %v15,%v17,%v20
vmlhf %v15,%v17,%v20
vml %v15,%v17,%v20,13
vmlb %v15,%v17,%v20
vmlhw %v15,%v17,%v20
vmlf %v15,%v17,%v20
vme %v15,%v17,%v20,13
vmeb %v15,%v17,%v20
vmeh %v15,%v17,%v20
vmef %v15,%v17,%v20
vmle %v15,%v17,%v20,13
vmleb %v15,%v17,%v20
vmleh %v15,%v17,%v20
vmlef %v15,%v17,%v20
vmo %v15,%v17,%v20,13
vmob %v15,%v17,%v20
vmoh %v15,%v17,%v20
vmof %v15,%v17,%v20
vmlo %v15,%v17,%v20,13
vmlob %v15,%v17,%v20
vmloh %v15,%v17,%v20
vmlof %v15,%v17,%v20
vno %v15,%v17,%v20
vnot %v15,%v17
vo %v15,%v17,%v20
vpopct %v15,%v17,13
verllv %v15,%v17,%v20,13
verllvb %v15,%v17,%v20
verllvh %v15,%v17,%v20
verllvf %v15,%v17,%v20
verllvg %v15,%v17,%v20
verll %v15,%v17,4000(%r6),13
verllb %v15,%v17,4000(%r6)
verllh %v15,%v17,4000(%r6)
verllf %v15,%v17,4000(%r6)
verllg %v15,%v17,4000(%r6)
verim %v15,%v17,%v20,253,12
verimb %v15,%v17,%v20,253
verimh %v15,%v17,%v20,253
verimf %v15,%v17,%v20,253
verimg %v15,%v17,%v20,253
veslv %v15,%v17,%v20,13
veslvb %v15,%v17,%v20
veslvh %v15,%v17,%v20
veslvf %v15,%v17,%v20
veslvg %v15,%v17,%v20
vesl %v15,%v17,4000(%r6),13
veslb %v15,%v17,4000(%r6)
veslh %v15,%v17,4000(%r6)
veslf %v15,%v17,4000(%r6)
veslg %v15,%v17,4000(%r6)
vesrav %v15,%v17,%v20,13
vesravb %v15,%v17,%v20
vesravh %v15,%v17,%v20
vesravf %v15,%v17,%v20
vesravg %v15,%v17,%v20
vesra %v15,%v17,4000(%r6),13
vesrab %v15,%v17,4000(%r6)
vesrah %v15,%v17,4000(%r6)
vesraf %v15,%v17,4000(%r6)
vesrag %v15,%v17,4000(%r6)
vesrlv %v15,%v17,%v20,13
vesrlvb %v15,%v17,%v20
vesrlvh %v15,%v17,%v20
vesrlvf %v15,%v17,%v20
vesrlvg %v15,%v17,%v20
vesrl %v15,%v17,4000(%r6),13
vesrlb %v15,%v17,4000(%r6)
vesrlh %v15,%v17,4000(%r6)
vesrlf %v15,%v17,4000(%r6)
vesrlg %v15,%v17,4000(%r6)
vsl %v15,%v17,%v20
vslb %v15,%v17,%v20
vsldb %v15,%v17,%v20,253
vsra %v15,%v17,%v20
vsrab %v15,%v17,%v20
vsrl %v15,%v17,%v20
vsrlb %v15,%v17,%v20
vs %v15,%v17,%v20,13
vsb %v15,%v17,%v20
vsh %v15,%v17,%v20
vsf %v15,%v17,%v20
vsg %v15,%v17,%v20
vsq %v15,%v17,%v20
vscbi %v15,%v17,%v20,13
vscbib %v15,%v17,%v20
vscbih %v15,%v17,%v20
vscbif %v15,%v17,%v20
vscbig %v15,%v17,%v20
vscbiq %v15,%v17,%v20
vsbi %v15,%v17,%v20,%v24,13
vsbiq %v15,%v17,%v20,%v24
vsbcbi %v15,%v17,%v20,%v24,13
vsbcbiq %v15,%v17,%v20,%v24
vsumg %v15,%v17,%v20,13
vsumgh %v15,%v17,%v20
vsumgf %v15,%v17,%v20
vsumq %v15,%v17,%v20,13
vsumqf %v15,%v17,%v20
vsumqg %v15,%v17,%v20
vsum %v15,%v17,%v20,13
vsumb %v15,%v17,%v20
vsumh %v15,%v17,%v20
vtm %v15,%v17
vfae %v15,%v17,%v20,13
vfae %v15,%v17,%v20,13,12
vfaeb %v15,%v17,%v20
vfaeb %v15,%v17,%v20,13
vfaeh %v15,%v17,%v20
vfaeh %v15,%v17,%v20,13
vfaef %v15,%v17,%v20
vfaef %v15,%v17,%v20,13
vfaebs %v15,%v17,%v20
vfaebs %v15,%v17,%v20,13
vfaehs %v15,%v17,%v20
vfaehs %v15,%v17,%v20,13
vfaefs %v15,%v17,%v20
vfaefs %v15,%v17,%v20,13
vfaezb %v15,%v17,%v20
vfaezb %v15,%v17,%v20,13
vfaezh %v15,%v17,%v20
vfaezh %v15,%v17,%v20,13
vfaezf %v15,%v17,%v20
vfaezf %v15,%v17,%v20,13
vfaezbs %v15,%v17,%v20
vfaezbs %v15,%v17,%v20,13
vfaezhs %v15,%v17,%v20
vfaezhs %v15,%v17,%v20,13
vfaezfs %v15,%v17,%v20
vfaezfs %v15,%v17,%v20,13
vfee %v15,%v17,%v20,13
vfee %v15,%v17,%v20,13,12
vfeeb %v15,%v17,%v20
vfeeb %v15,%v17,%v20,13
vfeeh %v15,%v17,%v20
vfeeh %v15,%v17,%v20,13
vfeef %v15,%v17,%v20
vfeef %v15,%v17,%v20,13
vfeebs %v15,%v17,%v20
vfeehs %v15,%v17,%v20
vfeefs %v15,%v17,%v20
vfeezb %v15,%v17,%v20
vfeezh %v15,%v17,%v20
vfeezf %v15,%v17,%v20
vfeezbs %v15,%v17,%v20
vfeezhs %v15,%v17,%v20
vfeezfs %v15,%v17,%v20
vfene %v15,%v17,%v20,13
vfene %v15,%v17,%v20,13,12
vfeneb %v15,%v17,%v20
vfeneb %v15,%v17,%v20,13
vfeneh %v15,%v17,%v20
vfeneh %v15,%v17,%v20,13
vfenef %v15,%v17,%v20
vfenef %v15,%v17,%v20,13
vfenebs %v15,%v17,%v20
vfenehs %v15,%v17,%v20
vfenefs %v15,%v17,%v20
vfenezb %v15,%v17,%v20
vfenezh %v15,%v17,%v20
vfenezf %v15,%v17,%v20
vfenezbs %v15,%v17,%v20
vfenezhs %v15,%v17,%v20
vfenezfs %v15,%v17,%v20
vistr %v15,%v17,13
vistr %v15,%v17,13,12
vistrb %v15,%v17
vistrb %v15,%v17,13
vistrh %v15,%v17
vistrh %v15,%v17,13
vistrf %v15,%v17
vistrf %v15,%v17,13
vistrbs %v15,%v17
vistrhs %v15,%v17
vistrfs %v15,%v17
vstrc %v15,%v17,%v20,%v24,13
vstrc %v15,%v17,%v20,%v24,13,12
vstrcb %v15,%v17,%v20,%v24
vstrcb %v15,%v17,%v20,%v24,13
vstrch %v15,%v17,%v20,%v24
vstrch %v15,%v17,%v20,%v24,13
vstrcf %v15,%v17,%v20,%v24
vstrcf %v15,%v17,%v20,%v24,13
vstrcbs %v15,%v17,%v20,%v24
vstrcbs %v15,%v17,%v20,%v24,13
vstrchs %v15,%v17,%v20,%v24
vstrchs %v15,%v17,%v20,%v24,13
vstrcfs %v15,%v17,%v20,%v24
vstrcfs %v15,%v17,%v20,%v24,13
vstrczb %v15,%v17,%v20,%v24
vstrczb %v15,%v17,%v20,%v24,13
vstrczh %v15,%v17,%v20,%v24
vstrczh %v15,%v17,%v20,%v24,13
vstrczf %v15,%v17,%v20,%v24
vstrczf %v15,%v17,%v20,%v24,13
vstrczbs %v15,%v17,%v20,%v24
vstrczbs %v15,%v17,%v20,%v24,13
vstrczhs %v15,%v17,%v20,%v24
vstrczhs %v15,%v17,%v20,%v24,13
vstrczfs %v15,%v17,%v20,%v24
vstrczfs %v15,%v17,%v20,%v24,13
vfa %v15,%v17,%v20,13,12
vfadb %v15,%v17,%v20
wfadb %v15,%v17,%v20
wfc %v15,%v17,13,12
wfcdb %v15,%v17
wfk %v15,%v17,13,12
wfkdb %v15,%v17
vfce %v15,%v17,%v20,13,12,11
vfcedb %v15,%v17,%v20
vfcedbs %v15,%v17,%v20
wfcedb %v15,%v17,%v20
wfcedbs %v15,%v17,%v20
vfch %v15,%v17,%v20,13,12,11
vfchdb %v15,%v17,%v20
vfchdbs %v15,%v17,%v20
wfchdb %v15,%v17,%v20
wfchdbs %v15,%v17,%v20
vfche %v15,%v17,%v20,13,12,11
vfchedb %v15,%v17,%v20
vfchedbs %v15,%v17,%v20
wfchedb %v15,%v17,%v20
wfchedbs %v15,%v17,%v20
vcdg %v15,%v17,13,12,11
vcdgb %v15,%v17,13,12
wcdgb %v15,%v17,13,12
vcdlg %v15,%v17,13,12,11
vcdlgb %v15,%v17,13,12
wcdlgb %v15,%v17,13,12
vcgd %v15,%v17,13,12,11
vcgdb %v15,%v17,13,12
wcgdb %v15,%v17,13,12
vclgd %v15,%v17,13,12,11
vclgdb %v15,%v17,13,12
wclgdb %v15,%v17,13,12
vfd %v15,%v17,%v20,13,12
vfddb %v15,%v17,%v20
wfddb %v15,%v17,%v20
vfi %v15,%v17,13,12,11
vfidb %v15,%v17,13,12
wfidb %v15,%v17,13,12
vlde %v15,%v17,13,12
vldeb %v15,%v17
wldeb %v15,%v17
vled %v15,%v17,13,12,11
vledb %v15,%v17,13,12
wledb %v15,%v17,13,12
vfm %v15,%v17,%v20,13,12
vfmdb %v15,%v17,%v20
wfmdb %v15,%v17,%v20
vfma %v15,%v17,%v20,%v24,13,12
vfmadb %v15,%v17,%v20,%v24
wfmadb %v15,%v17,%v20,%v24
vfms %v15,%v17,%v20,%v24,13,12
vfmsdb %v15,%v17,%v20,%v24
wfmsdb %v15,%v17,%v20,%v24
vfpso %v15,%v17,13,12,11
vfpsodb %v15,%v17,13
wfpsodb %v15,%v17,13
vflcdb %v15,%v17
wflcdb %v15,%v17
vflndb %v15,%v17
wflndb %v15,%v17
vflpdb %v15,%v17
wflpdb %v15,%v17
vfsq %v15,%v17,13,12
vfsqdb %v15,%v17
wfsqdb %v15,%v17
vfs %v15,%v17,%v20,13,12
vfsdb %v15,%v17,%v20
wfsdb %v15,%v17,%v20
vftci %v15,%v17,4093,12,11
vftcidb %v15,%v17,4093
wftcidb %v15,%v17,4093
cdpt %f3,4000(251,%r6),12
cxpt %f1,4000(251,%r6),12
cpdt %f3,4000(251,%r6),12
cpxt %f1,4000(251,%r6),12
locfhr %r6,%r9,13
locfhro %r6,%r9
locfhrh %r6,%r9
locfhrp %r6,%r9
locfhrnle %r6,%r9
locfhrl %r6,%r9
locfhrm %r6,%r9
locfhrnhe %r6,%r9
locfhrlh %r6,%r9
locfhrne %r6,%r9
locfhrnz %r6,%r9
locfhre %r6,%r9
locfhrz %r6,%r9
locfhrnlh %r6,%r9
locfhrhe %r6,%r9
locfhrnl %r6,%r9
locfhrnm %r6,%r9
locfhrle %r6,%r9
locfhrnh %r6,%r9
locfhrnp %r6,%r9
locfhrno %r6,%r9
locfh %r6,-10000(%r9),13
locfho %r6,-10000(%r9)
locfhh %r6,-10000(%r9)
locfhp %r6,-10000(%r9)
locfhnle %r6,-10000(%r9)
locfhl %r6,-10000(%r9)
locfhm %r6,-10000(%r9)
locfhnhe %r6,-10000(%r9)
locfhlh %r6,-10000(%r9)
locfhne %r6,-10000(%r9)
locfhnz %r6,-10000(%r9)
locfhe %r6,-10000(%r9)
locfhz %r6,-10000(%r9)
locfhnlh %r6,-10000(%r9)
locfhhe %r6,-10000(%r9)
locfhnl %r6,-10000(%r9)
locfhnm %r6,-10000(%r9)
locfhle %r6,-10000(%r9)
locfhnh %r6,-10000(%r9)
locfhnp %r6,-10000(%r9)
locfhno %r6,-10000(%r9)
lochi %r6,-32765,12
lochio %r6,-32765
lochih %r6,-32765
lochip %r6,-32765
lochinle %r6,-32765
lochil %r6,-32765
lochim %r6,-32765
lochinhe %r6,-32765
lochilh %r6,-32765
lochine %r6,-32765
lochinz %r6,-32765
lochie %r6,-32765
lochiz %r6,-32765
lochinlh %r6,-32765
lochihe %r6,-32765
lochinl %r6,-32765
lochinm %r6,-32765
lochile %r6,-32765
lochinh %r6,-32765
lochinp %r6,-32765
lochino %r6,-32765
locghi %r6,-32765,12
locghio %r6,-32765
locghih %r6,-32765
locghip %r6,-32765
locghinle %r6,-32765
locghil %r6,-32765
locghim %r6,-32765
locghinhe %r6,-32765
locghilh %r6,-32765
locghine %r6,-32765
locghinz %r6,-32765
locghie %r6,-32765
locghiz %r6,-32765
locghinlh %r6,-32765
locghihe %r6,-32765
locghinl %r6,-32765
locghinm %r6,-32765
locghile %r6,-32765
locghinh %r6,-32765
locghinp %r6,-32765
locghino %r6,-32765
lochhi %r6,-32765,12
lochhio %r6,-32765
lochhih %r6,-32765
lochhip %r6,-32765
lochhinle %r6,-32765
lochhil %r6,-32765
lochhim %r6,-32765
lochhinhe %r6,-32765
lochhilh %r6,-32765
lochhine %r6,-32765
lochhinz %r6,-32765
lochhie %r6,-32765
lochhiz %r6,-32765
lochhinlh %r6,-32765
lochhihe %r6,-32765
lochhinl %r6,-32765
lochhinm %r6,-32765
lochhile %r6,-32765
lochhinh %r6,-32765
lochhinp %r6,-32765
lochhino %r6,-32765
stocfh %r6,-10000(%r9),13
stocfho %r6,-10000(%r9)
stocfhh %r6,-10000(%r9)
stocfhp %r6,-10000(%r9)
stocfhnle %r6,-10000(%r9)
stocfhl %r6,-10000(%r9)
stocfhm %r6,-10000(%r9)
stocfhnhe %r6,-10000(%r9)
stocfhlh %r6,-10000(%r9)
stocfhne %r6,-10000(%r9)
stocfhnz %r6,-10000(%r9)
stocfhe %r6,-10000(%r9)
stocfhz %r6,-10000(%r9)
stocfhnlh %r6,-10000(%r9)
stocfhhe %r6,-10000(%r9)
stocfhnl %r6,-10000(%r9)
stocfhnm %r6,-10000(%r9)
stocfhle %r6,-10000(%r9)
stocfhnh %r6,-10000(%r9)
stocfhnp %r6,-10000(%r9)
stocfhno %r6,-10000(%r9)
llzrgf %r6,-10000(%r9,%r11)
lzrf %r6,-10000(%r9,%r11)
lzrg %r6,-10000(%r9,%r11)
ppno %r6,%r9
vl %v15,4000(%r6,%r9)
vl %v15,4000(%r6,%r9),13
vlm %v15,%v17,4000(%r6)
vlm %v15,%v17,4000(%r6),13
vst %v15,4000(%r6,%r9)
vst %v15,4000(%r6,%r9),13
vstm %v15,%v17,4000(%r6)
vstm %v15,%v17,4000(%r6),13
|
tactcomplabs/xbgas-binutils-gdb
| 12,646
|
gas/testsuite/gas/tic4x/addressing.s
|
;;
;; test all addressing modes and register constraints
;; (types/classes is read from include/opcodes/tic4x.h)
;;
.text
start:
;;
;; Type B - infix condition branch
;;
Type_BI:bu Type_BI ; Unconditional branch (00000)
bc Type_BI ; Carry branch (00001)
blo Type_BI ; Lower than branch (00001)
bls Type_BI ; Lower than or same branch (00010)
bhi Type_BI ; Higher than branch (00011)
bhs Type_BI ; Higher than or same branch (00100)
bnc Type_BI ; No carry branch (00100)
beq Type_BI ; Equal to branch (00101)
bz Type_BI ; Zero branch (00101)
bne Type_BI ; Not equal to branch (00110)
bnz Type_BI ; Not zero branch (00110)
blt Type_BI ; Less than branch (00111)
bn Type_BI ; Negative branch (00111)
ble Type_BI ; Less than or equal to branch (01000)
bgt Type_BI ; Greater than branch (01001)
bp Type_BI ; Positive branch (01001)
bge Type_BI ; Greater than or equal branch (01010)
bnn Type_BI ; Nonnegative branch (01010)
bnv Type_BI ; No overflow branch (01000)
bv Type_BI ; Overflow branch (01101)
bnuf Type_BI ; No underflow branch (01110)
buf Type_BI ; Underflow branch (01111)
bnlv Type_BI ; No latched overflow branch (10000)
blv Type_BI ; Latched overflow branch (10001)
bnluf Type_BI ; No latched FP underflow branch (10010)
bluf Type_BI ; Latched FP underflow branch (10011)
bzuf Type_BI ; Zero or FP underflow branch (10100)
b Type_BI ; Unconditional branch (00000)
;;
;; Type C - infix condition load
;;
Type_CI:ldiu R0,R0 ; Unconditional load (00000)
ldic R0,R0 ; Carry load (00001)
ldilo R0,R0 ; Lower than load (00001)
ldils R0,R0 ; Lower than or same load (00010)
ldihi R0,R0 ; Higher than load (00011)
ldihs R0,R0 ; Higher than or same load (00100)
ldinc R0,R0 ; No carry load (00100)
ldieq R0,R0 ; Equal to load (00101)
ldiz R0,R0 ; Zero load (00101)
ldine R0,R0 ; Not equal to load (00110)
ldinz R0,R0 ; Not zero load (00110)
ldil R0,R0 ; Less than load (00111)
ldin R0,R0 ; Negative load (00111)
ldile R0,R0 ; Less than or equal to load (01000)
ldigt R0,R0 ; Greater than load (01001)
ldip R0,R0 ; Positive load (01001)
ldige R0,R0 ; Greater than or equal load (01010)
ldinn R0,R0 ; Nonnegative load (01010)
ldinv R0,R0 ; No overflow load (01000)
ldiv R0,R0 ; Overflow load (01101)
ldinuf R0,R0 ; No underflow load (01110)
ldiuf R0,R0 ; Underflow load (01111)
ldinlv R0,R0 ; No latched overflow load (10000)
ldilv R0,R0 ; Latched overflow load (10001)
ldinluf R0,R0 ; No latched FP underflow load (10010)
ldiluf R0,R0 ; Latched FP underflow load (10011)
ldizuf R0,R0 ; Zero or FP underflow load (10100)
;;
;; Type * - Indirect (full)
;;
Type_ind:
ldi *AR0,R0 ; Indirect addressing (G=10)
ldi *+AR0(5),R0 ; with predisplacement add
ldi *-AR0(5),R0 ; with predisplacement subtract
ldi *++AR0(5),R0 ; with predisplacement add and modify
ldi *--AR0(5),R0 ; with predisplacement subtract and modify
ldi *AR0++(5),R0 ; with postdisplacement add and modify
ldi *AR0--(5),R0 ; with postdisplacement subtract and modify
ldi *AR0++(5)%,R0 ; with postdisplacement add and circular modify
ldi *AR0--(5)%,R0 ; with postdisplacement subtract and circular modify
ldi *+AR0(IR0),R0 ; with predisplacement add
ldi *-AR0(IR0),R0 ; with predisplacement subtract
ldi *++AR0(IR0),R0 ; with predisplacement add and modify
ldi *--AR0(IR0),R0 ; with predisplacement subtract and modify
ldi *AR0++(IR0),R0 ; with postdisplacement add and modify
ldi *AR0--(IR0),R0 ; with postdisplacement subtract and modify
ldi *AR0++(IR0)%,R0 ; with postdisplacement add and circular modify
ldi *AR0--(IR0)%,R0 ; with postdisplacement subtract and circular modify
ldi *AR0++(IR0)B,R0 ; with postincrement add and bit-reversed modify
ldi *AR0++,R0 ; Same as *AR0++(1)
;;
;; Type # - Direct for ldp
;;
Type_ldp:
ldp 12
ldp @start
ldp start
;;
;; Type @ - Direct
;;
Type_dir:
ldi @start,R0
ldi start,R0
ldi @16,R0
ldi @65535,R0
;;
;; Type A - Address register
;;
Type_A: dbc AR0,R0
dbc AR2,R0
dbc AR7,R0
;;
;; Type B - Unsigned integer (PC)
;;
Type_B: br start
br 0x809800
;;
;; Type C - Indirect
;;
.ifdef TEST_C4X
Type_C: addc3 *+AR0(5),R0,R0
.endif
;;
;; Type E - Register (all)
;;
Type_E: andn3 R0,R0,R0
andn3 AR0,R0,R0
addc3 DP,R0,R0
andn3 R7,R0,R0
;;
;; Type e - Register (0-11)
;;
Type_ee:subf3 R7,R0,R0
addf3 R0,R0,R0
addf3 R7,R0,R0
cmpf3 R7,R0
.ifdef TEST_C4X
addf3 R11,R0,R0
.endif
;;
;; Type F - Short float immediate
;;
Type_F: ldf 0,R0
ldf 3.5,R0
ldf -3.5,R0
ldf 0e-3.5e-1,R0
;;
;; Type G - Register (all)
;;
Type_G: andn3 R0,AR0,R0
addc3 R0,DP,R0
addc3 R0,R0,R0
andn3 R0,R7,R0
;;
;; Type g - Register (0-11)
;;
Type_gg:subf3 R0,R7,R0
addf3 R0,R0,R0
addf3 R0,R7,R0
cmpf3 R0,R7
.ifdef TEST_C4X
addf3 R0,R11,R0
.endif
;;
;; Type H - Register (0-7)
;;
Type_H: stf R0,*AR0 &|| stf R0,*AR0
stf R0,*AR0 &|| stf R2,*AR0
stf R0,*AR0 &|| stf R7,*AR0
;;
;; Type I - Indirect
;;
Type_I: addf3 *AR0,R0,R0 ; Indirect addressing (G=10)
addf3 *+AR0(1),R0,R0 ; with predisplacement add
addf3 *-AR0(1),R0,R0 ; with predisplacement subtract
addf3 *++AR0(1),R0,R0 ; with predisplacement add and modify
addf3 *--AR0(1),R0,R0 ; with predisplacement subtract and modify
addf3 *AR0++(1),R0,R0 ; with postdisplacement add and modify
addf3 *AR0--(1),R0,R0 ; with postdisplacement subtract and modify
addf3 *AR0++(1)%,R0,R0; with postdisplacement add and circular modify
addf3 *AR0--(1)%,R0,R0; with postdisplacement subtract and circular modify
addf3 *+AR0(IR0),R0,R0; with predisplacement add
addf3 *-AR0(IR0),R0,R0; with predisplacement subtract
addf3 *++AR0(IR0),R0,R0; with predisplacement add and modify
addf3 *--AR0(IR0),R0,R0; with predisplacement subtract and modify
addf3 *AR0++(IR0),R0,R0; with postdisplacement add and modify
addf3 *AR0--(IR0),R0,R0; with postdisplacement subtract and modify
addf3 *AR0++(IR0)%,R0,R0; with postdisplacement add and circular modify
addf3 *AR0--(IR0)%,R0,R0; with postdisplacement subtract and circular modify
addf3 *AR0++(IR0)B,R0,R0; with postincrement add and bit-reversed modify
addf3 *AR0++,R0,R0 ; Same as *AR0++(1)
;;
;; Type J - Indirect
;;
Type_J: addf3 R0,*AR0,R0 ; Indirect addressing (G=10)
addf3 R0,*+AR0(1),R0 ; with predisplacement add
addf3 R0,*-AR0(1),R0 ; with predisplacement subtract
addf3 R0,*++AR0(1),R0 ; with predisplacement add and modify
addf3 R0,*--AR0(1),R0 ; with predisplacement subtract and modify
addf3 R0,*AR0++(1),R0 ; with postdisplacement add and modify
addf3 R0,*AR0--(1),R0 ; with postdisplacement subtract and modify
addf3 R0,*AR0++(1)%,R0; with postdisplacement add and circular modify
addf3 R0,*AR0--(1)%,R0; with postdisplacement subtract and circular modify
addf3 R0,*+AR0(IR0),R0; with predisplacement add
addf3 R0,*-AR0(IR0),R0; with predisplacement subtract
addf3 R0,*++AR0(IR0),R0; with predisplacement add and modify
addf3 R0,*--AR0(IR0),R0; with predisplacement subtract and modify
addf3 R0,*AR0++(IR0),R0; with postdisplacement add and modify
addf3 R0,*AR0--(IR0),R0; with postdisplacement subtract and modify
addf3 R0,*AR0++(IR0)%,R0; with postdisplacement add and circular modify
addf3 R0,*AR0--(IR0)%,R0; with postdisplacement subtract and circular modify
addf3 R0,*AR0++(IR0)B,R0; with postincrement add and bit-reversed modify
addf3 R0,*AR0++,R0 ; Same as *AR0++(1)
;;
;; Type K - Register (0-7)
;;
Type_K: ldf *AR0,R0 &|| ldf *AR0,R1
ldf *AR0,R0 &|| ldf *AR0,R2
ldf *AR0,R0 &|| ldf *AR0,R7
;;
;; Type L - Register (0-7)
;;
Type_L: stf R0,*AR0 &|| stf R0,*AR0
stf R2,*AR0 &|| stf R0,*AR0
stf R7,*AR0 &|| stf R0,*AR0
;;
;; Type M - Register (2-3)
;;
Type_M: mpyf3 *AR0,*AR0,R0 &|| addf3 R0,R0,R2
mpyf3 *AR0,*AR0,R0 &|| addf3 R0,R0,R3
;;
;; Type N - Register (0-1)
;;
Type_N: mpyf3 *AR0,*AR0,R0 &|| addf3 R0,R0,R2
mpyf3 *AR0,*AR0,R1 &|| addf3 R0,R0,R2
;;
;; Type O - Indirect
;;
.ifdef TEST_C4X
Type_O: addc3 *+AR0(5),*+AR0(5),R0
.endif
;;
;; Type P - Displacement (PC rel)
;;
Type_P: callc start
callc 1
;;
;; Type Q - Register (all)
;;
Type_Q: ldi R0,R0
ldi AR0,R0
ldi DP,R0
ldi SP,R0
;;
;; Type q - Register (0-11)
;;
Type_qq:fix R0,R0
fix R7,R0
.ifdef TEST_C4X
fix R11,R0
absf R11,R0
.endif
;;
;; Type R - Register (all)
;;
Type_R: ldi R0,R0
ldi R0,AR0
ldi R0,DP
ldi R0,SP
;;
;; Type r - Register (0-11)
;;
Type_rr:ldf R0,R0
ldf R0,R7
.ifdef TEST_C4X
ldf R0,R11
.endif
;;
;; Type S - Signed immediate
;;
Type_S: ldi 0,R0
ldi -123,R0
ldi 6543,R0
ldi -32768, R0
;;
;; Type T - Integer
;;
.ifdef TEST_C4X
Type_T: stik 0,*AR0
stik 12,*AR0
stik -5,*AR0
.endif
;;
;; Type U - Unsigned integer
;;
Type_U: and 0,R0
and 256,R0
and 65535,R0
;;
;; Type V - Vector
;;
Type_V: trapu 12
trapu 0
trapu 31
.ifdef TEST_C4X
trapu 511
.endif
;;
;; Type W - Short int
;;
.ifdef TEST_C4X
Type_W: addc3 -3,R0,R0
addc3 5,R0,R0
.endif
;;
;; Type X - Expansion register
;;
.ifdef TEST_C4X
Type_X: ldep IVTP,R0
ldep TVTP,R0
.endif
;;
;; Type Y - Address register
;;
.ifdef TEST_C4X
Type_Y: lda R0,AR0
lda R0,DP
lda R0,SP
lda R0,IR0
.endif
;;
;; Type Z - Expansion register
;;
.ifdef TEST_C4X
Type_Z: ldpe R0,IVTP
ldpe R0,TVTP
.endif
|
tactcomplabs/xbgas-binutils-gdb
| 1,549
|
gas/testsuite/gas/tic4x/registers.s
|
;; test all register names c3x
.text
;; Test the base names
.ifdef TEST_ALL
start: ldi R0,R0
ldi R0,R1
ldi R0,R2
ldi R0,R3
ldi R0,R4
ldi R0,R5
ldi R0,R6
ldi R0,R7
ldi R0,AR0
ldi R0,AR1
ldi R0,AR2
ldi R0,AR3
ldi R0,AR4
ldi R0,AR5
ldi R0,AR6
ldi R0,AR7
ldi R0,DP
ldi R0,IR0
ldi R0,IR1
ldi R0,BK
ldi R0,SP
ldi R0,ST
.endif
.ifdef TEST_C3X
ldi R0,IE
ldi R0,IF
ldi R0,IOF
.endif
.ifdef TEST_C4X
ldi R0,DIE
ldi R0,IIE
ldi R0,IIF
.endif
.ifdef TEST_ALL
ldi R0,RS
ldi R0,RE
ldi R0,RC
.endif
.ifdef TEST_C4X
ldi R0,R8
ldi R0,R9
ldi R0,R10
ldi R0,R11
ldpe R0,IVTP
ldpe R0,TVTP
.endif
;; Test the alternative names
.ifdef TEST_ALL
ldf F0,F0
ldf F0,F1
ldf F0,F2
ldf F0,F3
ldf F0,F4
ldf F0,F5
ldf F0,F6
ldf F0,F7
.endif
.ifdef TEST_C4X
ldf F0,F8
ldf F0,F9
ldf F0,F10
ldf F0,F11
.endif
.end
|
tactcomplabs/xbgas-binutils-gdb
| 178,320
|
gas/testsuite/gas/tic4x/opcodes.s
|
; File is autogenerated from allopcodes.S - do not edit
; Please use ./rebuild.sh to rebuild this file
;;;
;;; Test all opcodes and argument permuation
;;; To make our job a lot simpler, we define a couple of
;;; insn classes, that we use to generate the proper
;;; test output.
;;;
;;; To rebuild this file you must use
;;; ./rebuild.sh
;;;
;;; These definitions are used within this file:
;;; TEST_C3X Enables testing of c3x opcodes
;;; TEST_C4X Enables testing of c4x opcodes
;;; TEST_ENH Enable testing of enhanced opcodes
;;; TEST_IDLE2 Enable testing of IDLE2 command
;;; TEST_LPWR Enable testing of LOPOWER commands
;;;
.text
;;------------------------------------
;; C3X INSNS
;;------------------------------------
start: .ifdef TEST_C3X & absf_B: & absf R1, R0 & absf R0 & absf @start, R0 & absf *+AR0(5), R0 & absf 3.5, R0 & .endif
.ifdef TEST_C3X & absf_stf_P: & absf *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| absf *+AR0(1), R0 & .endif & .ifdef TEST_ENH & absf_stf_P_enh: & absf R0, R0 &|| stf R1, *+AR1(1) & absf R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| absf R0, R0 & stf R1, *+AR1(1) &|| absf R0 & .endif
.ifdef TEST_C3X & absi_A: & absi AR1, AR0 & absi AR0 & absi @start, AR0 & absi *+AR0(5), AR0 & absi -5, AR0 & .endif
.ifdef TEST_C3X & absi_sti_P: & absi *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| absi *+AR0(1), R0 & .endif & .ifdef TEST_ENH & absi_sti_P_enh: & absi R0, R0 &|| sti R1, *+AR1(1) & absi R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| absi R0, R0 & sti R1, *+AR1(1) &|| absi R0 & .endif
.ifdef TEST_C3X & addc_A: & addc AR1, AR0 & addc AR0 & addc @start, AR0 & addc *+AR0(5), AR0 & addc -5, AR0 & .endif
.ifdef TEST_C3X & addc_TC: & addc AR2, AR1, AR0 & addc AR1, AR0 & addc AR1, *+AR0(1), AR0 & addc *+AR0(1), AR1, AR0 & addc *+AR0(1), AR0 & addc *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & addc_TC_c4x: & addc -5, AR1, AR0 & addc -5, AR0 & addc AR1, -5, AR0 & addc *+AR0(5), AR1, AR0 & addc *+AR0(5), AR0 & addc AR1, *+AR0(5), AR0 & addc -5, *+AR0(5), AR0 & addc *+AR0(5), -5, AR0 & addc *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & addc3_TC: & addc3 AR2, AR1, AR0 & addc3 AR1, AR0 & addc3 AR1, *+AR0(1), AR0 & addc3 *+AR0(1), AR1, AR0 & addc3 *+AR0(1), AR0 & addc3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & addc3_TC_c4x: & addc3 -5, AR1, AR0 & addc3 -5, AR0 & addc3 AR1, -5, AR0 & addc3 *+AR0(5), AR1, AR0 & addc3 *+AR0(5), AR0 & addc3 AR1, *+AR0(5), AR0 & addc3 -5, *+AR0(5), AR0 & addc3 *+AR0(5), -5, AR0 & addc3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C3X & addf_B: & addf R1, R0 & addf R0 & addf @start, R0 & addf *+AR0(5), R0 & addf 3.5, R0 & .endif
.ifdef TEST_C3X & addf_SC: & addf R2, R1, R0 & addf R1, R0 & addf R1, *+AR0(1), R0 & addf *+AR0(1), R1, R0 & addf *+AR0(1), R0 & addf *+AR0(1), *+AR1(1), R0 & .endif & .ifdef TEST_C4X & addf_SC_c4x: & addf *+AR0(5), R1, R0 & addf *+AR0(5), R0 & addf R1, *+AR0(5), R0 & addf *+AR0(5), *+AR1(5), R0 & .endif & .ifdef TEST_C3X & addf3_SC: & addf3 R2, R1, R0 & addf3 R1, R0 & addf3 R1, *+AR0(1), R0 & addf3 *+AR0(1), R1, R0 & addf3 *+AR0(1), R0 & addf3 *+AR0(1), *+AR1(1), R0 & .endif & .ifdef TEST_C4X & addf3_SC_c4x: & addf3 *+AR0(5), R1, R0 & addf3 *+AR0(5), R0 & addf3 R1, *+AR0(5), R0 & addf3 *+AR0(5), *+AR1(5), R0 & .endif
.ifdef TEST_C3X & addf_stf_QC: & addf *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & addf *+AR0(1), R0 &|| stf R1, *+AR1(1) & addf R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| addf *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| addf *+AR0(1), R0 & stf R1, *+AR1(1) &|| addf R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addf_stf_QC_enh: & addf AR0, R1, R0 &|| stf R1, *+AR1(1) & addf R2, R1, R0 &|| stf R1, *+AR1(1) & addf R1, R0 &|| stf R1, *+AR1(1) & addf R0 &|| stf R1, *+AR1(1) & addf R0, AR0, R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| addf AR0, R1, R0 & stf R1, *+AR1(1) &|| addf R2, R1, R0 & stf R1, *+AR1(1) &|| addf R1, R0 & stf R1, *+AR1(1) &|| addf R0 & stf R1, *+AR1(1) &|| addf R0, AR0, R0 & .endif & .ifdef TEST_C3X & addf3_stf_QC: & addf3 *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & addf3 *+AR0(1), R0 &|| stf R1, *+AR1(1) & addf3 R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| addf3 *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| addf3 *+AR0(1), R0 & stf R1, *+AR1(1) &|| addf3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addf3_stf_QC_enh: & addf3 AR0, R1, R0 &|| stf R1, *+AR1(1) & addf3 R2, R1, R0 &|| stf R1, *+AR1(1) & addf3 R1, R0 &|| stf R1, *+AR1(1) & addf3 R0 &|| stf R1, *+AR1(1) & addf3 R0, AR0, R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| addf3 AR0, R1, R0 & stf R1, *+AR1(1) &|| addf3 R2, R1, R0 & stf R1, *+AR1(1) &|| addf3 R1, R0 & stf R1, *+AR1(1) &|| addf3 R0 & stf R1, *+AR1(1) &|| addf3 R0, AR0, R0 & .endif
.ifdef TEST_C3X & addi_A: & addi AR1, AR0 & addi AR0 & addi @start, AR0 & addi *+AR0(5), AR0 & addi -5, AR0 & .endif
.ifdef TEST_C3X & addi_TC: & addi AR2, AR1, AR0 & addi AR1, AR0 & addi AR1, *+AR0(1), AR0 & addi *+AR0(1), AR1, AR0 & addi *+AR0(1), AR0 & addi *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & addi_TC_c4x: & addi -5, AR1, AR0 & addi -5, AR0 & addi AR1, -5, AR0 & addi *+AR0(5), AR1, AR0 & addi *+AR0(5), AR0 & addi AR1, *+AR0(5), AR0 & addi -5, *+AR0(5), AR0 & addi *+AR0(5), -5, AR0 & addi *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & addi3_TC: & addi3 AR2, AR1, AR0 & addi3 AR1, AR0 & addi3 AR1, *+AR0(1), AR0 & addi3 *+AR0(1), AR1, AR0 & addi3 *+AR0(1), AR0 & addi3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & addi3_TC_c4x: & addi3 -5, AR1, AR0 & addi3 -5, AR0 & addi3 AR1, -5, AR0 & addi3 *+AR0(5), AR1, AR0 & addi3 *+AR0(5), AR0 & addi3 AR1, *+AR0(5), AR0 & addi3 -5, *+AR0(5), AR0 & addi3 *+AR0(5), -5, AR0 & addi3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C3X & addi_sti_QC: & addi *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & addi *+AR0(1), R0 &|| sti R1, *+AR1(1) & addi R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| addi *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| addi *+AR0(1), R0 & sti R1, *+AR1(1) &|| addi R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addi_sti_QC_enh: & addi AR0, R1, R0 &|| sti R1, *+AR1(1) & addi R2, R1, R0 &|| sti R1, *+AR1(1) & addi R1, R0 &|| sti R1, *+AR1(1) & addi R0 &|| sti R1, *+AR1(1) & addi R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| addi AR0, R1, R0 & sti R1, *+AR1(1) &|| addi R2, R1, R0 & sti R1, *+AR1(1) &|| addi R1, R0 & sti R1, *+AR1(1) &|| addi R0 & sti R1, *+AR1(1) &|| addi R0, AR0, R0 & .endif & .ifdef TEST_C3X & addi3_sti_QC: & addi3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & addi3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & addi3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| addi3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| addi3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| addi3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addi3_sti_QC_enh: & addi3 AR0, R1, R0 &|| sti R1, *+AR1(1) & addi3 R2, R1, R0 &|| sti R1, *+AR1(1) & addi3 R1, R0 &|| sti R1, *+AR1(1) & addi3 R0 &|| sti R1, *+AR1(1) & addi3 R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| addi3 AR0, R1, R0 & sti R1, *+AR1(1) &|| addi3 R2, R1, R0 & sti R1, *+AR1(1) &|| addi3 R1, R0 & sti R1, *+AR1(1) &|| addi3 R0 & sti R1, *+AR1(1) &|| addi3 R0, AR0, R0 & .endif
.ifdef TEST_C3X & and_AU: & and AR1, AR0 & and AR0 & and @start, AR0 & and *+AR0(5), AR0 & and 5, AR0 & .endif
.ifdef TEST_C3X & and_TC: & and AR2, AR1, AR0 & and AR1, AR0 & and AR1, *+AR0(1), AR0 & and *+AR0(1), AR1, AR0 & and *+AR0(1), AR0 & and *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & and_TC_c4x: & and -5, AR1, AR0 & and -5, AR0 & and AR1, -5, AR0 & and *+AR0(5), AR1, AR0 & and *+AR0(5), AR0 & and AR1, *+AR0(5), AR0 & and -5, *+AR0(5), AR0 & and *+AR0(5), -5, AR0 & and *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & and3_TC: & and3 AR2, AR1, AR0 & and3 AR1, AR0 & and3 AR1, *+AR0(1), AR0 & and3 *+AR0(1), AR1, AR0 & and3 *+AR0(1), AR0 & and3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & and3_TC_c4x: & and3 -5, AR1, AR0 & and3 -5, AR0 & and3 AR1, -5, AR0 & and3 *+AR0(5), AR1, AR0 & and3 *+AR0(5), AR0 & and3 AR1, *+AR0(5), AR0 & and3 -5, *+AR0(5), AR0 & and3 *+AR0(5), -5, AR0 & and3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C3X & and_sti_QC: & and *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & and *+AR0(1), R0 &|| sti R1, *+AR1(1) & and R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| and *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| and *+AR0(1), R0 & sti R1, *+AR1(1) &|| and R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & and_sti_QC_enh: & and AR0, R1, R0 &|| sti R1, *+AR1(1) & and R2, R1, R0 &|| sti R1, *+AR1(1) & and R1, R0 &|| sti R1, *+AR1(1) & and R0 &|| sti R1, *+AR1(1) & and R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| and AR0, R1, R0 & sti R1, *+AR1(1) &|| and R2, R1, R0 & sti R1, *+AR1(1) &|| and R1, R0 & sti R1, *+AR1(1) &|| and R0 & sti R1, *+AR1(1) &|| and R0, AR0, R0 & .endif & .ifdef TEST_C3X & and3_sti_QC: & and3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & and3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & and3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| and3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| and3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| and3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & and3_sti_QC_enh: & and3 AR0, R1, R0 &|| sti R1, *+AR1(1) & and3 R2, R1, R0 &|| sti R1, *+AR1(1) & and3 R1, R0 &|| sti R1, *+AR1(1) & and3 R0 &|| sti R1, *+AR1(1) & and3 R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| and3 AR0, R1, R0 & sti R1, *+AR1(1) &|| and3 R2, R1, R0 & sti R1, *+AR1(1) &|| and3 R1, R0 & sti R1, *+AR1(1) &|| and3 R0 & sti R1, *+AR1(1) &|| and3 R0, AR0, R0 & .endif
.ifdef TEST_C3X & andn_AU: & andn AR1, AR0 & andn AR0 & andn @start, AR0 & andn *+AR0(5), AR0 & andn 5, AR0 & .endif
.ifdef TEST_C3X & andn_T: & andn AR2, AR1, AR0 & andn AR1, AR0 & andn AR1, *+AR0(1), AR0 & andn *+AR0(1), AR1, AR0 & andn *+AR0(1), AR0 & andn *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & andn_T_sc: & andn -5, AR1, AR0 & andn -5, AR0 & andn *+AR0(5), AR1, AR0 & andn *+AR0(5), AR0 & andn -5, *+AR0(5), AR0 & andn *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & andn3_T: & andn3 AR2, AR1, AR0 & andn3 AR1, AR0 & andn3 AR1, *+AR0(1), AR0 & andn3 *+AR0(1), AR1, AR0 & andn3 *+AR0(1), AR0 & andn3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & andn3_T_sc: & andn3 -5, AR1, AR0 & andn3 -5, AR0 & andn3 *+AR0(5), AR1, AR0 & andn3 *+AR0(5), AR0 & andn3 -5, *+AR0(5), AR0 & andn3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C3X & ash_A: & ash AR1, AR0 & ash AR0 & ash @start, AR0 & ash *+AR0(5), AR0 & ash -5, AR0 & .endif
.ifdef TEST_C3X & ash_T: & ash AR2, AR1, AR0 & ash AR1, AR0 & ash AR1, *+AR0(1), AR0 & ash *+AR0(1), AR1, AR0 & ash *+AR0(1), AR0 & ash *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & ash_T_sc: & ash -5, AR1, AR0 & ash -5, AR0 & ash *+AR0(5), AR1, AR0 & ash *+AR0(5), AR0 & ash -5, *+AR0(5), AR0 & ash *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & ash3_T: & ash3 AR2, AR1, AR0 & ash3 AR1, AR0 & ash3 AR1, *+AR0(1), AR0 & ash3 *+AR0(1), AR1, AR0 & ash3 *+AR0(1), AR0 & ash3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & ash3_T_sc: & ash3 -5, AR1, AR0 & ash3 -5, AR0 & ash3 *+AR0(5), AR1, AR0 & ash3 *+AR0(5), AR0 & ash3 -5, *+AR0(5), AR0 & ash3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C3X & ash_sti_Q: & ash R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ash R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & ash_sti_Q_enh: & ash R0, R0, R0 &|| sti R1, *+AR1(1) & ash R0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ash R0, R0, R0 & sti R1, *+AR1(1) &|| ash R0, R0 & .endif & .ifdef TEST_C3X & ash3_sti_Q: & ash3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ash3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & ash3_sti_Q_enh: & ash3 R0, R0, R0 &|| sti R1, *+AR1(1) & ash3 R0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ash3 R0, R0, R0 & sti R1, *+AR1(1) &|| ash3 R0, R0 & .endif
.ifdef TEST_C3X & bC_J: & bC R0 & bC start & b_J: & b R0 & b start & .endif
.ifdef TEST_C3X & bCd_J: & bCd R0 & bCd start & bd_J: & bd R0 & bd start & .endif
.ifdef TEST_C3X
br_I: br start
brd_I: brd start
call_I: call start
call_JS: callc R0
callc start
.endif
.ifdef TEST_C3X & cmpf_B: & cmpf R1, R0 & cmpf R0 & cmpf @start, R0 & cmpf *+AR0(5), R0 & cmpf 3.5, R0 & .endif
.ifdef TEST_C3X & cmpf_S2: & cmpf R2, R1 & cmpf R1, *+AR0(1) & cmpf *+AR0(1), R1 & cmpf *+AR0(1), *+AR1(1) & .endif & .ifdef TEST_C4X & cmpf_S2_c4x: & cmpf *+AR0(5), R1 & cmpf *+AR0(5), *+AR1(5) & .endif & .ifdef TEST_C3X & cmpf3_S2: & cmpf3 R2, R1 & cmpf3 R1, *+AR0(1) & cmpf3 *+AR0(1), R1 & cmpf3 *+AR0(1), *+AR1(1) & .endif & .ifdef TEST_C4X & cmpf3_S2_c4x: & cmpf3 *+AR0(5), R1 & cmpf3 *+AR0(5), *+AR1(5) & .endif
.ifdef TEST_C3X & cmpi_A: & cmpi AR1, AR0 & cmpi AR0 & cmpi @start, AR0 & cmpi *+AR0(5), AR0 & cmpi -5, AR0 & .endif
.ifdef TEST_C3X & cmpi_T2: & cmpi AR2, AR1 & cmpi AR1, *+AR0(1) & cmpi *+AR0(1), AR1 & cmpi *+AR1(1), *+AR0(1) & .endif & .ifdef TEST_C4X & cmpi_T2_c4x: & cmpi -5, AR1 & cmpi *+AR0(5), AR1 & cmpi -5, *+AR0(5) & cmpi *+AR0(5), *+AR1(5) & .endif & .ifdef TEST_C3X & cmpi3_T2: & cmpi3 AR2, AR1 & cmpi3 AR1, *+AR0(1) & cmpi3 *+AR0(1), AR1 & cmpi3 *+AR1(1), *+AR0(1) & .endif & .ifdef TEST_C4X & cmpi3_T2_c4x: & cmpi3 -5, AR1 & cmpi3 *+AR0(5), AR1 & cmpi3 -5, *+AR0(5) & cmpi3 *+AR0(5), *+AR1(5) & .endif
.ifdef TEST_C3X & dbC_D: & dbC AR0, R0 & dbC AR0, start & db_D: & db AR0, R0 & db AR0, start & .endif
.ifdef TEST_C3X & dbCd_D: & dbCd AR0, R0 & dbCd AR0, start & dbd_D: & dbd AR0, R0 & dbd AR0, start & .endif
.ifdef TEST_C3X & fix_AF: & fix R1, R0 & fix R0 & fix @start, AR0 & fix *+AR0(5), AR0 & fix 3.5, AR0 & .endif
.ifdef TEST_C3X & fix_sti_P: & fix *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| fix *+AR0(1), R0 & .endif & .ifdef TEST_ENH & fix_sti_P_enh: & fix R0, R0 &|| sti R1, *+AR1(1) & fix R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| fix R0, R0 & sti R1, *+AR1(1) &|| fix R0 & .endif
.ifdef TEST_C3X & float_BI: & float AR1, R0 & float R0 & float @start, R0 & float *+AR0(5), R0 & float -5, R0 & .endif
.ifdef TEST_C3X & float_stf_P: & float *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| float *+AR0(1), R0 & .endif & .ifdef TEST_ENH & float_stf_P_enh: & float R0, R0 &|| stf R1, *+AR1(1) & float R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| float R0, R0 & stf R1, *+AR1(1) &|| float R0 & .endif
.ifdef TEST_C3X
iack_Z: iack @start
iack *+AR0(1)
idle_Z: idle
.endif
.ifdef TEST_IDLE2
idle2_Z: idle2
.endif
.ifdef TEST_C3X & lde_B: & lde R1, R0 & lde R0 & lde @start, R0 & lde *+AR0(5), R0 & lde 3.5, R0 & .endif
.ifdef TEST_C3X & ldf_B: & ldf R1, R0 & ldf R0 & ldf @start, R0 & ldf *+AR0(5), R0 & ldf 3.5, R0 & .endif
.ifdef TEST_C3X & ldf_LL: & ldf *+AR0(1), R0 &|| ldf *+AR1(1), R1 & ldf2 *+AR0(1), R0 &|| ldf1 *+AR1(1), R1 & ldf1 *+AR1(1), R1 &|| ldf2 *+AR0(1), R0 & .endif & .ifdef TEST_ENH & ldf_LL_enh: & ldf R0, R0 &|| ldf *+AR1(1), R1 & ldf R0 &|| ldf *+AR1(1), R1 & ldf2 R0, R0 &|| ldf1 *+AR1(1), R1 & ldf2 R0 &|| ldf1 *+AR1(1), R1 & ldf1 *+AR1(1), R1 &|| ldf2 R0, R0 & ldf1 *+AR1(1), R1 &|| ldf2 R0 & .endif
.ifdef TEST_C3X & ldf_stf_P: & ldf *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| ldf *+AR0(1), R0 & .endif & .ifdef TEST_ENH & ldf_stf_P_enh: & ldf R0, R0 &|| stf R1, *+AR1(1) & ldf R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| ldf R0, R0 & stf R1, *+AR1(1) &|| ldf R0 & .endif
.ifdef TEST_C3X & ldfC_BB: & ldfC R1, R0 & ldfC R0 & ldfC @start, R0 & ldfC *+AR0(5), R0 & ldfC 3.5, R0 & .endif
.ifdef TEST_C3X & ldfi_B6: & ldfi @start, R0 & ldfi *+AR0(5), R0 & .endif
.ifdef TEST_C3X & ldi_A: & ldi AR1, AR0 & ldi AR0 & ldi @start, AR0 & ldi *+AR0(5), AR0 & ldi -5, AR0 & .endif
.ifdef TEST_C3X & ldi_LL: & ldi *+AR0(1), R0 &|| ldi *+AR1(1), R1 & ldi2 *+AR0(1), R0 &|| ldi1 *+AR1(1), R1 & ldi1 *+AR1(1), R1 &|| ldi2 *+AR0(1), R0 & .endif & .ifdef TEST_ENH & ldi_LL_enh: & ldi R0, R0 &|| ldi *+AR1(1), R1 & ldi R0 &|| ldi *+AR1(1), R1 & ldi2 R0, R0 &|| ldi1 *+AR1(1), R1 & ldi2 R0 &|| ldi1 *+AR1(1), R1 & ldi1 *+AR1(1), R1 &|| ldi2 R0, R0 & ldi1 *+AR1(1), R1 &|| ldi2 R0 & .endif
.ifdef TEST_C3X & ldi_sti_P: & ldi *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ldi *+AR0(1), R0 & .endif & .ifdef TEST_ENH & ldi_sti_P_enh: & ldi R0, R0 &|| sti R1, *+AR1(1) & ldi R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ldi R0, R0 & sti R1, *+AR1(1) &|| ldi R0 & .endif
.ifdef TEST_C3X & ldiC_AB: & ldiC AR1, AR0 & ldiC AR0 & ldiC @start, AR0 & ldiC *+AR0(5), AR0 & ldiC -5, AR0 & .endif
.ifdef TEST_C3X & ldii_A6: & ldii @start, AR0 & ldii *+AR0(5), AR0 & .endif
.ifdef TEST_C3X
ldp_Z: ldp start
.endif
.ifdef TEST_C3X & ldm_B: & ldm R1, R0 & ldm R0 & ldm @start, R0 & ldm *+AR0(5), R0 & ldm 3.5, R0 & .endif
.ifdef TEST_LPWR
lopower_Z: lopower
.endif
.ifdef TEST_C3X & lsh_A: & lsh AR1, AR0 & lsh AR0 & lsh @start, AR0 & lsh *+AR0(5), AR0 & lsh -5, AR0 & .endif
.ifdef TEST_C3X & lsh_T: & lsh AR2, AR1, AR0 & lsh AR1, AR0 & lsh AR1, *+AR0(1), AR0 & lsh *+AR0(1), AR1, AR0 & lsh *+AR0(1), AR0 & lsh *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & lsh_T_sc: & lsh -5, AR1, AR0 & lsh -5, AR0 & lsh *+AR0(5), AR1, AR0 & lsh *+AR0(5), AR0 & lsh -5, *+AR0(5), AR0 & lsh *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & lsh3_T: & lsh3 AR2, AR1, AR0 & lsh3 AR1, AR0 & lsh3 AR1, *+AR0(1), AR0 & lsh3 *+AR0(1), AR1, AR0 & lsh3 *+AR0(1), AR0 & lsh3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & lsh3_T_sc: & lsh3 -5, AR1, AR0 & lsh3 -5, AR0 & lsh3 *+AR0(5), AR1, AR0 & lsh3 *+AR0(5), AR0 & lsh3 -5, *+AR0(5), AR0 & lsh3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C3X & lsh_sti_Q: & lsh R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| lsh R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & lsh_sti_Q_enh: & lsh R0, R0, R0 &|| sti R1, *+AR1(1) & lsh R0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| lsh R0, R0, R0 & sti R1, *+AR1(1) &|| lsh R0, R0 & .endif & .ifdef TEST_C3X & lsh3_sti_Q: & lsh3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| lsh3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & lsh3_sti_Q_enh: & lsh3 R0, R0, R0 &|| sti R1, *+AR1(1) & lsh3 R0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| lsh3 R0, R0, R0 & sti R1, *+AR1(1) &|| lsh3 R0, R0 & .endif
.ifdef TEST_LPWR
maxspeed_Z: maxspeed
.endif
.ifdef TEST_C3X & mpyf_B: & mpyf R1, R0 & mpyf R0 & mpyf @start, R0 & mpyf *+AR0(5), R0 & mpyf 3.5, R0 & .endif
.ifdef TEST_C3X & mpyf_SC: & mpyf R2, R1, R0 & mpyf R1, R0 & mpyf R1, *+AR0(1), R0 & mpyf *+AR0(1), R1, R0 & mpyf *+AR0(1), R0 & mpyf *+AR0(1), *+AR1(1), R0 & .endif & .ifdef TEST_C4X & mpyf_SC_c4x: & mpyf *+AR0(5), R1, R0 & mpyf *+AR0(5), R0 & mpyf R1, *+AR0(5), R0 & mpyf *+AR0(5), *+AR1(5), R0 & .endif & .ifdef TEST_C3X & mpyf3_SC: & mpyf3 R2, R1, R0 & mpyf3 R1, R0 & mpyf3 R1, *+AR0(1), R0 & mpyf3 *+AR0(1), R1, R0 & mpyf3 *+AR0(1), R0 & mpyf3 *+AR0(1), *+AR1(1), R0 & .endif & .ifdef TEST_C4X & mpyf3_SC_c4x: & mpyf3 *+AR0(5), R1, R0 & mpyf3 *+AR0(5), R0 & mpyf3 R1, *+AR0(5), R0 & mpyf3 *+AR0(5), *+AR1(5), R0 & .endif
.ifdef TEST_C3X & mpyf_addf_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| addf R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| addf R0, R2 & mpyf *+AR0(1), R0, R0 &|| addf R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| addf *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| addf *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| addf *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| addf *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf_addf_M_enh: & mpyf R0, R0, R0 &|| addf R2, R2, R2 & mpyf R0, R0 &|| addf R2, R2, R2 & mpyf R0 &|| addf R2, R2, R2 & mpyf R0, R0 &|| addf R2, R2 & mpyf R0 &|| addf R2, R2 & mpyf R0 &|| addf R2 & mpyf AR0, AR0, R0 &|| addf R2, R2, R2 & mpyf AR0, R0, R0 &|| addf R0, AR0, R2 & mpyf R0, AR0, R0 &|| addf R0, AR0, R2 & mpyf R2, R1, R0 &|| addf AR0, AR1, R2 & mpyf AR0, R1, R0 &|| addf AR0, R3, R2 & mpyf R0, AR0, R0 &|| addf AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyf3_addf_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| addf R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| addf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| addf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| addf *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| addf *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf3_addf_M_enh: & mpyf3 R0, R0, R0 &|| addf R2, R2, R2 & mpyf3 R0, R0 &|| addf R2, R2, R2 & mpyf3 R0 &|| addf R2, R2, R2 & mpyf3 R0, R0 &|| addf R2, R2 & mpyf3 R0 &|| addf R2, R2 & mpyf3 R0 &|| addf R2 & mpyf3 AR0, AR0, R0 &|| addf R2, R2, R2 & mpyf3 AR0, R0, R0 &|| addf R0, AR0, R2 & mpyf3 R0, AR0, R0 &|| addf R0, AR0, R2 & mpyf3 R2, R1, R0 &|| addf AR0, AR1, R2 & mpyf3 AR0, R1, R0 &|| addf AR0, R3, R2 & mpyf3 R0, AR0, R0 &|| addf AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyf_addf3_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R2 & mpyf *+AR0(1), R0, R0 &|| addf3 R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| addf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf_addf3_M_enh: & mpyf R0, R0, R0 &|| addf3 R2, R2, R2 & mpyf R0, R0 &|| addf3 R2, R2, R2 & mpyf R0 &|| addf3 R2, R2, R2 & mpyf R0, R0 &|| addf3 R2, R2 & mpyf R0 &|| addf3 R2, R2 & mpyf R0 &|| addf3 R2 & mpyf AR0, AR0, R0 &|| addf3 R2, R2, R2 & mpyf AR0, R0, R0 &|| addf3 R0, AR0, R2 & mpyf R0, AR0, R0 &|| addf3 R0, AR0, R2 & mpyf R2, R1, R0 &|| addf3 AR0, AR1, R2 & mpyf AR0, R1, R0 &|| addf3 AR0, R3, R2 & mpyf R0, AR0, R0 &|| addf3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyf3_addf3_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| addf3 R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| addf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf3_addf3_M_enh: & mpyf3 R0, R0, R0 &|| addf3 R2, R2, R2 & mpyf3 R0, R0 &|| addf3 R2, R2, R2 & mpyf3 R0 &|| addf3 R2, R2, R2 & mpyf3 R0, R0 &|| addf3 R2, R2 & mpyf3 R0 &|| addf3 R2, R2 & mpyf3 R0 &|| addf3 R2 & mpyf3 AR0, AR0, R0 &|| addf3 R2, R2, R2 & mpyf3 AR0, R0, R0 &|| addf3 R0, AR0, R2 & mpyf3 R0, AR0, R0 &|| addf3 R0, AR0, R2 & mpyf3 R2, R1, R0 &|| addf3 AR0, AR1, R2 & mpyf3 AR0, R1, R0 &|| addf3 AR0, R3, R2 & mpyf3 R0, AR0, R0 &|| addf3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & addf_mpyf_M: & addf R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & addf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & addf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & addf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & addf *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addf_mpyf_M_enh: & addf R2, R2, R2 &|| mpyf R0, R0, R0 & addf R2, R2, R2 &|| mpyf R0, R0 & addf R2, R2, R2 &|| mpyf R0 & addf R2, R2 &|| mpyf R0, R0 & addf R2, R2 &|| mpyf R0 & addf R2 &|| mpyf R0 & addf R2, R2, R2 &|| mpyf AR0, AR0, R0 & addf R0, AR0, R2 &|| mpyf AR0, R0, R0 & addf R0, AR0, R2 &|| mpyf R0, AR0, R0 & addf AR0, AR1, R2 &|| mpyf R2, R1, R0 & addf AR0, R3, R2 &|| mpyf AR0, R1, R0 & addf AR0, R0, R2 &|| mpyf R0, AR0, R0 & .endif & .ifdef TEST_C3X & addf3_mpyf_M: & addf3 R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf3 R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & addf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & addf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf3 *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addf3_mpyf_M_enh: & addf3 R2, R2, R2 &|| mpyf R0, R0, R0 & addf3 R2, R2, R2 &|| mpyf R0, R0 & addf3 R2, R2, R2 &|| mpyf R0 & addf3 R2, R2 &|| mpyf R0, R0 & addf3 R2, R2 &|| mpyf R0 & addf3 R2 &|| mpyf R0 & addf3 R2, R2, R2 &|| mpyf AR0, AR0, R0 & addf3 R0, AR0, R2 &|| mpyf AR0, R0, R0 & addf3 R0, AR0, R2 &|| mpyf R0, AR0, R0 & addf3 AR0, AR1, R2 &|| mpyf R2, R1, R0 & addf3 AR0, R3, R2 &|| mpyf AR0, R1, R0 & addf3 AR0, R0, R2 &|| mpyf R0, AR0, R0 & .endif & .ifdef TEST_C3X & addf_mpyf3_M: & addf R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & addf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & addf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & addf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & addf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addf_mpyf3_M_enh: & addf R2, R2, R2 &|| mpyf3 R0, R0, R0 & addf R2, R2, R2 &|| mpyf3 R0, R0 & addf R2, R2, R2 &|| mpyf3 R0 & addf R2, R2 &|| mpyf3 R0, R0 & addf R2, R2 &|| mpyf3 R0 & addf R2 &|| mpyf3 R0 & addf R2, R2, R2 &|| mpyf3 AR0, AR0, R0 & addf R0, AR0, R2 &|| mpyf3 AR0, R0, R0 & addf R0, AR0, R2 &|| mpyf3 R0, AR0, R0 & addf AR0, AR1, R2 &|| mpyf3 R2, R1, R0 & addf AR0, R3, R2 &|| mpyf3 AR0, R1, R0 & addf AR0, R0, R2 &|| mpyf3 R0, AR0, R0 & .endif & .ifdef TEST_C3X & addf3_mpyf3_M: & addf3 R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf3 R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & addf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & addf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf3 *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addf3_mpyf3_M_enh: & addf3 R2, R2, R2 &|| mpyf3 R0, R0, R0 & addf3 R2, R2, R2 &|| mpyf3 R0, R0 & addf3 R2, R2, R2 &|| mpyf3 R0 & addf3 R2, R2 &|| mpyf3 R0, R0 & addf3 R2, R2 &|| mpyf3 R0 & addf3 R2 &|| mpyf3 R0 & addf3 R2, R2, R2 &|| mpyf3 AR0, AR0, R0 & addf3 R0, AR0, R2 &|| mpyf3 AR0, R0, R0 & addf3 R0, AR0, R2 &|| mpyf3 R0, AR0, R0 & addf3 AR0, AR1, R2 &|| mpyf3 R2, R1, R0 & addf3 AR0, R3, R2 &|| mpyf3 AR0, R1, R0 & addf3 AR0, R0, R2 &|| mpyf3 R0, AR0, R0 & .endif
.ifdef TEST_C3X & mpyf_stf_QC: & mpyf *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & mpyf *+AR0(1), R0 &|| stf R1, *+AR1(1) & mpyf R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| mpyf *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| mpyf *+AR0(1), R0 & stf R1, *+AR1(1) &|| mpyf R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & mpyf_stf_QC_enh: & mpyf AR0, R1, R0 &|| stf R1, *+AR1(1) & mpyf R2, R1, R0 &|| stf R1, *+AR1(1) & mpyf R1, R0 &|| stf R1, *+AR1(1) & mpyf R0 &|| stf R1, *+AR1(1) & mpyf R0, AR0, R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| mpyf AR0, R1, R0 & stf R1, *+AR1(1) &|| mpyf R2, R1, R0 & stf R1, *+AR1(1) &|| mpyf R1, R0 & stf R1, *+AR1(1) &|| mpyf R0 & stf R1, *+AR1(1) &|| mpyf R0, AR0, R0 & .endif & .ifdef TEST_C3X & mpyf3_stf_QC: & mpyf3 *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & mpyf3 *+AR0(1), R0 &|| stf R1, *+AR1(1) & mpyf3 R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| mpyf3 *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| mpyf3 *+AR0(1), R0 & stf R1, *+AR1(1) &|| mpyf3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & mpyf3_stf_QC_enh: & mpyf3 AR0, R1, R0 &|| stf R1, *+AR1(1) & mpyf3 R2, R1, R0 &|| stf R1, *+AR1(1) & mpyf3 R1, R0 &|| stf R1, *+AR1(1) & mpyf3 R0 &|| stf R1, *+AR1(1) & mpyf3 R0, AR0, R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| mpyf3 AR0, R1, R0 & stf R1, *+AR1(1) &|| mpyf3 R2, R1, R0 & stf R1, *+AR1(1) &|| mpyf3 R1, R0 & stf R1, *+AR1(1) &|| mpyf3 R0 & stf R1, *+AR1(1) &|| mpyf3 R0, AR0, R0 & .endif
.ifdef TEST_C3X & mpyf_subf_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| subf R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| subf R0, R2 & mpyf *+AR0(1), R0, R0 &|| subf R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| subf *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| subf *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| subf *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| subf *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf_subf_M_enh: & mpyf R0, R0, R0 &|| subf R2, R2, R2 & mpyf R0, R0 &|| subf R2, R2, R2 & mpyf R0 &|| subf R2, R2, R2 & mpyf R0, R0 &|| subf R2, R2 & mpyf R0 &|| subf R2, R2 & mpyf R0 &|| subf R2 & mpyf AR0, AR0, R0 &|| subf R2, R2, R2 & mpyf AR0, R0, R0 &|| subf R0, AR0, R2 & mpyf R0, AR0, R0 &|| subf R0, AR0, R2 & mpyf R2, R1, R0 &|| subf AR0, AR1, R2 & mpyf AR0, R1, R0 &|| subf AR0, R3, R2 & mpyf R0, AR0, R0 &|| subf AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyf3_subf_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| subf R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| subf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| subf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| subf *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| subf *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf3_subf_M_enh: & mpyf3 R0, R0, R0 &|| subf R2, R2, R2 & mpyf3 R0, R0 &|| subf R2, R2, R2 & mpyf3 R0 &|| subf R2, R2, R2 & mpyf3 R0, R0 &|| subf R2, R2 & mpyf3 R0 &|| subf R2, R2 & mpyf3 R0 &|| subf R2 & mpyf3 AR0, AR0, R0 &|| subf R2, R2, R2 & mpyf3 AR0, R0, R0 &|| subf R0, AR0, R2 & mpyf3 R0, AR0, R0 &|| subf R0, AR0, R2 & mpyf3 R2, R1, R0 &|| subf AR0, AR1, R2 & mpyf3 AR0, R1, R0 &|| subf AR0, R3, R2 & mpyf3 R0, AR0, R0 &|| subf AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyf_subf3_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R2 & mpyf *+AR0(1), R0, R0 &|| subf3 R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| subf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf_subf3_M_enh: & mpyf R0, R0, R0 &|| subf3 R2, R2, R2 & mpyf R0, R0 &|| subf3 R2, R2, R2 & mpyf R0 &|| subf3 R2, R2, R2 & mpyf R0, R0 &|| subf3 R2, R2 & mpyf R0 &|| subf3 R2, R2 & mpyf R0 &|| subf3 R2 & mpyf AR0, AR0, R0 &|| subf3 R2, R2, R2 & mpyf AR0, R0, R0 &|| subf3 R0, AR0, R2 & mpyf R0, AR0, R0 &|| subf3 R0, AR0, R2 & mpyf R2, R1, R0 &|| subf3 AR0, AR1, R2 & mpyf AR0, R1, R0 &|| subf3 AR0, R3, R2 & mpyf R0, AR0, R0 &|| subf3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyf3_subf3_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| subf3 R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| subf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf3_subf3_M_enh: & mpyf3 R0, R0, R0 &|| subf3 R2, R2, R2 & mpyf3 R0, R0 &|| subf3 R2, R2, R2 & mpyf3 R0 &|| subf3 R2, R2, R2 & mpyf3 R0, R0 &|| subf3 R2, R2 & mpyf3 R0 &|| subf3 R2, R2 & mpyf3 R0 &|| subf3 R2 & mpyf3 AR0, AR0, R0 &|| subf3 R2, R2, R2 & mpyf3 AR0, R0, R0 &|| subf3 R0, AR0, R2 & mpyf3 R0, AR0, R0 &|| subf3 R0, AR0, R2 & mpyf3 R2, R1, R0 &|| subf3 AR0, AR1, R2 & mpyf3 AR0, R1, R0 &|| subf3 AR0, R3, R2 & mpyf3 R0, AR0, R0 &|| subf3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & subf_mpyf_M: & subf R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & subf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & subf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & subf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & subf *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subf_mpyf_M_enh: & subf R2, R2, R2 &|| mpyf R0, R0, R0 & subf R2, R2, R2 &|| mpyf R0, R0 & subf R2, R2, R2 &|| mpyf R0 & subf R2, R2 &|| mpyf R0, R0 & subf R2, R2 &|| mpyf R0 & subf R2 &|| mpyf R0 & subf R2, R2, R2 &|| mpyf AR0, AR0, R0 & subf R0, AR0, R2 &|| mpyf AR0, R0, R0 & subf R0, AR0, R2 &|| mpyf R0, AR0, R0 & subf AR0, AR1, R2 &|| mpyf R2, R1, R0 & subf AR0, R3, R2 &|| mpyf AR0, R1, R0 & subf AR0, R0, R2 &|| mpyf R0, AR0, R0 & .endif & .ifdef TEST_C3X & subf3_mpyf_M: & subf3 R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf3 R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & subf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & subf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf3 *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subf3_mpyf_M_enh: & subf3 R2, R2, R2 &|| mpyf R0, R0, R0 & subf3 R2, R2, R2 &|| mpyf R0, R0 & subf3 R2, R2, R2 &|| mpyf R0 & subf3 R2, R2 &|| mpyf R0, R0 & subf3 R2, R2 &|| mpyf R0 & subf3 R2 &|| mpyf R0 & subf3 R2, R2, R2 &|| mpyf AR0, AR0, R0 & subf3 R0, AR0, R2 &|| mpyf AR0, R0, R0 & subf3 R0, AR0, R2 &|| mpyf R0, AR0, R0 & subf3 AR0, AR1, R2 &|| mpyf R2, R1, R0 & subf3 AR0, R3, R2 &|| mpyf AR0, R1, R0 & subf3 AR0, R0, R2 &|| mpyf R0, AR0, R0 & .endif & .ifdef TEST_C3X & subf_mpyf3_M: & subf R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & subf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & subf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & subf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & subf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subf_mpyf3_M_enh: & subf R2, R2, R2 &|| mpyf3 R0, R0, R0 & subf R2, R2, R2 &|| mpyf3 R0, R0 & subf R2, R2, R2 &|| mpyf3 R0 & subf R2, R2 &|| mpyf3 R0, R0 & subf R2, R2 &|| mpyf3 R0 & subf R2 &|| mpyf3 R0 & subf R2, R2, R2 &|| mpyf3 AR0, AR0, R0 & subf R0, AR0, R2 &|| mpyf3 AR0, R0, R0 & subf R0, AR0, R2 &|| mpyf3 R0, AR0, R0 & subf AR0, AR1, R2 &|| mpyf3 R2, R1, R0 & subf AR0, R3, R2 &|| mpyf3 AR0, R1, R0 & subf AR0, R0, R2 &|| mpyf3 R0, AR0, R0 & .endif & .ifdef TEST_C3X & subf3_mpyf3_M: & subf3 R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf3 R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & subf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & subf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf3 *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subf3_mpyf3_M_enh: & subf3 R2, R2, R2 &|| mpyf3 R0, R0, R0 & subf3 R2, R2, R2 &|| mpyf3 R0, R0 & subf3 R2, R2, R2 &|| mpyf3 R0 & subf3 R2, R2 &|| mpyf3 R0, R0 & subf3 R2, R2 &|| mpyf3 R0 & subf3 R2 &|| mpyf3 R0 & subf3 R2, R2, R2 &|| mpyf3 AR0, AR0, R0 & subf3 R0, AR0, R2 &|| mpyf3 AR0, R0, R0 & subf3 R0, AR0, R2 &|| mpyf3 R0, AR0, R0 & subf3 AR0, AR1, R2 &|| mpyf3 R2, R1, R0 & subf3 AR0, R3, R2 &|| mpyf3 AR0, R1, R0 & subf3 AR0, R0, R2 &|| mpyf3 R0, AR0, R0 & .endif
.ifdef TEST_C3X & mpyi_A: & mpyi AR1, AR0 & mpyi AR0 & mpyi @start, AR0 & mpyi *+AR0(5), AR0 & mpyi -5, AR0 & .endif
.ifdef TEST_C3X & mpyi_TC: & mpyi AR2, AR1, AR0 & mpyi AR1, AR0 & mpyi AR1, *+AR0(1), AR0 & mpyi *+AR0(1), AR1, AR0 & mpyi *+AR0(1), AR0 & mpyi *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & mpyi_TC_c4x: & mpyi -5, AR1, AR0 & mpyi -5, AR0 & mpyi AR1, -5, AR0 & mpyi *+AR0(5), AR1, AR0 & mpyi *+AR0(5), AR0 & mpyi AR1, *+AR0(5), AR0 & mpyi -5, *+AR0(5), AR0 & mpyi *+AR0(5), -5, AR0 & mpyi *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & mpyi3_TC: & mpyi3 AR2, AR1, AR0 & mpyi3 AR1, AR0 & mpyi3 AR1, *+AR0(1), AR0 & mpyi3 *+AR0(1), AR1, AR0 & mpyi3 *+AR0(1), AR0 & mpyi3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & mpyi3_TC_c4x: & mpyi3 -5, AR1, AR0 & mpyi3 -5, AR0 & mpyi3 AR1, -5, AR0 & mpyi3 *+AR0(5), AR1, AR0 & mpyi3 *+AR0(5), AR0 & mpyi3 AR1, *+AR0(5), AR0 & mpyi3 -5, *+AR0(5), AR0 & mpyi3 *+AR0(5), -5, AR0 & mpyi3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C3X & mpyi_addi_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| addi R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| addi R0, R2 & mpyi *+AR0(1), R0, R0 &|| addi R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| addi *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| addi *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| addi *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| addi *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi_addi_M_enh: & mpyi R0, R0, R0 &|| addi R2, R2, R2 & mpyi R0, R0 &|| addi R2, R2, R2 & mpyi R0 &|| addi R2, R2, R2 & mpyi R0, R0 &|| addi R2, R2 & mpyi R0 &|| addi R2, R2 & mpyi R0 &|| addi R2 & mpyi AR0, AR0, R0 &|| addi R2, R2, R2 & mpyi AR0, R0, R0 &|| addi R0, AR0, R2 & mpyi R0, AR0, R0 &|| addi R0, AR0, R2 & mpyi R2, R1, R0 &|| addi AR0, AR1, R2 & mpyi AR0, R1, R0 &|| addi AR0, R3, R2 & mpyi R0, AR0, R0 &|| addi AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyi3_addi_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| addi R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| addi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| addi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| addi *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| addi *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi3_addi_M_enh: & mpyi3 R0, R0, R0 &|| addi R2, R2, R2 & mpyi3 R0, R0 &|| addi R2, R2, R2 & mpyi3 R0 &|| addi R2, R2, R2 & mpyi3 R0, R0 &|| addi R2, R2 & mpyi3 R0 &|| addi R2, R2 & mpyi3 R0 &|| addi R2 & mpyi3 AR0, AR0, R0 &|| addi R2, R2, R2 & mpyi3 AR0, R0, R0 &|| addi R0, AR0, R2 & mpyi3 R0, AR0, R0 &|| addi R0, AR0, R2 & mpyi3 R2, R1, R0 &|| addi AR0, AR1, R2 & mpyi3 AR0, R1, R0 &|| addi AR0, R3, R2 & mpyi3 R0, AR0, R0 &|| addi AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyi_addi3_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R2 & mpyi *+AR0(1), R0, R0 &|| addi3 R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| addi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi_addi3_M_enh: & mpyi R0, R0, R0 &|| addi3 R2, R2, R2 & mpyi R0, R0 &|| addi3 R2, R2, R2 & mpyi R0 &|| addi3 R2, R2, R2 & mpyi R0, R0 &|| addi3 R2, R2 & mpyi R0 &|| addi3 R2, R2 & mpyi R0 &|| addi3 R2 & mpyi AR0, AR0, R0 &|| addi3 R2, R2, R2 & mpyi AR0, R0, R0 &|| addi3 R0, AR0, R2 & mpyi R0, AR0, R0 &|| addi3 R0, AR0, R2 & mpyi R2, R1, R0 &|| addi3 AR0, AR1, R2 & mpyi AR0, R1, R0 &|| addi3 AR0, R3, R2 & mpyi R0, AR0, R0 &|| addi3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyi3_addi3_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| addi3 R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| addi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi3_addi3_M_enh: & mpyi3 R0, R0, R0 &|| addi3 R2, R2, R2 & mpyi3 R0, R0 &|| addi3 R2, R2, R2 & mpyi3 R0 &|| addi3 R2, R2, R2 & mpyi3 R0, R0 &|| addi3 R2, R2 & mpyi3 R0 &|| addi3 R2, R2 & mpyi3 R0 &|| addi3 R2 & mpyi3 AR0, AR0, R0 &|| addi3 R2, R2, R2 & mpyi3 AR0, R0, R0 &|| addi3 R0, AR0, R2 & mpyi3 R0, AR0, R0 &|| addi3 R0, AR0, R2 & mpyi3 R2, R1, R0 &|| addi3 AR0, AR1, R2 & mpyi3 AR0, R1, R0 &|| addi3 AR0, R3, R2 & mpyi3 R0, AR0, R0 &|| addi3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & addi_mpyi_M: & addi R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & addi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & addi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & addi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & addi *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addi_mpyi_M_enh: & addi R2, R2, R2 &|| mpyi R0, R0, R0 & addi R2, R2, R2 &|| mpyi R0, R0 & addi R2, R2, R2 &|| mpyi R0 & addi R2, R2 &|| mpyi R0, R0 & addi R2, R2 &|| mpyi R0 & addi R2 &|| mpyi R0 & addi R2, R2, R2 &|| mpyi AR0, AR0, R0 & addi R0, AR0, R2 &|| mpyi AR0, R0, R0 & addi R0, AR0, R2 &|| mpyi R0, AR0, R0 & addi AR0, AR1, R2 &|| mpyi R2, R1, R0 & addi AR0, R3, R2 &|| mpyi AR0, R1, R0 & addi AR0, R0, R2 &|| mpyi R0, AR0, R0 & .endif & .ifdef TEST_C3X & addi3_mpyi_M: & addi3 R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi3 R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & addi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & addi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi3 *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addi3_mpyi_M_enh: & addi3 R2, R2, R2 &|| mpyi R0, R0, R0 & addi3 R2, R2, R2 &|| mpyi R0, R0 & addi3 R2, R2, R2 &|| mpyi R0 & addi3 R2, R2 &|| mpyi R0, R0 & addi3 R2, R2 &|| mpyi R0 & addi3 R2 &|| mpyi R0 & addi3 R2, R2, R2 &|| mpyi AR0, AR0, R0 & addi3 R0, AR0, R2 &|| mpyi AR0, R0, R0 & addi3 R0, AR0, R2 &|| mpyi R0, AR0, R0 & addi3 AR0, AR1, R2 &|| mpyi R2, R1, R0 & addi3 AR0, R3, R2 &|| mpyi AR0, R1, R0 & addi3 AR0, R0, R2 &|| mpyi R0, AR0, R0 & .endif & .ifdef TEST_C3X & addi_mpyi3_M: & addi R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & addi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & addi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & addi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & addi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addi_mpyi3_M_enh: & addi R2, R2, R2 &|| mpyi3 R0, R0, R0 & addi R2, R2, R2 &|| mpyi3 R0, R0 & addi R2, R2, R2 &|| mpyi3 R0 & addi R2, R2 &|| mpyi3 R0, R0 & addi R2, R2 &|| mpyi3 R0 & addi R2 &|| mpyi3 R0 & addi R2, R2, R2 &|| mpyi3 AR0, AR0, R0 & addi R0, AR0, R2 &|| mpyi3 AR0, R0, R0 & addi R0, AR0, R2 &|| mpyi3 R0, AR0, R0 & addi AR0, AR1, R2 &|| mpyi3 R2, R1, R0 & addi AR0, R3, R2 &|| mpyi3 AR0, R1, R0 & addi AR0, R0, R2 &|| mpyi3 R0, AR0, R0 & .endif & .ifdef TEST_C3X & addi3_mpyi3_M: & addi3 R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi3 R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & addi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & addi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi3 *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addi3_mpyi3_M_enh: & addi3 R2, R2, R2 &|| mpyi3 R0, R0, R0 & addi3 R2, R2, R2 &|| mpyi3 R0, R0 & addi3 R2, R2, R2 &|| mpyi3 R0 & addi3 R2, R2 &|| mpyi3 R0, R0 & addi3 R2, R2 &|| mpyi3 R0 & addi3 R2 &|| mpyi3 R0 & addi3 R2, R2, R2 &|| mpyi3 AR0, AR0, R0 & addi3 R0, AR0, R2 &|| mpyi3 AR0, R0, R0 & addi3 R0, AR0, R2 &|| mpyi3 R0, AR0, R0 & addi3 AR0, AR1, R2 &|| mpyi3 R2, R1, R0 & addi3 AR0, R3, R2 &|| mpyi3 AR0, R1, R0 & addi3 AR0, R0, R2 &|| mpyi3 R0, AR0, R0 & .endif
.ifdef TEST_C3X & mpyi_sti_QC: & mpyi *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & mpyi *+AR0(1), R0 &|| sti R1, *+AR1(1) & mpyi R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| mpyi *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| mpyi *+AR0(1), R0 & sti R1, *+AR1(1) &|| mpyi R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & mpyi_sti_QC_enh: & mpyi AR0, R1, R0 &|| sti R1, *+AR1(1) & mpyi R2, R1, R0 &|| sti R1, *+AR1(1) & mpyi R1, R0 &|| sti R1, *+AR1(1) & mpyi R0 &|| sti R1, *+AR1(1) & mpyi R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| mpyi AR0, R1, R0 & sti R1, *+AR1(1) &|| mpyi R2, R1, R0 & sti R1, *+AR1(1) &|| mpyi R1, R0 & sti R1, *+AR1(1) &|| mpyi R0 & sti R1, *+AR1(1) &|| mpyi R0, AR0, R0 & .endif & .ifdef TEST_C3X & mpyi3_sti_QC: & mpyi3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & mpyi3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & mpyi3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| mpyi3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| mpyi3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| mpyi3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & mpyi3_sti_QC_enh: & mpyi3 AR0, R1, R0 &|| sti R1, *+AR1(1) & mpyi3 R2, R1, R0 &|| sti R1, *+AR1(1) & mpyi3 R1, R0 &|| sti R1, *+AR1(1) & mpyi3 R0 &|| sti R1, *+AR1(1) & mpyi3 R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| mpyi3 AR0, R1, R0 & sti R1, *+AR1(1) &|| mpyi3 R2, R1, R0 & sti R1, *+AR1(1) &|| mpyi3 R1, R0 & sti R1, *+AR1(1) &|| mpyi3 R0 & sti R1, *+AR1(1) &|| mpyi3 R0, AR0, R0 & .endif
.ifdef TEST_C3X & mpyi_subi_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| subi R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| subi R0, R2 & mpyi *+AR0(1), R0, R0 &|| subi R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| subi *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| subi *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| subi *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| subi *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi_subi_M_enh: & mpyi R0, R0, R0 &|| subi R2, R2, R2 & mpyi R0, R0 &|| subi R2, R2, R2 & mpyi R0 &|| subi R2, R2, R2 & mpyi R0, R0 &|| subi R2, R2 & mpyi R0 &|| subi R2, R2 & mpyi R0 &|| subi R2 & mpyi AR0, AR0, R0 &|| subi R2, R2, R2 & mpyi AR0, R0, R0 &|| subi R0, AR0, R2 & mpyi R0, AR0, R0 &|| subi R0, AR0, R2 & mpyi R2, R1, R0 &|| subi AR0, AR1, R2 & mpyi AR0, R1, R0 &|| subi AR0, R3, R2 & mpyi R0, AR0, R0 &|| subi AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyi3_subi_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| subi R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| subi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| subi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| subi *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| subi *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi3_subi_M_enh: & mpyi3 R0, R0, R0 &|| subi R2, R2, R2 & mpyi3 R0, R0 &|| subi R2, R2, R2 & mpyi3 R0 &|| subi R2, R2, R2 & mpyi3 R0, R0 &|| subi R2, R2 & mpyi3 R0 &|| subi R2, R2 & mpyi3 R0 &|| subi R2 & mpyi3 AR0, AR0, R0 &|| subi R2, R2, R2 & mpyi3 AR0, R0, R0 &|| subi R0, AR0, R2 & mpyi3 R0, AR0, R0 &|| subi R0, AR0, R2 & mpyi3 R2, R1, R0 &|| subi AR0, AR1, R2 & mpyi3 AR0, R1, R0 &|| subi AR0, R3, R2 & mpyi3 R0, AR0, R0 &|| subi AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyi_subi3_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R2 & mpyi *+AR0(1), R0, R0 &|| subi3 R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| subi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi_subi3_M_enh: & mpyi R0, R0, R0 &|| subi3 R2, R2, R2 & mpyi R0, R0 &|| subi3 R2, R2, R2 & mpyi R0 &|| subi3 R2, R2, R2 & mpyi R0, R0 &|| subi3 R2, R2 & mpyi R0 &|| subi3 R2, R2 & mpyi R0 &|| subi3 R2 & mpyi AR0, AR0, R0 &|| subi3 R2, R2, R2 & mpyi AR0, R0, R0 &|| subi3 R0, AR0, R2 & mpyi R0, AR0, R0 &|| subi3 R0, AR0, R2 & mpyi R2, R1, R0 &|| subi3 AR0, AR1, R2 & mpyi AR0, R1, R0 &|| subi3 AR0, R3, R2 & mpyi R0, AR0, R0 &|| subi3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyi3_subi3_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| subi3 R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| subi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi3_subi3_M_enh: & mpyi3 R0, R0, R0 &|| subi3 R2, R2, R2 & mpyi3 R0, R0 &|| subi3 R2, R2, R2 & mpyi3 R0 &|| subi3 R2, R2, R2 & mpyi3 R0, R0 &|| subi3 R2, R2 & mpyi3 R0 &|| subi3 R2, R2 & mpyi3 R0 &|| subi3 R2 & mpyi3 AR0, AR0, R0 &|| subi3 R2, R2, R2 & mpyi3 AR0, R0, R0 &|| subi3 R0, AR0, R2 & mpyi3 R0, AR0, R0 &|| subi3 R0, AR0, R2 & mpyi3 R2, R1, R0 &|| subi3 AR0, AR1, R2 & mpyi3 AR0, R1, R0 &|| subi3 AR0, R3, R2 & mpyi3 R0, AR0, R0 &|| subi3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & subi_mpyi_M: & subi R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & subi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & subi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & subi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & subi *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subi_mpyi_M_enh: & subi R2, R2, R2 &|| mpyi R0, R0, R0 & subi R2, R2, R2 &|| mpyi R0, R0 & subi R2, R2, R2 &|| mpyi R0 & subi R2, R2 &|| mpyi R0, R0 & subi R2, R2 &|| mpyi R0 & subi R2 &|| mpyi R0 & subi R2, R2, R2 &|| mpyi AR0, AR0, R0 & subi R0, AR0, R2 &|| mpyi AR0, R0, R0 & subi R0, AR0, R2 &|| mpyi R0, AR0, R0 & subi AR0, AR1, R2 &|| mpyi R2, R1, R0 & subi AR0, R3, R2 &|| mpyi AR0, R1, R0 & subi AR0, R0, R2 &|| mpyi R0, AR0, R0 & .endif & .ifdef TEST_C3X & subi3_mpyi_M: & subi3 R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi3 R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & subi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & subi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi3 *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subi3_mpyi_M_enh: & subi3 R2, R2, R2 &|| mpyi R0, R0, R0 & subi3 R2, R2, R2 &|| mpyi R0, R0 & subi3 R2, R2, R2 &|| mpyi R0 & subi3 R2, R2 &|| mpyi R0, R0 & subi3 R2, R2 &|| mpyi R0 & subi3 R2 &|| mpyi R0 & subi3 R2, R2, R2 &|| mpyi AR0, AR0, R0 & subi3 R0, AR0, R2 &|| mpyi AR0, R0, R0 & subi3 R0, AR0, R2 &|| mpyi R0, AR0, R0 & subi3 AR0, AR1, R2 &|| mpyi R2, R1, R0 & subi3 AR0, R3, R2 &|| mpyi AR0, R1, R0 & subi3 AR0, R0, R2 &|| mpyi R0, AR0, R0 & .endif & .ifdef TEST_C3X & subi_mpyi3_M: & subi R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & subi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & subi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & subi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & subi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subi_mpyi3_M_enh: & subi R2, R2, R2 &|| mpyi3 R0, R0, R0 & subi R2, R2, R2 &|| mpyi3 R0, R0 & subi R2, R2, R2 &|| mpyi3 R0 & subi R2, R2 &|| mpyi3 R0, R0 & subi R2, R2 &|| mpyi3 R0 & subi R2 &|| mpyi3 R0 & subi R2, R2, R2 &|| mpyi3 AR0, AR0, R0 & subi R0, AR0, R2 &|| mpyi3 AR0, R0, R0 & subi R0, AR0, R2 &|| mpyi3 R0, AR0, R0 & subi AR0, AR1, R2 &|| mpyi3 R2, R1, R0 & subi AR0, R3, R2 &|| mpyi3 AR0, R1, R0 & subi AR0, R0, R2 &|| mpyi3 R0, AR0, R0 & .endif & .ifdef TEST_C3X & subi3_mpyi3_M: & subi3 R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi3 R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & subi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & subi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi3 *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subi3_mpyi3_M_enh: & subi3 R2, R2, R2 &|| mpyi3 R0, R0, R0 & subi3 R2, R2, R2 &|| mpyi3 R0, R0 & subi3 R2, R2, R2 &|| mpyi3 R0 & subi3 R2, R2 &|| mpyi3 R0, R0 & subi3 R2, R2 &|| mpyi3 R0 & subi3 R2 &|| mpyi3 R0 & subi3 R2, R2, R2 &|| mpyi3 AR0, AR0, R0 & subi3 R0, AR0, R2 &|| mpyi3 AR0, R0, R0 & subi3 R0, AR0, R2 &|| mpyi3 R0, AR0, R0 & subi3 AR0, AR1, R2 &|| mpyi3 R2, R1, R0 & subi3 AR0, R3, R2 &|| mpyi3 AR0, R1, R0 & subi3 AR0, R0, R2 &|| mpyi3 R0, AR0, R0 & .endif
.ifdef TEST_C3X & negb_A: & negb AR1, AR0 & negb AR0 & negb @start, AR0 & negb *+AR0(5), AR0 & negb -5, AR0 & .endif
.ifdef TEST_C3X & negf_B: & negf R1, R0 & negf R0 & negf @start, R0 & negf *+AR0(5), R0 & negf 3.5, R0 & .endif
.ifdef TEST_C3X & negf_stf_P: & negf *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| negf *+AR0(1), R0 & .endif & .ifdef TEST_ENH & negf_stf_P_enh: & negf R0, R0 &|| stf R1, *+AR1(1) & negf R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| negf R0, R0 & stf R1, *+AR1(1) &|| negf R0 & .endif
.ifdef TEST_C3X & negi_A: & negi AR1, AR0 & negi AR0 & negi @start, AR0 & negi *+AR0(5), AR0 & negi -5, AR0 & .endif
.ifdef TEST_C3X & negi_sti_P: & negi *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| negi *+AR0(1), R0 & .endif & .ifdef TEST_ENH & negi_sti_P_enh: & negi R0, R0 &|| sti R1, *+AR1(1) & negi R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| negi R0, R0 & sti R1, *+AR1(1) &|| negi R0 & .endif
.ifdef TEST_C3X & nop_A2: & nop AR0 & nop *+AR0(5) & nop & .endif
.ifdef TEST_C3X & norm_B: & norm R1, R0 & norm R0 & norm @start, R0 & norm *+AR0(5), R0 & norm 3.5, R0 & .endif
.ifdef TEST_C3X & not_AU: & not AR1, AR0 & not AR0 & not @start, AR0 & not *+AR0(5), AR0 & not 5, AR0 & .endif
.ifdef TEST_C3X & not_sti_P: & not *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| not *+AR0(1), R0 & .endif & .ifdef TEST_ENH & not_sti_P_enh: & not R0, R0 &|| sti R1, *+AR1(1) & not R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| not R0, R0 & sti R1, *+AR1(1) &|| not R0 & .endif
.ifdef TEST_C3X & or_AU: & or AR1, AR0 & or AR0 & or @start, AR0 & or *+AR0(5), AR0 & or 5, AR0 & .endif
.ifdef TEST_C3X & or_TC: & or AR2, AR1, AR0 & or AR1, AR0 & or AR1, *+AR0(1), AR0 & or *+AR0(1), AR1, AR0 & or *+AR0(1), AR0 & or *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & or_TC_c4x: & or -5, AR1, AR0 & or -5, AR0 & or AR1, -5, AR0 & or *+AR0(5), AR1, AR0 & or *+AR0(5), AR0 & or AR1, *+AR0(5), AR0 & or -5, *+AR0(5), AR0 & or *+AR0(5), -5, AR0 & or *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & or3_TC: & or3 AR2, AR1, AR0 & or3 AR1, AR0 & or3 AR1, *+AR0(1), AR0 & or3 *+AR0(1), AR1, AR0 & or3 *+AR0(1), AR0 & or3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & or3_TC_c4x: & or3 -5, AR1, AR0 & or3 -5, AR0 & or3 AR1, -5, AR0 & or3 *+AR0(5), AR1, AR0 & or3 *+AR0(5), AR0 & or3 AR1, *+AR0(5), AR0 & or3 -5, *+AR0(5), AR0 & or3 *+AR0(5), -5, AR0 & or3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C3X & or_sti_QC: & or *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & or *+AR0(1), R0 &|| sti R1, *+AR1(1) & or R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| or *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| or *+AR0(1), R0 & sti R1, *+AR1(1) &|| or R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & or_sti_QC_enh: & or AR0, R1, R0 &|| sti R1, *+AR1(1) & or R2, R1, R0 &|| sti R1, *+AR1(1) & or R1, R0 &|| sti R1, *+AR1(1) & or R0 &|| sti R1, *+AR1(1) & or R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| or AR0, R1, R0 & sti R1, *+AR1(1) &|| or R2, R1, R0 & sti R1, *+AR1(1) &|| or R1, R0 & sti R1, *+AR1(1) &|| or R0 & sti R1, *+AR1(1) &|| or R0, AR0, R0 & .endif & .ifdef TEST_C3X & or3_sti_QC: & or3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & or3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & or3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| or3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| or3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| or3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & or3_sti_QC_enh: & or3 AR0, R1, R0 &|| sti R1, *+AR1(1) & or3 R2, R1, R0 &|| sti R1, *+AR1(1) & or3 R1, R0 &|| sti R1, *+AR1(1) & or3 R0 &|| sti R1, *+AR1(1) & or3 R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| or3 AR0, R1, R0 & sti R1, *+AR1(1) &|| or3 R2, R1, R0 & sti R1, *+AR1(1) &|| or3 R1, R0 & sti R1, *+AR1(1) &|| or3 R0 & sti R1, *+AR1(1) &|| or3 R0, AR0, R0 & .endif
.ifdef TEST_C3X & pop_R: & pop AR0 & .endif
.ifdef TEST_C3X & popf_RF: & popf F0 & .endif
.ifdef TEST_C3X & push_R: & push AR0 & .endif
.ifdef TEST_C3X & pushf_RF: & pushf F0 & .endif
.ifdef TEST_C3X
reti_Z: retiC
reti
rets_Z: retsC
rets
.endif
.ifdef TEST_C3X & rnd_B: & rnd R1, R0 & rnd R0 & rnd @start, R0 & rnd *+AR0(5), R0 & rnd 3.5, R0 & .endif
.ifdef TEST_C3X & rol_R: & rol AR0 & .endif
.ifdef TEST_C3X & rolc_R: & rolc AR0 & .endif
.ifdef TEST_C3X & ror_R: & ror AR0 & .endif
.ifdef TEST_C3X & rorc_R: & rorc AR0 & .endif
.ifdef TEST_C3X
rptb_I2: rptb start
.endif
.ifdef TEST_C3X & rpts_A3: & rpts AR1 & rpts @start & rpts *+AR0(5) & rpts 5 & .endif
.ifdef TEST_C3X
sigi_Z: sigi
.endif
.ifdef TEST_C3X & stf_B7: & stf R0, @start & stf R0, *+AR0(5) & .endif
.ifdef TEST_C3X & stf_LS: & stf R0, *+AR0(1) &|| stf R1, *+AR1(1) & stf2 R0, *+AR0(1) &|| stf1 R1, *+AR1(1) & stf1 R1, *+AR1(1) &|| stf2 R0, *+AR0(1) & .endif & .ifdef TEST_ENH & stf_LS_enh: & stf R0, R0 &|| stf R1, *+AR1(1) & stf R0 &|| stf R1, *+AR1(1) & stf2 R0, R0 &|| stf1 R1, *+AR1(1) & stf2 R0 &|| stf1 R1, *+AR1(1) & stf1 R1, *+AR1(1) &|| stf2 R0, R0 & stf1 R1, *+AR1(1) &|| stf2 R0 & .endif
.ifdef TEST_C3X & stfi_B7: & stfi R0, @start & stfi R0, *+AR0(5) & .endif
.ifdef TEST_C3X & sti_A7: & sti AR0, @start & sti AR0, *+AR0(5) & .endif
.ifdef TEST_C3X & sti_LS: & sti R0, *+AR0(1) &|| sti R1, *+AR1(1) & sti2 R0, *+AR0(1) &|| sti1 R1, *+AR1(1) & sti1 R1, *+AR1(1) &|| sti2 R0, *+AR0(1) & .endif & .ifdef TEST_ENH & sti_LS_enh: & sti R0, R0 &|| sti R1, *+AR1(1) & sti R0 &|| sti R1, *+AR1(1) & sti2 R0, R0 &|| sti1 R1, *+AR1(1) & sti2 R0 &|| sti1 R1, *+AR1(1) & sti1 R1, *+AR1(1) &|| sti2 R0, R0 & sti1 R1, *+AR1(1) &|| sti2 R0 & .endif
.ifdef TEST_C3X & stii_A7: & stii AR0, @start & stii AR0, *+AR0(5) & .endif
.ifdef TEST_C3X & subb_A: & subb AR1, AR0 & subb AR0 & subb @start, AR0 & subb *+AR0(5), AR0 & subb -5, AR0 & .endif
.ifdef TEST_C3X & subb_T: & subb AR2, AR1, AR0 & subb AR1, AR0 & subb AR1, *+AR0(1), AR0 & subb *+AR0(1), AR1, AR0 & subb *+AR0(1), AR0 & subb *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & subb_T_sc: & subb -5, AR1, AR0 & subb -5, AR0 & subb *+AR0(5), AR1, AR0 & subb *+AR0(5), AR0 & subb -5, *+AR0(5), AR0 & subb *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & subb3_T: & subb3 AR2, AR1, AR0 & subb3 AR1, AR0 & subb3 AR1, *+AR0(1), AR0 & subb3 *+AR0(1), AR1, AR0 & subb3 *+AR0(1), AR0 & subb3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & subb3_T_sc: & subb3 -5, AR1, AR0 & subb3 -5, AR0 & subb3 *+AR0(5), AR1, AR0 & subb3 *+AR0(5), AR0 & subb3 -5, *+AR0(5), AR0 & subb3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C3X & subc_A: & subc AR1, AR0 & subc AR0 & subc @start, AR0 & subc *+AR0(5), AR0 & subc -5, AR0 & .endif
.ifdef TEST_C3X & subf_B: & subf R1, R0 & subf R0 & subf @start, R0 & subf *+AR0(5), R0 & subf 3.5, R0 & .endif
.ifdef TEST_C3X & subf_S: & subf R2, R1, R0 & subf R1, R0 & subf R1, *+AR0(1), R0 & subf *+AR0(1), R1, R0 & subf *+AR0(1), R0 & subf *+AR0(1), *+AR1(1), R0 & .endif & .ifdef TEST_C4X & subf_S_c4x: & subf *+AR0(5), R1, R0 & subf *+AR0(5), R0 & subf *+AR0(5), *+AR1(5), R0 & .endif & .ifdef TEST_C3X & subf3_S: & subf3 R2, R1, R0 & subf3 R1, R0 & subf3 R1, *+AR0(1), R0 & subf3 *+AR0(1), R1, R0 & subf3 *+AR0(1), R0 & subf3 *+AR0(1), *+AR1(1), R0 & .endif & .ifdef TEST_C4X & subf3_S_c4x: & subf3 *+AR0(5), R1, R0 & subf3 *+AR0(5), R0 & subf3 *+AR0(5), *+AR1(5), R0 & .endif
.ifdef TEST_C3X & subf_stf_Q: & subf R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| subf R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subf_stf_Q_enh: & subf R0, R0, R0 &|| stf R1, *+AR1(1) & subf R0, R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| subf R0, R0, R0 & stf R1, *+AR1(1) &|| subf R0, R0 & .endif & .ifdef TEST_C3X & subf3_stf_Q: & subf3 R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| subf3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subf3_stf_Q_enh: & subf3 R0, R0, R0 &|| stf R1, *+AR1(1) & subf3 R0, R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| subf3 R0, R0, R0 & stf R1, *+AR1(1) &|| subf3 R0, R0 & .endif
.ifdef TEST_C3X & subi_A: & subi AR1, AR0 & subi AR0 & subi @start, AR0 & subi *+AR0(5), AR0 & subi -5, AR0 & .endif
.ifdef TEST_C3X & subi_T: & subi AR2, AR1, AR0 & subi AR1, AR0 & subi AR1, *+AR0(1), AR0 & subi *+AR0(1), AR1, AR0 & subi *+AR0(1), AR0 & subi *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & subi_T_sc: & subi -5, AR1, AR0 & subi -5, AR0 & subi *+AR0(5), AR1, AR0 & subi *+AR0(5), AR0 & subi -5, *+AR0(5), AR0 & subi *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & subi3_T: & subi3 AR2, AR1, AR0 & subi3 AR1, AR0 & subi3 AR1, *+AR0(1), AR0 & subi3 *+AR0(1), AR1, AR0 & subi3 *+AR0(1), AR0 & subi3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & subi3_T_sc: & subi3 -5, AR1, AR0 & subi3 -5, AR0 & subi3 *+AR0(5), AR1, AR0 & subi3 *+AR0(5), AR0 & subi3 -5, *+AR0(5), AR0 & subi3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C3X & subi_sti_Q: & subi R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| subi R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subi_sti_Q_enh: & subi R0, R0, R0 &|| sti R1, *+AR1(1) & subi R0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| subi R0, R0, R0 & sti R1, *+AR1(1) &|| subi R0, R0 & .endif & .ifdef TEST_C3X & subi3_sti_Q: & subi3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| subi3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subi3_sti_Q_enh: & subi3 R0, R0, R0 &|| sti R1, *+AR1(1) & subi3 R0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| subi3 R0, R0, R0 & sti R1, *+AR1(1) &|| subi3 R0, R0 & .endif
.ifdef TEST_C3X & subrb_A: & subrb AR1, AR0 & subrb AR0 & subrb @start, AR0 & subrb *+AR0(5), AR0 & subrb -5, AR0 & .endif
.ifdef TEST_C3X & subrf_B: & subrf R1, R0 & subrf R0 & subrf @start, R0 & subrf *+AR0(5), R0 & subrf 3.5, R0 & .endif
.ifdef TEST_C3X & subri_A: & subri AR1, AR0 & subri AR0 & subri @start, AR0 & subri *+AR0(5), AR0 & subri -5, AR0 & .endif
.ifdef TEST_C3X
swi_Z: swi
trap_Z: trapC 10
trap 10
.endif
.ifdef TEST_C3X & tstb_AU: & tstb AR1, AR0 & tstb AR0 & tstb @start, AR0 & tstb *+AR0(5), AR0 & tstb 5, AR0 & .endif
.ifdef TEST_C3X & tstb_T2C: & tstb AR2, AR1 & tstb AR1, *+AR0(1) & tstb *+AR0(1), AR1 & tstb *+AR1(1), *+AR0(1) & .endif & .ifdef TEST_C4X & tstb_T2C_c4x: & tstb -5, AR1 & tstb AR1, -5 & tstb *+AR0(5), AR1 & tstb AR1, *+AR0(5) & tstb -5, *+AR0(5) & tstb *+AR0(5), -5 & tstb *+AR0(5), *+AR1(5) & .endif & .ifdef TEST_C3X & tstb3_T2C: & tstb3 AR2, AR1 & tstb3 AR1, *+AR0(1) & tstb3 *+AR0(1), AR1 & tstb3 *+AR1(1), *+AR0(1) & .endif & .ifdef TEST_C4X & tstb3_T2C_c4x: & tstb3 -5, AR1 & tstb3 AR1, -5 & tstb3 *+AR0(5), AR1 & tstb3 AR1, *+AR0(5) & tstb3 -5, *+AR0(5) & tstb3 *+AR0(5), -5 & tstb3 *+AR0(5), *+AR1(5) & .endif
.ifdef TEST_C3X & xor_AU: & xor AR1, AR0 & xor AR0 & xor @start, AR0 & xor *+AR0(5), AR0 & xor 5, AR0 & .endif
.ifdef TEST_C3X & xor_TC: & xor AR2, AR1, AR0 & xor AR1, AR0 & xor AR1, *+AR0(1), AR0 & xor *+AR0(1), AR1, AR0 & xor *+AR0(1), AR0 & xor *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & xor_TC_c4x: & xor -5, AR1, AR0 & xor -5, AR0 & xor AR1, -5, AR0 & xor *+AR0(5), AR1, AR0 & xor *+AR0(5), AR0 & xor AR1, *+AR0(5), AR0 & xor -5, *+AR0(5), AR0 & xor *+AR0(5), -5, AR0 & xor *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & xor3_TC: & xor3 AR2, AR1, AR0 & xor3 AR1, AR0 & xor3 AR1, *+AR0(1), AR0 & xor3 *+AR0(1), AR1, AR0 & xor3 *+AR0(1), AR0 & xor3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & xor3_TC_c4x: & xor3 -5, AR1, AR0 & xor3 -5, AR0 & xor3 AR1, -5, AR0 & xor3 *+AR0(5), AR1, AR0 & xor3 *+AR0(5), AR0 & xor3 AR1, *+AR0(5), AR0 & xor3 -5, *+AR0(5), AR0 & xor3 *+AR0(5), -5, AR0 & xor3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C3X & xor_sti_QC: & xor *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & xor *+AR0(1), R0 &|| sti R1, *+AR1(1) & xor R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| xor *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| xor *+AR0(1), R0 & sti R1, *+AR1(1) &|| xor R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & xor_sti_QC_enh: & xor AR0, R1, R0 &|| sti R1, *+AR1(1) & xor R2, R1, R0 &|| sti R1, *+AR1(1) & xor R1, R0 &|| sti R1, *+AR1(1) & xor R0 &|| sti R1, *+AR1(1) & xor R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| xor AR0, R1, R0 & sti R1, *+AR1(1) &|| xor R2, R1, R0 & sti R1, *+AR1(1) &|| xor R1, R0 & sti R1, *+AR1(1) &|| xor R0 & sti R1, *+AR1(1) &|| xor R0, AR0, R0 & .endif & .ifdef TEST_C3X & xor3_sti_QC: & xor3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & xor3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & xor3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| xor3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| xor3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| xor3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & xor3_sti_QC_enh: & xor3 AR0, R1, R0 &|| sti R1, *+AR1(1) & xor3 R2, R1, R0 &|| sti R1, *+AR1(1) & xor3 R1, R0 &|| sti R1, *+AR1(1) & xor3 R0 &|| sti R1, *+AR1(1) & xor3 R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| xor3 AR0, R1, R0 & sti R1, *+AR1(1) &|| xor3 R2, R1, R0 & sti R1, *+AR1(1) &|| xor3 R1, R0 & sti R1, *+AR1(1) &|| xor3 R0 & sti R1, *+AR1(1) &|| xor3 R0, AR0, R0 & .endif
;;------------------------------------
;; C4X INSNS
;;------------------------------------
.ifdef TEST_C4X
.ifdef TEST_C4X & bCaf_J: & bCaf R0 & bCaf start & baf_J: & baf R0 & baf start & .endif
.ifdef TEST_C4X & bCat_J: & bCat R0 & bCat start & bat_J: & bat R0 & bat start & .endif
.ifdef TEST_C4X & frieee_B6: & frieee @start, R0 & frieee *+AR0(5), R0 & .endif
.ifdef TEST_C4X & frieee_stf_P: & frieee *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| frieee *+AR0(1), R0 & .endif & .ifdef TEST_ENH & frieee_stf_P_enh: & frieee R0, R0 &|| stf R1, *+AR1(1) & frieee R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| frieee R0, R0 & stf R1, *+AR1(1) &|| frieee R0 & .endif
.ifdef TEST_C4X
laj_I: laj start
laj_JS: lajc R0
lajc start
lat_Z: latC 10
.endif
.ifdef TEST_C4X & lb0_A: & lb0 AR1, AR0 & lb0 AR0 & lb0 @start, AR0 & lb0 *+AR0(5), AR0 & lb0 -5, AR0 & .endif
.ifdef TEST_C4X & lb1_A: & lb1 AR1, AR0 & lb1 AR0 & lb1 @start, AR0 & lb1 *+AR0(5), AR0 & lb1 -5, AR0 & .endif
.ifdef TEST_C4X & lb2_A: & lb2 AR1, AR0 & lb2 AR0 & lb2 @start, AR0 & lb2 *+AR0(5), AR0 & lb2 -5, AR0 & .endif
.ifdef TEST_C4X & lb3_A: & lb3 AR1, AR0 & lb3 AR0 & lb3 @start, AR0 & lb3 *+AR0(5), AR0 & lb3 -5, AR0 & .endif
.ifdef TEST_C4X & lbu0_AU: & lbu0 AR1, AR0 & lbu0 AR0 & lbu0 @start, AR0 & lbu0 *+AR0(5), AR0 & lbu0 5, AR0 & .endif
.ifdef TEST_C4X & lbu1_AU: & lbu1 AR1, AR0 & lbu1 AR0 & lbu1 @start, AR0 & lbu1 *+AR0(5), AR0 & lbu1 5, AR0 & .endif
.ifdef TEST_C4X & lbu2_AU: & lbu2 AR1, AR0 & lbu2 AR0 & lbu2 @start, AR0 & lbu2 *+AR0(5), AR0 & lbu2 5, AR0 & .endif
.ifdef TEST_C4X & lbu3_AU: & lbu3 AR1, AR0 & lbu3 AR0 & lbu3 @start, AR0 & lbu3 *+AR0(5), AR0 & lbu3 5, AR0 & .endif
.ifdef TEST_C4X & lda_AY: & lda AR1, AR0 & lda @start, AR0 & lda *+AR0(5), AR0 & lda -5, AR0 & .endif
.ifdef TEST_C4X
ldep_Z: ldep IVTP, AR0
ldhi_Z: ldhi 35, R0
ldhi start, R0
ldpe_Z: ldpe AR0, IVTP
ldpk_Z: ldpk start
.endif
.ifdef TEST_C4X & lh0_A: & lh0 AR1, AR0 & lh0 AR0 & lh0 @start, AR0 & lh0 *+AR0(5), AR0 & lh0 -5, AR0 & .endif
.ifdef TEST_C4X & lh1_A: & lh1 AR1, AR0 & lh1 AR0 & lh1 @start, AR0 & lh1 *+AR0(5), AR0 & lh1 -5, AR0 & .endif
.ifdef TEST_C4X & lhu0_AU: & lhu0 AR1, AR0 & lhu0 AR0 & lhu0 @start, AR0 & lhu0 *+AR0(5), AR0 & lhu0 5, AR0 & .endif
.ifdef TEST_C4X & lhu1_AU: & lhu1 AR1, AR0 & lhu1 AR0 & lhu1 @start, AR0 & lhu1 *+AR0(5), AR0 & lhu1 5, AR0 & .endif
.ifdef TEST_C4X & lwl0_A: & lwl0 AR1, AR0 & lwl0 AR0 & lwl0 @start, AR0 & lwl0 *+AR0(5), AR0 & lwl0 -5, AR0 & .endif
.ifdef TEST_C4X & lwl1_A: & lwl1 AR1, AR0 & lwl1 AR0 & lwl1 @start, AR0 & lwl1 *+AR0(5), AR0 & lwl1 -5, AR0 & .endif
.ifdef TEST_C4X & lwl2_A: & lwl2 AR1, AR0 & lwl2 AR0 & lwl2 @start, AR0 & lwl2 *+AR0(5), AR0 & lwl2 -5, AR0 & .endif
.ifdef TEST_C4X & lwl3_A: & lwl3 AR1, AR0 & lwl3 AR0 & lwl3 @start, AR0 & lwl3 *+AR0(5), AR0 & lwl3 -5, AR0 & .endif
.ifdef TEST_C4X & lwr0_A: & lwr0 AR1, AR0 & lwr0 AR0 & lwr0 @start, AR0 & lwr0 *+AR0(5), AR0 & lwr0 -5, AR0 & .endif
.ifdef TEST_C4X & lwr1_A: & lwr1 AR1, AR0 & lwr1 AR0 & lwr1 @start, AR0 & lwr1 *+AR0(5), AR0 & lwr1 -5, AR0 & .endif
.ifdef TEST_C4X & lwr2_A: & lwr2 AR1, AR0 & lwr2 AR0 & lwr2 @start, AR0 & lwr2 *+AR0(5), AR0 & lwr2 -5, AR0 & .endif
.ifdef TEST_C4X & lwr3_A: & lwr3 AR1, AR0 & lwr3 AR0 & lwr3 @start, AR0 & lwr3 *+AR0(5), AR0 & lwr3 -5, AR0 & .endif
.ifdef TEST_C4X & mb0_A: & mb0 AR1, AR0 & mb0 AR0 & mb0 @start, AR0 & mb0 *+AR0(5), AR0 & mb0 -5, AR0 & .endif
.ifdef TEST_C4X & mb1_A: & mb1 AR1, AR0 & mb1 AR0 & mb1 @start, AR0 & mb1 *+AR0(5), AR0 & mb1 -5, AR0 & .endif
.ifdef TEST_C4X & mb2_A: & mb2 AR1, AR0 & mb2 AR0 & mb2 @start, AR0 & mb2 *+AR0(5), AR0 & mb2 -5, AR0 & .endif
.ifdef TEST_C4X & mb3_A: & mb3 AR1, AR0 & mb3 AR0 & mb3 @start, AR0 & mb3 *+AR0(5), AR0 & mb3 -5, AR0 & .endif
.ifdef TEST_C4X & mh0_A: & mh0 AR1, AR0 & mh0 AR0 & mh0 @start, AR0 & mh0 *+AR0(5), AR0 & mh0 -5, AR0 & .endif
.ifdef TEST_C4X & mh1_A: & mh1 AR1, AR0 & mh1 AR0 & mh1 @start, AR0 & mh1 *+AR0(5), AR0 & mh1 -5, AR0 & .endif
.ifdef TEST_C4X & mh2_A: & mh2 AR1, AR0 & mh2 AR0 & mh2 @start, AR0 & mh2 *+AR0(5), AR0 & mh2 -5, AR0 & .endif
.ifdef TEST_C4X & mh3_A: & mh3 AR1, AR0 & mh3 AR0 & mh3 @start, AR0 & mh3 *+AR0(5), AR0 & mh3 -5, AR0 & .endif
.ifdef TEST_C4X & mpyshi_A: & mpyshi AR1, AR0 & mpyshi AR0 & mpyshi @start, AR0 & mpyshi *+AR0(5), AR0 & mpyshi -5, AR0 & .endif
.ifdef TEST_C4X & mpyshi_TC: & mpyshi AR2, AR1, AR0 & mpyshi AR1, AR0 & mpyshi AR1, *+AR0(1), AR0 & mpyshi *+AR0(1), AR1, AR0 & mpyshi *+AR0(1), AR0 & mpyshi *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & mpyshi_TC_c4x: & mpyshi -5, AR1, AR0 & mpyshi -5, AR0 & mpyshi AR1, -5, AR0 & mpyshi *+AR0(5), AR1, AR0 & mpyshi *+AR0(5), AR0 & mpyshi AR1, *+AR0(5), AR0 & mpyshi -5, *+AR0(5), AR0 & mpyshi *+AR0(5), -5, AR0 & mpyshi *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C4X & mpyshi3_TC: & mpyshi3 AR2, AR1, AR0 & mpyshi3 AR1, AR0 & mpyshi3 AR1, *+AR0(1), AR0 & mpyshi3 *+AR0(1), AR1, AR0 & mpyshi3 *+AR0(1), AR0 & mpyshi3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & mpyshi3_TC_c4x: & mpyshi3 -5, AR1, AR0 & mpyshi3 -5, AR0 & mpyshi3 AR1, -5, AR0 & mpyshi3 *+AR0(5), AR1, AR0 & mpyshi3 *+AR0(5), AR0 & mpyshi3 AR1, *+AR0(5), AR0 & mpyshi3 -5, *+AR0(5), AR0 & mpyshi3 *+AR0(5), -5, AR0 & mpyshi3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C4X & mpyuhi_A: & mpyuhi AR1, AR0 & mpyuhi AR0 & mpyuhi @start, AR0 & mpyuhi *+AR0(5), AR0 & mpyuhi -5, AR0 & .endif
.ifdef TEST_C4X & mpyuhi_TC: & mpyuhi AR2, AR1, AR0 & mpyuhi AR1, AR0 & mpyuhi AR1, *+AR0(1), AR0 & mpyuhi *+AR0(1), AR1, AR0 & mpyuhi *+AR0(1), AR0 & mpyuhi *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & mpyuhi_TC_c4x: & mpyuhi -5, AR1, AR0 & mpyuhi -5, AR0 & mpyuhi AR1, -5, AR0 & mpyuhi *+AR0(5), AR1, AR0 & mpyuhi *+AR0(5), AR0 & mpyuhi AR1, *+AR0(5), AR0 & mpyuhi -5, *+AR0(5), AR0 & mpyuhi *+AR0(5), -5, AR0 & mpyuhi *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C4X & mpyuhi3_TC: & mpyuhi3 AR2, AR1, AR0 & mpyuhi3 AR1, AR0 & mpyuhi3 AR1, *+AR0(1), AR0 & mpyuhi3 *+AR0(1), AR1, AR0 & mpyuhi3 *+AR0(1), AR0 & mpyuhi3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & mpyuhi3_TC_c4x: & mpyuhi3 -5, AR1, AR0 & mpyuhi3 -5, AR0 & mpyuhi3 AR1, -5, AR0 & mpyuhi3 *+AR0(5), AR1, AR0 & mpyuhi3 *+AR0(5), AR0 & mpyuhi3 AR1, *+AR0(5), AR0 & mpyuhi3 -5, *+AR0(5), AR0 & mpyuhi3 *+AR0(5), -5, AR0 & mpyuhi3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C4X & rcpf_BA: & rcpf AR1, R0 & rcpf R0 & rcpf @start, R0 & rcpf *+AR0(5), R0 & rcpf 3.5, R0 & .endif
.ifdef TEST_C4X
retid_Z: retiCd
retid
rptb2_I2: rptb AR0
rptbd_I2: rptbd start
rptbd AR0
.endif
.ifdef TEST_C4X & rsqrf_B: & rsqrf R1, R0 & rsqrf R0 & rsqrf @start, R0 & rsqrf *+AR0(5), R0 & rsqrf 3.5, R0 & .endif
.ifdef TEST_C4X & sigi_A6: & sigi @start, AR0 & sigi *+AR0(5), AR0 & .endif
.ifdef TEST_C4X
sti2_A7: sti -5, @start
sti -5, *+AR0(5)
stik_Z: stik -5, @start
stik -5, *+AR0(5)
.endif
.ifdef TEST_C4X & toieee_B: & toieee R1, R0 & toieee R0 & toieee @start, R0 & toieee *+AR0(5), R0 & toieee 3.5, R0 & .endif
.ifdef TEST_C4X & toieee_stf_P: & toieee *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| toieee *+AR0(1), R0 & .endif & .ifdef TEST_ENH & toieee_stf_P_enh: & toieee R0, R0 &|| stf R1, *+AR1(1) & toieee R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| toieee R0, R0 & stf R1, *+AR1(1) &|| toieee R0 & .endif
.endif
.end
|
tactcomplabs/xbgas-binutils-gdb
| 9,316
|
gas/testsuite/gas/tic4x/allopcodes.S
|
;;;
;;; Test all opcodes and argument permuation
;;; To make our job a lot simpler, we define a couple of
;;; insn classes, that we use to generate the proper
;;; test output.
;;;
;;; To rebuild this file you must use
;;; ./rebuild.sh
;;;
;;; These definitions are used within this file:
;;; TEST_C3X Enables testing of c3x opcodes
;;; TEST_C4X Enables testing of c4x opcodes
;;; TEST_ENH Enable testing of enhanced opcodes
;;; TEST_IDLE2 Enable testing of IDLE2 command
;;; TEST_LPWR Enable testing of LOPOWER commands
;;;
#include "opclasses.h"
.text
;;------------------------------------
;; C3X INSNS
;;------------------------------------
start: B_CLASS( absf, TEST_C3X )
P_CLASS( absf, stf, TEST_C3X )
A_CLASS( absi, TEST_C3X )
P_CLASS( absi, sti, TEST_C3X )
A_CLASS( addc, TEST_C3X )
TC_CLASS( addc, TEST_C3X )
B_CLASS( addf, TEST_C3X )
SC_CLASS( addf, TEST_C3X )
QC_CLASS( addf, stf, TEST_C3X )
A_CLASS( addi, TEST_C3X )
TC_CLASS( addi, TEST_C3X )
QC_CLASS( addi, sti, TEST_C3X )
AU_CLASS( and, TEST_C3X )
TC_CLASS( and, TEST_C3X )
QC_CLASS( and, sti, TEST_C3X )
AU_CLASS( andn, TEST_C3X )
T_CLASS( andn, TEST_C3X )
A_CLASS( ash, TEST_C3X )
T_CLASS( ash, TEST_C3X )
Q_CLASS( ash, sti, TEST_C3X )
J_CLASS( bC, b, TEST_C3X )
J_CLASS( bCd, bd, TEST_C3X )
.ifdef TEST_C3X
br_I: br start
brd_I: brd start
call_I: call start
call_JS: callc R0
callc start
.endif
B_CLASS( cmpf, TEST_C3X )
S2_CLASS( cmpf, TEST_C3X )
A_CLASS( cmpi, TEST_C3X )
T2_CLASS( cmpi, TEST_C3X )
D_CLASS( dbC, db, TEST_C3X )
D_CLASS( dbCd, dbd, TEST_C3X )
AF_CLASS( fix, TEST_C3X )
P_CLASS( fix, sti, TEST_C3X )
BI_CLASS( float, TEST_C3X )
P_CLASS( float, stf, TEST_C3X )
.ifdef TEST_C3X
iack_Z: iack @start
iack *+AR0(1)
idle_Z: idle
.endif
.ifdef TEST_IDLE2
idle2_Z: idle2
.endif
B_CLASS( lde, TEST_C3X )
B_CLASS( ldf, TEST_C3X )
LL_CLASS( ldf, TEST_C3X )
P_CLASS( ldf, stf, TEST_C3X )
BB_CLASS( ldfC, TEST_C3X )
B6_CLASS( ldfi, TEST_C3X )
A_CLASS( ldi, TEST_C3X )
LL_CLASS( ldi, TEST_C3X )
P_CLASS( ldi, sti, TEST_C3X )
AB_CLASS( ldiC, TEST_C3X )
A6_CLASS( ldii, TEST_C3X )
.ifdef TEST_C3X
ldp_Z: ldp start
.endif
B_CLASS( ldm, TEST_C3X )
.ifdef TEST_LPWR
lopower_Z: lopower
.endif
A_CLASS( lsh, TEST_C3X )
T_CLASS( lsh, TEST_C3X )
Q_CLASS( lsh, sti, TEST_C3X )
.ifdef TEST_LPWR
maxspeed_Z: maxspeed
.endif
B_CLASS( mpyf, TEST_C3X )
SC_CLASS( mpyf, TEST_C3X )
M_CLASS( mpyf, addf, TEST_C3X )
QC_CLASS( mpyf, stf, TEST_C3X )
M_CLASS( mpyf, subf, TEST_C3X )
A_CLASS( mpyi, TEST_C3X )
TC_CLASS( mpyi, TEST_C3X )
M_CLASS( mpyi, addi, TEST_C3X )
QC_CLASS( mpyi, sti, TEST_C3X )
M_CLASS( mpyi, subi, TEST_C3X )
A_CLASS( negb, TEST_C3X )
B_CLASS( negf, TEST_C3X )
P_CLASS( negf, stf, TEST_C3X )
A_CLASS( negi, TEST_C3X )
P_CLASS( negi, sti, TEST_C3X )
A2_CLASS( nop, TEST_C3X )
B_CLASS( norm, TEST_C3X )
AU_CLASS( not, TEST_C3X )
P_CLASS( not, sti, TEST_C3X )
AU_CLASS( or, TEST_C3X )
TC_CLASS( or, TEST_C3X )
QC_CLASS( or, sti, TEST_C3X )
R_CLASS( pop, TEST_C3X )
RF_CLASS( popf, TEST_C3X )
R_CLASS( push, TEST_C3X )
RF_CLASS( pushf, TEST_C3X )
.ifdef TEST_C3X
reti_Z: retiC
reti
rets_Z: retsC
rets
.endif
B_CLASS( rnd, TEST_C3X )
R_CLASS( rol, TEST_C3X )
R_CLASS( rolc, TEST_C3X )
R_CLASS( ror, TEST_C3X )
R_CLASS( rorc, TEST_C3X )
.ifdef TEST_C3X
rptb_I2: rptb start
.endif
A3_CLASS( rpts, TEST_C3X )
.ifdef TEST_C3X
sigi_Z: sigi
.endif
B7_CLASS( stf, TEST_C3X )
LS_CLASS( stf, TEST_C3X )
B7_CLASS( stfi, TEST_C3X )
A7_CLASS( sti, TEST_C3X )
LS_CLASS( sti, TEST_C3X )
A7_CLASS( stii, TEST_C3X )
A_CLASS( subb, TEST_C3X )
T_CLASS( subb, TEST_C3X )
A_CLASS( subc, TEST_C3X )
B_CLASS( subf, TEST_C3X )
S_CLASS( subf, TEST_C3X )
Q_CLASS( subf, stf, TEST_C3X )
A_CLASS( subi, TEST_C3X )
T_CLASS( subi, TEST_C3X )
Q_CLASS( subi, sti, TEST_C3X )
A_CLASS( subrb, TEST_C3X )
B_CLASS( subrf, TEST_C3X )
A_CLASS( subri, TEST_C3X )
.ifdef TEST_C3X
swi_Z: swi
trap_Z: trapC 10
trap 10
.endif
AU_CLASS( tstb, TEST_C3X )
T2C_CLASS( tstb, TEST_C3X )
AU_CLASS( xor, TEST_C3X )
TC_CLASS( xor, TEST_C3X )
QC_CLASS( xor, sti, TEST_C3X )
;;------------------------------------
;; C4X INSNS
;;------------------------------------
.ifdef TEST_C4X
J_CLASS( bCaf, baf, TEST_C4X )
J_CLASS( bCat, bat, TEST_C4X )
B6_CLASS( frieee, TEST_C4X )
P_CLASS( frieee, stf, TEST_C4X )
.ifdef TEST_C4X
laj_I: laj start
laj_JS: lajc R0
lajc start
lat_Z: latC 10
.endif
A_CLASS( lb0, TEST_C4X )
A_CLASS( lb1, TEST_C4X )
A_CLASS( lb2, TEST_C4X )
A_CLASS( lb3, TEST_C4X )
AU_CLASS( lbu0, TEST_C4X )
AU_CLASS( lbu1, TEST_C4X )
AU_CLASS( lbu2, TEST_C4X )
AU_CLASS( lbu3, TEST_C4X )
AY_CLASS( lda, TEST_C4X )
.ifdef TEST_C4X
ldep_Z: ldep IVTP, AR0
ldhi_Z: ldhi 35, R0
ldhi start, R0
ldpe_Z: ldpe AR0, IVTP
ldpk_Z: ldpk start
.endif
A_CLASS( lh0, TEST_C4X )
A_CLASS( lh1, TEST_C4X )
AU_CLASS( lhu0, TEST_C4X )
AU_CLASS( lhu1, TEST_C4X )
A_CLASS( lwl0, TEST_C4X )
A_CLASS( lwl1, TEST_C4X )
A_CLASS( lwl2, TEST_C4X )
A_CLASS( lwl3, TEST_C4X )
A_CLASS( lwr0, TEST_C4X )
A_CLASS( lwr1, TEST_C4X )
A_CLASS( lwr2, TEST_C4X )
A_CLASS( lwr3, TEST_C4X )
A_CLASS( mb0, TEST_C4X )
A_CLASS( mb1, TEST_C4X )
A_CLASS( mb2, TEST_C4X )
A_CLASS( mb3, TEST_C4X )
A_CLASS( mh0, TEST_C4X )
A_CLASS( mh1, TEST_C4X )
A_CLASS( mh2, TEST_C4X )
A_CLASS( mh3, TEST_C4X )
A_CLASS( mpyshi, TEST_C4X )
TC_CLASS( mpyshi, TEST_C4X )
A_CLASS( mpyuhi, TEST_C4X )
TC_CLASS( mpyuhi, TEST_C4X )
BA_CLASS( rcpf, TEST_C4X )
.ifdef TEST_C4X
retid_Z: retiCd
retid
rptb2_I2: rptb AR0
rptbd_I2: rptbd start
rptbd AR0
.endif
B_CLASS( rsqrf, TEST_C4X )
A6_CLASS( sigi, TEST_C4X )
.ifdef TEST_C4X
sti2_A7: sti -5, @start
sti -5, *+AR0(5)
stik_Z: stik -5, @start
stik -5, *+AR0(5)
.endif
B_CLASS( toieee, TEST_C4X )
P_CLASS( toieee, stf, TEST_C4X )
.endif
.end
|
tactcomplabs/xbgas-binutils-gdb
| 23,409
|
gas/testsuite/gas/alpha/elf-reloc-8.s
|
.set noat
.set noreorder
.set nomacro
.arch ev6
.section .init.data,"aw",@progbits
.align 2
.type mount_initrd, @object
.size mount_initrd, 4
mount_initrd:
.long 0
.globl root_mountflags
.section .sdata,"aw",@progbits
.align 2
.type root_mountflags, @object
.size root_mountflags, 4
root_mountflags:
.long 32769
.section .sbss,"aw"
.type do_devfs, @object
.size do_devfs, 4
.align 2
do_devfs:
.zero 4
.section .init.text,"ax",@progbits
.align 2
.align 4
.ent load_ramdisk
load_ramdisk:
.frame $30,16,$26,0
.mask 0x4000000,-16
ldah $29,0($27) !gpdisp!1
lda $29,0($29) !gpdisp!1
$load_ramdisk..ng:
ldq $27,simple_strtol($29) !literal!2
lda $30,-16($30)
mov $31,$17
mov $31,$18
stq $26,0($30)
.prologue 1
jsr $26,($27),simple_strtol !lituse_jsr!2
ldah $29,0($26) !gpdisp!3
lda $29,0($29) !gpdisp!3
ldq $26,0($30)
and $0,3,$0
ldah $1,rd_doload($29) !gprelhigh
stl $0,rd_doload($1) !gprellow
lda $0,1($31)
lda $30,16($30)
ret $31,($26),1
.end load_ramdisk
.section .init.data
.type __setup_str_load_ramdisk, @object
.size __setup_str_load_ramdisk, 14
__setup_str_load_ramdisk:
.ascii "load_ramdisk=\0"
.section .init.setup,"aw",@progbits
.align 3
.type __setup_load_ramdisk, @object
.size __setup_load_ramdisk, 16
__setup_load_ramdisk:
.quad __setup_str_load_ramdisk
.quad load_ramdisk
.section .init.text
.align 2
.align 4
.ent readonly
readonly:
.frame $30,0,$26,0
ldah $29,0($27) !gpdisp!4
lda $29,0($29) !gpdisp!4
$readonly..ng:
.prologue 1
ldbu $1,0($16)
mov $31,$0
bne $1,$L167
ldl $1,root_mountflags($29) !gprel
lda $0,1($31)
bis $1,1,$1
stl $1,root_mountflags($29) !gprel
$L167:
ret $31,($26),1
.end readonly
.align 2
.align 4
.ent readwrite
readwrite:
.frame $30,0,$26,0
ldah $29,0($27) !gpdisp!5
lda $29,0($29) !gpdisp!5
$readwrite..ng:
.prologue 1
ldbu $1,0($16)
mov $31,$0
bne $1,$L169
ldl $1,root_mountflags($29) !gprel
lda $0,1($31)
bic $1,1,$1
stl $1,root_mountflags($29) !gprel
$L169:
ret $31,($26),1
.end readwrite
.section .init.data
.type __setup_str_readonly, @object
.size __setup_str_readonly, 3
__setup_str_readonly:
.ascii "ro\0"
.section .init.setup
.align 3
.type __setup_readonly, @object
.size __setup_readonly, 16
__setup_readonly:
.quad __setup_str_readonly
.quad readonly
.section .init.data
.type __setup_str_readwrite, @object
.size __setup_str_readwrite, 3
__setup_str_readwrite:
.ascii "rw\0"
.section .init.setup
.align 3
.type __setup_readwrite, @object
.size __setup_readwrite, 16
__setup_readwrite:
.quad __setup_str_readwrite
.quad readwrite
.section .rodata.str1.1,"aMS",@progbits,1
$LC1:
.ascii "/sys/block/%s/dev\0"
$LC2:
.ascii "/sys/block/%s/range\0"
.section .init.text
.align 2
.align 4
.ent try_name
try_name:
.frame $30,160,$26,0
.mask 0x4003e00,-160
ldah $29,0($27) !gpdisp!6
lda $29,0($29) !gpdisp!6
$try_name..ng:
lda $30,-160($30)
ldq $27,sprintf($29) !literal!25
stq $10,16($30)
stq $12,32($30)
mov $16,$10
mov $17,$12
ldah $17,$LC1($29) !gprelhigh
stq $26,0($30)
stq $9,8($30)
lda $16,48($30)
stq $11,24($30)
stq $13,40($30)
.prologue 1
mov $10,$18
lda $17,$LC1($17) !gprellow
jsr $26,($27),sprintf !lituse_jsr!25
ldah $29,0($26) !gpdisp!26
lda $29,0($29) !gpdisp!26
lda $16,48($30)
mov $31,$18
mov $31,$17
ldq $27,sys_open($29) !literal!23
jsr $26,($27),sys_open !lituse_jsr!23
ldah $29,0($26) !gpdisp!24
addl $31,$0,$9
lda $29,0($29) !gpdisp!24
blt $9,$L174
ldq $27,sys_read($29) !literal!21
lda $11,112($30)
mov $9,$16
lda $18,32($31)
mov $11,$17
jsr $26,($27),sys_read !lituse_jsr!21
ldah $29,0($26) !gpdisp!22
lda $29,0($29) !gpdisp!22
addl $31,$9,$16
addl $31,$0,$9
ldq $27,sys_close($29) !literal!19
jsr $26,($27),sys_close !lituse_jsr!19
ldah $29,0($26) !gpdisp!20
cmpeq $9,32,$2
cmple $9,0,$1
lda $29,0($29) !gpdisp!20
bis $1,$2,$1
bne $1,$L174
subl $9,1,$2
addq $11,$2,$0
ldbu $1,0($0)
cmpeq $1,10,$1
bne $1,$L189
$L174:
mov $31,$0
$L171:
ldq $26,0($30)
ldq $9,8($30)
ldq $10,16($30)
ldq $11,24($30)
ldq $12,32($30)
ldq $13,40($30)
lda $30,160($30)
ret $31,($26),1
$L189:
ldq $27,simple_strtoul($29) !literal!17
mov $11,$16
lda $17,144($30)
lda $18,16($31)
stb $31,0($0)
jsr $26,($27),simple_strtoul !lituse_jsr!17
ldah $29,0($26) !gpdisp!18
ldq $1,144($30)
lda $29,0($29) !gpdisp!18
addl $31,$0,$13
ldbu $2,0($1)
bne $2,$L174
mov $13,$0
beq $12,$L171
ldq $27,sprintf($29) !literal!15
ldah $17,$LC2($29) !gprelhigh
mov $10,$18
lda $16,48($30)
lda $17,$LC2($17) !gprellow
jsr $26,($27),sprintf !lituse_jsr!15
ldah $29,0($26) !gpdisp!16
lda $29,0($29) !gpdisp!16
lda $16,48($30)
mov $31,$18
mov $31,$17
ldq $27,sys_open($29) !literal!13
jsr $26,($27),sys_open !lituse_jsr!13
ldah $29,0($26) !gpdisp!14
addl $31,$0,$9
lda $29,0($29) !gpdisp!14
blt $9,$L174
ldq $27,sys_read($29) !literal!11
mov $9,$16
mov $11,$17
lda $18,32($31)
jsr $26,($27),sys_read !lituse_jsr!11
ldah $29,0($26) !gpdisp!12
lda $29,0($29) !gpdisp!12
addl $31,$9,$16
addl $31,$0,$9
ldq $27,sys_close($29) !literal!9
jsr $26,($27),sys_close !lituse_jsr!9
ldah $29,0($26) !gpdisp!10
cmpeq $9,32,$2
cmple $9,0,$1
lda $29,0($29) !gpdisp!10
bis $1,$2,$1
bne $1,$L174
subl $9,1,$2
addq $11,$2,$0
ldbu $1,0($0)
cmpeq $1,10,$1
beq $1,$L174
ldq $27,simple_strtoul($29) !literal!7
mov $11,$16
lda $17,144($30)
lda $18,10($31)
stb $31,0($0)
jsr $26,($27),simple_strtoul !lituse_jsr!7
ldah $29,0($26) !gpdisp!8
ldq $1,144($30)
lda $29,0($29) !gpdisp!8
addl $31,$0,$0
ldbu $2,0($1)
bne $2,$L174
cmplt $12,$0,$1
addl $13,$12,$0
bne $1,$L171
br $31,$L174
.end try_name
.section .rodata.str1.1
$LC3:
.ascii "/sys\0"
$LC4:
.ascii "sysfs\0"
$LC5:
.ascii "/dev/\0"
$LC6:
.ascii "nfs\0"
.section .init.text
.align 2
.align 4
.globl name_to_dev_t
.ent name_to_dev_t
name_to_dev_t:
.frame $30,96,$26,0
.mask 0x4001e00,-96
ldah $29,0($27) !gpdisp!27
lda $29,0($29) !gpdisp!27
$name_to_dev_t..ng:
lda $30,-96($30)
ldq $27,sys_mkdir($29) !literal!46
lda $17,448($31)
stq $12,32($30)
stq $9,8($30)
ldah $12,$LC3($29) !gprelhigh
lda $9,$LC3($12) !gprellow
stq $10,16($30)
stq $11,24($30)
mov $16,$10
stq $26,0($30)
.prologue 1
mov $31,$11
mov $9,$16
jsr $26,($27),sys_mkdir !lituse_jsr!46
ldah $29,0($26) !gpdisp!47
lda $29,0($29) !gpdisp!47
mov $9,$17
mov $31,$19
mov $31,$20
ldah $16,$LC4($29) !gprelhigh
ldq $27,sys_mount($29) !literal!44
lda $16,$LC4($16) !gprellow
mov $16,$18
jsr $26,($27),sys_mount !lituse_jsr!44
ldah $29,0($26) !gpdisp!45
lda $29,0($29) !gpdisp!45
blt $0,$L192
ldq $27,memcmp($29) !literal!42
ldah $17,$LC5($29) !gprelhigh
mov $10,$16
lda $18,5($31)
lda $17,$LC5($17) !gprellow
jsr $26,($27),memcmp !lituse_jsr!42
ldah $29,0($26) !gpdisp!43
lda $29,0($29) !gpdisp!43
bne $0,$L219
ldq $27,memcmp($29) !literal!38
lda $10,5($10)
ldah $17,$LC6($29) !gprelhigh
lda $18,4($31)
lda $11,255($31)
mov $10,$16
lda $17,$LC6($17) !gprellow
jsr $26,($27),memcmp !lituse_jsr!38
ldah $29,0($26) !gpdisp!39
lda $29,0($29) !gpdisp!39
beq $0,$L196
ldq $27,strlen($29) !literal!36
mov $10,$16
jsr $26,($27),strlen !lituse_jsr!36
ldah $29,0($26) !gpdisp!37
cmpule $0,31,$0
lda $29,0($29) !gpdisp!37
beq $0,$L195
ldq $27,strcpy($29) !literal!34
mov $10,$17
lda $16,48($30)
jsr $26,($27),strcpy !lituse_jsr!34
ldah $29,0($26) !gpdisp!35
ldbu $1,48($30)
lda $16,48($30)
lda $29,0($29) !gpdisp!35
mov $16,$2
stq $16,80($30)
beq $1,$L217
lda $3,46($31)
.align 4
$L204:
ldbu $1,0($2)
cmpeq $1,47,$1
bne $1,$L220
$L201:
lda $16,1($16)
stq $16,80($30)
mov $16,$2
ldbu $1,0($16)
bne $1,$L204
$L217:
lda $16,48($30)
mov $31,$17
bsr $26,try_name !samegp
addl $31,$0,$11
bne $11,$L196
ldq $16,80($30)
lda $2,48($30)
cmpule $16,$2,$1
mov $16,$3
bne $1,$L207
ldq $4,_ctype($29) !literal
ldbu $1,-1($16)
addq $1,$4,$1
ldbu $2,0($1)
and $2,4,$2
beq $2,$L207
.align 4
$L210:
lda $16,-1($3)
lda $2,48($30)
cmpule $16,$2,$1
stq $16,80($30)
mov $16,$3
bne $1,$L207
ldbu $1,-1($16)
addq $1,$4,$1
ldbu $2,0($1)
and $2,4,$2
bne $2,$L210
.align 4
$L207:
lda $2,48($30)
cmpeq $16,$2,$1
bne $1,$L195
ldbu $1,0($16)
sextb $1,$1
beq $1,$L195
cmpeq $1,48,$1
bne $1,$L195
ldq $27,simple_strtoul($29) !literal!32
mov $31,$17
lda $18,10($31)
jsr $26,($27),simple_strtoul !lituse_jsr!32
ldah $29,0($26) !gpdisp!33
ldq $1,80($30)
addl $31,$0,$9
lda $29,0($29) !gpdisp!33
lda $16,48($30)
mov $9,$17
stb $31,0($1)
bsr $26,try_name !samegp
addl $31,$0,$11
bne $11,$L196
ldq $4,80($30)
lda $1,50($30)
cmpult $4,$1,$1
bne $1,$L195
ldbu $1,-2($4)
ldq $3,_ctype($29) !literal
addq $1,$3,$1
ldbu $2,0($1)
and $2,4,$2
beq $2,$L195
ldbu $1,-1($4)
cmpeq $1,112,$1
bne $1,$L221
.align 4
$L195:
mov $31,$11
$L196:
ldq $27,sys_umount($29) !literal!30
lda $16,$LC3($12) !gprellow
mov $31,$17
jsr $26,($27),sys_umount !lituse_jsr!30
ldah $29,0($26) !gpdisp!31
lda $29,0($29) !gpdisp!31
$L192:
ldq $27,sys_rmdir($29) !literal!28
lda $16,$LC3($12) !gprellow
jsr $26,($27),sys_rmdir !lituse_jsr!28
ldah $29,0($26) !gpdisp!29
mov $11,$0
ldq $26,0($30)
ldq $9,8($30)
lda $29,0($29) !gpdisp!29
ldq $10,16($30)
ldq $11,24($30)
ldq $12,32($30)
lda $30,96($30)
ret $31,($26),1
$L221:
stb $31,-1($4)
mov $9,$17
lda $16,48($30)
bsr $26,try_name !samegp
addl $31,$0,$11
br $31,$L196
.align 4
$L220:
stb $3,0($2)
ldq $16,80($30)
br $31,$L201
.align 4
$L219:
ldq $27,simple_strtoul($29) !literal!40
mov $10,$16
lda $17,80($30)
lda $18,16($31)
jsr $26,($27),simple_strtoul !lituse_jsr!40
ldah $29,0($26) !gpdisp!41
ldq $1,80($30)
lda $29,0($29) !gpdisp!41
addl $31,$0,$11
ldbu $2,0($1)
beq $2,$L196
br $31,$L195
.end name_to_dev_t
.align 2
.align 4
.ent root_dev_setup
root_dev_setup:
.frame $30,16,$26,0
.mask 0x4000200,-16
ldah $29,0($27) !gpdisp!48
lda $29,0($29) !gpdisp!48
$root_dev_setup..ng:
lda $30,-16($30)
ldq $27,strncpy($29) !literal!49
mov $16,$17
lda $18,64($31)
stq $9,8($30)
stq $26,0($30)
.prologue 1
ldah $9,saved_root_name($29) !gprelhigh
lda $9,saved_root_name($9) !gprellow
mov $9,$16
jsr $26,($27),strncpy !lituse_jsr!49
ldah $29,0($26) !gpdisp!50
stb $31,63($9)
lda $0,1($31)
lda $29,0($29) !gpdisp!50
ldq $26,0($30)
ldq $9,8($30)
lda $30,16($30)
ret $31,($26),1
.end root_dev_setup
.section .init.data
.type __setup_str_root_dev_setup, @object
.size __setup_str_root_dev_setup, 6
__setup_str_root_dev_setup:
.ascii "root=\0"
.section .init.setup
.align 3
.type __setup_root_dev_setup, @object
.size __setup_root_dev_setup, 16
__setup_root_dev_setup:
.quad __setup_str_root_dev_setup
.quad root_dev_setup
.section .init.text
.align 2
.align 4
.ent root_data_setup
root_data_setup:
.frame $30,0,$26,0
ldah $29,0($27) !gpdisp!51
lda $29,0($29) !gpdisp!51
$root_data_setup..ng:
.prologue 1
ldah $1,root_mount_data($29) !gprelhigh
lda $0,1($31)
stq $16,root_mount_data($1) !gprellow
ret $31,($26),1
.end root_data_setup
.align 2
.align 4
.ent fs_names_setup
fs_names_setup:
.frame $30,0,$26,0
ldah $29,0($27) !gpdisp!52
lda $29,0($29) !gpdisp!52
$fs_names_setup..ng:
.prologue 1
ldah $1,root_fs_names($29) !gprelhigh
lda $0,1($31)
stq $16,root_fs_names($1) !gprellow
ret $31,($26),1
.end fs_names_setup
.section .init.data
.type __setup_str_root_data_setup, @object
.size __setup_str_root_data_setup, 11
__setup_str_root_data_setup:
.ascii "rootflags=\0"
.section .init.setup
.align 3
.type __setup_root_data_setup, @object
.size __setup_root_data_setup, 16
__setup_root_data_setup:
.quad __setup_str_root_data_setup
.quad root_data_setup
.section .init.data
.type __setup_str_fs_names_setup, @object
.size __setup_str_fs_names_setup, 12
__setup_str_fs_names_setup:
.ascii "rootfstype=\0"
.section .init.setup
.align 3
.type __setup_fs_names_setup, @object
.size __setup_fs_names_setup, 16
__setup_fs_names_setup:
.quad __setup_str_fs_names_setup
.quad fs_names_setup
.section .init.text
.align 2
.align 4
.ent get_fs_names
get_fs_names:
.frame $30,32,$26,0
.mask 0x4000600,-32
ldah $29,0($27) !gpdisp!53
lda $29,0($29) !gpdisp!53
$get_fs_names..ng:
ldah $1,root_fs_names($29) !gprelhigh
lda $30,-32($30)
ldq $17,root_fs_names($1) !gprellow
stq $10,16($30)
mov $16,$10
stq $26,0($30)
stq $9,8($30)
.prologue 1
beq $17,$L226
ldq $27,strcpy($29) !literal!58
jsr $26,($27),strcpy !lituse_jsr!58
ldah $29,0($26) !gpdisp!59
ldbu $1,0($10)
lda $29,0($29) !gpdisp!59
lda $10,1($10)
beq $1,$L232
.align 4
$L231:
ldbu $1,-1($10)
cmpeq $1,44,$1
bne $1,$L245
$L227:
ldbu $1,0($10)
lda $10,1($10)
bne $1,$L231
.align 4
$L232:
stb $31,0($10)
ldq $26,0($30)
ldq $9,8($30)
ldq $10,16($30)
lda $30,32($30)
ret $31,($26),1
.align 4
$L245:
stb $31,-1($10)
br $31,$L227
$L226:
ldq $27,get_filesystem_list($29) !literal!56
jsr $26,($27),get_filesystem_list !lituse_jsr!56
ldah $29,0($26) !gpdisp!57
addq $10,$0,$0
lda $9,-1($10)
lda $29,0($29) !gpdisp!57
stb $31,0($0)
beq $9,$L232
.align 4
$L241:
ldq $27,strchr($29) !literal!54
lda $9,1($9)
lda $17,10($31)
mov $9,$16
jsr $26,($27),strchr !lituse_jsr!54
ldah $29,0($26) !gpdisp!55
ldbu $1,0($9)
lda $29,0($29) !gpdisp!55
lda $9,1($9)
cmpeq $1,9,$1
bne $1,$L238
$L235:
mov $0,$9
bne $0,$L241
br $31,$L232
.align 4
$L238:
ldbu $1,0($9)
lda $9,1($9)
cmpeq $1,10,$2
stb $1,0($10)
lda $10,1($10)
beq $2,$L238
stb $31,-1($10)
br $31,$L235
.end get_fs_names
.section .rodata.str1.1
$LC7:
.ascii "/root\0"
$LC8:
.ascii "VFS: Cannot open root device \"%s\" or %s\12\0"
$LC9:
.ascii "Please append a correct \"root=\" boot option\12\0"
$LC10:
.ascii "VFS: Unable to mount root fs on %s\0"
$LC12:
.ascii " readonly\0"
$LC13:
.ascii "\0"
$LC11:
.ascii "VFS: Mounted root (%s filesystem)%s.\12\0"
.section .init.text
.align 2
.align 4
.ent mount_block_root
mount_block_root:
.frame $30,64,$26,0
.mask 0x400fe00,-64
ldah $29,0($27) !gpdisp!60
lda $29,0($29) !gpdisp!60
$mount_block_root..ng:
ldq $1,names_cachep($29) !literal
lda $30,-64($30)
ldq $27,kmem_cache_alloc($29) !literal!82
stq $12,32($30)
stq $11,24($30)
mov $16,$12
mov $17,$11
stq $26,0($30)
stq $9,8($30)
lda $17,464($31)
ldq $16,0($1)
stq $10,16($30)
stq $13,40($30)
stq $14,48($30)
stq $15,56($30)
.prologue 1
jsr $26,($27),kmem_cache_alloc !lituse_jsr!82
ldah $29,0($26) !gpdisp!83
lda $29,0($29) !gpdisp!83
mov $0,$16
mov $0,$10
bsr $26,get_fs_names !samegp
$L247:
ldbu $1,0($10)
mov $10,$9
beq $1,$L267
ldah $1,$LC7($29) !gprelhigh
ldah $13,root_mount_data($29) !gprelhigh
ldq $15,ROOT_DEV($29) !literal
lda $14,$LC7($1) !gprellow
$L262:
ldq $20,root_mount_data($13) !gprellow
ldq $27,sys_mount($29) !literal!80
mov $9,$18
mov $12,$16
mov $14,$17
mov $11,$19
jsr $26,($27),sys_mount !lituse_jsr!80
ldah $29,0($26) !gpdisp!81
addl $31,$0,$0
lda $29,0($29) !gpdisp!81
mov $9,$16
lda $1,13($0)
lda $2,22($0)
beq $1,$L255
bgt $1,$L259
beq $2,$L250
$L252:
ldl $1,0($15)
ldq $27,kdevname($29) !literal!78
bis $31,$1,$16
jsr $26,($27),kdevname !lituse_jsr!78
ldah $29,0($26) !gpdisp!79
lda $29,0($29) !gpdisp!79
mov $0,$18
ldq $27,printk($29) !literal!76
ldah $17,root_device_name($29) !gprelhigh
ldah $16,$LC8($29) !gprelhigh
lda $17,root_device_name($17) !gprellow
lda $16,$LC8($16) !gprellow
jsr $26,($27),printk !lituse_jsr!76
ldah $29,0($26) !gpdisp!77
lda $29,0($29) !gpdisp!77
ldq $27,printk($29) !literal!74
ldah $16,$LC9($29) !gprelhigh
lda $16,$LC9($16) !gprellow
jsr $26,($27),printk !lituse_jsr!74
ldah $29,0($26) !gpdisp!75
lda $29,0($29) !gpdisp!75
ldl $1,0($15)
ldq $27,kdevname($29) !literal!72
bis $31,$1,$16
jsr $26,($27),kdevname !lituse_jsr!72
ldah $29,0($26) !gpdisp!73
lda $29,0($29) !gpdisp!73
$L269:
mov $0,$17
ldah $16,$LC10($29) !gprelhigh
lda $16,$LC10($16) !gprellow
ldq $27,panic($29) !literal!67
jsr $26,($27),panic !lituse_jsr!67
.align 4
$L250:
ldq $27,strlen($29) !literal!70
jsr $26,($27),strlen !lituse_jsr!70
ldah $29,0($26) !gpdisp!71
addq $9,$0,$0
lda $29,0($29) !gpdisp!71
ldbu $1,1($0)
lda $9,1($0)
bne $1,$L262
$L267:
ldq $1,ROOT_DEV($29) !literal
ldq $27,kdevname($29) !literal!68
ldl $2,0($1)
bis $31,$2,$16
jsr $26,($27),kdevname !lituse_jsr!68
ldah $29,0($26) !gpdisp!69
lda $29,0($29) !gpdisp!69
br $31,$L269
$L259:
bne $0,$L252
$L254:
ldq $1,names_cachep($29) !literal
ldq $27,kmem_cache_free($29) !literal!65
mov $10,$17
ldq $16,0($1)
jsr $26,($27),kmem_cache_free !lituse_jsr!65
ldah $29,0($26) !gpdisp!66
lda $29,0($29) !gpdisp!66
mov $14,$16
ldq $27,sys_chdir($29) !literal!63
jsr $26,($27),sys_chdir !lituse_jsr!63
ldah $29,0($26) !gpdisp!64
ldq $4,64($8)
lda $29,0($29) !gpdisp!64
ldah $1,$LC12($29) !gprelhigh
lda $18,$LC12($1) !gprellow
ldq $2,1264($4)
ldq $3,40($2)
ldq $2,ROOT_DEV($29) !literal
ldq $1,40($3)
ldl $3,16($1)
ldq $4,56($1)
ldq $5,96($1)
stl $3,0($2)
ldq $17,0($4)
blbs $5,$L265
ldah $1,$LC13($29) !gprelhigh
lda $18,$LC13($1) !gprellow
$L265:
ldq $27,printk($29) !literal!61
ldah $16,$LC11($29) !gprelhigh
lda $16,$LC11($16) !gprellow
jsr $26,($27),printk !lituse_jsr!61
ldah $29,0($26) !gpdisp!62
ldq $26,0($30)
ldq $9,8($30)
lda $29,0($29) !gpdisp!62
ldq $10,16($30)
ldq $11,24($30)
ldq $12,32($30)
ldq $13,40($30)
ldq $14,48($30)
ldq $15,56($30)
lda $30,64($30)
ret $31,($26),1
$L255:
bis $11,1,$11
br $31,$L247
.end mount_block_root
.align 2
.align 4
.ent create_dev
create_dev:
.frame $30,96,$26,0
.mask 0x4000600,-96
ldah $29,0($27) !gpdisp!84
lda $29,0($29) !gpdisp!84
$create_dev..ng:
ldq $27,sys_unlink($29) !literal!87
lda $30,-96($30)
stq $9,8($30)
stq $10,16($30)
mov $16,$9
mov $17,$10
stq $26,0($30)
.prologue 1
jsr $26,($27),sys_unlink !lituse_jsr!87
ldah $29,0($26) !gpdisp!88
lda $29,0($29) !gpdisp!88
lda $0,-1($31)
mov $9,$16
mov $10,$18
ldl $1,do_devfs($29) !gprel
lda $17,24960($31)
beq $1,$L280
$L270:
ldq $26,0($30)
ldq $9,8($30)
ldq $10,16($30)
lda $30,96($30)
ret $31,($26),1
.align 4
$L280:
ldq $27,sys_mknod($29) !literal!85
jsr $26,($27),sys_mknod !lituse_jsr!85
ldah $29,0($26) !gpdisp!86
lda $29,0($29) !gpdisp!86
addl $31,$0,$0
br $31,$L270
.end create_dev
.align 2
.align 4
.ent rd_load_image
$rd_load_image..ng:
rd_load_image:
.frame $30,0,$26,0
.prologue 0
mov $31,$0
ret $31,($26),1
.end rd_load_image
.section .rodata.str1.1
$LC14:
.ascii "/dev/root\0"
.section .init.text
.align 2
.align 4
.ent rd_load_disk
rd_load_disk:
.frame $30,0,$26,0
ldah $29,0($27) !gpdisp!89
lda $29,0($29) !gpdisp!89
$rd_load_disk..ng:
.prologue 1
ldah $16,$LC14($29) !gprelhigh
lda $16,$LC14($16) !gprellow
br $31,rd_load_image !samegp
.end rd_load_disk
.align 2
.align 4
.ent mount_root
mount_root:
.frame $30,16,$26,0
.mask 0x4000200,-16
ldah $29,0($27) !gpdisp!90
lda $29,0($29) !gpdisp!90
$mount_root..ng:
ldq $1,ROOT_DEV($29) !literal
lda $30,-16($30)
ldah $18,root_device_name($29) !gprelhigh
stq $9,8($30)
lda $18,root_device_name($18) !gprellow
stq $26,0($30)
.prologue 1
ldah $9,$LC14($29) !gprelhigh
lda $9,$LC14($9) !gprellow
ldl $17,0($1)
mov $9,$16
bsr $26,create_dev !samegp
ldq $26,0($30)
mov $9,$16
ldl $17,root_mountflags($29) !gprel
ldq $9,8($30)
lda $30,16($30)
br $31,mount_block_root !samegp
.end mount_root
.align 2
.align 4
.ent handle_initrd
$handle_initrd..ng:
handle_initrd:
.frame $30,0,$26,0
.prologue 0
ret $31,($26),1
.end handle_initrd
.section .rodata.str1.1
$LC15:
.ascii "/dev/initrd\0"
.section .init.text
.align 2
.align 4
.ent initrd_load
initrd_load:
.frame $30,0,$26,0
ldah $29,0($27) !gpdisp!91
lda $29,0($29) !gpdisp!91
$initrd_load..ng:
.prologue 1
ldah $16,$LC15($29) !gprelhigh
lda $16,$LC15($16) !gprellow
br $31,rd_load_image !samegp
.end initrd_load
.section .rodata.str1.1
$LC16:
.ascii "/dev\0"
$LC17:
.ascii ".\0"
$LC18:
.ascii "/\0"
.text
.align 2
.align 4
.globl prepare_namespace
.ent prepare_namespace
prepare_namespace:
.frame $30,32,$26,0
.mask 0x4000e00,-32
ldah $29,0($27) !gpdisp!92
lda $29,0($29) !gpdisp!92
$prepare_namespace..ng:
lda $30,-32($30)
stq $10,16($30)
stq $9,8($30)
ldah $9,saved_root_name($29) !gprelhigh
ldq $10,ROOT_DEV($29) !literal
stq $11,24($30)
stq $26,0($30)
.prologue 1
ldbu $2,saved_root_name($9) !gprellow
ldl $1,0($10)
zapnot $1,15,$1
srl $1,8,$1
cmpeq $1,2,$11
bne $2,$L296
$L287:
ldl $17,0($10)
ldah $16,$LC14($29) !gprelhigh
mov $31,$18
lda $16,$LC14($16) !gprellow
bsr $26,create_dev !samegp
ldah $1,mount_initrd($29) !gprelhigh
ldl $2,mount_initrd($1) !gprellow
beq $2,$L290
bsr $26,initrd_load !samegp
beq $0,$L293
ldl $1,0($10)
lda $1,-256($1)
bne $1,$L297
.align 4
$L293:
bsr $26,mount_root !samegp
$L292:
ldq $27,sys_umount($29) !literal!98
ldah $16,$LC16($29) !gprelhigh
mov $31,$17
lda $16,$LC16($16) !gprellow
jsr $26,($27),sys_umount !lituse_jsr!98
ldah $29,0($26) !gpdisp!99
lda $29,0($29) !gpdisp!99
mov $31,$18
lda $19,8192($31)
mov $31,$20
ldah $9,$LC17($29) !gprelhigh
ldq $27,sys_mount($29) !literal!96
ldah $17,$LC18($29) !gprelhigh
lda $9,$LC17($9) !gprellow
lda $17,$LC18($17) !gprellow
mov $9,$16
jsr $26,($27),sys_mount !lituse_jsr!96
ldah $29,0($26) !gpdisp!97
lda $29,0($29) !gpdisp!97
mov $9,$16
ldq $27,sys_chroot($29) !literal!94
jsr $26,($27),sys_chroot !lituse_jsr!94
ldah $29,0($26) !gpdisp!95
lda $29,0($29) !gpdisp!95
ldq $1,security_ops($29) !literal
ldq $2,0($1)
ldq $27,184($2)
jsr $26,($27),0
ldah $29,0($26) !gpdisp!93
ldq $26,0($30)
ldq $9,8($30)
lda $29,0($29) !gpdisp!93
ldq $10,16($30)
ldq $11,24($30)
lda $30,32($30)
ret $31,($26),1
$L297:
bsr $26,handle_initrd !samegp
br $31,$L292
.align 4
$L290:
beq $11,$L293
ldah $1,rd_doload($29) !gprelhigh
ldl $2,rd_doload($1) !gprellow
beq $2,$L293
mov $31,$16
bsr $26,rd_load_disk !samegp
beq $0,$L293
lda $1,256($31)
stl $1,0($10)
br $31,$L293
.align 4
$L296:
lda $9,saved_root_name($9) !gprellow
mov $9,$16
bsr $26,name_to_dev_t !samegp
mov $9,$16
ldq $27,memcmp($29) !literal!102
ldah $17,$LC5($29) !gprelhigh
stl $0,0($10)
lda $18,5($31)
lda $17,$LC5($17) !gprellow
jsr $26,($27),memcmp !lituse_jsr!102
ldah $29,0($26) !gpdisp!103
lda $29,0($29) !gpdisp!103
lda $1,5($9)
cmoveq $0,$1,$9
ldq $27,strcpy($29) !literal!100
ldah $16,root_device_name($29) !gprelhigh
lda $16,root_device_name($16) !gprellow
mov $9,$17
jsr $26,($27),strcpy !lituse_jsr!100
ldah $29,0($26) !gpdisp!101
lda $29,0($29) !gpdisp!101
br $31,$L287
.end prepare_namespace
.comm ROOT_DEV,4,4
.globl rd_doload
.section .init.data
.align 2
.type rd_doload, @object
.size rd_doload, 4
rd_doload:
.zero 4
.section .bss
.type root_device_name, @object
.size root_device_name, 64
root_device_name:
.zero 64
.type saved_root_name, @object
.size saved_root_name, 64
saved_root_name:
.zero 64
.section .init.data
.align 3
.type root_mount_data, @object
.size root_mount_data, 8
root_mount_data:
.zero 8
.align 3
.type root_fs_names, @object
.size root_fs_names, 8
root_fs_names:
.zero 8
.ident "GCC: (GNU) 3.3 20021103 (experimental)"
|
tactcomplabs/xbgas-binutils-gdb
| 6,114
|
gas/testsuite/gas/iq2000/allinsn.s
|
.data
foodata: .word 42
.text
footext:
.text
.global add
add:
add %0,%0,%0
.text
.global addi
addi:
addi %0,%0,-4
.text
.global addiu
addiu:
addiu %0,%0,4
.text
.global addu
addu:
addu %0,%0,%0
.text
.global ado16
ado16:
ado16 %0,%0,%0
.text
.global and
and:
and %0,%0,%0
.text
.global andi
andi:
andi %0,%0,0xdead
.text
.global andoi
andoi:
andoi %0,%0,0
.text
.global andoui
andoui:
andoui %0,%0,0
.text
.global mrgb
mrgb:
mrgb %0,%0,%0,0
.text
.global nor
nor:
nor %0,%0,%0
.text
.global or
or:
or %0,%0,%0
.text
.global ori
ori:
ori %0,%0,-1
.text
.global orui
orui:
orui %0,%0,0
.text
.global ram
ram:
ram %0,%0,0,0,0
.text
.global sll
sll:
sll %0,%0,0
.text
.global sllv
sllv:
sllv %0,%0,%0
.text
.global slmv
slmv:
slmv %0,%0,%0,0
.text
.global slt
slt:
slt %0,%0,%0
.text
.global slti
slti:
slti %0,%0,0
.text
.global sltiu
sltiu:
sltiu %0,%0,0
.text
.global sltu
sltu:
sltu %0,%0,%0
.text
.global sra
sra:
sra %0,%0,0
.text
.global srav
srav:
srav %0,%0,%0
.text
.global srl
srl:
srl %0,%0,0
.text
.global srlv
srlv:
srlv %0,%0,%0
.text
.global srmv
srmv:
srmv %0,%0,%0,0
.text
.global sub
sub:
sub %0,%0,%0
.text
.global subu
subu:
subu %0,%0,%0
.text
.global xor
xor:
xor %0,%0,%0
.text
.global xori
xori:
xori %0,%0,0
.text
.global bbi
bbi:
bbi %0(0),footext
.text
.global bbin
bbin:
bbin %0(0),footext
.text
.global bbv
bbv:
bbv %0,%0,footext
.text
.global bbvn
bbvn:
bbvn %0,%0,footext
.text
.global beq
beq:
beq %0,%0,footext
.text
.global beql
beql:
beql %0,%0,footext
.text
.global bgez
bgez:
bgez %0,footext
.text
.global bgezal
bgezal:
bgezal %0,footext
.text
.global bgezall
bgezall:
bgezall %0,footext
.text
.global bgezl
bgezl:
bgezl %0,footext
.text
.global bgtz
bgtz:
bgtz %0,footext
.text
.global bgtzl
bgtzl:
bgtzl %0,footext
.text
.global blez
blez:
blez %0,footext
.text
.global blezl
blezl:
blezl %0,footext
.text
.global bltz
bltz:
bltz %0,footext
.text
.global bltzl
bltzl:
bltzl %0,footext
.text
.global bltzal
bltzal:
bltzal %0,footext
.text
.global bltzall
bltzall:
bltzall %0,footext
.text
.global bmb
bmb:
bmb %0,%0,footext
.text
.global bmb0
bmb0:
bmb0 %0,%0,footext
.text
.global bmb1
bmb1:
bmb1 %0,%0,footext
.text
.global bmb2
bmb2:
bmb2 %0,%0,footext
.text
.global bmb3
bmb3:
bmb3 %0,%0,footext
.text
.global bne
bne:
bne %0,%0,footext
.text
.global bnel
bnel:
bnel %0,%0,footext
.text
.global bctxt
bctxt:
bctxt %0,footext
.text
.global bc0f
bc0f:
bc0f footext
.text
.global bc0fl
bc0fl:
bc0fl footext
.text
.global bc3f
bc3f:
bc3f footext
.text
.global bc3fl
bc3fl:
bc3fl footext
.text
.global bc0t
bc0t:
bc0t footext
.text
.global bc0tl
bc0tl:
bc0tl footext
.text
.global bc3t
bc3t:
bc3t footext
.text
.global bc3tl
bc3tl:
bc3tl footext
.text
.global break
break:
break
.text
.global cfc0
cfc0:
cfc0 %0,%0
.text
.global cfc1
cfc1:
cfc1 %0,%0
.text
.global cfc2
cfc2:
cfc2 %0,%0
.text
.global cfc3
cfc3:
cfc3 %0,%0
.text
.global chkhdr
chkhdr:
chkhdr %0,%0
.text
.global ctc0
ctc0:
ctc0 %0,%0
.text
.global ctc1
ctc1:
ctc1 %0,%0
.text
.global ctc2
ctc2:
ctc2 %0,%0
.text
.global ctc3
ctc3:
ctc3 %0,%0
.text
.global jcr
jcr:
jcr %0
.text
.global luc32
nop
luc32:
# insert a nop here to pacify the assembler (luc32 may not follow jcr).
luc32 %0,%0
.text
.global luc32l
luc32l:
luc32l %0,%0
.text
.global luc64
luc64:
luc64 %0,%0
.text
.global luc64l
luc64l:
luc64l %0,%0
.text
.global luk
luk:
luk %0,%0
.text
.global lulck
lulck:
lulck %0
.text
.global lum32
lum32:
lum32 %0,%0
.text
.global lum32l
lum32l:
lum32l %0,%0
.text
.global lum64
lum64:
lum64 %0,%0
.text
.global lum64l
lum64l:
lum64l %0,%0
.text
.global lur
lur:
lur %0,%0
.text
.global lurl
lurl:
lurl %0,%0
.text
.global luulck
luulck:
luulck %0
.text
.global mfc0
mfc0:
mfc0 %0,%0
.text
.global mfc1
mfc1:
mfc1 %0,%0
.text
.global mfc2
mfc2:
mfc2 %0,%0
.text
.global mfc3
mfc3:
mfc3 %0,%0
.text
.global mtc0
mtc0:
mtc0 %0,%0
.text
.global mtc1
mtc1:
mtc1 %0,%0
.text
.global mtc2
mtc2:
mtc2 %0,%0
.text
.global mtc3
mtc3:
mtc3 %0,%0
.text
.global rb
rb:
rb %0,%0
.text
.global rbr1
rbr1:
rbr1 %0,0,0
.text
.global rbr30
rbr30:
rbr30 %0,0,0
.text
.global rfe
rfe:
rfe
.text
.global rx
rx:
rx %0,%0
.text
.global rxr1
rxr1:
rxr1 %0,0,0
.text
.global rxr30
rxr30:
rxr30 %0,0,0
.text
.global sleep
sleep:
sleep
.text
.global srrd
srrd:
srrd %0
.text
.global srrdl
srrdl:
srrdl %0
.text
.global srulck
srulck:
srulck %0
.text
.global srwr
srwr:
srwr %0,%0
.text
.global srwru
srwru:
srwru %0,%0
.text
.global syscall
syscall:
syscall
.text
.global trapqfl
trapqfl:
trapqfl
.text
.global trapqne
trapqne:
trapqne
.text
.global wb
wb:
wb %0,%0
.text
.global wbu
wbu:
wbu %0,%0
.text
.global wbr1
wbr1:
wbr1 %3,0,0
.text
.global wbr1u
wbr1u:
wbr1u %0,0,0
.text
.global wbr30
wbr30:
wbr30 %0,0,0
.text
.global wbr30u
wbr30u:
wbr30u %0,0,0
.text
.global wx
wx:
wx %0,%0
.text
.global wxu
wxu:
wxu %0,%0
.text
.global wxr1
wxr1:
wxr1 %0,0,0
.text
.global wxr1u
wxr1u:
wxr1u %0,0,0
.text
.global wxr30
wxr30:
wxr30 %0,0,0
.text
.global wxr30u
wxr30u:
wxr30u %0,0,0
.text
.global j
j:
j footext
.text
.global jal
jal:
jal footext
.text
.global jalr
jalr:
jalr %0,%0
.text
.global jr
jr:
jr %0
.text
.global lb
lb:
lb %0,0x1024(%0)
.text
.global lbu
lbu:
lbu %0,0x1024(%0)
.text
.global ldw
ldw:
ldw %0,0x1024(%0)
.text
.global lh
lh:
lh %0,0x1024(%0)
.text
.global lhu
lhu:
lhu %0,0x1024(%0)
.text
.global lui
lui:
lui %0,-1
.text
.global lw
lw:
lw %0,0x1024(%0)
.text
.global sb
sb:
sb %0,0x1024(%0)
.text
.global sdw
sdw:
sdw %0,0x1024(%0)
.text
.global sh
sh:
sh %0,0x1024(%0)
.text
.global sw
sw:
sw %0,0x1024(%0)
.text
.global traprel
traprel:
traprel %0
.text
.global pkrl
pkrl:
pkrl %0,%1
.text
.global pkrlr1
pkrlr1:
pkrlr1 %0,0,0
.text
.global pkrlr30
pkrlr30:
pkrlr30 %0,0,0
|
tactcomplabs/xbgas-binutils-gdb
| 1,540
|
gas/testsuite/gas/iq2000/yield0.s
|
# This test case includes a single case of a yield instruction
# (e.g. SLEEP) appearing in the branch delay slot. We expect
# the assembler to issue a warning about this!
.text
# yield insn in the branch delay slot.
beq %0,%0,foo
cfc2 %1, %1
# likewise for the rest.
beq %0,%0,foo
cfc3 %1, %1
beq %0,%0,foo
chkhdr %1, %1
beq %0,%0,foo
luc32 %1, %1
beq %0,%0,foo
luc32l %1, %1
beq %0,%0,foo
luc64 %1, %1
beq %0,%0,foo
luc64l %1, %1
beq %0,%0,foo
lulck %1
beq %0,%0,foo
lum32 %1, %1
beq %0,%0,foo
lum32l %1, %1
beq %0,%0,foo
lum64 %1, %1
beq %0,%0,foo
lum64l %1, %1
beq %0,%0,foo
lur %1, %1
beq %0,%0,foo
lurl %1, %1
beq %0,%0,foo
luulck %1
beq %0,%0,foo
mfc2 %1, %1
beq %0,%0,foo
mfc3 %1, %1
beq %0,%0,foo
rb %1, %1
beq %0,%0,foo
rbr1 %1, 1, 1
beq %0,%0,foo
rbr30 %1, 1, 1
beq %0,%0,foo
rx %1, %1
beq %0,%0,foo
rxr1 %1, 1, 1
beq %0,%0,foo
rxr30 %1, 1, 1
beq %0,%0,foo
sleep
beq %0,%0,foo
srrd %1
beq %0,%0,foo
srrdl %1
beq %0,%0,foo
srulck %1
beq %0,%0,foo
srwr %1, %1
beq %0,%0,foo
srwru %1, %1
beq %0,%0,foo
syscall
beq %0,%0,foo
trapqfl
beq %0,%0,foo
trapqne
beq %0,%0,foo
wb %1, %1
beq %0,%0,foo
wbu %1, %1
beq %0,%0,foo
wbr1 %1, 1, 1
beq %0,%0,foo
wbr1u %1, 1, 1
beq %0,%0,foo
wbr30 %1, 1, 1
beq %0,%0,foo
wbr30u %1, 1, 1
beq %0,%0,foo
wx %1, %1
beq %0,%0,foo
wxu %1, %1
beq %0,%0,foo
wxr1 %1, 1, 1
beq %0,%0,foo
wxr1u %1, 1, 1
beq %0,%0,foo
wxr30 %1, 1, 1
beq %0,%0,foo
wxr30u %1, 1, 1
foo: nop
|
tactcomplabs/xbgas-binutils-gdb
| 3,716
|
gas/testsuite/gas/tic6x/unwind-1.s
|
.cfi_sections .c6xabi.exidx
# standard layout
.p2align 8
f0:
.cfi_startproc
stw .d2t2 B3, *B15--(16)
.cfi_def_cfa_offset 16
.cfi_offset 19, 0
stw .d2t1 A11, *+B15(12)
.cfi_offset 11, -4
nop 4
.cfi_endproc
.endp
# standard layout (pr0)
.p2align 8
f1:
.cfi_startproc
.cfi_def_cfa_offset 8
stw .d2t1 A11, *+B15(8)
.cfi_offset 11, -0
stw .d2t1 A10, *+B15(4)
.cfi_offset 10, -4
nop 4
.cfi_endproc
.personalityindex 0
.endp
# standard layout (pr1)
.p2align 8
f2:
.cfi_startproc
stw .d2t2 B15, *B15--(24)
.cfi_def_cfa_offset 24
.cfi_offset 31, 0
stw .d2t2 B10, *+B15(20)
.cfi_offset 26, -4
stw .d2t2 B3, *+B15(16)
.cfi_offset 19, -8
stdw .d2t1 A11:A10, *+B15(8)
.cfi_offset 11, -12
.cfi_offset 10, -16
nop 4
.cfi_endproc
.personalityindex 1
.endp
# standard layout (pr3)
.p2align 8
f3:
.cfi_startproc
stw .d2t2 B3, *B15--(16)
.cfi_def_cfa_offset 16
.cfi_offset 19, 0
stw .d2t1 A11, *+B15(12)
.cfi_offset 11, -4
nop 4
.cfi_endproc
.personalityindex 3
.endp
# compact layout
.p2align 8
f4:
.cfi_startproc
stw .d2t2 B3, *B15--(8)
.cfi_offset 19, 0
.cfi_def_cfa_offset 8
stw .d2t1 A11, *B15--(8)
.cfi_offset 11, -8
.cfi_def_cfa_offset 16
nop 4
.cfi_endproc
.endp
# compact layout (pr0)
.p2align 8
f5:
.cfi_startproc
stw .d2t2 B3, *B15--(8)
.cfi_offset 19, 0
.cfi_def_cfa_offset 8
stw .d2t1 A11, *B15--(8)
.cfi_offset 11, -8
.cfi_def_cfa_offset 16
nop 4
.cfi_endproc
.personalityindex 0
.endp
# compact layout (pr4)
.p2align 8
f6:
.cfi_startproc
stw .d2t2 B3, *B15--(8)
.cfi_offset 19, 0
.cfi_def_cfa_offset 8
stw .d2t1 A11, *B15--(8)
.cfi_offset 11, -8
.cfi_def_cfa_offset 16
nop 4
.cfi_endproc
.personalityindex 4
.endp
# compact layout (aligned pair)
.p2align 8
f7:
.cfi_startproc
stw .d2t2 B10, *B15--(8)
.cfi_offset 26, 0
.cfi_def_cfa_offset 8
stw .d2t2 B3, *B15--(8)
.cfi_offset 19, -8
.cfi_def_cfa_offset 8
stdw .d2t1 A11:A10, *B15--(8)
.cfi_offset 11, -12
.cfi_offset 10, -16
.cfi_def_cfa_offset 24
nop 4
.cfi_endproc
.endp
# compact layout (aligned pair + 1)
.p2align 8
f8:
.cfi_startproc
stw .d2t2 B3, *B15--(8)
.cfi_offset 19, 0
.cfi_def_cfa_offset 8
stdw .d2t1 A13:A12, *B15--(8)
.cfi_offset 13, -4
.cfi_offset 12, -8
.cfi_def_cfa_offset 16
stw .d2t1 A10, *B15--(8)
.cfi_offset 10, -16
.cfi_def_cfa_offset 24
nop 4
.cfi_endproc
.endp
# compact layout (misaligned pair)
.p2align 8
f9:
.cfi_startproc
stw .d2t2 B11, *B15--(8)
.cfi_offset 27, 0
.cfi_def_cfa_offset 8
stw .d2t2 B10, *B15--(8)
.cfi_offset 26, -8
.cfi_def_cfa_offset 16
nop 4
.cfi_endproc
.endp
# standard frame pointer
.p2align 8
fa:
.cfi_startproc
stw .d2t1 A15, *B15--(16)
.cfi_def_cfa_offset 8
.cfi_offset 15, 0
mv .s1x B15, A15
addk .s1 16, A15
.cfi_def_cfa 15, 0
stw .d2t1 A11, *+B15(12)
.cfi_offset 11, -4
nop 4
.cfi_endproc
.endp
# compact frame pointer
.p2align 8
fb:
.cfi_startproc
stw .d2t1 A15, *B15--(8)
.cfi_def_cfa_offset 8
.cfi_offset 15, 0
mv .s1x B15, A15
addk .s1 16, A15
.cfi_def_cfa 15, 0
stw .d2t1 A11, *B15--(8)
.cfi_offset 11, -8
nop 4
.cfi_endproc
.endp
# custom layout
.p2align 8
fc:
.cfi_startproc
sub .s2 B15, 16, B15
stw .d2t2 B3, *+B15(12)
.cfi_def_cfa_offset 16
.cfi_offset 19, -4
nop 4
.cfi_endproc
.endp
# custom layout
.p2align 8
fd:
.cfi_startproc
sub .s2 B15, 16, B15
stw .d2t2 B3, *+B15(12)
.cfi_def_cfa_offset 16
.cfi_offset 19, -4
stw .d2t1 A11, *+B15(8)
.cfi_offset 11, -8
nop 4
.cfi_endproc
.endp
# custom layout
.p2align 8
fe:
.cfi_startproc
sub .s2 B15, 16, B15
stw .d2t2 B3, *+B15(12)
.cfi_def_cfa_offset 16
.cfi_offset 19, -4
stw .d2t1 A11, *+B15(4)
.cfi_offset 11, -12
nop 4
.cfi_endproc
.endp
# custom layout
.p2align 8
ff:
.cfi_startproc
addk .s2 -24, B15
stw .d2t2 B3, *+B15(24)
.cfi_def_cfa_offset 24
.cfi_offset 19, 0
stw .d2t1 A11, *+B15(4)
.cfi_offset 11, -20
nop 4
.cfi_endproc
.endp
|
tactcomplabs/xbgas-binutils-gdb
| 3,750
|
gas/testsuite/gas/tic6x/insns16-s-unit.s
|
; Test C64x+ S-unit compact instruction formats
.text
nop
.align 16
nop
.align 16
s3_nosat_op_0:
.short 0x000a
.short 0x201b
.short 0x512a
.short 0x713b
.short 0x824a
.short 0xa25b
.short 0xd36a
.short 0xf37b
.short 0xe28a
s3_nosat_op_1:
.short 0x0a9b
.short 0x39aa
.short 0x59bb
.short 0x68ca
.short 0x88db
.word 0xefe00000 | 0x0000
s3_sat_op_0:
.short 0x21ea
.short 0x41fb
.short 0x720a
.short 0x921b
.short 0xc32a
.short 0xe33b
.short 0xf24a
.short 0xb25b
.short 0x816a
s3_sat_op_1:
.short 0xa87b
.short 0xd88a
.short 0xfa9b
.short 0xeaaa
.short 0x7bbb
.word 0xefe00000 | 0x4000
s3i:
.short 0x040a
.short 0x251b
.short 0x362a
.short 0x573b
.short 0x444a
.short 0x655b
.short 0x766a
.short 0x9ffb
.short 0x8cea
.short 0xaddb
.short 0xbeca
.short 0xdfbb
.short 0xccaa
.short 0xed9b
.word 0xefe00000 | 0x0000
smvk8:
.short 0x0012
.short 0x1113
.short 0x2232
.short 0x3333
.short 0x4752
.short 0x5653
.short 0x6572
.short 0x78f3
.short 0x8992
.short 0x9a93
.short 0xabb2
.short 0xbed2
.short 0xcdf3
.short 0xfc92
.word 0xefe00000 | 0x0000
ssh5_nosat:
.short 0x0402
.short 0x1503
.short 0x2682
.short 0x3783
.short 0x4c22
.short 0x5d23
.short 0x6ea2
.short 0x7fa3
.short 0x8442
.short 0x9543
.short 0xa6c2
.short 0xb7c3
.short 0xcc42
.short 0xdd43
.word 0xefe00000 | 0x0000
ssh5_sat:
.short 0xec02
.short 0xfd03
.short 0xe682
.short 0xd783
.short 0xc422
.short 0xb523
.short 0xaea2
.short 0x9fa3
.short 0x8c42
.short 0x7d43
.short 0x66c2
.short 0x57c3
.short 0x4442
.short 0x3543
.word 0xefe00000 | 0x4000
s2sh:
.short 0x0462
.short 0x2563
.short 0x4662
.short 0x6f63
.short 0x8c62
.short 0xad63
.short 0xce62
.short 0xf7e3
.short 0xd4e2
.short 0xb5e3
.short 0x96e2
.short 0x7fe3
.short 0x5ce2
.short 0x3de3
.word 0xefe00000
sc5:
.short 0x0002
.short 0x1103
.short 0x2202
.short 0x3303
.short 0x4a22
.short 0x5923
.short 0x6822
.short 0x71a3
.short 0x82a2
.short 0x93c3
.short 0xa2c2
.short 0xb9c3
.short 0xc8c2
.short 0xf9c3
.word 0xefe00000
s2ext:
.short 0x0062
.short 0x2163
.short 0x4262
.short 0x6b63
.short 0x8862
.short 0xa963
.short 0xca62
.short 0xf3e3
.short 0xd0e2
.short 0xb1e3
.short 0x9ae2
.short 0x7be3
.short 0x58e2
.short 0x39e3
.word 0xefe00000
sx2op:
.short 0x002e
.short 0x212f
.short 0x522e
.short 0x732f
.short 0x802e
.short 0xa12f
.short 0xd22e
.short 0xfb2f
.short 0x082e
.short 0x292f
.short 0x5a2e
.short 0x7b2f
.short 0x882e
.short 0xa92f
.word 0xefe00000
sx5:
.short 0x042e
.short 0x152f
.short 0x262e
.short 0x372f
.short 0x4c2e
.short 0x5d2f
.short 0x6e2e
.short 0x77af
.short 0x84ae
.short 0x95af
.short 0xaeae
.short 0xbfaf
.short 0xccae
.short 0xfdaf
.word 0xefe00000
sx1:
.short 0x586e
.short 0x596f
.short 0x5a6e
.short 0x5b6f
.short 0x586e
.short 0x796f
.short 0x7a6e
.short 0x7bef
.short 0x78ee
.short 0x79ef
.short 0xdaee
.short 0xdbef
.short 0xd8ee
.short 0xd9ef
.word 0xefe00000
sx1_rs:
.short 0x586e
.short 0x596f
.short 0x5a6e
.short 0x5b6f
.short 0x586e
.short 0x796f
.short 0x7a6e
.short 0x7bef
.short 0x78ee
.short 0x79ef
.short 0xdaee
.short 0xdbef
.short 0xd8ee
.short 0xd9ef
.word 0xefe00000 | 0x00080000
sx1b:
.short 0x006e
.short 0x216f
.short 0x22ee
.short 0x43ef
.short 0x446e
.short 0x656f
.short 0x66ee
.short 0x87ef
.short 0x866e
.short 0xa56f
.short 0xa4ee
.short 0xc3ef
.short 0xc26e
.short 0xe16f
.word 0xefe00000
sx1b_rs:
.short 0x006e
.short 0x216f
.short 0x22ee
.short 0x43ef
.short 0x446e
.short 0x656f
.short 0x66ee
.short 0x87ef
.short 0x866e
.short 0xa56f
.short 0xa4ee
.short 0xc3ef
.short 0xc26e
.short 0xe16f
.word 0xefe00000 | 0x00080000
|
tactcomplabs/xbgas-binutils-gdb
| 3,716
|
gas/testsuite/gas/tic6x/unwind-2.s
|
.cfi_sections .c6xabi.exidx
# standard layout
.p2align 8
f0:
.cfi_startproc
stw .d2t2 B3, *B15--(16)
.cfi_def_cfa_offset 16
.cfi_offset 19, 0
stw .d2t1 A11, *+B15(12)
.cfi_offset 11, -4
nop 4
.cfi_endproc
.endp
# standard layout (pr0)
.p2align 8
f1:
.cfi_startproc
.cfi_def_cfa_offset 8
stw .d2t1 A11, *+B15(8)
.cfi_offset 11, -0
stw .d2t1 A10, *+B15(4)
.cfi_offset 10, -4
nop 4
.cfi_endproc
.personalityindex 0
.endp
# standard layout (pr1)
.p2align 8
f2:
.cfi_startproc
stw .d2t2 B15, *B15--(24)
.cfi_def_cfa_offset 24
.cfi_offset 31, 0
stw .d2t2 B10, *+B15(20)
.cfi_offset 26, -4
stw .d2t2 B3, *+B15(16)
.cfi_offset 19, -8
stdw .d2t1 A11:A10, *+B15(8)
.cfi_offset 11, -16
.cfi_offset 10, -12
nop 4
.cfi_endproc
.personalityindex 1
.endp
# standard layout (pr3)
.p2align 8
f3:
.cfi_startproc
stw .d2t2 B3, *B15--(16)
.cfi_def_cfa_offset 16
.cfi_offset 19, 0
stw .d2t1 A11, *+B15(12)
.cfi_offset 11, -4
nop 4
.cfi_endproc
.personalityindex 3
.endp
# compact layout
.p2align 8
f4:
.cfi_startproc
stw .d2t2 B3, *B15--(8)
.cfi_offset 19, 0
.cfi_def_cfa_offset 8
stw .d2t1 A11, *B15--(8)
.cfi_offset 11, -8
.cfi_def_cfa_offset 16
nop 4
.cfi_endproc
.endp
# compact layout (pr0)
.p2align 8
f5:
.cfi_startproc
stw .d2t2 B3, *B15--(8)
.cfi_offset 19, 0
.cfi_def_cfa_offset 8
stw .d2t1 A11, *B15--(8)
.cfi_offset 11, -8
.cfi_def_cfa_offset 16
nop 4
.cfi_endproc
.personalityindex 0
.endp
# compact layout (pr4)
.p2align 8
f6:
.cfi_startproc
stw .d2t2 B3, *B15--(8)
.cfi_offset 19, 0
.cfi_def_cfa_offset 8
stw .d2t1 A11, *B15--(8)
.cfi_offset 11, -8
.cfi_def_cfa_offset 16
nop 4
.cfi_endproc
.personalityindex 4
.endp
# compact layout (aligned pair)
.p2align 8
f7:
.cfi_startproc
stw .d2t2 B10, *B15--(8)
.cfi_offset 26, 0
.cfi_def_cfa_offset 8
stw .d2t2 B3, *B15--(8)
.cfi_offset 19, -8
.cfi_def_cfa_offset 8
stdw .d2t1 A11:A10, *B15--(8)
.cfi_offset 11, -16
.cfi_offset 10, -12
.cfi_def_cfa_offset 24
nop 4
.cfi_endproc
.endp
# compact layout (aligned pair + 1)
.p2align 8
f8:
.cfi_startproc
stw .d2t2 B3, *B15--(8)
.cfi_offset 19, 0
.cfi_def_cfa_offset 8
stdw .d2t1 A13:A12, *B15--(8)
.cfi_offset 13, -8
.cfi_offset 12, -4
.cfi_def_cfa_offset 16
stw .d2t1 A10, *B15--(8)
.cfi_offset 10, -16
.cfi_def_cfa_offset 24
nop 4
.cfi_endproc
.endp
# compact layout (misaligned pair)
.p2align 8
f9:
.cfi_startproc
stw .d2t2 B11, *B15--(8)
.cfi_offset 27, 0
.cfi_def_cfa_offset 8
stw .d2t2 B10, *B15--(8)
.cfi_offset 26, -8
.cfi_def_cfa_offset 16
nop 4
.cfi_endproc
.endp
# standard frame pointer
.p2align 8
fa:
.cfi_startproc
stw .d2t1 A15, *B15--(16)
.cfi_def_cfa_offset 8
.cfi_offset 15, 0
mv .s1x B15, A15
addk .s1 16, A15
.cfi_def_cfa 15, 0
stw .d2t1 A11, *+B15(12)
.cfi_offset 11, -4
nop 4
.cfi_endproc
.endp
# compact frame pointer
.p2align 8
fb:
.cfi_startproc
stw .d2t1 A15, *B15--(8)
.cfi_def_cfa_offset 8
.cfi_offset 15, 0
mv .s1x B15, A15
addk .s1 16, A15
.cfi_def_cfa 15, 0
stw .d2t1 A11, *B15--(8)
.cfi_offset 11, -8
nop 4
.cfi_endproc
.endp
# custom layout
.p2align 8
fc:
.cfi_startproc
sub .s2 B15, 16, B15
stw .d2t2 B3, *+B15(12)
.cfi_def_cfa_offset 16
.cfi_offset 19, -4
nop 4
.cfi_endproc
.endp
# custom layout
.p2align 8
fd:
.cfi_startproc
sub .s2 B15, 16, B15
stw .d2t2 B3, *+B15(12)
.cfi_def_cfa_offset 16
.cfi_offset 19, -4
stw .d2t1 A11, *+B15(8)
.cfi_offset 11, -8
nop 4
.cfi_endproc
.endp
# custom layout
.p2align 8
fe:
.cfi_startproc
sub .s2 B15, 16, B15
stw .d2t2 B3, *+B15(12)
.cfi_def_cfa_offset 16
.cfi_offset 19, -4
stw .d2t1 A11, *+B15(4)
.cfi_offset 11, -12
nop 4
.cfi_endproc
.endp
# custom layout
.p2align 8
ff:
.cfi_startproc
addk .s2 -24, B15
stw .d2t2 B3, *+B15(24)
.cfi_def_cfa_offset 24
.cfi_offset 19, 0
stw .d2t1 A11, *+B15(4)
.cfi_offset 11, -20
nop 4
.cfi_endproc
.endp
|
tactcomplabs/xbgas-binutils-gdb
| 2,174
|
gas/testsuite/gas/tic6x/reloc-bad-3.s
|
# Test relocation overflow and insufficiently divisible values. Note
# that divisibility checks for constant values are only applicable to
# load and store offsets, not ADDA, because constant values are
# encoded literally for ADDA, and divisbility checks for offsets from
# symbols are only applicable with REL relocations.
.data
t0:
.short b65535-b0
.short b65536-b0
.short b0-b32768
.short b32767-b65536
.byte b255-b0
.byte b256-b0
.byte b0-b128
.byte b127-b256
.text
.nocmp
.globl f
f:
addab .D1X b14,b32767-b0,a5
addab .D1X b14,b32768-b0,a5
addab .D1X b14,b127-b128,a5
addah .D1X b14,b32767-b0,a5
addah .D1X b14,b32768-b0,a5
addah .D1X b14,b127-b128,a5
addaw .D1X b14,b32767-b0,a5
addaw .D1X b14,b32768-b0,a5
addaw .D1X b14,b127-b128,a5
addk .S1 b32767-b0,a9
addk .S1 b0-b32768,a9
addk .S1 b32768-b0,a9
addk .S1 b32767-b65536,a9
mvk .S1 b32767-b0,a9
mvk .S1 b0-b32768,a9
mvk .S1 b32768-b0,a9
mvk .S1 b32767-b65536,a9
ldb .D2T2 *+b14(b32767-b0),b1
ldb .D2T2 *+b14(b32768-b0),b1
ldb .D2T2 *+b14(b32767-b32768),b1
ldbu .D2T2 *+b14(b32767-b0),b1
ldbu .D2T2 *+b14(b32768-b0),b1
ldbu .D2T2 *+b14(b32767-b32768),b1
ldh .D2T2 *+b14(h32767-h0),b1
ldh .D2T2 *+b14(h32768-h0),b1
ldh .D2T2 *+b14(h32767-h32768),b1
ldh .D2T2 *+b14(b32768-b32767),b1
ldhu .D2T2 *+b14(h32767-h0),b1
ldhu .D2T2 *+b14(h32768-h0),b1
ldhu .D2T2 *+b14(h32767-h32768),b1
ldhu .D2T2 *+b14(b32768-b32767),b1
ldw .D2T2 *+b14(w32767-w0),b1
ldw .D2T2 *+b14(w32768-w0),b1
ldw .D2T2 *+b14(w32767-w32768),b1
ldw .D2T2 *+b14(h32768-h32767),b1
stb .D2T2 b1,*+b14(b32767-b0)
stb .D2T2 b1,*+b14(b32768-b0)
stb .D2T2 b1,*+b14(b32767-b32768)
sth .D2T2 b1,*+b14(h32767-h0)
sth .D2T2 b1,*+b14(h32768-h0)
sth .D2T2 b1,*+b14(h32767-h32768)
sth .D2T2 b1,*+b14(b32768-b32767)
stw .D2T2 b1,*+b14(w32767-w0)
stw .D2T2 b1,*+b14(w32768-w0)
stw .D2T2 b1,*+b14(w32767-w32768)
stw .D2T2 b1,*+b14(h32768-h32767)
b0:
.space 127
b127:
.space 1
b128:
.space 127
b255:
.space 1
b256:
.space 32511
b32767:
.space 1
b32768:
.space 32767
b65535:
.space 1
b65536:
.word 0
h0:
.space 65534
h32767:
.space 2
h32768:
.word 0
w0:
.space 131068
w32767:
.space 4
w32768:
.word 0
|
tactcomplabs/xbgas-binutils-gdb
| 1,040
|
gas/testsuite/gas/tic6x/predicate-bad-2.s
|
# Test predicates allowed or disallowed depending on the architecture.
.text
.globl f
f:
[A0] nop
[A1] nop
[A2] nop
[B0] nop
[B1] nop
[B2] nop
[!A0] nop
[!A1] nop
[!A2] nop
[!B0] nop
[!B1] nop
[!B2] nop
.arch c64x
[A0] nop
[A1] nop
[A2] nop
[B0] nop
[B1] nop
[B2] nop
[!A0] nop
[!A1] nop
[!A2] nop
[!B0] nop
[!B1] nop
[!B2] nop
.arch c64x+
[A0] nop
[A1] nop
[A2] nop
[B0] nop
[B1] nop
[B2] nop
[!A0] nop
[!A1] nop
[!A2] nop
[!B0] nop
[!B1] nop
[!B2] nop
.arch c67x
[A0] nop
[A1] nop
[A2] nop
[B0] nop
[B1] nop
[B2] nop
[!A0] nop
[!A1] nop
[!A2] nop
[!B0] nop
[!B1] nop
[!B2] nop
.arch c67x+
[A0] nop
[A1] nop
[A2] nop
[B0] nop
[B1] nop
[B2] nop
[!A0] nop
[!A1] nop
[!A2] nop
[!B0] nop
[!B1] nop
[!B2] nop
.arch c674x
[A0] nop
[A1] nop
[A2] nop
[B0] nop
[B1] nop
[B2] nop
[!A0] nop
[!A1] nop
[!A2] nop
[!B0] nop
[!B1] nop
[!B2] nop
.arch c62x
[A0] nop
[A1] nop
[A2] nop
[B0] nop
[B1] nop
[B2] nop
[!A0] nop
[!A1] nop
[!A2] nop
[!B0] nop
[!B1] nop
[!B2] nop
|
tactcomplabs/xbgas-binutils-gdb
| 2,453
|
gas/testsuite/gas/tic6x/insns16-doff4.s
|
; Test C64x+ 16 bits instructions - doff4 format
.text
.nocmp
doff4:
nop
.align 16
nop
.align 16
.short 0x0004
.short 0x1004
.short 0x0204
.short 0x000c
.short 0x0005
.short 0x1005
.short 0x0205
.short 0x000d
.short 0x1005
.short 0x0205
.short 0x120d
.short 0x2a0d
.short 0x3a1d
.short 0x221d
.word 0xefe00000
.short 0x0004
.short 0x1004
.short 0x0204
.short 0x000c
.short 0x0005
.short 0x1005
.short 0x0205
.short 0x000d
.short 0x1005
.short 0x0205
.short 0x120d
.short 0x2a0d
.short 0x3a1d
.short 0x221d
.word 0xefe8c000
.short 0x0004
.short 0x1004
.short 0x0204
.short 0x000c
.short 0x0005
.short 0x1005
.short 0x0205
.short 0x000d
.short 0x1005
.short 0x0205
.short 0x120d
.short 0x2a0d
.short 0x3a1d
.short 0x221d
.word 0xefe9c000
.short 0x0004
.short 0x1004
.short 0x0204
.short 0x000c
.short 0x0005
.short 0x1005
.short 0x0205
.short 0x000d
.short 0x1005
.short 0x0205
.short 0x120d
.short 0x2a0d
.short 0x3a1d
.short 0x221d
.word 0xefeac000
.short 0x0004
.short 0x1004
.short 0x0204
.short 0x000c
.short 0x0005
.short 0x1005
.short 0x0205
.short 0x000d
.short 0x1005
.short 0x0205
.short 0x120d
.short 0x2a0d
.short 0x3a1d
.short 0x221d
.word 0xefebc000
.short 0x0004
.short 0x1004
.short 0x0204
.short 0x000c
.short 0x0005
.short 0x1005
.short 0x0205
.short 0x000d
.short 0x1005
.short 0x0205
.short 0x120d
.short 0x2a0d
.short 0x3a1d
.short 0x221d
.word 0xefecc000
.short 0x0004
.short 0x1004
.short 0x0204
.short 0x000c
.short 0x0005
.short 0x1005
.short 0x0205
.short 0x000d
.short 0x1005
.short 0x0205
.short 0x120d
.short 0x2a0d
.short 0x3a1d
.short 0x221d
.word 0xefedc000
.short 0x0004
.short 0x1004
.short 0x0204
.short 0x000c
.short 0x0005
.short 0x1005
.short 0x0205
.short 0x000d
.short 0x1005
.short 0x0205
.short 0x120d
.short 0x2a0d
.short 0x3a1d
.short 0x221d
.word 0xefeec000
.short 0x0004
.short 0x1004
.short 0x0204
.short 0x000c
.short 0x0005
.short 0x1005
.short 0x0205
.short 0x000d
.short 0x1005
.short 0x0205
.short 0x120d
.short 0x2a0d
.short 0x3a1d
.short 0x221d
.word 0xefefc000
.short 0x0014
.short 0x1014
.short 0x0214
.short 0x001c
.short 0x0015
.short 0x1015
.short 0x0215
.short 0x001d
.short 0x1015
.short 0x0215
.short 0x121d
.short 0x2a1d
.short 0x3a1d
.short 0x221d
.word 0xefefc000
|
tactcomplabs/xbgas-binutils-gdb
| 2,380
|
gas/testsuite/gas/tic6x/insns16-dinc.s
|
; Test C64x+ dinc compact instruction format
.text
dinc:
nop
.align 16
nop
.align 16
.short 0x0c04
.short 0x1c04
.short 0x0e04
.short 0x0c0c
.short 0x0c05
.short 0x1c05
.short 0x0e05
.short 0x0c0d
.short 0x1c05
.short 0x0c05
.short 0x1e0d
.short 0x2e0d
.short 0x3e1d
.short 0x2e1d
.word 0xefe00000
.short 0x0c04
.short 0x1c04
.short 0x0e04
.short 0x0c0c
.short 0x0c05
.short 0x1c05
.short 0x0e05
.short 0x0c0d
.short 0x1c05
.short 0x0e05
.short 0x1e0d
.short 0x2e0d
.short 0x3e1d
.short 0x2e1d
.word 0xefe8c000
.short 0x0c04
.short 0x1c04
.short 0x0e04
.short 0x0c0c
.short 0x0c05
.short 0x1c05
.short 0x0e05
.short 0x0c0d
.short 0x1c05
.short 0x0e05
.short 0x1e0d
.short 0x2e0d
.short 0x3e1d
.short 0x2e1d
.word 0xefe9c000
.short 0x0c04
.short 0x1c04
.short 0x0e04
.short 0x0c0c
.short 0x0c05
.short 0x1c05
.short 0x0e05
.short 0x0c0d
.short 0x1c05
.short 0x0e05
.short 0x1e0d
.short 0x2e0d
.short 0x3e1d
.short 0x2e1d
.word 0xefeac000
.short 0x0e04
.short 0x1e04
.short 0x0e04
.short 0x0c0c
.short 0x0c05
.short 0x1c05
.short 0x0e05
.short 0x0c0d
.short 0x1c05
.short 0x0e05
.short 0x1e0d
.short 0x2e0d
.short 0x3e1d
.short 0x2e1d
.word 0xefebc000
.short 0x0c04
.short 0x1c04
.short 0x0e04
.short 0x0c0c
.short 0x0c05
.short 0x1c05
.short 0x0e05
.short 0x0c0d
.short 0x1c05
.short 0x0e05
.short 0x1e0d
.short 0x2e0d
.short 0x3e1d
.short 0x2e1d
.word 0xefecc000
.short 0x0c04
.short 0x1c04
.short 0x0e04
.short 0x0c0c
.short 0x0c05
.short 0x1c05
.short 0x0e05
.short 0x0c0d
.short 0x1c05
.short 0x0e05
.short 0x1e0d
.short 0x2e0d
.short 0x3e1d
.short 0x2e1d
.word 0xefedc000
.short 0x0c04
.short 0x1c04
.short 0x0e04
.short 0x0c0c
.short 0x0c05
.short 0x1c05
.short 0x0e05
.short 0x0c0d
.short 0x1c05
.short 0x0e05
.short 0x1e0d
.short 0x2e0d
.short 0x3e1d
.short 0x2e1d
.word 0xefeec000
.short 0x0c04
.short 0x1c04
.short 0x0e04
.short 0x0c0c
.short 0x0c05
.short 0x1c05
.short 0x0e05
.short 0x0c0d
.short 0x1c05
.short 0x0e05
.short 0x1e0d
.short 0x2e0d
.short 0x3e1d
.short 0x2e1d
.word 0xefefc000
.short 0x0c14
.short 0x1c14
.short 0x0e14
.short 0x0c1c
.short 0x0c15
.short 0x1c15
.short 0x0e15
.short 0x0c1d
.short 0x1c15
.short 0x0e15
.short 0x1e1d
.short 0x2e1d
.short 0x3e1d
.short 0x2e1d
.word 0xefefc000
|
tactcomplabs/xbgas-binutils-gdb
| 1,745
|
gas/testsuite/gas/tic6x/insns16-d-unit.s
|
; Test C64x+ D-unit compact instruction formats
.text
nop
.align 16
nop
.align 16
dstk: ; op = 0 | STW (.unit) src, *B15[ucst5]
; op = 1 | LDW (.unit)*B15[ucst5], dst
.short 0x8c05
.short 0x9c05
.short 0x8c05
.short 0x9c05
.short 0xcc35
.short 0xfc05
.short 0xdcf5
.short 0x8c0d
.short 0x9c0d
.short 0x8c0d
.short 0x9c0d
.short 0xcc3d
.short 0xfc0d
.short 0xdcfd
.word 0xefe00000
dx2op: ; op = 0 | ADD (.unit) src1, src2, dst (src1 = dst)
; op = 1 | SUB (.unit) src1, src2, dst (src1 = dst, dst = src1 - src2
.short 0x0036
.short 0x0037
.short 0x0836
.short 0x0837
.short 0x1036
.short 0x1837
.short 0x8036
.short 0xc037
.short 0xe836
.short 0x8837
.short 0xda36
.short 0xe037
.short 0xd236
.short 0xe3b7
.word 0xefe00000
dx5: ; ADDAW (.unit)B15, ucst5, dst
.short 0x0436
.short 0x0437
.short 0x0c36
.short 0x0c37
.short 0x1436
.short 0x1c37
.short 0x8436
.short 0xc437
.short 0xec36
.short 0x8c37
.short 0xde36
.short 0xe437
.short 0xd636
.short 0xe7b7
.word 0xefe00000
dx5p:
.short 0x0c77
.short 0x2d77
.short 0x4e77
.short 0x6f77
.short 0x8c77
.short 0xad77
.short 0xce77
.short 0xeff7
.short 0x2cf7
.short 0x4df7
.short 0x6ef7
.short 0x8ff7
.short 0xacf7
.short 0xcdf7
.word 0xefe00000
dx1:
.short 0x7876
.short 0x7877
.short 0x78f6
.short 0x79f7
.short 0x5876
.short 0x9877
.short 0xd876
.short 0x7877
.short 0x7876
.short 0x7877
.short 0x7876
.short 0x7877
.short 0x7876
.short 0x7877
.word 0xefe00000
dpp:
.short 0x0077
.short 0x4177
.short 0xa277
.short 0xe377
.short 0x2477
.short 0x6577
.short 0x8677
.short 0x0777
.short 0x11f7
.short 0x52f7
.short 0x4777
.short 0x6777
.short 0x15f7
.short 0x56f7
.word 0xefe80000
|
tactcomplabs/xbgas-binutils-gdb
| 2,448
|
gas/testsuite/gas/tic6x/insns16-dind.s
|
; Test C64x+ dind compact instruction format
.text
.nocmp
dind:
nop
.align 16
nop
.align 16
.short 0x0404
.short 0x1404
.short 0x0604
.short 0x040c
.short 0x0405
.short 0x1405
.short 0x0605
.short 0x040d
.short 0x1405
.short 0x0405
.short 0x160d
.short 0x260d
.short 0x361d
.short 0x261d
.word 0xefe00000
.short 0x0404
.short 0x1404
.short 0x0604
.short 0x040c
.short 0x0405
.short 0x1405
.short 0x0605
.short 0x040d
.short 0x1405
.short 0x0605
.short 0x160d
.short 0x260d
.short 0x361d
.short 0x261d
.word 0xefe8c000
.short 0x0404
.short 0x1404
.short 0x0604
.short 0x040c
.short 0x0405
.short 0x1405
.short 0x0605
.short 0x040d
.short 0x1405
.short 0x0605
.short 0x160d
.short 0x260d
.short 0x361d
.short 0x261d
.word 0xefe9c000
.short 0x0404
.short 0x1404
.short 0x0604
.short 0x040c
.short 0x0405
.short 0x1405
.short 0x0605
.short 0x040d
.short 0x1405
.short 0x0605
.short 0x160d
.short 0x260d
.short 0x361d
.short 0x261d
.word 0xefeac000
.short 0x0604
.short 0x1604
.short 0x0604
.short 0x040c
.short 0x0405
.short 0x1405
.short 0x0605
.short 0x040d
.short 0x1405
.short 0x0605
.short 0x160d
.short 0x260d
.short 0x361d
.short 0x261d
.word 0xefebc000
.short 0x0404
.short 0x1404
.short 0x0604
.short 0x040c
.short 0x0405
.short 0x1405
.short 0x0605
.short 0x040d
.short 0x1405
.short 0x0605
.short 0x160d
.short 0x260d
.short 0x361d
.short 0x261d
.word 0xefecc000
.short 0x0404
.short 0x1404
.short 0x0604
.short 0x040c
.short 0x0405
.short 0x1405
.short 0x0605
.short 0x040d
.short 0x1405
.short 0x0605
.short 0x160d
.short 0x260d
.short 0x361d
.short 0x261d
.word 0xefedc000
.short 0x0404
.short 0x1404
.short 0x0604
.short 0x040c
.short 0x0405
.short 0x1405
.short 0x0605
.short 0x040d
.short 0x1405
.short 0x0605
.short 0x160d
.short 0x260d
.short 0x361d
.short 0x261d
.word 0xefeec000
.short 0x0404
.short 0x1404
.short 0x0604
.short 0x040c
.short 0x0405
.short 0x1405
.short 0x0605
.short 0x040d
.short 0x1405
.short 0x0605
.short 0x160d
.short 0x260d
.short 0x361d
.short 0x261d
.word 0xefefc000
.short 0x0414
.short 0x1414
.short 0x0614
.short 0x041c
.short 0x0415
.short 0x1415
.short 0x0615
.short 0x041d
.short 0x1415
.short 0x0615
.short 0x161d
.short 0x261d
.short 0x361d
.short 0x261d
.word 0xefefc000
|
tactcomplabs/xbgas-binutils-gdb
| 2,865
|
gas/testsuite/gas/tic6x/insns-c674x-reloc.s
|
# Test C674x instructions generating relocations.
.data
w1:
.word 1
w2:
.word 2
.text
.nocmp
.globl ext1
.globl ext2
.globl ext3
.globl a1
.globl b1
.globl f
f:
addab .D1X b14,ext1,a5
addab .D2 b15,(ext2+7),b7
addab .D1X b14,(a1),a20
addab .D2 b14,(b1),b30
addab .D1X b14,w2-w1,a15
addab .D2 b14,w4-w3,b16
addah .D1X b14,ext1,a5
addah .D2 b15,(ext2+6),b7
addah .D1X b14,(a1),a20
addah .D2 b14,(b1),b30
addah .D1X b14,w2-w1,a15
addah .D2 b14,w4-w3,b16
addaw .D1X b14,ext1,a5
addaw .D2 b15,(ext2+8),b7
addaw .D1X b14,(a1),a20
addaw .D2 b14,(b1),b30
addaw .D1X b14,w2-w1,a15
addaw .D2 b14,w4-w3,b16
addaw .D1X b14,$DSBT_INDEX(__c6xabi_DSBT_BASE),a5
addaw .D2 b15,$GOT(ext2)+8,b7
addk .S1 ext1+3,a1
addk .S2 $dpr_byte(ext2)+5,b3
addk .S1 w2-w1,a4
addk .S2 w3-w4,b5
mvk .S1 ext1+3,a1
mvk .S2 $dpr_byte(ext2)+5,b3
mvk .S1 w2-w1,a4
mvk .S2 w3-w4,b5
mvkh .S1 ext3+1,a1
mvkh .S2 $DPR_GOT(ext2)+2,b2
mvkh .S1 $DPR_BYTE(ext1)+3,a3
mvkh .S2 $DPR_HWORD(ext3)+4,b4
mvkh .S1 $DPR_WORD(ext2)+5,a5
mvkh .S2 s1-s0,b6
mvklh .S1 ext3+1,a1
mvklh .S2 $DPR_GOT(ext2)+2,b2
mvklh .S1 $DPR_BYTE(ext1)+3,a3
mvklh .S2 $DPR_HWORD(ext3)+4,b4
mvklh .S1 $DPR_WORD(ext2)+5,a5
mvklh .S2 s1-s0,b6
mvkl .S1 ext3+1,a1
mvkl .S2 $DPR_GOT(ext2)+2,b2
mvkl .S1 $DPR_BYTE(ext1)+3,a3
mvkl .S2 $DPR_HWORD(ext3)+4,b4
mvkl .S1 $DPR_WORD(ext2)+5,a5
mvkl .S2 s1-s0,b6
ldb .D2T2 *+b14(ext1),b1
ldb .D2T1 *+b15(ext2+7),a1
ldb .D2T2 *+b15(b1),b1
ldb .D2T1 *+b14(a1),a1
ldb .D2T2 *+b14(w2-w1),b1
ldb .D2T1 *+b14(w4-w3),a1
ldbu .D2T2 *+b14(ext1),b1
ldbu .D2T1 *+b15(ext2+7),a1
ldbu .D2T2 *+b15(b1),b1
ldbu .D2T1 *+b14(a1),a1
ldbu .D2T2 *+b14(w2-w1),b1
ldbu .D2T1 *+b14(w4-w3),a1
ldh .D2T2 *+b14(ext1),b1
ldh .D2T1 *+b15(ext2+6),a1
ldh .D2T2 *+b15(b1),b1
ldh .D2T1 *+b14(a1),a1
ldh .D2T2 *+b14(w2-w1),b1
ldh .D2T1 *+b14(w4-w3),a1
ldhu .D2T2 *+b14(ext1),b1
ldhu .D2T1 *+b15(ext2+6),a1
ldhu .D2T2 *+b15(b1),b1
ldhu .D2T1 *+b14(a1),a1
ldhu .D2T2 *+b14(w2-w1),b1
ldhu .D2T1 *+b14(w4-w3),a1
ldw .D2T2 *+b14(ext1),b1
ldw .D2T1 *+b15(ext2+4),a1
ldw .D2T2 *+b15(b1),b1
ldw .D2T1 *+b14(a1),a1
ldw .D2T2 *+b14(w2-w1),b1
ldw .D2T1 *+b14(w4-w3),a1
ldw .D2T2 *+b14($DSBT_INDEX(__c6xabi_DSBT_BASE)),b1
ldw .D2T1 *+b14($GOT(ext2)+4),a1
stb .D2T2 b1,*+b14(ext1)
stb .D2T1 a1,*+b15(ext2+7)
stb .D2T2 b1,*+b15(b1)
stb .D2T1 a1,*+b14(a1)
stb .D2T2 b1,*+b14(w2-w1)
stb .D2T1 a1,*+b14(w4-w3)
sth .D2T2 b1,*+b14(ext1)
sth .D2T1 a1,*+b15(ext2+6)
sth .D2T2 b1,*+b15(b1)
sth .D2T1 a1,*+b14(a1)
sth .D2T2 b1,*+b14(w2-w1)
sth .D2T1 a1,*+b14(w4-w3)
stw .D2T2 b1,*+b14(ext1)
stw .D2T1 a1,*+b15(ext2+4)
stw .D2T2 b1,*+b15(b1)
stw .D2T1 a1,*+b14(a1)
stw .D2T2 b1,*+b14(w2-w1)
stw .D2T1 a1,*+b14(w4-w3)
stw .D2T2 b1,*+b14($DSBT_INDEX(__c6xabi_DSBT_BASE))
stw .D2T1 a1,*+b14($GOT(ext2)+4)
.data
w3:
.word 3
w4:
.word 4
s0:
.space 131073
s1:
.word 5
|
tactcomplabs/xbgas-binutils-gdb
| 1,990
|
gas/testsuite/gas/tic6x/unwind-bad-2.s
|
.cfi_sections .c6xabi.exidx
.cfi_startproc
# stack pointer offset too large for personality routine
.cfi_def_cfa_offset 0x3f8
.cfi_endproc
.personalityindex 3
.endp
.cfi_startproc
.cfi_def_cfa_offset 8
stw .d2t1 A11, *+B15(8)
.cfi_offset 11, -0
stw .d2t1 A10, *+B15(4)
.cfi_offset 10, -4
nop 4
.cfi_endproc
# stack frame layout does not match personality routine
.personalityindex 4
.endp
.cfi_startproc
stw .d2t2 B3, *B15--(8)
.cfi_offset 19, 0
.cfi_def_cfa_offset 8
stw .d2t1 A11, *B15--(8)
.cfi_offset 11, -8
.cfi_def_cfa_offset 16
nop 4
.cfi_endproc
# stack frame layout does not match personality routine
.personalityindex 3
.endp
.cfi_startproc
stw .d2t2 B4, *B15--(8)
# unable to generate unwinding opcode for reg 20
.cfi_offset 20, 0
.cfi_endproc
.endp
.cfi_startproc
mv .s2 B3, B4
# unable to generate unwinding opcode for reg 20
.cfi_register 19, 20
.cfi_endproc
.endp
.cfi_startproc
mv .s2 B4, B3
# unable to generate unwinding opcode for reg 20
.cfi_register 20, 19
.cfi_endproc
.endp
.cfi_startproc
stw .d2t2 B10, *B15--(8)
# unable to generate unwinding opcode for reg 20
.cfi_offset 26, 0
mv .s2 B3, B10
# unable to restore return address from previously restored reg
.cfi_register 19, 26
.cfi_endproc
.endp
.cfi_startproc
nop
# unhandled CFA insn for unwinding (259)
.cfi_escape 42
.cfi_endproc
.endp
.cfi_startproc
nop
# unable to generate unwinding opcode for frame pointer reg 14
.cfi_def_cfa_register 14
.cfi_endproc
.endp
.cfi_startproc
nop
# unable to generate unwinding opcode for frame pointer offset
.cfi_def_cfa 15, 8
.cfi_endproc
.endp
.cfi_startproc
nop
# unwound stack pointer not doubleword aligned
.cfi_def_cfa_offset 12
.cfi_endproc
.endp
.cfi_startproc
nop
.cfi_offset 10, 0
# stack frame layout too complex for unwinder
.cfi_offset 11, -0x808
.cfi_def_cfa_offset 0x10000
.cfi_endproc
.endp
.cfi_startproc
nop
.cfi_offset 12, -0
.cfi_offset 11, -4
.cfi_offset 10, -8
.cfi_def_cfa_offset 8
# unwound frame has negative size
.cfi_endproc
.endp
|
tactcomplabs/xbgas-binutils-gdb
| 5,445
|
gas/testsuite/gas/tic6x/reloc-bad-2.s
|
# Test expressions not representable by relocations.
.globl a
.globl b
.data
d:
.word $DSBT_INDEX(__c6xabi_DSBT_BASE)
.word $got(b)
.word $dpr_got(a)
.word $dpr_byte(b)
.word $dpr_hword(a)
.word $dpr_word(b)
.word $pcr_offset(b,f)
.text
.nocmp
.globl f
f:
addab .D1X b14,$dsbt_index(__c6xabi_DSBT_BASE),a5
addab .D1X b14,$GOT(b),a5
addab .D1X b14,$DPR_GOT(b),a5
addab .D1X b14,$DPR_BYTE(b),a5
addab .D1X b14,$DPR_HWORD(b),a5
addab .D1X b14,$DPR_WORD(b),a5
addab .D1X b14,$PCR_OFFSET(b,f),a5
addah .D1X b14,$dsbt_index(__c6xabi_DSBT_BASE),a5
addah .D1X b14,$GOT(b),a5
addah .D1X b14,$DPR_GOT(b),a5
addah .D1X b14,$DPR_BYTE(b),a5
addah .D1X b14,$DPR_HWORD(b),a5
addah .D1X b14,$DPR_WORD(b),a5
addah .D1X b14,$PCR_OFFSET(b,f),a5
addaw .D1X b14,$DPR_GOT(b),a5
addaw .D1X b14,$DPR_BYTE(b),a5
addaw .D1X b14,$DPR_HWORD(b),a5
addaw .D1X b14,$DPR_WORD(b),a5
addaw .D1X b14,$PCR_OFFSET(b,f),a5
addk .S1 $dsbt_index(__c6xabi_DSBT_BASE),a7
addk .S1 $got(b),a7
addk .S1 $dpr_got(b),a7
addk .S1 $dpr_hword(b),a7
addk .S1 $dpr_word(b),a7
addk .S1 $pcr_offset(b,f),a7
mvk .S1 $dsbt_index(__c6xabi_DSBT_BASE),a7
mvk .S1 $got(b),a7
mvk .S1 $dpr_got(b),a7
mvk .S1 $dpr_hword(b),a7
mvk .S1 $dpr_word(b),a7
mvkh .S1 $dsbt_index(__c6xabi_DSBT_BASE),a7
mvkh .S1 $got(b),a7
mvklh .S1 $dsbt_index(__c6xabi_DSBT_BASE),a7
mvklh .S1 $got(b),a7
mvkl .S1 $dsbt_index(__c6xabi_DSBT_BASE),a7
mvkl .S1 $got(b),a7
addkpc .S2 $dsbt_index(__c6xabi_DSBT_BASE),b3,0
addkpc .S2 $GOT(b),b3,0
addkpc .S2 $DPR_GOT(b),b3,0
addkpc .S2 $DPR_BYTE(b),b3,0
addkpc .S2 $DPR_HWORD(b),b3,0
addkpc .S2 $DPR_WORD(b),b3,0
addkpc .S2 $PCR_OFFSET(b,f),b3,0
b .S1 $dsbt_index(__c6xabi_DSBT_BASE)
b .S1 $GOT(b)
b .S1 $DPR_GOT(b)
b .S1 $DPR_BYTE(b)
b .S1 $DPR_HWORD(b)
b .S1 $DPR_WORD(b)
b .S1 $PCR_OFFSET(b,f)
call .S1 $dsbt_index(__c6xabi_DSBT_BASE)
call .S1 $GOT(b)
call .S1 $DPR_GOT(b)
call .S1 $DPR_BYTE(b)
call .S1 $DPR_HWORD(b)
call .S1 $DPR_WORD(b)
call .S1 $PCR_OFFSET(b,f)
bdec .S1 $dsbt_index(__c6xabi_DSBT_BASE),a1
bdec .S1 $GOT(b),a1
bdec .S1 $DPR_GOT(b),a1
bdec .S1 $DPR_BYTE(b),a1
bdec .S1 $DPR_HWORD(b),a1
bdec .S1 $DPR_WORD(b),a1
bdec .S1 $PCR_OFFSET(b,f),a1
bpos .S2 $dsbt_index(__c6xabi_DSBT_BASE),b1
bpos .S2 $GOT(b),b1
bpos .S2 $DPR_GOT(b),b1
bpos .S2 $DPR_BYTE(b),b1
bpos .S2 $DPR_HWORD(b),b1
bpos .S2 $DPR_WORD(b),b1
bpos .S2 $PCR_OFFSET(b,f),b1
bnop .S1 $dsbt_index(__c6xabi_DSBT_BASE),1
bnop .S1 $GOT(b),1
bnop .S1 $DPR_GOT(b),1
bnop .S1 $DPR_BYTE(b),1
bnop .S1 $DPR_HWORD(b),1
bnop .S1 $DPR_WORD(b),1
bnop .S1 $PCR_OFFSET(b,f),1
callnop $dsbt_index(__c6xabi_DSBT_BASE),1
callnop $GOT(b),1
callnop $DPR_GOT(b),1
callnop $DPR_BYTE(b),1
callnop $DPR_HWORD(b),1
callnop $DPR_WORD(b),1
callnop $PCR_OFFSET(b,f),1
callp .S1 $dsbt_index(__c6xabi_DSBT_BASE),a3
callp .S1 $GOT(b),a3
callp .S1 $DPR_GOT(b),a3
callp .S1 $DPR_BYTE(b),a3
callp .S1 $DPR_HWORD(b),a3
callp .S1 $DPR_WORD(b),a3
callp .S1 $PCR_OFFSET(b,f),a3
callret .S1 $dsbt_index(__c6xabi_DSBT_BASE)
callret .S1 $GOT(b)
callret .S1 $DPR_GOT(b)
callret .S1 $DPR_BYTE(b)
callret .S1 $DPR_HWORD(b)
callret .S1 $DPR_WORD(b)
callret .S1 $PCR_OFFSET(b,f)
ret .S1 $dsbt_index(__c6xabi_DSBT_BASE)
ret .S1 $GOT(b)
ret .S1 $DPR_GOT(b)
ret .S1 $DPR_BYTE(b)
ret .S1 $DPR_HWORD(b)
ret .S1 $DPR_WORD(b)
ret .S1 $PCR_OFFSET(b,f)
retp .S1 $dsbt_index(__c6xabi_DSBT_BASE),a3
retp .S1 $GOT(b),a3
retp .S1 $DPR_GOT(b),a3
retp .S1 $DPR_BYTE(b),a3
retp .S1 $DPR_HWORD(b),a3
retp .S1 $DPR_WORD(b),a3
retp .S1 $PCR_OFFSET(b,f),a3
ldb .D2T2 *+b14($dsbt_index(__c6xabi_DSBT_BASE)),b1
ldb .D2T2 *+b14($GOT(b)),b1
ldb .D2T2 *+b14($DPR_GOT(b)),b1
ldb .D2T2 *+b14($DPR_BYTE(b)),b1
ldb .D2T2 *+b14($DPR_HWORD(b)),b1
ldb .D2T2 *+b14($DPR_WORD(b)),b1
ldb .D2T2 *+b14($PCR_OFFSET(b,f)),b1
ldbu .D2T2 *+b14($dsbt_index(__c6xabi_DSBT_BASE)),b1
ldbu .D2T2 *+b14($GOT(b)),b1
ldbu .D2T2 *+b14($DPR_GOT(b)),b1
ldbu .D2T2 *+b14($DPR_BYTE(b)),b1
ldbu .D2T2 *+b14($DPR_HWORD(b)),b1
ldbu .D2T2 *+b14($DPR_WORD(b)),b1
ldbu .D2T2 *+b14($PCR_OFFSET(b,f)),b1
ldh .D2T2 *+b14($dsbt_index(__c6xabi_DSBT_BASE)),b1
ldh .D2T2 *+b14($GOT(b)),b1
ldh .D2T2 *+b14($DPR_GOT(b)),b1
ldh .D2T2 *+b14($DPR_BYTE(b)),b1
ldh .D2T2 *+b14($DPR_HWORD(b)),b1
ldh .D2T2 *+b14($DPR_WORD(b)),b1
ldh .D2T2 *+b14($PCR_OFFSET(b,f)),b1
ldhu .D2T2 *+b14($dsbt_index(__c6xabi_DSBT_BASE)),b1
ldhu .D2T2 *+b14($GOT(b)),b1
ldhu .D2T2 *+b14($DPR_GOT(b)),b1
ldhu .D2T2 *+b14($DPR_BYTE(b)),b1
ldhu .D2T2 *+b14($DPR_HWORD(b)),b1
ldhu .D2T2 *+b14($DPR_WORD(b)),b1
ldhu .D2T2 *+b14($PCR_OFFSET(b,f)),b1
ldw .D2T2 *+b14($DPR_GOT(b)),b1
ldw .D2T2 *+b14($DPR_BYTE(b)),b1
ldw .D2T2 *+b14($DPR_HWORD(b)),b1
ldw .D2T2 *+b14($DPR_WORD(b)),b1
ldw .D2T2 *+b14($PCR_OFFSET(b,f)),b1
stb .D2T2 b1,*+b14($dsbt_index(__c6xabi_DSBT_BASE))
stb .D2T2 b1,*+b14($GOT(b))
stb .D2T2 b1,*+b14($DPR_GOT(b))
stb .D2T2 b1,*+b14($DPR_BYTE(b))
stb .D2T2 b1,*+b14($DPR_HWORD(b))
stb .D2T2 b1,*+b14($DPR_WORD(b))
stb .D2T2 b1,*+b14($PCR_OFFSET(b,f))
sth .D2T2 b1,*+b14($dsbt_index(__c6xabi_DSBT_BASE))
sth .D2T2 b1,*+b14($GOT(b))
sth .D2T2 b1,*+b14($DPR_GOT(b))
sth .D2T2 b1,*+b14($DPR_BYTE(b))
sth .D2T2 b1,*+b14($DPR_HWORD(b))
sth .D2T2 b1,*+b14($DPR_WORD(b))
sth .D2T2 b1,*+b14($PCR_OFFSET(b,f))
stw .D2T2 b1,*+b14($DPR_GOT(b))
stw .D2T2 b1,*+b14($DPR_BYTE(b))
stw .D2T2 b1,*+b14($DPR_HWORD(b))
stw .D2T2 b1,*+b14($DPR_WORD(b))
stw .D2T2 b1,*+b14($PCR_OFFSET(b,f))
|
tactcomplabs/xbgas-binutils-gdb
| 38,810
|
gas/testsuite/gas/tic6x/insns-c674x.s
|
# Test C674x instructions.
.text
.nocmp
.globl f
f:
abs .L1 a5,a7
abs .L1X b11,a14
[a1] abs .L2 b16,b19
[!b2] abs .L2X a7,b31
[b1] abs .L1 a11:a10,a19:a18
abs .L2 b13:b12,b1:b0
abs2 .L1 a9,a10
[a2] abs2 .L1X b23,a5
abs2 .L2 b3,b14
abs2 .L2X a28,b25
.word 0x0c180b20
absdp .S1 a7:a6,a25:a24
[a0] absdp .S2 b3:b2,b5:b4
.word 0x0c1feb20
abssp .S1 a9,a8
abssp .S1X b18,a16
[b0] abssp .S2 b0,b7
[!a1] abssp .S2X a1,b26
add .L1 a5,a10,a20
[!a2] add .L1X a3,b11,a4
[!b1] add .L2 b9,b8,b7
add .L2X b30,a20,b10
add .L1 a10,a11,a21:a20
add .L1X a13,b26,a15:a14
[!a0] add .L2 b29,b28,b27:b26
add .L2X b25,a24,b23:b22
[!b0] add .L1 a1,a3:a2,a5:a4
add .L1X b20,a17:a16,a15:a14
add .L2 b24,b23:b22,b21:b20
[b2] add .L2X a6,b17:b16,b15:b14
add .L1 -16,a5,a6
[a0] add .L1X 15,b11,a30
add .L2 -11,b9,b10
add .L2X 14,a5,b7
add .L1 5,a3:a2,a7:a6
[b0] add .L2 -7,b29:b28,b29:b28
[!a0] add .S1 a11,a12,a13
add .S1X a14,b15,a16
add .S2 b17,b18,b19
add .S2X b20,a30,b25
add .S1 -16,a4,a11
add .S1X 13,b9,a23
[!b0] add .S2 15,b25,b11
add .S2X -4,a1,b2
add .D1 a5,a9,a2
[a1] add .D2 b16,b17,b18
[b1] add .D1 a5,31,a6
add .D2 b22,0,b21
.word 0x01042840
[!a1] add .D1X a1,b2,a3
add .D2X b7,a8,b9
.word 0x00842af0
add .D2 b4,-5,b21
[!b1] add .D1X b5,-16,a4
add .D2X a2,15,b9
addab .D1 a5,a10,a15
[a2] addab .D2 b24,b23,b22
[b2] addab .D1 a25,31,a28
addab .D2 b4,0,b7
addab .D1X b14,32767,a5
addab .D2 b15,32,b29
addad .D1 a4,a7,a11
[!a2] addad .D2 b5,b8,b13
[!b2] addad .D1 a13,31,a4
addad .D2 b21,0,b5
addah .D1 a5,a10,a15
[a0] addah .D2 b24,b23,b22
[b0] addah .D1 a25,31,a28
addah .D2 b4,0,b7
addah .D1X b14,32767,a5
addah .D2 b15,32,b29
addaw .D1 a5,a10,a15
[!a0] addaw .D2 b24,b23,b22
[!b0] addaw .D1 a25,31,a28
addaw .D2 b4,0,b7
addaw .D1X b14,32767,a5
addaw .D2 b15,32,b29
adddp .L1 a3:a2,a15:a14,a19:a18
[b1] adddp .L1X a9:a8,b7:b6,a21:a20
adddp .L2 b3:b2,b15:b14,b19:b18
[b1] adddp .L2X b9:b8,a7:a6,b21:b20
[a1] adddp .S1 a13:a12,a25:a24,a29:a28
adddp .S1X a19:a18,b17:b16,a31:a30
[a1] adddp .S2 b13:b12,b25:b24,b29:b28
adddp .S2X b19:b18,a17:a16,b31:b30
addk .S1 -32768,a5
[!a1] addk .S2 32767,b4
addsp .L1 a5,a6,a7
[!b1] addsp .L1X a5,b10,a20
[a2] addsp .L2 b25,b24,b23
addsp .L2X b30,a20,b10
addsp .S1 a5,a6,a7
[b2] addsp .S1X a5,b10,a20
[!a2] addsp .S2 b25,b24,b23
addsp .S2X b30,a20,b10
addsub .L1 a22,a21,a25:a24
addsub .L1X a20,b19,a17:a16
addsub .L2 b4,b7,b17:b16
addsub .L2X b4,a8,b1:b0
addsub2 .L1 a22,a21,a25:a24
addsub2 .L1X a20,b19,a17:a16
addsub2 .L2 b4,b7,b17:b16
addsub2 .L2X b4,a8,b1:b0
[!b2] addu .L1 a4,a5,a7:a6
addu .L1X a20,b19,a29:a28
[a0] addu .L2 b11,b10,b9:b8
addu .L2X b4,a7,b3:b2
addu .L1 a11,a9:a8,a7:a6
[b0] addu .L1X b20,a21:a20,a23:a22
[!a0] addu .L2 b23,b21:b20,b27:b26
addu .L2X a14,b17:b16,b19:b18
add2 .S1 a7,a6,a5
[!b0] add2 .S1X a10,b9,a8
add2 .S2 b18,b17,b16
[b1] add2 .S2X b22,a29,b21
add2 .L1 a7,a6,a5
[a1] add2 .L1X a10,b9,a8
add2 .L2 b18,b17,b16
[!a1] add2 .L2X b22,a29,b21
add2 .D1 a7,a6,a5
[!b1] add2 .D1X a10,b9,a8
add2 .D2 b18,b17,b16
[a2] add2 .D2X b22,a29,b21
[b2] add4 .L1 a30,a27,a24
add4 .L1X a23,b24,a25
add4 .L2 b24,b26,b27
[!a2] add4 .L2X b14,a17,b20
[!b2] and .L1 a1,a2,a3
and .L1X a10,b3,a11
[a0] and .L2 b19,b23,b29
and .L2X b7,a8,b9
and .L1 -16,a4,a5
[b0] and .L1X 15,b6,a7
[!a0] and .L2 -3,b20,b18
and .L2X 9,a20,b18
[!b0] and .S1 a1,a2,a3
and .S1X a10,b3,a11
[a1] and .S2 b19,b23,b29
and .S2X b7,a8,b9
and .S1 -16,a4,a5
[b1] and .S1X 15,b6,a7
[!a1] and .S2 12,b20,b18
and .S2X -8,a20,b18
[!b1] and .D1 a1,a2,a3
and .D1X a10,b3,a11
[a2] and .D2 b19,b23,b29
and .D2X b7,a8,b9
and .D1 -16,a4,a5
[b2] and .D1X 15,b6,a7
[!a2] and .D2 -14,b20,b18
and .D2X 13,a20,b18
andn .L1 a20,a18,a17
[!b2] andn .L1X a16,b15,a14
[a0] andn .L2 b23,b25,b27
andn .L2X b4,a5,b8
andn .S1 a20,a18,a17
[b0] andn .S1X a16,b15,a14
[!a0] andn .S2 b23,b25,b27
andn .S2X b4,a5,b8
andn .D1 a20,a18,a17
[!b0] andn .D1X a16,b15,a14
[a1] andn .D2 b23,b25,b27
andn .D2X b4,a5,b8
avg2 .M1 a8,a11,a14
[b1] avg2 .M1X a17,b20,a23
avg2 .M2 b26,b29,b0
[!a1] avg2 .M2X b3,a6,b9
avgu4 .M1 a8,a11,a14
[!b1] avgu4 .M1X a17,b20,a23
avgu4 .M2 b26,b29,b0
[a2] avgu4 .M2X b3,a6,b9
b .S2 b4
b .S2 b3
[b2] b .S2X a4
[!a2] call .S2 b4
call .S2X a4
callret .S2 b4
[!b2] callret .S2X a4
ret .S2 b4
[a0] ret .S2X a4
[b0] b .S2 irp
[!a0] b .S2 nrp
call .S2 irp
[a0] call .S2 nrp
[b0] callret .S2 irp
callret .S2 nrp
[b0] ret .S2 irp
ret .S2 nrp
bitc4 .M1 a4,a14
[!b0] bitc4 .M1X b5,a15
bitc4 .M2 b16,b26
[b1] bitc4 .M2X a1,b31
bitr .M1 a4,a14
[a1] bitr .M1X b5,a15
bitr .M2 b16,b26
[!a1] bitr .M2X a1,b31
bnop .S2 B5,0
[!b1] bnop .S2X A20,7
callnop .S2 B5,0
[a2] callnop .S2X A20,7
clr .S1 a5,0,31,a10
[b2] clr .S2 b10,31,0,b5
[!a2] clr .S1 a7,a14,a21
clr .S1X b9,a18,a27
clr .S2 b20,b18,b16
[!b2] clr .S2X a4,b16,b31
cmpeq .L1 a1,a3,a3
[a0] cmpeq .L1X a1,b4,a7
[b0] cmpeq .L2 b10,b11,b12
cmpeq .L2X b13,a14,b15
[!a0] cmpeq .L1 -16,a16,a17
cmpeq .L1X 15,b18,a19
cmpeq .L2 3,b20,b22
[!b0] cmpeq .L2X 4,a23,b25
cmpeq .L1 a4,a7:a6,a18
[a1] cmpeq .L1X b9,a11:a10,a20
cmpeq .L2 b21,b23:b22,b25
[b1] cmpeq .L2X a19,b25:b24,b27
[!a1] cmpeq .L1 -16,a15:a14,a22
[!b1] cmpeq .L2 15,b19:b18,b17
cmpeq2 .S1 a11,a9,a10
[a2] cmpeq2 .S1X a12,b14,a15
cmpeq2 .S2 b16,b20,b24
[b2] cmpeq2 .S2X b19,a23,b22
[!a2] cmpeq4 .S1 a20,a23,a26
cmpeq4 .S1X a31,b4,a15
[!b2] cmpeq4 .S2 b9,b26,b5
cmpeq4 .S2X b3,a5,b8
cmpeqdp .S1 a9:a8,a7:a6,a5
[a0] cmpeqdp .S1X a3:a2,b1:b0,a31
[b0] cmpeqdp .S2 b21:b20,b17:b16,b25
cmpeqdp .S2X b5:b4,a7:a6,b9
cmpeqsp .S1 a20,a21,a22
[!b0] cmpeqsp .S1X a23,b24,a25
[!a0] cmpeqsp .S2 b26,b27,b28
cmpeqsp .S2X b29,a30,b31
cmpgt .L1 a1,a3,a3
[a1] cmpgt .L1X a1,b4,a7
[b1] cmpgt .L2 b10,b11,b12
cmpgt .L2X b13,a14,b15
[!a1] cmpgt .L1 -16,a16,a17
cmpgt .L1X 15,b18,a19
cmpgt .L2 3,b20,b22
[!b1] cmpgt .L2X 4,a23,b25
cmpgt .L1 a4,a7:a6,a18
[a2] cmpgt .L1X b9,a11:a10,a20
cmpgt .L2 b21,b23:b22,b25
[b2] cmpgt .L2X a19,b25:b24,b27
[!a2] cmpgt .L1 -16,a15:a14,a22
[!b2] cmpgt .L2 15,b19:b18,b17
[a1] cmpgt .L1X b4,a1,a7
cmpgt .L2X a14,b13,b15
[!a1] cmpgt .L1 a16,-16,a17
cmpgt .L1X b18,15,a19
cmpgt .L2 b20,3,b22
[!b1] cmpgt .L2X a23,4,b25
cmpgt .L1 a7:a6,a4,a18
[a2] cmpgt .L1X a11:a10,b9,a20
cmpgt .L2 b23:b22,b21,b25
[b2] cmpgt .L2X b25:b24,a19,b27
[!a2] cmpgt .L1 a15:a14,-16,a22
[!b2] cmpgt .L2 b19:b18,15,b17
cmpgt2 .S1 a16,a15,a14
[a0] cmpgt2 .S1X a13,b12,a11
cmpgt2 .S2 b10,b9,b8
[b0] cmpgt2 .S2X b7,a6,b5
[!a0] cmpgtdp .S1 a3:a2,a1:a0,a31
cmpgtdp .S1X a29:a28,b27:b26,a25
cmpgtdp .S2 b23:b22,b21:b20,b19
[!b0] cmpgtdp .S2X b17:b16,a15:a14,b13
[a1] cmpgtsp .S1 a3,a1,a31
cmpgtsp .S1X a29,b27,a25
cmpgtsp .S2 b23,b21,b19
[b1] cmpgtsp .S2X b17,a15,b13
cmpgtu .L1 a1,a3,a3
[a1] cmpgtu .L1X a1,b4,a7
[b1] cmpgtu .L2 b10,b11,b12
cmpgtu .L2X b13,a14,b15
[!a1] cmpgtu .L1 0,a16,a17
cmpgtu .L1X 31,b18,a19
cmpgtu .L2 3,b20,b22
[!b1] cmpgtu .L2X 4,a23,b25
cmpgtu .L1 a4,a7:a6,a18
[a2] cmpgtu .L1X b9,a11:a10,a20
cmpgtu .L2 b21,b23:b22,b25
[b2] cmpgtu .L2X a19,b25:b24,b27
[!a2] cmpgtu .L1 0,a15:a14,a22
[!b2] cmpgtu .L2 31,b19:b18,b17
cmpgtu4 .S1 a25,a27,a23
[a0] cmpgtu4 .S1X a21,b20,a17
cmpgtu4 .S2 b11,b13,b17
[b0] cmpgtu4 .S2X b19,a23,b29
cmplt .L1 a1,a3,a3
[a1] cmplt .L1X a1,b4,a7
[b1] cmplt .L2 b10,b11,b12
cmplt .L2X b13,a14,b15
[!a1] cmplt .L1 -16,a16,a17
cmplt .L1X 15,b18,a19
cmplt .L2 3,b20,b22
[!b1] cmplt .L2X 4,a23,b25
cmplt .L1 a4,a7:a6,a18
[a2] cmplt .L1X b9,a11:a10,a20
cmplt .L2 b21,b23:b22,b25
[b2] cmplt .L2X a19,b25:b24,b27
[!a2] cmplt .L1 -16,a15:a14,a22
[!b2] cmplt .L2 15,b19:b18,b17
[a1] cmplt .L1X b4,a1,a7
cmplt .L2X a14,b13,b15
[!a1] cmplt .L1 a16,-16,a17
cmplt .L1X b18,15,a19
cmplt .L2 b20,3,b22
[!b1] cmplt .L2X a23,4,b25
cmplt .L1 a7:a6,a4,a18
[a2] cmplt .L1X a11:a10,b9,a20
cmplt .L2 b23:b22,b21,b25
[b2] cmplt .L2X b25:b24,a19,b27
[!a2] cmplt .L1 a15:a14,-16,a22
[!b2] cmplt .L2 b19:b18,15,b17
cmplt2 .S1 a16,a15,a14
[a0] cmplt2 .S1X b12,a13,a11
cmplt2 .S2 b10,b9,b8
[b0] cmplt2 .S2X a6,b7,b5
[!a0] cmpltdp .S1 a3:a2,a1:a0,a31
cmpltdp .S1X a29:a28,b27:b26,a25
cmpltdp .S2 b23:b22,b21:b20,b19
[!b0] cmpltdp .S2X b17:b16,a15:a14,b13
[a1] cmpltsp .S1 a3,a1,a31
cmpltsp .S1X a29,b27,a25
cmpltsp .S2 b23,b21,b19
[b1] cmpltsp .S2X b17,a15,b13
cmpltu .L1 a1,a3,a3
[a1] cmpltu .L1X a1,b4,a7
[b1] cmpltu .L2 b10,b11,b12
cmpltu .L2X b13,a14,b15
[!a1] cmpltu .L1 0,a16,a17
cmpltu .L1X 31,b18,a19
cmpltu .L2 3,b20,b22
[!b1] cmpltu .L2X 4,a23,b25
cmpltu .L1 a4,a7:a6,a18
[a2] cmpltu .L1X b9,a11:a10,a20
cmpltu .L2 b21,b23:b22,b25
[b2] cmpltu .L2X a19,b25:b24,b27
[!a2] cmpltu .L1 0,a15:a14,a22
[!b2] cmpltu .L2 31,b19:b18,b17
cmpltu4 .S1 a25,a27,a23
[a0] cmpltu4 .S1X b20,a21,a17
cmpltu4 .S2 b11,b13,b17
[b0] cmpltu4 .S2X a23,b19,b29
cmpy .M1 a1,a2,a5:a4
cmpy .M1X a4,b5,a7:a6
cmpy .M2 b8,b9,b11:b10
cmpy .M2X b11,a12,b13:b12
cmpyr .M1 a1,a2,a5
cmpyr .M1X a4,b5,a7
cmpyr .M2 b8,b9,b11
cmpyr .M2X b11,a12,b13
cmpyr1 .M1 a1,a2,a5
cmpyr1 .M1X a4,b5,a7
cmpyr1 .M2 b8,b9,b11
cmpyr1 .M2X b11,a12,b13
ddotp4 .M1 a1,a2,a5:a4
ddotp4 .M1X a4,b5,a7:a6
ddotp4 .M2 b8,b9,b11:b10
ddotp4 .M2X b11,a12,b13:b12
ddotph2 .M1 a1:a0,a2,a5:a4
ddotph2 .M1X a3:a2,b5,a7:a6
ddotph2 .M2 b7:b6,b9,b11:b10
ddotph2 .M2X b11:b10,a12,b13:b12
ddotph2r .M1 a1:a0,a2,a5
ddotph2r .M1X a3:a2,b5,a7
ddotph2r .M2 b7:b6,b9,b11
ddotph2r .M2X b11:b10,a12,b13
ddotpl2 .M1 a1:a0,a2,a5:a4
ddotpl2 .M1X a3:a2,b5,a7:a6
ddotpl2 .M2 b7:b6,b9,b11:b10
ddotpl2 .M2X b11:b10,a12,b13:b12
ddotpl2r .M1 a1:a0,a2,a5
ddotpl2r .M1X a3:a2,b5,a7
ddotpl2r .M2 b7:b6,b9,b11
ddotpl2r .M2X b11:b10,a12,b13
deal .M1 a8,a9
[!a0] deal .M1X b10,a11
[!b0] deal .M2 b12,b13
deal .M2X a14,b15
dint
[a1] dmv .S1 a4,a5,a7:a6
dmv .S1X a8,b9,a11:a10
dmv .S2 b12,b13,b15:b14
[b1] dmv .S2X b16,a17,b19:b18
dotp2 .M1 a20,a15,a10
[!a1] dotp2 .M1X a10,b5,a0
dotp2 .M2 b7,b14,b21
[!b1] dotp2 .M2X b23,a20,b17
dotp2 .M1 a20,a15,a11:a10
[a2] dotp2 .M1X a10,b5,a1:a0
[b2] dotp2 .M2 b7,b14,b21:b20
dotp2 .M2X b23,a20,b17:b16
dotpn2 .M1 a20,a15,a10
[!a2] dotpn2 .M1X a10,b5,a0
dotpn2 .M2 b7,b14,b21
[!b2] dotpn2 .M2X b23,a20,b17
dotpnrsu2 .M1 a20,a15,a10
[a0] dotpnrsu2 .M1X a10,b5,a0
dotpnrsu2 .M2 b7,b14,b21
[b0] dotpnrsu2 .M2X b23,a20,b17
[!a0] dotpnrus2 .M1 a20,a15,a10
dotpnrus2 .M1X b5,a10,a0
dotpnrus2 .M2 b7,b14,b21
[!b0] dotpnrus2 .M2X a20,b23,b17
dotprsu2 .M1 a20,a15,a10
[a1] dotprsu2 .M1X a10,b5,a0
dotprsu2 .M2 b7,b14,b21
[b1] dotprsu2 .M2X b23,a20,b17
[!a1] dotprus2 .M1 a20,a15,a10
dotprus2 .M1X b5,a10,a0
dotprus2 .M2 b7,b14,b21
[!b1] dotprus2 .M2X a20,b23,b17
dotpsu4 .M1 a20,a15,a10
[a2] dotpsu4 .M1X a10,b5,a0
dotpsu4 .M2 b7,b14,b21
[b2] dotpsu4 .M2X b23,a20,b17
dotpus4 .M1 a20,a15,a10
[!a2] dotpus4 .M1X b5,a10,a0
dotpus4 .M2 b7,b14,b21
[!b2] dotpus4 .M2X a20,b23,b17
dotpu4 .M1 a20,a15,a10
[a0] dotpu4 .M1X a10,b5,a0
dotpu4 .M2 b7,b14,b21
[b0] dotpu4 .M2X b23,a20,b17
dpack2 .L1 a30,a27,a25:a24
dpack2 .L1X a21,b18,a15:a14
dpack2 .L2 b12,b9,b7:b6
dpack2 .L2X b3,a0,b29:b28
dpackx2 .L1 a30,a27,a25:a24
dpackx2 .L1X a21,b18,a15:a14
dpackx2 .L2 b12,b9,b7:b6
dpackx2 .L2X b3,a0,b29:b28
.word 0x01900118
dpint .L1 a5:a4,a3
[!a0] dpint .L2 b5:b4,b3
.word 0x0197e118
.word 0x01900138
dpsp .L1 a5:a4,a3
[!b0] dpsp .L2 b5:b4,b3
.word 0x0197e138
.word 0x0190003a
[a1] dptrunc .L1 a5:a4,a3
dptrunc .L2 b5:b4,b3
.word 0x0197e03a
ext .S1 a5,0,31,a10
[b1] ext .S2 b10,31,0,b5
[!a1] ext .S1 a7,a14,a21
ext .S1X b9,a18,a27
ext .S2 b20,b18,b16
[!b1] ext .S2X a4,b16,b31
extu .S1 a5,0,31,a10
[a2] extu .S2 b10,31,0,b5
[b2] extu .S1 a7,a14,a21
extu .S1X b9,a18,a27
extu .S2 b20,b18,b16
[!a2] extu .S2X a4,b16,b31
gmpy .M1 a25,a16,a9
gmpy .M2 b5,b12,b13
[!b2] gmpy4 .M1 a2,a3,a5
gmpy4 .M1X a7,b11,a13
gmpy4 .M2 b17,b19,b23
[a0] gmpy4 .M2X b29,a31,b5
idle
intdp .L1 a1,a3:a2
[b0] intdp .L1X b5,a7:a6
[!a0] intdp .L2 b9,b11:b10
intdp .L2X a5,b13:b12
intdpu .L1 a1,a3:a2
[!b0] intdpu .L1X b5,a7:a6
[a1] intdpu .L2 b9,b11:b10
intdpu .L2X a5,b13:b12
intsp .L1 a1,a3
[b1] intsp .L1X b5,a7
[!a1] intsp .L2 b9,b11
intsp .L2X a5,b13
intspu .L1 a1,a3
[!b1] intspu .L1X b5,a7
[a2] intspu .L2 b9,b11
intspu .L2X a5,b13
ldb .D1T1 *a5,a7
[b2] ldb .D1T2 *++a9,b11
ldb .D2T1 *--b13,a15
[!a2] ldb .D2T2 *b17++,b19
ldb .D1T1 *a21--,a23
[!b2] ldb .D2T2 *-b25[31],b27
ldb .D1T1 *+a29[0],a31
ldb .D1T1 *-a0(2),a2
ldb .D1T1 *-a4[a5],a6
ldb .D1T1 *+a7[a8],a9
ldb .D1T1 *--a10[11],a12
ldb .D1T1 *++a13(14),a15
ldb .D1T1 *a16--(17),a18
ldb .D1T1 *a19++(20),a21
ldb .D1T1 *--a22[a23],a24
ldb .D1T1 *++a25[a26],a27
ldb .D1T1 *a28--[a29],a30
ldb .D1T1 *a31++[a0],a1
[a0] ldb .D2T1 *+b14(32767),a15
ldb .D2T2 *+b15[32767],b16
ldbu .D1T1 *a5,a7
[b2] ldbu .D1T2 *++a9,b11
ldbu .D2T1 *--b13,a15
[!a2] ldbu .D2T2 *b17++,b19
ldbu .D1T1 *a21--,a23
[!b2] ldbu .D2T2 *-b25[31],b27
ldbu .D1T1 *+a29[0],a31
ldbu .D1T1 *-a0(2),a2
ldbu .D1T1 *-a4[a5],a6
ldbu .D1T1 *+a7[a8],a9
ldbu .D1T1 *--a10[11],a12
ldbu .D1T1 *++a13(14),a15
ldbu .D1T1 *a16--(17),a18
ldbu .D1T1 *a19++(20),a21
ldbu .D1T1 *--a22[a23],a24
ldbu .D1T1 *++a25[a26],a27
ldbu .D1T1 *a28--[a29],a30
ldbu .D1T1 *a31++[a0],a1
[a0] ldbu .D2T1 *+b14(32767),a15
ldbu .D2T2 *+b15[32767],b16
lddw .D1T1 *a5,a7:a6
[b2] lddw .D1T2 *++a9,b11:b10
lddw .D2T1 *--b13,a15:a14
[!a2] lddw .D2T2 *b17++,b19:b18
lddw .D1T1 *a21--,a23:a22
[!b2] lddw .D2T2 *-b25[31],b27:b26
lddw .D1T1 *+a29[0],a31:a30
lddw .D1T1 *-a0(248),a3:a2
lddw .D1T1 *-a4[a5],a7:a6
lddw .D1T1 *+a7[a8],a9:a8
lddw .D1T1 *--a10[11],a13:a12
lddw .D1T1 *++a13(16),a15:a14
lddw .D1T1 *a16--(24),a19:a18
lddw .D1T1 *a19++(32),a21:a20
lddw .D1T1 *--a22[a23],a25:a24
lddw .D1T1 *++a25[a26],a27:a26
lddw .D1T1 *a28--[a29],a31:a30
lddw .D1T1 *a31++[a0],a1:a0
ldh .D1T1 *a5,a7
[b2] ldh .D1T2 *++a9,b11
ldh .D2T1 *--b13,a15
[!a2] ldh .D2T2 *b17++,b19
ldh .D1T1 *a21--,a23
[!b2] ldh .D2T2 *-b25[31],b27
ldh .D1T1 *+a29[0],a31
ldh .D1T1 *-a0(62),a2
ldh .D1T1 *-a4[a5],a6
ldh .D1T1 *+a7[a8],a9
ldh .D1T1 *--a10[11],a12
ldh .D1T1 *++a13(14),a15
ldh .D1T1 *a16--(18),a18
ldh .D1T1 *a19++(20),a21
ldh .D1T1 *--a22[a23],a24
ldh .D1T1 *++a25[a26],a27
ldh .D1T1 *a28--[a29],a30
ldh .D1T1 *a31++[a0],a1
[a0] ldh .D2T1 *+b14(65534),a15
ldh .D2T2 *+b15[32767],b16
ldhu .D1T1 *a5,a7
[b2] ldhu .D1T2 *++a9,b11
ldhu .D2T1 *--b13,a15
[!a2] ldhu .D2T2 *b17++,b19
ldhu .D1T1 *a21--,a23
[!b2] ldhu .D2T2 *-b25[31],b27
ldhu .D1T1 *+a29[0],a31
ldhu .D1T1 *-a0(62),a2
ldhu .D1T1 *-a4[a5],a6
ldhu .D1T1 *+a7[a8],a9
ldhu .D1T1 *--a10[11],a12
ldhu .D1T1 *++a13(14),a15
ldhu .D1T1 *a16--(18),a18
ldhu .D1T1 *a19++(20),a21
ldhu .D1T1 *--a22[a23],a24
ldhu .D1T1 *++a25[a26],a27
ldhu .D1T1 *a28--[a29],a30
ldhu .D1T1 *a31++[a0],a1
[a0] ldhu .D2T1 *+b14(65534),a15
ldhu .D2T2 *+b15[32767],b16
ldndw .D1T1 *a5,a7:a6
[b2] ldndw .D1T2 *++a9,b11:b10
ldndw .D2T1 *--b13,a15:a14
[!a2] ldndw .D2T2 *b17++,b19:b18
ldndw .D1T1 *a21--,a23:a22
[!b2] ldndw .D2T2 *-b25[31],b27:b26
ldndw .D1T1 *+a29[0],a31:a30
ldndw .D1T1 *-a0(31),a3:a2
ldndw .D1T1 *-a4[a5],a7:a6
ldndw .D1T1 *+a7(a8),a9:a8
ldndw .D1T1 *--a10[11],a13:a12
ldndw .D1T1 *++a13(16),a15:a14
ldndw .D1T1 *a16--(24),a19:a18
ldndw .D1T1 *a19++(30),a21:a20
ldndw .D1T1 *--a22[a23],a25:a24
ldndw .D1T1 *++a25(a26),a27:a26
ldndw .D1T1 *a28--[a29],a31:a30
ldndw .D1T1 *a31++(a0),a1:a0
ldnw .D1T1 *a5,a7
[b2] ldnw .D1T2 *++a9,b11
ldnw .D2T1 *--b13,a15
[!a2] ldnw .D2T2 *b17++,b19
ldnw .D1T1 *a21--,a23
[!b2] ldnw .D2T2 *-b25[31],b27
ldnw .D1T1 *+a29[0],a31
ldnw .D1T1 *-a0(124),a2
ldnw .D1T1 *-a4[a5],a6
ldnw .D1T1 *+a7[a8],a9
ldnw .D1T1 *--a10[11],a12
ldnw .D1T1 *++a13(16),a15
ldnw .D1T1 *a16--(20),a18
ldnw .D1T1 *a19++(24),a21
ldnw .D1T1 *--a22[a23],a24
ldnw .D1T1 *++a25[a26],a27
ldnw .D1T1 *a28--[a29],a30
ldnw .D1T1 *a31++[a0],a1
ldw .D1T1 *a5,a7
[b2] ldw .D1T2 *++a9,b11
ldw .D2T1 *--b13,a15
[!a2] ldw .D2T2 *b17++,b19
ldw .D1T1 *a21--,a23
[!b2] ldw .D2T2 *-b25[31],b27
ldw .D1T1 *+a29[0],a31
ldw .D1T1 *-a0(124),a2
ldw .D1T1 *-a4[a5],a6
ldw .D1T1 *+a7[a8],a9
ldw .D1T1 *--a10[11],a12
ldw .D1T1 *++a13(16),a15
ldw .D1T1 *a16--(20),a18
ldw .D1T1 *a19++(24),a21
ldw .D1T1 *--a22[a23],a24
ldw .D1T1 *++a25[a26],a27
ldw .D1T1 *a28--[a29],a30
ldw .D1T1 *a31++[a0],a1
[a0] ldw .D2T1 *+b14(131068),a15
ldw .D2T2 *+b15[32767],b16
lmbd .L1 a5,a8,a13
[b0] lmbd .L1X a21,b2,a23
[!a0] lmbd .L2 b25,b16,b9
lmbd .L2X b1,a2,b3
lmbd .L1 0,a8,a13
[!b0] lmbd .L1X 1,b2,a23
[a1] lmbd .L2 15,b16,b9
lmbd .L2X -16,a2,b3
max2 .L1 a1,a2,a3
[b1] max2 .L1X a4,b5,a6
[!a1] max2 .L2 b7,b8,b9
max2 .L2X b10,a11,b12
max2 .S1 a1,a2,a3
[!b1] max2 .S1X a4,b5,a6
max2 .S2 b7,b8,b9
[a2] max2 .S2X b10,a11,b12
[b2] maxu4 .L1 a13,a14,a15
maxu4 .L1X a16,b17,a18
maxu4 .L2 b19,b20,b21
[!a2] maxu4 .L2X b22,a23,b24
min2 .L1 a1,a2,a3
[!b2] min2 .L1X a4,b5,a6
[a0] min2 .L2 b7,b8,b9
min2 .L2X b10,a11,b12
min2 .S1 a1,a2,a3
[b0] min2 .S1X a4,b5,a6
min2 .S2 b7,b8,b9
[!a0] min2 .S2X b10,a11,b12
[!b0] minu4 .L1 a13,a14,a15
minu4 .L1X a16,b17,a18
minu4 .L2 b19,b20,b21
[a1] minu4 .L2X b22,a23,b24
mpy .M1 a25,a26,a27
[b1] mpy .M1X a28,b29,a30
[!a1] mpy .M2 b31,b0,b1
mpy .M2X b2,a3,b4
[!b1] mpy .M1 -16,a5,a6
mpy .M1X 15,b7,a8
mpy .M2 5,b9,b10
[a2] mpy .M2X -4,a11,b12
mpydp .M1 a1:a0,a3:a2,a5:a4
mpydp .M2X b1:b0,a1:a0,b1:b0
[b2] mpydp .M2 b7:b6,b9:b8,b11:b10
mpyh .M1 a0,a1,a2
[!a2] mpyh .M1X a3,b4,a5
[!b2] mpyh .M2 b6,b7,b8
mpyh .M2X b9,a10,b11
mpyhi .M1 a0,a1,a3:a2
[a0] mpyhi .M1X a3,b4,a5:a4
[b0] mpyhi .M2 b6,b7,b9:b8
mpyhi .M2X b9,a10,b11:b10
mpyhir .M1 a0,a1,a2
[!a0] mpyhir .M1X a3,b4,a5
[!b0] mpyhir .M2 b6,b7,b8
mpyhir .M2X b9,a10,b11
mpyhl .M1 a0,a1,a2
[a1] mpyhl .M1X a3,b4,a5
[b1] mpyhl .M2 b6,b7,b8
mpyhl .M2X b9,a10,b11
mpyhlu .M1 a0,a1,a2
[!a1] mpyhlu .M1X a3,b4,a5
[!b1] mpyhlu .M2 b6,b7,b8
mpyhlu .M2X b9,a10,b11
mpyhslu .M1 a0,a1,a2
[a2] mpyhslu .M1X a3,b4,a5
[b2] mpyhslu .M2 b6,b7,b8
mpyhslu .M2X b9,a10,b11
mpyhsu .M1 a0,a1,a2
[!a2] mpyhsu .M1X a3,b4,a5
[!b2] mpyhsu .M2 b6,b7,b8
mpyhsu .M2X b9,a10,b11
mpyhu .M1 a0,a1,a2
[a0] mpyhu .M1X a3,b4,a5
[b0] mpyhu .M2 b6,b7,b8
mpyhu .M2X b9,a10,b11
mpyhuls .M1 a0,a1,a2
[!a0] mpyhuls .M1X a3,b4,a5
[!b0] mpyhuls .M2 b6,b7,b8
mpyhuls .M2X b9,a10,b11
mpyhus .M1 a0,a1,a2
[a1] mpyhus .M1X a3,b4,a5
[b1] mpyhus .M2 b6,b7,b8
mpyhus .M2X b9,a10,b11
[!a1] mpyi .M1 a0,a1,a2
mpyi .M1X a3,b4,a5
[!b1] mpyi .M2 b6,b7,b8
mpyi .M2X b9,a10,b11
[a2] mpyi .M1 -16,a1,a2
mpyi .M1X 15,b4,a5
[b2] mpyi .M2 7,b7,b8
mpyi .M2X -6,a10,b11
mpyid .M1 a0,a1,a3:a2
[!a2] mpyid .M1X a3,b4,a5:a4
[!b2] mpyid .M2 b6,b7,b9:b8
mpyid .M2X b9,a10,b11:b10
mpyid .M1 -16,a1,a3:a2
[a0] mpyid .M1X 2,b4,a5:a4
mpyid .M2 15,b7,b9:b8
[b0] mpyid .M2X -7,a10,b11:b10
mpyih .M1 a0,a1,a3:a2
[!a0] mpyih .M1X b4,a3,a5:a4
[!b0] mpyih .M2 b6,b7,b9:b8
mpyih .M2X a10,b9,b11:b10
[a1] mpyihr .M1 a0,a1,a2
mpyihr .M1X b4,a3,a5
[b1] mpyihr .M2 b6,b7,b8
mpyihr .M2X a10,b9,b11
mpyil .M1 a0,a1,a3:a2
[!a1] mpyil .M1X b4,a3,a5:a4
mpyil .M2 b6,b7,b9:b8
[!b1] mpyil .M2X a10,b9,b11:b10
[a2] mpyilr .M1 a0,a1,a2
mpyilr .M1X b4,a3,a5
mpyilr .M2 b6,b7,b8
[b2] mpyilr .M2X a10,b9,b11
mpylh .M1 a0,a1,a2
[!a2] mpylh .M1X a3,b4,a5
[!b2] mpylh .M2 b6,b7,b8
mpylh .M2X b9,a10,b11
mpylhu .M1 a0,a1,a2
[a0] mpylhu .M1X a3,b4,a5
[b0] mpylhu .M2 b6,b7,b8
mpylhu .M2X b9,a10,b11
mpyli .M1 a0,a1,a3:a2
[!a0] mpyli .M1X a3,b4,a5:a4
[!b0] mpyli .M2 b6,b7,b9:b8
mpyli .M2X b9,a10,b11:b10
mpylir .M1 a0,a1,a2
[a1] mpylir .M1X a3,b4,a5
mpylir .M2 b6,b7,b8
[b1] mpylir .M2X b9,a10,b11
[!a1] mpylshu .M1 a0,a1,a2
mpylshu .M1X a3,b4,a5
mpylshu .M2 b6,b7,b8
[!b1] mpylshu .M2X b9,a10,b11
mpyluhs .M1 a0,a1,a2
[a2] mpyluhs .M1X a3,b4,a5
mpyluhs .M2 b6,b7,b8
[b2] mpyluhs .M2X b9,a10,b11
mpysp .M1 a0,a1,a2
[!a2] mpysp .M1X a3,b4,a5
mpysp .M2 b6,b7,b8
[!b2] mpysp .M2X b9,a10,b11
[a0] mpyspdp .M1 a12,a15:a14,a17:a16
mpyspdp .M1X a18,b19:b18,a21:a20
mpyspdp .M2 b22,b25:b24,b27:b26
[b0] mpyspdp .M2X b29,a31:a30,b1:b0
mpysp2dp .M1 a0,a1,a3:a2
[!a0] mpysp2dp .M1X a3,b4,a5:a4
[!b0] mpysp2dp .M2 b6,b7,b9:b8
mpysp2dp .M2X b9,a10,b11:b10
[a1] mpysu .M1 a0,a1,a2
mpysu .M1X a3,b4,a5
[b1] mpysu .M2 b6,b7,b8
mpysu .M2X b9,a10,b11
[!a1] mpysu .M1 -16,a1,a2
mpysu .M1X 15,b4,a5
mpysu .M2 3,b7,b8
[!b1] mpysu .M2X -9,a10,b11
mpysu4 .M1 a0,a1,a3:a2
[!a0] mpysu4 .M1X a3,b4,a5:a4
[!b0] mpysu4 .M2 b6,b7,b9:b8
mpysu4 .M2X b9,a10,b11:b10
[a1] mpyu .M1 a0,a1,a2
mpyu .M1X a3,b4,a5
mpyu .M2 b6,b7,b8
[b1] mpyu .M2X b9,a10,b11
mpyu4 .M1 a0,a1,a3:a2
[!a1] mpyu4 .M1X a3,b4,a5:a4
[!b1] mpyu4 .M2 b6,b7,b9:b8
mpyu4 .M2X b9,a10,b11:b10
[a2] mpyus .M1 a0,a1,a2
mpyus .M1X a3,b4,a5
mpyus .M2 b6,b7,b8
[b2] mpyus .M2X b9,a10,b11
mpyus4 .M1 a0,a1,a3:a2
[!a2] mpyus4 .M1X b4,a3,a5:a4
[!b2] mpyus4 .M2 b6,b7,b9:b8
mpyus4 .M2X a10,b9,b11:b10
mpy2 .M1 a0,a1,a3:a2
[a0] mpy2 .M1X a3,b4,a5:a4
[b0] mpy2 .M2 b6,b7,b9:b8
mpy2 .M2X b9,a10,b11:b10
mpy2ir .M1 a0,a1,a3:a2
mpy2ir .M1X a3,b4,a5:a4
mpy2ir .M2 b6,b7,b9:b8
mpy2ir .M2X b9,a10,b11:b10
[!a0] mpy32 .M1 a0,a1,a2
mpy32 .M1X a3,b4,a5
mpy32 .M2 b6,b7,b8
[!b0] mpy32 .M2X b9,a10,b11
mpy32 .M1 a0,a1,a3:a2
[a1] mpy32 .M1X a3,b4,a5:a4
[b1] mpy32 .M2 b6,b7,b9:b8
mpy32 .M2X b9,a10,b11:b10
mpy32su .M1 a0,a1,a3:a2
[!a1] mpy32su .M1X a3,b4,a5:a4
[!b1] mpy32su .M2 b6,b7,b9:b8
mpy32su .M2X b9,a10,b11:b10
mpy32u .M1 a0,a1,a3:a2
[a2] mpy32u .M1X a3,b4,a5:a4
[b2] mpy32u .M2 b6,b7,b9:b8
mpy32u .M2X b9,a10,b11:b10
mpy32us .M1 a0,a1,a3:a2
[!a2] mpy32us .M1X a3,b4,a5:a4
[!b2] mpy32us .M2 b6,b7,b9:b8
mpy32us .M2X b9,a10,b11:b10
[a0] mv .L1 a5,a7
mv .L1X b8,a13
[b0] mv .L2 b12,b15
mv .L2X a17,b19
[!a0] mv .S1 a5,a7
mv .S1X b8,a13
mv .S2 b12,b15
[!b0] mv .S2X a17,b19
[a1] mv .D1 a5,a7
mv .D1X b8,a13
[b1] mv .D2 b12,b15
mv .D2X a17,b19
[a0] mvc .S2 amr,b5
mvc .S2 b6,amr
[b0] mvc .S2X a7,amr
mvc .S2 csr,b8
mvc .S2 b8,csr
mvc .S2 dnum,b9
mvc .S2 b10,ecr
mvc .S2 efr,b11
mvc .S2 fadcr,b12
mvc .S2 b13,fadcr
mvc .S2 faucr,b14
mvc .S2 b15,faucr
mvc .S2 fmcr,b16
mvc .S2 b17,fmcr
mvc .S2 gfpgfr,b18
mvc .S2 b19,gfpgfr
mvc .S2 gplya,b20
mvc .S2 b21,gplya
mvc .S2 gplyb,b22
mvc .S2 b23,gplyb
mvc .S2 b24,icr
mvc .S2 ier,b25
mvc .S2 b26,ier
mvc .S2 ierr,b27
mvc .S2 b28,ierr
mvc .S2 ifr,b29
mvc .S2 ilc,b30
mvc .S2 b31,ilc
mvc .S2 irp,b0
mvc .S2 b1,irp
mvc .S2 b2,isr
mvc .S2 istp,b3
mvc .S2 b4,istp
mvc .S2 itsr,b5
mvc .S2 b6,itsr
mvc .S2 nrp,b7
mvc .S2 b8,nrp
mvc .S2 ntsr,b9
mvc .S2 b10,ntsr
mvc .S2 pce1,b11
mvc .S2 rep,b12
mvc .S2 b13,rep
mvc .S2 rilc,b14
mvc .S2 b15,rilc
mvc .S2 ssr,b16
mvc .S2 b17,ssr
mvc .S2 tsch,b18
mvc .S2 tscl,b19
mvc .S2 b20,tscl
mvc .S2 tsr,b21
mvc .S2 b22,tsr
.word 0x0001e3e2
.word 0x0005e3e2
.word 0x0181e3a2
.word 0x0201e3a2
.word 0x0301e3a2
.word 0x0101e3a2
.word 0x0281e3a2
.word 0x0381e3a2
.word 0x004203e2
mvd .M1 a4,a5
[!a0] mvd .M1X b6,a7
[!b0] mvd .M2 b8,b9
mvd .M2X a10,b11
[!b1] mvk .S1 -32768,a5
mvk .S2 32767,b4
mvk .L1 -16,a4
[a1] mvk .L2 15,b4
[b1] mvk .D1 6,a4
mvk .D2 -9,b12
mvkh .S1 0x12345678,a6
[a2] mvkh .S2 0xfedcba98,b7
[b2] mvklh .S1 0x12345678,a6
mvklh .S2 0xfedcba98,b7
mvkl .S1 0x12345678,a6
[!a2] mvkl .S2 0xfedcba98,b7
neg .S1 a5,a6
[a0] neg .S1X b7,a8
[b0] neg .S2 b9,b10
neg .S2X a11,b12
[!a0] neg .L1 a13,a14
neg .L1X b15,a16
neg .L2 b17,b18
[!b0] neg .L2X a19,b20
[b1] neg .L1 a21:a20,a23:a22
neg .L2 b25:b24,b27:b26
nop 1
nop 2
nop
nop 3
nop 4
nop 5
nop 6
nop 7
nop 8
nop 9
[!b2] norm .L1 a4,a5
norm .L1X b6,a7
norm .L2 b8,b9
[a0] norm .L2X a10,b11
norm .L1 a5:a4,a6
[b0] norm .L2 b9:b8,b10
not .L1 a1,a2
[b2] not .L1X b3,a4
[!a2] not .L2 b5,b6
not .L2X a7,b8
[!b2] not .S1 a1,a2
not .S1X b3,a4
not .S2 b5,b6
[a0] not .S2X a7,b8
[b0] not .D1 a1,a2
not .D1X b3,a4
not .D2 b5,b6
[!a0] not .D2X a7,b8
[!a0] or .D1 a1,a2,a3
or .D1X a4,b5,a6
or .D2 b7,b8,b9
[!b0] or .D2X b10,a11,b12
or .D1 -16,a2,a3
[a1] or .D1X 11,b5,a6
[b1] or .D2 15,b8,b9
or .D2X -13,a11,b12
[!a1] or .L1 a1,a2,a3
or .L1X a4,b5,a6
or .L2 b7,b8,b9
[!b1] or .L2X b10,a11,b12
or .L1 -16,a2,a3
[a2] or .L1X 11,b5,a6
[b2] or .L2 15,b8,b9
or .L2X -13,a11,b12
[!a2] or .S1 a1,a2,a3
or .S1X a4,b5,a6
or .S2 b7,b8,b9
[!b2] or .S2X b10,a11,b12
or .S1 -16,a2,a3
[a0] or .S1X 11,b5,a6
[b0] or .S2 15,b8,b9
or .S2X -13,a11,b12
[!a0] pack2 .L1 a1,a2,a3
pack2 .L1X a5,b8,a13
pack2 .L2 b21,b2,b23
[!b0] pack2 .L2X b25,a16,b9
[a1] pack2 .S1 a1,a2,a3
pack2 .S1X a5,b8,a13
pack2 .S2 b21,b2,b23
[b1] pack2 .S2X b25,a16,b9
[!a1] packh2 .L1 a1,a2,a3
packh2 .L1X a5,b8,a13
packh2 .L2 b21,b2,b23
[!b1] packh2 .L2X b25,a16,b9
[a2] packh2 .S1 a1,a2,a3
packh2 .S1X a5,b8,a13
packh2 .S2 b21,b2,b23
[b2] packh2 .S2X b25,a16,b9
[!a2] packh4 .L1 a1,a2,a3
packh4 .L1X a5,b8,a13
packh4 .L2 b21,b2,b23
[!b2] packh4 .L2X b25,a16,b9
[a0] packhl2 .L1 a1,a2,a3
packhl2 .L1X a5,b8,a13
packhl2 .L2 b21,b2,b23
[b0] packhl2 .L2X b25,a16,b9
packhl2 .S1 a1,a2,a3
[!a0] packhl2 .S1X a5,b8,a13
[!b0] packhl2 .S2 b21,b2,b23
packhl2 .S2X b25,a16,b9
[a1] packlh2 .L1 a1,a2,a3
packlh2 .L1X a5,b8,a13
packlh2 .L2 b21,b2,b23
[b1] packlh2 .L2X b25,a16,b9
packlh2 .S1 a1,a2,a3
[!a1] packlh2 .S1X a5,b8,a13
[!b1] packlh2 .S2 b21,b2,b23
packlh2 .S2X b25,a16,b9
[a2] packl4 .L1 a1,a2,a3
packl4 .L1X a5,b8,a13
packl4 .L2 b21,b2,b23
[b2] packl4 .L2X b25,a16,b9
.word 0x03100b60
rcpdp .S1 a5:a4,a7:a6
[!a2] rcpdp .S2 b9:b8,b11:b10
.word 0x0317eb60
rcpsp .S1 a0,a1
[!b2] rcpsp .S1X b2,a3
[a0] rcpsp .S2 b4,b5
rcpsp .S2X a6,b7
rint
[b0] rotl .M1 a0,a1,a2
rotl .M1X b3,a4,a5
rotl .M2 b6,b7,b8
[!a0] rotl .M2X a9,b10,b11
rotl .M1 a12,0,a13
[!b0] rotl .M1X b14,31,a15
[a1] rotl .M2 b16,17,b17
rotl .M2X a18,25,b19
rpack2 .S1 a1,a2,a3
rpack2 .S1X a4,b5,a6
rpack2 .S2 b7,b8,b9
rpack2 .S2X b10,a11,b12
.word 0x03100ba0
rsqrdp .S1 a5:a4,a7:a6
[b1] rsqrdp .S2 b9:b8,b11:b10
.word 0x0317eba0
rsqrsp .S1 a0,a1
[!a1] rsqrsp .S1X b2,a3
[!b1] rsqrsp .S2 b4,b5
rsqrsp .S2X a6,b7
sadd .L1 a1,a2,a3
[a2] sadd .L1X a4,b5,a6
[b2] sadd .L2 b7,b8,b9
sadd .L2X b10,a11,b12
[!a2] sadd .L1 a13,a15:a14,a17:a16
sadd .L1X b18,a21:a20,a23:a22
sadd .L2 b24,b27:b26,b29:b28
[!b2] sadd .L2X a30,b1:b0,b3:b2
sadd .L1 -16,a4,a5
[a0] sadd .L1X 15,b6,a7
[b0] sadd .L2 12,b8,b9
sadd .L2X -11,a10,b11
sadd .L1 -16,a13:a12,a15:a14
[!a0] sadd .L2 15,b21:b20,b23:b22
[!b0] sadd .S1 a28,a29,a30
sadd .S1X a31,b0,a1
sadd .S2 b2,b3,b4
[a1] sadd .S2X b5,a6,b7
sadd2 .S1 a1,a2,a3
[b1] sadd2 .S1X a4,b5,a6
[!a1] sadd2 .S2 b7,b8,b9
sadd2 .S2X b10,a11,b12
saddsub .L1 a0,a1,a3:a2
saddsub .L1X a4,b5,a7:a6
saddsub .L2 b8,b9,b11:b10
saddsub .L2X b12,a13,b15:b14
saddsub2 .L1 a0,a1,a3:a2
saddsub2 .L1X a4,b5,a7:a6
saddsub2 .L2 b8,b9,b11:b10
saddsub2 .L2X b12,a13,b15:b14
[!b1] saddsu2 .S1 a16,a17,a18
saddsu2 .S1X b19,a20,a21
saddsu2 .S2 b22,b23,b24
[a2] saddsu2 .S2X a25,b26,b27
saddus2 .S1 a28,a29,a30
[b2] saddus2 .S1X a31,b0,a1
[!a2] saddus2 .S2 b2,b3,b4
saddus2 .S2X b5,a6,b7
saddu4 .S1 a28,a29,a30
[!b2] saddu4 .S1X a31,b0,a1
[a0] saddu4 .S2 b2,b3,b4
saddu4 .S2X b5,a6,b7
[b0] sat .L1 a3:a2,a20
sat .L2 b7:b6,b15
set .S1 a1,31,0,a2
[!a0] set .S2 b3,0,31,b4
set .S1 a5,a6,a7
[!b0] set .S1X b8,a9,a10
[a1] set .S2 b11,b12,b13
set .S2X a14,b15,b16
shfl .M1 a17,a18
[b1] shfl .M1X b19,a20
[!a1] shfl .M2 b21,b22
shfl .M2X a23,b24
shfl3 .L1 a0,a1,a3:a2
shfl3 .L1X a4,b5,a7:a6
shfl3 .L2 b8,b9,b11:b10
shfl3 .L2X b12,a13,b15:b14
shl .S1 a1,a2,a3
[!b1] shl .S1X b4,a5,a6
[a2] shl .S2 b7,b8,b9
shl .S2X a10,b11,b12
[b2] shl .S1 a15:a14,a16,a19:a18
shl .S2 b21:b20,b22,b25:b24
[!a2] shl .S1 a26,a27,a29:a28
shl .S1X b30,a31,a1:a0
shl .S2 b2,b3,b5:b4
[!b2] shl .S2X a6,b7,b9:b8
shl .S1 a1,0,a3
[a0] shl .S1X b4,31,a6
[b0] shl .S2 b7,17,b9
shl .S2X a10,12,b12
[!a0] shl .S1 a15:a14,0,a19:a18
shl .S2 b21:b20,31,b25:b24
[!b0] shl .S1 a26,31,a29:a28
shl .S1X b30,0,a1:a0
shl .S2 b2,5,b5:b4
[a1] shl .S2X a6,9,b9:b8
shlmb .L1 a1,a2,a3
[b1] shlmb .L1X a4,b5,a6
[!a1] shlmb .L2 b7,b8,b9
shlmb .L2X b10,a11,b12
shlmb .S1 a1,a2,a3
[!b1] shlmb .S1X a4,b5,a6
[a2] shlmb .S2 b7,b8,b9
shlmb .S2X b10,a11,b12
shr .S1 a1,a2,a3
[b2] shr .S1X b4,a5,a6
[!a2] shr .S2 b7,b8,b9
shr .S2X a10,b11,b12
[!b2] shr .S1 a15:a14,a16,a19:a18
shr .S2 b21:b20,b22,b25:b24
shr .S1 a1,0,a3
[a0] shr .S1X b4,31,a6
[b0] shr .S2 b7,17,b9
shr .S2X a10,12,b12
[!a0] shr .S1 a15:a14,0,a19:a18
shr .S2 b21:b20,31,b25:b24
shr2 .S1 a1,a2,a3
[!b0] shr2 .S1X b4,a5,a6
[a1] shr2 .S2 b7,b8,b9
shr2 .S2X a10,b11,b12
shr2 .S1 a1,31,a3
[b1] shr2 .S1X b4,0,a6
[!a1] shr2 .S2 b7,5,b9
shr2 .S2X a10,25,b12
shrmb .S1 a1,a2,a3
[!b1] shrmb .S1X a4,b5,a6
[a2] shrmb .S2 b7,b8,b9
shrmb .S2X b10,a11,b12
shru .S1 a1,a2,a3
[b2] shru .S1X b4,a5,a6
[!a2] shru .S2 b7,b8,b9
shru .S2X a10,b11,b12
[!b2] shru .S1 a15:a14,a16,a19:a18
shru .S2 b21:b20,b22,b25:b24
shru .S1 a1,0,a3
[a0] shru .S1X b4,31,a6
[b0] shru .S2 b7,17,b9
shru .S2X a10,12,b12
[!a0] shru .S1 a15:a14,0,a19:a18
shru .S2 b21:b20,31,b25:b24
shru2 .S1 a1,a2,a3
[!b0] shru2 .S1X b4,a5,a6
[a1] shru2 .S2 b7,b8,b9
shru2 .S2X a10,b11,b12
shru2 .S1 a1,31,a3
[b1] shru2 .S1X b4,0,a6
[!a1] shru2 .S2 b7,5,b9
shru2 .S2X a10,25,b12
smpy .M1 a5,a6,a7
[!b1] smpy .M1X a8,b9,a10
[a2] smpy .M2 b11,b12,b13
smpy .M2X b14,a15,b16
smpyh .M1 a5,a6,a7
[b2] smpyh .M1X a8,b9,a10
[!a2] smpyh .M2 b11,b12,b13
smpyh .M2X b14,a15,b16
smpyhl .M1 a5,a6,a7
[!b2] smpyhl .M1X a8,b9,a10
[a0] smpyhl .M2 b11,b12,b13
smpyhl .M2X b14,a15,b16
smpylh .M1 a5,a6,a7
[b0] smpylh .M1X a8,b9,a10
[!a0] smpylh .M2 b11,b12,b13
smpylh .M2X b14,a15,b16
[!b0] smpy2 .M1 a17,a18,a21:a20
smpy2 .M1X a22,b23,a25:a24
smpy2 .M2 b26,b27,b29:b28
[a1] smpy2 .M2X b30,a31,b1:b0
smpy32 .M1 a17,a18,a21
smpy32 .M1X a22,b23,a25
smpy32 .M2 b26,b27,b29
smpy32 .M2X b30,a31,b1
spack2 .S1 a1,a2,a3
[b1] spack2 .S1X a4,b5,a6
[!a1] spack2 .S2 b7,b8,b9
spack2 .S2X b10,a11,b12
spacku4 .S1 a1,a2,a3
[!b1] spacku4 .S1X a4,b5,a6
[a2] spacku4 .S2 b7,b8,b9
spacku4 .S2X b10,a11,b12
[b2] spdp .S1 a13,a15:a14
spdp .S1X b15,a17:a16
spdp .S2 b18,b21:b20
[!a2] spdp .S2X a21,b23:b22
[!b2] spint .L1 a13,a15
spint .L1X b15,a17
spint .L2 b18,b21
[a0] spint .L2X a21,b23
[b0] sptrunc .L1 a13,a15
sptrunc .L1X b15,a17
sptrunc .L2 b18,b21
[!a0] sptrunc .L2X a21,b23
sshl .S1 a1,a2,a3
[!b0] sshl .S1X b4,a5,a6
[a1] sshl .S2 b7,b8,b9
sshl .S2X a10,b11,b12
sshl .S1 a13,31,a14
[b1] sshl .S1X b15,0,a16
[!a1] sshl .S2 b17,25,b18
sshl .S2X a19,7,b20
sshvl .M1 a1,a2,a3
[!b1] sshvl .M1X b4,a5,a6
[a2] sshvl .M2 b7,b8,b9
sshvl .M2X a10,b11,b12
sshvr .M1 a1,a2,a3
[!b1] sshvr .M1X b4,a5,a6
[a2] sshvr .M2 b7,b8,b9
sshvr .M2X a10,b11,b12
[b2] ssub .L1 a1,a2,a3
ssub .L1X a4,b5,a6
ssub .L2 b7,b8,b9
[!a2] ssub .L2X b10,a11,b12
ssub .L1X b13,a14,a15
[!b2] ssub .L2X a16,b17,b18
.word 0x000003f8
ssub .L1 -16,a19,a20
[a0] ssub .L1X 15,b21,a22
[b0] ssub .L2 7,b23,b24
ssub .L2X -9,a25,b26
ssub .L1 -16,a29:a28,a31:a30
[!a0] ssub .L2 15,b1:b0,b3:b2
ssub2 .L1 a1,a2,a3
[!b0] ssub2 .L1X a4,b5,a6
[a1] ssub2 .L2 b7,b8,b9
ssub2 .L2X b10,a11,b12
stb .D1T1 a7,*a5
[b2] stb .D1T2 b11,*++a9
stb .D2T1 a15,*--b13
[!a2] stb .D2T2 b19,*b17++
stb .D1T1 a23,*a21--
[!b2] stb .D2T2 b27,*-b25[31]
stb .D1T1 a31,*+a29[0]
stb .D1T1 a2,*-a0(2)
stb .D1T1 a6,*-a4[a5]
stb .D1T1 a9,*+a7[a8]
stb .D1T1 a12,*--a10[11]
stb .D1T1 a15,*++a13(14)
stb .D1T1 a18,*a16--(17)
stb .D1T1 a21,*a19++(20)
stb .D1T1 a24,*--a22[a23]
stb .D1T1 a27,*++a25[a26]
stb .D1T1 a30,*a28--[a29]
stb .D1T1 a1,*a31++[a0]
[a0] stb .D2T1 a15,*+b14(32767)
stb .D2T2 b16,*+b15[32767]
stdw .D1T1 a7:a6,*a5
[b2] stdw .D1T2 b11:b10,*++a9
stdw .D2T1 a15:a14,*--b13
[!a2] stdw .D2T2 b19:b18,*b17++
stdw .D1T1 a23:a22,*a21--
[!b2] stdw .D2T2 b27:b26,*-b25[31]
stdw .D1T1 a31:a30,*+a29[0]
stdw .D1T1 a3:a2,*-a0(248)
stdw .D1T1 a7:a6,*-a4[a5]
stdw .D1T1 a9:a8,*+a7[a8]
stdw .D1T1 a13:a12,*--a10[11]
stdw .D1T1 a15:a14,*++a13(16)
stdw .D1T1 a19:a18,*a16--(24)
stdw .D1T1 a21:a20,*a19++(32)
stdw .D1T1 a25:a24,*--a22[a23]
stdw .D1T1 a27:a26,*++a25[a26]
stdw .D1T1 a31:a30,*a28--[a29]
stdw .D1T1 a1:a0,*a31++[a0]
sth .D1T1 a7,*a5
[b2] sth .D1T2 b11,*++a9
sth .D2T1 a15,*--b13
[!a2] sth .D2T2 b19,*b17++
sth .D1T1 a23,*a21--
[!b2] sth .D2T2 b27,*-b25[31]
sth .D1T1 a31,*+a29[0]
sth .D1T1 a2,*-a0(62)
sth .D1T1 a6,*-a4[a5]
sth .D1T1 a9,*+a7[a8]
sth .D1T1 a12,*--a10[11]
sth .D1T1 a15,*++a13(14)
sth .D1T1 a18,*a16--(18)
sth .D1T1 a21,*a19++(20)
sth .D1T1 a24,*--a22[a23]
sth .D1T1 a27,*++a25[a26]
sth .D1T1 a30,*a28--[a29]
sth .D1T1 a1,*a31++[a0]
[a0] sth .D2T1 a15,*+b14(65534)
sth .D2T2 b16,*+b15[32767]
stndw .D1T1 a7:a6,*a5
[b2] stndw .D1T2 b11:b10,*++a9
stndw .D2T1 a15:a14,*--b13
[!a2] stndw .D2T2 b19:b18,*b17++
stndw .D1T1 a23:a22,*a21--
[!b2] stndw .D2T2 b27:b26,*-b25[31]
stndw .D1T1 a31:a30,*+a29[0]
stndw .D1T1 a3:a2,*-a0(31)
stndw .D1T1 a7:a6,*-a4[a5]
stndw .D1T1 a9:a8,*+a7(a8)
stndw .D1T1 a13:a12,*--a10[11]
stndw .D1T1 a15:a14,*++a13(16)
stndw .D1T1 a19:a18,*a16--(24)
stndw .D1T1 a21:a20,*a19++(30)
stndw .D1T1 a25:a24,*--a22[a23]
stndw .D1T1 a27:a26,*++a25(a26)
stndw .D1T1 a31:a30,*a28--[a29]
stndw .D1T1 a1:a0,*a31++(a0)
stnw .D1T1 a7,*a5
[b2] stnw .D1T2 b11,*++a9
stnw .D2T1 a15,*--b13
[!a2] stnw .D2T2 b19,*b17++
stnw .D1T1 a23,*a21--
[!b2] stnw .D2T2 b27,*-b25[31]
stnw .D1T1 a31,*+a29[0]
stnw .D1T1 a2,*-a0(124)
stnw .D1T1 a6,*-a4[a5]
stnw .D1T1 a9,*+a7[a8]
stnw .D1T1 a12,*--a10[11]
stnw .D1T1 a15,*++a13(16)
stnw .D1T1 a18,*a16--(20)
stnw .D1T1 a21,*a19++(24)
stnw .D1T1 a24,*--a22[a23]
stnw .D1T1 a27,*++a25[a26]
stnw .D1T1 a30,*a28--[a29]
stnw .D1T1 a1,*a31++[a0]
stw .D1T1 a7,*a5
[b2] stw .D1T2 b11,*++a9
stw .D2T1 a15,*--b13
[!a2] stw .D2T2 b19,*b17++
stw .D1T1 a23,*a21--
[!b2] stw .D2T2 b27,*-b25[31]
stw .D1T1 a31,*+a29[0]
stw .D1T1 a2,*-a0(124)
stw .D1T1 a6,*-a4[a5]
stw .D1T1 a9,*+a7[a8]
stw .D1T1 a12,*--a10[11]
stw .D1T1 a15,*++a13(16)
stw .D1T1 a18,*a16--(20)
stw .D1T1 a21,*a19++(24)
stw .D1T1 a24,*--a22[a23]
stw .D1T1 a27,*++a25[a26]
stw .D1T1 a30,*a28--[a29]
stw .D1T1 a1,*a31++[a0]
[a0] stw .D2T1 a15,*+b14(131068)
stw .D2T2 b16,*+b15[32767]
sub .L1 a1,a2,a3
[b0] sub .L1X a4,b5,a6
[!a0] sub .L2 b7,b8,b9
sub .L2X b10,a11,b12
[!b0] sub .L1X b13,a14,a15
sub .L2X a16,b17,b18
.word 0x07b9a2f8
[a1] sub .L1 a19,a20,a23:a22
sub .L1X a24,b25,a27:a26
sub .L2 b28,b29,b31:b30
[b1] sub .L2X b0,a1,b3:b2
sub .L1X b4,a5,a7:a6
[!a1] sub .L2X a8,b9,b11:b10
.word 0x031486f8
sub .L1 -16,a12,a13
[!b1] sub .L1X 15,b14,a15
[a2] sub .L2 7,b16,b17
sub .L2X -9,a18,b19
sub .L1 -16,a21:a20,a23:a22
[b2] sub .L2 15,b25:b24,b27:b26
sub .S1 a1,a2,a3
[!a2] sub .S1X a4,b5,a6
[!b2] sub .S2 b7,b8,b9
sub .S2X b10,a11,b12
[a0] sub .S1X b13,a14,a15
sub .S2X a16,b17,b18
.word 0x07b5cd70
[b0] sub .S1 -16,a19,a20
sub .S1X 15,b21,a22
sub .S2 13,b23,b24
[!a0] sub .S2X -11,a25,b26
sub .D1 a27,a28,a29
[!b0] sub .D2 b30,b31,b0
[a1] sub .D1 a1,0,a2
sub .D2 b3,31,b4
sub .D1X a5,b6,a7
[b1] sub .D2X b8,a9,b10
.word 0x0398ab30
sub .L1 a5,16,a6
[a0] sub .L1X b11,-15,a30
sub .L2 b9,11,b10
sub .L2X a5,-14,b7
sub .L1 a3:a2,-5,a7:a6
[b0] sub .L2 b29:b28,7,b29:b28
sub .S1 a4,16,a11
sub .S1X b9,-13,a23
[!b0] sub .S2 b25,-15,b11
sub .S2X a1,4,b2
subab .D1 a1,a2,a3
[!a1] subab .D2 b4,b5,b6
subab .D1 a7,0,a8
[!b1] subab .D2 b9,31,b10
subabs4 .L1 a1,a2,a3
[a2] subabs4 .L1X a4,b5,a6
[b2] subabs4 .L2 b7,b8,b9
subabs4 .L2X b10,a11,b12
subah .D1 a1,a2,a3
[!a2] subah .D2 b4,b5,b6
[!b2] subah .D1 a7,0,a8
subah .D2 b9,31,b10
subaw .D1 a1,a2,a3
[a0] subaw .D2 b4,b5,b6
[b0] subaw .D1 a7,0,a8
subaw .D2 b9,31,b10
[!a0] subc .L1 a3,a4,a5
subc .L1X a6,b7,a8
subc .L2 b9,b10,b11
[!b0] subc .L2X b12,a13,b14
subdp .L1 a3:a2,a5:a4,a7:a6
[a1] subdp .L1X a9:a8,b11:b10,a13:a12
[b1] subdp .L2 b15:b14,b17:b16,b19:b18
subdp .L2X b21:b20,a23:a22,b25:b24
[!a1] subdp .L1X b27:b26,a29:a28,a31:a30
subdp .L2X a1:a0,b3:b2,b5:b4
.word 0x0f7343b8
subdp .S1 a3:a2,a5:a4,a7:a6
[a1] subdp .S1X a9:a8,b11:b10,a13:a12
[b1] subdp .S2 b15:b14,b17:b16,b19:b18
subdp .S2X b21:b20,a23:a22,b25:b24
[!a1] subdp .S1X b27:b26,a29:a28,a31:a30
subdp .S2X a1:a0,b3:b2,b5:b4
.word 0x0f6b8ef8
subsp .L1 a3,a5,a7
[a1] subsp .L1X a9,b11,a13
[b1] subsp .L2 b15,b17,b19
subsp .L2X b21,a23,b25
[!a1] subsp .L1X b27,a29,a31
subsp .L2X a1,b3,b5
.word 0x0ff762b8
subsp .S1 a3,a5,a7
[!b1] subsp .S1X a9,b11,a13
[a2] subsp .S2 b15,b17,b19
subsp .S2X b21,a23,b25
[b2] subsp .S1X b27,a29,a31
subsp .S2X a1,b3,b5
.word 0x0fefaeb8
subu .L1 a2,a3,a5:a4
[!a2] subu .L1X a6,b7,a9:a8
[!b2] subu .L2 b10,b11,b13:b12
subu .L2X b14,a15,b17:b16
[a0] subu .L1X b18,a19,a21:a20
subu .L2X a22,b23,b25:b24
.word 0x0a4e47f8
sub2 .L1 a1,a2,a3
[b0] sub2 .L1X a4,b5,a6
[!a0] sub2 .L2 b7,b8,b9
sub2 .L2X b10,a11,b12
sub2 .S1 a1,a2,a3
[!b0] sub2 .S1X a4,b5,a6
[a1] sub2 .S2 b7,b8,b9
sub2 .S2X b10,a11,b12
sub2 .D1 a1,a2,a3
[b1] sub2 .D1X a4,b5,a6
[!a1] sub2 .D2 b7,b8,b9
sub2 .D2X b10,a11,b12
sub4 .L1 a1,a2,a3
[!b1] sub4 .L1X a4,b5,a6
[a2] sub4 .L2 b7,b8,b9
sub4 .L2X b10,a11,b12
swap2 .L1 a3,a7
[b2] swap2 .L2 b9,b11
[!a2] swap2 .S1 a13,a15
swap2 .S2 b23,b29
[!b2] swap4 .L1 a1,a2
swap4 .L1X b3,a4
swap4 .L2 b5,b6
[a0] swap4 .L2X a7,b8
swe
swenr
unpkhu4 .L1 a1,a2
[b0] unpkhu4 .L1X b3,a4
[!a0] unpkhu4 .L2 b5,b6
unpkhu4 .L2X a7,b8
unpkhu4 .S1 a1,a2
[!b0] unpkhu4 .S1X b3,a4
[a1] unpkhu4 .S2 b5,b6
unpkhu4 .S2X a7,b8
unpklu4 .L1 a1,a2
[b1] unpklu4 .L1X b3,a4
[!a1] unpklu4 .L2 b5,b6
unpklu4 .L2X a7,b8
unpklu4 .S1 a1,a2
[!b1] unpklu4 .S1X b3,a4
[a2] unpklu4 .S2 b5,b6
unpklu4 .S2X a7,b8
xor .L1 a1,a2,a3
[b2] xor .L1X a4,b5,a6
[!a2] xor .L2 b7,b8,b9
xor .L2X b10,a11,b12
[!b2] xor .L1 -16,a13,a14
xor .L1X 15,b15,a16
xor .L2 3,b17,b18
[a0] xor .L2X -12,a19,b20
xor .S1 a1,a2,a3
[b0] xor .S1X a4,b5,a6
[!a0] xor .S2 b7,b8,b9
xor .S2X b10,a11,b12
[!b0] xor .S1 -16,a13,a14
xor .S1X 15,b15,a16
xor .S2 3,b17,b18
[a1] xor .S2X -12,a19,b20
xor .D1 a1,a2,a3
[b0] xor .D1X a4,b5,a6
[!a0] xor .D2 b7,b8,b9
xor .D2X b10,a11,b12
[!b0] xor .D1 -16,a13,a14
xor .D1X 15,b15,a16
xor .D2 3,b17,b18
[a1] xor .D2X -12,a19,b20
xormpy .M1 a1,a2,a3
xormpy .M1X a4,b5,a6
xormpy .M2 b7,b8,b9
xormpy .M2X b10,a11,b12
xpnd2 .M1 a13,a14
[b1] xpnd2 .M1X b15,a16
[!a1] xpnd2 .M2 b17,b18
xpnd2 .M2X a19,b20
xpnd4 .M1 a13,a14
[!b1] xpnd4 .M1X b15,a16
[a2] xpnd4 .M2 b17,b18
xpnd4 .M2X a19,b20
zero .L1 a1
[b2] zero .L2 b2
[!a2] zero .L1 a5:a4
zero .L2 b7:b6
zero .D1 a8
[!b2] zero .D2 b9
[a0] zero .S1 a10
zero .S2 b11
|
tactcomplabs/xbgas-binutils-gdb
| 2,380
|
gas/testsuite/gas/tic6x/insns16-ddec.s
|
; Test C64x+ ddec compact instruction format
.text
ddec:
nop
.align 16
nop
.align 16
.short 0x4c04
.short 0x5c04
.short 0x4e04
.short 0x4c0c
.short 0x4c05
.short 0x5c05
.short 0x4e05
.short 0x4c0d
.short 0x5c05
.short 0x4c05
.short 0x5e0d
.short 0x6e0d
.short 0x7e1d
.short 0x6e1d
.word 0xefe00000
.short 0x4c04
.short 0x5c04
.short 0x4e04
.short 0x4c0c
.short 0x4c05
.short 0x5c05
.short 0x4e05
.short 0x4c0d
.short 0x5c05
.short 0x4e05
.short 0x5e0d
.short 0x6e0d
.short 0x7e1d
.short 0x6e1d
.word 0xefe8c000
.short 0x4c04
.short 0x5c04
.short 0x4e04
.short 0x4c0c
.short 0x4c05
.short 0x5c05
.short 0x4e05
.short 0x4c0d
.short 0x5c05
.short 0x4e05
.short 0x5e0d
.short 0x6e0d
.short 0x7e1d
.short 0x6e1d
.word 0xefe9c000
.short 0x4c04
.short 0x5c04
.short 0x4e04
.short 0x4c0c
.short 0x4c05
.short 0x5c05
.short 0x4e05
.short 0x4c0d
.short 0x5c05
.short 0x4e05
.short 0x5e0d
.short 0x6e0d
.short 0x7e1d
.short 0x6e1d
.word 0xefeac000
.short 0x4e04
.short 0x5e04
.short 0x4e04
.short 0x4c0c
.short 0x4c05
.short 0x5c05
.short 0x4e05
.short 0x4c0d
.short 0x5c05
.short 0x4e05
.short 0x5e0d
.short 0x6e0d
.short 0x7e1d
.short 0x6e1d
.word 0xefebc000
.short 0x4c04
.short 0x5c04
.short 0x4e04
.short 0x4c0c
.short 0x4c05
.short 0x5c05
.short 0x4e05
.short 0x4c0d
.short 0x5c05
.short 0x4e05
.short 0x5e0d
.short 0x6e0d
.short 0x7e1d
.short 0x6e1d
.word 0xefecc000
.short 0x4c04
.short 0x5c04
.short 0x4e04
.short 0x4c0c
.short 0x4c05
.short 0x5c05
.short 0x4e05
.short 0x4c0d
.short 0x5c05
.short 0x4e05
.short 0x5e0d
.short 0x6e0d
.short 0x7e1d
.short 0x6e1d
.word 0xefedc000
.short 0x4c04
.short 0x5c04
.short 0x4e04
.short 0x4c0c
.short 0x4c05
.short 0x5c05
.short 0x4e05
.short 0x4c0d
.short 0x5c05
.short 0x4e05
.short 0x5e0d
.short 0x6e0d
.short 0x7e1d
.short 0x6e1d
.word 0xefeec000
.short 0x4c04
.short 0x5c04
.short 0x4e04
.short 0x4c0c
.short 0x4c05
.short 0x5c05
.short 0x4e05
.short 0x4c0d
.short 0x5c05
.short 0x4e05
.short 0x5e0d
.short 0x6e0d
.short 0x7e1d
.short 0x6e1d
.word 0xefefc000
.short 0x4c14
.short 0x5c14
.short 0x4e14
.short 0x4c1c
.short 0x4c15
.short 0x5c15
.short 0x4e15
.short 0x4c1d
.short 0x5c15
.short 0x4e15
.short 0x5e1d
.short 0x6e1d
.short 0x7e1d
.short 0x6e1d
.word 0xefefc000
|
tactcomplabs/xbgas-binutils-gdb
| 3,732
|
gas/testsuite/gas/tic6x/reloc-bad-6.s
|
# Test relocation overflow and insufficiently divisible values for
# PC-relative operands.
.text
.nocmp
f7_0:
nop
nop
nop
nop
nop
nop
nop
f7_28:
nop
f7_32:
.space 256
f7_288:
addkpc .S2 f7_32,b1,0
addkpc .S2 f7_28,b1,0
addkpc .S2 f7_32,b1,0
addkpc .S2 f7_0,b1,0
addkpc .S2 f7_544,b1,0
addkpc .S2 f7_540,b1,0
addkpc .S2 f7_288+1,b1,0
nop
f7_320:
.space 220
f7_540:
nop
f7_544:
nop
nop
nop
nop
nop
nop
nop
nop
f10_0:
nop
nop
nop
nop
nop
nop
nop
f10_28:
nop
f10_32:
.space 2048
f10_2080:
bdec .S1 f10_32,a1
bdec .S1 f10_28,a1
bdec .S1 f10_32,a1
bdec .S1 f10_0,a1
bdec .S1 f10_4128,a1
bdec .S1 f10_4124,a1
bdec .S1 f10_2080+1,a1
nop
f10_2112:
.space 2012
f10_4124:
nop
f10_4128:
nop
nop
nop
nop
nop
nop
nop
nop
g10_0:
nop
nop
nop
nop
nop
nop
nop
g10_28:
nop
g10_32:
.space 2048
g10_2080:
bpos .S1 g10_32,a1
bpos .S1 g10_28,a1
bpos .S1 g10_32,a1
bpos .S1 g10_0,a1
bpos .S1 g10_4128,a1
bpos .S1 g10_4124,a1
bpos .S1 g10_2080+1,a1
nop
g10_2112:
.space 2012
g10_4124:
nop
g10_4128:
nop
nop
nop
nop
nop
nop
nop
nop
f12_0:
nop
nop
nop
nop
nop
nop
nop
f12_28:
nop
f12_32:
.space 8192
f12_8224:
bnop f12_32,2
bnop f12_28,2
bnop f12_32,2
bnop f12_0,2
bnop f12_16416,2
bnop f12_16412,2
bnop f12_8224+1,2
nop
f12_8256:
.space 8156
f12_16412:
nop
f12_16416:
nop
nop
nop
nop
nop
nop
nop
nop
g12_0:
nop
nop
nop
nop
nop
nop
nop
g12_28:
nop
g12_32:
.space 8192
g12_8224:
callnop g12_32,2
callnop g12_28,2
callnop g12_32,2
callnop g12_0,2
callnop g12_16416,2
callnop g12_16412,2
callnop g12_8224+1,2
nop
g12_8256:
.space 8156
g12_16412:
nop
g12_16416:
nop
nop
nop
nop
nop
nop
nop
nop
f21_0:
nop
nop
nop
nop
nop
nop
nop
f21_28:
nop
f21_32:
.space 4194304
f21_4194336:
b .S1 f21_32
b .S1 f21_28
b .S1 f21_32
b .S1 f21_0
b .S1 f21_8388640
b .S1 f21_8388636
b .S1 f21_4194336+1
nop
f21_4194368:
.space 4194268
f21_8388636:
nop
f21_8388640:
nop
nop
nop
nop
nop
nop
nop
nop
g21_0:
nop
nop
nop
nop
nop
nop
nop
g21_28:
nop
g21_32:
.space 4194304
g21_4194336:
call .S1 g21_32
call .S1 g21_28
call .S1 g21_32
call .S1 g21_0
call .S1 g21_8388640
call .S1 g21_8388636
call .S1 g21_4194336+1
nop
g21_4194368:
.space 4194268
g21_8388636:
nop
g21_8388640:
nop
nop
nop
nop
nop
nop
nop
nop
h21_0:
nop
nop
nop
nop
nop
nop
nop
h21_28:
nop
h21_32:
.space 4194304
h21_4194336:
callp .S2 h21_32,b3
callp .S2 h21_28,b3
callp .S2 h21_32,b3
callp .S2 h21_0,b3
callp .S2 h21_8388640,b3
callp .S2 h21_8388636,b3
callp .S2 h21_4194336+1,b3
nop
h21_4194368:
.space 4194268
h21_8388636:
nop
h21_8388640:
nop
nop
nop
nop
nop
nop
nop
nop
i21_0:
nop
nop
nop
nop
nop
nop
nop
i21_28:
nop
i21_32:
.space 4194304
i21_4194336:
callret .S1 i21_32
callret .S1 i21_28
callret .S1 i21_32
callret .S1 i21_0
callret .S1 i21_8388640
callret .S1 i21_8388636
callret .S1 i21_4194336+1
nop
i21_4194368:
.space 4194268
i21_8388636:
nop
i21_8388640:
nop
nop
nop
nop
nop
nop
nop
nop
j21_0:
nop
nop
nop
nop
nop
nop
nop
j21_28:
nop
j21_32:
.space 4194304
j21_4194336:
ret .S1 j21_32
ret .S1 j21_28
ret .S1 j21_32
ret .S1 j21_0
ret .S1 j21_8388640
ret .S1 j21_8388636
ret .S1 j21_4194336+1
nop
j21_4194368:
.space 4194268
j21_8388636:
nop
j21_8388640:
nop
nop
nop
nop
nop
nop
nop
nop
k21_0:
nop
nop
nop
nop
nop
nop
nop
k21_28:
nop
k21_32:
.space 4194304
k21_4194336:
retp .S1 k21_32,a3
retp .S1 k21_28,a3
retp .S1 k21_32,a3
retp .S1 k21_0,a3
retp .S1 k21_8388640,a3
retp .S1 k21_8388636,a3
retp .S1 k21_4194336+1,a3
nop
k21_4194368:
.space 4194268
k21_8388636:
nop
k21_8388640:
nop
nop
nop
nop
nop
nop
nop
nop
|
tactcomplabs/xbgas-binutils-gdb
| 1,099
|
gas/testsuite/gas/tic6x/insns16-m-unit.s
|
; Test C64x+ M-unit compact instruction formats
.text
nop
.align 16
nop
.align 16
m3_op_00:
.short 0x231e
.short 0x469f
.short 0x799e
.short 0x9c1f
.short 0xa71e
.short 0xca9f
.short 0xfd9e
m3_op_01:
.short 0x213e
.short 0x46bf
.short 0x7bbe
.short 0x9c3f
.short 0xa53e
.short 0xcabf
.short 0xffbe
.word 0xefe00000
m3_op_10:
.short 0x225e
.short 0x47df
.short 0x78de
.short 0x9d5f
.short 0xa6de
.short 0xcbdf
.short 0xfc5e
m3_op_11:
.short 0x207e
.short 0x45ff
.short 0x7afe
.short 0x9f7f
.short 0xa47e
.short 0xc9ff
.short 0xfefe
.word 0xefe80000
m3_op_00_sat:
.short 0x231e
.short 0x469f
.short 0x799e
.short 0x9c1f
.short 0xa71e
.short 0xca9f
.short 0xfd9e
m3_op_01_sat:
.short 0x213e
.short 0x46bf
.short 0x7bbe
.short 0x9c3f
.short 0xa53e
.short 0xcabf
.short 0xffbe
.word 0xefe84000
m3_op_10_sat:
.short 0x225e
.short 0x47df
.short 0x78de
.short 0x9d5f
.short 0xa6de
.short 0xcbdf
.short 0xfc5e
m3_op_11_sat:
.short 0x207e
.short 0x45ff
.short 0x7afe
.short 0x9f7f
.short 0xa47e
.short 0xc9ff
.short 0xfefe
.word 0xefe04000
|
tactcomplabs/xbgas-binutils-gdb
| 2,751
|
gas/testsuite/gas/tic6x/insns16-l-unit.s
|
; Test C64x+ L-unit compact instruction formats
.text
nop
.align 16
nop
.align 16
l3_nosat_l:
.short 0x0010
.short 0x2120
.short 0x4230
.short 0x6340
.short 0x8050
.short 0xa160
.short 0xc270
.short 0xeb80
.short 0x0890
.short 0x29a0
.short 0x4ab0
.short 0x6bc0
.short 0x88d0
.short 0xa9e0
.word 0xefe00000
l3_sat_h:
.short 0xc2f0
.short 0xe300
.short 0x0010
.short 0x2120
.short 0x4230
.short 0x6340
.short 0x8050
.short 0xa960
.short 0xca70
.short 0xeb80
.short 0x0890
.short 0x29a0
.short 0x4ab0
.short 0x6bc0
.word 0xefe84000
l3i:
.short 0x0410
.short 0x3520
.short 0x4630
.short 0x7740
.short 0x8550
.short 0xb660
.short 0xc770
.short 0x1c80
.short 0x2d90
.short 0x5ea0
.short 0x6fb0
.short 0x9cc0
.short 0xadd0
.short 0xdee0
.word 0xefe00000
l2c_op_000:
.short 0x0408
.short 0x2409
.short 0x4418
.short 0x6419
.short 0x9408
.short 0xb409
.short 0xd418
l2c_op_001:
.short 0xf439
.short 0x2428
.short 0x4429
.short 0x6438
.short 0x8439
.short 0xb428
.short 0xd429
.word 0xefe00000
l2c_op_010:
.short 0x0458
.short 0x2449
.short 0x4448
.short 0x6459
.short 0x9458
.short 0xb449
.short 0xd448
l2c_op_011:
.short 0xf479
.short 0x2468
.short 0x4469
.short 0x6478
.short 0x8479
.short 0xb468
.short 0xd469
.word 0xefe80000
l2c_op_100:
.short 0x0c18
.short 0x2c09
.short 0x4c08
.short 0x6c19
.short 0x9c18
.short 0xbc09
.short 0xdc08
l2c_op_101:
.short 0xfc39
.short 0x2c28
.short 0x4c29
.short 0x6c38
.short 0x8c39
.short 0xbc28
.short 0xdc29
.word 0xefe00000
l2c_op_110:
.short 0x0c58
.short 0x2c49
.short 0x4c48
.short 0x6c59
.short 0x9c58
.short 0xbc49
.short 0xdc48
l2c_op_111:
.short 0xfc79
.short 0x2c68
.short 0x4c69
.short 0x6c78
.short 0x8c79
.short 0xbc68
.short 0xdc69
.word 0xefe80000
lx5:
.short 0x0426
.short 0x2527
.short 0x46a6
.short 0x67a7
.short 0x8626
.short 0xa527
.short 0xc4a6
.short 0xf5a7
.short 0x1626
.short 0x3727
.short 0x56a6
.short 0x75a7
.short 0x9426
.short 0xb527
.word 0xefe00000
lx3c:
.short 0x0026
.short 0x2127
.short 0x42a6
.short 0x63a7
.short 0x8226
.short 0xa127
.short 0xc0a6
.short 0xe1a7
.short 0x0226
.short 0x2327
.short 0x42a6
.short 0x61a7
.short 0x8026
.short 0xa127
.word 0xefe00000
lx1c:
.short 0x1026
.short 0x3127
.short 0x52a6
.short 0x73a7
.short 0x9226
.short 0xb127
.short 0xd0a6
.short 0xf1a7
.short 0x1226
.short 0x3327
.short 0x52a6
.short 0x71a7
.short 0x9026
.short 0xb127
.word 0xefe00000
lx1:
.short 0x5b66
.short 0x5a67
.short 0x59e6
.short 0x58e7
.short 0x5866
.short 0x5967
.short 0x5ae6
.short 0x7be7
.short 0x7b66
.short 0x7a67
.short 0x79e6
.short 0x78e7
.short 0x7866
.short 0x7967
.word 0xefe00000
|
tactcomplabs/xbgas-binutils-gdb
| 28,021
|
gas/testsuite/gas/tic6x/insns-bad-1.s
|
# Test bad instructions and operands.
.text
.globl f
f:
nonesuch foo bar
nop nonconst
nop 2,
nop 2,3
nop 2 , 4
nop 2 4
nop 0
nop -1
nop 10000
nop 10
nop 15
abs .L1 a1,
abs .L1 a1
abs .S1 a1,a2
abs .L1 foo,bar
abs .L1X foo,bar
abs .L1 A0,A00
abs .L1 A32,A1
abs .L1 B1,A1
abs .L1 A1,B1
abs .L1X A1,A1
abs .L1X B1,B1
abs .L2 A3,B4
abs .L2 B4,A3
abs .L2X A7,A8
abs .L2X b9,b10
abs .L1 A2:A1,A3:A2
abs .L2 B5:B4,B2:B3
abs .L1 A3:B2,A5:A4
abs .L2 B1:B0,A5:A4
abs .L1X B1:B0,A1:A0
abs .L1 A1:A0,A11
abs2 .L1 a1
abs2 .S1 a1,a2
abs2 .L1 foo,a3:a2
abs2 .L2X b1,b2
absdp .L1 a3:a2,a1:a0
absdp .S2 b1:b0
absdp .S2 b1,b0
absdp .S2X a1:a0,b1:b0
abssp .L1 a0,a0
abssp .S1 a1:a0
abssp .S1X a0,a1
abssp .S2 a1,b0
add .M1 a0,a0,a0
add .L1 a0,b0,a0
add .L1X a0,a0,a0
add .L1 a1:a0,a3:a2,a5:a4
add .L1X 16,b2,a3
add .L1X -17,b2,a3
add .L1X 5,a3:a2,a7:a6
add .L2 100,b5:b4,b9:b8
add .L1 a0,a0
add .S1 a0,a0,a1:a0
add .S2 b1,b2
add .S1X 4,a5,a7
add .S2X -17,a9,b11
add .S1 16,a14,a13
add .D1T1 a1,a1,a1
add .D1 a1,a1
add .D2 b1,-17,b2
add .D2 b1,32,b4
add .D1X b1,b1,a1
add .D2X a5,-17,b1
add .D2X a20,16,b4
addab .L1 a4,a5,a6
addab .D1X a7,a8,a9
addab .D1 a2,a3
addab .D2 a1,b2,b3
addab .D1 a1,-1,a2
addab .D2 b1,32,b2
addab .D1X b14,-1,a2
addab .D2 b15,32768,b20
addab .D1 a14,32,a20
addad .D1X a4,a5,a6
addad .S1 a10,a9,a8
addad .D1 a1,a2,a3,a4
addad .D2 b4,-1,b4
addad .D2 b4,32,b3
addad .D1 a1,b2,a3
addad .D2 b14,foo,b4
addah .L1 a4,a5,a6
addah .D1X a7,a8,a9
addah .D1 a2,a3
addah .D2 a1,b2,b3
addah .D1 a1,-1,a2
addah .D2 b1,32,b2
addah .D1X b14,-1,a2
addah .D2 b15,32768,b20
addah .D1 a14,32,a20
addaw .L1 a4,a5,a6
addaw .D1X a7,a8,a9
addaw .D1 a2,a3
addaw .D2 a1,b2,b3
addaw .D1 a1,-1,a2
addaw .D2 b1,32,b2
addaw .D1X b14,-1,a2
addaw .D2 b15,32768,b20
addaw .D1 a14,32,a20
adddp .D1 a1:a0,a1:a0,a1:a0
adddp .L1 a1:a0,a1:a0
adddp .L2 b1,b1,b1
adddp .L1 a1:a0,b1:b0,a1:a0
adddp .L2X b1:b0,b3:b2,b5:b4
addk .L1 0,a1
addk .S2 32768,b1
addk .S1 -32769,a1
addk .S2 0
addk .S2X 0,a1
mvk .M1 0,a1
mvk .S2 32768,b1
mvk .S1 -32769,a1
mvk .S2 0,b1,0
mvk .S1X 0,b1
mvkh .L1 0,a1
mvkh .S2 0,b1,0
mvkh .S1X 0,b1
mvklh .L1 0,a1
mvklh .S2 0,b1,0
mvklh .S1X 0,b1
mvkl .L1 0,a1
mvkl .S2 0,b1,0
mvkl .S1X 0,b1
addkpc .S1 f,a1,0
addkpc .S2X f,a1,0
addkpc .S2 0,b2,0
addkpc .S2 f,b2
addkpc .S2 f,b2,-1
addkpc .S2 f,b2,8
b .L1 f
b .S1X f
b .S1 f,0
b .S1 0
call .L1 f
call .S1X f
call .S1 f,0
call .S1 0
bdec .L1 f,a1
bdec .S1X f,b1
bdec .S1 f,b1
bdec .S2 0,b2
bdec .S2 f,b1,0
bpos .L1 f,a1
bpos .S1X f,b1
bpos .S1 f,b1
bpos .S2 0,b2
bpos .S2 f,b1,0
bnop .L1 f,0
bnop .S1X f,0
bnop f,-1
bnop 0,0
bnop f,8
callnop .L1 f,0
callnop .S1X f,0
callnop f,-1
callnop 0,0
callnop f,8
callp .L1 f,a3
callp .S1X f,b3
callp .S1 f,a4
callp .S1 0,a3
callp .S1 f,b3
callp .S2 f,a3
addsp .D1 a1,a2,a3
addsp .L1 a1
addsp .L2 a2,0
addsp .L1 b1,a1,a3
addsp .S2X b1,b2,b3
addsub .M1 a2,a3,a5:a4
addsub .L1 a1
addsub .L1 a1,a2,a3
addsub .L2 a1,b1,b3:b2
addsub2 .M1 a2,a3,a5:a4
addsub2 .L1 a1
addsub2 .L1 a1,a2,a3
addsub2 .L2 a1,b1,b3:b2
addu .D2 b4,b5,b7:b6
addu .L2 b1,b2
addu .L1 b1,a1,a3:a2
addu .L2X a4,b7:b6,b5
add2 .M1 a1,a2,a3
add2 .S1 a1,a2,a3,a4
add2 .L1 b1,a1,a2
add2 .D2X b1,b2,b3
add4 .S1 a1,a2,a3
add4 .L1 a1,a2,a3,a4
add4 .L1 b1,a1,a2
add4 .L2X b1,b2,b3
and .M2 b1,b2,b3
and .L1 -17,a4,a5
and .L2 16,b3,b4
and .S1X -17,b4,a5
and .S2X 16,a3,b4
and .D1 -17,a4,a5
and .D2 16,b3,b4
and .D1 b1,a2,a3
andn .M1 a1,a2,a3
andn .S1 a1
andn .D1X b2,b2,a3
andn .S2 0,b2,b3
avg2 .S1 a1,a2,a3
avg2 .M1 a1,a2
avg2 .M1 b1,a2,a2
avg2 .M2X a1,a2,b3
avgu4 .S1 a1,a2,a3
avgu4 .M1 a1,a2
avgu4 .M1 b1,a2,a2
avgu4 .M2X a1,a2,b3
b .L2 b1
b .S2 b1,0
call .M2 b1
call .S2 b1,0
callret .D2 b1
callret .S2 b1,0
ret .L2 b1
ret .S2 b1,0
b .S2X irp
b .L2 irp
b .S2X nrp
b .M2 nrp
bitc4 .M1 a1,a2,a3
bitc4 .L1 a1,a2
bitc4 .M2 b2,a1
bitc4 .M2X b3,b4
bitr .M1 a1
bitr .S1 a1,a2
bitr .M2 b2,a1
bitr .M2X b3,b4
bnop .M1 a5,0
bnop .S1X b5,0
bnop .S2 b3,-1
bnop .S2 b3,8
bnop .S2 b3
callnop .M1 a5,0
callnop .S1X b5,0
callnop .S2 b3,-1
callnop .S2 b3,8
callnop .S2 b3
clr .L1 a1,0,1,a2
clr .M2 b1,b2,b3
clr .S1 a1,a1
clr .S1X a1,0,0,a1
clr .S2 b1,a1,b1
cmpeq .S1 a1,a2,a3
cmpeq .L1 a1,a2,a3,a4
cmpeq .L1 a1:a0,a3:a2,a5
cmpeq .L2 -17,b4,b5
cmpeq .L2 16,b4,b5
cmpeq .L1 -17,a5:a4,a3
cmpeq .L1 16,a5:a4,a3
cmpeq .L1X -16,a5:a4,a3
cmpeq2 .L1 a1,a2,a3
cmpeq2 .S1 a1,a2
cmpeq2 .S1 a1,b2,a3
cmpeq2 .S2X b1,b2,b3
cmpeq4 .D1 a1,a2,a3
cmpeq4 .S1 a1
cmpeq4 .S2 a1,b2,b3
cmpeq4 .S1X a4,a5,a6
cmpeqdp .M1 a3:a2,a1:a0,a5
cmpeqdp .S1 a3:a2
cmpeqdp .S1 a3,a2,a1
cmpeqdp .S2 a3:a2,b1:b0,b5
cmpeqdp .S2X b3:b2,b1:b0,b31
cmpeqsp .S1 a1
cmpeqsp .M2 b1,b2,b3
cmpeqsp .S2X b1,b2,b3
cmpeqsp .S1 b1,a2,a3
cmpgt .S1 a1,a2,a3
cmpgt .L1 a1,a2,a3,a4
cmpgt .L1 a1:a0,a3:a2,a5
cmpgt .L2 -17,b4,b5
cmpgt .L2 16,b4,b5
cmpgt .L1 -17,a5:a4,a3
cmpgt .L1 16,a5:a4,a3
cmpgt .L1X -16,a5:a4,a3
cmpgt2 .L1 a1,a2,a3
cmpgt2 .S1 a1,a2
cmpgt2 .S1 b1,a2,a3
cmpgt2 .S2X b1,b3,b3
cmpgtdp .L1 a1:a0,a1:a0,a0
cmpgtdp .S1 a1:a0
cmpgtdp .S1 b1:b0,a1:a0,a2
cmpgtdp .S2X b5:b4,b3:b2,b1
cmpgtsp .L1 a1,a1,a0
cmpgtsp .S1 a1
cmpgtsp .S1 b1,a1,a2
cmpgtsp .S2X b5,b3,b1
cmpgtu .S1 a1,a2,a3
cmpgtu .L1 a1,a2,a3,a4
cmpgtu .L1 a1:a0,a3:a2,a5
cmpgtu .L2 -1,b4,b5
cmpgtu .L2 32,b4,b5
cmpgtu .L1 -1,a5:a4,a3
cmpgtu .L1 32,a5:a4,a3
cmpgtu .L1X 0,a5:a4,a3
cmpgtu4 .D1 a1,a2,a3
cmpgtu4 .S1 a1,a2
cmpgtu4 .S1 a1,a2,b3
cmpgtu4 .S2X b1,b2,b3
cmplt .S1 a1,a2,a3
cmplt .L1 a1,a2,a3,a4
cmplt .L1 a1:a0,a3:a2,a5
cmplt .L2 -17,b4,b5
cmplt .L2 16,b4,b5
cmplt .L1 -17,a5:a4,a3
cmplt .L1 16,a5:a4,a3
cmplt .L1X -16,a5:a4,a3
cmplt2 .L1 a1,a2,a3
cmplt2 .S1 a1,a2
cmplt2 .S1 a2,b1,a3
cmplt2 .S2X b1,b3,b3
cmpltdp .L1 a1:a0,a1:a0,a0
cmpltdp .S1 a1:a0
cmpltdp .S1 b1:b0,a1:a0,a2
cmpltdp .S2X b5:b4,b3:b2,b1
cmpltsp .L1 a1,a1,a0
cmpltsp .S1 a1
cmpltsp .S1 b1,a1,a2
cmpltsp .S2X b5,b3,b1
cmpltu .S1 a1,a2,a3
cmpltu .L1 a1,a2,a3,a4
cmpltu .L1 a1:a0,a3:a2,a5
cmpltu .L2 -1,b4,b5
cmpltu .L2 32,b4,b5
cmpltu .L1 -1,a5:a4,a3
cmpltu .L1 32,a5:a4,a3
cmpltu .L1X 0,a5:a4,a3
cmpltu4 .D1 a1,a2,a3
cmpltu4 .S1 a1,a2
cmpltu4 .S1 a1,a2,b3
cmpltu4 .S2X b1,b2,b3
cmpy .S1 a1,a2,a5:a4
cmpy .M1 a1,a2
cmpy .M1 b1,a1,a3:a2
cmpy .M2X b3,b4,b7:b6
cmpyr .S1 a1,a2,a5
cmpyr .M1 a1,a2
cmpyr .M1 b1,a1,a3
cmpyr .M2X b3,b4,b7
cmpyr1 .L1 a1,a2,a5
cmpyr1 .M1 a1,a2
cmpyr1 .M1 b1,a1,a3
cmpyr1 .M2X b3,b4,b7
ddotp4 .D1 a1,a3,a5:a4
ddotp4 .M1 a1,a3
ddotp4 .M1X a1,a2,a5:a4
ddotp4 .M2 a1,b1,b3:b2
ddotph2 .L1 a1:a0,a3,a5:a4
ddotph2 .M1 a1:a0,a3
ddotph2 .M1X a1:a0,a2,a5:a4
ddotph2 .M2 a1:a0,b1,b3:b2
ddotph2r .S1 a1:a0,a3,a5
ddotph2r .M1 a1:a0,a3
ddotph2r .M1X a1:a0,a2,a5
ddotph2r .M2 a1:a0,b1,b3
ddotpl2 .L1 a1:a0,a3,a5:a4
ddotpl2 .M1 a1:a0,a3
ddotpl2 .M1X a1:a0,a2,a5:a4
ddotpl2 .M2 a1:a0,b1,b3:b2
ddotpl2r .L1 a1:a0,a3,a5
ddotpl2r .M1 a1:a0,a3
ddotpl2r .M1X a1:a0,a2,a5
ddotpl2r .M2 a1:a0,b1,b3
deal .D1 a1,a2
deal .M1 a1,a2,a3
deal .M2 b1,a1
deal .M2X b1,b2
dint .S1
dint a1
dmv .M1 a1,a2,a5:a4
dmv .S1 a1,a2
dmv .S2 a1,b2,b5:b4
dmv .S2X b1,b2,b5:b4
dotp2 .L1 a1,a2,a3
dotp2 .M1 a1,a2
dotp2 .M1 b1,a2,a3
dotp2 .M1X a1,a2,a3
dotp2 .M2 a1,b2,b5:b4
dotp2 .M2X b3,b4,b7:b6
dotpn2 .L1 a1,a2,a3
dotpn2 .M1 a1,a2
dotpn2 .M1 b1,a2,a3
dotpn2 .M1X a1,a2,a3
dotpnrsu2 .L1 a1,a2,a3
dotpnrsu2 .M1 a1,a2
dotpnrsu2 .M1 b1,a2,a3
dotpnrsu2 .M1X a1,a2,a3
dotpnrus2 .L1 a1,a2,a3
dotpnrus2 .M1 a1,a2
dotpnrus2 .M1 a2,b1,a3
dotpnrus2 .M1X a1,a2,a3
dotprsu2 .L1 a1,a2,a3
dotprsu2 .M1 a1,a2
dotprsu2 .M1 b1,a2,a3
dotprsu2 .M1X a1,a2,a3
dotprus2 .L1 a1,a2,a3
dotprus2 .M1 a1,a2
dotprus2 .M1 a2,b1,a3
dotprus2 .M1X a1,a2,a3
dotpsu4 .L1 a1,a2,a3
dotpsu4 .M1 a1,a2
dotpsu4 .M1 b1,a2,a3
dotpsu4 .M1X a1,a2,a3
dotpus4 .L1 a1,a2,a3
dotpus4 .M1 a1,a2
dotpus4 .M1 a2,b1,a3
dotpus4 .M1X a1,a2,a3
dotpu4 .L1 a1,a2,a3
dotpu4 .M1 a1,a2
dotpu4 .M1 b1,a2,a3
dotpu4 .M1X a1,a2,a3
dpack2 .M1 a0,a1,a3:a2
dpack2 .L1 a0,a1
dpack2 .L1 a1,a2,b3:b2
dpack2 .L2X b3,b4,b7:b6
dpackx2 .M1 a0,a1,a3:a2
dpackx2 .L1 a0,a1
dpackx2 .L1 a1,a2,b3:b2
dpackx2 .L2X b3,b4,b7:b6
dpint .S1 a5:a4,a3
dpint .L1X b5:b4,a3
dpint .L2 a5:a4,b3
dpsp .S1 a5:a4,a3
dpsp .L1X b5:b4,a3
dpsp .L2 a5:a4,b3
dptrunc .S1 a5:a4,a3
dptrunc .L1X b5:b4,a3
dptrunc .L2 a5:a4,b3
ext .L1 a1,0,1,a2
ext .M2 b1,b2,b3
ext .S1 a1,a1
ext .S1X a1,0,0,a1
ext .S2 b1,a1,b1
clr .S1 a0,-1,0,a1
clr .S1 a0,32,0,a1
clr .S1 a0,0,-1,a1
clr .S1 a0,0,32,a1
ext .S1 a0,-1,0,a1
ext .S1 a0,32,0,a1
ext .S1 a0,0,-1,a1
ext .S1 a0,0,32,a1
extu .L1 a1,0,1,a2
extu .M2 b1,b2,b3
extu .S1 a1,a1
extu .S1X a1,0,0,a1
extu .S2 b1,a1,b1
extu .S1 a0,-1,0,a1
extu .S1 a0,32,0,a1
extu .S1 a0,0,-1,a1
extu .S1 a0,0,32,a1
gmpy .L1 a1,a2,a3
gmpy .M1 a1,a2
gmpy .M1X a1,a2,a3
gmpy .M2 a1,b2,b3
gmpy4 .S1 a1,a2,a3
gmpy4 .M1 a1,a2,a3,a4
gmpy4 .M1 b1,a1,a2
gmpy4 .M2X b1,b2,b3
idle .S1
idle a0
intdp .S1 a5,a3:a2
intdp .L1 a5
intdp .L2 b0,a1:a0
intdp .L1X b5,b3:b2
intdpu .D1 a5,a3:a2
intdpu .L1 a5
intdpu .L2 b0,a1:a0
intdpu .L1X b5,b3:b2
intsp .S1 a5,a3
intsp .L1 a5
intsp .L2 b0,a1
intsp .L1X b5,b3
intspu .D1 a5,a3
intspu .L1 a5
intspu .L2 b0,a1
intspu .L1X b5,b3
cmtl .D2T1 *b0,a0
cmtl .D1T1 *a0,a1
cmtl .L1 *a0,a1
cmtl .D2T2 *+b0(0),b1
cmtl .D2T2 *-b0[0],b1
cmtl .D2T2 *++b0,b1
cmtl .D2T2 *--b0,b1
cmtl .D2T2 *b0++,b1
cmtl .D2T2 *b0--,b1
cmtl .D2T2 *+b0[b1],b2
cmtl .D2T2 *a0,b1
cmtl .D2T2 *b0,a1
ll .D2T1 *b0,a0
ll .D1T1 *a0,a1
ll .S1 *a0,a1
ll .D2T2 *+b0(0),b1
ll .D2T2 *-b0[0],b1
ll .D2T2 *++b0,b1
ll .D2T2 *--b0,b1
ll .D2T2 *b0++,b1
ll .D2T2 *b0--,b1
ll .D2T2 *+b0[b1],b2
ll .D2T2 *a0,b1
ll .D2T2 *b0,a1
sl .D2T1 a0,*b0
sl .D1T1 a1,*a0
sl .L1 a1,*a0
sl .D2T2 b1,*+b0(0)
sl .D2T2 b1,*-b0[0]
sl .D2T2 b1,*++b0
sl .D2T2 b1,*--b0
sl .D2T2 b1,*b0++
sl .D2T2 b1,*b0--
sl .D2T2 b2,*+b0[b1]
sl .D2T2 b1,*a0
sl .D2T2 a1,*b0
ldb .L1 *a1,a0
ldb .D1T1 *a1,b1
ldb .D1T1 *b1,a1
ldb .D2T2 *a1,b1
ldb .D2T2 *b1,a1
ldb .D1T1 *a1
ldb .D1T1 *+a1[b1],a2
ldb .D1T1 *+a1,a2
ldb .D1T1 *-a1,a2
ldb .D1T1 *a1++[32],a2
ldb .D1T1 *a1++(32),a2
ldb .D1T1 *--a1[-1],a2
ldb .D1T1 *--a1(-1),a2
ldb .D1T1 *+a1(a2),a3
ldb .D2T2 *+b14[foo],b16
ldbu .S1 *a1,a0
ldbu .D1T1 *a1,b1
ldbu .D1T1 *b1,a1
ldbu .D2T2 *a1,b1
ldbu .D2T2 *b1,a1
ldbu .D1T1 *a1
ldbu .D1T1 *+a1[b1],a2
ldbu .D1T1 *+a1,a2
ldbu .D1T1 *-a1,a2
ldbu .D1T1 *a1++[32],a2
ldbu .D1T1 *a1++(32),a2
ldbu .D1T1 *--a1[-1],a2
ldbu .D1T1 *--a1(-1),a2
ldbu .D1T1 *+a1(a2),a3
ldbu .D2T2 *+b14[foo],b16
lddw .L1 *a1,a1:a0
lddw .D1T1 *a1,b1:b0
lddw .D1T1 *b1,a1:a0
lddw .D2T2 *a1,b1:b0
lddw .D2T2 *b1,a1:a0
lddw .D1T1 *a1
lddw .D1T1 *+a1[b1],a3:a2
lddw .D1T1 *+a1,a3:a2
lddw .D1T1 *-a1,a3:a2
lddw .D1T1 *a1++[32],a3:a2
lddw .D1T1 *a1++(256),a3:a2
lddw .D1T1 *--a1[-1],a3:a2
lddw .D1T1 *--a1(-8),a3:a2
lddw .D1T1 *+a1(a2),a3:a2
lddw .D2T2 *+b14[foo],b17:b16
lddw .D1T1 *+a1(1),a3:a2
lddw .D2T2 *+b14(b15),b17:b16
ldh .M1 *a1,a0
ldh .D1T1 *a1,b1
ldh .D1T1 *b1,a1
ldh .D2T2 *a1,b1
ldh .D2T2 *b1,a1
ldh .D1T1 *a1
ldh .D1T1 *+a1[b1],a2
ldh .D1T1 *+a1,a2
ldh .D1T1 *-a1,a2
ldh .D1T1 *a1++[32],a2
ldh .D1T1 *a1++(64),a2
ldh .D1T1 *--a1[-1],a2
ldh .D1T1 *--a1(-2),a2
ldh .D1T1 *+a1(a2),a3
ldh .D2T2 *+b14[foo],b16
ldh .D2T2 *+b1(1),b2
ldhu .S1 *a1,a0
ldhu .D1T1 *a1,b1
ldhu .D1T1 *b1,a1
ldhu .D2T2 *a1,b1
ldhu .D2T2 *b1,a1
ldhu .D1T1 *a1
ldhu .D1T1 *+a1[b1],a2
ldhu .D1T1 *+a1,a2
ldhu .D1T1 *-a1,a2
ldhu .D1T1 *a1++[32],a2
ldhu .D1T1 *a1++(64),a2
ldhu .D1T1 *--a1[-1],a2
ldhu .D1T1 *--a1(-2),a2
ldhu .D1T1 *+a1(a2),a3
ldhu .D2T2 *+b14[foo],b16
ldhu .D2T2 *+b1(1),b2
ldndw .L1 *a1,a1:a0
ldndw .D1T1 *a1,b1:b0
ldndw .D1T1 *b1,a1:a0
ldndw .D2T2 *a1,b1:b0
ldndw .D2T2 *b1,a1:a0
ldndw .D1T1 *a1
ldndw .D1T1 *+a1[b1],a3:a2
ldndw .D1T1 *+a1,a3:a2
ldndw .D1T1 *-a1,a3:a2
ldndw .D1T1 *a1++[32],a3:a2
ldndw .D1T1 *a1++(32),a3:a2
ldndw .D1T1 *--a1[-1],a3:a2
ldndw .D1T1 *--a1(-1),a3:a2
ldndw .D2T2 *+b14[foo],b17:b16
ldnw .S1 *a1,a0
ldnw .D1T1 *a1,b1
ldnw .D1T1 *b1,a1
ldnw .D2T2 *a1,b1
ldnw .D2T2 *b1,a1
ldnw .D1T1 *a1
ldnw .D1T1 *+a1[b1],a2
ldnw .D1T1 *+a1,a2
ldnw .D1T1 *-a1,a2
ldnw .D1T1 *a1++[32],a2
ldnw .D1T1 *a1++(128),a2
ldnw .D1T1 *--a1[-1],a2
ldnw .D1T1 *--a1(-4),a2
ldnw .D1T1 *+a1(a2),a3
ldnw .D2T2 *+b14[foo],b16
ldnw .D2T2 *+b1(2),b2
ldw .S1 *a1,a0
ldw .D1T1 *a1,b1
ldw .D1T1 *b1,a1
ldw .D2T2 *a1,b1
ldw .D2T2 *b1,a1
ldw .D1T1 *a1
ldw .D1T1 *+a1[b1],a2
ldw .D1T1 *+a1,a2
ldw .D1T1 *-a1,a2
ldw .D1T1 *a1++[32],a2
ldw .D1T1 *a1++(128),a2
ldw .D1T1 *--a1[-1],a2
ldw .D1T1 *--a1(-4),a2
ldw .D1T1 *+a1(a2),a3
ldw .D2T2 *+b14[foo],b16
ldw .D2T2 *+b1(2),b2
ldb .D2T2 *+b14[-1],b1
ldb .D2T2 *+b14[32768],b1
ldbu .D2T2 *+b14[-1],b1
ldbu .D2T2 *+b14[32768],b1
ldh .D2T2 *+b14[-1],b1
ldh .D2T2 *+b14[32768],b1
ldhu .D2T2 *+b14[-1],b1
ldhu .D2T2 *+b14[32768],b1
ldw .D2T2 *+b14[-1],b1
ldw .D2T2 *+b14[32768],b1
lmbd .S1 a1,a2,a3
lmbd .L1 a1,a2
lmbd .L1 b1,a2,a3
lmbd .L2X b1,b2,b3
lmbd .L1 -17,a1,a2
lmbd .L1 16,a1,a2
max2 .M1 a1,a2,a3
max2 .L1 a1,a2
max2 .L1 b1,a2,a3
max2 .L2X b1,b2,b3
max2 .S2X b1,b2,b3
max2 .S2 a1,b2,b3
maxu4 .S1 a1,a2,a3
maxu4 .L1 a1,a2
maxu4 .L1 b1,a2,a3
maxu4 .L2X b1,b2,b3
min2 .M1 a1,a2,a3
min2 .L1 a1,a2
min2 .L1 b1,a2,a3
min2 .L2X b1,b2,b3
min2 .S2X b1,b2,b3
min2 .S2 a1,b2,b3
minu4 .S1 a1,a2,a3
minu4 .L1 a1,a2
minu4 .L1 b1,a2,a3
minu4 .L2X b1,b2,b3
mpy .L1 a1,a2,a3
mpy .M1 a1,a2
mpy .M1 b1,a2,a3
mpy .M2X b1,b2,b3
mpy .M2 -17,b1,b2
mpy .M1 16,a1,a2
mpy .M2X 0,b2,b3
mpydp .D1 a1:a0,a1:a0,a1:a0
mpydp .M1 a1:a0,a1:a0
mpydp .M1 b1:b0,a1:a0,a3:a2
mpyh .S1 a1,a2,a3
mpyh .M1 a1,a2
mpyh .M1 b1,a2,a3
mpyh .M2X b1,b2,b3
mpyhi .D1 a1,a2,a5:a4
mpyhi .M1 a1,a2
mpyhi .M1 b1,a2,a5:a4
mpyhi .M2X b1,b2,b5:b4
mpyhir .D1 a1,a2,a3
mpyhir .M1 a1,a2
mpyhir .M1 b1,a2,a3
mpyhir .M2X b1,b2,b3
mpyhl .L1 a1,a2,a3
mpyhl .M1 a1,a2
mpyhl .M1 b1,a2,a3
mpyhl .M2X b1,b2,b3
mpyhlu .S1 a1,a2,a3
mpyhlu .M1 a1,a2
mpyhlu .M1 b1,a2,a3
mpyhlu .M2X b1,b2,b3
mpyhslu .S1 a1,a2,a3
mpyhslu .M1 a1,a2
mpyhslu .M1 b1,a2,a3
mpyhslu .M2X b1,b2,b3
mpyhsu .S1 a1,a2,a3
mpyhsu .M1 a1,a2
mpyhsu .M1 b1,a2,a3
mpyhsu .M2X b1,b2,b3
mpyhu .D1 a1,a2,a3
mpyhu .M1 a1,a2
mpyhu .M1 b1,a2,a3
mpyhu .M2X b1,b2,b3
mpyhuls .S1 a1,a2,a3
mpyhuls .M1 a1,a2
mpyhuls .M1 b1,a2,a3
mpyhuls .M2X b1,b2,b3
mpyhus .S1 a1,a2,a3
mpyhus .M1 a1,a2
mpyhus .M1 b1,a2,a3
mpyhus .M2X b1,b2,b3
mpyi .L1 a1,a2,a3
mpyi .M1 a1,a2
mpyi .M1 b1,a2,a3
mpyi .M2X b1,b2,b3
mpyi .M1 -17,a2,a3
mpyi .M2 16,b2,b3
mpyid .D1 a1,a2,a3:a2
mpyid .M1 a1,a2
mpyid .M1 b1,a2,a3:a2
mpyid .M2X b1,b2,b3:b2
mpyid .M1 -17,a2,a3:a2
mpyid .M2 16,b2,b3:b2
mpyih .D1 a1,a2,a5:a4
mpyih .M1 a1,a2
mpyih .M1 b1,a2,a5:a4
mpyih .M2X b1,b2,b5:b4
mpyihr .D1 a1,a2,a3
mpyihr .M1 a1,a2
mpyihr .M1 b1,a2,a3
mpyihr .M2X b1,b2,b3
mpyil .S1 a1,a2,a5:a4
mpyil .M1 a1,a2
mpyil .M1 b1,a2,a5:a4
mpyil .M2X b1,b2,b5:b4
mpyilr .L1 a1,a2,a3
mpyilr .M1 a1,a2
mpyilr .M1 b1,a2,a3
mpyilr .M2X b1,b2,b3
mpylh .S1 a1,a2,a3
mpylh .M1 a1,a2
mpylh .M1 b1,a2,a3
mpylh .M2X b1,b2,b3
mpylhu .D1 a1,a2,a3
mpylhu .M1 a1,a2
mpylhu .M1 b1,a2,a3
mpylhu .M2X b1,b2,b3
mpyli .S1 a1,a2,a3:a2
mpyli .M1 a1,a2
mpyli .M1 b1,a2,a3:a2
mpyli .M2X b1,b2,b3:b2
mpylir .D1 a1,a2,a3
mpylir .M1 a1,a2
mpylir .M1 b1,a2,a3
mpylir .M2X b1,b2,b3
mpylshu .L1 a1,a2,a3
mpylshu .M1 a1,a2
mpylshu .M1 b1,a2,a3
mpylshu .M2X b1,b2,b3
mpyluhs .S1 a1,a2,a3
mpyluhs .M1 a1,a2
mpyluhs .M1 b1,a2,a3
mpyluhs .M2X b1,b2,b3
mpysp .D1 a1,a2,a3
mpysp .M1 a1,a2
mpysp .M1 b1,a2,a3
mpysp .M2X b1,b2,b3
mpyspdp .L1 a1,a1:a0,a1:a0
mpyspdp .M1 a1,a1:a0,a1:a0,a1:a0
mpyspdp .M1 b1,a1:a0,a1:a0
mpyspdp .M2X b1,b1:b0,b1:b0
mpysp2dp .S1 a1,a2,a3:a2
mpysp2dp .M1 a1,a2
mpysp2dp .M1 b1,a2,a3:a2
mpysp2dp .M2X b1,b2,b3:b2
mpysu .D1 a1,a2,a3
mpysu .M1 a1,a2
mpysu .M1 b1,a2,a3
mpysu .M2X b1,b2,b3
mpysu .M1 -17,a2,a3
mpysu .M2 16,b2,b3
mpysu4 .S1 a1,a2,a3:a2
mpysu4 .M1 a1,a2
mpysu4 .M1 b1,a2,a3:a2
mpysu4 .M2X b1,b2,b3:b2
mpyu .L1 a1,a2,a3
mpyu .M1 a1,a2
mpyu .M1 b1,a2,a3
mpyu .M2X b1,b2,b3
mpyu4 .D1 a1,a2,a3:a2
mpyu4 .M1 a1,a2
mpyu4 .M1 b1,a2,a3:a2
mpyu4 .M2X b1,b2,b3:b2
mpyus .S1 a1,a2,a3
mpyus .M1 a1,a2
mpyus .M1 b1,a2,a3
mpyus .M2X b1,b2,b3
mpyus4 .L1 a1,a2,a3:a2
mpyus4 .M1 a1,a2
mpyus4 .M1 b1,a2,a3:a2
mpyus4 .M2X b1,b2,b3:b2
mpy2 .D1 a1,a2,a3:a2
mpy2 .M1 a1,a2
mpy2 .M1 b1,a2,a3:a2
mpy2 .M2X b1,b2,b3:b2
mpy2ir .L1 a1,a2,a3:a2
mpy2ir .M1 a1,a2
mpy2ir .M1 b1,a2,a3:a2
mpy2ir .M2X b1,b2,b3:b2
mpy32 .L1 a1,a2,a3
mpy32 .M1 a1,a2
mpy32 .M1 b1,a2,a3
mpy32 .M2X b1,b2,b3
mpy32 .M1 b1,a2,a3:a2
mpy32 .M1X a1,a2,a5:a4
mpy32su .L1 a1,a2,a3:a2
mpy32su .M1 a1,a2
mpy32su .M2X b1,b2,b3:b2
mpy32su .M1 b1,a2,a3:a2
mpy32u .L1 a1,a2,a3:a2
mpy32u .M1 a1,a2
mpy32u .M2X b1,b2,b3:b2
mpy32u .M1 b1,a2,a3:a2
mpy32us .L1 a1,a2,a3:a2
mpy32us .M1 a1,a2
mpy32us .M2X b1,b2,b3:b2
mpy32us .M1 b1,a2,a3:a2
mvc .L2 b2,amr
mvc .S2X amr,a1
mvc .S2 b2,nonesuch
mvc .S2 b0,dnum
mvc .S2 ecr,b0
mvc .S2 b0,efr
mvc .S2 icr,b0
mvc .S2 b0,ifr
mvc .S2 isr,b0
mvc .S2 b0,pce1
mvc .S2 b0,tsch
mv .M1 a1,a2
mv .L1 a1,a2,a3
mv .L1 a1,b2
mv .L2X b1,b2
mv .S1 a1,b2
mv .S2X b1,b2
mv .D1 a1,b2
mv .D2X b1,b2
mvd .L1 a1,a2
mvd .M1 a3,a4,a5
mvd .M1 a1,b2
mvd .M2X b3,b4
mvk .L1 -17,a0
mvk .L1 16,a0
mvk .L1X 0,a0
mvk .D2 -17,b0
mvk .D2 16,b0
mvk .D2X 0,b0
norm .S1 a1,a0
norm .L1 a1:a0,a0,a0
norm .L1X b1:b0,a1
norm .L2 b1,a1
norm .L2X b1,b1
or .M1 a1,a2,a3
or .L1 a1,a2
or .D1 -17,a0,a0
or .D1X 16,b0,a0
or .L1 -17,a0,a0
or .L1X 16,b0,a0
or .S2 -17,b0,b0
or .S2X 16,a0,b0
or .D1 a0,a0,b0
or .D2X b0,b0,b0
or .L1X a0,a0,a0
or .S2 b0,b0,a0
pack2 .D1 a0,a0,a0
pack2 .L1 a0,a0
pack2 .S1 a0,a1,b2
pack2 .L2X b0,b0,b0
packh2 .M1 a0,a0,a0
packh2 .L1 a0,a0
packh2 .S1 a0,a1,b2
packh2 .L2X b0,b0,b0
packh4 .S1 a0,a0,a0
packh4 .L1 a0,a0
packh4 .L1 a0,a1,b2
packh4 .L2X b0,b0,b0
packhl2 .M1 a0,a0,a0
packhl2 .L1 a0,a0
packhl2 .S1 a0,a1,b2
packhl2 .L2X b0,b0,b0
packlh2 .D1 a0,a0,a0
packlh2 .L1 a0,a0
packlh2 .S1 a0,a1,b2
packlh2 .L2X b0,b0,b0
packl4 .S1 a0,a0,a0
packl4 .L1 a0,a0
packl4 .L1 a0,a1,b2
packl4 .L2X b0,b0,b0
rcpdp .L1 a1:a0,a1:a0
rcpdp .S1 a1:a0
rcpdp .S1 b1:b0,a1:a0
rcpdp .S2X a1:a0,b1:b0
rcpsp .L1 a0,a0
rcpsp .S1 a0,a0,a0
rcpsp .S2 b0,a0
rcpsp .S1X a0,a0
rint .S2
rint a0
rotl .S1 a0,a0,a0
rotl .M1 a0,a0
rotl .M1 a0,b0,a0
rotl .M2X b0,b0,b0
rotl .M1 a0,-1,a0
rotl .M2 b0,32,b0
rotl .M2X b0,0,b0
rpack2 .L1 a0,a0,a0
rpack2 .S1 a0,a0
rpack2 .S2 a0,b0,b0
rpack2 .S1X a0,a0,a0
rsqrdp .L1 a1:a0,a1:a0
rsqrdp .S1 a1:a0
rsqrdp .S1 b1:b0,a1:a0
rsqrdp .S2X a1:a0,b1:b0
rsqrsp .L1 a0,a0
rsqrsp .S1 a0,a0,a0
rsqrsp .S2 b0,a0
rsqrsp .S1X a0,a0
sadd .D1 a1,a2,a3
sadd .L1 a1,a2
sadd .S1 0,a1,a2
sadd .L1X 0,a1:a0,a1:a0
sadd .L1 b0,a0,a0
sadd .L1X a0,a0,a0
sadd .L2 -17,b0,b0
sadd .L2 16,b0,b0
sadd .L1 -17,a1:a0,a1:a0
sadd .L1 16,a1:a0,a1:a0
sadd2 .L1 a0,a0,a0
sadd2 .S1 a0,a0
sadd2 .S2 a0,b0,b0
sadd2 .S2X b0,b0,b0
saddsub .S1 a0,a0,a1:a0
saddsub .L1 a0,a0
saddsub .L1 a0,a0,a0
saddsub .L2 a0,b0,b1:b0
saddsub .L2X b0,b0,b1:b0
saddsub2 .S1 a0,a0,a1:a0
saddsub2 .L1 a0,a0
saddsub2 .L1 a0,a0,a0
saddsub2 .L2 a0,b0,b1:b0
saddsub2 .L2X b0,b0,b1:b0
saddsu2 .L1 a0,a0,a0
saddsu2 .S1 a0
saddsu2 .S2 b0,a0,b0
saddsu2 .S2X b0,b0,b0
saddus2 .M1 a0,a0,a0
saddus2 .S1 a0,a0
saddus2 .S1 b0,a0,a0
saddus2 .S1X a0,a0,a0
saddu4 .D1 a0,a0,a0
saddu4 .S1 a0,a0
saddu4 .S1 b0,a0,a0
saddu4 .S1X a0,a0,a0
sat .S1 a1:a0,a0
sat .L1X b1:b0,a0
sat .L1 a1:a0
sat .L1 b1:b0,a0
set .L1 a0,0,0,a0
set .S1 a0
set .S1 a0,-1,0,a0
set .S1 a0,32,0,a0
set .S1 a0,0,-1,a0
set .S1 a0,0,32,a0
set .S1X b0,0,0,a0
set .S1X a0,a0,a0
set .S2 b0,a0,b0
shfl .S1 a0,a0
shfl .M1 a0,a0,a0
shfl .M1 a0,b0
shfl .M2X b0,b0
shfl3 .M1 a0,a0,a1:a0
shfl3 .L1 a0,a0
shfl3 .L1 b0,a0,a1:a0
shfl3 .L2X b0,b0,b1:b0
shl .L1 a0,a0,a0
shl .S1 a0,a0
shl .S1X a1:a0,a0,a1:a0
shl .S1 a0,b0,a0
shl .S2X b0,b0,b1:b0
shl .S1 a0,-1,a0
shl .S1 a0,32,a0
shl .S2 b1:b0,-1,b1:b0
shl .S2 b1:b0,32,b1:b0
shl .S1X b0,-1,a1:a0
shl .S1X b0,32,a1:a0
shlmb .D1 a0,a0,a0
shlmb .L1 a0,a0
shlmb .L1 b0,a0,a0
shlmb .L2X b0,b0,b0
shlmb .S1 b0,a0,a0
shlmb .S2X b0,b0,b0
shr .L1 a0,a0,a0
shr .S1 a0,a0
shr .S1X a1:a0,a0,a1:a0
shr .S1 a0,b0,a0
shr .S1 a0,-1,a0
shr .S1 a0,32,a0
shr .S2 b1:b0,-1,b1:b0
shr .S2 b1:b0,32,b1:b0
shr2 .L1 a0,a0,a0
shr2 .L1 a0,0,a0
shr2 .S1 a0,a0
shr2 .S1 a1,b0,a0
shr2 .S2X b0,b0,b0
shr2 .S1 a0,-1,a0
shr2 .S1 a0,32,a0
shrmb .M1 a0,a0,a0
shrmb .L1 a0,a0
shrmb .L1 b0,a0,a0
shrmb .L2X b0,b0,b0
shrmb .S1 b0,a0,a0
shrmb .S2X b0,b0,b0
shru .D1 a0,a0,a0
shru .S1 a0,a0
shru .S1X a1:a0,a0,a1:a0
shru .S1 a0,b0,a0
shru .S1 a0,-1,a0
shru .S1 a0,32,a0
shru .S2 b1:b0,-1,b1:b0
shru .S2 b1:b0,32,b1:b0
shru2 .L1 a0,a0,a0
shru2 .L1 a0,0,a0
shru2 .S1 a0,a0
shru2 .S1 a1,b0,a0
shru2 .S2X b0,b0,b0
shru2 .S1 a0,-1,a0
shru2 .S1 a0,32,a0
smpy .L1 a0,a0,a0
smpy .M1 a0,a0
smpy .M2 a0,b0,b0
smpy .M1X a0,a0,a0
smpyh .S1 a0,a0,a0
smpyh .M1 a0,a0
smpyh .M2 a0,b0,b0
smpyh .M1X a0,a0,a0
smpyhl .D1 a0,a0,a0
smpyhl .M1 a0,a0
smpyhl .M2 a0,b0,b0
smpyhl .M1X a0,a0,a0
smpylh .L1 a0,a0,a0
smpylh .M1 a0,a0
smpylh .M2 a0,b0,b0
smpylh .M1X a0,a0,a0
smpy2 .S1 a0,a0,a1:a0
smpy2 .M1 a0,a0
smpy2 .M2 a0,b0,b1:b0
smpy2 .M2X b0,b0,b1:b0
smpy32 .L1 a0,a0,a0
smpy32 .M1 a0,a0
smpy32 .M2 a0,b0,b0
smpy32 .M1X a0,a0,a0
spack2 .L1 a0,a0,a0
spack2 .S1 a0,a0
spack2 .S1 b0,a0,a0
spack2 .S2X b0,b0,b0
spacku4 .L1 a0,a0,a0
spacku4 .S1 a0,a0
spacku4 .S1 b0,a0,a0
spacku4 .S2X b0,b0,b0
spdp .M1 a0,a1:a0
spdp .S1 a0
spdp .S1 a0,b1:b0
spdp .S2X b0,b1:b0
spint .S1 a0,a0
spint .L1 a0,a0,a0
spint .L2 b0,a0
spint .L1X a0,a0
sptrunc .D1 a0,a0
sptrunc .L1 a0,a0,a0
sptrunc .L2 b0,a0
sptrunc .L1X a0,a0
sshl .L1 a0,a0,a0
sshl .S1 a0,a0
sshl .S1 a0,b0,a0
sshl .S1X a0,a0,a0
sshl .S2 b0,-1,b0
sshl .S2 b0,32,b0
sshvl .S1 a0,a0,a0
sshvl .M1 a0,a0
sshvl .M1 a0,b0,a0
sshvl .M1X a0,a0,a0
sshvr .L1 a0,a0,a0
sshvr .M1 a0,a0
sshvr .M1 a0,b0,a0
sshvr .M1X a0,a0,a0
ssub .S1 a0,a0,a0
ssub .L1 a0,a0
ssub .L1 a0,a0,b0
ssub .L1X a0,a0,a0
ssub .L2 -17,b0,b0
ssub .L2 16,b0,b0
ssub .L1X 0,a1:a0,a1:a0
ssub .L1 -17,a1:a0,a1:a0
ssub .L1 16,a1:a0,a1:a0
ssub2 .S1 a0,a0,a0
ssub2 .L1 a0,a0
ssub2 .L1 a0,b0,a0
ssub2 .L1X a0,a0,a0
stb .L1 a0,*a1
stb .D1T1 b1,*a1
stb .D1T1 a1,*b1
stb .D2T2 b1,*a1
stb .D2T2 a1,*b1
stb .D1T1 *a1
stb .D1T1 a2,*+a1[b1]
stb .D1T1 a2,*+a1
stb .D1T1 a2,*-a1
stb .D1T1 a2,*a1++[32]
stb .D1T1 a2,*a1++(32)
stb .D1T1 a2,*--a1[-1]
stb .D1T1 a2,*--a1(-1)
stb .D1T1 a3,*+a1(a2)
stb .D2T2 b16,*+b14[foo]
stb .D2T2 b1,*+b14[-1]
stb .D2T2 b1,*+b14[32768]
stdw .L1 a1:a0,*a1
stdw .D1T1 b1:b0,*a1
stdw .D1T1 a1:a0,*b1
stdw .D2T2 b1:b0,*a1
stdw .D2T2 a1:a0,*b1
stdw .D1T1 *a1
stdw .D1T1 a3:a2,*+a1[b1]
stdw .D1T1 a3:a2,*+a1
stdw .D1T1 a3:a2,*-a1
stdw .D1T1 a3:a2,*a1++[32]
stdw .D1T1 a3:a2,*a1++(256)
stdw .D1T1 a3:a2,*--a1[-1]
stdw .D1T1 a3:a2,*--a1(-8)
stdw .D1T1 a3:a2,*+a1(a2)
stdw .D2T2 b17:b16,*+b14[foo]
stdw .D1T1 a3:a2,*+a1(1)
stdw .D2T2 b17:b16,*+b14(b15)
sth .M1 a0,*a1
sth .D1T1 b1,*a1
sth .D1T1 a1,*b1
sth .D2T2 b1,*a1
sth .D2T2 a1,*b1
sth .D1T1 *a1
sth .D1T1 a2,*+a1[b1]
sth .D1T1 a2,*+a1
sth .D1T1 a2,*-a1
sth .D1T1 a2,*a1++[32]
sth .D1T1 a2,*a1++(64)
sth .D1T1 a2,*--a1[-1]
sth .D1T1 a2,*--a1(-2)
sth .D1T1 a3,*+a1(a2)
sth .D2T2 b16,*+b14[foo]
sth .D2T2 b2,*+b1(1)
sth .D2T2 b1,*+b14[-1]
sth .D2T2 b1,*+b14[32768]
stndw .L1 a1:a0,*a1
stndw .D1T1 b1:b0,*a1
stndw .D1T1 a1:a0,*b1
stndw .D2T2 b1:b0,*a1
stndw .D2T2 a1:a0,*b1
stndw .D1T1 *a1
stndw .D1T1 a3:a2,*+a1[b1]
stndw .D1T1 a3:a2,*+a1
stndw .D1T1 a3:a2,*-a1
stndw .D1T1 a3:a2,*a1++[32]
stndw .D1T1 a3:a2,*a1++(32)
stndw .D1T1 a3:a2,*--a1[-1]
stndw .D1T1 a3:a2,*--a1(-1)
stndw .D2T2 b17:b16,*+b14[foo]
stnw .S1 a0,*a1
stnw .D1T1 b1,*a1
stnw .D1T1 a1,*b1
stnw .D2T2 b1,*a1
stnw .D2T2 a1,*b1
stnw .D1T1 *a1
stnw .D1T1 a2,*+a1[b1]
stnw .D1T1 a2,*+a1
stnw .D1T1 a2,*-a1
stnw .D1T1 a2,*a1++[32]
stnw .D1T1 a2,*a1++(128)
stnw .D1T1 a2,*--a1[-1]
stnw .D1T1 a2,*--a1(-4)
stnw .D1T1 a3,*+a1(a2)
stnw .D2T2 b16,*+b14[foo]
stnw .D2T2 b2,*+b1(2)
stw .S1 a0,*a1
stw .D1T1 b1,*a1
stw .D1T1 a1,*b1
stw .D2T2 b1,*a1
stw .D2T2 a1,*b1
stw .D1T1 *a1
stw .D1T1 a2,*+a1[b1]
stw .D1T1 a2,*+a1
stw .D1T1 a2,*-a1
stw .D1T1 a2,*a1++[32]
stw .D1T1 a2,*a1++(128)
stw .D1T1 a2,*--a1[-1]
stw .D1T1 a2,*--a1(-4)
stw .D1T1 a3,*+a1(a2)
stw .D2T2 b16,*+b14[foo]
stw .D2T2 b2,*+b1(2)
stw .D2T2 b1,*+b14[-1]
stw .D2T2 b1,*+b14[32768]
neg .D1 a1,a2
neg .S1 a1:a0,a1:a0
neg .S1 a1,a1,a1
neg .S1 a1,b1
neg .S1X a1,a1
neg .L2X b1:b0,b1:b0
neg .L2 b0,a0
neg .L2X b0,b0
sub .M1 a0,a0,a0
sub .L1 a0,a0
sub .L1 b0,b0,a0
sub .L2X b0,b0,b0
sub .L1X 0,a1:a0,a1:a0
sub .L2 -17,b0,b0
sub .L2 16,b0,b0
sub .L1 -17,a1:a0,a1:a0
sub .L1 16,a1:a0,a1:a0
sub .S1 a0,a0
sub .S1 a0,a0,b0
sub .S1X a0,a0,a0
sub .S1 -17,a0,a0
sub .S1 16,a0,a0
sub .S1 0,a1:a0,a1:a0
sub .D1 a0
sub .D1 b0,a0,a0
sub .D1X a0,a0,a0
sub .D1X b0,0,a0
sub .D1 a0,-1,a0
sub .D1 a0,32,a0
subab .S1 a0,a0,a0
subab .D1 a0,a0
subab .D1 a0,b0,a0
subab .D1X a0,b0,a0
subab .D1X b0,0,a0
subab .D2 b0,-1,b0
subab .D2 b14,32,b14
subabs4 .S1 a0,a0,a0
subabs4 .L1 a0,a0
subabs4 .L1 a0,a0,b0
subabs4 .L2X b0,b0,b0
subah .M1 a0,a0,a0
subah .D1 a0,a0
subah .D1 a0,b0,a0
subah .D1X a0,b0,a0
subah .D1X b0,0,a0
subah .D2 b0,-1,b0
subah .D2 b14,32,b14
subaw .L1 a0,a0,a0
subaw .D1 a0,a0
subaw .D1 a0,b0,a0
subaw .D1X a0,b0,a0
subaw .D1X b0,0,a0
subaw .D2 b0,-1,b0
subaw .D2 b14,32,b14
subc .S1 a0,a0,a0
subc .L1 a0,a0
subc .L1 b0,a0,a0
subc .L2X b0,b0,b0
subdp .D1 a1:a0,a1:a0,a1:a0
subdp .L1 a1:a0
subdp .L1 b1:b0,a1:a0,a1:a0
subdp .L1X a1:a0,a1:a0,a1:a0
subdp .S1 b1:b0,a1:a0,a1:a0
subdp .S1X a1:a0,a1:a0,a1:a0
subsp .M1 a0,a0,a0
subsp .L1 a0,a0
subsp .L1 a0,a0,b0
subsp .L2X b0,b0,b0
subsp .S1 a0,a0
subsp .S1 a0,a0,b0
subsp .S2X b0,b0,b0
subu .S1 a0,a0,a1:a0
subu .L1 a0,a0
subu .L1 a0,a0,a0
subu .L2 b0,b0,a1:a0
subu .L1X a0,a0,a1:a0
sub2 .M1 a0,a0,a0
sub2 .L1 a0,a0
sub2 .L1 a0,a0,b0
sub2 .L2X b0,b0,b0
sub2 .S1 a0,a0
sub2 .S1 a0,a0,b0
sub2 .S2X b0,b0,b0
sub2 .D1 a0,a0
sub2 .D1 a0,a0,b0
sub2 .D2X b0,b0,b0
sub4 .S1 a0,a0,a0
sub4 .L1 a0,a0
sub4 .L1 a0,a0,b0
sub4 .L2X b0,b0,b0
swap2 .D1 a0,a0
swap2 .L1 a0,a0,a0
swap2 .L1X b0,a0
swap2 .L2 a0,b0
swap2 .S1 a0,a0,a0
swap2 .S1X b0,a0
swap2 .S2 a0,b0
swap4 .S1 a0,a0
swap4 .L1 a0
swap4 .L1 a0,b0
swap4 .L1X a0,a0
swe .S1
swe a0
swenr .L1
swenr b0
unpkhu4 .D1 a0,a0
unpkhu4 .L1 a0,a0,a0
unpkhu4 .L1 a0,b0
unpkhu4 .L2X b0,b0
unpkhu4 .S1 a0,a0,a0
unpkhu4 .S1 a0,b0
unpkhu4 .S2X b0,b0
unpklu4 .M1 a0,a0
unpklu4 .L1 a0,a0,a0
unpklu4 .L1 a0,b0
unpklu4 .L2X b0,b0
unpklu4 .S1 a0,a0,a0
unpklu4 .S1 a0,b0
unpklu4 .S2X b0,b0
not .M1 a0,a0
not .L1 a0,a0,a0
not .L1 a0,b0
not .L1X a0,a0
not .S1 a0,a0,a0
not .S1 a0,b0
not .S1X a0,a0
not .D1 a0,a0,a0
not .D1 a0,b0
not .D1X a0,a0
xor .M1 a0,a0,a0
xor .L1 a0,a0
xor .L2 b0,b0,a0
xor .L2X b0,b0,b0
xor .L1 -17,a0,a0
xor .L1 16,a0,a0
xor .S1 a0,a0
xor .S2 b0,b0,a0
xor .S2X b0,b0,b0
xor .S1 -17,a0,a0
xor .S1 16,a0,a0
xor .D1 a0,a0
xor .D2 b0,b0,a0
xor .D2X b0,b0,b0
xor .D1 -17,a0,a0
xor .D1 16,a0,a0
xormpy .L1 a0,a0,a0
xormpy .M1 a0,a0
xormpy .M1 b0,a0,a0
xormpy .M1X a0,a0,a0
xpnd2 .S1 a0,a0
xpnd2 .M1 a0,a0,a0
xpnd2 .M1 a0,b0
xpnd2 .M1X a0,a0
xpnd4 .L1 a0,a0
xpnd4 .M1 a0,a0,a0
xpnd4 .M1 a0,b0
xpnd4 .M1X a0,a0
zero .M1 a0
zero .L1 a0,a0
zero .L2 a0
zero .D1 a0,a0
zero .D2 a0
zero .S1 a0,a0
zero .S2 a0
sub .L1 a0,17,a0
sub .L1 a0,-16,a0
sub .L1 a1:a0,17,a1:a0
sub .L1 a1:a0,-16,a1:a0
sub .S1 a0,17,a0
sub .S1 a0,-16,a0
addab .D1X b13,0,a5
addah .D1X b13,0,a5
addaw .D1X b13,0,a5
|
tactcomplabs/xbgas-binutils-gdb
| 1,151
|
gas/testsuite/gas/tic6x/insns-c674x-sploop.s
|
# Test C674x SPLOOP instructions. The present tests are placeholders
# to verify encoding that may not be valid when the full set of checks
# for invalid input are implemented and may need changing to valid
# code at that point.
.text
.nocmp
.globl f
f:
spmask
spmask l1
spmask L2
spmask s1
spmask S2
spmask D1
spmask d2
spmask M1
spmask m2
spmask D1,L1
spmask L1,D1
spmask L1,S1,D1,M1,M2,D2,S2,L2
spmask M1
||^ mv .L1 a0,a1
|| mv .D2 b0,b1
||^ mv .S1 a2,a3
spmaskr
spmaskr l1
spmaskr L2
spmaskr s1
spmaskr S2
spmaskr D1
spmaskr d2
spmaskr M1
spmaskr m2
spmaskr D1,L1
spmaskr L1,D1
spmaskr L1,S1,D1,M1,M2,D2,S2,L2
spmaskr M1
||^ mv .L1 a0,a1
|| mv .D2 b0,b1
||^ mv .S1 a2,a3
[a0] sploop 1
nop
spkernelr
[b0] sploopd 1
nop
spkernel
[!a0] sploopw 1
nop
spkernel
sploop 1
nop
spkernel 0,0
sploop 1
nop
spkernel 63,0
sploop 2
nop
spkernel 31,0
sploop 2
nop
spkernel 31,1
sploop 3
nop
spkernel 15,2
sploop 4
nop
spkernel 15,3
sploop 5
nop
spkernel 7,4
sploop 8
nop
spkernel 7,7
sploop 9
nop
spkernel 3,8
sploop 14
nop
spkernel 3,13
sploop 1
nop
spkernel 8,0
sploop 2
nop
spkernel 6,0
|
tactcomplabs/xbgas-binutils-gdb
| 1,317
|
gas/testsuite/gas/tic6x/insns16-s-unit-pcrel.s
|
; Test C64x+ S-unit pcrel compact instruction formats
.text
nop
.align 16
nop
.align 16
sbs7:
.short 0x000a
.short 0x004a
.short 0x214b
.short 0x428a
.short 0x63cb
.short 0x840a
.short 0xa54b
.short 0x868a
.short 0x77cb
.short 0x580a
.short 0x394b
.short 0x1a8a
.short 0x3bcb
.short 0x5c0a
.word 0xefe00000 | 0x8000
sbu8:
.short 0xcaca
.short 0xe7cb
.short 0xf84a
.short 0xcacb
.short 0xd84a
.short 0xf18b
.short 0xe84a
.short 0xd10b
.short 0xc74a
.short 0xeacb
.short 0xd18a
.short 0xea4b
.short 0xda4a
.short 0xd7cb
.word 0xefe00000 | 0x8000
scs10:
.short 0x0f1a
.short 0x1e5b
.short 0x2d9a
.short 0x3cdb
.short 0x4b9a
.short 0x5a5b
.short 0x691a
.short 0x785b
.short 0x879a
.short 0x96db
.short 0xa59a
.short 0xb45b
.short 0xc31a
.short 0xd2db
.word 0xefe00000 | 0x8000
sbs7c:
.short 0x002a
.short 0x216b
.short 0x427b
.short 0x637a
.short 0x846b
.short 0xa52a
.short 0x06bb
.short 0x07ba
.short 0x38ab
.short 0x592a
.short 0x7afb
.short 0x9bfa
.short 0xbceb
.short 0x0f2a
.word 0xefe00000 | 0x8000
sbu8c:
.short 0xc02a
.short 0xd16b
.short 0xd27b
.short 0xd37a
.short 0xc46b
.short 0xe52a
.short 0xe6bb
.short 0xe7ba
.short 0xc8ab
.short 0xf92a
.short 0xfafb
.short 0xfbfa
.short 0xcceb
.short 0xcf2a
.word 0xefe00000 | 0x8000
|
tactcomplabs/xbgas-binutils-gdb
| 2,636
|
gas/testsuite/gas/tic6x/insns-c674x-pcrel.s
|
# Test C674x instructions generating PC-relative relocations.
.text
.nocmp
.globl ext1
.globl ext2
.globl ext3
.globl a1
.globl b1
.globl irp
.globl nrp
f:
nop
nop
nop
nop
nop
nop
nop
addkpc .S2 f,b1,3
[a2] addkpc .S2 f+4,b3,7
addkpc .S2 g,b4,0
addkpc .S2 ext1+8,b5,4
g:
nop
nop
nop
nop
nop
f2:
nop
nop
b .S2 ext3+4
b .S1 ext2
b .S2 (nrp)
b .S2 (irp)
b .S1 (a1)
b .S2 f2
[b2] b .S2 f2+4
b .S2 g2
b .S2 (b1)
g2:
nop
nop
nop
nop
nop
f3:
nop
nop
call .S2 ext3+4
call .S1 ext2
call .S2 (nrp)
call .S2 (irp)
call .S1 (a1)
call .S2 f3
[b2] call .S2 f3+4
call .S2 g3
call .S2 (b1)
g3:
nop
nop
nop
nop
nop
f4:
nop
nop
bdec .S2 ext3+4,b2
bdec .S1 ext2,a2
bdec .S2 (nrp),b2
bdec .S2 (irp),b2
bdec .S1 (a1),a2
bdec .S2 f4,b2
[!a1] bdec .S2 f4+4,b2
bdec .S2 g4,b2
bdec .S2 (b1),b2
g4:
nop
nop
nop
nop
nop
f5:
nop
nop
bpos .S2 ext3+4,b2
bpos .S1 ext2,a2
bpos .S2 (nrp),b2
bpos .S2 (irp),b2
bpos .S1 (a1),a2
bpos .S2 f5,b2
[!b1] bpos .S2 f5+4,b2
bpos .S2 g5,b2
bpos .S2 (b1),b2
g5:
nop
nop
nop
nop
nop
f6:
nop
nop
bnop .S2 ext3+4,0
bnop .S1 ext2,1
bnop (nrp),2
bnop .S2 (irp),3
bnop .S1 (a1),4
bnop .S2 f6,5
[!b1] bnop .S2 f6+4,6
bnop g6,7
bnop .S2 (b1),0
g6:
nop
nop
nop
nop
nop
f7:
nop
nop
callnop .S2 ext3+4,0
callnop .S1 ext2,1
callnop (nrp),2
callnop .S2 (irp),3
callnop .S1 (a1),4
callnop .S2 f7,5
[a0] callnop .S2 f7+4,6
callnop g7,7
callnop .S2 (b1),0
g7:
nop
nop
nop
nop
nop
f8:
nop
nop
callp .S2 ext3+4,b3
callp .S1 ext2,a3
callp .S1 (nrp),a3
callp .S2 (irp),b3
callp .S1 (a1),a3
callp .S2 f8,b3
callp .S2 f8+4,b3
callp .S1 g8,a3
callp .S2 (b1),b3
g8:
nop
nop
nop
nop
nop
f9:
nop
nop
callret .S2 ext3+4
callret .S1 ext2
callret .S2 (nrp)
callret .S2 (irp)
callret .S1 (a1)
callret .S2 f9
[b2] callret .S2 f9+4
callret .S2 g9
callret .S2 (b1)
g9:
nop
nop
nop
nop
nop
f10:
nop
nop
ret .S2 ext3+4
ret .S1 ext2
ret .S2 (nrp)
ret .S2 (irp)
ret .S1 (a1)
ret .S2 f10
[b2] ret .S2 f10+4
ret .S2 g10
ret .S2 (b1)
g10:
nop
nop
nop
nop
nop
f11:
nop
nop
retp .S2 ext3+4,b3
retp .S1 ext2,a3
retp .S1 (nrp),a3
retp .S2 (irp),b3
retp .S1 (a1),a3
retp .S2 f11,b3
retp .S2 f11+4,b3
retp .S1 g11,a3
retp .S2 (b1),b3
g11:
nop
nop
nop
nop
nop
g12:
.word 0x3014a120
.word 0x2010a120
.word 0x00000410
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
.word 0x80801021
nop
nop
nop
nop
nop
nop
nop
nop
nop
g13:
.word 0x3014a120
.word 0x2010a120
.word 0x00000410
nop
nop
nop
nop
.word 0xe0000000
nop
nop
nop
nop
nop
nop
.word 0x80801021
.word 0xe0000000
|
tactcomplabs/xbgas-binutils-gdb
| 1,536
|
gas/testsuite/gas/tic6x/insns16-lsd-unit.s
|
; Test C64x+ L, S or D-unit compact instruction formats
.text
nop
.align 16
nop
.align 16
lsdmvto:
.short 0x0006
.short 0x000f
.short 0x0016
.short 0x0017
.short 0x000e
.short 0x0007
.short 0x0006
.short 0x100f
.short 0x1016
.short 0x1017
.short 0x100e
.short 0x1007
.short 0x1006
.short 0x100f
.word 0xefe00000 | 0x0000
lsdmvfr:
.short 0x0046
.short 0x004f
.short 0x0056
.short 0x0057
.short 0x004e
.short 0x0047
.short 0x0046
.short 0x104f
.short 0x1056
.short 0x1057
.short 0x104e
.short 0x1047
.short 0x1046
.short 0x104f
.word 0xefe00000 | 0x0000
lsdx1c:
.short 0x0866
.short 0x4967
.short 0x8ae6
.short 0xcbe7
.short 0x886e
.short 0x496f
.short 0x0aee
.short 0x6bef
.short 0xa876
.short 0xe977
.short 0xaaf6
.short 0x6bf7
.short 0x2866
.short 0x6967
.word 0xefe00000 | 0x0000
lsdx1:
.short 0x1866
.short 0x1867
.short 0x1866
.short 0x3867
.short 0x3866
.short 0x3877
.short 0x3876
.short 0xb877
.short 0xb876
.short 0xb86f
.short 0xf86e
.short 0xf86f
.short 0xf86e
.short 0xf86f
.word 0xefe00000 | 0x0000
|
tactcomplabs/xbgas-binutils-gdb
| 10,680
|
gas/testsuite/gas/z8k/inout.s
|
.text
in r1,#0x4444
inb rh3,#0x123
in r8,@r0
in r9,@r1
in r10,@r2
in r11,@r3
in r12,@r4
in r13,@r5
in r14,@r6
in r15,@r7
in r0,@r8
in r1,@r9
in r2,@r10
in r3,@r11
in r4,@r12
in r5,@r13
in r6,@r14
in r7,@r15
inb rh0,@r0
inb rh1,@r1
inb rh2,@r2
inb rh3,@r3
inb rh4,@r4
inb rh5,@r5
inb rh6,@r6
inb rh7,@r7
inb rl0,@r8
inb rl1,@r9
inb rl2,@r10
inb rl3,@r11
inb rl4,@r12
inb rl5,@r13
inb rl6,@r14
inb rl7,@r15
ind @r3,@r15,r8
ind @r1,@r14,r7
ind @r2,@r13,r6
ind @r3,@r12,r5
ind @r4,@r11,r0
ind @r5,@r10,r4
ind @r6,@r9,r3
ind @r7,@r8,r2
ind @r8,@r7,r1
ind @r9,@r6,r15
ind @r10,@r5,r14
ind @r11,@r4,r13
ind @r12,@r3,r11
ind @r13,@r2,r12
ind @r14,@r1,r10
ind @r15,@r0,r9
indb @r3,@r15,r8
indb @r1,@r14,r7
indb @r2,@r13,r6
indb @r3,@r12,r5
indb @r4,@r11,r0
indb @r5,@r10,r4
indb @r6,@r9,r3
indb @r7,@r8,r2
indb @r8,@r7,r1
indb @r9,@r6,r15
indb @r10,@r5,r14
indb @r11,@r4,r13
indb @r12,@r3,r11
indb @r13,@r2,r12
indb @r14,@r1,r10
indb @r15,@r0,r9
indr @r3,@r15,r8
indr @r1,@r14,r7
indr @r2,@r13,r6
indr @r3,@r12,r5
indr @r4,@r11,r0
indr @r5,@r10,r4
indr @r6,@r9,r3
indr @r7,@r8,r2
indr @r8,@r7,r1
indr @r9,@r6,r15
indr @r10,@r5,r14
indr @r11,@r4,r13
indr @r12,@r3,r11
indr @r13,@r2,r12
indr @r14,@r1,r10
indr @r15,@r0,r9
indrb @r3,@r15,r8
indrb @r1,@r14,r7
indrb @r2,@r13,r6
indrb @r3,@r12,r5
indrb @r4,@r11,r0
indrb @r5,@r10,r4
indrb @r6,@r9,r3
indrb @r7,@r8,r2
indrb @r8,@r7,r1
indrb @r9,@r6,r15
indrb @r10,@r5,r14
indrb @r11,@r4,r13
indrb @r12,@r3,r11
indrb @r13,@r2,r12
indrb @r14,@r1,r10
indrb @r15,@r0,r9
ini @r3,@r15,r8
ini @r1,@r14,r7
ini @r2,@r13,r6
ini @r3,@r12,r5
ini @r4,@r11,r0
ini @r5,@r10,r4
ini @r6,@r9,r3
ini @r7,@r8,r2
ini @r8,@r7,r1
ini @r9,@r6,r15
ini @r10,@r5,r14
ini @r11,@r4,r13
ini @r12,@r3,r11
ini @r13,@r2,r12
ini @r14,@r1,r10
ini @r15,@r0,r9
inib @r3,@r15,r8
inib @r1,@r14,r7
inib @r2,@r13,r6
inib @r3,@r12,r5
inib @r4,@r11,r0
inib @r5,@r10,r4
inib @r6,@r9,r3
inib @r7,@r8,r2
inib @r8,@r7,r1
inib @r9,@r6,r15
inib @r10,@r5,r14
inib @r11,@r4,r13
inib @r12,@r3,r11
inib @r13,@r2,r12
inib @r14,@r1,r10
inib @r15,@r0,r9
inir @r3,@r15,r8
inir @r1,@r14,r7
inir @r2,@r13,r6
inir @r3,@r12,r5
inir @r4,@r11,r0
inir @r5,@r10,r4
inir @r6,@r9,r3
inir @r7,@r8,r2
inir @r8,@r7,r1
inir @r9,@r6,r15
inir @r10,@r5,r14
inir @r11,@r4,r13
inir @r12,@r3,r11
inir @r13,@r2,r12
inir @r14,@r1,r10
inir @r15,@r0,r9
inirb @r3,@r15,r8
inirb @r1,@r14,r7
inirb @r2,@r13,r6
inirb @r3,@r12,r5
inirb @r4,@r11,r0
inirb @r5,@r10,r4
inirb @r6,@r9,r3
inirb @r7,@r8,r2
inirb @r8,@r7,r1
inirb @r9,@r6,r15
inirb @r10,@r5,r14
inirb @r11,@r4,r13
inirb @r12,@r3,r11
inirb @r13,@r2,r12
inirb @r14,@r1,r10
inirb @r15,@r0,r9
out #0x1234,r3
outb #0x123,rl2
out @r0,r8
out @r1,r9
out @r2,r10
out @r3,r11
out @r4,r12
out @r5,r13
out @r6,r14
out @r7,r15
out @r8,r0
out @r9,r1
out @r10,r2
out @r11,r3
out @r12,r4
out @r13,r5
out @r14,r6
out @r15,r7
outb @r0,rh0
outb @r1,rh1
outb @r2,rh2
outb @r3,rh3
outb @r4,rh4
outb @r5,rh5
outb @r6,rh6
outb @r7,rh7
outb @r8,rl0
outb @r9,rl1
outb @r10,rl2
outb @r11,rl3
outb @r12,rl4
outb @r13,rl5
outb @r14,rl6
outb @r15,rl7
outd @r0,@r15,r8
outd @r1,@r14,r7
outd @r2,@r13,r6
outd @r3,@r12,r5
outd @r4,@r11,r0
outd @r5,@r10,r4
outd @r6,@r9,r3
outd @r7,@r8,r2
outd @r8,@r7,r1
outd @r9,@r6,r15
outd @r10,@r5,r14
outd @r11,@r4,r13
outd @r12,@r3,r11
outd @r13,@r2,r12
outd @r14,@r1,r10
outd @r15,@r3,r9
outdb @r0,@r15,r8
outdb @r1,@r14,r7
outdb @r2,@r13,r6
outdb @r3,@r12,r5
outdb @r4,@r11,r0
outdb @r5,@r10,r4
outdb @r6,@r9,r3
outdb @r7,@r8,r2
outdb @r8,@r7,r1
outdb @r9,@r6,r15
outdb @r10,@r5,r14
outdb @r11,@r4,r13
outdb @r12,@r3,r11
outdb @r13,@r2,r12
outdb @r14,@r1,r10
outdb @r15,@r3,r9
otdr @r0,@r15,r8
otdr @r1,@r14,r7
otdr @r2,@r13,r6
otdr @r3,@r12,r5
otdr @r4,@r11,r0
otdr @r5,@r10,r4
otdr @r6,@r9,r3
otdr @r7,@r8,r2
otdr @r8,@r7,r1
otdr @r9,@r6,r15
otdr @r10,@r5,r14
otdr @r11,@r4,r13
otdr @r12,@r3,r11
otdr @r13,@r2,r12
otdr @r14,@r1,r10
otdr @r15,@r3,r9
otdrb @r0,@r15,r8
otdrb @r1,@r14,r7
otdrb @r2,@r13,r6
otdrb @r3,@r12,r5
otdrb @r4,@r11,r0
otdrb @r5,@r10,r4
otdrb @r6,@r9,r3
otdrb @r7,@r8,r2
otdrb @r8,@r7,r1
otdrb @r9,@r6,r15
otdrb @r10,@r5,r14
otdrb @r11,@r4,r13
otdrb @r12,@r3,r11
otdrb @r13,@r2,r12
otdrb @r14,@r1,r10
otdrb @r15,@r3,r9
outi @r0,@r15,r8
outi @r1,@r14,r7
outi @r2,@r13,r6
outi @r3,@r12,r5
outi @r4,@r11,r0
outi @r5,@r10,r4
outi @r6,@r9,r3
outi @r7,@r8,r2
outi @r8,@r7,r1
outi @r9,@r6,r15
outi @r10,@r5,r14
outi @r11,@r4,r13
outi @r12,@r3,r11
outi @r13,@r2,r12
outi @r14,@r1,r10
outi @r15,@r3,r9
outib @r0,@r15,r8
outib @r1,@r14,r7
outib @r2,@r13,r6
outib @r3,@r12,r5
outib @r4,@r11,r0
outib @r5,@r10,r4
outib @r6,@r9,r3
outib @r7,@r8,r2
outib @r8,@r7,r1
outib @r9,@r6,r15
outib @r10,@r5,r14
outib @r11,@r4,r13
outib @r12,@r3,r11
outib @r13,@r2,r12
outib @r14,@r1,r10
outib @r15,@r3,r9
otir @r0,@r15,r8
otir @r1,@r14,r7
otir @r2,@r13,r6
otir @r3,@r12,r5
otir @r4,@r11,r0
otir @r5,@r10,r4
otir @r6,@r9,r3
otir @r7,@r8,r2
otir @r8,@r7,r1
otir @r9,@r6,r15
otir @r10,@r5,r14
otir @r11,@r4,r13
otir @r12,@r3,r11
otir @r13,@r2,r12
otir @r14,@r1,r10
otir @r15,@r3,r9
otirb @r0,@r15,r8
otirb @r1,@r14,r7
otirb @r2,@r13,r6
otirb @r3,@r12,r5
otirb @r4,@r11,r0
otirb @r5,@r10,r4
otirb @r6,@r9,r3
otirb @r7,@r8,r2
otirb @r8,@r7,r1
otirb @r9,@r6,r15
otirb @r10,@r5,r14
otirb @r11,@r4,r13
otirb @r12,@r3,r11
otirb @r13,@r2,r12
otirb @r14,@r1,r10
otirb @r15,@r3,r9
sin r0,#124
sinb rh0,#1266
sind @r3,@r15,r8
sind @r1,@r14,r7
sind @r2,@r13,r6
sind @r3,@r12,r5
sind @r4,@r11,r0
sind @r5,@r10,r4
sind @r6,@r9,r3
sind @r7,@r8,r2
sind @r8,@r7,r1
sind @r9,@r6,r15
sind @r10,@r5,r14
sind @r11,@r4,r13
sind @r12,@r3,r11
sind @r13,@r2,r12
sind @r14,@r1,r10
sind @r15,@r0,r9
sindb @r3,@r15,r8
sindb @r1,@r14,r7
sindb @r2,@r13,r6
sindb @r3,@r12,r5
sindb @r4,@r11,r0
sindb @r5,@r10,r4
sindb @r6,@r9,r3
sindb @r7,@r8,r2
sindb @r8,@r7,r1
sindb @r9,@r6,r15
sindb @r10,@r5,r14
sindb @r11,@r4,r13
sindb @r12,@r3,r11
sindb @r13,@r2,r12
sindb @r14,@r1,r10
sindb @r15,@r0,r9
sindr @r3,@r15,r8
sindr @r1,@r14,r7
sindr @r2,@r13,r6
sindr @r3,@r12,r5
sindr @r4,@r11,r0
sindr @r5,@r10,r4
sindr @r6,@r9,r3
sindr @r7,@r8,r2
sindr @r8,@r7,r1
sindr @r9,@r6,r15
sindr @r10,@r5,r14
sindr @r11,@r4,r13
sindr @r12,@r3,r11
sindr @r13,@r2,r12
sindr @r14,@r1,r10
sindr @r15,@r0,r9
sindrb @r3,@r15,r8
sindrb @r1,@r14,r7
sindrb @r2,@r13,r6
sindrb @r3,@r12,r5
sindrb @r4,@r11,r0
sindrb @r5,@r10,r4
sindrb @r6,@r9,r3
sindrb @r7,@r8,r2
sindrb @r8,@r7,r1
sindrb @r9,@r6,r15
sindrb @r10,@r5,r14
sindrb @r11,@r4,r13
sindrb @r12,@r3,r11
sindrb @r13,@r2,r12
sindrb @r14,@r1,r10
sindrb @r15,@r0,r9
sini @r3,@r15,r8
sini @r1,@r14,r7
sini @r2,@r13,r6
sini @r3,@r12,r5
sini @r4,@r11,r0
sini @r5,@r10,r4
sini @r6,@r9,r3
sini @r7,@r8,r2
sini @r8,@r7,r1
sini @r9,@r6,r15
sini @r10,@r5,r14
sini @r11,@r4,r13
sini @r12,@r3,r11
sini @r13,@r2,r12
sini @r14,@r1,r10
sini @r15,@r0,r9
sinib @r3,@r15,r8
sinib @r1,@r14,r7
sinib @r2,@r13,r6
sinib @r3,@r12,r5
sinib @r4,@r11,r0
sinib @r5,@r10,r4
sinib @r6,@r9,r3
sinib @r7,@r8,r2
sinib @r8,@r7,r1
sinib @r9,@r6,r15
sinib @r10,@r5,r14
sinib @r11,@r4,r13
sinib @r12,@r3,r11
sinib @r13,@r2,r12
sinib @r14,@r1,r10
sinib @r15,@r0,r9
sinir @r3,@r15,r8
sinir @r1,@r14,r7
sinir @r2,@r13,r6
sinir @r3,@r12,r5
sinir @r4,@r11,r0
sinir @r5,@r10,r4
sinir @r6,@r9,r3
sinir @r7,@r8,r2
sinir @r8,@r7,r1
sinir @r9,@r6,r15
sinir @r10,@r5,r14
sinir @r11,@r4,r13
sinir @r12,@r3,r11
sinir @r13,@r2,r12
sinir @r14,@r1,r10
sinir @r15,@r0,r9
sinirb @r3,@r15,r8
sinirb @r1,@r14,r7
sinirb @r2,@r13,r6
sinirb @r3,@r12,r5
sinirb @r4,@r11,r0
sinirb @r5,@r10,r4
sinirb @r6,@r9,r3
sinirb @r7,@r8,r2
sinirb @r8,@r7,r1
sinirb @r9,@r6,r15
sinirb @r10,@r5,r14
sinirb @r11,@r4,r13
sinirb @r12,@r3,r11
sinirb @r13,@r2,r12
sinirb @r14,@r1,r10
sinirb @r15,@r0,r9
sout #0xbeee,r0
soutb #0xbabe,rh4
soutd @r0,@r15,r8
soutd @r1,@r14,r7
soutd @r2,@r13,r6
soutd @r3,@r12,r5
soutd @r4,@r11,r0
soutd @r5,@r10,r4
soutd @r6,@r9,r3
soutd @r7,@r8,r2
soutd @r8,@r7,r1
soutd @r9,@r6,r15
soutd @r10,@r5,r14
soutd @r11,@r4,r13
soutd @r12,@r3,r11
soutd @r13,@r2,r12
soutd @r14,@r1,r10
soutd @r15,@r3,r9
soutdb @r0,@r15,r8
soutdb @r1,@r14,r7
soutdb @r2,@r13,r6
soutdb @r3,@r12,r5
soutdb @r4,@r11,r0
soutdb @r5,@r10,r4
soutdb @r6,@r9,r3
soutdb @r7,@r8,r2
soutdb @r8,@r7,r1
soutdb @r9,@r6,r15
soutdb @r10,@r5,r14
soutdb @r11,@r4,r13
soutdb @r12,@r3,r11
soutdb @r13,@r2,r12
soutdb @r14,@r1,r10
soutdb @r15,@r3,r9
sotdr @r0,@r15,r8
sotdr @r1,@r14,r7
sotdr @r2,@r13,r6
sotdr @r3,@r12,r5
sotdr @r4,@r11,r0
sotdr @r5,@r10,r4
sotdr @r6,@r9,r3
sotdr @r7,@r8,r2
sotdr @r8,@r7,r1
sotdr @r9,@r6,r15
sotdr @r10,@r5,r14
sotdr @r11,@r4,r13
sotdr @r12,@r3,r11
sotdr @r13,@r2,r12
sotdr @r14,@r1,r10
sotdr @r15,@r3,r9
sotdrb @r0,@r15,r8
sotdrb @r1,@r14,r7
sotdrb @r2,@r13,r6
sotdrb @r3,@r12,r5
sotdrb @r4,@r11,r0
sotdrb @r5,@r10,r4
sotdrb @r6,@r9,r3
sotdrb @r7,@r8,r2
sotdrb @r8,@r7,r1
sotdrb @r9,@r6,r15
sotdrb @r10,@r5,r14
sotdrb @r11,@r4,r13
sotdrb @r12,@r3,r11
sotdrb @r13,@r2,r12
sotdrb @r14,@r1,r10
sotdrb @r15,@r3,r9
souti @r0,@r15,r8
souti @r1,@r14,r7
souti @r2,@r13,r6
souti @r3,@r12,r5
souti @r4,@r11,r0
souti @r5,@r10,r4
souti @r6,@r9,r3
souti @r7,@r8,r2
souti @r8,@r7,r1
souti @r9,@r6,r15
souti @r10,@r5,r14
souti @r11,@r4,r13
souti @r12,@r3,r11
souti @r13,@r2,r12
souti @r14,@r1,r10
souti @r15,@r3,r9
soutib @r0,@r15,r8
soutib @r1,@r14,r7
soutib @r2,@r13,r6
soutib @r3,@r12,r5
soutib @r4,@r11,r0
soutib @r5,@r10,r4
soutib @r6,@r9,r3
soutib @r7,@r8,r2
soutib @r8,@r7,r1
soutib @r9,@r6,r15
soutib @r10,@r5,r14
soutib @r11,@r4,r13
soutib @r12,@r3,r11
soutib @r13,@r2,r12
soutib @r14,@r1,r10
soutib @r15,@r3,r9
sotir @r0,@r15,r8
sotir @r1,@r14,r7
sotir @r2,@r13,r6
sotir @r3,@r12,r5
sotir @r4,@r11,r0
sotir @r5,@r10,r4
sotir @r6,@r9,r3
sotir @r7,@r8,r2
sotir @r8,@r7,r1
sotir @r9,@r6,r15
sotir @r10,@r5,r14
sotir @r11,@r4,r13
sotir @r12,@r3,r11
sotir @r13,@r2,r12
sotir @r14,@r1,r10
sotir @r15,@r3,r9
sotirb @r0,@r15,r8
sotirb @r1,@r14,r7
sotirb @r2,@r13,r6
sotirb @r3,@r12,r5
sotirb @r4,@r11,r0
sotirb @r5,@r10,r4
sotirb @r6,@r9,r3
sotirb @r7,@r8,r2
sotirb @r8,@r7,r1
sotirb @r9,@r6,r15
sotirb @r10,@r5,r14
sotirb @r11,@r4,r13
sotirb @r12,@r3,r11
sotirb @r13,@r2,r12
sotirb @r14,@r1,r10
sotirb @r15,@r3,r9
|
tactcomplabs/xbgas-binutils-gdb
| 4,001
|
gas/testsuite/gas/z8k/reglabel.s
|
! labels starting with a valid register name
.text
sp_label: lda r0,sp_label
r0_label: lda r0,r0_label
r1_label: lda r0,r1_label
r2_label: lda r0,r2_label
r3_label: lda r0,r3_label
r4_label: lda r0,r4_label
r5_label: lda r0,r5_label
r6_label: lda r0,r6_label
r7_label: lda r0,r7_label
r8_label: lda r0,r8_label
r9_label: lda r0,r9_label
r10_label: lda r0,r10_label
r11_label: lda r0,r11_label
r12_label: lda r0,r12_label
r13_label: lda r0,r13_label
r14_label: lda r0,r14_label
r15_label: lda r0,r15_label
r16_label: lda r0,r16_label ! not a valid register name anyway
rr0_label: lda r0,rr0_label
rr1_label: lda r0,rr1_label ! not a valid register name anyway
rr2_label: lda r0,rr2_label
rr3_label: lda r0,rr3_label ! not a valid register name anyway
rr4_label: lda r0,rr4_label
rr5_label: lda r0,rr5_label ! not a valid register name anyway
rr6_label: lda r0,rr6_label
rr7_label: lda r0,rr7_label ! not a valid register name anyway
rr8_label: lda r0,rr8_label
rr9_label: lda r0,rr9_label ! not a valid register name anyway
rr10_label: lda r0,rr10_label
rr11_label: lda r0,rr11_label ! not a valid register name anyway
rr12_label: lda r0,rr12_label
rr13_label: lda r0,rr13_label ! not a valid register name anyway
rr14_label: lda r0,rr14_label
rr15_label: lda r0,rr15_label ! not a valid register name anyway
rr16_label: lda r0,rr16_label ! not a valid register name anyway
rq0_label: lda r0,rq0_label
rq1_label: lda r0,rq1_label ! not a valid register name anyway
rq2_label: lda r0,rq2_label ! not a valid register name anyway
rq3_label: lda r0,rq3_label ! not a valid register name anyway
rq4_label: lda r0,rq4_label
rq5_label: lda r0,rq5_label ! not a valid register name anyway
rq6_label: lda r0,rq6_label ! not a valid register name anyway
rq7_label: lda r0,rq7_label ! not a valid register name anyway
rq8_label: lda r0,rq8_label
rq9_label: lda r0,rq9_label ! not a valid register name anyway
rq10_label: lda r0,rq10_label ! not a valid register name anyway
rq11_label: lda r0,rq11_label ! not a valid register name anyway
rq12_label: lda r0,rq12_label
rq13_label: lda r0,rq13_label ! not a valid register name anyway
rq14_label: lda r0,rq14_label ! not a valid register name anyway
rq15_label: lda r0,rq15_label ! not a valid register name anyway
rq16_label: lda r0,rq16_label ! not a valid register name anyway
rh0_label: lda r0,rh0_label
rh1_label: lda r0,rh1_label
rh2_label: lda r0,rh2_label
rh3_label: lda r0,rh3_label
rh4_label: lda r0,rh4_label
rh5_label: lda r0,rh5_label
rh6_label: lda r0,rh6_label
rh7_label: lda r0,rh7_label
rh8_label: lda r0,rh8_label ! not a valid register name anyway
rh9_label: lda r0,rh9_label ! not a valid register name anyway
rh10_label: lda r0,rh10_label ! not a valid register name anyway
rh11_label: lda r0,rh11_label ! not a valid register name anyway
rh12_label: lda r0,rh12_label ! not a valid register name anyway
rh13_label: lda r0,rh13_label ! not a valid register name anyway
rh14_label: lda r0,rh14_label ! not a valid register name anyway
rh15_label: lda r0,rh15_label ! not a valid register name anyway
rh16_label: lda r0,rh16_label ! not a valid register name anyway
rl0_label: lda r0,rl0_label
rl1_label: lda r0,rl1_label
rl2_label: lda r0,rl2_label
rl3_label: lda r0,rl3_label
rl4_label: lda r0,rl4_label
rl5_label: lda r0,rl5_label
rl6_label: lda r0,rl6_label
rl7_label: lda r0,rl7_label
rl8_label: lda r0,rl8_label ! not a valid register name anyway
rl9_label: lda r0,rl9_label ! not a valid register name anyway
rl10_label: lda r0,rl10_label ! not a valid register name anyway
rl11_label: lda r0,rl11_label ! not a valid register name anyway
rl12_label: lda r0,rl12_label ! not a valid register name anyway
rl13_label: lda r0,rl13_label ! not a valid register name anyway
rl14_label: lda r0,rl14_label ! not a valid register name anyway
rl15_label: lda r0,rl15_label ! not a valid register name anyway
rl16_label: lda r0,rl16_label ! not a valid register name anyway
r00_label: lda r0,r00_label ! not a valid register name anyway
|
tactcomplabs/xbgas-binutils-gdb
| 2,266
|
gas/testsuite/gas/xgate/all_insns.s
|
# Example of XGATE instructions
.sect .text
_start:
L0: adc r1, r2, r3
L1: bcc END_CODE
L2: add r4, r5, r6
L3: add r7 , #225
L4: addh r1, 255
L5: addl r2, #255
L6: add r4, 8004
L7: and r3, r4, r5
L8: and r1, #0x8004
L9: add r5, END_CODE
L10: and r7, END_CODE
L11: and r4, #65281
L12: andl r3, #01
L13: andh r6, #255
L14: asr r0, #3
L15: asr r1, r2
L16: bcc END_CODE
L17: bcs END_CODE
L18: beq END_CODE
L19: bfext r3, r4, r5
L20: bffo r6, r7
L21: bfins r0, r1, r2
L22: bfinsi r3, r4, r5
L23: bfinsx r6, r7, r0
L24: bge END_CODE
L25: bgt END_CODE
L26: bhi END_CODE
L27: bhs END_CODE
L28: bith r1, #32
L29: bitl r2, #0
L30: ble END_CODE
L31: blo END_CODE
L32: bls END_CODE
L33: blt END_CODE
L34: bmi END_CODE
L35: bne END_CODE
L36: bpl END_CODE
L37: bra END_CODE
L38: brk
L39: bvc END_CODE
L40: bvs END_CODE
L41: cmp r1, r2
L42: cmpl r3, #255
L43: com r4, r5
L44: cpc r6, r7
L45: cmp r1, #65535
L46: cpch r2, #255
L47: csem #4
L48: csem r5
L49: csl r6, #11
L50: csl r7, r0
L51: csr r1, #2
L52: csr r2, r3
L53: jal r4
L54: ldb r5, (r6, #20)
L55: ldb r7, (r0, r1+)
L56: ldb r7, (r0, -r1)
L57: ldb r0, (r0, r0)
L58: ldh r1, #255
L59: ldl r2, #255
L60: ldd r3, END_CODE
L61: ldw r4, (r5, #20)
L62: ldw r5, (r6, r7+)
L63: ldw r5, (r6, -r7)
L64: ldw r1, (r2, r4)
L65: lsl r1, #4
L66: lsl r2, r3
L67: lsr r4, #5
L68: lsr r5, r6
L69: mov r6, r7
L70: neg r1, r2
L71: nop
L72: or r1, r2, r3
L73: orh r4, #255
L74: orl r5, #255
L75: par r6
L76: rol r7, #6
L77: rol r1, r2
L78: ror r3, #5
L79: ror r4, r5
L80: rts
L81: sbc r1, r2, r3
L82: ssem #4
L83: ssem r1
L84: sex r2
L85: sif
L86: sif r4
L87: stb r5, (r6, #5)
L88: stb r0, (r0, r0+)
L89: stb r0, (r0, -r0)
L90: stb r2, (r0, r0)
L91: stw r1, (r2, #16)
L92: stw r1, (r2, r3+)
L93: stw r1, (r2, -r3)
L94: stw r2, (r3 ,r4)
L95: sub r3, r4, r6
L96: sub r4, #65535
L97: subh r5, #255
L98: subl r6, #255
L99: tfr r7, pc
L100: tfr r7,ccr
L101: tfr ccr, r7
L102: tst r1
L103: xnor r1, r2, r3
L104: xnorh r4, #255
L105: xnorl r5, #255
L106: com r3
END_CODE:
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