repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
tactcomplabs/xbgas-binutils-gdb | 3,377 | gas/testsuite/gas/d30v/opt.s | # D30V parallel optimization test
# assemble with "-O"
.text
start:
abs r1,r2
abs r3,r4
notfg f0,f4
notfg f1,f2
abs r1,r2
notfg f1,f2
# both change C flag
add r1,r2,r3
notfg C,f0
# one uses and one changes C flag
add r1,r2,r3
notfg f0,C
bra .
abs r1,r2
abs r1,r2
bra .
bsr .
abs r1,r2
a... |
tactcomplabs/xbgas-binutils-gdb | 7,078 | gas/testsuite/gas/d30v/inst.s | # test all instructions
start:
abs r21,r42
add r1,r2,r3
add r50,r51,0x1a
add r50,r51,0xdeadbeef
add2h r1,r2,r3
add2h r50,r51,0x1a
add2h r50,r51,0xdeadbeef
addc r1,r2,r3
addc r50,r51,0x1a
addc r50,r51,0xdeadbeef
addhlll r1,r2,r3
addhlll r50,r51,0x1a
addhlll r50,r51,0xdeadbeef
addhllh r1,r2,r3
addhll... |
tactcomplabs/xbgas-binutils-gdb | 1,394 | gas/testsuite/gas/mn10300/am33_6.s | .text
.am33
add_add r4,r1,r2,r3
add_add r4,r1,2,r3
add_sub r4,r1,r2,r3
add_sub r4,r1,2,r3
add_cmp r4,r1,r2,r3
add_cmp r4,r1,2,r3
add_mov r4,r1,r2,r3
add_mov r4,r1,2,r3
add_asr r4,r1,r2,r3
add_asr r4,r1,2,r3
add_lsr r4,r1,r2,r3
add_lsr r4,r1,2,r3
add_asl r4,r1,r2,r3
add_asl r4,r1,2,r3
cmp_add r4,r1,r2,r... |
tactcomplabs/xbgas-binutils-gdb | 26,639 | gas/testsuite/gas/mn10300/am33-2.s | .text
.am33_2
dcpf:
dcpf (r0)
dcpf (r10)
dcpf (d1)
dcpf (r7)
dcpf (e4)
dcpf (d2)
dcpf (r1)
dcpf (r11)
dcpf (a0)
dcpf (r2)
dcpf (e5)
dcpf (sp)
dcpf (d3, r12)
dcpf (a1, r3)
dcpf (a2, r13)
dcpf (r4, r14)
dcpf (a3, r8)
dcpf (r5, r15)
dcpf (r6, r9)
dcpf (r0, r10)
dcpf (r7, e4)
dcpf (r1, r11)
dcpf (r... |
tactcomplabs/xbgas-binutils-gdb | 1,358 | gas/testsuite/gas/mn10300/am33_5.s | .text
.am33
mov 0x7ffefdfc,r2
movu 0x7ffefdfc,r2
add 0x7ffefdfc,r2
addc 0x7ffefdfc,r2
sub 0x7ffefdfc,r2
subc 0x7ffefdfc,r2
cmp 0x7ffefdfc,r2
mov 0x7ffefdfc,xr2
and 0x7ffefdfc,r2
or 0x7ffefdfc,r2
xor 0x7ffefdfc,r2
asr 0x7ffefdfc,r2
lsr 0x7ffefdfc,r2
asl 0x7ffefdfc,r2
mul 0x7ffefdfc,r2
mulu 0x7ffefdfc,r... |
tactcomplabs/xbgas-binutils-gdb | 1,411 | gas/testsuite/gas/mn10300/am33_8.s | .text
.am33
xor_add r4,r1,r2,r3
xor_add r4,r1,2,r3
xor_sub r4,r1,r2,r3
xor_sub r4,r1,2,r3
xor_cmp r4,r1,r2,r3
xor_cmp r4,r1,2,r3
xor_mov r4,r1,r2,r3
xor_mov r4,r1,2,r3
xor_asr r4,r1,r2,r3
xor_asr r4,r1,2,r3
xor_lsr r4,r1,r2,r3
xor_lsr r4,r1,2,r3
xor_asl r4,r1,r2,r3
xor_asl r4,r1,2,r3
swhw_add r4,r1,r2,... |
tactcomplabs/xbgas-binutils-gdb | 1,943 | gas/testsuite/gas/mn10300/udf.s | .text
udf00 d0,d1
udf01 d0,d1
udf02 d0,d1
udf03 d0,d1
udf04 d0,d1
udf05 d0,d1
udf06 d0,d1
udf07 d0,d1
udf08 d0,d1
udf09 d0,d1
udf10 d0,d1
udf11 d0,d1
udf12 d0,d1
udf13 d0,d1
udf14 d0,d1
udf15 d0,d1
udf20 d0,d1
udf21 d0,d1
udf22 d0,d1
udf23 d0,d1
udf24 d0,d1
udf25 d0,d1
udf26 d0,d1
udf27 d0,d1
... |
tactcomplabs/xbgas-binutils-gdb | 1,089 | gas/testsuite/gas/mn10300/relax.s | .am33_2
.section .rlcb, "ax"
.global relax_long_cond_branch
relax_long_cond_branch:
clr d0
clr d1
.L1:
add d1,d0
inc d1
.fill 32764, 1, 0xcb
cmp 9,d1
ble .L1
rets
.section .rlfcb, "ax"
.global relax_long_float_cond_branch
relax_long_float_cond_branch:
clr d0
clr d1
.L2:
add d1,d0
inc d1
.fill... |
tactcomplabs/xbgas-binutils-gdb | 1,397 | gas/testsuite/gas/mn10300/am33_7.s | .text
.am33
cmp_add 4,r1,r2,r3
cmp_add 4,r1,2,r3
cmp_sub 4,r1,r2,r3
cmp_sub 4,r1,2,r3
cmp_mov 4,r1,r2,r3
cmp_mov 4,r1,2,r3
cmp_asr 4,r1,r2,r3
cmp_asr 4,r1,2,r3
cmp_lsr 4,r1,r2,r3
cmp_lsr 4,r1,2,r3
cmp_asl 4,r1,r2,r3
cmp_asl 4,r1,2,r3
sub_add 4,r1,r2,r3
sub_add 4,r1,2,r3
sub_sub 4,r1,r2,r3
sub_sub 4,r1... |
tactcomplabs/xbgas-binutils-gdb | 2,845 | gas/testsuite/gas/pdp11/opcode.s | # Opcode test for PDP-11.
# Copyright (C) 2002-2022 Free Software Foundation, Inc.
#
# This file is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later... |
tactcomplabs/xbgas-binutils-gdb | 1,739 | gas/testsuite/gas/avr/gccisr-01.s | .text
;;; Use SREG
__start1:
set
__vec1_start:
__gcc_isr 1
foo = __gcc_isr.n_pushed
cpi r16,1
__gcc_isr 2
__gcc_isr 0,r0
clt
__vec1_end:
__data1:
ldi r16, foo - 2
.word (__vec1_end - __vec1_start) / 2
;;; Nothing used.
__start2:
set
__vec2_start:
__gcc_isr 1
foo = _... |
tactcomplabs/xbgas-binutils-gdb | 377,321 | gas/testsuite/gas/metag/metacore21.s | .text
MOV D0Re0,D0Re0
MOV D0Re0,RD
ADD D0Re0,D0.7,D1.7
ADD D0.7,D0Re0,A1.7
ADD D0.7,D0.7,D0Re0
ADD D0.7,D0.7,A0.7
ADD D1Re0,D1Re0,D0.7
... |
tactcomplabs/xbgas-binutils-gdb | 99,203 | gas/testsuite/gas/metag/metafpu21.s | .text
F ADD FX.0,D0Re0,D0Re0
F ADDLT FX.0,D0Re0,D0.7
F ADDVS FX.0,D0Re0,RD
F ADDHI FX.0,D0.7,A1LbP
F ADD FX.0,D0.7,D1.7
F ADDLE FX.0,D0.7,A0FrP
F ADDEQ FX.1,D0Re0,D0.7
... |
tactcomplabs/xbgas-binutils-gdb | 1,510,387 | gas/testsuite/gas/metag/metadsp21.s | .text
D ADD D0Re0,D0Re0,D0Re0
DO ADD D0Re0,D0Re0,D0Re0
D ADD D0Re0,D0Re0,A1LbP
DM ADD D0Re0,D0Re0,A1.7
DO MOV D0Re0,D0.7
D ADD D0Re0,D0Re0,D1Re0
D ADD D0Re0,D0Re... |
tactcomplabs/xbgas-binutils-gdb | 6,479 | gas/testsuite/gas/metag/metafpu21ext.s | .text
FD ABS FX.0,FX.2
F ABS FX.3,FX.0
FL ABS FX.6,FX.4
F MMOVD D1.0,D1.3,D1.7,FX.0,FX.1,FX.2
F MMOVD D0.0,D0.1,FX.8,FX.9
F MMOVL D0.0,D0.1,D0.7,FX.2,FX.4,FX.6
F MMOVL D1.3,D1.4,FX.0,FX.2
F MMOVD FX.0,FX.1,FX.2,... |
tactcomplabs/xbgas-binutils-gdb | 316,000 | gas/testsuite/gas/metag/metacore12.s | .text
MOV D0Re0,D0Re0
MOV D0Re0,RD
ADD D0Re0,D0.7,D1.7
ADD D0.7,D0Re0,A1.7
ADD D0.7,D0.7,D0Re0
ADD D0.7,D0.7,A0.7
ADD D1Re0,D1Re0,D0.7
... |
tactcomplabs/xbgas-binutils-gdb | 21,991 | gas/testsuite/gas/mep/dj1.s |
mov $0,$0
mov $1,$0
mov $2,$0
mov $3,$0
mov $4,$0
mov $5,$0
mov $6,$0
mov $7,$0
mov $8,$0
mov $9,$0
mov $10,$0
mov $11,$0
mov $12,$0
mov $13,$0
mov $14,$0
mov $15,$0
mov $fp,$0
mov $tp,$0
mov $gp,$0
mov $sp,$0
sb $0,($0)
sh $0,($0)
sw $0,($0)
lb $0,($0)
lh $0,($0)
lw $0,($0)
lbu $0,($0)
... |
tactcomplabs/xbgas-binutils-gdb | 21,767 | gas/testsuite/gas/mep/allinsn.s | .data
foodata: .word 42
.text
footext:
.text
.global sb
sb:
sb $7,($fp)
sb $5,($9)
sb $7,($14)
sb $14,($fp)
sb $15,($14)
.text
.global sh
sh:
sh $3,($fp)
sh $12,($1)
sh $13,($2)
sh $2,($8)
sh $12,($10)
.text
.global sw
sw:
sw $11,($0)
sw $3,($7)
sw $13,($14)
sw $8,($9)
sw $gp,($fp)
.text
.globa... |
tactcomplabs/xbgas-binutils-gdb | 2,164 | gas/testsuite/gas/m32r/signed-relocs.s | ; check: not case sensitive for special operand modifier
; check: shigh, high, low
.text
relocs:
seth r0, #shigh(0x87654321)
add3 r0, r0, #low(0x87654321)
seth r0, #SHIGH(0x87654321)
add3 r0, r0, #LOW(0x87654321)
seth r0, #shigh(0x1234ffff)
add3 r0, r0, #low(0x1234ffff)
seth r0, #SHIGH(0x1234ffff)
add3 r0, r... |
tactcomplabs/xbgas-binutils-gdb | 7,440 | gas/testsuite/gas/m32r/m32rx.s | # Test new instructions
branchpoint:
.text
.global bcl
bcl:
bcl branchpoint
.text
.global bncl
bncl:
bncl branchpoint
.text
.global cmpz
cmpz:
cmpz fp
.text
.global cmpeq
cmpeq:
cmpeq fp, fp
.text
.global maclh1
maclh1:
maclh1 fp, fp
.text
.global macsl0
msblo:
msblo fp, fp
.text
.global m... |
tactcomplabs/xbgas-binutils-gdb | 1,966 | gas/testsuite/gas/m32r/outofrange.s | ; Test error messages where branches are out of range.
; { dg-do assemble { target m32r-*-* } }
.text
.global foo
foo:
bl.s label
; { dg-error "out of range" "out of range bl.s" { target *-*-* } { 8 } }
bnc.s label
; { dg-error "out of range" "out of range bnc.s" { target *-*-* } { 10 } }
bra.s label
; { d... |
tactcomplabs/xbgas-binutils-gdb | 1,056 | gas/testsuite/gas/m32r/pic2.s | .section .text
# R_M32R_GOTPC24
pic_gotpc:
bl.s .+4
ld24 r12,#_GLOBAL_OFFSET_TABLE_
add r12,lr
# R_M32R_GOTPC_HI_ULO
# R_M32R_GOTPC_HI_SLO
# R_M32R_GOTPC_LO
pic_gotpc_slo:
bl.s .+4
seth r12,#shigh(_GLOBAL_OFFSET_TABLE_)
add3 r12,r12,#low(_GLOBAL_OFFSET_TABLE_+4)
add r12,lr
pic_gotpc_ulo:
... |
tactcomplabs/xbgas-binutils-gdb | 5,133 | gas/testsuite/gas/m32r/allinsn.s | .data
foodata: .word 42
.text
footext:
.text
.global add
add:
add fp,fp
.text
.global add3
add3:
add3 fp,fp,#0
.text
.global and
and:
and fp,fp
.text
.global and3
and3:
and3 fp,fp,#0
.text
.global or
or:
or fp,fp
.text
.global or3
or3:
or3 fp,fp,#0
.text
.global xor
xor:
xor fp,fp
.text
.global... |
tactcomplabs/xbgas-binutils-gdb | 1,619 | gas/testsuite/gas/m32r/m32r2.s | # Test new instructions
.text
.global setpsw
setpsw:
setpsw 0xc1
setpsw 0xff
.text
.global clrpsw
clrpsw:
clrpsw 0xc1
clrpsw 0xff
.text
.global bset
bset:
bset #0,@(4,r1)
bset #1,@(4,r1)
bset #7,@(4,r1)
.text
.global bclr
bclr:
bclr #0,@(4,r1)
bclr #1,@(4,r1)
bclr #7,@(4,r1)
.text
.global btst... |
tactcomplabs/xbgas-binutils-gdb | 1,328 | gas/testsuite/gas/elf/dwarf2-5.s | /* Test view numbering.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any... |
tactcomplabs/xbgas-binutils-gdb | 5,257 | gas/testsuite/gas/elf/dwarf2-1.s | /* This testcase is derived from a similar test in GDB.
Copyright (C) 2009-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the Lic... |
tactcomplabs/xbgas-binutils-gdb | 5,382 | gas/testsuite/gas/elf/dwarf2-2.s | /* This testcase is derived from a similar test in GDB.
Copyright (C) 2009-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the Lic... |
tactcomplabs/xbgas-binutils-gdb | 2,789 | gas/testsuite/gas/elf/dwarf2-3.s | .file "beginwarn.c"
.section .debug_abbrev,"",%progbits
.Ldebug_abbrev0:
.section .debug_info,"",%progbits
.Ldebug_info0:
.section .debug_line,"",%progbits
.Ldebug_line0:
.text
.Ltext0:
.section .init_array
.align 4
.type init_array, %object
.size init_array, 4
init_array:
.long foo
.section .gnu.warning.foo... |
tactcomplabs/xbgas-binutils-gdb | 1,138 | gas/testsuite/gas/elf/dwarf2-10.s | /* Test view numbering zero-assert checking with zero-sized align.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3... |
tactcomplabs/xbgas-binutils-gdb | 2,486 | gas/testsuite/gas/elf/dwarf2-6.s | /* Test view number decoding.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your optio... |
tactcomplabs/xbgas-binutils-gdb | 1,654 | gas/testsuite/gas/elf/dwarf-5-file0-2.s | .file "test.c"
.text
.Ltext0:
.file 0 "/example" "test.c"
.globl x
.section .bss
.balign 4
.type x, %object
.size x, 4
x:
.zero 4
.text
.Letext0:
.file 1 "test.c"
.section .debug_info,"",%progbits
.Ldebug_info0:
.4byte 0x32
.2byte 0x5
.byte 0x1
.byte 0x4
.4byte .Ldebug_abbrev0
.uleb128 0x1
.4byte .LA... |
tactcomplabs/xbgas-binutils-gdb | 1,707 | gas/testsuite/gas/elf/dwarf-5-file0-3.s | .file "test.c"
.text
.Ltext0:
.file 0 "/current/directory" "/full/path/test.c"
.globl x
.section .bss
.balign 4
.type x, %object
.size x, 4
x:
.zero 4
.text
.Letext0:
.file 1 "/full/path/test.c"
.section .debug_info,"",%progbits
.Ldebug_info0:
.4byte 0x32
.2byte 0x5
.byte 0x1
.byte 0x4
.4byte .Ldebug_a... |
tactcomplabs/xbgas-binutils-gdb | 1,213 | gas/testsuite/gas/elf/dwarf2-19.s | /* Test view numbering continuity at subsection borders.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the Li... |
tactcomplabs/xbgas-binutils-gdb | 3,352 | gas/testsuite/gas/aarch64/sve-movprfx.s | movprfx z0, z0
MOVPRFX Z0, Z0
movprfx z1, z0
MOVPRFX Z1, Z0
movprfx z31, z0
MOVPRFX Z31, Z0
movprfx z0, z2
MOVPRFX Z0, Z2
movprfx z0, z31
MOVPRFX Z0, Z31
movprfx z0.b, p0/z, z0.b
MOVPRFX Z0.B, P0/Z, Z0.B
movprfx z1.b, p0/z, z0.b
MOVPRFX Z1.B, P0/Z, Z0.B
movprfx z31.b, p0/z, ... |
tactcomplabs/xbgas-binutils-gdb | 2,311 | gas/testsuite/gas/aarch64/f64mm.s | /* The instructions with non-zero register numbers are there to ensure we have
the correct argument positioning (i.e. check that the first argument is at
the end of the word etc).
The instructions with all-zero register numbers are to ensure the previous
encoding didn't just "happen" to fit -- so that if we... |
tactcomplabs/xbgas-binutils-gdb | 35,401 | gas/testsuite/gas/aarch64/sve2.s | /* The instructions with non-zero register numbers are there to ensure we have
the correct argument positioning (i.e. check that the first argument is at
the end of the word etc).
The instructions with all-zero register numbers are to ensure the previous
encoding didn't just "happen" to fit -- so that if we... |
tactcomplabs/xbgas-binutils-gdb | 1,789 | gas/testsuite/gas/aarch64/undefined_advsimd_armv8_3.s | # Generates tests to see if the following conditions make the instruction
# undefined:
#
# 1) size == 0
# 2) size == 3 && Q == 0
#
# These patterns can't be created by the assembler so instead manually encode
# them from a starting pattern.
.macro gen_insns_same opc
.inst \opc
.inst (\opc & 0xff3fffff) // size == 0
... |
tactcomplabs/xbgas-binutils-gdb | 2,722 | gas/testsuite/gas/aarch64/v8-r-sysregs.s | // Armv8-R system registers
mrs x0, mpuir_el1
mrs x0, mpuir_el2
mrs x0, prbar_el1
msr prbar_el1, x0
mrs x0, prbar_el2
msr prbar_el2, x0
mrs x0, prbar1_el1
msr prbar1_el1, x0
mrs x0, prbar2_el1
msr prbar2_el1, x0
mrs x0, prbar3_el1
msr prbar3_el1, x0
mrs x0, prbar4_el1
msr prbar4_el1, x0
mrs x0, prbar5_el1
msr prbar5_el... |
tactcomplabs/xbgas-binutils-gdb | 2,037 | gas/testsuite/gas/aarch64/illegal-bfloat16.s | // SVE
bfdot z0.s, z1.h, z2.s // Fails from size types
bfdot z0.s, z1.h, z3.s[3] // Fails from size types
bfdot z0.s, z1.h, z3.h[4] // Fails from index size
bfdot z0.s, z1.h, z8.h[3] // Fails from vector number
bfmmla z0.s, z1.h, z2.s // Fails from size types
bfcvt z0.h, p1/z, z2.s // Fails from merge ... |
tactcomplabs/xbgas-binutils-gdb | 1,279 | gas/testsuite/gas/aarch64/advsimd-across.s | /* advsimd-across.s Test file for AArch64 Advanced-SIMD across
instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as p... |
tactcomplabs/xbgas-binutils-gdb | 6,432 | gas/testsuite/gas/aarch64/diagnostic.s | // diagnostic.s Test file for diagnostic quality.
.text
fmul, s0, s1, s2
fmul , s0, s1, s2
fmul , s0, s1, s2
b.random label1
fmull s0
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
sys 1,c1,c3,3,
ext v0.8b, v1.8b, v2.8b, 8
ext v0.16b, v1.16b, v2.16b, 20
svc -1
svc 65536
ccmp w0, 32,... |
tactcomplabs/xbgas-binutils-gdb | 1,792 | gas/testsuite/gas/aarch64/i8mm.s | /* The instructions with non-zero register numbers are there to ensure we have
the correct argument positioning (i.e. check that the first argument is at
the end of the word etc).
The instructions with all-zero register numbers are to ensure the previous
encoding didn't just "happen" to fit -- so that if we... |
tactcomplabs/xbgas-binutils-gdb | 2,596 | gas/testsuite/gas/aarch64/neon-vfp-reglist.s |
# ARMv8 tests to test neon register
# lists syntax.
.macro ldnstn_reg_list type inst index rep
\inst\()1\rep {v0.\type}\index, [x0]
.ifb \index
.ifb \rep
\inst\()1 {v0.\type, v1.\type}\index, [x0]
\inst\()1 {v0.\type, v1.\type, v2.\type}\index, [x0]
\inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}\index, ... |
tactcomplabs/xbgas-binutils-gdb | 16,200 | gas/testsuite/gas/aarch64/dotproduct.s | UDOT V0.2S, V0.8B, V0.8B
UDOT V0.2S, V0.8B, V11.8B
UDOT V0.2S, V0.8B, V22.8B
UDOT V0.2S, V11.8B, V0.8B
UDOT V0.2S, V11.8B, V11.8B
UDOT V0.2S, V11.8B, V22.8B
UDOT V0.2S, V22.8B, V0.8B
UDOT V0.2S, V22.8B, V11.8B
UDOT V0.2S, V22.8B, V22.8B
UDOT V11.2S, V0.8B, V0.8B
UDOT V11.2S, V0.8B, V11.8B
UDOT V11.2S, V0.8B, V22.8B
UDO... |
tactcomplabs/xbgas-binutils-gdb | 1,447 | gas/testsuite/gas/aarch64/advsimd-armv8_3.s | /* Test file for ARMv8.3 complex arithmetics instructions. */
.text
.macro three_same op, sz
.irp rot, 0, 90, 180, 270
.irp d, 1.\sz, 2.\sz, 5.\sz, 13.\sz, 27.\sz
.irp m, 2.\sz, 3.\sz, 5.\sz, 14.\sz, 31.\sz
.irp n, 3.\sz, 4.\sz, 6.\sz, 15.\sz, 30.\sz
\op v\d, v\m, v\n, #\rot
.endr
.endr
.endr
.endr
.endm... |
tactcomplabs/xbgas-binutils-gdb | 2,507 | gas/testsuite/gas/aarch64/sme-4.s | /* SME Extension (ZERO). */
/* An all-zeros immediate is disassembled as an empty list { }. */
zero { }
/* An all-ones immediate is disassembled as {ZA}. */
zero { za }
zero { za0.b }
zero { za0.h, za1.h }
zero { za0.d, za1.d, za2.d, za3.d, za4.d, za5.d, za6.d, za7.d }
zero { za7.d, za6.d, za5.d, za4.d, za3.d, za2... |
tactcomplabs/xbgas-binutils-gdb | 2,150 | gas/testsuite/gas/aarch64/float-fp16.s | /* Test file for AArch64 half-precision floating-point instructions. */
.text
fccmp s0, s0, #0, eq
fccmp h0, h0, #0, eq
fccmp s1, s2, #0, le
fccmp h1, h2, #0, le
fccmpe s0, s0, #0, eq
fccmpe h0, h0, #0, eq
fccmpe s1, s2, #0, le
fccmpe h1, h2, #0, le
fcmp s0, s0
fcmp h0, h0
fcmp s1, s2
fcmp h1, h2
fcm... |
tactcomplabs/xbgas-binutils-gdb | 1,161 | gas/testsuite/gas/aarch64/sve-movprfx_25.s | /* Checks that CPY is allowed after a movprfx, special case in that SIMD&Scalar
version is also valid and Pg is 4 bits rather than 3.
Has invalid usages. Diagnosis required. */
.text
.arch armv8-a+sve
f:
/* OK, immediate predicated, alias mov. */
movprfx z1.d, p1/m, z3.d
cpy z1.d, p1/m, #12
/* ... |
tactcomplabs/xbgas-binutils-gdb | 4,376 | gas/testsuite/gas/aarch64/advsimd-fp16.s | /* simdhp.s Test file for AArch64 half-precision floating-point
vector instructions. */
/* Vector three-same. */
.macro three_same, op
\op v1.2d, v2.2d, v3.2d
\op v1.2s, v2.2s, v3.2s
\op v1.4s, v2.4s, v3.4s
\op v0.4h, v0.4h, v0.4h
\op v1.4h, v2.4h, v3.4h
\op v0.8h, v0.8h, v0.8h
\op v1.8h, v2.8h, v3.8h
... |
tactcomplabs/xbgas-binutils-gdb | 2,442 | gas/testsuite/gas/aarch64/illegal-sysreg-8.s | .macro roreg, name
mrs x0, \name
.endm
.macro woreg, name
msr \name, x1
.endm
.macro rwreg, name
mrs x2, \name
msr \name, x3
.endm
roreg lorid_el1
.arch armv8.2-a
roreg ccsidr2_el1
.arch armv8.3-a
rwreg trfcr_el1
roreg pmmir_el1
rwreg trfcr_el2
rwreg trfcr_el12
rwreg amcr_el0
roreg amcfgr_e... |
tactcomplabs/xbgas-binutils-gdb | 1,653 | gas/testsuite/gas/aarch64/fp-const0-parse.s | /* fp-const0-parse.s Test file For AArch64 float constant 0 parse.
Copyright (C) 2014-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
... |
tactcomplabs/xbgas-binutils-gdb | 1,212 | gas/testsuite/gas/aarch64/sme-7-illegal.s | /* Scalable Matrix Extension (SME). */
/* Load vector to ZA array. */
ldr za[w11, 0], [x0]
ldr za[w12, 1], [sp, x0]
ldr za[w12, 0], [sp, #1, mul vl]
ldr za[w13, 9], [x17, #19, mul vl]
ldr za[w13, 21], [x17, #21, mul vl]
ldr za[w15, 32], [x17, #15, mul vl]
ldr za[w16, 15], [sp, #15, mul vl]
ldr za[w12, 0], [x0, #0, m... |
tactcomplabs/xbgas-binutils-gdb | 1,126 | gas/testsuite/gas/aarch64/pac.s | /* ARMv8.3 Pointer authentication instructions. */
.text
/* Basic instructions. */
pacia x3, x4
pacia x5, sp
pacib x3, x4
pacib x5, sp
pacda x3, x4
pacda x5, sp
pacdb x3, x4
pacdb x5, sp
autia x3, x4
autia x5, sp
autib x3, x4
autib x5, sp
autda x3, x4
autda x5, sp
autdb x3, x4
autdb x5, sp
paci... |
tactcomplabs/xbgas-binutils-gdb | 3,239 | gas/testsuite/gas/aarch64/neon-fp-cvt-int.s | /* neon-fp-cvt-ins.s Test file for AArch64 NEON
floating-point<->fixed-point conversion and
floating-point<->integer conversion instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or... |
tactcomplabs/xbgas-binutils-gdb | 1,595 | gas/testsuite/gas/aarch64/armv8_4-a-registers.s | .macro gen_mrs reg
.irp m, 3, 11, 15
MRS X\m, \reg
.endr
.endm
.macro gen_tlbi reg
.irp m, 3, 11, 15
TLBI \reg, X\m
.endr
.endm
func:
# Secure second stage
gen_mrs VSTTBR_EL2
gen_mrs VSTCR_EL2
# Timer changes
gen_mrs CNTP_TVAL_EL0
gen_mrs CNTP_CTL_EL0
gen_mrs CNTP_CVAL_EL0
gen_mrs CNTV_TVAL_EL0
g... |
tactcomplabs/xbgas-binutils-gdb | 3,482 | gas/testsuite/gas/aarch64/sme-5.s | /* SME Extension (LD1x instructions). */
ld1b {za0h.b[w12, 0]}, p0/z, [x0]
ld1b {za0h.b[w12, 0]}, p0/z, [sp]
ld1b {za0h.b[w12, 0]}, p0/z, [sp, x0]
ld1b {za0h.b[w15, 15]}, p7/z, [x17]
ld1b {za0h.b[w15, 15]}, p7/z, [sp]
ld1b {za0h.b[w15, 15]}, p7/z, [sp, x17]
ld1h {za0h.h[w12, 0]}, p0/z, [x0]
ld1h {za0h.h[w12, 0]}, p0/... |
tactcomplabs/xbgas-binutils-gdb | 4,460 | gas/testsuite/gas/aarch64/reloc-insn.s | // Test file for AArch64 GAS -- instructions with relocation operators.
func:
// BFD_RELOC_AARCH64_MOVW_G0
// immediate
movz x0,#:abs_g0:u12
// BFD_RELOC_AARCH64_MOVW_G0_S
// immediate
movz x0,#:abs_g0_s:s12
// BFD_RELOC_AARCH64_MOVW_G1
// immediate
movz x1,#:abs_g1:u32
movk x1,#:abs_g0_nc:u32
// BFD_R... |
tactcomplabs/xbgas-binutils-gdb | 1,323 | gas/testsuite/gas/aarch64/illegal-memtag.s | func:
# ADDG/SUBG : Fail uimm6
addg x1, x2, #0x3ef, #0x6
subg x1, x2, #0x400, #0x3
subg x1, x2, -16, #0x3
# ADDG/SUBG : Fail uimm4
addg x1, x2, #0x3f0, #0x10
subg x1, x2, #0x3f0, -4
# STG/STZG/ST2G/LDG : Fail imm
stg x2, [x1, #15]
stzg x2, [x1, #-4097]!
st2g x2, [x1], #4096
ldg x1, [x2, #33]
ldg x1, [x2,... |
tactcomplabs/xbgas-binutils-gdb | 1,090 | gas/testsuite/gas/aarch64/crc32.s | /* crc32.s Test file for AArch64 CRC-32 and CRC-32C checksum instructions.
Copyright (C) 2013-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as publis... |
tactcomplabs/xbgas-binutils-gdb | 1,183 | gas/testsuite/gas/aarch64/lor.s | /* lor.s Test file for AArch64 LOR extension instructions.
Copyright (C) 2015-2022 Free Software Foundation, Inc. Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free... |
tactcomplabs/xbgas-binutils-gdb | 3,400 | gas/testsuite/gas/aarch64/int-insns.s | // Test file for AArch64 GAS -- basic integer instructions
func:
lsl x1, x2, x3
lsl x1, x2, #0
lsl x1, x2, #1
extr x1, x2, x3, #1
extr x1, x2, x3, #63
extr x1, x2, x3, #0
extr w1, w2, w3, #31
CSET x1, e... |
tactcomplabs/xbgas-binutils-gdb | 1,064 | gas/testsuite/gas/aarch64/floatdp2.s | /* floatdp2.s Test file for AArch64 Floating-point data-processing
(2 source) instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Publ... |
tactcomplabs/xbgas-binutils-gdb | 1,133 | gas/testsuite/gas/aarch64/msr.s | /*
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, ... |
tactcomplabs/xbgas-binutils-gdb | 1,184 | gas/testsuite/gas/aarch64/advsisd-copy.s | /* advsisd-copy.s Test file for AArch64 Advanced-SISD copy instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as publishe... |
tactcomplabs/xbgas-binutils-gdb | 1,728 | gas/testsuite/gas/aarch64/virthostext.s | /* virthostext.s Test file for ARMv8.1 Virtualization Host Extension
support.
Copyright (C) 2015-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as pu... |
tactcomplabs/xbgas-binutils-gdb | 5,708 | gas/testsuite/gas/aarch64/mops_invalid.s | .arch armv8.8-a
cpyfp x0, [x1]!, x2!
cpyfp x0!, [x1]!, x2!
cpyfp [x0], [x1]!, x2!
cpyfp [x0, #0]!, [x1]!, x2!
cpyfp [x0, xzr]!, [x1]!, x2!
cpyfp [x1]!, x0, x2!
cpyfp [x1]!, x0!, x2!
cpyfp [x1]!, [x0], x2!
cpyfp [x1]!, [x0, #0]!, x2!
cpyfp [x1]!, [x0, xzr]!, x2!
cpyfp [x0]!, [x1]!, x2
cpyfp [x0]!, [x1]!,... |
tactcomplabs/xbgas-binutils-gdb | 1,358 | gas/testsuite/gas/aarch64/neon-ins.s |
.macro iterate_regs_types macro_name reg
.irp index, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
.irp regs, 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
\macro_name \regs b \index \reg
.endr
.endr
.irp index, 0,1,2,3,4,5,6,7
.irp regs, 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,1... |
tactcomplabs/xbgas-binutils-gdb | 2,902 | gas/testsuite/gas/aarch64/alias.s | /* alias.s Test file for AArch64 instructions aliases or disassembly
preference. It is also used to test the -Mno-aliases option in
the disassemler.
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute i... |
tactcomplabs/xbgas-binutils-gdb | 1,792 | gas/testsuite/gas/aarch64/lse-atomic.s | /* lse-atomic.s Test file For AArch64 LSE atomic instructions encoding.
Copyright (C) 2014-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published... |
tactcomplabs/xbgas-binutils-gdb | 3,073 | gas/testsuite/gas/aarch64/movi.s | // movi.s Test file for AArch64 AdvSIMD modified immediate instruction MOVI
.text
.macro all_64bit_mask_movi dst
.irp b7, 0, 0xff00000000000000
.irp b6, 0, 0xff000000000000
.irp b5, 0, 0xff0000000000
.irp b4, 0, 0xff00000000
.irp b3, 0, 0xff000000
.irp b2, 0, 0xff0000
.irp b1, 0, 0xff00
.irp b0, 0, 0xff
mo... |
tactcomplabs/xbgas-binutils-gdb | 47,576 | gas/testsuite/gas/aarch64/illegal-sve2.s | movprfx z0.d, z1.d
adclb z0.d, z1.d, z2.d
movprfx z0.d, p0/m, z1.d
adclb z0.d, z1.d, z2.d
adclb z0.d, z0.s, z0.s
adclb z32.d, z0.d, z0.d
adclb z0.d, z32.d, z0.d
adclb z0.d, z0.d, z32.d
adclt z0.d, z0.s, z0.s
adclt z32.s, z0.s, z0.s
adclt z0.s, z32.s, z0.s
adclt z0.s, z0.s, z32.s
addhnb z0.b, z0.h, z0.b
addhnb z32.b,... |
tactcomplabs/xbgas-binutils-gdb | 1,315 | gas/testsuite/gas/aarch64/mops_invalid_2.s | .arch armv8.8-a+sve
cpyfpwtn [x0]!, [x1]!, x2!
cpyfewtn [x0]!, [x1]!, x2!
cpyfmwtn [x0]!, [x1]!, x2!
cpyfpwtn [x0]!, [x1]!, x2!
cpyfmtn [x0]!, [x1]!, x2!
cpyfetn [x0]!, [x1]!, x2!
cpyp [x0]!, [x1]!, x2!
setm [x0]!, x1!, x2
sete [x0]!, x1!, x2
cpyfpwt [x0]!, [x1]!, x2!
cpyfmwt [x3]!, [x1]!, x2!
cpyfewt ... |
tactcomplabs/xbgas-binutils-gdb | 1,438 | gas/testsuite/gas/aarch64/sme-2.s | /* Scalable Matrix Extension (SME). */
/* MOVA (tile to vector) variant. */
mova z0.b, p0/m, za0v.b[w12, 0]
mova z0.h, p0/m, za0v.h[w12, 0]
mova z0.s, p0/m, za0v.s[w12, 0]
mova z0.d, p0/m, za0v.d[w12, 0]
mova z0.q, p0/m, za0v.q[w12, 0]
mova z31.b, p7/m, za0v.b[w15, 15]
mova z31.h, p7/m, za1v.h[w15, 7]
mova z31.s, p... |
tactcomplabs/xbgas-binutils-gdb | 2,607 | gas/testsuite/gas/aarch64/ldst-exclusive.s | /* ldst-exclusive.s Test file for AArch64 load-store exclusive
instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as p... |
tactcomplabs/xbgas-binutils-gdb | 4,958 | gas/testsuite/gas/aarch64/sve-reg-diagnostic.s | .equ x0, 0
.equ s0, 0
.equ z0, 0
.equ z0.s, 0
.equ p0, 0
.equ p0.b, 1
cmeq v0.4s, v1.4s, x0 // Error (wrong register type)
cmeq v0.4s, v1.4s, #x0 // OK
cmeq v0.4s, v1.4s, s0 // Error (wrong register type)
cmeq v0.4s, v1.4s, #s0 // OK
cmeq v0.4s, v1.4s, z0 // OK (for compatibility)
cmeq v0.4s, v1.4s, #z0 //... |
tactcomplabs/xbgas-binutils-gdb | 2,163 | gas/testsuite/gas/aarch64/rdma.s | /* rdma.s Test file for AArch64 v8.1 Advanced-SIMD instructions.
Copyright (C) 2012-2022 Free Software Foundation, Inc. Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
th... |
tactcomplabs/xbgas-binutils-gdb | 1,515 | gas/testsuite/gas/aarch64/crypto.s | /* crypto.s Test file for AArch64 Advanced-SIMD Crypto instructions.
Copyright (C) 2012-2022 Free Software Foundation, Inc. Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
... |
tactcomplabs/xbgas-binutils-gdb | 2,784 | gas/testsuite/gas/aarch64/ldst-reg-uns-imm.s | /* ld-reg-uns-imm.s Test file for AArch64 load-store reg. (uns.imm)
instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License... |
tactcomplabs/xbgas-binutils-gdb | 1,304 | gas/testsuite/gas/aarch64/ls64.s | /* Atomic 64-byte load/store instructions. */
.arch armv8.6-a+ls64
/* Single-copy Atomic 64-byte Load. */
ld64b x0, [x1]
ld64b x2, [x1]
ld64b x4, [x1]
ld64b x6, [x1]
ld64b x8, [x1]
ld64b x10, [x1]
ld64b x12, [x1]
ld64b x14, [x1]
ld64b x16, [x1]
ld64b x18, [x1]
ld64b x20, [x1]
ld64b x22, [x1]
/* Single-c... |
tactcomplabs/xbgas-binutils-gdb | 4,188 | gas/testsuite/gas/aarch64/sme-i64.s | /* Scalable Matrix Extension (SME I64). */
/* ADDHA 64-bit variant. */
addha za0.d, p0/m, p1/m, z1.d
addha za1.d, p2/m, p3/m, z2.d
addha za2.d, p4/m, p5/m, z3.d
addha za3.d, p6/m, p7/m, z4.d
addha za4.d, p1/m, p0/m, z5.d
addha za5.d, p3/m, p2/m, z6.d
addha za6.d, p5/m, p4/m, z7.d
addha za7.d, p7/m, p6/m, z8.d
addha ... |
tactcomplabs/xbgas-binutils-gdb | 1,624 | gas/testsuite/gas/aarch64/illegal-by-element.s | .text
.macro gen_illegal op, p1, p2, p3
.irp w, v16.\p3, v27.\p3, v31.\p3
\op v2.\p1, v12.\p2, \w[0]
.endr
.endm
.macro gen_illegal2 op, p1, p2, p3
.irp x, \p1\()2
.irp y, \p2\()12
.irp w, v16.\p3, v27.\p3, v31.\p3
\op \x, \y, \w[0]
.endr
.endr
.endr
.endm
gen_illegal fmla, 4h, 4h, h
gen_illegal fml... |
tactcomplabs/xbgas-binutils-gdb | 1,877 | gas/testsuite/gas/aarch64/illegal-lse.s | /* illegal-lse.s Test file For AArch64 LSE atomic instructions that
could be rejected by the assembler.
Copyright (C) 2014-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU ... |
tactcomplabs/xbgas-binutils-gdb | 2,190 | gas/testsuite/gas/aarch64/programmer-friendly.s | // programmer-friendly.s Test file for AArch64 instructions variants that are
// not part of the architectural assembly syntax but are supported for the
// ease of assembly level programming.
.text
// The preferred architectural syntax does not accept the shifter
// LSL or any other shift operator, when the destinat... |
tactcomplabs/xbgas-binutils-gdb | 1,795 | gas/testsuite/gas/aarch64/tls.s | /* tls.s Test file for AArch64 TLS relocations.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software... |
tactcomplabs/xbgas-binutils-gdb | 1,703 | gas/testsuite/gas/aarch64/ldst-reg-imm-pre-ind.s | /* ldst-reg-imm-pre-ind.s Test file for AArch64
load-store reg. (imm.pre-ind.) instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Pub... |
tactcomplabs/xbgas-binutils-gdb | 4,081 | gas/testsuite/gas/aarch64/sme.s | /* Scalable Matrix Extension (SME). */
/* ADDHA 32-bit variant. */
addha za0.s, p0/m, p1/m, z1.s
addha za1.s, p2/m, p3/m, z2.s
addha za2.s, p4/m, p5/m, z3.s
addha za3.s, p6/m, p7/m, z4.s
/* ADDVA 32-bit variant. */
addva za0.s, p0/m, p1/m, z1.s
addva za1.s, p2/m, p3/m, z2.s
addva za2.s, p4/m, p5/m, z3.s
addva za3.... |
tactcomplabs/xbgas-binutils-gdb | 2,807 | gas/testsuite/gas/aarch64/ls64-invalid.s | /* Atomic 64-byte load/store instructions limit register number Rt to below
condition: the <Xt> register number should be even and <= 22. */
.arch armv8.7-a+ls64
/* Single-copy Atomic 64-byte Load. */
ld64b x0, [x1]
ld64b x1, [x1]
ld64b x2, [x1]
ld64b x3, [x1]
ld64b x4, [x1]
ld64b x5, [x1]
ld64b x6, [x1]
... |
tactcomplabs/xbgas-binutils-gdb | 5,586 | gas/testsuite/gas/aarch64/neon-vfp-reglist-post.s |
# ARMv8 tests to test neon register
# lists syntax.
.text
.arch armv8-a
# Post-index multiple elements
.macro ldst1_reg_list_post_imm_64 inst type
\inst\()1 {v0.\type}, [x0], #8
\inst\()1 {v0.\type, v1.\type}, [x0], #16
\inst\()1 {v0.\type, v1.\type, v2.\type}, [x0], #24
\inst\()1 {v0.\type, v1.\type, v2.... |
tactcomplabs/xbgas-binutils-gdb | 2,925 | gas/testsuite/gas/aarch64/sme-6.s | /* SME Extension (ST1x instructions). */
st1b {za0h.b[w12, 0]}, p0, [x0]
st1b {za0h.b[w12, 0]}, p0, [sp]
st1b {za0h.b[w12, 0]}, p0, [sp, x0]
st1b {za0h.b[w15, 15]}, p7, [x17]
st1b {za0h.b[w15, 15]}, p7, [sp]
st1b {za0h.b[w15, 15]}, p7, [sp, x17]
st1h {za0h.h[w12, 0]}, p0, [x0]
st1h {za0h.h[w12, 0]}, p0, [sp]
st1h {za... |
tactcomplabs/xbgas-binutils-gdb | 1,213 | gas/testsuite/gas/aarch64/mops.s | .arch armv8.8-a+memtag
dest .req x8
src .req x11
len .req x19
data .req x23
zero .req xzr
.macro pme_seq, op, suffix, r1, r2, r3
\op\()p\()\suffix \r1, \r2, \r3
\op\()m\()\suffix \r1, \r2, \r3
\op\()e\()\suffix \r1, \r2, \r3
.endm
.macro cpy_op1_op2, op, suffix
pme_seq \op, \suffix, [x0]!, [x1]!, x30!
pme_s... |
tactcomplabs/xbgas-binutils-gdb | 3,643 | gas/testsuite/gas/aarch64/sysreg-8.s | .macro roreg, name
mrs x0, \name
.endm
.macro woreg, name
msr \name, x1
.endm
.macro rwreg, name
mrs x2, \name
msr \name, x3
.endm
roreg id_dfr1_el1
roreg id_mmfr5_el1
roreg id_isar6_el1
rwreg icc_pmr_el1
roreg icc_iar0_el1
woreg icc_eoir0_el1
roreg icc_hppir0_el1
rwreg icc_bpr0_el1
rwreg icc_ap0... |
tactcomplabs/xbgas-binutils-gdb | 1,051 | gas/testsuite/gas/aarch64/armv8-ras-1_1.s | /* Armv8-A RAS 1.1 extension system registers.
Please note that early Armv8-a architectures do not officially support RAS
extension.
Certain use cases require developers to enable only more generic architecture
(e.g. -march=armv8-a) during system development. Users must use RAS extension
registers bearing in mind tha... |
tactcomplabs/xbgas-binutils-gdb | 1,027 | gas/testsuite/gas/aarch64/advsimd-misc.s | /* advsimd-abs.s Test file for AArch64 Advanced-SIMD Integer absolute
instruction.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public Licens... |
tactcomplabs/xbgas-binutils-gdb | 2,209 | gas/testsuite/gas/aarch64/ldst-reg-reg-offset.s | /* ldst-reg-reg-offset.s Test file for AArch64 load-store reg. (reg.offset)
instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public... |
tactcomplabs/xbgas-binutils-gdb | 1,335 | gas/testsuite/gas/aarch64/armv8_4-a-registers-illegal.s | # Secure second stage
MRS W0, VSTTBR_EL2
MRS W0, VSTCR_EL2
# Timer changes
MRS W0, CNTP_TVAL_EL0
MRS W0, CNTP_CTL_EL0
MRS W0, CNTP_CVAL_EL0
MRS W0, CNTV_TVAL_EL0
MRS W0, CNTV_CTL_EL0
MRS W0, CNTV_CVAL_EL0
MRS W0, CNTHVS_TVAL_EL2
MRS W0, CNTHVS_CVAL_EL2
MRS W0, CNTHVS_CTL_EL2
MRS W0, CNTHPS_TVAL_EL2
MRS W0, CNTHPS_CVA... |
tactcomplabs/xbgas-binutils-gdb | 1,704 | gas/testsuite/gas/aarch64/ldst-reg-imm-post-ind.s | /* ldst-reg-imm-post-ind.s Test file for AArch64
load-store reg. (imm.post-ind.) instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General P... |
tactcomplabs/xbgas-binutils-gdb | 3,107 | gas/testsuite/gas/aarch64/sve-dup.s | dup z0.b, #-255
dup z0.b, #-129
dup z0.b, #-128
dup z0.b, #-127
dup z0.b, #-1
dup z0.b, #0
dup z0.b, #1
dup z0.b, #127
dup z0.b, #128
dup z0.b, #255
dup z0.h, #-65535
dup z0.h, #-65536 + 127
dup z0.h, #-65536 + 256
dup z0.h, #-32768
dup z0.h, #-32768 + 256
dup z0.h, #-128
dup z0.h, #-127
dup z0.h, #-... |
tactcomplabs/xbgas-binutils-gdb | 1,912 | gas/testsuite/gas/aarch64/armv8-ras-1.s | /* ARMv8 RAS Extension. */
.text
.macro rw_sys_reg sys_reg xreg r w
.ifc \w, 1
msr \sys_reg, \xreg
.endif
.ifc \r, 1
mrs \xreg, \sys_reg
.endif
.endm
/* ARMv8-A. */
.arch armv8-a+ras
esb
hint #0x10
rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0
rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1
rw_sys... |
tactcomplabs/xbgas-binutils-gdb | 1,464 | gas/testsuite/gas/aarch64/illegal-3.s | // Test the disassembler's detection of illegal binary sequences.
// PR 21380:
.inst 0x4dc2d4ec
.inst 0x4de2d4fc
.inst 0x4dc2f4ec
.inst 0x4de2f4fc
// PR 20319:
# Check FMOV for Unallocated Encodings
# FMOV (register): type == 0x10
.inst 0x1ea04000
# FMOV (scalar, immediate): type == 0x10... |
tactcomplabs/xbgas-binutils-gdb | 1,040 | gas/testsuite/gas/aarch64/pan.s | /* pan.s Test file for AArch64 PAN instructions.
Copyright (C) 2015-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Softwar... |
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