url stringclasses 147
values | commit stringclasses 147
values | file_path stringlengths 7 101 | full_name stringlengths 1 94 | start stringlengths 6 10 | end stringlengths 6 11 | tactic stringlengths 1 11.2k | state_before stringlengths 3 2.09M | state_after stringlengths 6 2.09M | input stringlengths 73 2.09M |
|---|---|---|---|---|---|---|---|---|---|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitRes_succAbove_apply | [308, 1] | [312, 53] | rw [getBitRes_succAbove, getBitResSuccAbove_apply] | m : ℕ
q : BV (m + 1 + 1)
j : Fin (m + 2)
i : Fin (m + 1)
⊢ (getBitRes (j.succAbove i)) q =
(((getBitRes i) ((getBitRes j) q).2).1,
(getBitRes (i.predAbove j)).symm (((getBitRes j) q).1, ((getBitRes i) ((getBitRes j) q).2).2)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
q : BV (m + 1 + 1)
j : Fin (m + 2)
i : Fin (m + 1)
⊢ (getBitRes (j.succAbove i)) q =
(((getBitRes i) ((getBitRes j) q).2).1,
(getBitRes (i.predAbove j)).symm (((getBitRes j) q).1, ((getBitRes i) ((getBitRes j) q).2).2))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBitRes_succAbove_symm_apply | [314, 1] | [318, 58] | rw [getBitRes_succAbove, getBitResSuccAbove_symm_apply] | m : ℕ
b : Bool
p : BV (m + 1)
j : Fin (m + 2)
i : Fin (m + 1)
⊢ (getBitRes (j.succAbove i)).symm (b, p) =
(getBitRes j).symm (((getBitRes (i.predAbove j)) p).1, (getBitRes i).symm (b, ((getBitRes (i.predAbove j)) p).2)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
b : Bool
p : BV (m + 1)
j : Fin (m + 2)
i : Fin (m + 1)
⊢ (getBitRes (j.succAbove i)).symm (b, p) =
(getBitRes j).symm (((getBitRes (i.predAbove j)) p).1, (getBitRes i).symm (b, ((getBitRes (i.predAbove j)) p).2))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_succAbove | [320, 1] | [322, 85] | simp_rw [getRes_apply, mergeBitRes_apply, getBit_apply, getBitRes_succAbove_apply] | m : ℕ
q : BV (m + 1 + 1)
j : Fin (m + 2)
i : Fin (m + 1)
⊢ getRes (j.succAbove i) q = mergeBitRes (i.predAbove j) (getBit j q) (getRes i (getRes j q)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
q : BV (m + 1 + 1)
j : Fin (m + 2)
i : Fin (m + 1)
⊢ getRes (j.succAbove i) q = mergeBitRes (i.predAbove j) (getBit j q) (getRes i (getRes j q))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_succAbove | [324, 1] | [326, 66] | simp_rw [getRes_apply, getBit_apply, getBitRes_succAbove_apply] | m : ℕ
q : BV (m + 1 + 1)
j : Fin (m + 2)
i : Fin (m + 1)
⊢ getBit (j.succAbove i) q = getBit i (getRes j q) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
q : BV (m + 1 + 1)
j : Fin (m + 2)
i : Fin (m + 1)
⊢ getBit (j.succAbove i) q = getBit i (getRes j q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_succAbove | [328, 1] | [330, 90] | simp_rw [mergeBitRes_apply, getBit_apply, getRes_apply, getBitRes_succAbove_symm_apply] | m : ℕ
b : Bool
q : BV (m + 1)
j : Fin (m + 2)
i : Fin (m + 1)
⊢ mergeBitRes (j.succAbove i) b q =
mergeBitRes j (getBit (i.predAbove j) q) (mergeBitRes i b (getRes (i.predAbove j) q)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
b : Bool
q : BV (m + 1)
j : Fin (m + 2)
i : Fin (m + 1)
⊢ mergeBitRes (j.succAbove i) b q =
mergeBitRes j (getBit (i.predAbove j) q) (mergeBitRes i b (getRes (i.predAbove j) q))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_mergeBitRes | [332, 1] | [334, 66] | simp_rw [getBit_apply, mergeBitRes_apply, Equiv.apply_symm_apply] | a✝ : ℕ
i : Fin (a✝ + 1)
b : Bool
p : BV a✝
⊢ getBit i (mergeBitRes i b p) = b | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
b : Bool
p : BV a✝
⊢ getBit i (mergeBitRes i b p) = b
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_mergeBitRes | [336, 1] | [338, 66] | simp_rw [getRes_apply, mergeBitRes_apply, Equiv.apply_symm_apply] | a✝ : ℕ
i : Fin (a✝ + 1)
b : Bool
p : BV a✝
⊢ getRes i (mergeBitRes i b p) = p | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
b : Bool
p : BV a✝
⊢ getRes i (mergeBitRes i b p) = p
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_getBit_getRes | [340, 1] | [342, 93] | simp_rw [getRes_apply, mergeBitRes_apply, getBit_apply, Prod.mk.eta, Equiv.symm_apply_apply] | a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
⊢ mergeBitRes i (getBit i q) (getRes i q) = q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
⊢ mergeBitRes i (getBit i q) (getRes i q) = q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_Bool_inj | [348, 1] | [350, 87] | have h₂ := (congrArg (getBit i) h) | m : ℕ
b₁ : Bool
p₁ : BV m
b₂ : Bool
p₂ : BV m
i : Fin (m + 1)
h : mergeBitRes i b₁ p₁ = mergeBitRes i b₂ p₂
⊢ b₁ = b₂ | m : ℕ
b₁ : Bool
p₁ : BV m
b₂ : Bool
p₂ : BV m
i : Fin (m + 1)
h : mergeBitRes i b₁ p₁ = mergeBitRes i b₂ p₂
h₂ : getBit i (mergeBitRes i b₁ p₁) = getBit i (mergeBitRes i b₂ p₂)
⊢ b₁ = b₂ | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
b₁ : Bool
p₁ : BV m
b₂ : Bool
p₂ : BV m
i : Fin (m + 1)
h : mergeBitRes i b₁ p₁ = mergeBitRes i b₂ p₂
⊢ b₁ = b₂
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_Bool_inj | [348, 1] | [350, 87] | simp only [getBit_mergeBitRes] at h₂ | m : ℕ
b₁ : Bool
p₁ : BV m
b₂ : Bool
p₂ : BV m
i : Fin (m + 1)
h : mergeBitRes i b₁ p₁ = mergeBitRes i b₂ p₂
h₂ : getBit i (mergeBitRes i b₁ p₁) = getBit i (mergeBitRes i b₂ p₂)
⊢ b₁ = b₂ | m : ℕ
b₁ : Bool
p₁ : BV m
b₂ : Bool
p₂ : BV m
i : Fin (m + 1)
h : mergeBitRes i b₁ p₁ = mergeBitRes i b₂ p₂
h₂ : b₁ = b₂
⊢ b₁ = b₂ | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
b₁ : Bool
p₁ : BV m
b₂ : Bool
p₂ : BV m
i : Fin (m + 1)
h : mergeBitRes i b₁ p₁ = mergeBitRes i b₂ p₂
h₂ : getBit i (mergeBitRes i b₁ p₁) = getBit i (mergeBitRes i b₂ p₂)
⊢ b₁ = b₂
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_Bool_inj | [348, 1] | [350, 87] | exact h₂ | m : ℕ
b₁ : Bool
p₁ : BV m
b₂ : Bool
p₂ : BV m
i : Fin (m + 1)
h : mergeBitRes i b₁ p₁ = mergeBitRes i b₂ p₂
h₂ : b₁ = b₂
⊢ b₁ = b₂ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
b₁ : Bool
p₁ : BV m
b₂ : Bool
p₂ : BV m
i : Fin (m + 1)
h : mergeBitRes i b₁ p₁ = mergeBitRes i b₂ p₂
h₂ : b₁ = b₂
⊢ b₁ = b₂
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_Fin_inj | [352, 1] | [354, 85] | have h₂ := (congrArg (getRes i) h) | m : ℕ
b₁ : Bool
p₁ : BV m
b₂ : Bool
p₂ : BV m
i : Fin (m + 1)
h : mergeBitRes i b₁ p₁ = mergeBitRes i b₂ p₂
⊢ p₁ = p₂ | m : ℕ
b₁ : Bool
p₁ : BV m
b₂ : Bool
p₂ : BV m
i : Fin (m + 1)
h : mergeBitRes i b₁ p₁ = mergeBitRes i b₂ p₂
h₂ : getRes i (mergeBitRes i b₁ p₁) = getRes i (mergeBitRes i b₂ p₂)
⊢ p₁ = p₂ | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
b₁ : Bool
p₁ : BV m
b₂ : Bool
p₂ : BV m
i : Fin (m + 1)
h : mergeBitRes i b₁ p₁ = mergeBitRes i b₂ p₂
⊢ p₁ = p₂
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_Fin_inj | [352, 1] | [354, 85] | simp_rw [getRes_mergeBitRes] at h₂ | m : ℕ
b₁ : Bool
p₁ : BV m
b₂ : Bool
p₂ : BV m
i : Fin (m + 1)
h : mergeBitRes i b₁ p₁ = mergeBitRes i b₂ p₂
h₂ : getRes i (mergeBitRes i b₁ p₁) = getRes i (mergeBitRes i b₂ p₂)
⊢ p₁ = p₂ | m : ℕ
b₁ : Bool
p₁ : BV m
b₂ : Bool
p₂ : BV m
i : Fin (m + 1)
h : mergeBitRes i b₁ p₁ = mergeBitRes i b₂ p₂
h₂ : p₁ = p₂
⊢ p₁ = p₂ | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
b₁ : Bool
p₁ : BV m
b₂ : Bool
p₂ : BV m
i : Fin (m + 1)
h : mergeBitRes i b₁ p₁ = mergeBitRes i b₂ p₂
h₂ : getRes i (mergeBitRes i b₁ p₁) = getRes i (mergeBitRes i b₂ p₂)
⊢ p₁ = p₂
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_Fin_inj | [352, 1] | [354, 85] | exact h₂ | m : ℕ
b₁ : Bool
p₁ : BV m
b₂ : Bool
p₂ : BV m
i : Fin (m + 1)
h : mergeBitRes i b₁ p₁ = mergeBitRes i b₂ p₂
h₂ : p₁ = p₂
⊢ p₁ = p₂ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
b₁ : Bool
p₁ : BV m
b₂ : Bool
p₂ : BV m
i : Fin (m + 1)
h : mergeBitRes i b₁ p₁ = mergeBitRes i b₂ p₂
h₂ : p₁ = p₂
⊢ p₁ = p₂
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_inj_iff | [360, 1] | [362, 50] | rintro ⟨rfl, rfl⟩ | m : ℕ
b₁ : Bool
p₁ : BV m
b₂ : Bool
p₂ : BV m
i : Fin (m + 1)
⊢ b₁ = b₂ ∧ p₁ = p₂ → mergeBitRes i b₁ p₁ = mergeBitRes i b₂ p₂ | case intro
m : ℕ
b₁ : Bool
p₁ : BV m
i : Fin (m + 1)
⊢ mergeBitRes i b₁ p₁ = mergeBitRes i b₁ p₁ | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
b₁ : Bool
p₁ : BV m
b₂ : Bool
p₂ : BV m
i : Fin (m + 1)
⊢ b₁ = b₂ ∧ p₁ = p₂ → mergeBitRes i b₁ p₁ = mergeBitRes i b₂ p₂
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_inj_iff | [360, 1] | [362, 50] | rfl | case intro
m : ℕ
b₁ : Bool
p₁ : BV m
i : Fin (m + 1)
⊢ mergeBitRes i b₁ p₁ = mergeBitRes i b₁ p₁ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro
m : ℕ
b₁ : Bool
p₁ : BV m
i : Fin (m + 1)
⊢ mergeBitRes i b₁ p₁ = mergeBitRes i b₁ p₁
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_ne_inj_iff | [364, 1] | [365, 70] | rw [ne_eq, mergeBitRes_inj_iff, not_and_or] | m : ℕ
b₁ : Bool
p₁ : BV m
b₂ : Bool
p₂ : BV m
i : Fin (m + 1)
⊢ mergeBitRes i b₁ p₁ ≠ mergeBitRes i b₂ p₂ ↔ b₁ ≠ b₂ ∨ p₁ ≠ p₂ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
b₁ : Bool
p₁ : BV m
b₂ : Bool
p₂ : BV m
i : Fin (m + 1)
⊢ mergeBitRes i b₁ p₁ ≠ mergeBitRes i b₂ p₂ ↔ b₁ ≠ b₂ ∨ p₁ ≠ p₂
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_getBit_inj | [367, 1] | [369, 92] | rw [← mergeBitRes_getBit_getRes (i := i) (q := q₁), h₁, h₂, mergeBitRes_getBit_getRes] | m : ℕ
q₁ q₂ : BV (m + 1)
i : Fin (m + 1)
h₁ : getBit i q₁ = getBit i q₂
h₂ : getRes i q₁ = getRes i q₂
⊢ q₁ = q₂ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
q₁ q₂ : BV (m + 1)
i : Fin (m + 1)
h₁ : getBit i q₁ = getBit i q₂
h₂ : getRes i q₁ = getRes i q₂
⊢ q₁ = q₂
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_getBit_inj_iff | [371, 1] | [373, 70] | rintro rfl | m : ℕ
q₁ q₂ : BV (m + 1)
i : Fin (m + 1)
⊢ q₁ = q₂ → getBit i q₁ = getBit i q₂ ∧ getRes i q₁ = getRes i q₂ | m : ℕ
q₁ : BV (m + 1)
i : Fin (m + 1)
⊢ getBit i q₁ = getBit i q₁ ∧ getRes i q₁ = getRes i q₁ | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
q₁ q₂ : BV (m + 1)
i : Fin (m + 1)
⊢ q₁ = q₂ → getBit i q₁ = getBit i q₂ ∧ getRes i q₁ = getRes i q₂
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_getBit_inj_iff | [371, 1] | [373, 70] | exact ⟨rfl, rfl⟩ | m : ℕ
q₁ : BV (m + 1)
i : Fin (m + 1)
⊢ getBit i q₁ = getBit i q₁ ∧ getRes i q₁ = getRes i q₁ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
q₁ : BV (m + 1)
i : Fin (m + 1)
⊢ getBit i q₁ = getBit i q₁ ∧ getRes i q₁ = getRes i q₁
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_mergeBitRes_iff | [379, 1] | [381, 39] | rw [← mergeBitRes_eq_iff, eq_comm] | a✝ : ℕ
q : BV (a✝ + 1)
i : Fin (a✝ + 1)
b : Bool
p : BV a✝
⊢ q = mergeBitRes i b p ↔ getBit i q = b ∧ getRes i q = p | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
q : BV (a✝ + 1)
i : Fin (a✝ + 1)
b : Bool
p : BV a✝
⊢ q = mergeBitRes i b p ↔ getBit i q = b ∧ getRes i q = p
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_ne_iff | [383, 1] | [385, 70] | simp_rw [ne_eq, mergeBitRes_eq_iff, Decidable.not_and_iff_or_not] | a✝ : ℕ
i : Fin (a✝ + 1)
b : Bool
p : BV a✝
q : BV (a✝ + 1)
⊢ mergeBitRes i b p ≠ q ↔ getBit i q ≠ b ∨ getRes i q ≠ p | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
b : Bool
p : BV a✝
q : BV (a✝ + 1)
⊢ mergeBitRes i b p ≠ q ↔ getBit i q ≠ b ∨ getRes i q ≠ p
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | ne_mergeBitRes_iff | [387, 1] | [389, 39] | rw [← mergeBitRes_ne_iff, ne_comm] | a✝ : ℕ
q : BV (a✝ + 1)
i : Fin (a✝ + 1)
b : Bool
p : BV a✝
⊢ q ≠ mergeBitRes i b p ↔ getBit i q ≠ b ∨ getRes i q ≠ p | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
q : BV (a✝ + 1)
i : Fin (a✝ + 1)
b : Bool
p : BV a✝
⊢ q ≠ mergeBitRes i b p ↔ getBit i q ≠ b ∨ getRes i q ≠ p
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_getRes_of_getBit_eq | [391, 1] | [392, 41] | simp_rw [← h, mergeBitRes_getBit_getRes] | a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
b : Bool
h : getBit i q = b
⊢ mergeBitRes i b (getRes i q) = q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
b : Bool
h : getBit i q = b
⊢ mergeBitRes i b (getRes i q) = q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_getRes_cases | [394, 1] | [400, 22] | rcases (getBit i q).dichotomy with (h | h) <;>
simp_rw [h, mergeBitRes_getRes_of_getBit_eq h, false_and, and_self] | m : ℕ
i : Fin (m + 1)
q : BV (m + 1)
⊢ getBit i q = false ∧ mergeBitRes i false (getRes i q) = q ∨ getBit i q = true ∧ mergeBitRes i true (getRes i q) = q | case inl
m : ℕ
i : Fin (m + 1)
q : BV (m + 1)
h : getBit i q = false
⊢ True ∨ False
case inr
m : ℕ
i : Fin (m + 1)
q : BV (m + 1)
h : getBit i q = true
⊢ False ∨ True | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
q : BV (m + 1)
⊢ getBit i q = false ∧ mergeBitRes i false (getRes i q) = q ∨ getBit i q = true ∧ mergeBitRes i true (getRes i q) = q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_getRes_cases | [394, 1] | [400, 22] | simp_rw [or_false] | case inl
m : ℕ
i : Fin (m + 1)
q : BV (m + 1)
h : getBit i q = false
⊢ True ∨ False | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inl
m : ℕ
i : Fin (m + 1)
q : BV (m + 1)
h : getBit i q = false
⊢ True ∨ False
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_getRes_cases | [394, 1] | [400, 22] | simp_rw [or_true] | case inr
m : ℕ
i : Fin (m + 1)
q : BV (m + 1)
h : getBit i q = true
⊢ False ∨ True | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inr
m : ℕ
i : Fin (m + 1)
q : BV (m + 1)
h : getBit i q = true
⊢ False ∨ True
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_getBit_of_getRes_eq | [402, 1] | [403, 41] | simp_rw [← h, mergeBitRes_getBit_getRes] | a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
p : BV a✝
h : getRes i q = p
⊢ mergeBitRes i (getBit i q) p = q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
p : BV a✝
h : getRes i q = p
⊢ mergeBitRes i (getBit i q) p = q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_inv | [405, 1] | [406, 48] | simp_rw [← h₁, ← h₂, mergeBitRes_getBit_getRes] | a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
b : Bool
p : BV a✝
h₁ : getBit i q = b
h₂ : getRes i q = p
⊢ mergeBitRes i b p = q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
b : Bool
p : BV a✝
h₁ : getBit i q = b
h₂ : getRes i q = p
⊢ mergeBitRes i b p = q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_inv | [408, 1] | [410, 39] | rcases mergeBitRes_surj i q with ⟨b, p', rfl⟩ | m : ℕ
q : BV (m + 1)
p : BV m
i : Fin (m + 1)
h : mergeBitRes i (getBit i q) p = q
⊢ getRes i q = p | case intro.intro
m : ℕ
p : BV m
i : Fin (m + 1)
b : Bool
p' : BV m
h : mergeBitRes i (getBit i (mergeBitRes i b p')) p = mergeBitRes i b p'
⊢ getRes i (mergeBitRes i b p') = p | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
q : BV (m + 1)
p : BV m
i : Fin (m + 1)
h : mergeBitRes i (getBit i q) p = q
⊢ getRes i q = p
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_inv | [408, 1] | [410, 39] | rw [getRes_mergeBitRes] | case intro.intro
m : ℕ
p : BV m
i : Fin (m + 1)
b : Bool
p' : BV m
h : mergeBitRes i (getBit i (mergeBitRes i b p')) p = mergeBitRes i b p'
⊢ getRes i (mergeBitRes i b p') = p | case intro.intro
m : ℕ
p : BV m
i : Fin (m + 1)
b : Bool
p' : BV m
h : mergeBitRes i (getBit i (mergeBitRes i b p')) p = mergeBitRes i b p'
⊢ p' = p | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro
m : ℕ
p : BV m
i : Fin (m + 1)
b : Bool
p' : BV m
h : mergeBitRes i (getBit i (mergeBitRes i b p')) p = mergeBitRes i b p'
⊢ getRes i (mergeBitRes i b p') = p
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_inv | [408, 1] | [410, 39] | exact (mergeBitRes_Fin_inj i h).symm | case intro.intro
m : ℕ
p : BV m
i : Fin (m + 1)
b : Bool
p' : BV m
h : mergeBitRes i (getBit i (mergeBitRes i b p')) p = mergeBitRes i b p'
⊢ p' = p | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro
m : ℕ
p : BV m
i : Fin (m + 1)
b : Bool
p' : BV m
h : mergeBitRes i (getBit i (mergeBitRes i b p')) p = mergeBitRes i b p'
⊢ p' = p
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_inv | [412, 1] | [414, 40] | rcases mergeBitRes_surj i q with ⟨b', p', rfl⟩ | m : ℕ
b : Bool
q : BV (m + 1)
i : Fin (m + 1)
h : mergeBitRes i b (getRes i q) = q
⊢ getBit i q = b | case intro.intro
m : ℕ
b : Bool
i : Fin (m + 1)
b' : Bool
p' : BV m
h : mergeBitRes i b (getRes i (mergeBitRes i b' p')) = mergeBitRes i b' p'
⊢ getBit i (mergeBitRes i b' p') = b | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
b : Bool
q : BV (m + 1)
i : Fin (m + 1)
h : mergeBitRes i b (getRes i q) = q
⊢ getBit i q = b
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_inv | [412, 1] | [414, 40] | rw [getBit_mergeBitRes] | case intro.intro
m : ℕ
b : Bool
i : Fin (m + 1)
b' : Bool
p' : BV m
h : mergeBitRes i b (getRes i (mergeBitRes i b' p')) = mergeBitRes i b' p'
⊢ getBit i (mergeBitRes i b' p') = b | case intro.intro
m : ℕ
b : Bool
i : Fin (m + 1)
b' : Bool
p' : BV m
h : mergeBitRes i b (getRes i (mergeBitRes i b' p')) = mergeBitRes i b' p'
⊢ b' = b | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro
m : ℕ
b : Bool
i : Fin (m + 1)
b' : Bool
p' : BV m
h : mergeBitRes i b (getRes i (mergeBitRes i b' p')) = mergeBitRes i b' p'
⊢ getBit i (mergeBitRes i b' p') = b
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_inv | [412, 1] | [414, 40] | exact (mergeBitRes_Bool_inj i h).symm | case intro.intro
m : ℕ
b : Bool
i : Fin (m + 1)
b' : Bool
p' : BV m
h : mergeBitRes i b (getRes i (mergeBitRes i b' p')) = mergeBitRes i b' p'
⊢ b' = b | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro
m : ℕ
b : Bool
i : Fin (m + 1)
b' : Bool
p' : BV m
h : mergeBitRes i b (getRes i (mergeBitRes i b' p')) = mergeBitRes i b' p'
⊢ b' = b
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | forall_iff_forall_mergeBitRes | [416, 1] | [418, 95] | rcases mergeBitRes_surj i q with ⟨b, p, rfl⟩ | m : ℕ
i : Fin (m + 1)
pr : BV (m + 1) → Prop
h : ∀ (b : Bool) (p : BV m), pr (mergeBitRes i b p)
q : BV (m + 1)
⊢ pr q | case intro.intro
m : ℕ
i : Fin (m + 1)
pr : BV (m + 1) → Prop
h : ∀ (b : Bool) (p : BV m), pr (mergeBitRes i b p)
b : Bool
p : BV m
⊢ pr (mergeBitRes i b p) | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
pr : BV (m + 1) → Prop
h : ∀ (b : Bool) (p : BV m), pr (mergeBitRes i b p)
q : BV (m + 1)
⊢ pr q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | forall_iff_forall_mergeBitRes | [416, 1] | [418, 95] | exact h _ _ | case intro.intro
m : ℕ
i : Fin (m + 1)
pr : BV (m + 1) → Prop
h : ∀ (b : Bool) (p : BV m), pr (mergeBitRes i b p)
b : Bool
p : BV m
⊢ pr (mergeBitRes i b p) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro
m : ℕ
i : Fin (m + 1)
pr : BV (m + 1) → Prop
h : ∀ (b : Bool) (p : BV m), pr (mergeBitRes i b p)
b : Bool
p : BV m
⊢ pr (mergeBitRes i b p)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | forall_iff_forall_mergeBitRes_bool | [420, 1] | [426, 33] | rcases mergeBitRes_surj i q with ⟨(h|h), p, rfl⟩ | m : ℕ
i : Fin (m + 1)
pr : BV (m + 1) → Prop
h : (∀ (p : BV m), pr (mergeBitRes i false p)) ∧ ∀ (p : BV m), pr (mergeBitRes i true p)
q : BV (m + 1)
⊢ pr q | case intro.false.intro
m : ℕ
i : Fin (m + 1)
pr : BV (m + 1) → Prop
h : (∀ (p : BV m), pr (mergeBitRes i false p)) ∧ ∀ (p : BV m), pr (mergeBitRes i true p)
p : BV m
⊢ pr (mergeBitRes i false p)
case intro.true.intro
m : ℕ
i : Fin (m + 1)
pr : BV (m + 1) → Prop
h : (∀ (p : BV m), pr (mergeBitRes i false p)) ∧ ∀ (p : BV m), pr (mergeBitRes i true p)
p : BV m
⊢ pr (mergeBitRes i true p) | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
pr : BV (m + 1) → Prop
h : (∀ (p : BV m), pr (mergeBitRes i false p)) ∧ ∀ (p : BV m), pr (mergeBitRes i true p)
q : BV (m + 1)
⊢ pr q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | forall_iff_forall_mergeBitRes_bool | [420, 1] | [426, 33] | exact h.1 _ | case intro.false.intro
m : ℕ
i : Fin (m + 1)
pr : BV (m + 1) → Prop
h : (∀ (p : BV m), pr (mergeBitRes i false p)) ∧ ∀ (p : BV m), pr (mergeBitRes i true p)
p : BV m
⊢ pr (mergeBitRes i false p) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.false.intro
m : ℕ
i : Fin (m + 1)
pr : BV (m + 1) → Prop
h : (∀ (p : BV m), pr (mergeBitRes i false p)) ∧ ∀ (p : BV m), pr (mergeBitRes i true p)
p : BV m
⊢ pr (mergeBitRes i false p)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | forall_iff_forall_mergeBitRes_bool | [420, 1] | [426, 33] | exact h.2 _ | case intro.true.intro
m : ℕ
i : Fin (m + 1)
pr : BV (m + 1) → Prop
h : (∀ (p : BV m), pr (mergeBitRes i false p)) ∧ ∀ (p : BV m), pr (mergeBitRes i true p)
p : BV m
⊢ pr (mergeBitRes i true p) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.true.intro
m : ℕ
i : Fin (m + 1)
pr : BV (m + 1) → Prop
h : (∀ (p : BV m), pr (mergeBitRes i false p)) ∧ ∀ (p : BV m), pr (mergeBitRes i true p)
p : BV m
⊢ pr (mergeBitRes i true p)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | ne_iff_getBit_ne_or_getRes_ne | [441, 1] | [443, 51] | rw [ne_eq q₁, getRes_getBit_inj_iff i, not_and_or] | m : ℕ
q₁ q₂ : BV (m + 1)
i : Fin (m + 1)
⊢ q₁ ≠ q₂ ↔ getBit i q₁ ≠ getBit i q₂ ∨ getRes i q₁ ≠ getRes i q₂ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
q₁ q₂ : BV (m + 1)
i : Fin (m + 1)
⊢ q₁ ≠ q₂ ↔ getBit i q₁ ≠ getBit i q₂ ∨ getRes i q₁ ≠ getRes i q₂
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_ext_iff | [451, 1] | [457, 54] | refine' ⟨fun h _ => h ▸ rfl, fun h => _⟩ | m : ℕ
q q' : BV (m + 1)
⊢ q = q' ↔ ∀ (i : Fin (m + 1)), getBit i q = getBit i q' | m : ℕ
q q' : BV (m + 1)
h : ∀ (i : Fin (m + 1)), getBit i q = getBit i q'
⊢ q = q' | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
q q' : BV (m + 1)
⊢ q = q' ↔ ∀ (i : Fin (m + 1)), getBit i q = getBit i q'
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_ext_iff | [451, 1] | [457, 54] | induction' m with m IH | m : ℕ
q q' : BV (m + 1)
h : ∀ (i : Fin (m + 1)), getBit i q = getBit i q'
⊢ q = q' | case zero
q q' : BV (0 + 1)
h : ∀ (i : Fin (0 + 1)), getBit i q = getBit i q'
⊢ q = q'
case succ
m : ℕ
IH : ∀ {q q' : BV (m + 1)}, (∀ (i : Fin (m + 1)), getBit i q = getBit i q') → q = q'
q q' : BV (m + 1 + 1)
h : ∀ (i : Fin (m + 1 + 1)), getBit i q = getBit i q'
⊢ q = q' | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
q q' : BV (m + 1)
h : ∀ (i : Fin (m + 1)), getBit i q = getBit i q'
⊢ q = q'
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_ext_iff | [451, 1] | [457, 54] | simp_rw [getRes_getBit_inj_iff 0, Fin.eq_zero, and_true, h] | case zero
q q' : BV (0 + 1)
h : ∀ (i : Fin (0 + 1)), getBit i q = getBit i q'
⊢ q = q' | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case zero
q q' : BV (0 + 1)
h : ∀ (i : Fin (0 + 1)), getBit i q = getBit i q'
⊢ q = q'
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_ext_iff | [451, 1] | [457, 54] | simp_rw [Fin.forall_fin_succ (P := fun i => getBit i q = getBit i q'), getBit_succ] at h | case succ
m : ℕ
IH : ∀ {q q' : BV (m + 1)}, (∀ (i : Fin (m + 1)), getBit i q = getBit i q') → q = q'
q q' : BV (m + 1 + 1)
h : ∀ (i : Fin (m + 1 + 1)), getBit i q = getBit i q'
⊢ q = q' | case succ
m : ℕ
IH : ∀ {q q' : BV (m + 1)}, (∀ (i : Fin (m + 1)), getBit i q = getBit i q') → q = q'
q q' : BV (m + 1 + 1)
h : getBit 0 q = getBit 0 q' ∧ ∀ (i : Fin (m + 1)), getBit i (getRes 0 q) = getBit i (getRes 0 q')
⊢ q = q' | Please generate a tactic in lean4 to solve the state.
STATE:
case succ
m : ℕ
IH : ∀ {q q' : BV (m + 1)}, (∀ (i : Fin (m + 1)), getBit i q = getBit i q') → q = q'
q q' : BV (m + 1 + 1)
h : ∀ (i : Fin (m + 1 + 1)), getBit i q = getBit i q'
⊢ q = q'
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_ext_iff | [451, 1] | [457, 54] | exact (getRes_getBit_inj_iff 0).mpr ⟨h.1, IH h.2⟩ | case succ
m : ℕ
IH : ∀ {q q' : BV (m + 1)}, (∀ (i : Fin (m + 1)), getBit i q = getBit i q') → q = q'
q q' : BV (m + 1 + 1)
h : getBit 0 q = getBit 0 q' ∧ ∀ (i : Fin (m + 1)), getBit i (getRes 0 q) = getBit i (getRes 0 q')
⊢ q = q' | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case succ
m : ℕ
IH : ∀ {q q' : BV (m + 1)}, (∀ (i : Fin (m + 1)), getBit i q = getBit i q') → q = q'
q q' : BV (m + 1 + 1)
h : getBit 0 q = getBit 0 q' ∧ ∀ (i : Fin (m + 1)), getBit i (getRes 0 q) = getBit i (getRes 0 q')
⊢ q = q'
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | bitInvar_comp_of_bitInvar | [479, 1] | [480, 60] | simp_rw [Function.comp_apply, hf (g q), hg q] | a✝ : ℕ
i : Fin (a✝ + 1)
f g : Function.End (BV (a✝ + 1))
hf : bitInvar i f
hg : bitInvar i g
q : BV (a✝ + 1)
⊢ getBit i ((f ∘ g) q) = getBit i q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
f g : Function.End (BV (a✝ + 1))
hf : bitInvar i f
hg : bitInvar i g
q : BV (a✝ + 1)
⊢ getBit i ((f ∘ g) q) = getBit i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | bitInvar_of_comp_bitInvar_bitInvar | [485, 1] | [486, 75] | rw [← h (g q), ← hfg q, Function.comp_apply] | a✝ : ℕ
i : Fin (a✝ + 1)
f g : BV (a✝ + 1) → BV (a✝ + 1)
hfg : bitInvar i (f ∘ g)
h : bitInvar i f
q : BV (a✝ + 1)
⊢ getBit i (g q) = getBit i q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
f g : BV (a✝ + 1) → BV (a✝ + 1)
hfg : bitInvar i (f ∘ g)
h : bitInvar i f
q : BV (a✝ + 1)
⊢ getBit i (g q) = getBit i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_getBit_getRes_apply_eq_apply_of_bitinvar | [501, 1] | [503, 40] | rw [← h q, mergeBitRes_getBit_getRes] | a✝ : ℕ
i : Fin (a✝ + 1)
f : Function.End (BV (a✝ + 1))
q : BV (a✝ + 1)
h : bitInvar i f
⊢ mergeBitRes i (getBit i q) (getRes i (f q)) = f q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
f : Function.End (BV (a✝ + 1))
q : BV (a✝ + 1)
h : bitInvar i f
⊢ mergeBitRes i (getBit i q) (getRes i (f q)) = f q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_getRes_apply_mergeBitRes_of_bitinvar | [505, 1] | [508, 88] | convert (getBit_mergeBitRes ▸ mergeBitRes_getBit_getRes_apply_eq_apply_of_bitinvar h) | a✝ : ℕ
i : Fin (a✝ + 1)
f : Function.End (BV (a✝ + 1))
b : Bool
p : BV a✝
h : bitInvar i f
⊢ mergeBitRes i b (getRes i (f (mergeBitRes i b p))) = f (mergeBitRes i b p) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
f : Function.End (BV (a✝ + 1))
b : Bool
p : BV a✝
h : bitInvar i f
⊢ mergeBitRes i b (getRes i (f (mergeBitRes i b p))) = f (mergeBitRes i b p)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | endoOfBoolArrowEndo_bitInvar | [596, 1] | [599, 38] | simp_rw [bitInvar_iff_getBit_apply_eq_getBit, endoOfBoolArrowEndo_def,
getBit_mergeBitRes, implies_true] | m : ℕ
i : Fin (m + 1)
f : Bool → Function.End (BV m)
⊢ bitInvar i (endoOfBoolArrowEndo i f) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
f : Bool → Function.End (BV m)
⊢ bitInvar i (endoOfBoolArrowEndo i f)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | endoOfBoolArrowEndo_comp | [605, 1] | [608, 59] | simp_rw [Function.End.ext_iff, Function.comp_apply, endoOfBoolArrowEndo_def, getBit_mergeBitRes,
getRes_mergeBitRes, Function.comp_apply, implies_true] | m : ℕ
i : Fin (m + 1)
f g : Bool → Function.End (BV m)
⊢ (endoOfBoolArrowEndo i fun b => f b ∘ g b) = endoOfBoolArrowEndo i f ∘ endoOfBoolArrowEndo i g | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
f g : Bool → Function.End (BV m)
⊢ (endoOfBoolArrowEndo i fun b => f b ∘ g b) = endoOfBoolArrowEndo i f ∘ endoOfBoolArrowEndo i g
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | endoOfBoolArrowEndo_rightInverse | [621, 1] | [624, 24] | ext | m : ℕ
i : Fin (m + 1)
f : Bool → Function.End (BV m)
⊢ boolArrowEndoOfEndo i (endoOfBoolArrowEndo i f) = f | case h.H.h
m : ℕ
i : Fin (m + 1)
f : Bool → Function.End (BV m)
x✝¹ : Bool
x✝ : BV m
⊢ ↑(boolArrowEndoOfEndo i (endoOfBoolArrowEndo i f) x✝¹ x✝) = ↑(f x✝¹ x✝) | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
f : Bool → Function.End (BV m)
⊢ boolArrowEndoOfEndo i (endoOfBoolArrowEndo i f) = f
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | endoOfBoolArrowEndo_rightInverse | [621, 1] | [624, 24] | simp_rw [boolArrowEndoOfEndo_def, endoOfBoolArrowEndo_def, getBit_mergeBitRes,
getRes_mergeBitRes] | case h.H.h
m : ℕ
i : Fin (m + 1)
f : Bool → Function.End (BV m)
x✝¹ : Bool
x✝ : BV m
⊢ ↑(boolArrowEndoOfEndo i (endoOfBoolArrowEndo i f) x✝¹ x✝) = ↑(f x✝¹ x✝) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case h.H.h
m : ℕ
i : Fin (m + 1)
f : Bool → Function.End (BV m)
x✝¹ : Bool
x✝ : BV m
⊢ ↑(boolArrowEndoOfEndo i (endoOfBoolArrowEndo i f) x✝¹ x✝) = ↑(f x✝¹ x✝)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | endoOfBoolArrowEndo_leftInvOn | [626, 1] | [629, 44] | ext q | m : ℕ
i : Fin (m + 1)
f : Function.End (BV (m + 1))
hf : f ∈ bitInvar i
⊢ endoOfBoolArrowEndo i (boolArrowEndoOfEndo i f) = f | case H.h
m : ℕ
i : Fin (m + 1)
f : Function.End (BV (m + 1))
hf : f ∈ bitInvar i
q : BV (m + 1)
⊢ ↑(endoOfBoolArrowEndo i (boolArrowEndoOfEndo i f) q) = ↑(f q) | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
f : Function.End (BV (m + 1))
hf : f ∈ bitInvar i
⊢ endoOfBoolArrowEndo i (boolArrowEndoOfEndo i f) = f
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | endoOfBoolArrowEndo_leftInvOn | [626, 1] | [629, 44] | simp_rw [endoOfBoolArrowEndo_def, boolArrowEndoOfEndo_def, mergeBitRes_getBit_getRes,
mergeBitRes_getRes_of_getBit_eq (hf q)] | case H.h
m : ℕ
i : Fin (m + 1)
f : Function.End (BV (m + 1))
hf : f ∈ bitInvar i
q : BV (m + 1)
⊢ ↑(endoOfBoolArrowEndo i (boolArrowEndoOfEndo i f) q) = ↑(f q) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case H.h
m : ℕ
i : Fin (m + 1)
f : Function.End (BV (m + 1))
hf : f ∈ bitInvar i
q : BV (m + 1)
⊢ ↑(endoOfBoolArrowEndo i (boolArrowEndoOfEndo i f) q) = ↑(f q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | endoOfBoolArrowEndo_leftInverse_apply | [674, 1] | [679, 62] | simp_rw [endoOfBoolArrowEndo_def, getBit_mergeBitRes, getRes_mergeBitRes,
hfg (getBit i q) (getRes i q), mergeBitRes_getBit_getRes] | m : ℕ
i : Fin (m + 1)
f g : Bool → Function.End (BV m)
hfg : ∀ (b : Bool), Function.LeftInverse (f b) (g b)
q : BV (m + 1)
⊢ endoOfBoolArrowEndo i f (endoOfBoolArrowEndo i g q) = q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
f g : Bool → Function.End (BV m)
hfg : ∀ (b : Bool), Function.LeftInverse (f b) (g b)
q : BV (m + 1)
⊢ endoOfBoolArrowEndo i f (endoOfBoolArrowEndo i g q) = q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | boolArrowEndoOfEndo_leftInverse_apply_ofBitInvarLeft | [687, 1] | [692, 49] | simp_rw [boolArrowEndoOfEndo_def,
mergeBitRes_getRes_apply_mergeBitRes_of_bitinvar (bitInvar_of_leftInverse_bitInvar hfg hf),
hfg (mergeBitRes i b q), getRes_mergeBitRes] | m : ℕ
i : Fin (m + 1)
f g : Function.End (BV (m + 1))
hfg : Function.LeftInverse f g
hf : bitInvar i f
b : Bool
q : BV m
⊢ boolArrowEndoOfEndo i f b (boolArrowEndoOfEndo i g b q) = q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
f g : Function.End (BV (m + 1))
hfg : Function.LeftInverse f g
hf : bitInvar i f
b : Bool
q : BV m
⊢ boolArrowEndoOfEndo i f b (boolArrowEndoOfEndo i g b q) = q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | boolArrowEndoOfEndo_rightInverse_apply_ofBitInvarLeft | [694, 1] | [698, 49] | simp_rw [boolArrowEndoOfEndo_def, mergeBitRes_getRes_apply_mergeBitRes_of_bitinvar hf,
hfg (mergeBitRes i b q), getRes_mergeBitRes] | m : ℕ
i : Fin (m + 1)
f g : Function.End (BV (m + 1))
hfg : Function.RightInverse f g
hf : bitInvar i f
b : Bool
q : BV m
⊢ boolArrowEndoOfEndo i g b (boolArrowEndoOfEndo i f b q) = q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
f g : Function.End (BV (m + 1))
hfg : Function.RightInverse f g
hf : bitInvar i f
b : Bool
q : BV m
⊢ boolArrowEndoOfEndo i g b (boolArrowEndoOfEndo i f b q) = q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | boolArrowEndoOfEndo_comp_ofBitInvarRight | [710, 1] | [714, 57] | ext | m : ℕ
i : Fin (m + 1)
f g : Function.End (BV (m + 1))
hg : bitInvar i g
b : Bool
⊢ boolArrowEndoOfEndo i (f ∘ g) b = boolArrowEndoOfEndo i f b ∘ boolArrowEndoOfEndo i g b | case H.h
m : ℕ
i : Fin (m + 1)
f g : Function.End (BV (m + 1))
hg : bitInvar i g
b : Bool
x✝ : BV m
⊢ ↑(boolArrowEndoOfEndo i (f ∘ g) b x✝) = ↑((boolArrowEndoOfEndo i f b ∘ boolArrowEndoOfEndo i g b) x✝) | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
f g : Function.End (BV (m + 1))
hg : bitInvar i g
b : Bool
⊢ boolArrowEndoOfEndo i (f ∘ g) b = boolArrowEndoOfEndo i f b ∘ boolArrowEndoOfEndo i g b
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | boolArrowEndoOfEndo_comp_ofBitInvarRight | [710, 1] | [714, 57] | simp_rw [boolArrowEndoOfEndo_def, Function.comp_apply, boolArrowEndoOfEndo_def,
mergeBitRes_getRes_apply_mergeBitRes_of_bitinvar hg] | case H.h
m : ℕ
i : Fin (m + 1)
f g : Function.End (BV (m + 1))
hg : bitInvar i g
b : Bool
x✝ : BV m
⊢ ↑(boolArrowEndoOfEndo i (f ∘ g) b x✝) = ↑((boolArrowEndoOfEndo i f b ∘ boolArrowEndoOfEndo i g b) x✝) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case H.h
m : ℕ
i : Fin (m + 1)
f g : Function.End (BV (m + 1))
hg : bitInvar i g
b : Bool
x✝ : BV m
⊢ ↑(boolArrowEndoOfEndo i (f ∘ g) b x✝) = ↑((boolArrowEndoOfEndo i f b ∘ boolArrowEndoOfEndo i g b) x✝)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | boolArrowEndoOfEndo_mul_ofBitInvarRight | [716, 1] | [719, 62] | ext : 1 | m : ℕ
i : Fin (m + 1)
f g : Function.End (BV (m + 1))
hg : bitInvar i g
⊢ boolArrowEndoOfEndo i (f * g) = boolArrowEndoOfEndo i f * boolArrowEndoOfEndo i g | case h
m : ℕ
i : Fin (m + 1)
f g : Function.End (BV (m + 1))
hg : bitInvar i g
x✝ : Bool
⊢ boolArrowEndoOfEndo i (f * g) x✝ = (boolArrowEndoOfEndo i f * boolArrowEndoOfEndo i g) x✝ | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
f g : Function.End (BV (m + 1))
hg : bitInvar i g
⊢ boolArrowEndoOfEndo i (f * g) = boolArrowEndoOfEndo i f * boolArrowEndoOfEndo i g
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | boolArrowEndoOfEndo_mul_ofBitInvarRight | [716, 1] | [719, 62] | exact boolArrowEndoOfEndo_comp_ofBitInvarRight hg | case h
m : ℕ
i : Fin (m + 1)
f g : Function.End (BV (m + 1))
hg : bitInvar i g
x✝ : Bool
⊢ boolArrowEndoOfEndo i (f * g) x✝ = (boolArrowEndoOfEndo i f * boolArrowEndoOfEndo i g) x✝ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case h
m : ℕ
i : Fin (m + 1)
f g : Function.End (BV (m + 1))
hg : bitInvar i g
x✝ : Bool
⊢ boolArrowEndoOfEndo i (f * g) x✝ = (boolArrowEndoOfEndo i f * boolArrowEndoOfEndo i g) x✝
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | flipBit_base | [733, 1] | [735, 42] | simp_rw [Equiv.ext_iff, flipBit_apply, Fin.eq_zero i] | i : Fin (0 + 1)
⊢ flipBit i = Equiv.swap 0 1 | i : Fin (0 + 1)
⊢ ∀ (x : BV (0 + 1)), mergeBitRes 0 (!getBit 0 x) (getRes 0 x) = (Equiv.swap 0 1) x | Please generate a tactic in lean4 to solve the state.
STATE:
i : Fin (0 + 1)
⊢ flipBit i = Equiv.swap 0 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | flipBit_base | [733, 1] | [735, 42] | exact Fin.forall_fin_two.mpr ⟨rfl, rfl⟩ | i : Fin (0 + 1)
⊢ ∀ (x : BV (0 + 1)), mergeBitRes 0 (!getBit 0 x) (getRes 0 x) = (Equiv.swap 0 1) x | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
i : Fin (0 + 1)
⊢ ∀ (x : BV (0 + 1)), mergeBitRes 0 (!getBit 0 x) (getRes 0 x) = (Equiv.swap 0 1) x
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | flipBit_zero_apply | [737, 1] | [740, 78] | simp_rw [flipBit_apply, getBit_zero, Nat.pow_eq, finTwoEquiv_apply,
getRes_zero, mergeBitRes_zero, Bool.cond_not, Bool.cond_decide] | a✝ : ℕ
q : BV (a✝ + 1)
⊢ (flipBit 0) q = finProdFinEquiv (q.divNat, q.modNat.rev) | a✝ : ℕ
q : BV (a✝ + 1)
⊢ finProdFinEquiv (q.divNat, if q.modNat = 1 then 0 else 1) = finProdFinEquiv (q.divNat, q.modNat.rev) | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
q : BV (a✝ + 1)
⊢ (flipBit 0) q = finProdFinEquiv (q.divNat, q.modNat.rev)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | flipBit_zero_apply | [737, 1] | [740, 78] | rcases Fin.modNat_two_eq_zero_or_one q with (h | h) <;> simp_rw [h] <;> rfl | a✝ : ℕ
q : BV (a✝ + 1)
⊢ finProdFinEquiv (q.divNat, if q.modNat = 1 then 0 else 1) = finProdFinEquiv (q.divNat, q.modNat.rev) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
q : BV (a✝ + 1)
⊢ finProdFinEquiv (q.divNat, if q.modNat = 1 then 0 else 1) = finProdFinEquiv (q.divNat, q.modNat.rev)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | flipBit_mergeBitRes | [742, 1] | [744, 59] | rw [flipBit_apply, getBit_mergeBitRes, getRes_mergeBitRes] | a✝ : ℕ
i : Fin (a✝ + 1)
b : Bool
p : BV a✝
⊢ (flipBit i) (mergeBitRes i b p) = mergeBitRes i (!b) p | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
b : Bool
p : BV a✝
⊢ (flipBit i) (mergeBitRes i b p) = mergeBitRes i (!b) p
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | flipBit_mergeBitRes_zero | [752, 1] | [756, 6] | simp_rw [flipBit_zero_apply, mergeBitRes_zero_divNat,
mergeBitRes_zero_modNat, Bool.apply_cond (Fin.rev)] | b : Bool
a✝ : ℕ
p : BV a✝
⊢ (flipBit 0) (mergeBitRes 0 b p) = finProdFinEquiv (p, bif b then 0 else 1) | b : Bool
a✝ : ℕ
p : BV a✝
⊢ finProdFinEquiv (p, bif b then Fin.rev 1 else Fin.rev 0) = finProdFinEquiv (p, bif b then 0 else 1) | Please generate a tactic in lean4 to solve the state.
STATE:
b : Bool
a✝ : ℕ
p : BV a✝
⊢ (flipBit 0) (mergeBitRes 0 b p) = finProdFinEquiv (p, bif b then 0 else 1)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | flipBit_mergeBitRes_zero | [752, 1] | [756, 6] | rfl | b : Bool
a✝ : ℕ
p : BV a✝
⊢ finProdFinEquiv (p, bif b then Fin.rev 1 else Fin.rev 0) = finProdFinEquiv (p, bif b then 0 else 1) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
b : Bool
a✝ : ℕ
p : BV a✝
⊢ finProdFinEquiv (p, bif b then Fin.rev 1 else Fin.rev 0) = finProdFinEquiv (p, bif b then 0 else 1)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | mergeBitRes_getRes_of_getBit_not | [764, 1] | [766, 41] | simp_rw [flipBit_apply, h, Bool.not_not] | a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
b : Bool
h : getBit i q = !b
⊢ mergeBitRes i b (getRes i q) = (flipBit i) q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
b : Bool
h : getBit i q = !b
⊢ mergeBitRes i b (getRes i q) = (flipBit i) q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | flipBit_succ | [775, 1] | [777, 42] | simp_rw [flipBit_apply, getBit_succ, getRes_succ, mergeBitRes_succ,
getBit_mergeBitRes, getRes_mergeBitRes] | a✝ : ℕ
q : BV (a✝ + 1 + 1)
i : Fin (a✝ + 1)
⊢ (flipBit i.succ) q = mergeBitRes 0 (getBit 0 q) ((flipBit i) (getRes 0 q)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
q : BV (a✝ + 1 + 1)
i : Fin (a✝ + 1)
⊢ (flipBit i.succ) q = mergeBitRes 0 (getBit 0 q) ((flipBit i) (getRes 0 q))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | flipBit_castSucc | [779, 1] | [782, 42] | simp_rw [flipBit_apply, getBit_castSucc, getRes_castSucc, mergeBitRes_castSucc,
getBit_mergeBitRes, getRes_mergeBitRes] | a✝ : ℕ
q : BV (a✝ + 1 + 1)
i : Fin (a✝ + 1)
⊢ (flipBit i.castSucc) q =
mergeBitRes (Fin.last (a✝ + 1)) (getBit (Fin.last (a✝ + 1)) q) ((flipBit i) (getRes (Fin.last (a✝ + 1)) q)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
q : BV (a✝ + 1 + 1)
i : Fin (a✝ + 1)
⊢ (flipBit i.castSucc) q =
mergeBitRes (Fin.last (a✝ + 1)) (getBit (Fin.last (a✝ + 1)) q) ((flipBit i) (getRes (Fin.last (a✝ + 1)) q))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | flipBit_succAbove | [784, 1] | [787, 42] | simp_rw [flipBit_apply, getBit_succAbove, getRes_succAbove, mergeBitRes_succAbove,
getBit_mergeBitRes, getRes_mergeBitRes] | m : ℕ
i : Fin (m + 1)
q : BV (m + 1 + 1)
j : Fin (m + 2)
⊢ (flipBit (j.succAbove i)) q = mergeBitRes j (getBit j q) ((flipBit i) (getRes j q)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
q : BV (m + 1 + 1)
j : Fin (m + 2)
⊢ (flipBit (j.succAbove i)) q = mergeBitRes j (getBit j q) ((flipBit i) (getRes j q))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_iff | [789, 1] | [794, 25] | rcases mergeBitRes_surj i q with ⟨bq, pq, rfl⟩ | a✝ : ℕ
q : BV (a✝ + 1)
i : Fin (a✝ + 1)
r : BV (a✝ + 1)
⊢ q = (flipBit i) r ↔ getBit i q = !getBit i r ∧ getRes i q = getRes i r | case intro.intro
a✝ : ℕ
i : Fin (a✝ + 1)
r : BV (a✝ + 1)
bq : Bool
pq : BV a✝
⊢ mergeBitRes i bq pq = (flipBit i) r ↔
getBit i (mergeBitRes i bq pq) = !getBit i r ∧ getRes i (mergeBitRes i bq pq) = getRes i r | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
q : BV (a✝ + 1)
i : Fin (a✝ + 1)
r : BV (a✝ + 1)
⊢ q = (flipBit i) r ↔ getBit i q = !getBit i r ∧ getRes i q = getRes i r
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_iff | [789, 1] | [794, 25] | rcases mergeBitRes_surj i r with ⟨br, pr, rfl⟩ | case intro.intro
a✝ : ℕ
i : Fin (a✝ + 1)
r : BV (a✝ + 1)
bq : Bool
pq : BV a✝
⊢ mergeBitRes i bq pq = (flipBit i) r ↔
getBit i (mergeBitRes i bq pq) = !getBit i r ∧ getRes i (mergeBitRes i bq pq) = getRes i r | case intro.intro.intro.intro
a✝ : ℕ
i : Fin (a✝ + 1)
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
⊢ mergeBitRes i bq pq = (flipBit i) (mergeBitRes i br pr) ↔
getBit i (mergeBitRes i bq pq) = !getBit i (mergeBitRes i br pr) ∧
getRes i (mergeBitRes i bq pq) = getRes i (mergeBitRes i br pr) | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro
a✝ : ℕ
i : Fin (a✝ + 1)
r : BV (a✝ + 1)
bq : Bool
pq : BV a✝
⊢ mergeBitRes i bq pq = (flipBit i) r ↔
getBit i (mergeBitRes i bq pq) = !getBit i r ∧ getRes i (mergeBitRes i bq pq) = getRes i r
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_iff | [789, 1] | [794, 25] | simp_rw [flipBit_mergeBitRes, getBit_mergeBitRes, getRes_mergeBitRes,
mergeBitRes_inj_iff] | case intro.intro.intro.intro
a✝ : ℕ
i : Fin (a✝ + 1)
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
⊢ mergeBitRes i bq pq = (flipBit i) (mergeBitRes i br pr) ↔
getBit i (mergeBitRes i bq pq) = !getBit i (mergeBitRes i br pr) ∧
getRes i (mergeBitRes i bq pq) = getRes i (mergeBitRes i br pr) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro.intro.intro
a✝ : ℕ
i : Fin (a✝ + 1)
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
⊢ mergeBitRes i bq pq = (flipBit i) (mergeBitRes i br pr) ↔
getBit i (mergeBitRes i bq pq) = !getBit i (mergeBitRes i br pr) ∧
getRes i (mergeBitRes i bq pq) = getRes i (mergeBitRes i br pr)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | flipBit_flipBit | [796, 1] | [799, 45] | simp_rw [flipBit_apply (q := q), flipBit_mergeBitRes,
Bool.not_not, mergeBitRes_getBit_getRes] | a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
⊢ (flipBit i) ((flipBit i) q) = q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
⊢ (flipBit i) ((flipBit i) q) = q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | flipBit_mul_self | [807, 1] | [810, 20] | rw [mul_eq_one_iff_inv_eq] | a✝ : ℕ
i : Fin (a✝ + 1)
⊢ flipBit i * flipBit i = 1 | a✝ : ℕ
i : Fin (a✝ + 1)
⊢ (flipBit i)⁻¹ = flipBit i | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
⊢ flipBit i * flipBit i = 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | flipBit_mul_self | [807, 1] | [810, 20] | exact flipBit_inv | a✝ : ℕ
i : Fin (a✝ + 1)
⊢ (flipBit i)⁻¹ = flipBit i | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
⊢ (flipBit i)⁻¹ = flipBit i
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | flipBit_mul_cancel_right | [812, 1] | [814, 44] | rw [mul_assoc, flipBit_mul_self, mul_one] | a✝ : ℕ
ρ : Equiv.Perm (BV (a✝ + 1))
i : Fin (a✝ + 1)
⊢ ρ * flipBit i * flipBit i = ρ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
ρ : Equiv.Perm (BV (a✝ + 1))
i : Fin (a✝ + 1)
⊢ ρ * flipBit i * flipBit i = ρ
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | flipBit_mul_cancel_left | [816, 1] | [818, 46] | rw [← mul_assoc, flipBit_mul_self, one_mul] | a✝ : ℕ
i : Fin (a✝ + 1)
ρ : Equiv.Perm (BV (a✝ + 1))
⊢ flipBit i * (flipBit i * ρ) = ρ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
ρ : Equiv.Perm (BV (a✝ + 1))
⊢ flipBit i * (flipBit i * ρ) = ρ
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_flipBit | [820, 1] | [822, 46] | simp_rw [flipBit_apply, getBit_mergeBitRes] | a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
⊢ getBit i ((flipBit i) q) = !getBit i q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
⊢ getBit i ((flipBit i) q) = !getBit i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_flipBit | [824, 1] | [826, 41] | rw [flipBit_apply, getRes_mergeBitRes] | a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
⊢ getRes i ((flipBit i) q) = getRes i q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
⊢ getRes i ((flipBit i) q) = getRes i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_flipBit_of_ne | [828, 1] | [833, 47] | cases m | m : ℕ
q : BV (m + 1)
i j : Fin (m + 1)
h : i ≠ j
⊢ getBit i ((flipBit j) q) = getBit i q | case zero
q : BV (0 + 1)
i j : Fin (0 + 1)
h : i ≠ j
⊢ getBit i ((flipBit j) q) = getBit i q
case succ
n✝ : ℕ
q : BV (n✝ + 1 + 1)
i j : Fin (n✝ + 1 + 1)
h : i ≠ j
⊢ getBit i ((flipBit j) q) = getBit i q | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
q : BV (m + 1)
i j : Fin (m + 1)
h : i ≠ j
⊢ getBit i ((flipBit j) q) = getBit i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_flipBit_of_ne | [828, 1] | [833, 47] | exact (h ((Fin.subsingleton_one).elim i j)).elim | case zero
q : BV (0 + 1)
i j : Fin (0 + 1)
h : i ≠ j
⊢ getBit i ((flipBit j) q) = getBit i q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case zero
q : BV (0 + 1)
i j : Fin (0 + 1)
h : i ≠ j
⊢ getBit i ((flipBit j) q) = getBit i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_flipBit_of_ne | [828, 1] | [833, 47] | rcases Fin.exists_succAbove_eq h with ⟨k, rfl⟩ | case succ
n✝ : ℕ
q : BV (n✝ + 1 + 1)
i j : Fin (n✝ + 1 + 1)
h : i ≠ j
⊢ getBit i ((flipBit j) q) = getBit i q | case succ.intro
n✝ : ℕ
q : BV (n✝ + 1 + 1)
j : Fin (n✝ + 1 + 1)
k : Fin (n✝ + 1)
h : j.succAbove k ≠ j
⊢ getBit (j.succAbove k) ((flipBit j) q) = getBit (j.succAbove k) q | Please generate a tactic in lean4 to solve the state.
STATE:
case succ
n✝ : ℕ
q : BV (n✝ + 1 + 1)
i j : Fin (n✝ + 1 + 1)
h : i ≠ j
⊢ getBit i ((flipBit j) q) = getBit i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_flipBit_of_ne | [828, 1] | [833, 47] | simp_rw [getBit_succAbove, getRes_flipBit] | case succ.intro
n✝ : ℕ
q : BV (n✝ + 1 + 1)
j : Fin (n✝ + 1 + 1)
k : Fin (n✝ + 1)
h : j.succAbove k ≠ j
⊢ getBit (j.succAbove k) ((flipBit j) q) = getBit (j.succAbove k) q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case succ.intro
n✝ : ℕ
q : BV (n✝ + 1 + 1)
j : Fin (n✝ + 1 + 1)
k : Fin (n✝ + 1)
h : j.succAbove k ≠ j
⊢ getBit (j.succAbove k) ((flipBit j) q) = getBit (j.succAbove k) q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_zero_flipBit_succ | [838, 1] | [842, 42] | cases m | m : ℕ
q : BV (m + 1)
i : Fin m
⊢ getBit 0 ((flipBit i.succ) q) = getBit 0 q | case zero
q : BV (0 + 1)
i : Fin 0
⊢ getBit 0 ((flipBit i.succ) q) = getBit 0 q
case succ
n✝ : ℕ
q : BV (n✝ + 1 + 1)
i : Fin (n✝ + 1)
⊢ getBit 0 ((flipBit i.succ) q) = getBit 0 q | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
q : BV (m + 1)
i : Fin m
⊢ getBit 0 ((flipBit i.succ) q) = getBit 0 q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_zero_flipBit_succ | [838, 1] | [842, 42] | exact i.elim0 | case zero
q : BV (0 + 1)
i : Fin 0
⊢ getBit 0 ((flipBit i.succ) q) = getBit 0 q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case zero
q : BV (0 + 1)
i : Fin 0
⊢ getBit 0 ((flipBit i.succ) q) = getBit 0 q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_zero_flipBit_succ | [838, 1] | [842, 42] | rw [flipBit_succ, getBit_mergeBitRes] | case succ
n✝ : ℕ
q : BV (n✝ + 1 + 1)
i : Fin (n✝ + 1)
⊢ getBit 0 ((flipBit i.succ) q) = getBit 0 q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case succ
n✝ : ℕ
q : BV (n✝ + 1 + 1)
i : Fin (n✝ + 1)
⊢ getBit 0 ((flipBit i.succ) q) = getBit 0 q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_succ_flipBit_zero | [844, 1] | [848, 42] | cases m | m : ℕ
q : BV (m + 1)
i : Fin m
⊢ getBit i.succ ((flipBit 0) q) = getBit i.succ q | case zero
q : BV (0 + 1)
i : Fin 0
⊢ getBit i.succ ((flipBit 0) q) = getBit i.succ q
case succ
n✝ : ℕ
q : BV (n✝ + 1 + 1)
i : Fin (n✝ + 1)
⊢ getBit i.succ ((flipBit 0) q) = getBit i.succ q | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
q : BV (m + 1)
i : Fin m
⊢ getBit i.succ ((flipBit 0) q) = getBit i.succ q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_succ_flipBit_zero | [844, 1] | [848, 42] | exact i.elim0 | case zero
q : BV (0 + 1)
i : Fin 0
⊢ getBit i.succ ((flipBit 0) q) = getBit i.succ q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case zero
q : BV (0 + 1)
i : Fin 0
⊢ getBit i.succ ((flipBit 0) q) = getBit i.succ q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_succ_flipBit_zero | [844, 1] | [848, 42] | simp_rw [getBit_succ, getRes_flipBit] | case succ
n✝ : ℕ
q : BV (n✝ + 1 + 1)
i : Fin (n✝ + 1)
⊢ getBit i.succ ((flipBit 0) q) = getBit i.succ q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case succ
n✝ : ℕ
q : BV (n✝ + 1 + 1)
i : Fin (n✝ + 1)
⊢ getBit i.succ ((flipBit 0) q) = getBit i.succ q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | flipBit_ne_self | [856, 1] | [859, 46] | apply ne_of_getBit_ne i | a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
⊢ (flipBit i) q ≠ q | a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
⊢ getBit i ((flipBit i) q) ≠ getBit i q | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
⊢ (flipBit i) q ≠ q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | flipBit_ne_self | [856, 1] | [859, 46] | rw [getBit_flipBit, ne_eq, Bool.not_not_eq] | a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
⊢ getBit i ((flipBit i) q) ≠ getBit i q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
q : BV (a✝ + 1)
⊢ getBit i ((flipBit i) q) ≠ getBit i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_zero_eq_and_getBit_zero_opp_of_lt_of_flipBit_gt | [861, 1] | [869, 67] | rcases mergeBitRes_surj 0 q with ⟨bq, pq, rfl⟩ | a✝ : ℕ
r q : BV (a✝ + 1)
h : r < q
hf : (flipBit 0) q < (flipBit 0) r
⊢ getBit 0 r = false ∧ getBit 0 q = true ∧ getRes 0 r = getRes 0 q | case intro.intro
a✝ : ℕ
r : BV (a✝ + 1)
bq : Bool
pq : BV a✝
h : r < mergeBitRes 0 bq pq
hf : (flipBit 0) (mergeBitRes 0 bq pq) < (flipBit 0) r
⊢ getBit 0 r = false ∧ getBit 0 (mergeBitRes 0 bq pq) = true ∧ getRes 0 r = getRes 0 (mergeBitRes 0 bq pq) | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
r q : BV (a✝ + 1)
h : r < q
hf : (flipBit 0) q < (flipBit 0) r
⊢ getBit 0 r = false ∧ getBit 0 q = true ∧ getRes 0 r = getRes 0 q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_zero_eq_and_getBit_zero_opp_of_lt_of_flipBit_gt | [861, 1] | [869, 67] | rcases mergeBitRes_surj 0 r with ⟨br, pr, rfl⟩ | case intro.intro
a✝ : ℕ
r : BV (a✝ + 1)
bq : Bool
pq : BV a✝
h : r < mergeBitRes 0 bq pq
hf : (flipBit 0) (mergeBitRes 0 bq pq) < (flipBit 0) r
⊢ getBit 0 r = false ∧ getBit 0 (mergeBitRes 0 bq pq) = true ∧ getRes 0 r = getRes 0 (mergeBitRes 0 bq pq) | case intro.intro.intro.intro
a✝ : ℕ
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
h : mergeBitRes 0 br pr < mergeBitRes 0 bq pq
hf : (flipBit 0) (mergeBitRes 0 bq pq) < (flipBit 0) (mergeBitRes 0 br pr)
⊢ getBit 0 (mergeBitRes 0 br pr) = false ∧
getBit 0 (mergeBitRes 0 bq pq) = true ∧ getRes 0 (mergeBitRes 0 br pr) = getRes 0 (mergeBitRes 0 bq pq) | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro
a✝ : ℕ
r : BV (a✝ + 1)
bq : Bool
pq : BV a✝
h : r < mergeBitRes 0 bq pq
hf : (flipBit 0) (mergeBitRes 0 bq pq) < (flipBit 0) r
⊢ getBit 0 r = false ∧ getBit 0 (mergeBitRes 0 bq pq) = true ∧ getRes 0 r = getRes 0 (mergeBitRes 0 bq pq)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_zero_eq_and_getBit_zero_opp_of_lt_of_flipBit_gt | [861, 1] | [869, 67] | simp_rw [flipBit_mergeBitRes, getBit_mergeBitRes, getRes_mergeBitRes,
Fin.lt_iff_val_lt_val, mergeBitRes_zero, finProdFinEquiv_apply_val, Bool.cond_not, add_comm,
Bool.apply_cond (Fin.val), Fin.val_one, Fin.val_zero] at hf h ⊢ | case intro.intro.intro.intro
a✝ : ℕ
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
h : mergeBitRes 0 br pr < mergeBitRes 0 bq pq
hf : (flipBit 0) (mergeBitRes 0 bq pq) < (flipBit 0) (mergeBitRes 0 br pr)
⊢ getBit 0 (mergeBitRes 0 br pr) = false ∧
getBit 0 (mergeBitRes 0 bq pq) = true ∧ getRes 0 (mergeBitRes 0 br pr) = getRes 0 (mergeBitRes 0 bq pq) | case intro.intro.intro.intro
a✝ : ℕ
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
hf : (2 * ↑pq + bif bq then 0 else 1) < 2 * ↑pr + bif br then 0 else 1
h : (2 * ↑pr + bif br then 1 else 0) < 2 * ↑pq + bif bq then 1 else 0
⊢ br = false ∧ bq = true ∧ pr = pq | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro.intro.intro
a✝ : ℕ
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
h : mergeBitRes 0 br pr < mergeBitRes 0 bq pq
hf : (flipBit 0) (mergeBitRes 0 bq pq) < (flipBit 0) (mergeBitRes 0 br pr)
⊢ getBit 0 (mergeBitRes 0 br pr) = false ∧
getBit 0 (mergeBitRes 0 bq pq) = true ∧ getRes 0 (mergeBitRes 0 br pr) = getRes 0 (mergeBitRes 0 bq pq)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_zero_eq_and_getBit_zero_opp_of_lt_of_flipBit_gt | [861, 1] | [869, 67] | rcases Nat.eq_false_true_of_cond_succ_lt_of_cond_succ_lt h hf with ⟨hr, hq, he⟩ | case intro.intro.intro.intro
a✝ : ℕ
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
hf : (2 * ↑pq + bif bq then 0 else 1) < 2 * ↑pr + bif br then 0 else 1
h : (2 * ↑pr + bif br then 1 else 0) < 2 * ↑pq + bif bq then 1 else 0
⊢ br = false ∧ bq = true ∧ pr = pq | case intro.intro.intro.intro.intro.intro
a✝ : ℕ
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
hf : (2 * ↑pq + bif bq then 0 else 1) < 2 * ↑pr + bif br then 0 else 1
h : (2 * ↑pr + bif br then 1 else 0) < 2 * ↑pq + bif bq then 1 else 0
hr : br = false
hq : bq = true
he : 2 * ↑pr = 2 * ↑pq
⊢ br = false ∧ bq = true ∧ pr = pq | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro.intro.intro
a✝ : ℕ
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
hf : (2 * ↑pq + bif bq then 0 else 1) < 2 * ↑pr + bif br then 0 else 1
h : (2 * ↑pr + bif br then 1 else 0) < 2 * ↑pq + bif bq then 1 else 0
⊢ br = false ∧ bq = true ∧ pr = pq
TACTIC:
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