Datasets:
pkuAI4M
/
lean_github

Dataset card Data Studio Files
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https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Extras/isLeft_invariant.lean
Sum.isRight_eq_of_liftRel_inr_right
[26, 1]
[28, 17]
simp
case inr Ξ± : Type u Ξ² : Type v α✝ : Type u_1 γ✝ : Type u_2 ra : α✝ β†’ γ✝ β†’ Prop β✝ : Type u_3 δ✝ : Type u_4 rb : β✝ β†’ δ✝ β†’ Prop d : δ✝ b✝ : β✝ a✝ : rb b✝ d ⊒ (inr b✝).isRight = true
no goals
Please generate a tactic in lean4 to solve the state. STATE: case inr Ξ± : Type u Ξ² : Type v α✝ : Type u_1 γ✝ : Type u_2 ra : α✝ β†’ γ✝ β†’ Prop β✝ : Type u_3 δ✝ : Type u_4 rb : β✝ β†’ δ✝ β†’ Prop d : δ✝ b✝ : β✝ a✝ : rb b✝ d ⊒ (inr b✝).isRight = true TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Extras/isLeft_invariant.lean
Sum.liftRel_equiv_left_iff_symm_right
[30, 1]
[33, 71]
convert (H (e.symm cd))
Ξ± : Type u Ξ² : Type v α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ H : βˆ€ (ab : α₁ βŠ• β₁), LiftRel ra rb (e ab) ab cd : Ξ±β‚‚ βŠ• Ξ²β‚‚ ⊒ LiftRel ra rb cd (e.symm cd)
case h.e'_7 Ξ± : Type u Ξ² : Type v α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ H : βˆ€ (ab : α₁ βŠ• β₁), LiftRel ra rb (e ab) ab cd : Ξ±β‚‚ βŠ• Ξ²β‚‚ ⊒ cd = e (e.symm cd)
Please generate a tactic in lean4 to solve the state. STATE: Ξ± : Type u Ξ² : Type v α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ H : βˆ€ (ab : α₁ βŠ• β₁), LiftRel ra rb (e ab) ab cd : Ξ±β‚‚ βŠ• Ξ²β‚‚ ⊒ LiftRel ra rb cd (e.symm cd) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Extras/isLeft_invariant.lean
Sum.liftRel_equiv_left_iff_symm_right
[30, 1]
[33, 71]
exact (e.apply_symm_apply _).symm
case h.e'_7 Ξ± : Type u Ξ² : Type v α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ H : βˆ€ (ab : α₁ βŠ• β₁), LiftRel ra rb (e ab) ab cd : Ξ±β‚‚ βŠ• Ξ²β‚‚ ⊒ cd = e (e.symm cd)
no goals
Please generate a tactic in lean4 to solve the state. STATE: case h.e'_7 Ξ± : Type u Ξ² : Type v α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ H : βˆ€ (ab : α₁ βŠ• β₁), LiftRel ra rb (e ab) ab cd : Ξ±β‚‚ βŠ• Ξ²β‚‚ ⊒ cd = e (e.symm cd) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Extras/isLeft_invariant.lean
Sum.liftRel_equiv_left_iff_symm_right
[30, 1]
[33, 71]
convert (H (e ab))
Ξ± : Type u Ξ² : Type v α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ H : βˆ€ (cd : Ξ±β‚‚ βŠ• Ξ²β‚‚), LiftRel ra rb cd (e.symm cd) ab : α₁ βŠ• β₁ ⊒ LiftRel ra rb (e ab) ab
case h.e'_8 Ξ± : Type u Ξ² : Type v α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ H : βˆ€ (cd : Ξ±β‚‚ βŠ• Ξ²β‚‚), LiftRel ra rb cd (e.symm cd) ab : α₁ βŠ• β₁ ⊒ ab = e.symm (e ab)
Please generate a tactic in lean4 to solve the state. STATE: Ξ± : Type u Ξ² : Type v α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ H : βˆ€ (cd : Ξ±β‚‚ βŠ• Ξ²β‚‚), LiftRel ra rb cd (e.symm cd) ab : α₁ βŠ• β₁ ⊒ LiftRel ra rb (e ab) ab TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Extras/isLeft_invariant.lean
Sum.liftRel_equiv_left_iff_symm_right
[30, 1]
[33, 71]
exact (e.symm_apply_apply _).symm
case h.e'_8 Ξ± : Type u Ξ² : Type v α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ H : βˆ€ (cd : Ξ±β‚‚ βŠ• Ξ²β‚‚), LiftRel ra rb cd (e.symm cd) ab : α₁ βŠ• β₁ ⊒ ab = e.symm (e ab)
no goals
Please generate a tactic in lean4 to solve the state. STATE: case h.e'_8 Ξ± : Type u Ξ² : Type v α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ H : βˆ€ (cd : Ξ±β‚‚ βŠ• Ξ²β‚‚), LiftRel ra rb cd (e.symm cd) ab : α₁ βŠ• β₁ ⊒ ab = e.symm (e ab) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Extras/isLeft_invariant.lean
Sum.liftRel_equiv_right_iff_symm_left
[35, 1]
[37, 70]
convert liftRel_equiv_left_iff_symm_right.symm
Ξ± : Type u Ξ² : Type v α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 ra : α₁ β†’ Ξ±β‚‚ β†’ Prop rb : β₁ β†’ Ξ²β‚‚ β†’ Prop e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ⊒ (βˆ€ (ab : α₁ βŠ• β₁), LiftRel ra rb ab (e ab)) ↔ βˆ€ (cd : Ξ±β‚‚ βŠ• Ξ²β‚‚), LiftRel ra rb (e.symm cd) cd
case h.e'_1.h.h.e'_8.h.e'_5 Ξ± : Type u Ξ² : Type v α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 ra : α₁ β†’ Ξ±β‚‚ β†’ Prop rb : β₁ β†’ Ξ²β‚‚ β†’ Prop e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ a✝ : α₁ βŠ• β₁ ⊒ e = e.symm.symm
Please generate a tactic in lean4 to solve the state. STATE: Ξ± : Type u Ξ² : Type v α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 ra : α₁ β†’ Ξ±β‚‚ β†’ Prop rb : β₁ β†’ Ξ²β‚‚ β†’ Prop e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ⊒ (βˆ€ (ab : α₁ βŠ• β₁), LiftRel ra rb ab (e ab)) ↔ βˆ€ (cd : Ξ±β‚‚ βŠ• Ξ²β‚‚), LiftRel ra rb (e.symm cd) cd TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Extras/isLeft_invariant.lean
Sum.liftRel_equiv_right_iff_symm_left
[35, 1]
[37, 70]
exact e.symm_symm
case h.e'_1.h.h.e'_8.h.e'_5 Ξ± : Type u Ξ² : Type v α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 ra : α₁ β†’ Ξ±β‚‚ β†’ Prop rb : β₁ β†’ Ξ²β‚‚ β†’ Prop e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ a✝ : α₁ βŠ• β₁ ⊒ e = e.symm.symm
no goals
Please generate a tactic in lean4 to solve the state. STATE: case h.e'_1.h.h.e'_8.h.e'_5 Ξ± : Type u Ξ² : Type v α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 ra : α₁ β†’ Ξ±β‚‚ β†’ Prop rb : β₁ β†’ Ξ²β‚‚ β†’ Prop e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ a✝ : α₁ βŠ• β₁ ⊒ e = e.symm.symm TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Extras/isLeft_invariant.lean
equivOfLiftRelToEquivLeft_rel_left
[82, 1]
[85, 21]
simp only [equivOfLiftRelToEquivLeft_apply, ← liftRel_inl_inl (r := ra) (s := rb), inl_getLeft, he]
α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ he : βˆ€ (ab : α₁ βŠ• β₁), LiftRel ra rb (e ab) ab a : α₁ ⊒ ra ((equivOfLiftRelToEquivLeft he) a) a
no goals
Please generate a tactic in lean4 to solve the state. STATE: α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ he : βˆ€ (ab : α₁ βŠ• β₁), LiftRel ra rb (e ab) ab a : α₁ ⊒ ra ((equivOfLiftRelToEquivLeft he) a) a TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Extras/isLeft_invariant.lean
equivOfLiftRelToEquivRight_rel_right
[87, 1]
[90, 22]
simp only [equivOfLiftRelToEquivRight_apply, ← liftRel_inr_inr (r := ra) (s := rb), inr_getRight, he]
α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ he : βˆ€ (ab : α₁ βŠ• β₁), LiftRel ra rb (e ab) ab b : β₁ ⊒ rb ((equivOfLiftRelToEquivRight he) b) b
no goals
Please generate a tactic in lean4 to solve the state. STATE: α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ he : βˆ€ (ab : α₁ βŠ• β₁), LiftRel ra rb (e ab) ab b : β₁ ⊒ rb ((equivOfLiftRelToEquivRight he) b) b TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Extras/isLeft_invariant.lean
liftRelSumCongr_of_rel_left_rel_right
[92, 1]
[94, 31]
cases ab <;> simp [hea, heb]
α₁ : Type u_2 β₁ : Type u_4 Ξ±β‚‚ : Type u_1 Ξ²β‚‚ : Type u_3 e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ hea : βˆ€ (a : α₁), ra (ea a) a heb : βˆ€ (b : β₁), rb (eb b) b ab : α₁ βŠ• β₁ ⊒ LiftRel ra rb ((ea.sumCongr eb) ab) ab
no goals
Please generate a tactic in lean4 to solve the state. STATE: α₁ : Type u_2 β₁ : Type u_4 Ξ±β‚‚ : Type u_1 Ξ²β‚‚ : Type u_3 e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ hea : βˆ€ (a : α₁), ra (ea a) a heb : βˆ€ (b : β₁), rb (eb b) b ab : α₁ βŠ• β₁ ⊒ LiftRel ra rb ((ea.sumCongr eb) ab) ab TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Extras/isLeft_invariant.lean
sumCongrEquivLiftRelLeftRight_eq_self
[96, 1]
[98, 34]
ext ab
α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ he : βˆ€ (ab : α₁ βŠ• β₁), LiftRel ra rb (e ab) ab ⊒ (equivOfLiftRelToEquivLeft he).sumCongr (equivOfLiftRelToEquivRight he) = e
case H α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ he : βˆ€ (ab : α₁ βŠ• β₁), LiftRel ra rb (e ab) ab ab : α₁ βŠ• β₁ ⊒ ((equivOfLiftRelToEquivLeft he).sumCongr (equivOfLiftRelToEquivRight he)) ab = e ab
Please generate a tactic in lean4 to solve the state. STATE: α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ he : βˆ€ (ab : α₁ βŠ• β₁), LiftRel ra rb (e ab) ab ⊒ (equivOfLiftRelToEquivLeft he).sumCongr (equivOfLiftRelToEquivRight he) = e TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Extras/isLeft_invariant.lean
sumCongrEquivLiftRelLeftRight_eq_self
[96, 1]
[98, 34]
cases ab <;> simp [he]
case H α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ he : βˆ€ (ab : α₁ βŠ• β₁), LiftRel ra rb (e ab) ab ab : α₁ βŠ• β₁ ⊒ ((equivOfLiftRelToEquivLeft he).sumCongr (equivOfLiftRelToEquivRight he)) ab = e ab
no goals
Please generate a tactic in lean4 to solve the state. STATE: case H α₁ : Type u_1 β₁ : Type u_2 Ξ±β‚‚ : Type u_3 Ξ²β‚‚ : Type u_4 e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ he : βˆ€ (ab : α₁ βŠ• β₁), LiftRel ra rb (e ab) ab ab : α₁ βŠ• β₁ ⊒ ((equivOfLiftRelToEquivLeft he).sumCongr (equivOfLiftRelToEquivRight he)) ab = e ab TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Extras/isLeft_invariant.lean
equivIsLeftInvariant_iff_liftRel_top_top
[116, 1]
[122, 83]
simp_rw [Sum.forall, isLeft_inl, isLeft_inr, isLeft_eq_false, isLeft_iff, isRight_iff]
α₁ : Type u_2 β₁ : Type u_1 Ξ±β‚‚ : Type u_4 Ξ²β‚‚ : Type u_3 e✝ : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ⊒ (βˆ€ (ab : α₁ βŠ• β₁), (e ab).isLeft = ab.isLeft) ↔ βˆ€ (ab : α₁ βŠ• β₁), LiftRel ⊀ ⊀ (e ab) ab
α₁ : Type u_2 β₁ : Type u_1 Ξ±β‚‚ : Type u_4 Ξ²β‚‚ : Type u_3 e✝ : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ⊒ ((βˆ€ (a : α₁), βˆƒ y, e (inl a) = inl y) ∧ βˆ€ (b : β₁), βˆƒ y, e (inr b) = inr y) ↔ (βˆ€ (a : α₁), LiftRel ⊀ ⊀ (e (inl a)) (inl a)) ∧ βˆ€ (b : β₁), LiftRel ⊀ ⊀ (e (inr b)) (inr b)
Please generate a tactic in lean4 to solve the state. STATE: α₁ : Type u_2 β₁ : Type u_1 Ξ±β‚‚ : Type u_4 Ξ²β‚‚ : Type u_3 e✝ : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ⊒ (βˆ€ (ab : α₁ βŠ• β₁), (e ab).isLeft = ab.isLeft) ↔ βˆ€ (ab : α₁ βŠ• β₁), LiftRel ⊀ ⊀ (e ab) ab TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Extras/isLeft_invariant.lean
equivIsLeftInvariant_iff_liftRel_top_top
[116, 1]
[122, 83]
exact ⟨fun ⟨hA, hB⟩ => ⟨fun a => (hA a).elim (fun _ h => h β–Έ LiftRel.inl (trivial)), fun b => (hB b).elim (fun _ h => h β–Έ LiftRel.inr (trivial))⟩, fun ⟨hA, hB⟩ => ⟨fun a => isLeft_iff.mp (isLeft_eq_of_liftRel (hA a)), fun b => isRight_iff.mp (isRight_eq_of_liftRel (hB b))⟩⟩
α₁ : Type u_2 β₁ : Type u_1 Ξ±β‚‚ : Type u_4 Ξ²β‚‚ : Type u_3 e✝ : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ⊒ ((βˆ€ (a : α₁), βˆƒ y, e (inl a) = inl y) ∧ βˆ€ (b : β₁), βˆƒ y, e (inr b) = inr y) ↔ (βˆ€ (a : α₁), LiftRel ⊀ ⊀ (e (inl a)) (inl a)) ∧ βˆ€ (b : β₁), LiftRel ⊀ ⊀ (e (inr b)) (inr b)
no goals
Please generate a tactic in lean4 to solve the state. STATE: α₁ : Type u_2 β₁ : Type u_1 Ξ±β‚‚ : Type u_4 Ξ²β‚‚ : Type u_3 e✝ : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ⊒ ((βˆ€ (a : α₁), βˆƒ y, e (inl a) = inl y) ∧ βˆ€ (b : β₁), βˆƒ y, e (inr b) = inr y) ↔ (βˆ€ (a : α₁), LiftRel ⊀ ⊀ (e (inl a)) (inl a)) ∧ βˆ€ (b : β₁), LiftRel ⊀ ⊀ (e (inr b)) (inr b) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Extras/isLeft_invariant.lean
equivIsRightInvariant_iff_liftRel_top_top
[124, 1]
[129, 97]
rw [← equivIsLeftInvariant_iff_liftRel_top_top]
α₁ : Type u_2 β₁ : Type u_1 Ξ±β‚‚ : Type u_4 Ξ²β‚‚ : Type u_3 e✝ : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ⊒ (βˆ€ (ab : α₁ βŠ• β₁), (e ab).isRight = ab.isRight) ↔ βˆ€ (ab : α₁ βŠ• β₁), LiftRel ⊀ ⊀ (e ab) ab
α₁ : Type u_2 β₁ : Type u_1 Ξ±β‚‚ : Type u_4 Ξ²β‚‚ : Type u_3 e✝ : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ⊒ (βˆ€ (ab : α₁ βŠ• β₁), (e ab).isRight = ab.isRight) ↔ βˆ€ (ab : α₁ βŠ• β₁), (e ab).isLeft = ab.isLeft
Please generate a tactic in lean4 to solve the state. STATE: α₁ : Type u_2 β₁ : Type u_1 Ξ±β‚‚ : Type u_4 Ξ²β‚‚ : Type u_3 e✝ : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ⊒ (βˆ€ (ab : α₁ βŠ• β₁), (e ab).isRight = ab.isRight) ↔ βˆ€ (ab : α₁ βŠ• β₁), LiftRel ⊀ ⊀ (e ab) ab TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Extras/isLeft_invariant.lean
equivIsRightInvariant_iff_liftRel_top_top
[124, 1]
[129, 97]
simp_rw [Sum.forall]
α₁ : Type u_2 β₁ : Type u_1 Ξ±β‚‚ : Type u_4 Ξ²β‚‚ : Type u_3 e✝ : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ⊒ (βˆ€ (ab : α₁ βŠ• β₁), (e ab).isRight = ab.isRight) ↔ βˆ€ (ab : α₁ βŠ• β₁), (e ab).isLeft = ab.isLeft
α₁ : Type u_2 β₁ : Type u_1 Ξ±β‚‚ : Type u_4 Ξ²β‚‚ : Type u_3 e✝ : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ⊒ ((βˆ€ (a : α₁), (e (inl a)).isRight = (inl a).isRight) ∧ βˆ€ (b : β₁), (e (inr b)).isRight = (inr b).isRight) ↔ (βˆ€ (a : α₁), (e (inl a)).isLeft = (inl a).isLeft) ∧ βˆ€ (b : β₁), (e (inr b)).isLeft = (inr b).isLeft
Please generate a tactic in lean4 to solve the state. STATE: α₁ : Type u_2 β₁ : Type u_1 Ξ±β‚‚ : Type u_4 Ξ²β‚‚ : Type u_3 e✝ : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ⊒ (βˆ€ (ab : α₁ βŠ• β₁), (e ab).isRight = ab.isRight) ↔ βˆ€ (ab : α₁ βŠ• β₁), (e ab).isLeft = ab.isLeft TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Extras/isLeft_invariant.lean
equivIsRightInvariant_iff_liftRel_top_top
[124, 1]
[129, 97]
simp_rw [isRight_inl, isRight_eq_false, isRight_inr, isLeft_inl, isLeft_inr, isLeft_eq_false]
α₁ : Type u_2 β₁ : Type u_1 Ξ±β‚‚ : Type u_4 Ξ²β‚‚ : Type u_3 e✝ : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ⊒ ((βˆ€ (a : α₁), (e (inl a)).isRight = (inl a).isRight) ∧ βˆ€ (b : β₁), (e (inr b)).isRight = (inr b).isRight) ↔ (βˆ€ (a : α₁), (e (inl a)).isLeft = (inl a).isLeft) ∧ βˆ€ (b : β₁), (e (inr b)).isLeft = (inr b).isLeft
no goals
Please generate a tactic in lean4 to solve the state. STATE: α₁ : Type u_2 β₁ : Type u_1 Ξ±β‚‚ : Type u_4 Ξ²β‚‚ : Type u_3 e✝ : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ra : Ξ±β‚‚ β†’ α₁ β†’ Prop rb : Ξ²β‚‚ β†’ β₁ β†’ Prop ea : α₁ ≃ Ξ±β‚‚ eb : β₁ ≃ Ξ²β‚‚ e : α₁ βŠ• β₁ ≃ Ξ±β‚‚ βŠ• Ξ²β‚‚ ⊒ ((βˆ€ (a : α₁), (e (inl a)).isRight = (inl a).isRight) ∧ βˆ€ (b : β₁), (e (inr b)).isRight = (inr b).isRight) ↔ (βˆ€ (a : α₁), (e (inl a)).isLeft = (inl a).isLeft) ∧ βˆ€ (b : β₁), (e (inr b)).isLeft = (inr b).isLeft TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/FoldFin.lean
coe_foldFinLE
[22, 1]
[23, 68]
simp_rw [foldFin, Nat.lt_succ_of_le h, dite_true, Fin.coe_castLT]
m : β„• i : Fin (2 * m + 1) h : ↑i ≀ m ⊒ ↑(foldFin m i) = ↑i
no goals
Please generate a tactic in lean4 to solve the state. STATE: m : β„• i : Fin (2 * m + 1) h : ↑i ≀ m ⊒ ↑(foldFin m i) = ↑i TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/FoldFin.lean
foldFinCastLE
[31, 1]
[32, 77]
rw [Fin.ext_iff, coe_foldFinLE (Nat.le_of_lt_succ i.isLt), Fin.coe_castLE]
m : β„• i : Fin (m + 1) ⊒ foldFin m (Fin.castLE β‹― i) = i
no goals
Please generate a tactic in lean4 to solve the state. STATE: m : β„• i : Fin (m + 1) ⊒ foldFin m (Fin.castLE β‹― i) = i TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/FoldFin.lean
foldFinCastLT
[36, 1]
[37, 75]
rw [Fin.ext_iff, coe_foldFinLT i.isLt, Fin.coe_castLT, Fin.coe_castSucc]
m : β„• i : Fin m ⊒ foldFin m (i.castLT β‹―) = i.castSucc
no goals
Please generate a tactic in lean4 to solve the state. STATE: m : β„• i : Fin m ⊒ foldFin m (i.castLT β‹―) = i.castSucc TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/FoldFin.lean
foldFin_last
[41, 1]
[54, 9]
cases' m with m
m : β„• ⊒ foldFin m (Fin.last (2 * m)) = 0
case zero ⊒ foldFin 0 (Fin.last (2 * 0)) = 0 case succ m : β„• ⊒ foldFin (m + 1) (Fin.last (2 * (m + 1))) = 0
Please generate a tactic in lean4 to solve the state. STATE: m : β„• ⊒ foldFin m (Fin.last (2 * m)) = 0 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/FoldFin.lean
foldFin_last
[41, 1]
[54, 9]
rfl
case zero ⊒ foldFin 0 (Fin.last (2 * 0)) = 0
no goals
Please generate a tactic in lean4 to solve the state. STATE: case zero ⊒ foldFin 0 (Fin.last (2 * 0)) = 0 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/FoldFin.lean
foldFin_last
[41, 1]
[54, 9]
rw [foldFin]
case succ m : β„• ⊒ foldFin (m + 1) (Fin.last (2 * (m + 1))) = 0
case succ m : β„• ⊒ (if h : ↑(Fin.last (2 * (m + 1))) < m + 1 + 1 then (Fin.last (2 * (m + 1))).castLT h else (Fin.subNat (m + 1) ((finCongr β‹―) (Fin.last (2 * (m + 1)))) β‹―).rev) = 0
Please generate a tactic in lean4 to solve the state. STATE: case succ m : β„• ⊒ foldFin (m + 1) (Fin.last (2 * (m + 1))) = 0 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/FoldFin.lean
foldFin_last
[41, 1]
[54, 9]
rw [dif_neg]
case succ m : β„• ⊒ (if h : ↑(Fin.last (2 * (m + 1))) < m + 1 + 1 then (Fin.last (2 * (m + 1))).castLT h else (Fin.subNat (m + 1) ((finCongr β‹―) (Fin.last (2 * (m + 1)))) β‹―).rev) = 0
case succ m : β„• ⊒ (Fin.subNat (m + 1) ((finCongr β‹―) (Fin.last (2 * (m + 1)))) β‹―).rev = 0 case succ.hnc m : β„• ⊒ ¬↑(Fin.last (2 * (m + 1))) < m + 1 + 1
Please generate a tactic in lean4 to solve the state. STATE: case succ m : β„• ⊒ (if h : ↑(Fin.last (2 * (m + 1))) < m + 1 + 1 then (Fin.last (2 * (m + 1))).castLT h else (Fin.subNat (m + 1) ((finCongr β‹―) (Fin.last (2 * (m + 1)))) β‹―).rev) = 0 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/FoldFin.lean
foldFin_last
[41, 1]
[54, 9]
ext
case succ m : β„• ⊒ (Fin.subNat (m + 1) ((finCongr β‹―) (Fin.last (2 * (m + 1)))) β‹―).rev = 0 case succ.hnc m : β„• ⊒ ¬↑(Fin.last (2 * (m + 1))) < m + 1 + 1
case succ.h m : β„• ⊒ ↑(Fin.subNat (m + 1) ((finCongr β‹―) (Fin.last (2 * (m + 1)))) β‹―).rev = ↑0 case succ.hnc m : β„• ⊒ ¬↑(Fin.last (2 * (m + 1))) < m + 1 + 1
Please generate a tactic in lean4 to solve the state. STATE: case succ m : β„• ⊒ (Fin.subNat (m + 1) ((finCongr β‹―) (Fin.last (2 * (m + 1)))) β‹―).rev = 0 case succ.hnc m : β„• ⊒ ¬↑(Fin.last (2 * (m + 1))) < m + 1 + 1 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/FoldFin.lean
foldFin_last
[41, 1]
[54, 9]
simp
case succ.h m : β„• ⊒ ↑(Fin.subNat (m + 1) ((finCongr β‹―) (Fin.last (2 * (m + 1)))) β‹―).rev = ↑0 case succ.hnc m : β„• ⊒ ¬↑(Fin.last (2 * (m + 1))) < m + 1 + 1
case succ.h m : β„• ⊒ m + 1 - (m + 1 + 1 + m - (m + 1)) = 0 case succ.hnc m : β„• ⊒ ¬↑(Fin.last (2 * (m + 1))) < m + 1 + 1
Please generate a tactic in lean4 to solve the state. STATE: case succ.h m : β„• ⊒ ↑(Fin.subNat (m + 1) ((finCongr β‹―) (Fin.last (2 * (m + 1)))) β‹―).rev = ↑0 case succ.hnc m : β„• ⊒ ¬↑(Fin.last (2 * (m + 1))) < m + 1 + 1 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Order.lean
Order.eq_false_true_of_cond_succ_lt_of_cond_succ_lt
[11, 1]
[22, 25]
cases bm <;> cases bn <;> simp only [false_and, and_false, true_and, and_self, cond_true, cond_false, id_eq, succ_le_iff, succ_lt_succ_iff, lt_succ_iff] at *
α : Type u_1 inst✝² : PartialOrder α inst✝¹ : SuccOrder α inst✝ : NoMaxOrder α m n : α bm bn : Bool hmn : (bif bm then succ else id) m < (bif bn then succ else id) n hnm : (bif bn then id else succ) n < (bif bm then id else succ) m ⊒ bm = false ∧ bn = true ∧ m = n
case false.false Ξ± : Type u_1 inst✝² : PartialOrder Ξ± inst✝¹ : SuccOrder Ξ± inst✝ : NoMaxOrder Ξ± m n : Ξ± hmn : m < n hnm : n < m ⊒ False case false.true Ξ± : Type u_1 inst✝² : PartialOrder Ξ± inst✝¹ : SuccOrder Ξ± inst✝ : NoMaxOrder Ξ± m n : Ξ± hmn : m ≀ n hnm : n ≀ m ⊒ m = n case true.false Ξ± : Type u_1 inst✝² : PartialOrder Ξ± inst✝¹ : SuccOrder Ξ± inst✝ : NoMaxOrder Ξ± m n : Ξ± hmn : succ m < n hnm : succ n < m ⊒ False case true.true Ξ± : Type u_1 inst✝² : PartialOrder Ξ± inst✝¹ : SuccOrder Ξ± inst✝ : NoMaxOrder Ξ± m n : Ξ± hnm : n < m hmn : m < n ⊒ False
Please generate a tactic in lean4 to solve the state. STATE: α : Type u_1 inst✝² : PartialOrder α inst✝¹ : SuccOrder α inst✝ : NoMaxOrder α m n : α bm bn : Bool hmn : (bif bm then succ else id) m < (bif bn then succ else id) n hnm : (bif bn then id else succ) n < (bif bm then id else succ) m ⊒ bm = false ∧ bn = true ∧ m = n TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Order.lean
Order.eq_false_true_of_cond_succ_lt_of_cond_succ_lt
[11, 1]
[22, 25]
exact hmn.not_lt hnm
case false.false α : Type u_1 inst✝² : PartialOrder α inst✝¹ : SuccOrder α inst✝ : NoMaxOrder α m n : α hmn : m < n hnm : n < m ⊒ False
no goals
Please generate a tactic in lean4 to solve the state. STATE: case false.false α : Type u_1 inst✝² : PartialOrder α inst✝¹ : SuccOrder α inst✝ : NoMaxOrder α m n : α hmn : m < n hnm : n < m ⊒ False TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Order.lean
Order.eq_false_true_of_cond_succ_lt_of_cond_succ_lt
[11, 1]
[22, 25]
exact le_antisymm hmn hnm
case false.true Ξ± : Type u_1 inst✝² : PartialOrder Ξ± inst✝¹ : SuccOrder Ξ± inst✝ : NoMaxOrder Ξ± m n : Ξ± hmn : m ≀ n hnm : n ≀ m ⊒ m = n
no goals
Please generate a tactic in lean4 to solve the state. STATE: case false.true Ξ± : Type u_1 inst✝² : PartialOrder Ξ± inst✝¹ : SuccOrder Ξ± inst✝ : NoMaxOrder Ξ± m n : Ξ± hmn : m ≀ n hnm : n ≀ m ⊒ m = n TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Order.lean
Order.eq_false_true_of_cond_succ_lt_of_cond_succ_lt
[11, 1]
[22, 25]
exact lt_irrefl _ (((hnm.trans (lt_succ _)).trans hmn).trans (lt_succ _))
case true.false α : Type u_1 inst✝² : PartialOrder α inst✝¹ : SuccOrder α inst✝ : NoMaxOrder α m n : α hmn : succ m < n hnm : succ n < m ⊒ False
no goals
Please generate a tactic in lean4 to solve the state. STATE: case true.false α : Type u_1 inst✝² : PartialOrder α inst✝¹ : SuccOrder α inst✝ : NoMaxOrder α m n : α hmn : succ m < n hnm : succ n < m ⊒ False TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Order.lean
Order.eq_false_true_of_cond_succ_lt_of_cond_succ_lt
[11, 1]
[22, 25]
exact hmn.not_lt hnm
case true.true α : Type u_1 inst✝² : PartialOrder α inst✝¹ : SuccOrder α inst✝ : NoMaxOrder α m n : α hnm : n < m hmn : m < n ⊒ False
no goals
Please generate a tactic in lean4 to solve the state. STATE: case true.true α : Type u_1 inst✝² : PartialOrder α inst✝¹ : SuccOrder α inst✝ : NoMaxOrder α m n : α hnm : n < m hmn : m < n ⊒ False TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Nat.lean
Nat.eq_false_true_of_cond_succ_lt_of_cond_succ_lt
[12, 1]
[20, 86]
refine Order.eq_false_true_of_cond_succ_lt_of_cond_succ_lt ?_ ?_
m : β„• bm : Bool n : β„• bn : Bool hmn : (m + bif bm then 1 else 0) < n + bif bn then 1 else 0 hnm : (n + bif bn then 0 else 1) < m + bif bm then 0 else 1 ⊒ bm = false ∧ bn = true ∧ m = n
case refine_1 m : β„• bm : Bool n : β„• bn : Bool hmn : (m + bif bm then 1 else 0) < n + bif bn then 1 else 0 hnm : (n + bif bn then 0 else 1) < m + bif bm then 0 else 1 ⊒ (bif bm then Order.succ else id) m < (bif bn then Order.succ else id) n case refine_2 m : β„• bm : Bool n : β„• bn : Bool hmn : (m + bif bm then 1 else 0) < n + bif bn then 1 else 0 hnm : (n + bif bn then 0 else 1) < m + bif bm then 0 else 1 ⊒ (bif bn then id else Order.succ) n < (bif bm then id else Order.succ) m
Please generate a tactic in lean4 to solve the state. STATE: m : β„• bm : Bool n : β„• bn : Bool hmn : (m + bif bm then 1 else 0) < n + bif bn then 1 else 0 hnm : (n + bif bn then 0 else 1) < m + bif bm then 0 else 1 ⊒ bm = false ∧ bn = true ∧ m = n TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Nat.lean
Nat.eq_false_true_of_cond_succ_lt_of_cond_succ_lt
[12, 1]
[20, 86]
cases bm <;> cases bn <;> simp only [succ_eq_succ, cond_true, cond_false, id_eq] at hnm hmn ⊒ <;> exact hmn
case refine_1 m : β„• bm : Bool n : β„• bn : Bool hmn : (m + bif bm then 1 else 0) < n + bif bn then 1 else 0 hnm : (n + bif bn then 0 else 1) < m + bif bm then 0 else 1 ⊒ (bif bm then Order.succ else id) m < (bif bn then Order.succ else id) n
no goals
Please generate a tactic in lean4 to solve the state. STATE: case refine_1 m : β„• bm : Bool n : β„• bn : Bool hmn : (m + bif bm then 1 else 0) < n + bif bn then 1 else 0 hnm : (n + bif bn then 0 else 1) < m + bif bm then 0 else 1 ⊒ (bif bm then Order.succ else id) m < (bif bn then Order.succ else id) n TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Nat.lean
Nat.eq_false_true_of_cond_succ_lt_of_cond_succ_lt
[12, 1]
[20, 86]
cases bm <;> cases bn <;> simp only [succ_eq_succ, cond_true, cond_false, id_eq] at hnm hmn ⊒ <;> exact hnm
case refine_2 m : β„• bm : Bool n : β„• bn : Bool hmn : (m + bif bm then 1 else 0) < n + bif bn then 1 else 0 hnm : (n + bif bn then 0 else 1) < m + bif bm then 0 else 1 ⊒ (bif bn then id else Order.succ) n < (bif bm then id else Order.succ) m
no goals
Please generate a tactic in lean4 to solve the state. STATE: case refine_2 m : β„• bm : Bool n : β„• bn : Bool hmn : (m + bif bm then 1 else 0) < n + bif bn then 1 else 0 hnm : (n + bif bn then 0 else 1) < m + bif bm then 0 else 1 ⊒ (bif bn then id else Order.succ) n < (bif bm then id else Order.succ) m TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/Bool.lean
Bool.apply_cond
[3, 1]
[4, 62]
cases b <;> rfl
Ξ± : Type u_1 Ξ² : Type u_2 f : Ξ± β†’ Ξ² b : Bool x y : Ξ± ⊒ f (bif b then x else y) = bif b then f x else f y
no goals
Please generate a tactic in lean4 to solve the state. STATE: Ξ± : Type u_1 Ξ² : Type u_2 f : Ξ± β†’ Ξ² b : Bool x y : Ξ± ⊒ f (bif b then x else y) = bif b then f x else f y TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitRes_apply_zero
[44, 1]
[47, 99]
ext <;> simp only [getBitRes_apply, finFunctionFinEquiv, Equiv.ofRightInverseOfCardLE_symm_apply, Fin.val_zero', Nat.zero_div, Nat.zero_mod, Fin.zero_eta, finTwoEquiv_apply, zero_ne_one, decide_False, Equiv.ofRightInverseOfCardLE_apply, Fin.val_zero, zero_mul, Finset.sum_const_zero]
a✝ : β„• i : Fin (a✝ + 1) ⊒ (getBitRes i) 0 = (false, 0)
no goals
Please generate a tactic in lean4 to solve the state. STATE: a✝ : β„• i : Fin (a✝ + 1) ⊒ (getBitRes i) 0 = (false, 0) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBit_apply_zero
[49, 1]
[50, 40]
rw [getBit_apply, getBitRes_apply_zero]
a✝ : β„• i : Fin (a✝ + 1) ⊒ getBit i 0 = false
no goals
Please generate a tactic in lean4 to solve the state. STATE: a✝ : β„• i : Fin (a✝ + 1) ⊒ getBit i 0 = false TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getRes_apply_zero
[52, 1]
[53, 40]
rw [getRes_apply, getBitRes_apply_zero]
a✝ : β„• i : Fin (a✝ + 1) ⊒ getRes i 0 = 0
no goals
Please generate a tactic in lean4 to solve the state. STATE: a✝ : β„• i : Fin (a✝ + 1) ⊒ getRes i 0 = 0 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_apply_false_zero
[55, 1]
[56, 80]
rw [mergeBitRes_apply, ← getBitRes_apply_zero (i := i), Equiv.symm_apply_apply]
a✝ : β„• i : Fin (a✝ + 1) ⊒ mergeBitRes i false 0 = 0
no goals
Please generate a tactic in lean4 to solve the state. STATE: a✝ : β„• i : Fin (a✝ + 1) ⊒ mergeBitRes i false 0 = 0 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitRes_apply_two_pow
[58, 1]
[70, 74]
ext
m : β„• i : Fin (m + 1) ⊒ (getBitRes i) ⟨2 ^ ↑i, β‹―βŸ© = (true, 0)
case a m : β„• i : Fin (m + 1) ⊒ ((getBitRes i) ⟨2 ^ ↑i, β‹―βŸ©).1 = (true, 0).1 case a.h m : β„• i : Fin (m + 1) ⊒ ↑((getBitRes i) ⟨2 ^ ↑i, β‹―βŸ©).2 = ↑(true, 0).2
Please generate a tactic in lean4 to solve the state. STATE: m : β„• i : Fin (m + 1) ⊒ (getBitRes i) ⟨2 ^ ↑i, β‹―βŸ© = (true, 0) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitRes_apply_two_pow
[58, 1]
[70, 74]
simp only [getBitRes_apply, finFunctionFinEquiv, Equiv.ofRightInverseOfCardLE_symm_apply, gt_iff_lt, zero_lt_two, pow_pos, Nat.div_self, Nat.one_mod, Fin.mk_one, finTwoEquiv_apply, decide_True, Equiv.ofRightInverseOfCardLE_apply]
case a m : β„• i : Fin (m + 1) ⊒ ((getBitRes i) ⟨2 ^ ↑i, β‹―βŸ©).1 = (true, 0).1
no goals
Please generate a tactic in lean4 to solve the state. STATE: case a m : β„• i : Fin (m + 1) ⊒ ((getBitRes i) ⟨2 ^ ↑i, β‹―βŸ©).1 = (true, 0).1 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitRes_apply_two_pow
[58, 1]
[70, 74]
simp only [getBitRes_apply, finFunctionFinEquiv_apply_val, finFunctionFinEquiv_symm_apply_val, Fin.val_zero', Finset.sum_eq_zero_iff, Finset.mem_univ, mul_eq_zero, forall_true_left]
case a.h m : β„• i : Fin (m + 1) ⊒ ↑((getBitRes i) ⟨2 ^ ↑i, β‹―βŸ©).2 = ↑(true, 0).2
case a.h m : β„• i : Fin (m + 1) ⊒ βˆ€ (x : Fin m), 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0 ∨ 2 ^ ↑x = 0
Please generate a tactic in lean4 to solve the state. STATE: case a.h m : β„• i : Fin (m + 1) ⊒ ↑((getBitRes i) ⟨2 ^ ↑i, β‹―βŸ©).2 = ↑(true, 0).2 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitRes_apply_two_pow
[58, 1]
[70, 74]
refine' fun x => Or.inl _
case a.h m : β„• i : Fin (m + 1) ⊒ βˆ€ (x : Fin m), 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0 ∨ 2 ^ ↑x = 0
case a.h m : β„• i : Fin (m + 1) x : Fin m ⊒ 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0
Please generate a tactic in lean4 to solve the state. STATE: case a.h m : β„• i : Fin (m + 1) ⊒ βˆ€ (x : Fin m), 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0 ∨ 2 ^ ↑x = 0 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitRes_apply_two_pow
[58, 1]
[70, 74]
rcases (Fin.succAbove_ne i x).lt_or_lt with h | h <;> rw [Fin.lt_iff_val_lt_val] at h
case a.h m : β„• i : Fin (m + 1) x : Fin m ⊒ 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0
case a.h.inl m : β„• i : Fin (m + 1) x : Fin m h : ↑(i.succAbove x) < ↑i ⊒ 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0 case a.h.inr m : β„• i : Fin (m + 1) x : Fin m h : ↑i < ↑(i.succAbove x) ⊒ 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0
Please generate a tactic in lean4 to solve the state. STATE: case a.h m : β„• i : Fin (m + 1) x : Fin m ⊒ 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitRes_apply_two_pow
[58, 1]
[70, 74]
rw [Nat.pow_div h.le zero_lt_two, Nat.pow_mod, Nat.mod_self, Nat.zero_pow (Nat.sub_pos_of_lt h), Nat.zero_mod]
case a.h.inl m : β„• i : Fin (m + 1) x : Fin m h : ↑(i.succAbove x) < ↑i ⊒ 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0
no goals
Please generate a tactic in lean4 to solve the state. STATE: case a.h.inl m : β„• i : Fin (m + 1) x : Fin m h : ↑(i.succAbove x) < ↑i ⊒ 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitRes_apply_two_pow
[58, 1]
[70, 74]
rw [Nat.div_eq_of_lt (pow_lt_pow_right one_lt_two h), Nat.zero_mod]
case a.h.inr m : β„• i : Fin (m + 1) x : Fin m h : ↑i < ↑(i.succAbove x) ⊒ 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0
no goals
Please generate a tactic in lean4 to solve the state. STATE: case a.h.inr m : β„• i : Fin (m + 1) x : Fin m h : ↑i < ↑(i.succAbove x) ⊒ 2 ^ ↑i / 2 ^ ↑(i.succAbove x) % 2 = 0 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBit_apply_two_pow
[72, 1]
[74, 45]
rw [getBit_apply, getBitRes_apply_two_pow]
m : β„• i : Fin (m + 1) ⊒ getBit i ⟨2 ^ ↑i, β‹―βŸ© = true
no goals
Please generate a tactic in lean4 to solve the state. STATE: m : β„• i : Fin (m + 1) ⊒ getBit i ⟨2 ^ ↑i, β‹―βŸ© = true TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBit_apply_zero_one
[76, 1]
[78, 85]
convert getBit_apply_two_pow
m : β„• ⊒ getBit 0 1 = true
case h.e'_2.h.e'_3.h.h.e'_2 m : β„• ⊒ ↑1 = 2 ^ ↑0
Please generate a tactic in lean4 to solve the state. STATE: m : β„• ⊒ getBit 0 1 = true TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBit_apply_zero_one
[76, 1]
[78, 85]
rw [Fin.val_one', Nat.mod_eq_of_lt (Nat.one_lt_pow' _ _ ), Fin.val_zero, pow_zero]
case h.e'_2.h.e'_3.h.h.e'_2 m : β„• ⊒ ↑1 = 2 ^ ↑0
no goals
Please generate a tactic in lean4 to solve the state. STATE: case h.e'_2.h.e'_3.h.h.e'_2 m : β„• ⊒ ↑1 = 2 ^ ↑0 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getRes_apply_two_pow
[80, 1]
[82, 45]
rw [getRes_apply, getBitRes_apply_two_pow]
m : β„• i : Fin (m + 1) ⊒ getRes i ⟨2 ^ ↑i, β‹―βŸ© = 0
no goals
Please generate a tactic in lean4 to solve the state. STATE: m : β„• i : Fin (m + 1) ⊒ getRes i ⟨2 ^ ↑i, β‹―βŸ© = 0 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_apply_true_zero
[84, 1]
[86, 85]
rw [mergeBitRes_apply, ← getBitRes_apply_two_pow (i := i), Equiv.symm_apply_apply]
m : β„• i : Fin (m + 1) ⊒ mergeBitRes i true 0 = ⟨2 ^ ↑i, β‹―βŸ©
no goals
Please generate a tactic in lean4 to solve the state. STATE: m : β„• i : Fin (m + 1) ⊒ mergeBitRes i true 0 = ⟨2 ^ ↑i, β‹―βŸ© TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_apply'
[88, 1]
[97, 12]
unfold mergeBitRes getBitRes
m : β„• i : Fin (m + 1) b : Bool p : BV m ⊒ mergeBitRes i b p = βˆ‘ i' : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE β‹― p / 2 ^ ↑b % 2) i' * 2 ^ ↑i'
m : β„• i : Fin (m + 1) b : Bool p : BV m ⊒ Function.curry (⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i)) (finTwoEquiv.prodCongr finFunctionFinEquiv)).symm) b p = βˆ‘ i' : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE β‹― p / 2 ^ ↑b % 2) i' * 2 ^ ↑i'
Please generate a tactic in lean4 to solve the state. STATE: m : β„• i : Fin (m + 1) b : Bool p : BV m ⊒ mergeBitRes i b p = βˆ‘ i' : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE β‹― p / 2 ^ ↑b % 2) i' * 2 ^ ↑i' TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_apply'
[88, 1]
[97, 12]
simp [finFunctionFinEquiv]
m : β„• i : Fin (m + 1) b : Bool p : BV m ⊒ Function.curry (⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i)) (finTwoEquiv.prodCongr finFunctionFinEquiv)).symm) b p = βˆ‘ i' : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE β‹― p / 2 ^ ↑b % 2) i' * 2 ^ ↑i'
m : β„• i : Fin (m + 1) b : Bool p : BV m ⊒ βŸ¨βˆ‘ i_1 : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) i_1) * 2 ^ ↑i_1, β‹―βŸ© = βˆ‘ i' : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE β‹― p / 2 ^ ↑b % 2) i' * 2 ^ ↑i'
Please generate a tactic in lean4 to solve the state. STATE: m : β„• i : Fin (m + 1) b : Bool p : BV m ⊒ Function.curry (⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i)) (finTwoEquiv.prodCongr finFunctionFinEquiv)).symm) b p = βˆ‘ i' : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE β‹― p / 2 ^ ↑b % 2) i' * 2 ^ ↑i' TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_apply'
[88, 1]
[97, 12]
norm_cast
m : β„• i : Fin (m + 1) b : Bool p : BV m ⊒ βŸ¨βˆ‘ i_1 : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) i_1) * 2 ^ ↑i_1, β‹―βŸ© = βˆ‘ i' : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE β‹― p / 2 ^ ↑b % 2) i' * 2 ^ ↑i'
m : β„• i : Fin (m + 1) b : Bool p : BV m ⊒ βŸ¨βˆ‘ x : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x, β‹―βŸ© = βˆ‘ x : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE β‹― p / ↑(2 ^ ↑b) % 2) x * ↑(2 ^ ↑x)
Please generate a tactic in lean4 to solve the state. STATE: m : β„• i : Fin (m + 1) b : Bool p : BV m ⊒ βŸ¨βˆ‘ i_1 : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) i_1) * 2 ^ ↑i_1, β‹―βŸ© = βˆ‘ i' : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE β‹― p / 2 ^ ↑b % 2) i' * 2 ^ ↑i' TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_apply'
[88, 1]
[97, 12]
ext
m : β„• i : Fin (m + 1) b : Bool p : BV m ⊒ βŸ¨βˆ‘ x : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x, β‹―βŸ© = βˆ‘ x : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE β‹― p / ↑(2 ^ ↑b) % 2) x * ↑(2 ^ ↑x)
case h m : β„• i : Fin (m + 1) b : Bool p : BV m ⊒ β†‘βŸ¨βˆ‘ x : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x, β‹―βŸ© = ↑(βˆ‘ x : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE β‹― p / ↑(2 ^ ↑b) % 2) x * ↑(2 ^ ↑x))
Please generate a tactic in lean4 to solve the state. STATE: m : β„• i : Fin (m + 1) b : Bool p : BV m ⊒ βŸ¨βˆ‘ x : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x, β‹―βŸ© = βˆ‘ x : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE β‹― p / ↑(2 ^ ↑b) % 2) x * ↑(2 ^ ↑x) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_apply'
[88, 1]
[97, 12]
simp
case h m : β„• i : Fin (m + 1) b : Bool p : BV m ⊒ β†‘βŸ¨βˆ‘ x : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x, β‹―βŸ© = ↑(βˆ‘ x : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE β‹― p / ↑(2 ^ ↑b) % 2) x * ↑(2 ^ ↑x))
case h m : β„• i : Fin (m + 1) b : Bool p : BV m ⊒ βˆ‘ x : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x = ↑(βˆ‘ x : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE β‹― p / 2 ^ ↑b % 2) x * 2 ^ ↑x)
Please generate a tactic in lean4 to solve the state. STATE: case h m : β„• i : Fin (m + 1) b : Bool p : BV m ⊒ β†‘βŸ¨βˆ‘ x : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x, β‹―βŸ© = ↑(βˆ‘ x : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE β‹― p / ↑(2 ^ ↑b) % 2) x * ↑(2 ^ ↑x)) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_apply'
[88, 1]
[97, 12]
norm_cast
case h m : β„• i : Fin (m + 1) b : Bool p : BV m ⊒ βˆ‘ x : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x = ↑(βˆ‘ x : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE β‹― p / 2 ^ ↑b % 2) x * 2 ^ ↑x)
case h m : β„• i : Fin (m + 1) b : Bool p : BV m ⊒ βˆ‘ x : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x = ↑(βˆ‘ x : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE β‹― p / ↑(2 ^ ↑b) % 2) x * ↑(2 ^ ↑x))
Please generate a tactic in lean4 to solve the state. STATE: case h m : β„• i : Fin (m + 1) b : Bool p : BV m ⊒ βˆ‘ x : Fin (m + 1), ↑(i.insertNth (bif b then 1 else 0) (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x = ↑(βˆ‘ x : Fin (m + 1), i.insertNth (bif b then 1 else 0) (fun b => Fin.castLE β‹― p / 2 ^ ↑b % 2) x * 2 ^ ↑x) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_apply_true_eq_apply_false_add_apply_true_zero
[99, 1]
[108, 70]
unfold mergeBitRes getBitRes
m : β„• p : BV m i : Fin (m + 1) ⊒ mergeBitRes i true p = mergeBitRes i false p + mergeBitRes i true 0
m : β„• p : BV m i : Fin (m + 1) ⊒ Function.curry (⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i)) (finTwoEquiv.prodCongr finFunctionFinEquiv)).symm) true p = Function.curry (⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i)) (finTwoEquiv.prodCongr finFunctionFinEquiv)).symm) false p + Function.curry (⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i)) (finTwoEquiv.prodCongr finFunctionFinEquiv)).symm) true 0
Please generate a tactic in lean4 to solve the state. STATE: m : β„• p : BV m i : Fin (m + 1) ⊒ mergeBitRes i true p = mergeBitRes i false p + mergeBitRes i true 0 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_apply_true_eq_apply_false_add_apply_true_zero
[99, 1]
[108, 70]
simp [finFunctionFinEquiv]
m : β„• p : BV m i : Fin (m + 1) ⊒ Function.curry (⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i)) (finTwoEquiv.prodCongr finFunctionFinEquiv)).symm) true p = Function.curry (⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i)) (finTwoEquiv.prodCongr finFunctionFinEquiv)).symm) false p + Function.curry (⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i)) (finTwoEquiv.prodCongr finFunctionFinEquiv)).symm) true 0
m : β„• p : BV m i : Fin (m + 1) ⊒ βŸ¨βˆ‘ i_1 : Fin (m + 1), ↑(i.insertNth 1 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) i_1) * 2 ^ ↑i_1, β‹―βŸ© = βŸ¨βˆ‘ i_1 : Fin (m + 1), ↑(i.insertNth 0 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) i_1) * 2 ^ ↑i_1, β‹―βŸ© + βŸ¨βˆ‘ i_1 : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) i_1) * 2 ^ ↑i_1, β‹―βŸ©
Please generate a tactic in lean4 to solve the state. STATE: m : β„• p : BV m i : Fin (m + 1) ⊒ Function.curry (⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i)) (finTwoEquiv.prodCongr finFunctionFinEquiv)).symm) true p = Function.curry (⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i)) (finTwoEquiv.prodCongr finFunctionFinEquiv)).symm) false p + Function.curry (⇑(Trans.trans (Trans.trans finFunctionFinEquiv.symm (Equiv.piFinSuccAbove (fun a => Fin 2) i)) (finTwoEquiv.prodCongr finFunctionFinEquiv)).symm) true 0 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_apply_true_eq_apply_false_add_apply_true_zero
[99, 1]
[108, 70]
norm_cast
m : β„• p : BV m i : Fin (m + 1) ⊒ βŸ¨βˆ‘ i_1 : Fin (m + 1), ↑(i.insertNth 1 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) i_1) * 2 ^ ↑i_1, β‹―βŸ© = βŸ¨βˆ‘ i_1 : Fin (m + 1), ↑(i.insertNth 0 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) i_1) * 2 ^ ↑i_1, β‹―βŸ© + βŸ¨βˆ‘ i_1 : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) i_1) * 2 ^ ↑i_1, β‹―βŸ©
m : β„• p : BV m i : Fin (m + 1) ⊒ βŸ¨βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x, β‹―βŸ© = βŸ¨βˆ‘ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x, β‹―βŸ© + βŸ¨βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x, β‹―βŸ©
Please generate a tactic in lean4 to solve the state. STATE: m : β„• p : BV m i : Fin (m + 1) ⊒ βŸ¨βˆ‘ i_1 : Fin (m + 1), ↑(i.insertNth 1 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) i_1) * 2 ^ ↑i_1, β‹―βŸ© = βŸ¨βˆ‘ i_1 : Fin (m + 1), ↑(i.insertNth 0 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) i_1) * 2 ^ ↑i_1, β‹―βŸ© + βŸ¨βˆ‘ i_1 : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) i_1) * 2 ^ ↑i_1, β‹―βŸ© TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_apply_true_eq_apply_false_add_apply_true_zero
[99, 1]
[108, 70]
simp_rw [Fin.add_def]
m : β„• p : BV m i : Fin (m + 1) ⊒ βŸ¨βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x, β‹―βŸ© = βŸ¨βˆ‘ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x, β‹―βŸ© + βŸ¨βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x, β‹―βŸ©
m : β„• p : BV m i : Fin (m + 1) ⊒ βŸ¨βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x, β‹―βŸ© = ⟨(βˆ‘ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x + βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x) % 2 ^ (m + 1), β‹―βŸ©
Please generate a tactic in lean4 to solve the state. STATE: m : β„• p : BV m i : Fin (m + 1) ⊒ βŸ¨βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x, β‹―βŸ© = βŸ¨βˆ‘ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x, β‹―βŸ© + βŸ¨βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x, β‹―βŸ© TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_apply_true_eq_apply_false_add_apply_true_zero
[99, 1]
[108, 70]
ext : 1
m : β„• p : BV m i : Fin (m + 1) ⊒ βŸ¨βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x, β‹―βŸ© = ⟨(βˆ‘ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x + βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x) % 2 ^ (m + 1), β‹―βŸ©
case h m : β„• p : BV m i : Fin (m + 1) ⊒ β†‘βŸ¨βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x, β‹―βŸ© = β†‘βŸ¨(βˆ‘ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x + βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x) % 2 ^ (m + 1), β‹―βŸ©
Please generate a tactic in lean4 to solve the state. STATE: m : β„• p : BV m i : Fin (m + 1) ⊒ βŸ¨βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x, β‹―βŸ© = ⟨(βˆ‘ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x + βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x) % 2 ^ (m + 1), β‹―βŸ© TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_apply_true_eq_apply_false_add_apply_true_zero
[99, 1]
[108, 70]
simp
case h m : β„• p : BV m i : Fin (m + 1) ⊒ β†‘βŸ¨βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x, β‹―βŸ© = β†‘βŸ¨(βˆ‘ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x + βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x) % 2 ^ (m + 1), β‹―βŸ©
case h m : β„• p : BV m i : Fin (m + 1) ⊒ βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x = (βˆ‘ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x + βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x) % 2 ^ (m + 1)
Please generate a tactic in lean4 to solve the state. STATE: case h m : β„• p : BV m i : Fin (m + 1) ⊒ β†‘βŸ¨βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x, β‹―βŸ© = β†‘βŸ¨(βˆ‘ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x + βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x) % 2 ^ (m + 1), β‹―βŸ© TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_apply_true_eq_apply_false_add_apply_true_zero
[99, 1]
[108, 70]
rw [← Finset.sum_add_distrib, Finset.sum_nat_mod, Finset.sum_congr]
case h m : β„• p : BV m i : Fin (m + 1) ⊒ βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x = (βˆ‘ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x + βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x) % 2 ^ (m + 1)
case h m : β„• p : BV m i : Fin (m + 1) ⊒ ?m.88623.sum ?m.88625 = (βˆ‘ i_1 : Fin (m + 1), (↑(i.insertNth 0 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) i_1) * 2 ^ ↑i_1 + ↑(i.insertNth 1 (fun b => 0) i_1) * 2 ^ ↑i_1) % 2 ^ (m + 1)) % 2 ^ (m + 1) case h.h m : β„• p : BV m i : Fin (m + 1) ⊒ Finset.univ = ?m.88623 case h.a m : β„• p : BV m i : Fin (m + 1) ⊒ βˆ€ x ∈ ?m.88623, ↑(i.insertNth 1 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x = ?m.88625 x m : β„• p : BV m i : Fin (m + 1) ⊒ Finset (Fin (m + 1)) m : β„• p : BV m i : Fin (m + 1) ⊒ Fin (m + 1) β†’ β„•
Please generate a tactic in lean4 to solve the state. STATE: case h m : β„• p : BV m i : Fin (m + 1) ⊒ βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x = (βˆ‘ x : Fin (m + 1), ↑(i.insertNth 0 (fun b => βŸ¨β†‘p / 2 ^ ↑b % 2, β‹―βŸ©) x) * 2 ^ ↑x + βˆ‘ x : Fin (m + 1), ↑(i.insertNth 1 (fun b => 0) x) * 2 ^ ↑x) % 2 ^ (m + 1) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitResZero_symm_apply
[120, 1]
[121, 65]
cases b <;> rfl
b : Bool a✝ : β„• p : BV a✝ ⊒ getBitResZero.symm (b, p) = finProdFinEquiv (p, bif b then 1 else 0)
no goals
Please generate a tactic in lean4 to solve the state. STATE: b : Bool a✝ : β„• p : BV a✝ ⊒ getBitResZero.symm (b, p) = finProdFinEquiv (p, bif b then 1 else 0) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitRes_zero
[123, 1]
[136, 61]
ext q : 1
m : β„• ⊒ getBitRes 0 = getBitResZero
case H m : β„• q : BV (m + 1) ⊒ (getBitRes 0) q = getBitResZero q
Please generate a tactic in lean4 to solve the state. STATE: m : β„• ⊒ getBitRes 0 = getBitResZero TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitRes_zero
[123, 1]
[136, 61]
simp_rw [getBitRes_apply, getBitResZero_apply, Fin.zero_succAbove, finFunctionFinEquiv, Equiv.ofRightInverseOfCardLE_symm_apply, Fin.val_zero, pow_zero, Nat.div_one, finTwoEquiv_apply, Fin.val_succ, Equiv.ofRightInverseOfCardLE_apply, Nat.pow_eq, Prod.mk.injEq, decide_eq_decide, Fin.ext_iff, Fin.val_one, Fin.coe_modNat, Finset.sum_fin_eq_sum_range, dite_eq_ite, Fin.coe_divNat, true_and]
case H m : β„• q : BV (m + 1) ⊒ (getBitRes 0) q = getBitResZero q
case H m : β„• q : BV (m + 1) ⊒ (βˆ‘ x ∈ Finset.range m, if x < m then ↑q / 2 ^ (x + 1) % 2 * 2 ^ x else 0) = ↑q / 2
Please generate a tactic in lean4 to solve the state. STATE: case H m : β„• q : BV (m + 1) ⊒ (getBitRes 0) q = getBitResZero q TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitRes_zero
[123, 1]
[136, 61]
rw [Finset.sum_ite_of_true (h := fun _ H => (Finset.mem_range.mp H))]
case H m : β„• q : BV (m + 1) ⊒ (βˆ‘ x ∈ Finset.range m, if x < m then ↑q / 2 ^ (x + 1) % 2 * 2 ^ x else 0) = ↑q / 2
case H m : β„• q : BV (m + 1) ⊒ βˆ‘ x ∈ Finset.range m, ↑q / 2 ^ (x + 1) % 2 * 2 ^ x = ↑q / 2
Please generate a tactic in lean4 to solve the state. STATE: case H m : β„• q : BV (m + 1) ⊒ (βˆ‘ x ∈ Finset.range m, if x < m then ↑q / 2 ^ (x + 1) % 2 * 2 ^ x else 0) = ↑q / 2 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitRes_zero
[123, 1]
[136, 61]
refine' Nat.eq_of_mul_eq_mul_left (zero_lt_two) (add_right_cancel (b := (q : β„•) / 2 ^ 0 % 2 * 2 ^ 0) _)
case H m : β„• q : BV (m + 1) ⊒ βˆ‘ x ∈ Finset.range m, ↑q / 2 ^ (x + 1) % 2 * 2 ^ x = ↑q / 2
case H m : β„• q : BV (m + 1) ⊒ 2 * βˆ‘ x ∈ Finset.range m, ↑q / 2 ^ (x + 1) % 2 * 2 ^ x + ↑q / 2 ^ 0 % 2 * 2 ^ 0 = 2 * (↑q / 2) + ↑q / 2 ^ 0 % 2 * 2 ^ 0
Please generate a tactic in lean4 to solve the state. STATE: case H m : β„• q : BV (m + 1) ⊒ βˆ‘ x ∈ Finset.range m, ↑q / 2 ^ (x + 1) % 2 * 2 ^ x = ↑q / 2 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitRes_zero
[123, 1]
[136, 61]
simp_rw [Finset.mul_sum, mul_left_comm (2 : β„•), ← Nat.pow_succ', Nat.succ_eq_add_one, ← Finset.sum_range_succ' (fun x => (q : β„•) / 2 ^ x % 2 * 2 ^ x), pow_zero, Nat.div_one, mul_one, Nat.div_add_mod, Finset.sum_range, ← finFunctionFinEquiv_symm_apply_val, ← finFunctionFinEquiv_apply_val, Equiv.apply_symm_apply]
case H m : β„• q : BV (m + 1) ⊒ 2 * βˆ‘ x ∈ Finset.range m, ↑q / 2 ^ (x + 1) % 2 * 2 ^ x + ↑q / 2 ^ 0 % 2 * 2 ^ 0 = 2 * (↑q / 2) + ↑q / 2 ^ 0 % 2 * 2 ^ 0
no goals
Please generate a tactic in lean4 to solve the state. STATE: case H m : β„• q : BV (m + 1) ⊒ 2 * βˆ‘ x ∈ Finset.range m, ↑q / 2 ^ (x + 1) % 2 * 2 ^ x + ↑q / 2 ^ 0 % 2 * 2 ^ 0 = 2 * (↑q / 2) + ↑q / 2 ^ 0 % 2 * 2 ^ 0 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitRes_zero_apply
[138, 1]
[139, 48]
simp_rw [getBitRes_zero, getBitResZero_apply]
m : β„• q : BV (m + 1) ⊒ (getBitRes 0) q = (finTwoEquiv q.modNat, q.divNat)
no goals
Please generate a tactic in lean4 to solve the state. STATE: m : β„• q : BV (m + 1) ⊒ (getBitRes 0) q = (finTwoEquiv q.modNat, q.divNat) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitRes_zero_symm_apply
[141, 1]
[142, 100]
simp_rw [getBitRes_zero, getBitResZero_symm_apply]
m : β„• b : Bool p : BV m ⊒ (getBitRes 0).symm (b, p) = finProdFinEquiv (p, bif b then 1 else 0)
no goals
Please generate a tactic in lean4 to solve the state. STATE: m : β„• b : Bool p : BV m ⊒ (getBitRes 0).symm (b, p) = finProdFinEquiv (p, bif b then 1 else 0) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBit_zero
[144, 1]
[145, 47]
simp_rw [getBit_apply, getBitRes_zero_apply]
a✝ : β„• q : BV (a✝ + 1) ⊒ getBit 0 q = finTwoEquiv q.modNat
no goals
Please generate a tactic in lean4 to solve the state. STATE: a✝ : β„• q : BV (a✝ + 1) ⊒ getBit 0 q = finTwoEquiv q.modNat TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getRes_zero
[147, 1]
[148, 47]
simp_rw [getRes_apply, getBitRes_zero_apply]
a✝ : β„• q : BV (a✝ + 1) ⊒ getRes 0 q = q.divNat
no goals
Please generate a tactic in lean4 to solve the state. STATE: a✝ : β„• q : BV (a✝ + 1) ⊒ getRes 0 q = q.divNat TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_zero
[150, 1]
[151, 57]
simp_rw [mergeBitRes_apply, getBitRes_zero_symm_apply]
b : Bool a✝ : β„• p : BV a✝ ⊒ mergeBitRes 0 b p = finProdFinEquiv (p, bif b then 1 else 0)
no goals
Please generate a tactic in lean4 to solve the state. STATE: b : Bool a✝ : β„• p : BV a✝ ⊒ mergeBitRes 0 b p = finProdFinEquiv (p, bif b then 1 else 0) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_zero_divNat_modNat
[153, 1]
[156, 25]
simp_rw [← finProdFinEquiv_symm_apply, Equiv.symm_apply_eq]
b : Bool a✝ : β„• p : BV a✝ ⊒ ((mergeBitRes 0 b p).divNat, (mergeBitRes 0 b p).modNat) = (p, bif b then 1 else 0)
b : Bool a✝ : β„• p : BV a✝ ⊒ mergeBitRes 0 b p = finProdFinEquiv (p, bif b then 1 else 0)
Please generate a tactic in lean4 to solve the state. STATE: b : Bool a✝ : β„• p : BV a✝ ⊒ ((mergeBitRes 0 b p).divNat, (mergeBitRes 0 b p).modNat) = (p, bif b then 1 else 0) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_zero_divNat_modNat
[153, 1]
[156, 25]
exact mergeBitRes_zero
b : Bool a✝ : β„• p : BV a✝ ⊒ mergeBitRes 0 b p = finProdFinEquiv (p, bif b then 1 else 0)
no goals
Please generate a tactic in lean4 to solve the state. STATE: b : Bool a✝ : β„• p : BV a✝ ⊒ mergeBitRes 0 b p = finProdFinEquiv (p, bif b then 1 else 0) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_zero_apply_true_zero_eq_one
[164, 1]
[167, 43]
simp_rw [mergeBitRes_zero, Fin.ext_iff, finProdFinEquiv_apply_val, Fin.val_zero', mul_zero, add_zero, Bool.cond_true, Fin.val_one, Fin.val_one', ← Nat.pow_succ, Nat.mod_eq_of_lt (Nat.one_lt_pow' _ _ )]
m : β„• ⊒ mergeBitRes 0 true 0 = 1
no goals
Please generate a tactic in lean4 to solve the state. STATE: m : β„• ⊒ mergeBitRes 0 true 0 = 1 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_base_true
[169, 1]
[170, 82]
rw [Fin.eq_zero p, Fin.eq_zero i]
i : Fin (0 + 1) p : BV 0 ⊒ mergeBitRes i true p = 1
i : Fin (0 + 1) p : BV 0 ⊒ mergeBitRes 0 true 0 = 1
Please generate a tactic in lean4 to solve the state. STATE: i : Fin (0 + 1) p : BV 0 ⊒ mergeBitRes i true p = 1 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_base_true
[169, 1]
[170, 82]
exact mergeBitRes_zero_apply_true_zero_eq_one
i : Fin (0 + 1) p : BV 0 ⊒ mergeBitRes 0 true 0 = 1
no goals
Please generate a tactic in lean4 to solve the state. STATE: i : Fin (0 + 1) p : BV 0 ⊒ mergeBitRes 0 true 0 = 1 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_base_false
[172, 1]
[173, 56]
rw [Fin.eq_zero p]
i : Fin (0 + 1) p : BV 0 ⊒ mergeBitRes i false p = 0
i : Fin (0 + 1) p : BV 0 ⊒ mergeBitRes i false 0 = 0
Please generate a tactic in lean4 to solve the state. STATE: i : Fin (0 + 1) p : BV 0 ⊒ mergeBitRes i false p = 0 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_base_false
[172, 1]
[173, 56]
exact mergeBitRes_apply_false_zero
i : Fin (0 + 1) p : BV 0 ⊒ mergeBitRes i false 0 = 0
no goals
Please generate a tactic in lean4 to solve the state. STATE: i : Fin (0 + 1) p : BV 0 ⊒ mergeBitRes i false 0 = 0 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBit_base
[178, 1]
[180, 65]
rw [Fin.eq_zero i]
i : Fin (0 + 1) q : BV (0 + 1) ⊒ getBit i q = decide (q = 1)
i : Fin (0 + 1) q : BV (0 + 1) ⊒ getBit 0 q = decide (q = 1)
Please generate a tactic in lean4 to solve the state. STATE: i : Fin (0 + 1) q : BV (0 + 1) ⊒ getBit i q = decide (q = 1) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBit_base
[178, 1]
[180, 65]
rcases Fin.exists_fin_two.mp ⟨q, rfl⟩ with (rfl | rfl) <;> rfl
i : Fin (0 + 1) q : BV (0 + 1) ⊒ getBit 0 q = decide (q = 1)
no goals
Please generate a tactic in lean4 to solve the state. STATE: i : Fin (0 + 1) q : BV (0 + 1) ⊒ getBit 0 q = decide (q = 1) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getRes_base
[182, 1]
[184, 65]
rw [Fin.eq_zero i]
i : Fin (0 + 1) q : BV (0 + 1) ⊒ getRes i q = 0
i : Fin (0 + 1) q : BV (0 + 1) ⊒ getRes 0 q = 0
Please generate a tactic in lean4 to solve the state. STATE: i : Fin (0 + 1) q : BV (0 + 1) ⊒ getRes i q = 0 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getRes_base
[182, 1]
[184, 65]
rcases Fin.exists_fin_two.mp ⟨q, rfl⟩ with (rfl | rfl) <;> rfl
i : Fin (0 + 1) q : BV (0 + 1) ⊒ getRes 0 q = 0
no goals
Please generate a tactic in lean4 to solve the state. STATE: i : Fin (0 + 1) q : BV (0 + 1) ⊒ getRes 0 q = 0 TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitRes_succ
[202, 1]
[207, 53]
simp_rw [Equiv.ext_iff, getBitResSucc_apply, getBitRes_apply, getBitRes_symm_apply, Equiv.symm_apply_apply, Prod.mk.injEq, EmbeddingLike.apply_eq_iff_eq, Fin.eq_insertNth_iff, Fin.succAbove_zero, Fin.succ_succAbove_zero, Fin.succ_succAbove_succ, true_and, implies_true]
m : β„• i : Fin (m + 1) ⊒ getBitRes i.succ = getBitResSucc i
no goals
Please generate a tactic in lean4 to solve the state. STATE: m : β„• i : Fin (m + 1) ⊒ getBitRes i.succ = getBitResSucc i TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitRes_succ_apply
[209, 1]
[212, 43]
rw [getBitRes_succ, getBitResSucc_apply]
m : β„• q : BV (m + 1 + 1) i : Fin (m + 1) ⊒ (getBitRes i.succ) q = (((getBitRes i) ((getBitRes 0) q).2).1, (getBitRes 0).symm (((getBitRes 0) q).1, ((getBitRes i) ((getBitRes 0) q).2).2))
no goals
Please generate a tactic in lean4 to solve the state. STATE: m : β„• q : BV (m + 1 + 1) i : Fin (m + 1) ⊒ (getBitRes i.succ) q = (((getBitRes i) ((getBitRes 0) q).2).1, (getBitRes 0).symm (((getBitRes 0) q).1, ((getBitRes i) ((getBitRes 0) q).2).2)) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitRes_succ_symm_apply
[214, 1]
[216, 48]
rw [getBitRes_succ, getBitResSucc_symm_apply]
m : β„• b : Bool p : BV (m + 1) i : Fin (m + 1) ⊒ (getBitRes i.succ).symm (b, p) = (getBitRes 0).symm (((getBitRes 0) p).1, (getBitRes i).symm (b, ((getBitRes 0) p).2))
no goals
Please generate a tactic in lean4 to solve the state. STATE: m : β„• b : Bool p : BV (m + 1) i : Fin (m + 1) ⊒ (getBitRes i.succ).symm (b, p) = (getBitRes 0).symm (((getBitRes 0) p).1, (getBitRes i).symm (b, ((getBitRes 0) p).2)) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getRes_succ
[218, 1]
[220, 80]
simp_rw [getRes_apply, mergeBitRes_apply, getBit_apply, getBitRes_succ_apply]
m : β„• q : BV (m + 1 + 1) i : Fin (m + 1) ⊒ getRes i.succ q = mergeBitRes 0 (getBit 0 q) (getRes i (getRes 0 q))
no goals
Please generate a tactic in lean4 to solve the state. STATE: m : β„• q : BV (m + 1 + 1) i : Fin (m + 1) ⊒ getRes i.succ q = mergeBitRes 0 (getBit 0 q) (getRes i (getRes 0 q)) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBit_succ
[222, 1]
[224, 61]
simp_rw [getRes_apply, getBit_apply, getBitRes_succ_apply]
m : β„• q : BV (m + 1 + 1) i : Fin (m + 1) ⊒ getBit i.succ q = getBit i (getRes 0 q)
no goals
Please generate a tactic in lean4 to solve the state. STATE: m : β„• q : BV (m + 1 + 1) i : Fin (m + 1) ⊒ getBit i.succ q = getBit i (getRes 0 q) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_succ
[226, 1]
[228, 85]
simp_rw [mergeBitRes_apply, getBit_apply, getRes_apply, getBitRes_succ_symm_apply]
m : β„• b : Bool q : BV (m + 1) i : Fin (m + 1) ⊒ mergeBitRes i.succ b q = mergeBitRes 0 (getBit 0 q) (mergeBitRes i b (getRes 0 q))
no goals
Please generate a tactic in lean4 to solve the state. STATE: m : β„• b : Bool q : BV (m + 1) i : Fin (m + 1) ⊒ mergeBitRes i.succ b q = mergeBitRes 0 (getBit 0 q) (mergeBitRes i b (getRes 0 q)) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitResLast_symm_apply
[230, 1]
[231, 65]
cases b <;> rfl
b : Bool a✝ : β„• p : BV a✝ ⊒ getBitResZero.symm (b, p) = finProdFinEquiv (p, bif b then 1 else 0)
no goals
Please generate a tactic in lean4 to solve the state. STATE: b : Bool a✝ : β„• p : BV a✝ ⊒ getBitResZero.symm (b, p) = finProdFinEquiv (p, bif b then 1 else 0) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitRes_castSucc
[251, 1]
[256, 61]
simp_rw [Equiv.ext_iff, getBitResCastSucc_apply, getBitRes_apply, getBitRes_symm_apply, Equiv.symm_apply_apply, Prod.mk.injEq, EmbeddingLike.apply_eq_iff_eq, Fin.eq_insertNth_iff, Fin.succAbove_last, Fin.castSucc_succAbove_last, Fin.castSucc_succAbove_castSucc, true_and, implies_true]
m : β„• i : Fin (m + 1) ⊒ getBitRes i.castSucc = getBitResCastSucc i
no goals
Please generate a tactic in lean4 to solve the state. STATE: m : β„• i : Fin (m + 1) ⊒ getBitRes i.castSucc = getBitResCastSucc i TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitRes_castSucc_apply
[258, 1]
[262, 51]
rw [getBitRes_castSucc, getBitResCastSucc_apply]
m : β„• q : BV (m + 1 + 1) i : Fin (m + 1) ⊒ (getBitRes i.castSucc) q = (((getBitRes i) ((getBitRes (Fin.last (m + 1))) q).2).1, (getBitRes (Fin.last m)).symm (((getBitRes (Fin.last (m + 1))) q).1, ((getBitRes i) ((getBitRes (Fin.last (m + 1))) q).2).2))
no goals
Please generate a tactic in lean4 to solve the state. STATE: m : β„• q : BV (m + 1 + 1) i : Fin (m + 1) ⊒ (getBitRes i.castSucc) q = (((getBitRes i) ((getBitRes (Fin.last (m + 1))) q).2).1, (getBitRes (Fin.last m)).symm (((getBitRes (Fin.last (m + 1))) q).1, ((getBitRes i) ((getBitRes (Fin.last (m + 1))) q).2).2)) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitRes_castSucc_symm_apply
[264, 1]
[267, 56]
rw [getBitRes_castSucc, getBitResCastSucc_symm_apply]
m : β„• b : Bool p : BV (m + 1) i : Fin (m + 1) ⊒ (getBitRes i.castSucc).symm (b, p) = (getBitRes (Fin.last (m + 1))).symm (((getBitRes (Fin.last m)) p).1, (getBitRes i).symm (b, ((getBitRes (Fin.last m)) p).2))
no goals
Please generate a tactic in lean4 to solve the state. STATE: m : β„• b : Bool p : BV (m + 1) i : Fin (m + 1) ⊒ (getBitRes i.castSucc).symm (b, p) = (getBitRes (Fin.last (m + 1))).symm (((getBitRes (Fin.last m)) p).1, (getBitRes i).symm (b, ((getBitRes (Fin.last m)) p).2)) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getRes_castSucc
[269, 1]
[271, 84]
simp_rw [getRes_apply, mergeBitRes_apply, getBit_apply, getBitRes_castSucc_apply]
m : β„• q : BV (m + 1 + 1) i : Fin (m + 1) ⊒ getRes i.castSucc q = mergeBitRes (Fin.last m) (getBit (Fin.last (m + 1)) q) (getRes i (getRes (Fin.last (m + 1)) q))
no goals
Please generate a tactic in lean4 to solve the state. STATE: m : β„• q : BV (m + 1 + 1) i : Fin (m + 1) ⊒ getRes i.castSucc q = mergeBitRes (Fin.last m) (getBit (Fin.last (m + 1)) q) (getRes i (getRes (Fin.last (m + 1)) q)) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBit_castSucc
[273, 1]
[275, 65]
simp_rw [getRes_apply, getBit_apply, getBitRes_castSucc_apply]
m : β„• q : BV (m + 1 + 1) i : Fin (m + 1) ⊒ getBit i.castSucc q = getBit i (getRes (Fin.last (m + 1)) q)
no goals
Please generate a tactic in lean4 to solve the state. STATE: m : β„• q : BV (m + 1 + 1) i : Fin (m + 1) ⊒ getBit i.castSucc q = getBit i (getRes (Fin.last (m + 1)) q) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
mergeBitRes_castSucc
[277, 1]
[279, 89]
simp_rw [mergeBitRes_apply, getBit_apply, getRes_apply, getBitRes_castSucc_symm_apply]
m : β„• b : Bool q : BV (m + 1) i : Fin (m + 1) ⊒ mergeBitRes i.castSucc b q = mergeBitRes (Fin.last (m + 1)) (getBit (Fin.last m) q) (mergeBitRes i b (getRes (Fin.last m) q))
no goals
Please generate a tactic in lean4 to solve the state. STATE: m : β„• b : Bool q : BV (m + 1) i : Fin (m + 1) ⊒ mergeBitRes i.castSucc b q = mergeBitRes (Fin.last (m + 1)) (getBit (Fin.last m) q) (mergeBitRes i b (getRes (Fin.last m) q)) TACTIC:
https://github.com/linesthatinterlace/controlbits.git
4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01
Controlbits/BitResiduum.lean
getBitRes_succAbove
[300, 1]
[306, 73]
simp_rw [Equiv.ext_iff, getBitResSuccAbove_apply, getBitRes_apply, getBitRes_symm_apply, Equiv.symm_apply_apply, Prod.mk.injEq, EmbeddingLike.apply_eq_iff_eq, Fin.eq_insertNth_iff, Fin.succAbove_succAbove_predAbove, Fin.succAbove_succAbove_predAbove_succAbove, true_and, implies_true]
m : β„• j : Fin (m + 2) i : Fin (m + 1) ⊒ getBitRes (j.succAbove i) = getBitResSuccAbove j i
no goals
Please generate a tactic in lean4 to solve the state. STATE: m : β„• j : Fin (m + 2) i : Fin (m + 1) ⊒ getBitRes (j.succAbove i) = getBitResSuccAbove j i TACTIC: