url stringclasses 147
values | commit stringclasses 147
values | file_path stringlengths 7 101 | full_name stringlengths 1 94 | start stringlengths 6 10 | end stringlengths 6 11 | tactic stringlengths 1 11.2k | state_before stringlengths 3 2.09M | state_after stringlengths 6 2.09M | input stringlengths 73 2.09M |
|---|---|---|---|---|---|---|---|---|---|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_zero_eq_and_getBit_zero_opp_of_lt_of_flipBit_gt | [861, 1] | [869, 67] | exact ⟨hr, hq, Fin.ext (Nat.eq_of_mul_eq_mul_left zero_lt_two he)⟩ | case intro.intro.intro.intro.intro.intro
a✝ : ℕ
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
hf : (2 * ↑pq + bif bq then 0 else 1) < 2 * ↑pr + bif br then 0 else 1
h : (2 * ↑pr + bif br then 1 else 0) < 2 * ↑pq + bif bq then 1 else 0
hr : br = false
hq : bq = true
he : 2 * ↑pr = 2 * ↑pq
⊢ br = false ∧ bq = true ∧ pr = pq | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro.intro.intro.intro.intro
a✝ : ℕ
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
hf : (2 * ↑pq + bif bq then 0 else 1) < 2 * ↑pr + bif br then 0 else 1
h : (2 * ↑pr + bif br then 1 else 0) < 2 * ↑pq + bif bq then 1 else 0
hr : br = false
hq : bq = true
he : 2 * ↑pr = 2 * ↑pq
⊢ br = false ∧ bq = true ∧ pr = pq
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_zero_of_lt_of_flipBit_zero_gt | [871, 1] | [874, 65] | rcases getRes_zero_eq_and_getBit_zero_opp_of_lt_of_flipBit_gt h hf with ⟨hr, hq, hrq⟩ | a✝ : ℕ
r q : BV (a✝ + 1)
h : r < q
hf : (flipBit 0) q < (flipBit 0) r
⊢ r = (flipBit 0) q | case intro.intro
a✝ : ℕ
r q : BV (a✝ + 1)
h : r < q
hf : (flipBit 0) q < (flipBit 0) r
hr : getBit 0 r = false
hq : getBit 0 q = true
hrq : getRes 0 r = getRes 0 q
⊢ r = (flipBit 0) q | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
r q : BV (a✝ + 1)
h : r < q
hf : (flipBit 0) q < (flipBit 0) r
⊢ r = (flipBit 0) q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_zero_of_lt_of_flipBit_zero_gt | [871, 1] | [874, 65] | simp only [eq_flipBit_iff, hr, hq, hrq, Bool.not_true, and_self] | case intro.intro
a✝ : ℕ
r q : BV (a✝ + 1)
h : r < q
hf : (flipBit 0) q < (flipBit 0) r
hr : getBit 0 r = false
hq : getBit 0 q = true
hrq : getRes 0 r = getRes 0 q
⊢ r = (flipBit 0) q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro
a✝ : ℕ
r q : BV (a✝ + 1)
h : r < q
hf : (flipBit 0) q < (flipBit 0) r
hr : getBit 0 r = false
hq : getBit 0 q = true
hrq : getRes 0 r = getRes 0 q
⊢ r = (flipBit 0) q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_zero_of_lt_of_flipBit_zero_gt' | [876, 1] | [888, 74] | rcases mergeBitRes_surj i q with ⟨bq, pq, rfl⟩ | a✝ : ℕ
r q : BV (a✝ + 1)
i : Fin (a✝ + 1)
h : r < q
hf : (flipBit i) q < (flipBit i) r
⊢ ∀ k ≥ i, getBit k r = getBit k ((flipBit i) q) | case intro.intro
a✝ : ℕ
r : BV (a✝ + 1)
i : Fin (a✝ + 1)
bq : Bool
pq : BV a✝
h : r < mergeBitRes i bq pq
hf : (flipBit i) (mergeBitRes i bq pq) < (flipBit i) r
⊢ ∀ k ≥ i, getBit k r = getBit k ((flipBit i) (mergeBitRes i bq pq)) | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
r q : BV (a✝ + 1)
i : Fin (a✝ + 1)
h : r < q
hf : (flipBit i) q < (flipBit i) r
⊢ ∀ k ≥ i, getBit k r = getBit k ((flipBit i) q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_zero_of_lt_of_flipBit_zero_gt' | [876, 1] | [888, 74] | rcases mergeBitRes_surj i r with ⟨br, pr, rfl⟩ | case intro.intro
a✝ : ℕ
r : BV (a✝ + 1)
i : Fin (a✝ + 1)
bq : Bool
pq : BV a✝
h : r < mergeBitRes i bq pq
hf : (flipBit i) (mergeBitRes i bq pq) < (flipBit i) r
⊢ ∀ k ≥ i, getBit k r = getBit k ((flipBit i) (mergeBitRes i bq pq)) | case intro.intro.intro.intro
a✝ : ℕ
i : Fin (a✝ + 1)
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
h : mergeBitRes i br pr < mergeBitRes i bq pq
hf : (flipBit i) (mergeBitRes i bq pq) < (flipBit i) (mergeBitRes i br pr)
⊢ ∀ k ≥ i, getBit k (mergeBitRes i br pr) = getBit k ((flipBit i) (mergeBitRes i bq pq)) | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro
a✝ : ℕ
r : BV (a✝ + 1)
i : Fin (a✝ + 1)
bq : Bool
pq : BV a✝
h : r < mergeBitRes i bq pq
hf : (flipBit i) (mergeBitRes i bq pq) < (flipBit i) r
⊢ ∀ k ≥ i, getBit k r = getBit k ((flipBit i) (mergeBitRes i bq pq))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_zero_of_lt_of_flipBit_zero_gt' | [876, 1] | [888, 74] | simp_rw [flipBit_mergeBitRes] at hf | case intro.intro.intro.intro
a✝ : ℕ
i : Fin (a✝ + 1)
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
h : mergeBitRes i br pr < mergeBitRes i bq pq
hf : (flipBit i) (mergeBitRes i bq pq) < (flipBit i) (mergeBitRes i br pr)
⊢ ∀ k ≥ i, getBit k (mergeBitRes i br pr) = getBit k ((flipBit i) (mergeBitRes i bq pq)) | case intro.intro.intro.intro
a✝ : ℕ
i : Fin (a✝ + 1)
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
h : mergeBitRes i br pr < mergeBitRes i bq pq
hf : mergeBitRes i (!bq) pq < mergeBitRes i (!br) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i br pr) = getBit k ((flipBit i) (mergeBitRes i bq pq)) | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro.intro.intro
a✝ : ℕ
i : Fin (a✝ + 1)
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
h : mergeBitRes i br pr < mergeBitRes i bq pq
hf : (flipBit i) (mergeBitRes i bq pq) < (flipBit i) (mergeBitRes i br pr)
⊢ ∀ k ≥ i, getBit k (mergeBitRes i br pr) = getBit k ((flipBit i) (mergeBitRes i bq pq))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_zero_of_lt_of_flipBit_zero_gt' | [876, 1] | [888, 74] | cases br <;> cases bq | case intro.intro.intro.intro
a✝ : ℕ
i : Fin (a✝ + 1)
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
h : mergeBitRes i br pr < mergeBitRes i bq pq
hf : mergeBitRes i (!bq) pq < mergeBitRes i (!br) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i br pr) = getBit k ((flipBit i) (mergeBitRes i bq pq)) | case intro.intro.intro.intro.false.false
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i false pr < mergeBitRes i false pq
hf : mergeBitRes i (!false) pq < mergeBitRes i (!false) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i false pr) = getBit k ((flipBit i) (mergeBitRes i false pq))
case intro.intro.intro.intro.false.true
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i false pr < mergeBitRes i true pq
hf : mergeBitRes i (!true) pq < mergeBitRes i (!false) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i false pr) = getBit k ((flipBit i) (mergeBitRes i true pq))
case intro.intro.intro.intro.true.false
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i true pr < mergeBitRes i false pq
hf : mergeBitRes i (!false) pq < mergeBitRes i (!true) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i true pr) = getBit k ((flipBit i) (mergeBitRes i false pq))
case intro.intro.intro.intro.true.true
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i true pr < mergeBitRes i true pq
hf : mergeBitRes i (!true) pq < mergeBitRes i (!true) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i true pr) = getBit k ((flipBit i) (mergeBitRes i true pq)) | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro.intro.intro
a✝ : ℕ
i : Fin (a✝ + 1)
bq : Bool
pq : BV a✝
br : Bool
pr : BV a✝
h : mergeBitRes i br pr < mergeBitRes i bq pq
hf : mergeBitRes i (!bq) pq < mergeBitRes i (!br) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i br pr) = getBit k ((flipBit i) (mergeBitRes i bq pq))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_zero_of_lt_of_flipBit_zero_gt' | [876, 1] | [888, 74] | sorry | case intro.intro.intro.intro.false.false
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i false pr < mergeBitRes i false pq
hf : mergeBitRes i (!false) pq < mergeBitRes i (!false) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i false pr) = getBit k ((flipBit i) (mergeBitRes i false pq)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro.intro.intro.false.false
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i false pr < mergeBitRes i false pq
hf : mergeBitRes i (!false) pq < mergeBitRes i (!false) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i false pr) = getBit k ((flipBit i) (mergeBitRes i false pq))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_zero_of_lt_of_flipBit_zero_gt' | [876, 1] | [888, 74] | sorry | case intro.intro.intro.intro.false.true
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i false pr < mergeBitRes i true pq
hf : mergeBitRes i (!true) pq < mergeBitRes i (!false) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i false pr) = getBit k ((flipBit i) (mergeBitRes i true pq)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro.intro.intro.false.true
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i false pr < mergeBitRes i true pq
hf : mergeBitRes i (!true) pq < mergeBitRes i (!false) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i false pr) = getBit k ((flipBit i) (mergeBitRes i true pq))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_zero_of_lt_of_flipBit_zero_gt' | [876, 1] | [888, 74] | sorry | case intro.intro.intro.intro.true.false
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i true pr < mergeBitRes i false pq
hf : mergeBitRes i (!false) pq < mergeBitRes i (!true) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i true pr) = getBit k ((flipBit i) (mergeBitRes i false pq)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro.intro.intro.true.false
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i true pr < mergeBitRes i false pq
hf : mergeBitRes i (!false) pq < mergeBitRes i (!true) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i true pr) = getBit k ((flipBit i) (mergeBitRes i false pq))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | eq_flipBit_zero_of_lt_of_flipBit_zero_gt' | [876, 1] | [888, 74] | sorry | case intro.intro.intro.intro.true.true
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i true pr < mergeBitRes i true pq
hf : mergeBitRes i (!true) pq < mergeBitRes i (!true) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i true pr) = getBit k ((flipBit i) (mergeBitRes i true pq)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro.intro.intro.true.true
a✝ : ℕ
i : Fin (a✝ + 1)
pq pr : BV a✝
h : mergeBitRes i true pr < mergeBitRes i true pq
hf : mergeBitRes i (!true) pq < mergeBitRes i (!true) pr
⊢ ∀ k ≥ i, getBit k (mergeBitRes i true pr) = getBit k ((flipBit i) (mergeBitRes i true pq))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBitCore_condFlipBitCore | [897, 1] | [899, 87] | rcases (c (getRes i q)).dichotomy with h | h <;>
simp only [condFlipBitCore, h, cond_true, cond_false, getRes_flipBit, flipBit_flipBit] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ condFlipBitCore i c (condFlipBitCore i c q) = q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ condFlipBitCore i c (condFlipBitCore i c q) = q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_apply_eq_mergeBitRes | [913, 1] | [917, 49] | rw [condFlipBit_apply] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit i c) q = mergeBitRes i (xor (c (getRes i q)) (getBit i q)) (getRes i q) | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (bif c (getRes i q) then (flipBit i) q else q) = mergeBitRes i (xor (c (getRes i q)) (getBit i q)) (getRes i q) | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit i c) q = mergeBitRes i (xor (c (getRes i q)) (getBit i q)) (getRes i q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_apply_eq_mergeBitRes | [913, 1] | [917, 49] | cases (c (getRes i q)) | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (bif c (getRes i q) then (flipBit i) q else q) = mergeBitRes i (xor (c (getRes i q)) (getBit i q)) (getRes i q) | case false
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (bif false then (flipBit i) q else q) = mergeBitRes i (xor false (getBit i q)) (getRes i q)
case true
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (bif true then (flipBit i) q else q) = mergeBitRes i (xor true (getBit i q)) (getRes i q) | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (bif c (getRes i q) then (flipBit i) q else q) = mergeBitRes i (xor (c (getRes i q)) (getBit i q)) (getRes i q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_apply_eq_mergeBitRes | [913, 1] | [917, 49] | rw [cond_false, Bool.false_xor, mergeBitRes_getBit_getRes] | case false
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (bif false then (flipBit i) q else q) = mergeBitRes i (xor false (getBit i q)) (getRes i q) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case false
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (bif false then (flipBit i) q else q) = mergeBitRes i (xor false (getBit i q)) (getRes i q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_apply_eq_mergeBitRes | [913, 1] | [917, 49] | rw [cond_true, Bool.true_xor, flipBit_apply] | case true
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (bif true then (flipBit i) q else q) = mergeBitRes i (xor true (getBit i q)) (getRes i q) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case true
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (bif true then (flipBit i) q else q) = mergeBitRes i (xor true (getBit i q)) (getRes i q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_apply_eq_swap_apply | [919, 1] | [921, 80] | exact condFlipBit_apply_eq_mergeBitRes.trans (Equiv.swap_apply_left _ _).symm | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit i c) q = (Equiv.swap q (mergeBitRes i (xor (c (getRes i q)) (getBit i q)) (getRes i q))) q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit i c) q = (Equiv.swap q (mergeBitRes i (xor (c (getRes i q)) (getBit i q)) (getRes i q))) q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_base | [923, 1] | [926, 22] | ext q : 1 | i : Fin (0 + 1)
c : BV 0 → Bool
⊢ condFlipBit i c = bif c 0 then Equiv.swap 0 1 else 1 | case H
i : Fin (0 + 1)
c : BV 0 → Bool
q : BV (0 + 1)
⊢ (condFlipBit i c) q = (bif c 0 then Equiv.swap 0 1 else 1) q | Please generate a tactic in lean4 to solve the state.
STATE:
i : Fin (0 + 1)
c : BV 0 → Bool
⊢ condFlipBit i c = bif c 0 then Equiv.swap 0 1 else 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_base | [923, 1] | [926, 22] | rw [condFlipBit_apply, Fin.eq_zero (getRes i q), flipBit_base] | case H
i : Fin (0 + 1)
c : BV 0 → Bool
q : BV (0 + 1)
⊢ (condFlipBit i c) q = (bif c 0 then Equiv.swap 0 1 else 1) q | case H
i : Fin (0 + 1)
c : BV 0 → Bool
q : BV (0 + 1)
⊢ (bif c 0 then (Equiv.swap 0 1) q else q) = (bif c 0 then Equiv.swap 0 1 else 1) q | Please generate a tactic in lean4 to solve the state.
STATE:
case H
i : Fin (0 + 1)
c : BV 0 → Bool
q : BV (0 + 1)
⊢ (condFlipBit i c) q = (bif c 0 then Equiv.swap 0 1 else 1) q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_base | [923, 1] | [926, 22] | cases (c 0) <;> rfl | case H
i : Fin (0 + 1)
c : BV 0 → Bool
q : BV (0 + 1)
⊢ (bif c 0 then (Equiv.swap 0 1) q else q) = (bif c 0 then Equiv.swap 0 1 else 1) q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case H
i : Fin (0 + 1)
c : BV 0 → Bool
q : BV (0 + 1)
⊢ (bif c 0 then (Equiv.swap 0 1) q else q) = (bif c 0 then Equiv.swap 0 1 else 1) q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_mergeBitRes | [928, 1] | [930, 78] | rw [condFlipBit_apply_eq_mergeBitRes, getRes_mergeBitRes, getBit_mergeBitRes] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
b : Bool
p : BV a✝
⊢ (condFlipBit i c) (mergeBitRes i b p) = mergeBitRes i (xor (c p) b) p | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
b : Bool
p : BV a✝
⊢ (condFlipBit i c) (mergeBitRes i b p) = mergeBitRes i (xor (c p) b) p
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_mul_self | [942, 1] | [945, 54] | ext | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
⊢ condFlipBit i c * condFlipBit i c = 1 | case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
x✝ : BV (a✝ + 1)
⊢ ↑((condFlipBit i c * condFlipBit i c) x✝) = ↑(1 x✝) | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
⊢ condFlipBit i c * condFlipBit i c = 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_mul_self | [942, 1] | [945, 54] | simp_rw [Equiv.Perm.coe_mul, Function.comp_apply,
condFlipBit_condFlipBit, Equiv.Perm.coe_one, id_eq] | case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
x✝ : BV (a✝ + 1)
⊢ ↑((condFlipBit i c * condFlipBit i c) x✝) = ↑(1 x✝) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
x✝ : BV (a✝ + 1)
⊢ ↑((condFlipBit i c * condFlipBit i c) x✝) = ↑(1 x✝)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_mul_cancel_right | [947, 1] | [949, 48] | rw [mul_assoc, condFlipBit_mul_self, mul_one] | a✝ : ℕ
ρ : Equiv.Perm (BV (a✝ + 1))
i : Fin (a✝ + 1)
c : BV a✝ → Bool
⊢ ρ * condFlipBit i c * condFlipBit i c = ρ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
ρ : Equiv.Perm (BV (a✝ + 1))
i : Fin (a✝ + 1)
c : BV a✝ → Bool
⊢ ρ * condFlipBit i c * condFlipBit i c = ρ
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_mul_cancel_left | [951, 1] | [953, 50] | rw [← mul_assoc, condFlipBit_mul_self, one_mul] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
ρ : Equiv.Perm (BV (a✝ + 1))
⊢ condFlipBit i c * (condFlipBit i c * ρ) = ρ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
ρ : Equiv.Perm (BV (a✝ + 1))
⊢ condFlipBit i c * (condFlipBit i c * ρ) = ρ
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_flipBit_of_all_true | [955, 1] | [958, 6] | ext | a✝ : ℕ
i : Fin (a✝ + 1)
⊢ flipBit i = condFlipBit i (Function.const (BV a✝) true) | case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
x✝ : BV (a✝ + 1)
⊢ ↑((flipBit i) x✝) = ↑((condFlipBit i (Function.const (BV a✝) true)) x✝) | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
⊢ flipBit i = condFlipBit i (Function.const (BV a✝) true)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_flipBit_of_all_true | [955, 1] | [958, 6] | rw [condFlipBit_apply] | case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
x✝ : BV (a✝ + 1)
⊢ ↑((flipBit i) x✝) = ↑((condFlipBit i (Function.const (BV a✝) true)) x✝) | case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
x✝ : BV (a✝ + 1)
⊢ ↑((flipBit i) x✝) = ↑(bif Function.const (BV a✝) true (getRes i x✝) then (flipBit i) x✝ else x✝) | Please generate a tactic in lean4 to solve the state.
STATE:
case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
x✝ : BV (a✝ + 1)
⊢ ↑((flipBit i) x✝) = ↑((condFlipBit i (Function.const (BV a✝) true)) x✝)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_flipBit_of_all_true | [955, 1] | [958, 6] | rfl | case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
x✝ : BV (a✝ + 1)
⊢ ↑((flipBit i) x✝) = ↑(bif Function.const (BV a✝) true (getRes i x✝) then (flipBit i) x✝ else x✝) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
x✝ : BV (a✝ + 1)
⊢ ↑((flipBit i) x✝) = ↑(bif Function.const (BV a✝) true (getRes i x✝) then (flipBit i) x✝ else x✝)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_apply_comm | [962, 1] | [965, 42] | simp_rw [condFlipBit_apply_eq_mergeBitRes, getRes_mergeBitRes,
getBit_mergeBitRes, Bool.xor_left_comm] | a✝ : ℕ
i : Fin (a✝ + 1)
c d : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit i c) ((condFlipBit i d) q) = (condFlipBit i d) ((condFlipBit i c) q) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c d : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit i c) ((condFlipBit i d) q) = (condFlipBit i d) ((condFlipBit i c) q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_comm | [967, 1] | [969, 80] | ext | a✝ : ℕ
i : Fin (a✝ + 1)
c d : BV a✝ → Bool
⊢ condFlipBit i c * condFlipBit i d = condFlipBit i d * condFlipBit i c | case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
c d : BV a✝ → Bool
x✝ : BV (a✝ + 1)
⊢ ↑((condFlipBit i c * condFlipBit i d) x✝) = ↑((condFlipBit i d * condFlipBit i c) x✝) | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c d : BV a✝ → Bool
⊢ condFlipBit i c * condFlipBit i d = condFlipBit i d * condFlipBit i c
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_comm | [967, 1] | [969, 80] | simp_rw [Equiv.Perm.coe_mul, Function.comp_apply, condFlipBit_apply_comm] | case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
c d : BV a✝ → Bool
x✝ : BV (a✝ + 1)
⊢ ↑((condFlipBit i c * condFlipBit i d) x✝) = ↑((condFlipBit i d * condFlipBit i c) x✝) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case H.h
a✝ : ℕ
i : Fin (a✝ + 1)
c d : BV a✝ → Bool
x✝ : BV (a✝ + 1)
⊢ ↑((condFlipBit i c * condFlipBit i d) x✝) = ↑((condFlipBit i d * condFlipBit i c) x✝)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_apply_comm_flipBit | [971, 1] | [973, 63] | rw [condFlipBit_flipBit_of_all_true, condFlipBit_apply_comm] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit i c) ((flipBit i) q) = (flipBit i) ((condFlipBit i c) q) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit i c) ((flipBit i) q) = (flipBit i) ((condFlipBit i c) q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_comm_flipBit | [975, 1] | [977, 57] | rw [condFlipBit_flipBit_of_all_true, condFlipBit_comm] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
⊢ condFlipBit i c * flipBit i = flipBit i * condFlipBit i c | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
⊢ condFlipBit i c * flipBit i = flipBit i * condFlipBit i c
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_apply_flipBit | [979, 1] | [984, 41] | rw [condFlipBit_apply_comm_flipBit] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit i c) ((flipBit i) q) = bif c (getRes i q) then q else (flipBit i) q | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (flipBit i) ((condFlipBit i c) q) = bif c (getRes i q) then q else (flipBit i) q | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit i c) ((flipBit i) q) = bif c (getRes i q) then q else (flipBit i) q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_apply_flipBit | [979, 1] | [984, 41] | rcases (c (getRes i q)).dichotomy with h | h <;> rw [condFlipBit_apply, h] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (flipBit i) ((condFlipBit i c) q) = bif c (getRes i q) then q else (flipBit i) q | case inl
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = false
⊢ (flipBit i) (bif false then (flipBit i) q else q) = bif false then q else (flipBit i) q
case inr
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = true
⊢ (flipBit i) (bif true then (flipBit i) q else q) = bif true then q else (flipBit i) q | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (flipBit i) ((condFlipBit i c) q) = bif c (getRes i q) then q else (flipBit i) q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_apply_flipBit | [979, 1] | [984, 41] | simp_rw [cond_false] | case inl
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = false
⊢ (flipBit i) (bif false then (flipBit i) q else q) = bif false then q else (flipBit i) q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inl
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = false
⊢ (flipBit i) (bif false then (flipBit i) q else q) = bif false then q else (flipBit i) q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_apply_flipBit | [979, 1] | [984, 41] | simp_rw [cond_true, flipBit_flipBit] | case inr
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = true
⊢ (flipBit i) (bif true then (flipBit i) q else q) = bif true then q else (flipBit i) q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inr
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = true
⊢ (flipBit i) (bif true then (flipBit i) q else q) = bif true then q else (flipBit i) q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_condFlipBit | [986, 1] | [990, 33] | rcases (c (getRes i q)).dichotomy with h | h <;> rw [condFlipBit_apply, h] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ getRes i ((condFlipBit i c) q) = getRes i q | case inl
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = false
⊢ getRes i (bif false then (flipBit i) q else q) = getRes i q
case inr
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = true
⊢ getRes i (bif true then (flipBit i) q else q) = getRes i q | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ getRes i ((condFlipBit i c) q) = getRes i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_condFlipBit | [986, 1] | [990, 33] | rfl | case inl
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = false
⊢ getRes i (bif false then (flipBit i) q else q) = getRes i q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inl
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = false
⊢ getRes i (bif false then (flipBit i) q else q) = getRes i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getRes_condFlipBit | [986, 1] | [990, 33] | rw [cond_true, getRes_flipBit] | case inr
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = true
⊢ getRes i (bif true then (flipBit i) q else q) = getRes i q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inr
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
h : c (getRes i q) = true
⊢ getRes i (bif true then (flipBit i) q else q) = getRes i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_condFlipBit | [992, 1] | [995, 73] | rcases (c (getRes i q)).dichotomy with hc | hc <;>
simp only [condFlipBit_apply, cond_false, hc, cond_true, getBit_flipBit] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ getBit i ((condFlipBit i c) q) = bif c (getRes i q) then !getBit i q else getBit i q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ getBit i ((condFlipBit i c) q) = bif c (getRes i q) then !getBit i q else getBit i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_condFlipBit' | [997, 1] | [1001, 49] | rcases (c (getRes i q)).dichotomy with hc | hc <;>
simp only [condFlipBit_apply, hc, cond_false, cond_true,
Bool.false_xor, Bool.true_xor, getBit_flipBit] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ getBit i ((condFlipBit i c) q) = xor (c (getRes i q)) (getBit i q) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ getBit i ((condFlipBit i c) q) = xor (c (getRes i q)) (getBit i q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_condFlipBit'' | [1003, 1] | [1006, 90] | rcases (getBit i q).dichotomy with hc | hc <;>
simp only [getBit_condFlipBit', hc, Bool.xor_false, Bool.xor_true, cond_true, cond_false] | a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ getBit i ((condFlipBit i c) q) = bif getBit i q then !c (getRes i q) else c (getRes i q) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
i : Fin (a✝ + 1)
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ getBit i ((condFlipBit i c) q) = bif getBit i q then !c (getRes i q) else c (getRes i q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_condFlipBit_of_ne | [1008, 1] | [1013, 45] | rw [condFlipBit_apply] | m : ℕ
c : BV m → Bool
q : BV (m + 1)
i j : Fin (m + 1)
hij : i ≠ j
⊢ getBit i ((condFlipBit j c) q) = getBit i q | m : ℕ
c : BV m → Bool
q : BV (m + 1)
i j : Fin (m + 1)
hij : i ≠ j
⊢ getBit i (bif c (getRes j q) then (flipBit j) q else q) = getBit i q | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
c : BV m → Bool
q : BV (m + 1)
i j : Fin (m + 1)
hij : i ≠ j
⊢ getBit i ((condFlipBit j c) q) = getBit i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_condFlipBit_of_ne | [1008, 1] | [1013, 45] | rcases (c (getRes j q)).dichotomy with (h | h) <;> simp_rw [h] | m : ℕ
c : BV m → Bool
q : BV (m + 1)
i j : Fin (m + 1)
hij : i ≠ j
⊢ getBit i (bif c (getRes j q) then (flipBit j) q else q) = getBit i q | case inl
m : ℕ
c : BV m → Bool
q : BV (m + 1)
i j : Fin (m + 1)
hij : i ≠ j
h : c (getRes j q) = false
⊢ getBit i (bif false then (flipBit j) q else q) = getBit i q
case inr
m : ℕ
c : BV m → Bool
q : BV (m + 1)
i j : Fin (m + 1)
hij : i ≠ j
h : c (getRes j q) = true
⊢ getBit i (bif true then (flipBit j) q else q) = getBit i q | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
c : BV m → Bool
q : BV (m + 1)
i j : Fin (m + 1)
hij : i ≠ j
⊢ getBit i (bif c (getRes j q) then (flipBit j) q else q) = getBit i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_condFlipBit_of_ne | [1008, 1] | [1013, 45] | rw [cond_false] | case inl
m : ℕ
c : BV m → Bool
q : BV (m + 1)
i j : Fin (m + 1)
hij : i ≠ j
h : c (getRes j q) = false
⊢ getBit i (bif false then (flipBit j) q else q) = getBit i q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inl
m : ℕ
c : BV m → Bool
q : BV (m + 1)
i j : Fin (m + 1)
hij : i ≠ j
h : c (getRes j q) = false
⊢ getBit i (bif false then (flipBit j) q else q) = getBit i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | getBit_condFlipBit_of_ne | [1008, 1] | [1013, 45] | rw [cond_true, getBit_flipBit_of_ne hij] | case inr
m : ℕ
c : BV m → Bool
q : BV (m + 1)
i j : Fin (m + 1)
hij : i ≠ j
h : c (getRes j q) = true
⊢ getBit i (bif true then (flipBit j) q else q) = getBit i q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inr
m : ℕ
c : BV m → Bool
q : BV (m + 1)
i j : Fin (m + 1)
hij : i ≠ j
h : c (getRes j q) = true
⊢ getBit i (bif true then (flipBit j) q else q) = getBit i q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_succ_apply | [1018, 1] | [1022, 44] | simp_rw [condFlipBit_apply_eq_mergeBitRes, mergeBitRes_succ, getRes_succ, getBit_succ,
getBit_mergeBitRes, getRes_mergeBitRes] | m : ℕ
c : BV (m + 1) → Bool
q : BV (m + 1 + 1)
i : Fin (m + 1)
⊢ (condFlipBit i.succ c) q =
mergeBitRes 0 (getBit 0 q) ((condFlipBit i fun p => c (mergeBitRes 0 (getBit 0 q) p)) (getRes 0 q)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
c : BV (m + 1) → Bool
q : BV (m + 1 + 1)
i : Fin (m + 1)
⊢ (condFlipBit i.succ c) q =
mergeBitRes 0 (getBit 0 q) ((condFlipBit i fun p => c (mergeBitRes 0 (getBit 0 q) p)) (getRes 0 q))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_succAbove_apply | [1024, 1] | [1030, 23] | simp_rw [condFlipBit_apply, getRes_succAbove,
Bool.apply_cond (fun x => mergeBitRes j (getBit j q) x), mergeBitRes_getBit_getRes,
flipBit_succAbove] | m : ℕ
c : BV (m + 1) → Bool
q : BV (m + 1 + 1)
j : Fin (m + 2)
i : Fin (m + 1)
⊢ (condFlipBit (j.succAbove i) c) q =
mergeBitRes j (getBit j q) ((condFlipBit i fun p => c (mergeBitRes (i.predAbove j) (getBit j q) p)) (getRes j q)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
c : BV (m + 1) → Bool
q : BV (m + 1 + 1)
j : Fin (m + 2)
i : Fin (m + 1)
⊢ (condFlipBit (j.succAbove i) c) q =
mergeBitRes j (getBit j q) ((condFlipBit i fun p => c (mergeBitRes (i.predAbove j) (getBit j q) p)) (getRes j q))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_zero_apply | [1032, 1] | [1036, 58] | rw [condFlipBit_apply, flipBit_zero_apply, getRes_zero] | a✝ : ℕ
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit 0 c) q = bif c q.divNat then finProdFinEquiv (q.divNat, q.modNat.rev) else q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
c : BV a✝ → Bool
q : BV (a✝ + 1)
⊢ (condFlipBit 0 c) q = bif c q.divNat then finProdFinEquiv (q.divNat, q.modNat.rev) else q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_zero_mergeBitRes | [1038, 1] | [1040, 54] | simp_rw [condFlipBit_mergeBitRes, mergeBitRes_zero] | a✝ : ℕ
c : BV a✝ → Bool
b : Bool
p : BV a✝
⊢ (condFlipBit 0 c) (mergeBitRes 0 b p) = finProdFinEquiv (p, bif xor (c p) b then 1 else 0) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
c : BV a✝ → Bool
b : Bool
p : BV a✝
⊢ (condFlipBit 0 c) (mergeBitRes 0 b p) = finProdFinEquiv (p, bif xor (c p) b then 1 else 0)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_zero_mergeBitRes_true | [1042, 1] | [1044, 71] | simp_rw [condFlipBit_zero_mergeBitRes, Bool.xor_true, Bool.cond_not] | a✝ : ℕ
c : BV a✝ → Bool
p : BV a✝
⊢ (condFlipBit 0 c) (mergeBitRes 0 true p) = finProdFinEquiv (p, bif c p then 0 else 1) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
c : BV a✝ → Bool
p : BV a✝
⊢ (condFlipBit 0 c) (mergeBitRes 0 true p) = finProdFinEquiv (p, bif c p then 0 else 1)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | condFlipBit_zero_mergeBitRes_false | [1046, 1] | [1048, 57] | simp_rw [condFlipBit_zero_mergeBitRes, Bool.xor_false] | a✝ : ℕ
c : BV a✝ → Bool
p : BV a✝
⊢ (condFlipBit 0 c) (mergeBitRes 0 false p) = finProdFinEquiv (p, bif c p then 1 else 0) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
a✝ : ℕ
c : BV a✝ → Bool
p : BV a✝
⊢ (condFlipBit 0 c) (mergeBitRes 0 false p) = finProdFinEquiv (p, bif c p then 1 else 0)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/BitResiduum.lean | bitInvarMulEquiv_last_apply_condFlipBits | [1069, 1] | [1073, 100] | rw [← Fin.predAbove_right_last (i := i), bitInvarMulEquiv_apply_condFlipBits, Fin.succAbove_last] | m : ℕ
c : BV (m + 1) → Bool
i : Fin (m + 1)
⊢ ↑((bitInvarMulEquiv (Fin.last (m + 1))) fun b => condFlipBit i fun p => c (mergeBitRes (Fin.last m) b p)) =
condFlipBit i.castSucc c | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
c : BV (m + 1) → Bool
i : Fin (m + 1)
⊢ ↑((bitInvarMulEquiv (Fin.last (m + 1))) fun b => condFlipBit i fun p => c (mergeBitRes (Fin.last m) b p)) =
condFlipBit i.castSucc c
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_inv_mul_eq_mul_inv_cmtr | [13, 1] | [14, 75] | simp_rw [commutatorElement_inv, commutatorElement_def, inv_inv, mul_assoc] | G : Type u
inst✝ : Group G
x y : G
⊢ ⁅x, y⁆⁻¹ * y = y * ⁅x, y⁻¹⁆ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
G : Type u
inst✝ : Group G
x y : G
⊢ ⁅x, y⁆⁻¹ * y = y * ⁅x, y⁻¹⁆
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_mul_eq_mul_inv_cmtr_inv | [16, 1] | [18, 43] | simp_rw [commutatorElement_inv, commutatorElement_def, inv_mul_cancel_right,
mul_assoc, mul_inv_cancel_left, inv_inv] | G : Type u
inst✝ : Group G
x y : G
⊢ ⁅x, y⁆ * y = y * ⁅x, y⁻¹⁆⁻¹ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
G : Type u
inst✝ : Group G
x y : G
⊢ ⁅x, y⁆ * y = y * ⁅x, y⁻¹⁆⁻¹
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_pow_inv_mul_eq_mul_inv_cmtr_pow | [20, 1] | [24, 34] | induction' k with n hn | G : Type u
inst✝ : Group G
x y : G
k : ℕ
⊢ (⁅x, y⁆ ^ k)⁻¹ * y = y * ⁅x, y⁻¹⁆ ^ k | case zero
G : Type u
inst✝ : Group G
x y : G
⊢ (⁅x, y⁆ ^ 0)⁻¹ * y = y * ⁅x, y⁻¹⁆ ^ 0
case succ
G : Type u
inst✝ : Group G
x y : G
n : ℕ
hn : (⁅x, y⁆ ^ n)⁻¹ * y = y * ⁅x, y⁻¹⁆ ^ n
⊢ (⁅x, y⁆ ^ (n + 1))⁻¹ * y = y * ⁅x, y⁻¹⁆ ^ (n + 1) | Please generate a tactic in lean4 to solve the state.
STATE:
G : Type u
inst✝ : Group G
x y : G
k : ℕ
⊢ (⁅x, y⁆ ^ k)⁻¹ * y = y * ⁅x, y⁻¹⁆ ^ k
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_pow_inv_mul_eq_mul_inv_cmtr_pow | [20, 1] | [24, 34] | simp_rw [pow_zero, inv_one, mul_one, one_mul] | case zero
G : Type u
inst✝ : Group G
x y : G
⊢ (⁅x, y⁆ ^ 0)⁻¹ * y = y * ⁅x, y⁻¹⁆ ^ 0 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case zero
G : Type u
inst✝ : Group G
x y : G
⊢ (⁅x, y⁆ ^ 0)⁻¹ * y = y * ⁅x, y⁻¹⁆ ^ 0
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_pow_inv_mul_eq_mul_inv_cmtr_pow | [20, 1] | [24, 34] | simp_rw [pow_succ ⁅x, y⁻¹⁆, pow_succ' ⁅x, y⁆, ← mul_assoc, hn.symm, mul_inv_rev, mul_assoc,
cmtr_inv_mul_eq_mul_inv_cmtr] | case succ
G : Type u
inst✝ : Group G
x y : G
n : ℕ
hn : (⁅x, y⁆ ^ n)⁻¹ * y = y * ⁅x, y⁻¹⁆ ^ n
⊢ (⁅x, y⁆ ^ (n + 1))⁻¹ * y = y * ⁅x, y⁻¹⁆ ^ (n + 1) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case succ
G : Type u
inst✝ : Group G
x y : G
n : ℕ
hn : (⁅x, y⁆ ^ n)⁻¹ * y = y * ⁅x, y⁻¹⁆ ^ n
⊢ (⁅x, y⁆ ^ (n + 1))⁻¹ * y = y * ⁅x, y⁻¹⁆ ^ (n + 1)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | pow_mul_eq_mul_inv_cmtr_pow_inv | [26, 1] | [28, 99] | rw [eq_mul_inv_iff_mul_eq, mul_assoc, ← cmtr_pow_inv_mul_eq_mul_inv_cmtr_pow, mul_inv_cancel_left] | G : Type u
inst✝ : Group G
x y : G
k : ℕ
⊢ ⁅x, y⁆ ^ k * y = y * (⁅x, y⁻¹⁆ ^ k)⁻¹ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
G : Type u
inst✝ : Group G
x y : G
k : ℕ
⊢ ⁅x, y⁆ ^ k * y = y * (⁅x, y⁻¹⁆ ^ k)⁻¹
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_zpow_inv_mul_eq_mul_inv_cmtr_zpow | [30, 1] | [33, 79] | cases k | G : Type u
inst✝ : Group G
x y : G
k : ℤ
⊢ (⁅x, y⁆ ^ k)⁻¹ * y = y * ⁅x, y⁻¹⁆ ^ k | case ofNat
G : Type u
inst✝ : Group G
x y : G
a✝ : ℕ
⊢ (⁅x, y⁆ ^ Int.ofNat a✝)⁻¹ * y = y * ⁅x, y⁻¹⁆ ^ Int.ofNat a✝
case negSucc
G : Type u
inst✝ : Group G
x y : G
a✝ : ℕ
⊢ (⁅x, y⁆ ^ Int.negSucc a✝)⁻¹ * y = y * ⁅x, y⁻¹⁆ ^ Int.negSucc a✝ | Please generate a tactic in lean4 to solve the state.
STATE:
G : Type u
inst✝ : Group G
x y : G
k : ℤ
⊢ (⁅x, y⁆ ^ k)⁻¹ * y = y * ⁅x, y⁻¹⁆ ^ k
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_zpow_inv_mul_eq_mul_inv_cmtr_zpow | [30, 1] | [33, 79] | simp only [Int.ofNat_eq_coe, zpow_natCast, zpow_neg, cmtr_pow_inv_mul_eq_mul_inv_cmtr_pow] | case ofNat
G : Type u
inst✝ : Group G
x y : G
a✝ : ℕ
⊢ (⁅x, y⁆ ^ Int.ofNat a✝)⁻¹ * y = y * ⁅x, y⁻¹⁆ ^ Int.ofNat a✝ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case ofNat
G : Type u
inst✝ : Group G
x y : G
a✝ : ℕ
⊢ (⁅x, y⁆ ^ Int.ofNat a✝)⁻¹ * y = y * ⁅x, y⁻¹⁆ ^ Int.ofNat a✝
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_zpow_inv_mul_eq_mul_inv_cmtr_zpow | [30, 1] | [33, 79] | simp only [zpow_negSucc, zpow_neg, inv_inv, pow_mul_eq_mul_inv_cmtr_pow_inv] | case negSucc
G : Type u
inst✝ : Group G
x y : G
a✝ : ℕ
⊢ (⁅x, y⁆ ^ Int.negSucc a✝)⁻¹ * y = y * ⁅x, y⁻¹⁆ ^ Int.negSucc a✝ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case negSucc
G : Type u
inst✝ : Group G
x y : G
a✝ : ℕ
⊢ (⁅x, y⁆ ^ Int.negSucc a✝)⁻¹ * y = y * ⁅x, y⁻¹⁆ ^ Int.negSucc a✝
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_zpow_mul_eq_mul_inv_cmtr_zpow_inv | [35, 1] | [37, 77] | rw [← zpow_neg, ← cmtr_zpow_inv_mul_eq_mul_inv_cmtr_zpow, zpow_neg, inv_inv] | G : Type u
inst✝ : Group G
x y : G
k : ℤ
⊢ ⁅x, y⁆ ^ k * y = y * (⁅x, y⁻¹⁆ ^ k)⁻¹ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
G : Type u
inst✝ : Group G
x y : G
k : ℤ
⊢ ⁅x, y⁆ ^ k * y = y * (⁅x, y⁻¹⁆ ^ k)⁻¹
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_inv_eq_cmtr_iff_cmtr_square_id | [39, 1] | [43, 36] | simp_rw [pow_two, commutatorElement_eq_one_iff_mul_comm, eq_comm (a := (x * (y * y))),
commutatorElement_def, mul_assoc, mul_left_cancel_iff, ← inv_mul_eq_one (a := y * (x⁻¹ * y⁻¹)),
mul_eq_one_iff_eq_inv, mul_inv_rev, inv_inv, mul_assoc, ← eq_inv_mul_iff_mul_eq (b := y),
mul_inv_eq_iff_eq_mul, mul_assoc] | G : Type u
inst✝ : Group G
x y : G
⊢ ⁅x, y⁆ = ⁅x, y⁻¹⁆ ↔ ⁅x, y ^ 2⁆ = 1 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
G : Type u
inst✝ : Group G
x y : G
⊢ ⁅x, y⁆ = ⁅x, y⁻¹⁆ ↔ ⁅x, y ^ 2⁆ = 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | mul_cmtr_unfix_of_unfix | [57, 1] | [61, 34] | simp_rw [Perm.mul_apply, cmtr_apply,
← Perm.eq_inv_iff_eq (f := y).not, ← Perm.eq_inv_iff_eq (f := x).not] | α : Type u
x y : Perm α
q : α
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (y * ⁅x, y⁆) q ≠ q | α : Type u
x y : Perm α
q : α
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), ¬y (x⁻¹ (y⁻¹ q)) = x⁻¹ (y⁻¹ q) | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
x y : Perm α
q : α
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (y * ⁅x, y⁆) q ≠ q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | mul_cmtr_unfix_of_unfix | [57, 1] | [61, 34] | exact fun q => hy (x⁻¹ (y⁻¹ q)) | α : Type u
x y : Perm α
q : α
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), ¬y (x⁻¹ (y⁻¹ q)) = x⁻¹ (y⁻¹ q) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
x y : Perm α
q : α
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), ¬y (x⁻¹ (y⁻¹ q)) = x⁻¹ (y⁻¹ q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_mul_unfix_of_unfix | [63, 1] | [66, 28] | simp_rw [Perm.mul_apply, cmtr_apply, Perm.inv_apply_self, ← Perm.eq_inv_iff_eq (f := x).not] | α : Type u
x y : Perm α
q : α
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (⁅x, y⁆ * y) q ≠ q | α : Type u
x y : Perm α
q : α
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), ¬y (x⁻¹ q) = x⁻¹ q | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
x y : Perm α
q : α
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (⁅x, y⁆ * y) q ≠ q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_mul_unfix_of_unfix | [63, 1] | [66, 28] | exact fun q => hy (x⁻¹ q) | α : Type u
x y : Perm α
q : α
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), ¬y (x⁻¹ q) = x⁻¹ q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
x y : Perm α
q : α
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), ¬y (x⁻¹ q) = x⁻¹ q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | mul_inv_cmtr_inv_unfix_of_unfix | [68, 1] | [71, 35] | simp_rw [← cmtr_mul_eq_mul_inv_cmtr_inv] | α : Type u
x y : Perm α
q : α
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (y * ⁅x, y⁻¹⁆⁻¹) q ≠ q | α : Type u
x y : Perm α
q : α
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (⁅x, y⁆ * y) q ≠ q | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
x y : Perm α
q : α
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (y * ⁅x, y⁻¹⁆⁻¹) q ≠ q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | mul_inv_cmtr_inv_unfix_of_unfix | [68, 1] | [71, 35] | exact cmtr_mul_unfix_of_unfix hy | α : Type u
x y : Perm α
q : α
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (⁅x, y⁆ * y) q ≠ q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
x y : Perm α
q : α
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (⁅x, y⁆ * y) q ≠ q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_inv_apply_ne_apply_of_unfix | [73, 1] | [77, 56] | simp_rw [Perm.inv_eq_iff_eq.not] | α : Type u
x y : Perm α
q : α
hy : ∀ (q : α), y q ≠ q
⊢ ⁅x, y⁆⁻¹ q ≠ y q | α : Type u
x y : Perm α
q : α
hy : ∀ (q : α), y q ≠ q
⊢ ¬q = ⁅x, y⁆ (y q) | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
x y : Perm α
q : α
hy : ∀ (q : α), y q ≠ q
⊢ ⁅x, y⁆⁻¹ q ≠ y q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_inv_apply_ne_apply_of_unfix | [73, 1] | [77, 56] | exact Ne.symm (cmtr_mul_unfix_of_unfix (x := x) hy q) | α : Type u
x y : Perm α
q : α
hy : ∀ (q : α), y q ≠ q
⊢ ¬q = ⁅x, y⁆ (y q) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
x y : Perm α
q : α
hy : ∀ (q : α), y q ≠ q
⊢ ¬q = ⁅x, y⁆ (y q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | mul_cmtr_pow_unfix | [79, 1] | [90, 26] | induction' k using Nat.twoStepInduction with k IH | α : Type u
x y : Perm α
q : α
k : ℕ
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (y * ⁅x, y⁆ ^ k) q ≠ q | case H1
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (y * ⁅x, y⁆ ^ 0) q ≠ q
case H2
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (y * ⁅x, y⁆ ^ 1) q ≠ q
case H3
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
k : ℕ
IH : ∀ (q : α), (y * ⁅x, y⁆ ^ k) q ≠ q
_IH2✝ : ∀ (q : α), (y * ⁅x, y⁆ ^ k.succ) q ≠ q
⊢ ∀ (q : α), (y * ⁅x, y⁆ ^ k.succ.succ) q ≠ q | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
x y : Perm α
q : α
k : ℕ
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (y * ⁅x, y⁆ ^ k) q ≠ q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | mul_cmtr_pow_unfix | [79, 1] | [90, 26] | rw [pow_zero, mul_one] | case H1
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (y * ⁅x, y⁆ ^ 0) q ≠ q | case H1
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), y q ≠ q | Please generate a tactic in lean4 to solve the state.
STATE:
case H1
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (y * ⁅x, y⁆ ^ 0) q ≠ q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | mul_cmtr_pow_unfix | [79, 1] | [90, 26] | exact hy | case H1
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), y q ≠ q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case H1
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), y q ≠ q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | mul_cmtr_pow_unfix | [79, 1] | [90, 26] | rw [pow_one] | case H2
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (y * ⁅x, y⁆ ^ 1) q ≠ q | case H2
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (y * ⁅x, y⁆) q ≠ q | Please generate a tactic in lean4 to solve the state.
STATE:
case H2
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (y * ⁅x, y⁆ ^ 1) q ≠ q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | mul_cmtr_pow_unfix | [79, 1] | [90, 26] | exact mul_cmtr_unfix_of_unfix hy | case H2
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (y * ⁅x, y⁆) q ≠ q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case H2
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (y * ⁅x, y⁆) q ≠ q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | mul_cmtr_pow_unfix | [79, 1] | [90, 26] | intros q h | case H3
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
k : ℕ
IH : ∀ (q : α), (y * ⁅x, y⁆ ^ k) q ≠ q
_IH2✝ : ∀ (q : α), (y * ⁅x, y⁆ ^ k.succ) q ≠ q
⊢ ∀ (q : α), (y * ⁅x, y⁆ ^ k.succ.succ) q ≠ q | case H3
α : Type u
x y : Perm α
q✝ : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
k : ℕ
IH : ∀ (q : α), (y * ⁅x, y⁆ ^ k) q ≠ q
_IH2✝ : ∀ (q : α), (y * ⁅x, y⁆ ^ k.succ) q ≠ q
q : α
h : (y * ⁅x, y⁆ ^ k.succ.succ) q = q
⊢ False | Please generate a tactic in lean4 to solve the state.
STATE:
case H3
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
k : ℕ
IH : ∀ (q : α), (y * ⁅x, y⁆ ^ k) q ≠ q
_IH2✝ : ∀ (q : α), (y * ⁅x, y⁆ ^ k.succ) q ≠ q
⊢ ∀ (q : α), (y * ⁅x, y⁆ ^ k.succ.succ) q ≠ q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | mul_cmtr_pow_unfix | [79, 1] | [90, 26] | simp_rw [pow_succ (n := k.succ), pow_succ' (n := k), ← mul_assoc, ← hxy,
← cmtr_inv_mul_eq_mul_inv_cmtr, hxy, mul_assoc,
Perm.mul_apply, Perm.inv_eq_iff_eq] at h | case H3
α : Type u
x y : Perm α
q✝ : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
k : ℕ
IH : ∀ (q : α), (y * ⁅x, y⁆ ^ k) q ≠ q
_IH2✝ : ∀ (q : α), (y * ⁅x, y⁆ ^ k.succ) q ≠ q
q : α
h : (y * ⁅x, y⁆ ^ k.succ.succ) q = q
⊢ False | case H3
α : Type u
x y : Perm α
q✝ : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
k : ℕ
IH : ∀ (q : α), (y * ⁅x, y⁆ ^ k) q ≠ q
_IH2✝ : ∀ (q : α), (y * ⁅x, y⁆ ^ k.succ) q ≠ q
q : α
h : y ((⁅x, y⁆ ^ k) (⁅x, y⁆ q)) = ⁅x, y⁆ q
⊢ False | Please generate a tactic in lean4 to solve the state.
STATE:
case H3
α : Type u
x y : Perm α
q✝ : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
k : ℕ
IH : ∀ (q : α), (y * ⁅x, y⁆ ^ k) q ≠ q
_IH2✝ : ∀ (q : α), (y * ⁅x, y⁆ ^ k.succ) q ≠ q
q : α
h : (y * ⁅x, y⁆ ^ k.succ.succ) q = q
⊢ False
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | mul_cmtr_pow_unfix | [79, 1] | [90, 26] | exact IH (⁅x, y⁆ q) h | case H3
α : Type u
x y : Perm α
q✝ : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
k : ℕ
IH : ∀ (q : α), (y * ⁅x, y⁆ ^ k) q ≠ q
_IH2✝ : ∀ (q : α), (y * ⁅x, y⁆ ^ k.succ) q ≠ q
q : α
h : y ((⁅x, y⁆ ^ k) (⁅x, y⁆ q)) = ⁅x, y⁆ q
⊢ False | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case H3
α : Type u
x y : Perm α
q✝ : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
k : ℕ
IH : ∀ (q : α), (y * ⁅x, y⁆ ^ k) q ≠ q
_IH2✝ : ∀ (q : α), (y * ⁅x, y⁆ ^ k.succ) q ≠ q
q : α
h : y ((⁅x, y⁆ ^ k) (⁅x, y⁆ q)) = ⁅x, y⁆ q
⊢ False
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_pow_apply_ne_apply | [92, 1] | [95, 46] | simp_rw [← Perm.eq_inv_iff_eq.not, ← Perm.mul_apply, cmtr_pow_inv_mul_eq_mul_inv_cmtr_pow, hxy] | α : Type u
x y : Perm α
q : α
k : ℕ
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (⁅x, y⁆ ^ k) q ≠ y q | α : Type u
x y : Perm α
q : α
k : ℕ
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ¬q = (y * ⁅x, y⁆ ^ k) q | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
x y : Perm α
q : α
k : ℕ
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (⁅x, y⁆ ^ k) q ≠ y q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_pow_apply_ne_apply | [92, 1] | [95, 46] | exact Ne.symm (mul_cmtr_pow_unfix hxy hy _) | α : Type u
x y : Perm α
q : α
k : ℕ
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ¬q = (y * ⁅x, y⁆ ^ k) q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
x y : Perm α
q : α
k : ℕ
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ¬q = (y * ⁅x, y⁆ ^ k) q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_pow_mul_unfix | [97, 1] | [109, 28] | induction' k using Nat.twoStepInduction with k IH | α : Type u
x y : Perm α
q : α
k : ℕ
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (⁅x, y⁆ ^ k * y) q ≠ q | case H1
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (⁅x, y⁆ ^ 0 * y) q ≠ q
case H2
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (⁅x, y⁆ ^ 1 * y) q ≠ q
case H3
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
k : ℕ
IH : ∀ (q : α), (⁅x, y⁆ ^ k * y) q ≠ q
_IH2✝ : ∀ (q : α), (⁅x, y⁆ ^ k.succ * y) q ≠ q
⊢ ∀ (q : α), (⁅x, y⁆ ^ k.succ.succ * y) q ≠ q | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
x y : Perm α
q : α
k : ℕ
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (⁅x, y⁆ ^ k * y) q ≠ q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_pow_mul_unfix | [97, 1] | [109, 28] | rw [pow_zero, one_mul] | case H1
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (⁅x, y⁆ ^ 0 * y) q ≠ q | case H1
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), y q ≠ q | Please generate a tactic in lean4 to solve the state.
STATE:
case H1
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (⁅x, y⁆ ^ 0 * y) q ≠ q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_pow_mul_unfix | [97, 1] | [109, 28] | exact hy | case H1
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), y q ≠ q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case H1
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), y q ≠ q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_pow_mul_unfix | [97, 1] | [109, 28] | rw [pow_one] | case H2
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (⁅x, y⁆ ^ 1 * y) q ≠ q | case H2
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (⁅x, y⁆ * y) q ≠ q | Please generate a tactic in lean4 to solve the state.
STATE:
case H2
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (⁅x, y⁆ ^ 1 * y) q ≠ q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_pow_mul_unfix | [97, 1] | [109, 28] | exact cmtr_mul_unfix_of_unfix hy | case H2
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (⁅x, y⁆ * y) q ≠ q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case H2
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (q : α), (⁅x, y⁆ * y) q ≠ q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_pow_mul_unfix | [97, 1] | [109, 28] | intros q h | case H3
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
k : ℕ
IH : ∀ (q : α), (⁅x, y⁆ ^ k * y) q ≠ q
_IH2✝ : ∀ (q : α), (⁅x, y⁆ ^ k.succ * y) q ≠ q
⊢ ∀ (q : α), (⁅x, y⁆ ^ k.succ.succ * y) q ≠ q | case H3
α : Type u
x y : Perm α
q✝ : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
k : ℕ
IH : ∀ (q : α), (⁅x, y⁆ ^ k * y) q ≠ q
_IH2✝ : ∀ (q : α), (⁅x, y⁆ ^ k.succ * y) q ≠ q
q : α
h : (⁅x, y⁆ ^ k.succ.succ * y) q = q
⊢ False | Please generate a tactic in lean4 to solve the state.
STATE:
case H3
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
k : ℕ
IH : ∀ (q : α), (⁅x, y⁆ ^ k * y) q ≠ q
_IH2✝ : ∀ (q : α), (⁅x, y⁆ ^ k.succ * y) q ≠ q
⊢ ∀ (q : α), (⁅x, y⁆ ^ k.succ.succ * y) q ≠ q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_pow_mul_unfix | [97, 1] | [109, 28] | simp_rw [pow_succ (n := k.succ), pow_succ' (n := k), mul_assoc,
cmtr_mul_eq_mul_inv_cmtr_inv, hxy, Perm.mul_apply,
← Perm.eq_inv_iff_eq (f := ⁅x, y⁆)] at h | case H3
α : Type u
x y : Perm α
q✝ : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
k : ℕ
IH : ∀ (q : α), (⁅x, y⁆ ^ k * y) q ≠ q
_IH2✝ : ∀ (q : α), (⁅x, y⁆ ^ k.succ * y) q ≠ q
q : α
h : (⁅x, y⁆ ^ k.succ.succ * y) q = q
⊢ False | case H3
α : Type u
x y : Perm α
q✝ : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
k : ℕ
IH : ∀ (q : α), (⁅x, y⁆ ^ k * y) q ≠ q
_IH2✝ : ∀ (q : α), (⁅x, y⁆ ^ k.succ * y) q ≠ q
q : α
h : (⁅x, y⁆ ^ k) (y (⁅x, y⁆⁻¹ q)) = ⁅x, y⁆⁻¹ q
⊢ False | Please generate a tactic in lean4 to solve the state.
STATE:
case H3
α : Type u
x y : Perm α
q✝ : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
k : ℕ
IH : ∀ (q : α), (⁅x, y⁆ ^ k * y) q ≠ q
_IH2✝ : ∀ (q : α), (⁅x, y⁆ ^ k.succ * y) q ≠ q
q : α
h : (⁅x, y⁆ ^ k.succ.succ * y) q = q
⊢ False
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_pow_mul_unfix | [97, 1] | [109, 28] | exact IH (⁅x, y⁆⁻¹ q) h | case H3
α : Type u
x y : Perm α
q✝ : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
k : ℕ
IH : ∀ (q : α), (⁅x, y⁆ ^ k * y) q ≠ q
_IH2✝ : ∀ (q : α), (⁅x, y⁆ ^ k.succ * y) q ≠ q
q : α
h : (⁅x, y⁆ ^ k) (y (⁅x, y⁆⁻¹ q)) = ⁅x, y⁆⁻¹ q
⊢ False | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case H3
α : Type u
x y : Perm α
q✝ : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
k : ℕ
IH : ∀ (q : α), (⁅x, y⁆ ^ k * y) q ≠ q
_IH2✝ : ∀ (q : α), (⁅x, y⁆ ^ k.succ * y) q ≠ q
q : α
h : (⁅x, y⁆ ^ k) (y (⁅x, y⁆⁻¹ q)) = ⁅x, y⁆⁻¹ q
⊢ False
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_pow_inv_apply_ne_apply | [111, 1] | [114, 46] | simp_rw [Perm.inv_eq_iff_eq.not] | α : Type u
x y : Perm α
q : α
k : ℕ
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (⁅x, y⁆ ^ k)⁻¹ q ≠ y q | α : Type u
x y : Perm α
q : α
k : ℕ
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ¬q = (⁅x, y⁆ ^ k) (y q) | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
x y : Perm α
q : α
k : ℕ
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (⁅x, y⁆ ^ k)⁻¹ q ≠ y q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_pow_inv_apply_ne_apply | [111, 1] | [114, 46] | exact Ne.symm (cmtr_pow_mul_unfix hxy hy _) | α : Type u
x y : Perm α
q : α
k : ℕ
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ¬q = (⁅x, y⁆ ^ k) (y q) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
x y : Perm α
q : α
k : ℕ
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ¬q = (⁅x, y⁆ ^ k) (y q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_zpow_apply_ne_apply | [116, 1] | [122, 35] | cases k | α : Type u
x y : Perm α
q : α
k : ℤ
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (⁅x, y⁆ ^ k) q ≠ y q | case ofNat
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
a✝ : ℕ
⊢ (⁅x, y⁆ ^ Int.ofNat a✝) q ≠ y q
case negSucc
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
a✝ : ℕ
⊢ (⁅x, y⁆ ^ Int.negSucc a✝) q ≠ y q | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
x y : Perm α
q : α
k : ℤ
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (⁅x, y⁆ ^ k) q ≠ y q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_zpow_apply_ne_apply | [116, 1] | [122, 35] | simp only [Int.ofNat_eq_coe, zpow_natCast, ne_eq, hxy, hy, not_false_eq_true, implies_true,
cmtr_pow_apply_ne_apply] | case ofNat
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
a✝ : ℕ
⊢ (⁅x, y⁆ ^ Int.ofNat a✝) q ≠ y q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case ofNat
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
a✝ : ℕ
⊢ (⁅x, y⁆ ^ Int.ofNat a✝) q ≠ y q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_zpow_apply_ne_apply | [116, 1] | [122, 35] | simp only [zpow_negSucc, ne_eq, hxy, hy, not_false_eq_true, implies_true,
cmtr_pow_inv_apply_ne_apply] | case negSucc
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
a✝ : ℕ
⊢ (⁅x, y⁆ ^ Int.negSucc a✝) q ≠ y q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case negSucc
α : Type u
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
a✝ : ℕ
⊢ (⁅x, y⁆ ^ Int.negSucc a✝) q ≠ y q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_zpow_apply_ne_apply_cmtr_pow_apply | [124, 1] | [127, 40] | rw [← sub_add_cancel j k, zpow_add, Perm.mul_apply] | α : Type u
x y : Perm α
q : α
j k : ℤ
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (⁅x, y⁆ ^ j) q ≠ y ((⁅x, y⁆ ^ k) q) | α : Type u
x y : Perm α
q : α
j k : ℤ
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (⁅x, y⁆ ^ (j - k)) ((⁅x, y⁆ ^ k) q) ≠ y ((⁅x, y⁆ ^ k) q) | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
x y : Perm α
q : α
j k : ℤ
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (⁅x, y⁆ ^ j) q ≠ y ((⁅x, y⁆ ^ k) q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Commutator.lean | cmtr_zpow_apply_ne_apply_cmtr_pow_apply | [124, 1] | [127, 40] | exact cmtr_zpow_apply_ne_apply hxy hy | α : Type u
x y : Perm α
q : α
j k : ℤ
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (⁅x, y⁆ ^ (j - k)) ((⁅x, y⁆ ^ k) q) ≠ y ((⁅x, y⁆ ^ k) q) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
x y : Perm α
q : α
j k : ℤ
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (⁅x, y⁆ ^ (j - k)) ((⁅x, y⁆ ^ k) q) ≠ y ((⁅x, y⁆ ^ k) q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.isLeft_eq_of_liftRel_inl_right | [8, 1] | [10, 17] | cases h | α : Type u
β : Type v
α✝ : Type u_1
γ✝ : Type u_2
ra : α✝ → γ✝ → Prop
β✝ : Type u_3
δ✝ : Type u_4
rb : β✝ → δ✝ → Prop
ab : α✝ ⊕ β✝
c : γ✝
h : LiftRel ra rb ab (inl c)
⊢ ab.isLeft = true | case inl
α : Type u
β : Type v
α✝ : Type u_1
γ✝ : Type u_2
ra : α✝ → γ✝ → Prop
β✝ : Type u_3
δ✝ : Type u_4
rb : β✝ → δ✝ → Prop
c : γ✝
a✝¹ : α✝
a✝ : ra a✝¹ c
⊢ (inl a✝¹).isLeft = true | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
β : Type v
α✝ : Type u_1
γ✝ : Type u_2
ra : α✝ → γ✝ → Prop
β✝ : Type u_3
δ✝ : Type u_4
rb : β✝ → δ✝ → Prop
ab : α✝ ⊕ β✝
c : γ✝
h : LiftRel ra rb ab (inl c)
⊢ ab.isLeft = true
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.isLeft_eq_of_liftRel_inl_right | [8, 1] | [10, 17] | simp | case inl
α : Type u
β : Type v
α✝ : Type u_1
γ✝ : Type u_2
ra : α✝ → γ✝ → Prop
β✝ : Type u_3
δ✝ : Type u_4
rb : β✝ → δ✝ → Prop
c : γ✝
a✝¹ : α✝
a✝ : ra a✝¹ c
⊢ (inl a✝¹).isLeft = true | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inl
α : Type u
β : Type v
α✝ : Type u_1
γ✝ : Type u_2
ra : α✝ → γ✝ → Prop
β✝ : Type u_3
δ✝ : Type u_4
rb : β✝ → δ✝ → Prop
c : γ✝
a✝¹ : α✝
a✝ : ra a✝¹ c
⊢ (inl a✝¹).isLeft = true
TACTIC:
|
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