url stringclasses 147
values | commit stringclasses 147
values | file_path stringlengths 7 101 | full_name stringlengths 1 94 | start stringlengths 6 10 | end stringlengths 6 11 | tactic stringlengths 1 11.2k | state_before stringlengths 3 2.09M | state_after stringlengths 6 2.09M | input stringlengths 73 2.09M |
|---|---|---|---|---|---|---|---|---|---|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.isLeft_eq_of_liftRel_inl_left | [12, 1] | [14, 17] | cases h | α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
a : α✝¹
cd : α✝ ⊕ β✝
h : LiftRel ra rb (inl a) cd
⊢ cd.isLeft = true | case inl
α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
a : α✝¹
c✝ : α✝
a✝ : ra a c✝
⊢ (inl c✝).isLeft = true | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
a : α✝¹
cd : α✝ ⊕ β✝
h : LiftRel ra rb (inl a) cd
⊢ cd.isLeft = true
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.isLeft_eq_of_liftRel_inl_left | [12, 1] | [14, 17] | simp | case inl
α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
a : α✝¹
c✝ : α✝
a✝ : ra a c✝
⊢ (inl c✝).isLeft = true | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inl
α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
a : α✝¹
c✝ : α✝
a✝ : ra a c✝
⊢ (inl c✝).isLeft = true
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.isLeft_eq_of_liftRel | [16, 1] | [17, 19] | cases h <;> simp | α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
ab : α✝¹ ⊕ β✝¹
cd : α✝ ⊕ β✝
h : LiftRel ra rb ab cd
⊢ ab.isLeft = cd.isLeft | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
ab : α✝¹ ⊕ β✝¹
cd : α✝ ⊕ β✝
h : LiftRel ra rb ab cd
⊢ ab.isLeft = cd.isLeft
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.isRight_eq_of_liftRel | [19, 1] | [20, 19] | cases h <;> simp | α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
ab : α✝¹ ⊕ β✝¹
cd : α✝ ⊕ β✝
h : LiftRel ra rb ab cd
⊢ ab.isRight = cd.isRight | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
ab : α✝¹ ⊕ β✝¹
cd : α✝ ⊕ β✝
h : LiftRel ra rb ab cd
⊢ ab.isRight = cd.isRight
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.isRight_eq_of_liftRel_inr_left | [22, 1] | [24, 17] | cases h | α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
b : β✝¹
cd : α✝ ⊕ β✝
h : LiftRel ra rb (inr b) cd
⊢ cd.isRight = true | case inr
α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
b : β✝¹
d✝ : β✝
a✝ : rb b d✝
⊢ (inr d✝).isRight = true | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
b : β✝¹
cd : α✝ ⊕ β✝
h : LiftRel ra rb (inr b) cd
⊢ cd.isRight = true
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.isRight_eq_of_liftRel_inr_left | [22, 1] | [24, 17] | simp | case inr
α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
b : β✝¹
d✝ : β✝
a✝ : rb b d✝
⊢ (inr d✝).isRight = true | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inr
α : Type u
β : Type v
α✝¹ : Type u_1
α✝ : Type u_2
ra : α✝¹ → α✝ → Prop
β✝¹ : Type u_3
β✝ : Type u_4
rb : β✝¹ → β✝ → Prop
b : β✝¹
d✝ : β✝
a✝ : rb b d✝
⊢ (inr d✝).isRight = true
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.isRight_eq_of_liftRel_inr_right | [26, 1] | [28, 17] | cases h | α : Type u
β : Type v
α✝ : Type u_1
γ✝ : Type u_2
ra : α✝ → γ✝ → Prop
β✝ : Type u_3
δ✝ : Type u_4
rb : β✝ → δ✝ → Prop
ab : α✝ ⊕ β✝
d : δ✝
h : LiftRel ra rb ab (inr d)
⊢ ab.isRight = true | case inr
α : Type u
β : Type v
α✝ : Type u_1
γ✝ : Type u_2
ra : α✝ → γ✝ → Prop
β✝ : Type u_3
δ✝ : Type u_4
rb : β✝ → δ✝ → Prop
d : δ✝
b✝ : β✝
a✝ : rb b✝ d
⊢ (inr b✝).isRight = true | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
β : Type v
α✝ : Type u_1
γ✝ : Type u_2
ra : α✝ → γ✝ → Prop
β✝ : Type u_3
δ✝ : Type u_4
rb : β✝ → δ✝ → Prop
ab : α✝ ⊕ β✝
d : δ✝
h : LiftRel ra rb ab (inr d)
⊢ ab.isRight = true
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.isRight_eq_of_liftRel_inr_right | [26, 1] | [28, 17] | simp | case inr
α : Type u
β : Type v
α✝ : Type u_1
γ✝ : Type u_2
ra : α✝ → γ✝ → Prop
β✝ : Type u_3
δ✝ : Type u_4
rb : β✝ → δ✝ → Prop
d : δ✝
b✝ : β✝
a✝ : rb b✝ d
⊢ (inr b✝).isRight = true | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inr
α : Type u
β : Type v
α✝ : Type u_1
γ✝ : Type u_2
ra : α✝ → γ✝ → Prop
β✝ : Type u_3
δ✝ : Type u_4
rb : β✝ → δ✝ → Prop
d : δ✝
b✝ : β✝
a✝ : rb b✝ d
⊢ (inr b✝).isRight = true
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.liftRel_equiv_left_iff_symm_right | [30, 1] | [33, 71] | convert (H (e.symm cd)) | α : Type u
β : Type v
α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
H : ∀ (ab : α₁ ⊕ β₁), LiftRel ra rb (e ab) ab
cd : α₂ ⊕ β₂
⊢ LiftRel ra rb cd (e.symm cd) | case h.e'_7
α : Type u
β : Type v
α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
H : ∀ (ab : α₁ ⊕ β₁), LiftRel ra rb (e ab) ab
cd : α₂ ⊕ β₂
⊢ cd = e (e.symm cd) | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
β : Type v
α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
H : ∀ (ab : α₁ ⊕ β₁), LiftRel ra rb (e ab) ab
cd : α₂ ⊕ β₂
⊢ LiftRel ra rb cd (e.symm cd)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.liftRel_equiv_left_iff_symm_right | [30, 1] | [33, 71] | exact (e.apply_symm_apply _).symm | case h.e'_7
α : Type u
β : Type v
α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
H : ∀ (ab : α₁ ⊕ β₁), LiftRel ra rb (e ab) ab
cd : α₂ ⊕ β₂
⊢ cd = e (e.symm cd) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case h.e'_7
α : Type u
β : Type v
α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
H : ∀ (ab : α₁ ⊕ β₁), LiftRel ra rb (e ab) ab
cd : α₂ ⊕ β₂
⊢ cd = e (e.symm cd)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.liftRel_equiv_left_iff_symm_right | [30, 1] | [33, 71] | convert (H (e ab)) | α : Type u
β : Type v
α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
H : ∀ (cd : α₂ ⊕ β₂), LiftRel ra rb cd (e.symm cd)
ab : α₁ ⊕ β₁
⊢ LiftRel ra rb (e ab) ab | case h.e'_8
α : Type u
β : Type v
α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
H : ∀ (cd : α₂ ⊕ β₂), LiftRel ra rb cd (e.symm cd)
ab : α₁ ⊕ β₁
⊢ ab = e.symm (e ab) | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
β : Type v
α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
H : ∀ (cd : α₂ ⊕ β₂), LiftRel ra rb cd (e.symm cd)
ab : α₁ ⊕ β₁
⊢ LiftRel ra rb (e ab) ab
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.liftRel_equiv_left_iff_symm_right | [30, 1] | [33, 71] | exact (e.symm_apply_apply _).symm | case h.e'_8
α : Type u
β : Type v
α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
H : ∀ (cd : α₂ ⊕ β₂), LiftRel ra rb cd (e.symm cd)
ab : α₁ ⊕ β₁
⊢ ab = e.symm (e ab) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case h.e'_8
α : Type u
β : Type v
α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
H : ∀ (cd : α₂ ⊕ β₂), LiftRel ra rb cd (e.symm cd)
ab : α₁ ⊕ β₁
⊢ ab = e.symm (e ab)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.liftRel_equiv_right_iff_symm_left | [35, 1] | [37, 70] | convert liftRel_equiv_left_iff_symm_right.symm | α : Type u
β : Type v
α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
ra : α₁ → α₂ → Prop
rb : β₁ → β₂ → Prop
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
⊢ (∀ (ab : α₁ ⊕ β₁), LiftRel ra rb ab (e ab)) ↔ ∀ (cd : α₂ ⊕ β₂), LiftRel ra rb (e.symm cd) cd | case h.e'_1.h.h.e'_8.h.e'_5
α : Type u
β : Type v
α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
ra : α₁ → α₂ → Prop
rb : β₁ → β₂ → Prop
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
a✝ : α₁ ⊕ β₁
⊢ e = e.symm.symm | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
β : Type v
α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
ra : α₁ → α₂ → Prop
rb : β₁ → β₂ → Prop
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
⊢ (∀ (ab : α₁ ⊕ β₁), LiftRel ra rb ab (e ab)) ↔ ∀ (cd : α₂ ⊕ β₂), LiftRel ra rb (e.symm cd) cd
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | Sum.liftRel_equiv_right_iff_symm_left | [35, 1] | [37, 70] | exact e.symm_symm | case h.e'_1.h.h.e'_8.h.e'_5
α : Type u
β : Type v
α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
ra : α₁ → α₂ → Prop
rb : β₁ → β₂ → Prop
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
a✝ : α₁ ⊕ β₁
⊢ e = e.symm.symm | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case h.e'_1.h.h.e'_8.h.e'_5
α : Type u
β : Type v
α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
ra : α₁ → α₂ → Prop
rb : β₁ → β₂ → Prop
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
a✝ : α₁ ⊕ β₁
⊢ e = e.symm.symm
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | equivOfLiftRelToEquivLeft_rel_left | [82, 1] | [85, 21] | simp only [equivOfLiftRelToEquivLeft_apply, ← liftRel_inl_inl (r := ra) (s := rb),
inl_getLeft, he] | α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
he : ∀ (ab : α₁ ⊕ β₁), LiftRel ra rb (e ab) ab
a : α₁
⊢ ra ((equivOfLiftRelToEquivLeft he) a) a | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
he : ∀ (ab : α₁ ⊕ β₁), LiftRel ra rb (e ab) ab
a : α₁
⊢ ra ((equivOfLiftRelToEquivLeft he) a) a
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | equivOfLiftRelToEquivRight_rel_right | [87, 1] | [90, 22] | simp only [equivOfLiftRelToEquivRight_apply, ← liftRel_inr_inr (r := ra) (s := rb),
inr_getRight, he] | α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
he : ∀ (ab : α₁ ⊕ β₁), LiftRel ra rb (e ab) ab
b : β₁
⊢ rb ((equivOfLiftRelToEquivRight he) b) b | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
he : ∀ (ab : α₁ ⊕ β₁), LiftRel ra rb (e ab) ab
b : β₁
⊢ rb ((equivOfLiftRelToEquivRight he) b) b
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | liftRelSumCongr_of_rel_left_rel_right | [92, 1] | [94, 31] | cases ab <;> simp [hea, heb] | α₁ : Type u_2
β₁ : Type u_4
α₂ : Type u_1
β₂ : Type u_3
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
hea : ∀ (a : α₁), ra (ea a) a
heb : ∀ (b : β₁), rb (eb b) b
ab : α₁ ⊕ β₁
⊢ LiftRel ra rb ((ea.sumCongr eb) ab) ab | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α₁ : Type u_2
β₁ : Type u_4
α₂ : Type u_1
β₂ : Type u_3
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
hea : ∀ (a : α₁), ra (ea a) a
heb : ∀ (b : β₁), rb (eb b) b
ab : α₁ ⊕ β₁
⊢ LiftRel ra rb ((ea.sumCongr eb) ab) ab
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | sumCongrEquivLiftRelLeftRight_eq_self | [96, 1] | [98, 34] | ext ab | α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
he : ∀ (ab : α₁ ⊕ β₁), LiftRel ra rb (e ab) ab
⊢ (equivOfLiftRelToEquivLeft he).sumCongr (equivOfLiftRelToEquivRight he) = e | case H
α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
he : ∀ (ab : α₁ ⊕ β₁), LiftRel ra rb (e ab) ab
ab : α₁ ⊕ β₁
⊢ ((equivOfLiftRelToEquivLeft he).sumCongr (equivOfLiftRelToEquivRight he)) ab = e ab | Please generate a tactic in lean4 to solve the state.
STATE:
α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
he : ∀ (ab : α₁ ⊕ β₁), LiftRel ra rb (e ab) ab
⊢ (equivOfLiftRelToEquivLeft he).sumCongr (equivOfLiftRelToEquivRight he) = e
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | sumCongrEquivLiftRelLeftRight_eq_self | [96, 1] | [98, 34] | cases ab <;> simp [he] | case H
α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
he : ∀ (ab : α₁ ⊕ β₁), LiftRel ra rb (e ab) ab
ab : α₁ ⊕ β₁
⊢ ((equivOfLiftRelToEquivLeft he).sumCongr (equivOfLiftRelToEquivRight he)) ab = e ab | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case H
α₁ : Type u_1
β₁ : Type u_2
α₂ : Type u_3
β₂ : Type u_4
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
he : ∀ (ab : α₁ ⊕ β₁), LiftRel ra rb (e ab) ab
ab : α₁ ⊕ β₁
⊢ ((equivOfLiftRelToEquivLeft he).sumCongr (equivOfLiftRelToEquivRight he)) ab = e ab
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | equivIsLeftInvariant_iff_liftRel_top_top | [116, 1] | [122, 83] | simp_rw [Sum.forall, isLeft_inl, isLeft_inr, isLeft_eq_false, isLeft_iff, isRight_iff] | α₁ : Type u_2
β₁ : Type u_1
α₂ : Type u_4
β₂ : Type u_3
e✝ : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
⊢ (∀ (ab : α₁ ⊕ β₁), (e ab).isLeft = ab.isLeft) ↔ ∀ (ab : α₁ ⊕ β₁), LiftRel ⊤ ⊤ (e ab) ab | α₁ : Type u_2
β₁ : Type u_1
α₂ : Type u_4
β₂ : Type u_3
e✝ : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
⊢ ((∀ (a : α₁), ∃ y, e (inl a) = inl y) ∧ ∀ (b : β₁), ∃ y, e (inr b) = inr y) ↔
(∀ (a : α₁), LiftRel ⊤ ⊤ (e (inl a)) (inl a)) ∧ ∀ (b : β₁), LiftRel ⊤ ⊤ (e (inr b)) (inr b) | Please generate a tactic in lean4 to solve the state.
STATE:
α₁ : Type u_2
β₁ : Type u_1
α₂ : Type u_4
β₂ : Type u_3
e✝ : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
⊢ (∀ (ab : α₁ ⊕ β₁), (e ab).isLeft = ab.isLeft) ↔ ∀ (ab : α₁ ⊕ β₁), LiftRel ⊤ ⊤ (e ab) ab
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | equivIsLeftInvariant_iff_liftRel_top_top | [116, 1] | [122, 83] | exact ⟨fun ⟨hA, hB⟩ => ⟨fun a => (hA a).elim (fun _ h => h ▸ LiftRel.inl (trivial)),
fun b => (hB b).elim (fun _ h => h ▸ LiftRel.inr (trivial))⟩,
fun ⟨hA, hB⟩ => ⟨fun a => isLeft_iff.mp (isLeft_eq_of_liftRel (hA a)),
fun b => isRight_iff.mp (isRight_eq_of_liftRel (hB b))⟩⟩ | α₁ : Type u_2
β₁ : Type u_1
α₂ : Type u_4
β₂ : Type u_3
e✝ : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
⊢ ((∀ (a : α₁), ∃ y, e (inl a) = inl y) ∧ ∀ (b : β₁), ∃ y, e (inr b) = inr y) ↔
(∀ (a : α₁), LiftRel ⊤ ⊤ (e (inl a)) (inl a)) ∧ ∀ (b : β₁), LiftRel ⊤ ⊤ (e (inr b)) (inr b) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α₁ : Type u_2
β₁ : Type u_1
α₂ : Type u_4
β₂ : Type u_3
e✝ : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
⊢ ((∀ (a : α₁), ∃ y, e (inl a) = inl y) ∧ ∀ (b : β₁), ∃ y, e (inr b) = inr y) ↔
(∀ (a : α₁), LiftRel ⊤ ⊤ (e (inl a)) (inl a)) ∧ ∀ (b : β₁), LiftRel ⊤ ⊤ (e (inr b)) (inr b)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | equivIsRightInvariant_iff_liftRel_top_top | [124, 1] | [129, 97] | rw [← equivIsLeftInvariant_iff_liftRel_top_top] | α₁ : Type u_2
β₁ : Type u_1
α₂ : Type u_4
β₂ : Type u_3
e✝ : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
⊢ (∀ (ab : α₁ ⊕ β₁), (e ab).isRight = ab.isRight) ↔ ∀ (ab : α₁ ⊕ β₁), LiftRel ⊤ ⊤ (e ab) ab | α₁ : Type u_2
β₁ : Type u_1
α₂ : Type u_4
β₂ : Type u_3
e✝ : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
⊢ (∀ (ab : α₁ ⊕ β₁), (e ab).isRight = ab.isRight) ↔ ∀ (ab : α₁ ⊕ β₁), (e ab).isLeft = ab.isLeft | Please generate a tactic in lean4 to solve the state.
STATE:
α₁ : Type u_2
β₁ : Type u_1
α₂ : Type u_4
β₂ : Type u_3
e✝ : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
⊢ (∀ (ab : α₁ ⊕ β₁), (e ab).isRight = ab.isRight) ↔ ∀ (ab : α₁ ⊕ β₁), LiftRel ⊤ ⊤ (e ab) ab
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | equivIsRightInvariant_iff_liftRel_top_top | [124, 1] | [129, 97] | simp_rw [Sum.forall] | α₁ : Type u_2
β₁ : Type u_1
α₂ : Type u_4
β₂ : Type u_3
e✝ : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
⊢ (∀ (ab : α₁ ⊕ β₁), (e ab).isRight = ab.isRight) ↔ ∀ (ab : α₁ ⊕ β₁), (e ab).isLeft = ab.isLeft | α₁ : Type u_2
β₁ : Type u_1
α₂ : Type u_4
β₂ : Type u_3
e✝ : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
⊢ ((∀ (a : α₁), (e (inl a)).isRight = (inl a).isRight) ∧ ∀ (b : β₁), (e (inr b)).isRight = (inr b).isRight) ↔
(∀ (a : α₁), (e (inl a)).isLeft = (inl a).isLeft) ∧ ∀ (b : β₁), (e (inr b)).isLeft = (inr b).isLeft | Please generate a tactic in lean4 to solve the state.
STATE:
α₁ : Type u_2
β₁ : Type u_1
α₂ : Type u_4
β₂ : Type u_3
e✝ : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
⊢ (∀ (ab : α₁ ⊕ β₁), (e ab).isRight = ab.isRight) ↔ ∀ (ab : α₁ ⊕ β₁), (e ab).isLeft = ab.isLeft
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Extras/isLeft_invariant.lean | equivIsRightInvariant_iff_liftRel_top_top | [124, 1] | [129, 97] | simp_rw [isRight_inl, isRight_eq_false, isRight_inr, isLeft_inl, isLeft_inr, isLeft_eq_false] | α₁ : Type u_2
β₁ : Type u_1
α₂ : Type u_4
β₂ : Type u_3
e✝ : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
⊢ ((∀ (a : α₁), (e (inl a)).isRight = (inl a).isRight) ∧ ∀ (b : β₁), (e (inr b)).isRight = (inr b).isRight) ↔
(∀ (a : α₁), (e (inl a)).isLeft = (inl a).isLeft) ∧ ∀ (b : β₁), (e (inr b)).isLeft = (inr b).isLeft | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α₁ : Type u_2
β₁ : Type u_1
α₂ : Type u_4
β₂ : Type u_3
e✝ : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
ra : α₂ → α₁ → Prop
rb : β₂ → β₁ → Prop
ea : α₁ ≃ α₂
eb : β₁ ≃ β₂
e : α₁ ⊕ β₁ ≃ α₂ ⊕ β₂
⊢ ((∀ (a : α₁), (e (inl a)).isRight = (inl a).isRight) ∧ ∀ (b : β₁), (e (inr b)).isRight = (inr b).isRight) ↔
(∀ (a : α₁), (e (inl a)).isLeft = (inl a).isLeft) ∧ ∀ (b : β₁), (e (inr b)).isLeft = (inr b).isLeft
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/PermFintwo.lean | Fin.perm_fin_two | [6, 1] | [13, 87] | rw [Equiv.ext_iff, forall_fin_two] | π : Equiv.Perm (Fin 2)
⊢ π = if π 0 = 1 then Equiv.swap 0 1 else 1 | π : Equiv.Perm (Fin 2)
⊢ π 0 = (if π 0 = 1 then Equiv.swap 0 1 else 1) 0 ∧ π 1 = (if π 0 = 1 then Equiv.swap 0 1 else 1) 1 | Please generate a tactic in lean4 to solve the state.
STATE:
π : Equiv.Perm (Fin 2)
⊢ π = if π 0 = 1 then Equiv.swap 0 1 else 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/PermFintwo.lean | Fin.perm_fin_two | [6, 1] | [13, 87] | rcases (exists_fin_two.mp ⟨π 0, rfl⟩) with (h0 | h0) <;>
rcases (exists_fin_two.mp ⟨π 1, rfl⟩) with (h1 | h1) <;>
simp only [h0, ite_true, Equiv.swap_apply_left, h1, Equiv.swap_apply_right, one_eq_zero_iff, id_eq,
OfNat.ofNat_ne_one, and_false, zero_eq_one_iff, ite_false, Equiv.Perm.coe_one, and_self] <;>
exact (zero_ne_one ((EmbeddingLike.apply_eq_iff_eq _).mp (h0.trans (h1.symm)))).elim | π : Equiv.Perm (Fin 2)
⊢ π 0 = (if π 0 = 1 then Equiv.swap 0 1 else 1) 0 ∧ π 1 = (if π 0 = 1 then Equiv.swap 0 1 else 1) 1 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
π : Equiv.Perm (Fin 2)
⊢ π 0 = (if π 0 = 1 then Equiv.swap 0 1 else 1) 0 ∧ π 1 = (if π 0 = 1 then Equiv.swap 0 1 else 1) 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/PermFintwo.lean | Fin.perm_fin_two_mul_self | [15, 1] | [19, 17] | rw [perm_fin_two π] | π : Equiv.Perm (Fin 2)
⊢ π * π = 1 | π : Equiv.Perm (Fin 2)
⊢ ((if π 0 = 1 then Equiv.swap 0 1 else 1) * if π 0 = 1 then Equiv.swap 0 1 else 1) = 1 | Please generate a tactic in lean4 to solve the state.
STATE:
π : Equiv.Perm (Fin 2)
⊢ π * π = 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/PermFintwo.lean | Fin.perm_fin_two_mul_self | [15, 1] | [19, 17] | split_ifs | π : Equiv.Perm (Fin 2)
⊢ ((if π 0 = 1 then Equiv.swap 0 1 else 1) * if π 0 = 1 then Equiv.swap 0 1 else 1) = 1 | case pos
π : Equiv.Perm (Fin 2)
h✝ : π 0 = 1
⊢ Equiv.swap 0 1 * Equiv.swap 0 1 = 1
case neg
π : Equiv.Perm (Fin 2)
h✝ : ¬π 0 = 1
⊢ 1 * 1 = 1 | Please generate a tactic in lean4 to solve the state.
STATE:
π : Equiv.Perm (Fin 2)
⊢ ((if π 0 = 1 then Equiv.swap 0 1 else 1) * if π 0 = 1 then Equiv.swap 0 1 else 1) = 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/PermFintwo.lean | Fin.perm_fin_two_mul_self | [15, 1] | [19, 17] | rw [Equiv.swap_mul_self] | case pos
π : Equiv.Perm (Fin 2)
h✝ : π 0 = 1
⊢ Equiv.swap 0 1 * Equiv.swap 0 1 = 1 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case pos
π : Equiv.Perm (Fin 2)
h✝ : π 0 = 1
⊢ Equiv.swap 0 1 * Equiv.swap 0 1 = 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/PermFintwo.lean | Fin.perm_fin_two_mul_self | [15, 1] | [19, 17] | rw [mul_one] | case neg
π : Equiv.Perm (Fin 2)
h✝ : ¬π 0 = 1
⊢ 1 * 1 = 1 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case neg
π : Equiv.Perm (Fin 2)
h✝ : ¬π 0 = 1
⊢ 1 * 1 = 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/PermFintwo.lean | Fin.perm_fin_two_apply_apply | [21, 1] | [22, 75] | rw [← Equiv.Perm.mul_apply, perm_fin_two_mul_self, Equiv.Perm.one_apply] | q : Fin 2
π : Equiv.Perm (Fin 2)
⊢ π (π q) = q | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
q : Fin 2
π : Equiv.Perm (Fin 2)
⊢ π (π q) = q
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/PermFintwo.lean | Fin.perm_fin_two_of_fix_zero | [24, 1] | [26, 62] | rw [perm_fin_two π] | π : Equiv.Perm (Fin 2)
h : π 0 = 0
⊢ π = 1 | π : Equiv.Perm (Fin 2)
h : π 0 = 0
⊢ (if π 0 = 1 then Equiv.swap 0 1 else 1) = 1 | Please generate a tactic in lean4 to solve the state.
STATE:
π : Equiv.Perm (Fin 2)
h : π 0 = 0
⊢ π = 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/PermFintwo.lean | Fin.perm_fin_two_of_fix_zero | [24, 1] | [26, 62] | simp_rw [h, zero_eq_one_iff, OfNat.ofNat_ne_one, ite_false] | π : Equiv.Perm (Fin 2)
h : π 0 = 0
⊢ (if π 0 = 1 then Equiv.swap 0 1 else 1) = 1 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
π : Equiv.Perm (Fin 2)
h : π 0 = 0
⊢ (if π 0 = 1 then Equiv.swap 0 1 else 1) = 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/PermFintwo.lean | Fin.perm_fin_two_of_fix_one | [28, 1] | [30, 92] | rw [perm_fin_two π, ← h] | π : Equiv.Perm (Fin 2)
h : π 1 = 1
⊢ π = 1 | π : Equiv.Perm (Fin 2)
h : π 1 = 1
⊢ (if π 0 = π 1 then Equiv.swap 0 (π 1) else 1) = 1 | Please generate a tactic in lean4 to solve the state.
STATE:
π : Equiv.Perm (Fin 2)
h : π 1 = 1
⊢ π = 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/PermFintwo.lean | Fin.perm_fin_two_of_fix_one | [28, 1] | [30, 92] | simp only [EmbeddingLike.apply_eq_iff_eq, zero_eq_one_iff, OfNat.ofNat_ne_one, ite_false] | π : Equiv.Perm (Fin 2)
h : π 1 = 1
⊢ (if π 0 = π 1 then Equiv.swap 0 (π 1) else 1) = 1 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
π : Equiv.Perm (Fin 2)
h : π 1 = 1
⊢ (if π 0 = π 1 then Equiv.swap 0 (π 1) else 1) = 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/PermFintwo.lean | Fin.perm_fin_two_of_unfix_zero | [32, 1] | [34, 24] | rw [perm_fin_two π] | π : Equiv.Perm (Fin 2)
h : π 0 = 1
⊢ π = Equiv.swap 0 1 | π : Equiv.Perm (Fin 2)
h : π 0 = 1
⊢ (if π 0 = 1 then Equiv.swap 0 1 else 1) = Equiv.swap 0 1 | Please generate a tactic in lean4 to solve the state.
STATE:
π : Equiv.Perm (Fin 2)
h : π 0 = 1
⊢ π = Equiv.swap 0 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/PermFintwo.lean | Fin.perm_fin_two_of_unfix_zero | [32, 1] | [34, 24] | simp_rw [h, ite_true] | π : Equiv.Perm (Fin 2)
h : π 0 = 1
⊢ (if π 0 = 1 then Equiv.swap 0 1 else 1) = Equiv.swap 0 1 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
π : Equiv.Perm (Fin 2)
h : π 0 = 1
⊢ (if π 0 = 1 then Equiv.swap 0 1 else 1) = Equiv.swap 0 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/PermFintwo.lean | Fin.perm_fin_two_of_unfix_one | [36, 1] | [38, 24] | rw [perm_fin_two π, ← perm_fin_two_apply_apply (π := π) (q := 1)] | π : Equiv.Perm (Fin 2)
h : π 1 = 0
⊢ π = Equiv.swap 0 1 | π : Equiv.Perm (Fin 2)
h : π 1 = 0
⊢ (if π 0 = π (π 1) then Equiv.swap 0 (π (π 1)) else 1) = Equiv.swap 0 (π (π 1)) | Please generate a tactic in lean4 to solve the state.
STATE:
π : Equiv.Perm (Fin 2)
h : π 1 = 0
⊢ π = Equiv.swap 0 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/PermFintwo.lean | Fin.perm_fin_two_of_unfix_one | [36, 1] | [38, 24] | simp_rw [h, ite_true] | π : Equiv.Perm (Fin 2)
h : π 1 = 0
⊢ (if π 0 = π (π 1) then Equiv.swap 0 (π (π 1)) else 1) = Equiv.swap 0 (π (π 1)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
π : Equiv.Perm (Fin 2)
h : π 1 = 0
⊢ (if π 0 = π (π 1) then Equiv.swap 0 (π (π 1)) else 1) = Equiv.swap 0 (π (π 1))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/PermFintwo.lean | Fin.cmtr_fin_two | [40, 1] | [46, 46] | rw [perm_fin_two x, perm_fin_two y] | x y : Equiv.Perm (Fin 2)
⊢ ⁅x, y⁆ = 1 | x y : Equiv.Perm (Fin 2)
⊢ ⁅if x 0 = 1 then Equiv.swap 0 1 else 1, if y 0 = 1 then Equiv.swap 0 1 else 1⁆ = 1 | Please generate a tactic in lean4 to solve the state.
STATE:
x y : Equiv.Perm (Fin 2)
⊢ ⁅x, y⁆ = 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/PermFintwo.lean | Fin.cmtr_fin_two | [40, 1] | [46, 46] | by_cases h : (x 0 = 1) | x y : Equiv.Perm (Fin 2)
⊢ ⁅if x 0 = 1 then Equiv.swap 0 1 else 1, if y 0 = 1 then Equiv.swap 0 1 else 1⁆ = 1 | case pos
x y : Equiv.Perm (Fin 2)
h : x 0 = 1
⊢ ⁅if x 0 = 1 then Equiv.swap 0 1 else 1, if y 0 = 1 then Equiv.swap 0 1 else 1⁆ = 1
case neg
x y : Equiv.Perm (Fin 2)
h : ¬x 0 = 1
⊢ ⁅if x 0 = 1 then Equiv.swap 0 1 else 1, if y 0 = 1 then Equiv.swap 0 1 else 1⁆ = 1 | Please generate a tactic in lean4 to solve the state.
STATE:
x y : Equiv.Perm (Fin 2)
⊢ ⁅if x 0 = 1 then Equiv.swap 0 1 else 1, if y 0 = 1 then Equiv.swap 0 1 else 1⁆ = 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/PermFintwo.lean | Fin.cmtr_fin_two | [40, 1] | [46, 46] | by_cases h₂ : (y 0 = 1) | case pos
x y : Equiv.Perm (Fin 2)
h : x 0 = 1
⊢ ⁅if x 0 = 1 then Equiv.swap 0 1 else 1, if y 0 = 1 then Equiv.swap 0 1 else 1⁆ = 1 | case pos
x y : Equiv.Perm (Fin 2)
h : x 0 = 1
h₂ : y 0 = 1
⊢ ⁅if x 0 = 1 then Equiv.swap 0 1 else 1, if y 0 = 1 then Equiv.swap 0 1 else 1⁆ = 1
case neg
x y : Equiv.Perm (Fin 2)
h : x 0 = 1
h₂ : ¬y 0 = 1
⊢ ⁅if x 0 = 1 then Equiv.swap 0 1 else 1, if y 0 = 1 then Equiv.swap 0 1 else 1⁆ = 1 | Please generate a tactic in lean4 to solve the state.
STATE:
case pos
x y : Equiv.Perm (Fin 2)
h : x 0 = 1
⊢ ⁅if x 0 = 1 then Equiv.swap 0 1 else 1, if y 0 = 1 then Equiv.swap 0 1 else 1⁆ = 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/PermFintwo.lean | Fin.cmtr_fin_two | [40, 1] | [46, 46] | rw [if_pos h, if_pos h₂, commutatorElement_self] | case pos
x y : Equiv.Perm (Fin 2)
h : x 0 = 1
h₂ : y 0 = 1
⊢ ⁅if x 0 = 1 then Equiv.swap 0 1 else 1, if y 0 = 1 then Equiv.swap 0 1 else 1⁆ = 1 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case pos
x y : Equiv.Perm (Fin 2)
h : x 0 = 1
h₂ : y 0 = 1
⊢ ⁅if x 0 = 1 then Equiv.swap 0 1 else 1, if y 0 = 1 then Equiv.swap 0 1 else 1⁆ = 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/PermFintwo.lean | Fin.cmtr_fin_two | [40, 1] | [46, 46] | rw [if_neg h₂, commutatorElement_one_right] | case neg
x y : Equiv.Perm (Fin 2)
h : x 0 = 1
h₂ : ¬y 0 = 1
⊢ ⁅if x 0 = 1 then Equiv.swap 0 1 else 1, if y 0 = 1 then Equiv.swap 0 1 else 1⁆ = 1 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case neg
x y : Equiv.Perm (Fin 2)
h : x 0 = 1
h₂ : ¬y 0 = 1
⊢ ⁅if x 0 = 1 then Equiv.swap 0 1 else 1, if y 0 = 1 then Equiv.swap 0 1 else 1⁆ = 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/PermFintwo.lean | Fin.cmtr_fin_two | [40, 1] | [46, 46] | rw [if_neg h, commutatorElement_one_left] | case neg
x y : Equiv.Perm (Fin 2)
h : ¬x 0 = 1
⊢ ⁅if x 0 = 1 then Equiv.swap 0 1 else 1, if y 0 = 1 then Equiv.swap 0 1 else 1⁆ = 1 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case neg
x y : Equiv.Perm (Fin 2)
h : ¬x 0 = 1
⊢ ⁅if x 0 = 1 then Equiv.swap 0 1 else 1, if y 0 = 1 then Equiv.swap 0 1 else 1⁆ = 1
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Bool.lean | Bool.apply_cond | [3, 1] | [4, 62] | cases b <;> rfl | α : Type u_1
β : Type u_2
f : α → β
b : Bool
x y : α
⊢ f (bif b then x else y) = bif b then f x else f y | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u_1
β : Type u_2
f : α → β
b : Bool
x y : α
⊢ f (bif b then x else y) = bif b then f x else f y
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Submonoid.lean | MulEquiv.mem_iff_map_mem_units_of_mem_iff_map_mem | [18, 1] | [21, 91] | simp_rw [Submonoid.mem_units_iff, ← e.map_inv, ← h, iff_self_and, inv_mem_iff, imp_self] | G : Type u_1
M : Type u_2
inst✝¹ : Group G
inst✝ : Monoid M
e : G ≃* Mˣ
S : Subgroup G
T : Submonoid M
h : ∀ (s : G), s ∈ S ↔ ↑(e s) ∈ T
s : G
⊢ s ∈ S ↔ e s ∈ T.units | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
G : Type u_1
M : Type u_2
inst✝¹ : Group G
inst✝ : Monoid M
e : G ≃* Mˣ
S : Subgroup G
T : Submonoid M
h : ∀ (s : G), s ∈ S ↔ ↑(e s) ∈ T
s : G
⊢ s ∈ S ↔ e s ∈ T.units
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.rev_eq_zero_iff_last | [10, 1] | [12, 26] | convert rev_inj | m : ℕ
i : Fin (m + 1)
⊢ i.rev = 0 ↔ i = last m | case h.e'_1.h.e'_3.h
m : ℕ
i : Fin (m + 1)
⊢ 0 = (last m).rev | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
⊢ i.rev = 0 ↔ i = last m
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.rev_eq_zero_iff_last | [10, 1] | [12, 26] | exact (rev_last m).symm | case h.e'_1.h.e'_3.h
m : ℕ
i : Fin (m + 1)
⊢ 0 = (last m).rev | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case h.e'_1.h.e'_3.h
m : ℕ
i : Fin (m + 1)
⊢ 0 = (last m).rev
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.rev_ne_zero_iff_ne_last | [14, 1] | [15, 40] | simp_rw [ne_eq, rev_eq_zero_iff_last] | m : ℕ
i : Fin (m + 1)
⊢ i.rev ≠ 0 ↔ i ≠ last m | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
⊢ i.rev ≠ 0 ↔ i ≠ last m
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.rev_pos_iff_lt_last | [17, 1] | [19, 32] | simp_rw [lt_last_iff_ne_last, pos_iff_ne_zero] | m : ℕ
i : Fin (m + 1)
⊢ 0 < i.rev ↔ i < last m | m : ℕ
i : Fin (m + 1)
⊢ i.rev ≠ 0 ↔ i ≠ last m | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
⊢ 0 < i.rev ↔ i < last m
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.rev_pos_iff_lt_last | [17, 1] | [19, 32] | exact rev_ne_zero_iff_ne_last | m : ℕ
i : Fin (m + 1)
⊢ i.rev ≠ 0 ↔ i ≠ last m | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
⊢ i.rev ≠ 0 ↔ i ≠ last m
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.eq_zero_iff_rev_eq_last | [21, 1] | [22, 43] | convert rev_rev i ▸ rev_eq_zero_iff_last | m : ℕ
i : Fin (m + 1)
⊢ i = 0 ↔ i.rev = last m | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
⊢ i = 0 ↔ i.rev = last m
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.ne_zero_iff_rev_ne_last | [24, 1] | [25, 46] | convert rev_rev i ▸ rev_ne_zero_iff_ne_last | m : ℕ
i : Fin (m + 1)
⊢ i ≠ 0 ↔ i.rev ≠ last m | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
⊢ i ≠ 0 ↔ i.rev ≠ last m
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.pos_iff_rev_lt_last | [27, 1] | [28, 42] | convert rev_rev i ▸ rev_pos_iff_lt_last | m : ℕ
i : Fin (m + 1)
⊢ 0 < i ↔ i.rev < last m | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
⊢ 0 < i ↔ i.rev < last m
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.rev_castSucc_succ | [30, 1] | [31, 50] | simp_rw [rev_succ, rev_castSucc, succ_castSucc] | m : ℕ
i : Fin m
⊢ i.castSucc.succ.rev = i.rev.castSucc.succ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin m
⊢ i.castSucc.succ.rev = i.rev.castSucc.succ
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.rev_succ_castSucc | [33, 1] | [34, 47] | simp_rw [← succ_castSucc, rev_castSucc_succ] | m : ℕ
i : Fin m
⊢ i.succ.castSucc.rev = i.rev.succ.castSucc | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin m
⊢ i.succ.castSucc.rev = i.rev.succ.castSucc
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.castSucc_rev_castSucc | [36, 1] | [37, 50] | simp_rw [rev_succ, rev_castSucc, succ_castSucc] | m : ℕ
i : Fin m
⊢ i.castSucc.rev.castSucc = i.succ.rev.succ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin m
⊢ i.castSucc.rev.castSucc = i.succ.rev.succ
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.succAbove_succAbove_predAbove | [51, 1] | [61, 12] | rcases lt_or_le (castSucc i) j with (h | h) | m : ℕ
i : Fin (m + 1)
j : Fin (m + 2)
⊢ (j.succAbove i).succAbove (i.predAbove j) = j | case inl
m : ℕ
i : Fin (m + 1)
j : Fin (m + 2)
h : i.castSucc < j
⊢ (j.succAbove i).succAbove (i.predAbove j) = j
case inr
m : ℕ
i : Fin (m + 1)
j : Fin (m + 2)
h : j ≤ i.castSucc
⊢ (j.succAbove i).succAbove (i.predAbove j) = j | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
j : Fin (m + 2)
⊢ (j.succAbove i).succAbove (i.predAbove j) = j
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.succAbove_succAbove_predAbove | [51, 1] | [61, 12] | rw [succAbove_of_castSucc_lt _ _ h, predAbove_of_castSucc_lt _ _ h,
succAbove_castSucc_of_le, succ_pred] | case inl
m : ℕ
i : Fin (m + 1)
j : Fin (m + 2)
h : i.castSucc < j
⊢ (j.succAbove i).succAbove (i.predAbove j) = j | case inl.h
m : ℕ
i : Fin (m + 1)
j : Fin (m + 2)
h : i.castSucc < j
⊢ i ≤ j.pred ⋯ | Please generate a tactic in lean4 to solve the state.
STATE:
case inl
m : ℕ
i : Fin (m + 1)
j : Fin (m + 2)
h : i.castSucc < j
⊢ (j.succAbove i).succAbove (i.predAbove j) = j
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.succAbove_succAbove_predAbove | [51, 1] | [61, 12] | rw [le_pred_iff, ← castSucc_lt_iff_succ_le] | case inl.h
m : ℕ
i : Fin (m + 1)
j : Fin (m + 2)
h : i.castSucc < j
⊢ i ≤ j.pred ⋯ | case inl.h
m : ℕ
i : Fin (m + 1)
j : Fin (m + 2)
h : i.castSucc < j
⊢ i.castSucc < j | Please generate a tactic in lean4 to solve the state.
STATE:
case inl.h
m : ℕ
i : Fin (m + 1)
j : Fin (m + 2)
h : i.castSucc < j
⊢ i ≤ j.pred ⋯
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.succAbove_succAbove_predAbove | [51, 1] | [61, 12] | exact h | case inl.h
m : ℕ
i : Fin (m + 1)
j : Fin (m + 2)
h : i.castSucc < j
⊢ i.castSucc < j | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inl.h
m : ℕ
i : Fin (m + 1)
j : Fin (m + 2)
h : i.castSucc < j
⊢ i.castSucc < j
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.succAbove_succAbove_predAbove | [51, 1] | [61, 12] | rw [succAbove_of_le_castSucc _ _ h, predAbove_of_le_castSucc _ _ h,
succAbove_succ_of_le, castSucc_castPred] | case inr
m : ℕ
i : Fin (m + 1)
j : Fin (m + 2)
h : j ≤ i.castSucc
⊢ (j.succAbove i).succAbove (i.predAbove j) = j | case inr.h
m : ℕ
i : Fin (m + 1)
j : Fin (m + 2)
h : j ≤ i.castSucc
⊢ j.castPred ⋯ ≤ i | Please generate a tactic in lean4 to solve the state.
STATE:
case inr
m : ℕ
i : Fin (m + 1)
j : Fin (m + 2)
h : j ≤ i.castSucc
⊢ (j.succAbove i).succAbove (i.predAbove j) = j
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.succAbove_succAbove_predAbove | [51, 1] | [61, 12] | rw [castPred_le_iff] | case inr.h
m : ℕ
i : Fin (m + 1)
j : Fin (m + 2)
h : j ≤ i.castSucc
⊢ j.castPred ⋯ ≤ i | case inr.h
m : ℕ
i : Fin (m + 1)
j : Fin (m + 2)
h : j ≤ i.castSucc
⊢ j ≤ i.castSucc | Please generate a tactic in lean4 to solve the state.
STATE:
case inr.h
m : ℕ
i : Fin (m + 1)
j : Fin (m + 2)
h : j ≤ i.castSucc
⊢ j.castPred ⋯ ≤ i
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.succAbove_succAbove_predAbove | [51, 1] | [61, 12] | exact h | case inr.h
m : ℕ
i : Fin (m + 1)
j : Fin (m + 2)
h : j ≤ i.castSucc
⊢ j ≤ i.castSucc | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inr.h
m : ℕ
i : Fin (m + 1)
j : Fin (m + 2)
h : j ≤ i.castSucc
⊢ j ≤ i.castSucc
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.castSucc_le_succAbove | [66, 1] | [68, 32] | obtain h | h := succAbove_eq_castSucc_or_succ p i <;> rw [h] | n : ℕ
p : Fin (n + 1)
i : Fin n
⊢ i.castSucc ≤ p.succAbove i | case inr
n : ℕ
p : Fin (n + 1)
i : Fin n
h : p.succAbove i = i.succ
⊢ i.castSucc ≤ i.succ | Please generate a tactic in lean4 to solve the state.
STATE:
n : ℕ
p : Fin (n + 1)
i : Fin n
⊢ i.castSucc ≤ p.succAbove i
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.castSucc_le_succAbove | [66, 1] | [68, 32] | exact (castSucc_lt_succ _).le | case inr
n : ℕ
p : Fin (n + 1)
i : Fin n
h : p.succAbove i = i.succ
⊢ i.castSucc ≤ i.succ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inr
n : ℕ
p : Fin (n + 1)
i : Fin n
h : p.succAbove i = i.succ
⊢ i.castSucc ≤ i.succ
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.succAbove_le_succ | [70, 1] | [72, 32] | obtain h | h := succAbove_eq_castSucc_or_succ p i <;> rw [h] | n : ℕ
p : Fin (n + 1)
i : Fin n
⊢ p.succAbove i ≤ i.succ | case inl
n : ℕ
p : Fin (n + 1)
i : Fin n
h : p.succAbove i = i.castSucc
⊢ i.castSucc ≤ i.succ | Please generate a tactic in lean4 to solve the state.
STATE:
n : ℕ
p : Fin (n + 1)
i : Fin n
⊢ p.succAbove i ≤ i.succ
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.succAbove_le_succ | [70, 1] | [72, 32] | exact (castSucc_lt_succ _).le | case inl
n : ℕ
p : Fin (n + 1)
i : Fin n
h : p.succAbove i = i.castSucc
⊢ i.castSucc ≤ i.succ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inl
n : ℕ
p : Fin (n + 1)
i : Fin n
h : p.succAbove i = i.castSucc
⊢ i.castSucc ≤ i.succ
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.succAbove_succAbove_predAbove_succAbove | [74, 1] | [93, 46] | rcases lt_or_le (castSucc i) j with (hij | hij) | m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
⊢ (j.succAbove i).succAbove ((i.predAbove j).succAbove k) = j.succAbove (i.succAbove k) | case inl
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : i.castSucc < j
⊢ (j.succAbove i).succAbove ((i.predAbove j).succAbove k) = j.succAbove (i.succAbove k)
case inr
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : j ≤ i.castSucc
⊢ (j.succAbove i).succAbove ((i.predAbove j).succAbove k) = j.succAbove (i.succAbove k) | Please generate a tactic in lean4 to solve the state.
STATE:
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
⊢ (j.succAbove i).succAbove ((i.predAbove j).succAbove k) = j.succAbove (i.succAbove k)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.succAbove_succAbove_predAbove_succAbove | [74, 1] | [93, 46] | rw [succAbove_of_castSucc_lt _ _ hij, predAbove_of_castSucc_lt _ _ hij] | case inl
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : i.castSucc < j
⊢ (j.succAbove i).succAbove ((i.predAbove j).succAbove k) = j.succAbove (i.succAbove k) | case inl
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : i.castSucc < j
⊢ i.castSucc.succAbove ((j.pred ⋯).succAbove k) = j.succAbove (i.succAbove k) | Please generate a tactic in lean4 to solve the state.
STATE:
case inl
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : i.castSucc < j
⊢ (j.succAbove i).succAbove ((i.predAbove j).succAbove k) = j.succAbove (i.succAbove k)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.succAbove_succAbove_predAbove_succAbove | [74, 1] | [93, 46] | rcases lt_or_le (castSucc k) i with (hik | hik) | case inl
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : i.castSucc < j
⊢ i.castSucc.succAbove ((j.pred ⋯).succAbove k) = j.succAbove (i.succAbove k) | case inl.inl
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : i.castSucc < j
hik : k.castSucc < i
⊢ i.castSucc.succAbove ((j.pred ⋯).succAbove k) = j.succAbove (i.succAbove k)
case inl.inr
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : i.castSucc < j
hik : i ≤ k.castSucc
⊢ i.castSucc.succAbove ((j.pred ⋯).succAbove k) = j.succAbove (i.succAbove k) | Please generate a tactic in lean4 to solve the state.
STATE:
case inl
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : i.castSucc < j
⊢ i.castSucc.succAbove ((j.pred ⋯).succAbove k) = j.succAbove (i.succAbove k)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.succAbove_succAbove_predAbove_succAbove | [74, 1] | [93, 46] | have H := (castSucc_lt_iff_succ_le.mp
(castSucc_lt_castSucc_iff.mpr hik)).trans_lt hij | case inl.inl
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : i.castSucc < j
hik : k.castSucc < i
⊢ i.castSucc.succAbove ((j.pred ⋯).succAbove k) = j.succAbove (i.succAbove k) | case inl.inl
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : i.castSucc < j
hik : k.castSucc < i
H : k.castSucc.succ < j
⊢ i.castSucc.succAbove ((j.pred ⋯).succAbove k) = j.succAbove (i.succAbove k) | Please generate a tactic in lean4 to solve the state.
STATE:
case inl.inl
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : i.castSucc < j
hik : k.castSucc < i
⊢ i.castSucc.succAbove ((j.pred ⋯).succAbove k) = j.succAbove (i.succAbove k)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.succAbove_succAbove_predAbove_succAbove | [74, 1] | [93, 46] | rw [succAbove_of_castSucc_lt _ _ hik, succAbove_of_succ_le _ _ H.le,
succAbove_of_castSucc_lt _ k ((lt_pred_iff _).mpr H), succAbove_castSucc_of_lt _ _ hik] | case inl.inl
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : i.castSucc < j
hik : k.castSucc < i
H : k.castSucc.succ < j
⊢ i.castSucc.succAbove ((j.pred ⋯).succAbove k) = j.succAbove (i.succAbove k) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inl.inl
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : i.castSucc < j
hik : k.castSucc < i
H : k.castSucc.succ < j
⊢ i.castSucc.succAbove ((j.pred ⋯).succAbove k) = j.succAbove (i.succAbove k)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.succAbove_succAbove_predAbove_succAbove | [74, 1] | [93, 46] | rw [succAbove_of_le_castSucc _ _ hik,
succAbove_castSucc_of_le, ← succ_succAbove_succ, succ_pred] | case inl.inr
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : i.castSucc < j
hik : i ≤ k.castSucc
⊢ i.castSucc.succAbove ((j.pred ⋯).succAbove k) = j.succAbove (i.succAbove k) | case inl.inr.h
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : i.castSucc < j
hik : i ≤ k.castSucc
⊢ i ≤ (j.pred ⋯).succAbove k | Please generate a tactic in lean4 to solve the state.
STATE:
case inl.inr
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : i.castSucc < j
hik : i ≤ k.castSucc
⊢ i.castSucc.succAbove ((j.pred ⋯).succAbove k) = j.succAbove (i.succAbove k)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.succAbove_succAbove_predAbove_succAbove | [74, 1] | [93, 46] | exact hik.trans (castSucc_le_succAbove _ _) | case inl.inr.h
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : i.castSucc < j
hik : i ≤ k.castSucc
⊢ i ≤ (j.pred ⋯).succAbove k | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inl.inr.h
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : i.castSucc < j
hik : i ≤ k.castSucc
⊢ i ≤ (j.pred ⋯).succAbove k
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.succAbove_succAbove_predAbove_succAbove | [74, 1] | [93, 46] | rw [succAbove_of_le_castSucc _ _ hij, predAbove_of_le_castSucc _ _ hij] | case inr
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : j ≤ i.castSucc
⊢ (j.succAbove i).succAbove ((i.predAbove j).succAbove k) = j.succAbove (i.succAbove k) | case inr
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : j ≤ i.castSucc
⊢ i.succ.succAbove ((j.castPred ⋯).succAbove k) = j.succAbove (i.succAbove k) | Please generate a tactic in lean4 to solve the state.
STATE:
case inr
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : j ≤ i.castSucc
⊢ (j.succAbove i).succAbove ((i.predAbove j).succAbove k) = j.succAbove (i.succAbove k)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.succAbove_succAbove_predAbove_succAbove | [74, 1] | [93, 46] | rcases lt_or_le i (succ k) with (hik | hik) | case inr
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : j ≤ i.castSucc
⊢ i.succ.succAbove ((j.castPred ⋯).succAbove k) = j.succAbove (i.succAbove k) | case inr.inl
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : j ≤ i.castSucc
hik : i < k.succ
⊢ i.succ.succAbove ((j.castPred ⋯).succAbove k) = j.succAbove (i.succAbove k)
case inr.inr
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : j ≤ i.castSucc
hik : k.succ ≤ i
⊢ i.succ.succAbove ((j.castPred ⋯).succAbove k) = j.succAbove (i.succAbove k) | Please generate a tactic in lean4 to solve the state.
STATE:
case inr
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : j ≤ i.castSucc
⊢ i.succ.succAbove ((j.castPred ⋯).succAbove k) = j.succAbove (i.succAbove k)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.succAbove_succAbove_predAbove_succAbove | [74, 1] | [93, 46] | have H := ((hij.trans_lt (castSucc_lt_castSucc_iff.mpr hik))) | case inr.inl
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : j ≤ i.castSucc
hik : i < k.succ
⊢ i.succ.succAbove ((j.castPred ⋯).succAbove k) = j.succAbove (i.succAbove k) | case inr.inl
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : j ≤ i.castSucc
hik : i < k.succ
H : j < k.succ.castSucc
⊢ i.succ.succAbove ((j.castPred ⋯).succAbove k) = j.succAbove (i.succAbove k) | Please generate a tactic in lean4 to solve the state.
STATE:
case inr.inl
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : j ≤ i.castSucc
hik : i < k.succ
⊢ i.succ.succAbove ((j.castPred ⋯).succAbove k) = j.succAbove (i.succAbove k)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.succAbove_succAbove_predAbove_succAbove | [74, 1] | [93, 46] | rw [succAbove_of_lt_succ _ _ hik, succAbove_of_le_castSucc _ _ H.le,
succAbove_of_lt_succ _ k ((castPred_lt_iff _).mpr H), succAbove_succ_of_lt _ _ hik] | case inr.inl
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : j ≤ i.castSucc
hik : i < k.succ
H : j < k.succ.castSucc
⊢ i.succ.succAbove ((j.castPred ⋯).succAbove k) = j.succAbove (i.succAbove k) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inr.inl
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : j ≤ i.castSucc
hik : i < k.succ
H : j < k.succ.castSucc
⊢ i.succ.succAbove ((j.castPred ⋯).succAbove k) = j.succAbove (i.succAbove k)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.succAbove_succAbove_predAbove_succAbove | [74, 1] | [93, 46] | rw [succAbove_of_succ_le _ _ hik, succAbove_succ_of_le,
← castSucc_succAbove_castSucc, castSucc_castPred] | case inr.inr
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : j ≤ i.castSucc
hik : k.succ ≤ i
⊢ i.succ.succAbove ((j.castPred ⋯).succAbove k) = j.succAbove (i.succAbove k) | case inr.inr.h
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : j ≤ i.castSucc
hik : k.succ ≤ i
⊢ (j.castPred ⋯).succAbove k ≤ i | Please generate a tactic in lean4 to solve the state.
STATE:
case inr.inr
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : j ≤ i.castSucc
hik : k.succ ≤ i
⊢ i.succ.succAbove ((j.castPred ⋯).succAbove k) = j.succAbove (i.succAbove k)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Fin.lean | Fin.succAbove_succAbove_predAbove_succAbove | [74, 1] | [93, 46] | exact (succAbove_le_succ _ _).trans hik | case inr.inr.h
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : j ≤ i.castSucc
hik : k.succ ≤ i
⊢ (j.castPred ⋯).succAbove k ≤ i | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case inr.inr.h
m : ℕ
i : Fin (m + 1)
k : Fin m
j : Fin (m + 2)
hij : j ≤ i.castSucc
hik : k.succ ≤ i
⊢ (j.castPred ⋯).succAbove k ≤ i
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Equivs.lean | piFinSuccCastSucc_apply | [11, 1] | [17, 6] | simp_rw [Prod.ext_iff, Function.funext_iff] | n : ℕ
α : Type u_1
v : Fin (n + 2) → α
⊢ piFinSuccCastSucc v = ((v 0, v (last (n + 1))), v ∘ fun i => i.castSucc.succ) | n : ℕ
α : Type u_1
v : Fin (n + 2) → α
⊢ ((piFinSuccCastSucc v).1.1 = v 0 ∧ (piFinSuccCastSucc v).1.2 = v (last (n + 1))) ∧
∀ (a : Fin n), (piFinSuccCastSucc v).2 a = (v ∘ fun i => i.castSucc.succ) a | Please generate a tactic in lean4 to solve the state.
STATE:
n : ℕ
α : Type u_1
v : Fin (n + 2) → α
⊢ piFinSuccCastSucc v = ((v 0, v (last (n + 1))), v ∘ fun i => i.castSucc.succ)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Equivs.lean | piFinSuccCastSucc_apply | [11, 1] | [17, 6] | refine' ⟨⟨rfl, rfl⟩, fun _ => _⟩ | n : ℕ
α : Type u_1
v : Fin (n + 2) → α
⊢ ((piFinSuccCastSucc v).1.1 = v 0 ∧ (piFinSuccCastSucc v).1.2 = v (last (n + 1))) ∧
∀ (a : Fin n), (piFinSuccCastSucc v).2 a = (v ∘ fun i => i.castSucc.succ) a | n : ℕ
α : Type u_1
v : Fin (n + 2) → α
x✝ : Fin n
⊢ (piFinSuccCastSucc v).2 x✝ = (v ∘ fun i => i.castSucc.succ) x✝ | Please generate a tactic in lean4 to solve the state.
STATE:
n : ℕ
α : Type u_1
v : Fin (n + 2) → α
⊢ ((piFinSuccCastSucc v).1.1 = v 0 ∧ (piFinSuccCastSucc v).1.2 = v (last (n + 1))) ∧
∀ (a : Fin n), (piFinSuccCastSucc v).2 a = (v ∘ fun i => i.castSucc.succ) a
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Equivs.lean | piFinSuccCastSucc_apply | [11, 1] | [17, 6] | simp_rw [piFinSuccCastSucc, Equiv.instTrans_trans, Equiv.trans_apply, Equiv.prodCongr_apply,
Equiv.piFinSuccAbove_apply, extractNth, succAbove_last] | n : ℕ
α : Type u_1
v : Fin (n + 2) → α
x✝ : Fin n
⊢ (piFinSuccCastSucc v).2 x✝ = (v ∘ fun i => i.castSucc.succ) x✝ | n : ℕ
α : Type u_1
v : Fin (n + 2) → α
x✝ : Fin n
⊢ ((Equiv.prodAssoc α α (Fin n → α)).symm
(Prod.map (⇑(Equiv.refl α)) (fun f => (f (last n), fun j => f j.castSucc)) ((Equiv.piFinSucc (n + 1) α) v))).2
x✝ =
(v ∘ fun i => i.castSucc.succ) x✝ | Please generate a tactic in lean4 to solve the state.
STATE:
n : ℕ
α : Type u_1
v : Fin (n + 2) → α
x✝ : Fin n
⊢ (piFinSuccCastSucc v).2 x✝ = (v ∘ fun i => i.castSucc.succ) x✝
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Equivs.lean | piFinSuccCastSucc_apply | [11, 1] | [17, 6] | rfl | n : ℕ
α : Type u_1
v : Fin (n + 2) → α
x✝ : Fin n
⊢ ((Equiv.prodAssoc α α (Fin n → α)).symm
(Prod.map (⇑(Equiv.refl α)) (fun f => (f (last n), fun j => f j.castSucc)) ((Equiv.piFinSucc (n + 1) α) v))).2
x✝ =
(v ∘ fun i => i.castSucc.succ) x✝ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
n : ℕ
α : Type u_1
v : Fin (n + 2) → α
x✝ : Fin n
⊢ ((Equiv.prodAssoc α α (Fin n → α)).symm
(Prod.map (⇑(Equiv.refl α)) (fun f => (f (last n), fun j => f j.castSucc)) ((Equiv.piFinSucc (n + 1) α) v))).2
x✝ =
(v ∘ fun i => i.castSucc.succ) x✝
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Equivs.lean | piFinSuccCastSucc_apply_fst_fst | [19, 1] | [21, 48] | simp_rw [piFinSuccCastSucc_apply] | n : ℕ
α : Type u_1
v : Fin (n + 2) → α
⊢ (piFinSuccCastSucc v).1.1 = v 0 | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
n : ℕ
α : Type u_1
v : Fin (n + 2) → α
⊢ (piFinSuccCastSucc v).1.1 = v 0
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Equivs.lean | piFinSuccCastSucc_apply_fst_snd | [23, 1] | [25, 55] | simp_rw [piFinSuccCastSucc_apply] | n : ℕ
α : Type u_1
v : Fin (n + 2) → α
⊢ (piFinSuccCastSucc v).1.2 = v (last (n + 1)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
n : ℕ
α : Type u_1
v : Fin (n + 2) → α
⊢ (piFinSuccCastSucc v).1.2 = v (last (n + 1))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Equivs.lean | piFinSuccCastSucc_apply_snd | [27, 1] | [29, 77] | simp only [piFinSuccCastSucc_apply] | n : ℕ
α : Type u_1
v : Fin (n + 2) → α
⊢ (piFinSuccCastSucc v).2 = v ∘ fun i => i.castSucc.succ | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
n : ℕ
α : Type u_1
v : Fin (n + 2) → α
⊢ (piFinSuccCastSucc v).2 = v ∘ fun i => i.castSucc.succ
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Equivs.lean | piFinSuccCastSucc_symm_apply_castSucc_succ | [31, 1] | [37, 58] | simp only [piFinSuccCastSucc, Equiv.instTrans_trans, Equiv.symm_trans_apply, Equiv.symm_symm,
Equiv.prodAssoc_apply, Equiv.prodCongr_symm, Equiv.refl_symm, Equiv.prodCongr_apply,
Equiv.coe_refl, Equiv.piFinSuccAbove_symm_apply, insertNth_last', Prod_map, id_eq,
Equiv.piFinSucc_symm_apply, cons_succ, snoc_castSucc] | α : Type u_1
n : ℕ
a b : α
v : Fin n → α
i : Fin n
⊢ piFinSuccCastSucc.symm ((a, b), v) i.castSucc.succ = v i | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u_1
n : ℕ
a b : α
v : Fin n → α
i : Fin n
⊢ piFinSuccCastSucc.symm ((a, b), v) i.castSucc.succ = v i
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Equivs.lean | piFinSuccCastSucc_symm_apply_succ_castSucc | [39, 1] | [42, 68] | rw [<- succ_castSucc, piFinSuccCastSucc_symm_apply_castSucc_succ] | α : Type u_1
n : ℕ
a b : α
v : Fin n → α
i : Fin n
⊢ piFinSuccCastSucc.symm ((a, b), v) i.succ.castSucc = v i | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u_1
n : ℕ
a b : α
v : Fin n → α
i : Fin n
⊢ piFinSuccCastSucc.symm ((a, b), v) i.succ.castSucc = v i
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/Equivs.lean | piFinSuccCastSucc_symm_apply_last | [48, 1] | [54, 67] | simp_rw [piFinSuccCastSucc, Equiv.instTrans_trans, Equiv.symm_trans_apply, Equiv.symm_symm,
Equiv.prodAssoc_apply, Equiv.prodCongr_symm, Equiv.refl_symm, Equiv.prodCongr_apply,
Equiv.coe_refl, Equiv.piFinSuccAbove_symm_apply, insertNth_last', Prod_map, id_eq,
Equiv.piFinSucc_symm_apply, cons_snoc_eq_snoc_cons, snoc_last] | α : Type u_1
n : ℕ
a b : α
v : Fin n → α
⊢ piFinSuccCastSucc.symm ((a, b), v) (last (n + 1)) = b | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u_1
n : ℕ
a b : α
v : Fin n → α
⊢ piFinSuccCastSucc.symm ((a, b), v) (last (n + 1)) = b
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleMin_cmtr_apply_comm | [12, 1] | [16, 65] | simp_rw [cycleMin_eq_cycleMin_apply (x := y (x q)), ← Perm.mul_apply, ← mul_assoc,
cmtr_mul_eq_mul_inv_cmtr_inv, commutatorElement_inv, Perm.mul_apply,
cmtr_apply, inv_inv, Perm.inv_apply_self, Perm.apply_inv_self] | α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
⊢ CycleMin ⁅x, y⁆ (x (y q)) = CycleMin ⁅x, y⁆ (y (x q)) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝² : Fintype α
inst✝¹ : DecidableEq α
x y : Perm α
q : α
inst✝ : LinearOrder α
⊢ CycleMin ⁅x, y⁆ (x (y q)) = CycleMin ⁅x, y⁆ (y (x q))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleAt_cmtr_disjoint_image | [18, 1] | [23, 55] | simp_rw [Finset.disjoint_iff_ne, Finset.mem_image, mem_cycleAt_iff] | α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ Disjoint (CycleAt ⁅x, y⁆ q) (Finset.image (⇑y) (CycleAt ⁅x, y⁆ q)) | α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (a : α), ⁅x, y⁆.SameCycle q a → ∀ (b : α), (∃ a, ⁅x, y⁆.SameCycle q a ∧ y a = b) → a ≠ b | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ Disjoint (CycleAt ⁅x, y⁆ q) (Finset.image (⇑y) (CycleAt ⁅x, y⁆ q))
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleAt_cmtr_disjoint_image | [18, 1] | [23, 55] | rintro _ ⟨j, rfl⟩ _ ⟨_, ⟨⟨_, rfl⟩, rfl⟩⟩ | α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (a : α), ⁅x, y⁆.SameCycle q a → ∀ (b : α), (∃ a, ⁅x, y⁆.SameCycle q a ∧ y a = b) → a ≠ b | case intro.intro.intro.intro
α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
j w✝ : ℤ
⊢ (⁅x, y⁆ ^ j) q ≠ y ((⁅x, y⁆ ^ w✝) q) | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ ∀ (a : α), ⁅x, y⁆.SameCycle q a → ∀ (b : α), (∃ a, ⁅x, y⁆.SameCycle q a ∧ y a = b) → a ≠ b
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleAt_cmtr_disjoint_image | [18, 1] | [23, 55] | exact cmtr_zpow_apply_ne_apply_cmtr_pow_apply hxy hy | case intro.intro.intro.intro
α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
j w✝ : ℤ
⊢ (⁅x, y⁆ ^ j) q ≠ y ((⁅x, y⁆ ^ w✝) q) | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
case intro.intro.intro.intro
α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
j w✝ : ℤ
⊢ (⁅x, y⁆ ^ j) q ≠ y ((⁅x, y⁆ ^ w✝) q)
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleAt_cmtr_card_le_card_univ_div_two | [25, 1] | [31, 51] | rw [cycleAt_card_eq_orderOf_cycleOf, Nat.le_div_iff_mul_le (zero_lt_two), mul_comm, two_mul] | α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ orderOf (⁅x, y⁆.cycleOf q) ≤ Finset.univ.card / 2 | α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (CycleAt ⁅x, y⁆ q).card + (CycleAt ⁅x, y⁆ q).card ≤ Finset.univ.card | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ orderOf (⁅x, y⁆.cycleOf q) ≤ Finset.univ.card / 2
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleAt_cmtr_card_le_card_univ_div_two | [25, 1] | [31, 51] | nth_rewrite 2 [← Finset.card_image_of_injective _ (y.injective)] | α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (CycleAt ⁅x, y⁆ q).card + (CycleAt ⁅x, y⁆ q).card ≤ Finset.univ.card | α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (CycleAt ⁅x, y⁆ q).card + (Finset.image (⇑y) (CycleAt ⁅x, y⁆ q)).card ≤ Finset.univ.card | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (CycleAt ⁅x, y⁆ q).card + (CycleAt ⁅x, y⁆ q).card ≤ Finset.univ.card
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleAt_cmtr_card_le_card_univ_div_two | [25, 1] | [31, 51] | rw [← Finset.card_union_of_disjoint (cycleAt_cmtr_disjoint_image hxy hy)] | α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (CycleAt ⁅x, y⁆ q).card + (Finset.image (⇑y) (CycleAt ⁅x, y⁆ q)).card ≤ Finset.univ.card | α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (CycleAt ⁅x, y⁆ q ∪ Finset.image (⇑y) (CycleAt ⁅x, y⁆ q)).card ≤ Finset.univ.card | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (CycleAt ⁅x, y⁆ q).card + (Finset.image (⇑y) (CycleAt ⁅x, y⁆ q)).card ≤ Finset.univ.card
TACTIC:
|
https://github.com/linesthatinterlace/controlbits.git | 4a0d924f7bd9e6dcc6719ef05314fdfd702c6a01 | Controlbits/CommutatorCycles.lean | cycleAt_cmtr_card_le_card_univ_div_two | [25, 1] | [31, 51] | exact Finset.card_le_card (Finset.subset_univ _) | α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (CycleAt ⁅x, y⁆ q ∪ Finset.image (⇑y) (CycleAt ⁅x, y⁆ q)).card ≤ Finset.univ.card | no goals | Please generate a tactic in lean4 to solve the state.
STATE:
α : Type u
inst✝¹ : Fintype α
inst✝ : DecidableEq α
x y : Perm α
q : α
hxy : ⁅x, y⁻¹⁆ = ⁅x, y⁆
hy : ∀ (q : α), y q ≠ q
⊢ (CycleAt ⁅x, y⁆ q ∪ Finset.image (⇑y) (CycleAt ⁅x, y⁆ q)).card ≤ Finset.univ.card
TACTIC:
|
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