content stringlengths 1 1.04M ⌀ |
|---|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:46:07 07/16/2015
-- Design Name:
-- Module Name: reg8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision: ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
architecture rtl of fifo is
begin
process
begin
var1 := '0' WHEN rd_en = '1' else '1';
var2 := '0' when rd_en = '1' else '1';
wr_en_a <= force '0' WHEN rd_en = '1' else '1';
wr_en_b <= force '0' when rd_en = '1' else '1';
end process;
concurrent_wr_en_a <= '0' WHEN rd_en = '1' else '1';... |
architecture rtl of fifo is
begin
process
begin
var1 := '0' WHEN rd_en = '1' else '1';
var2 := '0' when rd_en = '1' else '1';
wr_en_a <= force '0' WHEN rd_en = '1' else '1';
wr_en_b <= force '0' when rd_en = '1' else '1';
end process;
concurrent_wr_en_a <= '0' WHEN rd_en = '1' else '1';... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:03:18 10/26/2009
-- Design Name:
-- Module Name: IprtReg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:03:18 10/26/2009
-- Design Name:
-- Module Name: IprtReg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:03:18 10/26/2009
-- Design Name:
-- Module Name: IprtReg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
package fifo_pkg is
signal wr_en : std_logic;
signal rd_en : std_logic;
constant c_constant : integer;
alias alias1 : subtype_indicator is name;
alias alias1 is name;
signal wr_en : std_logic;
signal rd_en : std_logic;
constant c_constant : integer;
alias a... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
package body RTL is
attribute mark_debug of wr_en : signal is "true";
attribute mark_debug of almost_empty : signal is "true";
attribute mark_debug of full : signal is "true";
procedure rst_procedure is
attribute mark_debug of wr_en : signal is "true";
attribute mark_debug of almost_e... |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
package foo_pkg is
type my_int is range 0 to 100;
subtype my_int_sub is my_int range 10 to 20;
end package;
-------------------------------------------------------------------------------
use work.foo_pkg.all;
entity foo is
port (
o : out my_int;
i : in my_int );
end entity;
------------... |
package foo_pkg is
type my_int is range 0 to 100;
subtype my_int_sub is my_int range 10 to 20;
end package;
-------------------------------------------------------------------------------
use work.foo_pkg.all;
entity foo is
port (
o : out my_int;
i : in my_int );
end entity;
------------... |
package foo_pkg is
type my_int is range 0 to 100;
subtype my_int_sub is my_int range 10 to 20;
end package;
-------------------------------------------------------------------------------
use work.foo_pkg.all;
entity foo is
port (
o : out my_int;
i : in my_int );
end entity;
------------... |
library ieee;
use ieee.std_logic_1164.all;
--##########################
--######## AND GATES #######
--##########################
entity AND2 is
port
(
I1 :in std_logic;
I2 :in std_logic;
O :out std_logic
);
end entity AND2;
library ieee;
... |
library ieee;
use ieee.std_logic_1164.all;
--##########################
--######## AND GATES #######
--##########################
entity AND2 is
port
(
I1 :in std_logic;
I2 :in std_logic;
O :out std_logic
);
end entity AND2;
library ieee;
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--! @file symbolizer_even_ea.vhd
--! @brief Takes a parallel bus and maps it to symbols
--! @author Scott Teal (Scott@Teals.org)
--! @date 2013-11-05
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except i... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Package: ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Package: ... |
-- This is the top level MIPS architecture
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
entity mips is
generic ( DEMO : boolean := false);
port (
sysclk : in std_logic;
rst : in std_logic;
-- VGA I/O
vgaclk : in std_logic;
r, g, b : out std_logic_v... |
-------------------------------------------------------------------------------
-- File Name : AC_CR_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : AC_CR_ROM
--
-- Content : AC_CR_ROM Chrominance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-----------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : AC_CR_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : AC_CR_ROM
--
-- Content : AC_CR_ROM Chrominance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-----------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : AC_CR_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : AC_CR_ROM
--
-- Content : AC_CR_ROM Chrominance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-----------------------------------------... |
-- NEED RESULT: ARCH00618: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00618: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00618: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00618.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00618.P2: Multi transport... |
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... |
------------------------------------------------------------------------------------------------------------------------
-- POWERLINK IP-Core
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditio... |
------------------------------------------------------------------------------------------------------------------------
-- POWERLINK IP-Core
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditio... |
------------------------------------------------------------------------------------------------------------------------
-- POWERLINK IP-Core
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditio... |
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY STATUS_REGISTER IS
PORT (
carryIn, overflowIn : IN std_logic;
data : IN std_logic_vector (15 DOWNTO 0);
carry, zero, sign, parity, borrow, overflow : OUT std_logic
);
END STATUS_REGISTER;
ARCHITECTURE STATUS_REGISTER_ARCH OF STATUS_REG... |
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemen... |
--
-- UART 16750
--
-- Author: Sebastian Witt
-- Date: 29.01.2008
-- Version: 1.5
--
-- History: 1.0 - Initial version
-- 1.1 - THR empty interrupt register connected to RST
-- 1.2 - Registered outputs
-- 1.3 - Automatic flow control
-- 1.4 - De-assert IIR FIFO64 when FIF... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versi... |
library verilog;
use verilog.vl_types.all;
entity MUX4_1 is
port(
Sel : in vl_logic_vector(1 downto 0);
S0 : in vl_logic_vector(7 downto 0);
S1 : in vl_logic_vector(7 downto 0);
S2 : in vl_logic_vector(7 downto 0);
... |
library verilog;
use verilog.vl_types.all;
entity MUX4_1 is
port(
Sel : in vl_logic_vector(1 downto 0);
S0 : in vl_logic_vector(7 downto 0);
S1 : in vl_logic_vector(7 downto 0);
S2 : in vl_logic_vector(7 downto 0);
... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectua... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectua... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity tb_usb_host is
end entity;
architecture tb of tb_usb_host is
signal ulpi_clock : std_logic := '0';
signal ulpi_reset : std_logic;
signal ULPI_DATA : std_logic_vector(7 downto... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity tb_usb_host is
end entity;
architecture tb of tb_usb_host is
signal ulpi_clock : std_logic := '0';
signal ulpi_reset : std_logic;
signal ULPI_DATA : std_logic_vector(7 downto... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity tb_usb_host is
end entity;
architecture tb of tb_usb_host is
signal ulpi_clock : std_logic := '0';
signal ulpi_reset : std_logic;
signal ULPI_DATA : std_logic_vector(7 downto... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VC... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:52:03 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the F... |
library ieee;
use ieee.std_logic_1164.all;
entity logic_unit is
port (
A,B : in std_logic_vector(7 downto 0);
Cin : in std_logic;
mode : in std_logic_vector(1 downto 0);
F : out std_logic_vector(7 downto 0)
);
end logic_unit;
architecture arch of logic_unit is
signal F_buffer: std_logic_vector(7 downt... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package package0 is
-- Roundup logarithm with base 2 (first x that 2^x is larger or equal to given number)
function log2 (n : integer) return integer;
end package0;
package body package0 is
function log2... |
--------------------------------------------------------------------------------
-- Title : Transmitter FIFO with AxiStream interfaces
-- Version : 1.3
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_t... |
--------------------------------------------------------------------------------
-- Title : Transmitter FIFO with AxiStream interfaces
-- Version : 1.3
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_t... |
--------------------------------------------------------------------------------
-- Title : Transmitter FIFO with AxiStream interfaces
-- Version : 1.3
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_t... |
-------------------------------------------------------------------------------
--
-- The Wishbone master module.
--
-- $Id: wb_master.vhd,v 1.5 2005-06-11 10:16:05 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezise... |
-- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
architecture rtl of ovl_next is
constant assert_name : string := "OVL_NEXT";
constant path ... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Sat Sep 23 13:26:01 2017
-- Host : DarkCube running 64-bit major releas... |
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
B_RD_EN : buffer std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
WR_EN : in std_logic;
DATA : out std_logic_vector(31 downto 0);
RD_EN ... |
----------------------------------------------------------------------------------
-- Company: LBNL
-- Engineer: Arnaud Sautaux
--
-- Create Date: 07/27/2017 10:50:41 AM
-- Design Name: DDR3 Wishbone control core
-- Module Name: ddr3_ctrl_wb - Behavioral
-- Project Name: YARR
-- Target Devices:
-- Tool Versions: Viva... |
---------------------------------------------------------------------
-- Coprocessor
--
-- Part of the LXP32 test platform
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Performs a simple arithmetic operation, uses interrupt to wake
-- up the CPU.
--
-- Note: regardless of whether this description is synthesizable... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.types.all;
entity aeshw_v1_0_S_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DAT... |
entity sub is
port ( p : in bit_vector(7 downto 0) );
end entity;
architecture test of sub is
alias a1 : bit_vector(3 downto 0) is p(7 downto 4);
alias a2 : bit_vector(3 downto 0) is p(3 downto 0);
begin
process is
begin
wait for 2 ns;
assert a1 = "1111";
assert a2 = "0000"... |
-- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your opt... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:08:56 05/24/2011
-- Design Name:
-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_single_debouncer.vhd
-- Project Name: oscilloscope
-- Target Device:
-- Tool versions:
-- ... |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
PORT MAP (
PORT_1 => w_port... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "clk_divider"
-- Project :
-------------------------------------------------------------------------------
-- File : clk_divider_tb.vhd
-- Author : Pedro Messias Jose da Cunha B... |
-- file: clks_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not... |
-- $Id: serport_uart_tx.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: serport_uart_tx - syn
-- Description: ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use work.exploration_pkg.all;
package vector_pkg is
type Vector is record
x : real;
y : real;
end record;
function norm(vec : Vector) return real;
end;
package body exploration_pkg is
function norm(vec : Vector) return... |
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: petera@cs.adelaide.edu.au
--
-- This program is free software; you can redistribute it and/or modify
-- it... |
package p is
function add2(x : integer) return integer;
end package;
package body p is
function add2(x : integer) return integer is
begin
return x + 2;
end function;
end package body;
entity link1 is
end entity;
use work.p.all;
architecture test of link1 is
begin
process is
begin
... |
package p is
function add2(x : integer) return integer;
end package;
package body p is
function add2(x : integer) return integer is
begin
return x + 2;
end function;
end package body;
entity link1 is
end entity;
use work.p.all;
architecture test of link1 is
begin
process is
begin
... |
package p is
function add2(x : integer) return integer;
end package;
package body p is
function add2(x : integer) return integer is
begin
return x + 2;
end function;
end package body;
entity link1 is
end entity;
use work.p.all;
architecture test of link1 is
begin
process is
begin
... |
package p is
function add2(x : integer) return integer;
end package;
package body p is
function add2(x : integer) return integer is
begin
return x + 2;
end function;
end package body;
entity link1 is
end entity;
use work.p.all;
architecture test of link1 is
begin
process is
begin
... |
package p is
function add2(x : integer) return integer;
end package;
package body p is
function add2(x : integer) return integer is
begin
return x + 2;
end function;
end package body;
entity link1 is
end entity;
use work.p.all;
architecture test of link1 is
begin
process is
begin
... |
--
-- Reduced from VESTs cases tc640 and tc641
--
entity file7 is
end entity;
architecture test of file7 is
subtype word is bit_vector(0 to 15);
constant size : integer := 7;
type primary_memory is array (0 to size) of word;
type primary_memory_file is file of primary_memory;
constant C38 ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful... |
---------------------------------------------------------
-- JAM CPU
-- Simulation wrapper
--
-- License: LGPL v2+ (see the file LICENSE)
-- Copyright © 2002:
-- Anders Lindström, Johan E. Thelin, Michael Nordseth
---------------------------------------------------------
-- This is free software; you can redistribute ... |
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity SimpleDecimator is
generic (
wordLength : natural := 8;
divider : natural := 2
);
port (
input : in std_logic_vector(wordLength-1 downto 0);
output : out std_logic_vector(wordLength-1 downto 0);
reset : in std_logic;
clk :... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-... |
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