content stringlengths 1 1.04M ⌀ |
|---|
package arith1 is
function div(x, y : integer) return integer;
function div(x, y : real) return real;
function div(x : integer; y : real) return real;
function exp(x : real; y : integer) return real;
function exp(x, y : integer) return integer;
function neg(x : integer) return integer;
fun... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
entity bug is
port(data: out integer);
end entity bug;
architecture arc of bug is
begin
end architecture arc;
entity bug_sim is
end entity bug_sim;
architecture sim of bug_sim is
signal data: natural;
begin
u0: entity work.bug
port map(data => data);
end architecture sim;
|
entity bug is
port(data: out integer);
end entity bug;
architecture arc of bug is
begin
end architecture arc;
entity bug_sim is
end entity bug_sim;
architecture sim of bug_sim is
signal data: natural;
begin
u0: entity work.bug
port map(data => data);
end architecture sim;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... |
----------------------------------------------------------------------
-- brdRstClk (for EmCraft SoC FG896 Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- board/kit dependency : LEDs & SW polarity
--
----------------------------------------------------------... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:15:16 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major... |
-- Top level entity, MARK_II SoC
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: v.mlejnecky@seznam.cz
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MARK_II is
port(
--rs232... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--------------------------------------------------
-- Module Name: Hex4Digs_2_SSeg - behavioral --
--------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.Hex4Digs_2_SSeg_Package.all;
entity Hex4Digs_2_SSeg is
Port ( clock : in ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.87... |
library verilog;
use verilog.vl_types.all;
entity R_SEQ is
port(
address : in vl_logic_vector(7 downto 0);
clock : in vl_logic;
q : out vl_logic_vector(127 downto 0)
);
end R_SEQ;
|
library verilog;
use verilog.vl_types.all;
entity R_SEQ is
port(
address : in vl_logic_vector(7 downto 0);
clock : in vl_logic;
q : out vl_logic_vector(127 downto 0)
);
end R_SEQ;
|
package pack is
function add4(x : in integer) return integer;
end package;
package body pack is
function add4(x : in integer) return integer is
begin
return x + 4;
end function;
end package body;
-------------------------------------------------------------------------------
entity ffold ... |
package pack is
function add4(x : in integer) return integer;
end package;
package body pack is
function add4(x : in integer) return integer is
begin
return x + 4;
end function;
end package body;
-------------------------------------------------------------------------------
entity ffold ... |
package pack is
function add4(x : in integer) return integer;
end package;
package body pack is
function add4(x : in integer) return integer is
begin
return x + 4;
end function;
end package body;
-------------------------------------------------------------------------------
entity ffold ... |
----------------------------------------------------------------------------------
-- Company: Universidad Complutense de Madrid
-- Engineer: Hortensia Mecha
--
-- Design Name: divisor
-- Module Name: divisor - divisor_arch
-- Project Name:
-- Target Devices:
-- Description: Creación de un reloj de 1Hz ... |
----------------------------------------------------------------------------------
-- Company: Universidad Complutense de Madrid
-- Engineer: Hortensia Mecha
--
-- Design Name: divisor
-- Module Name: divisor - divisor_arch
-- Project Name:
-- Target Devices:
-- Description: Creación de un reloj de 1Hz ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pixel_gen is port (
clk : in std_logic;
x0,y0 : in std_logic_vector(17 downto 0);
overflow_bits : out std_logic_vector(19 downto 0));
end pixel_gen;
architecture Behavioral of pixel_gen is
type pipe_state is (s1,s2,s3);
signal ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:42:21 08/16/2010
-- Design Name:
-- Module Name: C:/Users/georgecuris/Desktop/Folders/FPGA/Projects/Current Projects/Systems/testytest/top_level_TB.vhd
-- Project Name: testyte... |
entity FIFO is
port (
port1 : in std_logic;
port1 : out std_logic;
port1 : inout std_logic bus;
port1 : buffer std_logic bus := "asdf";
port1 : linkage std_logic := "asdf";
port1 : std_logic
);
end entity FIFO;
entity FIFO is
port (
signal port1 : in std_logic;
signal port1 : ou... |
-- VHDL Entity lab10_WriteBack_Stage_lib.lab10_WriteBack_Stage.symbol
--
-- Created:
-- by - Hong.Hong (HSM)
-- at - 01:13:04 04/23/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY lab10_WriteBa... |
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity FIFO is
end entity;
entity FIFO is
end entity;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for mdec_core
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:56:34 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\nreset2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: mdec_core-... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 17/08/2015
--! Module Name: elinkInterface_package
--! Project Name: FELIX
-------------------------------------------------------------------------------... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 17/08/2015
--! Module Name: elinkInterface_package
--! Project Name: FELIX
-------------------------------------------------------------------------------... |
-- Nancy Minderman
-- nancy.minderman@ualberta.ca
-- This file makes extensive use of Altera template structures.
-- This file is the top-level file for lab 1 winter 2014 for version 12.1sp1 on Windows 7
-- A library clause declares a name as a library. It
-- does not create the library; it simply forward declares ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity arpServerWrapper is
generic ( keyLength : integer := 32;
valueLength : integer := 48);
Port ( aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
myMacAddr... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity arpServerWrapper is
generic ( keyLength : integer := 32;
valueLength : integer := 48);
Port ( aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
myMacAddr... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity mem_bus_slave_bfm is
generic (
g_name : string;
g_latency : positive := 2 );
port (
clock : in std_logic;
req ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity mem_bus_slave_bfm is
generic (
g_name : string;
g_latency : positive := 2 );
port (
clock : in std_logic;
req ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity mem_bus_slave_bfm is
generic (
g_name : string;
g_latency : positive := 2 );
port (
clock : in std_logic;
req ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity mem_bus_slave_bfm is
generic (
g_name : string;
g_latency : positive := 2 );
port (
clock : in std_logic;
req ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity mem_bus_slave_bfm is
generic (
g_name : string;
g_latency : positive := 2 );
port (
clock : in std_logic;
req ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp_tx - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp_tx - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- ... |
-------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- Description
-- Containing a bridge between a RapidIO network and a Wishbone bus. Packets
-- NWRITE and N... |
-- This file has been automatically generated by go-iec61499-vhdl and should not be edited by hand
-- Converter written by Hammond Pearce and available at github.com/kiwih/go-iec61499-vhdl
-- This file represents the Basic Function Block for ConveyorController
library ieee;
use ieee.std_logic_1164.all;
use ieee.numer... |
-- This file has been automatically generated by go-iec61499-vhdl and should not be edited by hand
-- Converter written by Hammond Pearce and available at github.com/kiwih/go-iec61499-vhdl
-- This file represents the Basic Function Block for ConveyorController
library ieee;
use ieee.std_logic_1164.all;
use ieee.numer... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.all;
entity register_generic is
generic(N: integer);
port( CK: in std_logic;
RESET: in std_logic;
ENABLE: in std_logic;
D: in std_logic_vector(N-1 downto 0);
Q: out std_logic_vector(N-1 downto 0));
end r... |
--------------------------------------------------------------------------------
-- Title : DMA for VME Interface
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : dma.vhd
-- Author : michael.miehling@men.de
-- Organization :... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity lshiftLEDs is
Port ( trigger : in STD_LOGIC;
leds : out STD_LOGIC_VECTOR (7 downto 0));
end lshiftLEDs;
architecture Behavioral of lshiftLEDs is
signal ileds : std_logic_vector(7 downto 0) := "00000001";
begin
leds <= ileds;
process(trigge... |
-------------------------------------------------------------------------------
-- Title : Pipeline
-- Project :
-------------------------------------------------------------------------------
-- File : pipeline.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-06-10
-- Las... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
entity test is
end test;
architecture only of test is
type integer_array is array ( natural range <> ) of integer;
function return_biggest ( inputs : integer_array )
return integer is
variable retval : integer := integer'left;
begin
for i in inputs'range loop
if inputs(i) > retval then
... |
entity test is
end test;
architecture only of test is
type integer_array is array ( natural range <> ) of integer;
function return_biggest ( inputs : integer_array )
return integer is
variable retval : integer := integer'left;
begin
for i in inputs'range loop
if inputs(i) > retval then
... |
entity test is
end test;
architecture only of test is
type integer_array is array ( natural range <> ) of integer;
function return_biggest ( inputs : integer_array )
return integer is
variable retval : integer := integer'left;
begin
for i in inputs'range loop
if inputs(i) > retval then
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Q8_4_ADD is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of Q8_4_ADD is
begin
-----------------------... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
library IEEE;
use IEEE.std_logic_1164.all; -- defines std_logic types
-- 4 axis version with 48 I/O bits
entity HostMot5_4 is
port
(
LRD: in STD_LOGIC;
LWR: in STD_LOGIC;
LW_R: in STD_LOGIC;
ALE: in STD_LOGIC;
ADS: in STD_LOGIC;
BLAST: in STD_LOGIC;
WAITO: in STD_LOGIC;
LOCKO: in STD_... |
-------------------------------------------------------------------------------
-- upcnt_n.vhd entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
-------------------------------------------------------------------------------
-- upcnt_n.vhd entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
-------------------------------------------------------------------------------
-- Title : Multiplier testbench
-- Project :
-------------------------------------------------------------------------------
-- File : multiplier_bench.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
---------------------------------------------------------------------
---- ----
---- OpenCores IDE Controller ----
---- ATA/ATAPI-5 PIO controller with write PingPong ----
---- ... |
---------------------------------------------------------------------
---- ----
---- OpenCores IDE Controller ----
---- ATA/ATAPI-5 PIO controller with write PingPong ----
---- ... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
--... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fa IS
PORT(
a,b,Cin : IN std_logic;
S,Cout : OUT std_logic
);
END ENTITY;
ARCHITECTURE behavior OF fa IS
BEGIN
S <= a XOR b XOR Cin;
Cout <= (a AND b) OR ((a XOR b) AND Cin);
END ARCHITECTURE behavior; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.MATH_REAL.ALL;
entity fm_modulator is Port (
clk, clk_modulator : in STD_LOGIC;
data : in signed (8 downto 0);
fm_out : out STD_LOGIC);
end fm_modulator;
architecture Behavioral of fm_modulator is
constant input_clk : real := ... |
entity repro is
end;
architecture behav of repro is
function f return natural is
begin
return 5;
end f;
constant cst : natural := f;
type rec1 is record
r : bit_vector (1 to cst);
end record;
type rec is record
v : bit_vector;
r : rec1;
end record;
procedure assign (signal s : out... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
m... |
-- $Id: nexys3_fusp_dummy.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either ver... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pr_axis_loopback is
generic (
DATAWIDTH : integer := 64
);
port (
s_axis_data_tdata : in std_logic_vector(DATAWIDTH-1 downto 0);
s_axis_data_tkeep : in std_logic_... |
architecture RTL of ENTITY_NAME is
begin
process
begin
SEL_LABEL : some target := some expression when some condition else
some expression when some condition else
some expression;
SEL_LABEL : some target := some expression when some conditi... |
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 10:34:28 09/09/2015
-- Design Name:
-- Module Name: Challenge1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Descriptio... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-------------------------------------------------------------------------------
-- Title : Register File
-- Project :
-------------------------------------------------------------------------------
-- File : reg_file.vhd
-- Author : Calle <calle@Alukiste>
-- Created : 2012-03-11
-- Platform :
... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_ok_5_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- ... |
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