rtl-llm/vhdl_github · Datasets at Hugging Face

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------------------------------------------------------- --! @author Andrew Powell --! @date March 16, 2017 --! @brief Contains the entity and architecture of the --! Wrapper Plasma-SoC Top Module. ------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.plasoc_cpu_pack.plasoc_cpu; use work.plasoc_int_pack.plasoc_int; use work.plasoc_int_pack.default_interrupt_total; use work.plasoc_timer_pack.plasoc_timer; use work.plasoc_gpio_pack.plasoc_gpio; use work.plasoc_gpio_pack.default_data_out_width; use work.plasoc_gpio_pack.default_data_in_width; use work.plasoc_uart_pack.plasoc_uart; use work.plasoc_0_crossbar_wrap_pack.plasoc_0_crossbar_wrap; use work.plasoc_0_crossbar_wrap_pack.clogb2; use work.plasoc_axi4_full2lite_pack.plasoc_axi4_full2lite; entity axiplasma_wrapper is generic ( lower_app : string := "boot"; upper_app : string := "none"; upper_ext : boolean := true); port( raw_clock : in std_logic; -- 100 MHz on the Nexys 4. raw_nreset : in std_logic; gpio_output : out std_logic_vector(default_data_out_width-1 downto 0); gpio_input : in std_logic_vector(default_data_in_width-1 downto 0); uart_tx : out std_logic; uart_rx : in std_logic; DDR2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 ); DDR2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 ); DDR2_cas_n : out STD_LOGIC; DDR2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR2_cke : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 ); DDR2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 ); DDR2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 ); DDR2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 ); DDR2_odt : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR2_ras_n : out STD_LOGIC; DDR2_we_n : out STD_LOGIC); end axiplasma_wrapper; architecture Behavioral of axiplasma_wrapper is component mig_wrap_wrapper is port ( ACLK : in STD_LOGIC; ARESETN : in STD_LOGIC; DDR2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 ); DDR2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 ); DDR2_cas_n : out STD_LOGIC; DDR2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR2_cke : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 ); DDR2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 ); DDR2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 ); DDR2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 ); DDR2_odt : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR2_ras_n : out STD_LOGIC; DDR2_we_n : out STD_LOGIC; S00_ARESETN : in STD_LOGIC; S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_arready : out STD_LOGIC; S00_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_arvalid : in STD_LOGIC; S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_awready : out STD_LOGIC; S00_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_awvalid : in STD_LOGIC; S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_bready : in STD_LOGIC; S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_bvalid : out STD_LOGIC; S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_rlast : out STD_LOGIC; S00_AXI_rready : in STD_LOGIC; S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_rvalid : out STD_LOGIC; S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_wlast : in STD_LOGIC; S00_AXI_wready : out STD_LOGIC; S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_wvalid : in STD_LOGIC; clk_ref_i : in STD_LOGIC; sys_rst : in STD_LOGIC); end component; -- Component declarations. component bram is generic ( select_app : string := "none"; -- jump, boot, main address_width : integer := 18; data_width : integer := 32; bram_depth : integer := 65536); port( bram_rst_a : in std_logic; bram_clk_a : in std_logic; bram_en_a : in std_logic; bram_we_a : in std_logic_vector(data_width/8-1 downto 0); bram_addr_a : in std_logic_vector(address_width-1 downto 0); bram_wrdata_a : in std_logic_vector(data_width-1 downto 0); bram_rddata_a : out std_logic_vector(data_width-1 downto 0) := (others=>'0')); end component; component axi_cdma_0 is port ( m_axi_aclk : in std_logic; s_axi_lite_aclk : in std_logic; s_axi_lite_aresetn : in std_logic; cdma_introut : out std_logic; s_axi_lite_awready : out std_logic; s_axi_lite_awvalid : in std_logic; s_axi_lite_awaddr : in std_logic_vector(5 downto 0); s_axi_lite_wready : out std_logic; s_axi_lite_wvalid : in std_logic; s_axi_lite_wdata : in std_logic_vector(31 downto 0); s_axi_lite_bready : in std_logic; s_axi_lite_bvalid : out std_logic; s_axi_lite_bresp : out std_logic_vector(1 downto 0); s_axi_lite_arready : out std_logic; s_axi_lite_arvalid : in std_logic; s_axi_lite_araddr : in std_logic_vector(5 downto 0); s_axi_lite_rready : in std_logic; s_axi_lite_rvalid : out std_logic; s_axi_lite_rdata : out std_logic_vector(31 downto 0); s_axi_lite_rresp : out std_logic_vector(1 downto 0); m_axi_arready : in std_logic; m_axi_arvalid : out std_logic; m_axi_araddr : out std_logic_vector(31 downto 0); m_axi_arlen : out std_logic_vector(7 downto 0); m_axi_arsize : out std_logic_vector(2 downto 0); m_axi_arburst : out std_logic_vector(1 downto 0); m_axi_arprot : out std_logic_vector(2 downto 0); m_axi_arcache : out std_logic_vector(3 downto 0); m_axi_rready : out std_logic; m_axi_rvalid : in std_logic; m_axi_rdata : in std_logic_vector(31 downto 0); m_axi_rresp : in std_logic_vector(1 downto 0); m_axi_rlast : in std_logic; m_axi_awready : in std_logic; m_axi_awvalid : out std_logic; m_axi_awaddr : out std_logic_vector(31 downto 0); m_axi_awlen : out std_logic_vector(7 downto 0); m_axi_awsize : out std_logic_vector(2 downto 0); m_axi_awburst : out std_logic_vector(1 downto 0); m_axi_awprot : out std_logic_vector(2 downto 0); m_axi_awcache : out std_logic_vector(3 downto 0); m_axi_wready : in std_logic; m_axi_wvalid : out std_logic; m_axi_wdata : out std_logic_vector(31 downto 0); m_axi_wstrb : out std_logic_vector(3 downto 0); m_axi_wlast : out std_logic; m_axi_bready : out std_logic; m_axi_bvalid : in std_logic; m_axi_bresp : in std_logic_vector(1 downto 0); cdma_tvect_out : out std_logic_vector(31 downto 0)); end component; component clk_wiz_0 is port ( aclk : out std_logic; ddr_aclk : out std_logic; resetn : in std_logic; locked : out std_logic; raw_clock : in std_logic); end component; component proc_sys_reset_0 is port ( slowest_sync_clk : in std_logic; ext_reset_in : in std_logic; aux_reset_in : in std_logic; mb_debug_sys_rst : in std_logic; dcm_locked : in std_logic; mb_reset : out std_logic; bus_struct_reset : out std_logic_vector(0 downto 0); peripheral_reset : out std_logic_vector(0 downto 0); interconnect_aresetn : out std_logic_vector(0 downto 0); peripheral_aresetn : out std_logic_vector(0 downto 0)); end component; component axi_bram_ctrl_0 is port ( s_axi_aclk : in std_logic; s_axi_aresetn : in std_logic; s_axi_awid : in std_logic_vector(0 downto 0); s_axi_awaddr : in std_logic_vector(15 downto 0); s_axi_awlen : in std_logic_vector(7 downto 0); s_axi_awsize : in std_logic_vector(2 downto 0); s_axi_awburst : in std_logic_vector(1 downto 0); s_axi_awlock : in std_logic; s_axi_awcache : in std_logic_vector(3 downto 0); s_axi_awprot : in std_logic_vector(2 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; s_axi_wdata : in std_logic_vector(31 downto 0); s_axi_wstrb : in std_logic_vector(3 downto 0); s_axi_wlast : in std_logic; s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; s_axi_bid : out std_logic_vector(0 downto 0); s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; s_axi_arid : in std_logic_vector(0 downto 0); s_axi_araddr : in std_logic_vector(15 downto 0); s_axi_arlen : in std_logic_vector(7 downto 0); s_axi_arsize : in std_logic_vector(2 downto 0); s_axi_arburst : in std_logic_vector(1 downto 0); s_axi_arlock : in std_logic; s_axi_arcache : in std_logic_vector(3 downto 0); s_axi_arprot : in std_logic_vector(2 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; s_axi_rid : out std_logic_vector(0 downto 0); s_axi_rdata : out std_logic_vector(31 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rlast : out std_logic; s_axi_rvalid : out std_logic; s_axi_rready : in std_logic; bram_rst_a : out std_logic; bram_clk_a : out std_logic; bram_en_a : out std_logic; bram_we_a : out std_logic_vector(3 downto 0); bram_addr_a : out std_logic_vector(15 downto 0); bram_wrdata_a : out std_logic_vector(31 downto 0); bram_rddata_a : in std_logic_vector(31 downto 0)); end component; component axi_bram_ctrl_1 is port ( s_axi_aclk : in std_logic; s_axi_aresetn : in std_logic; s_axi_awid : in std_logic_vector(0 downto 0); s_axi_awaddr : in std_logic_vector(17 downto 0); s_axi_awlen : in std_logic_vector(7 downto 0); s_axi_awsize : in std_logic_vector(2 downto 0); s_axi_awburst : in std_logic_vector(1 downto 0); s_axi_awlock : in std_logic; s_axi_awcache : in std_logic_vector(3 downto 0); s_axi_awprot : in std_logic_vector(2 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; s_axi_wdata : in std_logic_vector(31 downto 0); s_axi_wstrb : in std_logic_vector(3 downto 0); s_axi_wlast : in std_logic; s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; s_axi_bid : out std_logic_vector(0 downto 0); s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; s_axi_arid : in std_logic_vector(0 downto 0); s_axi_araddr : in std_logic_vector(17 downto 0); s_axi_arlen : in std_logic_vector(7 downto 0); s_axi_arsize : in std_logic_vector(2 downto 0); s_axi_arburst : in std_logic_vector(1 downto 0); s_axi_arlock : in std_logic; s_axi_arcache : in std_logic_vector(3 downto 0); s_axi_arprot : in std_logic_vector(2 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; s_axi_rid : out std_logic_vector(0 downto 0); s_axi_rdata : out std_logic_vector(31 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rlast : out std_logic; s_axi_rvalid : out std_logic; s_axi_rready : in std_logic; bram_rst_a : out std_logic; bram_clk_a : out std_logic; bram_en_a : out std_logic; bram_we_a : out std_logic_vector(3 downto 0); bram_addr_a : out std_logic_vector(17 downto 0); bram_wrdata_a : out std_logic_vector(31 downto 0); bram_rddata_a : in std_logic_vector(31 downto 0)); end component; constant axi_address_width : integer := 32; constant axi_data_width : integer := 32; constant axi_master_amount : integer := 5; constant axi_slave_amount : integer := 2; constant axi_slave_id_width : integer := 0; constant axi_master_id_width : integer := clogb2(axi_slave_amount)+axi_slave_id_width; constant axi_lite_address_width : integer := 16; -- a misnomer. constant axi_ram_address_width : integer := 18; constant axi_ram_depth : integer := 65536; signal aclk : std_logic; signal ddr_aclk : std_logic; signal aresetn : std_logic_vector(0 downto 0); signal cross_aresetn : std_logic_vector(0 downto 0); signal dcm_locked : std_logic; signal cpu_axi_full_awid : std_logic_vector(axi_slave_id_width-1 downto 0); signal cpu_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0); signal cpu_axi_full_awlen : std_logic_vector(7 downto 0); signal cpu_axi_full_awsize : std_logic_vector(2 downto 0); signal cpu_axi_full_awburst : std_logic_vector(1 downto 0); signal cpu_axi_full_awlock : std_logic; signal cpu_axi_full_awcache : std_logic_vector(3 downto 0); signal cpu_axi_full_awprot : std_logic_vector(2 downto 0); signal cpu_axi_full_awqos : std_logic_vector(3 downto 0); signal cpu_axi_full_awregion : std_logic_vector(3 downto 0); signal cpu_axi_full_awvalid : std_logic; signal cpu_axi_full_awready : std_logic; signal cpu_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0); signal cpu_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal cpu_axi_full_wlast : std_logic; signal cpu_axi_full_wvalid : std_logic; signal cpu_axi_full_wready : std_logic; signal cpu_axi_full_bid : std_logic_vector(axi_slave_id_width-1 downto 0); signal cpu_axi_full_bresp : std_logic_vector(1 downto 0); signal cpu_axi_full_bvalid : std_logic; signal cpu_axi_full_bready : std_logic; signal cpu_axi_full_arid : std_logic_vector(axi_slave_id_width-1 downto 0); signal cpu_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0); signal cpu_axi_full_arlen : std_logic_vector(7 downto 0); signal cpu_axi_full_arsize : std_logic_vector(2 downto 0); signal cpu_axi_full_arburst : std_logic_vector(1 downto 0); signal cpu_axi_full_arlock : std_logic; signal cpu_axi_full_arcache : std_logic_vector(3 downto 0); signal cpu_axi_full_arprot : std_logic_vector(2 downto 0); signal cpu_axi_full_arqos : std_logic_vector(3 downto 0); signal cpu_axi_full_arregion : std_logic_vector(3 downto 0); signal cpu_axi_full_arvalid : std_logic; signal cpu_axi_full_arready : std_logic; signal cpu_axi_full_rid : std_logic_vector(axi_slave_id_width-1 downto 0); signal cpu_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0); signal cpu_axi_full_rresp : std_logic_vector(1 downto 0); signal cpu_axi_full_rlast : std_logic; signal cpu_axi_full_rvalid : std_logic; signal cpu_axi_full_rready : std_logic; signal cdma_axi_full_awid : std_logic_vector(axi_slave_id_width-1 downto 0); signal cdma_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0); signal cdma_axi_full_awlen : std_logic_vector(7 downto 0); signal cdma_axi_full_awsize : std_logic_vector(2 downto 0); signal cdma_axi_full_awburst : std_logic_vector(1 downto 0); signal cdma_axi_full_awlock : std_logic; signal cdma_axi_full_awcache : std_logic_vector(3 downto 0); signal cdma_axi_full_awprot : std_logic_vector(2 downto 0); signal cdma_axi_full_awqos : std_logic_vector(3 downto 0); signal cdma_axi_full_awregion : std_logic_vector(3 downto 0); signal cdma_axi_full_awvalid : std_logic; signal cdma_axi_full_awready : std_logic; signal cdma_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0); signal cdma_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal cdma_axi_full_wlast : std_logic; signal cdma_axi_full_wvalid : std_logic; signal cdma_axi_full_wready : std_logic; signal cdma_axi_full_bid : std_logic_vector(axi_slave_id_width-1 downto 0); signal cdma_axi_full_bresp : std_logic_vector(1 downto 0); signal cdma_axi_full_bvalid : std_logic; signal cdma_axi_full_bready : std_logic; signal cdma_axi_full_arid : std_logic_vector(axi_slave_id_width-1 downto 0); signal cdma_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0); signal cdma_axi_full_arlen : std_logic_vector(7 downto 0); signal cdma_axi_full_arsize : std_logic_vector(2 downto 0); signal cdma_axi_full_arburst : std_logic_vector(1 downto 0); signal cdma_axi_full_arlock : std_logic; signal cdma_axi_full_arcache : std_logic_vector(3 downto 0); signal cdma_axi_full_arprot : std_logic_vector(2 downto 0); signal cdma_axi_full_arqos : std_logic_vector(3 downto 0); signal cdma_axi_full_arregion : std_logic_vector(3 downto 0); signal cdma_axi_full_arvalid : std_logic; signal cdma_axi_full_arready : std_logic; signal cdma_axi_full_rid : std_logic_vector(axi_slave_id_width-1 downto 0); signal cdma_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0); signal cdma_axi_full_rresp : std_logic_vector(1 downto 0); signal cdma_axi_full_rlast : std_logic; signal cdma_axi_full_rvalid : std_logic; signal cdma_axi_full_rready : std_logic; signal bram_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0); signal bram_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0); signal bram_axi_full_awlen : std_logic_vector(7 downto 0); signal bram_axi_full_awsize : std_logic_vector(2 downto 0); signal bram_axi_full_awburst : std_logic_vector(1 downto 0); signal bram_axi_full_awlock : std_logic; signal bram_axi_full_awcache : std_logic_vector(3 downto 0); signal bram_axi_full_awprot : std_logic_vector(2 downto 0); signal bram_axi_full_awqos : std_logic_vector(3 downto 0); signal bram_axi_full_awregion : std_logic_vector(3 downto 0); signal bram_axi_full_awvalid : std_logic; signal bram_axi_full_awready : std_logic; signal bram_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0); signal bram_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal bram_axi_full_wlast : std_logic; signal bram_axi_full_wvalid : std_logic; signal bram_axi_full_wready : std_logic; signal bram_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0); signal bram_axi_full_bresp : std_logic_vector(1 downto 0); signal bram_axi_full_bvalid : std_logic; signal bram_axi_full_bready : std_logic; signal bram_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0); signal bram_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0); signal bram_axi_full_arlen : std_logic_vector(7 downto 0); signal bram_axi_full_arsize : std_logic_vector(2 downto 0); signal bram_axi_full_arburst : std_logic_vector(1 downto 0); signal bram_axi_full_arlock : std_logic; signal bram_axi_full_arcache : std_logic_vector(3 downto 0); signal bram_axi_full_arprot : std_logic_vector(2 downto 0); signal bram_axi_full_arqos : std_logic_vector(3 downto 0); signal bram_axi_full_arregion : std_logic_vector(3 downto 0); signal bram_axi_full_arvalid : std_logic; signal bram_axi_full_arready : std_logic; signal bram_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0); signal bram_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0); signal bram_axi_full_rresp : std_logic_vector(1 downto 0); signal bram_axi_full_rlast : std_logic; signal bram_axi_full_rvalid : std_logic; signal bram_axi_full_rready : std_logic; signal bram_bram_rst_a : STD_LOGIC; signal bram_bram_clk_a : STD_LOGIC; signal bram_bram_en_a : STD_LOGIC; signal bram_bram_we_a : STD_LOGIC_VECTOR(axi_data_width/8-1 DOWNTO 0); signal bram_bram_addr_a : STD_LOGIC_VECTOR(axi_lite_address_width-1 DOWNTO 0); signal bram_bram_wrdata_a : STD_LOGIC_VECTOR(axi_data_width-1 DOWNTO 0); signal bram_bram_rddata_a : STD_LOGIC_VECTOR(axi_data_width-1 DOWNTO 0); signal ram_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0); signal ram_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0); signal ram_axi_full_awlen : std_logic_vector(7 downto 0); signal ram_axi_full_awsize : std_logic_vector(2 downto 0); signal ram_axi_full_awburst : std_logic_vector(1 downto 0); signal ram_axi_full_awlock : std_logic; signal ram_axi_full_awcache : std_logic_vector(3 downto 0); signal ram_axi_full_awprot : std_logic_vector(2 downto 0); signal ram_axi_full_awqos : std_logic_vector(3 downto 0); signal ram_axi_full_awregion : std_logic_vector(3 downto 0); signal ram_axi_full_awvalid : std_logic; signal ram_axi_full_awready : std_logic; signal ram_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0); signal ram_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal ram_axi_full_wlast : std_logic; signal ram_axi_full_wvalid : std_logic; signal ram_axi_full_wready : std_logic; signal ram_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0); signal ram_axi_full_bresp : std_logic_vector(1 downto 0); signal ram_axi_full_bvalid : std_logic; signal ram_axi_full_bready : std_logic; signal ram_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0); signal ram_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0); signal ram_axi_full_arlen : std_logic_vector(7 downto 0); signal ram_axi_full_arsize : std_logic_vector(2 downto 0); signal ram_axi_full_arburst : std_logic_vector(1 downto 0); signal ram_axi_full_arlock : std_logic; signal ram_axi_full_arcache : std_logic_vector(3 downto 0); signal ram_axi_full_arprot : std_logic_vector(2 downto 0); signal ram_axi_full_arqos : std_logic_vector(3 downto 0); signal ram_axi_full_arregion : std_logic_vector(3 downto 0); signal ram_axi_full_arvalid : std_logic; signal ram_axi_full_arready : std_logic; signal ram_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0); signal ram_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0); signal ram_axi_full_rresp : std_logic_vector(1 downto 0); signal ram_axi_full_rlast : std_logic; signal ram_axi_full_rvalid : std_logic; signal ram_axi_full_rready : std_logic; signal ram_axi_full_arlock_slv : std_logic_vector (0 downto 0); signal ram_axi_full_awlock_slv : std_logic_vector (0 downto 0); signal ram_axi_full_arid_slv : std_logic_vector(3 downto 0) := (others=>'0'); signal ram_axi_full_awid_slv : std_logic_vector(3 downto 0) := (others=>'0'); signal ram_axi_full_bid_slv : std_logic_vector(3 downto 0) := (others=>'0'); signal ram_axi_full_rid_slv : std_logic_vector(3 downto 0) := (others=>'0'); signal ram_bram_rst_a : std_logic; signal ram_bram_clk_a : std_logic; signal ram_bram_en_a : std_logic; signal ram_bram_we_a : std_logic_vector(axi_data_width/8-1 downto 0); signal ram_bram_addr_a : std_logic_vector(axi_ram_address_width-1 downto 0); signal ram_bram_wrdata_a : std_logic_vector(axi_data_width-1 downto 0); signal ram_bram_rddata_a : std_logic_vector(axi_data_width-1 downto 0); signal int_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0); signal int_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0); signal int_axi_full_awlen : std_logic_vector(7 downto 0); signal int_axi_full_awsize : std_logic_vector(2 downto 0); signal int_axi_full_awburst : std_logic_vector(1 downto 0); signal int_axi_full_awlock : std_logic; signal int_axi_full_awcache : std_logic_vector(3 downto 0); signal int_axi_full_awprot : std_logic_vector(2 downto 0); signal int_axi_full_awqos : std_logic_vector(3 downto 0); signal int_axi_full_awregion : std_logic_vector(3 downto 0); signal int_axi_full_awvalid : std_logic; signal int_axi_full_awready : std_logic; signal int_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0); signal int_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal int_axi_full_wlast : std_logic; signal int_axi_full_wvalid : std_logic; signal int_axi_full_wready : std_logic; signal int_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0); signal int_axi_full_bresp : std_logic_vector(1 downto 0); signal int_axi_full_bvalid : std_logic; signal int_axi_full_bready : std_logic; signal int_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0); signal int_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0); signal int_axi_full_arlen : std_logic_vector(7 downto 0); signal int_axi_full_arsize : std_logic_vector(2 downto 0); signal int_axi_full_arburst : std_logic_vector(1 downto 0); signal int_axi_full_arlock : std_logic; signal int_axi_full_arcache : std_logic_vector(3 downto 0); signal int_axi_full_arprot : std_logic_vector(2 downto 0); signal int_axi_full_arqos : std_logic_vector(3 downto 0); signal int_axi_full_arregion : std_logic_vector(3 downto 0); signal int_axi_full_arvalid : std_logic; signal int_axi_full_arready : std_logic; signal int_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0); signal int_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0); signal int_axi_full_rresp : std_logic_vector(1 downto 0); signal int_axi_full_rlast : std_logic; signal int_axi_full_rvalid : std_logic; signal int_axi_full_rready : std_logic; signal timer_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0); signal timer_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0); signal timer_axi_full_awlen : std_logic_vector(7 downto 0); signal timer_axi_full_awsize : std_logic_vector(2 downto 0); signal timer_axi_full_awburst : std_logic_vector(1 downto 0); signal timer_axi_full_awlock : std_logic; signal timer_axi_full_awcache : std_logic_vector(3 downto 0); signal timer_axi_full_awprot : std_logic_vector(2 downto 0); signal timer_axi_full_awqos : std_logic_vector(3 downto 0); signal timer_axi_full_awregion : std_logic_vector(3 downto 0); signal timer_axi_full_awvalid : std_logic; signal timer_axi_full_awready : std_logic; signal timer_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0); signal timer_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal timer_axi_full_wlast : std_logic; signal timer_axi_full_wvalid : std_logic; signal timer_axi_full_wready : std_logic; signal timer_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0); signal timer_axi_full_bresp : std_logic_vector(1 downto 0); signal timer_axi_full_bvalid : std_logic; signal timer_axi_full_bready : std_logic; signal timer_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0); signal timer_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0); signal timer_axi_full_arlen : std_logic_vector(7 downto 0); signal timer_axi_full_arsize : std_logic_vector(2 downto 0); signal timer_axi_full_arburst : std_logic_vector(1 downto 0); signal timer_axi_full_arlock : std_logic; signal timer_axi_full_arcache : std_logic_vector(3 downto 0); signal timer_axi_full_arprot : std_logic_vector(2 downto 0); signal timer_axi_full_arqos : std_logic_vector(3 downto 0); signal timer_axi_full_arregion : std_logic_vector(3 downto 0); signal timer_axi_full_arvalid : std_logic; signal timer_axi_full_arready : std_logic; signal timer_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0); signal timer_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0); signal timer_axi_full_rresp : std_logic_vector(1 downto 0); signal timer_axi_full_rlast : std_logic; signal timer_axi_full_rvalid : std_logic; signal timer_axi_full_rready : std_logic; signal gpio_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0); signal gpio_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0); signal gpio_axi_full_awlen : std_logic_vector(7 downto 0); signal gpio_axi_full_awsize : std_logic_vector(2 downto 0); signal gpio_axi_full_awburst : std_logic_vector(1 downto 0); signal gpio_axi_full_awlock : std_logic; signal gpio_axi_full_awcache : std_logic_vector(3 downto 0); signal gpio_axi_full_awprot : std_logic_vector(2 downto 0); signal gpio_axi_full_awqos : std_logic_vector(3 downto 0); signal gpio_axi_full_awregion : std_logic_vector(3 downto 0); signal gpio_axi_full_awvalid : std_logic; signal gpio_axi_full_awready : std_logic; signal gpio_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0); signal gpio_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal gpio_axi_full_wlast : std_logic; signal gpio_axi_full_wvalid : std_logic; signal gpio_axi_full_wready : std_logic; signal gpio_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0); signal gpio_axi_full_bresp : std_logic_vector(1 downto 0); signal gpio_axi_full_bvalid : std_logic; signal gpio_axi_full_bready : std_logic; signal gpio_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0); signal gpio_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0); signal gpio_axi_full_arlen : std_logic_vector(7 downto 0); signal gpio_axi_full_arsize : std_logic_vector(2 downto 0); signal gpio_axi_full_arburst : std_logic_vector(1 downto 0); signal gpio_axi_full_arlock : std_logic; signal gpio_axi_full_arcache : std_logic_vector(3 downto 0); signal gpio_axi_full_arprot : std_logic_vector(2 downto 0); signal gpio_axi_full_arqos : std_logic_vector(3 downto 0); signal gpio_axi_full_arregion : std_logic_vector(3 downto 0); signal gpio_axi_full_arvalid : std_logic; signal gpio_axi_full_arready : std_logic; signal gpio_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0); signal gpio_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0); signal gpio_axi_full_rresp : std_logic_vector(1 downto 0); signal gpio_axi_full_rlast : std_logic; signal gpio_axi_full_rvalid : std_logic; signal gpio_axi_full_rready : std_logic; signal cdmareg_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0); signal cdmareg_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0); signal cdmareg_axi_full_awlen : std_logic_vector(7 downto 0); signal cdmareg_axi_full_awsize : std_logic_vector(2 downto 0); signal cdmareg_axi_full_awburst : std_logic_vector(1 downto 0); signal cdmareg_axi_full_awlock : std_logic; signal cdmareg_axi_full_awcache : std_logic_vector(3 downto 0); signal cdmareg_axi_full_awprot : std_logic_vector(2 downto 0); signal cdmareg_axi_full_awqos : std_logic_vector(3 downto 0); signal cdmareg_axi_full_awregion : std_logic_vector(3 downto 0); signal cdmareg_axi_full_awvalid : std_logic; signal cdmareg_axi_full_awready : std_logic; signal cdmareg_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0); signal cdmareg_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal cdmareg_axi_full_wlast : std_logic; signal cdmareg_axi_full_wvalid : std_logic; signal cdmareg_axi_full_wready : std_logic; signal cdmareg_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0); signal cdmareg_axi_full_bresp : std_logic_vector(1 downto 0); signal cdmareg_axi_full_bvalid : std_logic; signal cdmareg_axi_full_bready : std_logic; signal cdmareg_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0); signal cdmareg_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0); signal cdmareg_axi_full_arlen : std_logic_vector(7 downto 0); signal cdmareg_axi_full_arsize : std_logic_vector(2 downto 0); signal cdmareg_axi_full_arburst : std_logic_vector(1 downto 0); signal cdmareg_axi_full_arlock : std_logic; signal cdmareg_axi_full_arcache : std_logic_vector(3 downto 0); signal cdmareg_axi_full_arprot : std_logic_vector(2 downto 0); signal cdmareg_axi_full_arqos : std_logic_vector(3 downto 0); signal cdmareg_axi_full_arregion : std_logic_vector(3 downto 0); signal cdmareg_axi_full_arvalid : std_logic; signal cdmareg_axi_full_arready : std_logic; signal cdmareg_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0); signal cdmareg_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0); signal cdmareg_axi_full_rresp : std_logic_vector(1 downto 0); signal cdmareg_axi_full_rlast : std_logic; signal cdmareg_axi_full_rvalid : std_logic; signal cdmareg_axi_full_rready : std_logic; signal timer_extra_0_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0); signal timer_extra_0_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0); signal timer_extra_0_axi_full_awlen : std_logic_vector(7 downto 0); signal timer_extra_0_axi_full_awsize : std_logic_vector(2 downto 0); signal timer_extra_0_axi_full_awburst : std_logic_vector(1 downto 0); signal timer_extra_0_axi_full_awlock : std_logic; signal timer_extra_0_axi_full_awcache : std_logic_vector(3 downto 0); signal timer_extra_0_axi_full_awprot : std_logic_vector(2 downto 0); signal timer_extra_0_axi_full_awqos : std_logic_vector(3 downto 0); signal timer_extra_0_axi_full_awregion : std_logic_vector(3 downto 0); signal timer_extra_0_axi_full_awvalid : std_logic; signal timer_extra_0_axi_full_awready : std_logic; signal timer_extra_0_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0); signal timer_extra_0_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal timer_extra_0_axi_full_wlast : std_logic; signal timer_extra_0_axi_full_wvalid : std_logic; signal timer_extra_0_axi_full_wready : std_logic; signal timer_extra_0_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0); signal timer_extra_0_axi_full_bresp : std_logic_vector(1 downto 0); signal timer_extra_0_axi_full_bvalid : std_logic; signal timer_extra_0_axi_full_bready : std_logic; signal timer_extra_0_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0); signal timer_extra_0_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0); signal timer_extra_0_axi_full_arlen : std_logic_vector(7 downto 0); signal timer_extra_0_axi_full_arsize : std_logic_vector(2 downto 0); signal timer_extra_0_axi_full_arburst : std_logic_vector(1 downto 0); signal timer_extra_0_axi_full_arlock : std_logic; signal timer_extra_0_axi_full_arcache : std_logic_vector(3 downto 0); signal timer_extra_0_axi_full_arprot : std_logic_vector(2 downto 0); signal timer_extra_0_axi_full_arqos : std_logic_vector(3 downto 0); signal timer_extra_0_axi_full_arregion : std_logic_vector(3 downto 0); signal timer_extra_0_axi_full_arvalid : std_logic; signal timer_extra_0_axi_full_arready : std_logic; signal timer_extra_0_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0); signal timer_extra_0_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0); signal timer_extra_0_axi_full_rresp : std_logic_vector(1 downto 0); signal timer_extra_0_axi_full_rlast : std_logic; signal timer_extra_0_axi_full_rvalid : std_logic; signal timer_extra_0_axi_full_rready : std_logic; signal uart_axi_full_awid : std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0); signal uart_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0); signal uart_axi_full_awlen : std_logic_vector(7 downto 0); signal uart_axi_full_awsize : std_logic_vector(2 downto 0); signal uart_axi_full_awburst : std_logic_vector(1 downto 0); signal uart_axi_full_awlock : std_logic; signal uart_axi_full_awcache : std_logic_vector(3 downto 0); signal uart_axi_full_awprot : std_logic_vector(2 downto 0); signal uart_axi_full_awqos : std_logic_vector(3 downto 0); signal uart_axi_full_awregion : std_logic_vector(3 downto 0); signal uart_axi_full_awvalid : std_logic; signal uart_axi_full_awready : std_logic; signal uart_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0); signal uart_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal uart_axi_full_wlast : std_logic; signal uart_axi_full_wvalid : std_logic; signal uart_axi_full_wready : std_logic; signal uart_axi_full_bid : std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0); signal uart_axi_full_bresp : std_logic_vector(1 downto 0); signal uart_axi_full_bvalid : std_logic; signal uart_axi_full_bready : std_logic; signal uart_axi_full_arid : std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0); signal uart_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0); signal uart_axi_full_arlen : std_logic_vector(7 downto 0); signal uart_axi_full_arsize : std_logic_vector(2 downto 0); signal uart_axi_full_arburst : std_logic_vector(1 downto 0); signal uart_axi_full_arlock : std_logic; signal uart_axi_full_arcache : std_logic_vector(3 downto 0); signal uart_axi_full_arprot : std_logic_vector(2 downto 0); signal uart_axi_full_arqos : std_logic_vector(3 downto 0); signal uart_axi_full_arregion : std_logic_vector(3 downto 0); signal uart_axi_full_arvalid : std_logic; signal uart_axi_full_arready : std_logic; signal uart_axi_full_rid : std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0); signal uart_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0); signal uart_axi_full_rresp : std_logic_vector(1 downto 0); signal uart_axi_full_rlast : std_logic; signal uart_axi_full_rvalid : std_logic; signal uart_axi_full_rready : std_logic; signal int_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal int_axi_lite_awprot : std_logic_vector(2 downto 0); signal int_axi_lite_awvalid : std_logic; signal int_axi_lite_awready : std_logic; signal int_axi_lite_wvalid : std_logic; signal int_axi_lite_wready : std_logic; signal int_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0); signal int_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal int_axi_lite_bvalid : std_logic; signal int_axi_lite_bready : std_logic; signal int_axi_lite_bresp : std_logic_vector(1 downto 0); signal int_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal int_axi_lite_arprot : std_logic_vector(2 downto 0); signal int_axi_lite_arvalid : std_logic; signal int_axi_lite_arready : std_logic; signal int_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); signal int_axi_lite_rvalid : std_logic; signal int_axi_lite_rready : std_logic; signal int_axi_lite_rresp : std_logic_vector(1 downto 0); signal timer_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal timer_axi_lite_awprot : std_logic_vector(2 downto 0); signal timer_axi_lite_awvalid : std_logic; signal timer_axi_lite_awready : std_logic; signal timer_axi_lite_wvalid : std_logic; signal timer_axi_lite_wready : std_logic; signal timer_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0); signal timer_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal timer_axi_lite_bvalid : std_logic; signal timer_axi_lite_bready : std_logic; signal timer_axi_lite_bresp : std_logic_vector(1 downto 0); signal timer_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal timer_axi_lite_arprot : std_logic_vector(2 downto 0); signal timer_axi_lite_arvalid : std_logic; signal timer_axi_lite_arready : std_logic; signal timer_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); signal timer_axi_lite_rvalid : std_logic; signal timer_axi_lite_rready : std_logic; signal timer_axi_lite_rresp : std_logic_vector(1 downto 0); signal gpio_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal gpio_axi_lite_awprot : std_logic_vector(2 downto 0); signal gpio_axi_lite_awvalid : std_logic; signal gpio_axi_lite_awready : std_logic; signal gpio_axi_lite_wvalid : std_logic; signal gpio_axi_lite_wready : std_logic; signal gpio_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0); signal gpio_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal gpio_axi_lite_bvalid : std_logic; signal gpio_axi_lite_bready : std_logic; signal gpio_axi_lite_bresp : std_logic_vector(1 downto 0); signal gpio_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal gpio_axi_lite_arprot : std_logic_vector(2 downto 0); signal gpio_axi_lite_arvalid : std_logic; signal gpio_axi_lite_arready : std_logic; signal gpio_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); signal gpio_axi_lite_rvalid : std_logic; signal gpio_axi_lite_rready : std_logic; signal gpio_axi_lite_rresp : std_logic_vector(1 downto 0); signal cdmareg_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal cdmareg_axi_lite_awprot : std_logic_vector(2 downto 0); signal cdmareg_axi_lite_awvalid : std_logic; signal cdmareg_axi_lite_awready : std_logic; signal cdmareg_axi_lite_wvalid : std_logic; signal cdmareg_axi_lite_wready : std_logic; signal cdmareg_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0); signal cdmareg_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal cdmareg_axi_lite_bvalid : std_logic; signal cdmareg_axi_lite_bready : std_logic; signal cdmareg_axi_lite_bresp : std_logic_vector(1 downto 0); signal cdmareg_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal cdmareg_axi_lite_arprot : std_logic_vector(2 downto 0); signal cdmareg_axi_lite_arvalid : std_logic; signal cdmareg_axi_lite_arready : std_logic; signal cdmareg_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); signal cdmareg_axi_lite_rvalid : std_logic; signal cdmareg_axi_lite_rready : std_logic; signal cdmareg_axi_lite_rresp : std_logic_vector(1 downto 0); signal uart_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal uart_axi_lite_awprot : std_logic_vector(2 downto 0); signal uart_axi_lite_awvalid : std_logic; signal uart_axi_lite_awready : std_logic; signal uart_axi_lite_wvalid : std_logic; signal uart_axi_lite_wready : std_logic; signal uart_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0); signal uart_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal uart_axi_lite_bvalid : std_logic; signal uart_axi_lite_bready : std_logic; signal uart_axi_lite_bresp : std_logic_vector(1 downto 0); signal uart_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal uart_axi_lite_arprot : std_logic_vector(2 downto 0); signal uart_axi_lite_arvalid : std_logic; signal uart_axi_lite_arready : std_logic; signal uart_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0); signal uart_axi_lite_rvalid : std_logic; signal uart_axi_lite_rready : std_logic; signal uart_axi_lite_rresp : std_logic_vector(1 downto 0); signal timer_extra_0_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal timer_extra_0_axi_lite_awprot : std_logic_vector(2 downto 0); signal timer_extra_0_axi_lite_awvalid : std_logic; signal timer_extra_0_axi_lite_awready : std_logic; signal timer_extra_0_axi_lite_wvalid : std_logic; signal timer_extra_0_axi_lite_wready : std_logic; signal timer_extra_0_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0); signal timer_extra_0_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal timer_extra_0_axi_lite_bvalid : std_logic; signal timer_extra_0_axi_lite_bready : std_logic; signal timer_extra_0_axi_lite_bresp : std_logic_vector(1 downto 0); signal timer_extra_0_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal timer_extra_0_axi_lite_arprot : std_logic_vector(2 downto 0); signal timer_extra_0_axi_lite_arvalid : std_logic; signal timer_extra_0_axi_lite_arready : std_logic; signal timer_extra_0_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0); signal timer_extra_0_axi_lite_rvalid : std_logic; signal timer_extra_0_axi_lite_rready : std_logic; signal timer_extra_0_axi_lite_rresp : std_logic_vector(1 downto 0); signal cpu_int : std_logic; signal int_dev_ints : std_logic_vector(default_interrupt_total-1 downto 0) := (others=>'0'); signal timer_int : std_logic; signal gpio_int : std_logic; signal cdma_int : std_logic; signal uart_int : std_logic; signal timer_extra_0_int : std_logic; begin int_dev_ints(0) <= timer_int; int_dev_ints(1) <= gpio_int; int_dev_ints(2) <= cdma_int; int_dev_ints(3) <= uart_int; int_dev_ints(4) <= timer_extra_0_int; cdma_axi_full_awlock <= '0'; cdma_axi_full_arlock <= '0'; ram_axi_full_arlock_slv(0) <= ram_axi_full_arlock; ram_axi_full_awlock_slv(0) <= ram_axi_full_awlock; ram_axi_full_arid_slv(axi_master_id_width-1 downto 0) <= ram_axi_full_arid; ram_axi_full_awid_slv(axi_master_id_width-1 downto 0) <= ram_axi_full_awid; ram_axi_full_bid_slv(axi_master_id_width-1 downto 0) <= ram_axi_full_bid; ram_axi_full_rid_slv(axi_master_id_width-1 downto 0) <= ram_axi_full_rid; -- Clock instantiation. clk_wiz_inst : clk_wiz_0 port map ( aclk => aclk, ddr_aclk => ddr_aclk, resetn => raw_nreset, locked => dcm_locked, raw_clock => raw_clock); -- Reset core instantiation. proc_sys_reset_inst : proc_sys_reset_0 PORT map ( slowest_sync_clk => aclk, ext_reset_in => raw_nreset, aux_reset_in => '0', mb_debug_sys_rst => '0', dcm_locked => dcm_locked, mb_reset => open, bus_struct_reset => open, peripheral_reset => open, interconnect_aresetn => cross_aresetn, peripheral_aresetn => aresetn); -- Crossbar instantiation. plasoc_0_crossbar_wrap_inst : plasoc_0_crossbar_wrap port map ( cpu_s_axi_awid => cpu_axi_full_awid, cpu_s_axi_awaddr => cpu_axi_full_awaddr, cpu_s_axi_awlen => cpu_axi_full_awlen, cpu_s_axi_awsize => cpu_axi_full_awsize, cpu_s_axi_awburst => cpu_axi_full_awburst, cpu_s_axi_awlock => cpu_axi_full_awlock, cpu_s_axi_awcache => cpu_axi_full_awcache, cpu_s_axi_awprot => cpu_axi_full_awprot, cpu_s_axi_awqos => cpu_axi_full_awqos, cpu_s_axi_awregion => cpu_axi_full_awregion, cpu_s_axi_awvalid => cpu_axi_full_awvalid, cpu_s_axi_awready => cpu_axi_full_awready, cpu_s_axi_wdata => cpu_axi_full_wdata, cpu_s_axi_wstrb => cpu_axi_full_wstrb, cpu_s_axi_wlast => cpu_axi_full_wlast, cpu_s_axi_wvalid => cpu_axi_full_wvalid, cpu_s_axi_wready => cpu_axi_full_wready, cpu_s_axi_bid => cpu_axi_full_bid, cpu_s_axi_bresp => cpu_axi_full_bresp, cpu_s_axi_bvalid => cpu_axi_full_bvalid, cpu_s_axi_bready => cpu_axi_full_bready, cpu_s_axi_arid => cpu_axi_full_arid, cpu_s_axi_araddr => cpu_axi_full_araddr, cpu_s_axi_arlen => cpu_axi_full_arlen, cpu_s_axi_arsize => cpu_axi_full_arsize, cpu_s_axi_arburst => cpu_axi_full_arburst, cpu_s_axi_arlock => cpu_axi_full_arlock, cpu_s_axi_arcache => cpu_axi_full_arcache, cpu_s_axi_arprot => cpu_axi_full_arprot, cpu_s_axi_arqos => cpu_axi_full_arqos, cpu_s_axi_arregion => cpu_axi_full_arregion, cpu_s_axi_arvalid => cpu_axi_full_arvalid, cpu_s_axi_arready => cpu_axi_full_arready, cpu_s_axi_rid => cpu_axi_full_rid, cpu_s_axi_rdata => cpu_axi_full_rdata, cpu_s_axi_rresp => cpu_axi_full_rresp, cpu_s_axi_rlast => cpu_axi_full_rlast, cpu_s_axi_rvalid => cpu_axi_full_rvalid, cpu_s_axi_rready => cpu_axi_full_rready, cdma_s_axi_awid => cdma_axi_full_awid, cdma_s_axi_awaddr => cdma_axi_full_awaddr, cdma_s_axi_awlen => cdma_axi_full_awlen, cdma_s_axi_awsize => cdma_axi_full_awsize, cdma_s_axi_awburst => cdma_axi_full_awburst, cdma_s_axi_awlock => cdma_axi_full_awlock, cdma_s_axi_awcache => cdma_axi_full_awcache, cdma_s_axi_awprot => cdma_axi_full_awprot, cdma_s_axi_awqos => cdma_axi_full_awqos, cdma_s_axi_awregion => cdma_axi_full_awregion, cdma_s_axi_awvalid => cdma_axi_full_awvalid, cdma_s_axi_awready => cdma_axi_full_awready, cdma_s_axi_wdata => cdma_axi_full_wdata, cdma_s_axi_wstrb => cdma_axi_full_wstrb, cdma_s_axi_wlast => cdma_axi_full_wlast, cdma_s_axi_wvalid => cdma_axi_full_wvalid, cdma_s_axi_wready => cdma_axi_full_wready, cdma_s_axi_bid => cdma_axi_full_bid, cdma_s_axi_bresp => cdma_axi_full_bresp, cdma_s_axi_bvalid => cdma_axi_full_bvalid, cdma_s_axi_bready => cdma_axi_full_bready, cdma_s_axi_arid => cdma_axi_full_arid, cdma_s_axi_araddr => cdma_axi_full_araddr, cdma_s_axi_arlen => cdma_axi_full_arlen, cdma_s_axi_arsize => cdma_axi_full_arsize, cdma_s_axi_arburst => cdma_axi_full_arburst, cdma_s_axi_arlock => cdma_axi_full_arlock, cdma_s_axi_arcache => cdma_axi_full_arcache, cdma_s_axi_arprot => cdma_axi_full_arprot, cdma_s_axi_arqos => cdma_axi_full_arqos, cdma_s_axi_arregion => cdma_axi_full_arregion, cdma_s_axi_arvalid => cdma_axi_full_arvalid, cdma_s_axi_arready => cdma_axi_full_arready, cdma_s_axi_rid => cdma_axi_full_rid, cdma_s_axi_rdata => cdma_axi_full_rdata, cdma_s_axi_rresp => cdma_axi_full_rresp, cdma_s_axi_rlast => cdma_axi_full_rlast, cdma_s_axi_rvalid => cdma_axi_full_rvalid, cdma_s_axi_rready => cdma_axi_full_rready, bram_m_axi_awid => bram_axi_full_awid, bram_m_axi_awaddr => bram_axi_full_awaddr, bram_m_axi_awlen => bram_axi_full_awlen, bram_m_axi_awsize => bram_axi_full_awsize, bram_m_axi_awburst => bram_axi_full_awburst, bram_m_axi_awlock => bram_axi_full_awlock, bram_m_axi_awcache => bram_axi_full_awcache, bram_m_axi_awprot => bram_axi_full_awprot, bram_m_axi_awqos => bram_axi_full_awqos, bram_m_axi_awregion => bram_axi_full_awregion, bram_m_axi_awvalid => bram_axi_full_awvalid, bram_m_axi_awready => bram_axi_full_awready, bram_m_axi_wdata => bram_axi_full_wdata, bram_m_axi_wstrb => bram_axi_full_wstrb, bram_m_axi_wlast => bram_axi_full_wlast, bram_m_axi_wvalid => bram_axi_full_wvalid, bram_m_axi_wready => bram_axi_full_wready, bram_m_axi_bid => bram_axi_full_bid, bram_m_axi_bresp => bram_axi_full_bresp, bram_m_axi_bvalid => bram_axi_full_bvalid, bram_m_axi_bready => bram_axi_full_bready, bram_m_axi_arid => bram_axi_full_arid, bram_m_axi_araddr => bram_axi_full_araddr, bram_m_axi_arlen => bram_axi_full_arlen, bram_m_axi_arsize => bram_axi_full_arsize, bram_m_axi_arburst => bram_axi_full_arburst, bram_m_axi_arlock => bram_axi_full_arlock, bram_m_axi_arcache => bram_axi_full_arcache, bram_m_axi_arprot => bram_axi_full_arprot, bram_m_axi_arqos => bram_axi_full_arqos, bram_m_axi_arregion => bram_axi_full_arregion, bram_m_axi_arvalid => bram_axi_full_arvalid, bram_m_axi_arready => bram_axi_full_arready, bram_m_axi_rid => bram_axi_full_rid, bram_m_axi_rdata => bram_axi_full_rdata, bram_m_axi_rresp => bram_axi_full_rresp, bram_m_axi_rlast => bram_axi_full_rlast, bram_m_axi_rvalid => bram_axi_full_rvalid, bram_m_axi_rready => bram_axi_full_rready, ram_m_axi_awid => ram_axi_full_awid, ram_m_axi_awaddr => ram_axi_full_awaddr, ram_m_axi_awlen => ram_axi_full_awlen, ram_m_axi_awsize => ram_axi_full_awsize, ram_m_axi_awburst => ram_axi_full_awburst, ram_m_axi_awlock => ram_axi_full_awlock, ram_m_axi_awcache => ram_axi_full_awcache, ram_m_axi_awprot => ram_axi_full_awprot, ram_m_axi_awqos => ram_axi_full_awqos, ram_m_axi_awregion => ram_axi_full_awregion, ram_m_axi_awvalid => ram_axi_full_awvalid, ram_m_axi_awready => ram_axi_full_awready, ram_m_axi_wdata => ram_axi_full_wdata, ram_m_axi_wstrb => ram_axi_full_wstrb, ram_m_axi_wlast => ram_axi_full_wlast, ram_m_axi_wvalid => ram_axi_full_wvalid, ram_m_axi_wready => ram_axi_full_wready, ram_m_axi_bid => ram_axi_full_bid, ram_m_axi_bresp => ram_axi_full_bresp, ram_m_axi_bvalid => ram_axi_full_bvalid, ram_m_axi_bready => ram_axi_full_bready, ram_m_axi_arid => ram_axi_full_arid, ram_m_axi_araddr => ram_axi_full_araddr, ram_m_axi_arlen => ram_axi_full_arlen, ram_m_axi_arsize => ram_axi_full_arsize, ram_m_axi_arburst => ram_axi_full_arburst, ram_m_axi_arlock => ram_axi_full_arlock, ram_m_axi_arcache => ram_axi_full_arcache, ram_m_axi_arprot => ram_axi_full_arprot, ram_m_axi_arqos => ram_axi_full_arqos, ram_m_axi_arregion => ram_axi_full_arregion, ram_m_axi_arvalid => ram_axi_full_arvalid, ram_m_axi_arready => ram_axi_full_arready, ram_m_axi_rid => ram_axi_full_rid, ram_m_axi_rdata => ram_axi_full_rdata, ram_m_axi_rresp => ram_axi_full_rresp, ram_m_axi_rlast => ram_axi_full_rlast, ram_m_axi_rvalid => ram_axi_full_rvalid, ram_m_axi_rready => ram_axi_full_rready, int_m_axi_awid => int_axi_full_awid, int_m_axi_awaddr => int_axi_full_awaddr, int_m_axi_awlen => int_axi_full_awlen, int_m_axi_awsize => int_axi_full_awsize, int_m_axi_awburst => int_axi_full_awburst, int_m_axi_awlock => int_axi_full_awlock, int_m_axi_awcache => int_axi_full_awcache, int_m_axi_awprot => int_axi_full_awprot, int_m_axi_awqos => int_axi_full_awqos, int_m_axi_awregion => int_axi_full_awregion, int_m_axi_awvalid => int_axi_full_awvalid, int_m_axi_awready => int_axi_full_awready, int_m_axi_wdata => int_axi_full_wdata, int_m_axi_wstrb => int_axi_full_wstrb, int_m_axi_wlast => int_axi_full_wlast, int_m_axi_wvalid => int_axi_full_wvalid, int_m_axi_wready => int_axi_full_wready, int_m_axi_bid => int_axi_full_bid, int_m_axi_bresp => int_axi_full_bresp, int_m_axi_bvalid => int_axi_full_bvalid, int_m_axi_bready => int_axi_full_bready, int_m_axi_arid => int_axi_full_arid, int_m_axi_araddr => int_axi_full_araddr, int_m_axi_arlen => int_axi_full_arlen, int_m_axi_arsize => int_axi_full_arsize, int_m_axi_arburst => int_axi_full_arburst, int_m_axi_arlock => int_axi_full_arlock, int_m_axi_arcache => int_axi_full_arcache, int_m_axi_arprot => int_axi_full_arprot, int_m_axi_arqos => int_axi_full_arqos, int_m_axi_arregion => int_axi_full_arregion, int_m_axi_arvalid => int_axi_full_arvalid, int_m_axi_arready => int_axi_full_arready, int_m_axi_rid => int_axi_full_rid, int_m_axi_rdata => int_axi_full_rdata, int_m_axi_rresp => int_axi_full_rresp, int_m_axi_rlast => int_axi_full_rlast, int_m_axi_rvalid => int_axi_full_rvalid, int_m_axi_rready => int_axi_full_rready, timer_m_axi_awid => timer_axi_full_awid, timer_m_axi_awaddr => timer_axi_full_awaddr, timer_m_axi_awlen => timer_axi_full_awlen, timer_m_axi_awsize => timer_axi_full_awsize, timer_m_axi_awburst => timer_axi_full_awburst, timer_m_axi_awlock => timer_axi_full_awlock, timer_m_axi_awcache => timer_axi_full_awcache, timer_m_axi_awprot => timer_axi_full_awprot, timer_m_axi_awqos => timer_axi_full_awqos, timer_m_axi_awregion => timer_axi_full_awregion, timer_m_axi_awvalid => timer_axi_full_awvalid, timer_m_axi_awready => timer_axi_full_awready, timer_m_axi_wdata => timer_axi_full_wdata, timer_m_axi_wstrb => timer_axi_full_wstrb, timer_m_axi_wlast => timer_axi_full_wlast, timer_m_axi_wvalid => timer_axi_full_wvalid, timer_m_axi_wready => timer_axi_full_wready, timer_m_axi_bid => timer_axi_full_bid, timer_m_axi_bresp => timer_axi_full_bresp, timer_m_axi_bvalid => timer_axi_full_bvalid, timer_m_axi_bready => timer_axi_full_bready, timer_m_axi_arid => timer_axi_full_arid, timer_m_axi_araddr => timer_axi_full_araddr, timer_m_axi_arlen => timer_axi_full_arlen, timer_m_axi_arsize => timer_axi_full_arsize, timer_m_axi_arburst => timer_axi_full_arburst, timer_m_axi_arlock => timer_axi_full_arlock, timer_m_axi_arcache => timer_axi_full_arcache, timer_m_axi_arprot => timer_axi_full_arprot, timer_m_axi_arqos => timer_axi_full_arqos, timer_m_axi_arregion => timer_axi_full_arregion, timer_m_axi_arvalid => timer_axi_full_arvalid, timer_m_axi_arready => timer_axi_full_arready, timer_m_axi_rid => timer_axi_full_rid, timer_m_axi_rdata => timer_axi_full_rdata, timer_m_axi_rresp => timer_axi_full_rresp, timer_m_axi_rlast => timer_axi_full_rlast, timer_m_axi_rvalid => timer_axi_full_rvalid, timer_m_axi_rready => timer_axi_full_rready, gpio_m_axi_awid => gpio_axi_full_awid, gpio_m_axi_awaddr => gpio_axi_full_awaddr, gpio_m_axi_awlen => gpio_axi_full_awlen, gpio_m_axi_awsize => gpio_axi_full_awsize, gpio_m_axi_awburst => gpio_axi_full_awburst, gpio_m_axi_awlock => gpio_axi_full_awlock, gpio_m_axi_awcache => gpio_axi_full_awcache, gpio_m_axi_awprot => gpio_axi_full_awprot, gpio_m_axi_awqos => gpio_axi_full_awqos, gpio_m_axi_awregion => gpio_axi_full_awregion, gpio_m_axi_awvalid => gpio_axi_full_awvalid, gpio_m_axi_awready => gpio_axi_full_awready, gpio_m_axi_wdata => gpio_axi_full_wdata, gpio_m_axi_wstrb => gpio_axi_full_wstrb, gpio_m_axi_wlast => gpio_axi_full_wlast, gpio_m_axi_wvalid => gpio_axi_full_wvalid, gpio_m_axi_wready => gpio_axi_full_wready, gpio_m_axi_bid => gpio_axi_full_bid, gpio_m_axi_bresp => gpio_axi_full_bresp, gpio_m_axi_bvalid => gpio_axi_full_bvalid, gpio_m_axi_bready => gpio_axi_full_bready, gpio_m_axi_arid => gpio_axi_full_arid, gpio_m_axi_araddr => gpio_axi_full_araddr, gpio_m_axi_arlen => gpio_axi_full_arlen, gpio_m_axi_arsize => gpio_axi_full_arsize, gpio_m_axi_arburst => gpio_axi_full_arburst, gpio_m_axi_arlock => gpio_axi_full_arlock, gpio_m_axi_arcache => gpio_axi_full_arcache, gpio_m_axi_arprot => gpio_axi_full_arprot, gpio_m_axi_arqos => gpio_axi_full_arqos, gpio_m_axi_arregion => gpio_axi_full_arregion, gpio_m_axi_arvalid => gpio_axi_full_arvalid, gpio_m_axi_arready => gpio_axi_full_arready, gpio_m_axi_rid => gpio_axi_full_rid, gpio_m_axi_rdata => gpio_axi_full_rdata, gpio_m_axi_rresp => gpio_axi_full_rresp, gpio_m_axi_rlast => gpio_axi_full_rlast, gpio_m_axi_rvalid => gpio_axi_full_rvalid, gpio_m_axi_rready => gpio_axi_full_rready, cdma_m_axi_awid => cdmareg_axi_full_awid, cdma_m_axi_awaddr => cdmareg_axi_full_awaddr, cdma_m_axi_awlen => cdmareg_axi_full_awlen, cdma_m_axi_awsize => cdmareg_axi_full_awsize, cdma_m_axi_awburst => cdmareg_axi_full_awburst, cdma_m_axi_awlock => cdmareg_axi_full_awlock, cdma_m_axi_awcache => cdmareg_axi_full_awcache, cdma_m_axi_awprot => cdmareg_axi_full_awprot, cdma_m_axi_awqos => cdmareg_axi_full_awqos, cdma_m_axi_awregion => cdmareg_axi_full_awregion, cdma_m_axi_awvalid => cdmareg_axi_full_awvalid, cdma_m_axi_awready => cdmareg_axi_full_awready, cdma_m_axi_wdata => cdmareg_axi_full_wdata, cdma_m_axi_wstrb => cdmareg_axi_full_wstrb, cdma_m_axi_wlast => cdmareg_axi_full_wlast, cdma_m_axi_wvalid => cdmareg_axi_full_wvalid, cdma_m_axi_wready => cdmareg_axi_full_wready, cdma_m_axi_bid => cdmareg_axi_full_bid, cdma_m_axi_bresp => cdmareg_axi_full_bresp, cdma_m_axi_bvalid => cdmareg_axi_full_bvalid, cdma_m_axi_bready => cdmareg_axi_full_bready, cdma_m_axi_arid => cdmareg_axi_full_arid, cdma_m_axi_araddr => cdmareg_axi_full_araddr, cdma_m_axi_arlen => cdmareg_axi_full_arlen, cdma_m_axi_arsize => cdmareg_axi_full_arsize, cdma_m_axi_arburst => cdmareg_axi_full_arburst, cdma_m_axi_arlock => cdmareg_axi_full_arlock, cdma_m_axi_arcache => cdmareg_axi_full_arcache, cdma_m_axi_arprot => cdmareg_axi_full_arprot, cdma_m_axi_arqos => cdmareg_axi_full_arqos, cdma_m_axi_arregion => cdmareg_axi_full_arregion, cdma_m_axi_arvalid => cdmareg_axi_full_arvalid, cdma_m_axi_arready => cdmareg_axi_full_arready, cdma_m_axi_rid => cdmareg_axi_full_rid, cdma_m_axi_rdata => cdmareg_axi_full_rdata, cdma_m_axi_rresp => cdmareg_axi_full_rresp, cdma_m_axi_rlast => cdmareg_axi_full_rlast, cdma_m_axi_rvalid => cdmareg_axi_full_rvalid, cdma_m_axi_rready => cdmareg_axi_full_rready, uart_m_axi_awid => uart_axi_full_awid, uart_m_axi_awaddr => uart_axi_full_awaddr, uart_m_axi_awlen => uart_axi_full_awlen, uart_m_axi_awsize => uart_axi_full_awsize, uart_m_axi_awburst => uart_axi_full_awburst, uart_m_axi_awlock => uart_axi_full_awlock, uart_m_axi_awcache => uart_axi_full_awcache, uart_m_axi_awprot => uart_axi_full_awprot, uart_m_axi_awqos => uart_axi_full_awqos, uart_m_axi_awregion => uart_axi_full_awregion, uart_m_axi_awvalid => uart_axi_full_awvalid, uart_m_axi_awready => uart_axi_full_awready, uart_m_axi_wdata => uart_axi_full_wdata, uart_m_axi_wstrb => uart_axi_full_wstrb, uart_m_axi_wlast => uart_axi_full_wlast, uart_m_axi_wvalid => uart_axi_full_wvalid, uart_m_axi_wready => uart_axi_full_wready, uart_m_axi_bid => uart_axi_full_bid, uart_m_axi_bresp => uart_axi_full_bresp, uart_m_axi_bvalid => uart_axi_full_bvalid, uart_m_axi_bready => uart_axi_full_bready, uart_m_axi_arid => uart_axi_full_arid, uart_m_axi_araddr => uart_axi_full_araddr, uart_m_axi_arlen => uart_axi_full_arlen, uart_m_axi_arsize => uart_axi_full_arsize, uart_m_axi_arburst => uart_axi_full_arburst, uart_m_axi_arlock => uart_axi_full_arlock, uart_m_axi_arcache => uart_axi_full_arcache, uart_m_axi_arprot => uart_axi_full_arprot, uart_m_axi_arqos => uart_axi_full_arqos, uart_m_axi_arregion => uart_axi_full_arregion, uart_m_axi_arvalid => uart_axi_full_arvalid, uart_m_axi_arready => uart_axi_full_arready, uart_m_axi_rid => uart_axi_full_rid, uart_m_axi_rdata => uart_axi_full_rdata, uart_m_axi_rresp => uart_axi_full_rresp, uart_m_axi_rlast => uart_axi_full_rlast, uart_m_axi_rvalid => uart_axi_full_rvalid, uart_m_axi_rready => uart_axi_full_rready, timer_extra_0_m_axi_awid => timer_extra_0_axi_full_awid, timer_extra_0_m_axi_awaddr => timer_extra_0_axi_full_awaddr, timer_extra_0_m_axi_awlen => timer_extra_0_axi_full_awlen, timer_extra_0_m_axi_awsize => timer_extra_0_axi_full_awsize, timer_extra_0_m_axi_awburst => timer_extra_0_axi_full_awburst, timer_extra_0_m_axi_awlock => timer_extra_0_axi_full_awlock, timer_extra_0_m_axi_awcache => timer_extra_0_axi_full_awcache, timer_extra_0_m_axi_awprot => timer_extra_0_axi_full_awprot, timer_extra_0_m_axi_awqos => timer_extra_0_axi_full_awqos, timer_extra_0_m_axi_awregion => timer_extra_0_axi_full_awregion, timer_extra_0_m_axi_awvalid => timer_extra_0_axi_full_awvalid, timer_extra_0_m_axi_awready => timer_extra_0_axi_full_awready, timer_extra_0_m_axi_wdata => timer_extra_0_axi_full_wdata, timer_extra_0_m_axi_wstrb => timer_extra_0_axi_full_wstrb, timer_extra_0_m_axi_wlast => timer_extra_0_axi_full_wlast, timer_extra_0_m_axi_wvalid => timer_extra_0_axi_full_wvalid, timer_extra_0_m_axi_wready => timer_extra_0_axi_full_wready, timer_extra_0_m_axi_bid => timer_extra_0_axi_full_bid, timer_extra_0_m_axi_bresp => timer_extra_0_axi_full_bresp, timer_extra_0_m_axi_bvalid => timer_extra_0_axi_full_bvalid, timer_extra_0_m_axi_bready => timer_extra_0_axi_full_bready, timer_extra_0_m_axi_arid => timer_extra_0_axi_full_arid, timer_extra_0_m_axi_araddr => timer_extra_0_axi_full_araddr, timer_extra_0_m_axi_arlen => timer_extra_0_axi_full_arlen, timer_extra_0_m_axi_arsize => timer_extra_0_axi_full_arsize, timer_extra_0_m_axi_arburst => timer_extra_0_axi_full_arburst, timer_extra_0_m_axi_arlock => timer_extra_0_axi_full_arlock, timer_extra_0_m_axi_arcache => timer_extra_0_axi_full_arcache, timer_extra_0_m_axi_arprot => timer_extra_0_axi_full_arprot, timer_extra_0_m_axi_arqos => timer_extra_0_axi_full_arqos, timer_extra_0_m_axi_arregion => timer_extra_0_axi_full_arregion, timer_extra_0_m_axi_arvalid => timer_extra_0_axi_full_arvalid, timer_extra_0_m_axi_arready => timer_extra_0_axi_full_arready, timer_extra_0_m_axi_rid => timer_extra_0_axi_full_rid, timer_extra_0_m_axi_rdata => timer_extra_0_axi_full_rdata, timer_extra_0_m_axi_rresp => timer_extra_0_axi_full_rresp, timer_extra_0_m_axi_rlast => timer_extra_0_axi_full_rlast, timer_extra_0_m_axi_rvalid => timer_extra_0_axi_full_rvalid, timer_extra_0_m_axi_rready => timer_extra_0_axi_full_rready, aclk => aclk, aresetn => cross_aresetn(0)); plasoc_cpu_inst : plasoc_cpu port map ( aclk => aclk, aresetn => aresetn(0), intr_in => cpu_int, axi_awid => cpu_axi_full_awid, axi_awaddr => cpu_axi_full_awaddr, axi_awlen => cpu_axi_full_awlen, axi_awsize => cpu_axi_full_awsize, axi_awburst => cpu_axi_full_awburst, axi_awlock => cpu_axi_full_awlock, axi_awcache => cpu_axi_full_awcache, axi_awprot => cpu_axi_full_awprot, axi_awqos => cpu_axi_full_awqos, axi_awregion => cpu_axi_full_awregion, axi_awvalid => cpu_axi_full_awvalid, axi_awready => cpu_axi_full_awready, axi_wdata => cpu_axi_full_wdata, axi_wstrb => cpu_axi_full_wstrb, axi_wlast => cpu_axi_full_wlast, axi_wvalid => cpu_axi_full_wvalid, axi_wready => cpu_axi_full_wready, axi_bid => cpu_axi_full_bid, axi_bresp => cpu_axi_full_bresp, axi_bvalid => cpu_axi_full_bvalid, axi_bready => cpu_axi_full_bready, axi_arid => cpu_axi_full_arid, axi_araddr => cpu_axi_full_araddr, axi_arlen => cpu_axi_full_arlen, axi_arsize => cpu_axi_full_arsize, axi_arburst => cpu_axi_full_arburst, axi_arlock => cpu_axi_full_arlock, axi_arcache => cpu_axi_full_arcache, axi_arprot => cpu_axi_full_arprot, axi_arqos => cpu_axi_full_arqos, axi_arregion => cpu_axi_full_arregion, axi_arvalid => cpu_axi_full_arvalid, axi_arready => cpu_axi_full_arready, axi_rid => cpu_axi_full_rid, axi_rdata => cpu_axi_full_rdata, axi_rresp => cpu_axi_full_rresp, axi_rlast => cpu_axi_full_rlast, axi_rvalid => cpu_axi_full_rvalid, axi_rready => cpu_axi_full_rready); int_full2lite_inst : plasoc_axi4_full2lite generic map ( axi_slave_id_width => axi_master_id_width, axi_address_width => axi_lite_address_width, axi_data_width => axi_data_width) port map ( aclk => aclk, aresetn => aresetn(0), s_axi_awid => int_axi_full_awid, s_axi_awaddr => int_axi_full_awaddr(axi_lite_address_width-1 downto 0), s_axi_awlen => int_axi_full_awlen, s_axi_awsize => int_axi_full_awsize, s_axi_awburst => int_axi_full_awburst, s_axi_awlock => int_axi_full_awlock, s_axi_awcache => int_axi_full_awcache, s_axi_awprot => int_axi_full_awprot, s_axi_awqos => int_axi_full_awqos, s_axi_awregion => int_axi_full_awregion, s_axi_awvalid => int_axi_full_awvalid, s_axi_awready => int_axi_full_awready, s_axi_wdata => int_axi_full_wdata, s_axi_wstrb => int_axi_full_wstrb, s_axi_wlast => int_axi_full_wlast, s_axi_wvalid => int_axi_full_wvalid, s_axi_wready => int_axi_full_wready, s_axi_bid => int_axi_full_bid, s_axi_bresp => int_axi_full_bresp, s_axi_bvalid => int_axi_full_bvalid, s_axi_bready => int_axi_full_bready, s_axi_arid => int_axi_full_arid, s_axi_araddr => int_axi_full_araddr(axi_lite_address_width-1 downto 0), s_axi_arlen => int_axi_full_arlen, s_axi_arsize => int_axi_full_arsize, s_axi_arburst => int_axi_full_arburst, s_axi_arlock => int_axi_full_arlock, s_axi_arcache => int_axi_full_arcache, s_axi_arprot => int_axi_full_arprot, s_axi_arqos => int_axi_full_arqos, s_axi_arregion => int_axi_full_arregion, s_axi_arvalid => int_axi_full_arvalid, s_axi_arready => int_axi_full_arready, s_axi_rid => int_axi_full_rid, s_axi_rdata => int_axi_full_rdata, s_axi_rresp => int_axi_full_rresp, s_axi_rlast => int_axi_full_rlast, s_axi_rvalid => int_axi_full_rvalid, s_axi_rready => int_axi_full_rready, m_axi_awaddr => int_axi_lite_awaddr, m_axi_awprot => int_axi_lite_awprot, m_axi_awvalid => int_axi_lite_awvalid, m_axi_awready => int_axi_lite_awready, m_axi_wvalid => int_axi_lite_wvalid, m_axi_wready => int_axi_lite_wready, m_axi_wdata => int_axi_lite_wdata, m_axi_wstrb => int_axi_lite_wstrb, m_axi_bvalid => int_axi_lite_bvalid, m_axi_bready => int_axi_lite_bready, m_axi_bresp => int_axi_lite_bresp, m_axi_araddr => int_axi_lite_araddr, m_axi_arprot => int_axi_lite_arprot, m_axi_arvalid => int_axi_lite_arvalid, m_axi_arready => int_axi_lite_arready, m_axi_rdata => int_axi_lite_rdata, m_axi_rvalid => int_axi_lite_rvalid, m_axi_rready => int_axi_lite_rready, m_axi_rresp => int_axi_lite_rresp); timer_full2lite_inst : plasoc_axi4_full2lite generic map ( axi_slave_id_width => axi_master_id_width, axi_address_width => axi_lite_address_width, axi_data_width => axi_data_width) port map ( aclk => aclk, aresetn => aresetn(0), s_axi_awid => timer_axi_full_awid, s_axi_awaddr => timer_axi_full_awaddr(axi_lite_address_width-1 downto 0), s_axi_awlen => timer_axi_full_awlen, s_axi_awsize => timer_axi_full_awsize, s_axi_awburst => timer_axi_full_awburst, s_axi_awlock => timer_axi_full_awlock, s_axi_awcache => timer_axi_full_awcache, s_axi_awprot => timer_axi_full_awprot, s_axi_awqos => timer_axi_full_awqos, s_axi_awregion => timer_axi_full_awregion, s_axi_awvalid => timer_axi_full_awvalid, s_axi_awready => timer_axi_full_awready, s_axi_wdata => timer_axi_full_wdata, s_axi_wstrb => timer_axi_full_wstrb, s_axi_wlast => timer_axi_full_wlast, s_axi_wvalid => timer_axi_full_wvalid, s_axi_wready => timer_axi_full_wready, s_axi_bid => timer_axi_full_bid, s_axi_bresp => timer_axi_full_bresp, s_axi_bvalid => timer_axi_full_bvalid, s_axi_bready => timer_axi_full_bready, s_axi_arid => timer_axi_full_arid, s_axi_araddr => timer_axi_full_araddr(axi_lite_address_width-1 downto 0), s_axi_arlen => timer_axi_full_arlen, s_axi_arsize => timer_axi_full_arsize, s_axi_arburst => timer_axi_full_arburst, s_axi_arlock => timer_axi_full_arlock, s_axi_arcache => timer_axi_full_arcache, s_axi_arprot => timer_axi_full_arprot, s_axi_arqos => timer_axi_full_arqos, s_axi_arregion => timer_axi_full_arregion, s_axi_arvalid => timer_axi_full_arvalid, s_axi_arready => timer_axi_full_arready, s_axi_rid => timer_axi_full_rid, s_axi_rdata => timer_axi_full_rdata, s_axi_rresp => timer_axi_full_rresp, s_axi_rlast => timer_axi_full_rlast, s_axi_rvalid => timer_axi_full_rvalid, s_axi_rready => timer_axi_full_rready, m_axi_awaddr => timer_axi_lite_awaddr, m_axi_awprot => timer_axi_lite_awprot, m_axi_awvalid => timer_axi_lite_awvalid, m_axi_awready => timer_axi_lite_awready, m_axi_wvalid => timer_axi_lite_wvalid, m_axi_wready => timer_axi_lite_wready, m_axi_wdata => timer_axi_lite_wdata, m_axi_wstrb => timer_axi_lite_wstrb, m_axi_bvalid => timer_axi_lite_bvalid, m_axi_bready => timer_axi_lite_bready, m_axi_bresp => timer_axi_lite_bresp, m_axi_araddr => timer_axi_lite_araddr, m_axi_arprot => timer_axi_lite_arprot, m_axi_arvalid => timer_axi_lite_arvalid, m_axi_arready => timer_axi_lite_arready, m_axi_rdata => timer_axi_lite_rdata, m_axi_rvalid => timer_axi_lite_rvalid, m_axi_rready => timer_axi_lite_rready, m_axi_rresp => timer_axi_lite_rresp); gpio_full2lite_inst : plasoc_axi4_full2lite generic map ( axi_slave_id_width => axi_master_id_width, axi_address_width => axi_lite_address_width, axi_data_width => axi_data_width) port map ( aclk => aclk, aresetn => aresetn(0), s_axi_awid => gpio_axi_full_awid, s_axi_awaddr => gpio_axi_full_awaddr(axi_lite_address_width-1 downto 0), s_axi_awlen => gpio_axi_full_awlen, s_axi_awsize => gpio_axi_full_awsize, s_axi_awburst => gpio_axi_full_awburst, s_axi_awlock => gpio_axi_full_awlock, s_axi_awcache => gpio_axi_full_awcache, s_axi_awprot => gpio_axi_full_awprot, s_axi_awqos => gpio_axi_full_awqos, s_axi_awregion => gpio_axi_full_awregion, s_axi_awvalid => gpio_axi_full_awvalid, s_axi_awready => gpio_axi_full_awready, s_axi_wdata => gpio_axi_full_wdata, s_axi_wstrb => gpio_axi_full_wstrb, s_axi_wlast => gpio_axi_full_wlast, s_axi_wvalid => gpio_axi_full_wvalid, s_axi_wready => gpio_axi_full_wready, s_axi_bid => gpio_axi_full_bid, s_axi_bresp => gpio_axi_full_bresp, s_axi_bvalid => gpio_axi_full_bvalid, s_axi_bready => gpio_axi_full_bready, s_axi_arid => gpio_axi_full_arid, s_axi_araddr => gpio_axi_full_araddr(axi_lite_address_width-1 downto 0), s_axi_arlen => gpio_axi_full_arlen, s_axi_arsize => gpio_axi_full_arsize, s_axi_arburst => gpio_axi_full_arburst, s_axi_arlock => gpio_axi_full_arlock, s_axi_arcache => gpio_axi_full_arcache, s_axi_arprot => gpio_axi_full_arprot, s_axi_arqos => gpio_axi_full_arqos, s_axi_arregion => gpio_axi_full_arregion, s_axi_arvalid => gpio_axi_full_arvalid, s_axi_arready => gpio_axi_full_arready, s_axi_rid => gpio_axi_full_rid, s_axi_rdata => gpio_axi_full_rdata, s_axi_rresp => gpio_axi_full_rresp, s_axi_rlast => gpio_axi_full_rlast, s_axi_rvalid => gpio_axi_full_rvalid, s_axi_rready => gpio_axi_full_rready, m_axi_awaddr => gpio_axi_lite_awaddr, m_axi_awprot => gpio_axi_lite_awprot, m_axi_awvalid => gpio_axi_lite_awvalid, m_axi_awready => gpio_axi_lite_awready, m_axi_wvalid => gpio_axi_lite_wvalid, m_axi_wready => gpio_axi_lite_wready, m_axi_wdata => gpio_axi_lite_wdata, m_axi_wstrb => gpio_axi_lite_wstrb, m_axi_bvalid => gpio_axi_lite_bvalid, m_axi_bready => gpio_axi_lite_bready, m_axi_bresp => gpio_axi_lite_bresp, m_axi_araddr => gpio_axi_lite_araddr, m_axi_arprot => gpio_axi_lite_arprot, m_axi_arvalid => gpio_axi_lite_arvalid, m_axi_arready => gpio_axi_lite_arready, m_axi_rdata => gpio_axi_lite_rdata, m_axi_rvalid => gpio_axi_lite_rvalid, m_axi_rready => gpio_axi_lite_rready, m_axi_rresp => gpio_axi_lite_rresp); cdmareg_full2lite_inst : plasoc_axi4_full2lite generic map ( axi_slave_id_width => axi_master_id_width, axi_address_width => axi_lite_address_width, axi_data_width => axi_data_width) port map ( aclk => aclk, aresetn => aresetn(0), s_axi_awid => cdmareg_axi_full_awid, s_axi_awaddr => cdmareg_axi_full_awaddr(axi_lite_address_width-1 downto 0), s_axi_awlen => cdmareg_axi_full_awlen, s_axi_awsize => cdmareg_axi_full_awsize, s_axi_awburst => cdmareg_axi_full_awburst, s_axi_awlock => cdmareg_axi_full_awlock, s_axi_awcache => cdmareg_axi_full_awcache, s_axi_awprot => cdmareg_axi_full_awprot, s_axi_awqos => cdmareg_axi_full_awqos, s_axi_awregion => cdmareg_axi_full_awregion, s_axi_awvalid => cdmareg_axi_full_awvalid, s_axi_awready => cdmareg_axi_full_awready, s_axi_wdata => cdmareg_axi_full_wdata, s_axi_wstrb => cdmareg_axi_full_wstrb, s_axi_wlast => cdmareg_axi_full_wlast, s_axi_wvalid => cdmareg_axi_full_wvalid, s_axi_wready => cdmareg_axi_full_wready, s_axi_bid => cdmareg_axi_full_bid, s_axi_bresp => cdmareg_axi_full_bresp, s_axi_bvalid => cdmareg_axi_full_bvalid, s_axi_bready => cdmareg_axi_full_bready, s_axi_arid => cdmareg_axi_full_arid, s_axi_araddr => cdmareg_axi_full_araddr(axi_lite_address_width-1 downto 0), s_axi_arlen => cdmareg_axi_full_arlen, s_axi_arsize => cdmareg_axi_full_arsize, s_axi_arburst => cdmareg_axi_full_arburst, s_axi_arlock => cdmareg_axi_full_arlock, s_axi_arcache => cdmareg_axi_full_arcache, s_axi_arprot => cdmareg_axi_full_arprot, s_axi_arqos => cdmareg_axi_full_arqos, s_axi_arregion => cdmareg_axi_full_arregion, s_axi_arvalid => cdmareg_axi_full_arvalid, s_axi_arready => cdmareg_axi_full_arready, s_axi_rid => cdmareg_axi_full_rid, s_axi_rdata => cdmareg_axi_full_rdata, s_axi_rresp => cdmareg_axi_full_rresp, s_axi_rlast => cdmareg_axi_full_rlast, s_axi_rvalid => cdmareg_axi_full_rvalid, s_axi_rready => cdmareg_axi_full_rready, m_axi_awaddr => cdmareg_axi_lite_awaddr, m_axi_awprot => cdmareg_axi_lite_awprot, m_axi_awvalid => cdmareg_axi_lite_awvalid, m_axi_awready => cdmareg_axi_lite_awready, m_axi_wvalid => cdmareg_axi_lite_wvalid, m_axi_wready => cdmareg_axi_lite_wready, m_axi_wdata => cdmareg_axi_lite_wdata, m_axi_wstrb => cdmareg_axi_lite_wstrb, m_axi_bvalid => cdmareg_axi_lite_bvalid, m_axi_bready => cdmareg_axi_lite_bready, m_axi_bresp => cdmareg_axi_lite_bresp, m_axi_araddr => cdmareg_axi_lite_araddr, m_axi_arprot => cdmareg_axi_lite_arprot, m_axi_arvalid => cdmareg_axi_lite_arvalid, m_axi_arready => cdmareg_axi_lite_arready, m_axi_rdata => cdmareg_axi_lite_rdata, m_axi_rvalid => cdmareg_axi_lite_rvalid, m_axi_rready => cdmareg_axi_lite_rready, m_axi_rresp => cdmareg_axi_lite_rresp); uart_full2lite_inst : plasoc_axi4_full2lite generic map ( axi_slave_id_width => axi_master_id_width, axi_address_width => axi_lite_address_width, axi_data_width => axi_data_width) port map ( aclk => aclk, aresetn => aresetn(0), s_axi_awid => uart_axi_full_awid, s_axi_awaddr => uart_axi_full_awaddr(axi_lite_address_width-1 downto 0), s_axi_awlen => uart_axi_full_awlen, s_axi_awsize => uart_axi_full_awsize, s_axi_awburst => uart_axi_full_awburst, s_axi_awlock => uart_axi_full_awlock, s_axi_awcache => uart_axi_full_awcache, s_axi_awprot => uart_axi_full_awprot, s_axi_awqos => uart_axi_full_awqos, s_axi_awregion => uart_axi_full_awregion, s_axi_awvalid => uart_axi_full_awvalid, s_axi_awready => uart_axi_full_awready, s_axi_wdata => uart_axi_full_wdata, s_axi_wstrb => uart_axi_full_wstrb, s_axi_wlast => uart_axi_full_wlast, s_axi_wvalid => uart_axi_full_wvalid, s_axi_wready => uart_axi_full_wready, s_axi_bid => uart_axi_full_bid, s_axi_bresp => uart_axi_full_bresp, s_axi_bvalid => uart_axi_full_bvalid, s_axi_bready => uart_axi_full_bready, s_axi_arid => uart_axi_full_arid, s_axi_araddr => uart_axi_full_araddr(axi_lite_address_width-1 downto 0), s_axi_arlen => uart_axi_full_arlen, s_axi_arsize => uart_axi_full_arsize, s_axi_arburst => uart_axi_full_arburst, s_axi_arlock => uart_axi_full_arlock, s_axi_arcache => uart_axi_full_arcache, s_axi_arprot => uart_axi_full_arprot, s_axi_arqos => uart_axi_full_arqos, s_axi_arregion => uart_axi_full_arregion, s_axi_arvalid => uart_axi_full_arvalid, s_axi_arready => uart_axi_full_arready, s_axi_rid => uart_axi_full_rid, s_axi_rdata => uart_axi_full_rdata, s_axi_rresp => uart_axi_full_rresp, s_axi_rlast => uart_axi_full_rlast, s_axi_rvalid => uart_axi_full_rvalid, s_axi_rready => uart_axi_full_rready, m_axi_awaddr => uart_axi_lite_awaddr, m_axi_awprot => uart_axi_lite_awprot, m_axi_awvalid => uart_axi_lite_awvalid, m_axi_awready => uart_axi_lite_awready, m_axi_wvalid => uart_axi_lite_wvalid, m_axi_wready => uart_axi_lite_wready, m_axi_wdata => uart_axi_lite_wdata, m_axi_wstrb => uart_axi_lite_wstrb, m_axi_bvalid => uart_axi_lite_bvalid, m_axi_bready => uart_axi_lite_bready, m_axi_bresp => uart_axi_lite_bresp, m_axi_araddr => uart_axi_lite_araddr, m_axi_arprot => uart_axi_lite_arprot, m_axi_arvalid => uart_axi_lite_arvalid, m_axi_arready => uart_axi_lite_arready, m_axi_rdata => uart_axi_lite_rdata, m_axi_rvalid => uart_axi_lite_rvalid, m_axi_rready => uart_axi_lite_rready, m_axi_rresp => uart_axi_lite_rresp); timer_extra_0_full2lite_inst : plasoc_axi4_full2lite generic map ( axi_slave_id_width => axi_master_id_width, axi_address_width => axi_lite_address_width, axi_data_width => axi_data_width) port map ( aclk => aclk, aresetn => aresetn(0), s_axi_awid => timer_extra_0_axi_full_awid, s_axi_awaddr => timer_extra_0_axi_full_awaddr(axi_lite_address_width-1 downto 0), s_axi_awlen => timer_extra_0_axi_full_awlen, s_axi_awsize => timer_extra_0_axi_full_awsize, s_axi_awburst => timer_extra_0_axi_full_awburst, s_axi_awlock => timer_extra_0_axi_full_awlock, s_axi_awcache => timer_extra_0_axi_full_awcache, s_axi_awprot => timer_extra_0_axi_full_awprot, s_axi_awqos => timer_extra_0_axi_full_awqos, s_axi_awregion => timer_extra_0_axi_full_awregion, s_axi_awvalid => timer_extra_0_axi_full_awvalid, s_axi_awready => timer_extra_0_axi_full_awready, s_axi_wdata => timer_extra_0_axi_full_wdata, s_axi_wstrb => timer_extra_0_axi_full_wstrb, s_axi_wlast => timer_extra_0_axi_full_wlast, s_axi_wvalid => timer_extra_0_axi_full_wvalid, s_axi_wready => timer_extra_0_axi_full_wready, s_axi_bid => timer_extra_0_axi_full_bid, s_axi_bresp => timer_extra_0_axi_full_bresp, s_axi_bvalid => timer_extra_0_axi_full_bvalid, s_axi_bready => timer_extra_0_axi_full_bready, s_axi_arid => timer_extra_0_axi_full_arid, s_axi_araddr => timer_extra_0_axi_full_araddr(axi_lite_address_width-1 downto 0), s_axi_arlen => timer_extra_0_axi_full_arlen, s_axi_arsize => timer_extra_0_axi_full_arsize, s_axi_arburst => timer_extra_0_axi_full_arburst, s_axi_arlock => timer_extra_0_axi_full_arlock, s_axi_arcache => timer_extra_0_axi_full_arcache, s_axi_arprot => timer_extra_0_axi_full_arprot, s_axi_arqos => timer_extra_0_axi_full_arqos, s_axi_arregion => timer_extra_0_axi_full_arregion, s_axi_arvalid => timer_extra_0_axi_full_arvalid, s_axi_arready => timer_extra_0_axi_full_arready, s_axi_rid => timer_extra_0_axi_full_rid, s_axi_rdata => timer_extra_0_axi_full_rdata, s_axi_rresp => timer_extra_0_axi_full_rresp, s_axi_rlast => timer_extra_0_axi_full_rlast, s_axi_rvalid => timer_extra_0_axi_full_rvalid, s_axi_rready => timer_extra_0_axi_full_rready, m_axi_awaddr => timer_extra_0_axi_lite_awaddr, m_axi_awprot => timer_extra_0_axi_lite_awprot, m_axi_awvalid => timer_extra_0_axi_lite_awvalid, m_axi_awready => timer_extra_0_axi_lite_awready, m_axi_wvalid => timer_extra_0_axi_lite_wvalid, m_axi_wready => timer_extra_0_axi_lite_wready, m_axi_wdata => timer_extra_0_axi_lite_wdata, m_axi_wstrb => timer_extra_0_axi_lite_wstrb, m_axi_bvalid => timer_extra_0_axi_lite_bvalid, m_axi_bready => timer_extra_0_axi_lite_bready, m_axi_bresp => timer_extra_0_axi_lite_bresp, m_axi_araddr => timer_extra_0_axi_lite_araddr, m_axi_arprot => timer_extra_0_axi_lite_arprot, m_axi_arvalid => timer_extra_0_axi_lite_arvalid, m_axi_arready => timer_extra_0_axi_lite_arready, m_axi_rdata => timer_extra_0_axi_lite_rdata, m_axi_rvalid => timer_extra_0_axi_lite_rvalid, m_axi_rready => timer_extra_0_axi_lite_rready, m_axi_rresp => timer_extra_0_axi_lite_rresp); bram_cntrl_inst : axi_bram_ctrl_0 port map ( s_axi_aclk => aclk, s_axi_aresetn => aresetn(0), s_axi_awid => bram_axi_full_awid, s_axi_awaddr => bram_axi_full_awaddr(axi_lite_address_width-1 downto 0), s_axi_awlen => bram_axi_full_awlen, s_axi_awsize => bram_axi_full_awsize, s_axi_awburst => bram_axi_full_awburst, s_axi_awlock => bram_axi_full_awlock, s_axi_awcache => bram_axi_full_awcache, s_axi_awprot => bram_axi_full_awprot, s_axi_awvalid => bram_axi_full_awvalid, s_axi_awready => bram_axi_full_awready, s_axi_wdata => bram_axi_full_wdata, s_axi_wstrb => bram_axi_full_wstrb, s_axi_wlast => bram_axi_full_wlast, s_axi_wvalid => bram_axi_full_wvalid, s_axi_wready => bram_axi_full_wready, s_axi_bid => bram_axi_full_bid, s_axi_bresp => bram_axi_full_bresp, s_axi_bvalid => bram_axi_full_bvalid, s_axi_bready => bram_axi_full_bready, s_axi_arid => bram_axi_full_arid, s_axi_araddr => bram_axi_full_araddr(axi_lite_address_width-1 downto 0), s_axi_arlen => bram_axi_full_arlen, s_axi_arsize => bram_axi_full_arsize, s_axi_arburst => bram_axi_full_arburst, s_axi_arlock => bram_axi_full_arlock, s_axi_arcache => bram_axi_full_arcache, s_axi_arprot => bram_axi_full_arprot, s_axi_arvalid => bram_axi_full_arvalid, s_axi_arready => bram_axi_full_arready, s_axi_rid => bram_axi_full_rid, s_axi_rdata => bram_axi_full_rdata, s_axi_rresp => bram_axi_full_rresp, s_axi_rlast => bram_axi_full_rlast, s_axi_rvalid => bram_axi_full_rvalid, s_axi_rready => bram_axi_full_rready, bram_rst_a => bram_bram_rst_a, bram_clk_a => bram_bram_clk_a, bram_en_a => bram_bram_en_a, bram_we_a => bram_bram_we_a, bram_addr_a => bram_bram_addr_a, bram_wrdata_a => bram_bram_wrdata_a, bram_rddata_a => bram_bram_rddata_a); bram_inst : bram generic map ( select_app => lower_app, address_width => axi_lite_address_width, data_width => axi_data_width, bram_depth => 1024 ) port map ( bram_rst_a => bram_bram_rst_a, bram_clk_a => bram_bram_clk_a, bram_en_a => bram_bram_en_a, bram_we_a => bram_bram_we_a, bram_addr_a => bram_bram_addr_a, bram_wrdata_a => bram_bram_wrdata_a, bram_rddata_a => bram_bram_rddata_a); gen_int_mm : if upper_ext=false generate ram_cntrl_inst : axi_bram_ctrl_1 port map ( s_axi_aclk => aclk, s_axi_aresetn => aresetn(0), s_axi_awid => ram_axi_full_awid, s_axi_awaddr => ram_axi_full_awaddr(axi_ram_address_width-1 downto 0), s_axi_awlen => ram_axi_full_awlen, s_axi_awsize => ram_axi_full_awsize, s_axi_awburst => ram_axi_full_awburst, s_axi_awlock => ram_axi_full_awlock, s_axi_awcache => ram_axi_full_awcache, s_axi_awprot => ram_axi_full_awprot, s_axi_awvalid => ram_axi_full_awvalid, s_axi_awready => ram_axi_full_awready, s_axi_wdata => ram_axi_full_wdata, s_axi_wstrb => ram_axi_full_wstrb, s_axi_wlast => ram_axi_full_wlast, s_axi_wvalid => ram_axi_full_wvalid, s_axi_wready => ram_axi_full_wready, s_axi_bid => ram_axi_full_bid, s_axi_bresp => ram_axi_full_bresp, s_axi_bvalid => ram_axi_full_bvalid, s_axi_bready => ram_axi_full_bready, s_axi_arid => ram_axi_full_arid, s_axi_araddr => ram_axi_full_araddr(axi_ram_address_width-1 downto 0), s_axi_arlen => ram_axi_full_arlen, s_axi_arsize => ram_axi_full_arsize, s_axi_arburst => ram_axi_full_arburst, s_axi_arlock => ram_axi_full_arlock, s_axi_arcache => ram_axi_full_arcache, s_axi_arprot => ram_axi_full_arprot, s_axi_arvalid => ram_axi_full_arvalid, s_axi_arready => ram_axi_full_arready, s_axi_rid => ram_axi_full_rid, s_axi_rdata => ram_axi_full_rdata, s_axi_rresp => ram_axi_full_rresp, s_axi_rlast => ram_axi_full_rlast, s_axi_rvalid => ram_axi_full_rvalid, s_axi_rready => ram_axi_full_rready, bram_rst_a => ram_bram_rst_a, bram_clk_a => ram_bram_clk_a, bram_en_a => ram_bram_en_a, bram_we_a => ram_bram_we_a, bram_addr_a => ram_bram_addr_a, bram_wrdata_a => ram_bram_wrdata_a, bram_rddata_a => ram_bram_rddata_a); ram_inst : bram generic map ( select_app => upper_app, address_width => axi_ram_address_width, data_width => axi_data_width, bram_depth => axi_ram_depth) port map ( bram_rst_a => ram_bram_rst_a, bram_clk_a => ram_bram_clk_a, bram_en_a => ram_bram_en_a, bram_we_a => ram_bram_we_a, bram_addr_a => ram_bram_addr_a, bram_wrdata_a => ram_bram_wrdata_a, bram_rddata_a => ram_bram_rddata_a); end generate; gen_ext_mm : if upper_ext=true generate mig_wrap_wrapper_inst : mig_wrap_wrapper port map ( ACLK => aclk, ARESETN => cross_aresetn(0), DDR2_addr => DDR2_addr, DDR2_ba => DDR2_ba, DDR2_cas_n => DDR2_cas_n, DDR2_ck_n => DDR2_ck_n, DDR2_ck_p => DDR2_ck_p, DDR2_cke => DDR2_cke, DDR2_cs_n => DDR2_cs_n, DDR2_dm => DDR2_dm, DDR2_dq => DDR2_dq, DDR2_dqs_n => DDR2_dqs_n, DDR2_dqs_p => DDR2_dqs_p, DDR2_odt => DDR2_odt, DDR2_ras_n => DDR2_ras_n, DDR2_we_n => DDR2_we_n, S00_ARESETN => aresetn(0), S00_AXI_araddr => ram_axi_full_araddr, S00_AXI_arburst => ram_axi_full_arburst, S00_AXI_arcache => ram_axi_full_arcache, S00_AXI_arid => ram_axi_full_arid_slv, S00_AXI_arlen => ram_axi_full_arlen, S00_AXI_arlock => ram_axi_full_arlock_slv, S00_AXI_arprot => ram_axi_full_arprot, S00_AXI_arqos => ram_axi_full_arqos, S00_AXI_arready => ram_axi_full_arready, S00_AXI_arregion => ram_axi_full_arregion, S00_AXI_arsize => ram_axi_full_arsize, S00_AXI_arvalid => ram_axi_full_arvalid, S00_AXI_awaddr => ram_axi_full_awaddr, S00_AXI_awburst => ram_axi_full_awburst, S00_AXI_awcache => ram_axi_full_awcache, S00_AXI_awid => ram_axi_full_awid_slv, S00_AXI_awlen => ram_axi_full_awlen, S00_AXI_awlock => ram_axi_full_awlock_slv, S00_AXI_awprot => ram_axi_full_awprot, S00_AXI_awqos => ram_axi_full_awqos, S00_AXI_awready => ram_axi_full_awready, S00_AXI_awregion => ram_axi_full_awregion, S00_AXI_awsize => ram_axi_full_awsize, S00_AXI_awvalid => ram_axi_full_awvalid, S00_AXI_bid => ram_axi_full_bid_slv, S00_AXI_bready => ram_axi_full_bready, S00_AXI_bresp => ram_axi_full_bresp, S00_AXI_bvalid => ram_axi_full_bvalid, S00_AXI_rdata => ram_axi_full_rdata, S00_AXI_rid => ram_axi_full_rid_slv, S00_AXI_rlast => ram_axi_full_rlast, S00_AXI_rready => ram_axi_full_rready, S00_AXI_rresp => ram_axi_full_rresp, S00_AXI_rvalid => ram_axi_full_rvalid, S00_AXI_wdata => ram_axi_full_wdata, S00_AXI_wlast => ram_axi_full_wlast, S00_AXI_wready => ram_axi_full_wready, S00_AXI_wstrb => ram_axi_full_wstrb, S00_AXI_wvalid => ram_axi_full_wvalid, clk_ref_i => ddr_aclk, sys_rst => raw_nreset); end generate; plasoc_int_inst : plasoc_int generic map ( axi_address_width => axi_lite_address_width, axi_data_width => axi_data_width) port map ( aclk => aclk, aresetn => aresetn(0), cpu_int => cpu_int, dev_ints => int_dev_ints, axi_awaddr => int_axi_lite_awaddr, axi_awprot => int_axi_lite_awprot, axi_awvalid => int_axi_lite_awvalid, axi_awready => int_axi_lite_awready, axi_wvalid => int_axi_lite_wvalid, axi_wready => int_axi_lite_wready, axi_wdata => int_axi_lite_wdata, axi_wstrb => int_axi_lite_wstrb, axi_bvalid => int_axi_lite_bvalid, axi_bready => int_axi_lite_bready, axi_bresp => int_axi_lite_bresp, axi_araddr => int_axi_lite_araddr, axi_arprot => int_axi_lite_arprot, axi_arvalid => int_axi_lite_arvalid, axi_arready => int_axi_lite_arready, axi_rdata => int_axi_lite_rdata, axi_rvalid => int_axi_lite_rvalid, axi_rready => int_axi_lite_rready, axi_rresp => int_axi_lite_rresp); plasoc_timer_inst : plasoc_timer generic map ( axi_address_width => axi_lite_address_width, axi_data_width => axi_data_width) port map ( aclk => aclk, aresetn => aresetn(0), axi_awaddr => timer_axi_lite_awaddr, axi_awprot => timer_axi_lite_awprot, axi_awvalid => timer_axi_lite_awvalid, axi_awready => timer_axi_lite_awready, axi_wvalid => timer_axi_lite_wvalid, axi_wready => timer_axi_lite_wready, axi_wdata => timer_axi_lite_wdata, axi_wstrb => timer_axi_lite_wstrb, axi_bvalid => timer_axi_lite_bvalid, axi_bready => timer_axi_lite_bready, axi_bresp => timer_axi_lite_bresp, axi_araddr => timer_axi_lite_araddr, axi_arprot => timer_axi_lite_arprot, axi_arvalid => timer_axi_lite_arvalid, axi_arready => timer_axi_lite_arready, axi_rdata => timer_axi_lite_rdata, axi_rvalid => timer_axi_lite_rvalid, axi_rready => timer_axi_lite_rready, axi_rresp => timer_axi_lite_rresp, done => timer_int); plasoc_gpio_inst : plasoc_gpio generic map ( axi_address_width => axi_lite_address_width, axi_data_width => axi_data_width) port map ( aclk => aclk, aresetn => aresetn(0), data_in => gpio_input, data_out => gpio_output, int => gpio_int, axi_awaddr => gpio_axi_lite_awaddr, axi_awprot => gpio_axi_lite_awprot, axi_awvalid => gpio_axi_lite_awvalid, axi_awready => gpio_axi_lite_awready, axi_wvalid => gpio_axi_lite_wvalid, axi_wready => gpio_axi_lite_wready, axi_wdata => gpio_axi_lite_wdata, axi_wstrb => gpio_axi_lite_wstrb, axi_bvalid => gpio_axi_lite_bvalid, axi_bready => gpio_axi_lite_bready, axi_bresp => gpio_axi_lite_bresp, axi_araddr => gpio_axi_lite_araddr, axi_arprot => gpio_axi_lite_arprot, axi_arvalid => gpio_axi_lite_arvalid, axi_arready => gpio_axi_lite_arready, axi_rdata => gpio_axi_lite_rdata, axi_rvalid => gpio_axi_lite_rvalid, axi_rready => gpio_axi_lite_rready, axi_rresp => gpio_axi_lite_rresp); axi_cdma_inst : axi_cdma_0 PORT map ( m_axi_aclk => aclk, s_axi_lite_aclk => aclk, s_axi_lite_aresetn => aresetn(0), cdma_introut => cdma_int, s_axi_lite_awaddr => cdmareg_axi_lite_awaddr(5 downto 0), s_axi_lite_awvalid => cdmareg_axi_lite_awvalid, s_axi_lite_awready => cdmareg_axi_lite_awready, s_axi_lite_wvalid => cdmareg_axi_lite_wvalid, s_axi_lite_wready => cdmareg_axi_lite_wready, s_axi_lite_wdata => cdmareg_axi_lite_wdata, s_axi_lite_bvalid => cdmareg_axi_lite_bvalid, s_axi_lite_bready => cdmareg_axi_lite_bready, s_axi_lite_bresp => cdmareg_axi_lite_bresp, s_axi_lite_araddr => cdmareg_axi_lite_araddr(5 downto 0), s_axi_lite_arvalid => cdmareg_axi_lite_arvalid, s_axi_lite_arready => cdmareg_axi_lite_arready, s_axi_lite_rdata => cdmareg_axi_lite_rdata, s_axi_lite_rvalid => cdmareg_axi_lite_rvalid, s_axi_lite_rready => cdmareg_axi_lite_rready, s_axi_lite_rresp => cdmareg_axi_lite_rresp, m_axi_arready => cdma_axi_full_arready, m_axi_arvalid => cdma_axi_full_arvalid, m_axi_araddr => cdma_axi_full_araddr, m_axi_arlen => cdma_axi_full_arlen, m_axi_arsize => cdma_axi_full_arsize, m_axi_arburst => cdma_axi_full_arburst, m_axi_arprot => cdma_axi_full_arprot, m_axi_arcache => cdma_axi_full_arcache, m_axi_rready => cdma_axi_full_rready, m_axi_rvalid => cdma_axi_full_rvalid, m_axi_rdata => cdma_axi_full_rdata, m_axi_rresp => cdma_axi_full_rresp, m_axi_rlast => cdma_axi_full_rlast, m_axi_awready => cdma_axi_full_awready, m_axi_awvalid => cdma_axi_full_awvalid, m_axi_awaddr => cdma_axi_full_awaddr, m_axi_awlen => cdma_axi_full_awlen, m_axi_awsize => cdma_axi_full_awsize, m_axi_awburst => cdma_axi_full_awburst, m_axi_awprot => cdma_axi_full_awprot, m_axi_awcache => cdma_axi_full_awcache, m_axi_wready => cdma_axi_full_wready, m_axi_wvalid => cdma_axi_full_wvalid, m_axi_wdata => cdma_axi_full_wdata, m_axi_wstrb => cdma_axi_full_wstrb, m_axi_wlast => cdma_axi_full_wlast, m_axi_bready => cdma_axi_full_bready, m_axi_bvalid => cdma_axi_full_bvalid, m_axi_bresp => cdma_axi_full_bresp, cdma_tvect_out => open); plasoc_uart_inst : plasoc_uart generic map ( axi_address_width => axi_lite_address_width, axi_data_width => axi_data_width) port map ( aclk => aclk, aresetn => aresetn(0), axi_awaddr => uart_axi_lite_awaddr, axi_awprot => uart_axi_lite_awprot, axi_awvalid => uart_axi_lite_awvalid, axi_awready => uart_axi_lite_awready, axi_wvalid => uart_axi_lite_wvalid, axi_wready => uart_axi_lite_wready, axi_wdata => uart_axi_lite_wdata, axi_wstrb => uart_axi_lite_wstrb, axi_bvalid => uart_axi_lite_bvalid, axi_bready => uart_axi_lite_bready, axi_bresp => uart_axi_lite_bresp, axi_araddr => uart_axi_lite_araddr, axi_arprot => uart_axi_lite_arprot, axi_arvalid => uart_axi_lite_arvalid, axi_arready => uart_axi_lite_arready, axi_rdata => uart_axi_lite_rdata, axi_rvalid => uart_axi_lite_rvalid, axi_rready => uart_axi_lite_rready, axi_rresp => uart_axi_lite_rresp, tx => uart_tx, rx => uart_rx, status_in_avail => uart_int); plasoc_timer_extra_0_inst : plasoc_timer generic map ( axi_address_width => axi_lite_address_width, axi_data_width => axi_data_width) port map ( aclk => aclk, aresetn => aresetn(0), axi_awaddr => timer_extra_0_axi_lite_awaddr, axi_awprot => timer_extra_0_axi_lite_awprot, axi_awvalid => timer_extra_0_axi_lite_awvalid, axi_awready => timer_extra_0_axi_lite_awready, axi_wvalid => timer_extra_0_axi_lite_wvalid, axi_wready => timer_extra_0_axi_lite_wready, axi_wdata => timer_extra_0_axi_lite_wdata, axi_wstrb => timer_extra_0_axi_lite_wstrb, axi_bvalid => timer_extra_0_axi_lite_bvalid, axi_bready => timer_extra_0_axi_lite_bready, axi_bresp => timer_extra_0_axi_lite_bresp, axi_araddr => timer_extra_0_axi_lite_araddr, axi_arprot => timer_extra_0_axi_lite_arprot, axi_arvalid => timer_extra_0_axi_lite_arvalid, axi_arready => timer_extra_0_axi_lite_arready, axi_rdata => timer_extra_0_axi_lite_rdata, axi_rvalid => timer_extra_0_axi_lite_rvalid, axi_rready => timer_extra_0_axi_lite_rready, axi_rresp => timer_extra_0_axi_lite_rresp, done => timer_extra_0_int); end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity LS is Port ( x : in std_logic_vector(10 downto 0); shift : in std_logic_vector(2 downto 0); y : out std_logic_vector(18 downto 0)); -- y : out std_logic_vector(16 downto 0); -- clk : in std_logic); end LS; architecture Behavioral of LS is signal reg1 : std_logic_vector(13 downto 0); signal reg2 : std_logic_vector(17 downto 0); component mux2t1 Port ( In1 : in std_logic; In2 : in std_logic; sel : in std_logic; Output : out std_logic); -- Output : out std_logic; -- clock : in std_logic); end component; begin C1: mux2t1 port map('0', x(0), shift(0), reg1(0)); -- port map('0', x(0), shift(0), reg1(0), clk); Layer1 : for i in 1 to 10 generate C1: mux2t1 port map(x(i - 1), x(i), shift(0), reg1(i)); -- port map(x(i - 1), x(i), shift(0), reg1(i), clk); end generate; reg1(13) <= x(10); reg1(12) <= x(10); reg1(11) <= x(10); C20: mux2t1 port map('0', reg1(0), shift(1), reg2(0)); -- port map('0', reg1(0), shift(1), reg2(0), clk); C21: mux2t1 port map('0', reg1(1), shift(1), reg2(1)); -- port map('0', reg1(1), shift(1), reg2(1), clk); Layer2 : for i in 2 to 13 generate C2: mux2t1 port map(reg1(i - 2), reg1(i), shift(1), reg2(i)); -- port map(reg1(i - 2), reg1(i), shift(1), reg2(i), clk); end generate; reg2(17) <= x(10); reg2(16) <= x(10); reg2(15) <= x(10); reg2(14) <= x(10); C30: mux2t1 port map('0', reg2(0), shift(2), y(0)); -- port map('0', reg2(0), shift(2), y(0), clk); C31: mux2t1 port map('0', reg2(1), shift(2), y(1)); -- port map('0', reg2(1), shift(2), y(1), clk); C32: mux2t1 port map('0', reg2(2), shift(2), y(2)); -- port map('0', reg2(2), shift(2), y(2), clk); C33: mux2t1 port map('0', reg2(3), shift(2), y(3)); -- port map('0', reg2(3), shift(2), y(3), clk); Layer3 : for i in 4 to 17 generate C3: mux2t1 port map(reg2(i - 4), reg2(i), shift(2), y(i)); -- port map(reg2(i - 4), reg2(i), shift(2), y(i), clk); end generate; y(18) <= x(10); end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity new3phd is Port ( clk: in STD_LOGIC; pwmrefcnt: in STD_LOGIC_VECTOR(9 downto 0); ibus: in STD_LOGIC_VECTOR (31 downto 0); obus: out STD_LOGIC_VECTOR (31 downto 0); writestb: in STD_LOGIC; readstb: in STD_LOGIC; addr: in STD_LOGIC_VECTOR (1 downto 0); outa: out STD_LOGIC; outb: out STD_LOGIC; outc: out STD_LOGIC ); end new3phd; architecture behavioral of new3phd is signal creg: STD_LOGIC_VECTOR (2 downto 0); alias refmsb: std_logic is pwmrefcnt(9); signal oldrefmsb: std_logic; signal FIFORead: std_logic; signal Start: std_logic; signal HostStart: std_logic; signal PopData: STD_LOGIC_VECTOR (31 downto 0); alias PWMPtr: STD_LOGIC_VECTOR (1 downto 0) is PopData(1 downto 0); alias Aflag: std_logic is PopData(4); signal PushData: STD_LOGIC_VECTOR (31 downto 0); signal FIFOdatawr: STD_LOGIC; signal IncDataCount: STD_LOGIC; signal IncDataCountp: STD_LOGIC; signal PushPtr: STD_LOGIC_VECTOR (7 downto 0); signal PopPtr: STD_LOGIC_VECTOR (7 downto 0); signal FPopPtr: STD_LOGIC_VECTOR (7 downto 0); signal DataCount: STD_LOGIC_VECTOR (8 downto 0); signal pwmas: STD_LOGIC_VECTOR (9 downto 0); signal pwmbs: STD_LOGIC_VECTOR (9 downto 0); signal pwmcs: STD_LOGIC_VECTOR (9 downto 0); signal pwmae: STD_LOGIC_VECTOR (9 downto 0); signal pwmbe: STD_LOGIC_VECTOR (9 downto 0); signal pwmce: STD_LOGIC_VECTOR (9 downto 0); signal pwmapol: STD_LOGIC; signal pwmbpol: STD_LOGIC; signal pwmcpol: STD_LOGIC; signal pwmouta: STD_LOGIC; signal pwmoutb: STD_LOGIC; signal pwmoutc: STD_LOGIC; component FIFOMem32 IS port ( addra: IN std_logic_VECTOR(7 downto 0); addrb: IN std_logic_VECTOR(7 downto 0); clka: IN std_logic; clkb: IN std_logic; dina: IN std_logic_VECTOR(31 downto 0); dinb: IN std_logic_VECTOR(31 downto 0); douta: OUT std_logic_VECTOR(31 downto 0); doutb: OUT std_logic_VECTOR(31 downto 0); wea: IN std_logic; web: IN std_logic); end component FIFOMem32; begin AFIFO: FIFOMem32 port map ( addra => FPopPtr, addrb => PushPtr, clka => clk, clkb => clk, dina => x"00000000", dinb => ibus, douta => PopData, doutb => PushData, wea => '0', web => FIFOdatawr ); athreephase: process (clk,addr,readstb,writestb, creg, pwmouta, pwmoutb, pwmoutc ) begin if clk'event and clk = '1' then IncDataCount <= IncDataCountP; if (IncDataCount = '1') and (FIFOREAD = '0') then IncDataCount <= '0'; IncDataCountP <= '0'; DataCount <= DataCount + 1; end if; if (UNSIGNED(pwmrefcnt) >= UNSIGNED(pwmas)) and (UNSIGNED(pwmrefcnt) <= UNSIGNED(pwmae)) then pwmouta <= '1' xor pwmapol; else pwmouta <= '0' xor pwmapol; end if; if (UNSIGNED(pwmrefcnt) >= UNSIGNED(pwmbs)) and (UNSIGNED(pwmrefcnt) <= UNSIGNED(pwmbe)) then pwmoutb <= '1' xor pwmbpol; else pwmoutb <= '0' xor pwmbpol; end if; if (UNSIGNED(pwmrefcnt) >= UNSIGNED(pwmcs)) and (UNSIGNED(pwmrefcnt) <= UNSIGNED(pwmce)) then pwmoutc <= '1' xor pwmcpol; else pwmoutc <= '0' xor pwmcpol; end if; oldrefmsb <= refmsb; if FIFORead = '1' and DataCount /= 0 then case PWMPtr is when "00" => pwmas <= PopData(14 downto 5); pwmae <= PopData(30 downto 21); pwmapol <= PopData(31); when "01" => pwmbs <= PopData(14 downto 5); pwmbe <= PopData(30 downto 21); pwmbpol <= PopData(31); when "10" => pwmcs <= PopData(14 downto 5); pwmce <= PopData(30 downto 21); pwmcpol <= PopData(31); when others => null; end case; PopPtr <= FPopPtr; DataCount <= DataCount -1; end if; if writestb = '1' then case addr is when "00" => PushPtr <= PushPtr + 1; IncDataCountp <= '1'; when "01" => creg <= ibus(2 downto 0); when "10" => Datacount <= (others => '0'); PopPtr <= (others => '0'); PushPtr <= (others => '0'); when others => null; end case; end if; end if; -- clk if ((Start = '1') or (AFlag = '0')) and (DataCount /= 0) then FIFORead <= '1'; FPopPtr <= PopPtr +1; else FIFORead <= '0'; FPopPtr <= PopPtr; end if; if writestb = '1' and addr = "11" then HostStart <= '1'; else HostStart <= '0'; end if; if writestb = '1' and addr = "00" then FIFOdataWr <= '1'; else FIFODataWr <= '0'; end if; if (oldrefmsb = '1' and refmsb = '0' and AFlag = '1' and creg(0) = '1') or (Hoststart = '1' ) then Start <= '1'; else Start <= '0'; end if; obus <= (others => 'Z'); if readstb = '1' then case addr is when "00" => obus <= PopData; when "01" => obus <= (2 => creg(2),1 => creg(1),0 =>creg(0), others => '0'); when "10" => obus(8 downto 0) <= DataCount; when others => obus <= (others => 'Z'); end case; else obus <= (others => 'Z'); end if; if creg(1) = '1' then if creg(2) = '0' then outa <= pwmouta; outb <= pwmoutb; outc <= pwmoutc; else outa <= pwmoutb; outb <= pwmouta; outc <= pwmoutc; end if; else outa <= 'Z'; outb <= 'Z'; outc <= 'Z'; end if; end process; end behavioral;
---------------------------------------------------------------------------------- -- Engineer: Mike Field <hamster@snap.net.nz> -- -- Module Name: input_serialiser -- -- Description: A 5-bits per cycle SDR input serialiser -- -- Maybe in the future the 'bitslip' funciton can be implemented. ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VComponents.all; entity input_serialiser is Port ( clk_fabric_x2 : in STD_LOGIC; clk_input : in STD_LOGIC; strobe : in STD_LOGIC; ser_data : out STD_LOGIC_VECTOR (4 downto 0); ser_input : in STD_LOGIC); end input_serialiser; architecture Behavioral of input_serialiser is signal clk0, clk1, clkdiv : std_logic; signal cascade : std_logic; constant bitslip : std_logic := '0'; begin clkdiv <= clk_fabric_x2; clk0 <= clk_input; clk1 <= '0'; ISERDES2_master : ISERDES2 generic map ( BITSLIP_ENABLE => TRUE, -- Enable Bitslip Functionality (TRUE/FALSE) DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR") DATA_WIDTH => 5, -- Parallel data width selection (2-8) INTERFACE_TYPE => "RETIMED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED" SERDES_MODE => "MASTER" -- "NONE", "MASTER" or "SLAVE" ) port map ( CFB0 => open, -- 1-bit output: Clock feed-through route output CFB1 => open, -- 1-bit output: Clock feed-through route output DFB => open, -- 1-bit output: Feed-through clock output FABRICOUT => open, -- 1-bit output: Unsynchrnonized data output INCDEC => open, -- 1-bit output: Phase detector output -- Q1 - Q4: 1-bit (each) output: Registered outputs to FPGA logic Q1 => ser_data(1), Q2 => ser_data(2), Q3 => ser_data(3), Q4 => ser_data(4), SHIFTOUT => cascade, -- 1-bit output: Cascade output signal for master/slave I/O VALID => open, -- 1-bit output: Output status of the phase detector BITSLIP => bitslip , -- 1-bit input: Bitslip enable input CE0 => '1', -- 1-bit input: Clock enable input CLK0 => clk0, -- 1-bit input: I/O clock network input CLK1 => clk1, -- 1-bit input: Secondary I/O clock network input CLKDIV => clkdiv, -- 1-bit input: FPGA logic domain clock input D => ser_input, -- 1-bit input: Input data IOCE => strobe, -- 1-bit input: Data strobe input RST => '0', -- 1-bit input: Asynchronous reset input SHIFTIN => '0' -- 1-bit input: Cascade input signal for master/slave I/O ); ISERDES2_slave : ISERDES2 generic map ( BITSLIP_ENABLE => TRUE, -- Enable Bitslip Functionality (TRUE/FALSE) DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR") DATA_WIDTH => 5, -- Parallel data width selection (2-8) INTERFACE_TYPE => "RETIMED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED" SERDES_MODE => "SLAVE" -- "NONE", "MASTER" or "SLAVE" ) port map ( CFB0 => open, -- 1-bit output: Clock feed-through route output CFB1 => open, -- 1-bit output: Clock feed-through route output DFB => open, -- 1-bit output: Feed-through clock output FABRICOUT => open, -- 1-bit output: Unsynchrnonized data output INCDEC => open, -- 1-bit output: Phase detector output -- Q1 - Q4: 1-bit (each) output: Registered outputs to FPGA logic Q1 => open, Q2 => open, Q3 => open, Q4 => ser_data(0), SHIFTOUT => open, -- 1-bit output: Cascade output signal for master/slave I/O VALID => open, -- 1-bit output: Output status of the phase detector BITSLIP => bitslip, -- 1-bit input: Bitslip enable input CE0 => '1', -- 1-bit input: Clock enable input CLK0 => clk0, -- 1-bit input: I/O clock network input CLK1 => clk1, -- 1-bit input: Secondary I/O clock network input CLKDIV => clkdiv, -- 1-bit input: FPGA logic domain clock input D => '0', -- 1-bit input: Input data IOCE => '1', -- 1-bit input: Data strobe input RST => '0', -- 1-bit input: Asynchronous reset input SHIFTIN => cascade -- 1-bit input: Cascade input signal for master/slave I/O ); end Behavioral;
---------------------------------------------------------------------------------- -- Engineer: Mike Field <hamster@snap.net.nz> -- -- Module Name: input_serialiser -- -- Description: A 5-bits per cycle SDR input serialiser -- -- Maybe in the future the 'bitslip' funciton can be implemented. ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VComponents.all; entity input_serialiser is Port ( clk_fabric_x2 : in STD_LOGIC; clk_input : in STD_LOGIC; strobe : in STD_LOGIC; ser_data : out STD_LOGIC_VECTOR (4 downto 0); ser_input : in STD_LOGIC); end input_serialiser; architecture Behavioral of input_serialiser is signal clk0, clk1, clkdiv : std_logic; signal cascade : std_logic; constant bitslip : std_logic := '0'; begin clkdiv <= clk_fabric_x2; clk0 <= clk_input; clk1 <= '0'; ISERDES2_master : ISERDES2 generic map ( BITSLIP_ENABLE => TRUE, -- Enable Bitslip Functionality (TRUE/FALSE) DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR") DATA_WIDTH => 5, -- Parallel data width selection (2-8) INTERFACE_TYPE => "RETIMED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED" SERDES_MODE => "MASTER" -- "NONE", "MASTER" or "SLAVE" ) port map ( CFB0 => open, -- 1-bit output: Clock feed-through route output CFB1 => open, -- 1-bit output: Clock feed-through route output DFB => open, -- 1-bit output: Feed-through clock output FABRICOUT => open, -- 1-bit output: Unsynchrnonized data output INCDEC => open, -- 1-bit output: Phase detector output -- Q1 - Q4: 1-bit (each) output: Registered outputs to FPGA logic Q1 => ser_data(1), Q2 => ser_data(2), Q3 => ser_data(3), Q4 => ser_data(4), SHIFTOUT => cascade, -- 1-bit output: Cascade output signal for master/slave I/O VALID => open, -- 1-bit output: Output status of the phase detector BITSLIP => bitslip , -- 1-bit input: Bitslip enable input CE0 => '1', -- 1-bit input: Clock enable input CLK0 => clk0, -- 1-bit input: I/O clock network input CLK1 => clk1, -- 1-bit input: Secondary I/O clock network input CLKDIV => clkdiv, -- 1-bit input: FPGA logic domain clock input D => ser_input, -- 1-bit input: Input data IOCE => strobe, -- 1-bit input: Data strobe input RST => '0', -- 1-bit input: Asynchronous reset input SHIFTIN => '0' -- 1-bit input: Cascade input signal for master/slave I/O ); ISERDES2_slave : ISERDES2 generic map ( BITSLIP_ENABLE => TRUE, -- Enable Bitslip Functionality (TRUE/FALSE) DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR") DATA_WIDTH => 5, -- Parallel data width selection (2-8) INTERFACE_TYPE => "RETIMED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED" SERDES_MODE => "SLAVE" -- "NONE", "MASTER" or "SLAVE" ) port map ( CFB0 => open, -- 1-bit output: Clock feed-through route output CFB1 => open, -- 1-bit output: Clock feed-through route output DFB => open, -- 1-bit output: Feed-through clock output FABRICOUT => open, -- 1-bit output: Unsynchrnonized data output INCDEC => open, -- 1-bit output: Phase detector output -- Q1 - Q4: 1-bit (each) output: Registered outputs to FPGA logic Q1 => open, Q2 => open, Q3 => open, Q4 => ser_data(0), SHIFTOUT => open, -- 1-bit output: Cascade output signal for master/slave I/O VALID => open, -- 1-bit output: Output status of the phase detector BITSLIP => bitslip, -- 1-bit input: Bitslip enable input CE0 => '1', -- 1-bit input: Clock enable input CLK0 => clk0, -- 1-bit input: I/O clock network input CLK1 => clk1, -- 1-bit input: Secondary I/O clock network input CLKDIV => clkdiv, -- 1-bit input: FPGA logic domain clock input D => '0', -- 1-bit input: Input data IOCE => '1', -- 1-bit input: Data strobe input RST => '0', -- 1-bit input: Asynchronous reset input SHIFTIN => cascade -- 1-bit input: Cascade input signal for master/slave I/O ); end Behavioral;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity fc_system_v4 is port( flight_no : in std_logic_vector(2 downto 0); request: in std_logic; reset,clk : in std_logic; clk3_out,clk10_out : out std_logic;--For demo only grant,denied: out std_logic ); end fc_system_v4; architecture beh of fc_system_v4 is type state_type is (IDLE,WBReq,WBGrant,WBOnly,Deny,Deny_t,NBReq,NBGrant); signal state_reg,state_next:state_type; signal clk3_count,clk10_count : unsigned(26 downto 0); signal pulse3_1sec,pulse10_1sec: std_logic; signal clk10_reg,clk10_next:unsigned(3 downto 0); signal clk3_reg,clk3_next:unsigned(1 downto 0); signal load10_clk,load3_clk:std_logic; signal clk3_out_reg,clk3_out_next,clk10_out_reg,clk10_out_next:std_logic;--Demo only signal reset3,reset10:std_logic; begin process(clk,reset) begin if(reset ='1') then state_reg<=IDLE; elsif (clk' event and clk ='1') then state_reg<=state_next; end if; end process; --Clock process process(clk,reset3) begin if(reset3 ='1') then clk3_count <= (others => '0'); elsif (clk' event and clk ='1') then clk3_count <= clk3_count + 1; end if; end process; process(clk,reset10) begin if(reset10 ='1') then clk10_count <= (others => '0'); elsif (clk' event and clk ='1') then clk10_count <= clk10_count + 1; end if; end process; process(pulse10_1sec,load10_clk) begin if(load10_clk ='1') then clk10_reg<="1010"; clk10_out_reg<='1'; elsif(pulse10_1sec' event and pulse10_1sec ='1') then clk10_reg <= clk10_next; clk10_out_reg <= clk10_out_next;--Demo only end if; end process; process(pulse3_1sec,load3_clk) begin if(load3_clk ='1') then clk3_reg<="11"; clk3_out_reg<='1'; elsif(pulse3_1sec' event and pulse3_1sec ='1') then clk3_reg <= clk3_next; clk3_out_reg <= clk3_out_next;--Demo only end if; end process; pulse3_1sec <= clk3_count(26); pulse10_1sec <= clk10_count(26); reset3 <= load3_clk or reset; reset10 <= load10_clk or reset; clk3_out_next <= not clk3_out_reg; clk10_out_next <= not clk10_out_reg; clk3_out<=clk3_out_reg; clk10_out<=clk10_out_reg; clk10_next <= (others =>'0') when (clk10_reg = "0000") else (clk10_reg - 1); clk3_next <= (others => '0') when (clk3_reg ="00" ) else (clk3_reg - 1); --Next state logic and output logic process(state_reg,request,clk10_reg,clk3_reg) begin grant <= '0'; denied <='0'; load10_clk <='0'; load3_clk <='0'; case state_reg is when IDLE => if(request ='1') then if(flight_no="001" or flight_no="011" or flight_no ="111") then state_next <= WBReq; else state_next <= NBReq; end if; else state_next <= IDLE; end if; when WBReq=> load10_clk<='1'; state_next <= WBGrant; when WBGrant => if(clk10_reg = "0111") then --3Sec elapsed state_next <= WBOnly; else state_next <= WBGrant; end if; grant <= '1'; when WBOnly => if(request = '1') then if(flight_no="001" or flight_no="011" or flight_no ="111") then state_next <= WBReq; else state_next <= Deny_t; end if; elsif(clk10_reg="0000") then state_next <= IDLE; else state_next <= WBOnly; end if; when Deny_t => load3_clk <='1'; state_next <= Deny; when Deny => if(clk3_reg = "00") then state_next<=WBOnly; else state_next <= Deny; end if; denied <='1'; when NBReq => load3_clk <='1'; --load10_clk <='1'; --Demo purposr only state_next <= NBGrant; when NBGrant => if(clk3_reg ="00") then state_next <= IDLE; else state_next <= NBGrant; end if; grant <= '1'; end case; end process; end beh;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_textio.all; entity scratch_pad is port ( data_in1, data_in2 : in std_logic_vector(7 downto 0); raddr_write1, raddr_write2 : in std_logic_vector(3 downto 0); data_out : out std_logic_vector(7 downto 0); raddr_read : in std_logic_vector(3 downto 0); re, we, clk : in std_logic ); end entity; architecture behav of scratch_pad is type mem_array is array(15 downto 0) of std_logic_vector(7 downto 0); signal mem_data : mem_array; begin process (clk) begin if (rising_edge(clk) and (we = '1')) then mem_data(conv_integer(raddr_write1)) <= data_in1; report "Scratch Pad write addr: " & integer'image(conv_integer(raddr_write1)) & " data: " & integer'image(conv_integer(data_in1)); mem_data(conv_integer(raddr_write2)) <= data_in2; report "Scratch Pad write addr: " & integer'image(conv_integer(raddr_write2)) & " data: " & integer'image(conv_integer(data_in2)); elsif (falling_edge(clk) and (re = '1')) then data_out <= mem_data(conv_integer(raddr_read)); report "Scratch Pad read addr: " & integer'image(conv_integer(raddr_read)) & " data: " & integer'image(conv_integer(mem_data(conv_integer(raddr_read)))); end if; end process; end architecture;
package pack1 is type my_int1 is range 0 to 10; end package; ------------------------------------------------------------------------------- package pack2 is type my_int1 is range 0 to 10; end package; ------------------------------------------------------------------------------- use work.pack1; use work.pack2; entity no_use_clause is port ( a : in pack1.my_int1; b : out pack2.my_int1 ); end entity; ------------------------------------------------------------------------------- architecture a of no_use_clause is type my_int1 is range 10 to 50; begin process is begin -- Should fail as types have same name but from different packages b <= a; end process; process is variable v : pack2.my_int1; begin b <= v; -- OK end process; process is variable v : my_int1; begin -- Should fail as local my_int1 distinct from pack1.my_int1 v := a; end process; end architecture; ------------------------------------------------------------------------------- use work.pack1.all; entity foo is generic ( g : my_int1 ); port ( p : in my_int1 ); end entity; ------------------------------------------------------------------------------- architecture a of foo is -- Architecture decls exist in same scope as entity so this should -- generate an error signal g : my_int1; begin end architecture; ------------------------------------------------------------------------------- architecture b of foo is -- Should also generate an error signal p : my_int1; begin end architecture; ------------------------------------------------------------------------------- architecture c of foo is begin -- This is OK as processes define a new scope process is variable p : my_int1; variable g : my_int1; begin g := 6; p := 2; wait for 1 ns; end process; end architecture; ------------------------------------------------------------------------------- entity overload is port ( SI: in bit; SO: out bit ); end ; architecture behave of overload is begin foo_inst: SO <= SI; end behave; ------------------------------------------------------------------------------- use work.all; entity no_use_clause is port ( a : in pack1.my_int1; -- OK b : out my_int1 ); -- Error end entity; ------------------------------------------------------------------------------- package pack3 is type my_enum is (E1, E2, E3); end package; ------------------------------------------------------------------------------- use work.pack3.all; package pack4 is type my_enum_array is array (integer range <>) of my_enum; end package; ------------------------------------------------------------------------------- use work.pack4.all; architecture a of foo is signal x : my_enum_array(1 to 3); -- OK signal y : my_enum_array(1 to 3) := (others => E1); -- Error: E1 not visible begin end architecture; ------------------------------------------------------------------------------- package pack5 is function func1(x : integer) return boolean; function func2(x : integer) return boolean; function "and"(x, y : integer) return boolean; end package; ------------------------------------------------------------------------------- use work.pack5.func1; architecture a2 of foo is begin process is begin assert func1(4); -- OK assert func2(5); -- Error end process; end architecture; ------------------------------------------------------------------------------- use work.pack5.not_here; -- Error architecture a3 of foo is begin end architecture; ------------------------------------------------------------------------------- entity bar is end entity; architecture a4 of bar is begin process is use work.pack1.all; variable x : my_int1; -- OK begin x := 5; end process; process is variable x : my_int1; -- Error begin end process; b: block is use work.pack1; signal x : pack1.my_int1; -- OK begin end block; end architecture; ------------------------------------------------------------------------------- use work.pack5."and"; architecture a5 of bar is begin process is begin assert 1 and 2; -- OK assert work.pack5."and"(1, 2); -- OK assert pack5."and"(1, 2); -- OK end process; end architecture; ------------------------------------------------------------------------------- package pack6 is component bar is end component; end package; ------------------------------------------------------------------------------- use work.pack6.all; architecture a6 of bar is begin process is begin report bar'path_name; -- OK (references entity) end process; end architecture; ------------------------------------------------------------------------------- use foo.bar.all; -- Error architecture a7 of bar is begin end architecture; ------------------------------------------------------------------------------- package pack7 is function foo(x : in integer) return boolean; function foo(y : in real) return boolean; end package; ------------------------------------------------------------------------------- use work.pack7.foo; architecture issue62 of bar is begin process is begin assert foo(integer'(1)); -- OK assert foo(real'(1.6)); -- OK end process; end architecture; ------------------------------------------------------------------------------- use work.all; use work.pack1.all; architecture issue63 of bar is signal x : my_int1; -- OK begin end architecture; ------------------------------------------------------------------------------- package pack8 is function min(x, y : in integer) return integer; end package; ------------------------------------------------------------------------------- use work.pack8.all; -- OK architecture unit_decl_crash of bar is begin process is variable x : integer := min(1, 2); -- OK begin end process; end architecture;
architecture RTL of FIFO is begin process begin -- These are passing a := b or d; a := '0' when c = '0' else '1' when d = '1' else 'Z'; -- Failing variations a := b or d; a := '0' when c = '0' else '1' when d = '1' else 'Z'; end process; end architecture RTL;
-- -- All rights reserved -- -- Redistribution and use in source and synthezised forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- * Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- -- * Redistributions in synthesized form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- * Neither the name of the author nor the names of other contributors may -- be used to endorse or promote products derived from this software without -- specific prior written agreement from the author. -- -- * License is granted for non-commercial use only. A fee may not be charged -- for redistributions as source code or in synthesized/hardware form without -- specific prior written agreement from the author. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; -- for AND_REDUCE use ieee.numeric_std.all; entity i2c_loader is generic ( device_address : integer := 16#1a#; -- Address of slave to be loaded num_retries : integer := 0; -- Number of retries to allow before stopping log2_divider : integer := 6 -- Length of clock divider in bits. Resulting bus frequency is CLK/2^(log2_divider + 2) ); port ( clock_i : in std_logic; reset_i : in std_logic; i2c_scl_io : inout std_logic; i2c_sda_io : inout std_logic; is_done_o : out std_logic; is_error_o : out std_logic ); end entity; architecture rtl of i2c_loader is --/---------+---------------------------+---------+--------+---------+--------+------+------+------+--------+---------\ --\|Register \|B15 B14 B13 B12 B11 B10 B9 \| B8 \| B7 \| B6 \| B5 \| B4 \| B3 \| B2 \| B1 \| B0 \| --+---------+---------------------------+---------+--------+---------+--------+------+------+------+--------+---------+ --\|R0 (00h) \| 0 0 0 0 0 0 0 \|LRIN BOTH\|LIN MUTE\| 0 \| 0 \| LINVOL \| --+---------+---------------------------+---------+--------+---------+--------+---------------------------------------+ --\|R1 (02h) \| 0 0 0 0 0 0 1 \|RLIN BOTH\|RIN MUTE\| 0 \| 0 \| RINVOL \| --+---------+---------------------------+---------+--------+---------+--------+---------------------------------------+ --\|R2 (04h) \| 0 0 0 0 0 1 0 \|LRHP BOTH\|LZCEN \| LHPVOL \| --+---------+---------------------------+---------+--------+----------------------------------------------------------+ --\|R3 (06h) \| 0 0 0 0 0 1 1 \|RLHP BOTH\|RZCEN \| RHPVOL \| --+---------+---------------------------+---------+--------+---------+--------+------+------+------+--------+---------+ --\|R4 (08h) \| 0 0 0 0 1 0 0 \| 0 \| SIDEATT \|SIDETONE\|DACSEL\|BYPASS\|INSEL \|MUTE MIC\|MIC BOOST\| --+---------+---------------------------+---------+--------+---------+--------+------+------+------+--------+---------+ --\|R5 (0Ah) \| 0 0 0 0 1 0 1 \| 0 \| 0 \| 0 \| 0 \| HPOR \|DAC MU\| DEEMPH \| ADC HPD \| --+---------+---------------------------+---------+--------+---------+--------+------+------+------+--------+---------+ --\|R6 (0Ch) \| 0 0 0 0 1 1 0 \| 0 \|PWR OFF \|CLK OUTPD\| OSCPD \|OUTPD \|DACPD \|ADCPD \| MICPD \|LINEINPD \| --+---------+---------------------------+---------+--------+---------+--------+------+------+------+--------+---------+ --\|R7 (0Eh) \| 0 0 0 0 1 1 1 \| 0 \|BCLK INV\| MS \|LR SWAP \| LRP \| IWL \| FORMAT \| --+---------+---------------------------+---------+--------+---------+--------+------+-------------+--------+---------+ --\|R8 (10h) \| 0 0 0 1 0 0 0 \| 0 \|CLKO /2 \| CLKI /2 \| SR \| BOSR \|USB/NORM \| --+---------+---------------------------+---------+--------+---------+--------+------+------+------+--------+---------+ --\|R9 (12h) \| 0 0 0 1 0 0 1 \| 0 \| 0 \| 0 \| 0 \| 0 \| 0 \| 0 \| 0 \| ACTIVE \| --+---------+---------------------------+---------+--------+---------+--------+------+------+------+--------+---------+ --\|R15 (1Eh)\| 0 0 0 1 1 1 1 \| RESET \| --\---------+---------------------------+-----------------------------------------------------------------------------/ type regs is array(0 to 21) of std_logic_vector(7 downto 0); constant init_regs : regs := ( X"00", X"00", -- dummy X"00", X"08", -- Left line in, unmute, ?dB -- 0 0 00 10111 X"02", X"80", -- Right line in, mute -- 0 1 00 00000 X"04", X"79", -- Left headphone out, 0dB X"06", X"79", -- Right headphone out, 0dB X"08", X"10", -- Audio path, DAC enabled, Line in, Bypass off, mic unmuted -- X"0A", X"00", -- Digital path, Unmute, HP filter enabled, no DEEMPH -- X"0A", X"02", -- Digital path, Unmute, HP filter enabled, DEEMPH 32KHz -- X"0A", X"04", -- Digital path, Unmute, HP filter enabled, DEEMPH 44.1KHz X"0A", X"06", -- Digital path, Unmute, HP filter enabled, DEEMPH 48KHz X"0C", X"62", -- Power down mic, clkout and xtal osc X"0E", X"02", -- Format 16-bit I2S, no bit inversion or phase changes -- X"10", X"0D", -- Sampling control, 8 kHz USB mode (MCLK = 250fs * 6) -- X"10", X"01", -- Sampling control, 48 KHz, USB mode (MCLK = 250fs) -- X"10", X"3F", -- Sampling control, 88.2 KHz, USB mode (MCLK = 136fs) X"10", X"1D", -- Sampling control, 96 KHz, USB mode (MCLK = 125fs) X"12", X"01" -- Activate ); constant burst_length : positive := 2; -- Number of bursts (i.e. total number of registers) constant num_bursts : positive := (init_regs'length / burst_length); -- Number of bytes to transfer per burst type state_t is (Idle, Start, Data, Ack, Stop, Pause, Done); signal state : state_t; signal phase : std_logic_vector(1 downto 0); subtype nbit_t is integer range 0 to 7; signal nbit : nbit_t; subtype nbyte_t is integer range 0 to burst_length; -- +1 for address byte signal nbyte : nbyte_t; subtype thisbyte_t is integer range 0 to init_regs'length; -- +1 for "done" signal thisbyte : thisbyte_t; subtype retries_t is integer range 0 to num_retries; signal retries : retries_t; signal clken : std_logic; signal divider : std_logic_vector(log2_divider-1 downto 0); signal shiftreg : std_logic_vector(7 downto 0); signal scl_out : std_logic; signal sda_out : std_logic; signal nak : std_logic; begin -- Create open-drain outputs for I2C bus i2c_scl_io <= '0' when scl_out = '0' else 'Z'; i2c_sda_io <= '0' when sda_out = '0' else 'Z'; -- Status outputs are driven both ways is_done_o <= '1' when state = Done else '0'; is_error_o <= nak; -- Generate clock enable for desired bus speed clken <= AND_REDUCE(divider); process(reset_i, clock_i) begin if reset_i = '1' then divider <= (others => '0'); elsif falling_edge(clock_i) then divider <= divider + '1'; end if; end process; -- The I2C loader process process(reset_i, clock_i, clken) begin if reset_i = '1' then scl_out <= '1'; sda_out <= '1'; state <= Idle; phase <= "00"; nbit <= 0; nbyte <= 0; thisbyte <= 0; shiftreg <= (others => '0'); nak <= '0'; -- No error retries <= num_retries; elsif rising_edge(clock_i) and clken = '1' then -- Next phase by default phase <= phase + 1; -- STATE: IDLE if state = Idle then -- Start loading the device registers straight away -- A 'GO' bit could be polled here if required state <= Start; phase <= "00"; scl_out <= '1'; sda_out <= '1'; -- STATE: START elsif state = Start then -- Generate START condition case phase is when "00" => -- Drop SDA first sda_out <= '0'; when "10" => -- Then drop SCL scl_out <= '0'; when "11" => -- Advance to next state -- Shift register loaded with device slave address state <= Data; nbit <= 7; shiftreg <= std_logic_vector(to_unsigned(device_address,7)) & '0'; -- writing nbyte <= burst_length; when others => null; end case; -- STATE: DATA elsif state = Data then -- Generate data case phase is when "00" => -- Drop SCL scl_out <= '0'; when "01" => -- Output data and shift (MSb first) sda_out <= shiftreg(7); shiftreg <= shiftreg(6 downto 0) & '0'; when "10" => -- Raise SCL scl_out <= '1'; when "11" => -- Next bit or advance to next state when done if nbit = 0 then state <= Ack; else nbit <= nbit - 1; end if; when others => null; end case; -- STATE: ACK elsif state = Ack then -- Generate ACK clock and check for error condition case phase is when "00" => -- Drop SCL scl_out <= '0'; when "01" => -- Float data sda_out <= '1'; when "10" => -- Sample ack bit nak <= i2c_sda_io; if i2c_sda_io = '1' then -- Error nbyte <= 0; -- Close this burst and skip remaining registers thisbyte <= init_regs'length; else -- Hold ACK to avoid spurious stops - this seems to fix a -- problem with the Wolfson codec which releases the ACK -- right on the falling edge of the clock pulse. It looks like -- the device interprets this is a STOP condition and then fails -- to acknowledge the next byte. We can avoid this by holding the -- ACK condition for a little longer. sda_out <= '0'; end if; -- Raise SCL scl_out <= '1'; when "11" => -- Advance to next state if nbyte = 0 then -- No more bytes in this burst - generate a STOP state <= Stop; else -- Generate next byte state <= Data; nbit <= 7; shiftreg <= init_regs(thisbyte); nbyte <= nbyte - 1; thisbyte <= thisbyte + 1; end if; when others => null; end case; -- STATE: STOP elsif state = Stop then -- Generate STOP condition case phase is when "00" => -- Drop SCL first scl_out <= '0'; when "01" => -- Drop SDA sda_out <= '0'; when "10" => -- Raise SCL scl_out <= '1'; when "11" => if thisbyte = init_regs'length then -- All registers done, advance to finished state. This will -- bring SDA high while SCL is still high, completing the STOP -- condition state <= Done; else -- Load the next register after a short delay state <= Pause; end if; when others => null; end case; -- STATE: PAUSE elsif state = Pause then -- Delay for one cycle of 'phase' then start the next burst scl_out <= '1'; sda_out <= '1'; if phase = "11" then state <= Start; end if; -- STATE: DONE else -- Finished scl_out <= '1'; sda_out <= '1'; if nak = '1' and retries > 0 then -- We can retry in the event of a NAK in case the -- slave got out of sync for some reason retries <= retries - 1; state <= Idle; end if; end if; end if; end process; end architecture;
architecture ARCH of ENTITY1 is begin U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); -- Violations below U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); end architecture ARCH;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2013, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: syncram64 -- File: syncram64.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: 64-bit syncronous 1-port ram with 32-bit write strobes -- and tech selection ------------------------------------------------------------------------------ library ieee; library techmap; use ieee.std_logic_1164.all; use techmap.gencomp.all; use techmap.allmem.all; library grlib; use grlib.config.all; use grlib.config_types.all; use grlib.stdlib.all; entity syncram64 is generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; paren : integer := 0; custombits : integer := 1); port ( clk : in std_ulogic; address : in std_logic_vector (abits -1 downto 0); datain : in std_logic_vector (63+8paren downto 0); dataout : out std_logic_vector (63+8paren downto 0); enable : in std_logic_vector (1 downto 0); write : in std_logic_vector (1 downto 0); testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none; customclk: in std_ulogic := '0'; customin : in std_logic_vector(2custombits-1 downto 0) := (others => '0'); customout:out std_logic_vector(2custombits-1 downto 0)); end; architecture rtl of syncram64 is component unisim_syncram64 generic ( abits : integer := 9); port ( clk : in std_ulogic; address : in std_logic_vector (abits -1 downto 0); datain : in std_logic_vector (63 downto 0); dataout : out std_logic_vector (63 downto 0); enable : in std_logic_vector (1 downto 0); write : in std_logic_vector (1 downto 0) ); end component; component artisan_syncram64 generic ( abits : integer := 9); port ( clk : in std_ulogic; address : in std_logic_vector (abits -1 downto 0); datain : in std_logic_vector (63 downto 0); dataout : out std_logic_vector (63 downto 0); enable : in std_logic_vector (1 downto 0); write : in std_logic_vector (1 downto 0) ); end component; component custom1_syncram64 generic ( abits : integer := 9); port ( clk : in std_ulogic; address : in std_logic_vector (abits -1 downto 0); datain : in std_logic_vector (63 downto 0); dataout : out std_logic_vector (63 downto 0); enable : in std_logic_vector (1 downto 0); write : in std_logic_vector (1 downto 0) ); end component; component smic13_syncram64 generic ( abits : integer := 9); port ( clk : in std_ulogic; address : in std_logic_vector (abits -1 downto 0); datain : in std_logic_vector (63 downto 0); dataout : out std_logic_vector (63 downto 0); enable : in std_logic_vector (1 downto 0); write : in std_logic_vector (1 downto 0) ); end component; signal dinp, doutp : std_logic_vector(71 downto 0); signal xenable : std_logic_vector(1 downto 0); signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0); begin xenable <= enable when testen=0 or testin(TESTIN_WIDTH-2)='0' else "00"; custominx(custominx'high downto custombits) <= (others => '0'); custominx(custombits-1 downto 0) <= customin(custombits-1 downto 0); nocust: if syncram_has_customif(tech)=0 or has_sram64(tech)=0 or paren=1 generate customoutx <= (others => '0'); end generate; nopar : if paren = 0 generate s64 : if has_sram64(tech) = 1 generate xc2v : if (is_unisim(tech) = 1) generate x0 : unisim_syncram64 generic map (abits) port map (clk, address, datain(63 downto 0), dataout(63 downto 0), xenable, write); end generate; arti : if tech = memartisan generate x0 : artisan_syncram64 generic map (abits) port map (clk, address, datain(63 downto 0), dataout(63 downto 0), xenable, write); end generate; cust1: if tech = custom1 generate x0 : custom1_syncram64 generic map (abits) port map (clk, address, datain(63 downto 0), dataout(63 downto 0), xenable, write); end generate; smic: if tech = smic013 generate x0 : smic13_syncram64 generic map (abits) port map (clk, address, datain(63 downto 0), dataout(63 downto 0), xenable, write); end generate; n2x : if tech = easic45 generate x0 : n2x_syncram_we generic map (abits => abits, dbits => 64) port map(clk, address, datain(63 downto 0), dataout(63 downto 0), xenable, write); end generate; customout(2custombits-1 downto custombits) <= (others => '0'); customout(custombits-1 downto 0) <= customoutx(custombits-1 downto 0); -- pragma translate_off dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate x : process begin assert false report "syncram64: " & tost(2abits) & "x64" & " (" & tech_table(tech) & ")" severity note; wait; end process; end generate; -- pragma translate_on end generate; nos64 : if has_sram64(tech) = 0 generate x0 : syncram generic map (tech, abits, 32, testen, custombits) port map (clk, address, datain(63 downto 32), dataout(63 downto 32), enable(1), write(1), testin, customclk, customin(2custombits-1 downto custombits), customout(2custombits-1 downto custombits)); x1 : syncram generic map (tech, abits, 32, testen, custombits) port map (clk, address, datain(31 downto 0), dataout(31 downto 0), enable(0), write(0), testin, customclk, customin(custombits-1 downto 0), customout(custombits-1 downto 0)); end generate; end generate; par : if paren = 1 generate dinp <= datain(63+8paren downto 60+8paren) & datain(63 downto 32) & datain(63+4paren downto 60+4paren) & datain(31 downto 0); dataout <= doutp(71 downto 68) & doutp(35 downto 32) & doutp(67 downto 36) & doutp(31-8+8paren downto 0); x0 : syncram generic map (tech, abits, 36, testen, custombits) port map (clk, address, dinp(71 downto 36), doutp(71 downto 36), enable(1), write(1), testin, customclk, customin(2custombits-1 downto custombits), customout(2custombits-1 downto custombits)); x1 : syncram generic map (tech, abits, 36, testen, custombits) port map (clk, address, dinp(35 downto 0), doutp(35 downto 0), enable(0), write(0), testin, customclk, customin(custombits-1 downto 0), customout(custombits-1 downto 0)); end generate; end;
-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 17:34:36 02/22/2016 -- Design Name: -- Module Name: C:/Users/Arthur/Documents/FPGA_temp/serial_out/tb_uart.vhd -- Project Name: serial_out -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: uart -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY tb_uart IS END tb_uart; ARCHITECTURE behavior OF tb_uart IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT uart PORT( clk : in std_logic; tx_data : in std_logic_vector(7 downto 0); tx_en : in std_logic; tx_ready : out std_logic; tx : out std_logic); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal tx_data : std_logic_vector(7 downto 0) := "10101011"; signal tx_en : std_logic := '0'; --Outputs signal tx_ready : std_logic; signal tx : std_logic; -- Clock period definitions constant clk_period : time := 31.25 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: uart PORT MAP ( clk => clk, tx_en => tx_en, tx_data => tx_data, tx_ready => tx_ready, tx => tx ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin wait for 5 us; -- insert stimulus here tx_en <= '1'; wait for 5 us; tx_en <= '0'; wait for 120 us; tx_en <= '1'; wait for 100 us; tx_en <= '0'; wait for 300 us; end process; END;
------------------------------------------------------------------------------- --! @project Serialized hardware implementation of Asconv128128 --! @author Michael Fivez --! @license This project is released under the GNU Public License. --! The license and distribution terms for this file may be --! found in the file LICENSE in this distribution or at --! http://www.gnu.org/licenses/gpl-3.0.txt --! @note This is an hardware implementation made for my graduation thesis --! at the KULeuven, in the COSIC department (year 2015-2016) --! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions', --! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications) ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Ascon_StateUpdate_datapath is port( Clk : in std_logic; -- Clock Reset : in std_logic; -- Reset (synchronous) -- Control signals RoundNr : in std_logic_vector(3 downto 0); -- biggest round is 12 sel1,sel2,sel3,sel4 : in std_logic_vector(1 downto 0); sel0 : in std_logic_vector(2 downto 0); selout : in std_logic; SelSbox : in std_logic_vector(1 downto 0); SelDiff : in std_logic_vector(2 downto 0); Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : in std_logic; SboxEnable : in std_logic; ActivateGen : in std_logic; GenSize : in std_logic_vector(3 downto 0); -- Data signals IV : in std_logic_vector(127 downto 0); Key : in std_logic_vector(127 downto 0); DataIn : in std_logic_vector(127 downto 0); DataOut : out std_logic_vector(127 downto 0) ); end entity Ascon_StateUpdate_datapath; architecture structural of Ascon_StateUpdate_datapath is -- constants constant EXTRAIV : std_logic_vector(63 downto 0) := x"80800c0800000000"; -- used in the initialization constant SEPCONSTANT : std_logic_vector(63 downto 0) := x"0000000000000001"; constant ADCONSTANT : std_logic_vector(63 downto 0) := x"8000000000000000"; -- Register signals signal SboxReg0In,SboxReg1In,SboxReg2In,SboxReg3In,SboxReg4In : std_logic_vector(63 downto 0); signal SboxReg0Out,SboxReg1Out,SboxReg2Out,SboxReg3Out,SboxReg4Out : std_logic_vector(63 downto 0); signal DiffReg0Out,DiffReg1Out,DiffReg2Out,DiffReg3Out,DiffReg4Out : std_logic_vector(63 downto 0); signal RegOutIn,RegOutOut : std_logic_vector(127 downto 0); -- Internal signals on datapath signal Sbox0In,Sbox1In,Sbox2In,Sbox3In,Sbox4In : std_logic_vector(15 downto 0); signal Sbox0Out,Sbox1Out,Sbox2Out,Sbox3Out,Sbox4Out : std_logic_vector(15 downto 0); signal Diff1In, Diff2In, Diff3In, DiffOut : std_logic_vector(63 downto 0); signal XorReg01,XorReg02,XorReg11,XorReg12 : std_logic_vector(63 downto 0); signal XorReg2,XorReg31,XorReg32,XorReg4 : std_logic_vector(63 downto 0); signal OutSig0,OutSig1 : std_logic_vector(127 downto 0); begin -- declare and connect all sub entities sboxregisters: entity work.Sbox_registers port map(Clk ,Sbox0Out, Sbox1Out, Sbox2Out, Sbox3Out, Sbox4Out, Sbox0In, Sbox1In, Sbox2In, Sbox3In, Sbox4In, SboxReg0In, SboxReg1In, SboxReg2In, SboxReg3In, SboxReg4In, SboxReg0Out, SboxReg1Out, SboxReg2Out, SboxReg3Out, SboxReg4Out, SelSbox, SboxEnable, Reg0En, Reg1En, Reg2En, Reg3En, Reg4En); sbox: entity work.Sbox port map(Sbox0In,Sbox1In,Sbox2In,Sbox3In,Sbox4In,RoundNr,Sbox0Out,Sbox1Out,Sbox2Out,Sbox3Out,Sbox4Out,SelSbox); difflayer: entity work.FullDiffusionLayer port map(Diff1In,Diff2In,Diff3In,DiffOut); outpgen: entity work.OutputGenerator port map(SboxReg0Out,SboxReg1Out,DataIn,GenSize,ActivateGen,XorReg01,XorReg11,OutSig0); -- ActivateGen is a bit that indicates decryption or not --------------------------------------------- ------ Combinatorial logic for a round ------ --------------------------------------------- datapath: process(Diff1In, Diff2In, Diff3In, DiffOut, SboxReg0In, SboxReg1In, SboxReg2In, SboxReg3In, SboxReg4In, OutSig0, OutSig1, XorReg01, XorReg02, XorReg11, XorReg12, XorReg2, XorReg31, XorReg32, XorReg4, SboxReg0Out, SboxReg1Out, SboxReg2Out, SboxReg3Out, SboxReg4Out, Key, IV, RegOutIn, RegOutOut, sel0, sel1, sel2, sel3, sel4, selout) is begin -- Set correct inputs in registers if sel0 = "000" then SboxReg0In <= DiffOut; elsif sel0 = "001" then SboxReg0In <= EXTRAIV; elsif sel0 = "010" then SboxReg0In <= XorReg01; elsif sel0 = "011" then SboxReg0In <= XorReg02; else SboxReg0In <= SboxReg0Out xor ADCONSTANT; end if; if sel1 = "00" then SboxReg1In <= DiffOut; elsif sel1 = "01" then SboxReg1In <= Key(127 downto 64); elsif sel1 = "10" then SboxReg1In <= XorReg11; else SboxReg1In <= XorReg12; end if; if sel2 = "00" then SboxReg2In <= DiffOut; elsif sel2 = "01" then SboxReg2In <= Key(63 downto 0); else SboxReg2In <= XorReg2; end if; if sel3 = "00" then SboxReg3In <= DiffOut; elsif sel3 = "01" then SboxReg3In <= IV(127 downto 64); elsif sel3 = "10" then SboxReg3In <= XorReg31; else SboxReg3In <= XorReg32; end if; if sel4 = "00" then SboxReg4In <= DiffOut; elsif sel4 = "01" then SboxReg4In <= IV(63 downto 0); elsif sel4 = "10" then SboxReg4In <= XorReg4; else SboxReg4In <= SboxReg4Out xor SEPCONSTANT; end if; XorReg02 <= SboxReg0Out xor Key(127 downto 64); XorReg12 <= SboxReg1Out xor Key(63 downto 0); XorReg2 <= SboxReg2Out xor Key(127 downto 64); XorReg31 <= SboxReg3Out xor Key(127 downto 64); XorReg32 <= SboxReg3Out xor Key(63 downto 0); XorReg4 <= SboxReg4Out xor Key(63 downto 0); -- Set output OutSig1(127 downto 64) <= XorReg31; OutSig1(63 downto 0) <= XorReg4; if selout = '0' then RegOutIn <= OutSig0; else RegOutIn <= OutSig1; end if; DataOut <= RegOutOut; if SelDiff = "000" then Diff1In(63 downto 64 - 19) <= SboxReg0Out(19 - 1 downto 0); Diff1In(63 - 19 downto 0) <= SboxReg0Out(63 downto 19); Diff2In(63 downto 64 - 28) <= SboxReg0Out(28 - 1 downto 0); Diff2In(63 - 28 downto 0) <= SboxReg0Out(63 downto 28); Diff3In <= SboxReg0Out; elsif SelDiff = "001" then Diff1In(63 downto 64 - 61) <= SboxReg1Out(61 - 1 downto 0); Diff1In(63 - 61 downto 0) <= SboxReg1Out(63 downto 61); Diff2In(63 downto 64 - 39) <= SboxReg1Out(39 - 1 downto 0); Diff2In(63 - 39 downto 0) <= SboxReg1Out(63 downto 39); Diff3In <= SboxReg1Out; elsif SelDiff = "010" then Diff1In(63 downto 64 - 1) <= SboxReg2Out(1 - 1 downto 0); Diff1In(63 - 1 downto 0) <= SboxReg2Out(63 downto 1); Diff2In(63 downto 64 - 6) <= SboxReg2Out(6 - 1 downto 0); Diff2In(63 - 6 downto 0) <= SboxReg2Out(63 downto 6); Diff3In <= SboxReg2Out; elsif SelDiff = "011" then Diff1In(63 downto 64 - 10) <= SboxReg3Out(10 - 1 downto 0); Diff1In(63 - 10 downto 0) <= SboxReg3Out(63 downto 10); Diff2In(63 downto 64 - 17) <= SboxReg3Out(17 - 1 downto 0); Diff2In(63 - 17 downto 0) <= SboxReg3Out(63 downto 17); Diff3In <= SboxReg3Out; else Diff1In(63 downto 64 - 7) <= SboxReg4Out(7 - 1 downto 0); Diff1In(63 - 7 downto 0) <= SboxReg4Out(63 downto 7); Diff2In(63 downto 64 - 41) <= SboxReg4Out(41 - 1 downto 0); Diff2In(63 - 41 downto 0) <= SboxReg4Out(63 downto 41); Diff3In <= SboxReg4Out; end if; end process datapath; --------------------------------------------- ------ The registers in the datapath -------- --------------------------------------------- registerdatapath : process(Clk,Reset) is begin if(Clk = '1' and Clk'event) then if Reset = '1' then -- synchronous reset RegOutOut <= (others => '0'); else if RegOutEn = '1' then RegOutOut <= RegOutIn; end if; end if; end if; end process registerdatapath; end architecture structural;
------------------------------------------------------------------------------- -- Title : UART -- Project : UART ------------------------------------------------------------------------------- -- File : MiniUart.vhd -- Author : Philippe CARTON -- (philippe.carton2@libertysurf.fr) -- Organization: -- Created : 15/12/2001 -- Last update : 8/1/2003 -- Platform : Foundation 3.1i -- Simulators : ModelSim 5.5b -- Synthesizers: Xilinx Synthesis -- Targets : Xilinx Spartan -- Dependency : IEEE std_logic_1164, Rxunit.vhd, Txunit.vhd, utils.vhd ------------------------------------------------------------------------------- -- Description: Uart (Universal Asynchronous Receiver Transmitter) for SoC. -- Wishbone compatable. ------------------------------------------------------------------------------- -- Copyright (c) notice -- This core adheres to the GNU public license -- ------------------------------------------------------------------------------- -- Revisions : -- Revision Number : -- Version : -- Date : -- Modifier : name <email> -- Description : -- ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity MINIUART is generic ( MainClockSpeed : integer; DefaultBaud : integer ); port ( -- Wishbone signals WB_CLK_I : in std_logic; -- clock WB_RST_I : in std_logic; -- Reset input WB_ADR_I : in std_logic_vector(1 downto 0); -- Adress bus WB_DAT_I : in std_logic_vector(7 downto 0); -- DataIn Bus WB_DAT_O : out std_logic_vector(7 downto 0); -- DataOut Bus WB_WE_I : in std_logic; -- Write Enable WB_STB_I : in std_logic; -- Strobe WB_ACK_O : out std_logic; -- Acknowledge -- process signals IntTx_O : out std_logic; -- Transmit interrupt: indicate waiting for Byte IntRx_O : out std_logic; -- Receive interrupt: indicate Byte received BR_Clk_I : in std_logic; -- Clock used for Transmit/Receive TxD_PAD_O : out std_logic; -- Tx RS232 Line RxD_PAD_I : in std_logic; -- Rx RS232 Line ESC_O : out std_logic; BREAK_O : out std_logic); end MINIUART; -- Architecture for UART for synthesis architecture Behaviour of MINIUART is component Counter port ( Clk : in std_logic; -- Clock Reset : in std_logic; -- Reset input CE : in std_logic; -- Chip Enable Count : in std_logic_vector (15 downto 0); -- Count revolution O : out std_logic); -- Output end component; component RxUnit port ( Clk : in std_logic; -- system clock signal Reset : in std_logic; -- Reset input Enable : in std_logic; -- Enable input ReadA : in std_logic; -- Async Read Received Byte RxD : in std_logic; -- RS-232 data input RxAv : out std_logic; -- Byte available DataO : out std_logic_vector(7 downto 0)); -- Byte received end component; component TxUnit port ( Clk : in std_logic; -- Clock signal Reset : in std_logic; -- Reset input Enable : in std_logic; -- Enable input LoadA : in std_logic; -- Asynchronous Load TxD : out std_logic; -- RS-232 data output Busy : out std_logic; -- Tx Busy DataI : in std_logic_vector(7 downto 0)); -- Byte to transmit end component; signal RxData : std_logic_vector(7 downto 0); -- Last Byte received signal RxData1 : std_logic_vector(7 downto 0); signal TxData : std_logic_vector(7 downto 0); -- Last bytes transmitted signal SReg : std_logic_vector(1 downto 0); -- Status register signal CReg : std_logic_vector(7 downto 2); -- Control register signal EnabRx : std_logic; -- Enable RX unit signal EnabTx : std_logic; -- Enable TX unit signal RxAv : std_logic; -- Data Received signal TxBusy : std_logic; -- Transmiter Busy signal ReadA : std_logic; -- Async Read receive buffer signal LoadA : std_logic; -- Async Load transmit buffer signal Sig0 : std_logic; -- gnd signal signal Sig1 : std_logic; -- vcc signal signal Divisor : std_logic_vector(15 downto 0); -- Baud Rate begin sig0 <= '0'; sig1 <= '1'; Uart_Rxrate : Counter -- Baud Rate adjust port map (BR_CLK_I, sig0, sig1, Divisor, EnabRx); Uart_Txrate : Counter -- 4 Divider for Tx port map (BR_CLK_I, Sig0, EnabRx, std_logic_vector(to_unsigned(4, 16)), EnabTx); Uart_TxUnit : TxUnit port map (BR_CLK_I, WB_RST_I, EnabTX, LoadA, TxD_PAD_O, TxBusy, TxData); Uart_RxUnit : RxUnit port map (BR_CLK_I, WB_RST_I, EnabRX, ReadA, RxD_PAD_I, RxAv, RxData); IntTx_O <= not TxBusy; IntRx_O <= RxAv; SReg(0) <= not TxBusy; SReg(1) <= RxAv; -- 16MHz x 1M = 64ms -- ESCctrl: process(WB_CLK_I) -- variable count : unsigned(19 downto 0); -- begin -- if Rising_Edge(WB_CLK_I) then -- if (WB_RST_I = '1') then -- ESC_O <= '1'; -- count := (others => '0'); -- elsif RxData = X"1B" then -- ESC_O <= '0'; -- count := (others => '1'); -- elsif count > 0 then -- count := count - 1; -- else -- ESC_O <= '1'; -- end if; -- end if; -- end process; BREAKctrl: process(WB_CLK_I) variable count : unsigned(7 downto 0); begin if Rising_Edge(WB_CLK_I) then RxData1 <= RxData; if (WB_RST_I = '1') then BREAK_O <= '1'; count := (others => '0'); elsif RxData1 /= X"1A" and RxData = X"1A" and CReg(7) = '1' then BREAK_O <= '0'; count := (others => '1'); elsif count > 0 then count := count - 1; else BREAK_O <= '1'; end if; end if; end process; ESC_O <= '0' when RxData = X"1B" and CReg(6) = '1' else '1'; -- Implements WishBone data exchange. -- Clocked on rising edge. Synchronous Reset RST_I WBctrl : process(WB_CLK_I, WB_RST_I, WB_STB_I, WB_WE_I, WB_ADR_I) variable StatM : std_logic_vector(4 downto 0); begin if Rising_Edge(WB_CLK_I) then if (WB_RST_I = '1') then ReadA <= '0'; LoadA <= '0'; Divisor <= std_logic_vector(to_unsigned(MainClockSpeed / 4 / DefaultBaud, 16)); CReg(7 downto 2) <= "000000"; else if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "00") then -- Write Byte to Tx TxData <= WB_DAT_I; LoadA <= '1'; -- Load signal else LoadA <= '0'; end if; if (WB_STB_I = '1' and WB_WE_I = '0' and WB_ADR_I = "00") then -- Read Byte from Rx ReadA <= '1'; -- Read signal else ReadA <= '0'; end if; if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "01") then -- Write Control CReg <= WB_DAT_I(7 downto 2); end if; if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "10") then -- Write Divisor Low Divisor(7 downto 0) <= WB_DAT_I; end if; if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "11") then -- Write Divisor High Divisor(15 downto 8) <= WB_DAT_I; end if; end if; end if; end process; WB_ACK_O <= WB_STB_I; WB_DAT_O <= RxData when WB_ADR_I = "00" else -- Read Byte from Rx CReg & SReg when WB_ADR_I = "01" else -- Read Control/Status Reg Divisor(7 downto 0) when WB_ADR_I = "10" else -- Read Divisor Low Divisor(15 downto 8) when WB_ADR_I = "11" else -- Read Divisor Low "00000000"; end Behaviour;
-- NEED RESULT: ARCH00246: All formal modes and classes are allowed default classes tested passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00246 -- -- AUTHOR: -- -- D. Hyman -- -- TEST OBJECTIVES: -- -- 2.1.1 (1) -- 2.1.1 (2) -- 2.1.1 (3) -- 2.1.1 (4) -- 2.1.1 (5) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00246) -- ENT00246_Test_Bench(ARCH00246_Test_Bench) -- -- REVISION HISTORY: -- -- 15-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.all ; architecture ARCH00246 of E00000 is signal s : integer := 25; -- the following procedure tests 2.1.1 (2) -- it also tests 2.1.1 (1) by assigning variables to the -- inout and out parameters procedure proc_with_all_formal_modes ( x : in integer; y : inout integer; z : out integer) is begin z := y; y := x; end proc_with_all_formal_modes ; -- the following procedure tests 2.1.1 (3) procedure proc_with_all_formal_classes ( constant c : integer; variable v : out integer; signal s : integer) is begin v := c + s ; end proc_with_all_formal_classes ; -- the following function tests 2.1.1 (4) function func_with_all_formal_modes ( x : in integer) return integer is begin return x + 1; end func_with_all_formal_modes ; -- the following function tests 2.1.1 (5) function func_with_all_formal_classes ( constant c : integer; signal s : integer) return integer is begin return c + s; end func_with_all_formal_classes ; begin P : process constant c : integer := 101; variable v : integer := 150; variable w : integer := 200; variable x : integer := 300; variable y : integer := 400; variable z : integer := 500; begin proc_with_all_formal_modes (x, y, z); proc_with_all_formal_classes (c, v, s) ; test_report ( "ARCH00246" , "All formal modes and classes are allowed " & "default classes tested", (func_with_all_formal_modes (w) = w+1) and (func_with_all_formal_classes (c, s) = c+25) and (v = c+25) and (z = 400) and (y = 300) and (x = 300) ) ; wait ; end process P ; end ARCH00246 ; entity ENT00246_Test_Bench is end ENT00246_Test_Bench ; architecture ARCH00246_Test_Bench of ENT00246_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00246 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00246_Test_Bench ;
-- -- vhdl -- ------------------------------------------------------------------------------- -- Copyright (c) 2012, The CARPE Project, All rights reserved. -- -- See the AUTHORS file for individual contributors. -- -- -- -- Copyright and related rights are licensed under the Solderpad -- -- Hardware License, Version 0.51 (the "License"); you may not use this -- -- file except in compliance with the License. You may obtain a copy of -- -- the License at http://solderpad.org/licenses/SHL-0.51. -- -- -- -- Unless required by applicable law or agreed to in writing, software, -- -- hardware and materials distributed under this License is distributed -- -- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -- -- either express or implied. See the License for the specific language -- -- governing permissions and limitations under the License. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity syncram_2r1w_inferred is generic ( addr_bits : natural := 6; data_bits : natural := 32; write_first : boolean := true ); port ( clk : in std_ulogic; we : in std_ulogic; waddr : in std_ulogic_vector((addr_bits-1) downto 0); wdata : in std_ulogic_vector((data_bits-1) downto 0); re1 : in std_ulogic; raddr1 : in std_ulogic_vector((addr_bits-1) downto 0); rdata1 : out std_ulogic_vector((data_bits-1) downto 0); re2 : in std_ulogic; raddr2 : in std_ulogic_vector((addr_bits-1) downto 0); rdata2 : out std_ulogic_vector((data_bits-1) downto 0) ); end;
------------------------------------------------------------------------------- -- -- MSX1 FPGA project -- -- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com) -- -- All rights reserved -- -- Redistribution and use in source and synthezised forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- -- Redistributions in synthesized form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- Neither the name of the author nor the names of other contributors may -- be used to endorse or promote products derived from this software without -- specific prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- Please report bugs to the author, but before you do so, please -- make sure that this is not a derivative work and that -- you have the latest version of this file. -- ------------------------------------------------------------------------------- -- -- Generic single port RAM. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity spram is generic ( addr_width_g : integer := 8; data_width_g : integer := 8 ); port ( clk_i : in std_logic; we_i : in std_logic; addr_i : in std_logic_vector(addr_width_g-1 downto 0); data_i : in std_logic_vector(data_width_g-1 downto 0); data_o : out std_logic_vector(data_width_g-1 downto 0) ); end spram; library ieee; use ieee.numeric_std.all; architecture rtl of spram is type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); signal ram_q : ram_t -- pragma translate_off := (others => (others => '0')) -- pragma translate_on ; signal read_addr_q : unsigned(addr_width_g-1 downto 0); begin process (clk_i) begin if rising_edge(clk_i) then if we_i = '1' then ram_q(to_integer(unsigned(addr_i))) <= data_i; end if; read_addr_q <= unsigned(addr_i); end if; end process; data_o <= ram_q(to_integer(read_addr_q)); end rtl;
-------------------------------------------------------------------------------- -- -- FIFO Generator Core Demo Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: fg_tb_dverif.vhd -- -- Description: -- Used for FIFO read interface stimulus generation and data checking -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_misc.all; LIBRARY work; USE work.fg_tb_pkg.ALL; ENTITY fg_tb_dverif IS GENERIC( C_DIN_WIDTH : INTEGER := 0; C_DOUT_WIDTH : INTEGER := 0; C_USE_EMBEDDED_REG : INTEGER := 0; C_CH_TYPE : INTEGER := 0; TB_SEED : INTEGER := 2 ); PORT( RESET : IN STD_LOGIC; RD_CLK : IN STD_LOGIC; PRC_RD_EN : IN STD_LOGIC; EMPTY : IN STD_LOGIC; DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); RD_EN : OUT STD_LOGIC; DOUT_CHK : OUT STD_LOGIC ); END ENTITY; ARCHITECTURE fg_dv_arch OF fg_tb_dverif IS CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0); CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8); CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH); SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL data_chk : STD_LOGIC := '1'; SIGNAL rand_num : STD_LOGIC_VECTOR(8LOOP_COUNT-1 downto 0); SIGNAL rd_en_i : STD_LOGIC := '0'; SIGNAL pr_r_en : STD_LOGIC := '0'; SIGNAL rd_en_d1 : STD_LOGIC := '1'; SIGNAL rd_d_sel_d1 : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0):= (OTHERS => '0'); BEGIN DOUT_CHK <= data_chk; RD_EN <= rd_en_i; rd_en_i <= PRC_RD_EN; rd_en_d1 <= '1'; data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE ------------------------------------------------------- -- Expected data generation and checking for data_fifo ------------------------------------------------------- PROCESS (RD_CLK,RESET) BEGIN IF (RESET = '1') THEN rd_d_sel_d1 <= (OTHERS => '0'); ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF (rd_en_i = '1' AND EMPTY = '0' AND rd_en_d1 = '1') THEN rd_d_sel_d1 <= rd_d_sel_d1+"1"; END IF; END IF; END PROCESS; pr_r_en <= (AND_REDUCE(rd_d_sel_d1)) AND rd_en_i AND NOT EMPTY; expected_dout <= rand_num(C_DIN_WIDTH-C_DOUT_WIDTHconv_integer(rd_d_sel_d1)-1 DOWNTO C_DIN_WIDTH-C_DOUT_WIDTH(conv_integer(rd_d_sel_d1)+1)); gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE rd_gen_inst2:fg_tb_rng GENERIC MAP( WIDTH => 8, SEED => TB_SEED+N ) PORT MAP( CLK => RD_CLK, RESET => RESET, RANDOM_NUM => rand_num(8(N+1)-1 downto 8*N), ENABLE => pr_r_en ); END GENERATE; PROCESS (RD_CLK,RESET) BEGIN IF(RESET = '1') THEN data_chk <= '0'; ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF(EMPTY = '0') THEN IF(DATA_OUT = expected_dout) THEN data_chk <= '0'; ELSE data_chk <= '1'; END IF; END IF; END IF; END PROCESS; END GENERATE data_fifo_chk; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- FIFO Generator Core Demo Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: fg_tb_dverif.vhd -- -- Description: -- Used for FIFO read interface stimulus generation and data checking -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_misc.all; LIBRARY work; USE work.fg_tb_pkg.ALL; ENTITY fg_tb_dverif IS GENERIC( C_DIN_WIDTH : INTEGER := 0; C_DOUT_WIDTH : INTEGER := 0; C_USE_EMBEDDED_REG : INTEGER := 0; C_CH_TYPE : INTEGER := 0; TB_SEED : INTEGER := 2 ); PORT( RESET : IN STD_LOGIC; RD_CLK : IN STD_LOGIC; PRC_RD_EN : IN STD_LOGIC; EMPTY : IN STD_LOGIC; DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); RD_EN : OUT STD_LOGIC; DOUT_CHK : OUT STD_LOGIC ); END ENTITY; ARCHITECTURE fg_dv_arch OF fg_tb_dverif IS CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0); CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8); CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH); SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL data_chk : STD_LOGIC := '1'; SIGNAL rand_num : STD_LOGIC_VECTOR(8LOOP_COUNT-1 downto 0); SIGNAL rd_en_i : STD_LOGIC := '0'; SIGNAL pr_r_en : STD_LOGIC := '0'; SIGNAL rd_en_d1 : STD_LOGIC := '1'; SIGNAL rd_d_sel_d1 : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0):= (OTHERS => '0'); BEGIN DOUT_CHK <= data_chk; RD_EN <= rd_en_i; rd_en_i <= PRC_RD_EN; rd_en_d1 <= '1'; data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE ------------------------------------------------------- -- Expected data generation and checking for data_fifo ------------------------------------------------------- PROCESS (RD_CLK,RESET) BEGIN IF (RESET = '1') THEN rd_d_sel_d1 <= (OTHERS => '0'); ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF (rd_en_i = '1' AND EMPTY = '0' AND rd_en_d1 = '1') THEN rd_d_sel_d1 <= rd_d_sel_d1+"1"; END IF; END IF; END PROCESS; pr_r_en <= (AND_REDUCE(rd_d_sel_d1)) AND rd_en_i AND NOT EMPTY; expected_dout <= rand_num(C_DIN_WIDTH-C_DOUT_WIDTHconv_integer(rd_d_sel_d1)-1 DOWNTO C_DIN_WIDTH-C_DOUT_WIDTH(conv_integer(rd_d_sel_d1)+1)); gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE rd_gen_inst2:fg_tb_rng GENERIC MAP( WIDTH => 8, SEED => TB_SEED+N ) PORT MAP( CLK => RD_CLK, RESET => RESET, RANDOM_NUM => rand_num(8(N+1)-1 downto 8*N), ENABLE => pr_r_en ); END GENERATE; PROCESS (RD_CLK,RESET) BEGIN IF(RESET = '1') THEN data_chk <= '0'; ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF(EMPTY = '0') THEN IF(DATA_OUT = expected_dout) THEN data_chk <= '0'; ELSE data_chk <= '1'; END IF; END IF; END IF; END PROCESS; END GENERATE data_fifo_chk; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- FIFO Generator Core Demo Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: fg_tb_dverif.vhd -- -- Description: -- Used for FIFO read interface stimulus generation and data checking -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_misc.all; LIBRARY work; USE work.fg_tb_pkg.ALL; ENTITY fg_tb_dverif IS GENERIC( C_DIN_WIDTH : INTEGER := 0; C_DOUT_WIDTH : INTEGER := 0; C_USE_EMBEDDED_REG : INTEGER := 0; C_CH_TYPE : INTEGER := 0; TB_SEED : INTEGER := 2 ); PORT( RESET : IN STD_LOGIC; RD_CLK : IN STD_LOGIC; PRC_RD_EN : IN STD_LOGIC; EMPTY : IN STD_LOGIC; DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); RD_EN : OUT STD_LOGIC; DOUT_CHK : OUT STD_LOGIC ); END ENTITY; ARCHITECTURE fg_dv_arch OF fg_tb_dverif IS CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0); CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8); CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH); SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL data_chk : STD_LOGIC := '1'; SIGNAL rand_num : STD_LOGIC_VECTOR(8LOOP_COUNT-1 downto 0); SIGNAL rd_en_i : STD_LOGIC := '0'; SIGNAL pr_r_en : STD_LOGIC := '0'; SIGNAL rd_en_d1 : STD_LOGIC := '1'; SIGNAL rd_d_sel_d1 : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0):= (OTHERS => '0'); BEGIN DOUT_CHK <= data_chk; RD_EN <= rd_en_i; rd_en_i <= PRC_RD_EN; rd_en_d1 <= '1'; data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE ------------------------------------------------------- -- Expected data generation and checking for data_fifo ------------------------------------------------------- PROCESS (RD_CLK,RESET) BEGIN IF (RESET = '1') THEN rd_d_sel_d1 <= (OTHERS => '0'); ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF (rd_en_i = '1' AND EMPTY = '0' AND rd_en_d1 = '1') THEN rd_d_sel_d1 <= rd_d_sel_d1+"1"; END IF; END IF; END PROCESS; pr_r_en <= (AND_REDUCE(rd_d_sel_d1)) AND rd_en_i AND NOT EMPTY; expected_dout <= rand_num(C_DIN_WIDTH-C_DOUT_WIDTHconv_integer(rd_d_sel_d1)-1 DOWNTO C_DIN_WIDTH-C_DOUT_WIDTH(conv_integer(rd_d_sel_d1)+1)); gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE rd_gen_inst2:fg_tb_rng GENERIC MAP( WIDTH => 8, SEED => TB_SEED+N ) PORT MAP( CLK => RD_CLK, RESET => RESET, RANDOM_NUM => rand_num(8(N+1)-1 downto 8*N), ENABLE => pr_r_en ); END GENERATE; PROCESS (RD_CLK,RESET) BEGIN IF(RESET = '1') THEN data_chk <= '0'; ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF(EMPTY = '0') THEN IF(DATA_OUT = expected_dout) THEN data_chk <= '0'; ELSE data_chk <= '1'; END IF; END IF; END IF; END PROCESS; END GENERATE data_fifo_chk; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- FIFO Generator Core Demo Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: fg_tb_dverif.vhd -- -- Description: -- Used for FIFO read interface stimulus generation and data checking -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_misc.all; LIBRARY work; USE work.fg_tb_pkg.ALL; ENTITY fg_tb_dverif IS GENERIC( C_DIN_WIDTH : INTEGER := 0; C_DOUT_WIDTH : INTEGER := 0; C_USE_EMBEDDED_REG : INTEGER := 0; C_CH_TYPE : INTEGER := 0; TB_SEED : INTEGER := 2 ); PORT( RESET : IN STD_LOGIC; RD_CLK : IN STD_LOGIC; PRC_RD_EN : IN STD_LOGIC; EMPTY : IN STD_LOGIC; DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); RD_EN : OUT STD_LOGIC; DOUT_CHK : OUT STD_LOGIC ); END ENTITY; ARCHITECTURE fg_dv_arch OF fg_tb_dverif IS CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0); CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8); CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH); SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL data_chk : STD_LOGIC := '1'; SIGNAL rand_num : STD_LOGIC_VECTOR(8LOOP_COUNT-1 downto 0); SIGNAL rd_en_i : STD_LOGIC := '0'; SIGNAL pr_r_en : STD_LOGIC := '0'; SIGNAL rd_en_d1 : STD_LOGIC := '1'; SIGNAL rd_d_sel_d1 : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0):= (OTHERS => '0'); BEGIN DOUT_CHK <= data_chk; RD_EN <= rd_en_i; rd_en_i <= PRC_RD_EN; rd_en_d1 <= '1'; data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE ------------------------------------------------------- -- Expected data generation and checking for data_fifo ------------------------------------------------------- PROCESS (RD_CLK,RESET) BEGIN IF (RESET = '1') THEN rd_d_sel_d1 <= (OTHERS => '0'); ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF (rd_en_i = '1' AND EMPTY = '0' AND rd_en_d1 = '1') THEN rd_d_sel_d1 <= rd_d_sel_d1+"1"; END IF; END IF; END PROCESS; pr_r_en <= (AND_REDUCE(rd_d_sel_d1)) AND rd_en_i AND NOT EMPTY; expected_dout <= rand_num(C_DIN_WIDTH-C_DOUT_WIDTHconv_integer(rd_d_sel_d1)-1 DOWNTO C_DIN_WIDTH-C_DOUT_WIDTH(conv_integer(rd_d_sel_d1)+1)); gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE rd_gen_inst2:fg_tb_rng GENERIC MAP( WIDTH => 8, SEED => TB_SEED+N ) PORT MAP( CLK => RD_CLK, RESET => RESET, RANDOM_NUM => rand_num(8(N+1)-1 downto 8*N), ENABLE => pr_r_en ); END GENERATE; PROCESS (RD_CLK,RESET) BEGIN IF(RESET = '1') THEN data_chk <= '0'; ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF(EMPTY = '0') THEN IF(DATA_OUT = expected_dout) THEN data_chk <= '0'; ELSE data_chk <= '1'; END IF; END IF; END IF; END PROCESS; END GENERATE data_fifo_chk; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- FIFO Generator Core Demo Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: fg_tb_dverif.vhd -- -- Description: -- Used for FIFO read interface stimulus generation and data checking -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_misc.all; LIBRARY work; USE work.fg_tb_pkg.ALL; ENTITY fg_tb_dverif IS GENERIC( C_DIN_WIDTH : INTEGER := 0; C_DOUT_WIDTH : INTEGER := 0; C_USE_EMBEDDED_REG : INTEGER := 0; C_CH_TYPE : INTEGER := 0; TB_SEED : INTEGER := 2 ); PORT( RESET : IN STD_LOGIC; RD_CLK : IN STD_LOGIC; PRC_RD_EN : IN STD_LOGIC; EMPTY : IN STD_LOGIC; DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); RD_EN : OUT STD_LOGIC; DOUT_CHK : OUT STD_LOGIC ); END ENTITY; ARCHITECTURE fg_dv_arch OF fg_tb_dverif IS CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0); CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8); CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH); SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL data_chk : STD_LOGIC := '1'; SIGNAL rand_num : STD_LOGIC_VECTOR(8LOOP_COUNT-1 downto 0); SIGNAL rd_en_i : STD_LOGIC := '0'; SIGNAL pr_r_en : STD_LOGIC := '0'; SIGNAL rd_en_d1 : STD_LOGIC := '1'; SIGNAL rd_d_sel_d1 : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0):= (OTHERS => '0'); BEGIN DOUT_CHK <= data_chk; RD_EN <= rd_en_i; rd_en_i <= PRC_RD_EN; rd_en_d1 <= '1'; data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE ------------------------------------------------------- -- Expected data generation and checking for data_fifo ------------------------------------------------------- PROCESS (RD_CLK,RESET) BEGIN IF (RESET = '1') THEN rd_d_sel_d1 <= (OTHERS => '0'); ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF (rd_en_i = '1' AND EMPTY = '0' AND rd_en_d1 = '1') THEN rd_d_sel_d1 <= rd_d_sel_d1+"1"; END IF; END IF; END PROCESS; pr_r_en <= (AND_REDUCE(rd_d_sel_d1)) AND rd_en_i AND NOT EMPTY; expected_dout <= rand_num(C_DIN_WIDTH-C_DOUT_WIDTHconv_integer(rd_d_sel_d1)-1 DOWNTO C_DIN_WIDTH-C_DOUT_WIDTH(conv_integer(rd_d_sel_d1)+1)); gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE rd_gen_inst2:fg_tb_rng GENERIC MAP( WIDTH => 8, SEED => TB_SEED+N ) PORT MAP( CLK => RD_CLK, RESET => RESET, RANDOM_NUM => rand_num(8(N+1)-1 downto 8*N), ENABLE => pr_r_en ); END GENERATE; PROCESS (RD_CLK,RESET) BEGIN IF(RESET = '1') THEN data_chk <= '0'; ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF(EMPTY = '0') THEN IF(DATA_OUT = expected_dout) THEN data_chk <= '0'; ELSE data_chk <= '1'; END IF; END IF; END IF; END PROCESS; END GENERATE data_fifo_chk; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- FIFO Generator Core Demo Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: fg_tb_dverif.vhd -- -- Description: -- Used for FIFO read interface stimulus generation and data checking -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_misc.all; LIBRARY work; USE work.fg_tb_pkg.ALL; ENTITY fg_tb_dverif IS GENERIC( C_DIN_WIDTH : INTEGER := 0; C_DOUT_WIDTH : INTEGER := 0; C_USE_EMBEDDED_REG : INTEGER := 0; C_CH_TYPE : INTEGER := 0; TB_SEED : INTEGER := 2 ); PORT( RESET : IN STD_LOGIC; RD_CLK : IN STD_LOGIC; PRC_RD_EN : IN STD_LOGIC; EMPTY : IN STD_LOGIC; DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); RD_EN : OUT STD_LOGIC; DOUT_CHK : OUT STD_LOGIC ); END ENTITY; ARCHITECTURE fg_dv_arch OF fg_tb_dverif IS CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0); CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8); CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH); SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL data_chk : STD_LOGIC := '1'; SIGNAL rand_num : STD_LOGIC_VECTOR(8LOOP_COUNT-1 downto 0); SIGNAL rd_en_i : STD_LOGIC := '0'; SIGNAL pr_r_en : STD_LOGIC := '0'; SIGNAL rd_en_d1 : STD_LOGIC := '1'; SIGNAL rd_d_sel_d1 : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0):= (OTHERS => '0'); BEGIN DOUT_CHK <= data_chk; RD_EN <= rd_en_i; rd_en_i <= PRC_RD_EN; rd_en_d1 <= '1'; data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE ------------------------------------------------------- -- Expected data generation and checking for data_fifo ------------------------------------------------------- PROCESS (RD_CLK,RESET) BEGIN IF (RESET = '1') THEN rd_d_sel_d1 <= (OTHERS => '0'); ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF (rd_en_i = '1' AND EMPTY = '0' AND rd_en_d1 = '1') THEN rd_d_sel_d1 <= rd_d_sel_d1+"1"; END IF; END IF; END PROCESS; pr_r_en <= (AND_REDUCE(rd_d_sel_d1)) AND rd_en_i AND NOT EMPTY; expected_dout <= rand_num(C_DIN_WIDTH-C_DOUT_WIDTHconv_integer(rd_d_sel_d1)-1 DOWNTO C_DIN_WIDTH-C_DOUT_WIDTH(conv_integer(rd_d_sel_d1)+1)); gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE rd_gen_inst2:fg_tb_rng GENERIC MAP( WIDTH => 8, SEED => TB_SEED+N ) PORT MAP( CLK => RD_CLK, RESET => RESET, RANDOM_NUM => rand_num(8(N+1)-1 downto 8*N), ENABLE => pr_r_en ); END GENERATE; PROCESS (RD_CLK,RESET) BEGIN IF(RESET = '1') THEN data_chk <= '0'; ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF(EMPTY = '0') THEN IF(DATA_OUT = expected_dout) THEN data_chk <= '0'; ELSE data_chk <= '1'; END IF; END IF; END IF; END PROCESS; END GENERATE data_fifo_chk; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- FIFO Generator Core Demo Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: fg_tb_dverif.vhd -- -- Description: -- Used for FIFO read interface stimulus generation and data checking -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_misc.all; LIBRARY work; USE work.fg_tb_pkg.ALL; ENTITY fg_tb_dverif IS GENERIC( C_DIN_WIDTH : INTEGER := 0; C_DOUT_WIDTH : INTEGER := 0; C_USE_EMBEDDED_REG : INTEGER := 0; C_CH_TYPE : INTEGER := 0; TB_SEED : INTEGER := 2 ); PORT( RESET : IN STD_LOGIC; RD_CLK : IN STD_LOGIC; PRC_RD_EN : IN STD_LOGIC; EMPTY : IN STD_LOGIC; DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); RD_EN : OUT STD_LOGIC; DOUT_CHK : OUT STD_LOGIC ); END ENTITY; ARCHITECTURE fg_dv_arch OF fg_tb_dverif IS CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0); CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8); CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH); SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL data_chk : STD_LOGIC := '1'; SIGNAL rand_num : STD_LOGIC_VECTOR(8LOOP_COUNT-1 downto 0); SIGNAL rd_en_i : STD_LOGIC := '0'; SIGNAL pr_r_en : STD_LOGIC := '0'; SIGNAL rd_en_d1 : STD_LOGIC := '1'; SIGNAL rd_d_sel_d1 : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0):= (OTHERS => '0'); BEGIN DOUT_CHK <= data_chk; RD_EN <= rd_en_i; rd_en_i <= PRC_RD_EN; rd_en_d1 <= '1'; data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE ------------------------------------------------------- -- Expected data generation and checking for data_fifo ------------------------------------------------------- PROCESS (RD_CLK,RESET) BEGIN IF (RESET = '1') THEN rd_d_sel_d1 <= (OTHERS => '0'); ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF (rd_en_i = '1' AND EMPTY = '0' AND rd_en_d1 = '1') THEN rd_d_sel_d1 <= rd_d_sel_d1+"1"; END IF; END IF; END PROCESS; pr_r_en <= (AND_REDUCE(rd_d_sel_d1)) AND rd_en_i AND NOT EMPTY; expected_dout <= rand_num(C_DIN_WIDTH-C_DOUT_WIDTHconv_integer(rd_d_sel_d1)-1 DOWNTO C_DIN_WIDTH-C_DOUT_WIDTH(conv_integer(rd_d_sel_d1)+1)); gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE rd_gen_inst2:fg_tb_rng GENERIC MAP( WIDTH => 8, SEED => TB_SEED+N ) PORT MAP( CLK => RD_CLK, RESET => RESET, RANDOM_NUM => rand_num(8(N+1)-1 downto 8*N), ENABLE => pr_r_en ); END GENERATE; PROCESS (RD_CLK,RESET) BEGIN IF(RESET = '1') THEN data_chk <= '0'; ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF(EMPTY = '0') THEN IF(DATA_OUT = expected_dout) THEN data_chk <= '0'; ELSE data_chk <= '1'; END IF; END IF; END IF; END PROCESS; END GENERATE data_fifo_chk; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- FIFO Generator Core Demo Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: fg_tb_dverif.vhd -- -- Description: -- Used for FIFO read interface stimulus generation and data checking -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_misc.all; LIBRARY work; USE work.fg_tb_pkg.ALL; ENTITY fg_tb_dverif IS GENERIC( C_DIN_WIDTH : INTEGER := 0; C_DOUT_WIDTH : INTEGER := 0; C_USE_EMBEDDED_REG : INTEGER := 0; C_CH_TYPE : INTEGER := 0; TB_SEED : INTEGER := 2 ); PORT( RESET : IN STD_LOGIC; RD_CLK : IN STD_LOGIC; PRC_RD_EN : IN STD_LOGIC; EMPTY : IN STD_LOGIC; DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); RD_EN : OUT STD_LOGIC; DOUT_CHK : OUT STD_LOGIC ); END ENTITY; ARCHITECTURE fg_dv_arch OF fg_tb_dverif IS CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0); CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8); CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH); SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL data_chk : STD_LOGIC := '1'; SIGNAL rand_num : STD_LOGIC_VECTOR(8LOOP_COUNT-1 downto 0); SIGNAL rd_en_i : STD_LOGIC := '0'; SIGNAL pr_r_en : STD_LOGIC := '0'; SIGNAL rd_en_d1 : STD_LOGIC := '1'; SIGNAL rd_d_sel_d1 : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0):= (OTHERS => '0'); BEGIN DOUT_CHK <= data_chk; RD_EN <= rd_en_i; rd_en_i <= PRC_RD_EN; rd_en_d1 <= '1'; data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE ------------------------------------------------------- -- Expected data generation and checking for data_fifo ------------------------------------------------------- PROCESS (RD_CLK,RESET) BEGIN IF (RESET = '1') THEN rd_d_sel_d1 <= (OTHERS => '0'); ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF (rd_en_i = '1' AND EMPTY = '0' AND rd_en_d1 = '1') THEN rd_d_sel_d1 <= rd_d_sel_d1+"1"; END IF; END IF; END PROCESS; pr_r_en <= (AND_REDUCE(rd_d_sel_d1)) AND rd_en_i AND NOT EMPTY; expected_dout <= rand_num(C_DIN_WIDTH-C_DOUT_WIDTHconv_integer(rd_d_sel_d1)-1 DOWNTO C_DIN_WIDTH-C_DOUT_WIDTH(conv_integer(rd_d_sel_d1)+1)); gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE rd_gen_inst2:fg_tb_rng GENERIC MAP( WIDTH => 8, SEED => TB_SEED+N ) PORT MAP( CLK => RD_CLK, RESET => RESET, RANDOM_NUM => rand_num(8(N+1)-1 downto 8*N), ENABLE => pr_r_en ); END GENERATE; PROCESS (RD_CLK,RESET) BEGIN IF(RESET = '1') THEN data_chk <= '0'; ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF(EMPTY = '0') THEN IF(DATA_OUT = expected_dout) THEN data_chk <= '0'; ELSE data_chk <= '1'; END IF; END IF; END IF; END PROCESS; END GENERATE data_fifo_chk; END ARCHITECTURE;
------------------------------------------------------------------------------- -- axi_datamover_s2mm_full_wrap.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_s2mm_full_wrap.vhd -- -- Description: -- This file implements the DataMover S2MM FULL Wrapper. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all ; -- axi_datamover Library Modules library axi_datamover_v5_1_10; use axi_datamover_v5_1_10.axi_datamover_reset ; use axi_datamover_v5_1_10.axi_datamover_cmd_status ; use axi_datamover_v5_1_10.axi_datamover_pcc ; use axi_datamover_v5_1_10.axi_datamover_ibttcc ; use axi_datamover_v5_1_10.axi_datamover_indet_btt ; use axi_datamover_v5_1_10.axi_datamover_s2mm_realign ; use axi_datamover_v5_1_10.axi_datamover_addr_cntl ; use axi_datamover_v5_1_10.axi_datamover_wrdata_cntl ; use axi_datamover_v5_1_10.axi_datamover_wr_status_cntl; Use axi_datamover_v5_1_10.axi_datamover_skid2mm_buf ; Use axi_datamover_v5_1_10.axi_datamover_skid_buf ; Use axi_datamover_v5_1_10.axi_datamover_wr_sf ; ------------------------------------------------------------------------------- entity axi_datamover_s2mm_full_wrap is generic ( C_INCLUDE_S2MM : Integer range 0 to 2 := 1; -- Specifies the type of S2MM function to include -- 0 = Omit S2MM functionality -- 1 = Full S2MM Functionality -- 2 = Lite S2MM functionality C_S2MM_AWID : Integer range 0 to 255 := 9; -- Specifies the constant value to output on -- the ARID output port C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the S2MM ID port C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the S2MM Master Stream Data -- Channel data bus C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit S2MM Status FIFO -- 1 = Include S2MM Status FIFO C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the S2MM Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0; -- Specifies if DRE is to be included in the S2MM function -- 0 = Omit DRE -- 1 = Include DRE C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the S2MM function C_S2MM_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the S2MM Command Interface C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0; -- Specifies if support for indeterminate packet lengths -- are to be received on the input Stream interface -- 0 = Omit support (User MUST transfer the exact number of -- bytes on the Stream interface as specified in the BTT -- field of the Corresponding DataMover Command) -- 1 = Include support for indeterminate packet lengths -- This causes FIFOs to be added and "Store and Forward" -- behavior of the S2MM function C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3; -- This parameter specifies the depth of the S2MM internal -- address pipeline queues in the Write Address Controller -- and the Write Data Controller. Increasing this value will -- allow more Write Addresses to be issued to the AXI4 Write -- Address Channel before transmission of the associated -- write data on the Write Data Channel. C_TAG_WIDTH : Integer range 1 to 8 := 4 ; -- Width of the TAG field C_INCLUDE_S2MM_GP_SF : Integer range 0 to 1 := 1 ; -- This parameter specifies the inclusion/omission of the -- S2MM (Write) General Purpose Store and Forward function -- 0 = Omit GP Store and Forward -- 1 = Include GP Store and Forward C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1; C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1; C_ENABLE_SKID_BUF : string := "11111"; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- S2MM Primary Clock and Reset inputs ---------------------------- s2mm_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- ------------------------------------------------------------------- -- S2MM Primary Reset input --------------------------------------- s2mm_aresetn : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------------- -- S2MM Halt request input control -------------------------------- s2mm_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- S2MM Halt Complete status flag -- s2mm_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------------------- -- S2MM Error discrete output ------------------------------------- s2mm_err : Out std_logic; -- -- Composite Error indication -- ------------------------------------------------------------------- -- Optional Command and Status Clock and Reset ------------------- -- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 -- -- s2mm_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- s2mm_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- ------------------------------------------------------------------ -- User Command Interface Ports (AXI Stream) ----------------------------------------------------- s2mm_cmd_wvalid : in std_logic; -- s2mm_cmd_wready : out std_logic; -- s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); -- -------------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) -------------------------------------------------------- s2mm_sts_wvalid : out std_logic; -- s2mm_sts_wready : in std_logic; -- s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT24)+8)-1 downto 0); -- s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT24)+8)/8)-1 downto 0); -- s2mm_sts_wlast : out std_logic; -- ---------------------------------------------------------------------------------------------------- -- Address posting controls --------------------------------------- s2mm_allow_addr_req : in std_logic; -- s2mm_addr_req_posted : out std_logic; -- s2mm_wr_xfer_cmplt : out std_logic; -- s2mm_ld_nxt_len : out std_logic; -- s2mm_wr_len : out std_logic_vector(7 downto 0); -- ------------------------------------------------------------------- -- S2MM AXI Address Channel I/O -------------------------------------- s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- s2mm_awlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- s2mm_awsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- s2mm_awburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- s2mm_awprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- s2mm_awcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel PROT output -- s2mm_awuser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel PROT output -- -- s2mm_awvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- s2mm_awready : in std_logic; -- -- AXI Address Channel READY input -- ----------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ----------- -- s2mm__awlock : out std_logic_vector(2 downto 0); -- -- s2mm__awcache : out std_logic_vector(4 downto 0); -- -- s2mm__awqos : out std_logic_vector(3 downto 0); -- -- s2mm__awregion : out std_logic_vector(3 downto 0); -- ----------------------------------------------------------------------- -- S2MM AXI MMap Write Data Channel I/O --------------------------------------------- s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); -- s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); -- s2mm_wlast : Out std_logic; -- s2mm_wvalid : Out std_logic; -- s2mm_wready : In std_logic; -- -------------------------------------------------------------------------------------- -- S2MM AXI MMap Write response Channel I/O ----------------------------------------- s2mm_bresp : In std_logic_vector(1 downto 0); -- s2mm_bvalid : In std_logic; -- s2mm_bready : Out std_logic; -- -------------------------------------------------------------------------------------- -- S2MM AXI Master Stream Channel I/O ----------------------------------------------- s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); -- s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); -- s2mm_strm_wlast : In std_logic; -- s2mm_strm_wvalid : In std_logic; -- s2mm_strm_wready : Out std_logic; -- -------------------------------------------------------------------------------------- -- Testing Support I/O ------------------------------------------ s2mm_dbg_sel : in std_logic_vector( 3 downto 0); -- s2mm_dbg_data : out std_logic_vector(31 downto 0) -- ----------------------------------------------------------------- ); end entity axi_datamover_s2mm_full_wrap; architecture implementation of axi_datamover_s2mm_full_wrap is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations ---------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: func_calc_wdemux_sel_bits -- -- Function Description: -- This function calculates the number of address bits needed for -- the Write Strobe demux select control. -- ------------------------------------------------------------------- function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is Variable num_addr_bits_needed : Integer range 1 to 7 := 1; begin case mmap_dwidth_value is when 32 => num_addr_bits_needed := 2; when 64 => num_addr_bits_needed := 3; when 128 => num_addr_bits_needed := 4; when 256 => num_addr_bits_needed := 5; when 512 => num_addr_bits_needed := 6; when others => -- 1024 bits num_addr_bits_needed := 7; end case; Return (num_addr_bits_needed); end function func_calc_wdemux_sel_bits; ------------------------------------------------------------------- -- Function -- -- Function Name: func_include_dre -- -- Function Description: -- This function desides if conditions are right for allowing DRE -- inclusion. -- ------------------------------------------------------------------- function func_include_dre (need_dre : integer; needed_data_width : integer) return integer is Variable include_dre : Integer := 0; begin if (need_dre = 1 and needed_data_width < 128 and needed_data_width > 8) Then include_dre := 1; Else include_dre := 0; End if; Return (include_dre); end function func_include_dre; ------------------------------------------------------------------- -- Function -- -- Function Name: func_get_align_width -- -- Function Description: -- This function calculates the needed DRE alignment port width\ -- based upon the inclusion of DRE and the needed bit width of the -- DRE. -- ------------------------------------------------------------------- function func_get_align_width (dre_included : integer; dre_data_width : integer) return integer is Variable align_port_width : Integer := 1; begin if (dre_included = 1) then If (dre_data_width = 64) Then align_port_width := 3; Elsif (dre_data_width = 32) Then align_port_width := 2; else -- 16 bit data width align_port_width := 1; End if; else align_port_width := 1; end if; Return (align_port_width); end function func_get_align_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_set_status_width -- -- Function Description: -- This function sets the width of the Status pipe depending on the -- Store and Forward inclusion or ommision. -- ------------------------------------------------------------------- function funct_set_status_width (store_forward_enabled : integer) return integer is Variable temp_status_bit_width : Integer := 8; begin If (store_forward_enabled = 1) Then temp_status_bit_width := 32; Else temp_status_bit_width := 8; End if; Return (temp_status_bit_width); end function funct_set_status_width; ------------------------------------------------------------------- -- Function -- -- Function Name: get_bits_needed -- -- Function Description: -- -- ------------------------------------------------------------------- function get_bits_needed (max_bytes : integer) return integer is Variable fvar_temp_bit_width : Integer := 1; begin if (max_bytes <= 1) then fvar_temp_bit_width := 1; elsif (max_bytes <= 3) then fvar_temp_bit_width := 2; elsif (max_bytes <= 7) then fvar_temp_bit_width := 3; elsif (max_bytes <= 15) then fvar_temp_bit_width := 4; elsif (max_bytes <= 31) then fvar_temp_bit_width := 5; elsif (max_bytes <= 63) then fvar_temp_bit_width := 6; elsif (max_bytes <= 127) then fvar_temp_bit_width := 7; elsif (max_bytes <= 255) then fvar_temp_bit_width := 8; elsif (max_bytes <= 511) then fvar_temp_bit_width := 9; elsif (max_bytes <= 1023) then fvar_temp_bit_width := 10; elsif (max_bytes <= 2047) then fvar_temp_bit_width := 11; elsif (max_bytes <= 4095) then fvar_temp_bit_width := 12; elsif (max_bytes <= 8191) then fvar_temp_bit_width := 13; else -- 8k - 16K fvar_temp_bit_width := 14; end if; Return (fvar_temp_bit_width); end function get_bits_needed; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_rnd2pwr_of_2 -- -- Function Description: -- Rounds the input value up to the nearest power of 2 between -- 128 and 8192. -- ------------------------------------------------------------------- function funct_rnd2pwr_of_2 (input_value : integer) return integer is Variable temp_pwr2 : Integer := 128; begin if (input_value <= 128) then temp_pwr2 := 128; elsif (input_value <= 256) then temp_pwr2 := 256; elsif (input_value <= 512) then temp_pwr2 := 512; elsif (input_value <= 1024) then temp_pwr2 := 1024; elsif (input_value <= 2048) then temp_pwr2 := 2048; elsif (input_value <= 4096) then temp_pwr2 := 4096; else temp_pwr2 := 8192; end if; Return (temp_pwr2); end function funct_rnd2pwr_of_2; ------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_need_realigner -- -- Function Description: -- Determines if the Realigner module needs to be included. -- ------------------------------------------------------------------- function funct_need_realigner (indet_btt_enabled : integer; dre_included : integer; gp_sf_included : integer) return integer is Variable temp_val : Integer := 0; begin If ((indet_btt_enabled = 1) or (dre_included = 1) or (gp_sf_included = 1)) Then temp_val := 1; else temp_val := 0; End if; Return (temp_val); end function funct_need_realigner; ------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_sf_offset_width -- -- Function Description: -- This function calculates the address offset width needed by -- the GP Store and Forward module with data packing. -- ------------------------------------------------------------------- function funct_get_sf_offset_width (mmap_dwidth : integer; stream_dwidth : integer) return integer is Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth; Variable fvar_temp_offset_width : Integer := 1; begin case FCONST_WIDTH_RATIO is when 1 => fvar_temp_offset_width := 1; when 2 => fvar_temp_offset_width := 1; when 4 => fvar_temp_offset_width := 2; when 8 => fvar_temp_offset_width := 3; when 16 => fvar_temp_offset_width := 4; when 32 => fvar_temp_offset_width := 5; when 64 => fvar_temp_offset_width := 6; when others => fvar_temp_offset_width := 7; end case; Return (fvar_temp_offset_width); end function funct_get_sf_offset_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_stream_width2use -- -- Function Description: -- This function calculates the Stream width to use for S2MM -- modules downstream from the upsizing Store and Forward. If -- Store and forward is present, then the effective Stream width -- is the MMAP data width. If no Store and Forward then the Stream -- width is the input Stream width from the User. -- ------------------------------------------------------------------- function funct_get_stream_width2use (mmap_data_width : integer; stream_data_width : integer; sf_enabled : integer) return integer is Variable fvar_temp_width : Integer := 32; begin If (sf_enabled > 0) Then fvar_temp_width := mmap_data_width; Else fvar_temp_width := stream_data_width; End if; Return (fvar_temp_width); end function funct_get_stream_width2use; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_bytes_per_dbeat -- -- Function Description: -- This function calculates the number of bytes transfered per -- databeat on the MMap AXI4 Write Data Channel by the S2MM. The -- value is based on input parameterization of included functions -- in the S2MM block. -- ------------------------------------------------------------------- function funct_get_bytes_per_dbeat (ibtt_enabled : integer ; gpsf_enabled : integer ; stream_dwidth : integer ; mmap_dwidth : integer ) return integer is Variable fvar_temp_bytes_per_xfer : Integer := 4; begin If (ibtt_enabled > 0 or gpsf_enabled > 0) Then -- transfers will be upsized to mmap data width fvar_temp_bytes_per_xfer := mmap_dwidth/8; Else -- transfers will be in stream data widths (may be narrow transfers on mmap) fvar_temp_bytes_per_xfer := stream_dwidth/8; End if; Return (fvar_temp_bytes_per_xfer); end function funct_get_bytes_per_dbeat; -- Constant Declarations ---------------------------------------- Constant SF_ENABLED : integer := C_INCLUDE_S2MM_GP_SF + C_S2MM_SUPPORT_INDET_BTT; Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_S2MM_MDATA_WIDTH, C_S2MM_SDATA_WIDTH, SF_ENABLED); Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant IS_NOT_MM2S : integer range 0 to 1 := 0; Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID; Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH; Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH; Constant S2MM_MDATA_WIDTH : integer range 32 to 1024 := C_S2MM_MDATA_WIDTH; Constant S2MM_SDATA_WIDTH : integer range 8 to 1024 := C_S2MM_SDATA_WIDTH; Constant S2MM_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH; Constant S2MM_CMD_WIDTH : integer := (S2MM_TAG_WIDTH+S2MM_ADDR_WIDTH+32); Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := C_INCLUDE_S2MM_STSFIFO; Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH; Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC; Constant S2MM_BURST_SIZE : integer range 2 to 256 := C_S2MM_BURST_SIZE; Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH); Constant S2MM_BTT_USED : integer range 8 to 23 := C_S2MM_BTT_USED; Constant BITS_PER_BYTE : integer := 8; Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_S2MM_DRE, S2MM_SDATA_WIDTH); Constant DRE_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant S2MM_DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_S2MM_DRE, S2MM_SDATA_WIDTH); Constant DRE_SUPPORT_SCATTER : integer range 0 to 1 := 1; Constant ENABLE_INDET_BTT_SF : integer range 0 to 1 := C_S2MM_SUPPORT_INDET_BTT; Constant ENABLE_GP_SF : integer range 0 to 1 := C_INCLUDE_S2MM_GP_SF ; Constant BYTES_PER_MMAP_DBEAT : integer := funct_get_bytes_per_dbeat(ENABLE_INDET_BTT_SF , ENABLE_GP_SF , S2MM_SDATA_WIDTH , S2MM_MDATA_WIDTH); Constant MAX_BYTES_PER_BURST : integer := BYTES_PER_MMAP_DBEATS2MM_BURST_SIZE; Constant IBTT_XFER_BYTES_WIDTH : integer := get_bits_needed(MAX_BYTES_PER_BURST); Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2; -- 2 added for going -- full thresholding -- in WSC Constant WSC_STATUS_WIDTH : integer range 8 to 32 := funct_set_status_width(ENABLE_INDET_BTT_SF); Constant WSC_BYTES_RCVD_WIDTH : integer range 8 to 32 := S2MM_BTT_USED; Constant ADD_REALIGNER : integer := funct_need_realigner(ENABLE_INDET_BTT_SF , INCLUDE_S2MM_DRE , ENABLE_GP_SF); -- Calculates the minimum needed depth of the GP Store and Forward FIFO -- based on the S2MM pipeline depth and the max allowed Burst length Constant PIPEDEPTH_BURST_LEN_PROD : integer := (ADDR_CNTL_FIFO_DEPTH+2) * S2MM_BURST_SIZE; -- Assigns the depth of the optional GP Store and Forward FIFO to the nearest -- power of 2 Constant SF_FIFO_DEPTH : integer range 128 to 8192 := funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD); -- Calculate the width of the Store and Forward Starting Address Offset bus Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(S2MM_MDATA_WIDTH, S2MM_SDATA_WIDTH); -- Signal Declarations ------------------------------------------ signal sig_cmd_stat_rst_user : std_logic := '0'; signal sig_cmd_stat_rst_int : std_logic := '0'; signal sig_mmap_rst : std_logic := '0'; signal sig_stream_rst : std_logic := '0'; signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0'); signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd2mstr_cmd_valid : std_logic := '0'; signal sig_mst2cmd_cmd_ready : std_logic := '0'; signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0'); signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_cmd_cmplt : std_logic := '0'; signal sig_mstr2addr_calc_error : std_logic := '0'; signal sig_mstr2addr_cmd_valid : std_logic := '0'; signal sig_addr2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_drr : std_logic := '0'; signal sig_mstr2data_eof : std_logic := '0'; signal sig_mstr2data_sequential : std_logic := '0'; signal sig_mstr2data_calc_error : std_logic := '0'; signal sig_mstr2data_cmd_last : std_logic := '0'; signal sig_mstr2data_cmd_valid : std_logic := '0'; signal sig_data2mstr_cmd_ready : std_logic := '0'; signal sig_addr2data_addr_posted : std_logic := '0'; signal sig_data2addr_data_rdy : std_logic := '0'; signal sig_data2all_tlast_error : std_logic := '0'; signal sig_data2all_dcntlr_halted : std_logic := '0'; signal sig_addr2wsc_calc_error : std_logic := '0'; signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0'; signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0'); signal sig_data2wsc_cmd_empty : std_logic := '0'; signal sig_data2wsc_calc_err : std_logic := '0'; signal sig_data2wsc_cmd_cmplt : std_logic := '0'; signal sig_data2wsc_last_err : std_logic := '0'; signal sig_calc2dm_calc_err : std_logic := '0'; signal sig_wsc2stat_status : std_logic_vector(WSC_STATUS_WIDTH-1 downto 0) := (others => '0'); signal sig_stat2wsc_status_ready : std_logic := '0'; signal sig_wsc2stat_status_valid : std_logic := '0'; signal sig_wsc2mstr_halt_pipe : std_logic := '0'; signal sig_data2wsc_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_wvalid : std_logic := '0'; signal sig_skid2data_wready : std_logic := '0'; signal sig_data2skid_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_data2skid_wlast : std_logic := '0'; signal sig_skid2axi_wvalid : std_logic := '0'; signal sig_axi2skid_wready : std_logic := '0'; signal sig_skid2axi_wdata : std_logic_vector(S2MM_MDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_skid2axi_wstrb : std_logic_vector((S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_skid2axi_wlast : std_logic := '0'; signal sig_data2wsc_sof : std_logic := '0'; signal sig_data2wsc_eof : std_logic := '0'; signal sig_data2wsc_valid : std_logic := '0'; signal sig_wsc2data_ready : std_logic := '0'; signal sig_data2wsc_eop : std_logic := '0'; signal sig_data2wsc_bytes_rcvd : std_logic_vector(WSC_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0'); signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_sf2pcc_xfer_valid : std_logic := '0'; signal sig_pcc2sf_xfer_ready : std_logic := '0'; signal sig_sf2pcc_cmd_cmplt : std_logic := '0'; signal sig_sf2pcc_packet_eop : std_logic := '0'; signal sig_sf2pcc_xfer_bytes : std_logic_vector(IBTT_XFER_BYTES_WIDTH-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tvalid : std_logic := '0'; signal sig_wdc2ibtt_tready : std_logic := '0'; signal sig_ibtt2wdc_tdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tlast : std_logic := '0'; signal sig_ibtt2wdc_eop : std_logic := '0'; signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(7 downto 0) := (others => '0'); signal sig_dre2ibtt_tvalid : std_logic := '0'; signal sig_ibtt2dre_tready : std_logic := '0'; signal sig_dre2ibtt_tdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_dre2ibtt_tstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_dre2ibtt_tlast : std_logic := '0'; signal sig_dre2ibtt_eop : std_logic := '0'; signal sig_dre2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2dre_cmd_valid : std_logic := '0'; signal sig_mstr2dre_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_dre_src_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_dre_dest_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_btt : std_logic_vector(S2MM_BTT_USED-1 downto 0) := (others => '0'); signal sig_mstr2dre_drr : std_logic := '0'; signal sig_mstr2dre_eof : std_logic := '0'; signal sig_mstr2dre_cmd_cmplt : std_logic := '0'; signal sig_mstr2dre_calc_error : std_logic := '0'; signal sig_realign2wdc_eop_error : std_logic := '0'; signal sig_dre2all_halted : std_logic := '0'; signal sig_rst2all_stop_request : std_logic := '0'; signal sig_data2rst_stop_cmplt : std_logic := '0'; signal sig_addr2rst_stop_cmplt : std_logic := '0'; signal sig_data2addr_stop_req : std_logic := '0'; signal sig_wsc2rst_stop_cmplt : std_logic := '0'; signal sig_data2skid_halt : std_logic := '0'; signal skid2dre_wvalid : std_logic := '0'; signal dre2skid_wready : std_logic := '0'; signal skid2dre_wdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0'); signal skid2dre_wstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal skid2dre_wlast : std_logic := '0'; signal sig_s2mm_allow_addr_req : std_logic := '0'; signal sig_ok_to_post_wr_addr : std_logic := '0'; signal sig_s2mm_addr_req_posted : std_logic := '0'; signal sig_s2mm_wr_xfer_cmplt : std_logic := '0'; signal sig_s2mm_ld_nxt_len : std_logic := '0'; signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_ibtt2wdc_error : std_logic := '0'; signal sig_sf_strt_addr_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_cache2mstr_command : std_logic_vector (7 downto 0); signal s2mm_awcache_int : std_logic_vector (3 downto 0); signal s2mm_awuser_int : std_logic_vector (3 downto 0); begin --(architecture implementation) -- Debug/Test Port Assignments s2mm_dbg_data <= sig_dbg_data_mux_out; -- Note that only the s2mm_dbg_sel(0) is used at this time sig_dbg_data_mux_out <= sig_dbg_data_1 When (s2mm_dbg_sel(0) = '1') else sig_dbg_data_0 ; sig_dbg_data_0 <= X"CAFE1111" ; -- 32 bit Constant indicating S2MM FULL type sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ; sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ; sig_dbg_data_1(2) <= sig_mmap_rst ; sig_dbg_data_1(3) <= sig_stream_rst ; sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ; sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ; sig_dbg_data_1(6) <= sig_stat2wsc_status_ready; sig_dbg_data_1(7) <= sig_wsc2stat_status_valid; sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error --sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADD_DEBUG_EOP -- -- If Generate Description: -- -- This IfGen adds in the EOP status marker to the debug -- vector data when Indet BTT Store and Forward is enabled. -- ------------------------------------------------------------ GEN_ADD_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 1) generate begin sig_dbg_data_1(19) <= sig_wsc2stat_status(31) ; -- EOP Marker end generate GEN_ADD_DEBUG_EOP; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_DEBUG_EOP -- -- If Generate Description: -- -- This IfGen zeros the debug vector bit used for the EOP -- status marker when Indet BTT Store and Forward is not -- enabled. -- ------------------------------------------------------------ GEN_NO_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 0) generate begin sig_dbg_data_1(19) <= '0' ; -- EOP Marker end generate GEN_NO_DEBUG_EOP; ---- End of Debug/Test Support -------------------------------- -- Assign the Address posting control outputs s2mm_addr_req_posted <= sig_s2mm_addr_req_posted ; s2mm_wr_xfer_cmplt <= sig_s2mm_wr_xfer_cmplt ; s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len ; s2mm_wr_len <= sig_s2mm_wr_len ; -- Write Data Channel I/O s2mm_wvalid <= sig_skid2axi_wvalid; sig_axi2skid_wready <= s2mm_wready ; s2mm_wdata <= sig_skid2axi_wdata ; s2mm_wlast <= sig_skid2axi_wlast ; GEN_S2MM_TKEEP_ENABLE2 : if C_ENABLE_S2MM_TKEEP = 1 generate begin s2mm_wstrb <= sig_skid2axi_wstrb ; end generate GEN_S2MM_TKEEP_ENABLE2; GEN_S2MM_TKEEP_DISABLE2 : if C_ENABLE_S2MM_TKEEP = 0 generate begin s2mm_wstrb <= (others => '1'); end generate GEN_S2MM_TKEEP_DISABLE2; GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate begin -- Cache signal tie-off s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96); end generate GEN_CACHE; GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate begin -- Cache signal tie-off s2mm_awcache <= s2mm_awcache_int; -- pre Interface-X guidelines for Masters s2mm_awuser <= s2mm_awuser_int; -- pre Interface-X guidelines for Masters sig_s2mm_cache_data <= s2mm_cmd_wdata(79+(C_S2MM_ADDR_WIDTH-32) downto 72+(C_S2MM_ADDR_WIDTH-32)); -- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96); end generate GEN_CACHE2; -- Internal error output discrete s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error; -- Rip the used portion of the Command Interface Command Data -- and throw away the padding sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0); ------------------------------------------------------------ -- Instance: I_RESET -- -- Description: -- Reset Block -- ------------------------------------------------------------ I_RESET : entity axi_datamover_v5_1_10.axi_datamover_reset generic map ( C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ) port map ( primary_aclk => s2mm_aclk , primary_aresetn => s2mm_aresetn , secondary_awclk => s2mm_cmdsts_awclk , secondary_aresetn => s2mm_cmdsts_aresetn , halt_req => s2mm_halt , halt_cmplt => s2mm_halt_cmplt , flush_stop_request => sig_rst2all_stop_request , data_cntlr_stopped => sig_data2rst_stop_cmplt , addr_cntlr_stopped => sig_addr2rst_stop_cmplt , aux1_stopped => sig_wsc2rst_stop_cmplt , aux2_stopped => LOGIC_HIGH , cmd_stat_rst_user => sig_cmd_stat_rst_user , cmd_stat_rst_int => sig_cmd_stat_rst_int , mmap_rst => sig_mmap_rst , stream_rst => sig_stream_rst ); ------------------------------------------------------------ -- Instance: I_CMD_STATUS -- -- Description: -- Command and Status Interface Block -- ------------------------------------------------------------ I_CMD_STATUS : entity axi_datamover_v5_1_10.axi_datamover_cmd_status generic map ( C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO , C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH , C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_STS_WIDTH => WSC_STATUS_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , secondary_awclk => s2mm_cmdsts_awclk , user_reset => sig_cmd_stat_rst_user , internal_reset => sig_cmd_stat_rst_int , cmd_wvalid => s2mm_cmd_wvalid , cmd_wready => s2mm_cmd_wready , cmd_wdata => sig_s2mm_cmd_wdata , cache_data => sig_s2mm_cache_data , sts_wvalid => s2mm_sts_wvalid , sts_wready => s2mm_sts_wready , sts_wdata => s2mm_sts_wdata , sts_wstrb => s2mm_sts_wstrb , sts_wlast => s2mm_sts_wlast , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid , cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready , mstr2stat_status => sig_wsc2stat_status , stat2mstr_status_ready => sig_stat2wsc_status_ready , mst2stst_status_valid => sig_wsc2stat_status_valid ); ------------------------------------------------------------ -- Instance: I_WR_STATUS_CNTLR -- -- Description: -- Write Status Controller Block -- ------------------------------------------------------------ I_WR_STATUS_CNTLR : entity axi_datamover_v5_1_10.axi_datamover_wr_status_cntl generic map ( C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH , C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH , C_STS_WIDTH => WSC_STATUS_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , rst2wsc_stop_request => sig_rst2all_stop_request , wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt , addr2wsc_addr_posted => sig_addr2data_addr_posted , s2mm_bresp => s2mm_bresp , s2mm_bvalid => s2mm_bvalid , s2mm_bready => s2mm_bready , calc2wsc_calc_error => sig_calc2dm_calc_err , addr2wsc_calc_error => sig_addr2wsc_calc_error , addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty , data2wsc_tag => sig_data2wsc_tag , data2wsc_calc_error => sig_data2wsc_calc_err , data2wsc_last_error => sig_data2wsc_last_err , data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt , data2wsc_valid => sig_data2wsc_valid , wsc2data_ready => sig_wsc2data_ready , data2wsc_eop => sig_data2wsc_eop , data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd , wsc2stat_status => sig_wsc2stat_status , stat2wsc_status_ready => sig_stat2wsc_status_ready , wsc2stat_status_valid => sig_wsc2stat_status_valid , wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe ); ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_PCC -- -- If Generate Description: -- Include the normal Predictive Command Calculator function, -- Store and Forward is not an included feature. -- -- ------------------------------------------------------------ GEN_INCLUDE_PCC : if (ENABLE_INDET_BTT_SF = 0) generate begin ------------------------------------------------------------ -- Instance: I_MSTR_PCC -- -- Description: -- Predictive Command Calculator Block -- ------------------------------------------------------------ I_MSTR_PCC : entity axi_datamover_v5_1_10.axi_datamover_pcc generic map ( C_IS_MM2S => IS_NOT_MM2S , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_BTT_USED => S2MM_BTT_USED , C_SUPPORT_INDET_BTT => ENABLE_INDET_BTT_SF , C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ) port map ( -- Clock input primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , mstr2data_dre_src_align => open , mstr2data_dre_dest_align => open , calc_error => sig_calc2dm_calc_err , dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset ); end generate GEN_INCLUDE_PCC; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_IBTTCC -- -- If Generate Description: -- Include the Indeterminate BTT Command Calculator function, -- Store and Forward is enabled in the S2MM. -- -- ------------------------------------------------------------ GEN_INCLUDE_IBTTCC : if (ENABLE_INDET_BTT_SF = 1) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_MSTR_SFCC -- -- Description: -- Instantiates the Store and Forward Command Calculator -- Block. -- ------------------------------------------------------------ I_S2MM_MSTR_IBTTCC : entity axi_datamover_v5_1_10.axi_datamover_ibttcc generic map ( C_SF_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_BTT_USED => S2MM_BTT_USED , C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ) port map ( -- Clock input primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid , pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready , sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt , sf2pcc_packet_eop => sig_sf2pcc_packet_eop , sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , calc_error => sig_calc2dm_calc_err , dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset ); end generate GEN_INCLUDE_IBTTCC; ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate begin ------------------------------------------------------------ -- Instance: I_S2MM_STRM_SKID_BUF -- -- Description: -- Instance for the S2MM Skid Buffer which provides for -- registerd Slave Stream inputs and supports bi-dir -- throttling. -- ------------------------------------------------------------ I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => S2MM_SDATA_WIDTH ) port map ( -- System Ports aclk => s2mm_aclk , arst => sig_mmap_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => sig_data2skid_halt , -- Slave Side (Stream Data Input) s_valid => s2mm_strm_wvalid , s_ready => s2mm_strm_wready , s_data => s2mm_strm_wdata , s_strb => s2mm_strm_wstrb , s_last => s2mm_strm_wlast , -- Master Side (Stream Data Output m_valid => skid2dre_wvalid , m_ready => dre2skid_wready , m_data => skid2dre_wdata , m_strb => skid2dre_wstrb , m_last => skid2dre_wlast ); end generate ENABLE_AXIS_SKID; DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate begin skid2dre_wvalid <= s2mm_strm_wvalid; s2mm_strm_wready <= dre2skid_wready; skid2dre_wdata <= s2mm_strm_wdata; skid2dre_wstrb <= s2mm_strm_wstrb; skid2dre_wlast <= s2mm_strm_wlast; end generate DISABLE_AXIS_SKID; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_REALIGNER -- -- If Generate Description: -- Omit the S2MM Realignment Engine -- -- ------------------------------------------------------------ GEN_NO_REALIGNER : if (ADD_REALIGNER = 0) generate begin -- Set to Always ready for DRE to PCC Command Interface sig_dre2mstr_cmd_ready <= LOGIC_HIGH; -- Without DRE and Scatter, the end of packet is the TLAST --sig_dre2ibtt_eop <= skid2dre_wlast ; sig_dre2ibtt_eop <= sig_dre2ibtt_tlast ; -- use skid buffered version -- Cant't detect undrrun/overrun here sig_realign2wdc_eop_error <= '0'; ENABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '1' generate begin ------------------------------------------------------------ -- Instance: I_NO_REALIGN_SKID_BUF -- -- Description: -- Instance for a Skid Buffer which provides for -- Fmax timing improvement between the Null Absorber and -- the Write Data controller when the Realigner is not -- present (no DRE and no Store and Forward case). -- ------------------------------------------------------------ I_NO_REALIGN_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => S2MM_SDATA_WIDTH ) port map ( -- System Ports aclk => s2mm_aclk , arst => sig_mmap_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => LOGIC_LOW , -- Slave Side (Null Absorber Input) s_valid => skid2dre_wvalid , s_ready => dre2skid_wready , s_data => skid2dre_wdata , s_strb => skid2dre_wstrb , s_last => skid2dre_wlast , -- Master Side (Stream Data Output to WData Cntlr) m_valid => sig_dre2ibtt_tvalid , m_ready => sig_ibtt2dre_tready , m_data => sig_dre2ibtt_tdata , m_strb => sig_dre2ibtt_tstrb , m_last => sig_dre2ibtt_tlast ); end generate ENABLE_NOREALIGNER_SKID; DISABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '0' generate begin sig_dre2ibtt_tvalid <= skid2dre_wvalid; dre2skid_wready <= sig_ibtt2dre_tready; sig_dre2ibtt_tdata <= skid2dre_wdata; sig_dre2ibtt_tstrb <= skid2dre_wstrb; sig_dre2ibtt_tlast <= skid2dre_wlast; end generate DISABLE_NOREALIGNER_SKID; end generate GEN_NO_REALIGNER; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_REALIGNER -- -- If Generate Description: -- Include the S2MM realigner Module. It hosts the S2MM DRE -- and the Scatter Block. -- -- Note that the General Purpose Store and Forward Module -- needs the Scatter function to detect input overrun and -- underrun events on the AXI Stream input. Thus the Realigner -- is included whenever the GP Store and Forward is enabled. -- ------------------------------------------------------------ GEN_INCLUDE_REALIGNER : if (ADD_REALIGNER = 1) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_REALIGNER -- -- Description: -- Instance for the S2MM Data Realignment Module. -- ------------------------------------------------------------ I_S2MM_REALIGNER : entity axi_datamover_v5_1_10.axi_datamover_s2mm_realign generic map ( C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_INCLUDE_DRE => INCLUDE_S2MM_DRE , C_DRE_CNTL_FIFO_DEPTH => DRE_CNTL_FIFO_DEPTH , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SUPPORT_SCATTER => DRE_SUPPORT_SCATTER , C_BTT_USED => S2MM_BTT_USED , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , -- Write Data Controller or Store and Forward I/O ------- wdc2dre_wready => sig_ibtt2dre_tready , dre2wdc_wvalid => sig_dre2ibtt_tvalid , dre2wdc_wdata => sig_dre2ibtt_tdata , dre2wdc_wstrb => sig_dre2ibtt_tstrb , dre2wdc_wlast => sig_dre2ibtt_tlast , dre2wdc_eop => sig_dre2ibtt_eop , -- Starting offset output ------------------------------- dre2sf_strt_offset => sig_sf_strt_addr_offset , -- AXI Slave Stream In ----------------------------------- s2mm_strm_wready => dre2skid_wready , s2mm_strm_wvalid => skid2dre_wvalid , s2mm_strm_wdata => skid2dre_wdata , s2mm_strm_wstrb => skid2dre_wstrb , s2mm_strm_wlast => skid2dre_wlast , -- Command Calculator Interface -------------------------- dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset , -- Premature TLAST assertion error flag dre2all_tlast_error => sig_realign2wdc_eop_error , -- DRE Halted Status dre2all_halted => sig_dre2all_halted ); end generate GEN_INCLUDE_REALIGNER; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ENABLE_INDET_BTT_SF -- -- If Generate Description: -- Include the Indeterminate BTT Logic with specialized -- Store and Forward function, This also requires the -- Scatter Engine in the Realigner module. -- -- ------------------------------------------------------------ GEN_ENABLE_INDET_BTT_SF : if (ENABLE_INDET_BTT_SF = 1) generate begin -- Pass the Realigner EOP error through sig_ibtt2wdc_error <= sig_realign2wdc_eop_error; -- Use only external address posting enable sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ; ------------------------------------------------------------ -- Instance: I_INDET_BTT -- -- Description: -- Instance for the Indeterminate BTT with Store and Forward -- module. -- ------------------------------------------------------------ I_INDET_BTT : entity axi_datamover_v5_1_10.axi_datamover_indet_btt generic map ( C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , C_IBTT_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH , C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_ENABLE_DRE => INCLUDE_S2MM_DRE , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , ibtt2wdc_stbs_asserted => sig_ibtt2wdc_stbs_asserted, ibtt2wdc_eop => sig_ibtt2wdc_eop , ibtt2wdc_tdata => sig_ibtt2wdc_tdata , ibtt2wdc_tstrb => sig_ibtt2wdc_tstrb , ibtt2wdc_tlast => sig_ibtt2wdc_tlast , ibtt2wdc_tvalid => sig_ibtt2wdc_tvalid , wdc2ibtt_tready => sig_wdc2ibtt_tready , dre2ibtt_tvalid => sig_dre2ibtt_tvalid , ibtt2dre_tready => sig_ibtt2dre_tready , dre2ibtt_tdata => sig_dre2ibtt_tdata , dre2ibtt_tstrb => sig_dre2ibtt_tstrb , dre2ibtt_tlast => sig_dre2ibtt_tlast , dre2ibtt_eop => sig_dre2ibtt_eop , dre2ibtt_strt_addr_offset => sig_sf_strt_addr_offset , sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid , pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready , sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt , sf2pcc_packet_eop => sig_sf2pcc_packet_eop , sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes ); end generate GEN_ENABLE_INDET_BTT_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_SF -- -- If Generate Description: -- Bypasses any store and Forward functions. -- -- ------------------------------------------------------------ GEN_NO_SF : if (ENABLE_INDET_BTT_SF = 0 and ENABLE_GP_SF = 0) generate begin -- Use only external address posting enable sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ; -- Housekeep unused signal in this case sig_ok_to_post_wr_addr <= '0' ; -- SFCC Interface Signals that are not used sig_pcc2sf_xfer_ready <= '0' ; sig_sf2pcc_xfer_valid <= '0' ; sig_sf2pcc_cmd_cmplt <= '0' ; sig_sf2pcc_packet_eop <= '0' ; sig_sf2pcc_xfer_bytes <= (others => '0') ; -- Just pass DRE signals through sig_ibtt2dre_tready <= sig_wdc2ibtt_tready ; sig_ibtt2wdc_tvalid <= sig_dre2ibtt_tvalid ; sig_ibtt2wdc_tdata <= sig_dre2ibtt_tdata ; sig_ibtt2wdc_tstrb <= sig_dre2ibtt_tstrb ; sig_ibtt2wdc_tlast <= sig_dre2ibtt_tlast ; sig_ibtt2wdc_eop <= sig_dre2ibtt_eop ; sig_ibtt2wdc_stbs_asserted <= (others => '0') ; -- Pass the Realigner EOP error through sig_ibtt2wdc_error <= sig_realign2wdc_eop_error; end generate GEN_NO_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_GP_SF -- -- If Generate Description: -- Include the General Purpose Store and Forward module. -- This If Generate can only be enabled when -- Indeterminate BTT mode is not enabled. The General Purpose -- Store and Forward is instantiated in place of the Indet -- BTT Store and Forward. -- ------------------------------------------------------------ GEN_INCLUDE_GP_SF : if (ENABLE_INDET_BTT_SF = 0 and ENABLE_GP_SF = 1) generate begin -- Merge the external address posting control with the -- SF address posting control. sig_s2mm_allow_addr_req <= s2mm_allow_addr_req and sig_ok_to_post_wr_addr ; -- Zero these out since Indet BTT is not enabled, they -- are only used by the WDC in that mode sig_ibtt2wdc_stbs_asserted <= (others => '0') ; sig_ibtt2wdc_eop <= '0' ; -- SFCC Interface Signals that are not used sig_pcc2sf_xfer_ready <= '0' ; sig_sf2pcc_xfer_valid <= '0' ; sig_sf2pcc_cmd_cmplt <= '0' ; sig_sf2pcc_packet_eop <= '0' ; sig_sf2pcc_xfer_bytes <= (others => '0') ; ------------------------------------------------------------ -- Instance: I_S2MM_GP_SF -- -- Description: -- Instance for the S2MM (Write) General Purpose Store and -- Forward Module. This module can only be enabled when -- Indeterminate BTT mode is not enabled. It is connected -- in place of the IBTT Module when GP SF is enabled. -- ------------------------------------------------------------ I_S2MM_GP_SF : entity axi_datamover_v5_1_10.axi_datamover_wr_sf generic map ( C_WR_ADDR_PIPE_DEPTH => ADDR_CNTL_FIFO_DEPTH , C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset inputs ----------------------------- aclk => s2mm_aclk , reset => sig_mmap_rst , -- Slave Stream Input -------------------------------- sf2sin_tready => sig_ibtt2dre_tready , sin2sf_tvalid => sig_dre2ibtt_tvalid , sin2sf_tdata => sig_dre2ibtt_tdata , sin2sf_tkeep => sig_dre2ibtt_tstrb , sin2sf_tlast => sig_dre2ibtt_tlast , sin2sf_error => sig_realign2wdc_eop_error , -- Starting Address Offset Input --------------------- sin2sf_strt_addr_offset => sig_sf_strt_addr_offset , -- DataMover Write Side Address Pipelining Control Interface -------- ok_to_post_wr_addr => sig_ok_to_post_wr_addr , wr_addr_posted => sig_s2mm_addr_req_posted , wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt , wr_ld_nxt_len => sig_s2mm_ld_nxt_len , wr_len => sig_s2mm_wr_len , -- Write Side Stream Out to DataMover S2MM ------------- sout2sf_tready => sig_wdc2ibtt_tready , sf2sout_tvalid => sig_ibtt2wdc_tvalid , sf2sout_tdata => sig_ibtt2wdc_tdata , sf2sout_tkeep => sig_ibtt2wdc_tstrb , sf2sout_tlast => sig_ibtt2wdc_tlast , sf2sout_error => sig_ibtt2wdc_error ); end generate GEN_INCLUDE_GP_SF; ------------------------------------------------------------ -- Instance: I_ADDR_CNTL -- -- Description: -- Address Controller Block -- ------------------------------------------------------------ I_ADDR_CNTL : entity axi_datamover_v5_1_10.axi_datamover_addr_cntl generic map ( C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_ADDR_ID => S2MM_AWID_VALUE , C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , addr2axi_aid => s2mm_awid , addr2axi_aaddr => s2mm_awaddr , addr2axi_alen => s2mm_awlen , addr2axi_asize => s2mm_awsize , addr2axi_aburst => s2mm_awburst , addr2axi_aprot => s2mm_awprot , addr2axi_avalid => s2mm_awvalid , addr2axi_acache => s2mm_awcache_int , addr2axi_auser => s2mm_awuser_int , axi2addr_aready => s2mm_awready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , -- mstr2addr_cache_info => sig_cache2mstr_command , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt , allow_addr_req => sig_s2mm_allow_addr_req , addr_req_posted => sig_s2mm_addr_req_posted , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => sig_data2addr_data_rdy , data2addr_stop_req => sig_data2addr_stop_req , addr2stat_calc_error => sig_addr2wsc_calc_error , addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty ); ------------------------------------------------------------ -- Instance: I_WR_DATA_CNTL -- -- Description: -- Write Data Controller Block -- ------------------------------------------------------------ I_WR_DATA_CNTL : entity axi_datamover_v5_1_10.axi_datamover_wrdata_cntl generic map ( C_REALIGNER_INCLUDED => ADD_REALIGNER , C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , rst2data_stop_request => sig_rst2all_stop_request , data2addr_stop_req => sig_data2addr_stop_req , data2rst_stop_cmplt => sig_data2rst_stop_cmplt , wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt , s2mm_ld_nxt_len => sig_s2mm_ld_nxt_len , s2mm_wr_len => sig_s2mm_wr_len , data2skid_saddr_lsb => sig_data2skid_addr_lsb , data2skid_wdata => sig_data2skid_wdata , data2skid_wstrb => sig_data2skid_wstrb , data2skid_wlast => sig_data2skid_wlast , data2skid_wvalid => sig_data2skid_wvalid , skid2data_wready => sig_skid2data_wready , s2mm_strm_wvalid => sig_ibtt2wdc_tvalid , s2mm_strm_wready => sig_wdc2ibtt_tready , s2mm_strm_wdata => sig_ibtt2wdc_tdata , s2mm_strm_wstrb => sig_ibtt2wdc_tstrb , s2mm_strm_wlast => sig_ibtt2wdc_tlast , s2mm_strm_eop => sig_ibtt2wdc_eop , s2mm_stbs_asserted => sig_ibtt2wdc_stbs_asserted, realign2wdc_eop_error => sig_ibtt2wdc_error , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => sig_data2addr_data_rdy , data2all_tlast_error => sig_data2all_tlast_error , data2all_dcntlr_halted => sig_data2all_dcntlr_halted, data2skid_halt => sig_data2skid_halt , data2wsc_tag => sig_data2wsc_tag , data2wsc_calc_err => sig_data2wsc_calc_err , data2wsc_last_err => sig_data2wsc_last_err , data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt , wsc2data_ready => sig_wsc2data_ready , data2wsc_valid => sig_data2wsc_valid , data2wsc_eop => sig_data2wsc_eop , data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd , wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe ); --ENABLE_AXIMMAP_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate --begin ------------------------------------------------------------ -- Instance: I_S2MM_MMAP_SKID_BUF -- -- Description: -- Instance for the S2MM Skid Buffer which provides for -- registered outputs and supports bi-dir throttling. -- -- This Module also provides Write Data Bus Mirroring and WSTRB -- Demuxing to match a narrow Stream to a wider MMap Write -- Channel. By doing this in the skid buffer, the resource -- utilization of the skid buffer can be minimized by only -- having to buffer/mux the Stream data width, not the MMap -- Data width. -- ------------------------------------------------------------ I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_skid2mm_buf generic map ( C_MDATA_WIDTH => S2MM_MDATA_WIDTH , C_SDATA_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH ) port map ( -- System Ports ACLK => s2mm_aclk , ARST => sig_stream_rst , -- Slave Side (Wr Data Controller Input Side ) S_ADDR_LSB => sig_data2skid_addr_lsb, S_VALID => sig_data2skid_wvalid , S_READY => sig_skid2data_wready , S_Data => sig_data2skid_wdata , S_STRB => sig_data2skid_wstrb , S_Last => sig_data2skid_wlast , -- Master Side (MMap Write Data Output Side) M_VALID => sig_skid2axi_wvalid , M_READY => sig_axi2skid_wready , M_Data => sig_skid2axi_wdata , M_STRB => sig_skid2axi_wstrb , M_Last => sig_skid2axi_wlast ); --end generate ENABLE_AXIMMAP_SKID; end implementation;
------------------------------------------------------------------------------- -- axi_datamover_s2mm_full_wrap.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_s2mm_full_wrap.vhd -- -- Description: -- This file implements the DataMover S2MM FULL Wrapper. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all ; -- axi_datamover Library Modules library axi_datamover_v5_1_10; use axi_datamover_v5_1_10.axi_datamover_reset ; use axi_datamover_v5_1_10.axi_datamover_cmd_status ; use axi_datamover_v5_1_10.axi_datamover_pcc ; use axi_datamover_v5_1_10.axi_datamover_ibttcc ; use axi_datamover_v5_1_10.axi_datamover_indet_btt ; use axi_datamover_v5_1_10.axi_datamover_s2mm_realign ; use axi_datamover_v5_1_10.axi_datamover_addr_cntl ; use axi_datamover_v5_1_10.axi_datamover_wrdata_cntl ; use axi_datamover_v5_1_10.axi_datamover_wr_status_cntl; Use axi_datamover_v5_1_10.axi_datamover_skid2mm_buf ; Use axi_datamover_v5_1_10.axi_datamover_skid_buf ; Use axi_datamover_v5_1_10.axi_datamover_wr_sf ; ------------------------------------------------------------------------------- entity axi_datamover_s2mm_full_wrap is generic ( C_INCLUDE_S2MM : Integer range 0 to 2 := 1; -- Specifies the type of S2MM function to include -- 0 = Omit S2MM functionality -- 1 = Full S2MM Functionality -- 2 = Lite S2MM functionality C_S2MM_AWID : Integer range 0 to 255 := 9; -- Specifies the constant value to output on -- the ARID output port C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the S2MM ID port C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the S2MM Master Stream Data -- Channel data bus C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit S2MM Status FIFO -- 1 = Include S2MM Status FIFO C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the S2MM Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0; -- Specifies if DRE is to be included in the S2MM function -- 0 = Omit DRE -- 1 = Include DRE C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the S2MM function C_S2MM_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the S2MM Command Interface C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0; -- Specifies if support for indeterminate packet lengths -- are to be received on the input Stream interface -- 0 = Omit support (User MUST transfer the exact number of -- bytes on the Stream interface as specified in the BTT -- field of the Corresponding DataMover Command) -- 1 = Include support for indeterminate packet lengths -- This causes FIFOs to be added and "Store and Forward" -- behavior of the S2MM function C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3; -- This parameter specifies the depth of the S2MM internal -- address pipeline queues in the Write Address Controller -- and the Write Data Controller. Increasing this value will -- allow more Write Addresses to be issued to the AXI4 Write -- Address Channel before transmission of the associated -- write data on the Write Data Channel. C_TAG_WIDTH : Integer range 1 to 8 := 4 ; -- Width of the TAG field C_INCLUDE_S2MM_GP_SF : Integer range 0 to 1 := 1 ; -- This parameter specifies the inclusion/omission of the -- S2MM (Write) General Purpose Store and Forward function -- 0 = Omit GP Store and Forward -- 1 = Include GP Store and Forward C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1; C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1; C_ENABLE_SKID_BUF : string := "11111"; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- S2MM Primary Clock and Reset inputs ---------------------------- s2mm_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- ------------------------------------------------------------------- -- S2MM Primary Reset input --------------------------------------- s2mm_aresetn : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------------- -- S2MM Halt request input control -------------------------------- s2mm_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- S2MM Halt Complete status flag -- s2mm_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------------------- -- S2MM Error discrete output ------------------------------------- s2mm_err : Out std_logic; -- -- Composite Error indication -- ------------------------------------------------------------------- -- Optional Command and Status Clock and Reset ------------------- -- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 -- -- s2mm_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- s2mm_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- ------------------------------------------------------------------ -- User Command Interface Ports (AXI Stream) ----------------------------------------------------- s2mm_cmd_wvalid : in std_logic; -- s2mm_cmd_wready : out std_logic; -- s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); -- -------------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) -------------------------------------------------------- s2mm_sts_wvalid : out std_logic; -- s2mm_sts_wready : in std_logic; -- s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT24)+8)-1 downto 0); -- s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT24)+8)/8)-1 downto 0); -- s2mm_sts_wlast : out std_logic; -- ---------------------------------------------------------------------------------------------------- -- Address posting controls --------------------------------------- s2mm_allow_addr_req : in std_logic; -- s2mm_addr_req_posted : out std_logic; -- s2mm_wr_xfer_cmplt : out std_logic; -- s2mm_ld_nxt_len : out std_logic; -- s2mm_wr_len : out std_logic_vector(7 downto 0); -- ------------------------------------------------------------------- -- S2MM AXI Address Channel I/O -------------------------------------- s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- s2mm_awlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- s2mm_awsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- s2mm_awburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- s2mm_awprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- s2mm_awcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel PROT output -- s2mm_awuser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel PROT output -- -- s2mm_awvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- s2mm_awready : in std_logic; -- -- AXI Address Channel READY input -- ----------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ----------- -- s2mm__awlock : out std_logic_vector(2 downto 0); -- -- s2mm__awcache : out std_logic_vector(4 downto 0); -- -- s2mm__awqos : out std_logic_vector(3 downto 0); -- -- s2mm__awregion : out std_logic_vector(3 downto 0); -- ----------------------------------------------------------------------- -- S2MM AXI MMap Write Data Channel I/O --------------------------------------------- s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); -- s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); -- s2mm_wlast : Out std_logic; -- s2mm_wvalid : Out std_logic; -- s2mm_wready : In std_logic; -- -------------------------------------------------------------------------------------- -- S2MM AXI MMap Write response Channel I/O ----------------------------------------- s2mm_bresp : In std_logic_vector(1 downto 0); -- s2mm_bvalid : In std_logic; -- s2mm_bready : Out std_logic; -- -------------------------------------------------------------------------------------- -- S2MM AXI Master Stream Channel I/O ----------------------------------------------- s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); -- s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); -- s2mm_strm_wlast : In std_logic; -- s2mm_strm_wvalid : In std_logic; -- s2mm_strm_wready : Out std_logic; -- -------------------------------------------------------------------------------------- -- Testing Support I/O ------------------------------------------ s2mm_dbg_sel : in std_logic_vector( 3 downto 0); -- s2mm_dbg_data : out std_logic_vector(31 downto 0) -- ----------------------------------------------------------------- ); end entity axi_datamover_s2mm_full_wrap; architecture implementation of axi_datamover_s2mm_full_wrap is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations ---------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: func_calc_wdemux_sel_bits -- -- Function Description: -- This function calculates the number of address bits needed for -- the Write Strobe demux select control. -- ------------------------------------------------------------------- function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is Variable num_addr_bits_needed : Integer range 1 to 7 := 1; begin case mmap_dwidth_value is when 32 => num_addr_bits_needed := 2; when 64 => num_addr_bits_needed := 3; when 128 => num_addr_bits_needed := 4; when 256 => num_addr_bits_needed := 5; when 512 => num_addr_bits_needed := 6; when others => -- 1024 bits num_addr_bits_needed := 7; end case; Return (num_addr_bits_needed); end function func_calc_wdemux_sel_bits; ------------------------------------------------------------------- -- Function -- -- Function Name: func_include_dre -- -- Function Description: -- This function desides if conditions are right for allowing DRE -- inclusion. -- ------------------------------------------------------------------- function func_include_dre (need_dre : integer; needed_data_width : integer) return integer is Variable include_dre : Integer := 0; begin if (need_dre = 1 and needed_data_width < 128 and needed_data_width > 8) Then include_dre := 1; Else include_dre := 0; End if; Return (include_dre); end function func_include_dre; ------------------------------------------------------------------- -- Function -- -- Function Name: func_get_align_width -- -- Function Description: -- This function calculates the needed DRE alignment port width\ -- based upon the inclusion of DRE and the needed bit width of the -- DRE. -- ------------------------------------------------------------------- function func_get_align_width (dre_included : integer; dre_data_width : integer) return integer is Variable align_port_width : Integer := 1; begin if (dre_included = 1) then If (dre_data_width = 64) Then align_port_width := 3; Elsif (dre_data_width = 32) Then align_port_width := 2; else -- 16 bit data width align_port_width := 1; End if; else align_port_width := 1; end if; Return (align_port_width); end function func_get_align_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_set_status_width -- -- Function Description: -- This function sets the width of the Status pipe depending on the -- Store and Forward inclusion or ommision. -- ------------------------------------------------------------------- function funct_set_status_width (store_forward_enabled : integer) return integer is Variable temp_status_bit_width : Integer := 8; begin If (store_forward_enabled = 1) Then temp_status_bit_width := 32; Else temp_status_bit_width := 8; End if; Return (temp_status_bit_width); end function funct_set_status_width; ------------------------------------------------------------------- -- Function -- -- Function Name: get_bits_needed -- -- Function Description: -- -- ------------------------------------------------------------------- function get_bits_needed (max_bytes : integer) return integer is Variable fvar_temp_bit_width : Integer := 1; begin if (max_bytes <= 1) then fvar_temp_bit_width := 1; elsif (max_bytes <= 3) then fvar_temp_bit_width := 2; elsif (max_bytes <= 7) then fvar_temp_bit_width := 3; elsif (max_bytes <= 15) then fvar_temp_bit_width := 4; elsif (max_bytes <= 31) then fvar_temp_bit_width := 5; elsif (max_bytes <= 63) then fvar_temp_bit_width := 6; elsif (max_bytes <= 127) then fvar_temp_bit_width := 7; elsif (max_bytes <= 255) then fvar_temp_bit_width := 8; elsif (max_bytes <= 511) then fvar_temp_bit_width := 9; elsif (max_bytes <= 1023) then fvar_temp_bit_width := 10; elsif (max_bytes <= 2047) then fvar_temp_bit_width := 11; elsif (max_bytes <= 4095) then fvar_temp_bit_width := 12; elsif (max_bytes <= 8191) then fvar_temp_bit_width := 13; else -- 8k - 16K fvar_temp_bit_width := 14; end if; Return (fvar_temp_bit_width); end function get_bits_needed; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_rnd2pwr_of_2 -- -- Function Description: -- Rounds the input value up to the nearest power of 2 between -- 128 and 8192. -- ------------------------------------------------------------------- function funct_rnd2pwr_of_2 (input_value : integer) return integer is Variable temp_pwr2 : Integer := 128; begin if (input_value <= 128) then temp_pwr2 := 128; elsif (input_value <= 256) then temp_pwr2 := 256; elsif (input_value <= 512) then temp_pwr2 := 512; elsif (input_value <= 1024) then temp_pwr2 := 1024; elsif (input_value <= 2048) then temp_pwr2 := 2048; elsif (input_value <= 4096) then temp_pwr2 := 4096; else temp_pwr2 := 8192; end if; Return (temp_pwr2); end function funct_rnd2pwr_of_2; ------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_need_realigner -- -- Function Description: -- Determines if the Realigner module needs to be included. -- ------------------------------------------------------------------- function funct_need_realigner (indet_btt_enabled : integer; dre_included : integer; gp_sf_included : integer) return integer is Variable temp_val : Integer := 0; begin If ((indet_btt_enabled = 1) or (dre_included = 1) or (gp_sf_included = 1)) Then temp_val := 1; else temp_val := 0; End if; Return (temp_val); end function funct_need_realigner; ------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_sf_offset_width -- -- Function Description: -- This function calculates the address offset width needed by -- the GP Store and Forward module with data packing. -- ------------------------------------------------------------------- function funct_get_sf_offset_width (mmap_dwidth : integer; stream_dwidth : integer) return integer is Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth; Variable fvar_temp_offset_width : Integer := 1; begin case FCONST_WIDTH_RATIO is when 1 => fvar_temp_offset_width := 1; when 2 => fvar_temp_offset_width := 1; when 4 => fvar_temp_offset_width := 2; when 8 => fvar_temp_offset_width := 3; when 16 => fvar_temp_offset_width := 4; when 32 => fvar_temp_offset_width := 5; when 64 => fvar_temp_offset_width := 6; when others => fvar_temp_offset_width := 7; end case; Return (fvar_temp_offset_width); end function funct_get_sf_offset_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_stream_width2use -- -- Function Description: -- This function calculates the Stream width to use for S2MM -- modules downstream from the upsizing Store and Forward. If -- Store and forward is present, then the effective Stream width -- is the MMAP data width. If no Store and Forward then the Stream -- width is the input Stream width from the User. -- ------------------------------------------------------------------- function funct_get_stream_width2use (mmap_data_width : integer; stream_data_width : integer; sf_enabled : integer) return integer is Variable fvar_temp_width : Integer := 32; begin If (sf_enabled > 0) Then fvar_temp_width := mmap_data_width; Else fvar_temp_width := stream_data_width; End if; Return (fvar_temp_width); end function funct_get_stream_width2use; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_bytes_per_dbeat -- -- Function Description: -- This function calculates the number of bytes transfered per -- databeat on the MMap AXI4 Write Data Channel by the S2MM. The -- value is based on input parameterization of included functions -- in the S2MM block. -- ------------------------------------------------------------------- function funct_get_bytes_per_dbeat (ibtt_enabled : integer ; gpsf_enabled : integer ; stream_dwidth : integer ; mmap_dwidth : integer ) return integer is Variable fvar_temp_bytes_per_xfer : Integer := 4; begin If (ibtt_enabled > 0 or gpsf_enabled > 0) Then -- transfers will be upsized to mmap data width fvar_temp_bytes_per_xfer := mmap_dwidth/8; Else -- transfers will be in stream data widths (may be narrow transfers on mmap) fvar_temp_bytes_per_xfer := stream_dwidth/8; End if; Return (fvar_temp_bytes_per_xfer); end function funct_get_bytes_per_dbeat; -- Constant Declarations ---------------------------------------- Constant SF_ENABLED : integer := C_INCLUDE_S2MM_GP_SF + C_S2MM_SUPPORT_INDET_BTT; Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_S2MM_MDATA_WIDTH, C_S2MM_SDATA_WIDTH, SF_ENABLED); Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant IS_NOT_MM2S : integer range 0 to 1 := 0; Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID; Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH; Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH; Constant S2MM_MDATA_WIDTH : integer range 32 to 1024 := C_S2MM_MDATA_WIDTH; Constant S2MM_SDATA_WIDTH : integer range 8 to 1024 := C_S2MM_SDATA_WIDTH; Constant S2MM_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH; Constant S2MM_CMD_WIDTH : integer := (S2MM_TAG_WIDTH+S2MM_ADDR_WIDTH+32); Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := C_INCLUDE_S2MM_STSFIFO; Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH; Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC; Constant S2MM_BURST_SIZE : integer range 2 to 256 := C_S2MM_BURST_SIZE; Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH); Constant S2MM_BTT_USED : integer range 8 to 23 := C_S2MM_BTT_USED; Constant BITS_PER_BYTE : integer := 8; Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_S2MM_DRE, S2MM_SDATA_WIDTH); Constant DRE_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant S2MM_DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_S2MM_DRE, S2MM_SDATA_WIDTH); Constant DRE_SUPPORT_SCATTER : integer range 0 to 1 := 1; Constant ENABLE_INDET_BTT_SF : integer range 0 to 1 := C_S2MM_SUPPORT_INDET_BTT; Constant ENABLE_GP_SF : integer range 0 to 1 := C_INCLUDE_S2MM_GP_SF ; Constant BYTES_PER_MMAP_DBEAT : integer := funct_get_bytes_per_dbeat(ENABLE_INDET_BTT_SF , ENABLE_GP_SF , S2MM_SDATA_WIDTH , S2MM_MDATA_WIDTH); Constant MAX_BYTES_PER_BURST : integer := BYTES_PER_MMAP_DBEATS2MM_BURST_SIZE; Constant IBTT_XFER_BYTES_WIDTH : integer := get_bits_needed(MAX_BYTES_PER_BURST); Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2; -- 2 added for going -- full thresholding -- in WSC Constant WSC_STATUS_WIDTH : integer range 8 to 32 := funct_set_status_width(ENABLE_INDET_BTT_SF); Constant WSC_BYTES_RCVD_WIDTH : integer range 8 to 32 := S2MM_BTT_USED; Constant ADD_REALIGNER : integer := funct_need_realigner(ENABLE_INDET_BTT_SF , INCLUDE_S2MM_DRE , ENABLE_GP_SF); -- Calculates the minimum needed depth of the GP Store and Forward FIFO -- based on the S2MM pipeline depth and the max allowed Burst length Constant PIPEDEPTH_BURST_LEN_PROD : integer := (ADDR_CNTL_FIFO_DEPTH+2) * S2MM_BURST_SIZE; -- Assigns the depth of the optional GP Store and Forward FIFO to the nearest -- power of 2 Constant SF_FIFO_DEPTH : integer range 128 to 8192 := funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD); -- Calculate the width of the Store and Forward Starting Address Offset bus Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(S2MM_MDATA_WIDTH, S2MM_SDATA_WIDTH); -- Signal Declarations ------------------------------------------ signal sig_cmd_stat_rst_user : std_logic := '0'; signal sig_cmd_stat_rst_int : std_logic := '0'; signal sig_mmap_rst : std_logic := '0'; signal sig_stream_rst : std_logic := '0'; signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0'); signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd2mstr_cmd_valid : std_logic := '0'; signal sig_mst2cmd_cmd_ready : std_logic := '0'; signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0'); signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_cmd_cmplt : std_logic := '0'; signal sig_mstr2addr_calc_error : std_logic := '0'; signal sig_mstr2addr_cmd_valid : std_logic := '0'; signal sig_addr2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_drr : std_logic := '0'; signal sig_mstr2data_eof : std_logic := '0'; signal sig_mstr2data_sequential : std_logic := '0'; signal sig_mstr2data_calc_error : std_logic := '0'; signal sig_mstr2data_cmd_last : std_logic := '0'; signal sig_mstr2data_cmd_valid : std_logic := '0'; signal sig_data2mstr_cmd_ready : std_logic := '0'; signal sig_addr2data_addr_posted : std_logic := '0'; signal sig_data2addr_data_rdy : std_logic := '0'; signal sig_data2all_tlast_error : std_logic := '0'; signal sig_data2all_dcntlr_halted : std_logic := '0'; signal sig_addr2wsc_calc_error : std_logic := '0'; signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0'; signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0'); signal sig_data2wsc_cmd_empty : std_logic := '0'; signal sig_data2wsc_calc_err : std_logic := '0'; signal sig_data2wsc_cmd_cmplt : std_logic := '0'; signal sig_data2wsc_last_err : std_logic := '0'; signal sig_calc2dm_calc_err : std_logic := '0'; signal sig_wsc2stat_status : std_logic_vector(WSC_STATUS_WIDTH-1 downto 0) := (others => '0'); signal sig_stat2wsc_status_ready : std_logic := '0'; signal sig_wsc2stat_status_valid : std_logic := '0'; signal sig_wsc2mstr_halt_pipe : std_logic := '0'; signal sig_data2wsc_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_wvalid : std_logic := '0'; signal sig_skid2data_wready : std_logic := '0'; signal sig_data2skid_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_data2skid_wlast : std_logic := '0'; signal sig_skid2axi_wvalid : std_logic := '0'; signal sig_axi2skid_wready : std_logic := '0'; signal sig_skid2axi_wdata : std_logic_vector(S2MM_MDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_skid2axi_wstrb : std_logic_vector((S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_skid2axi_wlast : std_logic := '0'; signal sig_data2wsc_sof : std_logic := '0'; signal sig_data2wsc_eof : std_logic := '0'; signal sig_data2wsc_valid : std_logic := '0'; signal sig_wsc2data_ready : std_logic := '0'; signal sig_data2wsc_eop : std_logic := '0'; signal sig_data2wsc_bytes_rcvd : std_logic_vector(WSC_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0'); signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_sf2pcc_xfer_valid : std_logic := '0'; signal sig_pcc2sf_xfer_ready : std_logic := '0'; signal sig_sf2pcc_cmd_cmplt : std_logic := '0'; signal sig_sf2pcc_packet_eop : std_logic := '0'; signal sig_sf2pcc_xfer_bytes : std_logic_vector(IBTT_XFER_BYTES_WIDTH-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tvalid : std_logic := '0'; signal sig_wdc2ibtt_tready : std_logic := '0'; signal sig_ibtt2wdc_tdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tlast : std_logic := '0'; signal sig_ibtt2wdc_eop : std_logic := '0'; signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(7 downto 0) := (others => '0'); signal sig_dre2ibtt_tvalid : std_logic := '0'; signal sig_ibtt2dre_tready : std_logic := '0'; signal sig_dre2ibtt_tdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_dre2ibtt_tstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_dre2ibtt_tlast : std_logic := '0'; signal sig_dre2ibtt_eop : std_logic := '0'; signal sig_dre2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2dre_cmd_valid : std_logic := '0'; signal sig_mstr2dre_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_dre_src_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_dre_dest_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_btt : std_logic_vector(S2MM_BTT_USED-1 downto 0) := (others => '0'); signal sig_mstr2dre_drr : std_logic := '0'; signal sig_mstr2dre_eof : std_logic := '0'; signal sig_mstr2dre_cmd_cmplt : std_logic := '0'; signal sig_mstr2dre_calc_error : std_logic := '0'; signal sig_realign2wdc_eop_error : std_logic := '0'; signal sig_dre2all_halted : std_logic := '0'; signal sig_rst2all_stop_request : std_logic := '0'; signal sig_data2rst_stop_cmplt : std_logic := '0'; signal sig_addr2rst_stop_cmplt : std_logic := '0'; signal sig_data2addr_stop_req : std_logic := '0'; signal sig_wsc2rst_stop_cmplt : std_logic := '0'; signal sig_data2skid_halt : std_logic := '0'; signal skid2dre_wvalid : std_logic := '0'; signal dre2skid_wready : std_logic := '0'; signal skid2dre_wdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0'); signal skid2dre_wstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal skid2dre_wlast : std_logic := '0'; signal sig_s2mm_allow_addr_req : std_logic := '0'; signal sig_ok_to_post_wr_addr : std_logic := '0'; signal sig_s2mm_addr_req_posted : std_logic := '0'; signal sig_s2mm_wr_xfer_cmplt : std_logic := '0'; signal sig_s2mm_ld_nxt_len : std_logic := '0'; signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_ibtt2wdc_error : std_logic := '0'; signal sig_sf_strt_addr_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_cache2mstr_command : std_logic_vector (7 downto 0); signal s2mm_awcache_int : std_logic_vector (3 downto 0); signal s2mm_awuser_int : std_logic_vector (3 downto 0); begin --(architecture implementation) -- Debug/Test Port Assignments s2mm_dbg_data <= sig_dbg_data_mux_out; -- Note that only the s2mm_dbg_sel(0) is used at this time sig_dbg_data_mux_out <= sig_dbg_data_1 When (s2mm_dbg_sel(0) = '1') else sig_dbg_data_0 ; sig_dbg_data_0 <= X"CAFE1111" ; -- 32 bit Constant indicating S2MM FULL type sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ; sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ; sig_dbg_data_1(2) <= sig_mmap_rst ; sig_dbg_data_1(3) <= sig_stream_rst ; sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ; sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ; sig_dbg_data_1(6) <= sig_stat2wsc_status_ready; sig_dbg_data_1(7) <= sig_wsc2stat_status_valid; sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error --sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADD_DEBUG_EOP -- -- If Generate Description: -- -- This IfGen adds in the EOP status marker to the debug -- vector data when Indet BTT Store and Forward is enabled. -- ------------------------------------------------------------ GEN_ADD_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 1) generate begin sig_dbg_data_1(19) <= sig_wsc2stat_status(31) ; -- EOP Marker end generate GEN_ADD_DEBUG_EOP; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_DEBUG_EOP -- -- If Generate Description: -- -- This IfGen zeros the debug vector bit used for the EOP -- status marker when Indet BTT Store and Forward is not -- enabled. -- ------------------------------------------------------------ GEN_NO_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 0) generate begin sig_dbg_data_1(19) <= '0' ; -- EOP Marker end generate GEN_NO_DEBUG_EOP; ---- End of Debug/Test Support -------------------------------- -- Assign the Address posting control outputs s2mm_addr_req_posted <= sig_s2mm_addr_req_posted ; s2mm_wr_xfer_cmplt <= sig_s2mm_wr_xfer_cmplt ; s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len ; s2mm_wr_len <= sig_s2mm_wr_len ; -- Write Data Channel I/O s2mm_wvalid <= sig_skid2axi_wvalid; sig_axi2skid_wready <= s2mm_wready ; s2mm_wdata <= sig_skid2axi_wdata ; s2mm_wlast <= sig_skid2axi_wlast ; GEN_S2MM_TKEEP_ENABLE2 : if C_ENABLE_S2MM_TKEEP = 1 generate begin s2mm_wstrb <= sig_skid2axi_wstrb ; end generate GEN_S2MM_TKEEP_ENABLE2; GEN_S2MM_TKEEP_DISABLE2 : if C_ENABLE_S2MM_TKEEP = 0 generate begin s2mm_wstrb <= (others => '1'); end generate GEN_S2MM_TKEEP_DISABLE2; GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate begin -- Cache signal tie-off s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96); end generate GEN_CACHE; GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate begin -- Cache signal tie-off s2mm_awcache <= s2mm_awcache_int; -- pre Interface-X guidelines for Masters s2mm_awuser <= s2mm_awuser_int; -- pre Interface-X guidelines for Masters sig_s2mm_cache_data <= s2mm_cmd_wdata(79+(C_S2MM_ADDR_WIDTH-32) downto 72+(C_S2MM_ADDR_WIDTH-32)); -- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96); end generate GEN_CACHE2; -- Internal error output discrete s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error; -- Rip the used portion of the Command Interface Command Data -- and throw away the padding sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0); ------------------------------------------------------------ -- Instance: I_RESET -- -- Description: -- Reset Block -- ------------------------------------------------------------ I_RESET : entity axi_datamover_v5_1_10.axi_datamover_reset generic map ( C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ) port map ( primary_aclk => s2mm_aclk , primary_aresetn => s2mm_aresetn , secondary_awclk => s2mm_cmdsts_awclk , secondary_aresetn => s2mm_cmdsts_aresetn , halt_req => s2mm_halt , halt_cmplt => s2mm_halt_cmplt , flush_stop_request => sig_rst2all_stop_request , data_cntlr_stopped => sig_data2rst_stop_cmplt , addr_cntlr_stopped => sig_addr2rst_stop_cmplt , aux1_stopped => sig_wsc2rst_stop_cmplt , aux2_stopped => LOGIC_HIGH , cmd_stat_rst_user => sig_cmd_stat_rst_user , cmd_stat_rst_int => sig_cmd_stat_rst_int , mmap_rst => sig_mmap_rst , stream_rst => sig_stream_rst ); ------------------------------------------------------------ -- Instance: I_CMD_STATUS -- -- Description: -- Command and Status Interface Block -- ------------------------------------------------------------ I_CMD_STATUS : entity axi_datamover_v5_1_10.axi_datamover_cmd_status generic map ( C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO , C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH , C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_STS_WIDTH => WSC_STATUS_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , secondary_awclk => s2mm_cmdsts_awclk , user_reset => sig_cmd_stat_rst_user , internal_reset => sig_cmd_stat_rst_int , cmd_wvalid => s2mm_cmd_wvalid , cmd_wready => s2mm_cmd_wready , cmd_wdata => sig_s2mm_cmd_wdata , cache_data => sig_s2mm_cache_data , sts_wvalid => s2mm_sts_wvalid , sts_wready => s2mm_sts_wready , sts_wdata => s2mm_sts_wdata , sts_wstrb => s2mm_sts_wstrb , sts_wlast => s2mm_sts_wlast , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid , cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready , mstr2stat_status => sig_wsc2stat_status , stat2mstr_status_ready => sig_stat2wsc_status_ready , mst2stst_status_valid => sig_wsc2stat_status_valid ); ------------------------------------------------------------ -- Instance: I_WR_STATUS_CNTLR -- -- Description: -- Write Status Controller Block -- ------------------------------------------------------------ I_WR_STATUS_CNTLR : entity axi_datamover_v5_1_10.axi_datamover_wr_status_cntl generic map ( C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH , C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH , C_STS_WIDTH => WSC_STATUS_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , rst2wsc_stop_request => sig_rst2all_stop_request , wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt , addr2wsc_addr_posted => sig_addr2data_addr_posted , s2mm_bresp => s2mm_bresp , s2mm_bvalid => s2mm_bvalid , s2mm_bready => s2mm_bready , calc2wsc_calc_error => sig_calc2dm_calc_err , addr2wsc_calc_error => sig_addr2wsc_calc_error , addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty , data2wsc_tag => sig_data2wsc_tag , data2wsc_calc_error => sig_data2wsc_calc_err , data2wsc_last_error => sig_data2wsc_last_err , data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt , data2wsc_valid => sig_data2wsc_valid , wsc2data_ready => sig_wsc2data_ready , data2wsc_eop => sig_data2wsc_eop , data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd , wsc2stat_status => sig_wsc2stat_status , stat2wsc_status_ready => sig_stat2wsc_status_ready , wsc2stat_status_valid => sig_wsc2stat_status_valid , wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe ); ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_PCC -- -- If Generate Description: -- Include the normal Predictive Command Calculator function, -- Store and Forward is not an included feature. -- -- ------------------------------------------------------------ GEN_INCLUDE_PCC : if (ENABLE_INDET_BTT_SF = 0) generate begin ------------------------------------------------------------ -- Instance: I_MSTR_PCC -- -- Description: -- Predictive Command Calculator Block -- ------------------------------------------------------------ I_MSTR_PCC : entity axi_datamover_v5_1_10.axi_datamover_pcc generic map ( C_IS_MM2S => IS_NOT_MM2S , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_BTT_USED => S2MM_BTT_USED , C_SUPPORT_INDET_BTT => ENABLE_INDET_BTT_SF , C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ) port map ( -- Clock input primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , mstr2data_dre_src_align => open , mstr2data_dre_dest_align => open , calc_error => sig_calc2dm_calc_err , dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset ); end generate GEN_INCLUDE_PCC; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_IBTTCC -- -- If Generate Description: -- Include the Indeterminate BTT Command Calculator function, -- Store and Forward is enabled in the S2MM. -- -- ------------------------------------------------------------ GEN_INCLUDE_IBTTCC : if (ENABLE_INDET_BTT_SF = 1) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_MSTR_SFCC -- -- Description: -- Instantiates the Store and Forward Command Calculator -- Block. -- ------------------------------------------------------------ I_S2MM_MSTR_IBTTCC : entity axi_datamover_v5_1_10.axi_datamover_ibttcc generic map ( C_SF_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_BTT_USED => S2MM_BTT_USED , C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ) port map ( -- Clock input primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid , pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready , sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt , sf2pcc_packet_eop => sig_sf2pcc_packet_eop , sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , calc_error => sig_calc2dm_calc_err , dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset ); end generate GEN_INCLUDE_IBTTCC; ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate begin ------------------------------------------------------------ -- Instance: I_S2MM_STRM_SKID_BUF -- -- Description: -- Instance for the S2MM Skid Buffer which provides for -- registerd Slave Stream inputs and supports bi-dir -- throttling. -- ------------------------------------------------------------ I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => S2MM_SDATA_WIDTH ) port map ( -- System Ports aclk => s2mm_aclk , arst => sig_mmap_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => sig_data2skid_halt , -- Slave Side (Stream Data Input) s_valid => s2mm_strm_wvalid , s_ready => s2mm_strm_wready , s_data => s2mm_strm_wdata , s_strb => s2mm_strm_wstrb , s_last => s2mm_strm_wlast , -- Master Side (Stream Data Output m_valid => skid2dre_wvalid , m_ready => dre2skid_wready , m_data => skid2dre_wdata , m_strb => skid2dre_wstrb , m_last => skid2dre_wlast ); end generate ENABLE_AXIS_SKID; DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate begin skid2dre_wvalid <= s2mm_strm_wvalid; s2mm_strm_wready <= dre2skid_wready; skid2dre_wdata <= s2mm_strm_wdata; skid2dre_wstrb <= s2mm_strm_wstrb; skid2dre_wlast <= s2mm_strm_wlast; end generate DISABLE_AXIS_SKID; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_REALIGNER -- -- If Generate Description: -- Omit the S2MM Realignment Engine -- -- ------------------------------------------------------------ GEN_NO_REALIGNER : if (ADD_REALIGNER = 0) generate begin -- Set to Always ready for DRE to PCC Command Interface sig_dre2mstr_cmd_ready <= LOGIC_HIGH; -- Without DRE and Scatter, the end of packet is the TLAST --sig_dre2ibtt_eop <= skid2dre_wlast ; sig_dre2ibtt_eop <= sig_dre2ibtt_tlast ; -- use skid buffered version -- Cant't detect undrrun/overrun here sig_realign2wdc_eop_error <= '0'; ENABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '1' generate begin ------------------------------------------------------------ -- Instance: I_NO_REALIGN_SKID_BUF -- -- Description: -- Instance for a Skid Buffer which provides for -- Fmax timing improvement between the Null Absorber and -- the Write Data controller when the Realigner is not -- present (no DRE and no Store and Forward case). -- ------------------------------------------------------------ I_NO_REALIGN_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => S2MM_SDATA_WIDTH ) port map ( -- System Ports aclk => s2mm_aclk , arst => sig_mmap_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => LOGIC_LOW , -- Slave Side (Null Absorber Input) s_valid => skid2dre_wvalid , s_ready => dre2skid_wready , s_data => skid2dre_wdata , s_strb => skid2dre_wstrb , s_last => skid2dre_wlast , -- Master Side (Stream Data Output to WData Cntlr) m_valid => sig_dre2ibtt_tvalid , m_ready => sig_ibtt2dre_tready , m_data => sig_dre2ibtt_tdata , m_strb => sig_dre2ibtt_tstrb , m_last => sig_dre2ibtt_tlast ); end generate ENABLE_NOREALIGNER_SKID; DISABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '0' generate begin sig_dre2ibtt_tvalid <= skid2dre_wvalid; dre2skid_wready <= sig_ibtt2dre_tready; sig_dre2ibtt_tdata <= skid2dre_wdata; sig_dre2ibtt_tstrb <= skid2dre_wstrb; sig_dre2ibtt_tlast <= skid2dre_wlast; end generate DISABLE_NOREALIGNER_SKID; end generate GEN_NO_REALIGNER; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_REALIGNER -- -- If Generate Description: -- Include the S2MM realigner Module. It hosts the S2MM DRE -- and the Scatter Block. -- -- Note that the General Purpose Store and Forward Module -- needs the Scatter function to detect input overrun and -- underrun events on the AXI Stream input. Thus the Realigner -- is included whenever the GP Store and Forward is enabled. -- ------------------------------------------------------------ GEN_INCLUDE_REALIGNER : if (ADD_REALIGNER = 1) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_REALIGNER -- -- Description: -- Instance for the S2MM Data Realignment Module. -- ------------------------------------------------------------ I_S2MM_REALIGNER : entity axi_datamover_v5_1_10.axi_datamover_s2mm_realign generic map ( C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_INCLUDE_DRE => INCLUDE_S2MM_DRE , C_DRE_CNTL_FIFO_DEPTH => DRE_CNTL_FIFO_DEPTH , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SUPPORT_SCATTER => DRE_SUPPORT_SCATTER , C_BTT_USED => S2MM_BTT_USED , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , -- Write Data Controller or Store and Forward I/O ------- wdc2dre_wready => sig_ibtt2dre_tready , dre2wdc_wvalid => sig_dre2ibtt_tvalid , dre2wdc_wdata => sig_dre2ibtt_tdata , dre2wdc_wstrb => sig_dre2ibtt_tstrb , dre2wdc_wlast => sig_dre2ibtt_tlast , dre2wdc_eop => sig_dre2ibtt_eop , -- Starting offset output ------------------------------- dre2sf_strt_offset => sig_sf_strt_addr_offset , -- AXI Slave Stream In ----------------------------------- s2mm_strm_wready => dre2skid_wready , s2mm_strm_wvalid => skid2dre_wvalid , s2mm_strm_wdata => skid2dre_wdata , s2mm_strm_wstrb => skid2dre_wstrb , s2mm_strm_wlast => skid2dre_wlast , -- Command Calculator Interface -------------------------- dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset , -- Premature TLAST assertion error flag dre2all_tlast_error => sig_realign2wdc_eop_error , -- DRE Halted Status dre2all_halted => sig_dre2all_halted ); end generate GEN_INCLUDE_REALIGNER; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ENABLE_INDET_BTT_SF -- -- If Generate Description: -- Include the Indeterminate BTT Logic with specialized -- Store and Forward function, This also requires the -- Scatter Engine in the Realigner module. -- -- ------------------------------------------------------------ GEN_ENABLE_INDET_BTT_SF : if (ENABLE_INDET_BTT_SF = 1) generate begin -- Pass the Realigner EOP error through sig_ibtt2wdc_error <= sig_realign2wdc_eop_error; -- Use only external address posting enable sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ; ------------------------------------------------------------ -- Instance: I_INDET_BTT -- -- Description: -- Instance for the Indeterminate BTT with Store and Forward -- module. -- ------------------------------------------------------------ I_INDET_BTT : entity axi_datamover_v5_1_10.axi_datamover_indet_btt generic map ( C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , C_IBTT_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH , C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_ENABLE_DRE => INCLUDE_S2MM_DRE , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , ibtt2wdc_stbs_asserted => sig_ibtt2wdc_stbs_asserted, ibtt2wdc_eop => sig_ibtt2wdc_eop , ibtt2wdc_tdata => sig_ibtt2wdc_tdata , ibtt2wdc_tstrb => sig_ibtt2wdc_tstrb , ibtt2wdc_tlast => sig_ibtt2wdc_tlast , ibtt2wdc_tvalid => sig_ibtt2wdc_tvalid , wdc2ibtt_tready => sig_wdc2ibtt_tready , dre2ibtt_tvalid => sig_dre2ibtt_tvalid , ibtt2dre_tready => sig_ibtt2dre_tready , dre2ibtt_tdata => sig_dre2ibtt_tdata , dre2ibtt_tstrb => sig_dre2ibtt_tstrb , dre2ibtt_tlast => sig_dre2ibtt_tlast , dre2ibtt_eop => sig_dre2ibtt_eop , dre2ibtt_strt_addr_offset => sig_sf_strt_addr_offset , sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid , pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready , sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt , sf2pcc_packet_eop => sig_sf2pcc_packet_eop , sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes ); end generate GEN_ENABLE_INDET_BTT_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_SF -- -- If Generate Description: -- Bypasses any store and Forward functions. -- -- ------------------------------------------------------------ GEN_NO_SF : if (ENABLE_INDET_BTT_SF = 0 and ENABLE_GP_SF = 0) generate begin -- Use only external address posting enable sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ; -- Housekeep unused signal in this case sig_ok_to_post_wr_addr <= '0' ; -- SFCC Interface Signals that are not used sig_pcc2sf_xfer_ready <= '0' ; sig_sf2pcc_xfer_valid <= '0' ; sig_sf2pcc_cmd_cmplt <= '0' ; sig_sf2pcc_packet_eop <= '0' ; sig_sf2pcc_xfer_bytes <= (others => '0') ; -- Just pass DRE signals through sig_ibtt2dre_tready <= sig_wdc2ibtt_tready ; sig_ibtt2wdc_tvalid <= sig_dre2ibtt_tvalid ; sig_ibtt2wdc_tdata <= sig_dre2ibtt_tdata ; sig_ibtt2wdc_tstrb <= sig_dre2ibtt_tstrb ; sig_ibtt2wdc_tlast <= sig_dre2ibtt_tlast ; sig_ibtt2wdc_eop <= sig_dre2ibtt_eop ; sig_ibtt2wdc_stbs_asserted <= (others => '0') ; -- Pass the Realigner EOP error through sig_ibtt2wdc_error <= sig_realign2wdc_eop_error; end generate GEN_NO_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_GP_SF -- -- If Generate Description: -- Include the General Purpose Store and Forward module. -- This If Generate can only be enabled when -- Indeterminate BTT mode is not enabled. The General Purpose -- Store and Forward is instantiated in place of the Indet -- BTT Store and Forward. -- ------------------------------------------------------------ GEN_INCLUDE_GP_SF : if (ENABLE_INDET_BTT_SF = 0 and ENABLE_GP_SF = 1) generate begin -- Merge the external address posting control with the -- SF address posting control. sig_s2mm_allow_addr_req <= s2mm_allow_addr_req and sig_ok_to_post_wr_addr ; -- Zero these out since Indet BTT is not enabled, they -- are only used by the WDC in that mode sig_ibtt2wdc_stbs_asserted <= (others => '0') ; sig_ibtt2wdc_eop <= '0' ; -- SFCC Interface Signals that are not used sig_pcc2sf_xfer_ready <= '0' ; sig_sf2pcc_xfer_valid <= '0' ; sig_sf2pcc_cmd_cmplt <= '0' ; sig_sf2pcc_packet_eop <= '0' ; sig_sf2pcc_xfer_bytes <= (others => '0') ; ------------------------------------------------------------ -- Instance: I_S2MM_GP_SF -- -- Description: -- Instance for the S2MM (Write) General Purpose Store and -- Forward Module. This module can only be enabled when -- Indeterminate BTT mode is not enabled. It is connected -- in place of the IBTT Module when GP SF is enabled. -- ------------------------------------------------------------ I_S2MM_GP_SF : entity axi_datamover_v5_1_10.axi_datamover_wr_sf generic map ( C_WR_ADDR_PIPE_DEPTH => ADDR_CNTL_FIFO_DEPTH , C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset inputs ----------------------------- aclk => s2mm_aclk , reset => sig_mmap_rst , -- Slave Stream Input -------------------------------- sf2sin_tready => sig_ibtt2dre_tready , sin2sf_tvalid => sig_dre2ibtt_tvalid , sin2sf_tdata => sig_dre2ibtt_tdata , sin2sf_tkeep => sig_dre2ibtt_tstrb , sin2sf_tlast => sig_dre2ibtt_tlast , sin2sf_error => sig_realign2wdc_eop_error , -- Starting Address Offset Input --------------------- sin2sf_strt_addr_offset => sig_sf_strt_addr_offset , -- DataMover Write Side Address Pipelining Control Interface -------- ok_to_post_wr_addr => sig_ok_to_post_wr_addr , wr_addr_posted => sig_s2mm_addr_req_posted , wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt , wr_ld_nxt_len => sig_s2mm_ld_nxt_len , wr_len => sig_s2mm_wr_len , -- Write Side Stream Out to DataMover S2MM ------------- sout2sf_tready => sig_wdc2ibtt_tready , sf2sout_tvalid => sig_ibtt2wdc_tvalid , sf2sout_tdata => sig_ibtt2wdc_tdata , sf2sout_tkeep => sig_ibtt2wdc_tstrb , sf2sout_tlast => sig_ibtt2wdc_tlast , sf2sout_error => sig_ibtt2wdc_error ); end generate GEN_INCLUDE_GP_SF; ------------------------------------------------------------ -- Instance: I_ADDR_CNTL -- -- Description: -- Address Controller Block -- ------------------------------------------------------------ I_ADDR_CNTL : entity axi_datamover_v5_1_10.axi_datamover_addr_cntl generic map ( C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_ADDR_ID => S2MM_AWID_VALUE , C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , addr2axi_aid => s2mm_awid , addr2axi_aaddr => s2mm_awaddr , addr2axi_alen => s2mm_awlen , addr2axi_asize => s2mm_awsize , addr2axi_aburst => s2mm_awburst , addr2axi_aprot => s2mm_awprot , addr2axi_avalid => s2mm_awvalid , addr2axi_acache => s2mm_awcache_int , addr2axi_auser => s2mm_awuser_int , axi2addr_aready => s2mm_awready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , -- mstr2addr_cache_info => sig_cache2mstr_command , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt , allow_addr_req => sig_s2mm_allow_addr_req , addr_req_posted => sig_s2mm_addr_req_posted , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => sig_data2addr_data_rdy , data2addr_stop_req => sig_data2addr_stop_req , addr2stat_calc_error => sig_addr2wsc_calc_error , addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty ); ------------------------------------------------------------ -- Instance: I_WR_DATA_CNTL -- -- Description: -- Write Data Controller Block -- ------------------------------------------------------------ I_WR_DATA_CNTL : entity axi_datamover_v5_1_10.axi_datamover_wrdata_cntl generic map ( C_REALIGNER_INCLUDED => ADD_REALIGNER , C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , rst2data_stop_request => sig_rst2all_stop_request , data2addr_stop_req => sig_data2addr_stop_req , data2rst_stop_cmplt => sig_data2rst_stop_cmplt , wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt , s2mm_ld_nxt_len => sig_s2mm_ld_nxt_len , s2mm_wr_len => sig_s2mm_wr_len , data2skid_saddr_lsb => sig_data2skid_addr_lsb , data2skid_wdata => sig_data2skid_wdata , data2skid_wstrb => sig_data2skid_wstrb , data2skid_wlast => sig_data2skid_wlast , data2skid_wvalid => sig_data2skid_wvalid , skid2data_wready => sig_skid2data_wready , s2mm_strm_wvalid => sig_ibtt2wdc_tvalid , s2mm_strm_wready => sig_wdc2ibtt_tready , s2mm_strm_wdata => sig_ibtt2wdc_tdata , s2mm_strm_wstrb => sig_ibtt2wdc_tstrb , s2mm_strm_wlast => sig_ibtt2wdc_tlast , s2mm_strm_eop => sig_ibtt2wdc_eop , s2mm_stbs_asserted => sig_ibtt2wdc_stbs_asserted, realign2wdc_eop_error => sig_ibtt2wdc_error , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => sig_data2addr_data_rdy , data2all_tlast_error => sig_data2all_tlast_error , data2all_dcntlr_halted => sig_data2all_dcntlr_halted, data2skid_halt => sig_data2skid_halt , data2wsc_tag => sig_data2wsc_tag , data2wsc_calc_err => sig_data2wsc_calc_err , data2wsc_last_err => sig_data2wsc_last_err , data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt , wsc2data_ready => sig_wsc2data_ready , data2wsc_valid => sig_data2wsc_valid , data2wsc_eop => sig_data2wsc_eop , data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd , wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe ); --ENABLE_AXIMMAP_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate --begin ------------------------------------------------------------ -- Instance: I_S2MM_MMAP_SKID_BUF -- -- Description: -- Instance for the S2MM Skid Buffer which provides for -- registered outputs and supports bi-dir throttling. -- -- This Module also provides Write Data Bus Mirroring and WSTRB -- Demuxing to match a narrow Stream to a wider MMap Write -- Channel. By doing this in the skid buffer, the resource -- utilization of the skid buffer can be minimized by only -- having to buffer/mux the Stream data width, not the MMap -- Data width. -- ------------------------------------------------------------ I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_skid2mm_buf generic map ( C_MDATA_WIDTH => S2MM_MDATA_WIDTH , C_SDATA_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH ) port map ( -- System Ports ACLK => s2mm_aclk , ARST => sig_stream_rst , -- Slave Side (Wr Data Controller Input Side ) S_ADDR_LSB => sig_data2skid_addr_lsb, S_VALID => sig_data2skid_wvalid , S_READY => sig_skid2data_wready , S_Data => sig_data2skid_wdata , S_STRB => sig_data2skid_wstrb , S_Last => sig_data2skid_wlast , -- Master Side (MMap Write Data Output Side) M_VALID => sig_skid2axi_wvalid , M_READY => sig_axi2skid_wready , M_Data => sig_skid2axi_wdata , M_STRB => sig_skid2axi_wstrb , M_Last => sig_skid2axi_wlast ); --end generate ENABLE_AXIMMAP_SKID; end implementation;
------------------------------------------------------------------------------- -- axi_datamover_s2mm_full_wrap.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_s2mm_full_wrap.vhd -- -- Description: -- This file implements the DataMover S2MM FULL Wrapper. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all ; -- axi_datamover Library Modules library axi_datamover_v5_1_10; use axi_datamover_v5_1_10.axi_datamover_reset ; use axi_datamover_v5_1_10.axi_datamover_cmd_status ; use axi_datamover_v5_1_10.axi_datamover_pcc ; use axi_datamover_v5_1_10.axi_datamover_ibttcc ; use axi_datamover_v5_1_10.axi_datamover_indet_btt ; use axi_datamover_v5_1_10.axi_datamover_s2mm_realign ; use axi_datamover_v5_1_10.axi_datamover_addr_cntl ; use axi_datamover_v5_1_10.axi_datamover_wrdata_cntl ; use axi_datamover_v5_1_10.axi_datamover_wr_status_cntl; Use axi_datamover_v5_1_10.axi_datamover_skid2mm_buf ; Use axi_datamover_v5_1_10.axi_datamover_skid_buf ; Use axi_datamover_v5_1_10.axi_datamover_wr_sf ; ------------------------------------------------------------------------------- entity axi_datamover_s2mm_full_wrap is generic ( C_INCLUDE_S2MM : Integer range 0 to 2 := 1; -- Specifies the type of S2MM function to include -- 0 = Omit S2MM functionality -- 1 = Full S2MM Functionality -- 2 = Lite S2MM functionality C_S2MM_AWID : Integer range 0 to 255 := 9; -- Specifies the constant value to output on -- the ARID output port C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the S2MM ID port C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the S2MM Master Stream Data -- Channel data bus C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit S2MM Status FIFO -- 1 = Include S2MM Status FIFO C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the S2MM Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0; -- Specifies if DRE is to be included in the S2MM function -- 0 = Omit DRE -- 1 = Include DRE C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the S2MM function C_S2MM_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the S2MM Command Interface C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0; -- Specifies if support for indeterminate packet lengths -- are to be received on the input Stream interface -- 0 = Omit support (User MUST transfer the exact number of -- bytes on the Stream interface as specified in the BTT -- field of the Corresponding DataMover Command) -- 1 = Include support for indeterminate packet lengths -- This causes FIFOs to be added and "Store and Forward" -- behavior of the S2MM function C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3; -- This parameter specifies the depth of the S2MM internal -- address pipeline queues in the Write Address Controller -- and the Write Data Controller. Increasing this value will -- allow more Write Addresses to be issued to the AXI4 Write -- Address Channel before transmission of the associated -- write data on the Write Data Channel. C_TAG_WIDTH : Integer range 1 to 8 := 4 ; -- Width of the TAG field C_INCLUDE_S2MM_GP_SF : Integer range 0 to 1 := 1 ; -- This parameter specifies the inclusion/omission of the -- S2MM (Write) General Purpose Store and Forward function -- 0 = Omit GP Store and Forward -- 1 = Include GP Store and Forward C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1; C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1; C_ENABLE_SKID_BUF : string := "11111"; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- S2MM Primary Clock and Reset inputs ---------------------------- s2mm_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- ------------------------------------------------------------------- -- S2MM Primary Reset input --------------------------------------- s2mm_aresetn : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------------- -- S2MM Halt request input control -------------------------------- s2mm_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- S2MM Halt Complete status flag -- s2mm_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------------------- -- S2MM Error discrete output ------------------------------------- s2mm_err : Out std_logic; -- -- Composite Error indication -- ------------------------------------------------------------------- -- Optional Command and Status Clock and Reset ------------------- -- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 -- -- s2mm_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- s2mm_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- ------------------------------------------------------------------ -- User Command Interface Ports (AXI Stream) ----------------------------------------------------- s2mm_cmd_wvalid : in std_logic; -- s2mm_cmd_wready : out std_logic; -- s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); -- -------------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) -------------------------------------------------------- s2mm_sts_wvalid : out std_logic; -- s2mm_sts_wready : in std_logic; -- s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT24)+8)-1 downto 0); -- s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT24)+8)/8)-1 downto 0); -- s2mm_sts_wlast : out std_logic; -- ---------------------------------------------------------------------------------------------------- -- Address posting controls --------------------------------------- s2mm_allow_addr_req : in std_logic; -- s2mm_addr_req_posted : out std_logic; -- s2mm_wr_xfer_cmplt : out std_logic; -- s2mm_ld_nxt_len : out std_logic; -- s2mm_wr_len : out std_logic_vector(7 downto 0); -- ------------------------------------------------------------------- -- S2MM AXI Address Channel I/O -------------------------------------- s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- s2mm_awlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- s2mm_awsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- s2mm_awburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- s2mm_awprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- s2mm_awcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel PROT output -- s2mm_awuser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel PROT output -- -- s2mm_awvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- s2mm_awready : in std_logic; -- -- AXI Address Channel READY input -- ----------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ----------- -- s2mm__awlock : out std_logic_vector(2 downto 0); -- -- s2mm__awcache : out std_logic_vector(4 downto 0); -- -- s2mm__awqos : out std_logic_vector(3 downto 0); -- -- s2mm__awregion : out std_logic_vector(3 downto 0); -- ----------------------------------------------------------------------- -- S2MM AXI MMap Write Data Channel I/O --------------------------------------------- s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); -- s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); -- s2mm_wlast : Out std_logic; -- s2mm_wvalid : Out std_logic; -- s2mm_wready : In std_logic; -- -------------------------------------------------------------------------------------- -- S2MM AXI MMap Write response Channel I/O ----------------------------------------- s2mm_bresp : In std_logic_vector(1 downto 0); -- s2mm_bvalid : In std_logic; -- s2mm_bready : Out std_logic; -- -------------------------------------------------------------------------------------- -- S2MM AXI Master Stream Channel I/O ----------------------------------------------- s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); -- s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); -- s2mm_strm_wlast : In std_logic; -- s2mm_strm_wvalid : In std_logic; -- s2mm_strm_wready : Out std_logic; -- -------------------------------------------------------------------------------------- -- Testing Support I/O ------------------------------------------ s2mm_dbg_sel : in std_logic_vector( 3 downto 0); -- s2mm_dbg_data : out std_logic_vector(31 downto 0) -- ----------------------------------------------------------------- ); end entity axi_datamover_s2mm_full_wrap; architecture implementation of axi_datamover_s2mm_full_wrap is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations ---------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: func_calc_wdemux_sel_bits -- -- Function Description: -- This function calculates the number of address bits needed for -- the Write Strobe demux select control. -- ------------------------------------------------------------------- function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is Variable num_addr_bits_needed : Integer range 1 to 7 := 1; begin case mmap_dwidth_value is when 32 => num_addr_bits_needed := 2; when 64 => num_addr_bits_needed := 3; when 128 => num_addr_bits_needed := 4; when 256 => num_addr_bits_needed := 5; when 512 => num_addr_bits_needed := 6; when others => -- 1024 bits num_addr_bits_needed := 7; end case; Return (num_addr_bits_needed); end function func_calc_wdemux_sel_bits; ------------------------------------------------------------------- -- Function -- -- Function Name: func_include_dre -- -- Function Description: -- This function desides if conditions are right for allowing DRE -- inclusion. -- ------------------------------------------------------------------- function func_include_dre (need_dre : integer; needed_data_width : integer) return integer is Variable include_dre : Integer := 0; begin if (need_dre = 1 and needed_data_width < 128 and needed_data_width > 8) Then include_dre := 1; Else include_dre := 0; End if; Return (include_dre); end function func_include_dre; ------------------------------------------------------------------- -- Function -- -- Function Name: func_get_align_width -- -- Function Description: -- This function calculates the needed DRE alignment port width\ -- based upon the inclusion of DRE and the needed bit width of the -- DRE. -- ------------------------------------------------------------------- function func_get_align_width (dre_included : integer; dre_data_width : integer) return integer is Variable align_port_width : Integer := 1; begin if (dre_included = 1) then If (dre_data_width = 64) Then align_port_width := 3; Elsif (dre_data_width = 32) Then align_port_width := 2; else -- 16 bit data width align_port_width := 1; End if; else align_port_width := 1; end if; Return (align_port_width); end function func_get_align_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_set_status_width -- -- Function Description: -- This function sets the width of the Status pipe depending on the -- Store and Forward inclusion or ommision. -- ------------------------------------------------------------------- function funct_set_status_width (store_forward_enabled : integer) return integer is Variable temp_status_bit_width : Integer := 8; begin If (store_forward_enabled = 1) Then temp_status_bit_width := 32; Else temp_status_bit_width := 8; End if; Return (temp_status_bit_width); end function funct_set_status_width; ------------------------------------------------------------------- -- Function -- -- Function Name: get_bits_needed -- -- Function Description: -- -- ------------------------------------------------------------------- function get_bits_needed (max_bytes : integer) return integer is Variable fvar_temp_bit_width : Integer := 1; begin if (max_bytes <= 1) then fvar_temp_bit_width := 1; elsif (max_bytes <= 3) then fvar_temp_bit_width := 2; elsif (max_bytes <= 7) then fvar_temp_bit_width := 3; elsif (max_bytes <= 15) then fvar_temp_bit_width := 4; elsif (max_bytes <= 31) then fvar_temp_bit_width := 5; elsif (max_bytes <= 63) then fvar_temp_bit_width := 6; elsif (max_bytes <= 127) then fvar_temp_bit_width := 7; elsif (max_bytes <= 255) then fvar_temp_bit_width := 8; elsif (max_bytes <= 511) then fvar_temp_bit_width := 9; elsif (max_bytes <= 1023) then fvar_temp_bit_width := 10; elsif (max_bytes <= 2047) then fvar_temp_bit_width := 11; elsif (max_bytes <= 4095) then fvar_temp_bit_width := 12; elsif (max_bytes <= 8191) then fvar_temp_bit_width := 13; else -- 8k - 16K fvar_temp_bit_width := 14; end if; Return (fvar_temp_bit_width); end function get_bits_needed; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_rnd2pwr_of_2 -- -- Function Description: -- Rounds the input value up to the nearest power of 2 between -- 128 and 8192. -- ------------------------------------------------------------------- function funct_rnd2pwr_of_2 (input_value : integer) return integer is Variable temp_pwr2 : Integer := 128; begin if (input_value <= 128) then temp_pwr2 := 128; elsif (input_value <= 256) then temp_pwr2 := 256; elsif (input_value <= 512) then temp_pwr2 := 512; elsif (input_value <= 1024) then temp_pwr2 := 1024; elsif (input_value <= 2048) then temp_pwr2 := 2048; elsif (input_value <= 4096) then temp_pwr2 := 4096; else temp_pwr2 := 8192; end if; Return (temp_pwr2); end function funct_rnd2pwr_of_2; ------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_need_realigner -- -- Function Description: -- Determines if the Realigner module needs to be included. -- ------------------------------------------------------------------- function funct_need_realigner (indet_btt_enabled : integer; dre_included : integer; gp_sf_included : integer) return integer is Variable temp_val : Integer := 0; begin If ((indet_btt_enabled = 1) or (dre_included = 1) or (gp_sf_included = 1)) Then temp_val := 1; else temp_val := 0; End if; Return (temp_val); end function funct_need_realigner; ------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_sf_offset_width -- -- Function Description: -- This function calculates the address offset width needed by -- the GP Store and Forward module with data packing. -- ------------------------------------------------------------------- function funct_get_sf_offset_width (mmap_dwidth : integer; stream_dwidth : integer) return integer is Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth; Variable fvar_temp_offset_width : Integer := 1; begin case FCONST_WIDTH_RATIO is when 1 => fvar_temp_offset_width := 1; when 2 => fvar_temp_offset_width := 1; when 4 => fvar_temp_offset_width := 2; when 8 => fvar_temp_offset_width := 3; when 16 => fvar_temp_offset_width := 4; when 32 => fvar_temp_offset_width := 5; when 64 => fvar_temp_offset_width := 6; when others => fvar_temp_offset_width := 7; end case; Return (fvar_temp_offset_width); end function funct_get_sf_offset_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_stream_width2use -- -- Function Description: -- This function calculates the Stream width to use for S2MM -- modules downstream from the upsizing Store and Forward. If -- Store and forward is present, then the effective Stream width -- is the MMAP data width. If no Store and Forward then the Stream -- width is the input Stream width from the User. -- ------------------------------------------------------------------- function funct_get_stream_width2use (mmap_data_width : integer; stream_data_width : integer; sf_enabled : integer) return integer is Variable fvar_temp_width : Integer := 32; begin If (sf_enabled > 0) Then fvar_temp_width := mmap_data_width; Else fvar_temp_width := stream_data_width; End if; Return (fvar_temp_width); end function funct_get_stream_width2use; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_bytes_per_dbeat -- -- Function Description: -- This function calculates the number of bytes transfered per -- databeat on the MMap AXI4 Write Data Channel by the S2MM. The -- value is based on input parameterization of included functions -- in the S2MM block. -- ------------------------------------------------------------------- function funct_get_bytes_per_dbeat (ibtt_enabled : integer ; gpsf_enabled : integer ; stream_dwidth : integer ; mmap_dwidth : integer ) return integer is Variable fvar_temp_bytes_per_xfer : Integer := 4; begin If (ibtt_enabled > 0 or gpsf_enabled > 0) Then -- transfers will be upsized to mmap data width fvar_temp_bytes_per_xfer := mmap_dwidth/8; Else -- transfers will be in stream data widths (may be narrow transfers on mmap) fvar_temp_bytes_per_xfer := stream_dwidth/8; End if; Return (fvar_temp_bytes_per_xfer); end function funct_get_bytes_per_dbeat; -- Constant Declarations ---------------------------------------- Constant SF_ENABLED : integer := C_INCLUDE_S2MM_GP_SF + C_S2MM_SUPPORT_INDET_BTT; Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_S2MM_MDATA_WIDTH, C_S2MM_SDATA_WIDTH, SF_ENABLED); Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant IS_NOT_MM2S : integer range 0 to 1 := 0; Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID; Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH; Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH; Constant S2MM_MDATA_WIDTH : integer range 32 to 1024 := C_S2MM_MDATA_WIDTH; Constant S2MM_SDATA_WIDTH : integer range 8 to 1024 := C_S2MM_SDATA_WIDTH; Constant S2MM_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH; Constant S2MM_CMD_WIDTH : integer := (S2MM_TAG_WIDTH+S2MM_ADDR_WIDTH+32); Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := C_INCLUDE_S2MM_STSFIFO; Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH; Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC; Constant S2MM_BURST_SIZE : integer range 2 to 256 := C_S2MM_BURST_SIZE; Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH); Constant S2MM_BTT_USED : integer range 8 to 23 := C_S2MM_BTT_USED; Constant BITS_PER_BYTE : integer := 8; Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_S2MM_DRE, S2MM_SDATA_WIDTH); Constant DRE_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant S2MM_DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_S2MM_DRE, S2MM_SDATA_WIDTH); Constant DRE_SUPPORT_SCATTER : integer range 0 to 1 := 1; Constant ENABLE_INDET_BTT_SF : integer range 0 to 1 := C_S2MM_SUPPORT_INDET_BTT; Constant ENABLE_GP_SF : integer range 0 to 1 := C_INCLUDE_S2MM_GP_SF ; Constant BYTES_PER_MMAP_DBEAT : integer := funct_get_bytes_per_dbeat(ENABLE_INDET_BTT_SF , ENABLE_GP_SF , S2MM_SDATA_WIDTH , S2MM_MDATA_WIDTH); Constant MAX_BYTES_PER_BURST : integer := BYTES_PER_MMAP_DBEATS2MM_BURST_SIZE; Constant IBTT_XFER_BYTES_WIDTH : integer := get_bits_needed(MAX_BYTES_PER_BURST); Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2; -- 2 added for going -- full thresholding -- in WSC Constant WSC_STATUS_WIDTH : integer range 8 to 32 := funct_set_status_width(ENABLE_INDET_BTT_SF); Constant WSC_BYTES_RCVD_WIDTH : integer range 8 to 32 := S2MM_BTT_USED; Constant ADD_REALIGNER : integer := funct_need_realigner(ENABLE_INDET_BTT_SF , INCLUDE_S2MM_DRE , ENABLE_GP_SF); -- Calculates the minimum needed depth of the GP Store and Forward FIFO -- based on the S2MM pipeline depth and the max allowed Burst length Constant PIPEDEPTH_BURST_LEN_PROD : integer := (ADDR_CNTL_FIFO_DEPTH+2) * S2MM_BURST_SIZE; -- Assigns the depth of the optional GP Store and Forward FIFO to the nearest -- power of 2 Constant SF_FIFO_DEPTH : integer range 128 to 8192 := funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD); -- Calculate the width of the Store and Forward Starting Address Offset bus Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(S2MM_MDATA_WIDTH, S2MM_SDATA_WIDTH); -- Signal Declarations ------------------------------------------ signal sig_cmd_stat_rst_user : std_logic := '0'; signal sig_cmd_stat_rst_int : std_logic := '0'; signal sig_mmap_rst : std_logic := '0'; signal sig_stream_rst : std_logic := '0'; signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0'); signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd2mstr_cmd_valid : std_logic := '0'; signal sig_mst2cmd_cmd_ready : std_logic := '0'; signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0'); signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_cmd_cmplt : std_logic := '0'; signal sig_mstr2addr_calc_error : std_logic := '0'; signal sig_mstr2addr_cmd_valid : std_logic := '0'; signal sig_addr2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_drr : std_logic := '0'; signal sig_mstr2data_eof : std_logic := '0'; signal sig_mstr2data_sequential : std_logic := '0'; signal sig_mstr2data_calc_error : std_logic := '0'; signal sig_mstr2data_cmd_last : std_logic := '0'; signal sig_mstr2data_cmd_valid : std_logic := '0'; signal sig_data2mstr_cmd_ready : std_logic := '0'; signal sig_addr2data_addr_posted : std_logic := '0'; signal sig_data2addr_data_rdy : std_logic := '0'; signal sig_data2all_tlast_error : std_logic := '0'; signal sig_data2all_dcntlr_halted : std_logic := '0'; signal sig_addr2wsc_calc_error : std_logic := '0'; signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0'; signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0'); signal sig_data2wsc_cmd_empty : std_logic := '0'; signal sig_data2wsc_calc_err : std_logic := '0'; signal sig_data2wsc_cmd_cmplt : std_logic := '0'; signal sig_data2wsc_last_err : std_logic := '0'; signal sig_calc2dm_calc_err : std_logic := '0'; signal sig_wsc2stat_status : std_logic_vector(WSC_STATUS_WIDTH-1 downto 0) := (others => '0'); signal sig_stat2wsc_status_ready : std_logic := '0'; signal sig_wsc2stat_status_valid : std_logic := '0'; signal sig_wsc2mstr_halt_pipe : std_logic := '0'; signal sig_data2wsc_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_wvalid : std_logic := '0'; signal sig_skid2data_wready : std_logic := '0'; signal sig_data2skid_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_data2skid_wlast : std_logic := '0'; signal sig_skid2axi_wvalid : std_logic := '0'; signal sig_axi2skid_wready : std_logic := '0'; signal sig_skid2axi_wdata : std_logic_vector(S2MM_MDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_skid2axi_wstrb : std_logic_vector((S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_skid2axi_wlast : std_logic := '0'; signal sig_data2wsc_sof : std_logic := '0'; signal sig_data2wsc_eof : std_logic := '0'; signal sig_data2wsc_valid : std_logic := '0'; signal sig_wsc2data_ready : std_logic := '0'; signal sig_data2wsc_eop : std_logic := '0'; signal sig_data2wsc_bytes_rcvd : std_logic_vector(WSC_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0'); signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_sf2pcc_xfer_valid : std_logic := '0'; signal sig_pcc2sf_xfer_ready : std_logic := '0'; signal sig_sf2pcc_cmd_cmplt : std_logic := '0'; signal sig_sf2pcc_packet_eop : std_logic := '0'; signal sig_sf2pcc_xfer_bytes : std_logic_vector(IBTT_XFER_BYTES_WIDTH-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tvalid : std_logic := '0'; signal sig_wdc2ibtt_tready : std_logic := '0'; signal sig_ibtt2wdc_tdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tlast : std_logic := '0'; signal sig_ibtt2wdc_eop : std_logic := '0'; signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(7 downto 0) := (others => '0'); signal sig_dre2ibtt_tvalid : std_logic := '0'; signal sig_ibtt2dre_tready : std_logic := '0'; signal sig_dre2ibtt_tdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_dre2ibtt_tstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_dre2ibtt_tlast : std_logic := '0'; signal sig_dre2ibtt_eop : std_logic := '0'; signal sig_dre2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2dre_cmd_valid : std_logic := '0'; signal sig_mstr2dre_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_dre_src_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_dre_dest_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_btt : std_logic_vector(S2MM_BTT_USED-1 downto 0) := (others => '0'); signal sig_mstr2dre_drr : std_logic := '0'; signal sig_mstr2dre_eof : std_logic := '0'; signal sig_mstr2dre_cmd_cmplt : std_logic := '0'; signal sig_mstr2dre_calc_error : std_logic := '0'; signal sig_realign2wdc_eop_error : std_logic := '0'; signal sig_dre2all_halted : std_logic := '0'; signal sig_rst2all_stop_request : std_logic := '0'; signal sig_data2rst_stop_cmplt : std_logic := '0'; signal sig_addr2rst_stop_cmplt : std_logic := '0'; signal sig_data2addr_stop_req : std_logic := '0'; signal sig_wsc2rst_stop_cmplt : std_logic := '0'; signal sig_data2skid_halt : std_logic := '0'; signal skid2dre_wvalid : std_logic := '0'; signal dre2skid_wready : std_logic := '0'; signal skid2dre_wdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0'); signal skid2dre_wstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal skid2dre_wlast : std_logic := '0'; signal sig_s2mm_allow_addr_req : std_logic := '0'; signal sig_ok_to_post_wr_addr : std_logic := '0'; signal sig_s2mm_addr_req_posted : std_logic := '0'; signal sig_s2mm_wr_xfer_cmplt : std_logic := '0'; signal sig_s2mm_ld_nxt_len : std_logic := '0'; signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_ibtt2wdc_error : std_logic := '0'; signal sig_sf_strt_addr_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_cache2mstr_command : std_logic_vector (7 downto 0); signal s2mm_awcache_int : std_logic_vector (3 downto 0); signal s2mm_awuser_int : std_logic_vector (3 downto 0); begin --(architecture implementation) -- Debug/Test Port Assignments s2mm_dbg_data <= sig_dbg_data_mux_out; -- Note that only the s2mm_dbg_sel(0) is used at this time sig_dbg_data_mux_out <= sig_dbg_data_1 When (s2mm_dbg_sel(0) = '1') else sig_dbg_data_0 ; sig_dbg_data_0 <= X"CAFE1111" ; -- 32 bit Constant indicating S2MM FULL type sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ; sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ; sig_dbg_data_1(2) <= sig_mmap_rst ; sig_dbg_data_1(3) <= sig_stream_rst ; sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ; sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ; sig_dbg_data_1(6) <= sig_stat2wsc_status_ready; sig_dbg_data_1(7) <= sig_wsc2stat_status_valid; sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error --sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADD_DEBUG_EOP -- -- If Generate Description: -- -- This IfGen adds in the EOP status marker to the debug -- vector data when Indet BTT Store and Forward is enabled. -- ------------------------------------------------------------ GEN_ADD_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 1) generate begin sig_dbg_data_1(19) <= sig_wsc2stat_status(31) ; -- EOP Marker end generate GEN_ADD_DEBUG_EOP; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_DEBUG_EOP -- -- If Generate Description: -- -- This IfGen zeros the debug vector bit used for the EOP -- status marker when Indet BTT Store and Forward is not -- enabled. -- ------------------------------------------------------------ GEN_NO_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 0) generate begin sig_dbg_data_1(19) <= '0' ; -- EOP Marker end generate GEN_NO_DEBUG_EOP; ---- End of Debug/Test Support -------------------------------- -- Assign the Address posting control outputs s2mm_addr_req_posted <= sig_s2mm_addr_req_posted ; s2mm_wr_xfer_cmplt <= sig_s2mm_wr_xfer_cmplt ; s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len ; s2mm_wr_len <= sig_s2mm_wr_len ; -- Write Data Channel I/O s2mm_wvalid <= sig_skid2axi_wvalid; sig_axi2skid_wready <= s2mm_wready ; s2mm_wdata <= sig_skid2axi_wdata ; s2mm_wlast <= sig_skid2axi_wlast ; GEN_S2MM_TKEEP_ENABLE2 : if C_ENABLE_S2MM_TKEEP = 1 generate begin s2mm_wstrb <= sig_skid2axi_wstrb ; end generate GEN_S2MM_TKEEP_ENABLE2; GEN_S2MM_TKEEP_DISABLE2 : if C_ENABLE_S2MM_TKEEP = 0 generate begin s2mm_wstrb <= (others => '1'); end generate GEN_S2MM_TKEEP_DISABLE2; GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate begin -- Cache signal tie-off s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96); end generate GEN_CACHE; GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate begin -- Cache signal tie-off s2mm_awcache <= s2mm_awcache_int; -- pre Interface-X guidelines for Masters s2mm_awuser <= s2mm_awuser_int; -- pre Interface-X guidelines for Masters sig_s2mm_cache_data <= s2mm_cmd_wdata(79+(C_S2MM_ADDR_WIDTH-32) downto 72+(C_S2MM_ADDR_WIDTH-32)); -- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96); end generate GEN_CACHE2; -- Internal error output discrete s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error; -- Rip the used portion of the Command Interface Command Data -- and throw away the padding sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0); ------------------------------------------------------------ -- Instance: I_RESET -- -- Description: -- Reset Block -- ------------------------------------------------------------ I_RESET : entity axi_datamover_v5_1_10.axi_datamover_reset generic map ( C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ) port map ( primary_aclk => s2mm_aclk , primary_aresetn => s2mm_aresetn , secondary_awclk => s2mm_cmdsts_awclk , secondary_aresetn => s2mm_cmdsts_aresetn , halt_req => s2mm_halt , halt_cmplt => s2mm_halt_cmplt , flush_stop_request => sig_rst2all_stop_request , data_cntlr_stopped => sig_data2rst_stop_cmplt , addr_cntlr_stopped => sig_addr2rst_stop_cmplt , aux1_stopped => sig_wsc2rst_stop_cmplt , aux2_stopped => LOGIC_HIGH , cmd_stat_rst_user => sig_cmd_stat_rst_user , cmd_stat_rst_int => sig_cmd_stat_rst_int , mmap_rst => sig_mmap_rst , stream_rst => sig_stream_rst ); ------------------------------------------------------------ -- Instance: I_CMD_STATUS -- -- Description: -- Command and Status Interface Block -- ------------------------------------------------------------ I_CMD_STATUS : entity axi_datamover_v5_1_10.axi_datamover_cmd_status generic map ( C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO , C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH , C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_STS_WIDTH => WSC_STATUS_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , secondary_awclk => s2mm_cmdsts_awclk , user_reset => sig_cmd_stat_rst_user , internal_reset => sig_cmd_stat_rst_int , cmd_wvalid => s2mm_cmd_wvalid , cmd_wready => s2mm_cmd_wready , cmd_wdata => sig_s2mm_cmd_wdata , cache_data => sig_s2mm_cache_data , sts_wvalid => s2mm_sts_wvalid , sts_wready => s2mm_sts_wready , sts_wdata => s2mm_sts_wdata , sts_wstrb => s2mm_sts_wstrb , sts_wlast => s2mm_sts_wlast , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid , cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready , mstr2stat_status => sig_wsc2stat_status , stat2mstr_status_ready => sig_stat2wsc_status_ready , mst2stst_status_valid => sig_wsc2stat_status_valid ); ------------------------------------------------------------ -- Instance: I_WR_STATUS_CNTLR -- -- Description: -- Write Status Controller Block -- ------------------------------------------------------------ I_WR_STATUS_CNTLR : entity axi_datamover_v5_1_10.axi_datamover_wr_status_cntl generic map ( C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH , C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH , C_STS_WIDTH => WSC_STATUS_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , rst2wsc_stop_request => sig_rst2all_stop_request , wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt , addr2wsc_addr_posted => sig_addr2data_addr_posted , s2mm_bresp => s2mm_bresp , s2mm_bvalid => s2mm_bvalid , s2mm_bready => s2mm_bready , calc2wsc_calc_error => sig_calc2dm_calc_err , addr2wsc_calc_error => sig_addr2wsc_calc_error , addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty , data2wsc_tag => sig_data2wsc_tag , data2wsc_calc_error => sig_data2wsc_calc_err , data2wsc_last_error => sig_data2wsc_last_err , data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt , data2wsc_valid => sig_data2wsc_valid , wsc2data_ready => sig_wsc2data_ready , data2wsc_eop => sig_data2wsc_eop , data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd , wsc2stat_status => sig_wsc2stat_status , stat2wsc_status_ready => sig_stat2wsc_status_ready , wsc2stat_status_valid => sig_wsc2stat_status_valid , wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe ); ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_PCC -- -- If Generate Description: -- Include the normal Predictive Command Calculator function, -- Store and Forward is not an included feature. -- -- ------------------------------------------------------------ GEN_INCLUDE_PCC : if (ENABLE_INDET_BTT_SF = 0) generate begin ------------------------------------------------------------ -- Instance: I_MSTR_PCC -- -- Description: -- Predictive Command Calculator Block -- ------------------------------------------------------------ I_MSTR_PCC : entity axi_datamover_v5_1_10.axi_datamover_pcc generic map ( C_IS_MM2S => IS_NOT_MM2S , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_BTT_USED => S2MM_BTT_USED , C_SUPPORT_INDET_BTT => ENABLE_INDET_BTT_SF , C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ) port map ( -- Clock input primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , mstr2data_dre_src_align => open , mstr2data_dre_dest_align => open , calc_error => sig_calc2dm_calc_err , dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset ); end generate GEN_INCLUDE_PCC; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_IBTTCC -- -- If Generate Description: -- Include the Indeterminate BTT Command Calculator function, -- Store and Forward is enabled in the S2MM. -- -- ------------------------------------------------------------ GEN_INCLUDE_IBTTCC : if (ENABLE_INDET_BTT_SF = 1) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_MSTR_SFCC -- -- Description: -- Instantiates the Store and Forward Command Calculator -- Block. -- ------------------------------------------------------------ I_S2MM_MSTR_IBTTCC : entity axi_datamover_v5_1_10.axi_datamover_ibttcc generic map ( C_SF_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_BTT_USED => S2MM_BTT_USED , C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ) port map ( -- Clock input primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid , pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready , sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt , sf2pcc_packet_eop => sig_sf2pcc_packet_eop , sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , calc_error => sig_calc2dm_calc_err , dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset ); end generate GEN_INCLUDE_IBTTCC; ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate begin ------------------------------------------------------------ -- Instance: I_S2MM_STRM_SKID_BUF -- -- Description: -- Instance for the S2MM Skid Buffer which provides for -- registerd Slave Stream inputs and supports bi-dir -- throttling. -- ------------------------------------------------------------ I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => S2MM_SDATA_WIDTH ) port map ( -- System Ports aclk => s2mm_aclk , arst => sig_mmap_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => sig_data2skid_halt , -- Slave Side (Stream Data Input) s_valid => s2mm_strm_wvalid , s_ready => s2mm_strm_wready , s_data => s2mm_strm_wdata , s_strb => s2mm_strm_wstrb , s_last => s2mm_strm_wlast , -- Master Side (Stream Data Output m_valid => skid2dre_wvalid , m_ready => dre2skid_wready , m_data => skid2dre_wdata , m_strb => skid2dre_wstrb , m_last => skid2dre_wlast ); end generate ENABLE_AXIS_SKID; DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate begin skid2dre_wvalid <= s2mm_strm_wvalid; s2mm_strm_wready <= dre2skid_wready; skid2dre_wdata <= s2mm_strm_wdata; skid2dre_wstrb <= s2mm_strm_wstrb; skid2dre_wlast <= s2mm_strm_wlast; end generate DISABLE_AXIS_SKID; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_REALIGNER -- -- If Generate Description: -- Omit the S2MM Realignment Engine -- -- ------------------------------------------------------------ GEN_NO_REALIGNER : if (ADD_REALIGNER = 0) generate begin -- Set to Always ready for DRE to PCC Command Interface sig_dre2mstr_cmd_ready <= LOGIC_HIGH; -- Without DRE and Scatter, the end of packet is the TLAST --sig_dre2ibtt_eop <= skid2dre_wlast ; sig_dre2ibtt_eop <= sig_dre2ibtt_tlast ; -- use skid buffered version -- Cant't detect undrrun/overrun here sig_realign2wdc_eop_error <= '0'; ENABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '1' generate begin ------------------------------------------------------------ -- Instance: I_NO_REALIGN_SKID_BUF -- -- Description: -- Instance for a Skid Buffer which provides for -- Fmax timing improvement between the Null Absorber and -- the Write Data controller when the Realigner is not -- present (no DRE and no Store and Forward case). -- ------------------------------------------------------------ I_NO_REALIGN_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => S2MM_SDATA_WIDTH ) port map ( -- System Ports aclk => s2mm_aclk , arst => sig_mmap_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => LOGIC_LOW , -- Slave Side (Null Absorber Input) s_valid => skid2dre_wvalid , s_ready => dre2skid_wready , s_data => skid2dre_wdata , s_strb => skid2dre_wstrb , s_last => skid2dre_wlast , -- Master Side (Stream Data Output to WData Cntlr) m_valid => sig_dre2ibtt_tvalid , m_ready => sig_ibtt2dre_tready , m_data => sig_dre2ibtt_tdata , m_strb => sig_dre2ibtt_tstrb , m_last => sig_dre2ibtt_tlast ); end generate ENABLE_NOREALIGNER_SKID; DISABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '0' generate begin sig_dre2ibtt_tvalid <= skid2dre_wvalid; dre2skid_wready <= sig_ibtt2dre_tready; sig_dre2ibtt_tdata <= skid2dre_wdata; sig_dre2ibtt_tstrb <= skid2dre_wstrb; sig_dre2ibtt_tlast <= skid2dre_wlast; end generate DISABLE_NOREALIGNER_SKID; end generate GEN_NO_REALIGNER; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_REALIGNER -- -- If Generate Description: -- Include the S2MM realigner Module. It hosts the S2MM DRE -- and the Scatter Block. -- -- Note that the General Purpose Store and Forward Module -- needs the Scatter function to detect input overrun and -- underrun events on the AXI Stream input. Thus the Realigner -- is included whenever the GP Store and Forward is enabled. -- ------------------------------------------------------------ GEN_INCLUDE_REALIGNER : if (ADD_REALIGNER = 1) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_REALIGNER -- -- Description: -- Instance for the S2MM Data Realignment Module. -- ------------------------------------------------------------ I_S2MM_REALIGNER : entity axi_datamover_v5_1_10.axi_datamover_s2mm_realign generic map ( C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_INCLUDE_DRE => INCLUDE_S2MM_DRE , C_DRE_CNTL_FIFO_DEPTH => DRE_CNTL_FIFO_DEPTH , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SUPPORT_SCATTER => DRE_SUPPORT_SCATTER , C_BTT_USED => S2MM_BTT_USED , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , -- Write Data Controller or Store and Forward I/O ------- wdc2dre_wready => sig_ibtt2dre_tready , dre2wdc_wvalid => sig_dre2ibtt_tvalid , dre2wdc_wdata => sig_dre2ibtt_tdata , dre2wdc_wstrb => sig_dre2ibtt_tstrb , dre2wdc_wlast => sig_dre2ibtt_tlast , dre2wdc_eop => sig_dre2ibtt_eop , -- Starting offset output ------------------------------- dre2sf_strt_offset => sig_sf_strt_addr_offset , -- AXI Slave Stream In ----------------------------------- s2mm_strm_wready => dre2skid_wready , s2mm_strm_wvalid => skid2dre_wvalid , s2mm_strm_wdata => skid2dre_wdata , s2mm_strm_wstrb => skid2dre_wstrb , s2mm_strm_wlast => skid2dre_wlast , -- Command Calculator Interface -------------------------- dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset , -- Premature TLAST assertion error flag dre2all_tlast_error => sig_realign2wdc_eop_error , -- DRE Halted Status dre2all_halted => sig_dre2all_halted ); end generate GEN_INCLUDE_REALIGNER; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ENABLE_INDET_BTT_SF -- -- If Generate Description: -- Include the Indeterminate BTT Logic with specialized -- Store and Forward function, This also requires the -- Scatter Engine in the Realigner module. -- -- ------------------------------------------------------------ GEN_ENABLE_INDET_BTT_SF : if (ENABLE_INDET_BTT_SF = 1) generate begin -- Pass the Realigner EOP error through sig_ibtt2wdc_error <= sig_realign2wdc_eop_error; -- Use only external address posting enable sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ; ------------------------------------------------------------ -- Instance: I_INDET_BTT -- -- Description: -- Instance for the Indeterminate BTT with Store and Forward -- module. -- ------------------------------------------------------------ I_INDET_BTT : entity axi_datamover_v5_1_10.axi_datamover_indet_btt generic map ( C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , C_IBTT_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH , C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_ENABLE_DRE => INCLUDE_S2MM_DRE , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , ibtt2wdc_stbs_asserted => sig_ibtt2wdc_stbs_asserted, ibtt2wdc_eop => sig_ibtt2wdc_eop , ibtt2wdc_tdata => sig_ibtt2wdc_tdata , ibtt2wdc_tstrb => sig_ibtt2wdc_tstrb , ibtt2wdc_tlast => sig_ibtt2wdc_tlast , ibtt2wdc_tvalid => sig_ibtt2wdc_tvalid , wdc2ibtt_tready => sig_wdc2ibtt_tready , dre2ibtt_tvalid => sig_dre2ibtt_tvalid , ibtt2dre_tready => sig_ibtt2dre_tready , dre2ibtt_tdata => sig_dre2ibtt_tdata , dre2ibtt_tstrb => sig_dre2ibtt_tstrb , dre2ibtt_tlast => sig_dre2ibtt_tlast , dre2ibtt_eop => sig_dre2ibtt_eop , dre2ibtt_strt_addr_offset => sig_sf_strt_addr_offset , sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid , pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready , sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt , sf2pcc_packet_eop => sig_sf2pcc_packet_eop , sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes ); end generate GEN_ENABLE_INDET_BTT_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_SF -- -- If Generate Description: -- Bypasses any store and Forward functions. -- -- ------------------------------------------------------------ GEN_NO_SF : if (ENABLE_INDET_BTT_SF = 0 and ENABLE_GP_SF = 0) generate begin -- Use only external address posting enable sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ; -- Housekeep unused signal in this case sig_ok_to_post_wr_addr <= '0' ; -- SFCC Interface Signals that are not used sig_pcc2sf_xfer_ready <= '0' ; sig_sf2pcc_xfer_valid <= '0' ; sig_sf2pcc_cmd_cmplt <= '0' ; sig_sf2pcc_packet_eop <= '0' ; sig_sf2pcc_xfer_bytes <= (others => '0') ; -- Just pass DRE signals through sig_ibtt2dre_tready <= sig_wdc2ibtt_tready ; sig_ibtt2wdc_tvalid <= sig_dre2ibtt_tvalid ; sig_ibtt2wdc_tdata <= sig_dre2ibtt_tdata ; sig_ibtt2wdc_tstrb <= sig_dre2ibtt_tstrb ; sig_ibtt2wdc_tlast <= sig_dre2ibtt_tlast ; sig_ibtt2wdc_eop <= sig_dre2ibtt_eop ; sig_ibtt2wdc_stbs_asserted <= (others => '0') ; -- Pass the Realigner EOP error through sig_ibtt2wdc_error <= sig_realign2wdc_eop_error; end generate GEN_NO_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_GP_SF -- -- If Generate Description: -- Include the General Purpose Store and Forward module. -- This If Generate can only be enabled when -- Indeterminate BTT mode is not enabled. The General Purpose -- Store and Forward is instantiated in place of the Indet -- BTT Store and Forward. -- ------------------------------------------------------------ GEN_INCLUDE_GP_SF : if (ENABLE_INDET_BTT_SF = 0 and ENABLE_GP_SF = 1) generate begin -- Merge the external address posting control with the -- SF address posting control. sig_s2mm_allow_addr_req <= s2mm_allow_addr_req and sig_ok_to_post_wr_addr ; -- Zero these out since Indet BTT is not enabled, they -- are only used by the WDC in that mode sig_ibtt2wdc_stbs_asserted <= (others => '0') ; sig_ibtt2wdc_eop <= '0' ; -- SFCC Interface Signals that are not used sig_pcc2sf_xfer_ready <= '0' ; sig_sf2pcc_xfer_valid <= '0' ; sig_sf2pcc_cmd_cmplt <= '0' ; sig_sf2pcc_packet_eop <= '0' ; sig_sf2pcc_xfer_bytes <= (others => '0') ; ------------------------------------------------------------ -- Instance: I_S2MM_GP_SF -- -- Description: -- Instance for the S2MM (Write) General Purpose Store and -- Forward Module. This module can only be enabled when -- Indeterminate BTT mode is not enabled. It is connected -- in place of the IBTT Module when GP SF is enabled. -- ------------------------------------------------------------ I_S2MM_GP_SF : entity axi_datamover_v5_1_10.axi_datamover_wr_sf generic map ( C_WR_ADDR_PIPE_DEPTH => ADDR_CNTL_FIFO_DEPTH , C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset inputs ----------------------------- aclk => s2mm_aclk , reset => sig_mmap_rst , -- Slave Stream Input -------------------------------- sf2sin_tready => sig_ibtt2dre_tready , sin2sf_tvalid => sig_dre2ibtt_tvalid , sin2sf_tdata => sig_dre2ibtt_tdata , sin2sf_tkeep => sig_dre2ibtt_tstrb , sin2sf_tlast => sig_dre2ibtt_tlast , sin2sf_error => sig_realign2wdc_eop_error , -- Starting Address Offset Input --------------------- sin2sf_strt_addr_offset => sig_sf_strt_addr_offset , -- DataMover Write Side Address Pipelining Control Interface -------- ok_to_post_wr_addr => sig_ok_to_post_wr_addr , wr_addr_posted => sig_s2mm_addr_req_posted , wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt , wr_ld_nxt_len => sig_s2mm_ld_nxt_len , wr_len => sig_s2mm_wr_len , -- Write Side Stream Out to DataMover S2MM ------------- sout2sf_tready => sig_wdc2ibtt_tready , sf2sout_tvalid => sig_ibtt2wdc_tvalid , sf2sout_tdata => sig_ibtt2wdc_tdata , sf2sout_tkeep => sig_ibtt2wdc_tstrb , sf2sout_tlast => sig_ibtt2wdc_tlast , sf2sout_error => sig_ibtt2wdc_error ); end generate GEN_INCLUDE_GP_SF; ------------------------------------------------------------ -- Instance: I_ADDR_CNTL -- -- Description: -- Address Controller Block -- ------------------------------------------------------------ I_ADDR_CNTL : entity axi_datamover_v5_1_10.axi_datamover_addr_cntl generic map ( C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_ADDR_ID => S2MM_AWID_VALUE , C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , addr2axi_aid => s2mm_awid , addr2axi_aaddr => s2mm_awaddr , addr2axi_alen => s2mm_awlen , addr2axi_asize => s2mm_awsize , addr2axi_aburst => s2mm_awburst , addr2axi_aprot => s2mm_awprot , addr2axi_avalid => s2mm_awvalid , addr2axi_acache => s2mm_awcache_int , addr2axi_auser => s2mm_awuser_int , axi2addr_aready => s2mm_awready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , -- mstr2addr_cache_info => sig_cache2mstr_command , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt , allow_addr_req => sig_s2mm_allow_addr_req , addr_req_posted => sig_s2mm_addr_req_posted , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => sig_data2addr_data_rdy , data2addr_stop_req => sig_data2addr_stop_req , addr2stat_calc_error => sig_addr2wsc_calc_error , addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty ); ------------------------------------------------------------ -- Instance: I_WR_DATA_CNTL -- -- Description: -- Write Data Controller Block -- ------------------------------------------------------------ I_WR_DATA_CNTL : entity axi_datamover_v5_1_10.axi_datamover_wrdata_cntl generic map ( C_REALIGNER_INCLUDED => ADD_REALIGNER , C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , rst2data_stop_request => sig_rst2all_stop_request , data2addr_stop_req => sig_data2addr_stop_req , data2rst_stop_cmplt => sig_data2rst_stop_cmplt , wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt , s2mm_ld_nxt_len => sig_s2mm_ld_nxt_len , s2mm_wr_len => sig_s2mm_wr_len , data2skid_saddr_lsb => sig_data2skid_addr_lsb , data2skid_wdata => sig_data2skid_wdata , data2skid_wstrb => sig_data2skid_wstrb , data2skid_wlast => sig_data2skid_wlast , data2skid_wvalid => sig_data2skid_wvalid , skid2data_wready => sig_skid2data_wready , s2mm_strm_wvalid => sig_ibtt2wdc_tvalid , s2mm_strm_wready => sig_wdc2ibtt_tready , s2mm_strm_wdata => sig_ibtt2wdc_tdata , s2mm_strm_wstrb => sig_ibtt2wdc_tstrb , s2mm_strm_wlast => sig_ibtt2wdc_tlast , s2mm_strm_eop => sig_ibtt2wdc_eop , s2mm_stbs_asserted => sig_ibtt2wdc_stbs_asserted, realign2wdc_eop_error => sig_ibtt2wdc_error , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => sig_data2addr_data_rdy , data2all_tlast_error => sig_data2all_tlast_error , data2all_dcntlr_halted => sig_data2all_dcntlr_halted, data2skid_halt => sig_data2skid_halt , data2wsc_tag => sig_data2wsc_tag , data2wsc_calc_err => sig_data2wsc_calc_err , data2wsc_last_err => sig_data2wsc_last_err , data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt , wsc2data_ready => sig_wsc2data_ready , data2wsc_valid => sig_data2wsc_valid , data2wsc_eop => sig_data2wsc_eop , data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd , wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe ); --ENABLE_AXIMMAP_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate --begin ------------------------------------------------------------ -- Instance: I_S2MM_MMAP_SKID_BUF -- -- Description: -- Instance for the S2MM Skid Buffer which provides for -- registered outputs and supports bi-dir throttling. -- -- This Module also provides Write Data Bus Mirroring and WSTRB -- Demuxing to match a narrow Stream to a wider MMap Write -- Channel. By doing this in the skid buffer, the resource -- utilization of the skid buffer can be minimized by only -- having to buffer/mux the Stream data width, not the MMap -- Data width. -- ------------------------------------------------------------ I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_skid2mm_buf generic map ( C_MDATA_WIDTH => S2MM_MDATA_WIDTH , C_SDATA_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH ) port map ( -- System Ports ACLK => s2mm_aclk , ARST => sig_stream_rst , -- Slave Side (Wr Data Controller Input Side ) S_ADDR_LSB => sig_data2skid_addr_lsb, S_VALID => sig_data2skid_wvalid , S_READY => sig_skid2data_wready , S_Data => sig_data2skid_wdata , S_STRB => sig_data2skid_wstrb , S_Last => sig_data2skid_wlast , -- Master Side (MMap Write Data Output Side) M_VALID => sig_skid2axi_wvalid , M_READY => sig_axi2skid_wready , M_Data => sig_skid2axi_wdata , M_STRB => sig_skid2axi_wstrb , M_Last => sig_skid2axi_wlast ); --end generate ENABLE_AXIMMAP_SKID; end implementation;
-- -- Parameterisable N to M mux. -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- For Modelsim --use ieee.fixed_pkg.all; --use ieee.fixed_float_types.ALL; -- For ISE library ieee_proposed; use ieee_proposed.fixed_pkg.all; use IEEE.numeric_std.all; entity ParamExp is generic( BIT_TOP : integer := 20; BIT_BOTTOM : integer := -20); port( clk : In Std_logic; init_model : in STD_LOGIC; --signal to all components to go into their init state Start : In Std_logic; X : In sfixed(BIT_TOP downto BIT_BOTTOM); Done : Out Std_logic; Output : Out sfixed(BIT_TOP downto BIT_BOTTOM) ); end ParamExp; architecture RTL of ParamExp is type MEM is array (0 to 7) of sfixed(BIT_TOP downto BIT_BOTTOM); signal ISPOSITIVE : STD_LOGIC := '0'; signal ISGREATERTHANONE : STD_LOGIC := '0'; signal X_integer : sfixed(BIT_TOP downto 0); signal X_fraction : sfixed(0 downto BIT_BOTTOM); signal Output_int : sfixed(BIT_TOP downto BIT_BOTTOM); signal Done_int : Std_logic; signal output_fraction : sfixed(BIT_TOP downto BIT_BOTTOM); signal output_fraction_next : sfixed(BIT_TOP downto BIT_BOTTOM); signal current_term : sfixed(BIT_TOP downto BIT_BOTTOM); signal current_term_next : sfixed(BIT_TOP downto BIT_BOTTOM); signal COUNT_FRACTION : unsigned(3 downto 0); signal COUNT_FRACTION_next : unsigned(3 downto 0); signal DONEFRACTION : STD_LOGIC := '0'; signal DONEFRACTION_next : STD_LOGIC := '0'; signal output_integer : sfixed(BIT_TOP downto BIT_BOTTOM); signal output_integer_next : sfixed(BIT_TOP downto BIT_BOTTOM); signal COUNT_INTEGER : unsigned(BIT_TOP+1 downto 0); signal COUNT_INTEGER_next : unsigned(BIT_TOP+1 downto 0); signal DONEINTEGER : STD_LOGIC := '0'; signal DONEINTEGER_next : STD_LOGIC := '0'; signal E : sfixed(BIT_TOP downto BIT_BOTTOM) := to_sfixed(2.71828182845904523536028747135266249775724709369995,BIT_TOP,BIT_BOTTOM); signal EInv : sfixed(BIT_TOP downto BIT_BOTTOM) := resize(reciprocal(to_sfixed(2.71828182845904523536028747135266249775724709369995,BIT_TOP,BIT_BOTTOM)),BIT_TOP,BIT_BOTTOM); signal EMul : sfixed(BIT_TOP downto BIT_BOTTOM); signal n1: sfixed (BIT_TOP downto 0); signal n2: sfixed (n1'high + 1 downto n1'low); signal n3: ufixed (BIT_TOP + 1 downto 0); begin splitUpXProcess: process(X,X_integer,ispositive,E,EInv) begin X_integer <= resize(abs(X) - 0.5,BIT_TOP,0); X_fraction <= resize(abs(X) - X_integer,0,BIT_BOTTOM); if To_slv ( resize ( X ,BIT_TOP,BIT_BOTTOM))(BIT_TOP-BIT_BOTTOM) = '0' then ISPOSITIVE <= '1'; else ISPOSITIVE <= '0'; end if; if (ISPOSITIVE = '1') then EMul <= E; else EMul <= EInv; end if; end process splitUpXProcess; fractionCombProcess: process(COUNT_FRACTION,Start,output_fraction,current_term,X_fraction,ISPOSITIVE,current_term_next,init_model) variable MEM8Xsfixed : MEM := (to_sfixed (1,BIT_TOP, BIT_BOTTOM),to_sfixed (0.5,BIT_TOP, BIT_BOTTOM),to_sfixed (0.33333333,BIT_TOP, BIT_BOTTOM),to_sfixed (0.25,BIT_TOP, BIT_BOTTOM), to_sfixed (0.2,BIT_TOP, BIT_BOTTOM),to_sfixed (0.16666666667,BIT_TOP, BIT_BOTTOM),to_sfixed (0.142857142857,BIT_TOP, BIT_BOTTOM),to_sfixed (0.125,BIT_TOP, BIT_BOTTOM)); variable MEM8XsfixedOutTemp : sfixed(BIT_TOP downto BIT_BOTTOM); begin output_fraction_next <= output_fraction; COUNT_FRACTION_next <= COUNT_FRACTION; current_term_next <= current_term; DONEFRACTION_next <= '0'; MEM8XsfixedOutTemp := MEM8Xsfixed(to_integer(unsigned(COUNT_FRACTION(2 downto 0)))); current_term_next <= resize(MEM8XsfixedOutTemp * resize(X_fraction * current_term,BIT_TOP, BIT_BOTTOM),BIT_TOP, BIT_BOTTOM); if init_model = '1' then DONEFRACTION_next <= '1'; COUNT_FRACTION_next <= "1001"; output_fraction_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM); current_term_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM); else if Start = '1' then DONEFRACTION_next <= '0'; COUNT_FRACTION_next <= "0000"; output_fraction_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM); current_term_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM); elsif COUNT_FRACTION = "1001" then DONEFRACTION_next <= '1'; current_term_next <= current_term; else DONEFRACTION_next <= '0'; if (ISPOSITIVE = '1') then output_fraction_next <= resize(output_fraction + current_term_next,BIT_TOP, BIT_BOTTOM); else if (COUNT_FRACTION(0) = '0') then output_fraction_next <= resize(output_fraction - current_term_next,BIT_TOP, BIT_BOTTOM); else output_fraction_next <= resize(output_fraction + current_term_next,BIT_TOP, BIT_BOTTOM); end if; end if; COUNT_FRACTION_next <= COUNT_FRACTION + 1; end if; end if; end process fractionCombProcess; fractionSynProcess: process(clk) variable Sel : integer; begin if clk'event and clk = '1' then output_fraction <= output_fraction_next; COUNT_FRACTION <= COUNT_FRACTION_next; current_term <= current_term_next; DONEFRACTION <= DONEFRACTION_next; --report "The value of output_fraction = " & real'image(to_real(output_fraction)) & " and current_term " & -- real'image(to_real(current_term)); end if; end process fractionSynProcess; integerCombProcess: process(COUNT_INTEGER,output_integer,x_integer,Start,EMul,init_model) begin DONEINTEGER_next <= '0'; COUNT_INTEGER_next <= COUNT_INTEGER; output_integer_next <= output_integer; if init_model = '1' then DONEINTEGER_next <= '0'; COUNT_INTEGER_next <= to_unsigned(0,COUNT_INTEGER_next'length); output_integer_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM); else if Start = '1' then DONEINTEGER_next <= '0'; COUNT_INTEGER_next <= unsigned(ufixed(abs(X_integer))); output_integer_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM); else if COUNT_INTEGER = 0 then DONEINTEGER_next <= '1'; COUNT_INTEGER_next <= COUNT_INTEGER; output_integer_next <= output_integer; else DONEINTEGER_next <= '0'; output_integer_next <= resize(output_integer * EMul,BIT_TOP,BIT_BOTTOM); COUNT_INTEGER_next <= COUNT_INTEGER - 1; end if; end if; end if; end process integerCombProcess; integerSynProcess: process(clk,x_integer,count_integer,output_integer) begin COUNT_INTEGER <= COUNT_INTEGER; output_integer <= output_integer; if clk = '1' and clk'event then COUNT_INTEGER <= COUNT_INTEGER_next; output_integer <= output_integer_next; DONEINTEGER <= DONEINTEGER_next; end if; end process integerSynProcess; outputCombProcess: process(output_fraction,output_integer,DONEINTEGER,DONEFRACTION) begin Output_int <= resize(output_fraction * output_integer,BIT_TOP, BIT_BOTTOM); if DONEFRACTION = '1' and DONEINTEGER = '1' then Done_int <= '1'; else Done_int <= '0'; end if; end process outputCombProcess; Done <= Done_int; Output <= Output_int; --process (DONEFRACTION) --begin -- if (DONEFRACTION'event or DONEINTEGER'event) and DONEFRACTION = '1' and DONEINTEGER = '1' then -- report "The value of X_integer = " & real'image(to_real(X_integer)) & " and X_fraction " & real'image(to_real(X_fraction)); -- report "The value of exp( " & real'image(to_real(X)) & " ) = " & -- real'image(to_real(output_integer)) & " * " & real'image(to_real(output_fraction)); -- end if; --end process; end RTL;
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017 -- Date : Tue Oct 17 19:49:27 2017 -- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS -- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_led_controller_0_0_stub.vhdl -- Design : ip_design_led_controller_0_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is Port ( LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 ); s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s00_axi_awvalid : in STD_LOGIC; s00_axi_awready : out STD_LOGIC; s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s00_axi_wvalid : in STD_LOGIC; s00_axi_wready : out STD_LOGIC; s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s00_axi_bvalid : out STD_LOGIC; s00_axi_bready : in STD_LOGIC; s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 ); s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s00_axi_arvalid : in STD_LOGIC; s00_axi_arready : out STD_LOGIC; s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s00_axi_rvalid : out STD_LOGIC; s00_axi_rready : in STD_LOGIC; s00_axi_aclk : in STD_LOGIC; s00_axi_aresetn : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "LEDs_out[7:0],s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "led_controller_v1_0,Vivado 2017.3"; begin end;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc487.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s02b01x01p20n01i00487ent IS END c03s02b01x01p20n01i00487ent; ARCHITECTURE c03s02b01x01p20n01i00487arch OF c03s02b01x01p20n01i00487ent IS type MEM is array (positive range <>) of BIT; type ME1 is array (natural range <>) of Integer; subtype ME2 is ME1(0 to 3); subtype M1 is MEM (1 to 5); procedure F2 (X1 : inout MEM) is begin assert NOT((X1'LOW = 1) and (X1'High = 5)) report "*PASSED TEST: c03s02b01x01p20n01i00487" severity NOTE; assert ((X1'LOW = 1) and (X1'High = 5)) report "*FAILED TEST: c03s02b01x01p20n01i00487 - For an interface object of mode out, inout, or linkage, if the formal part does not contain a type conversion function, then the index ranges are obtained from the object denoted by the actual designator." severity ERROR; end F2; BEGIN TESTING: PROCESS variable S1 : M1 := "01110"; BEGIN F2(S1) ; -- No_failure_here wait; END PROCESS TESTING; END c03s02b01x01p20n01i00487arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc487.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s02b01x01p20n01i00487ent IS END c03s02b01x01p20n01i00487ent; ARCHITECTURE c03s02b01x01p20n01i00487arch OF c03s02b01x01p20n01i00487ent IS type MEM is array (positive range <>) of BIT; type ME1 is array (natural range <>) of Integer; subtype ME2 is ME1(0 to 3); subtype M1 is MEM (1 to 5); procedure F2 (X1 : inout MEM) is begin assert NOT((X1'LOW = 1) and (X1'High = 5)) report "*PASSED TEST: c03s02b01x01p20n01i00487" severity NOTE; assert ((X1'LOW = 1) and (X1'High = 5)) report "*FAILED TEST: c03s02b01x01p20n01i00487 - For an interface object of mode out, inout, or linkage, if the formal part does not contain a type conversion function, then the index ranges are obtained from the object denoted by the actual designator." severity ERROR; end F2; BEGIN TESTING: PROCESS variable S1 : M1 := "01110"; BEGIN F2(S1) ; -- No_failure_here wait; END PROCESS TESTING; END c03s02b01x01p20n01i00487arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc487.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s02b01x01p20n01i00487ent IS END c03s02b01x01p20n01i00487ent; ARCHITECTURE c03s02b01x01p20n01i00487arch OF c03s02b01x01p20n01i00487ent IS type MEM is array (positive range <>) of BIT; type ME1 is array (natural range <>) of Integer; subtype ME2 is ME1(0 to 3); subtype M1 is MEM (1 to 5); procedure F2 (X1 : inout MEM) is begin assert NOT((X1'LOW = 1) and (X1'High = 5)) report "*PASSED TEST: c03s02b01x01p20n01i00487" severity NOTE; assert ((X1'LOW = 1) and (X1'High = 5)) report "*FAILED TEST: c03s02b01x01p20n01i00487 - For an interface object of mode out, inout, or linkage, if the formal part does not contain a type conversion function, then the index ranges are obtained from the object denoted by the actual designator." severity ERROR; end F2; BEGIN TESTING: PROCESS variable S1 : M1 := "01110"; BEGIN F2(S1) ; -- No_failure_here wait; END PROCESS TESTING; END c03s02b01x01p20n01i00487arch;
entity assert4 is end entity; architecture test of assert4 is begin process is variable n : integer; begin n := 0; wait for 1 ns; assert n = 0 report integer'image(100 / n); wait; end process; end architecture;
entity assert4 is end entity; architecture test of assert4 is begin process is variable n : integer; begin n := 0; wait for 1 ns; assert n = 0 report integer'image(100 / n); wait; end process; end architecture;
entity assert4 is end entity; architecture test of assert4 is begin process is variable n : integer; begin n := 0; wait for 1 ns; assert n = 0 report integer'image(100 / n); wait; end process; end architecture;
entity assert4 is end entity; architecture test of assert4 is begin process is variable n : integer; begin n := 0; wait for 1 ns; assert n = 0 report integer'image(100 / n); wait; end process; end architecture;
entity assert4 is end entity; architecture test of assert4 is begin process is variable n : integer; begin n := 0; wait for 1 ns; assert n = 0 report integer'image(100 / n); wait; end process; end architecture;
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:axi_gpio:2.0 -- IP Revision: 6 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY axi_gpio_v2_0; USE axi_gpio_v2_0.axi_gpio; ENTITY base_zynq_design_axi_gpio_0_0 IS PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; ip2intc_irpt : OUT STD_LOGIC; gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); gpio2_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0) ); END base_zynq_design_axi_gpio_0_0; ARCHITECTURE base_zynq_design_axi_gpio_0_0_arch OF base_zynq_design_axi_gpio_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF base_zynq_design_axi_gpio_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT axi_gpio IS GENERIC ( C_FAMILY : STRING; C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER; C_GPIO_WIDTH : INTEGER; C_GPIO2_WIDTH : INTEGER; C_ALL_INPUTS : INTEGER; C_ALL_INPUTS_2 : INTEGER; C_ALL_OUTPUTS : INTEGER; C_ALL_OUTPUTS_2 : INTEGER; C_INTERRUPT_PRESENT : INTEGER; C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0); C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0); C_IS_DUAL : INTEGER; C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) ); PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; ip2intc_irpt : OUT STD_LOGIC; gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0); gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); gpio2_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0); gpio2_io_o : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); gpio2_io_t : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END COMPONENT axi_gpio; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF base_zynq_design_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2014.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF base_zynq_design_axi_gpio_0_0_arch : ARCHITECTURE IS "base_zynq_design_axi_gpio_0_0,axi_gpio,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF base_zynq_design_axi_gpio_0_0_arch: ARCHITECTURE IS "base_zynq_design_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=8,C_GPIO2_WIDTH=5,C_ALL_INPUTS=0,C_ALL_INPUTS_2=1,C_ALL_OUTPUTS=1,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=1,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=1,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O"; ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I"; BEGIN U0 : axi_gpio GENERIC MAP ( C_FAMILY => "zynq", C_S_AXI_ADDR_WIDTH => 9, C_S_AXI_DATA_WIDTH => 32, C_GPIO_WIDTH => 8, C_GPIO2_WIDTH => 5, C_ALL_INPUTS => 0, C_ALL_INPUTS_2 => 1, C_ALL_OUTPUTS => 1, C_ALL_OUTPUTS_2 => 0, C_INTERRUPT_PRESENT => 1, C_DOUT_DEFAULT => X"00000000", C_TRI_DEFAULT => X"FFFFFFFF", C_IS_DUAL => 1, C_DOUT_DEFAULT_2 => X"00000000", C_TRI_DEFAULT_2 => X"FFFFFFFF" ) PORT MAP ( s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_awaddr => s_axi_awaddr, s_axi_awvalid => s_axi_awvalid, s_axi_awready => s_axi_awready, s_axi_wdata => s_axi_wdata, s_axi_wstrb => s_axi_wstrb, s_axi_wvalid => s_axi_wvalid, s_axi_wready => s_axi_wready, s_axi_bresp => s_axi_bresp, s_axi_bvalid => s_axi_bvalid, s_axi_bready => s_axi_bready, s_axi_araddr => s_axi_araddr, s_axi_arvalid => s_axi_arvalid, s_axi_arready => s_axi_arready, s_axi_rdata => s_axi_rdata, s_axi_rresp => s_axi_rresp, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready, ip2intc_irpt => ip2intc_irpt, gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), gpio_io_o => gpio_io_o, gpio2_io_i => gpio2_io_i ); END base_zynq_design_axi_gpio_0_0_arch;
entity ent is end entity; library ieee; use ieee.std_logic_1164.all; package avmm_csr_pkg is type avmm_csr_array_t is array (natural range <>) of std_logic_vector(31 downto 0); end avmm_csr_pkg; library ieee; use work.avmm_csr_pkg.all; entity avmm_csr is Port ( reg_i : in avmm_csr_array_t ); end avmm_csr; architecture rtl of avmm_csr is begin end rtl; library ieee; use ieee.numeric_std_unsigned.all; entity dut is end entity dut; architecture rtl of dut is signal int : natural; begin inst : entity work.avmm_csr port map ( reg_i(0) => to_slv(int, 32) ); end architecture rtl;
-- ######################################################################## -- $Software: busiac -- $section : hardware component -- $Id: plus12.vhd 325 2015-06-03 12:47:32Z ia $ -- $HeadURL: svn://lunix120.ensiie.fr/ia/cours/archi/projet/busiac/vhdl/plus12.vhd $ -- $Author : Ivan Auge (Email: auge@ensiie.fr) -- ######################################################################## -- -- This file is part of the BUSIAC software: Copyright (C) 2010 by I. Auge. -- -- This program is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at your -- option) any later version. -- -- BUSIAC software is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY ; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General -- Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with the GNU C Library; see the file COPYING. If not, write to the Free -- Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -- -- ######################################################################*/ ------------------------------------------------------------------------------- -- Ce module additionne 2 nombres de 12 bits signés. -- Ses E/S sont les bus busin et busout. -- -- Input: -- busin_ctl (43 DOWNTO 40) : not used -- busin_asrc(39 DOWNTO 32) : adresse emetteur (E_ADR) -- busin_ades(31 DOWNTO 24) : adresse destination (MYADR) -- busin_data(23 DOWNTO 12) : operande B en complement a 2 -- busin_data(11 DOWNTO 0) : operande A en complement a 2 -- -- Output: -- busout_ctl (43 DOWNTO 40) : "0000" -- busout_asrc(39 DOWNTO 32) : MYADR -- busout_ades(31 DOWNTO 24) : E_ADR -- busout_data(23) : V (overflow) -- busout_data(22) : C (retenue sortante) -- busout_data(21) : N (résultat négatif) -- busout_data(20) : Z (résultat nul) -- busout_data(19 DOWNTO 12) : "00000000" -- busout_data(11 DOWNTO 0) : résultat en complément a 2 (A+B) ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; use IEEE.numeric_std.all; ENTITY plus12 IS GENERIC( MYADR : STD_LOGIC_VECTOR(7 downto 0) := x"C0" ); -- 192 PORT( clk : IN STD_LOGIC; reset : IN STD_LOGIC; -- interface busin busin : in STD_LOGIC_VECTOR(43 DOWNTO 0); busin_valid : in STD_LOGIC; busin_eated : out STD_LOGIC; -- interface busout busout : OUT STD_LOGIC_VECTOR(43 DOWNTO 0); busout_valid : OUT STD_LOGIC; busout_eated : IN STD_LOGIC; -- debug debug : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END plus12; ARCHITECTURE Montage OF plus12 IS TYPE T_CMD_LoadNoop IS (LOAD, NOOP); -- partie operative -- le registre de transfert de busin vers busout SIGNAL CMD_tft : T_CMD_LoadNoop; SIGNAL R_tft : STD_LOGIC_VECTOR(43 DOWNTO 0); -- le registre resultat de A+B, ov -- on etend R sur 13 bits pour avoir la retenue SIGNAL CMD_res : T_CMD_LoadNoop; SIGNAL R_res : STD_LOGIC_VECTOR(12 DOWNTO 0); -- les operandes A et B (1 bit de plus pour la retenue) SIGNAL A,B : STD_LOGIC_VECTOR (12 DOWNTO 0); -- V1 -- bits de retenue et de somme de A+B -- V1 SIGNAL r,s : STD_LOGIC_VECTOR (12 DOWNTO 0); -- V1 -- SIGNAL A,B : SIGNED (12 DOWNTO 0); -- V2 -- l' adresse destination SIGNAL busin_ades : STD_LOGIC_VECTOR ( 7 DOWNTO 0); -- message résulat SIGNAL mess_resultat : STD_LOGIC_VECTOR (43 DOWNTO 0); -- partie controle TYPE STATE_TYPE IS (ST_READ, ST_WRITE_TFT, ST_COMPUTE, ST_WRITE_SUM); SIGNAL state : STATE_TYPE; BEGIN ------------------------------------------------------------------------------- -- Partie Opérative ------------------------------------------------------------------------------- busin_ades <= busin(31 DOWNTO 24) ; a <= "0" & R_tft(23 DOWNTO 12) ; -- V1 b <= "0" & R_tft(11 DOWNTO 0) ; -- V1 -- a <= SIGNED (R_tft(23 DOWNTO 12)) ; -- V2 -- b <= SIGNED (R_tft(11 DOWNTO 0)) ; -- V2 mess_resultat(43 DOWNTO 40) <= "0000"; mess_resultat(39 DOWNTO 32) <= MYADR; mess_resultat(31 DOWNTO 24) <= R_tft(39 DOWNTO 32); mess_resultat(23) <= -- overflow '1' WHEN a(11)='1' AND b(11)='1' AND R_res(11)='0' ELSE -- N+N=P '1' WHEN a(11)='0' AND b(11)='0' AND R_res(11)='1' ELSE -- P+P=N '0' ; mess_resultat(22) <= R_res(12); -- cout mess_resultat(21) <= R_res(11); -- signe mess_resultat(20) <= -- null '1' WHEN R_res(11 downto 0) = x"000" ELSE '0'; mess_resultat(19 DOWNTO 12) <= "00000000" ; mess_resultat(11 DOWNTO 0) <= R_res(11 DOWNTO 0); -- s,r <-- a + b; -- V1 s <= a XOR b XOR r; -- V1 r(0) <= '0'; -- V1 r(12 DOWNTO 1) <= -- V1 ( a(11 DOWNTO 0) AND b(11 DOWNTO 0) ) OR -- V1 ( a(11 DOWNTO 0) AND r(11 DOWNTO 0) ) OR -- V1 ( r(11 DOWNTO 0) AND b(11 DOWNTO 0) ); -- V1 PROCESS (clk) BEGIN IF clk'EVENT AND clk = '1' THEN -- R_tft if ( CMD_tft = LOAD ) then R_tft <= busin; end if; -- R_res if ( CMD_res = LOAD ) then R_res(12 DOWNTO 0) <= s ; -- V1 -- R_res(12 DOWNTO 0) <= STD_LOGIC_VECTOR(a + b) ; -- V2 end if; END IF; END PROCESS; ------------------------------------------------------------------------------- -- Partie Controle ------------------------------------------------------------------------------- -- Inputs: busin_valid busout_eated -- Outputs: busin_eated busout_valid, CMD_res, CMD_tft, busout ------------------------------------------------------------------------------- -- fonction de transitition PROCESS (reset,clk) BEGIN IF reset = '1' THEN state <= ST_READ; ELSIF clk'EVENT AND clk = '1' THEN CASE state IS WHEN ST_READ => IF busin_valid = '1' and busin_ades = MYADR THEN state <= ST_COMPUTE; ELSIF busin_valid = '1' and busin_ades /= MYADR THEN state <= ST_WRITE_TFT; END IF; WHEN ST_COMPUTE => state <= ST_WRITE_SUM; WHEN ST_WRITE_SUM => IF busout_eated = '1' THEN state <= ST_READ; END IF; WHEN ST_WRITE_TFT => IF busout_eated = '1' THEN state <= ST_READ; END IF; END CASE; END IF; END PROCESS; -- fonction de sortie WITH state SELECT busin_eated <= '1' WHEN ST_READ, '0' WHEN OTHERS; WITH state SELECT busout_valid <= '1' WHEN ST_WRITE_TFT, '1' WHEN ST_WRITE_SUM, '0' WHEN OTHERS; WITH state SELECT CMD_res <= LOAD WHEN ST_Compute, NOOP WHEN OTHERS; WITH state SELECT CMD_tft <= LOAD WHEN ST_READ, NOOP WHEN OTHERS; WITH state SELECT busout <= mess_resultat WHEN ST_WRITE_SUM, R_tft WHEN OTHERS; END Montage;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 17:52:30 04/03/2013 -- Design Name: -- Module Name: muxx - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity muxx is Port ( S : in bit_VECTOR (1 downto 0); A : in STD_LOGIC_VECTOR (3 downto 0); D : out STD_LOGIC); end muxx; architecture Behavioral of muxx is begin process(s) --variable d : std_logic; begin case s is when "00" => d <= A(0); when "01" => d <= A(1); when "10" => d <= A(2); when "11" => d <= A(3); end case; -- D <= d; end process; end Behavioral;
-- ------------------------------------------------------------- -- -- File Name: hdlsrc/fft_16_bit/FFT_HDL_Optimized.vhd -- Created: 2017-03-27 23:13:58 -- -- Generated by MATLAB 9.1 and HDL Coder 3.9 -- -- ------------------------------------------------------------- -- ------------------------------------------------------------- -- -- Module: FFT_HDL_Optimized -- Source Path: fft_16_bit/FFT HDL Optimized -- Hierarchy Level: 1 -- -- FFT HDL Optimized -- -- ------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; USE work.fft_16_bit_pkg.ALL; ENTITY FFT_HDL_Optimized IS PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dataIn : IN vector_of_std_logic_vector16(0 TO 15); -- uint16 [16] validIn : IN std_logic; dataOut_re : OUT vector_of_std_logic_vector21(0 TO 15); -- sfix21 [16] dataOut_im : OUT vector_of_std_logic_vector21(0 TO 15); -- sfix21 [16] validOut : OUT std_logic ); END FFT_HDL_Optimized; ARCHITECTURE rtl OF FFT_HDL_Optimized IS -- Component Declarations COMPONENT RADIX22FFT_SDNF1_1 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_1_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_1_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_9_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_9_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_1_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_1_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_2_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_2_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_1_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_1_block3 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_5_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_5_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_13_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_13_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_9_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_9_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_10_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_10_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_9_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_2 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_1 : IN std_logic; -- ufix1 dout_1_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_1_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_9_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_9_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_1_re_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_1_im_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_1_block PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_2_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_2_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_10_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_10_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_3_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_3_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_4_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_4_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_3_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_1_block4 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_6_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_6_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_14_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_14_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_11_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_11_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_12_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_12_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_11_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_2_block PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_3 : IN std_logic; -- ufix1 dout_3_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_3_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_11_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_11_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_3_re_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_3_im_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_4_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_4_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_2 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_2_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_2_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_2_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLMULT_SDNF1_3 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_1_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_1_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_3_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_3_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : IN std_logic; twdl_3_1_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_1_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_2_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_2_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_2_vld : IN std_logic; softReset : IN std_logic; twdlXdin_1_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_2_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_2_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_1_block1 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_3_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_3_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_11_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_11_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_5_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_5_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_6_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_6_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_5_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_1_block5 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_7_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_7_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_15_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_15_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_13_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_13_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_14_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_14_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_13_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_2_block1 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_5 : IN std_logic; -- ufix1 dout_5_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_5_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_13_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_13_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_5_re_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_5_im_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_6_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_6_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_1_block2 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_4_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_4_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_12_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_12_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_7_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_7_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_8_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_8_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_7_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_1_block6 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_8_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_8_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_16_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_16_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_15_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_15_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_16_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_16_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_15_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_2_block2 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_7 : IN std_logic; -- ufix1 dout_7_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_7_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_15_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_15_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_7_re_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_7_im_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_8_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_8_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_3 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_3_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_3_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_3_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_4 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_4_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_4_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_4_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLMULT_SDNF1_3_block PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_5_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_5_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_7_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_7_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : IN std_logic; twdl_3_3_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_3_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_4_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_4_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_4_vld : IN std_logic; softReset : IN std_logic; twdlXdin_3_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_3_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_4_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_4_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_3_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_3 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_1_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_3_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_3_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_1_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_1_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_2_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_2_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_1_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_3_block PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_2_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_2_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_4_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_4_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_3_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_3_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_4_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_4_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_3_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_4 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_1 : IN std_logic; -- ufix1 dout_1_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_1_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_3_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_3_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_1_re_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_1_im_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_2_re : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_2_im : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_4_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_4_block PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_3 : IN std_logic; -- ufix1 dout_2_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_2_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_4_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_4_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_3_re : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_3_im : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_4_re_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_4_im_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_4_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_6 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_6_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_6_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_6_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLMULT_SDNF1_3_block1 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_4_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_4_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : IN std_logic; twdl_3_5_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_5_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_6_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_6_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_6_vld : IN std_logic; softReset : IN std_logic; twdlXdin_5_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_5_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_6_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_6_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_5_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_7 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_7_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_7_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_7_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_8 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_8_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_8_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_8_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLMULT_SDNF1_3_block2 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_6_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_6_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_8_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_8_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : IN std_logic; twdl_3_7_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_7_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_8_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_8_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_8_vld : IN std_logic; softReset : IN std_logic; twdlXdin_7_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_7_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_8_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_8_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_7_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_3_block1 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_5_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_5_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_7_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_7_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_5_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_5_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_6_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_6_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_5_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_3_block2 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_6_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_6_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_8_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_8_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_7_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_7_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_8_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_8_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_7_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_4_block1 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_5 : IN std_logic; -- ufix1 dout_5_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_5_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_7_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_7_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_5_re_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_5_im_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_6_re : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_6_im : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_4_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_4_block2 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_7 : IN std_logic; -- ufix1 dout_6_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_6_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_8_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_8_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_7_re : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_7_im : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_8_re_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_8_im_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_4_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_2_block3 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_9 : IN std_logic; -- ufix1 dout_2_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_2_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_10_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_10_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_9_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_9_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_10_re_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_10_im_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_2_block4 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_11 : IN std_logic; -- ufix1 dout_4_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_4_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_12_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_12_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_11_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_11_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_12_re_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_12_im_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_10 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_10_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_10_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_10_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLMULT_SDNF1_3_block3 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_9_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_9_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_11_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_11_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : IN std_logic; twdl_3_9_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_9_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_10_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_10_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_10_vld : IN std_logic; softReset : IN std_logic; twdlXdin_9_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_9_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_10_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_10_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_9_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_2_block5 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_13 : IN std_logic; -- ufix1 dout_6_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_6_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_14_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_14_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_13_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_13_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_14_re_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_14_im_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_2_block6 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_15 : IN std_logic; -- ufix1 dout_8_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_8_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_16_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_16_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_15_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_15_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_16_re_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_16_im_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_11 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_11_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_11_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_11_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_12 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_12_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_12_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_12_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLMULT_SDNF1_3_block4 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_13_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_13_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_15_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_15_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : IN std_logic; twdl_3_11_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_11_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_12_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_12_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_12_vld : IN std_logic; softReset : IN std_logic; twdlXdin_11_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_11_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_12_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_12_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_11_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_3_block3 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_9_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_9_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_11_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_11_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_9_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_9_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_10_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_10_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_9_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_3_block4 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_10_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_10_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_12_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_12_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_11_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_11_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_12_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_12_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_11_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_4_block3 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_9 : IN std_logic; -- ufix1 dout_9_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_9_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_11_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_11_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_9_re_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_9_im_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_10_re : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_10_im : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_4_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_4_block4 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_11 : IN std_logic; -- ufix1 dout_10_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_10_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_12_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_12_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_11_re : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_11_im : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_12_re_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_12_im_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_4_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_14 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_14_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_14_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_14_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLMULT_SDNF1_3_block5 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_10_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_10_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_12_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_12_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : IN std_logic; twdl_3_13_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_13_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_14_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_14_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_14_vld : IN std_logic; softReset : IN std_logic; twdlXdin_13_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_13_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_14_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_14_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_13_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_15 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_15_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_15_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_15_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_16 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_16_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_16_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_16_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLMULT_SDNF1_3_block6 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_14_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_14_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_16_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_16_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : IN std_logic; twdl_3_15_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_15_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_16_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_16_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_16_vld : IN std_logic; softReset : IN std_logic; twdlXdin_15_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_15_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_16_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_16_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_15_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_3_block5 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_13_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_13_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_15_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_15_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_13_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_13_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_14_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_14_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_13_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_3_block6 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_14_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_14_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_16_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_16_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_15_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_15_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_16_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_16_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_15_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_4_block5 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_13 : IN std_logic; -- ufix1 dout_13_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_13_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_15_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_15_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_13_re_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_13_im_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_14_re : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_14_im : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_4_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_4_block6 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_15 : IN std_logic; -- ufix1 dout_14_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_14_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_16_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_16_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_15_re : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_15_im : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_16_re_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_16_im_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_4_vld : OUT std_logic ); END COMPONENT; -- Component Configuration Statements FOR ALL : RADIX22FFT_SDNF1_1 USE ENTITY work.RADIX22FFT_SDNF1_1(rtl); FOR ALL : RADIX22FFT_SDNF1_1_block3 USE ENTITY work.RADIX22FFT_SDNF1_1_block3(rtl); FOR ALL : RADIX22FFT_SDNF2_2 USE ENTITY work.RADIX22FFT_SDNF2_2(rtl); FOR ALL : RADIX22FFT_SDNF1_1_block USE ENTITY work.RADIX22FFT_SDNF1_1_block(rtl); FOR ALL : RADIX22FFT_SDNF1_1_block4 USE ENTITY work.RADIX22FFT_SDNF1_1_block4(rtl); FOR ALL : RADIX22FFT_SDNF2_2_block USE ENTITY work.RADIX22FFT_SDNF2_2_block(rtl); FOR ALL : TWDLROM_3_2 USE ENTITY work.TWDLROM_3_2(rtl); FOR ALL : TWDLMULT_SDNF1_3 USE ENTITY work.TWDLMULT_SDNF1_3(rtl); FOR ALL : RADIX22FFT_SDNF1_1_block1 USE ENTITY work.RADIX22FFT_SDNF1_1_block1(rtl); FOR ALL : RADIX22FFT_SDNF1_1_block5 USE ENTITY work.RADIX22FFT_SDNF1_1_block5(rtl); FOR ALL : RADIX22FFT_SDNF2_2_block1 USE ENTITY work.RADIX22FFT_SDNF2_2_block1(rtl); FOR ALL : RADIX22FFT_SDNF1_1_block2 USE ENTITY work.RADIX22FFT_SDNF1_1_block2(rtl); FOR ALL : RADIX22FFT_SDNF1_1_block6 USE ENTITY work.RADIX22FFT_SDNF1_1_block6(rtl); FOR ALL : RADIX22FFT_SDNF2_2_block2 USE ENTITY work.RADIX22FFT_SDNF2_2_block2(rtl); FOR ALL : TWDLROM_3_3 USE ENTITY work.TWDLROM_3_3(rtl); FOR ALL : TWDLROM_3_4 USE ENTITY work.TWDLROM_3_4(rtl); FOR ALL : TWDLMULT_SDNF1_3_block USE ENTITY work.TWDLMULT_SDNF1_3_block(rtl); FOR ALL : RADIX22FFT_SDNF1_3 USE ENTITY work.RADIX22FFT_SDNF1_3(rtl); FOR ALL : RADIX22FFT_SDNF1_3_block USE ENTITY work.RADIX22FFT_SDNF1_3_block(rtl); FOR ALL : RADIX22FFT_SDNF2_4 USE ENTITY work.RADIX22FFT_SDNF2_4(rtl); FOR ALL : RADIX22FFT_SDNF2_4_block USE ENTITY work.RADIX22FFT_SDNF2_4_block(rtl); FOR ALL : TWDLROM_3_6 USE ENTITY work.TWDLROM_3_6(rtl); FOR ALL : TWDLMULT_SDNF1_3_block1 USE ENTITY work.TWDLMULT_SDNF1_3_block1(rtl); FOR ALL : TWDLROM_3_7 USE ENTITY work.TWDLROM_3_7(rtl); FOR ALL : TWDLROM_3_8 USE ENTITY work.TWDLROM_3_8(rtl); FOR ALL : TWDLMULT_SDNF1_3_block2 USE ENTITY work.TWDLMULT_SDNF1_3_block2(rtl); FOR ALL : RADIX22FFT_SDNF1_3_block1 USE ENTITY work.RADIX22FFT_SDNF1_3_block1(rtl); FOR ALL : RADIX22FFT_SDNF1_3_block2 USE ENTITY work.RADIX22FFT_SDNF1_3_block2(rtl); FOR ALL : RADIX22FFT_SDNF2_4_block1 USE ENTITY work.RADIX22FFT_SDNF2_4_block1(rtl); FOR ALL : RADIX22FFT_SDNF2_4_block2 USE ENTITY work.RADIX22FFT_SDNF2_4_block2(rtl); FOR ALL : RADIX22FFT_SDNF2_2_block3 USE ENTITY work.RADIX22FFT_SDNF2_2_block3(rtl); FOR ALL : RADIX22FFT_SDNF2_2_block4 USE ENTITY work.RADIX22FFT_SDNF2_2_block4(rtl); FOR ALL : TWDLROM_3_10 USE ENTITY work.TWDLROM_3_10(rtl); FOR ALL : TWDLMULT_SDNF1_3_block3 USE ENTITY work.TWDLMULT_SDNF1_3_block3(rtl); FOR ALL : RADIX22FFT_SDNF2_2_block5 USE ENTITY work.RADIX22FFT_SDNF2_2_block5(rtl); FOR ALL : RADIX22FFT_SDNF2_2_block6 USE ENTITY work.RADIX22FFT_SDNF2_2_block6(rtl); FOR ALL : TWDLROM_3_11 USE ENTITY work.TWDLROM_3_11(rtl); FOR ALL : TWDLROM_3_12 USE ENTITY work.TWDLROM_3_12(rtl); FOR ALL : TWDLMULT_SDNF1_3_block4 USE ENTITY work.TWDLMULT_SDNF1_3_block4(rtl); FOR ALL : RADIX22FFT_SDNF1_3_block3 USE ENTITY work.RADIX22FFT_SDNF1_3_block3(rtl); FOR ALL : RADIX22FFT_SDNF1_3_block4 USE ENTITY work.RADIX22FFT_SDNF1_3_block4(rtl); FOR ALL : RADIX22FFT_SDNF2_4_block3 USE ENTITY work.RADIX22FFT_SDNF2_4_block3(rtl); FOR ALL : RADIX22FFT_SDNF2_4_block4 USE ENTITY work.RADIX22FFT_SDNF2_4_block4(rtl); FOR ALL : TWDLROM_3_14 USE ENTITY work.TWDLROM_3_14(rtl); FOR ALL : TWDLMULT_SDNF1_3_block5 USE ENTITY work.TWDLMULT_SDNF1_3_block5(rtl); FOR ALL : TWDLROM_3_15 USE ENTITY work.TWDLROM_3_15(rtl); FOR ALL : TWDLROM_3_16 USE ENTITY work.TWDLROM_3_16(rtl); FOR ALL : TWDLMULT_SDNF1_3_block6 USE ENTITY work.TWDLMULT_SDNF1_3_block6(rtl); FOR ALL : RADIX22FFT_SDNF1_3_block5 USE ENTITY work.RADIX22FFT_SDNF1_3_block5(rtl); FOR ALL : RADIX22FFT_SDNF1_3_block6 USE ENTITY work.RADIX22FFT_SDNF1_3_block6(rtl); FOR ALL : RADIX22FFT_SDNF2_4_block5 USE ENTITY work.RADIX22FFT_SDNF2_4_block5(rtl); FOR ALL : RADIX22FFT_SDNF2_4_block6 USE ENTITY work.RADIX22FFT_SDNF2_4_block6(rtl); -- Signals SIGNAL rotate_1 : std_logic; -- ufix1 SIGNAL rotate_1_1 : std_logic; -- ufix1 SIGNAL dataIn_0 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_1_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_1_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_8 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_9_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_9_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL twdlXdin_1_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_1_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_9_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_9_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_1_vld : std_logic; SIGNAL softReset : std_logic; SIGNAL dout_1_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_1_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_2_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_2_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_1_vld : std_logic; SIGNAL dataIn_4 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_5_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_5_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_12 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_13_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_13_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL twdlXdin_5_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_5_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_13_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_13_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL dout_9_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_9_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_10_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_10_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_9_vld : std_logic; SIGNAL dout_1_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_1_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_2_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_2_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_2_vld : std_logic; SIGNAL rotate_3 : std_logic; -- ufix1 SIGNAL dataIn_1 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_2_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_2_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_9 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_10_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_10_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL twdlXdin_2_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_2_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_10_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_10_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL dout_3_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_3_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_4_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_4_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_3_vld : std_logic; SIGNAL dataIn_5 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_6_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_6_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_13 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_14_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_14_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL twdlXdin_6_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_6_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_14_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_14_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL dout_11_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_11_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_12_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_12_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_11_vld : std_logic; SIGNAL dout_3_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_3_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_4_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_4_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_2_vld_1 : std_logic; SIGNAL twdl_3_1_re : signed(16 DOWNTO 0); -- sfix17_En15 SIGNAL twdl_3_1_im : signed(16 DOWNTO 0); -- sfix17_En15 SIGNAL twdl_3_2_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_2_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_2_vld : std_logic; SIGNAL twdlXdin_1_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_1_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_2_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_2_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_1_vld_1 : std_logic; SIGNAL rotate_5 : std_logic; -- ufix1 SIGNAL dataIn_2 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_3_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_3_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_10 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_11_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_11_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL twdlXdin_3_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_3_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_11_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_11_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL dout_5_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_5_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_6_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_6_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_5_vld : std_logic; SIGNAL dataIn_6 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_7_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_7_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_14 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_15_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_15_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL twdlXdin_7_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_7_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_15_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_15_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL dout_13_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_13_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_14_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_14_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_13_vld : std_logic; SIGNAL dout_5_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_5_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_6_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_6_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_2_vld_2 : std_logic; SIGNAL rotate_7 : std_logic; -- ufix1 SIGNAL dataIn_3 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_4_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_4_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_11 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_12_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_12_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL twdlXdin_4_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_4_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_12_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_12_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL dout_7_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_7_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_8_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_8_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_7_vld : std_logic; SIGNAL dataIn_7 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_8_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_8_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_15 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_16_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_16_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL twdlXdin_8_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_8_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_16_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_16_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL dout_15_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_15_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_16_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_16_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_15_vld : std_logic; SIGNAL dout_7_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_7_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_8_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_8_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_2_vld_3 : std_logic; SIGNAL twdl_3_3_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_3_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_3_vld : std_logic; SIGNAL twdl_3_4_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_4_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_4_vld : std_logic; SIGNAL twdlXdin_3_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_3_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_4_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_4_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_3_vld : std_logic; SIGNAL dout_1_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_1_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_2_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_2_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_1_vld_1 : std_logic; SIGNAL dout_3_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_3_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_4_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_4_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_3_vld_1 : std_logic; SIGNAL dout_4_vld : std_logic; SIGNAL rotate_3_1 : std_logic; -- ufix1 SIGNAL dout_4_vld_1 : std_logic; SIGNAL rotate_5_1 : std_logic; -- ufix1 SIGNAL twdl_3_5_re : signed(16 DOWNTO 0); -- sfix17_En15 SIGNAL twdl_3_5_im : signed(16 DOWNTO 0); -- sfix17_En15 SIGNAL twdl_3_6_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_6_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_6_vld : std_logic; SIGNAL twdlXdin_5_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_5_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_6_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_6_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_5_vld : std_logic; SIGNAL twdl_3_7_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_7_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_7_vld : std_logic; SIGNAL twdl_3_8_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_8_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_8_vld : std_logic; SIGNAL twdlXdin_7_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_7_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_8_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_8_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_7_vld : std_logic; SIGNAL dout_5_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_5_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_6_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_6_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_5_vld_1 : std_logic; SIGNAL dout_7_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_7_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_8_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_8_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_7_vld_1 : std_logic; SIGNAL dout_4_vld_2 : std_logic; SIGNAL rotate_7_1 : std_logic; -- ufix1 SIGNAL dout_4_vld_3 : std_logic; SIGNAL rotate_9 : std_logic; -- ufix1 SIGNAL rotate_9_1 : std_logic; -- ufix1 SIGNAL dout_9_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_9_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_10_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_10_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_2_vld_4 : std_logic; SIGNAL rotate_11 : std_logic; -- ufix1 SIGNAL dout_11_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_11_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_12_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_12_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_2_vld_5 : std_logic; SIGNAL twdl_3_9_re : signed(16 DOWNTO 0); -- sfix17_En15 SIGNAL twdl_3_9_im : signed(16 DOWNTO 0); -- sfix17_En15 SIGNAL twdl_3_10_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_10_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_10_vld : std_logic; SIGNAL twdlXdin_9_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_9_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_10_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_10_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_9_vld : std_logic; SIGNAL rotate_13 : std_logic; -- ufix1 SIGNAL dout_13_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_13_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_14_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_14_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_2_vld_6 : std_logic; SIGNAL rotate_15 : std_logic; -- ufix1 SIGNAL dout_15_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_15_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_16_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_16_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_2_vld_7 : std_logic; SIGNAL twdl_3_11_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_11_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_11_vld : std_logic; SIGNAL twdl_3_12_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_12_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_12_vld : std_logic; SIGNAL twdlXdin_11_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_11_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_12_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_12_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_11_vld : std_logic; SIGNAL dout_9_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_9_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_10_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_10_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_9_vld_1 : std_logic; SIGNAL dout_11_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_11_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_12_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_12_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_11_vld_1 : std_logic; SIGNAL dout_4_vld_4 : std_logic; SIGNAL rotate_11_1 : std_logic; -- ufix1 SIGNAL dout_4_vld_5 : std_logic; SIGNAL rotate_13_1 : std_logic; -- ufix1 SIGNAL twdl_3_13_re : signed(16 DOWNTO 0); -- sfix17_En15 SIGNAL twdl_3_13_im : signed(16 DOWNTO 0); -- sfix17_En15 SIGNAL twdl_3_14_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_14_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_14_vld : std_logic; SIGNAL twdlXdin_13_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_13_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_14_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_14_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_13_vld : std_logic; SIGNAL twdl_3_15_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_15_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_15_vld : std_logic; SIGNAL twdl_3_16_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_16_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_16_vld : std_logic; SIGNAL twdlXdin_15_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_15_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_16_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_16_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_15_vld : std_logic; SIGNAL dout_13_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_13_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_14_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_14_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_13_vld_1 : std_logic; SIGNAL dout_15_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_15_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_16_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_16_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_15_vld_1 : std_logic; SIGNAL dout_4_vld_6 : std_logic; SIGNAL rotate_15_1 : std_logic; -- ufix1 SIGNAL dout_4_vld_7 : std_logic; SIGNAL dataOut_re_tmp : vector_of_std_logic_vector21(0 TO 15); -- ufix21 [16] SIGNAL dataOut_im_tmp : vector_of_std_logic_vector21(0 TO 15); -- ufix21 [16] BEGIN u_SDNF1_1_1 : RADIX22FFT_SDNF1_1 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_1_re => std_logic_vector(twdlXdin_1_re), -- sfix18 twdlXdin_1_im => std_logic_vector(twdlXdin_1_im), -- sfix18 twdlXdin_9_re => std_logic_vector(twdlXdin_9_re), -- sfix18 twdlXdin_9_im => std_logic_vector(twdlXdin_9_im), -- sfix18 twdlXdin_1_vld => twdlXdin_1_vld, softReset => softReset, dout_1_re => dout_1_re, -- sfix18 dout_1_im => dout_1_im, -- sfix18 dout_2_re => dout_2_re, -- sfix18 dout_2_im => dout_2_im, -- sfix18 dout_1_vld => dout_1_vld ); u_SDNF1_1_9 : RADIX22FFT_SDNF1_1_block3 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_5_re => std_logic_vector(twdlXdin_5_re), -- sfix18 twdlXdin_5_im => std_logic_vector(twdlXdin_5_im), -- sfix18 twdlXdin_13_re => std_logic_vector(twdlXdin_13_re), -- sfix18 twdlXdin_13_im => std_logic_vector(twdlXdin_13_im), -- sfix18 twdlXdin_1_vld => twdlXdin_1_vld, softReset => softReset, dout_9_re => dout_9_re, -- sfix18 dout_9_im => dout_9_im, -- sfix18 dout_10_re => dout_10_re, -- sfix18 dout_10_im => dout_10_im, -- sfix18 dout_9_vld => dout_9_vld ); u_SDNF2_2_1 : RADIX22FFT_SDNF2_2 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_1 => rotate_1_1, -- ufix1 dout_1_re => dout_1_re, -- sfix18 dout_1_im => dout_1_im, -- sfix18 dout_9_re => dout_9_re, -- sfix18 dout_9_im => dout_9_im, -- sfix18 dout_1_vld => dout_1_vld, softReset => softReset, dout_1_re_1 => dout_1_re_1, -- sfix19 dout_1_im_1 => dout_1_im_1, -- sfix19 dout_2_re => dout_2_re_1, -- sfix19 dout_2_im => dout_2_im_1, -- sfix19 dout_2_vld => dout_2_vld ); u_SDNF1_1_3 : RADIX22FFT_SDNF1_1_block PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_2_re => std_logic_vector(twdlXdin_2_re), -- sfix18 twdlXdin_2_im => std_logic_vector(twdlXdin_2_im), -- sfix18 twdlXdin_10_re => std_logic_vector(twdlXdin_10_re), -- sfix18 twdlXdin_10_im => std_logic_vector(twdlXdin_10_im), -- sfix18 twdlXdin_1_vld => twdlXdin_1_vld, softReset => softReset, dout_3_re => dout_3_re, -- sfix18 dout_3_im => dout_3_im, -- sfix18 dout_4_re => dout_4_re, -- sfix18 dout_4_im => dout_4_im, -- sfix18 dout_3_vld => dout_3_vld ); u_SDNF1_1_11 : RADIX22FFT_SDNF1_1_block4 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_6_re => std_logic_vector(twdlXdin_6_re), -- sfix18 twdlXdin_6_im => std_logic_vector(twdlXdin_6_im), -- sfix18 twdlXdin_14_re => std_logic_vector(twdlXdin_14_re), -- sfix18 twdlXdin_14_im => std_logic_vector(twdlXdin_14_im), -- sfix18 twdlXdin_1_vld => twdlXdin_1_vld, softReset => softReset, dout_11_re => dout_11_re, -- sfix18 dout_11_im => dout_11_im, -- sfix18 dout_12_re => dout_12_re, -- sfix18 dout_12_im => dout_12_im, -- sfix18 dout_11_vld => dout_11_vld ); u_SDNF2_2_3 : RADIX22FFT_SDNF2_2_block PORT MAP( clk => clk, reset => reset, enb => enb, rotate_3 => rotate_3, -- ufix1 dout_3_re => dout_3_re, -- sfix18 dout_3_im => dout_3_im, -- sfix18 dout_11_re => dout_11_re, -- sfix18 dout_11_im => dout_11_im, -- sfix18 dout_1_vld => dout_1_vld, softReset => softReset, dout_3_re_1 => dout_3_re_1, -- sfix19 dout_3_im_1 => dout_3_im_1, -- sfix19 dout_4_re => dout_4_re_1, -- sfix19 dout_4_im => dout_4_im_1, -- sfix19 dout_2_vld => dout_2_vld_1 ); u_twdlROM_3_2 : TWDLROM_3_2 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_2_re => twdl_3_2_re, -- sfix17_En15 twdl_3_2_im => twdl_3_2_im, -- sfix17_En15 twdl_3_2_vld => twdl_3_2_vld ); u_TWDLMULT_SDNF1_3_1 : TWDLMULT_SDNF1_3 PORT MAP( clk => clk, reset => reset, enb => enb, dout_1_re => dout_1_re_1, -- sfix19 dout_1_im => dout_1_im_1, -- sfix19 dout_3_re => dout_3_re_1, -- sfix19 dout_3_im => dout_3_im_1, -- sfix19 dout_2_vld => dout_2_vld, twdl_3_1_re => std_logic_vector(twdl_3_1_re), -- sfix17_En15 twdl_3_1_im => std_logic_vector(twdl_3_1_im), -- sfix17_En15 twdl_3_2_re => twdl_3_2_re, -- sfix17_En15 twdl_3_2_im => twdl_3_2_im, -- sfix17_En15 twdl_3_2_vld => twdl_3_2_vld, softReset => softReset, twdlXdin_1_re => twdlXdin_1_re_1, -- sfix20 twdlXdin_1_im => twdlXdin_1_im_1, -- sfix20 twdlXdin_2_re => twdlXdin_2_re_1, -- sfix20 twdlXdin_2_im => twdlXdin_2_im_1, -- sfix20 twdlXdin_1_vld => twdlXdin_1_vld_1 ); u_SDNF1_1_5 : RADIX22FFT_SDNF1_1_block1 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_3_re => std_logic_vector(twdlXdin_3_re), -- sfix18 twdlXdin_3_im => std_logic_vector(twdlXdin_3_im), -- sfix18 twdlXdin_11_re => std_logic_vector(twdlXdin_11_re), -- sfix18 twdlXdin_11_im => std_logic_vector(twdlXdin_11_im), -- sfix18 twdlXdin_1_vld => twdlXdin_1_vld, softReset => softReset, dout_5_re => dout_5_re, -- sfix18 dout_5_im => dout_5_im, -- sfix18 dout_6_re => dout_6_re, -- sfix18 dout_6_im => dout_6_im, -- sfix18 dout_5_vld => dout_5_vld ); u_SDNF1_1_13 : RADIX22FFT_SDNF1_1_block5 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_7_re => std_logic_vector(twdlXdin_7_re), -- sfix18 twdlXdin_7_im => std_logic_vector(twdlXdin_7_im), -- sfix18 twdlXdin_15_re => std_logic_vector(twdlXdin_15_re), -- sfix18 twdlXdin_15_im => std_logic_vector(twdlXdin_15_im), -- sfix18 twdlXdin_1_vld => twdlXdin_1_vld, softReset => softReset, dout_13_re => dout_13_re, -- sfix18 dout_13_im => dout_13_im, -- sfix18 dout_14_re => dout_14_re, -- sfix18 dout_14_im => dout_14_im, -- sfix18 dout_13_vld => dout_13_vld ); u_SDNF2_2_5 : RADIX22FFT_SDNF2_2_block1 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_5 => rotate_5, -- ufix1 dout_5_re => dout_5_re, -- sfix18 dout_5_im => dout_5_im, -- sfix18 dout_13_re => dout_13_re, -- sfix18 dout_13_im => dout_13_im, -- sfix18 dout_1_vld => dout_1_vld, softReset => softReset, dout_5_re_1 => dout_5_re_1, -- sfix19 dout_5_im_1 => dout_5_im_1, -- sfix19 dout_6_re => dout_6_re_1, -- sfix19 dout_6_im => dout_6_im_1, -- sfix19 dout_2_vld => dout_2_vld_2 ); u_SDNF1_1_7 : RADIX22FFT_SDNF1_1_block2 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_4_re => std_logic_vector(twdlXdin_4_re), -- sfix18 twdlXdin_4_im => std_logic_vector(twdlXdin_4_im), -- sfix18 twdlXdin_12_re => std_logic_vector(twdlXdin_12_re), -- sfix18 twdlXdin_12_im => std_logic_vector(twdlXdin_12_im), -- sfix18 twdlXdin_1_vld => twdlXdin_1_vld, softReset => softReset, dout_7_re => dout_7_re, -- sfix18 dout_7_im => dout_7_im, -- sfix18 dout_8_re => dout_8_re, -- sfix18 dout_8_im => dout_8_im, -- sfix18 dout_7_vld => dout_7_vld ); u_SDNF1_1_15 : RADIX22FFT_SDNF1_1_block6 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_8_re => std_logic_vector(twdlXdin_8_re), -- sfix18 twdlXdin_8_im => std_logic_vector(twdlXdin_8_im), -- sfix18 twdlXdin_16_re => std_logic_vector(twdlXdin_16_re), -- sfix18 twdlXdin_16_im => std_logic_vector(twdlXdin_16_im), -- sfix18 twdlXdin_1_vld => twdlXdin_1_vld, softReset => softReset, dout_15_re => dout_15_re, -- sfix18 dout_15_im => dout_15_im, -- sfix18 dout_16_re => dout_16_re, -- sfix18 dout_16_im => dout_16_im, -- sfix18 dout_15_vld => dout_15_vld ); u_SDNF2_2_7 : RADIX22FFT_SDNF2_2_block2 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_7 => rotate_7, -- ufix1 dout_7_re => dout_7_re, -- sfix18 dout_7_im => dout_7_im, -- sfix18 dout_15_re => dout_15_re, -- sfix18 dout_15_im => dout_15_im, -- sfix18 dout_1_vld => dout_1_vld, softReset => softReset, dout_7_re_1 => dout_7_re_1, -- sfix19 dout_7_im_1 => dout_7_im_1, -- sfix19 dout_8_re => dout_8_re_1, -- sfix19 dout_8_im => dout_8_im_1, -- sfix19 dout_2_vld => dout_2_vld_3 ); u_twdlROM_3_3 : TWDLROM_3_3 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_3_re => twdl_3_3_re, -- sfix17_En15 twdl_3_3_im => twdl_3_3_im, -- sfix17_En15 twdl_3_3_vld => twdl_3_3_vld ); u_twdlROM_3_4 : TWDLROM_3_4 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_4_re => twdl_3_4_re, -- sfix17_En15 twdl_3_4_im => twdl_3_4_im, -- sfix17_En15 twdl_3_4_vld => twdl_3_4_vld ); u_TWDLMULT_SDNF1_3_3 : TWDLMULT_SDNF1_3_block PORT MAP( clk => clk, reset => reset, enb => enb, dout_5_re => dout_5_re_1, -- sfix19 dout_5_im => dout_5_im_1, -- sfix19 dout_7_re => dout_7_re_1, -- sfix19 dout_7_im => dout_7_im_1, -- sfix19 dout_2_vld => dout_2_vld, twdl_3_3_re => twdl_3_3_re, -- sfix17_En15 twdl_3_3_im => twdl_3_3_im, -- sfix17_En15 twdl_3_4_re => twdl_3_4_re, -- sfix17_En15 twdl_3_4_im => twdl_3_4_im, -- sfix17_En15 twdl_3_4_vld => twdl_3_4_vld, softReset => softReset, twdlXdin_3_re => twdlXdin_3_re_1, -- sfix20 twdlXdin_3_im => twdlXdin_3_im_1, -- sfix20 twdlXdin_4_re => twdlXdin_4_re_1, -- sfix20 twdlXdin_4_im => twdlXdin_4_im_1, -- sfix20 twdlXdin_3_vld => twdlXdin_3_vld ); u_SDNF1_3_1 : RADIX22FFT_SDNF1_3 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_1_re => twdlXdin_1_re_1, -- sfix20 twdlXdin_1_im => twdlXdin_1_im_1, -- sfix20 twdlXdin_3_re => twdlXdin_3_re_1, -- sfix20 twdlXdin_3_im => twdlXdin_3_im_1, -- sfix20 twdlXdin_1_vld => twdlXdin_1_vld_1, softReset => softReset, dout_1_re => dout_1_re_2, -- sfix20 dout_1_im => dout_1_im_2, -- sfix20 dout_2_re => dout_2_re_2, -- sfix20 dout_2_im => dout_2_im_2, -- sfix20 dout_1_vld => dout_1_vld_1 ); u_SDNF1_3_3 : RADIX22FFT_SDNF1_3_block PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_2_re => twdlXdin_2_re_1, -- sfix20 twdlXdin_2_im => twdlXdin_2_im_1, -- sfix20 twdlXdin_4_re => twdlXdin_4_re_1, -- sfix20 twdlXdin_4_im => twdlXdin_4_im_1, -- sfix20 twdlXdin_1_vld => twdlXdin_1_vld_1, softReset => softReset, dout_3_re => dout_3_re_2, -- sfix20 dout_3_im => dout_3_im_2, -- sfix20 dout_4_re => dout_4_re_2, -- sfix20 dout_4_im => dout_4_im_2, -- sfix20 dout_3_vld => dout_3_vld_1 ); u_SDNF2_4_1 : RADIX22FFT_SDNF2_4 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_1 => rotate_1, -- ufix1 dout_1_re => dout_1_re_2, -- sfix20 dout_1_im => dout_1_im_2, -- sfix20 dout_3_re => dout_3_re_2, -- sfix20 dout_3_im => dout_3_im_2, -- sfix20 dout_1_vld => dout_1_vld_1, softReset => softReset, dout_1_re_1 => dataOut_re_tmp(0), -- sfix21 dout_1_im_1 => dataOut_im_tmp(0), -- sfix21 dout_2_re => dataOut_re_tmp(1), -- sfix21 dout_2_im => dataOut_im_tmp(1), -- sfix21 dout_4_vld => dout_4_vld ); u_SDNF2_4_3 : RADIX22FFT_SDNF2_4_block PORT MAP( clk => clk, reset => reset, enb => enb, rotate_3 => rotate_3_1, -- ufix1 dout_2_re => dout_2_re_2, -- sfix20 dout_2_im => dout_2_im_2, -- sfix20 dout_4_re => dout_4_re_2, -- sfix20 dout_4_im => dout_4_im_2, -- sfix20 dout_1_vld => dout_1_vld_1, softReset => softReset, dout_3_re => dataOut_re_tmp(2), -- sfix21 dout_3_im => dataOut_im_tmp(2), -- sfix21 dout_4_re_1 => dataOut_re_tmp(3), -- sfix21 dout_4_im_1 => dataOut_im_tmp(3), -- sfix21 dout_4_vld => dout_4_vld_1 ); u_twdlROM_3_6 : TWDLROM_3_6 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_6_re => twdl_3_6_re, -- sfix17_En15 twdl_3_6_im => twdl_3_6_im, -- sfix17_En15 twdl_3_6_vld => twdl_3_6_vld ); u_TWDLMULT_SDNF1_3_5 : TWDLMULT_SDNF1_3_block1 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_re => dout_2_re_1, -- sfix19 dout_2_im => dout_2_im_1, -- sfix19 dout_4_re => dout_4_re_1, -- sfix19 dout_4_im => dout_4_im_1, -- sfix19 dout_2_vld => dout_2_vld, twdl_3_5_re => std_logic_vector(twdl_3_5_re), -- sfix17_En15 twdl_3_5_im => std_logic_vector(twdl_3_5_im), -- sfix17_En15 twdl_3_6_re => twdl_3_6_re, -- sfix17_En15 twdl_3_6_im => twdl_3_6_im, -- sfix17_En15 twdl_3_6_vld => twdl_3_6_vld, softReset => softReset, twdlXdin_5_re => twdlXdin_5_re_1, -- sfix20 twdlXdin_5_im => twdlXdin_5_im_1, -- sfix20 twdlXdin_6_re => twdlXdin_6_re_1, -- sfix20 twdlXdin_6_im => twdlXdin_6_im_1, -- sfix20 twdlXdin_5_vld => twdlXdin_5_vld ); u_twdlROM_3_7 : TWDLROM_3_7 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_7_re => twdl_3_7_re, -- sfix17_En15 twdl_3_7_im => twdl_3_7_im, -- sfix17_En15 twdl_3_7_vld => twdl_3_7_vld ); u_twdlROM_3_8 : TWDLROM_3_8 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_8_re => twdl_3_8_re, -- sfix17_En15 twdl_3_8_im => twdl_3_8_im, -- sfix17_En15 twdl_3_8_vld => twdl_3_8_vld ); u_TWDLMULT_SDNF1_3_7 : TWDLMULT_SDNF1_3_block2 PORT MAP( clk => clk, reset => reset, enb => enb, dout_6_re => dout_6_re_1, -- sfix19 dout_6_im => dout_6_im_1, -- sfix19 dout_8_re => dout_8_re_1, -- sfix19 dout_8_im => dout_8_im_1, -- sfix19 dout_2_vld => dout_2_vld, twdl_3_7_re => twdl_3_7_re, -- sfix17_En15 twdl_3_7_im => twdl_3_7_im, -- sfix17_En15 twdl_3_8_re => twdl_3_8_re, -- sfix17_En15 twdl_3_8_im => twdl_3_8_im, -- sfix17_En15 twdl_3_8_vld => twdl_3_8_vld, softReset => softReset, twdlXdin_7_re => twdlXdin_7_re_1, -- sfix20 twdlXdin_7_im => twdlXdin_7_im_1, -- sfix20 twdlXdin_8_re => twdlXdin_8_re_1, -- sfix20 twdlXdin_8_im => twdlXdin_8_im_1, -- sfix20 twdlXdin_7_vld => twdlXdin_7_vld ); u_SDNF1_3_5 : RADIX22FFT_SDNF1_3_block1 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_5_re => twdlXdin_5_re_1, -- sfix20 twdlXdin_5_im => twdlXdin_5_im_1, -- sfix20 twdlXdin_7_re => twdlXdin_7_re_1, -- sfix20 twdlXdin_7_im => twdlXdin_7_im_1, -- sfix20 twdlXdin_1_vld => twdlXdin_1_vld_1, softReset => softReset, dout_5_re => dout_5_re_2, -- sfix20 dout_5_im => dout_5_im_2, -- sfix20 dout_6_re => dout_6_re_2, -- sfix20 dout_6_im => dout_6_im_2, -- sfix20 dout_5_vld => dout_5_vld_1 ); u_SDNF1_3_7 : RADIX22FFT_SDNF1_3_block2 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_6_re => twdlXdin_6_re_1, -- sfix20 twdlXdin_6_im => twdlXdin_6_im_1, -- sfix20 twdlXdin_8_re => twdlXdin_8_re_1, -- sfix20 twdlXdin_8_im => twdlXdin_8_im_1, -- sfix20 twdlXdin_1_vld => twdlXdin_1_vld_1, softReset => softReset, dout_7_re => dout_7_re_2, -- sfix20 dout_7_im => dout_7_im_2, -- sfix20 dout_8_re => dout_8_re_2, -- sfix20 dout_8_im => dout_8_im_2, -- sfix20 dout_7_vld => dout_7_vld_1 ); u_SDNF2_4_5 : RADIX22FFT_SDNF2_4_block1 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_5 => rotate_5_1, -- ufix1 dout_5_re => dout_5_re_2, -- sfix20 dout_5_im => dout_5_im_2, -- sfix20 dout_7_re => dout_7_re_2, -- sfix20 dout_7_im => dout_7_im_2, -- sfix20 dout_1_vld => dout_1_vld_1, softReset => softReset, dout_5_re_1 => dataOut_re_tmp(4), -- sfix21 dout_5_im_1 => dataOut_im_tmp(4), -- sfix21 dout_6_re => dataOut_re_tmp(5), -- sfix21 dout_6_im => dataOut_im_tmp(5), -- sfix21 dout_4_vld => dout_4_vld_2 ); u_SDNF2_4_7 : RADIX22FFT_SDNF2_4_block2 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_7 => rotate_7_1, -- ufix1 dout_6_re => dout_6_re_2, -- sfix20 dout_6_im => dout_6_im_2, -- sfix20 dout_8_re => dout_8_re_2, -- sfix20 dout_8_im => dout_8_im_2, -- sfix20 dout_1_vld => dout_1_vld_1, softReset => softReset, dout_7_re => dataOut_re_tmp(6), -- sfix21 dout_7_im => dataOut_im_tmp(6), -- sfix21 dout_8_re_1 => dataOut_re_tmp(7), -- sfix21 dout_8_im_1 => dataOut_im_tmp(7), -- sfix21 dout_4_vld => dout_4_vld_3 ); u_SDNF2_2_9 : RADIX22FFT_SDNF2_2_block3 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_9 => rotate_9_1, -- ufix1 dout_2_re => dout_2_re, -- sfix18 dout_2_im => dout_2_im, -- sfix18 dout_10_re => dout_10_re, -- sfix18 dout_10_im => dout_10_im, -- sfix18 dout_1_vld => dout_1_vld, softReset => softReset, dout_9_re => dout_9_re_1, -- sfix19 dout_9_im => dout_9_im_1, -- sfix19 dout_10_re_1 => dout_10_re_1, -- sfix19 dout_10_im_1 => dout_10_im_1, -- sfix19 dout_2_vld => dout_2_vld_4 ); u_SDNF2_2_11 : RADIX22FFT_SDNF2_2_block4 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_11 => rotate_11, -- ufix1 dout_4_re => dout_4_re, -- sfix18 dout_4_im => dout_4_im, -- sfix18 dout_12_re => dout_12_re, -- sfix18 dout_12_im => dout_12_im, -- sfix18 dout_1_vld => dout_1_vld, softReset => softReset, dout_11_re => dout_11_re_1, -- sfix19 dout_11_im => dout_11_im_1, -- sfix19 dout_12_re_1 => dout_12_re_1, -- sfix19 dout_12_im_1 => dout_12_im_1, -- sfix19 dout_2_vld => dout_2_vld_5 ); u_twdlROM_3_10 : TWDLROM_3_10 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_10_re => twdl_3_10_re, -- sfix17_En15 twdl_3_10_im => twdl_3_10_im, -- sfix17_En15 twdl_3_10_vld => twdl_3_10_vld ); u_TWDLMULT_SDNF1_3_9 : TWDLMULT_SDNF1_3_block3 PORT MAP( clk => clk, reset => reset, enb => enb, dout_9_re => dout_9_re_1, -- sfix19 dout_9_im => dout_9_im_1, -- sfix19 dout_11_re => dout_11_re_1, -- sfix19 dout_11_im => dout_11_im_1, -- sfix19 dout_2_vld => dout_2_vld, twdl_3_9_re => std_logic_vector(twdl_3_9_re), -- sfix17_En15 twdl_3_9_im => std_logic_vector(twdl_3_9_im), -- sfix17_En15 twdl_3_10_re => twdl_3_10_re, -- sfix17_En15 twdl_3_10_im => twdl_3_10_im, -- sfix17_En15 twdl_3_10_vld => twdl_3_10_vld, softReset => softReset, twdlXdin_9_re => twdlXdin_9_re_1, -- sfix20 twdlXdin_9_im => twdlXdin_9_im_1, -- sfix20 twdlXdin_10_re => twdlXdin_10_re_1, -- sfix20 twdlXdin_10_im => twdlXdin_10_im_1, -- sfix20 twdlXdin_9_vld => twdlXdin_9_vld ); u_SDNF2_2_13 : RADIX22FFT_SDNF2_2_block5 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_13 => rotate_13, -- ufix1 dout_6_re => dout_6_re, -- sfix18 dout_6_im => dout_6_im, -- sfix18 dout_14_re => dout_14_re, -- sfix18 dout_14_im => dout_14_im, -- sfix18 dout_1_vld => dout_1_vld, softReset => softReset, dout_13_re => dout_13_re_1, -- sfix19 dout_13_im => dout_13_im_1, -- sfix19 dout_14_re_1 => dout_14_re_1, -- sfix19 dout_14_im_1 => dout_14_im_1, -- sfix19 dout_2_vld => dout_2_vld_6 ); u_SDNF2_2_15 : RADIX22FFT_SDNF2_2_block6 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_15 => rotate_15, -- ufix1 dout_8_re => dout_8_re, -- sfix18 dout_8_im => dout_8_im, -- sfix18 dout_16_re => dout_16_re, -- sfix18 dout_16_im => dout_16_im, -- sfix18 dout_1_vld => dout_1_vld, softReset => softReset, dout_15_re => dout_15_re_1, -- sfix19 dout_15_im => dout_15_im_1, -- sfix19 dout_16_re_1 => dout_16_re_1, -- sfix19 dout_16_im_1 => dout_16_im_1, -- sfix19 dout_2_vld => dout_2_vld_7 ); u_twdlROM_3_11 : TWDLROM_3_11 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_11_re => twdl_3_11_re, -- sfix17_En15 twdl_3_11_im => twdl_3_11_im, -- sfix17_En15 twdl_3_11_vld => twdl_3_11_vld ); u_twdlROM_3_12 : TWDLROM_3_12 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_12_re => twdl_3_12_re, -- sfix17_En15 twdl_3_12_im => twdl_3_12_im, -- sfix17_En15 twdl_3_12_vld => twdl_3_12_vld ); u_TWDLMULT_SDNF1_3_11 : TWDLMULT_SDNF1_3_block4 PORT MAP( clk => clk, reset => reset, enb => enb, dout_13_re => dout_13_re_1, -- sfix19 dout_13_im => dout_13_im_1, -- sfix19 dout_15_re => dout_15_re_1, -- sfix19 dout_15_im => dout_15_im_1, -- sfix19 dout_2_vld => dout_2_vld, twdl_3_11_re => twdl_3_11_re, -- sfix17_En15 twdl_3_11_im => twdl_3_11_im, -- sfix17_En15 twdl_3_12_re => twdl_3_12_re, -- sfix17_En15 twdl_3_12_im => twdl_3_12_im, -- sfix17_En15 twdl_3_12_vld => twdl_3_12_vld, softReset => softReset, twdlXdin_11_re => twdlXdin_11_re_1, -- sfix20 twdlXdin_11_im => twdlXdin_11_im_1, -- sfix20 twdlXdin_12_re => twdlXdin_12_re_1, -- sfix20 twdlXdin_12_im => twdlXdin_12_im_1, -- sfix20 twdlXdin_11_vld => twdlXdin_11_vld ); u_SDNF1_3_9 : RADIX22FFT_SDNF1_3_block3 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_9_re => twdlXdin_9_re_1, -- sfix20 twdlXdin_9_im => twdlXdin_9_im_1, -- sfix20 twdlXdin_11_re => twdlXdin_11_re_1, -- sfix20 twdlXdin_11_im => twdlXdin_11_im_1, -- sfix20 twdlXdin_1_vld => twdlXdin_1_vld_1, softReset => softReset, dout_9_re => dout_9_re_2, -- sfix20 dout_9_im => dout_9_im_2, -- sfix20 dout_10_re => dout_10_re_2, -- sfix20 dout_10_im => dout_10_im_2, -- sfix20 dout_9_vld => dout_9_vld_1 ); u_SDNF1_3_11 : RADIX22FFT_SDNF1_3_block4 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_10_re => twdlXdin_10_re_1, -- sfix20 twdlXdin_10_im => twdlXdin_10_im_1, -- sfix20 twdlXdin_12_re => twdlXdin_12_re_1, -- sfix20 twdlXdin_12_im => twdlXdin_12_im_1, -- sfix20 twdlXdin_1_vld => twdlXdin_1_vld_1, softReset => softReset, dout_11_re => dout_11_re_2, -- sfix20 dout_11_im => dout_11_im_2, -- sfix20 dout_12_re => dout_12_re_2, -- sfix20 dout_12_im => dout_12_im_2, -- sfix20 dout_11_vld => dout_11_vld_1 ); u_SDNF2_4_9 : RADIX22FFT_SDNF2_4_block3 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_9 => rotate_9, -- ufix1 dout_9_re => dout_9_re_2, -- sfix20 dout_9_im => dout_9_im_2, -- sfix20 dout_11_re => dout_11_re_2, -- sfix20 dout_11_im => dout_11_im_2, -- sfix20 dout_1_vld => dout_1_vld_1, softReset => softReset, dout_9_re_1 => dataOut_re_tmp(8), -- sfix21 dout_9_im_1 => dataOut_im_tmp(8), -- sfix21 dout_10_re => dataOut_re_tmp(9), -- sfix21 dout_10_im => dataOut_im_tmp(9), -- sfix21 dout_4_vld => dout_4_vld_4 ); u_SDNF2_4_11 : RADIX22FFT_SDNF2_4_block4 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_11 => rotate_11_1, -- ufix1 dout_10_re => dout_10_re_2, -- sfix20 dout_10_im => dout_10_im_2, -- sfix20 dout_12_re => dout_12_re_2, -- sfix20 dout_12_im => dout_12_im_2, -- sfix20 dout_1_vld => dout_1_vld_1, softReset => softReset, dout_11_re => dataOut_re_tmp(10), -- sfix21 dout_11_im => dataOut_im_tmp(10), -- sfix21 dout_12_re_1 => dataOut_re_tmp(11), -- sfix21 dout_12_im_1 => dataOut_im_tmp(11), -- sfix21 dout_4_vld => dout_4_vld_5 ); u_twdlROM_3_14 : TWDLROM_3_14 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_14_re => twdl_3_14_re, -- sfix17_En15 twdl_3_14_im => twdl_3_14_im, -- sfix17_En15 twdl_3_14_vld => twdl_3_14_vld ); u_TWDLMULT_SDNF1_3_13 : TWDLMULT_SDNF1_3_block5 PORT MAP( clk => clk, reset => reset, enb => enb, dout_10_re => dout_10_re_1, -- sfix19 dout_10_im => dout_10_im_1, -- sfix19 dout_12_re => dout_12_re_1, -- sfix19 dout_12_im => dout_12_im_1, -- sfix19 dout_2_vld => dout_2_vld, twdl_3_13_re => std_logic_vector(twdl_3_13_re), -- sfix17_En15 twdl_3_13_im => std_logic_vector(twdl_3_13_im), -- sfix17_En15 twdl_3_14_re => twdl_3_14_re, -- sfix17_En15 twdl_3_14_im => twdl_3_14_im, -- sfix17_En15 twdl_3_14_vld => twdl_3_14_vld, softReset => softReset, twdlXdin_13_re => twdlXdin_13_re_1, -- sfix20 twdlXdin_13_im => twdlXdin_13_im_1, -- sfix20 twdlXdin_14_re => twdlXdin_14_re_1, -- sfix20 twdlXdin_14_im => twdlXdin_14_im_1, -- sfix20 twdlXdin_13_vld => twdlXdin_13_vld ); u_twdlROM_3_15 : TWDLROM_3_15 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_15_re => twdl_3_15_re, -- sfix17_En15 twdl_3_15_im => twdl_3_15_im, -- sfix17_En15 twdl_3_15_vld => twdl_3_15_vld ); u_twdlROM_3_16 : TWDLROM_3_16 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_16_re => twdl_3_16_re, -- sfix17_En15 twdl_3_16_im => twdl_3_16_im, -- sfix17_En15 twdl_3_16_vld => twdl_3_16_vld ); u_TWDLMULT_SDNF1_3_15 : TWDLMULT_SDNF1_3_block6 PORT MAP( clk => clk, reset => reset, enb => enb, dout_14_re => dout_14_re_1, -- sfix19 dout_14_im => dout_14_im_1, -- sfix19 dout_16_re => dout_16_re_1, -- sfix19 dout_16_im => dout_16_im_1, -- sfix19 dout_2_vld => dout_2_vld, twdl_3_15_re => twdl_3_15_re, -- sfix17_En15 twdl_3_15_im => twdl_3_15_im, -- sfix17_En15 twdl_3_16_re => twdl_3_16_re, -- sfix17_En15 twdl_3_16_im => twdl_3_16_im, -- sfix17_En15 twdl_3_16_vld => twdl_3_16_vld, softReset => softReset, twdlXdin_15_re => twdlXdin_15_re_1, -- sfix20 twdlXdin_15_im => twdlXdin_15_im_1, -- sfix20 twdlXdin_16_re => twdlXdin_16_re_1, -- sfix20 twdlXdin_16_im => twdlXdin_16_im_1, -- sfix20 twdlXdin_15_vld => twdlXdin_15_vld ); u_SDNF1_3_13 : RADIX22FFT_SDNF1_3_block5 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_13_re => twdlXdin_13_re_1, -- sfix20 twdlXdin_13_im => twdlXdin_13_im_1, -- sfix20 twdlXdin_15_re => twdlXdin_15_re_1, -- sfix20 twdlXdin_15_im => twdlXdin_15_im_1, -- sfix20 twdlXdin_1_vld => twdlXdin_1_vld_1, softReset => softReset, dout_13_re => dout_13_re_2, -- sfix20 dout_13_im => dout_13_im_2, -- sfix20 dout_14_re => dout_14_re_2, -- sfix20 dout_14_im => dout_14_im_2, -- sfix20 dout_13_vld => dout_13_vld_1 ); u_SDNF1_3_15 : RADIX22FFT_SDNF1_3_block6 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_14_re => twdlXdin_14_re_1, -- sfix20 twdlXdin_14_im => twdlXdin_14_im_1, -- sfix20 twdlXdin_16_re => twdlXdin_16_re_1, -- sfix20 twdlXdin_16_im => twdlXdin_16_im_1, -- sfix20 twdlXdin_1_vld => twdlXdin_1_vld_1, softReset => softReset, dout_15_re => dout_15_re_2, -- sfix20 dout_15_im => dout_15_im_2, -- sfix20 dout_16_re => dout_16_re_2, -- sfix20 dout_16_im => dout_16_im_2, -- sfix20 dout_15_vld => dout_15_vld_1 ); u_SDNF2_4_13 : RADIX22FFT_SDNF2_4_block5 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_13 => rotate_13_1, -- ufix1 dout_13_re => dout_13_re_2, -- sfix20 dout_13_im => dout_13_im_2, -- sfix20 dout_15_re => dout_15_re_2, -- sfix20 dout_15_im => dout_15_im_2, -- sfix20 dout_1_vld => dout_1_vld_1, softReset => softReset, dout_13_re_1 => dataOut_re_tmp(12), -- sfix21 dout_13_im_1 => dataOut_im_tmp(12), -- sfix21 dout_14_re => dataOut_re_tmp(13), -- sfix21 dout_14_im => dataOut_im_tmp(13), -- sfix21 dout_4_vld => dout_4_vld_6 ); u_SDNF2_4_15 : RADIX22FFT_SDNF2_4_block6 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_15 => rotate_15_1, -- ufix1 dout_14_re => dout_14_re_2, -- sfix20 dout_14_im => dout_14_im_2, -- sfix20 dout_16_re => dout_16_re_2, -- sfix20 dout_16_im => dout_16_im_2, -- sfix20 dout_1_vld => dout_1_vld_1, softReset => softReset, dout_15_re => dataOut_re_tmp(14), -- sfix21 dout_15_im => dataOut_im_tmp(14), -- sfix21 dout_16_re_1 => dataOut_re_tmp(15), -- sfix21 dout_16_im_1 => dataOut_im_tmp(15), -- sfix21 dout_4_vld => dout_4_vld_7 ); rotate_1 <= '0'; rotate_1_1 <= '0'; dataIn_0 <= unsigned(dataIn(0)); dataIn_1_cast_re <= signed(resize(dataIn_0, 17)); dataIn_1_cast_im <= to_signed(16#00000#, 17); dataIn_8 <= unsigned(dataIn(8)); dataIn_9_cast_re <= signed(resize(dataIn_8, 17)); dataIn_9_cast_im <= to_signed(16#00000#, 17); twdlXdin_1_re <= resize(dataIn_1_cast_re, 18); twdlXdin_1_im <= resize(dataIn_1_cast_im, 18); twdlXdin_9_re <= resize(dataIn_9_cast_re, 18); twdlXdin_9_im <= resize(dataIn_9_cast_im, 18); twdlXdin_1_vld <= '1' WHEN validIn /= '0' ELSE '0'; softReset <= '0'; dataIn_4 <= unsigned(dataIn(4)); dataIn_5_cast_re <= signed(resize(dataIn_4, 17)); dataIn_5_cast_im <= to_signed(16#00000#, 17); dataIn_12 <= unsigned(dataIn(12)); dataIn_13_cast_re <= signed(resize(dataIn_12, 17)); dataIn_13_cast_im <= to_signed(16#00000#, 17); twdlXdin_5_re <= resize(dataIn_5_cast_re, 18); twdlXdin_5_im <= resize(dataIn_5_cast_im, 18); twdlXdin_13_re <= resize(dataIn_13_cast_re, 18); twdlXdin_13_im <= resize(dataIn_13_cast_im, 18); rotate_3 <= '0'; dataIn_1 <= unsigned(dataIn(1)); dataIn_2_cast_re <= signed(resize(dataIn_1, 17)); dataIn_2_cast_im <= to_signed(16#00000#, 17); dataIn_9 <= unsigned(dataIn(9)); dataIn_10_cast_re <= signed(resize(dataIn_9, 17)); dataIn_10_cast_im <= to_signed(16#00000#, 17); twdlXdin_2_re <= resize(dataIn_2_cast_re, 18); twdlXdin_2_im <= resize(dataIn_2_cast_im, 18); twdlXdin_10_re <= resize(dataIn_10_cast_re, 18); twdlXdin_10_im <= resize(dataIn_10_cast_im, 18); dataIn_5 <= unsigned(dataIn(5)); dataIn_6_cast_re <= signed(resize(dataIn_5, 17)); dataIn_6_cast_im <= to_signed(16#00000#, 17); dataIn_13 <= unsigned(dataIn(13)); dataIn_14_cast_re <= signed(resize(dataIn_13, 17)); dataIn_14_cast_im <= to_signed(16#00000#, 17); twdlXdin_6_re <= resize(dataIn_6_cast_re, 18); twdlXdin_6_im <= resize(dataIn_6_cast_im, 18); twdlXdin_14_re <= resize(dataIn_14_cast_re, 18); twdlXdin_14_im <= resize(dataIn_14_cast_im, 18); twdl_3_1_re <= to_signed(16#08000#, 17); twdl_3_1_im <= to_signed(16#00000#, 17); rotate_5 <= '0'; dataIn_2 <= unsigned(dataIn(2)); dataIn_3_cast_re <= signed(resize(dataIn_2, 17)); dataIn_3_cast_im <= to_signed(16#00000#, 17); dataIn_10 <= unsigned(dataIn(10)); dataIn_11_cast_re <= signed(resize(dataIn_10, 17)); dataIn_11_cast_im <= to_signed(16#00000#, 17); twdlXdin_3_re <= resize(dataIn_3_cast_re, 18); twdlXdin_3_im <= resize(dataIn_3_cast_im, 18); twdlXdin_11_re <= resize(dataIn_11_cast_re, 18); twdlXdin_11_im <= resize(dataIn_11_cast_im, 18); dataIn_6 <= unsigned(dataIn(6)); dataIn_7_cast_re <= signed(resize(dataIn_6, 17)); dataIn_7_cast_im <= to_signed(16#00000#, 17); dataIn_14 <= unsigned(dataIn(14)); dataIn_15_cast_re <= signed(resize(dataIn_14, 17)); dataIn_15_cast_im <= to_signed(16#00000#, 17); twdlXdin_7_re <= resize(dataIn_7_cast_re, 18); twdlXdin_7_im <= resize(dataIn_7_cast_im, 18); twdlXdin_15_re <= resize(dataIn_15_cast_re, 18); twdlXdin_15_im <= resize(dataIn_15_cast_im, 18); rotate_7 <= '0'; dataIn_3 <= unsigned(dataIn(3)); dataIn_4_cast_re <= signed(resize(dataIn_3, 17)); dataIn_4_cast_im <= to_signed(16#00000#, 17); dataIn_11 <= unsigned(dataIn(11)); dataIn_12_cast_re <= signed(resize(dataIn_11, 17)); dataIn_12_cast_im <= to_signed(16#00000#, 17); twdlXdin_4_re <= resize(dataIn_4_cast_re, 18); twdlXdin_4_im <= resize(dataIn_4_cast_im, 18); twdlXdin_12_re <= resize(dataIn_12_cast_re, 18); twdlXdin_12_im <= resize(dataIn_12_cast_im, 18); dataIn_7 <= unsigned(dataIn(7)); dataIn_8_cast_re <= signed(resize(dataIn_7, 17)); dataIn_8_cast_im <= to_signed(16#00000#, 17); dataIn_15 <= unsigned(dataIn(15)); dataIn_16_cast_re <= signed(resize(dataIn_15, 17)); dataIn_16_cast_im <= to_signed(16#00000#, 17); twdlXdin_8_re <= resize(dataIn_8_cast_re, 18); twdlXdin_8_im <= resize(dataIn_8_cast_im, 18); twdlXdin_16_re <= resize(dataIn_16_cast_re, 18); twdlXdin_16_im <= resize(dataIn_16_cast_im, 18); rotate_3_1 <= '1'; rotate_5_1 <= '0'; twdl_3_5_re <= to_signed(16#08000#, 17); twdl_3_5_im <= to_signed(16#00000#, 17); rotate_7_1 <= '1'; rotate_9 <= '0'; rotate_9_1 <= '1'; rotate_11 <= '1'; twdl_3_9_re <= to_signed(16#08000#, 17); twdl_3_9_im <= to_signed(16#00000#, 17); rotate_13 <= '1'; rotate_15 <= '1'; rotate_11_1 <= '1'; rotate_13_1 <= '0'; twdl_3_13_re <= to_signed(16#08000#, 17); twdl_3_13_im <= to_signed(16#00000#, 17); rotate_15_1 <= '1'; dataOut_re <= dataOut_re_tmp; dataOut_im <= dataOut_im_tmp; validOut <= dout_4_vld; END rtl;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Synthesizable Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: DEBUG_RAM_synth.vhd -- -- Description: -- Synthesizable Testbench -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.NUMERIC_STD.ALL; USE IEEE.STD_LOGIC_MISC.ALL; LIBRARY STD; USE STD.TEXTIO.ALL; --LIBRARY unisim; --USE unisim.vcomponents.ALL; LIBRARY work; USE work.ALL; USE work.BMG_TB_PKG.ALL; ENTITY DEBUG_RAM_synth IS PORT( CLK_IN : IN STD_LOGIC; CLKB_IN : IN STD_LOGIC; RESET_IN : IN STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA ); END ENTITY; ARCHITECTURE DEBUG_RAM_synth_ARCH OF DEBUG_RAM_synth IS COMPONENT DEBUG_RAM_exdes PORT ( --Inputs - Port A WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); CLKA : IN STD_LOGIC; --Inputs - Port B ADDRB : IN STD_LOGIC_VECTOR(6 DOWNTO 0); DOUTB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CLKB : IN STD_LOGIC ); END COMPONENT; SIGNAL CLKA: STD_LOGIC := '0'; SIGNAL RSTA: STD_LOGIC := '0'; SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL CLKB: STD_LOGIC := '0'; SIGNAL RSTB: STD_LOGIC := '0'; SIGNAL ADDRB: STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRB_R: STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0'); SIGNAL DOUTB: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL CHECKER_EN : STD_LOGIC:='0'; SIGNAL CHECKER_EN_R : STD_LOGIC:='0'; SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); SIGNAL clk_in_i: STD_LOGIC; SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1'; SIGNAL clkb_in_i: STD_LOGIC; SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1'; SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1'; SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1'; SIGNAL ITER_R0 : STD_LOGIC := '0'; SIGNAL ITER_R1 : STD_LOGIC := '0'; SIGNAL ITER_R2 : STD_LOGIC := '0'; SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); BEGIN -- clk_buf: bufg -- PORT map( -- i => CLK_IN, -- o => clk_in_i -- ); clk_in_i <= CLK_IN; CLKA <= clk_in_i; -- clkb_buf: bufg -- PORT map( -- i => CLKB_IN, -- o => clkb_in_i -- ); clkb_in_i <= CLKB_IN; CLKB <= clkb_in_i; RSTA <= RESET_SYNC_R3 AFTER 50 ns; PROCESS(clk_in_i) BEGIN IF(RISING_EDGE(clk_in_i)) THEN RESET_SYNC_R1 <= RESET_IN; RESET_SYNC_R2 <= RESET_SYNC_R1; RESET_SYNC_R3 <= RESET_SYNC_R2; END IF; END PROCESS; RSTB <= RESETB_SYNC_R3 AFTER 50 ns; PROCESS(clkb_in_i) BEGIN IF(RISING_EDGE(clkb_in_i)) THEN RESETB_SYNC_R1 <= RESET_IN; RESETB_SYNC_R2 <= RESETB_SYNC_R1; RESETB_SYNC_R3 <= RESETB_SYNC_R2; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ISSUE_FLAG_STATUS<= (OTHERS => '0'); ELSE ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; END IF; END IF; END PROCESS; STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; BMG_DATA_CHECKER_INST: ENTITY work.CHECKER GENERIC MAP ( WRITE_WIDTH => 32, READ_WIDTH => 4 ) PORT MAP ( CLK => clkb_in_i, RST => RSTB, EN => CHECKER_EN_R, DATA_IN => DOUTB, STATUS => ISSUE_FLAG(0) ); PROCESS(clkb_in_i) BEGIN IF(RISING_EDGE(clkb_in_i)) THEN IF(RSTB='1') THEN CHECKER_EN_R <= '0'; ELSE CHECKER_EN_R <= CHECKER_EN AFTER 50 ns; END IF; END IF; END PROCESS; BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN PORT MAP( CLKA => clk_in_i, CLKB => clkb_in_i, TB_RST => RSTA, ADDRA => ADDRA, DINA => DINA, WEA => WEA, ADDRB => ADDRB, CHECK_DATA => CHECKER_EN ); PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STATUS(8) <= '0'; iter_r2 <= '0'; iter_r1 <= '0'; iter_r0 <= '0'; ELSE STATUS(8) <= iter_r2; iter_r2 <= iter_r1; iter_r1 <= iter_r0; iter_r0 <= STIMULUS_FLOW(8); END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STIMULUS_FLOW <= (OTHERS => '0'); ELSIF(WEA(0)='1') THEN STIMULUS_FLOW <= STIMULUS_FLOW+1; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN WEA_R <= (OTHERS=>'0') AFTER 50 ns; DINA_R <= (OTHERS=>'0') AFTER 50 ns; ELSE WEA_R <= WEA AFTER 50 ns; DINA_R <= DINA AFTER 50 ns; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ADDRA_R <= (OTHERS=> '0') AFTER 50 ns; ADDRB_R <= (OTHERS=> '0') AFTER 50 ns; ELSE ADDRA_R <= ADDRA AFTER 50 ns; ADDRB_R <= ADDRB AFTER 50 ns; END IF; END IF; END PROCESS; BMG_PORT: DEBUG_RAM_exdes PORT MAP ( --Port A WEA => WEA_R, ADDRA => ADDRA_R, DINA => DINA_R, CLKA => CLKA, --Port B ADDRB => ADDRB_R, DOUTB => DOUTB, CLKB => CLKB ); END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Synthesizable Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: DEBUG_RAM_synth.vhd -- -- Description: -- Synthesizable Testbench -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.NUMERIC_STD.ALL; USE IEEE.STD_LOGIC_MISC.ALL; LIBRARY STD; USE STD.TEXTIO.ALL; --LIBRARY unisim; --USE unisim.vcomponents.ALL; LIBRARY work; USE work.ALL; USE work.BMG_TB_PKG.ALL; ENTITY DEBUG_RAM_synth IS PORT( CLK_IN : IN STD_LOGIC; CLKB_IN : IN STD_LOGIC; RESET_IN : IN STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA ); END ENTITY; ARCHITECTURE DEBUG_RAM_synth_ARCH OF DEBUG_RAM_synth IS COMPONENT DEBUG_RAM_exdes PORT ( --Inputs - Port A WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); CLKA : IN STD_LOGIC; --Inputs - Port B ADDRB : IN STD_LOGIC_VECTOR(6 DOWNTO 0); DOUTB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CLKB : IN STD_LOGIC ); END COMPONENT; SIGNAL CLKA: STD_LOGIC := '0'; SIGNAL RSTA: STD_LOGIC := '0'; SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL CLKB: STD_LOGIC := '0'; SIGNAL RSTB: STD_LOGIC := '0'; SIGNAL ADDRB: STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRB_R: STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0'); SIGNAL DOUTB: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL CHECKER_EN : STD_LOGIC:='0'; SIGNAL CHECKER_EN_R : STD_LOGIC:='0'; SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); SIGNAL clk_in_i: STD_LOGIC; SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1'; SIGNAL clkb_in_i: STD_LOGIC; SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1'; SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1'; SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1'; SIGNAL ITER_R0 : STD_LOGIC := '0'; SIGNAL ITER_R1 : STD_LOGIC := '0'; SIGNAL ITER_R2 : STD_LOGIC := '0'; SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); BEGIN -- clk_buf: bufg -- PORT map( -- i => CLK_IN, -- o => clk_in_i -- ); clk_in_i <= CLK_IN; CLKA <= clk_in_i; -- clkb_buf: bufg -- PORT map( -- i => CLKB_IN, -- o => clkb_in_i -- ); clkb_in_i <= CLKB_IN; CLKB <= clkb_in_i; RSTA <= RESET_SYNC_R3 AFTER 50 ns; PROCESS(clk_in_i) BEGIN IF(RISING_EDGE(clk_in_i)) THEN RESET_SYNC_R1 <= RESET_IN; RESET_SYNC_R2 <= RESET_SYNC_R1; RESET_SYNC_R3 <= RESET_SYNC_R2; END IF; END PROCESS; RSTB <= RESETB_SYNC_R3 AFTER 50 ns; PROCESS(clkb_in_i) BEGIN IF(RISING_EDGE(clkb_in_i)) THEN RESETB_SYNC_R1 <= RESET_IN; RESETB_SYNC_R2 <= RESETB_SYNC_R1; RESETB_SYNC_R3 <= RESETB_SYNC_R2; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ISSUE_FLAG_STATUS<= (OTHERS => '0'); ELSE ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; END IF; END IF; END PROCESS; STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; BMG_DATA_CHECKER_INST: ENTITY work.CHECKER GENERIC MAP ( WRITE_WIDTH => 32, READ_WIDTH => 4 ) PORT MAP ( CLK => clkb_in_i, RST => RSTB, EN => CHECKER_EN_R, DATA_IN => DOUTB, STATUS => ISSUE_FLAG(0) ); PROCESS(clkb_in_i) BEGIN IF(RISING_EDGE(clkb_in_i)) THEN IF(RSTB='1') THEN CHECKER_EN_R <= '0'; ELSE CHECKER_EN_R <= CHECKER_EN AFTER 50 ns; END IF; END IF; END PROCESS; BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN PORT MAP( CLKA => clk_in_i, CLKB => clkb_in_i, TB_RST => RSTA, ADDRA => ADDRA, DINA => DINA, WEA => WEA, ADDRB => ADDRB, CHECK_DATA => CHECKER_EN ); PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STATUS(8) <= '0'; iter_r2 <= '0'; iter_r1 <= '0'; iter_r0 <= '0'; ELSE STATUS(8) <= iter_r2; iter_r2 <= iter_r1; iter_r1 <= iter_r0; iter_r0 <= STIMULUS_FLOW(8); END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STIMULUS_FLOW <= (OTHERS => '0'); ELSIF(WEA(0)='1') THEN STIMULUS_FLOW <= STIMULUS_FLOW+1; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN WEA_R <= (OTHERS=>'0') AFTER 50 ns; DINA_R <= (OTHERS=>'0') AFTER 50 ns; ELSE WEA_R <= WEA AFTER 50 ns; DINA_R <= DINA AFTER 50 ns; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ADDRA_R <= (OTHERS=> '0') AFTER 50 ns; ADDRB_R <= (OTHERS=> '0') AFTER 50 ns; ELSE ADDRA_R <= ADDRA AFTER 50 ns; ADDRB_R <= ADDRB AFTER 50 ns; END IF; END IF; END PROCESS; BMG_PORT: DEBUG_RAM_exdes PORT MAP ( --Port A WEA => WEA_R, ADDRA => ADDRA_R, DINA => DINA_R, CLKA => CLKA, --Port B ADDRB => ADDRB_R, DOUTB => DOUTB, CLKB => CLKB ); END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Synthesizable Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: DEBUG_RAM_synth.vhd -- -- Description: -- Synthesizable Testbench -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.NUMERIC_STD.ALL; USE IEEE.STD_LOGIC_MISC.ALL; LIBRARY STD; USE STD.TEXTIO.ALL; --LIBRARY unisim; --USE unisim.vcomponents.ALL; LIBRARY work; USE work.ALL; USE work.BMG_TB_PKG.ALL; ENTITY DEBUG_RAM_synth IS PORT( CLK_IN : IN STD_LOGIC; CLKB_IN : IN STD_LOGIC; RESET_IN : IN STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA ); END ENTITY; ARCHITECTURE DEBUG_RAM_synth_ARCH OF DEBUG_RAM_synth IS COMPONENT DEBUG_RAM_exdes PORT ( --Inputs - Port A WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); CLKA : IN STD_LOGIC; --Inputs - Port B ADDRB : IN STD_LOGIC_VECTOR(6 DOWNTO 0); DOUTB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CLKB : IN STD_LOGIC ); END COMPONENT; SIGNAL CLKA: STD_LOGIC := '0'; SIGNAL RSTA: STD_LOGIC := '0'; SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL CLKB: STD_LOGIC := '0'; SIGNAL RSTB: STD_LOGIC := '0'; SIGNAL ADDRB: STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRB_R: STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0'); SIGNAL DOUTB: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL CHECKER_EN : STD_LOGIC:='0'; SIGNAL CHECKER_EN_R : STD_LOGIC:='0'; SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); SIGNAL clk_in_i: STD_LOGIC; SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1'; SIGNAL clkb_in_i: STD_LOGIC; SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1'; SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1'; SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1'; SIGNAL ITER_R0 : STD_LOGIC := '0'; SIGNAL ITER_R1 : STD_LOGIC := '0'; SIGNAL ITER_R2 : STD_LOGIC := '0'; SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); BEGIN -- clk_buf: bufg -- PORT map( -- i => CLK_IN, -- o => clk_in_i -- ); clk_in_i <= CLK_IN; CLKA <= clk_in_i; -- clkb_buf: bufg -- PORT map( -- i => CLKB_IN, -- o => clkb_in_i -- ); clkb_in_i <= CLKB_IN; CLKB <= clkb_in_i; RSTA <= RESET_SYNC_R3 AFTER 50 ns; PROCESS(clk_in_i) BEGIN IF(RISING_EDGE(clk_in_i)) THEN RESET_SYNC_R1 <= RESET_IN; RESET_SYNC_R2 <= RESET_SYNC_R1; RESET_SYNC_R3 <= RESET_SYNC_R2; END IF; END PROCESS; RSTB <= RESETB_SYNC_R3 AFTER 50 ns; PROCESS(clkb_in_i) BEGIN IF(RISING_EDGE(clkb_in_i)) THEN RESETB_SYNC_R1 <= RESET_IN; RESETB_SYNC_R2 <= RESETB_SYNC_R1; RESETB_SYNC_R3 <= RESETB_SYNC_R2; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ISSUE_FLAG_STATUS<= (OTHERS => '0'); ELSE ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; END IF; END IF; END PROCESS; STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; BMG_DATA_CHECKER_INST: ENTITY work.CHECKER GENERIC MAP ( WRITE_WIDTH => 32, READ_WIDTH => 4 ) PORT MAP ( CLK => clkb_in_i, RST => RSTB, EN => CHECKER_EN_R, DATA_IN => DOUTB, STATUS => ISSUE_FLAG(0) ); PROCESS(clkb_in_i) BEGIN IF(RISING_EDGE(clkb_in_i)) THEN IF(RSTB='1') THEN CHECKER_EN_R <= '0'; ELSE CHECKER_EN_R <= CHECKER_EN AFTER 50 ns; END IF; END IF; END PROCESS; BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN PORT MAP( CLKA => clk_in_i, CLKB => clkb_in_i, TB_RST => RSTA, ADDRA => ADDRA, DINA => DINA, WEA => WEA, ADDRB => ADDRB, CHECK_DATA => CHECKER_EN ); PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STATUS(8) <= '0'; iter_r2 <= '0'; iter_r1 <= '0'; iter_r0 <= '0'; ELSE STATUS(8) <= iter_r2; iter_r2 <= iter_r1; iter_r1 <= iter_r0; iter_r0 <= STIMULUS_FLOW(8); END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STIMULUS_FLOW <= (OTHERS => '0'); ELSIF(WEA(0)='1') THEN STIMULUS_FLOW <= STIMULUS_FLOW+1; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN WEA_R <= (OTHERS=>'0') AFTER 50 ns; DINA_R <= (OTHERS=>'0') AFTER 50 ns; ELSE WEA_R <= WEA AFTER 50 ns; DINA_R <= DINA AFTER 50 ns; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ADDRA_R <= (OTHERS=> '0') AFTER 50 ns; ADDRB_R <= (OTHERS=> '0') AFTER 50 ns; ELSE ADDRA_R <= ADDRA AFTER 50 ns; ADDRB_R <= ADDRB AFTER 50 ns; END IF; END IF; END PROCESS; BMG_PORT: DEBUG_RAM_exdes PORT MAP ( --Port A WEA => WEA_R, ADDRA => ADDRA_R, DINA => DINA_R, CLKA => CLKA, --Port B ADDRB => ADDRB_R, DOUTB => DOUTB, CLKB => CLKB ); END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Synthesizable Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: DEBUG_RAM_synth.vhd -- -- Description: -- Synthesizable Testbench -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.NUMERIC_STD.ALL; USE IEEE.STD_LOGIC_MISC.ALL; LIBRARY STD; USE STD.TEXTIO.ALL; --LIBRARY unisim; --USE unisim.vcomponents.ALL; LIBRARY work; USE work.ALL; USE work.BMG_TB_PKG.ALL; ENTITY DEBUG_RAM_synth IS PORT( CLK_IN : IN STD_LOGIC; CLKB_IN : IN STD_LOGIC; RESET_IN : IN STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA ); END ENTITY; ARCHITECTURE DEBUG_RAM_synth_ARCH OF DEBUG_RAM_synth IS COMPONENT DEBUG_RAM_exdes PORT ( --Inputs - Port A WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); CLKA : IN STD_LOGIC; --Inputs - Port B ADDRB : IN STD_LOGIC_VECTOR(6 DOWNTO 0); DOUTB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CLKB : IN STD_LOGIC ); END COMPONENT; SIGNAL CLKA: STD_LOGIC := '0'; SIGNAL RSTA: STD_LOGIC := '0'; SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL CLKB: STD_LOGIC := '0'; SIGNAL RSTB: STD_LOGIC := '0'; SIGNAL ADDRB: STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRB_R: STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0'); SIGNAL DOUTB: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL CHECKER_EN : STD_LOGIC:='0'; SIGNAL CHECKER_EN_R : STD_LOGIC:='0'; SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); SIGNAL clk_in_i: STD_LOGIC; SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1'; SIGNAL clkb_in_i: STD_LOGIC; SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1'; SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1'; SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1'; SIGNAL ITER_R0 : STD_LOGIC := '0'; SIGNAL ITER_R1 : STD_LOGIC := '0'; SIGNAL ITER_R2 : STD_LOGIC := '0'; SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); BEGIN -- clk_buf: bufg -- PORT map( -- i => CLK_IN, -- o => clk_in_i -- ); clk_in_i <= CLK_IN; CLKA <= clk_in_i; -- clkb_buf: bufg -- PORT map( -- i => CLKB_IN, -- o => clkb_in_i -- ); clkb_in_i <= CLKB_IN; CLKB <= clkb_in_i; RSTA <= RESET_SYNC_R3 AFTER 50 ns; PROCESS(clk_in_i) BEGIN IF(RISING_EDGE(clk_in_i)) THEN RESET_SYNC_R1 <= RESET_IN; RESET_SYNC_R2 <= RESET_SYNC_R1; RESET_SYNC_R3 <= RESET_SYNC_R2; END IF; END PROCESS; RSTB <= RESETB_SYNC_R3 AFTER 50 ns; PROCESS(clkb_in_i) BEGIN IF(RISING_EDGE(clkb_in_i)) THEN RESETB_SYNC_R1 <= RESET_IN; RESETB_SYNC_R2 <= RESETB_SYNC_R1; RESETB_SYNC_R3 <= RESETB_SYNC_R2; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ISSUE_FLAG_STATUS<= (OTHERS => '0'); ELSE ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; END IF; END IF; END PROCESS; STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; BMG_DATA_CHECKER_INST: ENTITY work.CHECKER GENERIC MAP ( WRITE_WIDTH => 32, READ_WIDTH => 4 ) PORT MAP ( CLK => clkb_in_i, RST => RSTB, EN => CHECKER_EN_R, DATA_IN => DOUTB, STATUS => ISSUE_FLAG(0) ); PROCESS(clkb_in_i) BEGIN IF(RISING_EDGE(clkb_in_i)) THEN IF(RSTB='1') THEN CHECKER_EN_R <= '0'; ELSE CHECKER_EN_R <= CHECKER_EN AFTER 50 ns; END IF; END IF; END PROCESS; BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN PORT MAP( CLKA => clk_in_i, CLKB => clkb_in_i, TB_RST => RSTA, ADDRA => ADDRA, DINA => DINA, WEA => WEA, ADDRB => ADDRB, CHECK_DATA => CHECKER_EN ); PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STATUS(8) <= '0'; iter_r2 <= '0'; iter_r1 <= '0'; iter_r0 <= '0'; ELSE STATUS(8) <= iter_r2; iter_r2 <= iter_r1; iter_r1 <= iter_r0; iter_r0 <= STIMULUS_FLOW(8); END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STIMULUS_FLOW <= (OTHERS => '0'); ELSIF(WEA(0)='1') THEN STIMULUS_FLOW <= STIMULUS_FLOW+1; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN WEA_R <= (OTHERS=>'0') AFTER 50 ns; DINA_R <= (OTHERS=>'0') AFTER 50 ns; ELSE WEA_R <= WEA AFTER 50 ns; DINA_R <= DINA AFTER 50 ns; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ADDRA_R <= (OTHERS=> '0') AFTER 50 ns; ADDRB_R <= (OTHERS=> '0') AFTER 50 ns; ELSE ADDRA_R <= ADDRA AFTER 50 ns; ADDRB_R <= ADDRB AFTER 50 ns; END IF; END IF; END PROCESS; BMG_PORT: DEBUG_RAM_exdes PORT MAP ( --Port A WEA => WEA_R, ADDRA => ADDRA_R, DINA => DINA_R, CLKA => CLKA, --Port B ADDRB => ADDRB_R, DOUTB => DOUTB, CLKB => CLKB ); END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Synthesizable Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: DEBUG_RAM_synth.vhd -- -- Description: -- Synthesizable Testbench -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.NUMERIC_STD.ALL; USE IEEE.STD_LOGIC_MISC.ALL; LIBRARY STD; USE STD.TEXTIO.ALL; --LIBRARY unisim; --USE unisim.vcomponents.ALL; LIBRARY work; USE work.ALL; USE work.BMG_TB_PKG.ALL; ENTITY DEBUG_RAM_synth IS PORT( CLK_IN : IN STD_LOGIC; CLKB_IN : IN STD_LOGIC; RESET_IN : IN STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA ); END ENTITY; ARCHITECTURE DEBUG_RAM_synth_ARCH OF DEBUG_RAM_synth IS COMPONENT DEBUG_RAM_exdes PORT ( --Inputs - Port A WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); CLKA : IN STD_LOGIC; --Inputs - Port B ADDRB : IN STD_LOGIC_VECTOR(6 DOWNTO 0); DOUTB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CLKB : IN STD_LOGIC ); END COMPONENT; SIGNAL CLKA: STD_LOGIC := '0'; SIGNAL RSTA: STD_LOGIC := '0'; SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL CLKB: STD_LOGIC := '0'; SIGNAL RSTB: STD_LOGIC := '0'; SIGNAL ADDRB: STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRB_R: STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0'); SIGNAL DOUTB: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL CHECKER_EN : STD_LOGIC:='0'; SIGNAL CHECKER_EN_R : STD_LOGIC:='0'; SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); SIGNAL clk_in_i: STD_LOGIC; SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1'; SIGNAL clkb_in_i: STD_LOGIC; SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1'; SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1'; SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1'; SIGNAL ITER_R0 : STD_LOGIC := '0'; SIGNAL ITER_R1 : STD_LOGIC := '0'; SIGNAL ITER_R2 : STD_LOGIC := '0'; SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); BEGIN -- clk_buf: bufg -- PORT map( -- i => CLK_IN, -- o => clk_in_i -- ); clk_in_i <= CLK_IN; CLKA <= clk_in_i; -- clkb_buf: bufg -- PORT map( -- i => CLKB_IN, -- o => clkb_in_i -- ); clkb_in_i <= CLKB_IN; CLKB <= clkb_in_i; RSTA <= RESET_SYNC_R3 AFTER 50 ns; PROCESS(clk_in_i) BEGIN IF(RISING_EDGE(clk_in_i)) THEN RESET_SYNC_R1 <= RESET_IN; RESET_SYNC_R2 <= RESET_SYNC_R1; RESET_SYNC_R3 <= RESET_SYNC_R2; END IF; END PROCESS; RSTB <= RESETB_SYNC_R3 AFTER 50 ns; PROCESS(clkb_in_i) BEGIN IF(RISING_EDGE(clkb_in_i)) THEN RESETB_SYNC_R1 <= RESET_IN; RESETB_SYNC_R2 <= RESETB_SYNC_R1; RESETB_SYNC_R3 <= RESETB_SYNC_R2; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ISSUE_FLAG_STATUS<= (OTHERS => '0'); ELSE ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; END IF; END IF; END PROCESS; STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; BMG_DATA_CHECKER_INST: ENTITY work.CHECKER GENERIC MAP ( WRITE_WIDTH => 32, READ_WIDTH => 4 ) PORT MAP ( CLK => clkb_in_i, RST => RSTB, EN => CHECKER_EN_R, DATA_IN => DOUTB, STATUS => ISSUE_FLAG(0) ); PROCESS(clkb_in_i) BEGIN IF(RISING_EDGE(clkb_in_i)) THEN IF(RSTB='1') THEN CHECKER_EN_R <= '0'; ELSE CHECKER_EN_R <= CHECKER_EN AFTER 50 ns; END IF; END IF; END PROCESS; BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN PORT MAP( CLKA => clk_in_i, CLKB => clkb_in_i, TB_RST => RSTA, ADDRA => ADDRA, DINA => DINA, WEA => WEA, ADDRB => ADDRB, CHECK_DATA => CHECKER_EN ); PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STATUS(8) <= '0'; iter_r2 <= '0'; iter_r1 <= '0'; iter_r0 <= '0'; ELSE STATUS(8) <= iter_r2; iter_r2 <= iter_r1; iter_r1 <= iter_r0; iter_r0 <= STIMULUS_FLOW(8); END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STIMULUS_FLOW <= (OTHERS => '0'); ELSIF(WEA(0)='1') THEN STIMULUS_FLOW <= STIMULUS_FLOW+1; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN WEA_R <= (OTHERS=>'0') AFTER 50 ns; DINA_R <= (OTHERS=>'0') AFTER 50 ns; ELSE WEA_R <= WEA AFTER 50 ns; DINA_R <= DINA AFTER 50 ns; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ADDRA_R <= (OTHERS=> '0') AFTER 50 ns; ADDRB_R <= (OTHERS=> '0') AFTER 50 ns; ELSE ADDRA_R <= ADDRA AFTER 50 ns; ADDRB_R <= ADDRB AFTER 50 ns; END IF; END IF; END PROCESS; BMG_PORT: DEBUG_RAM_exdes PORT MAP ( --Port A WEA => WEA_R, ADDRA => ADDRA_R, DINA => DINA_R, CLKA => CLKA, --Port B ADDRB => ADDRB_R, DOUTB => DOUTB, CLKB => CLKB ); END ARCHITECTURE;
LIBRARY ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.VITAL_Primitives.all; entity servo_pwm_tb is end servo_pwm_tb; architecture behavior of servo_pwm_tb is component servo_pwm port( clk : in std_logic; reset_n : in std_logic; coe_servo : out std_logic; avs_s0_write_n : in std_logic; avs_s0_writedata : in std_logic_vector (15 downto 0) ); end component; signal clk : std_logic:= '1'; signal reset_n : std_logic; signal coe_servo : std_logic; signal avs_s0_write_n: std_logic; signal avs_s0_writedata: std_logic_vector (15 downto 0); constant clk_period : time := 10 ns; begin uut: servo_pwm port map ( clk => clk, reset_n => reset_n, coe_servo => coe_servo, avs_s0_write_n => avs_s0_write_n, avs_s0_writedata => avs_s0_writedata ); clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; stimuli: process begin reset_n <= '1'; wait for 6 ms; reset_n <= '0'; avs_s0_write_n <= '0'; wait for 6 ms; reset_n <= '1'; avs_s0_writedata <= "0000000010101010"; avs_s0_write_n <= '0'; wait for 1 ms; avs_s0_write_n <= '1'; wait for 6 ms; avs_s0_writedata <= "0000000000000000"; avs_s0_write_n <= '0'; wait for 1 ms; avs_s0_write_n <= '1'; wait for 6 ms; avs_s0_writedata <= "0000000010000010"; avs_s0_write_n <= '0'; wait for 1 ms; avs_s0_write_n <= '1'; wait for 6 ms; avs_s0_writedata <= "0000000000000000"; avs_s0_write_n <= '0'; wait for 1 ms; avs_s0_write_n <= '1'; wait for 6 ms; avs_s0_writedata <= "0000000010101010"; avs_s0_write_n <= '0'; wait for 1 ms; avs_s0_write_n <= '1'; wait; end process; end;
LIBRARY ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.VITAL_Primitives.all; entity servo_pwm_tb is end servo_pwm_tb; architecture behavior of servo_pwm_tb is component servo_pwm port( clk : in std_logic; reset_n : in std_logic; coe_servo : out std_logic; avs_s0_write_n : in std_logic; avs_s0_writedata : in std_logic_vector (15 downto 0) ); end component; signal clk : std_logic:= '1'; signal reset_n : std_logic; signal coe_servo : std_logic; signal avs_s0_write_n: std_logic; signal avs_s0_writedata: std_logic_vector (15 downto 0); constant clk_period : time := 10 ns; begin uut: servo_pwm port map ( clk => clk, reset_n => reset_n, coe_servo => coe_servo, avs_s0_write_n => avs_s0_write_n, avs_s0_writedata => avs_s0_writedata ); clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; stimuli: process begin reset_n <= '1'; wait for 6 ms; reset_n <= '0'; avs_s0_write_n <= '0'; wait for 6 ms; reset_n <= '1'; avs_s0_writedata <= "0000000010101010"; avs_s0_write_n <= '0'; wait for 1 ms; avs_s0_write_n <= '1'; wait for 6 ms; avs_s0_writedata <= "0000000000000000"; avs_s0_write_n <= '0'; wait for 1 ms; avs_s0_write_n <= '1'; wait for 6 ms; avs_s0_writedata <= "0000000010000010"; avs_s0_write_n <= '0'; wait for 1 ms; avs_s0_write_n <= '1'; wait for 6 ms; avs_s0_writedata <= "0000000000000000"; avs_s0_write_n <= '0'; wait for 1 ms; avs_s0_write_n <= '1'; wait for 6 ms; avs_s0_writedata <= "0000000010101010"; avs_s0_write_n <= '0'; wait for 1 ms; avs_s0_write_n <= '1'; wait; end process; end;
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; entity tdp_ram is generic ( ADDRWIDTH : positive := 7; WIDTH : positive := 8 ); port ( clk_a : in std_logic; read_a : in std_logic; write_a : in std_logic; addr_a : in std_logic_vector(ADDRWIDTH - 1 downto 0); data_read_a : out std_logic_vector(WIDTH - 1 downto 0); data_write_a : in std_logic_vector(WIDTH - 1 downto 0); clk_b : in std_logic; read_b : in std_logic; write_b : in std_logic; addr_b : in std_logic_vector(ADDRWIDTH - 1 downto 0); data_read_b : out std_logic_vector(WIDTH - 1 downto 0); data_write_b : in std_logic_vector(WIDTH - 1 downto 0) ); end tdp_ram; architecture behavioral of tdp_ram is begin process(clk_a, clk_b) type ram_t is array(0 to 2**ADDRWIDTH - 1) of std_logic_vector(WIDTH - 1 downto 0); variable store : ram_t := (others => (others => '0')); begin if rising_edge(clk_a) then if read_a = '1' then data_read_a <= store(to_integer(unsigned(addr_a))); end if; if write_a = '1' then store(to_integer(unsigned(addr_a))) := data_write_a; end if; end if; if rising_edge(clk_b) then if read_b = '1' then data_read_b <= store(to_integer(unsigned(addr_b))); end if; if write_b = '1' then store(to_integer(unsigned(addr_b))) := data_write_b; end if; end if; end process; end behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Sparcv8Monocycle is end Sparcv8Monocycle; architecture Behavioral of Sparcv8Monocycle is begin end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity CounterLoadUpDown4 is port( clk : in std_logic; updown: in std_logic; reset : in std_logic; enable: in std_logic; load : in std_logic; dataIn: in std_logic_vector(3 downto 0); count : out std_logic_vector(3 downto 0)); end CounterLoadUpDown4; architecture Behavioral of CounterLoadUpDown4 is signal s_count : unsigned (3 downto 0); begin process(clk, enable) begin if (enable = '1') then s_count <= (others => '0'); elsif(rising_edge(clk)) then if(reset='1') then s_count <= (others => '0'); elsif(load='1') then s_count <= unsigned(dataIn); elsif (updown = '1') then s_count <= s_count + 1; else s_count <= s_count - 1; end if; end if; end process; count <= std_logic_vector(s_count); end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity CounterLoadUpDown4 is port( clk : in std_logic; updown: in std_logic; reset : in std_logic; enable: in std_logic; load : in std_logic; dataIn: in std_logic_vector(3 downto 0); count : out std_logic_vector(3 downto 0)); end CounterLoadUpDown4; architecture Behavioral of CounterLoadUpDown4 is signal s_count : unsigned (3 downto 0); begin process(clk, enable) begin if (enable = '1') then s_count <= (others => '0'); elsif(rising_edge(clk)) then if(reset='1') then s_count <= (others => '0'); elsif(load='1') then s_count <= unsigned(dataIn); elsif (updown = '1') then s_count <= s_count + 1; else s_count <= s_count - 1; end if; end if; end process; count <= std_logic_vector(s_count); end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity CounterLoadUpDown4 is port( clk : in std_logic; updown: in std_logic; reset : in std_logic; enable: in std_logic; load : in std_logic; dataIn: in std_logic_vector(3 downto 0); count : out std_logic_vector(3 downto 0)); end CounterLoadUpDown4; architecture Behavioral of CounterLoadUpDown4 is signal s_count : unsigned (3 downto 0); begin process(clk, enable) begin if (enable = '1') then s_count <= (others => '0'); elsif(rising_edge(clk)) then if(reset='1') then s_count <= (others => '0'); elsif(load='1') then s_count <= unsigned(dataIn); elsif (updown = '1') then s_count <= s_count + 1; else s_count <= s_count - 1; end if; end if; end process; count <= std_logic_vector(s_count); end Behavioral;
-------------------------------------------------------------------------------- -- Copyright (c) 1995-2007 Xilinx, Inc. -- All Right Reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 9.2i -- \ \ Application : ISE -- / / Filename : asdf_selfcheck.vhw -- /___/ /\ Timestamp : Thu May 02 19:20:37 2013 -- \ \ / \ -- \___\/\___\ -- --Command: --Design Name: asdf_selfcheck_beh --Device: Xilinx -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_TEXTIO.ALL; USE STD.TEXTIO.ALL; ENTITY asdf_selfcheck_beh IS END asdf_selfcheck_beh; ARCHITECTURE testbench_arch OF asdf_selfcheck_beh IS COMPONENT T_flipflop PORT ( clk : In std_logic; T : In std_logic; Q : InOut std_logic; Qn : InOut std_logic ); END COMPONENT; SIGNAL clk : std_logic := '0'; SIGNAL T : std_logic := '0'; SIGNAL Q : std_logic := 'Z'; SIGNAL Qn : std_logic := 'Z'; SHARED VARIABLE TX_ERROR : INTEGER := 0; SHARED VARIABLE TX_OUT : LINE; constant PERIOD : time := 200 ns; constant DUTY_CYCLE : real := 0.5; constant OFFSET : time := 100 ns; BEGIN UUT : T_flipflop PORT MAP ( clk => clk, T => T, Q => Q, Qn => Qn ); PROCESS -- clock process for clk BEGIN WAIT for OFFSET; CLOCK_LOOP : LOOP clk <= '0'; WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE)); clk <= '1'; WAIT FOR (PERIOD * DUTY_CYCLE); END LOOP CLOCK_LOOP; END PROCESS; PROCESS BEGIN -- ------------- Current Time: 185ns WAIT FOR 185 ns; T <= '1'; -- ------------------------------------- WAIT FOR 1015 ns; IF (TX_ERROR = 0) THEN STD.TEXTIO.write(TX_OUT, string'("No errors or warnings")); ASSERT (FALSE) REPORT "Simulation successful (not a failure). No problems detected." SEVERITY FAILURE; ELSE STD.TEXTIO.write(TX_OUT, TX_ERROR); STD.TEXTIO.write(TX_OUT, string'(" errors found in simulation")); ASSERT (FALSE) REPORT "Errors found during simulation" SEVERITY FAILURE; END IF; END PROCESS; END testbench_arch;
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --use IEEE.MATH_REAL.ALL; --------------------------------------------------------------------------------- -- -- U S E R F U N C T I O N : E X T R A C T O B S E R V A T I O N -- -- -- The user function calcualtes a observation for a particle -- A pointer to the input data is given. The user process can -- ask for data at a specific address. -- -- Thus, all needed data can be loaded into the entity. Thus, -- the observation can be calculated via input data. When no more -- data is needed, the observation is stored into the local ram. -- -- If the observation is stored in the ram, the finished signal has -- to be set to '1'. -- ------------------------------------------------------------------------------------ entity uf_extract_observation is generic ( C_BURST_AWIDTH : integer := 12; C_BURST_DWIDTH : integer := 32 ); port ( clk : in std_logic; reset : in std_logic; -- burst ram interface o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1); o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1); i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1); o_RAMWE : out std_logic; o_RAMClk : out std_logic; -- init signal init : in std_logic; -- enable signal enable : in std_logic; -- parameters loaded parameter_loaded : in std_logic; parameter_loaded_ack : out std_logic; -- new particle loaded new_particle : in std_logic; new_particle_ack : out std_logic; -- input data address input_data_address : in std_logic_vector(0 to 31); input_data_needed : out std_logic; -- get word data word_data_en : in std_logic; word_address : out std_logic_vector(0 to 31); word_data : in std_logic_vector(0 to 31); word_data_ack : out std_logic; -- if the observation is calculated, this signal has to be set to '1' finished : out std_logic ); end uf_extract_observation; architecture Behavioral of uf_extract_observation is component pipelined_divider port ( clk: in std_logic; ce: in std_logic; aclr: in std_logic; sclr: in std_logic; dividend: in std_logic_VECTOR(31 downto 0); divisor: in std_logic_VECTOR(31 downto 0); quot: out std_logic_VECTOR(31 downto 0); remd: out std_logic_VECTOR(31 downto 0); rfd: out std_logic); end component; type hsv_function is array ( 0 to 255) of integer; -- GRANULARITY constant GRAN_EXP : integer := 14; constant GRANULARITY : integer := 2*GRAN_EXP; constant hd_values : hsv_function := ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9); constant sdvd_values : hsv_function := ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9); -- states type t_state is (STATE_INIT, STATE_READ_PARAMETER, STATE_INIT_HISTOGRAM, STATE_READ_PARTICLE, STATE_ANALYZE_PARTICLE, STATE_CALCULATE_HISTOGRAM, STATE_GET_PIXEL,STATE_UPDATE_HISTOGRAM, STATE_CHECK_FINISHED, STATE_NORMALIZE_HISTOGRAM, STATE_COPY_HISTOGRAM, STATE_FINISH); signal state : t_state; ----------------------------------------------------- -- signals needed for divider component ----------------------------------------------------- -- clock enable signal ce : std_logic; -- synchronous clear signal sclr : std_logic := '0'; -- asynchronous clear signal aclr : std_logic := '0'; -- dividend signal dividend : std_logic_vector(31 downto 0) := (others => '0'); -- divisor signal divisor : std_logic_vector(31 downto 0) := "00000000000000000000000000000001"; -- quotient signal quotient : std_logic_vector(31 downto 0) := (others => '0'); -- remainder signal remainder : std_logic_vector(31 downto 0) := (others => '0'); -- ready for data signal rfd : std_logic; -- local ram address for interface signal local_ram_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0'); signal local_ram_start_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0'); -- HSV signals signal H : std_logic_vector(0 to 7) := (others => '0'); signal S : std_logic_vector(0 to 7) := (others => '0'); signal V : std_logic_vector(0 to 7) := (others => '0'); signal H_store : std_logic_vector(0 to 7) := (others => '0'); signal S_store : std_logic_vector(0 to 7) := (others => '0'); signal V_store : std_logic_vector(0 to 7) := (others => '0'); constant S_THRESH : integer := 25; constant V_THRESH : integer := 50; signal hd : natural range 0 to 9 := 0; signal sd : natural range 0 to 9 := 0; signal vd : natural range 0 to 9 := 0; signal value : natural := 0; -- copy histogram signal copy_histo_en : std_logic := '0'; -- handshake signal signal copy_histo_done : std_logic := '0'; -- handshake signal signal copy_histo_addr : std_logic_vector(C_BURST_AWIDTH-1 downto 0); -- burst ram addr signal copy_histo_bucket : std_logic_vector(6 downto 0); -- histogram addr signal copy_histo_data : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0'); -- update histogram signal update_histo_en : std_logic := '0'; -- handshake signal signal update_histo_done : std_logic := '0'; -- handshake signal signal update_histo_addr : std_logic_vector(C_BURST_AWIDTH-1 downto 0); -- burst ram addr signal update_histo_bucket : std_logic_vector(6 downto 0); -- histogram addr -- clear histogram signal clear_histo_en : std_logic := '0'; -- handshake signal signal clear_histo_done : std_logic := '0'; -- handshake signal signal clear_histo_bucket : std_logic_vector(6 downto 0) := (others => '0'); -- histogram addr -- normalize histogram signal normalize_histo_en : std_logic := '0'; -- handshake signal signal normalize_histo_done : std_logic := '0'; -- handshake signal signal normalize_histo : std_logic := '0'; -- set histo_ram value signal normalize_histo_value : std_logic_vector(31 downto 0) := (others=>'0'); -- new normalized histo value signal normalize_histo_bucket : std_logic_vector(6 downto 0) := (others => '0'); -- histogram addr -- read particle data signal read_particle_en : std_logic := '0'; -- handshake signal signal read_particle_done : std_logic := '0'; -- handshake signal signal read_particle_addr : std_logic_vector(C_BURST_AWIDTH-1 downto 0) := (others=>'0'); -- analyze particle signal analyze_particle_en : std_logic := '0'; -- handshake signal signal analyze_particle_done : std_logic := '0'; -- handshake signal -- read parameter signal read_parameter_en : std_logic := '0'; -- handshake signal signal read_parameter_done : std_logic := '0'; -- handshake signal signal read_parameter_addr : std_logic_vector(C_BURST_AWIDTH-1 downto 0) := (others=>'0'); -- calculate histogram signal calc_histo_en : std_logic := '0'; -- handshake signal signal calc_histo_done : std_logic := '0'; -- handshake signal -- get_pixel signal get_pixel_en : std_logic := '0'; -- handshake signal signal get_pixel_done : std_logic := '0'; -- handshake signal -- histogram type t_ram is array (109 downto 0) of std_logic_vector(31 downto 0); signal histo_ram : t_ram; -- histogram memory signal histo_bucket : std_logic_vector(6 downto 0); -- current histogram bucket signal histo_inc : std_logic := '0'; -- enables incrementing signal histo_clear : std_logic := '0'; -- enables setting to zero signal histo_value : std_logic_vector(31 downto 0); -- value of current bucket -- particle data signal x : integer := 0; signal y : integer := 0; signal scale : integer := 0; signal width : integer := 0; signal height : integer := 0; -- input data -- left upper corner signal x1 : integer := 0; signal y1 : integer := 0; -- right bottom corner signal x2 : integer := 0; signal y2 : integer := 2; -- current pixel signal px : integer := 0; signal py : integer := 0; -- current pixel signal size_x : integer := 480; signal size_y : integer := 360; -- temporary signals signal temp_x : integer := 0; signal temp_y : integer := 0; signal temp : integer := 0; -- input data offset signal input_data_offset : integer := 0; -- sum of histogram signal sum : integer := 0; -- signal for counter signal i : integer := 0; signal j : integer := 0; begin divider : pipelined_divider port map ( clk => clk, ce => ce, aclr => aclr, sclr => sclr, dividend => dividend, divisor => divisor, quot => quotient, remd => remainder, rfd => rfd); -- burst ram interface o_RAMClk <= clk; ce <= enable; -- histogram memory is basically a single port ram with -- asynchronous read. the current bucket is incremented each -- clock cycle when histo_inc is high, or set to zero when -- histo_clear is high. -- @author: Andreas Agne histo_value <= histo_ram(CONV_INTEGER(histo_bucket)); histo_ram_proc : process(clk) begin if rising_edge(clk) then -- TRY: CLOCKED VERSION --histo_value <= histo_ram(CONV_INTEGER(histo_bucket)); if histo_inc = '1' then histo_ram(TO_INTEGER(UNSIGNED(histo_bucket))) <= histo_ram(CONV_INTEGER(histo_bucket)) + 1; elsif histo_clear = '1' then histo_ram(TO_INTEGER(UNSIGNED(histo_bucket))) <= (others=>'0'); elsif normalize_histo = '1' then histo_ram(TO_INTEGER(UNSIGNED(histo_bucket))) <= normalize_histo_value; end if; end if; end process; -- signals and processes related to updating the histogram from -- burst-ram data update_histo_proc : process(clk, reset, update_histo_en) variable step : natural range 0 to 3; begin if reset = '1' or update_histo_en = '0' then step := 0; histo_inc <= '0'; update_histo_addr <= (others => '0'); update_histo_done <= '0'; update_histo_bucket <= (others => '0'); elsif rising_edge(clk) then case step is when 0 => -- calculate hd hd <= hd_values(TO_INTEGER(UNSIGNED(H_store))); sd <= sdvd_values(TO_INTEGER(UNSIGNED(S_store))); vd <= sdvd_values(TO_INTEGER(UNSIGNED(V_store))); step := step + 1; when 1 => -- calculate histogram position if( S_THRESH <= S and V_THRESH <= V) then value <= 10 sd + hd; else value <= 100 + vd; end if; step := step + 1; when 2 => -- increment histogram value histo_inc <= '1'; update_histo_bucket <= STD_LOGIC_VECTOR(TO_UNSIGNED(value, 7)); step := step + 1; when 3 => -- turn off histogram incrementing, set handshake signal histo_inc <= '0'; update_histo_done <= '1'; -- when 0 => -- calculate hd -- hd <= hd_values(TO_INTEGER(UNSIGNED(H))); -- step := step + 1; -- -- when 1 => -- calculate sd -- sd <= sdvd_values(TO_INTEGER(UNSIGNED(S))); -- step := step + 1; -- -- when 2 => -- calculate vd -- vd <= sdvd_values(TO_INTEGER(UNSIGNED(V))); -- step := step + 1; -- -- when 3 => -- calculate histogram position (1 of 2) -- if( S_THRESH <= S and V_THRESH <= V) then -- value <= 10 * sd; -- else -- value <= 100 + vd; -- end if; -- step := step + 1; -- -- when 4 => -- calculate histogram position (2 of 2) -- if( S_THRESH <= S and V_THRESH <= V) then -- value <= value + hd; -- end if; -- step := step + 1; -- -- when 5 => -- increment histogram value -- histo_inc <= '1'; -- update_histo_bucket <= STD_LOGIC_VECTOR(TO_UNSIGNED(value, 7)); -- step := step + 1; -- -- when 6 => -- turn off histogram incrementing, set handshake signal -- histo_inc <= '0'; -- update_histo_done <= '1'; end case; end if; end process; -- signals and processes related to copying the histogram to -- burst-ram -- @author: Andreas Agne copy_histogram : process(clk, reset, copy_histo_en) variable step : natural range 0 to 7; begin if reset = '1' or copy_histo_en = '0' then copy_histo_addr <= (others => '0'); copy_histo_bucket <= (others => '0'); copy_histo_done <= '0'; o_RAMWE <= '0'; copy_histo_data <= (others => '0'); step := 0; elsif rising_edge(clk) then case step is when 0 => -- set histogram and burst ram addresses to 0 copy_histo_addr <= (others => '0'); copy_histo_bucket <= (others => '0'); step := step + 1; when 1 => -- copy first word copy_histo_addr <= (others => '0'); copy_histo_bucket <= copy_histo_bucket + 1; o_RAMWE <= '1'; copy_histo_data <= histo_value; step := step + 1; when 2 => -- copy remaining histogram buckets to burst ram copy_histo_addr <= copy_histo_addr + 1; copy_histo_bucket <= copy_histo_bucket + 1; o_RAMWE <= '1'; copy_histo_data <= histo_value; if (108 <= copy_histo_bucket) then step := step + 1; end if; when 3 => -- wait (1 of 2) o_RAMWE <= '1'; copy_histo_addr <= copy_histo_addr + 1; copy_histo_data <= histo_value; step := step + 1; when 4 => -- wait (2 of 2) o_RAMWE <= '1'; step := step + 1; when 5 => -- write n o_RAMWE <= '1'; copy_histo_addr <= copy_histo_addr + 1; copy_histo_data <= STD_LOGIC_VECTOR(TO_SIGNED(110, 32)); step := step + 1; when 6 => -- write dummy o_RAMWE <= '1'; copy_histo_addr <= copy_histo_addr + 1; copy_histo_data <= STD_LOGIC_VECTOR(TO_SIGNED(0, 32)); step := step + 1; when 7 => -- all buckets copied -> set handshake signal copy_histo_done <= '1'; copy_histo_bucket <= (others => '0'); o_RAMWE <= '0'; end case; end if; end process; -- signals and processes related to calculating the histogram calc_histo_proc : process(clk, reset, calc_histo_en) variable step : natural range 0 to 5; begin if reset = '1' or calc_histo_en = '0' then step := 0; H_store(0 to 7) <= (others => '0'); S_store(0 to 7) <= (others => '0'); V_store(0 to 7) <= (others => '0'); update_histo_en <= '0'; get_pixel_en <= '0'; calc_histo_done <= '0'; elsif rising_edge(clk) then case step is when 0 => -- get 1st pixel px <= x1; py <= y1; get_pixel_en <= '1'; update_histo_en <= '0'; step := step + 1; when 1 => -- first pixel stored if (get_pixel_done = '1') then H_store(0 to 7) <= H(0 to 7); S_store(0 to 7) <= S(0 to 7); V_store(0 to 7) <= V(0 to 7); get_pixel_en <= '0'; update_histo_en <= '0'; px <= px + 1; step := step + 1; end if; when 2 => -- start parallel execution or last update if (px > x2 and y2 <= py) then -- finished: last update step := step + 2; update_histo_en <= '1'; get_pixel_en <= '0'; elsif (px > x2 and py < y2) then -- next row px <= x1; py <= py + 1; -- read next pixel and update histogram for last one get_pixel_en <= '1'; update_histo_en <= '1'; step := step + 1; else -- default: read next pixel and update histogram for last one get_pixel_en <= '1'; update_histo_en <= '1'; step := step + 1; end if; when 3 => -- parallel execution finished if (update_histo_done = '1' and get_pixel_done = '1' ) then get_pixel_en <= '0'; update_histo_en <= '0'; H_store(0 to 7) <= H(0 to 7); S_store(0 to 7) <= S(0 to 7); V_store(0 to 7) <= V(0 to 7); px <= px + 1; step := step - 1; end if; when 4 => -- last histogram update if (update_histo_done = '1') then update_histo_en <= '0'; get_pixel_en <= '0'; step := step + 1; end if; when 5 => -- set handshake signal update_histo_en <= '0'; get_pixel_en <= '0'; calc_histo_done <= '1'; end case; end if; end process; -- signals and processes related to clearing the histogram -- @author: Andreas Agne clear_histogram_proc : process(clk, reset, clear_histo_en) variable step : natural range 0 to 3; begin if reset = '1' or clear_histo_en = '0' then step := 0; histo_clear <= '0'; clear_histo_bucket <= (others => '0'); clear_histo_done <= '0'; elsif rising_edge(clk) then case step is when 0 => -- enable bucket zeroing clear_histo_bucket <= (others => '0'); histo_clear <= '1'; step := step + 1; when 1 => -- visit every bucket clear_histo_bucket <= clear_histo_bucket + 1; if 108 <= clear_histo_bucket then step := step + 1; end if; when 2 => step := step + 1; when 3 => -- set handshake signal histo_clear <= '0'; clear_histo_bucket <= (others => '0'); clear_histo_done <= '1'; end case; end if; end process; -- reads parameter read_parameter_proc: process (clk, reset, read_parameter_en) variable step : natural range 0 to 4; begin if reset = '1' or read_parameter_en = '0' then step := 0; read_parameter_done <= '0'; parameter_loaded_ack <= '0'; elsif rising_edge(clk) then case step is when 0 => --! read parameter values read_parameter_addr <= local_ram_start_address_if; parameter_loaded_ack <= '0'; step := step + 1; when 1 => --! wait one cycle read_parameter_addr <= local_ram_start_address_if + 1; step := step + 1; when 2 => --! read size_x size_x <= TO_INTEGER(SIGNED(i_RAMData)); step := step + 1; when 3 => --! read size_y size_y <= TO_INTEGER(SIGNED(i_RAMData)); parameter_loaded_ack <= '1'; step := step + 1; when 4 => if (parameter_loaded = '0') then read_parameter_done <= '1'; parameter_loaded_ack <= '0'; end if; end case; end if; end process; -- signals and processes related to normalizing the histograme normalize_histogram_proc : process(clk, reset, normalize_histo_en, ce) variable step : natural range 0 to 7; begin if reset = '1' or normalize_histo_en = '0' then step := 0; normalize_histo_bucket <= (others => '0'); normalize_histo_done <= '0'; divisor <= "00000000000000000000000000000001"; elsif ce = '0' then elsif rising_edge(clk) then case step is when 0 => -- init sum calculation i <= 0; sum <= 0; step := step + 1; when 1 => -- calculate sum sum <= sum + CONV_INTEGER(histo_ram(i)); if (i < 109) then i <= i + 1; else step := step + 1; end if; -- init when 2 => normalize_histo_bucket <= (others => '0'); normalize_histo <= '0'; i <= 0; step := step + 1; -- modify histo_values (histo_value * GRANULARITY) and sum up histogram -- first histo_value when 3 => normalize_histo <= '1'; -- modify value: value * GRANULARITY normalize_histo_value <= histo_ram(i)(17 downto 0) & "00000000000000"; i <= 1; step := step + 1; -- other histo_values when 4 => normalize_histo <= '1'; -- modify value: value * GRANULARITY normalize_histo_value <= histo_ram(i)(17 downto 0) & "00000000000000"; if (i < 109) then i <= i + 1; end if; if (normalize_histo_bucket < 109) then normalize_histo_bucket <= normalize_histo_bucket + 1; else step := step + 1; end if; when 5 => -- start division normalize_histo <= '0'; normalize_histo_bucket <= (others => '0'); divisor <= STD_LOGIC_VECTOR(TO_SIGNED(sum, 32)); i <= 0; step := step + 1; when 6 => -- put all 110 histogram values into pipelined divider. -- pipelined divider has a latency of 36 clock cycles -- 36 = 32 (width of dividend) + 4 (see: coregen datasheed) -- one clock cycle per division if (i<110) then -- put histogram values to pipeline dividend <= histo_ram(i); i <= i + 1; end if; if (i > 36) then -- collect division results normalize_histo <= '1'; normalize_histo_value <= quotient; if (normalize_histo_bucket < 109 and i > 37) then normalize_histo_bucket <= normalize_histo_bucket + 1; elsif (109 <= normalize_histo_bucket) then step := step + 1; end if; end if; when 7 => -- set handshake signal; normalize_histo <= '0'; normalize_histo_bucket <= (others => '0'); normalize_histo_done <= '1'; end case; end if; end process; -- reads particle data needed for histogram calculation read_particle_proc: process (clk, reset, read_particle_en, ce) variable step : natural range 0 to 8; begin if reset = '1' or read_particle_en = '0' then step := 0; read_particle_done <= '0'; --local_ram_address_if <= local_ram_start_address_if; elsif ce = '0' then elsif rising_edge(clk) and ce = '1' then case step is when 0 => --! increment local ram address to get x value local_ram_address_if <= local_ram_start_address_if + 1; step := step + 1; when 1 => --! read particle values read_particle_addr <= local_ram_address_if; local_ram_address_if <= local_ram_address_if + 1; step := step + 1; when 2 => --! wait one cycle local_ram_address_if <= local_ram_address_if + 1; read_particle_addr <= local_ram_address_if; step := step + 1; when 3 => --! read x x <= TO_INTEGER(SIGNED(i_RAMData)); local_ram_address_if <= local_ram_address_if + 6; read_particle_addr <= local_ram_address_if; step := step + 1; when 4 => --! read y y <= TO_INTEGER(SIGNED(i_RAMData)); local_ram_address_if <= local_ram_address_if + 1; read_particle_addr <= local_ram_address_if; step := step + 1; when 5 => --! read scale scale <= TO_INTEGER(SIGNED(i_RAMData)); read_particle_addr <= local_ram_address_if; step := step + 1; when 6 => --! read width width <= TO_INTEGER(SIGNED(i_RAMData)); step := step + 1; when 7 => --! read height height <= TO_INTEGER(SIGNED(i_RAMData)); step := step + 1; when 8 => read_particle_done <= '1'; end case; end if; end process; -- analyzes particle data needed for histogram calculation analyze_particle_proc: process (clk, reset, analyze_particle_en, ce) variable step : natural range 0 to 17; begin if reset = '1' or analyze_particle_en = '0' then step := 0; analyze_particle_done <= '0'; elsif ce = '0' then elsif rising_edge(clk) and ce = '1' then case step is when 0 => --! calculate upper left corner (x1, y1) and lower bottom corner (x2, y2) of frame piece temp_x <= width - 1; temp_y <= height - 1; step := step + 1; when 1 => --! calculate (x1, y1) and (x2, y2) temp_x <= temp_x / 2; step := step + 1; when 2 => --! calculate (x1, y1) and (x2, y2) temp_y <= temp_y / 2; step := step + 1; when 3 => --! calculate (x1, y1) and (x2, y2) temp_x <= temp_x * scale; step := step + 1; when 4 => --! wait step := step + 1; when 5 => --! wait step := step + 1; when 6 => --! calculate (x1, y1) and (x2, y2) temp_y <= temp_y * scale; step := step + 1; when 7 => --! wait step := step + 1; when 8 => --! wait step := step + 1; when 9 => --! calculate (x1, y1) and (x2, y2) x1 <= x - temp_x; step := step + 1; when 10 => --! calculate (x1, y1) and (x2, y2) x2 <= x + temp_x; step := step + 1; when 11 => --! calculate (x1, y1) and (x2, y2) y1 <= y - temp_y; step := step + 1; when 12 => --! calculate (x1, y1) and (x2, y2) y2 <= y + temp_y; step := step + 1; when 13 => --! calculate (x1, y1) and (x2, y2) x1 <= x1 / GRANULARITY; step := step + 1; when 14 => --! calculate (x1, y1) and (x2, y2) y1 <= y1 / GRANULARITY; if (x1 < 0) then x1 <= 0; end if; step := step + 1; when 15 => --! calculate (x1, y1) and (x2, y2) x2 <= x2 / GRANULARITY; if (y1 < 0) then y1 <= 0; end if; step := step + 1; when 16 => --! calculate (x1, y1) and (x2, y2) if (x2 > size_x - 1) then x2 <= size_x - 1; end if; y2 <= y2 / GRANULARITY; step := step + 1; when 17 => --! finished if (y2 > size_y - 1) then y2 <= size_y - 1; end if; analyze_particle_done <= '1'; end case; end if; end process; -- get next pixel needed for histogram calculation get_pixel_proc: process (clk, reset, get_pixel_en, ce) variable step : natural range 0 to 5; begin if reset = '1' or get_pixel_en = '0' then step := 0; get_pixel_done <= '0'; --word_address <= (others=>'0'); word_data_ack <= '0'; elsif ce = '0' then elsif rising_edge(clk) then case step is when 0 => --! calculate offset for input data (1 of 3) input_data_offset <= 1024 * py; --input_data_offset <= 512 * py; step := step + 1; when 1 => --! calculate offset for input data (2 of 3) input_data_offset <= input_data_offset + px; step := step + 1; when 2 => --! calculate offset for input data (3 of 3) input_data_offset <= input_data_offset * 4; step := step + 1; when 3 => --! read pixel data using entitiy ports input_data_needed <= '1'; word_address <= input_data_address + input_data_offset; step := step + 1; when 4 => --! receive pixel data if word_data_en = '1' then input_data_needed <= '0'; word_data_ack <= '1'; step := step + 1; end if; when 5 => --! split pixel data to H,S,V signals H(0 to 7) <= word_data( 24 to 31); S(0 to 7) <= word_data( 16 to 23); V(0 to 7) <= word_data( 8 to 15); get_pixel_done <= '1'; end case; end if; end process; -- histogram ram mux -- @author: Andreas Agne -- updated mux_proc: process(update_histo_en, copy_histo_en, clear_histo_en, normalize_histo_en, read_particle_en, read_particle_addr, normalize_histo_bucket, update_histo_addr, update_histo_bucket, copy_histo_addr, copy_histo_bucket, clear_histo_bucket, read_parameter_en, read_parameter_addr, copy_histo_data) variable addr : std_logic_vector(C_BURST_AWIDTH - 1 downto 0); variable data : std_logic_vector(0 to C_BURST_DWIDTH-1); variable bucket : std_logic_vector(6 downto 0); begin if update_histo_en = '1' then addr := update_histo_addr; bucket := update_histo_bucket; data := (others => '0'); elsif copy_histo_en = '1' then addr := copy_histo_addr; bucket := copy_histo_bucket; data := copy_histo_data; elsif clear_histo_en = '1' then addr := (others => '0'); bucket := clear_histo_bucket; data := (others => '0'); elsif normalize_histo_en = '1' then addr := (others => '0'); bucket := normalize_histo_bucket; data := (others => '0'); elsif read_particle_en = '1' then addr := read_particle_addr; bucket := (others => '0'); data := (others => '0'); elsif read_parameter_en = '1' then addr := read_parameter_addr; bucket := (others => '0'); data := (others => '0'); else addr := (others => '0'); bucket := (others => '0'); data := (others => '0'); end if; o_RAMData <= data; o_RAMAddr <= addr(C_BURST_AWIDTH - 1 downto 0); histo_bucket <= bucket; end process; ---------------------------------------------------------------------------------- -- -- 1) initialize histogram, finished = '0' (if new_particle = '1') -- -- 2) read particle data -- -- 3) extract needed information -- -- 4) calculate input address, read pixel data (using entity ports) -- -- 5) update histogram -- -- 6) more pixel to load -- go to step 4 -- else -- go to step 7 -- -- 7) normalize histogram -- -- 8) write histogram into local ram -- -- 9) finshed = '1', wait for new_particle = '1' -- ---------------------------------------------------------------------------------- state_proc : process(clk, reset) begin if (reset = '1') then state <= STATE_INIT; new_particle_ack <= '0'; read_parameter_en <= '0'; finished <= '0'; elsif rising_edge(clk) then if init = '1' then state <= STATE_INIT; finished <= '0'; clear_histo_en <= '0'; elsif enable = '1' then case state is when STATE_INIT => --! init data finished <= '0'; calc_histo_en <= '0'; copy_histo_en <= '0'; read_particle_en <= '0'; analyze_particle_en <= '0'; if (new_particle = '1') then new_particle_ack <= '1'; clear_histo_en <= '1'; state <= STATE_INIT_HISTOGRAM; elsif (parameter_loaded = '1') then read_parameter_en <= '1'; state <= STATE_READ_PARAMETER; end if; when STATE_READ_PARAMETER => --! init histogram if (read_parameter_done = '1') then read_parameter_en <= '0'; state <= STATE_INIT; end if; ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ -- -- STEP 1: INIT HISTOGRAM -- ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ when STATE_INIT_HISTOGRAM => --! init histogram if (clear_histo_done = '1') then new_particle_ack <= '0'; clear_histo_en <= '0'; state <= STATE_READ_PARTICLE; read_particle_en <= '1'; end if; -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- ---- ---- STEP 2: READ PARTICLE ---- -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- when STATE_READ_PARTICLE => --! read particle values if (read_particle_done = '1') then analyze_particle_en <= '1'; read_particle_en <= '0'; state <= STATE_ANALYZE_PARTICLE; end if; ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ -- -- STEP 3: ANALYZE PARTICLE -- ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ when STATE_ANALYZE_PARTICLE => --! calculate upper left corner (x1, y1) and lower bottom corner (x2, y2) of frame piece if (analyze_particle_done = '1') then analyze_particle_en <= '0'; --get_pixel_en <= '1'; --px <= x1; --py <= y1; --state <= STATE_GET_PIXEL; calc_histo_en <= '1'; state <= STATE_CALCULATE_HISTOGRAM; end if; ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ -- -- STEP 4: GET PIXEL -- ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ when STATE_CALCULATE_HISTOGRAM => -- get next pixel for histogram calculation if (calc_histo_done = '1') then calc_histo_en <= '0'; normalize_histo_en <= '1'; state <= STATE_NORMALIZE_HISTOGRAM; end if; -- when STATE_GET_PIXEL => -- -- get next pixel for histogram calculation -- if (get_pixel_done = '1') then -- get_pixel_en <= '0'; -- update_histo_en <= '1'; -- state <= STATE_UPDATE_HISTOGRAM; -- end if; -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- ---- ---- STEP 5: HISTOGRAM UPDATE ---- -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- -- -- when STATE_UPDATE_HISTOGRAM => -- --! update histogram -- if update_histo_done = '1' then -- update_histo_en <= '0'; -- px <= px + 1; -- state <= STATE_CHECK_FINISHED; -- end if; ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ -- -- STEP 6: MORE PIXEL? -- ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ -- when STATE_CHECK_FINISHED => -- --! checks if more pixel have to be loaded -- if (px > x2 and y2 <= py) then -- -- finished -- normalize_histo_en <= '1'; -- state <= STATE_NORMALIZE_HISTOGRAM; -- -- CHANGE CHANGE CHANGE -- --copy_histo_en <= '1'; -- --state <= STATE_COPY_HISTOGRAM; -- -- END OF CHANGE CHANGE CHANGE -- elsif (px > x2 and py < y2) then -- -- next row -- px <= x1; -- py <= py + 1; -- state <= STATE_GET_PIXEL; -- get_pixel_en <= '1'; -- else -- -- default: next pixel -- state <= STATE_GET_PIXEL; -- get_pixel_en <= '1'; -- end if; -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- ---- ---- STEP 7: NORMALIZE HISTOGRAM ---- -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- when STATE_NORMALIZE_HISTOGRAM => --! normalize histogram if (normalize_histo_done = '1') then normalize_histo_en <= '0'; copy_histo_en <= '1'; state <= STATE_COPY_HISTOGRAM; end if; ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ -- -- STEP 8: WRITE HISTOGRAM TO LOCAL RAM -- ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ when STATE_COPY_HISTOGRAM => --! normalize histogram if (copy_histo_done = '1') then copy_histo_en <= '0'; state <= STATE_FINISH; end if; ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ -- -- STEP 9: HISTOGRAM CALCULATION FINISHED; WAIT FOR NEW_PARTICLE -- ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ when STATE_FINISH => --! write finished signal finished <= '1'; if (new_particle = '1') then state <= STATE_INIT; end if; when others => state <= STATE_INIT; end case; end if; end if; end process; end Behavioral;
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:axi_vdma:6.2 -- IP Revision: 8 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY axi_vdma_v6_2_8; USE axi_vdma_v6_2_8.axi_vdma; ENTITY block_design_axi_vdma_0_0 IS PORT ( s_axi_lite_aclk : IN STD_LOGIC; m_axi_mm2s_aclk : IN STD_LOGIC; m_axis_mm2s_aclk : IN STD_LOGIC; axi_resetn : IN STD_LOGIC; s_axi_lite_awvalid : IN STD_LOGIC; s_axi_lite_awready : OUT STD_LOGIC; s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_lite_wvalid : IN STD_LOGIC; s_axi_lite_wready : OUT STD_LOGIC; s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_lite_bvalid : OUT STD_LOGIC; s_axi_lite_bready : IN STD_LOGIC; s_axi_lite_arvalid : IN STD_LOGIC; s_axi_lite_arready : OUT STD_LOGIC; s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_lite_rvalid : OUT STD_LOGIC; s_axi_lite_rready : IN STD_LOGIC; s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); mm2s_fsync : IN STD_LOGIC; mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0); mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_mm2s_arvalid : OUT STD_LOGIC; m_axi_mm2s_arready : IN STD_LOGIC; m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_mm2s_rlast : IN STD_LOGIC; m_axi_mm2s_rvalid : IN STD_LOGIC; m_axi_mm2s_rready : OUT STD_LOGIC; m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_mm2s_tvalid : OUT STD_LOGIC; m_axis_mm2s_tready : IN STD_LOGIC; m_axis_mm2s_tlast : OUT STD_LOGIC; mm2s_introut : OUT STD_LOGIC ); END block_design_axi_vdma_0_0; ARCHITECTURE block_design_axi_vdma_0_0_arch OF block_design_axi_vdma_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF block_design_axi_vdma_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT axi_vdma IS GENERIC ( C_S_AXI_LITE_ADDR_WIDTH : INTEGER; C_S_AXI_LITE_DATA_WIDTH : INTEGER; C_DLYTMR_RESOLUTION : INTEGER; C_PRMRY_IS_ACLK_ASYNC : INTEGER; C_ENABLE_VIDPRMTR_READS : INTEGER; C_DYNAMIC_RESOLUTION : INTEGER; C_NUM_FSTORES : INTEGER; C_USE_FSYNC : INTEGER; C_USE_MM2S_FSYNC : INTEGER; C_USE_S2MM_FSYNC : INTEGER; C_FLUSH_ON_FSYNC : INTEGER; C_INCLUDE_INTERNAL_GENLOCK : INTEGER; C_INCLUDE_SG : INTEGER; C_M_AXI_SG_ADDR_WIDTH : INTEGER; C_M_AXI_SG_DATA_WIDTH : INTEGER; C_INCLUDE_MM2S : INTEGER; C_MM2S_GENLOCK_MODE : INTEGER; C_MM2S_GENLOCK_NUM_MASTERS : INTEGER; C_MM2S_GENLOCK_REPEAT_EN : INTEGER; C_MM2S_SOF_ENABLE : INTEGER; C_INCLUDE_MM2S_DRE : INTEGER; C_INCLUDE_MM2S_SF : INTEGER; C_MM2S_LINEBUFFER_DEPTH : INTEGER; C_MM2S_LINEBUFFER_THRESH : INTEGER; C_MM2S_MAX_BURST_LENGTH : INTEGER; C_M_AXI_MM2S_ADDR_WIDTH : INTEGER; C_M_AXI_MM2S_DATA_WIDTH : INTEGER; C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER; C_M_AXIS_MM2S_TUSER_BITS : INTEGER; C_INCLUDE_S2MM : INTEGER; C_S2MM_GENLOCK_MODE : INTEGER; C_S2MM_GENLOCK_NUM_MASTERS : INTEGER; C_S2MM_GENLOCK_REPEAT_EN : INTEGER; C_S2MM_SOF_ENABLE : INTEGER; C_INCLUDE_S2MM_DRE : INTEGER; C_INCLUDE_S2MM_SF : INTEGER; C_S2MM_LINEBUFFER_DEPTH : INTEGER; C_S2MM_LINEBUFFER_THRESH : INTEGER; C_S2MM_MAX_BURST_LENGTH : INTEGER; C_M_AXI_S2MM_ADDR_WIDTH : INTEGER; C_M_AXI_S2MM_DATA_WIDTH : INTEGER; C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER; C_S_AXIS_S2MM_TUSER_BITS : INTEGER; C_ENABLE_DEBUG_ALL : INTEGER; C_ENABLE_DEBUG_INFO_0 : INTEGER; C_ENABLE_DEBUG_INFO_1 : INTEGER; C_ENABLE_DEBUG_INFO_2 : INTEGER; C_ENABLE_DEBUG_INFO_3 : INTEGER; C_ENABLE_DEBUG_INFO_4 : INTEGER; C_ENABLE_DEBUG_INFO_5 : INTEGER; C_ENABLE_DEBUG_INFO_6 : INTEGER; C_ENABLE_DEBUG_INFO_7 : INTEGER; C_ENABLE_DEBUG_INFO_8 : INTEGER; C_ENABLE_DEBUG_INFO_9 : INTEGER; C_ENABLE_DEBUG_INFO_10 : INTEGER; C_ENABLE_DEBUG_INFO_11 : INTEGER; C_ENABLE_DEBUG_INFO_12 : INTEGER; C_ENABLE_DEBUG_INFO_13 : INTEGER; C_ENABLE_DEBUG_INFO_14 : INTEGER; C_ENABLE_DEBUG_INFO_15 : INTEGER; C_INSTANCE : STRING; C_SELECT_XPM : INTEGER; C_FAMILY : STRING ); PORT ( s_axi_lite_aclk : IN STD_LOGIC; m_axi_sg_aclk : IN STD_LOGIC; m_axi_mm2s_aclk : IN STD_LOGIC; m_axis_mm2s_aclk : IN STD_LOGIC; m_axi_s2mm_aclk : IN STD_LOGIC; s_axis_s2mm_aclk : IN STD_LOGIC; axi_resetn : IN STD_LOGIC; s_axi_lite_awvalid : IN STD_LOGIC; s_axi_lite_awready : OUT STD_LOGIC; s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_lite_wvalid : IN STD_LOGIC; s_axi_lite_wready : OUT STD_LOGIC; s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_lite_bvalid : OUT STD_LOGIC; s_axi_lite_bready : IN STD_LOGIC; s_axi_lite_arvalid : IN STD_LOGIC; s_axi_lite_arready : OUT STD_LOGIC; s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_lite_rvalid : OUT STD_LOGIC; s_axi_lite_rready : IN STD_LOGIC; s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); mm2s_fsync : IN STD_LOGIC; mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0); mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); s2mm_fsync : IN STD_LOGIC; s2mm_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0); s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); mm2s_buffer_empty : OUT STD_LOGIC; mm2s_buffer_almost_empty : OUT STD_LOGIC; s2mm_buffer_full : OUT STD_LOGIC; s2mm_buffer_almost_full : OUT STD_LOGIC; mm2s_fsync_out : OUT STD_LOGIC; s2mm_fsync_out : OUT STD_LOGIC; mm2s_prmtr_update : OUT STD_LOGIC; s2mm_prmtr_update : OUT STD_LOGIC; m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_sg_arvalid : OUT STD_LOGIC; m_axi_sg_arready : IN STD_LOGIC; m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_sg_rlast : IN STD_LOGIC; m_axi_sg_rvalid : IN STD_LOGIC; m_axi_sg_rready : OUT STD_LOGIC; m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_mm2s_arvalid : OUT STD_LOGIC; m_axi_mm2s_arready : IN STD_LOGIC; m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_mm2s_rlast : IN STD_LOGIC; m_axi_mm2s_rvalid : IN STD_LOGIC; m_axi_mm2s_rready : OUT STD_LOGIC; mm2s_prmry_reset_out_n : OUT STD_LOGIC; m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_mm2s_tvalid : OUT STD_LOGIC; m_axis_mm2s_tready : IN STD_LOGIC; m_axis_mm2s_tlast : OUT STD_LOGIC; m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_s2mm_awvalid : OUT STD_LOGIC; m_axi_s2mm_awready : IN STD_LOGIC; m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_s2mm_wlast : OUT STD_LOGIC; m_axi_s2mm_wvalid : OUT STD_LOGIC; m_axi_s2mm_wready : IN STD_LOGIC; m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_s2mm_bvalid : IN STD_LOGIC; m_axi_s2mm_bready : OUT STD_LOGIC; s2mm_prmry_reset_out_n : OUT STD_LOGIC; s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_s2mm_tvalid : IN STD_LOGIC; s_axis_s2mm_tready : OUT STD_LOGIC; s_axis_s2mm_tlast : IN STD_LOGIC; mm2s_introut : OUT STD_LOGIC; s2mm_introut : OUT STD_LOGIC; axi_vdma_tstvec : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ); END COMPONENT axi_vdma; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF block_design_axi_vdma_0_0_arch: ARCHITECTURE IS "axi_vdma,Vivado 2016.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF block_design_axi_vdma_0_0_arch : ARCHITECTURE IS "block_design_axi_vdma_0_0,axi_vdma,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF block_design_axi_vdma_0_0_arch: ARCHITECTURE IS "block_design_axi_vdma_0_0,axi_vdma,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_vdma,x_ipVersion=6.2,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=9,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=1,C_ENABLE_VIDPRMTR_READS=1,C_DYNAMIC_RESOLUTION=1,C_NUM_FSTORES=3,C_USE_FSYNC=1,C_USE_MM2S_FSYNC=1,C_USE_S2MM_FSYNC=2,C_FLUSH_ON_FSYNC=1,C_INCLUDE_INTERNAL_GENLOCK=1,C_INCLUDE_SG=0,C_M_AXI_SG_ADDR_WIDTH=32,C_" & "M_AXI_SG_DATA_WIDTH=32,C_INCLUDE_MM2S=1,C_MM2S_GENLOCK_MODE=1,C_MM2S_GENLOCK_NUM_MASTERS=1,C_MM2S_GENLOCK_REPEAT_EN=0,C_MM2S_SOF_ENABLE=1,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_MM2S_SF=0,C_MM2S_LINEBUFFER_DEPTH=2048,C_MM2S_LINEBUFFER_THRESH=4,C_MM2S_MAX_BURST_LENGTH=8,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=64,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_M_AXIS_MM2S_TUSER_BITS=1,C_INCLUDE_S2MM=0,C_S2MM_GENLOCK_MODE=0,C_S2MM_GENLOCK_NUM_MASTERS=1,C_S2MM_GENLOCK_REPEAT_EN=1,C_S2MM_SOF_ENABLE=1,C_INCLUDE_S2MM" & "_DRE=0,C_INCLUDE_S2MM_SF=1,C_S2MM_LINEBUFFER_DEPTH=512,C_S2MM_LINEBUFFER_THRESH=4,C_S2MM_MAX_BURST_LENGTH=8,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=64,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_S_AXIS_S2MM_TUSER_BITS=1,C_ENABLE_DEBUG_ALL=0,C_ENABLE_DEBUG_INFO_0=0,C_ENABLE_DEBUG_INFO_1=0,C_ENABLE_DEBUG_INFO_2=0,C_ENABLE_DEBUG_INFO_3=0,C_ENABLE_DEBUG_INFO_4=0,C_ENABLE_DEBUG_INFO_5=0,C_ENABLE_DEBUG_INFO_6=1,C_ENABLE_DEBUG_INFO_7=1,C_ENABLE_DEBUG_INFO_8=0,C_ENABLE_DEBUG_INFO_9=0,C_ENABLE_DEBUG_INFO_1" & "0=0,C_ENABLE_DEBUG_INFO_11=0,C_ENABLE_DEBUG_INFO_12=0,C_ENABLE_DEBUG_INFO_13=0,C_ENABLE_DEBUG_INFO_14=1,C_ENABLE_DEBUG_INFO_15=1,C_INSTANCE=axi_vdma,C_SELECT_XPM=0,C_FAMILY=zynq}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP"; ATTRIBUTE X_INTERFACE_INFO OF mm2s_fsync: SIGNAL IS "xilinx.com:signal:video_frame_sync:1.0 MM2S_FSYNC FRAME_SYNC"; ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_in: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_IN_0 FRAME_PTR"; ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_OUT FRAME_PTR"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TUSER"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST"; ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT"; BEGIN U0 : axi_vdma GENERIC MAP ( C_S_AXI_LITE_ADDR_WIDTH => 9, C_S_AXI_LITE_DATA_WIDTH => 32, C_DLYTMR_RESOLUTION => 125, C_PRMRY_IS_ACLK_ASYNC => 1, C_ENABLE_VIDPRMTR_READS => 1, C_DYNAMIC_RESOLUTION => 1, C_NUM_FSTORES => 3, C_USE_FSYNC => 1, C_USE_MM2S_FSYNC => 1, C_USE_S2MM_FSYNC => 2, C_FLUSH_ON_FSYNC => 1, C_INCLUDE_INTERNAL_GENLOCK => 1, C_INCLUDE_SG => 0, C_M_AXI_SG_ADDR_WIDTH => 32, C_M_AXI_SG_DATA_WIDTH => 32, C_INCLUDE_MM2S => 1, C_MM2S_GENLOCK_MODE => 1, C_MM2S_GENLOCK_NUM_MASTERS => 1, C_MM2S_GENLOCK_REPEAT_EN => 0, C_MM2S_SOF_ENABLE => 1, C_INCLUDE_MM2S_DRE => 0, C_INCLUDE_MM2S_SF => 0, C_MM2S_LINEBUFFER_DEPTH => 2048, C_MM2S_LINEBUFFER_THRESH => 4, C_MM2S_MAX_BURST_LENGTH => 8, C_M_AXI_MM2S_ADDR_WIDTH => 32, C_M_AXI_MM2S_DATA_WIDTH => 64, C_M_AXIS_MM2S_TDATA_WIDTH => 32, C_M_AXIS_MM2S_TUSER_BITS => 1, C_INCLUDE_S2MM => 0, C_S2MM_GENLOCK_MODE => 0, C_S2MM_GENLOCK_NUM_MASTERS => 1, C_S2MM_GENLOCK_REPEAT_EN => 1, C_S2MM_SOF_ENABLE => 1, C_INCLUDE_S2MM_DRE => 0, C_INCLUDE_S2MM_SF => 1, C_S2MM_LINEBUFFER_DEPTH => 512, C_S2MM_LINEBUFFER_THRESH => 4, C_S2MM_MAX_BURST_LENGTH => 8, C_M_AXI_S2MM_ADDR_WIDTH => 32, C_M_AXI_S2MM_DATA_WIDTH => 64, C_S_AXIS_S2MM_TDATA_WIDTH => 32, C_S_AXIS_S2MM_TUSER_BITS => 1, C_ENABLE_DEBUG_ALL => 0, C_ENABLE_DEBUG_INFO_0 => 0, C_ENABLE_DEBUG_INFO_1 => 0, C_ENABLE_DEBUG_INFO_2 => 0, C_ENABLE_DEBUG_INFO_3 => 0, C_ENABLE_DEBUG_INFO_4 => 0, C_ENABLE_DEBUG_INFO_5 => 0, C_ENABLE_DEBUG_INFO_6 => 1, C_ENABLE_DEBUG_INFO_7 => 1, C_ENABLE_DEBUG_INFO_8 => 0, C_ENABLE_DEBUG_INFO_9 => 0, C_ENABLE_DEBUG_INFO_10 => 0, C_ENABLE_DEBUG_INFO_11 => 0, C_ENABLE_DEBUG_INFO_12 => 0, C_ENABLE_DEBUG_INFO_13 => 0, C_ENABLE_DEBUG_INFO_14 => 1, C_ENABLE_DEBUG_INFO_15 => 1, C_INSTANCE => "axi_vdma", C_SELECT_XPM => 0, C_FAMILY => "zynq" ) PORT MAP ( s_axi_lite_aclk => s_axi_lite_aclk, m_axi_sg_aclk => '0', m_axi_mm2s_aclk => m_axi_mm2s_aclk, m_axis_mm2s_aclk => m_axis_mm2s_aclk, m_axi_s2mm_aclk => '0', s_axis_s2mm_aclk => '0', axi_resetn => axi_resetn, s_axi_lite_awvalid => s_axi_lite_awvalid, s_axi_lite_awready => s_axi_lite_awready, s_axi_lite_awaddr => s_axi_lite_awaddr, s_axi_lite_wvalid => s_axi_lite_wvalid, s_axi_lite_wready => s_axi_lite_wready, s_axi_lite_wdata => s_axi_lite_wdata, s_axi_lite_bresp => s_axi_lite_bresp, s_axi_lite_bvalid => s_axi_lite_bvalid, s_axi_lite_bready => s_axi_lite_bready, s_axi_lite_arvalid => s_axi_lite_arvalid, s_axi_lite_arready => s_axi_lite_arready, s_axi_lite_araddr => s_axi_lite_araddr, s_axi_lite_rvalid => s_axi_lite_rvalid, s_axi_lite_rready => s_axi_lite_rready, s_axi_lite_rdata => s_axi_lite_rdata, s_axi_lite_rresp => s_axi_lite_rresp, mm2s_fsync => mm2s_fsync, mm2s_frame_ptr_in => mm2s_frame_ptr_in, mm2s_frame_ptr_out => mm2s_frame_ptr_out, s2mm_fsync => '0', s2mm_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), m_axi_sg_arready => '0', m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_sg_rlast => '0', m_axi_sg_rvalid => '0', m_axi_mm2s_araddr => m_axi_mm2s_araddr, m_axi_mm2s_arlen => m_axi_mm2s_arlen, m_axi_mm2s_arsize => m_axi_mm2s_arsize, m_axi_mm2s_arburst => m_axi_mm2s_arburst, m_axi_mm2s_arprot => m_axi_mm2s_arprot, m_axi_mm2s_arcache => m_axi_mm2s_arcache, m_axi_mm2s_arvalid => m_axi_mm2s_arvalid, m_axi_mm2s_arready => m_axi_mm2s_arready, m_axi_mm2s_rdata => m_axi_mm2s_rdata, m_axi_mm2s_rresp => m_axi_mm2s_rresp, m_axi_mm2s_rlast => m_axi_mm2s_rlast, m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, m_axi_mm2s_rready => m_axi_mm2s_rready, m_axis_mm2s_tdata => m_axis_mm2s_tdata, m_axis_mm2s_tkeep => m_axis_mm2s_tkeep, m_axis_mm2s_tuser => m_axis_mm2s_tuser, m_axis_mm2s_tvalid => m_axis_mm2s_tvalid, m_axis_mm2s_tready => m_axis_mm2s_tready, m_axis_mm2s_tlast => m_axis_mm2s_tlast, m_axi_s2mm_awready => '0', m_axi_s2mm_wready => '0', m_axi_s2mm_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_s2mm_bvalid => '0', s_axis_s2mm_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_s2mm_tkeep => X"F", s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_s2mm_tvalid => '0', s_axis_s2mm_tlast => '0', mm2s_introut => mm2s_introut ); END block_design_axi_vdma_0_0_arch;
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:axi_vdma:6.2 -- IP Revision: 8 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY axi_vdma_v6_2_8; USE axi_vdma_v6_2_8.axi_vdma; ENTITY block_design_axi_vdma_0_0 IS PORT ( s_axi_lite_aclk : IN STD_LOGIC; m_axi_mm2s_aclk : IN STD_LOGIC; m_axis_mm2s_aclk : IN STD_LOGIC; axi_resetn : IN STD_LOGIC; s_axi_lite_awvalid : IN STD_LOGIC; s_axi_lite_awready : OUT STD_LOGIC; s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_lite_wvalid : IN STD_LOGIC; s_axi_lite_wready : OUT STD_LOGIC; s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_lite_bvalid : OUT STD_LOGIC; s_axi_lite_bready : IN STD_LOGIC; s_axi_lite_arvalid : IN STD_LOGIC; s_axi_lite_arready : OUT STD_LOGIC; s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_lite_rvalid : OUT STD_LOGIC; s_axi_lite_rready : IN STD_LOGIC; s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); mm2s_fsync : IN STD_LOGIC; mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0); mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_mm2s_arvalid : OUT STD_LOGIC; m_axi_mm2s_arready : IN STD_LOGIC; m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_mm2s_rlast : IN STD_LOGIC; m_axi_mm2s_rvalid : IN STD_LOGIC; m_axi_mm2s_rready : OUT STD_LOGIC; m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_mm2s_tvalid : OUT STD_LOGIC; m_axis_mm2s_tready : IN STD_LOGIC; m_axis_mm2s_tlast : OUT STD_LOGIC; mm2s_introut : OUT STD_LOGIC ); END block_design_axi_vdma_0_0; ARCHITECTURE block_design_axi_vdma_0_0_arch OF block_design_axi_vdma_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF block_design_axi_vdma_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT axi_vdma IS GENERIC ( C_S_AXI_LITE_ADDR_WIDTH : INTEGER; C_S_AXI_LITE_DATA_WIDTH : INTEGER; C_DLYTMR_RESOLUTION : INTEGER; C_PRMRY_IS_ACLK_ASYNC : INTEGER; C_ENABLE_VIDPRMTR_READS : INTEGER; C_DYNAMIC_RESOLUTION : INTEGER; C_NUM_FSTORES : INTEGER; C_USE_FSYNC : INTEGER; C_USE_MM2S_FSYNC : INTEGER; C_USE_S2MM_FSYNC : INTEGER; C_FLUSH_ON_FSYNC : INTEGER; C_INCLUDE_INTERNAL_GENLOCK : INTEGER; C_INCLUDE_SG : INTEGER; C_M_AXI_SG_ADDR_WIDTH : INTEGER; C_M_AXI_SG_DATA_WIDTH : INTEGER; C_INCLUDE_MM2S : INTEGER; C_MM2S_GENLOCK_MODE : INTEGER; C_MM2S_GENLOCK_NUM_MASTERS : INTEGER; C_MM2S_GENLOCK_REPEAT_EN : INTEGER; C_MM2S_SOF_ENABLE : INTEGER; C_INCLUDE_MM2S_DRE : INTEGER; C_INCLUDE_MM2S_SF : INTEGER; C_MM2S_LINEBUFFER_DEPTH : INTEGER; C_MM2S_LINEBUFFER_THRESH : INTEGER; C_MM2S_MAX_BURST_LENGTH : INTEGER; C_M_AXI_MM2S_ADDR_WIDTH : INTEGER; C_M_AXI_MM2S_DATA_WIDTH : INTEGER; C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER; C_M_AXIS_MM2S_TUSER_BITS : INTEGER; C_INCLUDE_S2MM : INTEGER; C_S2MM_GENLOCK_MODE : INTEGER; C_S2MM_GENLOCK_NUM_MASTERS : INTEGER; C_S2MM_GENLOCK_REPEAT_EN : INTEGER; C_S2MM_SOF_ENABLE : INTEGER; C_INCLUDE_S2MM_DRE : INTEGER; C_INCLUDE_S2MM_SF : INTEGER; C_S2MM_LINEBUFFER_DEPTH : INTEGER; C_S2MM_LINEBUFFER_THRESH : INTEGER; C_S2MM_MAX_BURST_LENGTH : INTEGER; C_M_AXI_S2MM_ADDR_WIDTH : INTEGER; C_M_AXI_S2MM_DATA_WIDTH : INTEGER; C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER; C_S_AXIS_S2MM_TUSER_BITS : INTEGER; C_ENABLE_DEBUG_ALL : INTEGER; C_ENABLE_DEBUG_INFO_0 : INTEGER; C_ENABLE_DEBUG_INFO_1 : INTEGER; C_ENABLE_DEBUG_INFO_2 : INTEGER; C_ENABLE_DEBUG_INFO_3 : INTEGER; C_ENABLE_DEBUG_INFO_4 : INTEGER; C_ENABLE_DEBUG_INFO_5 : INTEGER; C_ENABLE_DEBUG_INFO_6 : INTEGER; C_ENABLE_DEBUG_INFO_7 : INTEGER; C_ENABLE_DEBUG_INFO_8 : INTEGER; C_ENABLE_DEBUG_INFO_9 : INTEGER; C_ENABLE_DEBUG_INFO_10 : INTEGER; C_ENABLE_DEBUG_INFO_11 : INTEGER; C_ENABLE_DEBUG_INFO_12 : INTEGER; C_ENABLE_DEBUG_INFO_13 : INTEGER; C_ENABLE_DEBUG_INFO_14 : INTEGER; C_ENABLE_DEBUG_INFO_15 : INTEGER; C_INSTANCE : STRING; C_SELECT_XPM : INTEGER; C_FAMILY : STRING ); PORT ( s_axi_lite_aclk : IN STD_LOGIC; m_axi_sg_aclk : IN STD_LOGIC; m_axi_mm2s_aclk : IN STD_LOGIC; m_axis_mm2s_aclk : IN STD_LOGIC; m_axi_s2mm_aclk : IN STD_LOGIC; s_axis_s2mm_aclk : IN STD_LOGIC; axi_resetn : IN STD_LOGIC; s_axi_lite_awvalid : IN STD_LOGIC; s_axi_lite_awready : OUT STD_LOGIC; s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_lite_wvalid : IN STD_LOGIC; s_axi_lite_wready : OUT STD_LOGIC; s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_lite_bvalid : OUT STD_LOGIC; s_axi_lite_bready : IN STD_LOGIC; s_axi_lite_arvalid : IN STD_LOGIC; s_axi_lite_arready : OUT STD_LOGIC; s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_lite_rvalid : OUT STD_LOGIC; s_axi_lite_rready : IN STD_LOGIC; s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); mm2s_fsync : IN STD_LOGIC; mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0); mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); s2mm_fsync : IN STD_LOGIC; s2mm_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0); s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); mm2s_buffer_empty : OUT STD_LOGIC; mm2s_buffer_almost_empty : OUT STD_LOGIC; s2mm_buffer_full : OUT STD_LOGIC; s2mm_buffer_almost_full : OUT STD_LOGIC; mm2s_fsync_out : OUT STD_LOGIC; s2mm_fsync_out : OUT STD_LOGIC; mm2s_prmtr_update : OUT STD_LOGIC; s2mm_prmtr_update : OUT STD_LOGIC; m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_sg_arvalid : OUT STD_LOGIC; m_axi_sg_arready : IN STD_LOGIC; m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_sg_rlast : IN STD_LOGIC; m_axi_sg_rvalid : IN STD_LOGIC; m_axi_sg_rready : OUT STD_LOGIC; m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_mm2s_arvalid : OUT STD_LOGIC; m_axi_mm2s_arready : IN STD_LOGIC; m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_mm2s_rlast : IN STD_LOGIC; m_axi_mm2s_rvalid : IN STD_LOGIC; m_axi_mm2s_rready : OUT STD_LOGIC; mm2s_prmry_reset_out_n : OUT STD_LOGIC; m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_mm2s_tvalid : OUT STD_LOGIC; m_axis_mm2s_tready : IN STD_LOGIC; m_axis_mm2s_tlast : OUT STD_LOGIC; m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_s2mm_awvalid : OUT STD_LOGIC; m_axi_s2mm_awready : IN STD_LOGIC; m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_s2mm_wlast : OUT STD_LOGIC; m_axi_s2mm_wvalid : OUT STD_LOGIC; m_axi_s2mm_wready : IN STD_LOGIC; m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_s2mm_bvalid : IN STD_LOGIC; m_axi_s2mm_bready : OUT STD_LOGIC; s2mm_prmry_reset_out_n : OUT STD_LOGIC; s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_s2mm_tvalid : IN STD_LOGIC; s_axis_s2mm_tready : OUT STD_LOGIC; s_axis_s2mm_tlast : IN STD_LOGIC; mm2s_introut : OUT STD_LOGIC; s2mm_introut : OUT STD_LOGIC; axi_vdma_tstvec : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ); END COMPONENT axi_vdma; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF block_design_axi_vdma_0_0_arch: ARCHITECTURE IS "axi_vdma,Vivado 2016.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF block_design_axi_vdma_0_0_arch : ARCHITECTURE IS "block_design_axi_vdma_0_0,axi_vdma,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF block_design_axi_vdma_0_0_arch: ARCHITECTURE IS "block_design_axi_vdma_0_0,axi_vdma,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_vdma,x_ipVersion=6.2,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=9,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=1,C_ENABLE_VIDPRMTR_READS=1,C_DYNAMIC_RESOLUTION=1,C_NUM_FSTORES=3,C_USE_FSYNC=1,C_USE_MM2S_FSYNC=1,C_USE_S2MM_FSYNC=2,C_FLUSH_ON_FSYNC=1,C_INCLUDE_INTERNAL_GENLOCK=1,C_INCLUDE_SG=0,C_M_AXI_SG_ADDR_WIDTH=32,C_" & "M_AXI_SG_DATA_WIDTH=32,C_INCLUDE_MM2S=1,C_MM2S_GENLOCK_MODE=1,C_MM2S_GENLOCK_NUM_MASTERS=1,C_MM2S_GENLOCK_REPEAT_EN=0,C_MM2S_SOF_ENABLE=1,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_MM2S_SF=0,C_MM2S_LINEBUFFER_DEPTH=2048,C_MM2S_LINEBUFFER_THRESH=4,C_MM2S_MAX_BURST_LENGTH=8,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=64,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_M_AXIS_MM2S_TUSER_BITS=1,C_INCLUDE_S2MM=0,C_S2MM_GENLOCK_MODE=0,C_S2MM_GENLOCK_NUM_MASTERS=1,C_S2MM_GENLOCK_REPEAT_EN=1,C_S2MM_SOF_ENABLE=1,C_INCLUDE_S2MM" & "_DRE=0,C_INCLUDE_S2MM_SF=1,C_S2MM_LINEBUFFER_DEPTH=512,C_S2MM_LINEBUFFER_THRESH=4,C_S2MM_MAX_BURST_LENGTH=8,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=64,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_S_AXIS_S2MM_TUSER_BITS=1,C_ENABLE_DEBUG_ALL=0,C_ENABLE_DEBUG_INFO_0=0,C_ENABLE_DEBUG_INFO_1=0,C_ENABLE_DEBUG_INFO_2=0,C_ENABLE_DEBUG_INFO_3=0,C_ENABLE_DEBUG_INFO_4=0,C_ENABLE_DEBUG_INFO_5=0,C_ENABLE_DEBUG_INFO_6=1,C_ENABLE_DEBUG_INFO_7=1,C_ENABLE_DEBUG_INFO_8=0,C_ENABLE_DEBUG_INFO_9=0,C_ENABLE_DEBUG_INFO_1" & "0=0,C_ENABLE_DEBUG_INFO_11=0,C_ENABLE_DEBUG_INFO_12=0,C_ENABLE_DEBUG_INFO_13=0,C_ENABLE_DEBUG_INFO_14=1,C_ENABLE_DEBUG_INFO_15=1,C_INSTANCE=axi_vdma,C_SELECT_XPM=0,C_FAMILY=zynq}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP"; ATTRIBUTE X_INTERFACE_INFO OF mm2s_fsync: SIGNAL IS "xilinx.com:signal:video_frame_sync:1.0 MM2S_FSYNC FRAME_SYNC"; ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_in: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_IN_0 FRAME_PTR"; ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_OUT FRAME_PTR"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TUSER"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST"; ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT"; BEGIN U0 : axi_vdma GENERIC MAP ( C_S_AXI_LITE_ADDR_WIDTH => 9, C_S_AXI_LITE_DATA_WIDTH => 32, C_DLYTMR_RESOLUTION => 125, C_PRMRY_IS_ACLK_ASYNC => 1, C_ENABLE_VIDPRMTR_READS => 1, C_DYNAMIC_RESOLUTION => 1, C_NUM_FSTORES => 3, C_USE_FSYNC => 1, C_USE_MM2S_FSYNC => 1, C_USE_S2MM_FSYNC => 2, C_FLUSH_ON_FSYNC => 1, C_INCLUDE_INTERNAL_GENLOCK => 1, C_INCLUDE_SG => 0, C_M_AXI_SG_ADDR_WIDTH => 32, C_M_AXI_SG_DATA_WIDTH => 32, C_INCLUDE_MM2S => 1, C_MM2S_GENLOCK_MODE => 1, C_MM2S_GENLOCK_NUM_MASTERS => 1, C_MM2S_GENLOCK_REPEAT_EN => 0, C_MM2S_SOF_ENABLE => 1, C_INCLUDE_MM2S_DRE => 0, C_INCLUDE_MM2S_SF => 0, C_MM2S_LINEBUFFER_DEPTH => 2048, C_MM2S_LINEBUFFER_THRESH => 4, C_MM2S_MAX_BURST_LENGTH => 8, C_M_AXI_MM2S_ADDR_WIDTH => 32, C_M_AXI_MM2S_DATA_WIDTH => 64, C_M_AXIS_MM2S_TDATA_WIDTH => 32, C_M_AXIS_MM2S_TUSER_BITS => 1, C_INCLUDE_S2MM => 0, C_S2MM_GENLOCK_MODE => 0, C_S2MM_GENLOCK_NUM_MASTERS => 1, C_S2MM_GENLOCK_REPEAT_EN => 1, C_S2MM_SOF_ENABLE => 1, C_INCLUDE_S2MM_DRE => 0, C_INCLUDE_S2MM_SF => 1, C_S2MM_LINEBUFFER_DEPTH => 512, C_S2MM_LINEBUFFER_THRESH => 4, C_S2MM_MAX_BURST_LENGTH => 8, C_M_AXI_S2MM_ADDR_WIDTH => 32, C_M_AXI_S2MM_DATA_WIDTH => 64, C_S_AXIS_S2MM_TDATA_WIDTH => 32, C_S_AXIS_S2MM_TUSER_BITS => 1, C_ENABLE_DEBUG_ALL => 0, C_ENABLE_DEBUG_INFO_0 => 0, C_ENABLE_DEBUG_INFO_1 => 0, C_ENABLE_DEBUG_INFO_2 => 0, C_ENABLE_DEBUG_INFO_3 => 0, C_ENABLE_DEBUG_INFO_4 => 0, C_ENABLE_DEBUG_INFO_5 => 0, C_ENABLE_DEBUG_INFO_6 => 1, C_ENABLE_DEBUG_INFO_7 => 1, C_ENABLE_DEBUG_INFO_8 => 0, C_ENABLE_DEBUG_INFO_9 => 0, C_ENABLE_DEBUG_INFO_10 => 0, C_ENABLE_DEBUG_INFO_11 => 0, C_ENABLE_DEBUG_INFO_12 => 0, C_ENABLE_DEBUG_INFO_13 => 0, C_ENABLE_DEBUG_INFO_14 => 1, C_ENABLE_DEBUG_INFO_15 => 1, C_INSTANCE => "axi_vdma", C_SELECT_XPM => 0, C_FAMILY => "zynq" ) PORT MAP ( s_axi_lite_aclk => s_axi_lite_aclk, m_axi_sg_aclk => '0', m_axi_mm2s_aclk => m_axi_mm2s_aclk, m_axis_mm2s_aclk => m_axis_mm2s_aclk, m_axi_s2mm_aclk => '0', s_axis_s2mm_aclk => '0', axi_resetn => axi_resetn, s_axi_lite_awvalid => s_axi_lite_awvalid, s_axi_lite_awready => s_axi_lite_awready, s_axi_lite_awaddr => s_axi_lite_awaddr, s_axi_lite_wvalid => s_axi_lite_wvalid, s_axi_lite_wready => s_axi_lite_wready, s_axi_lite_wdata => s_axi_lite_wdata, s_axi_lite_bresp => s_axi_lite_bresp, s_axi_lite_bvalid => s_axi_lite_bvalid, s_axi_lite_bready => s_axi_lite_bready, s_axi_lite_arvalid => s_axi_lite_arvalid, s_axi_lite_arready => s_axi_lite_arready, s_axi_lite_araddr => s_axi_lite_araddr, s_axi_lite_rvalid => s_axi_lite_rvalid, s_axi_lite_rready => s_axi_lite_rready, s_axi_lite_rdata => s_axi_lite_rdata, s_axi_lite_rresp => s_axi_lite_rresp, mm2s_fsync => mm2s_fsync, mm2s_frame_ptr_in => mm2s_frame_ptr_in, mm2s_frame_ptr_out => mm2s_frame_ptr_out, s2mm_fsync => '0', s2mm_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), m_axi_sg_arready => '0', m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_sg_rlast => '0', m_axi_sg_rvalid => '0', m_axi_mm2s_araddr => m_axi_mm2s_araddr, m_axi_mm2s_arlen => m_axi_mm2s_arlen, m_axi_mm2s_arsize => m_axi_mm2s_arsize, m_axi_mm2s_arburst => m_axi_mm2s_arburst, m_axi_mm2s_arprot => m_axi_mm2s_arprot, m_axi_mm2s_arcache => m_axi_mm2s_arcache, m_axi_mm2s_arvalid => m_axi_mm2s_arvalid, m_axi_mm2s_arready => m_axi_mm2s_arready, m_axi_mm2s_rdata => m_axi_mm2s_rdata, m_axi_mm2s_rresp => m_axi_mm2s_rresp, m_axi_mm2s_rlast => m_axi_mm2s_rlast, m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, m_axi_mm2s_rready => m_axi_mm2s_rready, m_axis_mm2s_tdata => m_axis_mm2s_tdata, m_axis_mm2s_tkeep => m_axis_mm2s_tkeep, m_axis_mm2s_tuser => m_axis_mm2s_tuser, m_axis_mm2s_tvalid => m_axis_mm2s_tvalid, m_axis_mm2s_tready => m_axis_mm2s_tready, m_axis_mm2s_tlast => m_axis_mm2s_tlast, m_axi_s2mm_awready => '0', m_axi_s2mm_wready => '0', m_axi_s2mm_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_s2mm_bvalid => '0', s_axis_s2mm_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_s2mm_tkeep => X"F", s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_s2mm_tvalid => '0', s_axis_s2mm_tlast => '0', mm2s_introut => mm2s_introut ); END block_design_axi_vdma_0_0_arch;
-- ############################################################################# -- DE0_Nano_TRDB_D5M_LT24_top_level.vhd -- ==================================== -- -- BOARD : DE0-Nano from Terasic -- Author : Sahand Kashani-Akhavan from Terasic documentation -- Revision : 1.5 -- Last updated : 2017-06-11 12:48:26 UTC -- -- Syntax Rule : GROUP_NAME_N[bit] -- -- GROUP : specify a particular interface (ex: SDR_) -- NAME : signal name (ex: CONFIG, D, ...) -- bit : signal index -- _N : to specify an active-low signal -- ############################################################################# library ieee; use ieee.std_logic_1164.all; entity DE0_Nano_TRDB_D5M_LT24_top_level is port( -- CLOCK CLOCK_50 : in std_logic; -- LED LED : out std_logic_vector(7 downto 0); -- KEY_N KEY_N : in std_logic_vector(1 downto 0); -- SW SW : in std_logic_vector(3 downto 0); -- SDRAM DRAM_ADDR : out std_logic_vector(12 downto 0); DRAM_BA : out std_logic_vector(1 downto 0); DRAM_CAS_N : out std_logic; DRAM_CKE : out std_logic; DRAM_CLK : out std_logic; DRAM_CS_N : out std_logic; DRAM_DQ : inout std_logic_vector(15 downto 0); DRAM_DQM : out std_logic_vector(1 downto 0); DRAM_RAS_N : out std_logic; DRAM_WE_N : out std_logic; -- EPCS EPCS_ASDO : out std_logic; EPCS_DATA0 : in std_logic; EPCS_DCLK : out std_logic; EPCS_NCSO : out std_logic; -- Accelerometer and EEPROM G_SENSOR_CS_N : out std_logic; G_SENSOR_INT : in std_logic; I2C_SCLK : out std_logic; I2C_SDAT : inout std_logic; -- ADC ADC_CS_N : out std_logic; ADC_SADDR : out std_logic; ADC_SCLK : out std_logic; ADC_SDAT : in std_logic; -- 2x13 GPIO Header GPIO_2 : inout std_logic_vector(12 downto 0); GPIO_2_IN : in std_logic_vector(2 downto 0); -- GPIO_0 GPIO_0_D5M_D : in std_logic_vector(11 downto 0); GPIO_0_D5M_FVAL : in std_logic; GPIO_0_D5M_LVAL : in std_logic; GPIO_0_D5M_PIXCLK : in std_logic; GPIO_0_D5M_RESET_N : out std_logic; GPIO_0_D5M_SCLK : inout std_logic; GPIO_0_D5M_SDATA : inout std_logic; GPIO_0_D5M_STROBE : in std_logic; GPIO_0_D5M_TRIGGER : out std_logic; GPIO_0_D5M_XCLKIN : out std_logic; -- GPIO_1 GPIO_1_LT24_ADC_BUSY : in std_logic; GPIO_1_LT24_ADC_CS_N : out std_logic; GPIO_1_LT24_ADC_DCLK : out std_logic; GPIO_1_LT24_ADC_DIN : out std_logic; GPIO_1_LT24_ADC_DOUT : in std_logic; GPIO_1_LT24_ADC_PENIRQ_N : in std_logic; GPIO_1_LT24_CS_N : out std_logic; GPIO_1_LT24_D : out std_logic_vector(15 downto 0); GPIO_1_LT24_LCD_ON : out std_logic; GPIO_1_LT24_RD_N : out std_logic; GPIO_1_LT24_RESET_N : out std_logic; GPIO_1_LT24_RS : out std_logic; GPIO_1_LT24_WR_N : out std_logic ); end entity DE0_Nano_TRDB_D5M_LT24_top_level; architecture rtl of DE0_Nano_TRDB_D5M_LT24_top_level is begin end;
-- -- vhdl -- ------------------------------------------------------------------------------- -- Copyright (c) 2012, The CARPE Project, All rights reserved. -- -- See the AUTHORS file for individual contributors. -- -- -- -- Copyright and related rights are licensed under the Solderpad -- -- Hardware License, Version 0.51 (the "License"); you may not use this -- -- file except in compliance with the License. You may obtain a copy of -- -- the License at http://solderpad.org/licenses/SHL-0.51. -- -- -- -- Unless required by applicable law or agreed to in writing, software, -- -- hardware and materials distributed under this License is distributed -- -- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -- -- either express or implied. See the License for the specific language -- -- governing permissions and limitations under the License. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library sys; use sys.sys_pkg.all; use work.cpu_or1knd_i5_mmu_data_pkg.all; entity cpu_or1knd_i5_mmu_data is port ( clk : in std_ulogic; rstn : in std_ulogic; cpu_or1knd_i5_mmu_data_ctrl_in : in cpu_or1knd_i5_mmu_data_ctrl_in_type; cpu_or1knd_i5_mmu_data_dp_in : in cpu_or1knd_i5_mmu_data_dp_in_type; cpu_or1knd_i5_mmu_data_ctrl_out : out cpu_or1knd_i5_mmu_data_ctrl_out_type; cpu_or1knd_i5_mmu_data_dp_out : out cpu_or1knd_i5_mmu_data_dp_out_type; cpu_or1knd_i5_mmu_data_ctrl_in_pipe : in cpu_or1knd_i5_mmu_data_ctrl_in_pipe_type; cpu_or1knd_i5_mmu_data_dp_in_pipe : in cpu_or1knd_i5_mmu_data_dp_in_pipe_type; cpu_or1knd_i5_mmu_data_ctrl_out_pipe : out cpu_or1knd_i5_mmu_data_ctrl_out_pipe_type; cpu_or1knd_i5_mmu_data_dp_out_pipe : out cpu_or1knd_i5_mmu_data_dp_out_pipe_type ); end;
use Std.Textio.all; library IEEE; use ieee.std_logic_1164.ALL; entity test_divider is end; architecture test_divider of test_divider is component c_divider generic(width : INTEGER ; const :INTEGER ); port(Input: in std_logic_vector((width - 1) downto 0); Output : out std_logic_vector((width - 1) downto 0)); end component; for all : c_divider use entity WORK.c_divider(behavior); signal Input: std_logic_vector(3 downto 0); signal Output : std_logic_vector(3 downto 0); file S_IN : TEXT is out "c_divider_beh.out"; begin divider_1 : c_divider generic map(4,2) port map(Input, Output); test_process : process begin Input <= "1010"; wait for 50 ns; Input <= "0101"; wait for 50 ns; Input <= "0110"; wait for 50 ns; Input <= "0000"; wait for 50 ns; Input <= "0000"; wait for 50 ns; Input <= "0101"; wait for 50 ns; Input <= "1111"; wait for 50 ns; Input <= "1001"; wait for 50 ns; Input <= "1110"; wait for 50 ns; wait; end process test_process; end test_divider;
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3 -- IP Revision: 1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY blk_mem_gen_v8_3_1; USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1; ENTITY blk_mem_gen_0 IS PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END blk_mem_gen_0; ARCHITECTURE blk_mem_gen_0_arch OF blk_mem_gen_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_0_arch: ARCHITECTURE IS "yes"; COMPONENT blk_mem_gen_v8_3_1 IS GENERIC ( C_FAMILY : STRING; C_XDEVICEFAMILY : STRING; C_ELABORATION_DIR : STRING; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_AXI_SLAVE_TYPE : INTEGER; C_USE_BRAM_BLOCK : INTEGER; C_ENABLE_32BIT_ADDRESS : INTEGER; C_CTRL_ECC_ALGO : STRING; C_HAS_AXI_ID : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_MEM_TYPE : INTEGER; C_BYTE_SIZE : INTEGER; C_ALGORITHM : INTEGER; C_PRIM_TYPE : INTEGER; C_LOAD_INIT_FILE : INTEGER; C_INIT_FILE_NAME : STRING; C_INIT_FILE : STRING; C_USE_DEFAULT_DATA : INTEGER; C_DEFAULT_DATA : STRING; C_HAS_RSTA : INTEGER; C_RST_PRIORITY_A : STRING; C_RSTRAM_A : INTEGER; C_INITA_VAL : STRING; C_HAS_ENA : INTEGER; C_HAS_REGCEA : INTEGER; C_USE_BYTE_WEA : INTEGER; C_WEA_WIDTH : INTEGER; C_WRITE_MODE_A : STRING; C_WRITE_WIDTH_A : INTEGER; C_READ_WIDTH_A : INTEGER; C_WRITE_DEPTH_A : INTEGER; C_READ_DEPTH_A : INTEGER; C_ADDRA_WIDTH : INTEGER; C_HAS_RSTB : INTEGER; C_RST_PRIORITY_B : STRING; C_RSTRAM_B : INTEGER; C_INITB_VAL : STRING; C_HAS_ENB : INTEGER; C_HAS_REGCEB : INTEGER; C_USE_BYTE_WEB : INTEGER; C_WEB_WIDTH : INTEGER; C_WRITE_MODE_B : STRING; C_WRITE_WIDTH_B : INTEGER; C_READ_WIDTH_B : INTEGER; C_WRITE_DEPTH_B : INTEGER; C_READ_DEPTH_B : INTEGER; C_ADDRB_WIDTH : INTEGER; C_HAS_MEM_OUTPUT_REGS_A : INTEGER; C_HAS_MEM_OUTPUT_REGS_B : INTEGER; C_HAS_MUX_OUTPUT_REGS_A : INTEGER; C_HAS_MUX_OUTPUT_REGS_B : INTEGER; C_MUX_PIPELINE_STAGES : INTEGER; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER; C_USE_SOFTECC : INTEGER; C_USE_ECC : INTEGER; C_EN_ECC_PIPE : INTEGER; C_HAS_INJECTERR : INTEGER; C_SIM_COLLISION_CHECK : STRING; C_COMMON_CLK : INTEGER; C_DISABLE_WARN_BHV_COLL : INTEGER; C_EN_SLEEP_PIN : INTEGER; C_USE_URAM : INTEGER; C_EN_RDADDRA_CHG : INTEGER; C_EN_RDADDRB_CHG : INTEGER; C_EN_DEEPSLEEP_PIN : INTEGER; C_EN_SHUTDOWN_PIN : INTEGER; C_EN_SAFETY_CKT : INTEGER; C_DISABLE_WARN_BHV_RANGE : INTEGER; C_COUNT_36K_BRAM : STRING; C_COUNT_18K_BRAM : STRING; C_EST_POWER_SUMMARY : STRING ); PORT ( clka : IN STD_LOGIC; rsta : IN STD_LOGIC; ena : IN STD_LOGIC; regcea : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); clkb : IN STD_LOGIC; rstb : IN STD_LOGIC; enb : IN STD_LOGIC; regceb : IN STD_LOGIC; web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); injectsbiterr : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; eccpipece : IN STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); sleep : IN STD_LOGIC; deepsleep : IN STD_LOGIC; shutdown : IN STD_LOGIC; rsta_busy : OUT STD_LOGIC; rstb_busy : OUT STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; s_axi_injectsbiterr : IN STD_LOGIC; s_axi_injectdbiterr : IN STD_LOGIC; s_axi_sbiterr : OUT STD_LOGIC; s_axi_dbiterr : OUT STD_LOGIC; s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT blk_mem_gen_v8_3_1; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN"; ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; BEGIN U0 : blk_mem_gen_v8_3_1 GENERIC MAP ( C_FAMILY => "zynq", C_XDEVICEFAMILY => "zynq", C_ELABORATION_DIR => "./", C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_AXI_SLAVE_TYPE => 0, C_USE_BRAM_BLOCK => 0, C_ENABLE_32BIT_ADDRESS => 0, C_CTRL_ECC_ALGO => "NONE", C_HAS_AXI_ID => 0, C_AXI_ID_WIDTH => 4, C_MEM_TYPE => 0, C_BYTE_SIZE => 9, C_ALGORITHM => 1, C_PRIM_TYPE => 1, C_LOAD_INIT_FILE => 0, C_INIT_FILE_NAME => "no_coe_file_loaded", C_INIT_FILE => "blk_mem_gen_0.mem", C_USE_DEFAULT_DATA => 0, C_DEFAULT_DATA => "0", C_HAS_RSTA => 0, C_RST_PRIORITY_A => "CE", C_RSTRAM_A => 0, C_INITA_VAL => "0", C_HAS_ENA => 1, C_HAS_REGCEA => 0, C_USE_BYTE_WEA => 0, C_WEA_WIDTH => 1, C_WRITE_MODE_A => "WRITE_FIRST", C_WRITE_WIDTH_A => 8, C_READ_WIDTH_A => 8, C_WRITE_DEPTH_A => 256, C_READ_DEPTH_A => 256, C_ADDRA_WIDTH => 8, C_HAS_RSTB => 0, C_RST_PRIORITY_B => "CE", C_RSTRAM_B => 0, C_INITB_VAL => "0", C_HAS_ENB => 0, C_HAS_REGCEB => 0, C_USE_BYTE_WEB => 0, C_WEB_WIDTH => 1, C_WRITE_MODE_B => "WRITE_FIRST", C_WRITE_WIDTH_B => 8, C_READ_WIDTH_B => 8, C_WRITE_DEPTH_B => 256, C_READ_DEPTH_B => 256, C_ADDRB_WIDTH => 8, C_HAS_MEM_OUTPUT_REGS_A => 1, C_HAS_MEM_OUTPUT_REGS_B => 0, C_HAS_MUX_OUTPUT_REGS_A => 0, C_HAS_MUX_OUTPUT_REGS_B => 0, C_MUX_PIPELINE_STAGES => 0, C_HAS_SOFTECC_INPUT_REGS_A => 0, C_HAS_SOFTECC_OUTPUT_REGS_B => 0, C_USE_SOFTECC => 0, C_USE_ECC => 0, C_EN_ECC_PIPE => 0, C_HAS_INJECTERR => 0, C_SIM_COLLISION_CHECK => "ALL", C_COMMON_CLK => 0, C_DISABLE_WARN_BHV_COLL => 0, C_EN_SLEEP_PIN => 0, C_USE_URAM => 0, C_EN_RDADDRA_CHG => 0, C_EN_RDADDRB_CHG => 0, C_EN_DEEPSLEEP_PIN => 0, C_EN_SHUTDOWN_PIN => 0, C_EN_SAFETY_CKT => 0, C_DISABLE_WARN_BHV_RANGE => 0, C_COUNT_36K_BRAM => "0", C_COUNT_18K_BRAM => "1", C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.54005 mW" ) PORT MAP ( clka => clka, rsta => '0', ena => ena, regcea => '0', wea => wea, addra => addra, dina => dina, douta => douta, clkb => '0', rstb => '0', enb => '0', regceb => '0', web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), injectsbiterr => '0', injectdbiterr => '0', eccpipece => '0', sleep => '0', deepsleep => '0', shutdown => '0', s_aclk => '0', s_aresetn => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awvalid => '0', s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wlast => '0', s_axi_wvalid => '0', s_axi_bready => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arvalid => '0', s_axi_rready => '0', s_axi_injectsbiterr => '0', s_axi_injectdbiterr => '0' ); END blk_mem_gen_0_arch;
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.2 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== Library ieee; use ieee.std_logic_1164.all; entity convolve_kernel_fcud is generic ( ID : integer := 2; NUM_STAGE : integer := 4; din0_WIDTH : integer := 32; din1_WIDTH : integer := 32; dout_WIDTH : integer := 32 ); port ( clk : in std_logic; reset : in std_logic; ce : in std_logic; din0 : in std_logic_vector(din0_WIDTH-1 downto 0); din1 : in std_logic_vector(din1_WIDTH-1 downto 0); dout : out std_logic_vector(dout_WIDTH-1 downto 0) ); end entity; architecture arch of convolve_kernel_fcud is --------------------- Component --------------------- component convolve_kernel_ap_fmul_2_max_dsp_32 is port ( aclk : in std_logic; aclken : in std_logic; s_axis_a_tvalid : in std_logic; s_axis_a_tdata : in std_logic_vector(31 downto 0); s_axis_b_tvalid : in std_logic; s_axis_b_tdata : in std_logic_vector(31 downto 0); m_axis_result_tvalid : out std_logic; m_axis_result_tdata : out std_logic_vector(31 downto 0) ); end component; --------------------- Local signal ------------------ signal aclk : std_logic; signal aclken : std_logic; signal a_tvalid : std_logic; signal a_tdata : std_logic_vector(31 downto 0); signal b_tvalid : std_logic; signal b_tdata : std_logic_vector(31 downto 0); signal r_tvalid : std_logic; signal r_tdata : std_logic_vector(31 downto 0); signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0); signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0); begin --------------------- Instantiation ----------------- convolve_kernel_ap_fmul_2_max_dsp_32_u : component convolve_kernel_ap_fmul_2_max_dsp_32 port map ( aclk => aclk, aclken => aclken, s_axis_a_tvalid => a_tvalid, s_axis_a_tdata => a_tdata, s_axis_b_tvalid => b_tvalid, s_axis_b_tdata => b_tdata, m_axis_result_tvalid => r_tvalid, m_axis_result_tdata => r_tdata ); --------------------- Assignment -------------------- aclk <= clk; aclken <= ce; a_tvalid <= '1'; a_tdata <= din0_buf1; b_tvalid <= '1'; b_tdata <= din1_buf1; dout <= r_tdata; --------------------- Input buffer ------------------ process (clk) begin if clk'event and clk = '1' then if ce = '1' then din0_buf1 <= din0; din1_buf1 <= din1; end if; end if; end process; end architecture;
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.2 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== Library ieee; use ieee.std_logic_1164.all; entity convolve_kernel_fcud is generic ( ID : integer := 2; NUM_STAGE : integer := 4; din0_WIDTH : integer := 32; din1_WIDTH : integer := 32; dout_WIDTH : integer := 32 ); port ( clk : in std_logic; reset : in std_logic; ce : in std_logic; din0 : in std_logic_vector(din0_WIDTH-1 downto 0); din1 : in std_logic_vector(din1_WIDTH-1 downto 0); dout : out std_logic_vector(dout_WIDTH-1 downto 0) ); end entity; architecture arch of convolve_kernel_fcud is --------------------- Component --------------------- component convolve_kernel_ap_fmul_2_max_dsp_32 is port ( aclk : in std_logic; aclken : in std_logic; s_axis_a_tvalid : in std_logic; s_axis_a_tdata : in std_logic_vector(31 downto 0); s_axis_b_tvalid : in std_logic; s_axis_b_tdata : in std_logic_vector(31 downto 0); m_axis_result_tvalid : out std_logic; m_axis_result_tdata : out std_logic_vector(31 downto 0) ); end component; --------------------- Local signal ------------------ signal aclk : std_logic; signal aclken : std_logic; signal a_tvalid : std_logic; signal a_tdata : std_logic_vector(31 downto 0); signal b_tvalid : std_logic; signal b_tdata : std_logic_vector(31 downto 0); signal r_tvalid : std_logic; signal r_tdata : std_logic_vector(31 downto 0); signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0); signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0); begin --------------------- Instantiation ----------------- convolve_kernel_ap_fmul_2_max_dsp_32_u : component convolve_kernel_ap_fmul_2_max_dsp_32 port map ( aclk => aclk, aclken => aclken, s_axis_a_tvalid => a_tvalid, s_axis_a_tdata => a_tdata, s_axis_b_tvalid => b_tvalid, s_axis_b_tdata => b_tdata, m_axis_result_tvalid => r_tvalid, m_axis_result_tdata => r_tdata ); --------------------- Assignment -------------------- aclk <= clk; aclken <= ce; a_tvalid <= '1'; a_tdata <= din0_buf1; b_tvalid <= '1'; b_tdata <= din1_buf1; dout <= r_tdata; --------------------- Input buffer ------------------ process (clk) begin if clk'event and clk = '1' then if ce = '1' then din0_buf1 <= din0; din1_buf1 <= din1; end if; end if; end process; end architecture;
-- EMACS settings: -- tab-width: 2; indent-tabs-mode: t -- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Thomas B. Preusser -- -- Package: Simulation constants, functions and utilities. -- -- Description: -- ------------------------------------- -- .. TODO:: No documentation available. -- -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.math_real.all; library PoC; use PoC.utils.all; -- use PoC.strings.all; use PoC.vectors.all; -- use PoC.physical.all; package sim_types is constant C_SIM_VERBOSE : boolean := FALSE; -- POC_VERBOSE -- =========================================================================== -- Simulation Task and Status Management -- =========================================================================== type T_SIM_BOOLVEC is array(integer range <>) of boolean; subtype T_SIM_TEST_ID is integer range -1 to 1023; subtype T_SIM_TEST_NAME is string(1 to 256); subtype T_SIM_PROCESS_ID is natural range 0 to 1023; subtype T_SIM_PROCESS_NAME is string(1 to 64); subtype T_SIM_PROCESS_INSTNAME is string(1 to 256); type T_SIM_PROCESS_ID_VECTOR is array(natural range <>) of T_SIM_PROCESS_ID; type T_SIM_TEST_STATUS is ( SIM_TEST_STATUS_CREATED, SIM_TEST_STATUS_ACTIVE, SIM_TEST_STATUS_ENDED, SIM_TEST_STATUS_ZOMBI ); type T_SIM_PROCESS_STATUS is ( SIM_PROCESS_STATUS_ACTIVE, SIM_PROCESS_STATUS_ENDED ); type T_SIM_TEST is record ID : T_SIM_TEST_ID; Name : T_SIM_TEST_NAME; Status : T_SIM_TEST_STATUS; ProcessIDs : T_SIM_PROCESS_ID_VECTOR(T_SIM_PROCESS_ID); ProcessCount : T_SIM_PROCESS_ID; ActiveProcessCount : T_SIM_PROCESS_ID; end record; type T_SIM_TEST_VECTOR is array(integer range <>) of T_SIM_TEST; type T_SIM_PROCESS is record ID : T_SIM_PROCESS_ID; TestID : T_SIM_TEST_ID; Name : T_SIM_PROCESS_NAME; Status : T_SIM_PROCESS_STATUS; IsLowPriority : boolean; end record; type T_SIM_PROCESS_VECTOR is array(natural range <>) of T_SIM_PROCESS; constant C_SIM_DEFAULT_TEST_ID : T_SIM_TEST_ID := -1; constant C_SIM_DEFAULT_TEST_NAME : string := "Default test"; -- =========================================================================== -- Random Numbers -- =========================================================================== type T_SIM_RAND_SEED is record Seed1 : integer; Seed2 : integer; end record; procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED); procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedValue : in T_SIM_RAND_SEED); procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedVector : in T_INTVEC); procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedVector : in string); function randInitializeSeed return T_SIM_RAND_SEED; function randInitializeSeed(SeedValue : T_SIM_RAND_SEED) return T_SIM_RAND_SEED; function randInitializeSeed(SeedVector : T_INTVEC) return T_SIM_RAND_SEED; function randInitializeSeed(SeedVector : string) return T_SIM_RAND_SEED; -- Uniform distributed random values -- =========================================================================== procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL); procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; Minimum : integer; Maximum : integer); procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Minimum : REAL; Maximum : REAL); -- Normal / Gaussian distributed random values -- =========================================================================== procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; StandardDeviation : REAL := 1.0; Mean : REAL := 0.0); procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer); procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL); -- Poisson distributed random values -- =========================================================================== procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Mean : in REAL); procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; Mean : in REAL; Minimum : in integer; Maximum : in integer); procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL); -- =========================================================================== -- Clock Generation -- =========================================================================== -- type T_PERCENT is INTEGER'range units type T_PERCENT is range integer'low to INTEGER'high units ppb; ppm = 1000 ppb; permil = 1000 ppm; percent = 10 permil; one = 100 percent; end units; subtype T_WANDER is T_PERCENT range -1 one to 1 one; subtype T_DUTYCYCLE is T_PERCENT range 0 ppb to 1 one; type T_DEGREE is range integer'low to INTEGER'high units second; minute = 60 second; deg = 60 minute; end units; subtype T_PHASE is T_DEGREE range -360 deg to 360 deg; function ite(cond : boolean; value1 : T_DEGREE; value2 : T_DEGREE) return T_DEGREE; end package; package body sim_types is function ite(cond : boolean; value1 : T_DEGREE; value2 : T_DEGREE) return T_DEGREE is begin if cond then return value1; else return value2; end if; end function; -- =========================================================================== -- Random Numbers -- =========================================================================== constant MAX_SEED1_VALUE : positive := 2147483562; constant MAX_SEED2_VALUE : positive := 2147483398; function randGenerateInitialSeed return T_SIM_RAND_SEED is begin return ( Seed1 => 5, Seed2 => 3423 ); end function; function randBoundSeed(SeedValue : in T_SIM_RAND_SEED) return T_SIM_RAND_SEED is begin return ( Seed1 => (SeedValue.Seed1 - 1 mod MAX_SEED1_VALUE) + 1, Seed2 => (SeedValue.Seed2 - 1 mod MAX_SEED2_VALUE) + 1 ); end function; procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED) is begin Seed := randGenerateInitialSeed; end procedure; procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedValue : in T_SIM_RAND_SEED) is begin Seed := randBoundSeed(SeedValue); end procedure; procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedVector : in T_INTVEC) is begin if (SeedVector'length = 0) then Seed := randGenerateInitialSeed; elsif (SeedVector'length = 1) then Seed := randBoundSeed(T_SIM_RAND_SEED'( Seed1 => SeedVector(0), Seed2 => 92346 )); elsif (SeedVector'length = 2) then Seed := randBoundSeed(T_SIM_RAND_SEED'( Seed1 => SeedVector(0), Seed2 => SeedVector(1) )); else -- FIXME: -- Seed.Seed1 := SeedVector(0); -- Seed.Seed2 := SeedVector(1); end if; end procedure; procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedVector : in string) is begin if (SeedVector'length = 0) then Seed := randGenerateInitialSeed; elsif (SeedVector'length = 1) then Seed := T_SIM_RAND_SEED'( Seed1 => character'pos(SeedVector(1)), Seed2 => 39834 ); elsif (SeedVector'length = 2) then Seed := T_SIM_RAND_SEED'( Seed1 => character'pos(SeedVector(1)), Seed2 => character'pos(SeedVector(2)) ); else -- FIXME: -- Seed.Seed1 := CHARACTER'pos(SeedVector(0)); -- Seed.Seed2 := CHARACTER'pos(SeedVector(1)); end if; end procedure; function randInitializeSeed return T_SIM_RAND_SEED is begin return randGenerateInitialSeed; end function; function randInitializeSeed(SeedValue : T_SIM_RAND_SEED) return T_SIM_RAND_SEED is begin return randBoundSeed(SeedValue); end function; function randInitializeSeed(SeedVector : T_INTVEC) return T_SIM_RAND_SEED is variable Result : T_SIM_RAND_SEED; begin randInitializeSeed(Result, SeedVector); return Result; end function; function randInitializeSeed(SeedVector : string) return T_SIM_RAND_SEED is variable Result : T_SIM_RAND_SEED; begin randInitializeSeed(Result, SeedVector); return Result; end function; -- =========================================================================== -- Uniform distributed random values -- =========================================================================== procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL) is begin ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, Value); end procedure; procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; Minimum : integer; Maximum : integer) is variable rand : REAL; begin if Maximum < Minimum then report "randUniformDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand); Value := scale(rand, Minimum, Maximum); end procedure; procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Minimum : REAL; Maximum : REAL) is variable rand : REAL; begin if Maximum < Minimum then report "randUniformDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand); Value := scale(rand, Minimum, Maximum); end procedure; -- =========================================================================== -- Normal / Gaussian distributed random values -- =========================================================================== procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; StandardDeviation : REAL := 1.0; Mean : REAL := 0.0) is variable rand1 : REAL; variable rand2 : REAL; begin if StandardDeviation < 0.0 then report "randNormalDistributedValue: Standard deviation must be >= 0.0" severity FAILURE; end if; -- Box Muller transformation ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand1); ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand2); -- standard normal distribution: mean 0, variance 1 Value := StandardDeviation * (sqrt(-2.0 * log(rand1)) * cos(MATH_2_PI * rand2)) + Mean; end procedure; procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer) is variable rand_real : REAL; variable rand_int : integer; begin if Maximum < Minimum then report "randNormalDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; if StandardDeviation < 0.0 then report "randNormalDistributedValue: Standard deviation must be >= 0.0" severity FAILURE; end if; while TRUE loop randNormalDistributedValue(Seed, rand_real, StandardDeviation, Mean); rand_int := integer(round(rand_real)); exit when ((Minimum <= rand_int) and (rand_int <= Maximum)); end loop; Value := rand_int; end procedure; procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) is variable rand : REAL; begin if Maximum < Minimum then report "randNormalDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; if StandardDeviation < 0.0 then report "randNormalDistributedValue: Standard deviation must be >= 0.0" severity FAILURE; end if; while TRUE loop randNormalDistributedValue(Seed, rand, StandardDeviation, Mean); exit when ((Minimum <= rand) and (rand <= Maximum)); end loop; Value := rand; end procedure; -- =========================================================================== -- Poisson distributed random values -- =========================================================================== procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Mean : in REAL) is variable Product : Real; variable Bound : Real; variable rand : Real; variable Result : Real; begin Product := 1.0; Result := 0.0; Bound := exp(-1.0 * Mean); if ((Mean <= 0.0) or (Bound <= 0.0)) then report "randPoissonDistributedValue: Mean must be greater than 0.0." severity FAILURE; return; end if; while (Product >= Bound) loop ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand); Product := Product * rand; Result := Result + 1.0; end loop; Value := Result; end procedure; procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; Mean : in REAL; Minimum : in integer; Maximum : in integer) is variable rand_real : REAL; variable rand_int : integer; begin if Maximum < Minimum then report "randPoissonDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; while TRUE loop randPoissonDistributedValue(Seed, rand_real, Mean); rand_int := integer(round(rand_real)); exit when ((Minimum <= rand_int) and (rand_int <= Maximum)); end loop; Value := rand_int; end procedure; procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) is variable rand : REAL; begin if Maximum < Minimum then report "randPoissonDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; while TRUE loop randPoissonDistributedValue(Seed, rand, Mean); exit when ((Minimum <= rand) and (rand <= Maximum)); end loop; Value := rand; end procedure; end package body;
divisor2_inst : divisor2 PORT MAP ( clock => clock_sig, cout => cout_sig, q => q_sig );
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1103.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c06s05b00x00p03n01i01103ent IS END c06s05b00x00p03n01i01103ent; ARCHITECTURE c06s05b00x00p03n01i01103arch OF c06s05b00x00p03n01i01103ent IS BEGIN TESTING: PROCESS type FIVE is range 1 to 5; type ABASE is array (FIVE range <>) of BOOLEAN; subtype A1 is ABASE(FIVE); type R1 is record RE1: A1; end record; type R2 is record RE2: R1; end record; variable V1: A1; variable V2: R1 ; -- := (RE1=>(others=>TRUE)); variable V3: R2 ; -- := (RE2=>(RE1=>(others=>TRUE))); BEGIN V1(2 to 4) := V2.RE1(2 to 4); -- No_failure_here assert NOT(V1(2 to 4)=(false,false,false)) report "*PASSED TEST: c06s05b00x00p03n01i01103" severity NOTE; assert (V1(2 to 4)=(false,false,false)) report "*FAILED TEST: c06s05b00x00p03n01i01103 - Prefix of a slice can be a selected name." severity ERROR; wait; END PROCESS TESTING; END c06s05b00x00p03n01i01103arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1103.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c06s05b00x00p03n01i01103ent IS END c06s05b00x00p03n01i01103ent; ARCHITECTURE c06s05b00x00p03n01i01103arch OF c06s05b00x00p03n01i01103ent IS BEGIN TESTING: PROCESS type FIVE is range 1 to 5; type ABASE is array (FIVE range <>) of BOOLEAN; subtype A1 is ABASE(FIVE); type R1 is record RE1: A1; end record; type R2 is record RE2: R1; end record; variable V1: A1; variable V2: R1 ; -- := (RE1=>(others=>TRUE)); variable V3: R2 ; -- := (RE2=>(RE1=>(others=>TRUE))); BEGIN V1(2 to 4) := V2.RE1(2 to 4); -- No_failure_here assert NOT(V1(2 to 4)=(false,false,false)) report "*PASSED TEST: c06s05b00x00p03n01i01103" severity NOTE; assert (V1(2 to 4)=(false,false,false)) report "*FAILED TEST: c06s05b00x00p03n01i01103 - Prefix of a slice can be a selected name." severity ERROR; wait; END PROCESS TESTING; END c06s05b00x00p03n01i01103arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1103.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c06s05b00x00p03n01i01103ent IS END c06s05b00x00p03n01i01103ent; ARCHITECTURE c06s05b00x00p03n01i01103arch OF c06s05b00x00p03n01i01103ent IS BEGIN TESTING: PROCESS type FIVE is range 1 to 5; type ABASE is array (FIVE range <>) of BOOLEAN; subtype A1 is ABASE(FIVE); type R1 is record RE1: A1; end record; type R2 is record RE2: R1; end record; variable V1: A1; variable V2: R1 ; -- := (RE1=>(others=>TRUE)); variable V3: R2 ; -- := (RE2=>(RE1=>(others=>TRUE))); BEGIN V1(2 to 4) := V2.RE1(2 to 4); -- No_failure_here assert NOT(V1(2 to 4)=(false,false,false)) report "*PASSED TEST: c06s05b00x00p03n01i01103" severity NOTE; assert (V1(2 to 4)=(false,false,false)) report "*FAILED TEST: c06s05b00x00p03n01i01103 - Prefix of a slice can be a selected name." severity ERROR; wait; END PROCESS TESTING; END c06s05b00x00p03n01i01103arch;
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity p_jinfo_comps_info_dc_tbl_no is port ( wa0_data : in std_logic; wa0_addr : in std_logic_vector(1 downto 0); clk : in std_logic; ra0_addr : in std_logic_vector(1 downto 0); ra0_data : out std_logic; wa0_en : in std_logic ); end p_jinfo_comps_info_dc_tbl_no; architecture augh of p_jinfo_comps_info_dc_tbl_no is -- Embedded RAM type ram_type is array (0 to 2) of std_logic; signal ram : ram_type := (others => '0'); -- Little utility functions to make VHDL syntactically correct -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. -- This happens when accessing arrays with <= 2 cells, for example. function to_integer(B: std_logic) return integer is variable V: std_logic_vector(0 to 0); begin V(0) := B; return to_integer(unsigned(V)); end; function to_integer(V: std_logic_vector) return integer is begin return to_integer(unsigned(V)); end; begin -- Sequential process -- It handles the Writes process (clk) begin if rising_edge(clk) then -- Write to the RAM -- Note: there should be only one port. if wa0_en = '1' then ram( to_integer(wa0_addr) ) <= wa0_data; end if; end if; end process; -- The Read side (the outputs) ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 3 else '-'; end architecture;
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity p_jinfo_comps_info_dc_tbl_no is port ( wa0_data : in std_logic; wa0_addr : in std_logic_vector(1 downto 0); clk : in std_logic; ra0_addr : in std_logic_vector(1 downto 0); ra0_data : out std_logic; wa0_en : in std_logic ); end p_jinfo_comps_info_dc_tbl_no; architecture augh of p_jinfo_comps_info_dc_tbl_no is -- Embedded RAM type ram_type is array (0 to 2) of std_logic; signal ram : ram_type := (others => '0'); -- Little utility functions to make VHDL syntactically correct -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. -- This happens when accessing arrays with <= 2 cells, for example. function to_integer(B: std_logic) return integer is variable V: std_logic_vector(0 to 0); begin V(0) := B; return to_integer(unsigned(V)); end; function to_integer(V: std_logic_vector) return integer is begin return to_integer(unsigned(V)); end; begin -- Sequential process -- It handles the Writes process (clk) begin if rising_edge(clk) then -- Write to the RAM -- Note: there should be only one port. if wa0_en = '1' then ram( to_integer(wa0_addr) ) <= wa0_data; end if; end if; end process; -- The Read side (the outputs) ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 3 else '-'; end architecture;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1714.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c09s02b00x00p10n01i01714ent IS port (signal max : in natural); type word is array (natural range <>) of bit; subtype mem_array is word (0 to 7); END c09s02b00x00p10n01i01714ent; ARCHITECTURE c09s02b00x00p10n01i01714arch OF c09s02b00x00p10n01i01714ent IS signal idx : natural; signal mem : mem_array; BEGIN TESTING: PROCESS(bit_vector'("10101")) BEGIN assert FALSE report "***FAILED TEST: c09s02b00x00p10n01i01714 - Process sensitivity list can not be a qualified string." severity ERROR; END PROCESS TESTING; END c09s02b00x00p10n01i01714arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1714.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c09s02b00x00p10n01i01714ent IS port (signal max : in natural); type word is array (natural range <>) of bit; subtype mem_array is word (0 to 7); END c09s02b00x00p10n01i01714ent; ARCHITECTURE c09s02b00x00p10n01i01714arch OF c09s02b00x00p10n01i01714ent IS signal idx : natural; signal mem : mem_array; BEGIN TESTING: PROCESS(bit_vector'("10101")) BEGIN assert FALSE report "***FAILED TEST: c09s02b00x00p10n01i01714 - Process sensitivity list can not be a qualified string." severity ERROR; END PROCESS TESTING; END c09s02b00x00p10n01i01714arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1714.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c09s02b00x00p10n01i01714ent IS port (signal max : in natural); type word is array (natural range <>) of bit; subtype mem_array is word (0 to 7); END c09s02b00x00p10n01i01714ent; ARCHITECTURE c09s02b00x00p10n01i01714arch OF c09s02b00x00p10n01i01714ent IS signal idx : natural; signal mem : mem_array; BEGIN TESTING: PROCESS(bit_vector'("10101")) BEGIN assert FALSE report "***FAILED TEST: c09s02b00x00p10n01i01714 - Process sensitivity list can not be a qualified string." severity ERROR; END PROCESS TESTING; END c09s02b00x00p10n01i01714arch;
entity array1 is end entity; architecture test of array1 is type matrix_t is array (integer range <>, integer range <>) of integer; constant c : matrix_t(0 to 1, 0 to 1) := ( ( 1, 2 ), ( 3, 4 ) ); begin process is variable m : matrix_t(1 to 3, 1 to 3) := ( ( 1, 2, 3 ), ( 4, 5, 6 ), ( 7, 8, 9 ) ); begin report integer'image(m(1, 3)); report integer'image(m(2, 2)); assert m(2, 2) = 5; assert m(3, 1) = 7; report integer'image(c(1, 0)); assert c(1, 0) = 3; assert c = ( (1, 2), (3, 4) ); assert c /= ( (1, 2), (3, 5) ); wait; end process; end architecture;
--! --! Copyright (C) 2010 - 2013 Creonic GmbH --! --! @file: periodic_stimuli.vhd --! @brief: write and simulate a vhdl code that generates the signs sig1 and sig2 and signal y --! @author: Antonio Gutierrez --! @date: 2014-04-01 --! --! -------------------------------------- library ieee; use ieee.std_logic_1164.all; -------------------------------------- entity periodic_stimuli is --generic declarations end entity periodic_stimuli; -------------------------------------- architecture circuit of periodic_stimuli is signal sig1: std_logic := '1'; signal sig2: std_logic := '1'; signal y: std_logic: = '1'; begin -- stimuli sig1 -- (ii) sequential sig1_proc: process begin sig1 <= '1'; wait for 25 ns; sig1 <= '0'; wait for 50 ns; end process sig1_proc; sig2_proc: process begin sig2 <= '1'; wait for 25 ns; sig2 <= '0'; wait for 50 ns; sig2 <= '1'; wait for 25 ns; sig2 <= '0'; wait for 25 ns; sig2 <= '1'; wait for 50 ns; sig2 <= '0'; wait for 25 ns; end process sig2_proc; y_proc: process begin y <= '1'; wait for 20 ns; y <= '0'; wait for 10 ns; y <= '1'; wait for 10 ns; y <= '0'; wait for 40 ns; end process y_proc; end architecture circuit; --------------------------------------
-- -- Copyright (C) 2009-2012 Chris McClelland -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU Lesser General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Lesser General Public License for more details. -- -- You should have received a copy of the GNU Lesser General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity trace_fifo_wrapper is port( -- Clock clk_in : in std_logic; depth_out : out std_logic_vector(12 downto 0); -- Data is clocked into the FIFO on each clock edge where both valid & ready are high inputData_in : in std_logic_vector(55 downto 0); inputValid_in : in std_logic; inputReady_out : out std_logic; -- Data is clocked out of the FIFO on each clock edge where both valid & ready are high outputData_out : out std_logic_vector(55 downto 0); outputValid_out : out std_logic; outputReady_in : in std_logic ); end entity; architecture structural of trace_fifo_wrapper is signal inputFull : std_logic; signal outputEmpty : std_logic; begin -- Invert "full/empty" signals to give "ready/valid" signals inputReady_out <= not(inputFull); outputValid_out <= not(outputEmpty); -- The encapsulated FIFO fifo : entity work.xilinx_trace_fifo port map( clk => clk_in, data_count => depth_out, -- Production end din => inputData_in, wr_en => inputValid_in, full => inputFull, -- Consumption end dout => outputData_out, empty => outputEmpty, rd_en => outputReady_in ); end architecture;
--! --! Copyright 2019 Sergey Khabarov, sergeykhbr@gmail.com --! --! Licensed under the Apache License, Version 2.0 (the "License"); --! you may not use this file except in compliance with the License. --! You may obtain a copy of the License at --! --! http://www.apache.org/licenses/LICENSE-2.0 --! --! Unless required by applicable law or agreed to in writing, software --! distributed under the License is distributed on an "AS IS" BASIS, --! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --! See the License for the specific language governing permissions and --! limitations under the License. --! library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; -- or_reduce() library commonlib; use commonlib.types_common.all; library techmap; use techmap.types_mem.all; entity tagmem is generic ( memtech : integer := 0; async_reset : boolean := false; wayidx : integer := 0; abus : integer := 64; -- system bus address bus (32 or 64 bits) ibits : integer := 7; -- lines memory addres width (usually 6..8) lnbits : integer := 5; -- One line bits: log2(bytes_per_line) flbits : integer := 1; -- Total flags number saved with address tag snoop : boolean := false -- snoop channel (only with enabled L2-cache) ); port ( i_clk : in std_logic; i_nrst : in std_logic; i_addr : in std_logic_vector(abus-1 downto 0); i_wstrb : in std_logic_vector(2*lnbits-1 downto 0); i_wdata : in std_logic_vector(8(2*lnbits)-1 downto 0); i_wflags : in std_logic_vector(flbits-1 downto 0); o_raddr : out std_logic_vector(abus-1 downto 0); o_rdata : out std_logic_vector(8(2lnbits)-1 downto 0); o_rflags : out std_logic_vector(flbits-1 downto 0); o_hit : out std_logic; -- L2 snoop portm active when snoop = 1 i_snoop_addr : in std_logic_vector(abus-1 downto 0); o_snoop_flags : out std_logic_vector(flbits-1 downto 0) ); end; architecture arch_tagmem of tagmem is constant TAG_BITS : integer := abus - ibits - lnbits; constant TAG_WITH_FLAGS : integer := TAG_BITS + flbits; signal wb_index : std_logic_vector(ibits-1 downto 0); signal tago_rdata : std_logic_vector(TAG_WITH_FLAGS-1 downto 0); signal tagi_wdata : std_logic_vector(TAG_WITH_FLAGS-1 downto 0); signal tagi_we : std_logic; signal wb_snoop_index : std_logic_vector(ibits-1 downto 0); signal wb_snoop_tagaddr : std_logic_vector(TAG_BITS-1 downto 0); signal tago_snoop_rdata : std_logic_vector(TAG_WITH_FLAGS-1 downto 0); signal rb_tagaddr : std_logic_vector(TAG_BITS-1 downto 0); signal rb_index : std_logic_vector(ibits-1 downto 0); signal rb_snoop_tagaddr : std_logic_vector(TAG_BITS-1 downto 0); begin -- 1-byte memory banks combining into cache line dx : for n in 0 to 2lnbits-1 generate datax : ram_tech generic map ( memtech => memtech, abits => ibits, dbits => 8 ) port map ( i_clk => i_clk, i_addr => wb_index, i_wena => i_wstrb(n), i_wdata => i_wdata(8n+7 downto 8n), o_rdata => o_rdata(8n+7 downto 8n) ); end generate; tag0 : ram_tech generic map ( memtech => memtech, abits => ibits, dbits => TAG_WITH_FLAGS ) port map ( i_clk => i_clk, i_addr => wb_index, i_wena => tagi_we, i_wdata => tagi_wdata, o_rdata => tago_rdata ); snoopena : if snoop generate tagsnoop0 : ram_tech generic map ( memtech => memtech, abits => ibits, dbits => TAG_WITH_FLAGS ) port map ( i_clk => i_clk, i_addr => wb_snoop_index, i_wena => tagi_we, i_wdata => tagi_wdata, o_rdata => tago_snoop_rdata ); end generate; snoopdis : if not snoop generate tago_snoop_rdata <= (others => '0'); end generate; comb : process(i_nrst, i_addr, i_wstrb, i_wdata, i_wflags, tago_rdata, tago_snoop_rdata, rb_tagaddr, rb_index) variable vb_index : std_logic_vector(ibits-1 downto 0); variable vb_raddr : std_logic_vector(abus-1 downto 0); variable vb_tagi_wdata : std_logic_vector(TAG_WITH_FLAGS-1 downto 0); variable v_hit : std_logic; variable vb_snoop_index : std_logic_vector(ibits-1 downto 0); variable vb_snoop_tagaddr : std_logic_vector(TAG_BITS-1 downto 0); variable vb_snoop_flags : std_logic_vector(flbits-1 downto 0); begin v_hit := '0'; if rb_tagaddr = tago_rdata(TAG_BITS-1 downto 0) then v_hit := tago_rdata(TAG_BITS); -- valid bit end if; vb_raddr := (others => '0'); vb_raddr(abus-1 downto ibits + lnbits) := tago_rdata(TAG_BITS-1 downto 0); vb_raddr(ibits + lnbits - 1 downto lnbits) := rb_index; vb_index := i_addr(ibits + lnbits - 1 downto lnbits); vb_tagi_wdata := i_wflags & i_addr(abus-1 downto ibits + lnbits); if snoop then vb_snoop_flags := tago_snoop_rdata(TAG_WITH_FLAGS-1 downto TAG_BITS); vb_snoop_index := i_snoop_addr(ibits + lnbits - 1 downto lnbits); vb_snoop_tagaddr := i_snoop_addr(abus - 1 downto ibits + lnbits); if or_reduce(i_wstrb) = '1' then vb_snoop_index := vb_index; end if; if rb_snoop_tagaddr /= tago_snoop_rdata(TAG_BITS-1 downto 0) then vb_snoop_flags := (others => '0'); end if; else vb_snoop_flags := (others => '0'); vb_snoop_index := (others => '0'); vb_snoop_tagaddr := (others => '0'); end if; if not async_reset and i_nrst = '0' then vb_tagi_wdata := (others => '0'); vb_index := (others => '0'); end if; wb_index <= vb_index; tagi_we <= or_reduce(i_wstrb); tagi_wdata <= vb_tagi_wdata; o_raddr <= vb_raddr; o_rflags <= tago_rdata(TAG_WITH_FLAGS-1 downto TAG_BITS); o_hit <= v_hit; wb_snoop_index <= vb_snoop_index; wb_snoop_tagaddr <= vb_snoop_tagaddr; o_snoop_flags <= vb_snoop_flags; end process; -- registers: regs : process(i_clk, i_nrst) begin if async_reset and i_nrst = '0' then rb_tagaddr <= (others => '0'); rb_index <= (others => '0'); rb_snoop_tagaddr <= (others => '0'); elsif rising_edge(i_clk) then rb_tagaddr <= tagi_wdata(TAG_BITS-1 downto 0); rb_index <= wb_index; rb_snoop_tagaddr <= wb_snoop_tagaddr; end if; end process; end;
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use IEEE.NUMERIC_STD.all; use ieee.math_real.all; use std.textio.all; use ieee.std_logic_misc.all; package TB_Package is function Header_gen(Packet_length, source, destination, packet_id: integer ) return std_logic_vector ; function Body_gen(Packet_length, Data: integer ) return std_logic_vector ; function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ; procedure gen_packet(Packet_length, source, destination, packet_id, initial_delay: in integer; finish_time: in time; signal clk: in std_logic; signal DCTS: in std_logic; signal RTS: out std_logic; signal port_in: out std_logic_vector); procedure gen_random_packet(frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer; finish_time: in time; signal clk: in std_logic; signal DCTS: in std_logic; signal RTS: out std_logic; signal port_in: out std_logic_vector); procedure gen_bit_reversed_packet(frame_length, source, initial_delay, network_size, min_packet_size, max_packet_size: in integer; finish_time: in time; signal clk: in std_logic; signal DCTS: in std_logic; signal RTS: out std_logic; signal port_in: out std_logic_vector); procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic; signal CTS: out std_logic; signal DRTS: in std_logic; signal port_in: in std_logic_vector); procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer); end TB_Package; package body TB_Package is constant Header_type : std_logic_vector := "001"; constant Body_type : std_logic_vector := "010"; constant Tail_type : std_logic_vector := "100"; function Header_gen(Packet_length, source, destination, packet_id: integer) return std_logic_vector is variable Header_flit: std_logic_vector (31 downto 0); begin Header_flit := Header_type & std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) & std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)) & XOR_REDUCE(Header_type & std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) & std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8))); return Header_flit; end Header_gen; function Body_gen(Packet_length, Data: integer) return std_logic_vector is variable Body_flit: std_logic_vector (31 downto 0); begin Body_flit := Body_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Data, 28))); return Body_flit; end Body_gen; function Tail_gen(Packet_length, Data: integer) return std_logic_vector is variable Tail_flit: std_logic_vector (31 downto 0); begin Tail_flit := Tail_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Tail_type & std_logic_vector(to_unsigned(Data, 28))); return Tail_flit; end Tail_gen; procedure gen_packet(Packet_length, source, destination, packet_id, initial_delay: in integer; finish_time: in time; signal clk: in std_logic; signal DCTS: in std_logic; signal RTS: out std_logic; signal port_in: out std_logic_vector) is -- Packet_length of 3 means it has 1 header, 1 body and 1 tail. the number of body packets are equal to Packet_length-2 -- source: id of the source node -- destination: id of the destination node -- packet id: packet identification number! TODO: has to be implemented! -- initial_delay: waits for this number of clock cycles before sending the packet! variable seed1 :positive ; variable seed2 :positive ; variable rand : real ; variable first_time :boolean := true; variable destination_id: integer; variable LINEVARIABLE : line; file VEC_FILE : text is out "sent.txt"; begin while true loop RTS <= '0'; if first_time = true then for i in 0 to initial_delay loop wait until clk'event and clk ='0'; end loop; else wait until clk'event and clk ='0'; end if; --wait untill the falling edge of the clock to avoid race! report "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination); write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination) & " with length: "& integer'image(Packet_length)); writeline(VEC_FILE, LINEVARIABLE); port_in <= Header_gen(Packet_length, source, destination, packet_id); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; for I in 0 to Packet_length-3 loop uniform(seed1, seed2, rand); wait until clk'event and clk ='0'; port_in <= Body_gen(Packet_length, integer(rand1000.0)); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; end loop; wait until clk'event and clk ='0'; port_in <= Tail_gen(Packet_length, 200); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; if now > finish_time then wait; end if; end loop; end gen_packet; procedure gen_random_packet(frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer; finish_time: in time; signal clk: in std_logic; signal DCTS: in std_logic; signal RTS: out std_logic; signal port_in: out std_logic_vector) is -- frame_length is inverse of PIR. with the unit of clock cycles. which means how many clock cycles per packet to -- be injected. to build a true random traffic generator, we need to make a series of frames: -- -- -- <--- Frame length-----> <--- Frame length-----> <--- Frame length-----> -- -- <-----> \|<--------\|///////\|---->\|<----\|///////////\|---->\|<-\|////\|-------------->\| -- initial <-------> <----------> <-------------> -- delay frame Packet_size frame -- initial end delay -- delay -- -- source: id of the source node -- initial_delay: waits for this number of clock cycles before sending the packet! variable seed1 :positive ; variable seed2 :positive ; variable rand : real ; variable first_time :boolean := true; variable id_counter : integer:= 0; variable frame_starting_delay, Packet_length, frame_ending_delay: integer := 0; variable destination_id: integer; variable LINEVARIABLE : line; file VEC_FILE : text is out "sent.txt"; begin while true loop -- generating the ID id_counter := id_counter + 1; if id_counter = 256 then id_counter := 0; end if; -- generating the packet length uniform(seed1, seed2, rand); Packet_length := integer((integer(rand100.0)frame_length)/300); if (Packet_length < min_packet_size) then Packet_length:=min_packet_size; end if; if (Packet_length > max_packet_size) then Packet_length:=max_packet_size; end if; assert (3Packet_length<=frame_length) report "packet_length "& integer'image(Packet_length)&" exceeds frame size "& integer'image(frame_length) severity failure; --generating the frame initial delay uniform(seed1, seed2, rand); frame_starting_delay := integer(((integer(rand100.0)(frame_length - 3Packet_length)))/100); --generating the frame ending delay frame_ending_delay := frame_length - (3Packet_length+frame_starting_delay); RTS <= '0'; if first_time = true then port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ; wait until clk'event and clk ='1'; for i in 0 to initial_delay loop -- wait until clk'event and clk ='0'; wait for 1 ns; end loop; port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ; wait until clk'event and clk ='1'; for k in 0 to frame_starting_delay-1 loop --wait until clk'event and clk ='0'; wait for 1 ns; end loop; first_time := false; else wait until clk'event and clk ='1'; for k in 0 to frame_starting_delay-1 loop --wait until clk'event and clk ='0'; wait for 1 ns; end loop; end if; uniform(seed1, seed2, rand); destination_id := integer(rand3.0); while (destination_id = source) loop uniform(seed1, seed2, rand); destination_id := integer(rand3.0); end loop; --wait untill the falling edge of the clock to avoid race! report "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id); write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: "& integer'image(Packet_length)& " with id: "&integer'image(id_counter)); writeline(VEC_FILE, LINEVARIABLE); port_in <= Header_gen(Packet_length, source, destination_id, id_counter); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; for I in 0 to Packet_length-3 loop uniform(seed1, seed2, rand); wait until clk'event and clk ='0'; port_in <= Body_gen(Packet_length, integer(rand1000.0)); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; end loop; wait until clk'event and clk ='0'; uniform(seed1, seed2, rand); port_in <= Tail_gen(Packet_length, integer(rand1000.0)); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ; for l in 0 to frame_ending_delay-1 loop wait for 1 ns; end loop; port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ; if now > finish_time then wait; end if; end loop; end gen_random_packet; procedure gen_bit_reversed_packet(frame_length, source, initial_delay, network_size, min_packet_size, max_packet_size: in integer; finish_time: in time; signal clk: in std_logic; signal DCTS: in std_logic; signal RTS: out std_logic; signal port_in: out std_logic_vector) is -- frame_length is inverse of PIR. with the unit of clock cycles. which means how many clock cycles per packet to -- be injected. to build a true random traffic generator, we need to make a series of frames: -- -- -- <--- Frame length-----> <--- Frame length-----> <--- Frame length-----> -- -- <-----> \|<--------\|///////\|---->\|<----\|///////////\|---->\|<-\|////\|-------------->\| -- initial <-------> <----------> <-------------> -- delay frame Packet_size frame -- initial end delay -- delay -- -- source: id of the source node -- initial_delay: waits for this number of clock cycles before sending the packet! variable seed1 :positive ; variable seed2 :positive ; variable rand : real ; variable first_time :boolean := true; variable id_counter : integer:= 0; variable frame_starting_delay, Packet_length, frame_ending_delay: integer := 0; variable destination_id: integer; variable LINEVARIABLE : line; file VEC_FILE : text is out "sent.txt"; begin while true loop -- generating the ID id_counter := id_counter + 1; if id_counter = 256 then id_counter := 0; end if; -- generating the packet length uniform(seed1, seed2, rand); Packet_length := integer((integer(rand100.0)/300)frame_length); if (Packet_length < min_packet_size) then Packet_length := min_packet_size; end if; if (Packet_length > max_packet_size) then Packet_length := max_packet_size; end if; assert (3Packet_length<=frame_length) report "packet_length "& integer'image(Packet_length)&" exceeds frame size "& integer'image(frame_length) severity failure; --generating the frame initial delay uniform(seed1, seed2, rand); frame_starting_delay := integer(((integer(rand100.0)(frame_length - 3Packet_length)))/100); --generating the frame ending delay frame_ending_delay := frame_length - (3Packet_length+frame_starting_delay); RTS <= '0'; if first_time = true then port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ; wait until clk'event and clk ='1'; for i in 0 to initial_delay loop -- wait until clk'event and clk ='0'; wait for 1 ns; end loop; port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ; wait until clk'event and clk ='1'; for k in 0 to frame_starting_delay-1 loop --wait until clk'event and clk ='0'; wait for 1 ns; end loop; first_time := false; else wait until clk'event and clk ='1'; for k in 0 to frame_starting_delay-1 loop --wait until clk'event and clk ='0'; wait for 1 ns; end loop; end if; destination_id := to_integer(unsigned(not std_logic_vector(to_unsigned(source, network_size)))); if destination_id = source then wait; end if; --wait untill the falling edge of the clock to avoid race! report "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id); report " frame_size: " & integer'image(frame_length) & " packet_length: " & integer'image(Packet_length) & "starting_delay: " & integer'image(frame_starting_delay) & " ending_delay: " & integer'image(frame_ending_delay); write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: "& integer'image(Packet_length)& " with id: "&integer'image(id_counter)); writeline(VEC_FILE, LINEVARIABLE); port_in <= Header_gen(Packet_length, source, destination_id, id_counter); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; for I in 0 to Packet_length-3 loop uniform(seed1, seed2, rand); wait until clk'event and clk ='0'; port_in <= Body_gen(Packet_length, integer(rand1000.0)); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; end loop; wait until clk'event and clk ='0'; uniform(seed1, seed2, rand); port_in <= Tail_gen(Packet_length, integer(rand1000.0)); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ; for l in 0 to frame_ending_delay-1 loop wait for 1 ns; end loop; port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ; if now > finish_time then wait; end if; end loop; end gen_bit_reversed_packet; procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic; signal CTS: out std_logic; signal DRTS: in std_logic; signal port_in: in std_logic_vector) is -- initial_delay: waits for this number of clock cycles before sending the packet! variable source_node, destination_node, P_length, packet_id, counter: integer; variable LINEVARIABLE : line; file VEC_FILE : text is out "received.txt"; begin while true loop counter := 0; CTS <= '0'; wait until DRTS'event and DRTS ='1'; wait until clk'event and clk ='1'; CTS <= '1'; wait until clk'event and clk ='1'; if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then counter := 1; P_length := to_integer(unsigned(port_in(28 downto 17))); destination_node := to_integer(unsigned(port_in(16 downto 13))); source_node := to_integer(unsigned(port_in(12 downto 9))); packet_id := to_integer(unsigned(port_in(8 downto 1))); end if; CTS <= '0'; while (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) /= "100") loop wait until DRTS'event and DRTS ='1'; wait until clk'event and clk ='1'; CTS <= '1'; wait until clk'event and clk ='1'; counter := counter+1; CTS <= '0'; end loop; report "Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) & " with length: "& integer'image(P_length) & " counter: "& integer'image(counter); assert (P_length=counter) report "wrong packet size" severity failure; assert (Node_ID=destination_node) report "wrong packet destination " severity failure; write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length)& " id: "& integer'image(packet_id)); writeline(VEC_FILE, LINEVARIABLE); end loop; end get_packet; procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer) is variable seed1 :positive := seed_1; variable seed2 :positive := seed_2; variable rand : real; variable stuck: integer; begin sta_0 <= '0'; sta_1 <= '0'; while true loop sta_0 <= '0'; sta_1 <= '0'; for I in 0 to delay loop wait for 1 ns; end loop; uniform(seed1, seed2, rand); address <= std_logic_vector(to_unsigned(integer(rand31.0), 5)); uniform(seed1, seed2, rand); stuck := integer(rand*11.0); if stuck > 5 then sta_0 <= '1'; sta_1 <= '0'; else sta_0 <= '0'; sta_1 <= '1'; end if; wait for 1 ns; end loop; end gen_fault; end TB_Package;
entity case13 is end entity; architecture test of case13 is function get_bits (n : natural; b : bit) return bit_vector is variable v : bit_vector(1 to n); begin v := (others => b); return v; end function; signal n : natural := 3; signal b : bit; begin p1: process (n, b) is begin case get_bits(n, b) is when "111" => report "ones"; when "000" => report "zeros"; when others => assert false; end case; end process; stim: process is begin b <= '1'; wait for 0 ns; n <= 5; wait for 1 ns; assert false report "should not reach here!"; wait; end process; end architecture;
-- NEED RESULT: ARCH00657: Multiple interface declarations in correct order passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00657 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 4.3.1 (2) -- -- DESIGN UNIT ORDERING: -- -- ENT00657(ARCH00657) -- ENT00657_Test_Bench(ARCH00657_Test_Bench) -- -- REVISION HISTORY: -- -- 27-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.all ; entity ENT00657 is generic ( cinteger1, cinteger2, cinteger3 : integer ; cbool1, cbool2, cbool3 : boolean ; cstring1, cstring2, cstring3 : string ) ; port ( sinteger1, sinteger2, sinteger3 : integer ; sbool1, sbool2, sbool3 : boolean ; sstring1, sstring2, sstring3 : string ) ; end ENT00657 ; -- architecture ARCH00657 of ENT00657 is procedure p1 ( constant cinteger1, cinteger2, cinteger3 : integer ; constant cbool1, cbool2, cbool3 : boolean ; constant cstring1, cstring2, cstring3 : string ; variable vinteger1, vinteger2, vinteger3 : inout integer ; variable vbool1, vbool2, vbool3 : inout boolean ; variable vstring1, vstring2, vstring3 : inout string ; signal sinteger1, sinteger2, sinteger3 : integer ; signal sbool1, sbool2, sbool3 : boolean ; signal sstring1, sstring2, sstring3 : string ; variable correct : out boolean ) is begin correct := cinteger1 = 1 and cinteger2 = 2 and cinteger3 = 3 and cbool1 = true and cbool2 = false and cbool3 = true and cstring1 = "aa" and cstring2 = "bb" and cstring3 = "cc" and vinteger1 = 1 and vinteger2 = 2 and vinteger3 = 3 and vbool1 = true and vbool2 = false and vbool3 = true and vstring1 = "aa" and vstring2 = "bb" and vstring3 = "cc" and sinteger1 = 1 and sinteger2 = 2 and sinteger3 = 3 and sbool1 = true and sbool2 = false and sbool3 = true and sstring1 = "aa" and sstring2 = "bb" and sstring3 = "cc" ; end p1 ; begin process subtype str is string ( 1 to 2 ) ; variable correct : boolean ; variable vinteger1 : integer := cinteger1 ; variable vinteger2 : integer := cinteger2 ; variable vinteger3 : integer := cinteger3 ; variable vbool1 : boolean := cbool1 ; variable vbool2 : boolean := cbool2 ; variable vbool3 : boolean := cbool3 ; variable vstring1 : str := cstring1 ; variable vstring2 : str := cstring2 ; variable vstring3 : str := cstring3 ; begin p1 ( cinteger1, cinteger2, cinteger3, cbool1, cbool2, cbool3, cstring1, cstring2, cstring3, vinteger1, vinteger2, vinteger3, vbool1, vbool2, vbool3, vstring1, vstring2, vstring3, sinteger1, sinteger2, sinteger3, sbool1, sbool2, sbool3, sstring1, sstring2, sstring3, correct ) ; test_report ( "ARCH00657" , "Multiple interface declarations in correct order" , correct ) ; wait ; end process ; end ARCH00657 ; -- entity ENT00657_Test_Bench is end ENT00657_Test_Bench ; architecture ARCH00657_Test_Bench of ENT00657_Test_Bench is subtype str is string ( 1 to 2 ) ; signal sinteger1 : integer := 1 ; signal sinteger2 : integer := 2 ; signal sinteger3 : integer := 3 ; signal sbool1 : boolean := true ; signal sbool2 : boolean := false ; signal sbool3 : boolean := true ; signal sstring1 : str := "aa" ; signal sstring2 : str := "bb" ; signal sstring3 : str := "cc" ; begin L1: block component UUT generic ( cinteger1, cinteger2, cinteger3 : integer ; cbool1, cbool2, cbool3 : boolean ; cstring1, cstring2, cstring3 : string ) ; port ( sinteger1, sinteger2, sinteger3 : integer ; sbool1, sbool2, sbool3 : boolean ; sstring1, sstring2, sstring3 : string ) ; end component ; for CIS1 : UUT use entity WORK.ENT00657 ( ARCH00657 ) ; begin CIS1 : UUT generic map ( 1, 2, 3, true, false, true, "aa", "bb", "cc" ) port map ( sinteger1, sinteger2, sinteger3, sbool1, sbool2, sbool3, sstring1, sstring2, sstring3 ) ; end block L1 ; end ARCH00657_Test_Bench ; --
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 16:04:21 05/02/2016 -- Design Name: -- Module Name: contatore_4_cifre - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity contatore_4_cifre is end contatore_4_cifre; architecture Behavioral of contatore_4_cifre is component Contatore_1_cifra is port(Clock, Enable_in, UpDown, Reset, Preset : in std_logic; N_preset : in std_logic_vector(3 downto 0); N : out std_logic_vector(3 downto 0); Enable_out : out std_logic); end Contatore_1_cifra; begin C0:Contatore_1_cifra PORT MAP(Clock=>clock_timer_globale, Enable_in => enable, UpDown => updown, Reset => reset, Preset => preset, N_preset => npreset, N => N0, Enable_out => enable_0_to_1); C1:Contatore_1_cifra PORT MAP(Clock=>clock_timer_globale, Enable_in => enable_0_to_1, UpDown => updown, Reset => reset, Preset => preset, N_preset => npreset, N => N1, Enable_out => enable_1_to_2); C2:Contatore_1_cifra PORT MAP(Clock=>clock_timer_globale, Enable_in => enable_1_to_2, UpDown => updown, Reset => reset, Preset => preset, N_preset => npreset, N => N2, Enable_out => enable_2_to_3); C3:Contatore_1_cifra PORT MAP(Clock=>clock_timer_globale, Enable_in => enable_2_to_3, UpDown => updown, Reset => reset, Preset => preset, N_preset => npreset, N => N3, Enable_out => open); --C1:contatore_1_cifra PORT MAP(clock_timer=>clock_timer_globale, -- enable_in => enable_0_to_1, N_OUT => N1, -- enable_out => enable_1_to_2); --C2:contatore_1_cifra PORT MAP(clock_timer=>clock_timer_globale, - -- enable_in => enable_1_to_2, N_OUT => N2, -- enable_out => enable_2_to_3); --C3:contatore_1_cifra PORT MAP(clock_timer=>clock_timer_globale, -- enable_in => enable_2_to_3, N_OUT => N3, -- enable_out => open); end Behavioral;
-- This file is part of easyFPGA. -- Copyright 2013-2015 os-cillation GmbH -- -- easyFPGA is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- easyFPGA is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- -- 8-bit PWM using two-process design pattern -- (pwm8.vhd) -- -- @author Simon Gansen ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------- -- Type and component definition package ------------------------------------------------------------------------------- package pwm8_comp is type pwm8_in_type is record duty_cycle : std_logic_vector(7 downto 0); end record; component pwm8 port ( clk : in std_logic; rst : in std_logic; d : in pwm8_in_type; pwm : out std_logic ); end component; end package; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.pwm8_comp.all; ------------------------------------------------------------------------------- ENTITY pwm8 is ------------------------------------------------------------------------------- port ( clk : in std_logic; rst : in std_logic; d : in pwm8_in_type; pwm : out std_logic ); end pwm8; ------------------------------------------------------------------------------- ARCHITECTURE two_proc of pwm8 is ------------------------------------------------------------------------------- type reg_type is record pwm_cnt : unsigned(7 downto 0); -- pwm counter end record; signal reg_out, reg_in : reg_type; begin ------------------------------------------------------------------------------- COMBINATIONAL : process(d, reg_out) ------------------------------------------------------------------------------- variable tmp_var : reg_type; begin tmp_var := reg_out; -- default assignments ---algorithm------------------------------------------------------------- -- PWM: reset on overflow, increment otherwise if (tmp_var.pwm_cnt = 2**8-1) then tmp_var.pwm_cnt := (others => '0'); else tmp_var.pwm_cnt := reg_out.pwm_cnt + 1; end if; -- compare and drive output if (tmp_var.pwm_cnt >= unsigned(d.duty_cycle)) then pwm <= '0'; else pwm <= '1'; end if; ------------------------------------------------------------------------- reg_in <= tmp_var; -- drive register inputs end process COMBINATIONAL; ------------------------------------------------------------------------------- REGISTERS : process(clk,rst) ------------------------------------------------------------------------------- begin if (rst = '1') then reg_out.pwm_cnt <= (others => '0'); elsif rising_edge(clk) then reg_out <= reg_in; end if; end process REGISTERS; end two_proc;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc838.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity c01s03b01x00p02n01i00838ent_a is end c01s03b01x00p02n01i00838ent_a; architecture c01s03b01x00p02n01i00838arch_a of c01s03b01x00p02n01i00838ent_a is begin AC_BLK : block signal B : BIT; begin B <= '1'; end block; end; ENTITY c01s03b01x00p02n01i00838ent IS END c01s03b01x00p02n01i00838ent; ARCHITECTURE c01s03b01x00p02n01i00838arch OF c01s03b01x00p02n01i00838ent IS BEGIN A_BLK : block component C end component; begin L1 : C; L2 : C; L3 : C; end block; TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c01s03b01x00p02n01i00838 - Missing semicolon." severity ERROR; wait; END PROCESS TESTING; END c01s03b01x00p02n01i00838arch; configuration c01s03b01x00p02n01i00838cfg of c01s03b01x00p02n01i00838ent is for c01s03b01x00p02n01i00838arch for A_BLK for L1 : C use entity work.c01s03b01x00p02n01i00838ent_a (c01s03b01x00p02n01i00838arch_a) ; end for; for L2 : C use entity work.c01s03b01x00p02n01i00838ent_a (c01s03b01x00p02n01i00838arch_a) ; end for; for L3 : C use entity work.c01s03b01x00p02n01i00838ent_a (c01s03b01x00p02n01i00838arch_a) ; end for --- Failure_here end for; end for; end c01s03b01x00p02n01i00838cfg;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc838.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity c01s03b01x00p02n01i00838ent_a is end c01s03b01x00p02n01i00838ent_a; architecture c01s03b01x00p02n01i00838arch_a of c01s03b01x00p02n01i00838ent_a is begin AC_BLK : block signal B : BIT; begin B <= '1'; end block; end; ENTITY c01s03b01x00p02n01i00838ent IS END c01s03b01x00p02n01i00838ent; ARCHITECTURE c01s03b01x00p02n01i00838arch OF c01s03b01x00p02n01i00838ent IS BEGIN A_BLK : block component C end component; begin L1 : C; L2 : C; L3 : C; end block; TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c01s03b01x00p02n01i00838 - Missing semicolon." severity ERROR; wait; END PROCESS TESTING; END c01s03b01x00p02n01i00838arch; configuration c01s03b01x00p02n01i00838cfg of c01s03b01x00p02n01i00838ent is for c01s03b01x00p02n01i00838arch for A_BLK for L1 : C use entity work.c01s03b01x00p02n01i00838ent_a (c01s03b01x00p02n01i00838arch_a) ; end for; for L2 : C use entity work.c01s03b01x00p02n01i00838ent_a (c01s03b01x00p02n01i00838arch_a) ; end for; for L3 : C use entity work.c01s03b01x00p02n01i00838ent_a (c01s03b01x00p02n01i00838arch_a) ; end for --- Failure_here end for; end for; end c01s03b01x00p02n01i00838cfg;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc838.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity c01s03b01x00p02n01i00838ent_a is end c01s03b01x00p02n01i00838ent_a; architecture c01s03b01x00p02n01i00838arch_a of c01s03b01x00p02n01i00838ent_a is begin AC_BLK : block signal B : BIT; begin B <= '1'; end block; end; ENTITY c01s03b01x00p02n01i00838ent IS END c01s03b01x00p02n01i00838ent; ARCHITECTURE c01s03b01x00p02n01i00838arch OF c01s03b01x00p02n01i00838ent IS BEGIN A_BLK : block component C end component; begin L1 : C; L2 : C; L3 : C; end block; TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c01s03b01x00p02n01i00838 - Missing semicolon." severity ERROR; wait; END PROCESS TESTING; END c01s03b01x00p02n01i00838arch; configuration c01s03b01x00p02n01i00838cfg of c01s03b01x00p02n01i00838ent is for c01s03b01x00p02n01i00838arch for A_BLK for L1 : C use entity work.c01s03b01x00p02n01i00838ent_a (c01s03b01x00p02n01i00838arch_a) ; end for; for L2 : C use entity work.c01s03b01x00p02n01i00838ent_a (c01s03b01x00p02n01i00838arch_a) ; end for; for L3 : C use entity work.c01s03b01x00p02n01i00838ent_a (c01s03b01x00p02n01i00838arch_a) ; end for --- Failure_here end for; end for; end c01s03b01x00p02n01i00838cfg;
entity func21 is end entity; architecture test of func21 is type rec is record x, y : integer; end record; function func (r : rec) return integer is begin return r.x + r.y; end function; begin p1: process is variable a, b : integer; begin assert func(r.x => 1, r.y => 2) = 3; a := 4; b := 5; wait for 1 ns; assert func(r.x => a, r.y => b) = 9; wait; end process; end architecture;
-- Test case from Brian Padalino -- library ieee ; use ieee.std_logic_1164.all ; package pack is type iface_t is record cs : std_logic ; addr : std_logic_vector ; rdata : std_logic_vector ; wdata : std_logic_vector ; end record ; function init_iface_signals(addr_width : natural ; data_width : natural) return iface_t; end package ; package body pack is function init_iface_signals(addr_width : natural ; data_width : natural) return iface_t is variable rv : iface_t(addr(addr_width-1 downto 0), wdata(data_width-1 downto 0), rdata(data_width-1 downto 0)) ; begin rv.cs := '0' ; rv.addr := (rv.addr'range => '0') ; rv.wdata := (rv.wdata'range => '0') ; rv.rdata := (rv.rdata'range => '0') ; return rv ; end function ; end package body ; library ieee ; use ieee.std_logic_1164.all ; use work.pack.all ; entity master is port ( clock : in std_logic ; iface : inout iface_t := init_iface_signals(16, 32) ) ; end entity ; architecture arch of master is begin end architecture ; library ieee ; use ieee.std_logic_1164.all ; use work.pack.all ; entity signal23 is end entity ; architecture arch of signal23 is signal clock : std_logic := '0' ; signal iface : iface_t(addr(15 downto 0), rdata(31 downto 0), wdata(31 downto 0)) ; begin clock <= not clock after 1 ns ; U_master : entity work.master port map ( clock => clock, iface => iface ) ; tb : process begin report LF & "if:" & LF & " cs: " & std_logic'image(iface.cs) & LF & " addr: " & to_hstring(iface.addr) & LF & " rdata: " & to_hstring(iface.rdata) & LF & " wdata: " & to_hstring(iface.wdata) ; std.env.stop ; end process ; end architecture ;
entity ent is port ( i : in bit ); end ent; architecture a of ent is begin end;
-- -a --ieee=synopsis -fexplicit -Wc,-m32 -Wa,--32 -- -e -Wa,--32 -Wl,-m32 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity dmem is port (a: in std_logic_vector(31 downto 0); wd: in std_logic_vector(31 downto 0); clk, we: in bit; rd: out std_logic_vector(31 downto 0)); end entity; architecture arq_dmem of dmem is type mem is array (0 to 63) of std_logic_vector(31 downto 0); begin process(clk) variable my_mem: mem; variable address: std_logic_vector(5 downto 0); variable pos_a: integer; begin for pos in 0 to 63 loop --Inicializo mi memoria my_mem(pos) := std_logic_vector(to_unsigned(pos, 32)); end loop; if clk'EVENT and clk='1' then address := a(7 downto 2); pos_a := to_integer(unsigned(address)); if we='1' then my_mem(pos_a) := wd; rd <= wd; else rd <= my_mem(pos_a); end if; end if; end process; end architecture;
---- -- This file is part of etip-ss11-g07. -- -- Copyright (C) 2011 Lukas Märdian <lukasmaerdian@gmail.com> -- Copyright (C) 2011 M. S. -- Copyright (C) 2011 Orest Tarasiuk <orest.tarasiuk@tum.de> -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. ---- LIBRARY ieee; USE ieee.numeric_std.all; USE ieee.std_logic_1164.all; -- USE ieee.std_logic_unsigned.all; ENTITY BINBCD IS PORT( clk : IN std_logic; bin_input : IN std_logic_vector (16 DOWNTO 0); einer, zehner, hunderter, tausender, zehntausender : OUT std_logic_vector (3 DOWNTO 0); overflow : OUT std_logic ); END BINBCD; ARCHITECTURE DoubleDabbleV3 OF BINBCD IS SIGNAL overflw : std_logic := '1'; BEGIN PROCESS(clk) VARIABLE int_input : integer := 0; BEGIN IF (rising_edge(clk)) THEN int_input := to_integer(unsigned(bin_input)); IF (int_input <= 99999) THEN overflow <= '0'; overflw <= '0'; ELSE overflow <= '1'; overflw <= '1'; einer <= "0000"; zehner <= "0000"; hunderter <= "0000"; tausender <= "0000"; zehntausender <= "0000"; END IF; END IF; END PROCESS; PROCESS(clk) VARIABLE vector: std_logic_vector(36 DOWNTO 0) := "00000000000000000000" & bin_input; BEGIN IF (rising_edge(clk)) AND (overflw = '0') THEN FOR i IN 0 TO 17 LOOP -- Prüfen, ob größergleich 5; falls ja, dann 3 addieren für: -- Zehntausender IF (vector(35 DOWNTO 33) = "101") OR (vector(35 DOWNTO 33) = "110") OR (vector(35 DOWNTO 33) = "111") OR (vector(36) = '1') THEN vector(36 DOWNTO 33) := std_logic_vector(unsigned(vector(36 DOWNTO 33)) + "0011"); END IF; -- Tausender IF (vector(31 DOWNTO 29) = "101") OR (vector(31 DOWNTO 29) = "110") OR (vector(31 DOWNTO 29) = "111") OR (vector(32) = '1') THEN vector(32 DOWNTO 29) := std_logic_vector(unsigned(vector(32 DOWNTO 29)) + "0011"); END IF; -- Hunderter IF (vector(27 DOWNTO 25) = "101") OR (vector(27 DOWNTO 25) = "110") OR (vector(27 DOWNTO 25) = "111") OR (vector(28) = '1') THEN vector(28 DOWNTO 25) := std_logic_vector(unsigned(vector(28 DOWNTO 25)) + "0011"); END IF; -- Zehner IF (vector(23 DOWNTO 21) = "101") OR (vector(23 DOWNTO 21) = "110") OR (vector(23 DOWNTO 21) = "111") OR (vector(24) = '1') THEN vector(24 DOWNTO 21) := std_logic_vector(unsigned(vector(24 DOWNTO 21)) + "0011"); END IF; -- Einer IF (vector(19 DOWNTO 17) = "101") OR (vector(19 DOWNTO 17) = "110") OR (vector(19 DOWNTO 17) = "111") OR (vector(20) = '1') THEN vector(20 DOWNTO 17) := std_logic_vector(unsigned(vector(20 DOWNTO 17)) + "0011"); END IF; -- Shiften: vector := vector(35 DOWNTO 0) & '0'; END LOOP; -- Ergebnisse in die jeweiligen Stellen schreiben zehntausender <= vector(36 DOWNTO 33); tausender <= vector(32 DOWNTO 29); hunderter <= vector(28 DOWNTO 25); zehner <= vector(24 DOWNTO 21); einer <= vector(20 DOWNTO 17); END IF; END PROCESS; END DoubleDabbleV3;
use std.textio.all; package broken_module is type prot_t is protected procedure proc; end protected; end package; package body broken_module is type prot_t is protected body variable var : natural := 0; procedure file_proc is file fwrite : text; begin file_open(fwrite, "out", WRITE_MODE); file_close(fwrite); end procedure; procedure proc is begin file_proc; var := 0; -- Comment out this and it will not fail end procedure; end protected body; end package body; ------------------------------------------------------------------------------- entity issue91 is end entity; use work.broken_module.all; architecture test of issue91 is shared variable p : prot_t; begin process is begin p.proc; wait; end process; end architecture;
use std.textio.all; package broken_module is type prot_t is protected procedure proc; end protected; end package; package body broken_module is type prot_t is protected body variable var : natural := 0; procedure file_proc is file fwrite : text; begin file_open(fwrite, "out", WRITE_MODE); file_close(fwrite); end procedure; procedure proc is begin file_proc; var := 0; -- Comment out this and it will not fail end procedure; end protected body; end package body; ------------------------------------------------------------------------------- entity issue91 is end entity; use work.broken_module.all; architecture test of issue91 is shared variable p : prot_t; begin process is begin p.proc; wait; end process; end architecture;
use std.textio.all; package broken_module is type prot_t is protected procedure proc; end protected; end package; package body broken_module is type prot_t is protected body variable var : natural := 0; procedure file_proc is file fwrite : text; begin file_open(fwrite, "out", WRITE_MODE); file_close(fwrite); end procedure; procedure proc is begin file_proc; var := 0; -- Comment out this and it will not fail end procedure; end protected body; end package body; ------------------------------------------------------------------------------- entity issue91 is end entity; use work.broken_module.all; architecture test of issue91 is shared variable p : prot_t; begin process is begin p.proc; wait; end process; end architecture;
use std.textio.all; package broken_module is type prot_t is protected procedure proc; end protected; end package; package body broken_module is type prot_t is protected body variable var : natural := 0; procedure file_proc is file fwrite : text; begin file_open(fwrite, "out", WRITE_MODE); file_close(fwrite); end procedure; procedure proc is begin file_proc; var := 0; -- Comment out this and it will not fail end procedure; end protected body; end package body; ------------------------------------------------------------------------------- entity issue91 is end entity; use work.broken_module.all; architecture test of issue91 is shared variable p : prot_t; begin process is begin p.proc; wait; end process; end architecture;
architecture RTL of FIFO is signal sig1 : std_logic_vector(31 downto 0); signal sig2 : std_logic_vector( 3 downto 0); signal sig3 : std_logic_vector(c_width downto 0); -- Violations signal sig1 : std_logic_vector( 31 downto 0); signal sig2 : std_logic_vector(3 downto 0); signal sig3 : std_logic_vector(c_width downto 0); begin end architecture RTL;
Library ieee; Use ieee.std_logic_1164.all; Entity nreg is Generic ( n : integer := 16); port( Clk,Rst,enable : in std_logic; d : in std_logic_vector(n-1 downto 0); q : out std_logic_vector(n-1 downto 0)); end nreg; Architecture arch_nreg of nreg is begin Process (Clk,Rst) begin if Rst = '1' then q <= (others=>'0'); elsif clk'event and clk = '1' then if (enable = '1') then q <= d; end if; end if; end process; end arch_nreg;
-- -- WISHBONE revB2 compiant I2C master core -- -- author: Richard Herveille -- rev. 0.1 based on simple_i2c -- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman) -- rev. 0.3 may 4th 2001, fixed typo rev.0.2 txt -> txr -- rev. 0.4 may 8th, added some remarks, fixed some sensitivity list issues -- -- -- Changes compared to simple_i2c -- 1) WISHBONE interface -- 2) added start/stop detection -- 3) added busy bit -- 4) removed automatic tri-state buffer insertion (for ASIC support) -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity wishbone_i2c_master is port ( -- wishbone signals CLK_I : in std_logic; -- master clock input RST_I : in std_logic := '0'; -- synchronous active high reset nRESET: in std_logic := '1'; -- asynchronous active low reset ADR_I : in std_logic_vector(1 downto 0); -- lower address bits DAT_I : in std_logic_vector(15 downto 0); -- Databus input DAT_O : out std_logic_vector(15 downto 0); -- Databus output SEL_I : in std_logic_vector(1 downto 0); -- Byte select signals WE_I : in std_logic; -- Write enable input STB_I : in std_logic; -- Strobe signals / core select signal CYC_I : in std_logic; -- Valid bus cycle input ACK_O : out std_logic; -- Bus cycle acknowledge output INTA_O : out std_logic; -- interrupt request output signal -- I2C signals SCLi : in std_logic; -- I2C clock line SCLo : out std_logic; SDAi : in std_logic; -- I2C data line SDAo : out std_logic ); end entity wishbone_i2c_master; architecture structural of wishbone_i2c_master is component byte_ctrl is port ( clk : in std_logic; rst : in std_logic; -- synchronous active high reset (WISHBONE compatible) nReset : in std_logic; -- asynchornous active low reset (FPGA compatible) clk_cnt : in unsigned(15 downto 0); -- 4x SCL -- input signals ena, start, stop, read, write, ack_in : std_logic; Din : in std_logic_vector(7 downto 0); -- output signals cmd_ack : out std_logic; ack_out : out std_logic; Dout : out std_logic_vector(7 downto 0); i2c_busy : out std_logic; -- i2c signals SCLi : in std_logic; -- I2C clock line SCLo : out std_logic; SDAi : in std_logic; -- I2C data line SDAo : out std_logic ); end component byte_ctrl; -- registers signal prer : unsigned(15 downto 0); -- clock prescale register signal ctr : std_logic_vector(7 downto 0); -- control register signal txr : std_logic_vector(7 downto 0); -- transmit register signal rxr : std_logic_vector(7 downto 0); -- receive register signal cr : std_logic_vector(7 downto 0); -- command register signal sr : std_logic_vector(7 downto 0); -- status register -- done signal: command completed, clear command register signal done : std_logic; -- command register signals signal sta, sto, rd, wr, ack, iack : std_logic; -- core enable signal signal core_en : std_logic; -- status register signals signal irxack, rxack : std_logic; -- received aknowledge from slave signal tip : std_logic; -- transfer in progress signal irq_flag : std_logic; -- interrupt pending flag signal i2c_busy : std_logic; -- bus busy (start signal detected) begin -- generate acknowledge output signal ACK_O <= STB_I; -- since timing is always honored -- assign DAT_O assign_dato : process(ADR_I, prer, ctr, txr, cr, rxr, sr) begin case ADR_I is when "00" => DAT_O <= std_logic_vector(prer); when "01" => DAT_O <= (x"00" & ctr); when "10" => DAT_O <= (txr & cr); when "11" => DAT_O <= (rxr & sr); when others => DAT_O <= (others => 'X'); -- for simulation only end case; end process assign_dato; -- registers block regs_block: block -- address decode signals signal we_a0, we_a1, we_a2, we_a3 : std_logic; begin -- decode address lines we_a0 <= CYC_I and STB_I and WE_I and not ADR_I(1) and not ADR_I(0); -- 00 we_a1 <= CYC_I and STB_I and WE_I and not ADR_I(1) and ADR_I(0); -- 01 we_a2 <= CYC_I and STB_I and WE_I and ADR_I(1) and not ADR_I(0); -- 10 we_a3 <= CYC_I and STB_I and WE_I and ADR_I(1) and ADR_I(0); -- 11 -- store data in writeable registers -- prescale register write_prer: process(nRESET, CLK_I) begin if (nRESET = '0') then prer <= (others => '1'); elsif (CLK_I'event and CLK_I = '1') then if (RST_I = '1') then prer <= (others => '1'); else if ( (we_a0 and SEL_I(1)) = '1') then prer(15 downto 8) <= unsigned(DAT_I(15 downto 8)); end if; if ( (we_a0 and SEL_I(0)) = '1') then prer(7 downto 0) <= unsigned(DAT_I(7 downto 0)); end if; end if; end if; end process write_prer; -- control register write_ctr: process(nRESET, CLK_I) begin if (nRESET = '0') then ctr <= (others => '0'); elsif (CLK_I'event and CLK_I = '1') then if (RST_I = '1') then ctr <= (others => '0'); else if ( (we_a1 and SEL_I(0)) = '1') then ctr <= DAT_I(7 downto 0); end if; end if; end if; end process write_ctr; -- transmit register write_txr: process(nRESET, CLK_I) begin if (nRESET = '0') then txr <= (others => '0'); elsif (CLK_I'event and CLK_I = '1') then if (RST_I = '1') then txr <= (others => '0'); else if ( (we_a2 and SEL_I(1)) = '1') then txr <= DAT_I(15 downto 8); end if; end if; end if; end process write_txr; -- command register write_cr: process(nRESET, CLK_I) begin if (nRESET = '0') then cr <= (others => '0'); -- asynchronous clear elsif (CLK_I'event and CLK_I = '1') then if (RST_I = '1') then cr <= (others => '0'); -- synchronous clear else if ( (we_a2 and SEL_I(0)) = '1') then if (core_en = '1') then cr <= DAT_I(7 downto 0); -- only take new commands when I2C core is enabled, pending commands are finished end if; else if (done = '0') then cr(7 downto 4) <= cr(7 downto 4); else cr(7 downto 0) <= (others => '0'); -- clear command_bits when command completed end if; cr(2 downto 1) <= cr(2 downto 1); cr(0) <= cr(0) and irq_flag; -- automatically clear when irq_flag is cleared end if; end if; end if; end process write_cr; end block regs_block; -- decode command register sta <= cr(7); sto <= cr(6); rd <= cr(5); wr <= cr(4); ack <= cr(3); iack <= cr(0); -- decode control register core_en <= ctr(7); -- hookup byte controller block u1: byte_ctrl port map (clk => CLK_I, rst => RST_I, nReset => nRESET, clk_cnt => prer, ena => core_en, start => sta, stop => sto, read => rd, write => wr, ack_in => ack, i2c_busy => i2c_busy, Din => txr, cmd_ack => done, ack_out => irxack, Dout => rxr, -- note: maybe store rxr in registers ?? SCLi => SCLi, SCLo => SCLo, SDAi => SDAi, SDAo => SDAo); -- status register block + interrupt request signal st_block : block begin -- generate status register bits gen_sr_bits: process (CLK_I, nRESET) begin if (nRESET = '0') then rxack <= '0'; tip <= '0'; irq_flag <= '0'; elsif (CLK_I'event and CLK_I = '1') then if (RST_I = '1') then rxack <= '0'; tip <= '0'; irq_flag <= '0'; else rxack <= irxack; tip <= ( rd or wr ); irq_flag <= (done or irq_flag) and not iack; -- interrupt request flag is always generated end if; end if; end process gen_sr_bits; -- generate interrupt request signals gen_irq: process (CLK_I, nRESET) begin if (nRESET = '0') then INTA_O <= '0'; elsif (CLK_I'event and CLK_I = '1') then if (RST_I = '1') then INTA_O <= '0'; else INTA_O <= irq_flag and ctr(6); -- interrupt signal is only generated when IEN (interrupt enable bit) is set end if; end if; end process gen_irq; -- assign status register bits sr(7) <= rxack; sr(6) <= i2c_busy; sr(5 downto 2) <= (others => '0'); -- reserved sr(1) <= tip; sr(0) <= irq_flag; end block; end architecture structural; -- ------------------------------------------ -- Byte controller section ------------------------------------------ -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity byte_ctrl is port ( clk : in std_logic; rst : in std_logic; -- synchronous active high reset (WISHBONE compatible) nReset : in std_logic; -- asynchornous active low reset (FPGA compatible) clk_cnt : in unsigned(15 downto 0); -- 4x SCL -- input signals ena, start, stop, read, write, ack_in : std_logic; Din : in std_logic_vector(7 downto 0); -- output signals cmd_ack : out std_logic; ack_out : out std_logic; Dout : out std_logic_vector(7 downto 0); i2c_busy : out std_logic; -- i2c signals SCLi : in std_logic; -- I2C clock line SCLo : out std_logic; SDAi : in std_logic; -- I2C data line SDAo : out std_logic ); end entity byte_ctrl; architecture structural of byte_ctrl is component bit_ctrl is port ( clk : in std_logic; rst : in std_logic; nReset : in std_logic; clk_cnt : in unsigned(15 downto 0); -- clock prescale value ena : in std_logic; -- core enable signal cmd : in std_logic_vector(2 downto 0); cmd_ack : out std_logic; busy : out std_logic; Din : in std_logic; Dout : out std_logic; SCLin : in std_logic; -- I2C clock line SCLout : out std_logic; SDAin : in std_logic; -- I2C data line SDAout : out std_logic ); end component bit_ctrl; -- commands for i2c_core constant CMD_NOP : std_logic_vector(2 downto 0) := "000"; constant CMD_START : std_logic_vector(2 downto 0) := "010"; constant CMD_STOP : std_logic_vector(2 downto 0) := "011"; constant CMD_READ : std_logic_vector(2 downto 0) := "100"; constant CMD_WRITE : std_logic_vector(2 downto 0) := "101"; -- signals for bit_controller signal core_cmd : std_logic_vector(2 downto 0); signal core_ack, core_txd, core_rxd : std_logic; -- signals for shift register signal sr : std_logic_vector(7 downto 0); -- 8bit shift register signal shift, ld : std_logic; -- signals for state machine signal go, host_ack : std_logic; begin -- hookup bit_controller u1: bit_ctrl port map (clk, rst, nReset, clk_cnt, ena, core_cmd, core_ack, i2c_busy, core_txd, core_rxd, SCLi, SCLo, SDAi, SDAo); -- generate host-command-acknowledge cmd_ack <= host_ack; -- generate go-signal go <= (read or write) and not host_ack; -- assign Dout output to shift-register Dout <= sr; -- assign ack_out output to core_rxd (contains last received bit) ack_out <= core_rxd; -- generate shift register shift_register: process(clk) begin if (clk'event and clk = '1') then if (ld = '1') then sr <= din; elsif (shift = '1') then sr <= (sr(6 downto 0) & core_rxd); end if; end if; end process shift_register; -- -- state machine -- statemachine : block type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop); signal state : states; signal dcnt : unsigned(2 downto 0); begin -- -- command interpreter, translate complex commands into simpler I2C commands -- nxt_state_decoder: process(clk, nReset, state) variable nxt_state : states; variable idcnt : unsigned(2 downto 0); variable ihost_ack : std_logic; variable icore_cmd : std_logic_vector(2 downto 0); variable icore_txd : std_logic; variable ishift, iload : std_logic; begin -- 8 databits (1byte) of data to shift-in/out idcnt := dcnt; -- no acknowledge (until command complete) ihost_ack := '0'; icore_txd := core_txd; -- keep current command to bit_controller icore_cmd := core_cmd; -- no shifting or loading of shift-register ishift := '0'; iload := '0'; -- keep current state; nxt_state := state; case state is when st_idle => if (go = '1') then if (start = '1') then nxt_state := st_start; icore_cmd := CMD_START; elsif (read = '1') then nxt_state := st_read; icore_cmd := CMD_READ; idcnt := "111"; else nxt_state := st_write; icore_cmd := CMD_WRITE; idcnt := "111"; iload := '1'; end if; end if; when st_start => if (core_ack = '1') then if (read = '1') then nxt_state := st_read; icore_cmd := CMD_READ; idcnt := "111"; else nxt_state := st_write; icore_cmd := CMD_WRITE; idcnt := "111"; iload := '1'; end if; end if; when st_write => if (core_ack = '1') then idcnt := dcnt -1; -- count down Data_counter icore_txd := sr(7); if (dcnt = 0) then nxt_state := st_ack; icore_cmd := CMD_READ; else ishift := '1'; -- icore_txd := sr(7); end if; end if; when st_read => if (core_ack = '1') then idcnt := dcnt -1; -- count down Data_counter ishift := '1'; if (dcnt = 0) then nxt_state := st_ack; icore_cmd := CMD_WRITE; icore_txd := ack_in; end if; end if; when st_ack => if (core_ack = '1') then -- generate command acknowledge signal ihost_ack := '1'; -- Perform an additional shift, needed for 'read' (store last received bit in shift register) ishift := '1'; -- check for stop; Should a STOP command be generated ? if (stop = '1') then nxt_state := st_stop; icore_cmd := CMD_STOP; else nxt_state := st_idle; icore_cmd := CMD_NOP; end if; end if; when st_stop => if (core_ack = '1') then nxt_state := st_idle; icore_cmd := CMD_NOP; end if; when others => -- illegal states nxt_state := st_idle; icore_cmd := CMD_NOP; end case; -- generate registers if (nReset = '0') then core_cmd <= CMD_NOP; core_txd <= '0'; shift <= '0'; ld <= '0'; dcnt <= "111"; host_ack <= '0'; state <= st_idle; elsif (clk'event and clk = '1') then if (rst = '1') then core_cmd <= CMD_NOP; core_txd <= '0'; shift <= '0'; ld <= '0'; dcnt <= "111"; host_ack <= '0'; state <= st_idle; else state <= nxt_state; dcnt <= idcnt; shift <= ishift; ld <= iload; core_cmd <= icore_cmd; core_txd <= icore_txd; host_ack <= ihost_ack; end if; end if; end process nxt_state_decoder; end block statemachine; end architecture structural; -- ------------------------------------- -- Bit controller section ------------------------------------ -- -- Translate simple commands into SCL/SDA transitions -- Each command has 5 states, A/B/C/D/idle -- -- start: SCL ~~~~~~~~~~\____ -- SDA ~~~~~~~~\______ -- x \| A \| B \| C \| D \| i -- -- repstart SCL ____/~~~~\___ -- SDA __/~~~\______ -- x \| A \| B \| C \| D \| i -- -- stop SCL ____/~~~~~~~~ -- SDA ==\____/~~~~~ -- x \| A \| B \| C \| D \| i -- --- write SCL ____/~~~~\____ -- SDA ==X=========X= -- x \| A \| B \| C \| D \| i -- --- read SCL ____/~~~~\____ -- SDA XXXX=====XXXX -- x \| A \| B \| C \| D \| i -- -- Timing: Normal mode Fast mode ----------------------------------------------------------------- -- Fscl 100KHz 400KHz -- Th_scl 4.0us 0.6us High period of SCL -- Tl_scl 4.7us 1.3us Low period of SCL -- Tsu:sta 4.7us 0.6us setup time for a repeated start condition -- Tsu:sto 4.0us 0.6us setup time for a stop conditon -- Tbuf 4.7us 1.3us Bus free time between a stop and start condition -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity bit_ctrl is port ( clk : in std_logic; rst : in std_logic; nReset : in std_logic; clk_cnt : in unsigned(15 downto 0); -- clock prescale value ena : in std_logic; -- core enable signal cmd : in std_logic_vector(2 downto 0); cmd_ack : out std_logic; busy : out std_logic; Din : in std_logic; Dout : out std_logic; -- i2c lines SCLin : in std_logic; -- I2C clock line SCLout : out std_logic; SDAin : in std_logic; -- I2C data line SDAout : out std_logic ); end entity bit_ctrl; architecture structural of bit_ctrl is constant CMD_NOP : std_logic_vector(2 downto 0) := "000"; constant CMD_START : std_logic_vector(2 downto 0) := "010"; constant CMD_STOP : std_logic_vector(2 downto 0) := "011"; constant CMD_READ : std_logic_vector(2 downto 0) := "100"; constant CMD_WRITE : std_logic_vector(2 downto 0) := "101"; type cmds is (idle, start_a, start_b, start_c, start_d, stop_a, stop_b, stop_c, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d); signal state : cmds; signal SCLo, SDAo : std_logic; -- internal I2C lines signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs signal txd : std_logic; -- transmit bit signal clk_en, slave_wait :std_logic; -- clock generation signals -- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation) signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis) begin -- synchronize SCL and SDA inputs synch_SCL_SDA: process(clk) begin if (clk'event and clk = '1') then sSCL <= SCLin; sSDA <= SDAin; end if; end process synch_SCL_SDA; -- whenever the slave is not ready it can delay the cycle by pulling SCL low slave_wait <= '1' when ( (SCLo = '1') and (sSCL = '0') ) else '0'; -- generate clk enable signal gen_clken: process(clk, nReset) begin if (nReset = '0') then cnt <= (others => '0'); clk_en <= '1'; elsif (clk'event and clk = '1') then if (rst = '1') then cnt <= (others => '0'); clk_en <= '1'; else if ( (cnt = 0) or (ena = '0') ) then clk_en <= '1'; cnt <= clk_cnt; else if (slave_wait = '0') then cnt <= cnt -1; end if; clk_en <= '0'; end if; end if; end if; end process gen_clken; -- generate bus status controller bus_status_ctrl: block signal dSDA : std_logic; signal sta_condition : std_logic; signal sto_condition : std_logic; signal ibusy : std_logic; begin -- detect start condition => detect falling edge on SDA while SCL is high -- detect stop condition => detect rising edge on SDA while SCL is high det_sta_sto: process(clk) begin if (clk'event and clk = '1') then dSDA <= sSDA; -- generate a delayed version of sSDA sta_condition <= (not sSDA and dSDA) and sSCL; sto_condition <= (sSDA and not dSDA) and sSCL; end if; end process det_sta_sto; -- generate bus busy signal gen_busy: process(clk, nReset) begin if (nReset = '0') then ibusy <= '0'; elsif (clk'event and clk = '1') then if (rst = '1') then ibusy <= '0'; else ibusy <= (sta_condition or ibusy) and not sto_condition; end if; end if; end process gen_busy; -- assign output busy <= ibusy; end block bus_status_ctrl; -- generate statemachine nxt_state_decoder : process (clk, nReset, state, cmd) variable nxt_state : cmds; variable icmd_ack, store_sda : std_logic; variable itxd : std_logic; begin nxt_state := state; icmd_ack := '0'; -- default no acknowledge store_sda := '0'; itxd := txd; case (state) is -- idle when idle => case cmd is when CMD_START => nxt_state := start_a; icmd_ack := '1'; -- command completed when CMD_STOP => nxt_state := stop_a; icmd_ack := '1'; -- command completed when CMD_WRITE => nxt_state := wr_a; icmd_ack := '1'; -- command completed itxd := Din; when CMD_READ => nxt_state := rd_a; icmd_ack := '1'; -- command completed when others => nxt_state := idle; -- don't acknowledge NOP command icmd_ack := '1'; -- command completed end case; -- start when start_a => nxt_state := start_b; when start_b => nxt_state := start_c; when start_c => nxt_state := start_d; when start_d => nxt_state := idle; -- stop when stop_a => nxt_state := stop_b; when stop_b => nxt_state := stop_c; when stop_c => nxt_state := idle; -- read when rd_a => nxt_state := rd_b; when rd_b => nxt_state := rd_c; when rd_c => nxt_state := rd_d; store_sda := '1'; when rd_d => nxt_state := idle; -- write when wr_a => nxt_state := wr_b; when wr_b => nxt_state := wr_c; when wr_c => nxt_state := wr_d; when wr_d => nxt_state := idle; end case; -- generate regs if (nReset = '0') then state <= idle; cmd_ack <= '0'; txd <= '0'; Dout <= '0'; elsif (clk'event and clk = '1') then if (rst = '1') then state <= idle; cmd_ack <= '0'; txd <= '0'; Dout <= '0'; else if (clk_en = '1') then state <= nxt_state; txd <= itxd; if (store_sda = '1') then Dout <= sSDA; end if; end if; cmd_ack <= icmd_ack and clk_en; end if; end if; end process nxt_state_decoder; -- -- convert states to SCL and SDA signals -- output_decoder: process (clk, nReset, state) variable iscl, isda : std_logic; begin case (state) is when idle => iscl := SCLo; -- keep SCL in same state isda := sSDA; -- keep SDA in same state -- start when start_a => iscl := SCLo; -- keep SCL in same state (for repeated start) isda := '1'; -- set SDA high when start_b => iscl := '1'; -- set SCL high isda := '1'; -- keep SDA high when start_c => iscl := '1'; -- keep SCL high isda := '0'; -- sel SDA low when start_d => iscl := '0'; -- set SCL low isda := '0'; -- keep SDA low -- stop when stop_a => iscl := '0'; -- keep SCL disabled isda := '0'; -- set SDA low when stop_b => iscl := '1'; -- set SCL high isda := '0'; -- keep SDA low when stop_c => iscl := '1'; -- keep SCL high isda := '1'; -- set SDA high -- write when wr_a => iscl := '0'; -- keep SCL low isda := Din; when wr_b => iscl := '1'; -- set SCL high isda := Din; when wr_c => iscl := '1'; -- keep SCL high isda := Din; when wr_d => iscl := '0'; -- set SCL low isda := Din; -- read when rd_a => iscl := '0'; -- keep SCL low isda := '1'; -- tri-state SDA when rd_b => iscl := '1'; -- set SCL high isda := '1'; -- tri-state SDA when rd_c => iscl := '1'; -- keep SCL high isda := '1'; -- tri-state SDA when rd_d => iscl := '0'; -- set SCL low isda := '1'; -- tri-state SDA end case; -- generate registers if (nReset = '0') then SCLo <= '1'; SDAo <= '1'; elsif (clk'event and clk = '1') then if (rst = '1') then SCLo <= '1'; SDAo <= '1'; else if (clk_en = '1') then SCLo <= iscl; SDAo <= isda; end if; end if; end if; end process output_decoder; -- assign outputs SCLout <= SCLo; SDAout <= SDAo; end architecture structural;

------------------------------------------------------- --! @author Andrew Powell --! @date March 16, 2017 --! @brief Contains the entity and architecture of the --! Wrapper Plasma-SoC Top Module. ------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.plasoc_cpu_pack.plasoc_cpu; use work.plasoc_int_pack.plasoc_int; use work.plasoc_int_pack.default_interrupt_total; use work.plasoc_timer_pack.plasoc_timer; use work.plasoc_gpio_pack.plasoc_gpio; use work.plasoc_gpio_pack.default_data_out_width; use work.plasoc_gpio_pack.default_data_in_width; use work.plasoc_uart_pack.plasoc_uart; use work.plasoc_0_crossbar_wrap_pack.plasoc_0_crossbar_wrap; use work.plasoc_0_crossbar_wrap_pack.clogb2; use work.plasoc_axi4_full2lite_pack.plasoc_axi4_full2lite; entity axiplasma_wrapper is generic ( lower_app : string := "boot"; upper_app : string := "none"; upper_ext : boolean := true); port( raw_clock : in std_logic; -- 100 MHz on the Nexys 4. raw_nreset : in std_logic; gpio_output : out std_logic_vector(default_data_out_width-1 downto 0); gpio_input : in std_logic_vector(default_data_in_width-1 downto 0); uart_tx : out std_logic; uart_rx : in std_logic; DDR2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 ); DDR2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 ); DDR2_cas_n : out STD_LOGIC; DDR2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR2_cke : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 ); DDR2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 ); DDR2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 ); DDR2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 ); DDR2_odt : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR2_ras_n : out STD_LOGIC; DDR2_we_n : out STD_LOGIC); end axiplasma_wrapper; architecture Behavioral of axiplasma_wrapper is component mig_wrap_wrapper is port ( ACLK : in STD_LOGIC; ARESETN : in STD_LOGIC; DDR2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 ); DDR2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 ); DDR2_cas_n : out STD_LOGIC; DDR2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR2_cke : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 ); DDR2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 ); DDR2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 ); DDR2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 ); DDR2_odt : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR2_ras_n : out STD_LOGIC; DDR2_we_n : out STD_LOGIC; S00_ARESETN : in STD_LOGIC; S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_arready : out STD_LOGIC; S00_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_arvalid : in STD_LOGIC; S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_awready : out STD_LOGIC; S00_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_awvalid : in STD_LOGIC; S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_bready : in STD_LOGIC; S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_bvalid : out STD_LOGIC; S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_rlast : out STD_LOGIC; S00_AXI_rready : in STD_LOGIC; S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_rvalid : out STD_LOGIC; S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_wlast : in STD_LOGIC; S00_AXI_wready : out STD_LOGIC; S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_wvalid : in STD_LOGIC; clk_ref_i : in STD_LOGIC; sys_rst : in STD_LOGIC); end component; -- Component declarations. component bram is generic ( select_app : string := "none"; -- jump, boot, main address_width : integer := 18; data_width : integer := 32; bram_depth : integer := 65536); port( bram_rst_a : in std_logic; bram_clk_a : in std_logic; bram_en_a : in std_logic; bram_we_a : in std_logic_vector(data_width/8-1 downto 0); bram_addr_a : in std_logic_vector(address_width-1 downto 0); bram_wrdata_a : in std_logic_vector(data_width-1 downto 0); bram_rddata_a : out std_logic_vector(data_width-1 downto 0) := (others=>'0')); end component; component axi_cdma_0 is port ( m_axi_aclk : in std_logic; s_axi_lite_aclk : in std_logic; s_axi_lite_aresetn : in std_logic; cdma_introut : out std_logic; s_axi_lite_awready : out std_logic; s_axi_lite_awvalid : in std_logic; s_axi_lite_awaddr : in std_logic_vector(5 downto 0); s_axi_lite_wready : out std_logic; s_axi_lite_wvalid : in std_logic; s_axi_lite_wdata : in std_logic_vector(31 downto 0); s_axi_lite_bready : in std_logic; s_axi_lite_bvalid : out std_logic; s_axi_lite_bresp : out std_logic_vector(1 downto 0); s_axi_lite_arready : out std_logic; s_axi_lite_arvalid : in std_logic; s_axi_lite_araddr : in std_logic_vector(5 downto 0); s_axi_lite_rready : in std_logic; s_axi_lite_rvalid : out std_logic; s_axi_lite_rdata : out std_logic_vector(31 downto 0); s_axi_lite_rresp : out std_logic_vector(1 downto 0); m_axi_arready : in std_logic; m_axi_arvalid : out std_logic; m_axi_araddr : out std_logic_vector(31 downto 0); m_axi_arlen : out std_logic_vector(7 downto 0); m_axi_arsize : out std_logic_vector(2 downto 0); m_axi_arburst : out std_logic_vector(1 downto 0); m_axi_arprot : out std_logic_vector(2 downto 0); m_axi_arcache : out std_logic_vector(3 downto 0); m_axi_rready : out std_logic; m_axi_rvalid : in std_logic; m_axi_rdata : in std_logic_vector(31 downto 0); m_axi_rresp : in std_logic_vector(1 downto 0); m_axi_rlast : in std_logic; m_axi_awready : in std_logic; m_axi_awvalid : out std_logic; m_axi_awaddr : out std_logic_vector(31 downto 0); m_axi_awlen : out std_logic_vector(7 downto 0); m_axi_awsize : out std_logic_vector(2 downto 0); m_axi_awburst : out std_logic_vector(1 downto 0); m_axi_awprot : out std_logic_vector(2 downto 0); m_axi_awcache : out std_logic_vector(3 downto 0); m_axi_wready : in std_logic; m_axi_wvalid : out std_logic; m_axi_wdata : out std_logic_vector(31 downto 0); m_axi_wstrb : out std_logic_vector(3 downto 0); m_axi_wlast : out std_logic; m_axi_bready : out std_logic; m_axi_bvalid : in std_logic; m_axi_bresp : in std_logic_vector(1 downto 0); cdma_tvect_out : out std_logic_vector(31 downto 0)); end component; component clk_wiz_0 is port ( aclk : out std_logic; ddr_aclk : out std_logic; resetn : in std_logic; locked : out std_logic; raw_clock : in std_logic); end component; component proc_sys_reset_0 is port ( slowest_sync_clk : in std_logic; ext_reset_in : in std_logic; aux_reset_in : in std_logic; mb_debug_sys_rst : in std_logic; dcm_locked : in std_logic; mb_reset : out std_logic; bus_struct_reset : out std_logic_vector(0 downto 0); peripheral_reset : out std_logic_vector(0 downto 0); interconnect_aresetn : out std_logic_vector(0 downto 0); peripheral_aresetn : out std_logic_vector(0 downto 0)); end component; component axi_bram_ctrl_0 is port ( s_axi_aclk : in std_logic; s_axi_aresetn : in std_logic; s_axi_awid : in std_logic_vector(0 downto 0); s_axi_awaddr : in std_logic_vector(15 downto 0); s_axi_awlen : in std_logic_vector(7 downto 0); s_axi_awsize : in std_logic_vector(2 downto 0); s_axi_awburst : in std_logic_vector(1 downto 0); s_axi_awlock : in std_logic; s_axi_awcache : in std_logic_vector(3 downto 0); s_axi_awprot : in std_logic_vector(2 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; s_axi_wdata : in std_logic_vector(31 downto 0); s_axi_wstrb : in std_logic_vector(3 downto 0); s_axi_wlast : in std_logic; s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; s_axi_bid : out std_logic_vector(0 downto 0); s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; s_axi_arid : in std_logic_vector(0 downto 0); s_axi_araddr : in std_logic_vector(15 downto 0); s_axi_arlen : in std_logic_vector(7 downto 0); s_axi_arsize : in std_logic_vector(2 downto 0); s_axi_arburst : in std_logic_vector(1 downto 0); s_axi_arlock : in std_logic; s_axi_arcache : in std_logic_vector(3 downto 0); s_axi_arprot : in std_logic_vector(2 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; s_axi_rid : out std_logic_vector(0 downto 0); s_axi_rdata : out std_logic_vector(31 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rlast : out std_logic; s_axi_rvalid : out std_logic; s_axi_rready : in std_logic; bram_rst_a : out std_logic; bram_clk_a : out std_logic; bram_en_a : out std_logic; bram_we_a : out std_logic_vector(3 downto 0); bram_addr_a : out std_logic_vector(15 downto 0); bram_wrdata_a : out std_logic_vector(31 downto 0); bram_rddata_a : in std_logic_vector(31 downto 0)); end component; component axi_bram_ctrl_1 is port ( s_axi_aclk : in std_logic; s_axi_aresetn : in std_logic; s_axi_awid : in std_logic_vector(0 downto 0); s_axi_awaddr : in std_logic_vector(17 downto 0); s_axi_awlen : in std_logic_vector(7 downto 0); s_axi_awsize : in std_logic_vector(2 downto 0); s_axi_awburst : in std_logic_vector(1 downto 0); s_axi_awlock : in std_logic; s_axi_awcache : in std_logic_vector(3 downto 0); s_axi_awprot : in std_logic_vector(2 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; s_axi_wdata : in std_logic_vector(31 downto 0); s_axi_wstrb : in std_logic_vector(3 downto 0); s_axi_wlast : in std_logic; s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; s_axi_bid : out std_logic_vector(0 downto 0); s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; s_axi_arid : in std_logic_vector(0 downto 0); s_axi_araddr : in std_logic_vector(17 downto 0); s_axi_arlen : in std_logic_vector(7 downto 0); s_axi_arsize : in std_logic_vector(2 downto 0); s_axi_arburst : in std_logic_vector(1 downto 0); s_axi_arlock : in std_logic; s_axi_arcache : in std_logic_vector(3 downto 0); s_axi_arprot : in std_logic_vector(2 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; s_axi_rid : out std_logic_vector(0 downto 0); s_axi_rdata : out std_logic_vector(31 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rlast : out std_logic; s_axi_rvalid : out std_logic; s_axi_rready : in std_logic; bram_rst_a : out std_logic; bram_clk_a : out std_logic; bram_en_a : out std_logic; bram_we_a : out std_logic_vector(3 downto 0); bram_addr_a : out std_logic_vector(17 downto 0); bram_wrdata_a : out std_logic_vector(31 downto 0); bram_rddata_a : in std_logic_vector(31 downto 0)); end component; constant axi_address_width : integer := 32; constant axi_data_width : integer := 32; constant axi_master_amount : integer := 5; constant axi_slave_amount : integer := 2; constant axi_slave_id_width : integer := 0; constant axi_master_id_width : integer := clogb2(axi_slave_amount)+axi_slave_id_width; constant axi_lite_address_width : integer := 16; -- a misnomer. constant axi_ram_address_width : integer := 18; constant axi_ram_depth : integer := 65536; signal aclk : std_logic; signal ddr_aclk : std_logic; signal aresetn : std_logic_vector(0 downto 0); signal cross_aresetn : std_logic_vector(0 downto 0); signal dcm_locked : std_logic; signal cpu_axi_full_awid : std_logic_vector(axi_slave_id_width-1 downto 0); signal cpu_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0); signal cpu_axi_full_awlen : std_logic_vector(7 downto 0); signal cpu_axi_full_awsize : std_logic_vector(2 downto 0); signal cpu_axi_full_awburst : std_logic_vector(1 downto 0); signal cpu_axi_full_awlock : std_logic; signal cpu_axi_full_awcache : std_logic_vector(3 downto 0); signal cpu_axi_full_awprot : std_logic_vector(2 downto 0); signal cpu_axi_full_awqos : std_logic_vector(3 downto 0); signal cpu_axi_full_awregion : std_logic_vector(3 downto 0); signal cpu_axi_full_awvalid : std_logic; signal cpu_axi_full_awready : std_logic; signal cpu_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0); signal cpu_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal cpu_axi_full_wlast : std_logic; signal cpu_axi_full_wvalid : std_logic; signal cpu_axi_full_wready : std_logic; signal cpu_axi_full_bid : std_logic_vector(axi_slave_id_width-1 downto 0); signal cpu_axi_full_bresp : std_logic_vector(1 downto 0); signal cpu_axi_full_bvalid : std_logic; signal cpu_axi_full_bready : std_logic; signal cpu_axi_full_arid : std_logic_vector(axi_slave_id_width-1 downto 0); signal cpu_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0); signal cpu_axi_full_arlen : std_logic_vector(7 downto 0); signal cpu_axi_full_arsize : std_logic_vector(2 downto 0); signal cpu_axi_full_arburst : std_logic_vector(1 downto 0); signal cpu_axi_full_arlock : std_logic; signal cpu_axi_full_arcache : std_logic_vector(3 downto 0); signal cpu_axi_full_arprot : std_logic_vector(2 downto 0); signal cpu_axi_full_arqos : std_logic_vector(3 downto 0); signal cpu_axi_full_arregion : std_logic_vector(3 downto 0); signal cpu_axi_full_arvalid : std_logic; signal cpu_axi_full_arready : std_logic; signal cpu_axi_full_rid : std_logic_vector(axi_slave_id_width-1 downto 0); signal cpu_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0); signal cpu_axi_full_rresp : std_logic_vector(1 downto 0); signal cpu_axi_full_rlast : std_logic; signal cpu_axi_full_rvalid : std_logic; signal cpu_axi_full_rready : std_logic; signal cdma_axi_full_awid : std_logic_vector(axi_slave_id_width-1 downto 0); signal cdma_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0); signal cdma_axi_full_awlen : std_logic_vector(7 downto 0); signal cdma_axi_full_awsize : std_logic_vector(2 downto 0); signal cdma_axi_full_awburst : std_logic_vector(1 downto 0); signal cdma_axi_full_awlock : std_logic; signal cdma_axi_full_awcache : std_logic_vector(3 downto 0); signal cdma_axi_full_awprot : std_logic_vector(2 downto 0); signal cdma_axi_full_awqos : std_logic_vector(3 downto 0); signal cdma_axi_full_awregion : std_logic_vector(3 downto 0); signal cdma_axi_full_awvalid : std_logic; signal cdma_axi_full_awready : std_logic; signal cdma_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0); signal cdma_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal cdma_axi_full_wlast : std_logic; signal cdma_axi_full_wvalid : std_logic; signal cdma_axi_full_wready : std_logic; signal cdma_axi_full_bid : std_logic_vector(axi_slave_id_width-1 downto 0); signal cdma_axi_full_bresp : std_logic_vector(1 downto 0); signal cdma_axi_full_bvalid : std_logic; signal cdma_axi_full_bready : std_logic; signal cdma_axi_full_arid : std_logic_vector(axi_slave_id_width-1 downto 0); signal cdma_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0); signal cdma_axi_full_arlen : std_logic_vector(7 downto 0); signal cdma_axi_full_arsize : std_logic_vector(2 downto 0); signal cdma_axi_full_arburst : std_logic_vector(1 downto 0); signal cdma_axi_full_arlock : std_logic; signal cdma_axi_full_arcache : std_logic_vector(3 downto 0); signal cdma_axi_full_arprot : std_logic_vector(2 downto 0); signal cdma_axi_full_arqos : std_logic_vector(3 downto 0); signal cdma_axi_full_arregion : std_logic_vector(3 downto 0); signal cdma_axi_full_arvalid : std_logic; signal cdma_axi_full_arready : std_logic; signal cdma_axi_full_rid : std_logic_vector(axi_slave_id_width-1 downto 0); signal cdma_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0); signal cdma_axi_full_rresp : std_logic_vector(1 downto 0); signal cdma_axi_full_rlast : std_logic; signal cdma_axi_full_rvalid : std_logic; signal cdma_axi_full_rready : std_logic; signal bram_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0); signal bram_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0); signal bram_axi_full_awlen : std_logic_vector(7 downto 0); signal bram_axi_full_awsize : std_logic_vector(2 downto 0); signal bram_axi_full_awburst : std_logic_vector(1 downto 0); signal bram_axi_full_awlock : std_logic; signal bram_axi_full_awcache : std_logic_vector(3 downto 0); signal bram_axi_full_awprot : std_logic_vector(2 downto 0); signal bram_axi_full_awqos : std_logic_vector(3 downto 0); signal bram_axi_full_awregion : std_logic_vector(3 downto 0); signal bram_axi_full_awvalid : std_logic; signal bram_axi_full_awready : std_logic; signal bram_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0); signal bram_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal bram_axi_full_wlast : std_logic; signal bram_axi_full_wvalid : std_logic; signal bram_axi_full_wready : std_logic; signal bram_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0); signal bram_axi_full_bresp : std_logic_vector(1 downto 0); signal bram_axi_full_bvalid : std_logic; signal bram_axi_full_bready : std_logic; signal bram_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0); signal bram_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0); signal bram_axi_full_arlen : std_logic_vector(7 downto 0); signal bram_axi_full_arsize : std_logic_vector(2 downto 0); signal bram_axi_full_arburst : std_logic_vector(1 downto 0); signal bram_axi_full_arlock : std_logic; signal bram_axi_full_arcache : std_logic_vector(3 downto 0); signal bram_axi_full_arprot : std_logic_vector(2 downto 0); signal bram_axi_full_arqos : std_logic_vector(3 downto 0); signal bram_axi_full_arregion : std_logic_vector(3 downto 0); signal bram_axi_full_arvalid : std_logic; signal bram_axi_full_arready : std_logic; signal bram_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0); signal bram_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0); signal bram_axi_full_rresp : std_logic_vector(1 downto 0); signal bram_axi_full_rlast : std_logic; signal bram_axi_full_rvalid : std_logic; signal bram_axi_full_rready : std_logic; signal bram_bram_rst_a : STD_LOGIC; signal bram_bram_clk_a : STD_LOGIC; signal bram_bram_en_a : STD_LOGIC; signal bram_bram_we_a : STD_LOGIC_VECTOR(axi_data_width/8-1 DOWNTO 0); signal bram_bram_addr_a : STD_LOGIC_VECTOR(axi_lite_address_width-1 DOWNTO 0); signal bram_bram_wrdata_a : STD_LOGIC_VECTOR(axi_data_width-1 DOWNTO 0); signal bram_bram_rddata_a : STD_LOGIC_VECTOR(axi_data_width-1 DOWNTO 0); signal ram_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0); signal ram_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0); signal ram_axi_full_awlen : std_logic_vector(7 downto 0); signal ram_axi_full_awsize : std_logic_vector(2 downto 0); signal ram_axi_full_awburst : std_logic_vector(1 downto 0); signal ram_axi_full_awlock : std_logic; signal ram_axi_full_awcache : std_logic_vector(3 downto 0); signal ram_axi_full_awprot : std_logic_vector(2 downto 0); signal ram_axi_full_awqos : std_logic_vector(3 downto 0); signal ram_axi_full_awregion : std_logic_vector(3 downto 0); signal ram_axi_full_awvalid : std_logic; signal ram_axi_full_awready : std_logic; signal ram_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0); signal ram_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal ram_axi_full_wlast : std_logic; signal ram_axi_full_wvalid : std_logic; signal ram_axi_full_wready : std_logic; signal ram_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0); signal ram_axi_full_bresp : std_logic_vector(1 downto 0); signal ram_axi_full_bvalid : std_logic; signal ram_axi_full_bready : std_logic; signal ram_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0); signal ram_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0); signal ram_axi_full_arlen : std_logic_vector(7 downto 0); signal ram_axi_full_arsize : std_logic_vector(2 downto 0); signal ram_axi_full_arburst : std_logic_vector(1 downto 0); signal ram_axi_full_arlock : std_logic; signal ram_axi_full_arcache : std_logic_vector(3 downto 0); signal ram_axi_full_arprot : std_logic_vector(2 downto 0); signal ram_axi_full_arqos : std_logic_vector(3 downto 0); signal ram_axi_full_arregion : std_logic_vector(3 downto 0); signal ram_axi_full_arvalid : std_logic; signal ram_axi_full_arready : std_logic; signal ram_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0); signal ram_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0); signal ram_axi_full_rresp : std_logic_vector(1 downto 0); signal ram_axi_full_rlast : std_logic; signal ram_axi_full_rvalid : std_logic; signal ram_axi_full_rready : std_logic; signal ram_axi_full_arlock_slv : std_logic_vector (0 downto 0); signal ram_axi_full_awlock_slv : std_logic_vector (0 downto 0); signal ram_axi_full_arid_slv : std_logic_vector(3 downto 0) := (others=>'0'); signal ram_axi_full_awid_slv : std_logic_vector(3 downto 0) := (others=>'0'); signal ram_axi_full_bid_slv : std_logic_vector(3 downto 0) := (others=>'0'); signal ram_axi_full_rid_slv : std_logic_vector(3 downto 0) := (others=>'0'); signal ram_bram_rst_a : std_logic; signal ram_bram_clk_a : std_logic; signal ram_bram_en_a : std_logic; signal ram_bram_we_a : std_logic_vector(axi_data_width/8-1 downto 0); signal ram_bram_addr_a : std_logic_vector(axi_ram_address_width-1 downto 0); signal ram_bram_wrdata_a : std_logic_vector(axi_data_width-1 downto 0); signal ram_bram_rddata_a : std_logic_vector(axi_data_width-1 downto 0); signal int_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0); signal int_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0); signal int_axi_full_awlen : std_logic_vector(7 downto 0); signal int_axi_full_awsize : std_logic_vector(2 downto 0); signal int_axi_full_awburst : std_logic_vector(1 downto 0); signal int_axi_full_awlock : std_logic; signal int_axi_full_awcache : std_logic_vector(3 downto 0); signal int_axi_full_awprot : std_logic_vector(2 downto 0); signal int_axi_full_awqos : std_logic_vector(3 downto 0); signal int_axi_full_awregion : std_logic_vector(3 downto 0); signal int_axi_full_awvalid : std_logic; signal int_axi_full_awready : std_logic; signal int_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0); signal int_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal int_axi_full_wlast : std_logic; signal int_axi_full_wvalid : std_logic; signal int_axi_full_wready : std_logic; signal int_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0); signal int_axi_full_bresp : std_logic_vector(1 downto 0); signal int_axi_full_bvalid : std_logic; signal int_axi_full_bready : std_logic; signal int_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0); signal int_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0); signal int_axi_full_arlen : std_logic_vector(7 downto 0); signal int_axi_full_arsize : std_logic_vector(2 downto 0); signal int_axi_full_arburst : std_logic_vector(1 downto 0); signal int_axi_full_arlock : std_logic; signal int_axi_full_arcache : std_logic_vector(3 downto 0); signal int_axi_full_arprot : std_logic_vector(2 downto 0); signal int_axi_full_arqos : std_logic_vector(3 downto 0); signal int_axi_full_arregion : std_logic_vector(3 downto 0); signal int_axi_full_arvalid : std_logic; signal int_axi_full_arready : std_logic; signal int_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0); signal int_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0); signal int_axi_full_rresp : std_logic_vector(1 downto 0); signal int_axi_full_rlast : std_logic; signal int_axi_full_rvalid : std_logic; signal int_axi_full_rready : std_logic; signal timer_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0); signal timer_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0); signal timer_axi_full_awlen : std_logic_vector(7 downto 0); signal timer_axi_full_awsize : std_logic_vector(2 downto 0); signal timer_axi_full_awburst : std_logic_vector(1 downto 0); signal timer_axi_full_awlock : std_logic; signal timer_axi_full_awcache : std_logic_vector(3 downto 0); signal timer_axi_full_awprot : std_logic_vector(2 downto 0); signal timer_axi_full_awqos : std_logic_vector(3 downto 0); signal timer_axi_full_awregion : std_logic_vector(3 downto 0); signal timer_axi_full_awvalid : std_logic; signal timer_axi_full_awready : std_logic; signal timer_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0); signal timer_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal timer_axi_full_wlast : std_logic; signal timer_axi_full_wvalid : std_logic; signal timer_axi_full_wready : std_logic; signal timer_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0); signal timer_axi_full_bresp : std_logic_vector(1 downto 0); signal timer_axi_full_bvalid : std_logic; signal timer_axi_full_bready : std_logic; signal timer_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0); signal timer_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0); signal timer_axi_full_arlen : std_logic_vector(7 downto 0); signal timer_axi_full_arsize : std_logic_vector(2 downto 0); signal timer_axi_full_arburst : std_logic_vector(1 downto 0); signal timer_axi_full_arlock : std_logic; signal timer_axi_full_arcache : std_logic_vector(3 downto 0); signal timer_axi_full_arprot : std_logic_vector(2 downto 0); signal timer_axi_full_arqos : std_logic_vector(3 downto 0); signal timer_axi_full_arregion : std_logic_vector(3 downto 0); signal timer_axi_full_arvalid : std_logic; signal timer_axi_full_arready : std_logic; signal timer_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0); signal timer_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0); signal timer_axi_full_rresp : std_logic_vector(1 downto 0); signal timer_axi_full_rlast : std_logic; signal timer_axi_full_rvalid : std_logic; signal timer_axi_full_rready : std_logic; signal gpio_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0); signal gpio_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0); signal gpio_axi_full_awlen : std_logic_vector(7 downto 0); signal gpio_axi_full_awsize : std_logic_vector(2 downto 0); signal gpio_axi_full_awburst : std_logic_vector(1 downto 0); signal gpio_axi_full_awlock : std_logic; signal gpio_axi_full_awcache : std_logic_vector(3 downto 0); signal gpio_axi_full_awprot : std_logic_vector(2 downto 0); signal gpio_axi_full_awqos : std_logic_vector(3 downto 0); signal gpio_axi_full_awregion : std_logic_vector(3 downto 0); signal gpio_axi_full_awvalid : std_logic; signal gpio_axi_full_awready : std_logic; signal gpio_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0); signal gpio_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal gpio_axi_full_wlast : std_logic; signal gpio_axi_full_wvalid : std_logic; signal gpio_axi_full_wready : std_logic; signal gpio_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0); signal gpio_axi_full_bresp : std_logic_vector(1 downto 0); signal gpio_axi_full_bvalid : std_logic; signal gpio_axi_full_bready : std_logic; signal gpio_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0); signal gpio_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0); signal gpio_axi_full_arlen : std_logic_vector(7 downto 0); signal gpio_axi_full_arsize : std_logic_vector(2 downto 0); signal gpio_axi_full_arburst : std_logic_vector(1 downto 0); signal gpio_axi_full_arlock : std_logic; signal gpio_axi_full_arcache : std_logic_vector(3 downto 0); signal gpio_axi_full_arprot : std_logic_vector(2 downto 0); signal gpio_axi_full_arqos : std_logic_vector(3 downto 0); signal gpio_axi_full_arregion : std_logic_vector(3 downto 0); signal gpio_axi_full_arvalid : std_logic; signal gpio_axi_full_arready : std_logic; signal gpio_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0); signal gpio_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0); signal gpio_axi_full_rresp : std_logic_vector(1 downto 0); signal gpio_axi_full_rlast : std_logic; signal gpio_axi_full_rvalid : std_logic; signal gpio_axi_full_rready : std_logic; signal cdmareg_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0); signal cdmareg_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0); signal cdmareg_axi_full_awlen : std_logic_vector(7 downto 0); signal cdmareg_axi_full_awsize : std_logic_vector(2 downto 0); signal cdmareg_axi_full_awburst : std_logic_vector(1 downto 0); signal cdmareg_axi_full_awlock : std_logic; signal cdmareg_axi_full_awcache : std_logic_vector(3 downto 0); signal cdmareg_axi_full_awprot : std_logic_vector(2 downto 0); signal cdmareg_axi_full_awqos : std_logic_vector(3 downto 0); signal cdmareg_axi_full_awregion : std_logic_vector(3 downto 0); signal cdmareg_axi_full_awvalid : std_logic; signal cdmareg_axi_full_awready : std_logic; signal cdmareg_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0); signal cdmareg_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal cdmareg_axi_full_wlast : std_logic; signal cdmareg_axi_full_wvalid : std_logic; signal cdmareg_axi_full_wready : std_logic; signal cdmareg_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0); signal cdmareg_axi_full_bresp : std_logic_vector(1 downto 0); signal cdmareg_axi_full_bvalid : std_logic; signal cdmareg_axi_full_bready : std_logic; signal cdmareg_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0); signal cdmareg_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0); signal cdmareg_axi_full_arlen : std_logic_vector(7 downto 0); signal cdmareg_axi_full_arsize : std_logic_vector(2 downto 0); signal cdmareg_axi_full_arburst : std_logic_vector(1 downto 0); signal cdmareg_axi_full_arlock : std_logic; signal cdmareg_axi_full_arcache : std_logic_vector(3 downto 0); signal cdmareg_axi_full_arprot : std_logic_vector(2 downto 0); signal cdmareg_axi_full_arqos : std_logic_vector(3 downto 0); signal cdmareg_axi_full_arregion : std_logic_vector(3 downto 0); signal cdmareg_axi_full_arvalid : std_logic; signal cdmareg_axi_full_arready : std_logic; signal cdmareg_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0); signal cdmareg_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0); signal cdmareg_axi_full_rresp : std_logic_vector(1 downto 0); signal cdmareg_axi_full_rlast : std_logic; signal cdmareg_axi_full_rvalid : std_logic; signal cdmareg_axi_full_rready : std_logic; signal timer_extra_0_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0); signal timer_extra_0_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0); signal timer_extra_0_axi_full_awlen : std_logic_vector(7 downto 0); signal timer_extra_0_axi_full_awsize : std_logic_vector(2 downto 0); signal timer_extra_0_axi_full_awburst : std_logic_vector(1 downto 0); signal timer_extra_0_axi_full_awlock : std_logic; signal timer_extra_0_axi_full_awcache : std_logic_vector(3 downto 0); signal timer_extra_0_axi_full_awprot : std_logic_vector(2 downto 0); signal timer_extra_0_axi_full_awqos : std_logic_vector(3 downto 0); signal timer_extra_0_axi_full_awregion : std_logic_vector(3 downto 0); signal timer_extra_0_axi_full_awvalid : std_logic; signal timer_extra_0_axi_full_awready : std_logic; signal timer_extra_0_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0); signal timer_extra_0_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal timer_extra_0_axi_full_wlast : std_logic; signal timer_extra_0_axi_full_wvalid : std_logic; signal timer_extra_0_axi_full_wready : std_logic; signal timer_extra_0_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0); signal timer_extra_0_axi_full_bresp : std_logic_vector(1 downto 0); signal timer_extra_0_axi_full_bvalid : std_logic; signal timer_extra_0_axi_full_bready : std_logic; signal timer_extra_0_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0); signal timer_extra_0_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0); signal timer_extra_0_axi_full_arlen : std_logic_vector(7 downto 0); signal timer_extra_0_axi_full_arsize : std_logic_vector(2 downto 0); signal timer_extra_0_axi_full_arburst : std_logic_vector(1 downto 0); signal timer_extra_0_axi_full_arlock : std_logic; signal timer_extra_0_axi_full_arcache : std_logic_vector(3 downto 0); signal timer_extra_0_axi_full_arprot : std_logic_vector(2 downto 0); signal timer_extra_0_axi_full_arqos : std_logic_vector(3 downto 0); signal timer_extra_0_axi_full_arregion : std_logic_vector(3 downto 0); signal timer_extra_0_axi_full_arvalid : std_logic; signal timer_extra_0_axi_full_arready : std_logic; signal timer_extra_0_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0); signal timer_extra_0_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0); signal timer_extra_0_axi_full_rresp : std_logic_vector(1 downto 0); signal timer_extra_0_axi_full_rlast : std_logic; signal timer_extra_0_axi_full_rvalid : std_logic; signal timer_extra_0_axi_full_rready : std_logic; signal uart_axi_full_awid : std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0); signal uart_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0); signal uart_axi_full_awlen : std_logic_vector(7 downto 0); signal uart_axi_full_awsize : std_logic_vector(2 downto 0); signal uart_axi_full_awburst : std_logic_vector(1 downto 0); signal uart_axi_full_awlock : std_logic; signal uart_axi_full_awcache : std_logic_vector(3 downto 0); signal uart_axi_full_awprot : std_logic_vector(2 downto 0); signal uart_axi_full_awqos : std_logic_vector(3 downto 0); signal uart_axi_full_awregion : std_logic_vector(3 downto 0); signal uart_axi_full_awvalid : std_logic; signal uart_axi_full_awready : std_logic; signal uart_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0); signal uart_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal uart_axi_full_wlast : std_logic; signal uart_axi_full_wvalid : std_logic; signal uart_axi_full_wready : std_logic; signal uart_axi_full_bid : std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0); signal uart_axi_full_bresp : std_logic_vector(1 downto 0); signal uart_axi_full_bvalid : std_logic; signal uart_axi_full_bready : std_logic; signal uart_axi_full_arid : std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0); signal uart_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0); signal uart_axi_full_arlen : std_logic_vector(7 downto 0); signal uart_axi_full_arsize : std_logic_vector(2 downto 0); signal uart_axi_full_arburst : std_logic_vector(1 downto 0); signal uart_axi_full_arlock : std_logic; signal uart_axi_full_arcache : std_logic_vector(3 downto 0); signal uart_axi_full_arprot : std_logic_vector(2 downto 0); signal uart_axi_full_arqos : std_logic_vector(3 downto 0); signal uart_axi_full_arregion : std_logic_vector(3 downto 0); signal uart_axi_full_arvalid : std_logic; signal uart_axi_full_arready : std_logic; signal uart_axi_full_rid : std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0); signal uart_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0); signal uart_axi_full_rresp : std_logic_vector(1 downto 0); signal uart_axi_full_rlast : std_logic; signal uart_axi_full_rvalid : std_logic; signal uart_axi_full_rready : std_logic; signal int_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal int_axi_lite_awprot : std_logic_vector(2 downto 0); signal int_axi_lite_awvalid : std_logic; signal int_axi_lite_awready : std_logic; signal int_axi_lite_wvalid : std_logic; signal int_axi_lite_wready : std_logic; signal int_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0); signal int_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal int_axi_lite_bvalid : std_logic; signal int_axi_lite_bready : std_logic; signal int_axi_lite_bresp : std_logic_vector(1 downto 0); signal int_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal int_axi_lite_arprot : std_logic_vector(2 downto 0); signal int_axi_lite_arvalid : std_logic; signal int_axi_lite_arready : std_logic; signal int_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); signal int_axi_lite_rvalid : std_logic; signal int_axi_lite_rready : std_logic; signal int_axi_lite_rresp : std_logic_vector(1 downto 0); signal timer_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal timer_axi_lite_awprot : std_logic_vector(2 downto 0); signal timer_axi_lite_awvalid : std_logic; signal timer_axi_lite_awready : std_logic; signal timer_axi_lite_wvalid : std_logic; signal timer_axi_lite_wready : std_logic; signal timer_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0); signal timer_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal timer_axi_lite_bvalid : std_logic; signal timer_axi_lite_bready : std_logic; signal timer_axi_lite_bresp : std_logic_vector(1 downto 0); signal timer_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal timer_axi_lite_arprot : std_logic_vector(2 downto 0); signal timer_axi_lite_arvalid : std_logic; signal timer_axi_lite_arready : std_logic; signal timer_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); signal timer_axi_lite_rvalid : std_logic; signal timer_axi_lite_rready : std_logic; signal timer_axi_lite_rresp : std_logic_vector(1 downto 0); signal gpio_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal gpio_axi_lite_awprot : std_logic_vector(2 downto 0); signal gpio_axi_lite_awvalid : std_logic; signal gpio_axi_lite_awready : std_logic; signal gpio_axi_lite_wvalid : std_logic; signal gpio_axi_lite_wready : std_logic; signal gpio_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0); signal gpio_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal gpio_axi_lite_bvalid : std_logic; signal gpio_axi_lite_bready : std_logic; signal gpio_axi_lite_bresp : std_logic_vector(1 downto 0); signal gpio_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal gpio_axi_lite_arprot : std_logic_vector(2 downto 0); signal gpio_axi_lite_arvalid : std_logic; signal gpio_axi_lite_arready : std_logic; signal gpio_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); signal gpio_axi_lite_rvalid : std_logic; signal gpio_axi_lite_rready : std_logic; signal gpio_axi_lite_rresp : std_logic_vector(1 downto 0); signal cdmareg_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal cdmareg_axi_lite_awprot : std_logic_vector(2 downto 0); signal cdmareg_axi_lite_awvalid : std_logic; signal cdmareg_axi_lite_awready : std_logic; signal cdmareg_axi_lite_wvalid : std_logic; signal cdmareg_axi_lite_wready : std_logic; signal cdmareg_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0); signal cdmareg_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal cdmareg_axi_lite_bvalid : std_logic; signal cdmareg_axi_lite_bready : std_logic; signal cdmareg_axi_lite_bresp : std_logic_vector(1 downto 0); signal cdmareg_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal cdmareg_axi_lite_arprot : std_logic_vector(2 downto 0); signal cdmareg_axi_lite_arvalid : std_logic; signal cdmareg_axi_lite_arready : std_logic; signal cdmareg_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); signal cdmareg_axi_lite_rvalid : std_logic; signal cdmareg_axi_lite_rready : std_logic; signal cdmareg_axi_lite_rresp : std_logic_vector(1 downto 0); signal uart_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal uart_axi_lite_awprot : std_logic_vector(2 downto 0); signal uart_axi_lite_awvalid : std_logic; signal uart_axi_lite_awready : std_logic; signal uart_axi_lite_wvalid : std_logic; signal uart_axi_lite_wready : std_logic; signal uart_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0); signal uart_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal uart_axi_lite_bvalid : std_logic; signal uart_axi_lite_bready : std_logic; signal uart_axi_lite_bresp : std_logic_vector(1 downto 0); signal uart_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal uart_axi_lite_arprot : std_logic_vector(2 downto 0); signal uart_axi_lite_arvalid : std_logic; signal uart_axi_lite_arready : std_logic; signal uart_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0); signal uart_axi_lite_rvalid : std_logic; signal uart_axi_lite_rready : std_logic; signal uart_axi_lite_rresp : std_logic_vector(1 downto 0); signal timer_extra_0_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal timer_extra_0_axi_lite_awprot : std_logic_vector(2 downto 0); signal timer_extra_0_axi_lite_awvalid : std_logic; signal timer_extra_0_axi_lite_awready : std_logic; signal timer_extra_0_axi_lite_wvalid : std_logic; signal timer_extra_0_axi_lite_wready : std_logic; signal timer_extra_0_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0); signal timer_extra_0_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0); signal timer_extra_0_axi_lite_bvalid : std_logic; signal timer_extra_0_axi_lite_bready : std_logic; signal timer_extra_0_axi_lite_bresp : std_logic_vector(1 downto 0); signal timer_extra_0_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0); signal timer_extra_0_axi_lite_arprot : std_logic_vector(2 downto 0); signal timer_extra_0_axi_lite_arvalid : std_logic; signal timer_extra_0_axi_lite_arready : std_logic; signal timer_extra_0_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0); signal timer_extra_0_axi_lite_rvalid : std_logic; signal timer_extra_0_axi_lite_rready : std_logic; signal timer_extra_0_axi_lite_rresp : std_logic_vector(1 downto 0); signal cpu_int : std_logic; signal int_dev_ints : std_logic_vector(default_interrupt_total-1 downto 0) := (others=>'0'); signal timer_int : std_logic; signal gpio_int : std_logic; signal cdma_int : std_logic; signal uart_int : std_logic; signal timer_extra_0_int : std_logic; begin int_dev_ints(0) <= timer_int; int_dev_ints(1) <= gpio_int; int_dev_ints(2) <= cdma_int; int_dev_ints(3) <= uart_int; int_dev_ints(4) <= timer_extra_0_int; cdma_axi_full_awlock <= '0'; cdma_axi_full_arlock <= '0'; ram_axi_full_arlock_slv(0) <= ram_axi_full_arlock; ram_axi_full_awlock_slv(0) <= ram_axi_full_awlock; ram_axi_full_arid_slv(axi_master_id_width-1 downto 0) <= ram_axi_full_arid; ram_axi_full_awid_slv(axi_master_id_width-1 downto 0) <= ram_axi_full_awid; ram_axi_full_bid_slv(axi_master_id_width-1 downto 0) <= ram_axi_full_bid; ram_axi_full_rid_slv(axi_master_id_width-1 downto 0) <= ram_axi_full_rid; -- Clock instantiation. clk_wiz_inst : clk_wiz_0 port map ( aclk => aclk, ddr_aclk => ddr_aclk, resetn => raw_nreset, locked => dcm_locked, raw_clock => raw_clock); -- Reset core instantiation. proc_sys_reset_inst : proc_sys_reset_0 PORT map ( slowest_sync_clk => aclk, ext_reset_in => raw_nreset, aux_reset_in => '0', mb_debug_sys_rst => '0', dcm_locked => dcm_locked, mb_reset => open, bus_struct_reset => open, peripheral_reset => open, interconnect_aresetn => cross_aresetn, peripheral_aresetn => aresetn); -- Crossbar instantiation. plasoc_0_crossbar_wrap_inst : plasoc_0_crossbar_wrap port map ( cpu_s_axi_awid => cpu_axi_full_awid, cpu_s_axi_awaddr => cpu_axi_full_awaddr, cpu_s_axi_awlen => cpu_axi_full_awlen, cpu_s_axi_awsize => cpu_axi_full_awsize, cpu_s_axi_awburst => cpu_axi_full_awburst, cpu_s_axi_awlock => cpu_axi_full_awlock, cpu_s_axi_awcache => cpu_axi_full_awcache, cpu_s_axi_awprot => cpu_axi_full_awprot, cpu_s_axi_awqos => cpu_axi_full_awqos, cpu_s_axi_awregion => cpu_axi_full_awregion, cpu_s_axi_awvalid => cpu_axi_full_awvalid, cpu_s_axi_awready => cpu_axi_full_awready, cpu_s_axi_wdata => cpu_axi_full_wdata, cpu_s_axi_wstrb => cpu_axi_full_wstrb, cpu_s_axi_wlast => cpu_axi_full_wlast, cpu_s_axi_wvalid => cpu_axi_full_wvalid, cpu_s_axi_wready => cpu_axi_full_wready, cpu_s_axi_bid => cpu_axi_full_bid, cpu_s_axi_bresp => cpu_axi_full_bresp, cpu_s_axi_bvalid => cpu_axi_full_bvalid, cpu_s_axi_bready => cpu_axi_full_bready, cpu_s_axi_arid => cpu_axi_full_arid, cpu_s_axi_araddr => cpu_axi_full_araddr, cpu_s_axi_arlen => cpu_axi_full_arlen, cpu_s_axi_arsize => cpu_axi_full_arsize, cpu_s_axi_arburst => cpu_axi_full_arburst, cpu_s_axi_arlock => cpu_axi_full_arlock, cpu_s_axi_arcache => cpu_axi_full_arcache, cpu_s_axi_arprot => cpu_axi_full_arprot, cpu_s_axi_arqos => cpu_axi_full_arqos, cpu_s_axi_arregion => cpu_axi_full_arregion, cpu_s_axi_arvalid => cpu_axi_full_arvalid, cpu_s_axi_arready => cpu_axi_full_arready, cpu_s_axi_rid => cpu_axi_full_rid, cpu_s_axi_rdata => cpu_axi_full_rdata, cpu_s_axi_rresp => cpu_axi_full_rresp, cpu_s_axi_rlast => cpu_axi_full_rlast, cpu_s_axi_rvalid => cpu_axi_full_rvalid, cpu_s_axi_rready => cpu_axi_full_rready, cdma_s_axi_awid => cdma_axi_full_awid, cdma_s_axi_awaddr => cdma_axi_full_awaddr, cdma_s_axi_awlen => cdma_axi_full_awlen, cdma_s_axi_awsize => cdma_axi_full_awsize, cdma_s_axi_awburst => cdma_axi_full_awburst, cdma_s_axi_awlock => cdma_axi_full_awlock, cdma_s_axi_awcache => cdma_axi_full_awcache, cdma_s_axi_awprot => cdma_axi_full_awprot, cdma_s_axi_awqos => cdma_axi_full_awqos, cdma_s_axi_awregion => cdma_axi_full_awregion, cdma_s_axi_awvalid => cdma_axi_full_awvalid, cdma_s_axi_awready => cdma_axi_full_awready, cdma_s_axi_wdata => cdma_axi_full_wdata, cdma_s_axi_wstrb => cdma_axi_full_wstrb, cdma_s_axi_wlast => cdma_axi_full_wlast, cdma_s_axi_wvalid => cdma_axi_full_wvalid, cdma_s_axi_wready => cdma_axi_full_wready, cdma_s_axi_bid => cdma_axi_full_bid, cdma_s_axi_bresp => cdma_axi_full_bresp, cdma_s_axi_bvalid => cdma_axi_full_bvalid, cdma_s_axi_bready => cdma_axi_full_bready, cdma_s_axi_arid => cdma_axi_full_arid, cdma_s_axi_araddr => cdma_axi_full_araddr, cdma_s_axi_arlen => cdma_axi_full_arlen, cdma_s_axi_arsize => cdma_axi_full_arsize, cdma_s_axi_arburst => cdma_axi_full_arburst, cdma_s_axi_arlock => cdma_axi_full_arlock, cdma_s_axi_arcache => cdma_axi_full_arcache, cdma_s_axi_arprot => cdma_axi_full_arprot, cdma_s_axi_arqos => cdma_axi_full_arqos, cdma_s_axi_arregion => cdma_axi_full_arregion, cdma_s_axi_arvalid => cdma_axi_full_arvalid, cdma_s_axi_arready => cdma_axi_full_arready, cdma_s_axi_rid => cdma_axi_full_rid, cdma_s_axi_rdata => cdma_axi_full_rdata, cdma_s_axi_rresp => cdma_axi_full_rresp, cdma_s_axi_rlast => cdma_axi_full_rlast, cdma_s_axi_rvalid => cdma_axi_full_rvalid, cdma_s_axi_rready => cdma_axi_full_rready, bram_m_axi_awid => bram_axi_full_awid, bram_m_axi_awaddr => bram_axi_full_awaddr, bram_m_axi_awlen => bram_axi_full_awlen, bram_m_axi_awsize => bram_axi_full_awsize, bram_m_axi_awburst => bram_axi_full_awburst, bram_m_axi_awlock => bram_axi_full_awlock, bram_m_axi_awcache => bram_axi_full_awcache, bram_m_axi_awprot => bram_axi_full_awprot, bram_m_axi_awqos => bram_axi_full_awqos, bram_m_axi_awregion => bram_axi_full_awregion, bram_m_axi_awvalid => bram_axi_full_awvalid, bram_m_axi_awready => bram_axi_full_awready, bram_m_axi_wdata => bram_axi_full_wdata, bram_m_axi_wstrb => bram_axi_full_wstrb, bram_m_axi_wlast => bram_axi_full_wlast, bram_m_axi_wvalid => bram_axi_full_wvalid, bram_m_axi_wready => bram_axi_full_wready, bram_m_axi_bid => bram_axi_full_bid, bram_m_axi_bresp => bram_axi_full_bresp, bram_m_axi_bvalid => bram_axi_full_bvalid, bram_m_axi_bready => bram_axi_full_bready, bram_m_axi_arid => bram_axi_full_arid, bram_m_axi_araddr => bram_axi_full_araddr, bram_m_axi_arlen => bram_axi_full_arlen, bram_m_axi_arsize => bram_axi_full_arsize, bram_m_axi_arburst => bram_axi_full_arburst, bram_m_axi_arlock => bram_axi_full_arlock, bram_m_axi_arcache => bram_axi_full_arcache, bram_m_axi_arprot => bram_axi_full_arprot, bram_m_axi_arqos => bram_axi_full_arqos, bram_m_axi_arregion => bram_axi_full_arregion, bram_m_axi_arvalid => bram_axi_full_arvalid, bram_m_axi_arready => bram_axi_full_arready, bram_m_axi_rid => bram_axi_full_rid, bram_m_axi_rdata => bram_axi_full_rdata, bram_m_axi_rresp => bram_axi_full_rresp, bram_m_axi_rlast => bram_axi_full_rlast, bram_m_axi_rvalid => bram_axi_full_rvalid, bram_m_axi_rready => bram_axi_full_rready, ram_m_axi_awid => ram_axi_full_awid, ram_m_axi_awaddr => ram_axi_full_awaddr, ram_m_axi_awlen => ram_axi_full_awlen, ram_m_axi_awsize => ram_axi_full_awsize, ram_m_axi_awburst => ram_axi_full_awburst, ram_m_axi_awlock => ram_axi_full_awlock, ram_m_axi_awcache => ram_axi_full_awcache, ram_m_axi_awprot => ram_axi_full_awprot, ram_m_axi_awqos => ram_axi_full_awqos, ram_m_axi_awregion => ram_axi_full_awregion, ram_m_axi_awvalid => ram_axi_full_awvalid, ram_m_axi_awready => ram_axi_full_awready, ram_m_axi_wdata => ram_axi_full_wdata, ram_m_axi_wstrb => ram_axi_full_wstrb, ram_m_axi_wlast => ram_axi_full_wlast, ram_m_axi_wvalid => ram_axi_full_wvalid, ram_m_axi_wready => ram_axi_full_wready, ram_m_axi_bid => ram_axi_full_bid, ram_m_axi_bresp => ram_axi_full_bresp, ram_m_axi_bvalid => ram_axi_full_bvalid, ram_m_axi_bready => ram_axi_full_bready, ram_m_axi_arid => ram_axi_full_arid, ram_m_axi_araddr => ram_axi_full_araddr, ram_m_axi_arlen => ram_axi_full_arlen, ram_m_axi_arsize => ram_axi_full_arsize, ram_m_axi_arburst => ram_axi_full_arburst, ram_m_axi_arlock => ram_axi_full_arlock, ram_m_axi_arcache => ram_axi_full_arcache, ram_m_axi_arprot => ram_axi_full_arprot, ram_m_axi_arqos => ram_axi_full_arqos, ram_m_axi_arregion => ram_axi_full_arregion, ram_m_axi_arvalid => ram_axi_full_arvalid, ram_m_axi_arready => ram_axi_full_arready, ram_m_axi_rid => ram_axi_full_rid, ram_m_axi_rdata => ram_axi_full_rdata, ram_m_axi_rresp => ram_axi_full_rresp, ram_m_axi_rlast => ram_axi_full_rlast, ram_m_axi_rvalid => ram_axi_full_rvalid, ram_m_axi_rready => ram_axi_full_rready, int_m_axi_awid => int_axi_full_awid, int_m_axi_awaddr => int_axi_full_awaddr, int_m_axi_awlen => int_axi_full_awlen, int_m_axi_awsize => int_axi_full_awsize, int_m_axi_awburst => int_axi_full_awburst, int_m_axi_awlock => int_axi_full_awlock, int_m_axi_awcache => int_axi_full_awcache, int_m_axi_awprot => int_axi_full_awprot, int_m_axi_awqos => int_axi_full_awqos, int_m_axi_awregion => int_axi_full_awregion, int_m_axi_awvalid => int_axi_full_awvalid, int_m_axi_awready => int_axi_full_awready, int_m_axi_wdata => int_axi_full_wdata, int_m_axi_wstrb => int_axi_full_wstrb, int_m_axi_wlast => int_axi_full_wlast, int_m_axi_wvalid => int_axi_full_wvalid, int_m_axi_wready => int_axi_full_wready, int_m_axi_bid => int_axi_full_bid, int_m_axi_bresp => int_axi_full_bresp, int_m_axi_bvalid => int_axi_full_bvalid, int_m_axi_bready => int_axi_full_bready, int_m_axi_arid => int_axi_full_arid, int_m_axi_araddr => int_axi_full_araddr, int_m_axi_arlen => int_axi_full_arlen, int_m_axi_arsize => int_axi_full_arsize, int_m_axi_arburst => int_axi_full_arburst, int_m_axi_arlock => int_axi_full_arlock, int_m_axi_arcache => int_axi_full_arcache, int_m_axi_arprot => int_axi_full_arprot, int_m_axi_arqos => int_axi_full_arqos, int_m_axi_arregion => int_axi_full_arregion, int_m_axi_arvalid => int_axi_full_arvalid, int_m_axi_arready => int_axi_full_arready, int_m_axi_rid => int_axi_full_rid, int_m_axi_rdata => int_axi_full_rdata, int_m_axi_rresp => int_axi_full_rresp, int_m_axi_rlast => int_axi_full_rlast, int_m_axi_rvalid => int_axi_full_rvalid, int_m_axi_rready => int_axi_full_rready, timer_m_axi_awid => timer_axi_full_awid, timer_m_axi_awaddr => timer_axi_full_awaddr, timer_m_axi_awlen => timer_axi_full_awlen, timer_m_axi_awsize => timer_axi_full_awsize, timer_m_axi_awburst => timer_axi_full_awburst, timer_m_axi_awlock => timer_axi_full_awlock, timer_m_axi_awcache => timer_axi_full_awcache, timer_m_axi_awprot => timer_axi_full_awprot, timer_m_axi_awqos => timer_axi_full_awqos, timer_m_axi_awregion => timer_axi_full_awregion, timer_m_axi_awvalid => timer_axi_full_awvalid, timer_m_axi_awready => timer_axi_full_awready, timer_m_axi_wdata => timer_axi_full_wdata, timer_m_axi_wstrb => timer_axi_full_wstrb, timer_m_axi_wlast => timer_axi_full_wlast, timer_m_axi_wvalid => timer_axi_full_wvalid, timer_m_axi_wready => timer_axi_full_wready, timer_m_axi_bid => timer_axi_full_bid, timer_m_axi_bresp => timer_axi_full_bresp, timer_m_axi_bvalid => timer_axi_full_bvalid, timer_m_axi_bready => timer_axi_full_bready, timer_m_axi_arid => timer_axi_full_arid, timer_m_axi_araddr => timer_axi_full_araddr, timer_m_axi_arlen => timer_axi_full_arlen, timer_m_axi_arsize => timer_axi_full_arsize, timer_m_axi_arburst => timer_axi_full_arburst, timer_m_axi_arlock => timer_axi_full_arlock, timer_m_axi_arcache => timer_axi_full_arcache, timer_m_axi_arprot => timer_axi_full_arprot, timer_m_axi_arqos => timer_axi_full_arqos, timer_m_axi_arregion => timer_axi_full_arregion, timer_m_axi_arvalid => timer_axi_full_arvalid, timer_m_axi_arready => timer_axi_full_arready, timer_m_axi_rid => timer_axi_full_rid, timer_m_axi_rdata => timer_axi_full_rdata, timer_m_axi_rresp => timer_axi_full_rresp, timer_m_axi_rlast => timer_axi_full_rlast, timer_m_axi_rvalid => timer_axi_full_rvalid, timer_m_axi_rready => timer_axi_full_rready, gpio_m_axi_awid => gpio_axi_full_awid, gpio_m_axi_awaddr => gpio_axi_full_awaddr, gpio_m_axi_awlen => gpio_axi_full_awlen, gpio_m_axi_awsize => gpio_axi_full_awsize, gpio_m_axi_awburst => gpio_axi_full_awburst, gpio_m_axi_awlock => gpio_axi_full_awlock, gpio_m_axi_awcache => gpio_axi_full_awcache, gpio_m_axi_awprot => gpio_axi_full_awprot, gpio_m_axi_awqos => gpio_axi_full_awqos, gpio_m_axi_awregion => gpio_axi_full_awregion, gpio_m_axi_awvalid => gpio_axi_full_awvalid, gpio_m_axi_awready => gpio_axi_full_awready, gpio_m_axi_wdata => gpio_axi_full_wdata, gpio_m_axi_wstrb => gpio_axi_full_wstrb, gpio_m_axi_wlast => gpio_axi_full_wlast, gpio_m_axi_wvalid => gpio_axi_full_wvalid, gpio_m_axi_wready => gpio_axi_full_wready, gpio_m_axi_bid => gpio_axi_full_bid, gpio_m_axi_bresp => gpio_axi_full_bresp, gpio_m_axi_bvalid => gpio_axi_full_bvalid, gpio_m_axi_bready => gpio_axi_full_bready, gpio_m_axi_arid => gpio_axi_full_arid, gpio_m_axi_araddr => gpio_axi_full_araddr, gpio_m_axi_arlen => gpio_axi_full_arlen, gpio_m_axi_arsize => gpio_axi_full_arsize, gpio_m_axi_arburst => gpio_axi_full_arburst, gpio_m_axi_arlock => gpio_axi_full_arlock, gpio_m_axi_arcache => gpio_axi_full_arcache, gpio_m_axi_arprot => gpio_axi_full_arprot, gpio_m_axi_arqos => gpio_axi_full_arqos, gpio_m_axi_arregion => gpio_axi_full_arregion, gpio_m_axi_arvalid => gpio_axi_full_arvalid, gpio_m_axi_arready => gpio_axi_full_arready, gpio_m_axi_rid => gpio_axi_full_rid, gpio_m_axi_rdata => gpio_axi_full_rdata, gpio_m_axi_rresp => gpio_axi_full_rresp, gpio_m_axi_rlast => gpio_axi_full_rlast, gpio_m_axi_rvalid => gpio_axi_full_rvalid, gpio_m_axi_rready => gpio_axi_full_rready, cdma_m_axi_awid => cdmareg_axi_full_awid, cdma_m_axi_awaddr => cdmareg_axi_full_awaddr, cdma_m_axi_awlen => cdmareg_axi_full_awlen, cdma_m_axi_awsize => cdmareg_axi_full_awsize, cdma_m_axi_awburst => cdmareg_axi_full_awburst, cdma_m_axi_awlock => cdmareg_axi_full_awlock, cdma_m_axi_awcache => cdmareg_axi_full_awcache, cdma_m_axi_awprot => cdmareg_axi_full_awprot, cdma_m_axi_awqos => cdmareg_axi_full_awqos, cdma_m_axi_awregion => cdmareg_axi_full_awregion, cdma_m_axi_awvalid => cdmareg_axi_full_awvalid, cdma_m_axi_awready => cdmareg_axi_full_awready, cdma_m_axi_wdata => cdmareg_axi_full_wdata, cdma_m_axi_wstrb => cdmareg_axi_full_wstrb, cdma_m_axi_wlast => cdmareg_axi_full_wlast, cdma_m_axi_wvalid => cdmareg_axi_full_wvalid, cdma_m_axi_wready => cdmareg_axi_full_wready, cdma_m_axi_bid => cdmareg_axi_full_bid, cdma_m_axi_bresp => cdmareg_axi_full_bresp, cdma_m_axi_bvalid => cdmareg_axi_full_bvalid, cdma_m_axi_bready => cdmareg_axi_full_bready, cdma_m_axi_arid => cdmareg_axi_full_arid, cdma_m_axi_araddr => cdmareg_axi_full_araddr, cdma_m_axi_arlen => cdmareg_axi_full_arlen, cdma_m_axi_arsize => cdmareg_axi_full_arsize, cdma_m_axi_arburst => cdmareg_axi_full_arburst, cdma_m_axi_arlock => cdmareg_axi_full_arlock, cdma_m_axi_arcache => cdmareg_axi_full_arcache, cdma_m_axi_arprot => cdmareg_axi_full_arprot, cdma_m_axi_arqos => cdmareg_axi_full_arqos, cdma_m_axi_arregion => cdmareg_axi_full_arregion, cdma_m_axi_arvalid => cdmareg_axi_full_arvalid, cdma_m_axi_arready => cdmareg_axi_full_arready, cdma_m_axi_rid => cdmareg_axi_full_rid, cdma_m_axi_rdata => cdmareg_axi_full_rdata, cdma_m_axi_rresp => cdmareg_axi_full_rresp, cdma_m_axi_rlast => cdmareg_axi_full_rlast, cdma_m_axi_rvalid => cdmareg_axi_full_rvalid, cdma_m_axi_rready => cdmareg_axi_full_rready, uart_m_axi_awid => uart_axi_full_awid, uart_m_axi_awaddr => uart_axi_full_awaddr, uart_m_axi_awlen => uart_axi_full_awlen, uart_m_axi_awsize => uart_axi_full_awsize, uart_m_axi_awburst => uart_axi_full_awburst, uart_m_axi_awlock => uart_axi_full_awlock, uart_m_axi_awcache => uart_axi_full_awcache, uart_m_axi_awprot => uart_axi_full_awprot, uart_m_axi_awqos => uart_axi_full_awqos, uart_m_axi_awregion => uart_axi_full_awregion, uart_m_axi_awvalid => uart_axi_full_awvalid, uart_m_axi_awready => uart_axi_full_awready, uart_m_axi_wdata => uart_axi_full_wdata, uart_m_axi_wstrb => uart_axi_full_wstrb, uart_m_axi_wlast => uart_axi_full_wlast, uart_m_axi_wvalid => uart_axi_full_wvalid, uart_m_axi_wready => uart_axi_full_wready, uart_m_axi_bid => uart_axi_full_bid, uart_m_axi_bresp => uart_axi_full_bresp, uart_m_axi_bvalid => uart_axi_full_bvalid, uart_m_axi_bready => uart_axi_full_bready, uart_m_axi_arid => uart_axi_full_arid, uart_m_axi_araddr => uart_axi_full_araddr, uart_m_axi_arlen => uart_axi_full_arlen, uart_m_axi_arsize => uart_axi_full_arsize, uart_m_axi_arburst => uart_axi_full_arburst, uart_m_axi_arlock => uart_axi_full_arlock, uart_m_axi_arcache => uart_axi_full_arcache, uart_m_axi_arprot => uart_axi_full_arprot, uart_m_axi_arqos => uart_axi_full_arqos, uart_m_axi_arregion => uart_axi_full_arregion, uart_m_axi_arvalid => uart_axi_full_arvalid, uart_m_axi_arready => uart_axi_full_arready, uart_m_axi_rid => uart_axi_full_rid, uart_m_axi_rdata => uart_axi_full_rdata, uart_m_axi_rresp => uart_axi_full_rresp, uart_m_axi_rlast => uart_axi_full_rlast, uart_m_axi_rvalid => uart_axi_full_rvalid, uart_m_axi_rready => uart_axi_full_rready, timer_extra_0_m_axi_awid => timer_extra_0_axi_full_awid, timer_extra_0_m_axi_awaddr => timer_extra_0_axi_full_awaddr, timer_extra_0_m_axi_awlen => timer_extra_0_axi_full_awlen, timer_extra_0_m_axi_awsize => timer_extra_0_axi_full_awsize, timer_extra_0_m_axi_awburst => timer_extra_0_axi_full_awburst, timer_extra_0_m_axi_awlock => timer_extra_0_axi_full_awlock, timer_extra_0_m_axi_awcache => timer_extra_0_axi_full_awcache, timer_extra_0_m_axi_awprot => timer_extra_0_axi_full_awprot, timer_extra_0_m_axi_awqos => timer_extra_0_axi_full_awqos, timer_extra_0_m_axi_awregion => timer_extra_0_axi_full_awregion, timer_extra_0_m_axi_awvalid => timer_extra_0_axi_full_awvalid, timer_extra_0_m_axi_awready => timer_extra_0_axi_full_awready, timer_extra_0_m_axi_wdata => timer_extra_0_axi_full_wdata, timer_extra_0_m_axi_wstrb => timer_extra_0_axi_full_wstrb, timer_extra_0_m_axi_wlast => timer_extra_0_axi_full_wlast, timer_extra_0_m_axi_wvalid => timer_extra_0_axi_full_wvalid, timer_extra_0_m_axi_wready => timer_extra_0_axi_full_wready, timer_extra_0_m_axi_bid => timer_extra_0_axi_full_bid, timer_extra_0_m_axi_bresp => timer_extra_0_axi_full_bresp, timer_extra_0_m_axi_bvalid => timer_extra_0_axi_full_bvalid, timer_extra_0_m_axi_bready => timer_extra_0_axi_full_bready, timer_extra_0_m_axi_arid => timer_extra_0_axi_full_arid, timer_extra_0_m_axi_araddr => timer_extra_0_axi_full_araddr, timer_extra_0_m_axi_arlen => timer_extra_0_axi_full_arlen, timer_extra_0_m_axi_arsize => timer_extra_0_axi_full_arsize, timer_extra_0_m_axi_arburst => timer_extra_0_axi_full_arburst, timer_extra_0_m_axi_arlock => timer_extra_0_axi_full_arlock, timer_extra_0_m_axi_arcache => timer_extra_0_axi_full_arcache, timer_extra_0_m_axi_arprot => timer_extra_0_axi_full_arprot, timer_extra_0_m_axi_arqos => timer_extra_0_axi_full_arqos, timer_extra_0_m_axi_arregion => timer_extra_0_axi_full_arregion, timer_extra_0_m_axi_arvalid => timer_extra_0_axi_full_arvalid, timer_extra_0_m_axi_arready => timer_extra_0_axi_full_arready, timer_extra_0_m_axi_rid => timer_extra_0_axi_full_rid, timer_extra_0_m_axi_rdata => timer_extra_0_axi_full_rdata, timer_extra_0_m_axi_rresp => timer_extra_0_axi_full_rresp, timer_extra_0_m_axi_rlast => timer_extra_0_axi_full_rlast, timer_extra_0_m_axi_rvalid => timer_extra_0_axi_full_rvalid, timer_extra_0_m_axi_rready => timer_extra_0_axi_full_rready, aclk => aclk, aresetn => cross_aresetn(0)); plasoc_cpu_inst : plasoc_cpu port map ( aclk => aclk, aresetn => aresetn(0), intr_in => cpu_int, axi_awid => cpu_axi_full_awid, axi_awaddr => cpu_axi_full_awaddr, axi_awlen => cpu_axi_full_awlen, axi_awsize => cpu_axi_full_awsize, axi_awburst => cpu_axi_full_awburst, axi_awlock => cpu_axi_full_awlock, axi_awcache => cpu_axi_full_awcache, axi_awprot => cpu_axi_full_awprot, axi_awqos => cpu_axi_full_awqos, axi_awregion => cpu_axi_full_awregion, axi_awvalid => cpu_axi_full_awvalid, axi_awready => cpu_axi_full_awready, axi_wdata => cpu_axi_full_wdata, axi_wstrb => cpu_axi_full_wstrb, axi_wlast => cpu_axi_full_wlast, axi_wvalid => cpu_axi_full_wvalid, axi_wready => cpu_axi_full_wready, axi_bid => cpu_axi_full_bid, axi_bresp => cpu_axi_full_bresp, axi_bvalid => cpu_axi_full_bvalid, axi_bready => cpu_axi_full_bready, axi_arid => cpu_axi_full_arid, axi_araddr => cpu_axi_full_araddr, axi_arlen => cpu_axi_full_arlen, axi_arsize => cpu_axi_full_arsize, axi_arburst => cpu_axi_full_arburst, axi_arlock => cpu_axi_full_arlock, axi_arcache => cpu_axi_full_arcache, axi_arprot => cpu_axi_full_arprot, axi_arqos => cpu_axi_full_arqos, axi_arregion => cpu_axi_full_arregion, axi_arvalid => cpu_axi_full_arvalid, axi_arready => cpu_axi_full_arready, axi_rid => cpu_axi_full_rid, axi_rdata => cpu_axi_full_rdata, axi_rresp => cpu_axi_full_rresp, axi_rlast => cpu_axi_full_rlast, axi_rvalid => cpu_axi_full_rvalid, axi_rready => cpu_axi_full_rready); int_full2lite_inst : plasoc_axi4_full2lite generic map ( axi_slave_id_width => axi_master_id_width, axi_address_width => axi_lite_address_width, axi_data_width => axi_data_width) port map ( aclk => aclk, aresetn => aresetn(0), s_axi_awid => int_axi_full_awid, s_axi_awaddr => int_axi_full_awaddr(axi_lite_address_width-1 downto 0), s_axi_awlen => int_axi_full_awlen, s_axi_awsize => int_axi_full_awsize, s_axi_awburst => int_axi_full_awburst, s_axi_awlock => int_axi_full_awlock, s_axi_awcache => int_axi_full_awcache, s_axi_awprot => int_axi_full_awprot, s_axi_awqos => int_axi_full_awqos, s_axi_awregion => int_axi_full_awregion, s_axi_awvalid => int_axi_full_awvalid, s_axi_awready => int_axi_full_awready, s_axi_wdata => int_axi_full_wdata, s_axi_wstrb => int_axi_full_wstrb, s_axi_wlast => int_axi_full_wlast, s_axi_wvalid => int_axi_full_wvalid, s_axi_wready => int_axi_full_wready, s_axi_bid => int_axi_full_bid, s_axi_bresp => int_axi_full_bresp, s_axi_bvalid => int_axi_full_bvalid, s_axi_bready => int_axi_full_bready, s_axi_arid => int_axi_full_arid, s_axi_araddr => int_axi_full_araddr(axi_lite_address_width-1 downto 0), s_axi_arlen => int_axi_full_arlen, s_axi_arsize => int_axi_full_arsize, s_axi_arburst => int_axi_full_arburst, s_axi_arlock => int_axi_full_arlock, s_axi_arcache => int_axi_full_arcache, s_axi_arprot => int_axi_full_arprot, s_axi_arqos => int_axi_full_arqos, s_axi_arregion => int_axi_full_arregion, s_axi_arvalid => int_axi_full_arvalid, s_axi_arready => int_axi_full_arready, s_axi_rid => int_axi_full_rid, s_axi_rdata => int_axi_full_rdata, s_axi_rresp => int_axi_full_rresp, s_axi_rlast => int_axi_full_rlast, s_axi_rvalid => int_axi_full_rvalid, s_axi_rready => int_axi_full_rready, m_axi_awaddr => int_axi_lite_awaddr, m_axi_awprot => int_axi_lite_awprot, m_axi_awvalid => int_axi_lite_awvalid, m_axi_awready => int_axi_lite_awready, m_axi_wvalid => int_axi_lite_wvalid, m_axi_wready => int_axi_lite_wready, m_axi_wdata => int_axi_lite_wdata, m_axi_wstrb => int_axi_lite_wstrb, m_axi_bvalid => int_axi_lite_bvalid, m_axi_bready => int_axi_lite_bready, m_axi_bresp => int_axi_lite_bresp, m_axi_araddr => int_axi_lite_araddr, m_axi_arprot => int_axi_lite_arprot, m_axi_arvalid => int_axi_lite_arvalid, m_axi_arready => int_axi_lite_arready, m_axi_rdata => int_axi_lite_rdata, m_axi_rvalid => int_axi_lite_rvalid, m_axi_rready => int_axi_lite_rready, m_axi_rresp => int_axi_lite_rresp); timer_full2lite_inst : plasoc_axi4_full2lite generic map ( axi_slave_id_width => axi_master_id_width, axi_address_width => axi_lite_address_width, axi_data_width => axi_data_width) port map ( aclk => aclk, aresetn => aresetn(0), s_axi_awid => timer_axi_full_awid, s_axi_awaddr => timer_axi_full_awaddr(axi_lite_address_width-1 downto 0), s_axi_awlen => timer_axi_full_awlen, s_axi_awsize => timer_axi_full_awsize, s_axi_awburst => timer_axi_full_awburst, s_axi_awlock => timer_axi_full_awlock, s_axi_awcache => timer_axi_full_awcache, s_axi_awprot => timer_axi_full_awprot, s_axi_awqos => timer_axi_full_awqos, s_axi_awregion => timer_axi_full_awregion, s_axi_awvalid => timer_axi_full_awvalid, s_axi_awready => timer_axi_full_awready, s_axi_wdata => timer_axi_full_wdata, s_axi_wstrb => timer_axi_full_wstrb, s_axi_wlast => timer_axi_full_wlast, s_axi_wvalid => timer_axi_full_wvalid, s_axi_wready => timer_axi_full_wready, s_axi_bid => timer_axi_full_bid, s_axi_bresp => timer_axi_full_bresp, s_axi_bvalid => timer_axi_full_bvalid, s_axi_bready => timer_axi_full_bready, s_axi_arid => timer_axi_full_arid, s_axi_araddr => timer_axi_full_araddr(axi_lite_address_width-1 downto 0), s_axi_arlen => timer_axi_full_arlen, s_axi_arsize => timer_axi_full_arsize, s_axi_arburst => timer_axi_full_arburst, s_axi_arlock => timer_axi_full_arlock, s_axi_arcache => timer_axi_full_arcache, s_axi_arprot => timer_axi_full_arprot, s_axi_arqos => timer_axi_full_arqos, s_axi_arregion => timer_axi_full_arregion, s_axi_arvalid => timer_axi_full_arvalid, s_axi_arready => timer_axi_full_arready, s_axi_rid => timer_axi_full_rid, s_axi_rdata => timer_axi_full_rdata, s_axi_rresp => timer_axi_full_rresp, s_axi_rlast => timer_axi_full_rlast, s_axi_rvalid => timer_axi_full_rvalid, s_axi_rready => timer_axi_full_rready, m_axi_awaddr => timer_axi_lite_awaddr, m_axi_awprot => timer_axi_lite_awprot, m_axi_awvalid => timer_axi_lite_awvalid, m_axi_awready => timer_axi_lite_awready, m_axi_wvalid => timer_axi_lite_wvalid, m_axi_wready => timer_axi_lite_wready, m_axi_wdata => timer_axi_lite_wdata, m_axi_wstrb => timer_axi_lite_wstrb, m_axi_bvalid => timer_axi_lite_bvalid, m_axi_bready => timer_axi_lite_bready, m_axi_bresp => timer_axi_lite_bresp, m_axi_araddr => timer_axi_lite_araddr, m_axi_arprot => timer_axi_lite_arprot, m_axi_arvalid => timer_axi_lite_arvalid, m_axi_arready => timer_axi_lite_arready, m_axi_rdata => timer_axi_lite_rdata, m_axi_rvalid => timer_axi_lite_rvalid, m_axi_rready => timer_axi_lite_rready, m_axi_rresp => timer_axi_lite_rresp); gpio_full2lite_inst : plasoc_axi4_full2lite generic map ( axi_slave_id_width => axi_master_id_width, axi_address_width => axi_lite_address_width, axi_data_width => axi_data_width) port map ( aclk => aclk, aresetn => aresetn(0), s_axi_awid => gpio_axi_full_awid, s_axi_awaddr => gpio_axi_full_awaddr(axi_lite_address_width-1 downto 0), s_axi_awlen => gpio_axi_full_awlen, s_axi_awsize => gpio_axi_full_awsize, s_axi_awburst => gpio_axi_full_awburst, s_axi_awlock => gpio_axi_full_awlock, s_axi_awcache => gpio_axi_full_awcache, s_axi_awprot => gpio_axi_full_awprot, s_axi_awqos => gpio_axi_full_awqos, s_axi_awregion => gpio_axi_full_awregion, s_axi_awvalid => gpio_axi_full_awvalid, s_axi_awready => gpio_axi_full_awready, s_axi_wdata => gpio_axi_full_wdata, s_axi_wstrb => gpio_axi_full_wstrb, s_axi_wlast => gpio_axi_full_wlast, s_axi_wvalid => gpio_axi_full_wvalid, s_axi_wready => gpio_axi_full_wready, s_axi_bid => gpio_axi_full_bid, s_axi_bresp => gpio_axi_full_bresp, s_axi_bvalid => gpio_axi_full_bvalid, s_axi_bready => gpio_axi_full_bready, s_axi_arid => gpio_axi_full_arid, s_axi_araddr => gpio_axi_full_araddr(axi_lite_address_width-1 downto 0), s_axi_arlen => gpio_axi_full_arlen, s_axi_arsize => gpio_axi_full_arsize, s_axi_arburst => gpio_axi_full_arburst, s_axi_arlock => gpio_axi_full_arlock, s_axi_arcache => gpio_axi_full_arcache, s_axi_arprot => gpio_axi_full_arprot, s_axi_arqos => gpio_axi_full_arqos, s_axi_arregion => gpio_axi_full_arregion, s_axi_arvalid => gpio_axi_full_arvalid, s_axi_arready => gpio_axi_full_arready, s_axi_rid => gpio_axi_full_rid, s_axi_rdata => gpio_axi_full_rdata, s_axi_rresp => gpio_axi_full_rresp, s_axi_rlast => gpio_axi_full_rlast, s_axi_rvalid => gpio_axi_full_rvalid, s_axi_rready => gpio_axi_full_rready, m_axi_awaddr => gpio_axi_lite_awaddr, m_axi_awprot => gpio_axi_lite_awprot, m_axi_awvalid => gpio_axi_lite_awvalid, m_axi_awready => gpio_axi_lite_awready, m_axi_wvalid => gpio_axi_lite_wvalid, m_axi_wready => gpio_axi_lite_wready, m_axi_wdata => gpio_axi_lite_wdata, m_axi_wstrb => gpio_axi_lite_wstrb, m_axi_bvalid => gpio_axi_lite_bvalid, m_axi_bready => gpio_axi_lite_bready, m_axi_bresp => gpio_axi_lite_bresp, m_axi_araddr => gpio_axi_lite_araddr, m_axi_arprot => gpio_axi_lite_arprot, m_axi_arvalid => gpio_axi_lite_arvalid, m_axi_arready => gpio_axi_lite_arready, m_axi_rdata => gpio_axi_lite_rdata, m_axi_rvalid => gpio_axi_lite_rvalid, m_axi_rready => gpio_axi_lite_rready, m_axi_rresp => gpio_axi_lite_rresp); cdmareg_full2lite_inst : plasoc_axi4_full2lite generic map ( axi_slave_id_width => axi_master_id_width, axi_address_width => axi_lite_address_width, axi_data_width => axi_data_width) port map ( aclk => aclk, aresetn => aresetn(0), s_axi_awid => cdmareg_axi_full_awid, s_axi_awaddr => cdmareg_axi_full_awaddr(axi_lite_address_width-1 downto 0), s_axi_awlen => cdmareg_axi_full_awlen, s_axi_awsize => cdmareg_axi_full_awsize, s_axi_awburst => cdmareg_axi_full_awburst, s_axi_awlock => cdmareg_axi_full_awlock, s_axi_awcache => cdmareg_axi_full_awcache, s_axi_awprot => cdmareg_axi_full_awprot, s_axi_awqos => cdmareg_axi_full_awqos, s_axi_awregion => cdmareg_axi_full_awregion, s_axi_awvalid => cdmareg_axi_full_awvalid, s_axi_awready => cdmareg_axi_full_awready, s_axi_wdata => cdmareg_axi_full_wdata, s_axi_wstrb => cdmareg_axi_full_wstrb, s_axi_wlast => cdmareg_axi_full_wlast, s_axi_wvalid => cdmareg_axi_full_wvalid, s_axi_wready => cdmareg_axi_full_wready, s_axi_bid => cdmareg_axi_full_bid, s_axi_bresp => cdmareg_axi_full_bresp, s_axi_bvalid => cdmareg_axi_full_bvalid, s_axi_bready => cdmareg_axi_full_bready, s_axi_arid => cdmareg_axi_full_arid, s_axi_araddr => cdmareg_axi_full_araddr(axi_lite_address_width-1 downto 0), s_axi_arlen => cdmareg_axi_full_arlen, s_axi_arsize => cdmareg_axi_full_arsize, s_axi_arburst => cdmareg_axi_full_arburst, s_axi_arlock => cdmareg_axi_full_arlock, s_axi_arcache => cdmareg_axi_full_arcache, s_axi_arprot => cdmareg_axi_full_arprot, s_axi_arqos => cdmareg_axi_full_arqos, s_axi_arregion => cdmareg_axi_full_arregion, s_axi_arvalid => cdmareg_axi_full_arvalid, s_axi_arready => cdmareg_axi_full_arready, s_axi_rid => cdmareg_axi_full_rid, s_axi_rdata => cdmareg_axi_full_rdata, s_axi_rresp => cdmareg_axi_full_rresp, s_axi_rlast => cdmareg_axi_full_rlast, s_axi_rvalid => cdmareg_axi_full_rvalid, s_axi_rready => cdmareg_axi_full_rready, m_axi_awaddr => cdmareg_axi_lite_awaddr, m_axi_awprot => cdmareg_axi_lite_awprot, m_axi_awvalid => cdmareg_axi_lite_awvalid, m_axi_awready => cdmareg_axi_lite_awready, m_axi_wvalid => cdmareg_axi_lite_wvalid, m_axi_wready => cdmareg_axi_lite_wready, m_axi_wdata => cdmareg_axi_lite_wdata, m_axi_wstrb => cdmareg_axi_lite_wstrb, m_axi_bvalid => cdmareg_axi_lite_bvalid, m_axi_bready => cdmareg_axi_lite_bready, m_axi_bresp => cdmareg_axi_lite_bresp, m_axi_araddr => cdmareg_axi_lite_araddr, m_axi_arprot => cdmareg_axi_lite_arprot, m_axi_arvalid => cdmareg_axi_lite_arvalid, m_axi_arready => cdmareg_axi_lite_arready, m_axi_rdata => cdmareg_axi_lite_rdata, m_axi_rvalid => cdmareg_axi_lite_rvalid, m_axi_rready => cdmareg_axi_lite_rready, m_axi_rresp => cdmareg_axi_lite_rresp); uart_full2lite_inst : plasoc_axi4_full2lite generic map ( axi_slave_id_width => axi_master_id_width, axi_address_width => axi_lite_address_width, axi_data_width => axi_data_width) port map ( aclk => aclk, aresetn => aresetn(0), s_axi_awid => uart_axi_full_awid, s_axi_awaddr => uart_axi_full_awaddr(axi_lite_address_width-1 downto 0), s_axi_awlen => uart_axi_full_awlen, s_axi_awsize => uart_axi_full_awsize, s_axi_awburst => uart_axi_full_awburst, s_axi_awlock => uart_axi_full_awlock, s_axi_awcache => uart_axi_full_awcache, s_axi_awprot => uart_axi_full_awprot, s_axi_awqos => uart_axi_full_awqos, s_axi_awregion => uart_axi_full_awregion, s_axi_awvalid => uart_axi_full_awvalid, s_axi_awready => uart_axi_full_awready, s_axi_wdata => uart_axi_full_wdata, s_axi_wstrb => uart_axi_full_wstrb, s_axi_wlast => uart_axi_full_wlast, s_axi_wvalid => uart_axi_full_wvalid, s_axi_wready => uart_axi_full_wready, s_axi_bid => uart_axi_full_bid, s_axi_bresp => uart_axi_full_bresp, s_axi_bvalid => uart_axi_full_bvalid, s_axi_bready => uart_axi_full_bready, s_axi_arid => uart_axi_full_arid, s_axi_araddr => uart_axi_full_araddr(axi_lite_address_width-1 downto 0), s_axi_arlen => uart_axi_full_arlen, s_axi_arsize => uart_axi_full_arsize, s_axi_arburst => uart_axi_full_arburst, s_axi_arlock => uart_axi_full_arlock, s_axi_arcache => uart_axi_full_arcache, s_axi_arprot => uart_axi_full_arprot, s_axi_arqos => uart_axi_full_arqos, s_axi_arregion => uart_axi_full_arregion, s_axi_arvalid => uart_axi_full_arvalid, s_axi_arready => uart_axi_full_arready, s_axi_rid => uart_axi_full_rid, s_axi_rdata => uart_axi_full_rdata, s_axi_rresp => uart_axi_full_rresp, s_axi_rlast => uart_axi_full_rlast, s_axi_rvalid => uart_axi_full_rvalid, s_axi_rready => uart_axi_full_rready, m_axi_awaddr => uart_axi_lite_awaddr, m_axi_awprot => uart_axi_lite_awprot, m_axi_awvalid => uart_axi_lite_awvalid, m_axi_awready => uart_axi_lite_awready, m_axi_wvalid => uart_axi_lite_wvalid, m_axi_wready => uart_axi_lite_wready, m_axi_wdata => uart_axi_lite_wdata, m_axi_wstrb => uart_axi_lite_wstrb, m_axi_bvalid => uart_axi_lite_bvalid, m_axi_bready => uart_axi_lite_bready, m_axi_bresp => uart_axi_lite_bresp, m_axi_araddr => uart_axi_lite_araddr, m_axi_arprot => uart_axi_lite_arprot, m_axi_arvalid => uart_axi_lite_arvalid, m_axi_arready => uart_axi_lite_arready, m_axi_rdata => uart_axi_lite_rdata, m_axi_rvalid => uart_axi_lite_rvalid, m_axi_rready => uart_axi_lite_rready, m_axi_rresp => uart_axi_lite_rresp); timer_extra_0_full2lite_inst : plasoc_axi4_full2lite generic map ( axi_slave_id_width => axi_master_id_width, axi_address_width => axi_lite_address_width, axi_data_width => axi_data_width) port map ( aclk => aclk, aresetn => aresetn(0), s_axi_awid => timer_extra_0_axi_full_awid, s_axi_awaddr => timer_extra_0_axi_full_awaddr(axi_lite_address_width-1 downto 0), s_axi_awlen => timer_extra_0_axi_full_awlen, s_axi_awsize => timer_extra_0_axi_full_awsize, s_axi_awburst => timer_extra_0_axi_full_awburst, s_axi_awlock => timer_extra_0_axi_full_awlock, s_axi_awcache => timer_extra_0_axi_full_awcache, s_axi_awprot => timer_extra_0_axi_full_awprot, s_axi_awqos => timer_extra_0_axi_full_awqos, s_axi_awregion => timer_extra_0_axi_full_awregion, s_axi_awvalid => timer_extra_0_axi_full_awvalid, s_axi_awready => timer_extra_0_axi_full_awready, s_axi_wdata => timer_extra_0_axi_full_wdata, s_axi_wstrb => timer_extra_0_axi_full_wstrb, s_axi_wlast => timer_extra_0_axi_full_wlast, s_axi_wvalid => timer_extra_0_axi_full_wvalid, s_axi_wready => timer_extra_0_axi_full_wready, s_axi_bid => timer_extra_0_axi_full_bid, s_axi_bresp => timer_extra_0_axi_full_bresp, s_axi_bvalid => timer_extra_0_axi_full_bvalid, s_axi_bready => timer_extra_0_axi_full_bready, s_axi_arid => timer_extra_0_axi_full_arid, s_axi_araddr => timer_extra_0_axi_full_araddr(axi_lite_address_width-1 downto 0), s_axi_arlen => timer_extra_0_axi_full_arlen, s_axi_arsize => timer_extra_0_axi_full_arsize, s_axi_arburst => timer_extra_0_axi_full_arburst, s_axi_arlock => timer_extra_0_axi_full_arlock, s_axi_arcache => timer_extra_0_axi_full_arcache, s_axi_arprot => timer_extra_0_axi_full_arprot, s_axi_arqos => timer_extra_0_axi_full_arqos, s_axi_arregion => timer_extra_0_axi_full_arregion, s_axi_arvalid => timer_extra_0_axi_full_arvalid, s_axi_arready => timer_extra_0_axi_full_arready, s_axi_rid => timer_extra_0_axi_full_rid, s_axi_rdata => timer_extra_0_axi_full_rdata, s_axi_rresp => timer_extra_0_axi_full_rresp, s_axi_rlast => timer_extra_0_axi_full_rlast, s_axi_rvalid => timer_extra_0_axi_full_rvalid, s_axi_rready => timer_extra_0_axi_full_rready, m_axi_awaddr => timer_extra_0_axi_lite_awaddr, m_axi_awprot => timer_extra_0_axi_lite_awprot, m_axi_awvalid => timer_extra_0_axi_lite_awvalid, m_axi_awready => timer_extra_0_axi_lite_awready, m_axi_wvalid => timer_extra_0_axi_lite_wvalid, m_axi_wready => timer_extra_0_axi_lite_wready, m_axi_wdata => timer_extra_0_axi_lite_wdata, m_axi_wstrb => timer_extra_0_axi_lite_wstrb, m_axi_bvalid => timer_extra_0_axi_lite_bvalid, m_axi_bready => timer_extra_0_axi_lite_bready, m_axi_bresp => timer_extra_0_axi_lite_bresp, m_axi_araddr => timer_extra_0_axi_lite_araddr, m_axi_arprot => timer_extra_0_axi_lite_arprot, m_axi_arvalid => timer_extra_0_axi_lite_arvalid, m_axi_arready => timer_extra_0_axi_lite_arready, m_axi_rdata => timer_extra_0_axi_lite_rdata, m_axi_rvalid => timer_extra_0_axi_lite_rvalid, m_axi_rready => timer_extra_0_axi_lite_rready, m_axi_rresp => timer_extra_0_axi_lite_rresp); bram_cntrl_inst : axi_bram_ctrl_0 port map ( s_axi_aclk => aclk, s_axi_aresetn => aresetn(0), s_axi_awid => bram_axi_full_awid, s_axi_awaddr => bram_axi_full_awaddr(axi_lite_address_width-1 downto 0), s_axi_awlen => bram_axi_full_awlen, s_axi_awsize => bram_axi_full_awsize, s_axi_awburst => bram_axi_full_awburst, s_axi_awlock => bram_axi_full_awlock, s_axi_awcache => bram_axi_full_awcache, s_axi_awprot => bram_axi_full_awprot, s_axi_awvalid => bram_axi_full_awvalid, s_axi_awready => bram_axi_full_awready, s_axi_wdata => bram_axi_full_wdata, s_axi_wstrb => bram_axi_full_wstrb, s_axi_wlast => bram_axi_full_wlast, s_axi_wvalid => bram_axi_full_wvalid, s_axi_wready => bram_axi_full_wready, s_axi_bid => bram_axi_full_bid, s_axi_bresp => bram_axi_full_bresp, s_axi_bvalid => bram_axi_full_bvalid, s_axi_bready => bram_axi_full_bready, s_axi_arid => bram_axi_full_arid, s_axi_araddr => bram_axi_full_araddr(axi_lite_address_width-1 downto 0), s_axi_arlen => bram_axi_full_arlen, s_axi_arsize => bram_axi_full_arsize, s_axi_arburst => bram_axi_full_arburst, s_axi_arlock => bram_axi_full_arlock, s_axi_arcache => bram_axi_full_arcache, s_axi_arprot => bram_axi_full_arprot, s_axi_arvalid => bram_axi_full_arvalid, s_axi_arready => bram_axi_full_arready, s_axi_rid => bram_axi_full_rid, s_axi_rdata => bram_axi_full_rdata, s_axi_rresp => bram_axi_full_rresp, s_axi_rlast => bram_axi_full_rlast, s_axi_rvalid => bram_axi_full_rvalid, s_axi_rready => bram_axi_full_rready, bram_rst_a => bram_bram_rst_a, bram_clk_a => bram_bram_clk_a, bram_en_a => bram_bram_en_a, bram_we_a => bram_bram_we_a, bram_addr_a => bram_bram_addr_a, bram_wrdata_a => bram_bram_wrdata_a, bram_rddata_a => bram_bram_rddata_a); bram_inst : bram generic map ( select_app => lower_app, address_width => axi_lite_address_width, data_width => axi_data_width, bram_depth => 1024 ) port map ( bram_rst_a => bram_bram_rst_a, bram_clk_a => bram_bram_clk_a, bram_en_a => bram_bram_en_a, bram_we_a => bram_bram_we_a, bram_addr_a => bram_bram_addr_a, bram_wrdata_a => bram_bram_wrdata_a, bram_rddata_a => bram_bram_rddata_a); gen_int_mm : if upper_ext=false generate ram_cntrl_inst : axi_bram_ctrl_1 port map ( s_axi_aclk => aclk, s_axi_aresetn => aresetn(0), s_axi_awid => ram_axi_full_awid, s_axi_awaddr => ram_axi_full_awaddr(axi_ram_address_width-1 downto 0), s_axi_awlen => ram_axi_full_awlen, s_axi_awsize => ram_axi_full_awsize, s_axi_awburst => ram_axi_full_awburst, s_axi_awlock => ram_axi_full_awlock, s_axi_awcache => ram_axi_full_awcache, s_axi_awprot => ram_axi_full_awprot, s_axi_awvalid => ram_axi_full_awvalid, s_axi_awready => ram_axi_full_awready, s_axi_wdata => ram_axi_full_wdata, s_axi_wstrb => ram_axi_full_wstrb, s_axi_wlast => ram_axi_full_wlast, s_axi_wvalid => ram_axi_full_wvalid, s_axi_wready => ram_axi_full_wready, s_axi_bid => ram_axi_full_bid, s_axi_bresp => ram_axi_full_bresp, s_axi_bvalid => ram_axi_full_bvalid, s_axi_bready => ram_axi_full_bready, s_axi_arid => ram_axi_full_arid, s_axi_araddr => ram_axi_full_araddr(axi_ram_address_width-1 downto 0), s_axi_arlen => ram_axi_full_arlen, s_axi_arsize => ram_axi_full_arsize, s_axi_arburst => ram_axi_full_arburst, s_axi_arlock => ram_axi_full_arlock, s_axi_arcache => ram_axi_full_arcache, s_axi_arprot => ram_axi_full_arprot, s_axi_arvalid => ram_axi_full_arvalid, s_axi_arready => ram_axi_full_arready, s_axi_rid => ram_axi_full_rid, s_axi_rdata => ram_axi_full_rdata, s_axi_rresp => ram_axi_full_rresp, s_axi_rlast => ram_axi_full_rlast, s_axi_rvalid => ram_axi_full_rvalid, s_axi_rready => ram_axi_full_rready, bram_rst_a => ram_bram_rst_a, bram_clk_a => ram_bram_clk_a, bram_en_a => ram_bram_en_a, bram_we_a => ram_bram_we_a, bram_addr_a => ram_bram_addr_a, bram_wrdata_a => ram_bram_wrdata_a, bram_rddata_a => ram_bram_rddata_a); ram_inst : bram generic map ( select_app => upper_app, address_width => axi_ram_address_width, data_width => axi_data_width, bram_depth => axi_ram_depth) port map ( bram_rst_a => ram_bram_rst_a, bram_clk_a => ram_bram_clk_a, bram_en_a => ram_bram_en_a, bram_we_a => ram_bram_we_a, bram_addr_a => ram_bram_addr_a, bram_wrdata_a => ram_bram_wrdata_a, bram_rddata_a => ram_bram_rddata_a); end generate; gen_ext_mm : if upper_ext=true generate mig_wrap_wrapper_inst : mig_wrap_wrapper port map ( ACLK => aclk, ARESETN => cross_aresetn(0), DDR2_addr => DDR2_addr, DDR2_ba => DDR2_ba, DDR2_cas_n => DDR2_cas_n, DDR2_ck_n => DDR2_ck_n, DDR2_ck_p => DDR2_ck_p, DDR2_cke => DDR2_cke, DDR2_cs_n => DDR2_cs_n, DDR2_dm => DDR2_dm, DDR2_dq => DDR2_dq, DDR2_dqs_n => DDR2_dqs_n, DDR2_dqs_p => DDR2_dqs_p, DDR2_odt => DDR2_odt, DDR2_ras_n => DDR2_ras_n, DDR2_we_n => DDR2_we_n, S00_ARESETN => aresetn(0), S00_AXI_araddr => ram_axi_full_araddr, S00_AXI_arburst => ram_axi_full_arburst, S00_AXI_arcache => ram_axi_full_arcache, S00_AXI_arid => ram_axi_full_arid_slv, S00_AXI_arlen => ram_axi_full_arlen, S00_AXI_arlock => ram_axi_full_arlock_slv, S00_AXI_arprot => ram_axi_full_arprot, S00_AXI_arqos => ram_axi_full_arqos, S00_AXI_arready => ram_axi_full_arready, S00_AXI_arregion => ram_axi_full_arregion, S00_AXI_arsize => ram_axi_full_arsize, S00_AXI_arvalid => ram_axi_full_arvalid, S00_AXI_awaddr => ram_axi_full_awaddr, S00_AXI_awburst => ram_axi_full_awburst, S00_AXI_awcache => ram_axi_full_awcache, S00_AXI_awid => ram_axi_full_awid_slv, S00_AXI_awlen => ram_axi_full_awlen, S00_AXI_awlock => ram_axi_full_awlock_slv, S00_AXI_awprot => ram_axi_full_awprot, S00_AXI_awqos => ram_axi_full_awqos, S00_AXI_awready => ram_axi_full_awready, S00_AXI_awregion => ram_axi_full_awregion, S00_AXI_awsize => ram_axi_full_awsize, S00_AXI_awvalid => ram_axi_full_awvalid, S00_AXI_bid => ram_axi_full_bid_slv, S00_AXI_bready => ram_axi_full_bready, S00_AXI_bresp => ram_axi_full_bresp, S00_AXI_bvalid => ram_axi_full_bvalid, S00_AXI_rdata => ram_axi_full_rdata, S00_AXI_rid => ram_axi_full_rid_slv, S00_AXI_rlast => ram_axi_full_rlast, S00_AXI_rready => ram_axi_full_rready, S00_AXI_rresp => ram_axi_full_rresp, S00_AXI_rvalid => ram_axi_full_rvalid, S00_AXI_wdata => ram_axi_full_wdata, S00_AXI_wlast => ram_axi_full_wlast, S00_AXI_wready => ram_axi_full_wready, S00_AXI_wstrb => ram_axi_full_wstrb, S00_AXI_wvalid => ram_axi_full_wvalid, clk_ref_i => ddr_aclk, sys_rst => raw_nreset); end generate; plasoc_int_inst : plasoc_int generic map ( axi_address_width => axi_lite_address_width, axi_data_width => axi_data_width) port map ( aclk => aclk, aresetn => aresetn(0), cpu_int => cpu_int, dev_ints => int_dev_ints, axi_awaddr => int_axi_lite_awaddr, axi_awprot => int_axi_lite_awprot, axi_awvalid => int_axi_lite_awvalid, axi_awready => int_axi_lite_awready, axi_wvalid => int_axi_lite_wvalid, axi_wready => int_axi_lite_wready, axi_wdata => int_axi_lite_wdata, axi_wstrb => int_axi_lite_wstrb, axi_bvalid => int_axi_lite_bvalid, axi_bready => int_axi_lite_bready, axi_bresp => int_axi_lite_bresp, axi_araddr => int_axi_lite_araddr, axi_arprot => int_axi_lite_arprot, axi_arvalid => int_axi_lite_arvalid, axi_arready => int_axi_lite_arready, axi_rdata => int_axi_lite_rdata, axi_rvalid => int_axi_lite_rvalid, axi_rready => int_axi_lite_rready, axi_rresp => int_axi_lite_rresp); plasoc_timer_inst : plasoc_timer generic map ( axi_address_width => axi_lite_address_width, axi_data_width => axi_data_width) port map ( aclk => aclk, aresetn => aresetn(0), axi_awaddr => timer_axi_lite_awaddr, axi_awprot => timer_axi_lite_awprot, axi_awvalid => timer_axi_lite_awvalid, axi_awready => timer_axi_lite_awready, axi_wvalid => timer_axi_lite_wvalid, axi_wready => timer_axi_lite_wready, axi_wdata => timer_axi_lite_wdata, axi_wstrb => timer_axi_lite_wstrb, axi_bvalid => timer_axi_lite_bvalid, axi_bready => timer_axi_lite_bready, axi_bresp => timer_axi_lite_bresp, axi_araddr => timer_axi_lite_araddr, axi_arprot => timer_axi_lite_arprot, axi_arvalid => timer_axi_lite_arvalid, axi_arready => timer_axi_lite_arready, axi_rdata => timer_axi_lite_rdata, axi_rvalid => timer_axi_lite_rvalid, axi_rready => timer_axi_lite_rready, axi_rresp => timer_axi_lite_rresp, done => timer_int); plasoc_gpio_inst : plasoc_gpio generic map ( axi_address_width => axi_lite_address_width, axi_data_width => axi_data_width) port map ( aclk => aclk, aresetn => aresetn(0), data_in => gpio_input, data_out => gpio_output, int => gpio_int, axi_awaddr => gpio_axi_lite_awaddr, axi_awprot => gpio_axi_lite_awprot, axi_awvalid => gpio_axi_lite_awvalid, axi_awready => gpio_axi_lite_awready, axi_wvalid => gpio_axi_lite_wvalid, axi_wready => gpio_axi_lite_wready, axi_wdata => gpio_axi_lite_wdata, axi_wstrb => gpio_axi_lite_wstrb, axi_bvalid => gpio_axi_lite_bvalid, axi_bready => gpio_axi_lite_bready, axi_bresp => gpio_axi_lite_bresp, axi_araddr => gpio_axi_lite_araddr, axi_arprot => gpio_axi_lite_arprot, axi_arvalid => gpio_axi_lite_arvalid, axi_arready => gpio_axi_lite_arready, axi_rdata => gpio_axi_lite_rdata, axi_rvalid => gpio_axi_lite_rvalid, axi_rready => gpio_axi_lite_rready, axi_rresp => gpio_axi_lite_rresp); axi_cdma_inst : axi_cdma_0 PORT map ( m_axi_aclk => aclk, s_axi_lite_aclk => aclk, s_axi_lite_aresetn => aresetn(0), cdma_introut => cdma_int, s_axi_lite_awaddr => cdmareg_axi_lite_awaddr(5 downto 0), s_axi_lite_awvalid => cdmareg_axi_lite_awvalid, s_axi_lite_awready => cdmareg_axi_lite_awready, s_axi_lite_wvalid => cdmareg_axi_lite_wvalid, s_axi_lite_wready => cdmareg_axi_lite_wready, s_axi_lite_wdata => cdmareg_axi_lite_wdata, s_axi_lite_bvalid => cdmareg_axi_lite_bvalid, s_axi_lite_bready => cdmareg_axi_lite_bready, s_axi_lite_bresp => cdmareg_axi_lite_bresp, s_axi_lite_araddr => cdmareg_axi_lite_araddr(5 downto 0), s_axi_lite_arvalid => cdmareg_axi_lite_arvalid, s_axi_lite_arready => cdmareg_axi_lite_arready, s_axi_lite_rdata => cdmareg_axi_lite_rdata, s_axi_lite_rvalid => cdmareg_axi_lite_rvalid, s_axi_lite_rready => cdmareg_axi_lite_rready, s_axi_lite_rresp => cdmareg_axi_lite_rresp, m_axi_arready => cdma_axi_full_arready, m_axi_arvalid => cdma_axi_full_arvalid, m_axi_araddr => cdma_axi_full_araddr, m_axi_arlen => cdma_axi_full_arlen, m_axi_arsize => cdma_axi_full_arsize, m_axi_arburst => cdma_axi_full_arburst, m_axi_arprot => cdma_axi_full_arprot, m_axi_arcache => cdma_axi_full_arcache, m_axi_rready => cdma_axi_full_rready, m_axi_rvalid => cdma_axi_full_rvalid, m_axi_rdata => cdma_axi_full_rdata, m_axi_rresp => cdma_axi_full_rresp, m_axi_rlast => cdma_axi_full_rlast, m_axi_awready => cdma_axi_full_awready, m_axi_awvalid => cdma_axi_full_awvalid, m_axi_awaddr => cdma_axi_full_awaddr, m_axi_awlen => cdma_axi_full_awlen, m_axi_awsize => cdma_axi_full_awsize, m_axi_awburst => cdma_axi_full_awburst, m_axi_awprot => cdma_axi_full_awprot, m_axi_awcache => cdma_axi_full_awcache, m_axi_wready => cdma_axi_full_wready, m_axi_wvalid => cdma_axi_full_wvalid, m_axi_wdata => cdma_axi_full_wdata, m_axi_wstrb => cdma_axi_full_wstrb, m_axi_wlast => cdma_axi_full_wlast, m_axi_bready => cdma_axi_full_bready, m_axi_bvalid => cdma_axi_full_bvalid, m_axi_bresp => cdma_axi_full_bresp, cdma_tvect_out => open); plasoc_uart_inst : plasoc_uart generic map ( axi_address_width => axi_lite_address_width, axi_data_width => axi_data_width) port map ( aclk => aclk, aresetn => aresetn(0), axi_awaddr => uart_axi_lite_awaddr, axi_awprot => uart_axi_lite_awprot, axi_awvalid => uart_axi_lite_awvalid, axi_awready => uart_axi_lite_awready, axi_wvalid => uart_axi_lite_wvalid, axi_wready => uart_axi_lite_wready, axi_wdata => uart_axi_lite_wdata, axi_wstrb => uart_axi_lite_wstrb, axi_bvalid => uart_axi_lite_bvalid, axi_bready => uart_axi_lite_bready, axi_bresp => uart_axi_lite_bresp, axi_araddr => uart_axi_lite_araddr, axi_arprot => uart_axi_lite_arprot, axi_arvalid => uart_axi_lite_arvalid, axi_arready => uart_axi_lite_arready, axi_rdata => uart_axi_lite_rdata, axi_rvalid => uart_axi_lite_rvalid, axi_rready => uart_axi_lite_rready, axi_rresp => uart_axi_lite_rresp, tx => uart_tx, rx => uart_rx, status_in_avail => uart_int); plasoc_timer_extra_0_inst : plasoc_timer generic map ( axi_address_width => axi_lite_address_width, axi_data_width => axi_data_width) port map ( aclk => aclk, aresetn => aresetn(0), axi_awaddr => timer_extra_0_axi_lite_awaddr, axi_awprot => timer_extra_0_axi_lite_awprot, axi_awvalid => timer_extra_0_axi_lite_awvalid, axi_awready => timer_extra_0_axi_lite_awready, axi_wvalid => timer_extra_0_axi_lite_wvalid, axi_wready => timer_extra_0_axi_lite_wready, axi_wdata => timer_extra_0_axi_lite_wdata, axi_wstrb => timer_extra_0_axi_lite_wstrb, axi_bvalid => timer_extra_0_axi_lite_bvalid, axi_bready => timer_extra_0_axi_lite_bready, axi_bresp => timer_extra_0_axi_lite_bresp, axi_araddr => timer_extra_0_axi_lite_araddr, axi_arprot => timer_extra_0_axi_lite_arprot, axi_arvalid => timer_extra_0_axi_lite_arvalid, axi_arready => timer_extra_0_axi_lite_arready, axi_rdata => timer_extra_0_axi_lite_rdata, axi_rvalid => timer_extra_0_axi_lite_rvalid, axi_rready => timer_extra_0_axi_lite_rready, axi_rresp => timer_extra_0_axi_lite_rresp, done => timer_extra_0_int); end Behavioral;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity LS is Port ( x : in std_logic_vector(10 downto 0); shift : in std_logic_vector(2 downto 0); y : out std_logic_vector(18 downto 0)); -- y : out std_logic_vector(16 downto 0); -- clk : in std_logic); end LS; architecture Behavioral of LS is signal reg1 : std_logic_vector(13 downto 0); signal reg2 : std_logic_vector(17 downto 0); component mux2t1 Port ( In1 : in std_logic; In2 : in std_logic; sel : in std_logic; Output : out std_logic); -- Output : out std_logic; -- clock : in std_logic); end component; begin C1: mux2t1 port map('0', x(0), shift(0), reg1(0)); -- port map('0', x(0), shift(0), reg1(0), clk); Layer1 : for i in 1 to 10 generate C1: mux2t1 port map(x(i - 1), x(i), shift(0), reg1(i)); -- port map(x(i - 1), x(i), shift(0), reg1(i), clk); end generate; reg1(13) <= x(10); reg1(12) <= x(10); reg1(11) <= x(10); C20: mux2t1 port map('0', reg1(0), shift(1), reg2(0)); -- port map('0', reg1(0), shift(1), reg2(0), clk); C21: mux2t1 port map('0', reg1(1), shift(1), reg2(1)); -- port map('0', reg1(1), shift(1), reg2(1), clk); Layer2 : for i in 2 to 13 generate C2: mux2t1 port map(reg1(i - 2), reg1(i), shift(1), reg2(i)); -- port map(reg1(i - 2), reg1(i), shift(1), reg2(i), clk); end generate; reg2(17) <= x(10); reg2(16) <= x(10); reg2(15) <= x(10); reg2(14) <= x(10); C30: mux2t1 port map('0', reg2(0), shift(2), y(0)); -- port map('0', reg2(0), shift(2), y(0), clk); C31: mux2t1 port map('0', reg2(1), shift(2), y(1)); -- port map('0', reg2(1), shift(2), y(1), clk); C32: mux2t1 port map('0', reg2(2), shift(2), y(2)); -- port map('0', reg2(2), shift(2), y(2), clk); C33: mux2t1 port map('0', reg2(3), shift(2), y(3)); -- port map('0', reg2(3), shift(2), y(3), clk); Layer3 : for i in 4 to 17 generate C3: mux2t1 port map(reg2(i - 4), reg2(i), shift(2), y(i)); -- port map(reg2(i - 4), reg2(i), shift(2), y(i), clk); end generate; y(18) <= x(10); end Behavioral;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity new3phd is Port ( clk: in STD_LOGIC; pwmrefcnt: in STD_LOGIC_VECTOR(9 downto 0); ibus: in STD_LOGIC_VECTOR (31 downto 0); obus: out STD_LOGIC_VECTOR (31 downto 0); writestb: in STD_LOGIC; readstb: in STD_LOGIC; addr: in STD_LOGIC_VECTOR (1 downto 0); outa: out STD_LOGIC; outb: out STD_LOGIC; outc: out STD_LOGIC ); end new3phd; architecture behavioral of new3phd is signal creg: STD_LOGIC_VECTOR (2 downto 0); alias refmsb: std_logic is pwmrefcnt(9); signal oldrefmsb: std_logic; signal FIFORead: std_logic; signal Start: std_logic; signal HostStart: std_logic; signal PopData: STD_LOGIC_VECTOR (31 downto 0); alias PWMPtr: STD_LOGIC_VECTOR (1 downto 0) is PopData(1 downto 0); alias Aflag: std_logic is PopData(4); signal PushData: STD_LOGIC_VECTOR (31 downto 0); signal FIFOdatawr: STD_LOGIC; signal IncDataCount: STD_LOGIC; signal IncDataCountp: STD_LOGIC; signal PushPtr: STD_LOGIC_VECTOR (7 downto 0); signal PopPtr: STD_LOGIC_VECTOR (7 downto 0); signal FPopPtr: STD_LOGIC_VECTOR (7 downto 0); signal DataCount: STD_LOGIC_VECTOR (8 downto 0); signal pwmas: STD_LOGIC_VECTOR (9 downto 0); signal pwmbs: STD_LOGIC_VECTOR (9 downto 0); signal pwmcs: STD_LOGIC_VECTOR (9 downto 0); signal pwmae: STD_LOGIC_VECTOR (9 downto 0); signal pwmbe: STD_LOGIC_VECTOR (9 downto 0); signal pwmce: STD_LOGIC_VECTOR (9 downto 0); signal pwmapol: STD_LOGIC; signal pwmbpol: STD_LOGIC; signal pwmcpol: STD_LOGIC; signal pwmouta: STD_LOGIC; signal pwmoutb: STD_LOGIC; signal pwmoutc: STD_LOGIC; component FIFOMem32 IS port ( addra: IN std_logic_VECTOR(7 downto 0); addrb: IN std_logic_VECTOR(7 downto 0); clka: IN std_logic; clkb: IN std_logic; dina: IN std_logic_VECTOR(31 downto 0); dinb: IN std_logic_VECTOR(31 downto 0); douta: OUT std_logic_VECTOR(31 downto 0); doutb: OUT std_logic_VECTOR(31 downto 0); wea: IN std_logic; web: IN std_logic); end component FIFOMem32; begin AFIFO: FIFOMem32 port map ( addra => FPopPtr, addrb => PushPtr, clka => clk, clkb => clk, dina => x"00000000", dinb => ibus, douta => PopData, doutb => PushData, wea => '0', web => FIFOdatawr ); athreephase: process (clk,addr,readstb,writestb, creg, pwmouta, pwmoutb, pwmoutc ) begin if clk'event and clk = '1' then IncDataCount <= IncDataCountP; if (IncDataCount = '1') and (FIFOREAD = '0') then IncDataCount <= '0'; IncDataCountP <= '0'; DataCount <= DataCount + 1; end if; if (UNSIGNED(pwmrefcnt) >= UNSIGNED(pwmas)) and (UNSIGNED(pwmrefcnt) <= UNSIGNED(pwmae)) then pwmouta <= '1' xor pwmapol; else pwmouta <= '0' xor pwmapol; end if; if (UNSIGNED(pwmrefcnt) >= UNSIGNED(pwmbs)) and (UNSIGNED(pwmrefcnt) <= UNSIGNED(pwmbe)) then pwmoutb <= '1' xor pwmbpol; else pwmoutb <= '0' xor pwmbpol; end if; if (UNSIGNED(pwmrefcnt) >= UNSIGNED(pwmcs)) and (UNSIGNED(pwmrefcnt) <= UNSIGNED(pwmce)) then pwmoutc <= '1' xor pwmcpol; else pwmoutc <= '0' xor pwmcpol; end if; oldrefmsb <= refmsb; if FIFORead = '1' and DataCount /= 0 then case PWMPtr is when "00" => pwmas <= PopData(14 downto 5); pwmae <= PopData(30 downto 21); pwmapol <= PopData(31); when "01" => pwmbs <= PopData(14 downto 5); pwmbe <= PopData(30 downto 21); pwmbpol <= PopData(31); when "10" => pwmcs <= PopData(14 downto 5); pwmce <= PopData(30 downto 21); pwmcpol <= PopData(31); when others => null; end case; PopPtr <= FPopPtr; DataCount <= DataCount -1; end if; if writestb = '1' then case addr is when "00" => PushPtr <= PushPtr + 1; IncDataCountp <= '1'; when "01" => creg <= ibus(2 downto 0); when "10" => Datacount <= (others => '0'); PopPtr <= (others => '0'); PushPtr <= (others => '0'); when others => null; end case; end if; end if; -- clk if ((Start = '1') or (AFlag = '0')) and (DataCount /= 0) then FIFORead <= '1'; FPopPtr <= PopPtr +1; else FIFORead <= '0'; FPopPtr <= PopPtr; end if; if writestb = '1' and addr = "11" then HostStart <= '1'; else HostStart <= '0'; end if; if writestb = '1' and addr = "00" then FIFOdataWr <= '1'; else FIFODataWr <= '0'; end if; if (oldrefmsb = '1' and refmsb = '0' and AFlag = '1' and creg(0) = '1') or (Hoststart = '1' ) then Start <= '1'; else Start <= '0'; end if; obus <= (others => 'Z'); if readstb = '1' then case addr is when "00" => obus <= PopData; when "01" => obus <= (2 => creg(2),1 => creg(1),0 =>creg(0), others => '0'); when "10" => obus(8 downto 0) <= DataCount; when others => obus <= (others => 'Z'); end case; else obus <= (others => 'Z'); end if; if creg(1) = '1' then if creg(2) = '0' then outa <= pwmouta; outb <= pwmoutb; outc <= pwmoutc; else outa <= pwmoutb; outb <= pwmouta; outc <= pwmoutc; end if; else outa <= 'Z'; outb <= 'Z'; outc <= 'Z'; end if; end process; end behavioral;

---------------------------------------------------------------------------------- -- Engineer: Mike Field <hamster@snap.net.nz> -- -- Module Name: input_serialiser -- -- Description: A 5-bits per cycle SDR input serialiser -- -- Maybe in the future the 'bitslip' funciton can be implemented. ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VComponents.all; entity input_serialiser is Port ( clk_fabric_x2 : in STD_LOGIC; clk_input : in STD_LOGIC; strobe : in STD_LOGIC; ser_data : out STD_LOGIC_VECTOR (4 downto 0); ser_input : in STD_LOGIC); end input_serialiser; architecture Behavioral of input_serialiser is signal clk0, clk1, clkdiv : std_logic; signal cascade : std_logic; constant bitslip : std_logic := '0'; begin clkdiv <= clk_fabric_x2; clk0 <= clk_input; clk1 <= '0'; ISERDES2_master : ISERDES2 generic map ( BITSLIP_ENABLE => TRUE, -- Enable Bitslip Functionality (TRUE/FALSE) DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR") DATA_WIDTH => 5, -- Parallel data width selection (2-8) INTERFACE_TYPE => "RETIMED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED" SERDES_MODE => "MASTER" -- "NONE", "MASTER" or "SLAVE" ) port map ( CFB0 => open, -- 1-bit output: Clock feed-through route output CFB1 => open, -- 1-bit output: Clock feed-through route output DFB => open, -- 1-bit output: Feed-through clock output FABRICOUT => open, -- 1-bit output: Unsynchrnonized data output INCDEC => open, -- 1-bit output: Phase detector output -- Q1 - Q4: 1-bit (each) output: Registered outputs to FPGA logic Q1 => ser_data(1), Q2 => ser_data(2), Q3 => ser_data(3), Q4 => ser_data(4), SHIFTOUT => cascade, -- 1-bit output: Cascade output signal for master/slave I/O VALID => open, -- 1-bit output: Output status of the phase detector BITSLIP => bitslip , -- 1-bit input: Bitslip enable input CE0 => '1', -- 1-bit input: Clock enable input CLK0 => clk0, -- 1-bit input: I/O clock network input CLK1 => clk1, -- 1-bit input: Secondary I/O clock network input CLKDIV => clkdiv, -- 1-bit input: FPGA logic domain clock input D => ser_input, -- 1-bit input: Input data IOCE => strobe, -- 1-bit input: Data strobe input RST => '0', -- 1-bit input: Asynchronous reset input SHIFTIN => '0' -- 1-bit input: Cascade input signal for master/slave I/O ); ISERDES2_slave : ISERDES2 generic map ( BITSLIP_ENABLE => TRUE, -- Enable Bitslip Functionality (TRUE/FALSE) DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR") DATA_WIDTH => 5, -- Parallel data width selection (2-8) INTERFACE_TYPE => "RETIMED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED" SERDES_MODE => "SLAVE" -- "NONE", "MASTER" or "SLAVE" ) port map ( CFB0 => open, -- 1-bit output: Clock feed-through route output CFB1 => open, -- 1-bit output: Clock feed-through route output DFB => open, -- 1-bit output: Feed-through clock output FABRICOUT => open, -- 1-bit output: Unsynchrnonized data output INCDEC => open, -- 1-bit output: Phase detector output -- Q1 - Q4: 1-bit (each) output: Registered outputs to FPGA logic Q1 => open, Q2 => open, Q3 => open, Q4 => ser_data(0), SHIFTOUT => open, -- 1-bit output: Cascade output signal for master/slave I/O VALID => open, -- 1-bit output: Output status of the phase detector BITSLIP => bitslip, -- 1-bit input: Bitslip enable input CE0 => '1', -- 1-bit input: Clock enable input CLK0 => clk0, -- 1-bit input: I/O clock network input CLK1 => clk1, -- 1-bit input: Secondary I/O clock network input CLKDIV => clkdiv, -- 1-bit input: FPGA logic domain clock input D => '0', -- 1-bit input: Input data IOCE => '1', -- 1-bit input: Data strobe input RST => '0', -- 1-bit input: Asynchronous reset input SHIFTIN => cascade -- 1-bit input: Cascade input signal for master/slave I/O ); end Behavioral;

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity fc_system_v4 is port( flight_no : in std_logic_vector(2 downto 0); request: in std_logic; reset,clk : in std_logic; clk3_out,clk10_out : out std_logic;--For demo only grant,denied: out std_logic ); end fc_system_v4; architecture beh of fc_system_v4 is type state_type is (IDLE,WBReq,WBGrant,WBOnly,Deny,Deny_t,NBReq,NBGrant); signal state_reg,state_next:state_type; signal clk3_count,clk10_count : unsigned(26 downto 0); signal pulse3_1sec,pulse10_1sec: std_logic; signal clk10_reg,clk10_next:unsigned(3 downto 0); signal clk3_reg,clk3_next:unsigned(1 downto 0); signal load10_clk,load3_clk:std_logic; signal clk3_out_reg,clk3_out_next,clk10_out_reg,clk10_out_next:std_logic;--Demo only signal reset3,reset10:std_logic; begin process(clk,reset) begin if(reset ='1') then state_reg<=IDLE; elsif (clk' event and clk ='1') then state_reg<=state_next; end if; end process; --Clock process process(clk,reset3) begin if(reset3 ='1') then clk3_count <= (others => '0'); elsif (clk' event and clk ='1') then clk3_count <= clk3_count + 1; end if; end process; process(clk,reset10) begin if(reset10 ='1') then clk10_count <= (others => '0'); elsif (clk' event and clk ='1') then clk10_count <= clk10_count + 1; end if; end process; process(pulse10_1sec,load10_clk) begin if(load10_clk ='1') then clk10_reg<="1010"; clk10_out_reg<='1'; elsif(pulse10_1sec' event and pulse10_1sec ='1') then clk10_reg <= clk10_next; clk10_out_reg <= clk10_out_next;--Demo only end if; end process; process(pulse3_1sec,load3_clk) begin if(load3_clk ='1') then clk3_reg<="11"; clk3_out_reg<='1'; elsif(pulse3_1sec' event and pulse3_1sec ='1') then clk3_reg <= clk3_next; clk3_out_reg <= clk3_out_next;--Demo only end if; end process; pulse3_1sec <= clk3_count(26); pulse10_1sec <= clk10_count(26); reset3 <= load3_clk or reset; reset10 <= load10_clk or reset; clk3_out_next <= not clk3_out_reg; clk10_out_next <= not clk10_out_reg; clk3_out<=clk3_out_reg; clk10_out<=clk10_out_reg; clk10_next <= (others =>'0') when (clk10_reg = "0000") else (clk10_reg - 1); clk3_next <= (others => '0') when (clk3_reg ="00" ) else (clk3_reg - 1); --Next state logic and output logic process(state_reg,request,clk10_reg,clk3_reg) begin grant <= '0'; denied <='0'; load10_clk <='0'; load3_clk <='0'; case state_reg is when IDLE => if(request ='1') then if(flight_no="001" or flight_no="011" or flight_no ="111") then state_next <= WBReq; else state_next <= NBReq; end if; else state_next <= IDLE; end if; when WBReq=> load10_clk<='1'; state_next <= WBGrant; when WBGrant => if(clk10_reg = "0111") then --3Sec elapsed state_next <= WBOnly; else state_next <= WBGrant; end if; grant <= '1'; when WBOnly => if(request = '1') then if(flight_no="001" or flight_no="011" or flight_no ="111") then state_next <= WBReq; else state_next <= Deny_t; end if; elsif(clk10_reg="0000") then state_next <= IDLE; else state_next <= WBOnly; end if; when Deny_t => load3_clk <='1'; state_next <= Deny; when Deny => if(clk3_reg = "00") then state_next<=WBOnly; else state_next <= Deny; end if; denied <='1'; when NBReq => load3_clk <='1'; --load10_clk <='1'; --Demo purposr only state_next <= NBGrant; when NBGrant => if(clk3_reg ="00") then state_next <= IDLE; else state_next <= NBGrant; end if; grant <= '1'; end case; end process; end beh;

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_textio.all; entity scratch_pad is port ( data_in1, data_in2 : in std_logic_vector(7 downto 0); raddr_write1, raddr_write2 : in std_logic_vector(3 downto 0); data_out : out std_logic_vector(7 downto 0); raddr_read : in std_logic_vector(3 downto 0); re, we, clk : in std_logic ); end entity; architecture behav of scratch_pad is type mem_array is array(15 downto 0) of std_logic_vector(7 downto 0); signal mem_data : mem_array; begin process (clk) begin if (rising_edge(clk) and (we = '1')) then mem_data(conv_integer(raddr_write1)) <= data_in1; report "Scratch Pad write addr: " & integer'image(conv_integer(raddr_write1)) & " data: " & integer'image(conv_integer(data_in1)); mem_data(conv_integer(raddr_write2)) <= data_in2; report "Scratch Pad write addr: " & integer'image(conv_integer(raddr_write2)) & " data: " & integer'image(conv_integer(data_in2)); elsif (falling_edge(clk) and (re = '1')) then data_out <= mem_data(conv_integer(raddr_read)); report "Scratch Pad read addr: " & integer'image(conv_integer(raddr_read)) & " data: " & integer'image(conv_integer(mem_data(conv_integer(raddr_read)))); end if; end process; end architecture;

package pack1 is type my_int1 is range 0 to 10; end package; ------------------------------------------------------------------------------- package pack2 is type my_int1 is range 0 to 10; end package; ------------------------------------------------------------------------------- use work.pack1; use work.pack2; entity no_use_clause is port ( a : in pack1.my_int1; b : out pack2.my_int1 ); end entity; ------------------------------------------------------------------------------- architecture a of no_use_clause is type my_int1 is range 10 to 50; begin process is begin -- Should fail as types have same name but from different packages b <= a; end process; process is variable v : pack2.my_int1; begin b <= v; -- OK end process; process is variable v : my_int1; begin -- Should fail as local my_int1 distinct from pack1.my_int1 v := a; end process; end architecture; ------------------------------------------------------------------------------- use work.pack1.all; entity foo is generic ( g : my_int1 ); port ( p : in my_int1 ); end entity; ------------------------------------------------------------------------------- architecture a of foo is -- Architecture decls exist in same scope as entity so this should -- generate an error signal g : my_int1; begin end architecture; ------------------------------------------------------------------------------- architecture b of foo is -- Should also generate an error signal p : my_int1; begin end architecture; ------------------------------------------------------------------------------- architecture c of foo is begin -- This is OK as processes define a new scope process is variable p : my_int1; variable g : my_int1; begin g := 6; p := 2; wait for 1 ns; end process; end architecture; ------------------------------------------------------------------------------- entity overload is port ( SI: in bit; SO: out bit ); end ; architecture behave of overload is begin foo_inst: SO <= SI; end behave; ------------------------------------------------------------------------------- use work.all; entity no_use_clause is port ( a : in pack1.my_int1; -- OK b : out my_int1 ); -- Error end entity; ------------------------------------------------------------------------------- package pack3 is type my_enum is (E1, E2, E3); end package; ------------------------------------------------------------------------------- use work.pack3.all; package pack4 is type my_enum_array is array (integer range <>) of my_enum; end package; ------------------------------------------------------------------------------- use work.pack4.all; architecture a of foo is signal x : my_enum_array(1 to 3); -- OK signal y : my_enum_array(1 to 3) := (others => E1); -- Error: E1 not visible begin end architecture; ------------------------------------------------------------------------------- package pack5 is function func1(x : integer) return boolean; function func2(x : integer) return boolean; function "and"(x, y : integer) return boolean; end package; ------------------------------------------------------------------------------- use work.pack5.func1; architecture a2 of foo is begin process is begin assert func1(4); -- OK assert func2(5); -- Error end process; end architecture; ------------------------------------------------------------------------------- use work.pack5.not_here; -- Error architecture a3 of foo is begin end architecture; ------------------------------------------------------------------------------- entity bar is end entity; architecture a4 of bar is begin process is use work.pack1.all; variable x : my_int1; -- OK begin x := 5; end process; process is variable x : my_int1; -- Error begin end process; b: block is use work.pack1; signal x : pack1.my_int1; -- OK begin end block; end architecture; ------------------------------------------------------------------------------- use work.pack5."and"; architecture a5 of bar is begin process is begin assert 1 and 2; -- OK assert work.pack5."and"(1, 2); -- OK assert pack5."and"(1, 2); -- OK end process; end architecture; ------------------------------------------------------------------------------- package pack6 is component bar is end component; end package; ------------------------------------------------------------------------------- use work.pack6.all; architecture a6 of bar is begin process is begin report bar'path_name; -- OK (references entity) end process; end architecture; ------------------------------------------------------------------------------- use foo.bar.all; -- Error architecture a7 of bar is begin end architecture; ------------------------------------------------------------------------------- package pack7 is function foo(x : in integer) return boolean; function foo(y : in real) return boolean; end package; ------------------------------------------------------------------------------- use work.pack7.foo; architecture issue62 of bar is begin process is begin assert foo(integer'(1)); -- OK assert foo(real'(1.6)); -- OK end process; end architecture; ------------------------------------------------------------------------------- use work.all; use work.pack1.all; architecture issue63 of bar is signal x : my_int1; -- OK begin end architecture; ------------------------------------------------------------------------------- package pack8 is function min(x, y : in integer) return integer; end package; ------------------------------------------------------------------------------- use work.pack8.all; -- OK architecture unit_decl_crash of bar is begin process is variable x : integer := min(1, 2); -- OK begin end process; end architecture;

architecture RTL of FIFO is begin process begin -- These are passing a := b or d; a := '0' when c = '0' else '1' when d = '1' else 'Z'; -- Failing variations a := b or d; a := '0' when c = '0' else '1' when d = '1' else 'Z'; end process; end architecture RTL;

-- -- All rights reserved -- -- Redistribution and use in source and synthezised forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- * Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- -- * Redistributions in synthesized form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- * Neither the name of the author nor the names of other contributors may -- be used to endorse or promote products derived from this software without -- specific prior written agreement from the author. -- -- * License is granted for non-commercial use only. A fee may not be charged -- for redistributions as source code or in synthesized/hardware form without -- specific prior written agreement from the author. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; -- for AND_REDUCE use ieee.numeric_std.all; entity i2c_loader is generic ( device_address : integer := 16#1a#; -- Address of slave to be loaded num_retries : integer := 0; -- Number of retries to allow before stopping log2_divider : integer := 6 -- Length of clock divider in bits. Resulting bus frequency is CLK/2^(log2_divider + 2) ); port ( clock_i : in std_logic; reset_i : in std_logic; i2c_scl_io : inout std_logic; i2c_sda_io : inout std_logic; is_done_o : out std_logic; is_error_o : out std_logic ); end entity; architecture rtl of i2c_loader is --/---------+---------------------------+---------+--------+---------+--------+------+------+------+--------+---------\ --|Register |B15 B14 B13 B12 B11 B10 B9 | B8 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 | --+---------+---------------------------+---------+--------+---------+--------+------+------+------+--------+---------+ --|R0 (00h) | 0 0 0 0 0 0 0 |LRIN BOTH|LIN MUTE| 0 | 0 | LINVOL | --+---------+---------------------------+---------+--------+---------+--------+---------------------------------------+ --|R1 (02h) | 0 0 0 0 0 0 1 |RLIN BOTH|RIN MUTE| 0 | 0 | RINVOL | --+---------+---------------------------+---------+--------+---------+--------+---------------------------------------+ --|R2 (04h) | 0 0 0 0 0 1 0 |LRHP BOTH|LZCEN | LHPVOL | --+---------+---------------------------+---------+--------+----------------------------------------------------------+ --|R3 (06h) | 0 0 0 0 0 1 1 |RLHP BOTH|RZCEN | RHPVOL | --+---------+---------------------------+---------+--------+---------+--------+------+------+------+--------+---------+ --|R4 (08h) | 0 0 0 0 1 0 0 | 0 | SIDEATT |SIDETONE|DACSEL|BYPASS|INSEL |MUTE MIC|MIC BOOST| --+---------+---------------------------+---------+--------+---------+--------+------+------+------+--------+---------+ --|R5 (0Ah) | 0 0 0 0 1 0 1 | 0 | 0 | 0 | 0 | HPOR |DAC MU| DEEMPH | ADC HPD | --+---------+---------------------------+---------+--------+---------+--------+------+------+------+--------+---------+ --|R6 (0Ch) | 0 0 0 0 1 1 0 | 0 |PWR OFF |CLK OUTPD| OSCPD |OUTPD |DACPD |ADCPD | MICPD |LINEINPD | --+---------+---------------------------+---------+--------+---------+--------+------+------+------+--------+---------+ --|R7 (0Eh) | 0 0 0 0 1 1 1 | 0 |BCLK INV| MS |LR SWAP | LRP | IWL | FORMAT | --+---------+---------------------------+---------+--------+---------+--------+------+-------------+--------+---------+ --|R8 (10h) | 0 0 0 1 0 0 0 | 0 |CLKO /2 | CLKI /2 | SR | BOSR |USB/NORM | --+---------+---------------------------+---------+--------+---------+--------+------+------+------+--------+---------+ --|R9 (12h) | 0 0 0 1 0 0 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ACTIVE | --+---------+---------------------------+---------+--------+---------+--------+------+------+------+--------+---------+ --|R15 (1Eh)| 0 0 0 1 1 1 1 | RESET | --\---------+---------------------------+-----------------------------------------------------------------------------/ type regs is array(0 to 21) of std_logic_vector(7 downto 0); constant init_regs : regs := ( X"00", X"00", -- dummy X"00", X"08", -- Left line in, unmute, ?dB -- 0 0 00 10111 X"02", X"80", -- Right line in, mute -- 0 1 00 00000 X"04", X"79", -- Left headphone out, 0dB X"06", X"79", -- Right headphone out, 0dB X"08", X"10", -- Audio path, DAC enabled, Line in, Bypass off, mic unmuted -- X"0A", X"00", -- Digital path, Unmute, HP filter enabled, no DEEMPH -- X"0A", X"02", -- Digital path, Unmute, HP filter enabled, DEEMPH 32KHz -- X"0A", X"04", -- Digital path, Unmute, HP filter enabled, DEEMPH 44.1KHz X"0A", X"06", -- Digital path, Unmute, HP filter enabled, DEEMPH 48KHz X"0C", X"62", -- Power down mic, clkout and xtal osc X"0E", X"02", -- Format 16-bit I2S, no bit inversion or phase changes -- X"10", X"0D", -- Sampling control, 8 kHz USB mode (MCLK = 250fs * 6) -- X"10", X"01", -- Sampling control, 48 KHz, USB mode (MCLK = 250fs) -- X"10", X"3F", -- Sampling control, 88.2 KHz, USB mode (MCLK = 136fs) X"10", X"1D", -- Sampling control, 96 KHz, USB mode (MCLK = 125fs) X"12", X"01" -- Activate ); constant burst_length : positive := 2; -- Number of bursts (i.e. total number of registers) constant num_bursts : positive := (init_regs'length / burst_length); -- Number of bytes to transfer per burst type state_t is (Idle, Start, Data, Ack, Stop, Pause, Done); signal state : state_t; signal phase : std_logic_vector(1 downto 0); subtype nbit_t is integer range 0 to 7; signal nbit : nbit_t; subtype nbyte_t is integer range 0 to burst_length; -- +1 for address byte signal nbyte : nbyte_t; subtype thisbyte_t is integer range 0 to init_regs'length; -- +1 for "done" signal thisbyte : thisbyte_t; subtype retries_t is integer range 0 to num_retries; signal retries : retries_t; signal clken : std_logic; signal divider : std_logic_vector(log2_divider-1 downto 0); signal shiftreg : std_logic_vector(7 downto 0); signal scl_out : std_logic; signal sda_out : std_logic; signal nak : std_logic; begin -- Create open-drain outputs for I2C bus i2c_scl_io <= '0' when scl_out = '0' else 'Z'; i2c_sda_io <= '0' when sda_out = '0' else 'Z'; -- Status outputs are driven both ways is_done_o <= '1' when state = Done else '0'; is_error_o <= nak; -- Generate clock enable for desired bus speed clken <= AND_REDUCE(divider); process(reset_i, clock_i) begin if reset_i = '1' then divider <= (others => '0'); elsif falling_edge(clock_i) then divider <= divider + '1'; end if; end process; -- The I2C loader process process(reset_i, clock_i, clken) begin if reset_i = '1' then scl_out <= '1'; sda_out <= '1'; state <= Idle; phase <= "00"; nbit <= 0; nbyte <= 0; thisbyte <= 0; shiftreg <= (others => '0'); nak <= '0'; -- No error retries <= num_retries; elsif rising_edge(clock_i) and clken = '1' then -- Next phase by default phase <= phase + 1; -- STATE: IDLE if state = Idle then -- Start loading the device registers straight away -- A 'GO' bit could be polled here if required state <= Start; phase <= "00"; scl_out <= '1'; sda_out <= '1'; -- STATE: START elsif state = Start then -- Generate START condition case phase is when "00" => -- Drop SDA first sda_out <= '0'; when "10" => -- Then drop SCL scl_out <= '0'; when "11" => -- Advance to next state -- Shift register loaded with device slave address state <= Data; nbit <= 7; shiftreg <= std_logic_vector(to_unsigned(device_address,7)) & '0'; -- writing nbyte <= burst_length; when others => null; end case; -- STATE: DATA elsif state = Data then -- Generate data case phase is when "00" => -- Drop SCL scl_out <= '0'; when "01" => -- Output data and shift (MSb first) sda_out <= shiftreg(7); shiftreg <= shiftreg(6 downto 0) & '0'; when "10" => -- Raise SCL scl_out <= '1'; when "11" => -- Next bit or advance to next state when done if nbit = 0 then state <= Ack; else nbit <= nbit - 1; end if; when others => null; end case; -- STATE: ACK elsif state = Ack then -- Generate ACK clock and check for error condition case phase is when "00" => -- Drop SCL scl_out <= '0'; when "01" => -- Float data sda_out <= '1'; when "10" => -- Sample ack bit nak <= i2c_sda_io; if i2c_sda_io = '1' then -- Error nbyte <= 0; -- Close this burst and skip remaining registers thisbyte <= init_regs'length; else -- Hold ACK to avoid spurious stops - this seems to fix a -- problem with the Wolfson codec which releases the ACK -- right on the falling edge of the clock pulse. It looks like -- the device interprets this is a STOP condition and then fails -- to acknowledge the next byte. We can avoid this by holding the -- ACK condition for a little longer. sda_out <= '0'; end if; -- Raise SCL scl_out <= '1'; when "11" => -- Advance to next state if nbyte = 0 then -- No more bytes in this burst - generate a STOP state <= Stop; else -- Generate next byte state <= Data; nbit <= 7; shiftreg <= init_regs(thisbyte); nbyte <= nbyte - 1; thisbyte <= thisbyte + 1; end if; when others => null; end case; -- STATE: STOP elsif state = Stop then -- Generate STOP condition case phase is when "00" => -- Drop SCL first scl_out <= '0'; when "01" => -- Drop SDA sda_out <= '0'; when "10" => -- Raise SCL scl_out <= '1'; when "11" => if thisbyte = init_regs'length then -- All registers done, advance to finished state. This will -- bring SDA high while SCL is still high, completing the STOP -- condition state <= Done; else -- Load the next register after a short delay state <= Pause; end if; when others => null; end case; -- STATE: PAUSE elsif state = Pause then -- Delay for one cycle of 'phase' then start the next burst scl_out <= '1'; sda_out <= '1'; if phase = "11" then state <= Start; end if; -- STATE: DONE else -- Finished scl_out <= '1'; sda_out <= '1'; if nak = '1' and retries > 0 then -- We can retry in the event of a NAK in case the -- slave got out of sync for some reason retries <= retries - 1; state <= Idle; end if; end if; end if; end process; end architecture;

architecture ARCH of ENTITY1 is begin U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); -- Violations below U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); end architecture ARCH;

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2013, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: syncram64 -- File: syncram64.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: 64-bit syncronous 1-port ram with 32-bit write strobes -- and tech selection ------------------------------------------------------------------------------ library ieee; library techmap; use ieee.std_logic_1164.all; use techmap.gencomp.all; use techmap.allmem.all; library grlib; use grlib.config.all; use grlib.config_types.all; use grlib.stdlib.all; entity syncram64 is generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; paren : integer := 0; custombits : integer := 1); port ( clk : in std_ulogic; address : in std_logic_vector (abits -1 downto 0); datain : in std_logic_vector (63+8*paren downto 0); dataout : out std_logic_vector (63+8*paren downto 0); enable : in std_logic_vector (1 downto 0); write : in std_logic_vector (1 downto 0); testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none; customclk: in std_ulogic := '0'; customin : in std_logic_vector(2*custombits-1 downto 0) := (others => '0'); customout:out std_logic_vector(2*custombits-1 downto 0)); end; architecture rtl of syncram64 is component unisim_syncram64 generic ( abits : integer := 9); port ( clk : in std_ulogic; address : in std_logic_vector (abits -1 downto 0); datain : in std_logic_vector (63 downto 0); dataout : out std_logic_vector (63 downto 0); enable : in std_logic_vector (1 downto 0); write : in std_logic_vector (1 downto 0) ); end component; component artisan_syncram64 generic ( abits : integer := 9); port ( clk : in std_ulogic; address : in std_logic_vector (abits -1 downto 0); datain : in std_logic_vector (63 downto 0); dataout : out std_logic_vector (63 downto 0); enable : in std_logic_vector (1 downto 0); write : in std_logic_vector (1 downto 0) ); end component; component custom1_syncram64 generic ( abits : integer := 9); port ( clk : in std_ulogic; address : in std_logic_vector (abits -1 downto 0); datain : in std_logic_vector (63 downto 0); dataout : out std_logic_vector (63 downto 0); enable : in std_logic_vector (1 downto 0); write : in std_logic_vector (1 downto 0) ); end component; component smic13_syncram64 generic ( abits : integer := 9); port ( clk : in std_ulogic; address : in std_logic_vector (abits -1 downto 0); datain : in std_logic_vector (63 downto 0); dataout : out std_logic_vector (63 downto 0); enable : in std_logic_vector (1 downto 0); write : in std_logic_vector (1 downto 0) ); end component; signal dinp, doutp : std_logic_vector(71 downto 0); signal xenable : std_logic_vector(1 downto 0); signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0); begin xenable <= enable when testen=0 or testin(TESTIN_WIDTH-2)='0' else "00"; custominx(custominx'high downto custombits) <= (others => '0'); custominx(custombits-1 downto 0) <= customin(custombits-1 downto 0); nocust: if syncram_has_customif(tech)=0 or has_sram64(tech)=0 or paren=1 generate customoutx <= (others => '0'); end generate; nopar : if paren = 0 generate s64 : if has_sram64(tech) = 1 generate xc2v : if (is_unisim(tech) = 1) generate x0 : unisim_syncram64 generic map (abits) port map (clk, address, datain(63 downto 0), dataout(63 downto 0), xenable, write); end generate; arti : if tech = memartisan generate x0 : artisan_syncram64 generic map (abits) port map (clk, address, datain(63 downto 0), dataout(63 downto 0), xenable, write); end generate; cust1: if tech = custom1 generate x0 : custom1_syncram64 generic map (abits) port map (clk, address, datain(63 downto 0), dataout(63 downto 0), xenable, write); end generate; smic: if tech = smic013 generate x0 : smic13_syncram64 generic map (abits) port map (clk, address, datain(63 downto 0), dataout(63 downto 0), xenable, write); end generate; n2x : if tech = easic45 generate x0 : n2x_syncram_we generic map (abits => abits, dbits => 64) port map(clk, address, datain(63 downto 0), dataout(63 downto 0), xenable, write); end generate; customout(2*custombits-1 downto custombits) <= (others => '0'); customout(custombits-1 downto 0) <= customoutx(custombits-1 downto 0); -- pragma translate_off dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate x : process begin assert false report "syncram64: " & tost(2**abits) & "x64" & " (" & tech_table(tech) & ")" severity note; wait; end process; end generate; -- pragma translate_on end generate; nos64 : if has_sram64(tech) = 0 generate x0 : syncram generic map (tech, abits, 32, testen, custombits) port map (clk, address, datain(63 downto 32), dataout(63 downto 32), enable(1), write(1), testin, customclk, customin(2*custombits-1 downto custombits), customout(2*custombits-1 downto custombits)); x1 : syncram generic map (tech, abits, 32, testen, custombits) port map (clk, address, datain(31 downto 0), dataout(31 downto 0), enable(0), write(0), testin, customclk, customin(custombits-1 downto 0), customout(custombits-1 downto 0)); end generate; end generate; par : if paren = 1 generate dinp <= datain(63+8*paren downto 60+8*paren) & datain(63 downto 32) & datain(63+4*paren downto 60+4*paren) & datain(31 downto 0); dataout <= doutp(71 downto 68) & doutp(35 downto 32) & doutp(67 downto 36) & doutp(31-8+8*paren downto 0); x0 : syncram generic map (tech, abits, 36, testen, custombits) port map (clk, address, dinp(71 downto 36), doutp(71 downto 36), enable(1), write(1), testin, customclk, customin(2*custombits-1 downto custombits), customout(2*custombits-1 downto custombits)); x1 : syncram generic map (tech, abits, 36, testen, custombits) port map (clk, address, dinp(35 downto 0), doutp(35 downto 0), enable(0), write(0), testin, customclk, customin(custombits-1 downto 0), customout(custombits-1 downto 0)); end generate; end;

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 17:34:36 02/22/2016 -- Design Name: -- Module Name: C:/Users/Arthur/Documents/FPGA_temp/serial_out/tb_uart.vhd -- Project Name: serial_out -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: uart -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY tb_uart IS END tb_uart; ARCHITECTURE behavior OF tb_uart IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT uart PORT( clk : in std_logic; tx_data : in std_logic_vector(7 downto 0); tx_en : in std_logic; tx_ready : out std_logic; tx : out std_logic); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal tx_data : std_logic_vector(7 downto 0) := "10101011"; signal tx_en : std_logic := '0'; --Outputs signal tx_ready : std_logic; signal tx : std_logic; -- Clock period definitions constant clk_period : time := 31.25 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: uart PORT MAP ( clk => clk, tx_en => tx_en, tx_data => tx_data, tx_ready => tx_ready, tx => tx ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin wait for 5 us; -- insert stimulus here tx_en <= '1'; wait for 5 us; tx_en <= '0'; wait for 120 us; tx_en <= '1'; wait for 100 us; tx_en <= '0'; wait for 300 us; end process; END;

------------------------------------------------------------------------------- --! @project Serialized hardware implementation of Asconv128128 --! @author Michael Fivez --! @license This project is released under the GNU Public License. --! The license and distribution terms for this file may be --! found in the file LICENSE in this distribution or at --! http://www.gnu.org/licenses/gpl-3.0.txt --! @note This is an hardware implementation made for my graduation thesis --! at the KULeuven, in the COSIC department (year 2015-2016) --! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions', --! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications) ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Ascon_StateUpdate_datapath is port( Clk : in std_logic; -- Clock Reset : in std_logic; -- Reset (synchronous) -- Control signals RoundNr : in std_logic_vector(3 downto 0); -- biggest round is 12 sel1,sel2,sel3,sel4 : in std_logic_vector(1 downto 0); sel0 : in std_logic_vector(2 downto 0); selout : in std_logic; SelSbox : in std_logic_vector(1 downto 0); SelDiff : in std_logic_vector(2 downto 0); Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : in std_logic; SboxEnable : in std_logic; ActivateGen : in std_logic; GenSize : in std_logic_vector(3 downto 0); -- Data signals IV : in std_logic_vector(127 downto 0); Key : in std_logic_vector(127 downto 0); DataIn : in std_logic_vector(127 downto 0); DataOut : out std_logic_vector(127 downto 0) ); end entity Ascon_StateUpdate_datapath; architecture structural of Ascon_StateUpdate_datapath is -- constants constant EXTRAIV : std_logic_vector(63 downto 0) := x"80800c0800000000"; -- used in the initialization constant SEPCONSTANT : std_logic_vector(63 downto 0) := x"0000000000000001"; constant ADCONSTANT : std_logic_vector(63 downto 0) := x"8000000000000000"; -- Register signals signal SboxReg0In,SboxReg1In,SboxReg2In,SboxReg3In,SboxReg4In : std_logic_vector(63 downto 0); signal SboxReg0Out,SboxReg1Out,SboxReg2Out,SboxReg3Out,SboxReg4Out : std_logic_vector(63 downto 0); signal DiffReg0Out,DiffReg1Out,DiffReg2Out,DiffReg3Out,DiffReg4Out : std_logic_vector(63 downto 0); signal RegOutIn,RegOutOut : std_logic_vector(127 downto 0); -- Internal signals on datapath signal Sbox0In,Sbox1In,Sbox2In,Sbox3In,Sbox4In : std_logic_vector(15 downto 0); signal Sbox0Out,Sbox1Out,Sbox2Out,Sbox3Out,Sbox4Out : std_logic_vector(15 downto 0); signal Diff1In, Diff2In, Diff3In, DiffOut : std_logic_vector(63 downto 0); signal XorReg01,XorReg02,XorReg11,XorReg12 : std_logic_vector(63 downto 0); signal XorReg2,XorReg31,XorReg32,XorReg4 : std_logic_vector(63 downto 0); signal OutSig0,OutSig1 : std_logic_vector(127 downto 0); begin -- declare and connect all sub entities sboxregisters: entity work.Sbox_registers port map(Clk ,Sbox0Out, Sbox1Out, Sbox2Out, Sbox3Out, Sbox4Out, Sbox0In, Sbox1In, Sbox2In, Sbox3In, Sbox4In, SboxReg0In, SboxReg1In, SboxReg2In, SboxReg3In, SboxReg4In, SboxReg0Out, SboxReg1Out, SboxReg2Out, SboxReg3Out, SboxReg4Out, SelSbox, SboxEnable, Reg0En, Reg1En, Reg2En, Reg3En, Reg4En); sbox: entity work.Sbox port map(Sbox0In,Sbox1In,Sbox2In,Sbox3In,Sbox4In,RoundNr,Sbox0Out,Sbox1Out,Sbox2Out,Sbox3Out,Sbox4Out,SelSbox); difflayer: entity work.FullDiffusionLayer port map(Diff1In,Diff2In,Diff3In,DiffOut); outpgen: entity work.OutputGenerator port map(SboxReg0Out,SboxReg1Out,DataIn,GenSize,ActivateGen,XorReg01,XorReg11,OutSig0); -- ActivateGen is a bit that indicates decryption or not --------------------------------------------- ------ Combinatorial logic for a round ------ --------------------------------------------- datapath: process(Diff1In, Diff2In, Diff3In, DiffOut, SboxReg0In, SboxReg1In, SboxReg2In, SboxReg3In, SboxReg4In, OutSig0, OutSig1, XorReg01, XorReg02, XorReg11, XorReg12, XorReg2, XorReg31, XorReg32, XorReg4, SboxReg0Out, SboxReg1Out, SboxReg2Out, SboxReg3Out, SboxReg4Out, Key, IV, RegOutIn, RegOutOut, sel0, sel1, sel2, sel3, sel4, selout) is begin -- Set correct inputs in registers if sel0 = "000" then SboxReg0In <= DiffOut; elsif sel0 = "001" then SboxReg0In <= EXTRAIV; elsif sel0 = "010" then SboxReg0In <= XorReg01; elsif sel0 = "011" then SboxReg0In <= XorReg02; else SboxReg0In <= SboxReg0Out xor ADCONSTANT; end if; if sel1 = "00" then SboxReg1In <= DiffOut; elsif sel1 = "01" then SboxReg1In <= Key(127 downto 64); elsif sel1 = "10" then SboxReg1In <= XorReg11; else SboxReg1In <= XorReg12; end if; if sel2 = "00" then SboxReg2In <= DiffOut; elsif sel2 = "01" then SboxReg2In <= Key(63 downto 0); else SboxReg2In <= XorReg2; end if; if sel3 = "00" then SboxReg3In <= DiffOut; elsif sel3 = "01" then SboxReg3In <= IV(127 downto 64); elsif sel3 = "10" then SboxReg3In <= XorReg31; else SboxReg3In <= XorReg32; end if; if sel4 = "00" then SboxReg4In <= DiffOut; elsif sel4 = "01" then SboxReg4In <= IV(63 downto 0); elsif sel4 = "10" then SboxReg4In <= XorReg4; else SboxReg4In <= SboxReg4Out xor SEPCONSTANT; end if; XorReg02 <= SboxReg0Out xor Key(127 downto 64); XorReg12 <= SboxReg1Out xor Key(63 downto 0); XorReg2 <= SboxReg2Out xor Key(127 downto 64); XorReg31 <= SboxReg3Out xor Key(127 downto 64); XorReg32 <= SboxReg3Out xor Key(63 downto 0); XorReg4 <= SboxReg4Out xor Key(63 downto 0); -- Set output OutSig1(127 downto 64) <= XorReg31; OutSig1(63 downto 0) <= XorReg4; if selout = '0' then RegOutIn <= OutSig0; else RegOutIn <= OutSig1; end if; DataOut <= RegOutOut; if SelDiff = "000" then Diff1In(63 downto 64 - 19) <= SboxReg0Out(19 - 1 downto 0); Diff1In(63 - 19 downto 0) <= SboxReg0Out(63 downto 19); Diff2In(63 downto 64 - 28) <= SboxReg0Out(28 - 1 downto 0); Diff2In(63 - 28 downto 0) <= SboxReg0Out(63 downto 28); Diff3In <= SboxReg0Out; elsif SelDiff = "001" then Diff1In(63 downto 64 - 61) <= SboxReg1Out(61 - 1 downto 0); Diff1In(63 - 61 downto 0) <= SboxReg1Out(63 downto 61); Diff2In(63 downto 64 - 39) <= SboxReg1Out(39 - 1 downto 0); Diff2In(63 - 39 downto 0) <= SboxReg1Out(63 downto 39); Diff3In <= SboxReg1Out; elsif SelDiff = "010" then Diff1In(63 downto 64 - 1) <= SboxReg2Out(1 - 1 downto 0); Diff1In(63 - 1 downto 0) <= SboxReg2Out(63 downto 1); Diff2In(63 downto 64 - 6) <= SboxReg2Out(6 - 1 downto 0); Diff2In(63 - 6 downto 0) <= SboxReg2Out(63 downto 6); Diff3In <= SboxReg2Out; elsif SelDiff = "011" then Diff1In(63 downto 64 - 10) <= SboxReg3Out(10 - 1 downto 0); Diff1In(63 - 10 downto 0) <= SboxReg3Out(63 downto 10); Diff2In(63 downto 64 - 17) <= SboxReg3Out(17 - 1 downto 0); Diff2In(63 - 17 downto 0) <= SboxReg3Out(63 downto 17); Diff3In <= SboxReg3Out; else Diff1In(63 downto 64 - 7) <= SboxReg4Out(7 - 1 downto 0); Diff1In(63 - 7 downto 0) <= SboxReg4Out(63 downto 7); Diff2In(63 downto 64 - 41) <= SboxReg4Out(41 - 1 downto 0); Diff2In(63 - 41 downto 0) <= SboxReg4Out(63 downto 41); Diff3In <= SboxReg4Out; end if; end process datapath; --------------------------------------------- ------ The registers in the datapath -------- --------------------------------------------- registerdatapath : process(Clk,Reset) is begin if(Clk = '1' and Clk'event) then if Reset = '1' then -- synchronous reset RegOutOut <= (others => '0'); else if RegOutEn = '1' then RegOutOut <= RegOutIn; end if; end if; end if; end process registerdatapath; end architecture structural;

------------------------------------------------------------------------------- -- Title : UART -- Project : UART ------------------------------------------------------------------------------- -- File : MiniUart.vhd -- Author : Philippe CARTON -- (philippe.carton2@libertysurf.fr) -- Organization: -- Created : 15/12/2001 -- Last update : 8/1/2003 -- Platform : Foundation 3.1i -- Simulators : ModelSim 5.5b -- Synthesizers: Xilinx Synthesis -- Targets : Xilinx Spartan -- Dependency : IEEE std_logic_1164, Rxunit.vhd, Txunit.vhd, utils.vhd ------------------------------------------------------------------------------- -- Description: Uart (Universal Asynchronous Receiver Transmitter) for SoC. -- Wishbone compatable. ------------------------------------------------------------------------------- -- Copyright (c) notice -- This core adheres to the GNU public license -- ------------------------------------------------------------------------------- -- Revisions : -- Revision Number : -- Version : -- Date : -- Modifier : name <email> -- Description : -- ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity MINIUART is generic ( MainClockSpeed : integer; DefaultBaud : integer ); port ( -- Wishbone signals WB_CLK_I : in std_logic; -- clock WB_RST_I : in std_logic; -- Reset input WB_ADR_I : in std_logic_vector(1 downto 0); -- Adress bus WB_DAT_I : in std_logic_vector(7 downto 0); -- DataIn Bus WB_DAT_O : out std_logic_vector(7 downto 0); -- DataOut Bus WB_WE_I : in std_logic; -- Write Enable WB_STB_I : in std_logic; -- Strobe WB_ACK_O : out std_logic; -- Acknowledge -- process signals IntTx_O : out std_logic; -- Transmit interrupt: indicate waiting for Byte IntRx_O : out std_logic; -- Receive interrupt: indicate Byte received BR_Clk_I : in std_logic; -- Clock used for Transmit/Receive TxD_PAD_O : out std_logic; -- Tx RS232 Line RxD_PAD_I : in std_logic; -- Rx RS232 Line ESC_O : out std_logic; BREAK_O : out std_logic); end MINIUART; -- Architecture for UART for synthesis architecture Behaviour of MINIUART is component Counter port ( Clk : in std_logic; -- Clock Reset : in std_logic; -- Reset input CE : in std_logic; -- Chip Enable Count : in std_logic_vector (15 downto 0); -- Count revolution O : out std_logic); -- Output end component; component RxUnit port ( Clk : in std_logic; -- system clock signal Reset : in std_logic; -- Reset input Enable : in std_logic; -- Enable input ReadA : in std_logic; -- Async Read Received Byte RxD : in std_logic; -- RS-232 data input RxAv : out std_logic; -- Byte available DataO : out std_logic_vector(7 downto 0)); -- Byte received end component; component TxUnit port ( Clk : in std_logic; -- Clock signal Reset : in std_logic; -- Reset input Enable : in std_logic; -- Enable input LoadA : in std_logic; -- Asynchronous Load TxD : out std_logic; -- RS-232 data output Busy : out std_logic; -- Tx Busy DataI : in std_logic_vector(7 downto 0)); -- Byte to transmit end component; signal RxData : std_logic_vector(7 downto 0); -- Last Byte received signal RxData1 : std_logic_vector(7 downto 0); signal TxData : std_logic_vector(7 downto 0); -- Last bytes transmitted signal SReg : std_logic_vector(1 downto 0); -- Status register signal CReg : std_logic_vector(7 downto 2); -- Control register signal EnabRx : std_logic; -- Enable RX unit signal EnabTx : std_logic; -- Enable TX unit signal RxAv : std_logic; -- Data Received signal TxBusy : std_logic; -- Transmiter Busy signal ReadA : std_logic; -- Async Read receive buffer signal LoadA : std_logic; -- Async Load transmit buffer signal Sig0 : std_logic; -- gnd signal signal Sig1 : std_logic; -- vcc signal signal Divisor : std_logic_vector(15 downto 0); -- Baud Rate begin sig0 <= '0'; sig1 <= '1'; Uart_Rxrate : Counter -- Baud Rate adjust port map (BR_CLK_I, sig0, sig1, Divisor, EnabRx); Uart_Txrate : Counter -- 4 Divider for Tx port map (BR_CLK_I, Sig0, EnabRx, std_logic_vector(to_unsigned(4, 16)), EnabTx); Uart_TxUnit : TxUnit port map (BR_CLK_I, WB_RST_I, EnabTX, LoadA, TxD_PAD_O, TxBusy, TxData); Uart_RxUnit : RxUnit port map (BR_CLK_I, WB_RST_I, EnabRX, ReadA, RxD_PAD_I, RxAv, RxData); IntTx_O <= not TxBusy; IntRx_O <= RxAv; SReg(0) <= not TxBusy; SReg(1) <= RxAv; -- 16MHz x 1M = 64ms -- ESCctrl: process(WB_CLK_I) -- variable count : unsigned(19 downto 0); -- begin -- if Rising_Edge(WB_CLK_I) then -- if (WB_RST_I = '1') then -- ESC_O <= '1'; -- count := (others => '0'); -- elsif RxData = X"1B" then -- ESC_O <= '0'; -- count := (others => '1'); -- elsif count > 0 then -- count := count - 1; -- else -- ESC_O <= '1'; -- end if; -- end if; -- end process; BREAKctrl: process(WB_CLK_I) variable count : unsigned(7 downto 0); begin if Rising_Edge(WB_CLK_I) then RxData1 <= RxData; if (WB_RST_I = '1') then BREAK_O <= '1'; count := (others => '0'); elsif RxData1 /= X"1A" and RxData = X"1A" and CReg(7) = '1' then BREAK_O <= '0'; count := (others => '1'); elsif count > 0 then count := count - 1; else BREAK_O <= '1'; end if; end if; end process; ESC_O <= '0' when RxData = X"1B" and CReg(6) = '1' else '1'; -- Implements WishBone data exchange. -- Clocked on rising edge. Synchronous Reset RST_I WBctrl : process(WB_CLK_I, WB_RST_I, WB_STB_I, WB_WE_I, WB_ADR_I) variable StatM : std_logic_vector(4 downto 0); begin if Rising_Edge(WB_CLK_I) then if (WB_RST_I = '1') then ReadA <= '0'; LoadA <= '0'; Divisor <= std_logic_vector(to_unsigned(MainClockSpeed / 4 / DefaultBaud, 16)); CReg(7 downto 2) <= "000000"; else if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "00") then -- Write Byte to Tx TxData <= WB_DAT_I; LoadA <= '1'; -- Load signal else LoadA <= '0'; end if; if (WB_STB_I = '1' and WB_WE_I = '0' and WB_ADR_I = "00") then -- Read Byte from Rx ReadA <= '1'; -- Read signal else ReadA <= '0'; end if; if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "01") then -- Write Control CReg <= WB_DAT_I(7 downto 2); end if; if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "10") then -- Write Divisor Low Divisor(7 downto 0) <= WB_DAT_I; end if; if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "11") then -- Write Divisor High Divisor(15 downto 8) <= WB_DAT_I; end if; end if; end if; end process; WB_ACK_O <= WB_STB_I; WB_DAT_O <= RxData when WB_ADR_I = "00" else -- Read Byte from Rx CReg & SReg when WB_ADR_I = "01" else -- Read Control/Status Reg Divisor(7 downto 0) when WB_ADR_I = "10" else -- Read Divisor Low Divisor(15 downto 8) when WB_ADR_I = "11" else -- Read Divisor Low "00000000"; end Behaviour;

-- NEED RESULT: ARCH00246: All formal modes and classes are allowed default classes tested passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00246 -- -- AUTHOR: -- -- D. Hyman -- -- TEST OBJECTIVES: -- -- 2.1.1 (1) -- 2.1.1 (2) -- 2.1.1 (3) -- 2.1.1 (4) -- 2.1.1 (5) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00246) -- ENT00246_Test_Bench(ARCH00246_Test_Bench) -- -- REVISION HISTORY: -- -- 15-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.all ; architecture ARCH00246 of E00000 is signal s : integer := 25; -- the following procedure tests 2.1.1 (2) -- it also tests 2.1.1 (1) by assigning variables to the -- inout and out parameters procedure proc_with_all_formal_modes ( x : in integer; y : inout integer; z : out integer) is begin z := y; y := x; end proc_with_all_formal_modes ; -- the following procedure tests 2.1.1 (3) procedure proc_with_all_formal_classes ( constant c : integer; variable v : out integer; signal s : integer) is begin v := c + s ; end proc_with_all_formal_classes ; -- the following function tests 2.1.1 (4) function func_with_all_formal_modes ( x : in integer) return integer is begin return x + 1; end func_with_all_formal_modes ; -- the following function tests 2.1.1 (5) function func_with_all_formal_classes ( constant c : integer; signal s : integer) return integer is begin return c + s; end func_with_all_formal_classes ; begin P : process constant c : integer := 101; variable v : integer := 150; variable w : integer := 200; variable x : integer := 300; variable y : integer := 400; variable z : integer := 500; begin proc_with_all_formal_modes (x, y, z); proc_with_all_formal_classes (c, v, s) ; test_report ( "ARCH00246" , "All formal modes and classes are allowed " & "default classes tested", (func_with_all_formal_modes (w) = w+1) and (func_with_all_formal_classes (c, s) = c+25) and (v = c+25) and (z = 400) and (y = 300) and (x = 300) ) ; wait ; end process P ; end ARCH00246 ; entity ENT00246_Test_Bench is end ENT00246_Test_Bench ; architecture ARCH00246_Test_Bench of ENT00246_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00246 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00246_Test_Bench ;

-- -*- vhdl -*- ------------------------------------------------------------------------------- -- Copyright (c) 2012, The CARPE Project, All rights reserved. -- -- See the AUTHORS file for individual contributors. -- -- -- -- Copyright and related rights are licensed under the Solderpad -- -- Hardware License, Version 0.51 (the "License"); you may not use this -- -- file except in compliance with the License. You may obtain a copy of -- -- the License at http://solderpad.org/licenses/SHL-0.51. -- -- -- -- Unless required by applicable law or agreed to in writing, software, -- -- hardware and materials distributed under this License is distributed -- -- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -- -- either express or implied. See the License for the specific language -- -- governing permissions and limitations under the License. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity syncram_2r1w_inferred is generic ( addr_bits : natural := 6; data_bits : natural := 32; write_first : boolean := true ); port ( clk : in std_ulogic; we : in std_ulogic; waddr : in std_ulogic_vector((addr_bits-1) downto 0); wdata : in std_ulogic_vector((data_bits-1) downto 0); re1 : in std_ulogic; raddr1 : in std_ulogic_vector((addr_bits-1) downto 0); rdata1 : out std_ulogic_vector((data_bits-1) downto 0); re2 : in std_ulogic; raddr2 : in std_ulogic_vector((addr_bits-1) downto 0); rdata2 : out std_ulogic_vector((data_bits-1) downto 0) ); end;

------------------------------------------------------------------------------- -- -- MSX1 FPGA project -- -- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com) -- -- All rights reserved -- -- Redistribution and use in source and synthezised forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- -- Redistributions in synthesized form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- Neither the name of the author nor the names of other contributors may -- be used to endorse or promote products derived from this software without -- specific prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- Please report bugs to the author, but before you do so, please -- make sure that this is not a derivative work and that -- you have the latest version of this file. -- ------------------------------------------------------------------------------- -- -- Generic single port RAM. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity spram is generic ( addr_width_g : integer := 8; data_width_g : integer := 8 ); port ( clk_i : in std_logic; we_i : in std_logic; addr_i : in std_logic_vector(addr_width_g-1 downto 0); data_i : in std_logic_vector(data_width_g-1 downto 0); data_o : out std_logic_vector(data_width_g-1 downto 0) ); end spram; library ieee; use ieee.numeric_std.all; architecture rtl of spram is type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); signal ram_q : ram_t -- pragma translate_off := (others => (others => '0')) -- pragma translate_on ; signal read_addr_q : unsigned(addr_width_g-1 downto 0); begin process (clk_i) begin if rising_edge(clk_i) then if we_i = '1' then ram_q(to_integer(unsigned(addr_i))) <= data_i; end if; read_addr_q <= unsigned(addr_i); end if; end process; data_o <= ram_q(to_integer(read_addr_q)); end rtl;

-------------------------------------------------------------------------------- -- -- FIFO Generator Core Demo Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: fg_tb_dverif.vhd -- -- Description: -- Used for FIFO read interface stimulus generation and data checking -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_misc.all; LIBRARY work; USE work.fg_tb_pkg.ALL; ENTITY fg_tb_dverif IS GENERIC( C_DIN_WIDTH : INTEGER := 0; C_DOUT_WIDTH : INTEGER := 0; C_USE_EMBEDDED_REG : INTEGER := 0; C_CH_TYPE : INTEGER := 0; TB_SEED : INTEGER := 2 ); PORT( RESET : IN STD_LOGIC; RD_CLK : IN STD_LOGIC; PRC_RD_EN : IN STD_LOGIC; EMPTY : IN STD_LOGIC; DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); RD_EN : OUT STD_LOGIC; DOUT_CHK : OUT STD_LOGIC ); END ENTITY; ARCHITECTURE fg_dv_arch OF fg_tb_dverif IS CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0); CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8); CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH); SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL data_chk : STD_LOGIC := '1'; SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0); SIGNAL rd_en_i : STD_LOGIC := '0'; SIGNAL pr_r_en : STD_LOGIC := '0'; SIGNAL rd_en_d1 : STD_LOGIC := '1'; SIGNAL rd_d_sel_d1 : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0):= (OTHERS => '0'); BEGIN DOUT_CHK <= data_chk; RD_EN <= rd_en_i; rd_en_i <= PRC_RD_EN; rd_en_d1 <= '1'; data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE ------------------------------------------------------- -- Expected data generation and checking for data_fifo ------------------------------------------------------- PROCESS (RD_CLK,RESET) BEGIN IF (RESET = '1') THEN rd_d_sel_d1 <= (OTHERS => '0'); ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF (rd_en_i = '1' AND EMPTY = '0' AND rd_en_d1 = '1') THEN rd_d_sel_d1 <= rd_d_sel_d1+"1"; END IF; END IF; END PROCESS; pr_r_en <= (AND_REDUCE(rd_d_sel_d1)) AND rd_en_i AND NOT EMPTY; expected_dout <= rand_num(C_DIN_WIDTH-C_DOUT_WIDTH*conv_integer(rd_d_sel_d1)-1 DOWNTO C_DIN_WIDTH-C_DOUT_WIDTH*(conv_integer(rd_d_sel_d1)+1)); gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE rd_gen_inst2:fg_tb_rng GENERIC MAP( WIDTH => 8, SEED => TB_SEED+N ) PORT MAP( CLK => RD_CLK, RESET => RESET, RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N), ENABLE => pr_r_en ); END GENERATE; PROCESS (RD_CLK,RESET) BEGIN IF(RESET = '1') THEN data_chk <= '0'; ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF(EMPTY = '0') THEN IF(DATA_OUT = expected_dout) THEN data_chk <= '0'; ELSE data_chk <= '1'; END IF; END IF; END IF; END PROCESS; END GENERATE data_fifo_chk; END ARCHITECTURE;

------------------------------------------------------------------------------- -- axi_datamover_s2mm_full_wrap.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_s2mm_full_wrap.vhd -- -- Description: -- This file implements the DataMover S2MM FULL Wrapper. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all ; -- axi_datamover Library Modules library axi_datamover_v5_1_10; use axi_datamover_v5_1_10.axi_datamover_reset ; use axi_datamover_v5_1_10.axi_datamover_cmd_status ; use axi_datamover_v5_1_10.axi_datamover_pcc ; use axi_datamover_v5_1_10.axi_datamover_ibttcc ; use axi_datamover_v5_1_10.axi_datamover_indet_btt ; use axi_datamover_v5_1_10.axi_datamover_s2mm_realign ; use axi_datamover_v5_1_10.axi_datamover_addr_cntl ; use axi_datamover_v5_1_10.axi_datamover_wrdata_cntl ; use axi_datamover_v5_1_10.axi_datamover_wr_status_cntl; Use axi_datamover_v5_1_10.axi_datamover_skid2mm_buf ; Use axi_datamover_v5_1_10.axi_datamover_skid_buf ; Use axi_datamover_v5_1_10.axi_datamover_wr_sf ; ------------------------------------------------------------------------------- entity axi_datamover_s2mm_full_wrap is generic ( C_INCLUDE_S2MM : Integer range 0 to 2 := 1; -- Specifies the type of S2MM function to include -- 0 = Omit S2MM functionality -- 1 = Full S2MM Functionality -- 2 = Lite S2MM functionality C_S2MM_AWID : Integer range 0 to 255 := 9; -- Specifies the constant value to output on -- the ARID output port C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the S2MM ID port C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the S2MM Master Stream Data -- Channel data bus C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit S2MM Status FIFO -- 1 = Include S2MM Status FIFO C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the S2MM Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0; -- Specifies if DRE is to be included in the S2MM function -- 0 = Omit DRE -- 1 = Include DRE C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the S2MM function C_S2MM_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the S2MM Command Interface C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0; -- Specifies if support for indeterminate packet lengths -- are to be received on the input Stream interface -- 0 = Omit support (User MUST transfer the exact number of -- bytes on the Stream interface as specified in the BTT -- field of the Corresponding DataMover Command) -- 1 = Include support for indeterminate packet lengths -- This causes FIFOs to be added and "Store and Forward" -- behavior of the S2MM function C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3; -- This parameter specifies the depth of the S2MM internal -- address pipeline queues in the Write Address Controller -- and the Write Data Controller. Increasing this value will -- allow more Write Addresses to be issued to the AXI4 Write -- Address Channel before transmission of the associated -- write data on the Write Data Channel. C_TAG_WIDTH : Integer range 1 to 8 := 4 ; -- Width of the TAG field C_INCLUDE_S2MM_GP_SF : Integer range 0 to 1 := 1 ; -- This parameter specifies the inclusion/omission of the -- S2MM (Write) General Purpose Store and Forward function -- 0 = Omit GP Store and Forward -- 1 = Include GP Store and Forward C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1; C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1; C_ENABLE_SKID_BUF : string := "11111"; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- S2MM Primary Clock and Reset inputs ---------------------------- s2mm_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- ------------------------------------------------------------------- -- S2MM Primary Reset input --------------------------------------- s2mm_aresetn : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------------- -- S2MM Halt request input control -------------------------------- s2mm_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- S2MM Halt Complete status flag -- s2mm_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------------------- -- S2MM Error discrete output ------------------------------------- s2mm_err : Out std_logic; -- -- Composite Error indication -- ------------------------------------------------------------------- -- Optional Command and Status Clock and Reset ------------------- -- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 -- -- s2mm_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- s2mm_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- ------------------------------------------------------------------ -- User Command Interface Ports (AXI Stream) ----------------------------------------------------- s2mm_cmd_wvalid : in std_logic; -- s2mm_cmd_wready : out std_logic; -- s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); -- -------------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) -------------------------------------------------------- s2mm_sts_wvalid : out std_logic; -- s2mm_sts_wready : in std_logic; -- s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); -- s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); -- s2mm_sts_wlast : out std_logic; -- ---------------------------------------------------------------------------------------------------- -- Address posting controls --------------------------------------- s2mm_allow_addr_req : in std_logic; -- s2mm_addr_req_posted : out std_logic; -- s2mm_wr_xfer_cmplt : out std_logic; -- s2mm_ld_nxt_len : out std_logic; -- s2mm_wr_len : out std_logic_vector(7 downto 0); -- ------------------------------------------------------------------- -- S2MM AXI Address Channel I/O -------------------------------------- s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- s2mm_awlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- s2mm_awsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- s2mm_awburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- s2mm_awprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- s2mm_awcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel PROT output -- s2mm_awuser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel PROT output -- -- s2mm_awvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- s2mm_awready : in std_logic; -- -- AXI Address Channel READY input -- ----------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ----------- -- s2mm__awlock : out std_logic_vector(2 downto 0); -- -- s2mm__awcache : out std_logic_vector(4 downto 0); -- -- s2mm__awqos : out std_logic_vector(3 downto 0); -- -- s2mm__awregion : out std_logic_vector(3 downto 0); -- ----------------------------------------------------------------------- -- S2MM AXI MMap Write Data Channel I/O --------------------------------------------- s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); -- s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); -- s2mm_wlast : Out std_logic; -- s2mm_wvalid : Out std_logic; -- s2mm_wready : In std_logic; -- -------------------------------------------------------------------------------------- -- S2MM AXI MMap Write response Channel I/O ----------------------------------------- s2mm_bresp : In std_logic_vector(1 downto 0); -- s2mm_bvalid : In std_logic; -- s2mm_bready : Out std_logic; -- -------------------------------------------------------------------------------------- -- S2MM AXI Master Stream Channel I/O ----------------------------------------------- s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); -- s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); -- s2mm_strm_wlast : In std_logic; -- s2mm_strm_wvalid : In std_logic; -- s2mm_strm_wready : Out std_logic; -- -------------------------------------------------------------------------------------- -- Testing Support I/O ------------------------------------------ s2mm_dbg_sel : in std_logic_vector( 3 downto 0); -- s2mm_dbg_data : out std_logic_vector(31 downto 0) -- ----------------------------------------------------------------- ); end entity axi_datamover_s2mm_full_wrap; architecture implementation of axi_datamover_s2mm_full_wrap is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations ---------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: func_calc_wdemux_sel_bits -- -- Function Description: -- This function calculates the number of address bits needed for -- the Write Strobe demux select control. -- ------------------------------------------------------------------- function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is Variable num_addr_bits_needed : Integer range 1 to 7 := 1; begin case mmap_dwidth_value is when 32 => num_addr_bits_needed := 2; when 64 => num_addr_bits_needed := 3; when 128 => num_addr_bits_needed := 4; when 256 => num_addr_bits_needed := 5; when 512 => num_addr_bits_needed := 6; when others => -- 1024 bits num_addr_bits_needed := 7; end case; Return (num_addr_bits_needed); end function func_calc_wdemux_sel_bits; ------------------------------------------------------------------- -- Function -- -- Function Name: func_include_dre -- -- Function Description: -- This function desides if conditions are right for allowing DRE -- inclusion. -- ------------------------------------------------------------------- function func_include_dre (need_dre : integer; needed_data_width : integer) return integer is Variable include_dre : Integer := 0; begin if (need_dre = 1 and needed_data_width < 128 and needed_data_width > 8) Then include_dre := 1; Else include_dre := 0; End if; Return (include_dre); end function func_include_dre; ------------------------------------------------------------------- -- Function -- -- Function Name: func_get_align_width -- -- Function Description: -- This function calculates the needed DRE alignment port width\ -- based upon the inclusion of DRE and the needed bit width of the -- DRE. -- ------------------------------------------------------------------- function func_get_align_width (dre_included : integer; dre_data_width : integer) return integer is Variable align_port_width : Integer := 1; begin if (dre_included = 1) then If (dre_data_width = 64) Then align_port_width := 3; Elsif (dre_data_width = 32) Then align_port_width := 2; else -- 16 bit data width align_port_width := 1; End if; else align_port_width := 1; end if; Return (align_port_width); end function func_get_align_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_set_status_width -- -- Function Description: -- This function sets the width of the Status pipe depending on the -- Store and Forward inclusion or ommision. -- ------------------------------------------------------------------- function funct_set_status_width (store_forward_enabled : integer) return integer is Variable temp_status_bit_width : Integer := 8; begin If (store_forward_enabled = 1) Then temp_status_bit_width := 32; Else temp_status_bit_width := 8; End if; Return (temp_status_bit_width); end function funct_set_status_width; ------------------------------------------------------------------- -- Function -- -- Function Name: get_bits_needed -- -- Function Description: -- -- ------------------------------------------------------------------- function get_bits_needed (max_bytes : integer) return integer is Variable fvar_temp_bit_width : Integer := 1; begin if (max_bytes <= 1) then fvar_temp_bit_width := 1; elsif (max_bytes <= 3) then fvar_temp_bit_width := 2; elsif (max_bytes <= 7) then fvar_temp_bit_width := 3; elsif (max_bytes <= 15) then fvar_temp_bit_width := 4; elsif (max_bytes <= 31) then fvar_temp_bit_width := 5; elsif (max_bytes <= 63) then fvar_temp_bit_width := 6; elsif (max_bytes <= 127) then fvar_temp_bit_width := 7; elsif (max_bytes <= 255) then fvar_temp_bit_width := 8; elsif (max_bytes <= 511) then fvar_temp_bit_width := 9; elsif (max_bytes <= 1023) then fvar_temp_bit_width := 10; elsif (max_bytes <= 2047) then fvar_temp_bit_width := 11; elsif (max_bytes <= 4095) then fvar_temp_bit_width := 12; elsif (max_bytes <= 8191) then fvar_temp_bit_width := 13; else -- 8k - 16K fvar_temp_bit_width := 14; end if; Return (fvar_temp_bit_width); end function get_bits_needed; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_rnd2pwr_of_2 -- -- Function Description: -- Rounds the input value up to the nearest power of 2 between -- 128 and 8192. -- ------------------------------------------------------------------- function funct_rnd2pwr_of_2 (input_value : integer) return integer is Variable temp_pwr2 : Integer := 128; begin if (input_value <= 128) then temp_pwr2 := 128; elsif (input_value <= 256) then temp_pwr2 := 256; elsif (input_value <= 512) then temp_pwr2 := 512; elsif (input_value <= 1024) then temp_pwr2 := 1024; elsif (input_value <= 2048) then temp_pwr2 := 2048; elsif (input_value <= 4096) then temp_pwr2 := 4096; else temp_pwr2 := 8192; end if; Return (temp_pwr2); end function funct_rnd2pwr_of_2; ------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_need_realigner -- -- Function Description: -- Determines if the Realigner module needs to be included. -- ------------------------------------------------------------------- function funct_need_realigner (indet_btt_enabled : integer; dre_included : integer; gp_sf_included : integer) return integer is Variable temp_val : Integer := 0; begin If ((indet_btt_enabled = 1) or (dre_included = 1) or (gp_sf_included = 1)) Then temp_val := 1; else temp_val := 0; End if; Return (temp_val); end function funct_need_realigner; ------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_sf_offset_width -- -- Function Description: -- This function calculates the address offset width needed by -- the GP Store and Forward module with data packing. -- ------------------------------------------------------------------- function funct_get_sf_offset_width (mmap_dwidth : integer; stream_dwidth : integer) return integer is Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth; Variable fvar_temp_offset_width : Integer := 1; begin case FCONST_WIDTH_RATIO is when 1 => fvar_temp_offset_width := 1; when 2 => fvar_temp_offset_width := 1; when 4 => fvar_temp_offset_width := 2; when 8 => fvar_temp_offset_width := 3; when 16 => fvar_temp_offset_width := 4; when 32 => fvar_temp_offset_width := 5; when 64 => fvar_temp_offset_width := 6; when others => fvar_temp_offset_width := 7; end case; Return (fvar_temp_offset_width); end function funct_get_sf_offset_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_stream_width2use -- -- Function Description: -- This function calculates the Stream width to use for S2MM -- modules downstream from the upsizing Store and Forward. If -- Store and forward is present, then the effective Stream width -- is the MMAP data width. If no Store and Forward then the Stream -- width is the input Stream width from the User. -- ------------------------------------------------------------------- function funct_get_stream_width2use (mmap_data_width : integer; stream_data_width : integer; sf_enabled : integer) return integer is Variable fvar_temp_width : Integer := 32; begin If (sf_enabled > 0) Then fvar_temp_width := mmap_data_width; Else fvar_temp_width := stream_data_width; End if; Return (fvar_temp_width); end function funct_get_stream_width2use; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_bytes_per_dbeat -- -- Function Description: -- This function calculates the number of bytes transfered per -- databeat on the MMap AXI4 Write Data Channel by the S2MM. The -- value is based on input parameterization of included functions -- in the S2MM block. -- ------------------------------------------------------------------- function funct_get_bytes_per_dbeat (ibtt_enabled : integer ; gpsf_enabled : integer ; stream_dwidth : integer ; mmap_dwidth : integer ) return integer is Variable fvar_temp_bytes_per_xfer : Integer := 4; begin If (ibtt_enabled > 0 or gpsf_enabled > 0) Then -- transfers will be upsized to mmap data width fvar_temp_bytes_per_xfer := mmap_dwidth/8; Else -- transfers will be in stream data widths (may be narrow transfers on mmap) fvar_temp_bytes_per_xfer := stream_dwidth/8; End if; Return (fvar_temp_bytes_per_xfer); end function funct_get_bytes_per_dbeat; -- Constant Declarations ---------------------------------------- Constant SF_ENABLED : integer := C_INCLUDE_S2MM_GP_SF + C_S2MM_SUPPORT_INDET_BTT; Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_S2MM_MDATA_WIDTH, C_S2MM_SDATA_WIDTH, SF_ENABLED); Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant IS_NOT_MM2S : integer range 0 to 1 := 0; Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID; Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH; Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH; Constant S2MM_MDATA_WIDTH : integer range 32 to 1024 := C_S2MM_MDATA_WIDTH; Constant S2MM_SDATA_WIDTH : integer range 8 to 1024 := C_S2MM_SDATA_WIDTH; Constant S2MM_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH; Constant S2MM_CMD_WIDTH : integer := (S2MM_TAG_WIDTH+S2MM_ADDR_WIDTH+32); Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := C_INCLUDE_S2MM_STSFIFO; Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH; Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC; Constant S2MM_BURST_SIZE : integer range 2 to 256 := C_S2MM_BURST_SIZE; Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH); Constant S2MM_BTT_USED : integer range 8 to 23 := C_S2MM_BTT_USED; Constant BITS_PER_BYTE : integer := 8; Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_S2MM_DRE, S2MM_SDATA_WIDTH); Constant DRE_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant S2MM_DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_S2MM_DRE, S2MM_SDATA_WIDTH); Constant DRE_SUPPORT_SCATTER : integer range 0 to 1 := 1; Constant ENABLE_INDET_BTT_SF : integer range 0 to 1 := C_S2MM_SUPPORT_INDET_BTT; Constant ENABLE_GP_SF : integer range 0 to 1 := C_INCLUDE_S2MM_GP_SF ; Constant BYTES_PER_MMAP_DBEAT : integer := funct_get_bytes_per_dbeat(ENABLE_INDET_BTT_SF , ENABLE_GP_SF , S2MM_SDATA_WIDTH , S2MM_MDATA_WIDTH); Constant MAX_BYTES_PER_BURST : integer := BYTES_PER_MMAP_DBEAT*S2MM_BURST_SIZE; Constant IBTT_XFER_BYTES_WIDTH : integer := get_bits_needed(MAX_BYTES_PER_BURST); Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2; -- 2 added for going -- full thresholding -- in WSC Constant WSC_STATUS_WIDTH : integer range 8 to 32 := funct_set_status_width(ENABLE_INDET_BTT_SF); Constant WSC_BYTES_RCVD_WIDTH : integer range 8 to 32 := S2MM_BTT_USED; Constant ADD_REALIGNER : integer := funct_need_realigner(ENABLE_INDET_BTT_SF , INCLUDE_S2MM_DRE , ENABLE_GP_SF); -- Calculates the minimum needed depth of the GP Store and Forward FIFO -- based on the S2MM pipeline depth and the max allowed Burst length Constant PIPEDEPTH_BURST_LEN_PROD : integer := (ADDR_CNTL_FIFO_DEPTH+2) * S2MM_BURST_SIZE; -- Assigns the depth of the optional GP Store and Forward FIFO to the nearest -- power of 2 Constant SF_FIFO_DEPTH : integer range 128 to 8192 := funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD); -- Calculate the width of the Store and Forward Starting Address Offset bus Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(S2MM_MDATA_WIDTH, S2MM_SDATA_WIDTH); -- Signal Declarations ------------------------------------------ signal sig_cmd_stat_rst_user : std_logic := '0'; signal sig_cmd_stat_rst_int : std_logic := '0'; signal sig_mmap_rst : std_logic := '0'; signal sig_stream_rst : std_logic := '0'; signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0'); signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd2mstr_cmd_valid : std_logic := '0'; signal sig_mst2cmd_cmd_ready : std_logic := '0'; signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0'); signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_cmd_cmplt : std_logic := '0'; signal sig_mstr2addr_calc_error : std_logic := '0'; signal sig_mstr2addr_cmd_valid : std_logic := '0'; signal sig_addr2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_drr : std_logic := '0'; signal sig_mstr2data_eof : std_logic := '0'; signal sig_mstr2data_sequential : std_logic := '0'; signal sig_mstr2data_calc_error : std_logic := '0'; signal sig_mstr2data_cmd_last : std_logic := '0'; signal sig_mstr2data_cmd_valid : std_logic := '0'; signal sig_data2mstr_cmd_ready : std_logic := '0'; signal sig_addr2data_addr_posted : std_logic := '0'; signal sig_data2addr_data_rdy : std_logic := '0'; signal sig_data2all_tlast_error : std_logic := '0'; signal sig_data2all_dcntlr_halted : std_logic := '0'; signal sig_addr2wsc_calc_error : std_logic := '0'; signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0'; signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0'); signal sig_data2wsc_cmd_empty : std_logic := '0'; signal sig_data2wsc_calc_err : std_logic := '0'; signal sig_data2wsc_cmd_cmplt : std_logic := '0'; signal sig_data2wsc_last_err : std_logic := '0'; signal sig_calc2dm_calc_err : std_logic := '0'; signal sig_wsc2stat_status : std_logic_vector(WSC_STATUS_WIDTH-1 downto 0) := (others => '0'); signal sig_stat2wsc_status_ready : std_logic := '0'; signal sig_wsc2stat_status_valid : std_logic := '0'; signal sig_wsc2mstr_halt_pipe : std_logic := '0'; signal sig_data2wsc_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_wvalid : std_logic := '0'; signal sig_skid2data_wready : std_logic := '0'; signal sig_data2skid_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_data2skid_wlast : std_logic := '0'; signal sig_skid2axi_wvalid : std_logic := '0'; signal sig_axi2skid_wready : std_logic := '0'; signal sig_skid2axi_wdata : std_logic_vector(S2MM_MDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_skid2axi_wstrb : std_logic_vector((S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_skid2axi_wlast : std_logic := '0'; signal sig_data2wsc_sof : std_logic := '0'; signal sig_data2wsc_eof : std_logic := '0'; signal sig_data2wsc_valid : std_logic := '0'; signal sig_wsc2data_ready : std_logic := '0'; signal sig_data2wsc_eop : std_logic := '0'; signal sig_data2wsc_bytes_rcvd : std_logic_vector(WSC_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0'); signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_sf2pcc_xfer_valid : std_logic := '0'; signal sig_pcc2sf_xfer_ready : std_logic := '0'; signal sig_sf2pcc_cmd_cmplt : std_logic := '0'; signal sig_sf2pcc_packet_eop : std_logic := '0'; signal sig_sf2pcc_xfer_bytes : std_logic_vector(IBTT_XFER_BYTES_WIDTH-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tvalid : std_logic := '0'; signal sig_wdc2ibtt_tready : std_logic := '0'; signal sig_ibtt2wdc_tdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tlast : std_logic := '0'; signal sig_ibtt2wdc_eop : std_logic := '0'; signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(7 downto 0) := (others => '0'); signal sig_dre2ibtt_tvalid : std_logic := '0'; signal sig_ibtt2dre_tready : std_logic := '0'; signal sig_dre2ibtt_tdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_dre2ibtt_tstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_dre2ibtt_tlast : std_logic := '0'; signal sig_dre2ibtt_eop : std_logic := '0'; signal sig_dre2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2dre_cmd_valid : std_logic := '0'; signal sig_mstr2dre_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_dre_src_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_dre_dest_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_btt : std_logic_vector(S2MM_BTT_USED-1 downto 0) := (others => '0'); signal sig_mstr2dre_drr : std_logic := '0'; signal sig_mstr2dre_eof : std_logic := '0'; signal sig_mstr2dre_cmd_cmplt : std_logic := '0'; signal sig_mstr2dre_calc_error : std_logic := '0'; signal sig_realign2wdc_eop_error : std_logic := '0'; signal sig_dre2all_halted : std_logic := '0'; signal sig_rst2all_stop_request : std_logic := '0'; signal sig_data2rst_stop_cmplt : std_logic := '0'; signal sig_addr2rst_stop_cmplt : std_logic := '0'; signal sig_data2addr_stop_req : std_logic := '0'; signal sig_wsc2rst_stop_cmplt : std_logic := '0'; signal sig_data2skid_halt : std_logic := '0'; signal skid2dre_wvalid : std_logic := '0'; signal dre2skid_wready : std_logic := '0'; signal skid2dre_wdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0'); signal skid2dre_wstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal skid2dre_wlast : std_logic := '0'; signal sig_s2mm_allow_addr_req : std_logic := '0'; signal sig_ok_to_post_wr_addr : std_logic := '0'; signal sig_s2mm_addr_req_posted : std_logic := '0'; signal sig_s2mm_wr_xfer_cmplt : std_logic := '0'; signal sig_s2mm_ld_nxt_len : std_logic := '0'; signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_ibtt2wdc_error : std_logic := '0'; signal sig_sf_strt_addr_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_cache2mstr_command : std_logic_vector (7 downto 0); signal s2mm_awcache_int : std_logic_vector (3 downto 0); signal s2mm_awuser_int : std_logic_vector (3 downto 0); begin --(architecture implementation) -- Debug/Test Port Assignments s2mm_dbg_data <= sig_dbg_data_mux_out; -- Note that only the s2mm_dbg_sel(0) is used at this time sig_dbg_data_mux_out <= sig_dbg_data_1 When (s2mm_dbg_sel(0) = '1') else sig_dbg_data_0 ; sig_dbg_data_0 <= X"CAFE1111" ; -- 32 bit Constant indicating S2MM FULL type sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ; sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ; sig_dbg_data_1(2) <= sig_mmap_rst ; sig_dbg_data_1(3) <= sig_stream_rst ; sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ; sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ; sig_dbg_data_1(6) <= sig_stat2wsc_status_ready; sig_dbg_data_1(7) <= sig_wsc2stat_status_valid; sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error --sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADD_DEBUG_EOP -- -- If Generate Description: -- -- This IfGen adds in the EOP status marker to the debug -- vector data when Indet BTT Store and Forward is enabled. -- ------------------------------------------------------------ GEN_ADD_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 1) generate begin sig_dbg_data_1(19) <= sig_wsc2stat_status(31) ; -- EOP Marker end generate GEN_ADD_DEBUG_EOP; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_DEBUG_EOP -- -- If Generate Description: -- -- This IfGen zeros the debug vector bit used for the EOP -- status marker when Indet BTT Store and Forward is not -- enabled. -- ------------------------------------------------------------ GEN_NO_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 0) generate begin sig_dbg_data_1(19) <= '0' ; -- EOP Marker end generate GEN_NO_DEBUG_EOP; ---- End of Debug/Test Support -------------------------------- -- Assign the Address posting control outputs s2mm_addr_req_posted <= sig_s2mm_addr_req_posted ; s2mm_wr_xfer_cmplt <= sig_s2mm_wr_xfer_cmplt ; s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len ; s2mm_wr_len <= sig_s2mm_wr_len ; -- Write Data Channel I/O s2mm_wvalid <= sig_skid2axi_wvalid; sig_axi2skid_wready <= s2mm_wready ; s2mm_wdata <= sig_skid2axi_wdata ; s2mm_wlast <= sig_skid2axi_wlast ; GEN_S2MM_TKEEP_ENABLE2 : if C_ENABLE_S2MM_TKEEP = 1 generate begin s2mm_wstrb <= sig_skid2axi_wstrb ; end generate GEN_S2MM_TKEEP_ENABLE2; GEN_S2MM_TKEEP_DISABLE2 : if C_ENABLE_S2MM_TKEEP = 0 generate begin s2mm_wstrb <= (others => '1'); end generate GEN_S2MM_TKEEP_DISABLE2; GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate begin -- Cache signal tie-off s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96); end generate GEN_CACHE; GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate begin -- Cache signal tie-off s2mm_awcache <= s2mm_awcache_int; -- pre Interface-X guidelines for Masters s2mm_awuser <= s2mm_awuser_int; -- pre Interface-X guidelines for Masters sig_s2mm_cache_data <= s2mm_cmd_wdata(79+(C_S2MM_ADDR_WIDTH-32) downto 72+(C_S2MM_ADDR_WIDTH-32)); -- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96); end generate GEN_CACHE2; -- Internal error output discrete s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error; -- Rip the used portion of the Command Interface Command Data -- and throw away the padding sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0); ------------------------------------------------------------ -- Instance: I_RESET -- -- Description: -- Reset Block -- ------------------------------------------------------------ I_RESET : entity axi_datamover_v5_1_10.axi_datamover_reset generic map ( C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ) port map ( primary_aclk => s2mm_aclk , primary_aresetn => s2mm_aresetn , secondary_awclk => s2mm_cmdsts_awclk , secondary_aresetn => s2mm_cmdsts_aresetn , halt_req => s2mm_halt , halt_cmplt => s2mm_halt_cmplt , flush_stop_request => sig_rst2all_stop_request , data_cntlr_stopped => sig_data2rst_stop_cmplt , addr_cntlr_stopped => sig_addr2rst_stop_cmplt , aux1_stopped => sig_wsc2rst_stop_cmplt , aux2_stopped => LOGIC_HIGH , cmd_stat_rst_user => sig_cmd_stat_rst_user , cmd_stat_rst_int => sig_cmd_stat_rst_int , mmap_rst => sig_mmap_rst , stream_rst => sig_stream_rst ); ------------------------------------------------------------ -- Instance: I_CMD_STATUS -- -- Description: -- Command and Status Interface Block -- ------------------------------------------------------------ I_CMD_STATUS : entity axi_datamover_v5_1_10.axi_datamover_cmd_status generic map ( C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO , C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH , C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_STS_WIDTH => WSC_STATUS_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , secondary_awclk => s2mm_cmdsts_awclk , user_reset => sig_cmd_stat_rst_user , internal_reset => sig_cmd_stat_rst_int , cmd_wvalid => s2mm_cmd_wvalid , cmd_wready => s2mm_cmd_wready , cmd_wdata => sig_s2mm_cmd_wdata , cache_data => sig_s2mm_cache_data , sts_wvalid => s2mm_sts_wvalid , sts_wready => s2mm_sts_wready , sts_wdata => s2mm_sts_wdata , sts_wstrb => s2mm_sts_wstrb , sts_wlast => s2mm_sts_wlast , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid , cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready , mstr2stat_status => sig_wsc2stat_status , stat2mstr_status_ready => sig_stat2wsc_status_ready , mst2stst_status_valid => sig_wsc2stat_status_valid ); ------------------------------------------------------------ -- Instance: I_WR_STATUS_CNTLR -- -- Description: -- Write Status Controller Block -- ------------------------------------------------------------ I_WR_STATUS_CNTLR : entity axi_datamover_v5_1_10.axi_datamover_wr_status_cntl generic map ( C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH , C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH , C_STS_WIDTH => WSC_STATUS_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , rst2wsc_stop_request => sig_rst2all_stop_request , wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt , addr2wsc_addr_posted => sig_addr2data_addr_posted , s2mm_bresp => s2mm_bresp , s2mm_bvalid => s2mm_bvalid , s2mm_bready => s2mm_bready , calc2wsc_calc_error => sig_calc2dm_calc_err , addr2wsc_calc_error => sig_addr2wsc_calc_error , addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty , data2wsc_tag => sig_data2wsc_tag , data2wsc_calc_error => sig_data2wsc_calc_err , data2wsc_last_error => sig_data2wsc_last_err , data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt , data2wsc_valid => sig_data2wsc_valid , wsc2data_ready => sig_wsc2data_ready , data2wsc_eop => sig_data2wsc_eop , data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd , wsc2stat_status => sig_wsc2stat_status , stat2wsc_status_ready => sig_stat2wsc_status_ready , wsc2stat_status_valid => sig_wsc2stat_status_valid , wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe ); ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_PCC -- -- If Generate Description: -- Include the normal Predictive Command Calculator function, -- Store and Forward is not an included feature. -- -- ------------------------------------------------------------ GEN_INCLUDE_PCC : if (ENABLE_INDET_BTT_SF = 0) generate begin ------------------------------------------------------------ -- Instance: I_MSTR_PCC -- -- Description: -- Predictive Command Calculator Block -- ------------------------------------------------------------ I_MSTR_PCC : entity axi_datamover_v5_1_10.axi_datamover_pcc generic map ( C_IS_MM2S => IS_NOT_MM2S , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_BTT_USED => S2MM_BTT_USED , C_SUPPORT_INDET_BTT => ENABLE_INDET_BTT_SF , C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ) port map ( -- Clock input primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , mstr2data_dre_src_align => open , mstr2data_dre_dest_align => open , calc_error => sig_calc2dm_calc_err , dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset ); end generate GEN_INCLUDE_PCC; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_IBTTCC -- -- If Generate Description: -- Include the Indeterminate BTT Command Calculator function, -- Store and Forward is enabled in the S2MM. -- -- ------------------------------------------------------------ GEN_INCLUDE_IBTTCC : if (ENABLE_INDET_BTT_SF = 1) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_MSTR_SFCC -- -- Description: -- Instantiates the Store and Forward Command Calculator -- Block. -- ------------------------------------------------------------ I_S2MM_MSTR_IBTTCC : entity axi_datamover_v5_1_10.axi_datamover_ibttcc generic map ( C_SF_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_BTT_USED => S2MM_BTT_USED , C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ) port map ( -- Clock input primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid , pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready , sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt , sf2pcc_packet_eop => sig_sf2pcc_packet_eop , sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , calc_error => sig_calc2dm_calc_err , dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset ); end generate GEN_INCLUDE_IBTTCC; ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate begin ------------------------------------------------------------ -- Instance: I_S2MM_STRM_SKID_BUF -- -- Description: -- Instance for the S2MM Skid Buffer which provides for -- registerd Slave Stream inputs and supports bi-dir -- throttling. -- ------------------------------------------------------------ I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => S2MM_SDATA_WIDTH ) port map ( -- System Ports aclk => s2mm_aclk , arst => sig_mmap_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => sig_data2skid_halt , -- Slave Side (Stream Data Input) s_valid => s2mm_strm_wvalid , s_ready => s2mm_strm_wready , s_data => s2mm_strm_wdata , s_strb => s2mm_strm_wstrb , s_last => s2mm_strm_wlast , -- Master Side (Stream Data Output m_valid => skid2dre_wvalid , m_ready => dre2skid_wready , m_data => skid2dre_wdata , m_strb => skid2dre_wstrb , m_last => skid2dre_wlast ); end generate ENABLE_AXIS_SKID; DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate begin skid2dre_wvalid <= s2mm_strm_wvalid; s2mm_strm_wready <= dre2skid_wready; skid2dre_wdata <= s2mm_strm_wdata; skid2dre_wstrb <= s2mm_strm_wstrb; skid2dre_wlast <= s2mm_strm_wlast; end generate DISABLE_AXIS_SKID; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_REALIGNER -- -- If Generate Description: -- Omit the S2MM Realignment Engine -- -- ------------------------------------------------------------ GEN_NO_REALIGNER : if (ADD_REALIGNER = 0) generate begin -- Set to Always ready for DRE to PCC Command Interface sig_dre2mstr_cmd_ready <= LOGIC_HIGH; -- Without DRE and Scatter, the end of packet is the TLAST --sig_dre2ibtt_eop <= skid2dre_wlast ; sig_dre2ibtt_eop <= sig_dre2ibtt_tlast ; -- use skid buffered version -- Cant't detect undrrun/overrun here sig_realign2wdc_eop_error <= '0'; ENABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '1' generate begin ------------------------------------------------------------ -- Instance: I_NO_REALIGN_SKID_BUF -- -- Description: -- Instance for a Skid Buffer which provides for -- Fmax timing improvement between the Null Absorber and -- the Write Data controller when the Realigner is not -- present (no DRE and no Store and Forward case). -- ------------------------------------------------------------ I_NO_REALIGN_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => S2MM_SDATA_WIDTH ) port map ( -- System Ports aclk => s2mm_aclk , arst => sig_mmap_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => LOGIC_LOW , -- Slave Side (Null Absorber Input) s_valid => skid2dre_wvalid , s_ready => dre2skid_wready , s_data => skid2dre_wdata , s_strb => skid2dre_wstrb , s_last => skid2dre_wlast , -- Master Side (Stream Data Output to WData Cntlr) m_valid => sig_dre2ibtt_tvalid , m_ready => sig_ibtt2dre_tready , m_data => sig_dre2ibtt_tdata , m_strb => sig_dre2ibtt_tstrb , m_last => sig_dre2ibtt_tlast ); end generate ENABLE_NOREALIGNER_SKID; DISABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '0' generate begin sig_dre2ibtt_tvalid <= skid2dre_wvalid; dre2skid_wready <= sig_ibtt2dre_tready; sig_dre2ibtt_tdata <= skid2dre_wdata; sig_dre2ibtt_tstrb <= skid2dre_wstrb; sig_dre2ibtt_tlast <= skid2dre_wlast; end generate DISABLE_NOREALIGNER_SKID; end generate GEN_NO_REALIGNER; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_REALIGNER -- -- If Generate Description: -- Include the S2MM realigner Module. It hosts the S2MM DRE -- and the Scatter Block. -- -- Note that the General Purpose Store and Forward Module -- needs the Scatter function to detect input overrun and -- underrun events on the AXI Stream input. Thus the Realigner -- is included whenever the GP Store and Forward is enabled. -- ------------------------------------------------------------ GEN_INCLUDE_REALIGNER : if (ADD_REALIGNER = 1) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_REALIGNER -- -- Description: -- Instance for the S2MM Data Realignment Module. -- ------------------------------------------------------------ I_S2MM_REALIGNER : entity axi_datamover_v5_1_10.axi_datamover_s2mm_realign generic map ( C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_INCLUDE_DRE => INCLUDE_S2MM_DRE , C_DRE_CNTL_FIFO_DEPTH => DRE_CNTL_FIFO_DEPTH , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SUPPORT_SCATTER => DRE_SUPPORT_SCATTER , C_BTT_USED => S2MM_BTT_USED , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , -- Write Data Controller or Store and Forward I/O ------- wdc2dre_wready => sig_ibtt2dre_tready , dre2wdc_wvalid => sig_dre2ibtt_tvalid , dre2wdc_wdata => sig_dre2ibtt_tdata , dre2wdc_wstrb => sig_dre2ibtt_tstrb , dre2wdc_wlast => sig_dre2ibtt_tlast , dre2wdc_eop => sig_dre2ibtt_eop , -- Starting offset output ------------------------------- dre2sf_strt_offset => sig_sf_strt_addr_offset , -- AXI Slave Stream In ----------------------------------- s2mm_strm_wready => dre2skid_wready , s2mm_strm_wvalid => skid2dre_wvalid , s2mm_strm_wdata => skid2dre_wdata , s2mm_strm_wstrb => skid2dre_wstrb , s2mm_strm_wlast => skid2dre_wlast , -- Command Calculator Interface -------------------------- dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset , -- Premature TLAST assertion error flag dre2all_tlast_error => sig_realign2wdc_eop_error , -- DRE Halted Status dre2all_halted => sig_dre2all_halted ); end generate GEN_INCLUDE_REALIGNER; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ENABLE_INDET_BTT_SF -- -- If Generate Description: -- Include the Indeterminate BTT Logic with specialized -- Store and Forward function, This also requires the -- Scatter Engine in the Realigner module. -- -- ------------------------------------------------------------ GEN_ENABLE_INDET_BTT_SF : if (ENABLE_INDET_BTT_SF = 1) generate begin -- Pass the Realigner EOP error through sig_ibtt2wdc_error <= sig_realign2wdc_eop_error; -- Use only external address posting enable sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ; ------------------------------------------------------------ -- Instance: I_INDET_BTT -- -- Description: -- Instance for the Indeterminate BTT with Store and Forward -- module. -- ------------------------------------------------------------ I_INDET_BTT : entity axi_datamover_v5_1_10.axi_datamover_indet_btt generic map ( C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , C_IBTT_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH , C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_ENABLE_DRE => INCLUDE_S2MM_DRE , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , ibtt2wdc_stbs_asserted => sig_ibtt2wdc_stbs_asserted, ibtt2wdc_eop => sig_ibtt2wdc_eop , ibtt2wdc_tdata => sig_ibtt2wdc_tdata , ibtt2wdc_tstrb => sig_ibtt2wdc_tstrb , ibtt2wdc_tlast => sig_ibtt2wdc_tlast , ibtt2wdc_tvalid => sig_ibtt2wdc_tvalid , wdc2ibtt_tready => sig_wdc2ibtt_tready , dre2ibtt_tvalid => sig_dre2ibtt_tvalid , ibtt2dre_tready => sig_ibtt2dre_tready , dre2ibtt_tdata => sig_dre2ibtt_tdata , dre2ibtt_tstrb => sig_dre2ibtt_tstrb , dre2ibtt_tlast => sig_dre2ibtt_tlast , dre2ibtt_eop => sig_dre2ibtt_eop , dre2ibtt_strt_addr_offset => sig_sf_strt_addr_offset , sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid , pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready , sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt , sf2pcc_packet_eop => sig_sf2pcc_packet_eop , sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes ); end generate GEN_ENABLE_INDET_BTT_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_SF -- -- If Generate Description: -- Bypasses any store and Forward functions. -- -- ------------------------------------------------------------ GEN_NO_SF : if (ENABLE_INDET_BTT_SF = 0 and ENABLE_GP_SF = 0) generate begin -- Use only external address posting enable sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ; -- Housekeep unused signal in this case sig_ok_to_post_wr_addr <= '0' ; -- SFCC Interface Signals that are not used sig_pcc2sf_xfer_ready <= '0' ; sig_sf2pcc_xfer_valid <= '0' ; sig_sf2pcc_cmd_cmplt <= '0' ; sig_sf2pcc_packet_eop <= '0' ; sig_sf2pcc_xfer_bytes <= (others => '0') ; -- Just pass DRE signals through sig_ibtt2dre_tready <= sig_wdc2ibtt_tready ; sig_ibtt2wdc_tvalid <= sig_dre2ibtt_tvalid ; sig_ibtt2wdc_tdata <= sig_dre2ibtt_tdata ; sig_ibtt2wdc_tstrb <= sig_dre2ibtt_tstrb ; sig_ibtt2wdc_tlast <= sig_dre2ibtt_tlast ; sig_ibtt2wdc_eop <= sig_dre2ibtt_eop ; sig_ibtt2wdc_stbs_asserted <= (others => '0') ; -- Pass the Realigner EOP error through sig_ibtt2wdc_error <= sig_realign2wdc_eop_error; end generate GEN_NO_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_GP_SF -- -- If Generate Description: -- Include the General Purpose Store and Forward module. -- This If Generate can only be enabled when -- Indeterminate BTT mode is not enabled. The General Purpose -- Store and Forward is instantiated in place of the Indet -- BTT Store and Forward. -- ------------------------------------------------------------ GEN_INCLUDE_GP_SF : if (ENABLE_INDET_BTT_SF = 0 and ENABLE_GP_SF = 1) generate begin -- Merge the external address posting control with the -- SF address posting control. sig_s2mm_allow_addr_req <= s2mm_allow_addr_req and sig_ok_to_post_wr_addr ; -- Zero these out since Indet BTT is not enabled, they -- are only used by the WDC in that mode sig_ibtt2wdc_stbs_asserted <= (others => '0') ; sig_ibtt2wdc_eop <= '0' ; -- SFCC Interface Signals that are not used sig_pcc2sf_xfer_ready <= '0' ; sig_sf2pcc_xfer_valid <= '0' ; sig_sf2pcc_cmd_cmplt <= '0' ; sig_sf2pcc_packet_eop <= '0' ; sig_sf2pcc_xfer_bytes <= (others => '0') ; ------------------------------------------------------------ -- Instance: I_S2MM_GP_SF -- -- Description: -- Instance for the S2MM (Write) General Purpose Store and -- Forward Module. This module can only be enabled when -- Indeterminate BTT mode is not enabled. It is connected -- in place of the IBTT Module when GP SF is enabled. -- ------------------------------------------------------------ I_S2MM_GP_SF : entity axi_datamover_v5_1_10.axi_datamover_wr_sf generic map ( C_WR_ADDR_PIPE_DEPTH => ADDR_CNTL_FIFO_DEPTH , C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset inputs ----------------------------- aclk => s2mm_aclk , reset => sig_mmap_rst , -- Slave Stream Input -------------------------------- sf2sin_tready => sig_ibtt2dre_tready , sin2sf_tvalid => sig_dre2ibtt_tvalid , sin2sf_tdata => sig_dre2ibtt_tdata , sin2sf_tkeep => sig_dre2ibtt_tstrb , sin2sf_tlast => sig_dre2ibtt_tlast , sin2sf_error => sig_realign2wdc_eop_error , -- Starting Address Offset Input --------------------- sin2sf_strt_addr_offset => sig_sf_strt_addr_offset , -- DataMover Write Side Address Pipelining Control Interface -------- ok_to_post_wr_addr => sig_ok_to_post_wr_addr , wr_addr_posted => sig_s2mm_addr_req_posted , wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt , wr_ld_nxt_len => sig_s2mm_ld_nxt_len , wr_len => sig_s2mm_wr_len , -- Write Side Stream Out to DataMover S2MM ------------- sout2sf_tready => sig_wdc2ibtt_tready , sf2sout_tvalid => sig_ibtt2wdc_tvalid , sf2sout_tdata => sig_ibtt2wdc_tdata , sf2sout_tkeep => sig_ibtt2wdc_tstrb , sf2sout_tlast => sig_ibtt2wdc_tlast , sf2sout_error => sig_ibtt2wdc_error ); end generate GEN_INCLUDE_GP_SF; ------------------------------------------------------------ -- Instance: I_ADDR_CNTL -- -- Description: -- Address Controller Block -- ------------------------------------------------------------ I_ADDR_CNTL : entity axi_datamover_v5_1_10.axi_datamover_addr_cntl generic map ( C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_ADDR_ID => S2MM_AWID_VALUE , C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , addr2axi_aid => s2mm_awid , addr2axi_aaddr => s2mm_awaddr , addr2axi_alen => s2mm_awlen , addr2axi_asize => s2mm_awsize , addr2axi_aburst => s2mm_awburst , addr2axi_aprot => s2mm_awprot , addr2axi_avalid => s2mm_awvalid , addr2axi_acache => s2mm_awcache_int , addr2axi_auser => s2mm_awuser_int , axi2addr_aready => s2mm_awready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , -- mstr2addr_cache_info => sig_cache2mstr_command , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt , allow_addr_req => sig_s2mm_allow_addr_req , addr_req_posted => sig_s2mm_addr_req_posted , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => sig_data2addr_data_rdy , data2addr_stop_req => sig_data2addr_stop_req , addr2stat_calc_error => sig_addr2wsc_calc_error , addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty ); ------------------------------------------------------------ -- Instance: I_WR_DATA_CNTL -- -- Description: -- Write Data Controller Block -- ------------------------------------------------------------ I_WR_DATA_CNTL : entity axi_datamover_v5_1_10.axi_datamover_wrdata_cntl generic map ( C_REALIGNER_INCLUDED => ADD_REALIGNER , C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , rst2data_stop_request => sig_rst2all_stop_request , data2addr_stop_req => sig_data2addr_stop_req , data2rst_stop_cmplt => sig_data2rst_stop_cmplt , wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt , s2mm_ld_nxt_len => sig_s2mm_ld_nxt_len , s2mm_wr_len => sig_s2mm_wr_len , data2skid_saddr_lsb => sig_data2skid_addr_lsb , data2skid_wdata => sig_data2skid_wdata , data2skid_wstrb => sig_data2skid_wstrb , data2skid_wlast => sig_data2skid_wlast , data2skid_wvalid => sig_data2skid_wvalid , skid2data_wready => sig_skid2data_wready , s2mm_strm_wvalid => sig_ibtt2wdc_tvalid , s2mm_strm_wready => sig_wdc2ibtt_tready , s2mm_strm_wdata => sig_ibtt2wdc_tdata , s2mm_strm_wstrb => sig_ibtt2wdc_tstrb , s2mm_strm_wlast => sig_ibtt2wdc_tlast , s2mm_strm_eop => sig_ibtt2wdc_eop , s2mm_stbs_asserted => sig_ibtt2wdc_stbs_asserted, realign2wdc_eop_error => sig_ibtt2wdc_error , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => sig_data2addr_data_rdy , data2all_tlast_error => sig_data2all_tlast_error , data2all_dcntlr_halted => sig_data2all_dcntlr_halted, data2skid_halt => sig_data2skid_halt , data2wsc_tag => sig_data2wsc_tag , data2wsc_calc_err => sig_data2wsc_calc_err , data2wsc_last_err => sig_data2wsc_last_err , data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt , wsc2data_ready => sig_wsc2data_ready , data2wsc_valid => sig_data2wsc_valid , data2wsc_eop => sig_data2wsc_eop , data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd , wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe ); --ENABLE_AXIMMAP_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate --begin ------------------------------------------------------------ -- Instance: I_S2MM_MMAP_SKID_BUF -- -- Description: -- Instance for the S2MM Skid Buffer which provides for -- registered outputs and supports bi-dir throttling. -- -- This Module also provides Write Data Bus Mirroring and WSTRB -- Demuxing to match a narrow Stream to a wider MMap Write -- Channel. By doing this in the skid buffer, the resource -- utilization of the skid buffer can be minimized by only -- having to buffer/mux the Stream data width, not the MMap -- Data width. -- ------------------------------------------------------------ I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_skid2mm_buf generic map ( C_MDATA_WIDTH => S2MM_MDATA_WIDTH , C_SDATA_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH ) port map ( -- System Ports ACLK => s2mm_aclk , ARST => sig_stream_rst , -- Slave Side (Wr Data Controller Input Side ) S_ADDR_LSB => sig_data2skid_addr_lsb, S_VALID => sig_data2skid_wvalid , S_READY => sig_skid2data_wready , S_Data => sig_data2skid_wdata , S_STRB => sig_data2skid_wstrb , S_Last => sig_data2skid_wlast , -- Master Side (MMap Write Data Output Side) M_VALID => sig_skid2axi_wvalid , M_READY => sig_axi2skid_wready , M_Data => sig_skid2axi_wdata , M_STRB => sig_skid2axi_wstrb , M_Last => sig_skid2axi_wlast ); --end generate ENABLE_AXIMMAP_SKID; end implementation;

-- -- Parameterisable N to M mux. -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- For Modelsim --use ieee.fixed_pkg.all; --use ieee.fixed_float_types.ALL; -- For ISE library ieee_proposed; use ieee_proposed.fixed_pkg.all; use IEEE.numeric_std.all; entity ParamExp is generic( BIT_TOP : integer := 20; BIT_BOTTOM : integer := -20); port( clk : In Std_logic; init_model : in STD_LOGIC; --signal to all components to go into their init state Start : In Std_logic; X : In sfixed(BIT_TOP downto BIT_BOTTOM); Done : Out Std_logic; Output : Out sfixed(BIT_TOP downto BIT_BOTTOM) ); end ParamExp; architecture RTL of ParamExp is type MEM is array (0 to 7) of sfixed(BIT_TOP downto BIT_BOTTOM); signal ISPOSITIVE : STD_LOGIC := '0'; signal ISGREATERTHANONE : STD_LOGIC := '0'; signal X_integer : sfixed(BIT_TOP downto 0); signal X_fraction : sfixed(0 downto BIT_BOTTOM); signal Output_int : sfixed(BIT_TOP downto BIT_BOTTOM); signal Done_int : Std_logic; signal output_fraction : sfixed(BIT_TOP downto BIT_BOTTOM); signal output_fraction_next : sfixed(BIT_TOP downto BIT_BOTTOM); signal current_term : sfixed(BIT_TOP downto BIT_BOTTOM); signal current_term_next : sfixed(BIT_TOP downto BIT_BOTTOM); signal COUNT_FRACTION : unsigned(3 downto 0); signal COUNT_FRACTION_next : unsigned(3 downto 0); signal DONEFRACTION : STD_LOGIC := '0'; signal DONEFRACTION_next : STD_LOGIC := '0'; signal output_integer : sfixed(BIT_TOP downto BIT_BOTTOM); signal output_integer_next : sfixed(BIT_TOP downto BIT_BOTTOM); signal COUNT_INTEGER : unsigned(BIT_TOP+1 downto 0); signal COUNT_INTEGER_next : unsigned(BIT_TOP+1 downto 0); signal DONEINTEGER : STD_LOGIC := '0'; signal DONEINTEGER_next : STD_LOGIC := '0'; signal E : sfixed(BIT_TOP downto BIT_BOTTOM) := to_sfixed(2.71828182845904523536028747135266249775724709369995,BIT_TOP,BIT_BOTTOM); signal EInv : sfixed(BIT_TOP downto BIT_BOTTOM) := resize(reciprocal(to_sfixed(2.71828182845904523536028747135266249775724709369995,BIT_TOP,BIT_BOTTOM)),BIT_TOP,BIT_BOTTOM); signal EMul : sfixed(BIT_TOP downto BIT_BOTTOM); signal n1: sfixed (BIT_TOP downto 0); signal n2: sfixed (n1'high + 1 downto n1'low); signal n3: ufixed (BIT_TOP + 1 downto 0); begin splitUpXProcess: process(X,X_integer,ispositive,E,EInv) begin X_integer <= resize(abs(X) - 0.5,BIT_TOP,0); X_fraction <= resize(abs(X) - X_integer,0,BIT_BOTTOM); if To_slv ( resize ( X ,BIT_TOP,BIT_BOTTOM))(BIT_TOP-BIT_BOTTOM) = '0' then ISPOSITIVE <= '1'; else ISPOSITIVE <= '0'; end if; if (ISPOSITIVE = '1') then EMul <= E; else EMul <= EInv; end if; end process splitUpXProcess; fractionCombProcess: process(COUNT_FRACTION,Start,output_fraction,current_term,X_fraction,ISPOSITIVE,current_term_next,init_model) variable MEM8Xsfixed : MEM := (to_sfixed (1,BIT_TOP, BIT_BOTTOM),to_sfixed (0.5,BIT_TOP, BIT_BOTTOM),to_sfixed (0.33333333,BIT_TOP, BIT_BOTTOM),to_sfixed (0.25,BIT_TOP, BIT_BOTTOM), to_sfixed (0.2,BIT_TOP, BIT_BOTTOM),to_sfixed (0.16666666667,BIT_TOP, BIT_BOTTOM),to_sfixed (0.142857142857,BIT_TOP, BIT_BOTTOM),to_sfixed (0.125,BIT_TOP, BIT_BOTTOM)); variable MEM8XsfixedOutTemp : sfixed(BIT_TOP downto BIT_BOTTOM); begin output_fraction_next <= output_fraction; COUNT_FRACTION_next <= COUNT_FRACTION; current_term_next <= current_term; DONEFRACTION_next <= '0'; MEM8XsfixedOutTemp := MEM8Xsfixed(to_integer(unsigned(COUNT_FRACTION(2 downto 0)))); current_term_next <= resize(MEM8XsfixedOutTemp * resize(X_fraction * current_term,BIT_TOP, BIT_BOTTOM),BIT_TOP, BIT_BOTTOM); if init_model = '1' then DONEFRACTION_next <= '1'; COUNT_FRACTION_next <= "1001"; output_fraction_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM); current_term_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM); else if Start = '1' then DONEFRACTION_next <= '0'; COUNT_FRACTION_next <= "0000"; output_fraction_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM); current_term_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM); elsif COUNT_FRACTION = "1001" then DONEFRACTION_next <= '1'; current_term_next <= current_term; else DONEFRACTION_next <= '0'; if (ISPOSITIVE = '1') then output_fraction_next <= resize(output_fraction + current_term_next,BIT_TOP, BIT_BOTTOM); else if (COUNT_FRACTION(0) = '0') then output_fraction_next <= resize(output_fraction - current_term_next,BIT_TOP, BIT_BOTTOM); else output_fraction_next <= resize(output_fraction + current_term_next,BIT_TOP, BIT_BOTTOM); end if; end if; COUNT_FRACTION_next <= COUNT_FRACTION + 1; end if; end if; end process fractionCombProcess; fractionSynProcess: process(clk) variable Sel : integer; begin if clk'event and clk = '1' then output_fraction <= output_fraction_next; COUNT_FRACTION <= COUNT_FRACTION_next; current_term <= current_term_next; DONEFRACTION <= DONEFRACTION_next; --report "The value of output_fraction = " & real'image(to_real(output_fraction)) & " and current_term " & -- real'image(to_real(current_term)); end if; end process fractionSynProcess; integerCombProcess: process(COUNT_INTEGER,output_integer,x_integer,Start,EMul,init_model) begin DONEINTEGER_next <= '0'; COUNT_INTEGER_next <= COUNT_INTEGER; output_integer_next <= output_integer; if init_model = '1' then DONEINTEGER_next <= '0'; COUNT_INTEGER_next <= to_unsigned(0,COUNT_INTEGER_next'length); output_integer_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM); else if Start = '1' then DONEINTEGER_next <= '0'; COUNT_INTEGER_next <= unsigned(ufixed(abs(X_integer))); output_integer_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM); else if COUNT_INTEGER = 0 then DONEINTEGER_next <= '1'; COUNT_INTEGER_next <= COUNT_INTEGER; output_integer_next <= output_integer; else DONEINTEGER_next <= '0'; output_integer_next <= resize(output_integer * EMul,BIT_TOP,BIT_BOTTOM); COUNT_INTEGER_next <= COUNT_INTEGER - 1; end if; end if; end if; end process integerCombProcess; integerSynProcess: process(clk,x_integer,count_integer,output_integer) begin COUNT_INTEGER <= COUNT_INTEGER; output_integer <= output_integer; if clk = '1' and clk'event then COUNT_INTEGER <= COUNT_INTEGER_next; output_integer <= output_integer_next; DONEINTEGER <= DONEINTEGER_next; end if; end process integerSynProcess; outputCombProcess: process(output_fraction,output_integer,DONEINTEGER,DONEFRACTION) begin Output_int <= resize(output_fraction * output_integer,BIT_TOP, BIT_BOTTOM); if DONEFRACTION = '1' and DONEINTEGER = '1' then Done_int <= '1'; else Done_int <= '0'; end if; end process outputCombProcess; Done <= Done_int; Output <= Output_int; --process (DONEFRACTION) --begin -- if (DONEFRACTION'event or DONEINTEGER'event) and DONEFRACTION = '1' and DONEINTEGER = '1' then -- report "The value of X_integer = " & real'image(to_real(X_integer)) & " and X_fraction " & real'image(to_real(X_fraction)); -- report "The value of exp( " & real'image(to_real(X)) & " ) = " & -- real'image(to_real(output_integer)) & " * " & real'image(to_real(output_fraction)); -- end if; --end process; end RTL;

-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017 -- Date : Tue Oct 17 19:49:27 2017 -- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS -- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_led_controller_0_0_stub.vhdl -- Design : ip_design_led_controller_0_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is Port ( LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 ); s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s00_axi_awvalid : in STD_LOGIC; s00_axi_awready : out STD_LOGIC; s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s00_axi_wvalid : in STD_LOGIC; s00_axi_wready : out STD_LOGIC; s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s00_axi_bvalid : out STD_LOGIC; s00_axi_bready : in STD_LOGIC; s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 ); s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s00_axi_arvalid : in STD_LOGIC; s00_axi_arready : out STD_LOGIC; s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s00_axi_rvalid : out STD_LOGIC; s00_axi_rready : in STD_LOGIC; s00_axi_aclk : in STD_LOGIC; s00_axi_aresetn : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "LEDs_out[7:0],s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "led_controller_v1_0,Vivado 2017.3"; begin end;

-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc487.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s02b01x01p20n01i00487ent IS END c03s02b01x01p20n01i00487ent; ARCHITECTURE c03s02b01x01p20n01i00487arch OF c03s02b01x01p20n01i00487ent IS type MEM is array (positive range <>) of BIT; type ME1 is array (natural range <>) of Integer; subtype ME2 is ME1(0 to 3); subtype M1 is MEM (1 to 5); procedure F2 (X1 : inout MEM) is begin assert NOT((X1'LOW = 1) and (X1'High = 5)) report "***PASSED TEST: c03s02b01x01p20n01i00487" severity NOTE; assert ((X1'LOW = 1) and (X1'High = 5)) report "***FAILED TEST: c03s02b01x01p20n01i00487 - For an interface object of mode out, inout, or linkage, if the formal part does not contain a type conversion function, then the index ranges are obtained from the object denoted by the actual designator." severity ERROR; end F2; BEGIN TESTING: PROCESS variable S1 : M1 := "01110"; BEGIN F2(S1) ; -- No_failure_here wait; END PROCESS TESTING; END c03s02b01x01p20n01i00487arch;

entity assert4 is end entity; architecture test of assert4 is begin process is variable n : integer; begin n := 0; wait for 1 ns; assert n = 0 report integer'image(100 / n); wait; end process; end architecture;

-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:axi_gpio:2.0 -- IP Revision: 6 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY axi_gpio_v2_0; USE axi_gpio_v2_0.axi_gpio; ENTITY base_zynq_design_axi_gpio_0_0 IS PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; ip2intc_irpt : OUT STD_LOGIC; gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); gpio2_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0) ); END base_zynq_design_axi_gpio_0_0; ARCHITECTURE base_zynq_design_axi_gpio_0_0_arch OF base_zynq_design_axi_gpio_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF base_zynq_design_axi_gpio_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT axi_gpio IS GENERIC ( C_FAMILY : STRING; C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER; C_GPIO_WIDTH : INTEGER; C_GPIO2_WIDTH : INTEGER; C_ALL_INPUTS : INTEGER; C_ALL_INPUTS_2 : INTEGER; C_ALL_OUTPUTS : INTEGER; C_ALL_OUTPUTS_2 : INTEGER; C_INTERRUPT_PRESENT : INTEGER; C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0); C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0); C_IS_DUAL : INTEGER; C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) ); PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; ip2intc_irpt : OUT STD_LOGIC; gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0); gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); gpio2_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0); gpio2_io_o : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); gpio2_io_t : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END COMPONENT axi_gpio; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF base_zynq_design_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2014.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF base_zynq_design_axi_gpio_0_0_arch : ARCHITECTURE IS "base_zynq_design_axi_gpio_0_0,axi_gpio,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF base_zynq_design_axi_gpio_0_0_arch: ARCHITECTURE IS "base_zynq_design_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=8,C_GPIO2_WIDTH=5,C_ALL_INPUTS=0,C_ALL_INPUTS_2=1,C_ALL_OUTPUTS=1,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=1,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=1,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O"; ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I"; BEGIN U0 : axi_gpio GENERIC MAP ( C_FAMILY => "zynq", C_S_AXI_ADDR_WIDTH => 9, C_S_AXI_DATA_WIDTH => 32, C_GPIO_WIDTH => 8, C_GPIO2_WIDTH => 5, C_ALL_INPUTS => 0, C_ALL_INPUTS_2 => 1, C_ALL_OUTPUTS => 1, C_ALL_OUTPUTS_2 => 0, C_INTERRUPT_PRESENT => 1, C_DOUT_DEFAULT => X"00000000", C_TRI_DEFAULT => X"FFFFFFFF", C_IS_DUAL => 1, C_DOUT_DEFAULT_2 => X"00000000", C_TRI_DEFAULT_2 => X"FFFFFFFF" ) PORT MAP ( s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_awaddr => s_axi_awaddr, s_axi_awvalid => s_axi_awvalid, s_axi_awready => s_axi_awready, s_axi_wdata => s_axi_wdata, s_axi_wstrb => s_axi_wstrb, s_axi_wvalid => s_axi_wvalid, s_axi_wready => s_axi_wready, s_axi_bresp => s_axi_bresp, s_axi_bvalid => s_axi_bvalid, s_axi_bready => s_axi_bready, s_axi_araddr => s_axi_araddr, s_axi_arvalid => s_axi_arvalid, s_axi_arready => s_axi_arready, s_axi_rdata => s_axi_rdata, s_axi_rresp => s_axi_rresp, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready, ip2intc_irpt => ip2intc_irpt, gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), gpio_io_o => gpio_io_o, gpio2_io_i => gpio2_io_i ); END base_zynq_design_axi_gpio_0_0_arch;

entity ent is end entity; library ieee; use ieee.std_logic_1164.all; package avmm_csr_pkg is type avmm_csr_array_t is array (natural range <>) of std_logic_vector(31 downto 0); end avmm_csr_pkg; library ieee; use work.avmm_csr_pkg.all; entity avmm_csr is Port ( reg_i : in avmm_csr_array_t ); end avmm_csr; architecture rtl of avmm_csr is begin end rtl; library ieee; use ieee.numeric_std_unsigned.all; entity dut is end entity dut; architecture rtl of dut is signal int : natural; begin inst : entity work.avmm_csr port map ( reg_i(0) => to_slv(int, 32) ); end architecture rtl;

-- ######################################################################## -- $Software: busiac -- $section : hardware component -- $Id: plus12.vhd 325 2015-06-03 12:47:32Z ia $ -- $HeadURL: svn://lunix120.ensiie.fr/ia/cours/archi/projet/busiac/vhdl/plus12.vhd $ -- $Author : Ivan Auge (Email: auge@ensiie.fr) -- ######################################################################## -- -- This file is part of the BUSIAC software: Copyright (C) 2010 by I. Auge. -- -- This program is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at your -- option) any later version. -- -- BUSIAC software is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY ; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General -- Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with the GNU C Library; see the file COPYING. If not, write to the Free -- Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -- -- ######################################################################*/ ------------------------------------------------------------------------------- -- Ce module additionne 2 nombres de 12 bits signés. -- Ses E/S sont les bus busin et busout. -- -- Input: -- busin_ctl (43 DOWNTO 40) : not used -- busin_asrc(39 DOWNTO 32) : adresse emetteur (E_ADR) -- busin_ades(31 DOWNTO 24) : adresse destination (MYADR) -- busin_data(23 DOWNTO 12) : operande B en complement a 2 -- busin_data(11 DOWNTO 0) : operande A en complement a 2 -- -- Output: -- busout_ctl (43 DOWNTO 40) : "0000" -- busout_asrc(39 DOWNTO 32) : MYADR -- busout_ades(31 DOWNTO 24) : E_ADR -- busout_data(23) : V (overflow) -- busout_data(22) : C (retenue sortante) -- busout_data(21) : N (résultat négatif) -- busout_data(20) : Z (résultat nul) -- busout_data(19 DOWNTO 12) : "00000000" -- busout_data(11 DOWNTO 0) : résultat en complément a 2 (A+B) ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; use IEEE.numeric_std.all; ENTITY plus12 IS GENERIC( MYADR : STD_LOGIC_VECTOR(7 downto 0) := x"C0" ); -- 192 PORT( clk : IN STD_LOGIC; reset : IN STD_LOGIC; -- interface busin busin : in STD_LOGIC_VECTOR(43 DOWNTO 0); busin_valid : in STD_LOGIC; busin_eated : out STD_LOGIC; -- interface busout busout : OUT STD_LOGIC_VECTOR(43 DOWNTO 0); busout_valid : OUT STD_LOGIC; busout_eated : IN STD_LOGIC; -- debug debug : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END plus12; ARCHITECTURE Montage OF plus12 IS TYPE T_CMD_LoadNoop IS (LOAD, NOOP); -- partie operative -- le registre de transfert de busin vers busout SIGNAL CMD_tft : T_CMD_LoadNoop; SIGNAL R_tft : STD_LOGIC_VECTOR(43 DOWNTO 0); -- le registre resultat de A+B, ov -- on etend R sur 13 bits pour avoir la retenue SIGNAL CMD_res : T_CMD_LoadNoop; SIGNAL R_res : STD_LOGIC_VECTOR(12 DOWNTO 0); -- les operandes A et B (1 bit de plus pour la retenue) SIGNAL A,B : STD_LOGIC_VECTOR (12 DOWNTO 0); -- V1 -- bits de retenue et de somme de A+B -- V1 SIGNAL r,s : STD_LOGIC_VECTOR (12 DOWNTO 0); -- V1 -- SIGNAL A,B : SIGNED (12 DOWNTO 0); -- V2 -- l' adresse destination SIGNAL busin_ades : STD_LOGIC_VECTOR ( 7 DOWNTO 0); -- message résulat SIGNAL mess_resultat : STD_LOGIC_VECTOR (43 DOWNTO 0); -- partie controle TYPE STATE_TYPE IS (ST_READ, ST_WRITE_TFT, ST_COMPUTE, ST_WRITE_SUM); SIGNAL state : STATE_TYPE; BEGIN ------------------------------------------------------------------------------- -- Partie Opérative ------------------------------------------------------------------------------- busin_ades <= busin(31 DOWNTO 24) ; a <= "0" & R_tft(23 DOWNTO 12) ; -- V1 b <= "0" & R_tft(11 DOWNTO 0) ; -- V1 -- a <= SIGNED (R_tft(23 DOWNTO 12)) ; -- V2 -- b <= SIGNED (R_tft(11 DOWNTO 0)) ; -- V2 mess_resultat(43 DOWNTO 40) <= "0000"; mess_resultat(39 DOWNTO 32) <= MYADR; mess_resultat(31 DOWNTO 24) <= R_tft(39 DOWNTO 32); mess_resultat(23) <= -- overflow '1' WHEN a(11)='1' AND b(11)='1' AND R_res(11)='0' ELSE -- N+N=P '1' WHEN a(11)='0' AND b(11)='0' AND R_res(11)='1' ELSE -- P+P=N '0' ; mess_resultat(22) <= R_res(12); -- cout mess_resultat(21) <= R_res(11); -- signe mess_resultat(20) <= -- null '1' WHEN R_res(11 downto 0) = x"000" ELSE '0'; mess_resultat(19 DOWNTO 12) <= "00000000" ; mess_resultat(11 DOWNTO 0) <= R_res(11 DOWNTO 0); -- s,r <-- a + b; -- V1 s <= a XOR b XOR r; -- V1 r(0) <= '0'; -- V1 r(12 DOWNTO 1) <= -- V1 ( a(11 DOWNTO 0) AND b(11 DOWNTO 0) ) OR -- V1 ( a(11 DOWNTO 0) AND r(11 DOWNTO 0) ) OR -- V1 ( r(11 DOWNTO 0) AND b(11 DOWNTO 0) ); -- V1 PROCESS (clk) BEGIN IF clk'EVENT AND clk = '1' THEN -- R_tft if ( CMD_tft = LOAD ) then R_tft <= busin; end if; -- R_res if ( CMD_res = LOAD ) then R_res(12 DOWNTO 0) <= s ; -- V1 -- R_res(12 DOWNTO 0) <= STD_LOGIC_VECTOR(a + b) ; -- V2 end if; END IF; END PROCESS; ------------------------------------------------------------------------------- -- Partie Controle ------------------------------------------------------------------------------- -- Inputs: busin_valid busout_eated -- Outputs: busin_eated busout_valid, CMD_res, CMD_tft, busout ------------------------------------------------------------------------------- -- fonction de transitition PROCESS (reset,clk) BEGIN IF reset = '1' THEN state <= ST_READ; ELSIF clk'EVENT AND clk = '1' THEN CASE state IS WHEN ST_READ => IF busin_valid = '1' and busin_ades = MYADR THEN state <= ST_COMPUTE; ELSIF busin_valid = '1' and busin_ades /= MYADR THEN state <= ST_WRITE_TFT; END IF; WHEN ST_COMPUTE => state <= ST_WRITE_SUM; WHEN ST_WRITE_SUM => IF busout_eated = '1' THEN state <= ST_READ; END IF; WHEN ST_WRITE_TFT => IF busout_eated = '1' THEN state <= ST_READ; END IF; END CASE; END IF; END PROCESS; -- fonction de sortie WITH state SELECT busin_eated <= '1' WHEN ST_READ, '0' WHEN OTHERS; WITH state SELECT busout_valid <= '1' WHEN ST_WRITE_TFT, '1' WHEN ST_WRITE_SUM, '0' WHEN OTHERS; WITH state SELECT CMD_res <= LOAD WHEN ST_Compute, NOOP WHEN OTHERS; WITH state SELECT CMD_tft <= LOAD WHEN ST_READ, NOOP WHEN OTHERS; WITH state SELECT busout <= mess_resultat WHEN ST_WRITE_SUM, R_tft WHEN OTHERS; END Montage;

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 17:52:30 04/03/2013 -- Design Name: -- Module Name: muxx - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity muxx is Port ( S : in bit_VECTOR (1 downto 0); A : in STD_LOGIC_VECTOR (3 downto 0); D : out STD_LOGIC); end muxx; architecture Behavioral of muxx is begin process(s) --variable d : std_logic; begin case s is when "00" => d <= A(0); when "01" => d <= A(1); when "10" => d <= A(2); when "11" => d <= A(3); end case; -- D <= d; end process; end Behavioral;

-- ------------------------------------------------------------- -- -- File Name: hdlsrc/fft_16_bit/FFT_HDL_Optimized.vhd -- Created: 2017-03-27 23:13:58 -- -- Generated by MATLAB 9.1 and HDL Coder 3.9 -- -- ------------------------------------------------------------- -- ------------------------------------------------------------- -- -- Module: FFT_HDL_Optimized -- Source Path: fft_16_bit/FFT HDL Optimized -- Hierarchy Level: 1 -- -- FFT HDL Optimized -- -- ------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; USE work.fft_16_bit_pkg.ALL; ENTITY FFT_HDL_Optimized IS PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dataIn : IN vector_of_std_logic_vector16(0 TO 15); -- uint16 [16] validIn : IN std_logic; dataOut_re : OUT vector_of_std_logic_vector21(0 TO 15); -- sfix21 [16] dataOut_im : OUT vector_of_std_logic_vector21(0 TO 15); -- sfix21 [16] validOut : OUT std_logic ); END FFT_HDL_Optimized; ARCHITECTURE rtl OF FFT_HDL_Optimized IS -- Component Declarations COMPONENT RADIX22FFT_SDNF1_1 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_1_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_1_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_9_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_9_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_1_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_1_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_2_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_2_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_1_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_1_block3 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_5_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_5_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_13_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_13_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_9_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_9_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_10_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_10_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_9_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_2 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_1 : IN std_logic; -- ufix1 dout_1_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_1_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_9_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_9_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_1_re_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_1_im_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_1_block PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_2_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_2_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_10_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_10_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_3_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_3_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_4_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_4_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_3_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_1_block4 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_6_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_6_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_14_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_14_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_11_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_11_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_12_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_12_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_11_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_2_block PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_3 : IN std_logic; -- ufix1 dout_3_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_3_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_11_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_11_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_3_re_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_3_im_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_4_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_4_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_2 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_2_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_2_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_2_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLMULT_SDNF1_3 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_1_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_1_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_3_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_3_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : IN std_logic; twdl_3_1_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_1_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_2_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_2_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_2_vld : IN std_logic; softReset : IN std_logic; twdlXdin_1_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_2_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_2_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_1_block1 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_3_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_3_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_11_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_11_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_5_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_5_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_6_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_6_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_5_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_1_block5 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_7_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_7_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_15_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_15_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_13_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_13_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_14_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_14_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_13_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_2_block1 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_5 : IN std_logic; -- ufix1 dout_5_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_5_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_13_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_13_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_5_re_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_5_im_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_6_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_6_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_1_block2 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_4_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_4_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_12_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_12_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_7_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_7_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_8_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_8_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_7_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_1_block6 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_8_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_8_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_16_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_16_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_15_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_15_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_16_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_16_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18 dout_15_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_2_block2 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_7 : IN std_logic; -- ufix1 dout_7_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_7_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_15_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_15_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_7_re_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_7_im_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_8_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_8_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_3 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_3_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_3_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_3_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_4 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_4_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_4_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_4_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLMULT_SDNF1_3_block PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_5_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_5_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_7_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_7_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : IN std_logic; twdl_3_3_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_3_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_4_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_4_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_4_vld : IN std_logic; softReset : IN std_logic; twdlXdin_3_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_3_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_4_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_4_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_3_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_3 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_1_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_3_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_3_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_1_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_1_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_2_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_2_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_1_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_3_block PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_2_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_2_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_4_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_4_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_3_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_3_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_4_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_4_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_3_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_4 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_1 : IN std_logic; -- ufix1 dout_1_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_1_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_3_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_3_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_1_re_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_1_im_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_2_re : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_2_im : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_4_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_4_block PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_3 : IN std_logic; -- ufix1 dout_2_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_2_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_4_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_4_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_3_re : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_3_im : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_4_re_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_4_im_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_4_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_6 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_6_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_6_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_6_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLMULT_SDNF1_3_block1 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_4_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_4_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : IN std_logic; twdl_3_5_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_5_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_6_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_6_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_6_vld : IN std_logic; softReset : IN std_logic; twdlXdin_5_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_5_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_6_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_6_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_5_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_7 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_7_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_7_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_7_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_8 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_8_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_8_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_8_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLMULT_SDNF1_3_block2 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_6_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_6_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_8_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_8_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : IN std_logic; twdl_3_7_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_7_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_8_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_8_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_8_vld : IN std_logic; softReset : IN std_logic; twdlXdin_7_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_7_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_8_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_8_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_7_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_3_block1 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_5_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_5_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_7_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_7_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_5_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_5_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_6_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_6_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_5_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_3_block2 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_6_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_6_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_8_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_8_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_7_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_7_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_8_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_8_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_7_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_4_block1 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_5 : IN std_logic; -- ufix1 dout_5_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_5_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_7_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_7_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_5_re_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_5_im_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_6_re : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_6_im : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_4_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_4_block2 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_7 : IN std_logic; -- ufix1 dout_6_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_6_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_8_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_8_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_7_re : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_7_im : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_8_re_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_8_im_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_4_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_2_block3 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_9 : IN std_logic; -- ufix1 dout_2_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_2_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_10_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_10_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_9_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_9_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_10_re_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_10_im_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_2_block4 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_11 : IN std_logic; -- ufix1 dout_4_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_4_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_12_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_12_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_11_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_11_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_12_re_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_12_im_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_10 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_10_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_10_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_10_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLMULT_SDNF1_3_block3 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_9_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_9_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_11_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_11_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : IN std_logic; twdl_3_9_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_9_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_10_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_10_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_10_vld : IN std_logic; softReset : IN std_logic; twdlXdin_9_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_9_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_10_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_10_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_9_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_2_block5 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_13 : IN std_logic; -- ufix1 dout_6_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_6_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_14_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_14_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_13_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_13_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_14_re_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_14_im_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_2_block6 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_15 : IN std_logic; -- ufix1 dout_8_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_8_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_16_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_16_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_15_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_15_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_16_re_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_16_im_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_11 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_11_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_11_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_11_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_12 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_12_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_12_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_12_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLMULT_SDNF1_3_block4 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_13_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_13_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_15_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_15_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : IN std_logic; twdl_3_11_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_11_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_12_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_12_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_12_vld : IN std_logic; softReset : IN std_logic; twdlXdin_11_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_11_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_12_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_12_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_11_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_3_block3 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_9_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_9_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_11_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_11_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_9_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_9_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_10_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_10_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_9_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_3_block4 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_10_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_10_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_12_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_12_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_11_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_11_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_12_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_12_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_11_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_4_block3 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_9 : IN std_logic; -- ufix1 dout_9_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_9_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_11_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_11_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_9_re_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_9_im_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_10_re : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_10_im : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_4_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_4_block4 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_11 : IN std_logic; -- ufix1 dout_10_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_10_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_12_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_12_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_11_re : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_11_im : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_12_re_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_12_im_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_4_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_14 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_14_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_14_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_14_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLMULT_SDNF1_3_block5 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_10_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_10_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_12_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_12_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : IN std_logic; twdl_3_13_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_13_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_14_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_14_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_14_vld : IN std_logic; softReset : IN std_logic; twdlXdin_13_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_13_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_14_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_14_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_13_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_15 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_15_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_15_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_15_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLROM_3_16 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_2_vld : IN std_logic; softReset : IN std_logic; twdl_3_16_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_16_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_16_vld : OUT std_logic ); END COMPONENT; COMPONENT TWDLMULT_SDNF1_3_block6 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; dout_14_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_14_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_16_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_16_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19 dout_2_vld : IN std_logic; twdl_3_15_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_15_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_16_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_16_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15 twdl_3_16_vld : IN std_logic; softReset : IN std_logic; twdlXdin_15_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_15_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_16_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_16_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_15_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_3_block5 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_13_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_13_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_15_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_15_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_13_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_13_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_14_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_14_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_13_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF1_3_block6 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_14_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_14_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_16_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_16_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_15_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_15_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_16_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_16_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_15_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_4_block5 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_13 : IN std_logic; -- ufix1 dout_13_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_13_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_15_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_15_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_13_re_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_13_im_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_14_re : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_14_im : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_4_vld : OUT std_logic ); END COMPONENT; COMPONENT RADIX22FFT_SDNF2_4_block6 PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; rotate_15 : IN std_logic; -- ufix1 dout_14_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_14_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_16_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_16_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 dout_1_vld : IN std_logic; softReset : IN std_logic; dout_15_re : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_15_im : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_16_re_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_16_im_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21 dout_4_vld : OUT std_logic ); END COMPONENT; -- Component Configuration Statements FOR ALL : RADIX22FFT_SDNF1_1 USE ENTITY work.RADIX22FFT_SDNF1_1(rtl); FOR ALL : RADIX22FFT_SDNF1_1_block3 USE ENTITY work.RADIX22FFT_SDNF1_1_block3(rtl); FOR ALL : RADIX22FFT_SDNF2_2 USE ENTITY work.RADIX22FFT_SDNF2_2(rtl); FOR ALL : RADIX22FFT_SDNF1_1_block USE ENTITY work.RADIX22FFT_SDNF1_1_block(rtl); FOR ALL : RADIX22FFT_SDNF1_1_block4 USE ENTITY work.RADIX22FFT_SDNF1_1_block4(rtl); FOR ALL : RADIX22FFT_SDNF2_2_block USE ENTITY work.RADIX22FFT_SDNF2_2_block(rtl); FOR ALL : TWDLROM_3_2 USE ENTITY work.TWDLROM_3_2(rtl); FOR ALL : TWDLMULT_SDNF1_3 USE ENTITY work.TWDLMULT_SDNF1_3(rtl); FOR ALL : RADIX22FFT_SDNF1_1_block1 USE ENTITY work.RADIX22FFT_SDNF1_1_block1(rtl); FOR ALL : RADIX22FFT_SDNF1_1_block5 USE ENTITY work.RADIX22FFT_SDNF1_1_block5(rtl); FOR ALL : RADIX22FFT_SDNF2_2_block1 USE ENTITY work.RADIX22FFT_SDNF2_2_block1(rtl); FOR ALL : RADIX22FFT_SDNF1_1_block2 USE ENTITY work.RADIX22FFT_SDNF1_1_block2(rtl); FOR ALL : RADIX22FFT_SDNF1_1_block6 USE ENTITY work.RADIX22FFT_SDNF1_1_block6(rtl); FOR ALL : RADIX22FFT_SDNF2_2_block2 USE ENTITY work.RADIX22FFT_SDNF2_2_block2(rtl); FOR ALL : TWDLROM_3_3 USE ENTITY work.TWDLROM_3_3(rtl); FOR ALL : TWDLROM_3_4 USE ENTITY work.TWDLROM_3_4(rtl); FOR ALL : TWDLMULT_SDNF1_3_block USE ENTITY work.TWDLMULT_SDNF1_3_block(rtl); FOR ALL : RADIX22FFT_SDNF1_3 USE ENTITY work.RADIX22FFT_SDNF1_3(rtl); FOR ALL : RADIX22FFT_SDNF1_3_block USE ENTITY work.RADIX22FFT_SDNF1_3_block(rtl); FOR ALL : RADIX22FFT_SDNF2_4 USE ENTITY work.RADIX22FFT_SDNF2_4(rtl); FOR ALL : RADIX22FFT_SDNF2_4_block USE ENTITY work.RADIX22FFT_SDNF2_4_block(rtl); FOR ALL : TWDLROM_3_6 USE ENTITY work.TWDLROM_3_6(rtl); FOR ALL : TWDLMULT_SDNF1_3_block1 USE ENTITY work.TWDLMULT_SDNF1_3_block1(rtl); FOR ALL : TWDLROM_3_7 USE ENTITY work.TWDLROM_3_7(rtl); FOR ALL : TWDLROM_3_8 USE ENTITY work.TWDLROM_3_8(rtl); FOR ALL : TWDLMULT_SDNF1_3_block2 USE ENTITY work.TWDLMULT_SDNF1_3_block2(rtl); FOR ALL : RADIX22FFT_SDNF1_3_block1 USE ENTITY work.RADIX22FFT_SDNF1_3_block1(rtl); FOR ALL : RADIX22FFT_SDNF1_3_block2 USE ENTITY work.RADIX22FFT_SDNF1_3_block2(rtl); FOR ALL : RADIX22FFT_SDNF2_4_block1 USE ENTITY work.RADIX22FFT_SDNF2_4_block1(rtl); FOR ALL : RADIX22FFT_SDNF2_4_block2 USE ENTITY work.RADIX22FFT_SDNF2_4_block2(rtl); FOR ALL : RADIX22FFT_SDNF2_2_block3 USE ENTITY work.RADIX22FFT_SDNF2_2_block3(rtl); FOR ALL : RADIX22FFT_SDNF2_2_block4 USE ENTITY work.RADIX22FFT_SDNF2_2_block4(rtl); FOR ALL : TWDLROM_3_10 USE ENTITY work.TWDLROM_3_10(rtl); FOR ALL : TWDLMULT_SDNF1_3_block3 USE ENTITY work.TWDLMULT_SDNF1_3_block3(rtl); FOR ALL : RADIX22FFT_SDNF2_2_block5 USE ENTITY work.RADIX22FFT_SDNF2_2_block5(rtl); FOR ALL : RADIX22FFT_SDNF2_2_block6 USE ENTITY work.RADIX22FFT_SDNF2_2_block6(rtl); FOR ALL : TWDLROM_3_11 USE ENTITY work.TWDLROM_3_11(rtl); FOR ALL : TWDLROM_3_12 USE ENTITY work.TWDLROM_3_12(rtl); FOR ALL : TWDLMULT_SDNF1_3_block4 USE ENTITY work.TWDLMULT_SDNF1_3_block4(rtl); FOR ALL : RADIX22FFT_SDNF1_3_block3 USE ENTITY work.RADIX22FFT_SDNF1_3_block3(rtl); FOR ALL : RADIX22FFT_SDNF1_3_block4 USE ENTITY work.RADIX22FFT_SDNF1_3_block4(rtl); FOR ALL : RADIX22FFT_SDNF2_4_block3 USE ENTITY work.RADIX22FFT_SDNF2_4_block3(rtl); FOR ALL : RADIX22FFT_SDNF2_4_block4 USE ENTITY work.RADIX22FFT_SDNF2_4_block4(rtl); FOR ALL : TWDLROM_3_14 USE ENTITY work.TWDLROM_3_14(rtl); FOR ALL : TWDLMULT_SDNF1_3_block5 USE ENTITY work.TWDLMULT_SDNF1_3_block5(rtl); FOR ALL : TWDLROM_3_15 USE ENTITY work.TWDLROM_3_15(rtl); FOR ALL : TWDLROM_3_16 USE ENTITY work.TWDLROM_3_16(rtl); FOR ALL : TWDLMULT_SDNF1_3_block6 USE ENTITY work.TWDLMULT_SDNF1_3_block6(rtl); FOR ALL : RADIX22FFT_SDNF1_3_block5 USE ENTITY work.RADIX22FFT_SDNF1_3_block5(rtl); FOR ALL : RADIX22FFT_SDNF1_3_block6 USE ENTITY work.RADIX22FFT_SDNF1_3_block6(rtl); FOR ALL : RADIX22FFT_SDNF2_4_block5 USE ENTITY work.RADIX22FFT_SDNF2_4_block5(rtl); FOR ALL : RADIX22FFT_SDNF2_4_block6 USE ENTITY work.RADIX22FFT_SDNF2_4_block6(rtl); -- Signals SIGNAL rotate_1 : std_logic; -- ufix1 SIGNAL rotate_1_1 : std_logic; -- ufix1 SIGNAL dataIn_0 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_1_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_1_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_8 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_9_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_9_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL twdlXdin_1_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_1_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_9_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_9_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_1_vld : std_logic; SIGNAL softReset : std_logic; SIGNAL dout_1_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_1_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_2_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_2_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_1_vld : std_logic; SIGNAL dataIn_4 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_5_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_5_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_12 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_13_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_13_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL twdlXdin_5_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_5_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_13_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_13_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL dout_9_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_9_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_10_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_10_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_9_vld : std_logic; SIGNAL dout_1_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_1_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_2_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_2_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_2_vld : std_logic; SIGNAL rotate_3 : std_logic; -- ufix1 SIGNAL dataIn_1 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_2_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_2_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_9 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_10_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_10_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL twdlXdin_2_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_2_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_10_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_10_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL dout_3_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_3_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_4_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_4_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_3_vld : std_logic; SIGNAL dataIn_5 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_6_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_6_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_13 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_14_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_14_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL twdlXdin_6_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_6_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_14_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_14_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL dout_11_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_11_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_12_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_12_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_11_vld : std_logic; SIGNAL dout_3_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_3_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_4_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_4_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_2_vld_1 : std_logic; SIGNAL twdl_3_1_re : signed(16 DOWNTO 0); -- sfix17_En15 SIGNAL twdl_3_1_im : signed(16 DOWNTO 0); -- sfix17_En15 SIGNAL twdl_3_2_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_2_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_2_vld : std_logic; SIGNAL twdlXdin_1_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_1_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_2_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_2_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_1_vld_1 : std_logic; SIGNAL rotate_5 : std_logic; -- ufix1 SIGNAL dataIn_2 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_3_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_3_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_10 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_11_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_11_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL twdlXdin_3_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_3_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_11_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_11_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL dout_5_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_5_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_6_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_6_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_5_vld : std_logic; SIGNAL dataIn_6 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_7_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_7_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_14 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_15_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_15_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL twdlXdin_7_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_7_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_15_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_15_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL dout_13_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_13_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_14_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_14_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_13_vld : std_logic; SIGNAL dout_5_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_5_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_6_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_6_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_2_vld_2 : std_logic; SIGNAL rotate_7 : std_logic; -- ufix1 SIGNAL dataIn_3 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_4_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_4_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_11 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_12_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_12_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL twdlXdin_4_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_4_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_12_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_12_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL dout_7_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_7_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_8_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_8_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_7_vld : std_logic; SIGNAL dataIn_7 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_8_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_8_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_15 : unsigned(15 DOWNTO 0); -- uint16 SIGNAL dataIn_16_cast_re : signed(16 DOWNTO 0); -- sfix17 SIGNAL dataIn_16_cast_im : signed(16 DOWNTO 0); -- sfix17 SIGNAL twdlXdin_8_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_8_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_16_re : signed(17 DOWNTO 0); -- sfix18 SIGNAL twdlXdin_16_im : signed(17 DOWNTO 0); -- sfix18 SIGNAL dout_15_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_15_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_16_re : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_16_im : std_logic_vector(17 DOWNTO 0); -- ufix18 SIGNAL dout_15_vld : std_logic; SIGNAL dout_7_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_7_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_8_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_8_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_2_vld_3 : std_logic; SIGNAL twdl_3_3_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_3_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_3_vld : std_logic; SIGNAL twdl_3_4_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_4_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_4_vld : std_logic; SIGNAL twdlXdin_3_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_3_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_4_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_4_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_3_vld : std_logic; SIGNAL dout_1_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_1_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_2_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_2_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_1_vld_1 : std_logic; SIGNAL dout_3_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_3_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_4_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_4_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_3_vld_1 : std_logic; SIGNAL dout_4_vld : std_logic; SIGNAL rotate_3_1 : std_logic; -- ufix1 SIGNAL dout_4_vld_1 : std_logic; SIGNAL rotate_5_1 : std_logic; -- ufix1 SIGNAL twdl_3_5_re : signed(16 DOWNTO 0); -- sfix17_En15 SIGNAL twdl_3_5_im : signed(16 DOWNTO 0); -- sfix17_En15 SIGNAL twdl_3_6_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_6_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_6_vld : std_logic; SIGNAL twdlXdin_5_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_5_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_6_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_6_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_5_vld : std_logic; SIGNAL twdl_3_7_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_7_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_7_vld : std_logic; SIGNAL twdl_3_8_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_8_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_8_vld : std_logic; SIGNAL twdlXdin_7_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_7_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_8_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_8_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_7_vld : std_logic; SIGNAL dout_5_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_5_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_6_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_6_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_5_vld_1 : std_logic; SIGNAL dout_7_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_7_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_8_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_8_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_7_vld_1 : std_logic; SIGNAL dout_4_vld_2 : std_logic; SIGNAL rotate_7_1 : std_logic; -- ufix1 SIGNAL dout_4_vld_3 : std_logic; SIGNAL rotate_9 : std_logic; -- ufix1 SIGNAL rotate_9_1 : std_logic; -- ufix1 SIGNAL dout_9_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_9_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_10_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_10_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_2_vld_4 : std_logic; SIGNAL rotate_11 : std_logic; -- ufix1 SIGNAL dout_11_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_11_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_12_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_12_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_2_vld_5 : std_logic; SIGNAL twdl_3_9_re : signed(16 DOWNTO 0); -- sfix17_En15 SIGNAL twdl_3_9_im : signed(16 DOWNTO 0); -- sfix17_En15 SIGNAL twdl_3_10_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_10_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_10_vld : std_logic; SIGNAL twdlXdin_9_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_9_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_10_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_10_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_9_vld : std_logic; SIGNAL rotate_13 : std_logic; -- ufix1 SIGNAL dout_13_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_13_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_14_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_14_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_2_vld_6 : std_logic; SIGNAL rotate_15 : std_logic; -- ufix1 SIGNAL dout_15_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_15_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_16_re_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_16_im_1 : std_logic_vector(18 DOWNTO 0); -- ufix19 SIGNAL dout_2_vld_7 : std_logic; SIGNAL twdl_3_11_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_11_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_11_vld : std_logic; SIGNAL twdl_3_12_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_12_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_12_vld : std_logic; SIGNAL twdlXdin_11_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_11_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_12_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_12_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_11_vld : std_logic; SIGNAL dout_9_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_9_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_10_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_10_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_9_vld_1 : std_logic; SIGNAL dout_11_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_11_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_12_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_12_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_11_vld_1 : std_logic; SIGNAL dout_4_vld_4 : std_logic; SIGNAL rotate_11_1 : std_logic; -- ufix1 SIGNAL dout_4_vld_5 : std_logic; SIGNAL rotate_13_1 : std_logic; -- ufix1 SIGNAL twdl_3_13_re : signed(16 DOWNTO 0); -- sfix17_En15 SIGNAL twdl_3_13_im : signed(16 DOWNTO 0); -- sfix17_En15 SIGNAL twdl_3_14_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_14_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_14_vld : std_logic; SIGNAL twdlXdin_13_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_13_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_14_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_14_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_13_vld : std_logic; SIGNAL twdl_3_15_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_15_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_15_vld : std_logic; SIGNAL twdl_3_16_re : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_16_im : std_logic_vector(16 DOWNTO 0); -- ufix17 SIGNAL twdl_3_16_vld : std_logic; SIGNAL twdlXdin_15_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_15_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_16_re_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_16_im_1 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL twdlXdin_15_vld : std_logic; SIGNAL dout_13_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_13_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_14_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_14_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_13_vld_1 : std_logic; SIGNAL dout_15_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_15_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_16_re_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_16_im_2 : std_logic_vector(19 DOWNTO 0); -- ufix20 SIGNAL dout_15_vld_1 : std_logic; SIGNAL dout_4_vld_6 : std_logic; SIGNAL rotate_15_1 : std_logic; -- ufix1 SIGNAL dout_4_vld_7 : std_logic; SIGNAL dataOut_re_tmp : vector_of_std_logic_vector21(0 TO 15); -- ufix21 [16] SIGNAL dataOut_im_tmp : vector_of_std_logic_vector21(0 TO 15); -- ufix21 [16] BEGIN u_SDNF1_1_1 : RADIX22FFT_SDNF1_1 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_1_re => std_logic_vector(twdlXdin_1_re), -- sfix18 twdlXdin_1_im => std_logic_vector(twdlXdin_1_im), -- sfix18 twdlXdin_9_re => std_logic_vector(twdlXdin_9_re), -- sfix18 twdlXdin_9_im => std_logic_vector(twdlXdin_9_im), -- sfix18 twdlXdin_1_vld => twdlXdin_1_vld, softReset => softReset, dout_1_re => dout_1_re, -- sfix18 dout_1_im => dout_1_im, -- sfix18 dout_2_re => dout_2_re, -- sfix18 dout_2_im => dout_2_im, -- sfix18 dout_1_vld => dout_1_vld ); u_SDNF1_1_9 : RADIX22FFT_SDNF1_1_block3 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_5_re => std_logic_vector(twdlXdin_5_re), -- sfix18 twdlXdin_5_im => std_logic_vector(twdlXdin_5_im), -- sfix18 twdlXdin_13_re => std_logic_vector(twdlXdin_13_re), -- sfix18 twdlXdin_13_im => std_logic_vector(twdlXdin_13_im), -- sfix18 twdlXdin_1_vld => twdlXdin_1_vld, softReset => softReset, dout_9_re => dout_9_re, -- sfix18 dout_9_im => dout_9_im, -- sfix18 dout_10_re => dout_10_re, -- sfix18 dout_10_im => dout_10_im, -- sfix18 dout_9_vld => dout_9_vld ); u_SDNF2_2_1 : RADIX22FFT_SDNF2_2 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_1 => rotate_1_1, -- ufix1 dout_1_re => dout_1_re, -- sfix18 dout_1_im => dout_1_im, -- sfix18 dout_9_re => dout_9_re, -- sfix18 dout_9_im => dout_9_im, -- sfix18 dout_1_vld => dout_1_vld, softReset => softReset, dout_1_re_1 => dout_1_re_1, -- sfix19 dout_1_im_1 => dout_1_im_1, -- sfix19 dout_2_re => dout_2_re_1, -- sfix19 dout_2_im => dout_2_im_1, -- sfix19 dout_2_vld => dout_2_vld ); u_SDNF1_1_3 : RADIX22FFT_SDNF1_1_block PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_2_re => std_logic_vector(twdlXdin_2_re), -- sfix18 twdlXdin_2_im => std_logic_vector(twdlXdin_2_im), -- sfix18 twdlXdin_10_re => std_logic_vector(twdlXdin_10_re), -- sfix18 twdlXdin_10_im => std_logic_vector(twdlXdin_10_im), -- sfix18 twdlXdin_1_vld => twdlXdin_1_vld, softReset => softReset, dout_3_re => dout_3_re, -- sfix18 dout_3_im => dout_3_im, -- sfix18 dout_4_re => dout_4_re, -- sfix18 dout_4_im => dout_4_im, -- sfix18 dout_3_vld => dout_3_vld ); u_SDNF1_1_11 : RADIX22FFT_SDNF1_1_block4 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_6_re => std_logic_vector(twdlXdin_6_re), -- sfix18 twdlXdin_6_im => std_logic_vector(twdlXdin_6_im), -- sfix18 twdlXdin_14_re => std_logic_vector(twdlXdin_14_re), -- sfix18 twdlXdin_14_im => std_logic_vector(twdlXdin_14_im), -- sfix18 twdlXdin_1_vld => twdlXdin_1_vld, softReset => softReset, dout_11_re => dout_11_re, -- sfix18 dout_11_im => dout_11_im, -- sfix18 dout_12_re => dout_12_re, -- sfix18 dout_12_im => dout_12_im, -- sfix18 dout_11_vld => dout_11_vld ); u_SDNF2_2_3 : RADIX22FFT_SDNF2_2_block PORT MAP( clk => clk, reset => reset, enb => enb, rotate_3 => rotate_3, -- ufix1 dout_3_re => dout_3_re, -- sfix18 dout_3_im => dout_3_im, -- sfix18 dout_11_re => dout_11_re, -- sfix18 dout_11_im => dout_11_im, -- sfix18 dout_1_vld => dout_1_vld, softReset => softReset, dout_3_re_1 => dout_3_re_1, -- sfix19 dout_3_im_1 => dout_3_im_1, -- sfix19 dout_4_re => dout_4_re_1, -- sfix19 dout_4_im => dout_4_im_1, -- sfix19 dout_2_vld => dout_2_vld_1 ); u_twdlROM_3_2 : TWDLROM_3_2 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_2_re => twdl_3_2_re, -- sfix17_En15 twdl_3_2_im => twdl_3_2_im, -- sfix17_En15 twdl_3_2_vld => twdl_3_2_vld ); u_TWDLMULT_SDNF1_3_1 : TWDLMULT_SDNF1_3 PORT MAP( clk => clk, reset => reset, enb => enb, dout_1_re => dout_1_re_1, -- sfix19 dout_1_im => dout_1_im_1, -- sfix19 dout_3_re => dout_3_re_1, -- sfix19 dout_3_im => dout_3_im_1, -- sfix19 dout_2_vld => dout_2_vld, twdl_3_1_re => std_logic_vector(twdl_3_1_re), -- sfix17_En15 twdl_3_1_im => std_logic_vector(twdl_3_1_im), -- sfix17_En15 twdl_3_2_re => twdl_3_2_re, -- sfix17_En15 twdl_3_2_im => twdl_3_2_im, -- sfix17_En15 twdl_3_2_vld => twdl_3_2_vld, softReset => softReset, twdlXdin_1_re => twdlXdin_1_re_1, -- sfix20 twdlXdin_1_im => twdlXdin_1_im_1, -- sfix20 twdlXdin_2_re => twdlXdin_2_re_1, -- sfix20 twdlXdin_2_im => twdlXdin_2_im_1, -- sfix20 twdlXdin_1_vld => twdlXdin_1_vld_1 ); u_SDNF1_1_5 : RADIX22FFT_SDNF1_1_block1 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_3_re => std_logic_vector(twdlXdin_3_re), -- sfix18 twdlXdin_3_im => std_logic_vector(twdlXdin_3_im), -- sfix18 twdlXdin_11_re => std_logic_vector(twdlXdin_11_re), -- sfix18 twdlXdin_11_im => std_logic_vector(twdlXdin_11_im), -- sfix18 twdlXdin_1_vld => twdlXdin_1_vld, softReset => softReset, dout_5_re => dout_5_re, -- sfix18 dout_5_im => dout_5_im, -- sfix18 dout_6_re => dout_6_re, -- sfix18 dout_6_im => dout_6_im, -- sfix18 dout_5_vld => dout_5_vld ); u_SDNF1_1_13 : RADIX22FFT_SDNF1_1_block5 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_7_re => std_logic_vector(twdlXdin_7_re), -- sfix18 twdlXdin_7_im => std_logic_vector(twdlXdin_7_im), -- sfix18 twdlXdin_15_re => std_logic_vector(twdlXdin_15_re), -- sfix18 twdlXdin_15_im => std_logic_vector(twdlXdin_15_im), -- sfix18 twdlXdin_1_vld => twdlXdin_1_vld, softReset => softReset, dout_13_re => dout_13_re, -- sfix18 dout_13_im => dout_13_im, -- sfix18 dout_14_re => dout_14_re, -- sfix18 dout_14_im => dout_14_im, -- sfix18 dout_13_vld => dout_13_vld ); u_SDNF2_2_5 : RADIX22FFT_SDNF2_2_block1 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_5 => rotate_5, -- ufix1 dout_5_re => dout_5_re, -- sfix18 dout_5_im => dout_5_im, -- sfix18 dout_13_re => dout_13_re, -- sfix18 dout_13_im => dout_13_im, -- sfix18 dout_1_vld => dout_1_vld, softReset => softReset, dout_5_re_1 => dout_5_re_1, -- sfix19 dout_5_im_1 => dout_5_im_1, -- sfix19 dout_6_re => dout_6_re_1, -- sfix19 dout_6_im => dout_6_im_1, -- sfix19 dout_2_vld => dout_2_vld_2 ); u_SDNF1_1_7 : RADIX22FFT_SDNF1_1_block2 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_4_re => std_logic_vector(twdlXdin_4_re), -- sfix18 twdlXdin_4_im => std_logic_vector(twdlXdin_4_im), -- sfix18 twdlXdin_12_re => std_logic_vector(twdlXdin_12_re), -- sfix18 twdlXdin_12_im => std_logic_vector(twdlXdin_12_im), -- sfix18 twdlXdin_1_vld => twdlXdin_1_vld, softReset => softReset, dout_7_re => dout_7_re, -- sfix18 dout_7_im => dout_7_im, -- sfix18 dout_8_re => dout_8_re, -- sfix18 dout_8_im => dout_8_im, -- sfix18 dout_7_vld => dout_7_vld ); u_SDNF1_1_15 : RADIX22FFT_SDNF1_1_block6 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_8_re => std_logic_vector(twdlXdin_8_re), -- sfix18 twdlXdin_8_im => std_logic_vector(twdlXdin_8_im), -- sfix18 twdlXdin_16_re => std_logic_vector(twdlXdin_16_re), -- sfix18 twdlXdin_16_im => std_logic_vector(twdlXdin_16_im), -- sfix18 twdlXdin_1_vld => twdlXdin_1_vld, softReset => softReset, dout_15_re => dout_15_re, -- sfix18 dout_15_im => dout_15_im, -- sfix18 dout_16_re => dout_16_re, -- sfix18 dout_16_im => dout_16_im, -- sfix18 dout_15_vld => dout_15_vld ); u_SDNF2_2_7 : RADIX22FFT_SDNF2_2_block2 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_7 => rotate_7, -- ufix1 dout_7_re => dout_7_re, -- sfix18 dout_7_im => dout_7_im, -- sfix18 dout_15_re => dout_15_re, -- sfix18 dout_15_im => dout_15_im, -- sfix18 dout_1_vld => dout_1_vld, softReset => softReset, dout_7_re_1 => dout_7_re_1, -- sfix19 dout_7_im_1 => dout_7_im_1, -- sfix19 dout_8_re => dout_8_re_1, -- sfix19 dout_8_im => dout_8_im_1, -- sfix19 dout_2_vld => dout_2_vld_3 ); u_twdlROM_3_3 : TWDLROM_3_3 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_3_re => twdl_3_3_re, -- sfix17_En15 twdl_3_3_im => twdl_3_3_im, -- sfix17_En15 twdl_3_3_vld => twdl_3_3_vld ); u_twdlROM_3_4 : TWDLROM_3_4 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_4_re => twdl_3_4_re, -- sfix17_En15 twdl_3_4_im => twdl_3_4_im, -- sfix17_En15 twdl_3_4_vld => twdl_3_4_vld ); u_TWDLMULT_SDNF1_3_3 : TWDLMULT_SDNF1_3_block PORT MAP( clk => clk, reset => reset, enb => enb, dout_5_re => dout_5_re_1, -- sfix19 dout_5_im => dout_5_im_1, -- sfix19 dout_7_re => dout_7_re_1, -- sfix19 dout_7_im => dout_7_im_1, -- sfix19 dout_2_vld => dout_2_vld, twdl_3_3_re => twdl_3_3_re, -- sfix17_En15 twdl_3_3_im => twdl_3_3_im, -- sfix17_En15 twdl_3_4_re => twdl_3_4_re, -- sfix17_En15 twdl_3_4_im => twdl_3_4_im, -- sfix17_En15 twdl_3_4_vld => twdl_3_4_vld, softReset => softReset, twdlXdin_3_re => twdlXdin_3_re_1, -- sfix20 twdlXdin_3_im => twdlXdin_3_im_1, -- sfix20 twdlXdin_4_re => twdlXdin_4_re_1, -- sfix20 twdlXdin_4_im => twdlXdin_4_im_1, -- sfix20 twdlXdin_3_vld => twdlXdin_3_vld ); u_SDNF1_3_1 : RADIX22FFT_SDNF1_3 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_1_re => twdlXdin_1_re_1, -- sfix20 twdlXdin_1_im => twdlXdin_1_im_1, -- sfix20 twdlXdin_3_re => twdlXdin_3_re_1, -- sfix20 twdlXdin_3_im => twdlXdin_3_im_1, -- sfix20 twdlXdin_1_vld => twdlXdin_1_vld_1, softReset => softReset, dout_1_re => dout_1_re_2, -- sfix20 dout_1_im => dout_1_im_2, -- sfix20 dout_2_re => dout_2_re_2, -- sfix20 dout_2_im => dout_2_im_2, -- sfix20 dout_1_vld => dout_1_vld_1 ); u_SDNF1_3_3 : RADIX22FFT_SDNF1_3_block PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_2_re => twdlXdin_2_re_1, -- sfix20 twdlXdin_2_im => twdlXdin_2_im_1, -- sfix20 twdlXdin_4_re => twdlXdin_4_re_1, -- sfix20 twdlXdin_4_im => twdlXdin_4_im_1, -- sfix20 twdlXdin_1_vld => twdlXdin_1_vld_1, softReset => softReset, dout_3_re => dout_3_re_2, -- sfix20 dout_3_im => dout_3_im_2, -- sfix20 dout_4_re => dout_4_re_2, -- sfix20 dout_4_im => dout_4_im_2, -- sfix20 dout_3_vld => dout_3_vld_1 ); u_SDNF2_4_1 : RADIX22FFT_SDNF2_4 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_1 => rotate_1, -- ufix1 dout_1_re => dout_1_re_2, -- sfix20 dout_1_im => dout_1_im_2, -- sfix20 dout_3_re => dout_3_re_2, -- sfix20 dout_3_im => dout_3_im_2, -- sfix20 dout_1_vld => dout_1_vld_1, softReset => softReset, dout_1_re_1 => dataOut_re_tmp(0), -- sfix21 dout_1_im_1 => dataOut_im_tmp(0), -- sfix21 dout_2_re => dataOut_re_tmp(1), -- sfix21 dout_2_im => dataOut_im_tmp(1), -- sfix21 dout_4_vld => dout_4_vld ); u_SDNF2_4_3 : RADIX22FFT_SDNF2_4_block PORT MAP( clk => clk, reset => reset, enb => enb, rotate_3 => rotate_3_1, -- ufix1 dout_2_re => dout_2_re_2, -- sfix20 dout_2_im => dout_2_im_2, -- sfix20 dout_4_re => dout_4_re_2, -- sfix20 dout_4_im => dout_4_im_2, -- sfix20 dout_1_vld => dout_1_vld_1, softReset => softReset, dout_3_re => dataOut_re_tmp(2), -- sfix21 dout_3_im => dataOut_im_tmp(2), -- sfix21 dout_4_re_1 => dataOut_re_tmp(3), -- sfix21 dout_4_im_1 => dataOut_im_tmp(3), -- sfix21 dout_4_vld => dout_4_vld_1 ); u_twdlROM_3_6 : TWDLROM_3_6 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_6_re => twdl_3_6_re, -- sfix17_En15 twdl_3_6_im => twdl_3_6_im, -- sfix17_En15 twdl_3_6_vld => twdl_3_6_vld ); u_TWDLMULT_SDNF1_3_5 : TWDLMULT_SDNF1_3_block1 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_re => dout_2_re_1, -- sfix19 dout_2_im => dout_2_im_1, -- sfix19 dout_4_re => dout_4_re_1, -- sfix19 dout_4_im => dout_4_im_1, -- sfix19 dout_2_vld => dout_2_vld, twdl_3_5_re => std_logic_vector(twdl_3_5_re), -- sfix17_En15 twdl_3_5_im => std_logic_vector(twdl_3_5_im), -- sfix17_En15 twdl_3_6_re => twdl_3_6_re, -- sfix17_En15 twdl_3_6_im => twdl_3_6_im, -- sfix17_En15 twdl_3_6_vld => twdl_3_6_vld, softReset => softReset, twdlXdin_5_re => twdlXdin_5_re_1, -- sfix20 twdlXdin_5_im => twdlXdin_5_im_1, -- sfix20 twdlXdin_6_re => twdlXdin_6_re_1, -- sfix20 twdlXdin_6_im => twdlXdin_6_im_1, -- sfix20 twdlXdin_5_vld => twdlXdin_5_vld ); u_twdlROM_3_7 : TWDLROM_3_7 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_7_re => twdl_3_7_re, -- sfix17_En15 twdl_3_7_im => twdl_3_7_im, -- sfix17_En15 twdl_3_7_vld => twdl_3_7_vld ); u_twdlROM_3_8 : TWDLROM_3_8 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_8_re => twdl_3_8_re, -- sfix17_En15 twdl_3_8_im => twdl_3_8_im, -- sfix17_En15 twdl_3_8_vld => twdl_3_8_vld ); u_TWDLMULT_SDNF1_3_7 : TWDLMULT_SDNF1_3_block2 PORT MAP( clk => clk, reset => reset, enb => enb, dout_6_re => dout_6_re_1, -- sfix19 dout_6_im => dout_6_im_1, -- sfix19 dout_8_re => dout_8_re_1, -- sfix19 dout_8_im => dout_8_im_1, -- sfix19 dout_2_vld => dout_2_vld, twdl_3_7_re => twdl_3_7_re, -- sfix17_En15 twdl_3_7_im => twdl_3_7_im, -- sfix17_En15 twdl_3_8_re => twdl_3_8_re, -- sfix17_En15 twdl_3_8_im => twdl_3_8_im, -- sfix17_En15 twdl_3_8_vld => twdl_3_8_vld, softReset => softReset, twdlXdin_7_re => twdlXdin_7_re_1, -- sfix20 twdlXdin_7_im => twdlXdin_7_im_1, -- sfix20 twdlXdin_8_re => twdlXdin_8_re_1, -- sfix20 twdlXdin_8_im => twdlXdin_8_im_1, -- sfix20 twdlXdin_7_vld => twdlXdin_7_vld ); u_SDNF1_3_5 : RADIX22FFT_SDNF1_3_block1 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_5_re => twdlXdin_5_re_1, -- sfix20 twdlXdin_5_im => twdlXdin_5_im_1, -- sfix20 twdlXdin_7_re => twdlXdin_7_re_1, -- sfix20 twdlXdin_7_im => twdlXdin_7_im_1, -- sfix20 twdlXdin_1_vld => twdlXdin_1_vld_1, softReset => softReset, dout_5_re => dout_5_re_2, -- sfix20 dout_5_im => dout_5_im_2, -- sfix20 dout_6_re => dout_6_re_2, -- sfix20 dout_6_im => dout_6_im_2, -- sfix20 dout_5_vld => dout_5_vld_1 ); u_SDNF1_3_7 : RADIX22FFT_SDNF1_3_block2 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_6_re => twdlXdin_6_re_1, -- sfix20 twdlXdin_6_im => twdlXdin_6_im_1, -- sfix20 twdlXdin_8_re => twdlXdin_8_re_1, -- sfix20 twdlXdin_8_im => twdlXdin_8_im_1, -- sfix20 twdlXdin_1_vld => twdlXdin_1_vld_1, softReset => softReset, dout_7_re => dout_7_re_2, -- sfix20 dout_7_im => dout_7_im_2, -- sfix20 dout_8_re => dout_8_re_2, -- sfix20 dout_8_im => dout_8_im_2, -- sfix20 dout_7_vld => dout_7_vld_1 ); u_SDNF2_4_5 : RADIX22FFT_SDNF2_4_block1 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_5 => rotate_5_1, -- ufix1 dout_5_re => dout_5_re_2, -- sfix20 dout_5_im => dout_5_im_2, -- sfix20 dout_7_re => dout_7_re_2, -- sfix20 dout_7_im => dout_7_im_2, -- sfix20 dout_1_vld => dout_1_vld_1, softReset => softReset, dout_5_re_1 => dataOut_re_tmp(4), -- sfix21 dout_5_im_1 => dataOut_im_tmp(4), -- sfix21 dout_6_re => dataOut_re_tmp(5), -- sfix21 dout_6_im => dataOut_im_tmp(5), -- sfix21 dout_4_vld => dout_4_vld_2 ); u_SDNF2_4_7 : RADIX22FFT_SDNF2_4_block2 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_7 => rotate_7_1, -- ufix1 dout_6_re => dout_6_re_2, -- sfix20 dout_6_im => dout_6_im_2, -- sfix20 dout_8_re => dout_8_re_2, -- sfix20 dout_8_im => dout_8_im_2, -- sfix20 dout_1_vld => dout_1_vld_1, softReset => softReset, dout_7_re => dataOut_re_tmp(6), -- sfix21 dout_7_im => dataOut_im_tmp(6), -- sfix21 dout_8_re_1 => dataOut_re_tmp(7), -- sfix21 dout_8_im_1 => dataOut_im_tmp(7), -- sfix21 dout_4_vld => dout_4_vld_3 ); u_SDNF2_2_9 : RADIX22FFT_SDNF2_2_block3 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_9 => rotate_9_1, -- ufix1 dout_2_re => dout_2_re, -- sfix18 dout_2_im => dout_2_im, -- sfix18 dout_10_re => dout_10_re, -- sfix18 dout_10_im => dout_10_im, -- sfix18 dout_1_vld => dout_1_vld, softReset => softReset, dout_9_re => dout_9_re_1, -- sfix19 dout_9_im => dout_9_im_1, -- sfix19 dout_10_re_1 => dout_10_re_1, -- sfix19 dout_10_im_1 => dout_10_im_1, -- sfix19 dout_2_vld => dout_2_vld_4 ); u_SDNF2_2_11 : RADIX22FFT_SDNF2_2_block4 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_11 => rotate_11, -- ufix1 dout_4_re => dout_4_re, -- sfix18 dout_4_im => dout_4_im, -- sfix18 dout_12_re => dout_12_re, -- sfix18 dout_12_im => dout_12_im, -- sfix18 dout_1_vld => dout_1_vld, softReset => softReset, dout_11_re => dout_11_re_1, -- sfix19 dout_11_im => dout_11_im_1, -- sfix19 dout_12_re_1 => dout_12_re_1, -- sfix19 dout_12_im_1 => dout_12_im_1, -- sfix19 dout_2_vld => dout_2_vld_5 ); u_twdlROM_3_10 : TWDLROM_3_10 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_10_re => twdl_3_10_re, -- sfix17_En15 twdl_3_10_im => twdl_3_10_im, -- sfix17_En15 twdl_3_10_vld => twdl_3_10_vld ); u_TWDLMULT_SDNF1_3_9 : TWDLMULT_SDNF1_3_block3 PORT MAP( clk => clk, reset => reset, enb => enb, dout_9_re => dout_9_re_1, -- sfix19 dout_9_im => dout_9_im_1, -- sfix19 dout_11_re => dout_11_re_1, -- sfix19 dout_11_im => dout_11_im_1, -- sfix19 dout_2_vld => dout_2_vld, twdl_3_9_re => std_logic_vector(twdl_3_9_re), -- sfix17_En15 twdl_3_9_im => std_logic_vector(twdl_3_9_im), -- sfix17_En15 twdl_3_10_re => twdl_3_10_re, -- sfix17_En15 twdl_3_10_im => twdl_3_10_im, -- sfix17_En15 twdl_3_10_vld => twdl_3_10_vld, softReset => softReset, twdlXdin_9_re => twdlXdin_9_re_1, -- sfix20 twdlXdin_9_im => twdlXdin_9_im_1, -- sfix20 twdlXdin_10_re => twdlXdin_10_re_1, -- sfix20 twdlXdin_10_im => twdlXdin_10_im_1, -- sfix20 twdlXdin_9_vld => twdlXdin_9_vld ); u_SDNF2_2_13 : RADIX22FFT_SDNF2_2_block5 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_13 => rotate_13, -- ufix1 dout_6_re => dout_6_re, -- sfix18 dout_6_im => dout_6_im, -- sfix18 dout_14_re => dout_14_re, -- sfix18 dout_14_im => dout_14_im, -- sfix18 dout_1_vld => dout_1_vld, softReset => softReset, dout_13_re => dout_13_re_1, -- sfix19 dout_13_im => dout_13_im_1, -- sfix19 dout_14_re_1 => dout_14_re_1, -- sfix19 dout_14_im_1 => dout_14_im_1, -- sfix19 dout_2_vld => dout_2_vld_6 ); u_SDNF2_2_15 : RADIX22FFT_SDNF2_2_block6 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_15 => rotate_15, -- ufix1 dout_8_re => dout_8_re, -- sfix18 dout_8_im => dout_8_im, -- sfix18 dout_16_re => dout_16_re, -- sfix18 dout_16_im => dout_16_im, -- sfix18 dout_1_vld => dout_1_vld, softReset => softReset, dout_15_re => dout_15_re_1, -- sfix19 dout_15_im => dout_15_im_1, -- sfix19 dout_16_re_1 => dout_16_re_1, -- sfix19 dout_16_im_1 => dout_16_im_1, -- sfix19 dout_2_vld => dout_2_vld_7 ); u_twdlROM_3_11 : TWDLROM_3_11 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_11_re => twdl_3_11_re, -- sfix17_En15 twdl_3_11_im => twdl_3_11_im, -- sfix17_En15 twdl_3_11_vld => twdl_3_11_vld ); u_twdlROM_3_12 : TWDLROM_3_12 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_12_re => twdl_3_12_re, -- sfix17_En15 twdl_3_12_im => twdl_3_12_im, -- sfix17_En15 twdl_3_12_vld => twdl_3_12_vld ); u_TWDLMULT_SDNF1_3_11 : TWDLMULT_SDNF1_3_block4 PORT MAP( clk => clk, reset => reset, enb => enb, dout_13_re => dout_13_re_1, -- sfix19 dout_13_im => dout_13_im_1, -- sfix19 dout_15_re => dout_15_re_1, -- sfix19 dout_15_im => dout_15_im_1, -- sfix19 dout_2_vld => dout_2_vld, twdl_3_11_re => twdl_3_11_re, -- sfix17_En15 twdl_3_11_im => twdl_3_11_im, -- sfix17_En15 twdl_3_12_re => twdl_3_12_re, -- sfix17_En15 twdl_3_12_im => twdl_3_12_im, -- sfix17_En15 twdl_3_12_vld => twdl_3_12_vld, softReset => softReset, twdlXdin_11_re => twdlXdin_11_re_1, -- sfix20 twdlXdin_11_im => twdlXdin_11_im_1, -- sfix20 twdlXdin_12_re => twdlXdin_12_re_1, -- sfix20 twdlXdin_12_im => twdlXdin_12_im_1, -- sfix20 twdlXdin_11_vld => twdlXdin_11_vld ); u_SDNF1_3_9 : RADIX22FFT_SDNF1_3_block3 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_9_re => twdlXdin_9_re_1, -- sfix20 twdlXdin_9_im => twdlXdin_9_im_1, -- sfix20 twdlXdin_11_re => twdlXdin_11_re_1, -- sfix20 twdlXdin_11_im => twdlXdin_11_im_1, -- sfix20 twdlXdin_1_vld => twdlXdin_1_vld_1, softReset => softReset, dout_9_re => dout_9_re_2, -- sfix20 dout_9_im => dout_9_im_2, -- sfix20 dout_10_re => dout_10_re_2, -- sfix20 dout_10_im => dout_10_im_2, -- sfix20 dout_9_vld => dout_9_vld_1 ); u_SDNF1_3_11 : RADIX22FFT_SDNF1_3_block4 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_10_re => twdlXdin_10_re_1, -- sfix20 twdlXdin_10_im => twdlXdin_10_im_1, -- sfix20 twdlXdin_12_re => twdlXdin_12_re_1, -- sfix20 twdlXdin_12_im => twdlXdin_12_im_1, -- sfix20 twdlXdin_1_vld => twdlXdin_1_vld_1, softReset => softReset, dout_11_re => dout_11_re_2, -- sfix20 dout_11_im => dout_11_im_2, -- sfix20 dout_12_re => dout_12_re_2, -- sfix20 dout_12_im => dout_12_im_2, -- sfix20 dout_11_vld => dout_11_vld_1 ); u_SDNF2_4_9 : RADIX22FFT_SDNF2_4_block3 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_9 => rotate_9, -- ufix1 dout_9_re => dout_9_re_2, -- sfix20 dout_9_im => dout_9_im_2, -- sfix20 dout_11_re => dout_11_re_2, -- sfix20 dout_11_im => dout_11_im_2, -- sfix20 dout_1_vld => dout_1_vld_1, softReset => softReset, dout_9_re_1 => dataOut_re_tmp(8), -- sfix21 dout_9_im_1 => dataOut_im_tmp(8), -- sfix21 dout_10_re => dataOut_re_tmp(9), -- sfix21 dout_10_im => dataOut_im_tmp(9), -- sfix21 dout_4_vld => dout_4_vld_4 ); u_SDNF2_4_11 : RADIX22FFT_SDNF2_4_block4 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_11 => rotate_11_1, -- ufix1 dout_10_re => dout_10_re_2, -- sfix20 dout_10_im => dout_10_im_2, -- sfix20 dout_12_re => dout_12_re_2, -- sfix20 dout_12_im => dout_12_im_2, -- sfix20 dout_1_vld => dout_1_vld_1, softReset => softReset, dout_11_re => dataOut_re_tmp(10), -- sfix21 dout_11_im => dataOut_im_tmp(10), -- sfix21 dout_12_re_1 => dataOut_re_tmp(11), -- sfix21 dout_12_im_1 => dataOut_im_tmp(11), -- sfix21 dout_4_vld => dout_4_vld_5 ); u_twdlROM_3_14 : TWDLROM_3_14 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_14_re => twdl_3_14_re, -- sfix17_En15 twdl_3_14_im => twdl_3_14_im, -- sfix17_En15 twdl_3_14_vld => twdl_3_14_vld ); u_TWDLMULT_SDNF1_3_13 : TWDLMULT_SDNF1_3_block5 PORT MAP( clk => clk, reset => reset, enb => enb, dout_10_re => dout_10_re_1, -- sfix19 dout_10_im => dout_10_im_1, -- sfix19 dout_12_re => dout_12_re_1, -- sfix19 dout_12_im => dout_12_im_1, -- sfix19 dout_2_vld => dout_2_vld, twdl_3_13_re => std_logic_vector(twdl_3_13_re), -- sfix17_En15 twdl_3_13_im => std_logic_vector(twdl_3_13_im), -- sfix17_En15 twdl_3_14_re => twdl_3_14_re, -- sfix17_En15 twdl_3_14_im => twdl_3_14_im, -- sfix17_En15 twdl_3_14_vld => twdl_3_14_vld, softReset => softReset, twdlXdin_13_re => twdlXdin_13_re_1, -- sfix20 twdlXdin_13_im => twdlXdin_13_im_1, -- sfix20 twdlXdin_14_re => twdlXdin_14_re_1, -- sfix20 twdlXdin_14_im => twdlXdin_14_im_1, -- sfix20 twdlXdin_13_vld => twdlXdin_13_vld ); u_twdlROM_3_15 : TWDLROM_3_15 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_15_re => twdl_3_15_re, -- sfix17_En15 twdl_3_15_im => twdl_3_15_im, -- sfix17_En15 twdl_3_15_vld => twdl_3_15_vld ); u_twdlROM_3_16 : TWDLROM_3_16 PORT MAP( clk => clk, reset => reset, enb => enb, dout_2_vld => dout_2_vld, softReset => softReset, twdl_3_16_re => twdl_3_16_re, -- sfix17_En15 twdl_3_16_im => twdl_3_16_im, -- sfix17_En15 twdl_3_16_vld => twdl_3_16_vld ); u_TWDLMULT_SDNF1_3_15 : TWDLMULT_SDNF1_3_block6 PORT MAP( clk => clk, reset => reset, enb => enb, dout_14_re => dout_14_re_1, -- sfix19 dout_14_im => dout_14_im_1, -- sfix19 dout_16_re => dout_16_re_1, -- sfix19 dout_16_im => dout_16_im_1, -- sfix19 dout_2_vld => dout_2_vld, twdl_3_15_re => twdl_3_15_re, -- sfix17_En15 twdl_3_15_im => twdl_3_15_im, -- sfix17_En15 twdl_3_16_re => twdl_3_16_re, -- sfix17_En15 twdl_3_16_im => twdl_3_16_im, -- sfix17_En15 twdl_3_16_vld => twdl_3_16_vld, softReset => softReset, twdlXdin_15_re => twdlXdin_15_re_1, -- sfix20 twdlXdin_15_im => twdlXdin_15_im_1, -- sfix20 twdlXdin_16_re => twdlXdin_16_re_1, -- sfix20 twdlXdin_16_im => twdlXdin_16_im_1, -- sfix20 twdlXdin_15_vld => twdlXdin_15_vld ); u_SDNF1_3_13 : RADIX22FFT_SDNF1_3_block5 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_13_re => twdlXdin_13_re_1, -- sfix20 twdlXdin_13_im => twdlXdin_13_im_1, -- sfix20 twdlXdin_15_re => twdlXdin_15_re_1, -- sfix20 twdlXdin_15_im => twdlXdin_15_im_1, -- sfix20 twdlXdin_1_vld => twdlXdin_1_vld_1, softReset => softReset, dout_13_re => dout_13_re_2, -- sfix20 dout_13_im => dout_13_im_2, -- sfix20 dout_14_re => dout_14_re_2, -- sfix20 dout_14_im => dout_14_im_2, -- sfix20 dout_13_vld => dout_13_vld_1 ); u_SDNF1_3_15 : RADIX22FFT_SDNF1_3_block6 PORT MAP( clk => clk, reset => reset, enb => enb, twdlXdin_14_re => twdlXdin_14_re_1, -- sfix20 twdlXdin_14_im => twdlXdin_14_im_1, -- sfix20 twdlXdin_16_re => twdlXdin_16_re_1, -- sfix20 twdlXdin_16_im => twdlXdin_16_im_1, -- sfix20 twdlXdin_1_vld => twdlXdin_1_vld_1, softReset => softReset, dout_15_re => dout_15_re_2, -- sfix20 dout_15_im => dout_15_im_2, -- sfix20 dout_16_re => dout_16_re_2, -- sfix20 dout_16_im => dout_16_im_2, -- sfix20 dout_15_vld => dout_15_vld_1 ); u_SDNF2_4_13 : RADIX22FFT_SDNF2_4_block5 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_13 => rotate_13_1, -- ufix1 dout_13_re => dout_13_re_2, -- sfix20 dout_13_im => dout_13_im_2, -- sfix20 dout_15_re => dout_15_re_2, -- sfix20 dout_15_im => dout_15_im_2, -- sfix20 dout_1_vld => dout_1_vld_1, softReset => softReset, dout_13_re_1 => dataOut_re_tmp(12), -- sfix21 dout_13_im_1 => dataOut_im_tmp(12), -- sfix21 dout_14_re => dataOut_re_tmp(13), -- sfix21 dout_14_im => dataOut_im_tmp(13), -- sfix21 dout_4_vld => dout_4_vld_6 ); u_SDNF2_4_15 : RADIX22FFT_SDNF2_4_block6 PORT MAP( clk => clk, reset => reset, enb => enb, rotate_15 => rotate_15_1, -- ufix1 dout_14_re => dout_14_re_2, -- sfix20 dout_14_im => dout_14_im_2, -- sfix20 dout_16_re => dout_16_re_2, -- sfix20 dout_16_im => dout_16_im_2, -- sfix20 dout_1_vld => dout_1_vld_1, softReset => softReset, dout_15_re => dataOut_re_tmp(14), -- sfix21 dout_15_im => dataOut_im_tmp(14), -- sfix21 dout_16_re_1 => dataOut_re_tmp(15), -- sfix21 dout_16_im_1 => dataOut_im_tmp(15), -- sfix21 dout_4_vld => dout_4_vld_7 ); rotate_1 <= '0'; rotate_1_1 <= '0'; dataIn_0 <= unsigned(dataIn(0)); dataIn_1_cast_re <= signed(resize(dataIn_0, 17)); dataIn_1_cast_im <= to_signed(16#00000#, 17); dataIn_8 <= unsigned(dataIn(8)); dataIn_9_cast_re <= signed(resize(dataIn_8, 17)); dataIn_9_cast_im <= to_signed(16#00000#, 17); twdlXdin_1_re <= resize(dataIn_1_cast_re, 18); twdlXdin_1_im <= resize(dataIn_1_cast_im, 18); twdlXdin_9_re <= resize(dataIn_9_cast_re, 18); twdlXdin_9_im <= resize(dataIn_9_cast_im, 18); twdlXdin_1_vld <= '1' WHEN validIn /= '0' ELSE '0'; softReset <= '0'; dataIn_4 <= unsigned(dataIn(4)); dataIn_5_cast_re <= signed(resize(dataIn_4, 17)); dataIn_5_cast_im <= to_signed(16#00000#, 17); dataIn_12 <= unsigned(dataIn(12)); dataIn_13_cast_re <= signed(resize(dataIn_12, 17)); dataIn_13_cast_im <= to_signed(16#00000#, 17); twdlXdin_5_re <= resize(dataIn_5_cast_re, 18); twdlXdin_5_im <= resize(dataIn_5_cast_im, 18); twdlXdin_13_re <= resize(dataIn_13_cast_re, 18); twdlXdin_13_im <= resize(dataIn_13_cast_im, 18); rotate_3 <= '0'; dataIn_1 <= unsigned(dataIn(1)); dataIn_2_cast_re <= signed(resize(dataIn_1, 17)); dataIn_2_cast_im <= to_signed(16#00000#, 17); dataIn_9 <= unsigned(dataIn(9)); dataIn_10_cast_re <= signed(resize(dataIn_9, 17)); dataIn_10_cast_im <= to_signed(16#00000#, 17); twdlXdin_2_re <= resize(dataIn_2_cast_re, 18); twdlXdin_2_im <= resize(dataIn_2_cast_im, 18); twdlXdin_10_re <= resize(dataIn_10_cast_re, 18); twdlXdin_10_im <= resize(dataIn_10_cast_im, 18); dataIn_5 <= unsigned(dataIn(5)); dataIn_6_cast_re <= signed(resize(dataIn_5, 17)); dataIn_6_cast_im <= to_signed(16#00000#, 17); dataIn_13 <= unsigned(dataIn(13)); dataIn_14_cast_re <= signed(resize(dataIn_13, 17)); dataIn_14_cast_im <= to_signed(16#00000#, 17); twdlXdin_6_re <= resize(dataIn_6_cast_re, 18); twdlXdin_6_im <= resize(dataIn_6_cast_im, 18); twdlXdin_14_re <= resize(dataIn_14_cast_re, 18); twdlXdin_14_im <= resize(dataIn_14_cast_im, 18); twdl_3_1_re <= to_signed(16#08000#, 17); twdl_3_1_im <= to_signed(16#00000#, 17); rotate_5 <= '0'; dataIn_2 <= unsigned(dataIn(2)); dataIn_3_cast_re <= signed(resize(dataIn_2, 17)); dataIn_3_cast_im <= to_signed(16#00000#, 17); dataIn_10 <= unsigned(dataIn(10)); dataIn_11_cast_re <= signed(resize(dataIn_10, 17)); dataIn_11_cast_im <= to_signed(16#00000#, 17); twdlXdin_3_re <= resize(dataIn_3_cast_re, 18); twdlXdin_3_im <= resize(dataIn_3_cast_im, 18); twdlXdin_11_re <= resize(dataIn_11_cast_re, 18); twdlXdin_11_im <= resize(dataIn_11_cast_im, 18); dataIn_6 <= unsigned(dataIn(6)); dataIn_7_cast_re <= signed(resize(dataIn_6, 17)); dataIn_7_cast_im <= to_signed(16#00000#, 17); dataIn_14 <= unsigned(dataIn(14)); dataIn_15_cast_re <= signed(resize(dataIn_14, 17)); dataIn_15_cast_im <= to_signed(16#00000#, 17); twdlXdin_7_re <= resize(dataIn_7_cast_re, 18); twdlXdin_7_im <= resize(dataIn_7_cast_im, 18); twdlXdin_15_re <= resize(dataIn_15_cast_re, 18); twdlXdin_15_im <= resize(dataIn_15_cast_im, 18); rotate_7 <= '0'; dataIn_3 <= unsigned(dataIn(3)); dataIn_4_cast_re <= signed(resize(dataIn_3, 17)); dataIn_4_cast_im <= to_signed(16#00000#, 17); dataIn_11 <= unsigned(dataIn(11)); dataIn_12_cast_re <= signed(resize(dataIn_11, 17)); dataIn_12_cast_im <= to_signed(16#00000#, 17); twdlXdin_4_re <= resize(dataIn_4_cast_re, 18); twdlXdin_4_im <= resize(dataIn_4_cast_im, 18); twdlXdin_12_re <= resize(dataIn_12_cast_re, 18); twdlXdin_12_im <= resize(dataIn_12_cast_im, 18); dataIn_7 <= unsigned(dataIn(7)); dataIn_8_cast_re <= signed(resize(dataIn_7, 17)); dataIn_8_cast_im <= to_signed(16#00000#, 17); dataIn_15 <= unsigned(dataIn(15)); dataIn_16_cast_re <= signed(resize(dataIn_15, 17)); dataIn_16_cast_im <= to_signed(16#00000#, 17); twdlXdin_8_re <= resize(dataIn_8_cast_re, 18); twdlXdin_8_im <= resize(dataIn_8_cast_im, 18); twdlXdin_16_re <= resize(dataIn_16_cast_re, 18); twdlXdin_16_im <= resize(dataIn_16_cast_im, 18); rotate_3_1 <= '1'; rotate_5_1 <= '0'; twdl_3_5_re <= to_signed(16#08000#, 17); twdl_3_5_im <= to_signed(16#00000#, 17); rotate_7_1 <= '1'; rotate_9 <= '0'; rotate_9_1 <= '1'; rotate_11 <= '1'; twdl_3_9_re <= to_signed(16#08000#, 17); twdl_3_9_im <= to_signed(16#00000#, 17); rotate_13 <= '1'; rotate_15 <= '1'; rotate_11_1 <= '1'; rotate_13_1 <= '0'; twdl_3_13_re <= to_signed(16#08000#, 17); twdl_3_13_im <= to_signed(16#00000#, 17); rotate_15_1 <= '1'; dataOut_re <= dataOut_re_tmp; dataOut_im <= dataOut_im_tmp; validOut <= dout_4_vld; END rtl;

-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Synthesizable Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: DEBUG_RAM_synth.vhd -- -- Description: -- Synthesizable Testbench -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.NUMERIC_STD.ALL; USE IEEE.STD_LOGIC_MISC.ALL; LIBRARY STD; USE STD.TEXTIO.ALL; --LIBRARY unisim; --USE unisim.vcomponents.ALL; LIBRARY work; USE work.ALL; USE work.BMG_TB_PKG.ALL; ENTITY DEBUG_RAM_synth IS PORT( CLK_IN : IN STD_LOGIC; CLKB_IN : IN STD_LOGIC; RESET_IN : IN STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA ); END ENTITY; ARCHITECTURE DEBUG_RAM_synth_ARCH OF DEBUG_RAM_synth IS COMPONENT DEBUG_RAM_exdes PORT ( --Inputs - Port A WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); CLKA : IN STD_LOGIC; --Inputs - Port B ADDRB : IN STD_LOGIC_VECTOR(6 DOWNTO 0); DOUTB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CLKB : IN STD_LOGIC ); END COMPONENT; SIGNAL CLKA: STD_LOGIC := '0'; SIGNAL RSTA: STD_LOGIC := '0'; SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL CLKB: STD_LOGIC := '0'; SIGNAL RSTB: STD_LOGIC := '0'; SIGNAL ADDRB: STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRB_R: STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0'); SIGNAL DOUTB: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL CHECKER_EN : STD_LOGIC:='0'; SIGNAL CHECKER_EN_R : STD_LOGIC:='0'; SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); SIGNAL clk_in_i: STD_LOGIC; SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1'; SIGNAL clkb_in_i: STD_LOGIC; SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1'; SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1'; SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1'; SIGNAL ITER_R0 : STD_LOGIC := '0'; SIGNAL ITER_R1 : STD_LOGIC := '0'; SIGNAL ITER_R2 : STD_LOGIC := '0'; SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); BEGIN -- clk_buf: bufg -- PORT map( -- i => CLK_IN, -- o => clk_in_i -- ); clk_in_i <= CLK_IN; CLKA <= clk_in_i; -- clkb_buf: bufg -- PORT map( -- i => CLKB_IN, -- o => clkb_in_i -- ); clkb_in_i <= CLKB_IN; CLKB <= clkb_in_i; RSTA <= RESET_SYNC_R3 AFTER 50 ns; PROCESS(clk_in_i) BEGIN IF(RISING_EDGE(clk_in_i)) THEN RESET_SYNC_R1 <= RESET_IN; RESET_SYNC_R2 <= RESET_SYNC_R1; RESET_SYNC_R3 <= RESET_SYNC_R2; END IF; END PROCESS; RSTB <= RESETB_SYNC_R3 AFTER 50 ns; PROCESS(clkb_in_i) BEGIN IF(RISING_EDGE(clkb_in_i)) THEN RESETB_SYNC_R1 <= RESET_IN; RESETB_SYNC_R2 <= RESETB_SYNC_R1; RESETB_SYNC_R3 <= RESETB_SYNC_R2; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ISSUE_FLAG_STATUS<= (OTHERS => '0'); ELSE ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; END IF; END IF; END PROCESS; STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; BMG_DATA_CHECKER_INST: ENTITY work.CHECKER GENERIC MAP ( WRITE_WIDTH => 32, READ_WIDTH => 4 ) PORT MAP ( CLK => clkb_in_i, RST => RSTB, EN => CHECKER_EN_R, DATA_IN => DOUTB, STATUS => ISSUE_FLAG(0) ); PROCESS(clkb_in_i) BEGIN IF(RISING_EDGE(clkb_in_i)) THEN IF(RSTB='1') THEN CHECKER_EN_R <= '0'; ELSE CHECKER_EN_R <= CHECKER_EN AFTER 50 ns; END IF; END IF; END PROCESS; BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN PORT MAP( CLKA => clk_in_i, CLKB => clkb_in_i, TB_RST => RSTA, ADDRA => ADDRA, DINA => DINA, WEA => WEA, ADDRB => ADDRB, CHECK_DATA => CHECKER_EN ); PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STATUS(8) <= '0'; iter_r2 <= '0'; iter_r1 <= '0'; iter_r0 <= '0'; ELSE STATUS(8) <= iter_r2; iter_r2 <= iter_r1; iter_r1 <= iter_r0; iter_r0 <= STIMULUS_FLOW(8); END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STIMULUS_FLOW <= (OTHERS => '0'); ELSIF(WEA(0)='1') THEN STIMULUS_FLOW <= STIMULUS_FLOW+1; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN WEA_R <= (OTHERS=>'0') AFTER 50 ns; DINA_R <= (OTHERS=>'0') AFTER 50 ns; ELSE WEA_R <= WEA AFTER 50 ns; DINA_R <= DINA AFTER 50 ns; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ADDRA_R <= (OTHERS=> '0') AFTER 50 ns; ADDRB_R <= (OTHERS=> '0') AFTER 50 ns; ELSE ADDRA_R <= ADDRA AFTER 50 ns; ADDRB_R <= ADDRB AFTER 50 ns; END IF; END IF; END PROCESS; BMG_PORT: DEBUG_RAM_exdes PORT MAP ( --Port A WEA => WEA_R, ADDRA => ADDRA_R, DINA => DINA_R, CLKA => CLKA, --Port B ADDRB => ADDRB_R, DOUTB => DOUTB, CLKB => CLKB ); END ARCHITECTURE;

LIBRARY ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.VITAL_Primitives.all; entity servo_pwm_tb is end servo_pwm_tb; architecture behavior of servo_pwm_tb is component servo_pwm port( clk : in std_logic; reset_n : in std_logic; coe_servo : out std_logic; avs_s0_write_n : in std_logic; avs_s0_writedata : in std_logic_vector (15 downto 0) ); end component; signal clk : std_logic:= '1'; signal reset_n : std_logic; signal coe_servo : std_logic; signal avs_s0_write_n: std_logic; signal avs_s0_writedata: std_logic_vector (15 downto 0); constant clk_period : time := 10 ns; begin uut: servo_pwm port map ( clk => clk, reset_n => reset_n, coe_servo => coe_servo, avs_s0_write_n => avs_s0_write_n, avs_s0_writedata => avs_s0_writedata ); clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; stimuli: process begin reset_n <= '1'; wait for 6 ms; reset_n <= '0'; avs_s0_write_n <= '0'; wait for 6 ms; reset_n <= '1'; avs_s0_writedata <= "0000000010101010"; avs_s0_write_n <= '0'; wait for 1 ms; avs_s0_write_n <= '1'; wait for 6 ms; avs_s0_writedata <= "0000000000000000"; avs_s0_write_n <= '0'; wait for 1 ms; avs_s0_write_n <= '1'; wait for 6 ms; avs_s0_writedata <= "0000000010000010"; avs_s0_write_n <= '0'; wait for 1 ms; avs_s0_write_n <= '1'; wait for 6 ms; avs_s0_writedata <= "0000000000000000"; avs_s0_write_n <= '0'; wait for 1 ms; avs_s0_write_n <= '1'; wait for 6 ms; avs_s0_writedata <= "0000000010101010"; avs_s0_write_n <= '0'; wait for 1 ms; avs_s0_write_n <= '1'; wait; end process; end;

library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; entity tdp_ram is generic ( ADDRWIDTH : positive := 7; WIDTH : positive := 8 ); port ( clk_a : in std_logic; read_a : in std_logic; write_a : in std_logic; addr_a : in std_logic_vector(ADDRWIDTH - 1 downto 0); data_read_a : out std_logic_vector(WIDTH - 1 downto 0); data_write_a : in std_logic_vector(WIDTH - 1 downto 0); clk_b : in std_logic; read_b : in std_logic; write_b : in std_logic; addr_b : in std_logic_vector(ADDRWIDTH - 1 downto 0); data_read_b : out std_logic_vector(WIDTH - 1 downto 0); data_write_b : in std_logic_vector(WIDTH - 1 downto 0) ); end tdp_ram; architecture behavioral of tdp_ram is begin process(clk_a, clk_b) type ram_t is array(0 to 2**ADDRWIDTH - 1) of std_logic_vector(WIDTH - 1 downto 0); variable store : ram_t := (others => (others => '0')); begin if rising_edge(clk_a) then if read_a = '1' then data_read_a <= store(to_integer(unsigned(addr_a))); end if; if write_a = '1' then store(to_integer(unsigned(addr_a))) := data_write_a; end if; end if; if rising_edge(clk_b) then if read_b = '1' then data_read_b <= store(to_integer(unsigned(addr_b))); end if; if write_b = '1' then store(to_integer(unsigned(addr_b))) := data_write_b; end if; end if; end process; end behavioral;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Sparcv8Monocycle is end Sparcv8Monocycle; architecture Behavioral of Sparcv8Monocycle is begin end Behavioral;

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity CounterLoadUpDown4 is port( clk : in std_logic; updown: in std_logic; reset : in std_logic; enable: in std_logic; load : in std_logic; dataIn: in std_logic_vector(3 downto 0); count : out std_logic_vector(3 downto 0)); end CounterLoadUpDown4; architecture Behavioral of CounterLoadUpDown4 is signal s_count : unsigned (3 downto 0); begin process(clk, enable) begin if (enable = '1') then s_count <= (others => '0'); elsif(rising_edge(clk)) then if(reset='1') then s_count <= (others => '0'); elsif(load='1') then s_count <= unsigned(dataIn); elsif (updown = '1') then s_count <= s_count + 1; else s_count <= s_count - 1; end if; end if; end process; count <= std_logic_vector(s_count); end Behavioral;

-------------------------------------------------------------------------------- -- Copyright (c) 1995-2007 Xilinx, Inc. -- All Right Reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 9.2i -- \ \ Application : ISE -- / / Filename : asdf_selfcheck.vhw -- /___/ /\ Timestamp : Thu May 02 19:20:37 2013 -- \ \ / \ -- \___\/\___\ -- --Command: --Design Name: asdf_selfcheck_beh --Device: Xilinx -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_TEXTIO.ALL; USE STD.TEXTIO.ALL; ENTITY asdf_selfcheck_beh IS END asdf_selfcheck_beh; ARCHITECTURE testbench_arch OF asdf_selfcheck_beh IS COMPONENT T_flipflop PORT ( clk : In std_logic; T : In std_logic; Q : InOut std_logic; Qn : InOut std_logic ); END COMPONENT; SIGNAL clk : std_logic := '0'; SIGNAL T : std_logic := '0'; SIGNAL Q : std_logic := 'Z'; SIGNAL Qn : std_logic := 'Z'; SHARED VARIABLE TX_ERROR : INTEGER := 0; SHARED VARIABLE TX_OUT : LINE; constant PERIOD : time := 200 ns; constant DUTY_CYCLE : real := 0.5; constant OFFSET : time := 100 ns; BEGIN UUT : T_flipflop PORT MAP ( clk => clk, T => T, Q => Q, Qn => Qn ); PROCESS -- clock process for clk BEGIN WAIT for OFFSET; CLOCK_LOOP : LOOP clk <= '0'; WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE)); clk <= '1'; WAIT FOR (PERIOD * DUTY_CYCLE); END LOOP CLOCK_LOOP; END PROCESS; PROCESS BEGIN -- ------------- Current Time: 185ns WAIT FOR 185 ns; T <= '1'; -- ------------------------------------- WAIT FOR 1015 ns; IF (TX_ERROR = 0) THEN STD.TEXTIO.write(TX_OUT, string'("No errors or warnings")); ASSERT (FALSE) REPORT "Simulation successful (not a failure). No problems detected." SEVERITY FAILURE; ELSE STD.TEXTIO.write(TX_OUT, TX_ERROR); STD.TEXTIO.write(TX_OUT, string'(" errors found in simulation")); ASSERT (FALSE) REPORT "Errors found during simulation" SEVERITY FAILURE; END IF; END PROCESS; END testbench_arch;

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --use IEEE.MATH_REAL.ALL; --------------------------------------------------------------------------------- -- -- U S E R F U N C T I O N : E X T R A C T O B S E R V A T I O N -- -- -- The user function calcualtes a observation for a particle -- A pointer to the input data is given. The user process can -- ask for data at a specific address. -- -- Thus, all needed data can be loaded into the entity. Thus, -- the observation can be calculated via input data. When no more -- data is needed, the observation is stored into the local ram. -- -- If the observation is stored in the ram, the finished signal has -- to be set to '1'. -- ------------------------------------------------------------------------------------ entity uf_extract_observation is generic ( C_BURST_AWIDTH : integer := 12; C_BURST_DWIDTH : integer := 32 ); port ( clk : in std_logic; reset : in std_logic; -- burst ram interface o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1); o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1); i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1); o_RAMWE : out std_logic; o_RAMClk : out std_logic; -- init signal init : in std_logic; -- enable signal enable : in std_logic; -- parameters loaded parameter_loaded : in std_logic; parameter_loaded_ack : out std_logic; -- new particle loaded new_particle : in std_logic; new_particle_ack : out std_logic; -- input data address input_data_address : in std_logic_vector(0 to 31); input_data_needed : out std_logic; -- get word data word_data_en : in std_logic; word_address : out std_logic_vector(0 to 31); word_data : in std_logic_vector(0 to 31); word_data_ack : out std_logic; -- if the observation is calculated, this signal has to be set to '1' finished : out std_logic ); end uf_extract_observation; architecture Behavioral of uf_extract_observation is component pipelined_divider port ( clk: in std_logic; ce: in std_logic; aclr: in std_logic; sclr: in std_logic; dividend: in std_logic_VECTOR(31 downto 0); divisor: in std_logic_VECTOR(31 downto 0); quot: out std_logic_VECTOR(31 downto 0); remd: out std_logic_VECTOR(31 downto 0); rfd: out std_logic); end component; type hsv_function is array ( 0 to 255) of integer; -- GRANULARITY constant GRAN_EXP : integer := 14; constant GRANULARITY : integer := 2**GRAN_EXP; constant hd_values : hsv_function := ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9); constant sdvd_values : hsv_function := ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9); -- states type t_state is (STATE_INIT, STATE_READ_PARAMETER, STATE_INIT_HISTOGRAM, STATE_READ_PARTICLE, STATE_ANALYZE_PARTICLE, STATE_CALCULATE_HISTOGRAM, STATE_GET_PIXEL,STATE_UPDATE_HISTOGRAM, STATE_CHECK_FINISHED, STATE_NORMALIZE_HISTOGRAM, STATE_COPY_HISTOGRAM, STATE_FINISH); signal state : t_state; ----------------------------------------------------- -- signals needed for divider component ----------------------------------------------------- -- clock enable signal ce : std_logic; -- synchronous clear signal sclr : std_logic := '0'; -- asynchronous clear signal aclr : std_logic := '0'; -- dividend signal dividend : std_logic_vector(31 downto 0) := (others => '0'); -- divisor signal divisor : std_logic_vector(31 downto 0) := "00000000000000000000000000000001"; -- quotient signal quotient : std_logic_vector(31 downto 0) := (others => '0'); -- remainder signal remainder : std_logic_vector(31 downto 0) := (others => '0'); -- ready for data signal rfd : std_logic; -- local ram address for interface signal local_ram_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0'); signal local_ram_start_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0'); -- HSV signals signal H : std_logic_vector(0 to 7) := (others => '0'); signal S : std_logic_vector(0 to 7) := (others => '0'); signal V : std_logic_vector(0 to 7) := (others => '0'); signal H_store : std_logic_vector(0 to 7) := (others => '0'); signal S_store : std_logic_vector(0 to 7) := (others => '0'); signal V_store : std_logic_vector(0 to 7) := (others => '0'); constant S_THRESH : integer := 25; constant V_THRESH : integer := 50; signal hd : natural range 0 to 9 := 0; signal sd : natural range 0 to 9 := 0; signal vd : natural range 0 to 9 := 0; signal value : natural := 0; -- copy histogram signal copy_histo_en : std_logic := '0'; -- handshake signal signal copy_histo_done : std_logic := '0'; -- handshake signal signal copy_histo_addr : std_logic_vector(C_BURST_AWIDTH-1 downto 0); -- burst ram addr signal copy_histo_bucket : std_logic_vector(6 downto 0); -- histogram addr signal copy_histo_data : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0'); -- update histogram signal update_histo_en : std_logic := '0'; -- handshake signal signal update_histo_done : std_logic := '0'; -- handshake signal signal update_histo_addr : std_logic_vector(C_BURST_AWIDTH-1 downto 0); -- burst ram addr signal update_histo_bucket : std_logic_vector(6 downto 0); -- histogram addr -- clear histogram signal clear_histo_en : std_logic := '0'; -- handshake signal signal clear_histo_done : std_logic := '0'; -- handshake signal signal clear_histo_bucket : std_logic_vector(6 downto 0) := (others => '0'); -- histogram addr -- normalize histogram signal normalize_histo_en : std_logic := '0'; -- handshake signal signal normalize_histo_done : std_logic := '0'; -- handshake signal signal normalize_histo : std_logic := '0'; -- set histo_ram value signal normalize_histo_value : std_logic_vector(31 downto 0) := (others=>'0'); -- new normalized histo value signal normalize_histo_bucket : std_logic_vector(6 downto 0) := (others => '0'); -- histogram addr -- read particle data signal read_particle_en : std_logic := '0'; -- handshake signal signal read_particle_done : std_logic := '0'; -- handshake signal signal read_particle_addr : std_logic_vector(C_BURST_AWIDTH-1 downto 0) := (others=>'0'); -- analyze particle signal analyze_particle_en : std_logic := '0'; -- handshake signal signal analyze_particle_done : std_logic := '0'; -- handshake signal -- read parameter signal read_parameter_en : std_logic := '0'; -- handshake signal signal read_parameter_done : std_logic := '0'; -- handshake signal signal read_parameter_addr : std_logic_vector(C_BURST_AWIDTH-1 downto 0) := (others=>'0'); -- calculate histogram signal calc_histo_en : std_logic := '0'; -- handshake signal signal calc_histo_done : std_logic := '0'; -- handshake signal -- get_pixel signal get_pixel_en : std_logic := '0'; -- handshake signal signal get_pixel_done : std_logic := '0'; -- handshake signal -- histogram type t_ram is array (109 downto 0) of std_logic_vector(31 downto 0); signal histo_ram : t_ram; -- histogram memory signal histo_bucket : std_logic_vector(6 downto 0); -- current histogram bucket signal histo_inc : std_logic := '0'; -- enables incrementing signal histo_clear : std_logic := '0'; -- enables setting to zero signal histo_value : std_logic_vector(31 downto 0); -- value of current bucket -- particle data signal x : integer := 0; signal y : integer := 0; signal scale : integer := 0; signal width : integer := 0; signal height : integer := 0; -- input data -- left upper corner signal x1 : integer := 0; signal y1 : integer := 0; -- right bottom corner signal x2 : integer := 0; signal y2 : integer := 2; -- current pixel signal px : integer := 0; signal py : integer := 0; -- current pixel signal size_x : integer := 480; signal size_y : integer := 360; -- temporary signals signal temp_x : integer := 0; signal temp_y : integer := 0; signal temp : integer := 0; -- input data offset signal input_data_offset : integer := 0; -- sum of histogram signal sum : integer := 0; -- signal for counter signal i : integer := 0; signal j : integer := 0; begin divider : pipelined_divider port map ( clk => clk, ce => ce, aclr => aclr, sclr => sclr, dividend => dividend, divisor => divisor, quot => quotient, remd => remainder, rfd => rfd); -- burst ram interface o_RAMClk <= clk; ce <= enable; -- histogram memory is basically a single port ram with -- asynchronous read. the current bucket is incremented each -- clock cycle when histo_inc is high, or set to zero when -- histo_clear is high. -- @author: Andreas Agne histo_value <= histo_ram(CONV_INTEGER(histo_bucket)); histo_ram_proc : process(clk) begin if rising_edge(clk) then -- TRY: CLOCKED VERSION --histo_value <= histo_ram(CONV_INTEGER(histo_bucket)); if histo_inc = '1' then histo_ram(TO_INTEGER(UNSIGNED(histo_bucket))) <= histo_ram(CONV_INTEGER(histo_bucket)) + 1; elsif histo_clear = '1' then histo_ram(TO_INTEGER(UNSIGNED(histo_bucket))) <= (others=>'0'); elsif normalize_histo = '1' then histo_ram(TO_INTEGER(UNSIGNED(histo_bucket))) <= normalize_histo_value; end if; end if; end process; -- signals and processes related to updating the histogram from -- burst-ram data update_histo_proc : process(clk, reset, update_histo_en) variable step : natural range 0 to 3; begin if reset = '1' or update_histo_en = '0' then step := 0; histo_inc <= '0'; update_histo_addr <= (others => '0'); update_histo_done <= '0'; update_histo_bucket <= (others => '0'); elsif rising_edge(clk) then case step is when 0 => -- calculate hd hd <= hd_values(TO_INTEGER(UNSIGNED(H_store))); sd <= sdvd_values(TO_INTEGER(UNSIGNED(S_store))); vd <= sdvd_values(TO_INTEGER(UNSIGNED(V_store))); step := step + 1; when 1 => -- calculate histogram position if( S_THRESH <= S and V_THRESH <= V) then value <= 10 * sd + hd; else value <= 100 + vd; end if; step := step + 1; when 2 => -- increment histogram value histo_inc <= '1'; update_histo_bucket <= STD_LOGIC_VECTOR(TO_UNSIGNED(value, 7)); step := step + 1; when 3 => -- turn off histogram incrementing, set handshake signal histo_inc <= '0'; update_histo_done <= '1'; -- when 0 => -- calculate hd -- hd <= hd_values(TO_INTEGER(UNSIGNED(H))); -- step := step + 1; -- -- when 1 => -- calculate sd -- sd <= sdvd_values(TO_INTEGER(UNSIGNED(S))); -- step := step + 1; -- -- when 2 => -- calculate vd -- vd <= sdvd_values(TO_INTEGER(UNSIGNED(V))); -- step := step + 1; -- -- when 3 => -- calculate histogram position (1 of 2) -- if( S_THRESH <= S and V_THRESH <= V) then -- value <= 10 * sd; -- else -- value <= 100 + vd; -- end if; -- step := step + 1; -- -- when 4 => -- calculate histogram position (2 of 2) -- if( S_THRESH <= S and V_THRESH <= V) then -- value <= value + hd; -- end if; -- step := step + 1; -- -- when 5 => -- increment histogram value -- histo_inc <= '1'; -- update_histo_bucket <= STD_LOGIC_VECTOR(TO_UNSIGNED(value, 7)); -- step := step + 1; -- -- when 6 => -- turn off histogram incrementing, set handshake signal -- histo_inc <= '0'; -- update_histo_done <= '1'; end case; end if; end process; -- signals and processes related to copying the histogram to -- burst-ram -- @author: Andreas Agne copy_histogram : process(clk, reset, copy_histo_en) variable step : natural range 0 to 7; begin if reset = '1' or copy_histo_en = '0' then copy_histo_addr <= (others => '0'); copy_histo_bucket <= (others => '0'); copy_histo_done <= '0'; o_RAMWE <= '0'; copy_histo_data <= (others => '0'); step := 0; elsif rising_edge(clk) then case step is when 0 => -- set histogram and burst ram addresses to 0 copy_histo_addr <= (others => '0'); copy_histo_bucket <= (others => '0'); step := step + 1; when 1 => -- copy first word copy_histo_addr <= (others => '0'); copy_histo_bucket <= copy_histo_bucket + 1; o_RAMWE <= '1'; copy_histo_data <= histo_value; step := step + 1; when 2 => -- copy remaining histogram buckets to burst ram copy_histo_addr <= copy_histo_addr + 1; copy_histo_bucket <= copy_histo_bucket + 1; o_RAMWE <= '1'; copy_histo_data <= histo_value; if (108 <= copy_histo_bucket) then step := step + 1; end if; when 3 => -- wait (1 of 2) o_RAMWE <= '1'; copy_histo_addr <= copy_histo_addr + 1; copy_histo_data <= histo_value; step := step + 1; when 4 => -- wait (2 of 2) o_RAMWE <= '1'; step := step + 1; when 5 => -- write n o_RAMWE <= '1'; copy_histo_addr <= copy_histo_addr + 1; copy_histo_data <= STD_LOGIC_VECTOR(TO_SIGNED(110, 32)); step := step + 1; when 6 => -- write dummy o_RAMWE <= '1'; copy_histo_addr <= copy_histo_addr + 1; copy_histo_data <= STD_LOGIC_VECTOR(TO_SIGNED(0, 32)); step := step + 1; when 7 => -- all buckets copied -> set handshake signal copy_histo_done <= '1'; copy_histo_bucket <= (others => '0'); o_RAMWE <= '0'; end case; end if; end process; -- signals and processes related to calculating the histogram calc_histo_proc : process(clk, reset, calc_histo_en) variable step : natural range 0 to 5; begin if reset = '1' or calc_histo_en = '0' then step := 0; H_store(0 to 7) <= (others => '0'); S_store(0 to 7) <= (others => '0'); V_store(0 to 7) <= (others => '0'); update_histo_en <= '0'; get_pixel_en <= '0'; calc_histo_done <= '0'; elsif rising_edge(clk) then case step is when 0 => -- get 1st pixel px <= x1; py <= y1; get_pixel_en <= '1'; update_histo_en <= '0'; step := step + 1; when 1 => -- first pixel stored if (get_pixel_done = '1') then H_store(0 to 7) <= H(0 to 7); S_store(0 to 7) <= S(0 to 7); V_store(0 to 7) <= V(0 to 7); get_pixel_en <= '0'; update_histo_en <= '0'; px <= px + 1; step := step + 1; end if; when 2 => -- start parallel execution or last update if (px > x2 and y2 <= py) then -- finished: last update step := step + 2; update_histo_en <= '1'; get_pixel_en <= '0'; elsif (px > x2 and py < y2) then -- next row px <= x1; py <= py + 1; -- read next pixel and update histogram for last one get_pixel_en <= '1'; update_histo_en <= '1'; step := step + 1; else -- default: read next pixel and update histogram for last one get_pixel_en <= '1'; update_histo_en <= '1'; step := step + 1; end if; when 3 => -- parallel execution finished if (update_histo_done = '1' and get_pixel_done = '1' ) then get_pixel_en <= '0'; update_histo_en <= '0'; H_store(0 to 7) <= H(0 to 7); S_store(0 to 7) <= S(0 to 7); V_store(0 to 7) <= V(0 to 7); px <= px + 1; step := step - 1; end if; when 4 => -- last histogram update if (update_histo_done = '1') then update_histo_en <= '0'; get_pixel_en <= '0'; step := step + 1; end if; when 5 => -- set handshake signal update_histo_en <= '0'; get_pixel_en <= '0'; calc_histo_done <= '1'; end case; end if; end process; -- signals and processes related to clearing the histogram -- @author: Andreas Agne clear_histogram_proc : process(clk, reset, clear_histo_en) variable step : natural range 0 to 3; begin if reset = '1' or clear_histo_en = '0' then step := 0; histo_clear <= '0'; clear_histo_bucket <= (others => '0'); clear_histo_done <= '0'; elsif rising_edge(clk) then case step is when 0 => -- enable bucket zeroing clear_histo_bucket <= (others => '0'); histo_clear <= '1'; step := step + 1; when 1 => -- visit every bucket clear_histo_bucket <= clear_histo_bucket + 1; if 108 <= clear_histo_bucket then step := step + 1; end if; when 2 => step := step + 1; when 3 => -- set handshake signal histo_clear <= '0'; clear_histo_bucket <= (others => '0'); clear_histo_done <= '1'; end case; end if; end process; -- reads parameter read_parameter_proc: process (clk, reset, read_parameter_en) variable step : natural range 0 to 4; begin if reset = '1' or read_parameter_en = '0' then step := 0; read_parameter_done <= '0'; parameter_loaded_ack <= '0'; elsif rising_edge(clk) then case step is when 0 => --! read parameter values read_parameter_addr <= local_ram_start_address_if; parameter_loaded_ack <= '0'; step := step + 1; when 1 => --! wait one cycle read_parameter_addr <= local_ram_start_address_if + 1; step := step + 1; when 2 => --! read size_x size_x <= TO_INTEGER(SIGNED(i_RAMData)); step := step + 1; when 3 => --! read size_y size_y <= TO_INTEGER(SIGNED(i_RAMData)); parameter_loaded_ack <= '1'; step := step + 1; when 4 => if (parameter_loaded = '0') then read_parameter_done <= '1'; parameter_loaded_ack <= '0'; end if; end case; end if; end process; -- signals and processes related to normalizing the histograme normalize_histogram_proc : process(clk, reset, normalize_histo_en, ce) variable step : natural range 0 to 7; begin if reset = '1' or normalize_histo_en = '0' then step := 0; normalize_histo_bucket <= (others => '0'); normalize_histo_done <= '0'; divisor <= "00000000000000000000000000000001"; elsif ce = '0' then elsif rising_edge(clk) then case step is when 0 => -- init sum calculation i <= 0; sum <= 0; step := step + 1; when 1 => -- calculate sum sum <= sum + CONV_INTEGER(histo_ram(i)); if (i < 109) then i <= i + 1; else step := step + 1; end if; -- init when 2 => normalize_histo_bucket <= (others => '0'); normalize_histo <= '0'; i <= 0; step := step + 1; -- modify histo_values (histo_value * GRANULARITY) and sum up histogram -- first histo_value when 3 => normalize_histo <= '1'; -- modify value: value * GRANULARITY normalize_histo_value <= histo_ram(i)(17 downto 0) & "00000000000000"; i <= 1; step := step + 1; -- other histo_values when 4 => normalize_histo <= '1'; -- modify value: value * GRANULARITY normalize_histo_value <= histo_ram(i)(17 downto 0) & "00000000000000"; if (i < 109) then i <= i + 1; end if; if (normalize_histo_bucket < 109) then normalize_histo_bucket <= normalize_histo_bucket + 1; else step := step + 1; end if; when 5 => -- start division normalize_histo <= '0'; normalize_histo_bucket <= (others => '0'); divisor <= STD_LOGIC_VECTOR(TO_SIGNED(sum, 32)); i <= 0; step := step + 1; when 6 => -- put all 110 histogram values into pipelined divider. -- pipelined divider has a latency of 36 clock cycles -- 36 = 32 (width of dividend) + 4 (see: coregen datasheed) -- one clock cycle per division if (i<110) then -- put histogram values to pipeline dividend <= histo_ram(i); i <= i + 1; end if; if (i > 36) then -- collect division results normalize_histo <= '1'; normalize_histo_value <= quotient; if (normalize_histo_bucket < 109 and i > 37) then normalize_histo_bucket <= normalize_histo_bucket + 1; elsif (109 <= normalize_histo_bucket) then step := step + 1; end if; end if; when 7 => -- set handshake signal; normalize_histo <= '0'; normalize_histo_bucket <= (others => '0'); normalize_histo_done <= '1'; end case; end if; end process; -- reads particle data needed for histogram calculation read_particle_proc: process (clk, reset, read_particle_en, ce) variable step : natural range 0 to 8; begin if reset = '1' or read_particle_en = '0' then step := 0; read_particle_done <= '0'; --local_ram_address_if <= local_ram_start_address_if; elsif ce = '0' then elsif rising_edge(clk) and ce = '1' then case step is when 0 => --! increment local ram address to get x value local_ram_address_if <= local_ram_start_address_if + 1; step := step + 1; when 1 => --! read particle values read_particle_addr <= local_ram_address_if; local_ram_address_if <= local_ram_address_if + 1; step := step + 1; when 2 => --! wait one cycle local_ram_address_if <= local_ram_address_if + 1; read_particle_addr <= local_ram_address_if; step := step + 1; when 3 => --! read x x <= TO_INTEGER(SIGNED(i_RAMData)); local_ram_address_if <= local_ram_address_if + 6; read_particle_addr <= local_ram_address_if; step := step + 1; when 4 => --! read y y <= TO_INTEGER(SIGNED(i_RAMData)); local_ram_address_if <= local_ram_address_if + 1; read_particle_addr <= local_ram_address_if; step := step + 1; when 5 => --! read scale scale <= TO_INTEGER(SIGNED(i_RAMData)); read_particle_addr <= local_ram_address_if; step := step + 1; when 6 => --! read width width <= TO_INTEGER(SIGNED(i_RAMData)); step := step + 1; when 7 => --! read height height <= TO_INTEGER(SIGNED(i_RAMData)); step := step + 1; when 8 => read_particle_done <= '1'; end case; end if; end process; -- analyzes particle data needed for histogram calculation analyze_particle_proc: process (clk, reset, analyze_particle_en, ce) variable step : natural range 0 to 17; begin if reset = '1' or analyze_particle_en = '0' then step := 0; analyze_particle_done <= '0'; elsif ce = '0' then elsif rising_edge(clk) and ce = '1' then case step is when 0 => --! calculate upper left corner (x1, y1) and lower bottom corner (x2, y2) of frame piece temp_x <= width - 1; temp_y <= height - 1; step := step + 1; when 1 => --! calculate (x1, y1) and (x2, y2) temp_x <= temp_x / 2; step := step + 1; when 2 => --! calculate (x1, y1) and (x2, y2) temp_y <= temp_y / 2; step := step + 1; when 3 => --! calculate (x1, y1) and (x2, y2) temp_x <= temp_x * scale; step := step + 1; when 4 => --! wait step := step + 1; when 5 => --! wait step := step + 1; when 6 => --! calculate (x1, y1) and (x2, y2) temp_y <= temp_y * scale; step := step + 1; when 7 => --! wait step := step + 1; when 8 => --! wait step := step + 1; when 9 => --! calculate (x1, y1) and (x2, y2) x1 <= x - temp_x; step := step + 1; when 10 => --! calculate (x1, y1) and (x2, y2) x2 <= x + temp_x; step := step + 1; when 11 => --! calculate (x1, y1) and (x2, y2) y1 <= y - temp_y; step := step + 1; when 12 => --! calculate (x1, y1) and (x2, y2) y2 <= y + temp_y; step := step + 1; when 13 => --! calculate (x1, y1) and (x2, y2) x1 <= x1 / GRANULARITY; step := step + 1; when 14 => --! calculate (x1, y1) and (x2, y2) y1 <= y1 / GRANULARITY; if (x1 < 0) then x1 <= 0; end if; step := step + 1; when 15 => --! calculate (x1, y1) and (x2, y2) x2 <= x2 / GRANULARITY; if (y1 < 0) then y1 <= 0; end if; step := step + 1; when 16 => --! calculate (x1, y1) and (x2, y2) if (x2 > size_x - 1) then x2 <= size_x - 1; end if; y2 <= y2 / GRANULARITY; step := step + 1; when 17 => --! finished if (y2 > size_y - 1) then y2 <= size_y - 1; end if; analyze_particle_done <= '1'; end case; end if; end process; -- get next pixel needed for histogram calculation get_pixel_proc: process (clk, reset, get_pixel_en, ce) variable step : natural range 0 to 5; begin if reset = '1' or get_pixel_en = '0' then step := 0; get_pixel_done <= '0'; --word_address <= (others=>'0'); word_data_ack <= '0'; elsif ce = '0' then elsif rising_edge(clk) then case step is when 0 => --! calculate offset for input data (1 of 3) input_data_offset <= 1024 * py; --input_data_offset <= 512 * py; step := step + 1; when 1 => --! calculate offset for input data (2 of 3) input_data_offset <= input_data_offset + px; step := step + 1; when 2 => --! calculate offset for input data (3 of 3) input_data_offset <= input_data_offset * 4; step := step + 1; when 3 => --! read pixel data using entitiy ports input_data_needed <= '1'; word_address <= input_data_address + input_data_offset; step := step + 1; when 4 => --! receive pixel data if word_data_en = '1' then input_data_needed <= '0'; word_data_ack <= '1'; step := step + 1; end if; when 5 => --! split pixel data to H,S,V signals H(0 to 7) <= word_data( 24 to 31); S(0 to 7) <= word_data( 16 to 23); V(0 to 7) <= word_data( 8 to 15); get_pixel_done <= '1'; end case; end if; end process; -- histogram ram mux -- @author: Andreas Agne -- updated mux_proc: process(update_histo_en, copy_histo_en, clear_histo_en, normalize_histo_en, read_particle_en, read_particle_addr, normalize_histo_bucket, update_histo_addr, update_histo_bucket, copy_histo_addr, copy_histo_bucket, clear_histo_bucket, read_parameter_en, read_parameter_addr, copy_histo_data) variable addr : std_logic_vector(C_BURST_AWIDTH - 1 downto 0); variable data : std_logic_vector(0 to C_BURST_DWIDTH-1); variable bucket : std_logic_vector(6 downto 0); begin if update_histo_en = '1' then addr := update_histo_addr; bucket := update_histo_bucket; data := (others => '0'); elsif copy_histo_en = '1' then addr := copy_histo_addr; bucket := copy_histo_bucket; data := copy_histo_data; elsif clear_histo_en = '1' then addr := (others => '0'); bucket := clear_histo_bucket; data := (others => '0'); elsif normalize_histo_en = '1' then addr := (others => '0'); bucket := normalize_histo_bucket; data := (others => '0'); elsif read_particle_en = '1' then addr := read_particle_addr; bucket := (others => '0'); data := (others => '0'); elsif read_parameter_en = '1' then addr := read_parameter_addr; bucket := (others => '0'); data := (others => '0'); else addr := (others => '0'); bucket := (others => '0'); data := (others => '0'); end if; o_RAMData <= data; o_RAMAddr <= addr(C_BURST_AWIDTH - 1 downto 0); histo_bucket <= bucket; end process; ---------------------------------------------------------------------------------- -- -- 1) initialize histogram, finished = '0' (if new_particle = '1') -- -- 2) read particle data -- -- 3) extract needed information -- -- 4) calculate input address, read pixel data (using entity ports) -- -- 5) update histogram -- -- 6) more pixel to load -- go to step 4 -- else -- go to step 7 -- -- 7) normalize histogram -- -- 8) write histogram into local ram -- -- 9) finshed = '1', wait for new_particle = '1' -- ---------------------------------------------------------------------------------- state_proc : process(clk, reset) begin if (reset = '1') then state <= STATE_INIT; new_particle_ack <= '0'; read_parameter_en <= '0'; finished <= '0'; elsif rising_edge(clk) then if init = '1' then state <= STATE_INIT; finished <= '0'; clear_histo_en <= '0'; elsif enable = '1' then case state is when STATE_INIT => --! init data finished <= '0'; calc_histo_en <= '0'; copy_histo_en <= '0'; read_particle_en <= '0'; analyze_particle_en <= '0'; if (new_particle = '1') then new_particle_ack <= '1'; clear_histo_en <= '1'; state <= STATE_INIT_HISTOGRAM; elsif (parameter_loaded = '1') then read_parameter_en <= '1'; state <= STATE_READ_PARAMETER; end if; when STATE_READ_PARAMETER => --! init histogram if (read_parameter_done = '1') then read_parameter_en <= '0'; state <= STATE_INIT; end if; ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ -- -- STEP 1: INIT HISTOGRAM -- ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ when STATE_INIT_HISTOGRAM => --! init histogram if (clear_histo_done = '1') then new_particle_ack <= '0'; clear_histo_en <= '0'; state <= STATE_READ_PARTICLE; read_particle_en <= '1'; end if; -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- ---- ---- STEP 2: READ PARTICLE ---- -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- when STATE_READ_PARTICLE => --! read particle values if (read_particle_done = '1') then analyze_particle_en <= '1'; read_particle_en <= '0'; state <= STATE_ANALYZE_PARTICLE; end if; ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ -- -- STEP 3: ANALYZE PARTICLE -- ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ when STATE_ANALYZE_PARTICLE => --! calculate upper left corner (x1, y1) and lower bottom corner (x2, y2) of frame piece if (analyze_particle_done = '1') then analyze_particle_en <= '0'; --get_pixel_en <= '1'; --px <= x1; --py <= y1; --state <= STATE_GET_PIXEL; calc_histo_en <= '1'; state <= STATE_CALCULATE_HISTOGRAM; end if; ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ -- -- STEP 4: GET PIXEL -- ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ when STATE_CALCULATE_HISTOGRAM => -- get next pixel for histogram calculation if (calc_histo_done = '1') then calc_histo_en <= '0'; normalize_histo_en <= '1'; state <= STATE_NORMALIZE_HISTOGRAM; end if; -- when STATE_GET_PIXEL => -- -- get next pixel for histogram calculation -- if (get_pixel_done = '1') then -- get_pixel_en <= '0'; -- update_histo_en <= '1'; -- state <= STATE_UPDATE_HISTOGRAM; -- end if; -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- ---- ---- STEP 5: HISTOGRAM UPDATE ---- -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- -- -- when STATE_UPDATE_HISTOGRAM => -- --! update histogram -- if update_histo_done = '1' then -- update_histo_en <= '0'; -- px <= px + 1; -- state <= STATE_CHECK_FINISHED; -- end if; ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ -- -- STEP 6: MORE PIXEL? -- ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ -- when STATE_CHECK_FINISHED => -- --! checks if more pixel have to be loaded -- if (px > x2 and y2 <= py) then -- -- finished -- normalize_histo_en <= '1'; -- state <= STATE_NORMALIZE_HISTOGRAM; -- -- CHANGE CHANGE CHANGE -- --copy_histo_en <= '1'; -- --state <= STATE_COPY_HISTOGRAM; -- -- END OF CHANGE CHANGE CHANGE -- elsif (px > x2 and py < y2) then -- -- next row -- px <= x1; -- py <= py + 1; -- state <= STATE_GET_PIXEL; -- get_pixel_en <= '1'; -- else -- -- default: next pixel -- state <= STATE_GET_PIXEL; -- get_pixel_en <= '1'; -- end if; -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- ---- ---- STEP 7: NORMALIZE HISTOGRAM ---- -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- when STATE_NORMALIZE_HISTOGRAM => --! normalize histogram if (normalize_histo_done = '1') then normalize_histo_en <= '0'; copy_histo_en <= '1'; state <= STATE_COPY_HISTOGRAM; end if; ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ -- -- STEP 8: WRITE HISTOGRAM TO LOCAL RAM -- ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ when STATE_COPY_HISTOGRAM => --! normalize histogram if (copy_histo_done = '1') then copy_histo_en <= '0'; state <= STATE_FINISH; end if; ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ -- -- STEP 9: HISTOGRAM CALCULATION FINISHED; WAIT FOR NEW_PARTICLE -- ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ when STATE_FINISH => --! write finished signal finished <= '1'; if (new_particle = '1') then state <= STATE_INIT; end if; when others => state <= STATE_INIT; end case; end if; end if; end process; end Behavioral;

-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:axi_vdma:6.2 -- IP Revision: 8 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY axi_vdma_v6_2_8; USE axi_vdma_v6_2_8.axi_vdma; ENTITY block_design_axi_vdma_0_0 IS PORT ( s_axi_lite_aclk : IN STD_LOGIC; m_axi_mm2s_aclk : IN STD_LOGIC; m_axis_mm2s_aclk : IN STD_LOGIC; axi_resetn : IN STD_LOGIC; s_axi_lite_awvalid : IN STD_LOGIC; s_axi_lite_awready : OUT STD_LOGIC; s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_lite_wvalid : IN STD_LOGIC; s_axi_lite_wready : OUT STD_LOGIC; s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_lite_bvalid : OUT STD_LOGIC; s_axi_lite_bready : IN STD_LOGIC; s_axi_lite_arvalid : IN STD_LOGIC; s_axi_lite_arready : OUT STD_LOGIC; s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_lite_rvalid : OUT STD_LOGIC; s_axi_lite_rready : IN STD_LOGIC; s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); mm2s_fsync : IN STD_LOGIC; mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0); mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_mm2s_arvalid : OUT STD_LOGIC; m_axi_mm2s_arready : IN STD_LOGIC; m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_mm2s_rlast : IN STD_LOGIC; m_axi_mm2s_rvalid : IN STD_LOGIC; m_axi_mm2s_rready : OUT STD_LOGIC; m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_mm2s_tvalid : OUT STD_LOGIC; m_axis_mm2s_tready : IN STD_LOGIC; m_axis_mm2s_tlast : OUT STD_LOGIC; mm2s_introut : OUT STD_LOGIC ); END block_design_axi_vdma_0_0; ARCHITECTURE block_design_axi_vdma_0_0_arch OF block_design_axi_vdma_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF block_design_axi_vdma_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT axi_vdma IS GENERIC ( C_S_AXI_LITE_ADDR_WIDTH : INTEGER; C_S_AXI_LITE_DATA_WIDTH : INTEGER; C_DLYTMR_RESOLUTION : INTEGER; C_PRMRY_IS_ACLK_ASYNC : INTEGER; C_ENABLE_VIDPRMTR_READS : INTEGER; C_DYNAMIC_RESOLUTION : INTEGER; C_NUM_FSTORES : INTEGER; C_USE_FSYNC : INTEGER; C_USE_MM2S_FSYNC : INTEGER; C_USE_S2MM_FSYNC : INTEGER; C_FLUSH_ON_FSYNC : INTEGER; C_INCLUDE_INTERNAL_GENLOCK : INTEGER; C_INCLUDE_SG : INTEGER; C_M_AXI_SG_ADDR_WIDTH : INTEGER; C_M_AXI_SG_DATA_WIDTH : INTEGER; C_INCLUDE_MM2S : INTEGER; C_MM2S_GENLOCK_MODE : INTEGER; C_MM2S_GENLOCK_NUM_MASTERS : INTEGER; C_MM2S_GENLOCK_REPEAT_EN : INTEGER; C_MM2S_SOF_ENABLE : INTEGER; C_INCLUDE_MM2S_DRE : INTEGER; C_INCLUDE_MM2S_SF : INTEGER; C_MM2S_LINEBUFFER_DEPTH : INTEGER; C_MM2S_LINEBUFFER_THRESH : INTEGER; C_MM2S_MAX_BURST_LENGTH : INTEGER; C_M_AXI_MM2S_ADDR_WIDTH : INTEGER; C_M_AXI_MM2S_DATA_WIDTH : INTEGER; C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER; C_M_AXIS_MM2S_TUSER_BITS : INTEGER; C_INCLUDE_S2MM : INTEGER; C_S2MM_GENLOCK_MODE : INTEGER; C_S2MM_GENLOCK_NUM_MASTERS : INTEGER; C_S2MM_GENLOCK_REPEAT_EN : INTEGER; C_S2MM_SOF_ENABLE : INTEGER; C_INCLUDE_S2MM_DRE : INTEGER; C_INCLUDE_S2MM_SF : INTEGER; C_S2MM_LINEBUFFER_DEPTH : INTEGER; C_S2MM_LINEBUFFER_THRESH : INTEGER; C_S2MM_MAX_BURST_LENGTH : INTEGER; C_M_AXI_S2MM_ADDR_WIDTH : INTEGER; C_M_AXI_S2MM_DATA_WIDTH : INTEGER; C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER; C_S_AXIS_S2MM_TUSER_BITS : INTEGER; C_ENABLE_DEBUG_ALL : INTEGER; C_ENABLE_DEBUG_INFO_0 : INTEGER; C_ENABLE_DEBUG_INFO_1 : INTEGER; C_ENABLE_DEBUG_INFO_2 : INTEGER; C_ENABLE_DEBUG_INFO_3 : INTEGER; C_ENABLE_DEBUG_INFO_4 : INTEGER; C_ENABLE_DEBUG_INFO_5 : INTEGER; C_ENABLE_DEBUG_INFO_6 : INTEGER; C_ENABLE_DEBUG_INFO_7 : INTEGER; C_ENABLE_DEBUG_INFO_8 : INTEGER; C_ENABLE_DEBUG_INFO_9 : INTEGER; C_ENABLE_DEBUG_INFO_10 : INTEGER; C_ENABLE_DEBUG_INFO_11 : INTEGER; C_ENABLE_DEBUG_INFO_12 : INTEGER; C_ENABLE_DEBUG_INFO_13 : INTEGER; C_ENABLE_DEBUG_INFO_14 : INTEGER; C_ENABLE_DEBUG_INFO_15 : INTEGER; C_INSTANCE : STRING; C_SELECT_XPM : INTEGER; C_FAMILY : STRING ); PORT ( s_axi_lite_aclk : IN STD_LOGIC; m_axi_sg_aclk : IN STD_LOGIC; m_axi_mm2s_aclk : IN STD_LOGIC; m_axis_mm2s_aclk : IN STD_LOGIC; m_axi_s2mm_aclk : IN STD_LOGIC; s_axis_s2mm_aclk : IN STD_LOGIC; axi_resetn : IN STD_LOGIC; s_axi_lite_awvalid : IN STD_LOGIC; s_axi_lite_awready : OUT STD_LOGIC; s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_lite_wvalid : IN STD_LOGIC; s_axi_lite_wready : OUT STD_LOGIC; s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_lite_bvalid : OUT STD_LOGIC; s_axi_lite_bready : IN STD_LOGIC; s_axi_lite_arvalid : IN STD_LOGIC; s_axi_lite_arready : OUT STD_LOGIC; s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_lite_rvalid : OUT STD_LOGIC; s_axi_lite_rready : IN STD_LOGIC; s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); mm2s_fsync : IN STD_LOGIC; mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0); mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); s2mm_fsync : IN STD_LOGIC; s2mm_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0); s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); mm2s_buffer_empty : OUT STD_LOGIC; mm2s_buffer_almost_empty : OUT STD_LOGIC; s2mm_buffer_full : OUT STD_LOGIC; s2mm_buffer_almost_full : OUT STD_LOGIC; mm2s_fsync_out : OUT STD_LOGIC; s2mm_fsync_out : OUT STD_LOGIC; mm2s_prmtr_update : OUT STD_LOGIC; s2mm_prmtr_update : OUT STD_LOGIC; m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_sg_arvalid : OUT STD_LOGIC; m_axi_sg_arready : IN STD_LOGIC; m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_sg_rlast : IN STD_LOGIC; m_axi_sg_rvalid : IN STD_LOGIC; m_axi_sg_rready : OUT STD_LOGIC; m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_mm2s_arvalid : OUT STD_LOGIC; m_axi_mm2s_arready : IN STD_LOGIC; m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_mm2s_rlast : IN STD_LOGIC; m_axi_mm2s_rvalid : IN STD_LOGIC; m_axi_mm2s_rready : OUT STD_LOGIC; mm2s_prmry_reset_out_n : OUT STD_LOGIC; m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_mm2s_tvalid : OUT STD_LOGIC; m_axis_mm2s_tready : IN STD_LOGIC; m_axis_mm2s_tlast : OUT STD_LOGIC; m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_s2mm_awvalid : OUT STD_LOGIC; m_axi_s2mm_awready : IN STD_LOGIC; m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_s2mm_wlast : OUT STD_LOGIC; m_axi_s2mm_wvalid : OUT STD_LOGIC; m_axi_s2mm_wready : IN STD_LOGIC; m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_s2mm_bvalid : IN STD_LOGIC; m_axi_s2mm_bready : OUT STD_LOGIC; s2mm_prmry_reset_out_n : OUT STD_LOGIC; s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_s2mm_tvalid : IN STD_LOGIC; s_axis_s2mm_tready : OUT STD_LOGIC; s_axis_s2mm_tlast : IN STD_LOGIC; mm2s_introut : OUT STD_LOGIC; s2mm_introut : OUT STD_LOGIC; axi_vdma_tstvec : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ); END COMPONENT axi_vdma; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF block_design_axi_vdma_0_0_arch: ARCHITECTURE IS "axi_vdma,Vivado 2016.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF block_design_axi_vdma_0_0_arch : ARCHITECTURE IS "block_design_axi_vdma_0_0,axi_vdma,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF block_design_axi_vdma_0_0_arch: ARCHITECTURE IS "block_design_axi_vdma_0_0,axi_vdma,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_vdma,x_ipVersion=6.2,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=9,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=1,C_ENABLE_VIDPRMTR_READS=1,C_DYNAMIC_RESOLUTION=1,C_NUM_FSTORES=3,C_USE_FSYNC=1,C_USE_MM2S_FSYNC=1,C_USE_S2MM_FSYNC=2,C_FLUSH_ON_FSYNC=1,C_INCLUDE_INTERNAL_GENLOCK=1,C_INCLUDE_SG=0,C_M_AXI_SG_ADDR_WIDTH=32,C_" & "M_AXI_SG_DATA_WIDTH=32,C_INCLUDE_MM2S=1,C_MM2S_GENLOCK_MODE=1,C_MM2S_GENLOCK_NUM_MASTERS=1,C_MM2S_GENLOCK_REPEAT_EN=0,C_MM2S_SOF_ENABLE=1,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_MM2S_SF=0,C_MM2S_LINEBUFFER_DEPTH=2048,C_MM2S_LINEBUFFER_THRESH=4,C_MM2S_MAX_BURST_LENGTH=8,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=64,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_M_AXIS_MM2S_TUSER_BITS=1,C_INCLUDE_S2MM=0,C_S2MM_GENLOCK_MODE=0,C_S2MM_GENLOCK_NUM_MASTERS=1,C_S2MM_GENLOCK_REPEAT_EN=1,C_S2MM_SOF_ENABLE=1,C_INCLUDE_S2MM" & "_DRE=0,C_INCLUDE_S2MM_SF=1,C_S2MM_LINEBUFFER_DEPTH=512,C_S2MM_LINEBUFFER_THRESH=4,C_S2MM_MAX_BURST_LENGTH=8,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=64,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_S_AXIS_S2MM_TUSER_BITS=1,C_ENABLE_DEBUG_ALL=0,C_ENABLE_DEBUG_INFO_0=0,C_ENABLE_DEBUG_INFO_1=0,C_ENABLE_DEBUG_INFO_2=0,C_ENABLE_DEBUG_INFO_3=0,C_ENABLE_DEBUG_INFO_4=0,C_ENABLE_DEBUG_INFO_5=0,C_ENABLE_DEBUG_INFO_6=1,C_ENABLE_DEBUG_INFO_7=1,C_ENABLE_DEBUG_INFO_8=0,C_ENABLE_DEBUG_INFO_9=0,C_ENABLE_DEBUG_INFO_1" & "0=0,C_ENABLE_DEBUG_INFO_11=0,C_ENABLE_DEBUG_INFO_12=0,C_ENABLE_DEBUG_INFO_13=0,C_ENABLE_DEBUG_INFO_14=1,C_ENABLE_DEBUG_INFO_15=1,C_INSTANCE=axi_vdma,C_SELECT_XPM=0,C_FAMILY=zynq}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP"; ATTRIBUTE X_INTERFACE_INFO OF mm2s_fsync: SIGNAL IS "xilinx.com:signal:video_frame_sync:1.0 MM2S_FSYNC FRAME_SYNC"; ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_in: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_IN_0 FRAME_PTR"; ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_OUT FRAME_PTR"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TUSER"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST"; ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT"; BEGIN U0 : axi_vdma GENERIC MAP ( C_S_AXI_LITE_ADDR_WIDTH => 9, C_S_AXI_LITE_DATA_WIDTH => 32, C_DLYTMR_RESOLUTION => 125, C_PRMRY_IS_ACLK_ASYNC => 1, C_ENABLE_VIDPRMTR_READS => 1, C_DYNAMIC_RESOLUTION => 1, C_NUM_FSTORES => 3, C_USE_FSYNC => 1, C_USE_MM2S_FSYNC => 1, C_USE_S2MM_FSYNC => 2, C_FLUSH_ON_FSYNC => 1, C_INCLUDE_INTERNAL_GENLOCK => 1, C_INCLUDE_SG => 0, C_M_AXI_SG_ADDR_WIDTH => 32, C_M_AXI_SG_DATA_WIDTH => 32, C_INCLUDE_MM2S => 1, C_MM2S_GENLOCK_MODE => 1, C_MM2S_GENLOCK_NUM_MASTERS => 1, C_MM2S_GENLOCK_REPEAT_EN => 0, C_MM2S_SOF_ENABLE => 1, C_INCLUDE_MM2S_DRE => 0, C_INCLUDE_MM2S_SF => 0, C_MM2S_LINEBUFFER_DEPTH => 2048, C_MM2S_LINEBUFFER_THRESH => 4, C_MM2S_MAX_BURST_LENGTH => 8, C_M_AXI_MM2S_ADDR_WIDTH => 32, C_M_AXI_MM2S_DATA_WIDTH => 64, C_M_AXIS_MM2S_TDATA_WIDTH => 32, C_M_AXIS_MM2S_TUSER_BITS => 1, C_INCLUDE_S2MM => 0, C_S2MM_GENLOCK_MODE => 0, C_S2MM_GENLOCK_NUM_MASTERS => 1, C_S2MM_GENLOCK_REPEAT_EN => 1, C_S2MM_SOF_ENABLE => 1, C_INCLUDE_S2MM_DRE => 0, C_INCLUDE_S2MM_SF => 1, C_S2MM_LINEBUFFER_DEPTH => 512, C_S2MM_LINEBUFFER_THRESH => 4, C_S2MM_MAX_BURST_LENGTH => 8, C_M_AXI_S2MM_ADDR_WIDTH => 32, C_M_AXI_S2MM_DATA_WIDTH => 64, C_S_AXIS_S2MM_TDATA_WIDTH => 32, C_S_AXIS_S2MM_TUSER_BITS => 1, C_ENABLE_DEBUG_ALL => 0, C_ENABLE_DEBUG_INFO_0 => 0, C_ENABLE_DEBUG_INFO_1 => 0, C_ENABLE_DEBUG_INFO_2 => 0, C_ENABLE_DEBUG_INFO_3 => 0, C_ENABLE_DEBUG_INFO_4 => 0, C_ENABLE_DEBUG_INFO_5 => 0, C_ENABLE_DEBUG_INFO_6 => 1, C_ENABLE_DEBUG_INFO_7 => 1, C_ENABLE_DEBUG_INFO_8 => 0, C_ENABLE_DEBUG_INFO_9 => 0, C_ENABLE_DEBUG_INFO_10 => 0, C_ENABLE_DEBUG_INFO_11 => 0, C_ENABLE_DEBUG_INFO_12 => 0, C_ENABLE_DEBUG_INFO_13 => 0, C_ENABLE_DEBUG_INFO_14 => 1, C_ENABLE_DEBUG_INFO_15 => 1, C_INSTANCE => "axi_vdma", C_SELECT_XPM => 0, C_FAMILY => "zynq" ) PORT MAP ( s_axi_lite_aclk => s_axi_lite_aclk, m_axi_sg_aclk => '0', m_axi_mm2s_aclk => m_axi_mm2s_aclk, m_axis_mm2s_aclk => m_axis_mm2s_aclk, m_axi_s2mm_aclk => '0', s_axis_s2mm_aclk => '0', axi_resetn => axi_resetn, s_axi_lite_awvalid => s_axi_lite_awvalid, s_axi_lite_awready => s_axi_lite_awready, s_axi_lite_awaddr => s_axi_lite_awaddr, s_axi_lite_wvalid => s_axi_lite_wvalid, s_axi_lite_wready => s_axi_lite_wready, s_axi_lite_wdata => s_axi_lite_wdata, s_axi_lite_bresp => s_axi_lite_bresp, s_axi_lite_bvalid => s_axi_lite_bvalid, s_axi_lite_bready => s_axi_lite_bready, s_axi_lite_arvalid => s_axi_lite_arvalid, s_axi_lite_arready => s_axi_lite_arready, s_axi_lite_araddr => s_axi_lite_araddr, s_axi_lite_rvalid => s_axi_lite_rvalid, s_axi_lite_rready => s_axi_lite_rready, s_axi_lite_rdata => s_axi_lite_rdata, s_axi_lite_rresp => s_axi_lite_rresp, mm2s_fsync => mm2s_fsync, mm2s_frame_ptr_in => mm2s_frame_ptr_in, mm2s_frame_ptr_out => mm2s_frame_ptr_out, s2mm_fsync => '0', s2mm_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), m_axi_sg_arready => '0', m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_sg_rlast => '0', m_axi_sg_rvalid => '0', m_axi_mm2s_araddr => m_axi_mm2s_araddr, m_axi_mm2s_arlen => m_axi_mm2s_arlen, m_axi_mm2s_arsize => m_axi_mm2s_arsize, m_axi_mm2s_arburst => m_axi_mm2s_arburst, m_axi_mm2s_arprot => m_axi_mm2s_arprot, m_axi_mm2s_arcache => m_axi_mm2s_arcache, m_axi_mm2s_arvalid => m_axi_mm2s_arvalid, m_axi_mm2s_arready => m_axi_mm2s_arready, m_axi_mm2s_rdata => m_axi_mm2s_rdata, m_axi_mm2s_rresp => m_axi_mm2s_rresp, m_axi_mm2s_rlast => m_axi_mm2s_rlast, m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, m_axi_mm2s_rready => m_axi_mm2s_rready, m_axis_mm2s_tdata => m_axis_mm2s_tdata, m_axis_mm2s_tkeep => m_axis_mm2s_tkeep, m_axis_mm2s_tuser => m_axis_mm2s_tuser, m_axis_mm2s_tvalid => m_axis_mm2s_tvalid, m_axis_mm2s_tready => m_axis_mm2s_tready, m_axis_mm2s_tlast => m_axis_mm2s_tlast, m_axi_s2mm_awready => '0', m_axi_s2mm_wready => '0', m_axi_s2mm_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_s2mm_bvalid => '0', s_axis_s2mm_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_s2mm_tkeep => X"F", s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_s2mm_tvalid => '0', s_axis_s2mm_tlast => '0', mm2s_introut => mm2s_introut ); END block_design_axi_vdma_0_0_arch;

-- ############################################################################# -- DE0_Nano_TRDB_D5M_LT24_top_level.vhd -- ==================================== -- -- BOARD : DE0-Nano from Terasic -- Author : Sahand Kashani-Akhavan from Terasic documentation -- Revision : 1.5 -- Last updated : 2017-06-11 12:48:26 UTC -- -- Syntax Rule : GROUP_NAME_N[bit] -- -- GROUP : specify a particular interface (ex: SDR_) -- NAME : signal name (ex: CONFIG, D, ...) -- bit : signal index -- _N : to specify an active-low signal -- ############################################################################# library ieee; use ieee.std_logic_1164.all; entity DE0_Nano_TRDB_D5M_LT24_top_level is port( -- CLOCK CLOCK_50 : in std_logic; -- LED LED : out std_logic_vector(7 downto 0); -- KEY_N KEY_N : in std_logic_vector(1 downto 0); -- SW SW : in std_logic_vector(3 downto 0); -- SDRAM DRAM_ADDR : out std_logic_vector(12 downto 0); DRAM_BA : out std_logic_vector(1 downto 0); DRAM_CAS_N : out std_logic; DRAM_CKE : out std_logic; DRAM_CLK : out std_logic; DRAM_CS_N : out std_logic; DRAM_DQ : inout std_logic_vector(15 downto 0); DRAM_DQM : out std_logic_vector(1 downto 0); DRAM_RAS_N : out std_logic; DRAM_WE_N : out std_logic; -- EPCS EPCS_ASDO : out std_logic; EPCS_DATA0 : in std_logic; EPCS_DCLK : out std_logic; EPCS_NCSO : out std_logic; -- Accelerometer and EEPROM G_SENSOR_CS_N : out std_logic; G_SENSOR_INT : in std_logic; I2C_SCLK : out std_logic; I2C_SDAT : inout std_logic; -- ADC ADC_CS_N : out std_logic; ADC_SADDR : out std_logic; ADC_SCLK : out std_logic; ADC_SDAT : in std_logic; -- 2x13 GPIO Header GPIO_2 : inout std_logic_vector(12 downto 0); GPIO_2_IN : in std_logic_vector(2 downto 0); -- GPIO_0 GPIO_0_D5M_D : in std_logic_vector(11 downto 0); GPIO_0_D5M_FVAL : in std_logic; GPIO_0_D5M_LVAL : in std_logic; GPIO_0_D5M_PIXCLK : in std_logic; GPIO_0_D5M_RESET_N : out std_logic; GPIO_0_D5M_SCLK : inout std_logic; GPIO_0_D5M_SDATA : inout std_logic; GPIO_0_D5M_STROBE : in std_logic; GPIO_0_D5M_TRIGGER : out std_logic; GPIO_0_D5M_XCLKIN : out std_logic; -- GPIO_1 GPIO_1_LT24_ADC_BUSY : in std_logic; GPIO_1_LT24_ADC_CS_N : out std_logic; GPIO_1_LT24_ADC_DCLK : out std_logic; GPIO_1_LT24_ADC_DIN : out std_logic; GPIO_1_LT24_ADC_DOUT : in std_logic; GPIO_1_LT24_ADC_PENIRQ_N : in std_logic; GPIO_1_LT24_CS_N : out std_logic; GPIO_1_LT24_D : out std_logic_vector(15 downto 0); GPIO_1_LT24_LCD_ON : out std_logic; GPIO_1_LT24_RD_N : out std_logic; GPIO_1_LT24_RESET_N : out std_logic; GPIO_1_LT24_RS : out std_logic; GPIO_1_LT24_WR_N : out std_logic ); end entity DE0_Nano_TRDB_D5M_LT24_top_level; architecture rtl of DE0_Nano_TRDB_D5M_LT24_top_level is begin end;

-- -*- vhdl -*- ------------------------------------------------------------------------------- -- Copyright (c) 2012, The CARPE Project, All rights reserved. -- -- See the AUTHORS file for individual contributors. -- -- -- -- Copyright and related rights are licensed under the Solderpad -- -- Hardware License, Version 0.51 (the "License"); you may not use this -- -- file except in compliance with the License. You may obtain a copy of -- -- the License at http://solderpad.org/licenses/SHL-0.51. -- -- -- -- Unless required by applicable law or agreed to in writing, software, -- -- hardware and materials distributed under this License is distributed -- -- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -- -- either express or implied. See the License for the specific language -- -- governing permissions and limitations under the License. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library sys; use sys.sys_pkg.all; use work.cpu_or1knd_i5_mmu_data_pkg.all; entity cpu_or1knd_i5_mmu_data is port ( clk : in std_ulogic; rstn : in std_ulogic; cpu_or1knd_i5_mmu_data_ctrl_in : in cpu_or1knd_i5_mmu_data_ctrl_in_type; cpu_or1knd_i5_mmu_data_dp_in : in cpu_or1knd_i5_mmu_data_dp_in_type; cpu_or1knd_i5_mmu_data_ctrl_out : out cpu_or1knd_i5_mmu_data_ctrl_out_type; cpu_or1knd_i5_mmu_data_dp_out : out cpu_or1knd_i5_mmu_data_dp_out_type; cpu_or1knd_i5_mmu_data_ctrl_in_pipe : in cpu_or1knd_i5_mmu_data_ctrl_in_pipe_type; cpu_or1knd_i5_mmu_data_dp_in_pipe : in cpu_or1knd_i5_mmu_data_dp_in_pipe_type; cpu_or1knd_i5_mmu_data_ctrl_out_pipe : out cpu_or1knd_i5_mmu_data_ctrl_out_pipe_type; cpu_or1knd_i5_mmu_data_dp_out_pipe : out cpu_or1knd_i5_mmu_data_dp_out_pipe_type ); end;

use Std.Textio.all; library IEEE; use ieee.std_logic_1164.ALL; entity test_divider is end; architecture test_divider of test_divider is component c_divider generic(width : INTEGER ; const :INTEGER ); port(Input: in std_logic_vector((width - 1) downto 0); Output : out std_logic_vector((width - 1) downto 0)); end component; for all : c_divider use entity WORK.c_divider(behavior); signal Input: std_logic_vector(3 downto 0); signal Output : std_logic_vector(3 downto 0); file S_IN : TEXT is out "c_divider_beh.out"; begin divider_1 : c_divider generic map(4,2) port map(Input, Output); test_process : process begin Input <= "1010"; wait for 50 ns; Input <= "0101"; wait for 50 ns; Input <= "0110"; wait for 50 ns; Input <= "0000"; wait for 50 ns; Input <= "0000"; wait for 50 ns; Input <= "0101"; wait for 50 ns; Input <= "1111"; wait for 50 ns; Input <= "1001"; wait for 50 ns; Input <= "1110"; wait for 50 ns; wait; end process test_process; end test_divider;

-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3 -- IP Revision: 1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY blk_mem_gen_v8_3_1; USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1; ENTITY blk_mem_gen_0 IS PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END blk_mem_gen_0; ARCHITECTURE blk_mem_gen_0_arch OF blk_mem_gen_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_0_arch: ARCHITECTURE IS "yes"; COMPONENT blk_mem_gen_v8_3_1 IS GENERIC ( C_FAMILY : STRING; C_XDEVICEFAMILY : STRING; C_ELABORATION_DIR : STRING; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_AXI_SLAVE_TYPE : INTEGER; C_USE_BRAM_BLOCK : INTEGER; C_ENABLE_32BIT_ADDRESS : INTEGER; C_CTRL_ECC_ALGO : STRING; C_HAS_AXI_ID : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_MEM_TYPE : INTEGER; C_BYTE_SIZE : INTEGER; C_ALGORITHM : INTEGER; C_PRIM_TYPE : INTEGER; C_LOAD_INIT_FILE : INTEGER; C_INIT_FILE_NAME : STRING; C_INIT_FILE : STRING; C_USE_DEFAULT_DATA : INTEGER; C_DEFAULT_DATA : STRING; C_HAS_RSTA : INTEGER; C_RST_PRIORITY_A : STRING; C_RSTRAM_A : INTEGER; C_INITA_VAL : STRING; C_HAS_ENA : INTEGER; C_HAS_REGCEA : INTEGER; C_USE_BYTE_WEA : INTEGER; C_WEA_WIDTH : INTEGER; C_WRITE_MODE_A : STRING; C_WRITE_WIDTH_A : INTEGER; C_READ_WIDTH_A : INTEGER; C_WRITE_DEPTH_A : INTEGER; C_READ_DEPTH_A : INTEGER; C_ADDRA_WIDTH : INTEGER; C_HAS_RSTB : INTEGER; C_RST_PRIORITY_B : STRING; C_RSTRAM_B : INTEGER; C_INITB_VAL : STRING; C_HAS_ENB : INTEGER; C_HAS_REGCEB : INTEGER; C_USE_BYTE_WEB : INTEGER; C_WEB_WIDTH : INTEGER; C_WRITE_MODE_B : STRING; C_WRITE_WIDTH_B : INTEGER; C_READ_WIDTH_B : INTEGER; C_WRITE_DEPTH_B : INTEGER; C_READ_DEPTH_B : INTEGER; C_ADDRB_WIDTH : INTEGER; C_HAS_MEM_OUTPUT_REGS_A : INTEGER; C_HAS_MEM_OUTPUT_REGS_B : INTEGER; C_HAS_MUX_OUTPUT_REGS_A : INTEGER; C_HAS_MUX_OUTPUT_REGS_B : INTEGER; C_MUX_PIPELINE_STAGES : INTEGER; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER; C_USE_SOFTECC : INTEGER; C_USE_ECC : INTEGER; C_EN_ECC_PIPE : INTEGER; C_HAS_INJECTERR : INTEGER; C_SIM_COLLISION_CHECK : STRING; C_COMMON_CLK : INTEGER; C_DISABLE_WARN_BHV_COLL : INTEGER; C_EN_SLEEP_PIN : INTEGER; C_USE_URAM : INTEGER; C_EN_RDADDRA_CHG : INTEGER; C_EN_RDADDRB_CHG : INTEGER; C_EN_DEEPSLEEP_PIN : INTEGER; C_EN_SHUTDOWN_PIN : INTEGER; C_EN_SAFETY_CKT : INTEGER; C_DISABLE_WARN_BHV_RANGE : INTEGER; C_COUNT_36K_BRAM : STRING; C_COUNT_18K_BRAM : STRING; C_EST_POWER_SUMMARY : STRING ); PORT ( clka : IN STD_LOGIC; rsta : IN STD_LOGIC; ena : IN STD_LOGIC; regcea : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); clkb : IN STD_LOGIC; rstb : IN STD_LOGIC; enb : IN STD_LOGIC; regceb : IN STD_LOGIC; web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); injectsbiterr : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; eccpipece : IN STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); sleep : IN STD_LOGIC; deepsleep : IN STD_LOGIC; shutdown : IN STD_LOGIC; rsta_busy : OUT STD_LOGIC; rstb_busy : OUT STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; s_axi_injectsbiterr : IN STD_LOGIC; s_axi_injectdbiterr : IN STD_LOGIC; s_axi_sbiterr : OUT STD_LOGIC; s_axi_dbiterr : OUT STD_LOGIC; s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT blk_mem_gen_v8_3_1; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN"; ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; BEGIN U0 : blk_mem_gen_v8_3_1 GENERIC MAP ( C_FAMILY => "zynq", C_XDEVICEFAMILY => "zynq", C_ELABORATION_DIR => "./", C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_AXI_SLAVE_TYPE => 0, C_USE_BRAM_BLOCK => 0, C_ENABLE_32BIT_ADDRESS => 0, C_CTRL_ECC_ALGO => "NONE", C_HAS_AXI_ID => 0, C_AXI_ID_WIDTH => 4, C_MEM_TYPE => 0, C_BYTE_SIZE => 9, C_ALGORITHM => 1, C_PRIM_TYPE => 1, C_LOAD_INIT_FILE => 0, C_INIT_FILE_NAME => "no_coe_file_loaded", C_INIT_FILE => "blk_mem_gen_0.mem", C_USE_DEFAULT_DATA => 0, C_DEFAULT_DATA => "0", C_HAS_RSTA => 0, C_RST_PRIORITY_A => "CE", C_RSTRAM_A => 0, C_INITA_VAL => "0", C_HAS_ENA => 1, C_HAS_REGCEA => 0, C_USE_BYTE_WEA => 0, C_WEA_WIDTH => 1, C_WRITE_MODE_A => "WRITE_FIRST", C_WRITE_WIDTH_A => 8, C_READ_WIDTH_A => 8, C_WRITE_DEPTH_A => 256, C_READ_DEPTH_A => 256, C_ADDRA_WIDTH => 8, C_HAS_RSTB => 0, C_RST_PRIORITY_B => "CE", C_RSTRAM_B => 0, C_INITB_VAL => "0", C_HAS_ENB => 0, C_HAS_REGCEB => 0, C_USE_BYTE_WEB => 0, C_WEB_WIDTH => 1, C_WRITE_MODE_B => "WRITE_FIRST", C_WRITE_WIDTH_B => 8, C_READ_WIDTH_B => 8, C_WRITE_DEPTH_B => 256, C_READ_DEPTH_B => 256, C_ADDRB_WIDTH => 8, C_HAS_MEM_OUTPUT_REGS_A => 1, C_HAS_MEM_OUTPUT_REGS_B => 0, C_HAS_MUX_OUTPUT_REGS_A => 0, C_HAS_MUX_OUTPUT_REGS_B => 0, C_MUX_PIPELINE_STAGES => 0, C_HAS_SOFTECC_INPUT_REGS_A => 0, C_HAS_SOFTECC_OUTPUT_REGS_B => 0, C_USE_SOFTECC => 0, C_USE_ECC => 0, C_EN_ECC_PIPE => 0, C_HAS_INJECTERR => 0, C_SIM_COLLISION_CHECK => "ALL", C_COMMON_CLK => 0, C_DISABLE_WARN_BHV_COLL => 0, C_EN_SLEEP_PIN => 0, C_USE_URAM => 0, C_EN_RDADDRA_CHG => 0, C_EN_RDADDRB_CHG => 0, C_EN_DEEPSLEEP_PIN => 0, C_EN_SHUTDOWN_PIN => 0, C_EN_SAFETY_CKT => 0, C_DISABLE_WARN_BHV_RANGE => 0, C_COUNT_36K_BRAM => "0", C_COUNT_18K_BRAM => "1", C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.54005 mW" ) PORT MAP ( clka => clka, rsta => '0', ena => ena, regcea => '0', wea => wea, addra => addra, dina => dina, douta => douta, clkb => '0', rstb => '0', enb => '0', regceb => '0', web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), injectsbiterr => '0', injectdbiterr => '0', eccpipece => '0', sleep => '0', deepsleep => '0', shutdown => '0', s_aclk => '0', s_aresetn => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awvalid => '0', s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wlast => '0', s_axi_wvalid => '0', s_axi_bready => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arvalid => '0', s_axi_rready => '0', s_axi_injectsbiterr => '0', s_axi_injectdbiterr => '0' ); END blk_mem_gen_0_arch;

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.2 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== Library ieee; use ieee.std_logic_1164.all; entity convolve_kernel_fcud is generic ( ID : integer := 2; NUM_STAGE : integer := 4; din0_WIDTH : integer := 32; din1_WIDTH : integer := 32; dout_WIDTH : integer := 32 ); port ( clk : in std_logic; reset : in std_logic; ce : in std_logic; din0 : in std_logic_vector(din0_WIDTH-1 downto 0); din1 : in std_logic_vector(din1_WIDTH-1 downto 0); dout : out std_logic_vector(dout_WIDTH-1 downto 0) ); end entity; architecture arch of convolve_kernel_fcud is --------------------- Component --------------------- component convolve_kernel_ap_fmul_2_max_dsp_32 is port ( aclk : in std_logic; aclken : in std_logic; s_axis_a_tvalid : in std_logic; s_axis_a_tdata : in std_logic_vector(31 downto 0); s_axis_b_tvalid : in std_logic; s_axis_b_tdata : in std_logic_vector(31 downto 0); m_axis_result_tvalid : out std_logic; m_axis_result_tdata : out std_logic_vector(31 downto 0) ); end component; --------------------- Local signal ------------------ signal aclk : std_logic; signal aclken : std_logic; signal a_tvalid : std_logic; signal a_tdata : std_logic_vector(31 downto 0); signal b_tvalid : std_logic; signal b_tdata : std_logic_vector(31 downto 0); signal r_tvalid : std_logic; signal r_tdata : std_logic_vector(31 downto 0); signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0); signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0); begin --------------------- Instantiation ----------------- convolve_kernel_ap_fmul_2_max_dsp_32_u : component convolve_kernel_ap_fmul_2_max_dsp_32 port map ( aclk => aclk, aclken => aclken, s_axis_a_tvalid => a_tvalid, s_axis_a_tdata => a_tdata, s_axis_b_tvalid => b_tvalid, s_axis_b_tdata => b_tdata, m_axis_result_tvalid => r_tvalid, m_axis_result_tdata => r_tdata ); --------------------- Assignment -------------------- aclk <= clk; aclken <= ce; a_tvalid <= '1'; a_tdata <= din0_buf1; b_tvalid <= '1'; b_tdata <= din1_buf1; dout <= r_tdata; --------------------- Input buffer ------------------ process (clk) begin if clk'event and clk = '1' then if ce = '1' then din0_buf1 <= din0; din1_buf1 <= din1; end if; end if; end process; end architecture;

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Thomas B. Preusser -- -- Package: Simulation constants, functions and utilities. -- -- Description: -- ------------------------------------- -- .. TODO:: No documentation available. -- -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.math_real.all; library PoC; use PoC.utils.all; -- use PoC.strings.all; use PoC.vectors.all; -- use PoC.physical.all; package sim_types is constant C_SIM_VERBOSE : boolean := FALSE; -- POC_VERBOSE -- =========================================================================== -- Simulation Task and Status Management -- =========================================================================== type T_SIM_BOOLVEC is array(integer range <>) of boolean; subtype T_SIM_TEST_ID is integer range -1 to 1023; subtype T_SIM_TEST_NAME is string(1 to 256); subtype T_SIM_PROCESS_ID is natural range 0 to 1023; subtype T_SIM_PROCESS_NAME is string(1 to 64); subtype T_SIM_PROCESS_INSTNAME is string(1 to 256); type T_SIM_PROCESS_ID_VECTOR is array(natural range <>) of T_SIM_PROCESS_ID; type T_SIM_TEST_STATUS is ( SIM_TEST_STATUS_CREATED, SIM_TEST_STATUS_ACTIVE, SIM_TEST_STATUS_ENDED, SIM_TEST_STATUS_ZOMBI ); type T_SIM_PROCESS_STATUS is ( SIM_PROCESS_STATUS_ACTIVE, SIM_PROCESS_STATUS_ENDED ); type T_SIM_TEST is record ID : T_SIM_TEST_ID; Name : T_SIM_TEST_NAME; Status : T_SIM_TEST_STATUS; ProcessIDs : T_SIM_PROCESS_ID_VECTOR(T_SIM_PROCESS_ID); ProcessCount : T_SIM_PROCESS_ID; ActiveProcessCount : T_SIM_PROCESS_ID; end record; type T_SIM_TEST_VECTOR is array(integer range <>) of T_SIM_TEST; type T_SIM_PROCESS is record ID : T_SIM_PROCESS_ID; TestID : T_SIM_TEST_ID; Name : T_SIM_PROCESS_NAME; Status : T_SIM_PROCESS_STATUS; IsLowPriority : boolean; end record; type T_SIM_PROCESS_VECTOR is array(natural range <>) of T_SIM_PROCESS; constant C_SIM_DEFAULT_TEST_ID : T_SIM_TEST_ID := -1; constant C_SIM_DEFAULT_TEST_NAME : string := "Default test"; -- =========================================================================== -- Random Numbers -- =========================================================================== type T_SIM_RAND_SEED is record Seed1 : integer; Seed2 : integer; end record; procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED); procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedValue : in T_SIM_RAND_SEED); procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedVector : in T_INTVEC); procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedVector : in string); function randInitializeSeed return T_SIM_RAND_SEED; function randInitializeSeed(SeedValue : T_SIM_RAND_SEED) return T_SIM_RAND_SEED; function randInitializeSeed(SeedVector : T_INTVEC) return T_SIM_RAND_SEED; function randInitializeSeed(SeedVector : string) return T_SIM_RAND_SEED; -- Uniform distributed random values -- =========================================================================== procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL); procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; Minimum : integer; Maximum : integer); procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Minimum : REAL; Maximum : REAL); -- Normal / Gaussian distributed random values -- =========================================================================== procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; StandardDeviation : REAL := 1.0; Mean : REAL := 0.0); procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer); procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL); -- Poisson distributed random values -- =========================================================================== procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Mean : in REAL); procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; Mean : in REAL; Minimum : in integer; Maximum : in integer); procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL); -- =========================================================================== -- Clock Generation -- =========================================================================== -- type T_PERCENT is INTEGER'range units type T_PERCENT is range integer'low to INTEGER'high units ppb; ppm = 1000 ppb; permil = 1000 ppm; percent = 10 permil; one = 100 percent; end units; subtype T_WANDER is T_PERCENT range -1 one to 1 one; subtype T_DUTYCYCLE is T_PERCENT range 0 ppb to 1 one; type T_DEGREE is range integer'low to INTEGER'high units second; minute = 60 second; deg = 60 minute; end units; subtype T_PHASE is T_DEGREE range -360 deg to 360 deg; function ite(cond : boolean; value1 : T_DEGREE; value2 : T_DEGREE) return T_DEGREE; end package; package body sim_types is function ite(cond : boolean; value1 : T_DEGREE; value2 : T_DEGREE) return T_DEGREE is begin if cond then return value1; else return value2; end if; end function; -- =========================================================================== -- Random Numbers -- =========================================================================== constant MAX_SEED1_VALUE : positive := 2147483562; constant MAX_SEED2_VALUE : positive := 2147483398; function randGenerateInitialSeed return T_SIM_RAND_SEED is begin return ( Seed1 => 5, Seed2 => 3423 ); end function; function randBoundSeed(SeedValue : in T_SIM_RAND_SEED) return T_SIM_RAND_SEED is begin return ( Seed1 => (SeedValue.Seed1 - 1 mod MAX_SEED1_VALUE) + 1, Seed2 => (SeedValue.Seed2 - 1 mod MAX_SEED2_VALUE) + 1 ); end function; procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED) is begin Seed := randGenerateInitialSeed; end procedure; procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedValue : in T_SIM_RAND_SEED) is begin Seed := randBoundSeed(SeedValue); end procedure; procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedVector : in T_INTVEC) is begin if (SeedVector'length = 0) then Seed := randGenerateInitialSeed; elsif (SeedVector'length = 1) then Seed := randBoundSeed(T_SIM_RAND_SEED'( Seed1 => SeedVector(0), Seed2 => 92346 )); elsif (SeedVector'length = 2) then Seed := randBoundSeed(T_SIM_RAND_SEED'( Seed1 => SeedVector(0), Seed2 => SeedVector(1) )); else -- FIXME: -- Seed.Seed1 := SeedVector(0); -- Seed.Seed2 := SeedVector(1); end if; end procedure; procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedVector : in string) is begin if (SeedVector'length = 0) then Seed := randGenerateInitialSeed; elsif (SeedVector'length = 1) then Seed := T_SIM_RAND_SEED'( Seed1 => character'pos(SeedVector(1)), Seed2 => 39834 ); elsif (SeedVector'length = 2) then Seed := T_SIM_RAND_SEED'( Seed1 => character'pos(SeedVector(1)), Seed2 => character'pos(SeedVector(2)) ); else -- FIXME: -- Seed.Seed1 := CHARACTER'pos(SeedVector(0)); -- Seed.Seed2 := CHARACTER'pos(SeedVector(1)); end if; end procedure; function randInitializeSeed return T_SIM_RAND_SEED is begin return randGenerateInitialSeed; end function; function randInitializeSeed(SeedValue : T_SIM_RAND_SEED) return T_SIM_RAND_SEED is begin return randBoundSeed(SeedValue); end function; function randInitializeSeed(SeedVector : T_INTVEC) return T_SIM_RAND_SEED is variable Result : T_SIM_RAND_SEED; begin randInitializeSeed(Result, SeedVector); return Result; end function; function randInitializeSeed(SeedVector : string) return T_SIM_RAND_SEED is variable Result : T_SIM_RAND_SEED; begin randInitializeSeed(Result, SeedVector); return Result; end function; -- =========================================================================== -- Uniform distributed random values -- =========================================================================== procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL) is begin ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, Value); end procedure; procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; Minimum : integer; Maximum : integer) is variable rand : REAL; begin if Maximum < Minimum then report "randUniformDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand); Value := scale(rand, Minimum, Maximum); end procedure; procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Minimum : REAL; Maximum : REAL) is variable rand : REAL; begin if Maximum < Minimum then report "randUniformDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand); Value := scale(rand, Minimum, Maximum); end procedure; -- =========================================================================== -- Normal / Gaussian distributed random values -- =========================================================================== procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; StandardDeviation : REAL := 1.0; Mean : REAL := 0.0) is variable rand1 : REAL; variable rand2 : REAL; begin if StandardDeviation < 0.0 then report "randNormalDistributedValue: Standard deviation must be >= 0.0" severity FAILURE; end if; -- Box Muller transformation ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand1); ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand2); -- standard normal distribution: mean 0, variance 1 Value := StandardDeviation * (sqrt(-2.0 * log(rand1)) * cos(MATH_2_PI * rand2)) + Mean; end procedure; procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer) is variable rand_real : REAL; variable rand_int : integer; begin if Maximum < Minimum then report "randNormalDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; if StandardDeviation < 0.0 then report "randNormalDistributedValue: Standard deviation must be >= 0.0" severity FAILURE; end if; while TRUE loop randNormalDistributedValue(Seed, rand_real, StandardDeviation, Mean); rand_int := integer(round(rand_real)); exit when ((Minimum <= rand_int) and (rand_int <= Maximum)); end loop; Value := rand_int; end procedure; procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) is variable rand : REAL; begin if Maximum < Minimum then report "randNormalDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; if StandardDeviation < 0.0 then report "randNormalDistributedValue: Standard deviation must be >= 0.0" severity FAILURE; end if; while TRUE loop randNormalDistributedValue(Seed, rand, StandardDeviation, Mean); exit when ((Minimum <= rand) and (rand <= Maximum)); end loop; Value := rand; end procedure; -- =========================================================================== -- Poisson distributed random values -- =========================================================================== procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Mean : in REAL) is variable Product : Real; variable Bound : Real; variable rand : Real; variable Result : Real; begin Product := 1.0; Result := 0.0; Bound := exp(-1.0 * Mean); if ((Mean <= 0.0) or (Bound <= 0.0)) then report "randPoissonDistributedValue: Mean must be greater than 0.0." severity FAILURE; return; end if; while (Product >= Bound) loop ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand); Product := Product * rand; Result := Result + 1.0; end loop; Value := Result; end procedure; procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; Mean : in REAL; Minimum : in integer; Maximum : in integer) is variable rand_real : REAL; variable rand_int : integer; begin if Maximum < Minimum then report "randPoissonDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; while TRUE loop randPoissonDistributedValue(Seed, rand_real, Mean); rand_int := integer(round(rand_real)); exit when ((Minimum <= rand_int) and (rand_int <= Maximum)); end loop; Value := rand_int; end procedure; procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) is variable rand : REAL; begin if Maximum < Minimum then report "randPoissonDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; while TRUE loop randPoissonDistributedValue(Seed, rand, Mean); exit when ((Minimum <= rand) and (rand <= Maximum)); end loop; Value := rand; end procedure; end package body;

divisor2_inst : divisor2 PORT MAP ( clock => clock_sig, cout => cout_sig, q => q_sig );

-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1103.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c06s05b00x00p03n01i01103ent IS END c06s05b00x00p03n01i01103ent; ARCHITECTURE c06s05b00x00p03n01i01103arch OF c06s05b00x00p03n01i01103ent IS BEGIN TESTING: PROCESS type FIVE is range 1 to 5; type ABASE is array (FIVE range <>) of BOOLEAN; subtype A1 is ABASE(FIVE); type R1 is record RE1: A1; end record; type R2 is record RE2: R1; end record; variable V1: A1; variable V2: R1 ; -- := (RE1=>(others=>TRUE)); variable V3: R2 ; -- := (RE2=>(RE1=>(others=>TRUE))); BEGIN V1(2 to 4) := V2.RE1(2 to 4); -- No_failure_here assert NOT(V1(2 to 4)=(false,false,false)) report "***PASSED TEST: c06s05b00x00p03n01i01103" severity NOTE; assert (V1(2 to 4)=(false,false,false)) report "***FAILED TEST: c06s05b00x00p03n01i01103 - Prefix of a slice can be a selected name." severity ERROR; wait; END PROCESS TESTING; END c06s05b00x00p03n01i01103arch;

library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity p_jinfo_comps_info_dc_tbl_no is port ( wa0_data : in std_logic; wa0_addr : in std_logic_vector(1 downto 0); clk : in std_logic; ra0_addr : in std_logic_vector(1 downto 0); ra0_data : out std_logic; wa0_en : in std_logic ); end p_jinfo_comps_info_dc_tbl_no; architecture augh of p_jinfo_comps_info_dc_tbl_no is -- Embedded RAM type ram_type is array (0 to 2) of std_logic; signal ram : ram_type := (others => '0'); -- Little utility functions to make VHDL syntactically correct -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. -- This happens when accessing arrays with <= 2 cells, for example. function to_integer(B: std_logic) return integer is variable V: std_logic_vector(0 to 0); begin V(0) := B; return to_integer(unsigned(V)); end; function to_integer(V: std_logic_vector) return integer is begin return to_integer(unsigned(V)); end; begin -- Sequential process -- It handles the Writes process (clk) begin if rising_edge(clk) then -- Write to the RAM -- Note: there should be only one port. if wa0_en = '1' then ram( to_integer(wa0_addr) ) <= wa0_data; end if; end if; end process; -- The Read side (the outputs) ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 3 else '-'; end architecture;

-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1714.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c09s02b00x00p10n01i01714ent IS port (signal max : in natural); type word is array (natural range <>) of bit; subtype mem_array is word (0 to 7); END c09s02b00x00p10n01i01714ent; ARCHITECTURE c09s02b00x00p10n01i01714arch OF c09s02b00x00p10n01i01714ent IS signal idx : natural; signal mem : mem_array; BEGIN TESTING: PROCESS(bit_vector'("10101")) BEGIN assert FALSE report "***FAILED TEST: c09s02b00x00p10n01i01714 - Process sensitivity list can not be a qualified string." severity ERROR; END PROCESS TESTING; END c09s02b00x00p10n01i01714arch;

entity array1 is end entity; architecture test of array1 is type matrix_t is array (integer range <>, integer range <>) of integer; constant c : matrix_t(0 to 1, 0 to 1) := ( ( 1, 2 ), ( 3, 4 ) ); begin process is variable m : matrix_t(1 to 3, 1 to 3) := ( ( 1, 2, 3 ), ( 4, 5, 6 ), ( 7, 8, 9 ) ); begin report integer'image(m(1, 3)); report integer'image(m(2, 2)); assert m(2, 2) = 5; assert m(3, 1) = 7; report integer'image(c(1, 0)); assert c(1, 0) = 3; assert c = ( (1, 2), (3, 4) ); assert c /= ( (1, 2), (3, 5) ); wait; end process; end architecture;

--! --! Copyright (C) 2010 - 2013 Creonic GmbH --! --! @file: periodic_stimuli.vhd --! @brief: write and simulate a vhdl code that generates the signs sig1 and sig2 and signal y --! @author: Antonio Gutierrez --! @date: 2014-04-01 --! --! -------------------------------------- library ieee; use ieee.std_logic_1164.all; -------------------------------------- entity periodic_stimuli is --generic declarations end entity periodic_stimuli; -------------------------------------- architecture circuit of periodic_stimuli is signal sig1: std_logic := '1'; signal sig2: std_logic := '1'; signal y: std_logic: = '1'; begin -- stimuli sig1 -- (ii) sequential sig1_proc: process begin sig1 <= '1'; wait for 25 ns; sig1 <= '0'; wait for 50 ns; end process sig1_proc; sig2_proc: process begin sig2 <= '1'; wait for 25 ns; sig2 <= '0'; wait for 50 ns; sig2 <= '1'; wait for 25 ns; sig2 <= '0'; wait for 25 ns; sig2 <= '1'; wait for 50 ns; sig2 <= '0'; wait for 25 ns; end process sig2_proc; y_proc: process begin y <= '1'; wait for 20 ns; y <= '0'; wait for 10 ns; y <= '1'; wait for 10 ns; y <= '0'; wait for 40 ns; end process y_proc; end architecture circuit; --------------------------------------

-- -- Copyright (C) 2009-2012 Chris McClelland -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU Lesser General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Lesser General Public License for more details. -- -- You should have received a copy of the GNU Lesser General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity trace_fifo_wrapper is port( -- Clock clk_in : in std_logic; depth_out : out std_logic_vector(12 downto 0); -- Data is clocked into the FIFO on each clock edge where both valid & ready are high inputData_in : in std_logic_vector(55 downto 0); inputValid_in : in std_logic; inputReady_out : out std_logic; -- Data is clocked out of the FIFO on each clock edge where both valid & ready are high outputData_out : out std_logic_vector(55 downto 0); outputValid_out : out std_logic; outputReady_in : in std_logic ); end entity; architecture structural of trace_fifo_wrapper is signal inputFull : std_logic; signal outputEmpty : std_logic; begin -- Invert "full/empty" signals to give "ready/valid" signals inputReady_out <= not(inputFull); outputValid_out <= not(outputEmpty); -- The encapsulated FIFO fifo : entity work.xilinx_trace_fifo port map( clk => clk_in, data_count => depth_out, -- Production end din => inputData_in, wr_en => inputValid_in, full => inputFull, -- Consumption end dout => outputData_out, empty => outputEmpty, rd_en => outputReady_in ); end architecture;

--! --! Copyright 2019 Sergey Khabarov, sergeykhbr@gmail.com --! --! Licensed under the Apache License, Version 2.0 (the "License"); --! you may not use this file except in compliance with the License. --! You may obtain a copy of the License at --! --! http://www.apache.org/licenses/LICENSE-2.0 --! --! Unless required by applicable law or agreed to in writing, software --! distributed under the License is distributed on an "AS IS" BASIS, --! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --! See the License for the specific language governing permissions and --! limitations under the License. --! library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; -- or_reduce() library commonlib; use commonlib.types_common.all; library techmap; use techmap.types_mem.all; entity tagmem is generic ( memtech : integer := 0; async_reset : boolean := false; wayidx : integer := 0; abus : integer := 64; -- system bus address bus (32 or 64 bits) ibits : integer := 7; -- lines memory addres width (usually 6..8) lnbits : integer := 5; -- One line bits: log2(bytes_per_line) flbits : integer := 1; -- Total flags number saved with address tag snoop : boolean := false -- snoop channel (only with enabled L2-cache) ); port ( i_clk : in std_logic; i_nrst : in std_logic; i_addr : in std_logic_vector(abus-1 downto 0); i_wstrb : in std_logic_vector(2**lnbits-1 downto 0); i_wdata : in std_logic_vector(8*(2**lnbits)-1 downto 0); i_wflags : in std_logic_vector(flbits-1 downto 0); o_raddr : out std_logic_vector(abus-1 downto 0); o_rdata : out std_logic_vector(8*(2**lnbits)-1 downto 0); o_rflags : out std_logic_vector(flbits-1 downto 0); o_hit : out std_logic; -- L2 snoop portm active when snoop = 1 i_snoop_addr : in std_logic_vector(abus-1 downto 0); o_snoop_flags : out std_logic_vector(flbits-1 downto 0) ); end; architecture arch_tagmem of tagmem is constant TAG_BITS : integer := abus - ibits - lnbits; constant TAG_WITH_FLAGS : integer := TAG_BITS + flbits; signal wb_index : std_logic_vector(ibits-1 downto 0); signal tago_rdata : std_logic_vector(TAG_WITH_FLAGS-1 downto 0); signal tagi_wdata : std_logic_vector(TAG_WITH_FLAGS-1 downto 0); signal tagi_we : std_logic; signal wb_snoop_index : std_logic_vector(ibits-1 downto 0); signal wb_snoop_tagaddr : std_logic_vector(TAG_BITS-1 downto 0); signal tago_snoop_rdata : std_logic_vector(TAG_WITH_FLAGS-1 downto 0); signal rb_tagaddr : std_logic_vector(TAG_BITS-1 downto 0); signal rb_index : std_logic_vector(ibits-1 downto 0); signal rb_snoop_tagaddr : std_logic_vector(TAG_BITS-1 downto 0); begin -- 1-byte memory banks combining into cache line dx : for n in 0 to 2**lnbits-1 generate datax : ram_tech generic map ( memtech => memtech, abits => ibits, dbits => 8 ) port map ( i_clk => i_clk, i_addr => wb_index, i_wena => i_wstrb(n), i_wdata => i_wdata(8*n+7 downto 8*n), o_rdata => o_rdata(8*n+7 downto 8*n) ); end generate; tag0 : ram_tech generic map ( memtech => memtech, abits => ibits, dbits => TAG_WITH_FLAGS ) port map ( i_clk => i_clk, i_addr => wb_index, i_wena => tagi_we, i_wdata => tagi_wdata, o_rdata => tago_rdata ); snoopena : if snoop generate tagsnoop0 : ram_tech generic map ( memtech => memtech, abits => ibits, dbits => TAG_WITH_FLAGS ) port map ( i_clk => i_clk, i_addr => wb_snoop_index, i_wena => tagi_we, i_wdata => tagi_wdata, o_rdata => tago_snoop_rdata ); end generate; snoopdis : if not snoop generate tago_snoop_rdata <= (others => '0'); end generate; comb : process(i_nrst, i_addr, i_wstrb, i_wdata, i_wflags, tago_rdata, tago_snoop_rdata, rb_tagaddr, rb_index) variable vb_index : std_logic_vector(ibits-1 downto 0); variable vb_raddr : std_logic_vector(abus-1 downto 0); variable vb_tagi_wdata : std_logic_vector(TAG_WITH_FLAGS-1 downto 0); variable v_hit : std_logic; variable vb_snoop_index : std_logic_vector(ibits-1 downto 0); variable vb_snoop_tagaddr : std_logic_vector(TAG_BITS-1 downto 0); variable vb_snoop_flags : std_logic_vector(flbits-1 downto 0); begin v_hit := '0'; if rb_tagaddr = tago_rdata(TAG_BITS-1 downto 0) then v_hit := tago_rdata(TAG_BITS); -- valid bit end if; vb_raddr := (others => '0'); vb_raddr(abus-1 downto ibits + lnbits) := tago_rdata(TAG_BITS-1 downto 0); vb_raddr(ibits + lnbits - 1 downto lnbits) := rb_index; vb_index := i_addr(ibits + lnbits - 1 downto lnbits); vb_tagi_wdata := i_wflags & i_addr(abus-1 downto ibits + lnbits); if snoop then vb_snoop_flags := tago_snoop_rdata(TAG_WITH_FLAGS-1 downto TAG_BITS); vb_snoop_index := i_snoop_addr(ibits + lnbits - 1 downto lnbits); vb_snoop_tagaddr := i_snoop_addr(abus - 1 downto ibits + lnbits); if or_reduce(i_wstrb) = '1' then vb_snoop_index := vb_index; end if; if rb_snoop_tagaddr /= tago_snoop_rdata(TAG_BITS-1 downto 0) then vb_snoop_flags := (others => '0'); end if; else vb_snoop_flags := (others => '0'); vb_snoop_index := (others => '0'); vb_snoop_tagaddr := (others => '0'); end if; if not async_reset and i_nrst = '0' then vb_tagi_wdata := (others => '0'); vb_index := (others => '0'); end if; wb_index <= vb_index; tagi_we <= or_reduce(i_wstrb); tagi_wdata <= vb_tagi_wdata; o_raddr <= vb_raddr; o_rflags <= tago_rdata(TAG_WITH_FLAGS-1 downto TAG_BITS); o_hit <= v_hit; wb_snoop_index <= vb_snoop_index; wb_snoop_tagaddr <= vb_snoop_tagaddr; o_snoop_flags <= vb_snoop_flags; end process; -- registers: regs : process(i_clk, i_nrst) begin if async_reset and i_nrst = '0' then rb_tagaddr <= (others => '0'); rb_index <= (others => '0'); rb_snoop_tagaddr <= (others => '0'); elsif rising_edge(i_clk) then rb_tagaddr <= tagi_wdata(TAG_BITS-1 downto 0); rb_index <= wb_index; rb_snoop_tagaddr <= wb_snoop_tagaddr; end if; end process; end;

--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use IEEE.NUMERIC_STD.all; use ieee.math_real.all; use std.textio.all; use ieee.std_logic_misc.all; package TB_Package is function Header_gen(Packet_length, source, destination, packet_id: integer ) return std_logic_vector ; function Body_gen(Packet_length, Data: integer ) return std_logic_vector ; function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ; procedure gen_packet(Packet_length, source, destination, packet_id, initial_delay: in integer; finish_time: in time; signal clk: in std_logic; signal DCTS: in std_logic; signal RTS: out std_logic; signal port_in: out std_logic_vector); procedure gen_random_packet(frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer; finish_time: in time; signal clk: in std_logic; signal DCTS: in std_logic; signal RTS: out std_logic; signal port_in: out std_logic_vector); procedure gen_bit_reversed_packet(frame_length, source, initial_delay, network_size, min_packet_size, max_packet_size: in integer; finish_time: in time; signal clk: in std_logic; signal DCTS: in std_logic; signal RTS: out std_logic; signal port_in: out std_logic_vector); procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic; signal CTS: out std_logic; signal DRTS: in std_logic; signal port_in: in std_logic_vector); procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer); end TB_Package; package body TB_Package is constant Header_type : std_logic_vector := "001"; constant Body_type : std_logic_vector := "010"; constant Tail_type : std_logic_vector := "100"; function Header_gen(Packet_length, source, destination, packet_id: integer) return std_logic_vector is variable Header_flit: std_logic_vector (31 downto 0); begin Header_flit := Header_type & std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) & std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)) & XOR_REDUCE(Header_type & std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) & std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8))); return Header_flit; end Header_gen; function Body_gen(Packet_length, Data: integer) return std_logic_vector is variable Body_flit: std_logic_vector (31 downto 0); begin Body_flit := Body_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Data, 28))); return Body_flit; end Body_gen; function Tail_gen(Packet_length, Data: integer) return std_logic_vector is variable Tail_flit: std_logic_vector (31 downto 0); begin Tail_flit := Tail_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Tail_type & std_logic_vector(to_unsigned(Data, 28))); return Tail_flit; end Tail_gen; procedure gen_packet(Packet_length, source, destination, packet_id, initial_delay: in integer; finish_time: in time; signal clk: in std_logic; signal DCTS: in std_logic; signal RTS: out std_logic; signal port_in: out std_logic_vector) is -- Packet_length of 3 means it has 1 header, 1 body and 1 tail. the number of body packets are equal to Packet_length-2 -- source: id of the source node -- destination: id of the destination node -- packet id: packet identification number! TODO: has to be implemented! -- initial_delay: waits for this number of clock cycles before sending the packet! variable seed1 :positive ; variable seed2 :positive ; variable rand : real ; variable first_time :boolean := true; variable destination_id: integer; variable LINEVARIABLE : line; file VEC_FILE : text is out "sent.txt"; begin while true loop RTS <= '0'; if first_time = true then for i in 0 to initial_delay loop wait until clk'event and clk ='0'; end loop; else wait until clk'event and clk ='0'; end if; --wait untill the falling edge of the clock to avoid race! report "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination); write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination) & " with length: "& integer'image(Packet_length)); writeline(VEC_FILE, LINEVARIABLE); port_in <= Header_gen(Packet_length, source, destination, packet_id); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; for I in 0 to Packet_length-3 loop uniform(seed1, seed2, rand); wait until clk'event and clk ='0'; port_in <= Body_gen(Packet_length, integer(rand*1000.0)); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; end loop; wait until clk'event and clk ='0'; port_in <= Tail_gen(Packet_length, 200); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; if now > finish_time then wait; end if; end loop; end gen_packet; procedure gen_random_packet(frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer; finish_time: in time; signal clk: in std_logic; signal DCTS: in std_logic; signal RTS: out std_logic; signal port_in: out std_logic_vector) is -- frame_length is inverse of PIR. with the unit of clock cycles. which means how many clock cycles per packet to -- be injected. to build a true random traffic generator, we need to make a series of frames: -- -- -- <--- Frame length-----> <--- Frame length-----> <--- Frame length-----> -- -- <-----> |<--------|///////|---->|<----|///////////|---->|<-|////|-------------->| -- initial <-------> <----------> <-------------> -- delay frame Packet_size frame -- initial end delay -- delay -- -- source: id of the source node -- initial_delay: waits for this number of clock cycles before sending the packet! variable seed1 :positive ; variable seed2 :positive ; variable rand : real ; variable first_time :boolean := true; variable id_counter : integer:= 0; variable frame_starting_delay, Packet_length, frame_ending_delay: integer := 0; variable destination_id: integer; variable LINEVARIABLE : line; file VEC_FILE : text is out "sent.txt"; begin while true loop -- generating the ID id_counter := id_counter + 1; if id_counter = 256 then id_counter := 0; end if; -- generating the packet length uniform(seed1, seed2, rand); Packet_length := integer((integer(rand*100.0)*frame_length)/300); if (Packet_length < min_packet_size) then Packet_length:=min_packet_size; end if; if (Packet_length > max_packet_size) then Packet_length:=max_packet_size; end if; assert (3*Packet_length<=frame_length) report "packet_length "& integer'image(Packet_length)&" exceeds frame size "& integer'image(frame_length) severity failure; --generating the frame initial delay uniform(seed1, seed2, rand); frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100); --generating the frame ending delay frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay); RTS <= '0'; if first_time = true then port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ; wait until clk'event and clk ='1'; for i in 0 to initial_delay loop -- wait until clk'event and clk ='0'; wait for 1 ns; end loop; port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ; wait until clk'event and clk ='1'; for k in 0 to frame_starting_delay-1 loop --wait until clk'event and clk ='0'; wait for 1 ns; end loop; first_time := false; else wait until clk'event and clk ='1'; for k in 0 to frame_starting_delay-1 loop --wait until clk'event and clk ='0'; wait for 1 ns; end loop; end if; uniform(seed1, seed2, rand); destination_id := integer(rand*3.0); while (destination_id = source) loop uniform(seed1, seed2, rand); destination_id := integer(rand*3.0); end loop; --wait untill the falling edge of the clock to avoid race! report "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id); write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: "& integer'image(Packet_length)& " with id: "&integer'image(id_counter)); writeline(VEC_FILE, LINEVARIABLE); port_in <= Header_gen(Packet_length, source, destination_id, id_counter); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; for I in 0 to Packet_length-3 loop uniform(seed1, seed2, rand); wait until clk'event and clk ='0'; port_in <= Body_gen(Packet_length, integer(rand*1000.0)); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; end loop; wait until clk'event and clk ='0'; uniform(seed1, seed2, rand); port_in <= Tail_gen(Packet_length, integer(rand*1000.0)); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ; for l in 0 to frame_ending_delay-1 loop wait for 1 ns; end loop; port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ; if now > finish_time then wait; end if; end loop; end gen_random_packet; procedure gen_bit_reversed_packet(frame_length, source, initial_delay, network_size, min_packet_size, max_packet_size: in integer; finish_time: in time; signal clk: in std_logic; signal DCTS: in std_logic; signal RTS: out std_logic; signal port_in: out std_logic_vector) is -- frame_length is inverse of PIR. with the unit of clock cycles. which means how many clock cycles per packet to -- be injected. to build a true random traffic generator, we need to make a series of frames: -- -- -- <--- Frame length-----> <--- Frame length-----> <--- Frame length-----> -- -- <-----> |<--------|///////|---->|<----|///////////|---->|<-|////|-------------->| -- initial <-------> <----------> <-------------> -- delay frame Packet_size frame -- initial end delay -- delay -- -- source: id of the source node -- initial_delay: waits for this number of clock cycles before sending the packet! variable seed1 :positive ; variable seed2 :positive ; variable rand : real ; variable first_time :boolean := true; variable id_counter : integer:= 0; variable frame_starting_delay, Packet_length, frame_ending_delay: integer := 0; variable destination_id: integer; variable LINEVARIABLE : line; file VEC_FILE : text is out "sent.txt"; begin while true loop -- generating the ID id_counter := id_counter + 1; if id_counter = 256 then id_counter := 0; end if; -- generating the packet length uniform(seed1, seed2, rand); Packet_length := integer((integer(rand*100.0)/300)*frame_length); if (Packet_length < min_packet_size) then Packet_length := min_packet_size; end if; if (Packet_length > max_packet_size) then Packet_length := max_packet_size; end if; assert (3*Packet_length<=frame_length) report "packet_length "& integer'image(Packet_length)&" exceeds frame size "& integer'image(frame_length) severity failure; --generating the frame initial delay uniform(seed1, seed2, rand); frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100); --generating the frame ending delay frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay); RTS <= '0'; if first_time = true then port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ; wait until clk'event and clk ='1'; for i in 0 to initial_delay loop -- wait until clk'event and clk ='0'; wait for 1 ns; end loop; port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ; wait until clk'event and clk ='1'; for k in 0 to frame_starting_delay-1 loop --wait until clk'event and clk ='0'; wait for 1 ns; end loop; first_time := false; else wait until clk'event and clk ='1'; for k in 0 to frame_starting_delay-1 loop --wait until clk'event and clk ='0'; wait for 1 ns; end loop; end if; destination_id := to_integer(unsigned(not std_logic_vector(to_unsigned(source, network_size)))); if destination_id = source then wait; end if; --wait untill the falling edge of the clock to avoid race! report "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id); report " frame_size: " & integer'image(frame_length) & " packet_length: " & integer'image(Packet_length) & "starting_delay: " & integer'image(frame_starting_delay) & " ending_delay: " & integer'image(frame_ending_delay); write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: "& integer'image(Packet_length)& " with id: "&integer'image(id_counter)); writeline(VEC_FILE, LINEVARIABLE); port_in <= Header_gen(Packet_length, source, destination_id, id_counter); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; for I in 0 to Packet_length-3 loop uniform(seed1, seed2, rand); wait until clk'event and clk ='0'; port_in <= Body_gen(Packet_length, integer(rand*1000.0)); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; end loop; wait until clk'event and clk ='0'; uniform(seed1, seed2, rand); port_in <= Tail_gen(Packet_length, integer(rand*1000.0)); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ; for l in 0 to frame_ending_delay-1 loop wait for 1 ns; end loop; port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ; if now > finish_time then wait; end if; end loop; end gen_bit_reversed_packet; procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic; signal CTS: out std_logic; signal DRTS: in std_logic; signal port_in: in std_logic_vector) is -- initial_delay: waits for this number of clock cycles before sending the packet! variable source_node, destination_node, P_length, packet_id, counter: integer; variable LINEVARIABLE : line; file VEC_FILE : text is out "received.txt"; begin while true loop counter := 0; CTS <= '0'; wait until DRTS'event and DRTS ='1'; wait until clk'event and clk ='1'; CTS <= '1'; wait until clk'event and clk ='1'; if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then counter := 1; P_length := to_integer(unsigned(port_in(28 downto 17))); destination_node := to_integer(unsigned(port_in(16 downto 13))); source_node := to_integer(unsigned(port_in(12 downto 9))); packet_id := to_integer(unsigned(port_in(8 downto 1))); end if; CTS <= '0'; while (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) /= "100") loop wait until DRTS'event and DRTS ='1'; wait until clk'event and clk ='1'; CTS <= '1'; wait until clk'event and clk ='1'; counter := counter+1; CTS <= '0'; end loop; report "Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) & " with length: "& integer'image(P_length) & " counter: "& integer'image(counter); assert (P_length=counter) report "wrong packet size" severity failure; assert (Node_ID=destination_node) report "wrong packet destination " severity failure; write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length)& " id: "& integer'image(packet_id)); writeline(VEC_FILE, LINEVARIABLE); end loop; end get_packet; procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer) is variable seed1 :positive := seed_1; variable seed2 :positive := seed_2; variable rand : real; variable stuck: integer; begin sta_0 <= '0'; sta_1 <= '0'; while true loop sta_0 <= '0'; sta_1 <= '0'; for I in 0 to delay loop wait for 1 ns; end loop; uniform(seed1, seed2, rand); address <= std_logic_vector(to_unsigned(integer(rand*31.0), 5)); uniform(seed1, seed2, rand); stuck := integer(rand*11.0); if stuck > 5 then sta_0 <= '1'; sta_1 <= '0'; else sta_0 <= '0'; sta_1 <= '1'; end if; wait for 1 ns; end loop; end gen_fault; end TB_Package;

entity case13 is end entity; architecture test of case13 is function get_bits (n : natural; b : bit) return bit_vector is variable v : bit_vector(1 to n); begin v := (others => b); return v; end function; signal n : natural := 3; signal b : bit; begin p1: process (n, b) is begin case get_bits(n, b) is when "111" => report "ones"; when "000" => report "zeros"; when others => assert false; end case; end process; stim: process is begin b <= '1'; wait for 0 ns; n <= 5; wait for 1 ns; assert false report "should not reach here!"; wait; end process; end architecture;

-- NEED RESULT: ARCH00657: Multiple interface declarations in correct order passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00657 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 4.3.1 (2) -- -- DESIGN UNIT ORDERING: -- -- ENT00657(ARCH00657) -- ENT00657_Test_Bench(ARCH00657_Test_Bench) -- -- REVISION HISTORY: -- -- 27-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.all ; entity ENT00657 is generic ( cinteger1, cinteger2, cinteger3 : integer ; cbool1, cbool2, cbool3 : boolean ; cstring1, cstring2, cstring3 : string ) ; port ( sinteger1, sinteger2, sinteger3 : integer ; sbool1, sbool2, sbool3 : boolean ; sstring1, sstring2, sstring3 : string ) ; end ENT00657 ; -- architecture ARCH00657 of ENT00657 is procedure p1 ( constant cinteger1, cinteger2, cinteger3 : integer ; constant cbool1, cbool2, cbool3 : boolean ; constant cstring1, cstring2, cstring3 : string ; variable vinteger1, vinteger2, vinteger3 : inout integer ; variable vbool1, vbool2, vbool3 : inout boolean ; variable vstring1, vstring2, vstring3 : inout string ; signal sinteger1, sinteger2, sinteger3 : integer ; signal sbool1, sbool2, sbool3 : boolean ; signal sstring1, sstring2, sstring3 : string ; variable correct : out boolean ) is begin correct := cinteger1 = 1 and cinteger2 = 2 and cinteger3 = 3 and cbool1 = true and cbool2 = false and cbool3 = true and cstring1 = "aa" and cstring2 = "bb" and cstring3 = "cc" and vinteger1 = 1 and vinteger2 = 2 and vinteger3 = 3 and vbool1 = true and vbool2 = false and vbool3 = true and vstring1 = "aa" and vstring2 = "bb" and vstring3 = "cc" and sinteger1 = 1 and sinteger2 = 2 and sinteger3 = 3 and sbool1 = true and sbool2 = false and sbool3 = true and sstring1 = "aa" and sstring2 = "bb" and sstring3 = "cc" ; end p1 ; begin process subtype str is string ( 1 to 2 ) ; variable correct : boolean ; variable vinteger1 : integer := cinteger1 ; variable vinteger2 : integer := cinteger2 ; variable vinteger3 : integer := cinteger3 ; variable vbool1 : boolean := cbool1 ; variable vbool2 : boolean := cbool2 ; variable vbool3 : boolean := cbool3 ; variable vstring1 : str := cstring1 ; variable vstring2 : str := cstring2 ; variable vstring3 : str := cstring3 ; begin p1 ( cinteger1, cinteger2, cinteger3, cbool1, cbool2, cbool3, cstring1, cstring2, cstring3, vinteger1, vinteger2, vinteger3, vbool1, vbool2, vbool3, vstring1, vstring2, vstring3, sinteger1, sinteger2, sinteger3, sbool1, sbool2, sbool3, sstring1, sstring2, sstring3, correct ) ; test_report ( "ARCH00657" , "Multiple interface declarations in correct order" , correct ) ; wait ; end process ; end ARCH00657 ; -- entity ENT00657_Test_Bench is end ENT00657_Test_Bench ; architecture ARCH00657_Test_Bench of ENT00657_Test_Bench is subtype str is string ( 1 to 2 ) ; signal sinteger1 : integer := 1 ; signal sinteger2 : integer := 2 ; signal sinteger3 : integer := 3 ; signal sbool1 : boolean := true ; signal sbool2 : boolean := false ; signal sbool3 : boolean := true ; signal sstring1 : str := "aa" ; signal sstring2 : str := "bb" ; signal sstring3 : str := "cc" ; begin L1: block component UUT generic ( cinteger1, cinteger2, cinteger3 : integer ; cbool1, cbool2, cbool3 : boolean ; cstring1, cstring2, cstring3 : string ) ; port ( sinteger1, sinteger2, sinteger3 : integer ; sbool1, sbool2, sbool3 : boolean ; sstring1, sstring2, sstring3 : string ) ; end component ; for CIS1 : UUT use entity WORK.ENT00657 ( ARCH00657 ) ; begin CIS1 : UUT generic map ( 1, 2, 3, true, false, true, "aa", "bb", "cc" ) port map ( sinteger1, sinteger2, sinteger3, sbool1, sbool2, sbool3, sstring1, sstring2, sstring3 ) ; end block L1 ; end ARCH00657_Test_Bench ; --

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 16:04:21 05/02/2016 -- Design Name: -- Module Name: contatore_4_cifre - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity contatore_4_cifre is end contatore_4_cifre; architecture Behavioral of contatore_4_cifre is component Contatore_1_cifra is port(Clock, Enable_in, UpDown, Reset, Preset : in std_logic; N_preset : in std_logic_vector(3 downto 0); N : out std_logic_vector(3 downto 0); Enable_out : out std_logic); end Contatore_1_cifra; begin C0:Contatore_1_cifra PORT MAP(Clock=>clock_timer_globale, Enable_in => enable, UpDown => updown, Reset => reset, Preset => preset, N_preset => npreset, N => N0, Enable_out => enable_0_to_1); C1:Contatore_1_cifra PORT MAP(Clock=>clock_timer_globale, Enable_in => enable_0_to_1, UpDown => updown, Reset => reset, Preset => preset, N_preset => npreset, N => N1, Enable_out => enable_1_to_2); C2:Contatore_1_cifra PORT MAP(Clock=>clock_timer_globale, Enable_in => enable_1_to_2, UpDown => updown, Reset => reset, Preset => preset, N_preset => npreset, N => N2, Enable_out => enable_2_to_3); C3:Contatore_1_cifra PORT MAP(Clock=>clock_timer_globale, Enable_in => enable_2_to_3, UpDown => updown, Reset => reset, Preset => preset, N_preset => npreset, N => N3, Enable_out => open); --C1:contatore_1_cifra PORT MAP(clock_timer=>clock_timer_globale, -- enable_in => enable_0_to_1, N_OUT => N1, -- enable_out => enable_1_to_2); --C2:contatore_1_cifra PORT MAP(clock_timer=>clock_timer_globale, - -- enable_in => enable_1_to_2, N_OUT => N2, -- enable_out => enable_2_to_3); --C3:contatore_1_cifra PORT MAP(clock_timer=>clock_timer_globale, -- enable_in => enable_2_to_3, N_OUT => N3, -- enable_out => open); end Behavioral;

-- This file is part of easyFPGA. -- Copyright 2013-2015 os-cillation GmbH -- -- easyFPGA is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- easyFPGA is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- -- 8-bit PWM using two-process design pattern -- (pwm8.vhd) -- -- @author Simon Gansen ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------- -- Type and component definition package ------------------------------------------------------------------------------- package pwm8_comp is type pwm8_in_type is record duty_cycle : std_logic_vector(7 downto 0); end record; component pwm8 port ( clk : in std_logic; rst : in std_logic; d : in pwm8_in_type; pwm : out std_logic ); end component; end package; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.pwm8_comp.all; ------------------------------------------------------------------------------- ENTITY pwm8 is ------------------------------------------------------------------------------- port ( clk : in std_logic; rst : in std_logic; d : in pwm8_in_type; pwm : out std_logic ); end pwm8; ------------------------------------------------------------------------------- ARCHITECTURE two_proc of pwm8 is ------------------------------------------------------------------------------- type reg_type is record pwm_cnt : unsigned(7 downto 0); -- pwm counter end record; signal reg_out, reg_in : reg_type; begin ------------------------------------------------------------------------------- COMBINATIONAL : process(d, reg_out) ------------------------------------------------------------------------------- variable tmp_var : reg_type; begin tmp_var := reg_out; -- default assignments ---algorithm------------------------------------------------------------- -- PWM: reset on overflow, increment otherwise if (tmp_var.pwm_cnt = 2**8-1) then tmp_var.pwm_cnt := (others => '0'); else tmp_var.pwm_cnt := reg_out.pwm_cnt + 1; end if; -- compare and drive output if (tmp_var.pwm_cnt >= unsigned(d.duty_cycle)) then pwm <= '0'; else pwm <= '1'; end if; ------------------------------------------------------------------------- reg_in <= tmp_var; -- drive register inputs end process COMBINATIONAL; ------------------------------------------------------------------------------- REGISTERS : process(clk,rst) ------------------------------------------------------------------------------- begin if (rst = '1') then reg_out.pwm_cnt <= (others => '0'); elsif rising_edge(clk) then reg_out <= reg_in; end if; end process REGISTERS; end two_proc;

-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc838.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity c01s03b01x00p02n01i00838ent_a is end c01s03b01x00p02n01i00838ent_a; architecture c01s03b01x00p02n01i00838arch_a of c01s03b01x00p02n01i00838ent_a is begin AC_BLK : block signal B : BIT; begin B <= '1'; end block; end; ENTITY c01s03b01x00p02n01i00838ent IS END c01s03b01x00p02n01i00838ent; ARCHITECTURE c01s03b01x00p02n01i00838arch OF c01s03b01x00p02n01i00838ent IS BEGIN A_BLK : block component C end component; begin L1 : C; L2 : C; L3 : C; end block; TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c01s03b01x00p02n01i00838 - Missing semicolon." severity ERROR; wait; END PROCESS TESTING; END c01s03b01x00p02n01i00838arch; configuration c01s03b01x00p02n01i00838cfg of c01s03b01x00p02n01i00838ent is for c01s03b01x00p02n01i00838arch for A_BLK for L1 : C use entity work.c01s03b01x00p02n01i00838ent_a (c01s03b01x00p02n01i00838arch_a) ; end for; for L2 : C use entity work.c01s03b01x00p02n01i00838ent_a (c01s03b01x00p02n01i00838arch_a) ; end for; for L3 : C use entity work.c01s03b01x00p02n01i00838ent_a (c01s03b01x00p02n01i00838arch_a) ; end for --- Failure_here end for; end for; end c01s03b01x00p02n01i00838cfg;

entity func21 is end entity; architecture test of func21 is type rec is record x, y : integer; end record; function func (r : rec) return integer is begin return r.x + r.y; end function; begin p1: process is variable a, b : integer; begin assert func(r.x => 1, r.y => 2) = 3; a := 4; b := 5; wait for 1 ns; assert func(r.x => a, r.y => b) = 9; wait; end process; end architecture;

-- Test case from Brian Padalino -- library ieee ; use ieee.std_logic_1164.all ; package pack is type iface_t is record cs : std_logic ; addr : std_logic_vector ; rdata : std_logic_vector ; wdata : std_logic_vector ; end record ; function init_iface_signals(addr_width : natural ; data_width : natural) return iface_t; end package ; package body pack is function init_iface_signals(addr_width : natural ; data_width : natural) return iface_t is variable rv : iface_t(addr(addr_width-1 downto 0), wdata(data_width-1 downto 0), rdata(data_width-1 downto 0)) ; begin rv.cs := '0' ; rv.addr := (rv.addr'range => '0') ; rv.wdata := (rv.wdata'range => '0') ; rv.rdata := (rv.rdata'range => '0') ; return rv ; end function ; end package body ; library ieee ; use ieee.std_logic_1164.all ; use work.pack.all ; entity master is port ( clock : in std_logic ; iface : inout iface_t := init_iface_signals(16, 32) ) ; end entity ; architecture arch of master is begin end architecture ; library ieee ; use ieee.std_logic_1164.all ; use work.pack.all ; entity signal23 is end entity ; architecture arch of signal23 is signal clock : std_logic := '0' ; signal iface : iface_t(addr(15 downto 0), rdata(31 downto 0), wdata(31 downto 0)) ; begin clock <= not clock after 1 ns ; U_master : entity work.master port map ( clock => clock, iface => iface ) ; tb : process begin report LF & "if:" & LF & " cs: " & std_logic'image(iface.cs) & LF & " addr: " & to_hstring(iface.addr) & LF & " rdata: " & to_hstring(iface.rdata) & LF & " wdata: " & to_hstring(iface.wdata) ; std.env.stop ; end process ; end architecture ;

entity ent is port ( i : in bit ); end ent; architecture a of ent is begin end;

-- -a --ieee=synopsis -fexplicit -Wc,-m32 -Wa,--32 -- -e -Wa,--32 -Wl,-m32 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity dmem is port (a: in std_logic_vector(31 downto 0); wd: in std_logic_vector(31 downto 0); clk, we: in bit; rd: out std_logic_vector(31 downto 0)); end entity; architecture arq_dmem of dmem is type mem is array (0 to 63) of std_logic_vector(31 downto 0); begin process(clk) variable my_mem: mem; variable address: std_logic_vector(5 downto 0); variable pos_a: integer; begin for pos in 0 to 63 loop --Inicializo mi memoria my_mem(pos) := std_logic_vector(to_unsigned(pos, 32)); end loop; if clk'EVENT and clk='1' then address := a(7 downto 2); pos_a := to_integer(unsigned(address)); if we='1' then my_mem(pos_a) := wd; rd <= wd; else rd <= my_mem(pos_a); end if; end if; end process; end architecture;

---- -- This file is part of etip-ss11-g07. -- -- Copyright (C) 2011 Lukas Märdian <lukasmaerdian@gmail.com> -- Copyright (C) 2011 M. S. -- Copyright (C) 2011 Orest Tarasiuk <orest.tarasiuk@tum.de> -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. ---- LIBRARY ieee; USE ieee.numeric_std.all; USE ieee.std_logic_1164.all; -- USE ieee.std_logic_unsigned.all; ENTITY BINBCD IS PORT( clk : IN std_logic; bin_input : IN std_logic_vector (16 DOWNTO 0); einer, zehner, hunderter, tausender, zehntausender : OUT std_logic_vector (3 DOWNTO 0); overflow : OUT std_logic ); END BINBCD; ARCHITECTURE DoubleDabbleV3 OF BINBCD IS SIGNAL overflw : std_logic := '1'; BEGIN PROCESS(clk) VARIABLE int_input : integer := 0; BEGIN IF (rising_edge(clk)) THEN int_input := to_integer(unsigned(bin_input)); IF (int_input <= 99999) THEN overflow <= '0'; overflw <= '0'; ELSE overflow <= '1'; overflw <= '1'; einer <= "0000"; zehner <= "0000"; hunderter <= "0000"; tausender <= "0000"; zehntausender <= "0000"; END IF; END IF; END PROCESS; PROCESS(clk) VARIABLE vector: std_logic_vector(36 DOWNTO 0) := "00000000000000000000" & bin_input; BEGIN IF (rising_edge(clk)) AND (overflw = '0') THEN FOR i IN 0 TO 17 LOOP -- Prüfen, ob größergleich 5; falls ja, dann 3 addieren für: -- Zehntausender IF (vector(35 DOWNTO 33) = "101") OR (vector(35 DOWNTO 33) = "110") OR (vector(35 DOWNTO 33) = "111") OR (vector(36) = '1') THEN vector(36 DOWNTO 33) := std_logic_vector(unsigned(vector(36 DOWNTO 33)) + "0011"); END IF; -- Tausender IF (vector(31 DOWNTO 29) = "101") OR (vector(31 DOWNTO 29) = "110") OR (vector(31 DOWNTO 29) = "111") OR (vector(32) = '1') THEN vector(32 DOWNTO 29) := std_logic_vector(unsigned(vector(32 DOWNTO 29)) + "0011"); END IF; -- Hunderter IF (vector(27 DOWNTO 25) = "101") OR (vector(27 DOWNTO 25) = "110") OR (vector(27 DOWNTO 25) = "111") OR (vector(28) = '1') THEN vector(28 DOWNTO 25) := std_logic_vector(unsigned(vector(28 DOWNTO 25)) + "0011"); END IF; -- Zehner IF (vector(23 DOWNTO 21) = "101") OR (vector(23 DOWNTO 21) = "110") OR (vector(23 DOWNTO 21) = "111") OR (vector(24) = '1') THEN vector(24 DOWNTO 21) := std_logic_vector(unsigned(vector(24 DOWNTO 21)) + "0011"); END IF; -- Einer IF (vector(19 DOWNTO 17) = "101") OR (vector(19 DOWNTO 17) = "110") OR (vector(19 DOWNTO 17) = "111") OR (vector(20) = '1') THEN vector(20 DOWNTO 17) := std_logic_vector(unsigned(vector(20 DOWNTO 17)) + "0011"); END IF; -- Shiften: vector := vector(35 DOWNTO 0) & '0'; END LOOP; -- Ergebnisse in die jeweiligen Stellen schreiben zehntausender <= vector(36 DOWNTO 33); tausender <= vector(32 DOWNTO 29); hunderter <= vector(28 DOWNTO 25); zehner <= vector(24 DOWNTO 21); einer <= vector(20 DOWNTO 17); END IF; END PROCESS; END DoubleDabbleV3;

use std.textio.all; package broken_module is type prot_t is protected procedure proc; end protected; end package; package body broken_module is type prot_t is protected body variable var : natural := 0; procedure file_proc is file fwrite : text; begin file_open(fwrite, "out", WRITE_MODE); file_close(fwrite); end procedure; procedure proc is begin file_proc; var := 0; -- Comment out this and it will not fail end procedure; end protected body; end package body; ------------------------------------------------------------------------------- entity issue91 is end entity; use work.broken_module.all; architecture test of issue91 is shared variable p : prot_t; begin process is begin p.proc; wait; end process; end architecture;

architecture RTL of FIFO is signal sig1 : std_logic_vector(31 downto 0); signal sig2 : std_logic_vector( 3 downto 0); signal sig3 : std_logic_vector(c_width downto 0); -- Violations signal sig1 : std_logic_vector( 31 downto 0); signal sig2 : std_logic_vector(3 downto 0); signal sig3 : std_logic_vector(c_width downto 0); begin end architecture RTL;

Library ieee; Use ieee.std_logic_1164.all; Entity nreg is Generic ( n : integer := 16); port( Clk,Rst,enable : in std_logic; d : in std_logic_vector(n-1 downto 0); q : out std_logic_vector(n-1 downto 0)); end nreg; Architecture arch_nreg of nreg is begin Process (Clk,Rst) begin if Rst = '1' then q <= (others=>'0'); elsif clk'event and clk = '1' then if (enable = '1') then q <= d; end if; end if; end process; end arch_nreg;

-- -- WISHBONE revB2 compiant I2C master core -- -- author: Richard Herveille -- rev. 0.1 based on simple_i2c -- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman) -- rev. 0.3 may 4th 2001, fixed typo rev.0.2 txt -> txr -- rev. 0.4 may 8th, added some remarks, fixed some sensitivity list issues -- -- -- Changes compared to simple_i2c -- 1) WISHBONE interface -- 2) added start/stop detection -- 3) added busy bit -- 4) removed automatic tri-state buffer insertion (for ASIC support) -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity wishbone_i2c_master is port ( -- wishbone signals CLK_I : in std_logic; -- master clock input RST_I : in std_logic := '0'; -- synchronous active high reset nRESET: in std_logic := '1'; -- asynchronous active low reset ADR_I : in std_logic_vector(1 downto 0); -- lower address bits DAT_I : in std_logic_vector(15 downto 0); -- Databus input DAT_O : out std_logic_vector(15 downto 0); -- Databus output SEL_I : in std_logic_vector(1 downto 0); -- Byte select signals WE_I : in std_logic; -- Write enable input STB_I : in std_logic; -- Strobe signals / core select signal CYC_I : in std_logic; -- Valid bus cycle input ACK_O : out std_logic; -- Bus cycle acknowledge output INTA_O : out std_logic; -- interrupt request output signal -- I2C signals SCLi : in std_logic; -- I2C clock line SCLo : out std_logic; SDAi : in std_logic; -- I2C data line SDAo : out std_logic ); end entity wishbone_i2c_master; architecture structural of wishbone_i2c_master is component byte_ctrl is port ( clk : in std_logic; rst : in std_logic; -- synchronous active high reset (WISHBONE compatible) nReset : in std_logic; -- asynchornous active low reset (FPGA compatible) clk_cnt : in unsigned(15 downto 0); -- 4x SCL -- input signals ena, start, stop, read, write, ack_in : std_logic; Din : in std_logic_vector(7 downto 0); -- output signals cmd_ack : out std_logic; ack_out : out std_logic; Dout : out std_logic_vector(7 downto 0); i2c_busy : out std_logic; -- i2c signals SCLi : in std_logic; -- I2C clock line SCLo : out std_logic; SDAi : in std_logic; -- I2C data line SDAo : out std_logic ); end component byte_ctrl; -- registers signal prer : unsigned(15 downto 0); -- clock prescale register signal ctr : std_logic_vector(7 downto 0); -- control register signal txr : std_logic_vector(7 downto 0); -- transmit register signal rxr : std_logic_vector(7 downto 0); -- receive register signal cr : std_logic_vector(7 downto 0); -- command register signal sr : std_logic_vector(7 downto 0); -- status register -- done signal: command completed, clear command register signal done : std_logic; -- command register signals signal sta, sto, rd, wr, ack, iack : std_logic; -- core enable signal signal core_en : std_logic; -- status register signals signal irxack, rxack : std_logic; -- received aknowledge from slave signal tip : std_logic; -- transfer in progress signal irq_flag : std_logic; -- interrupt pending flag signal i2c_busy : std_logic; -- bus busy (start signal detected) begin -- generate acknowledge output signal ACK_O <= STB_I; -- since timing is always honored -- assign DAT_O assign_dato : process(ADR_I, prer, ctr, txr, cr, rxr, sr) begin case ADR_I is when "00" => DAT_O <= std_logic_vector(prer); when "01" => DAT_O <= (x"00" & ctr); when "10" => DAT_O <= (txr & cr); when "11" => DAT_O <= (rxr & sr); when others => DAT_O <= (others => 'X'); -- for simulation only end case; end process assign_dato; -- registers block regs_block: block -- address decode signals signal we_a0, we_a1, we_a2, we_a3 : std_logic; begin -- decode address lines we_a0 <= CYC_I and STB_I and WE_I and not ADR_I(1) and not ADR_I(0); -- 00 we_a1 <= CYC_I and STB_I and WE_I and not ADR_I(1) and ADR_I(0); -- 01 we_a2 <= CYC_I and STB_I and WE_I and ADR_I(1) and not ADR_I(0); -- 10 we_a3 <= CYC_I and STB_I and WE_I and ADR_I(1) and ADR_I(0); -- 11 -- store data in writeable registers -- prescale register write_prer: process(nRESET, CLK_I) begin if (nRESET = '0') then prer <= (others => '1'); elsif (CLK_I'event and CLK_I = '1') then if (RST_I = '1') then prer <= (others => '1'); else if ( (we_a0 and SEL_I(1)) = '1') then prer(15 downto 8) <= unsigned(DAT_I(15 downto 8)); end if; if ( (we_a0 and SEL_I(0)) = '1') then prer(7 downto 0) <= unsigned(DAT_I(7 downto 0)); end if; end if; end if; end process write_prer; -- control register write_ctr: process(nRESET, CLK_I) begin if (nRESET = '0') then ctr <= (others => '0'); elsif (CLK_I'event and CLK_I = '1') then if (RST_I = '1') then ctr <= (others => '0'); else if ( (we_a1 and SEL_I(0)) = '1') then ctr <= DAT_I(7 downto 0); end if; end if; end if; end process write_ctr; -- transmit register write_txr: process(nRESET, CLK_I) begin if (nRESET = '0') then txr <= (others => '0'); elsif (CLK_I'event and CLK_I = '1') then if (RST_I = '1') then txr <= (others => '0'); else if ( (we_a2 and SEL_I(1)) = '1') then txr <= DAT_I(15 downto 8); end if; end if; end if; end process write_txr; -- command register write_cr: process(nRESET, CLK_I) begin if (nRESET = '0') then cr <= (others => '0'); -- asynchronous clear elsif (CLK_I'event and CLK_I = '1') then if (RST_I = '1') then cr <= (others => '0'); -- synchronous clear else if ( (we_a2 and SEL_I(0)) = '1') then if (core_en = '1') then cr <= DAT_I(7 downto 0); -- only take new commands when I2C core is enabled, pending commands are finished end if; else if (done = '0') then cr(7 downto 4) <= cr(7 downto 4); else cr(7 downto 0) <= (others => '0'); -- clear command_bits when command completed end if; cr(2 downto 1) <= cr(2 downto 1); cr(0) <= cr(0) and irq_flag; -- automatically clear when irq_flag is cleared end if; end if; end if; end process write_cr; end block regs_block; -- decode command register sta <= cr(7); sto <= cr(6); rd <= cr(5); wr <= cr(4); ack <= cr(3); iack <= cr(0); -- decode control register core_en <= ctr(7); -- hookup byte controller block u1: byte_ctrl port map (clk => CLK_I, rst => RST_I, nReset => nRESET, clk_cnt => prer, ena => core_en, start => sta, stop => sto, read => rd, write => wr, ack_in => ack, i2c_busy => i2c_busy, Din => txr, cmd_ack => done, ack_out => irxack, Dout => rxr, -- note: maybe store rxr in registers ?? SCLi => SCLi, SCLo => SCLo, SDAi => SDAi, SDAo => SDAo); -- status register block + interrupt request signal st_block : block begin -- generate status register bits gen_sr_bits: process (CLK_I, nRESET) begin if (nRESET = '0') then rxack <= '0'; tip <= '0'; irq_flag <= '0'; elsif (CLK_I'event and CLK_I = '1') then if (RST_I = '1') then rxack <= '0'; tip <= '0'; irq_flag <= '0'; else rxack <= irxack; tip <= ( rd or wr ); irq_flag <= (done or irq_flag) and not iack; -- interrupt request flag is always generated end if; end if; end process gen_sr_bits; -- generate interrupt request signals gen_irq: process (CLK_I, nRESET) begin if (nRESET = '0') then INTA_O <= '0'; elsif (CLK_I'event and CLK_I = '1') then if (RST_I = '1') then INTA_O <= '0'; else INTA_O <= irq_flag and ctr(6); -- interrupt signal is only generated when IEN (interrupt enable bit) is set end if; end if; end process gen_irq; -- assign status register bits sr(7) <= rxack; sr(6) <= i2c_busy; sr(5 downto 2) <= (others => '0'); -- reserved sr(1) <= tip; sr(0) <= irq_flag; end block; end architecture structural; -- ------------------------------------------ -- Byte controller section ------------------------------------------ -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity byte_ctrl is port ( clk : in std_logic; rst : in std_logic; -- synchronous active high reset (WISHBONE compatible) nReset : in std_logic; -- asynchornous active low reset (FPGA compatible) clk_cnt : in unsigned(15 downto 0); -- 4x SCL -- input signals ena, start, stop, read, write, ack_in : std_logic; Din : in std_logic_vector(7 downto 0); -- output signals cmd_ack : out std_logic; ack_out : out std_logic; Dout : out std_logic_vector(7 downto 0); i2c_busy : out std_logic; -- i2c signals SCLi : in std_logic; -- I2C clock line SCLo : out std_logic; SDAi : in std_logic; -- I2C data line SDAo : out std_logic ); end entity byte_ctrl; architecture structural of byte_ctrl is component bit_ctrl is port ( clk : in std_logic; rst : in std_logic; nReset : in std_logic; clk_cnt : in unsigned(15 downto 0); -- clock prescale value ena : in std_logic; -- core enable signal cmd : in std_logic_vector(2 downto 0); cmd_ack : out std_logic; busy : out std_logic; Din : in std_logic; Dout : out std_logic; SCLin : in std_logic; -- I2C clock line SCLout : out std_logic; SDAin : in std_logic; -- I2C data line SDAout : out std_logic ); end component bit_ctrl; -- commands for i2c_core constant CMD_NOP : std_logic_vector(2 downto 0) := "000"; constant CMD_START : std_logic_vector(2 downto 0) := "010"; constant CMD_STOP : std_logic_vector(2 downto 0) := "011"; constant CMD_READ : std_logic_vector(2 downto 0) := "100"; constant CMD_WRITE : std_logic_vector(2 downto 0) := "101"; -- signals for bit_controller signal core_cmd : std_logic_vector(2 downto 0); signal core_ack, core_txd, core_rxd : std_logic; -- signals for shift register signal sr : std_logic_vector(7 downto 0); -- 8bit shift register signal shift, ld : std_logic; -- signals for state machine signal go, host_ack : std_logic; begin -- hookup bit_controller u1: bit_ctrl port map (clk, rst, nReset, clk_cnt, ena, core_cmd, core_ack, i2c_busy, core_txd, core_rxd, SCLi, SCLo, SDAi, SDAo); -- generate host-command-acknowledge cmd_ack <= host_ack; -- generate go-signal go <= (read or write) and not host_ack; -- assign Dout output to shift-register Dout <= sr; -- assign ack_out output to core_rxd (contains last received bit) ack_out <= core_rxd; -- generate shift register shift_register: process(clk) begin if (clk'event and clk = '1') then if (ld = '1') then sr <= din; elsif (shift = '1') then sr <= (sr(6 downto 0) & core_rxd); end if; end if; end process shift_register; -- -- state machine -- statemachine : block type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop); signal state : states; signal dcnt : unsigned(2 downto 0); begin -- -- command interpreter, translate complex commands into simpler I2C commands -- nxt_state_decoder: process(clk, nReset, state) variable nxt_state : states; variable idcnt : unsigned(2 downto 0); variable ihost_ack : std_logic; variable icore_cmd : std_logic_vector(2 downto 0); variable icore_txd : std_logic; variable ishift, iload : std_logic; begin -- 8 databits (1byte) of data to shift-in/out idcnt := dcnt; -- no acknowledge (until command complete) ihost_ack := '0'; icore_txd := core_txd; -- keep current command to bit_controller icore_cmd := core_cmd; -- no shifting or loading of shift-register ishift := '0'; iload := '0'; -- keep current state; nxt_state := state; case state is when st_idle => if (go = '1') then if (start = '1') then nxt_state := st_start; icore_cmd := CMD_START; elsif (read = '1') then nxt_state := st_read; icore_cmd := CMD_READ; idcnt := "111"; else nxt_state := st_write; icore_cmd := CMD_WRITE; idcnt := "111"; iload := '1'; end if; end if; when st_start => if (core_ack = '1') then if (read = '1') then nxt_state := st_read; icore_cmd := CMD_READ; idcnt := "111"; else nxt_state := st_write; icore_cmd := CMD_WRITE; idcnt := "111"; iload := '1'; end if; end if; when st_write => if (core_ack = '1') then idcnt := dcnt -1; -- count down Data_counter icore_txd := sr(7); if (dcnt = 0) then nxt_state := st_ack; icore_cmd := CMD_READ; else ishift := '1'; -- icore_txd := sr(7); end if; end if; when st_read => if (core_ack = '1') then idcnt := dcnt -1; -- count down Data_counter ishift := '1'; if (dcnt = 0) then nxt_state := st_ack; icore_cmd := CMD_WRITE; icore_txd := ack_in; end if; end if; when st_ack => if (core_ack = '1') then -- generate command acknowledge signal ihost_ack := '1'; -- Perform an additional shift, needed for 'read' (store last received bit in shift register) ishift := '1'; -- check for stop; Should a STOP command be generated ? if (stop = '1') then nxt_state := st_stop; icore_cmd := CMD_STOP; else nxt_state := st_idle; icore_cmd := CMD_NOP; end if; end if; when st_stop => if (core_ack = '1') then nxt_state := st_idle; icore_cmd := CMD_NOP; end if; when others => -- illegal states nxt_state := st_idle; icore_cmd := CMD_NOP; end case; -- generate registers if (nReset = '0') then core_cmd <= CMD_NOP; core_txd <= '0'; shift <= '0'; ld <= '0'; dcnt <= "111"; host_ack <= '0'; state <= st_idle; elsif (clk'event and clk = '1') then if (rst = '1') then core_cmd <= CMD_NOP; core_txd <= '0'; shift <= '0'; ld <= '0'; dcnt <= "111"; host_ack <= '0'; state <= st_idle; else state <= nxt_state; dcnt <= idcnt; shift <= ishift; ld <= iload; core_cmd <= icore_cmd; core_txd <= icore_txd; host_ack <= ihost_ack; end if; end if; end process nxt_state_decoder; end block statemachine; end architecture structural; -- ------------------------------------- -- Bit controller section ------------------------------------ -- -- Translate simple commands into SCL/SDA transitions -- Each command has 5 states, A/B/C/D/idle -- -- start: SCL ~~~~~~~~~~\____ -- SDA ~~~~~~~~\______ -- x | A | B | C | D | i -- -- repstart SCL ____/~~~~\___ -- SDA __/~~~\______ -- x | A | B | C | D | i -- -- stop SCL ____/~~~~~~~~ -- SDA ==\____/~~~~~ -- x | A | B | C | D | i -- --- write SCL ____/~~~~\____ -- SDA ==X=========X= -- x | A | B | C | D | i -- --- read SCL ____/~~~~\____ -- SDA XXXX=====XXXX -- x | A | B | C | D | i -- -- Timing: Normal mode Fast mode ----------------------------------------------------------------- -- Fscl 100KHz 400KHz -- Th_scl 4.0us 0.6us High period of SCL -- Tl_scl 4.7us 1.3us Low period of SCL -- Tsu:sta 4.7us 0.6us setup time for a repeated start condition -- Tsu:sto 4.0us 0.6us setup time for a stop conditon -- Tbuf 4.7us 1.3us Bus free time between a stop and start condition -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity bit_ctrl is port ( clk : in std_logic; rst : in std_logic; nReset : in std_logic; clk_cnt : in unsigned(15 downto 0); -- clock prescale value ena : in std_logic; -- core enable signal cmd : in std_logic_vector(2 downto 0); cmd_ack : out std_logic; busy : out std_logic; Din : in std_logic; Dout : out std_logic; -- i2c lines SCLin : in std_logic; -- I2C clock line SCLout : out std_logic; SDAin : in std_logic; -- I2C data line SDAout : out std_logic ); end entity bit_ctrl; architecture structural of bit_ctrl is constant CMD_NOP : std_logic_vector(2 downto 0) := "000"; constant CMD_START : std_logic_vector(2 downto 0) := "010"; constant CMD_STOP : std_logic_vector(2 downto 0) := "011"; constant CMD_READ : std_logic_vector(2 downto 0) := "100"; constant CMD_WRITE : std_logic_vector(2 downto 0) := "101"; type cmds is (idle, start_a, start_b, start_c, start_d, stop_a, stop_b, stop_c, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d); signal state : cmds; signal SCLo, SDAo : std_logic; -- internal I2C lines signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs signal txd : std_logic; -- transmit bit signal clk_en, slave_wait :std_logic; -- clock generation signals -- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation) signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis) begin -- synchronize SCL and SDA inputs synch_SCL_SDA: process(clk) begin if (clk'event and clk = '1') then sSCL <= SCLin; sSDA <= SDAin; end if; end process synch_SCL_SDA; -- whenever the slave is not ready it can delay the cycle by pulling SCL low slave_wait <= '1' when ( (SCLo = '1') and (sSCL = '0') ) else '0'; -- generate clk enable signal gen_clken: process(clk, nReset) begin if (nReset = '0') then cnt <= (others => '0'); clk_en <= '1'; elsif (clk'event and clk = '1') then if (rst = '1') then cnt <= (others => '0'); clk_en <= '1'; else if ( (cnt = 0) or (ena = '0') ) then clk_en <= '1'; cnt <= clk_cnt; else if (slave_wait = '0') then cnt <= cnt -1; end if; clk_en <= '0'; end if; end if; end if; end process gen_clken; -- generate bus status controller bus_status_ctrl: block signal dSDA : std_logic; signal sta_condition : std_logic; signal sto_condition : std_logic; signal ibusy : std_logic; begin -- detect start condition => detect falling edge on SDA while SCL is high -- detect stop condition => detect rising edge on SDA while SCL is high det_sta_sto: process(clk) begin if (clk'event and clk = '1') then dSDA <= sSDA; -- generate a delayed version of sSDA sta_condition <= (not sSDA and dSDA) and sSCL; sto_condition <= (sSDA and not dSDA) and sSCL; end if; end process det_sta_sto; -- generate bus busy signal gen_busy: process(clk, nReset) begin if (nReset = '0') then ibusy <= '0'; elsif (clk'event and clk = '1') then if (rst = '1') then ibusy <= '0'; else ibusy <= (sta_condition or ibusy) and not sto_condition; end if; end if; end process gen_busy; -- assign output busy <= ibusy; end block bus_status_ctrl; -- generate statemachine nxt_state_decoder : process (clk, nReset, state, cmd) variable nxt_state : cmds; variable icmd_ack, store_sda : std_logic; variable itxd : std_logic; begin nxt_state := state; icmd_ack := '0'; -- default no acknowledge store_sda := '0'; itxd := txd; case (state) is -- idle when idle => case cmd is when CMD_START => nxt_state := start_a; icmd_ack := '1'; -- command completed when CMD_STOP => nxt_state := stop_a; icmd_ack := '1'; -- command completed when CMD_WRITE => nxt_state := wr_a; icmd_ack := '1'; -- command completed itxd := Din; when CMD_READ => nxt_state := rd_a; icmd_ack := '1'; -- command completed when others => nxt_state := idle; -- don't acknowledge NOP command icmd_ack := '1'; -- command completed end case; -- start when start_a => nxt_state := start_b; when start_b => nxt_state := start_c; when start_c => nxt_state := start_d; when start_d => nxt_state := idle; -- stop when stop_a => nxt_state := stop_b; when stop_b => nxt_state := stop_c; when stop_c => nxt_state := idle; -- read when rd_a => nxt_state := rd_b; when rd_b => nxt_state := rd_c; when rd_c => nxt_state := rd_d; store_sda := '1'; when rd_d => nxt_state := idle; -- write when wr_a => nxt_state := wr_b; when wr_b => nxt_state := wr_c; when wr_c => nxt_state := wr_d; when wr_d => nxt_state := idle; end case; -- generate regs if (nReset = '0') then state <= idle; cmd_ack <= '0'; txd <= '0'; Dout <= '0'; elsif (clk'event and clk = '1') then if (rst = '1') then state <= idle; cmd_ack <= '0'; txd <= '0'; Dout <= '0'; else if (clk_en = '1') then state <= nxt_state; txd <= itxd; if (store_sda = '1') then Dout <= sSDA; end if; end if; cmd_ack <= icmd_ack and clk_en; end if; end if; end process nxt_state_decoder; -- -- convert states to SCL and SDA signals -- output_decoder: process (clk, nReset, state) variable iscl, isda : std_logic; begin case (state) is when idle => iscl := SCLo; -- keep SCL in same state isda := sSDA; -- keep SDA in same state -- start when start_a => iscl := SCLo; -- keep SCL in same state (for repeated start) isda := '1'; -- set SDA high when start_b => iscl := '1'; -- set SCL high isda := '1'; -- keep SDA high when start_c => iscl := '1'; -- keep SCL high isda := '0'; -- sel SDA low when start_d => iscl := '0'; -- set SCL low isda := '0'; -- keep SDA low -- stop when stop_a => iscl := '0'; -- keep SCL disabled isda := '0'; -- set SDA low when stop_b => iscl := '1'; -- set SCL high isda := '0'; -- keep SDA low when stop_c => iscl := '1'; -- keep SCL high isda := '1'; -- set SDA high -- write when wr_a => iscl := '0'; -- keep SCL low isda := Din; when wr_b => iscl := '1'; -- set SCL high isda := Din; when wr_c => iscl := '1'; -- keep SCL high isda := Din; when wr_d => iscl := '0'; -- set SCL low isda := Din; -- read when rd_a => iscl := '0'; -- keep SCL low isda := '1'; -- tri-state SDA when rd_b => iscl := '1'; -- set SCL high isda := '1'; -- tri-state SDA when rd_c => iscl := '1'; -- keep SCL high isda := '1'; -- tri-state SDA when rd_d => iscl := '0'; -- set SCL low isda := '1'; -- tri-state SDA end case; -- generate registers if (nReset = '0') then SCLo <= '1'; SDAo <= '1'; elsif (clk'event and clk = '1') then if (rst = '1') then SCLo <= '1'; SDAo <= '1'; else if (clk_en = '1') then SCLo <= iscl; SDAo <= isda; end if; end if; end if; end process output_decoder; -- assign outputs SCLout <= SCLo; SDAout <= SDAo; end architecture structural;