content stringlengths 1 1.04M ⌀ |
|---|
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 16, 2017
--! @brief Contains the entity and architecture of the
--! Wrapper Plasma-SoC Top Module.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.a... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LS is
Port ( x ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity new3phd is
Port (
clk: in STD_LOGIC;
pwmrefcnt: in STD_LOGIC_VECTOR(9 downto 0);
ibus: in STD_LOGIC_VECTOR (31 downto 0);
obus: out STD_LOGIC_VECTOR (31 downto 0);
writestb: i... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: input_serialiser
--
-- Description: A 5-bits per cycle SDR input serialiser
--
-- Maybe in the future the 'bitslip' funciton can be implemented.
----------... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: input_serialiser
--
-- Description: A 5-bits per cycle SDR input serialiser
--
-- Maybe in the future the 'bitslip' funciton can be implemented.
----------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fc_system_v4 is
port(
flight_no : in std_logic_vector(2 downto 0);
request: in std_logic;
reset,clk : in std_logic;
clk3_out,clk10_out : out std_logic;--For demo only
grant,denied: out std_logic
);
end fc_sys... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
entity scratch_pad is
port (
data_in1, data_in2 : in std_logic_vector(7 downto 0);
raddr_write1, raddr_write2 : in std_logic_vector(3 downto 0);
data_out : out std_logic_vector(7 downto 0);
raddr_read : ... |
package pack1 is
type my_int1 is range 0 to 10;
end package;
-------------------------------------------------------------------------------
package pack2 is
type my_int1 is range 0 to 10;
end package;
-------------------------------------------------------------------------------
use work.pack1;
use work.p... |
architecture RTL of FIFO is
begin
process
begin
-- These are passing
a :=
b or
d;
a :=
'0' when c = '0' else
'1' when d = '1' else
'Z';
-- Failing variations
a :=
b or
d;
a :=
'0' when c = '0' else
'1' when d = '1' else
'Z';... |
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.... |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:34:36 02/22/2016
-- Design Name:
-- Module Name: C:/Users/Arthur/Documents/FPGA_temp/serial_out/tb_uart.vhd
-- Project Name: serial_out
-- Target Device:
-- Tool versions:
-- Desc... |
-------------------------------------------------------------------------------
--! @project Serialized hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may... |
-------------------------------------------------------------------------------
-- Title : UART
-- Project : UART
-------------------------------------------------------------------------------
-- File : MiniUart.vhd
-- Author : Philippe CARTON
-- (philippe.carton2@libertysurf.fr)
-- ... |
-- NEED RESULT: ARCH00246: All formal modes and classes are allowed default classes tested passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
----------------------------------------... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that t... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_full_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 X... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_full_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 X... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_full_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 X... |
--
-- Parameterisable N to M mux.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use IEEE.numeric_std.all;
entity ParamExp is
generic(
BIT_TOP : integer := 20;
BIT_BO... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:27 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity assert4 is
end entity;
architecture test of assert4 is
begin
process is
variable n : integer;
begin
n := 0;
wait for 1 ns;
assert n = 0 report integer'image(100 / n);
wait;
end process;
end architecture;
|
entity assert4 is
end entity;
architecture test of assert4 is
begin
process is
variable n : integer;
begin
n := 0;
wait for 1 ns;
assert n = 0 report integer'image(100 / n);
wait;
end process;
end architecture;
|
entity assert4 is
end entity;
architecture test of assert4 is
begin
process is
variable n : integer;
begin
n := 0;
wait for 1 ns;
assert n = 0 report integer'image(100 / n);
wait;
end process;
end architecture;
|
entity assert4 is
end entity;
architecture test of assert4 is
begin
process is
variable n : integer;
begin
n := 0;
wait for 1 ns;
assert n = 0 report integer'image(100 / n);
wait;
end process;
end architecture;
|
entity assert4 is
end entity;
architecture test of assert4 is
begin
process is
variable n : integer;
begin
n := 0;
wait for 1 ns;
assert n = 0 report integer'image(100 / n);
wait;
end process;
end architecture;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
entity ent is
end entity;
library ieee;
use ieee.std_logic_1164.all;
package avmm_csr_pkg is
type avmm_csr_array_t is array (natural range <>) of std_logic_vector(31 downto 0);
end avmm_csr_pkg;
library ieee;
use work.avmm_csr_pkg.all;
entity avmm_csr is
Port (
reg_i : in avmm_csr_array_t
);
end avmm_csr;
... |
-- ########################################################################
-- $Software: busiac
-- $section : hardware component
-- $Id: plus12.vhd 325 2015-06-03 12:47:32Z ia $
-- $HeadURL: svn://lunix120.ensiie.fr/ia/cours/archi/projet/busiac/vhdl/plus12.vhd $
-- $Author : Ivan Auge (Email: auge@ensiie.fr)
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:52:30 04/03/2013
-- Design Name:
-- Module Name: muxx - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision: ... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/FFT_HDL_Optimized.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ------------------------------------------... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This... |
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.VITAL_Primitives.all;
entity servo_pwm_tb is
end servo_pwm_tb;
architecture behavior of servo_pwm_tb is
component servo_pwm
port(
clk : in std_logic;
reset_n : in std_logic;
coe_servo : out std_logic;
avs_s0_writ... |
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.VITAL_Primitives.all;
entity servo_pwm_tb is
end servo_pwm_tb;
architecture behavior of servo_pwm_tb is
component servo_pwm
port(
clk : in std_logic;
reset_n : in std_logic;
coe_servo : out std_logic;
avs_s0_writ... |
library ieee;
use ieee.std_logic_1164.all,
ieee.numeric_std.all;
entity tdp_ram is
generic (
ADDRWIDTH : positive := 7;
WIDTH : positive := 8
);
port (
clk_a : in std_logic;
read_a : in std_logic;
write_a : in std_logic;
addr_a ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Sparcv8Monocycle is
end Sparcv8Monocycle;
architecture Behavioral of Sparcv8Monocycle is
begin
end Behavioral; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity CounterLoadUpDown4 is
port( clk : in std_logic;
updown: in std_logic;
reset : in std_logic;
enable: in std_logic;
load : in std_logic;
dataIn: in std_logic_vector(3 downto 0);
count : out std_logic_vector(3 downto 0));
end ... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity CounterLoadUpDown4 is
port( clk : in std_logic;
updown: in std_logic;
reset : in std_logic;
enable: in std_logic;
load : in std_logic;
dataIn: in std_logic_vector(3 downto 0);
count : out std_logic_vector(3 downto 0));
end ... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity CounterLoadUpDown4 is
port( clk : in std_logic;
updown: in std_logic;
reset : in std_logic;
enable: in std_logic;
load : in std_logic;
dataIn: in std_logic_vector(3 downto 0);
count : out std_logic_vector(3 downto 0));
end ... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Ve... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.MATH_REAL.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : E X T R A C T O B S E R V A T I O N
--
--
-- The user functi... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- #############################################################################
-- DE0_Nano_TRDB_D5M_LT24_top_level.vhd
-- ====================================
--
-- BOARD : DE0-Nano from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.5
-- Last updated : 2017-06-11 12:48:26 UTC
-... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
use Std.Textio.all;
library IEEE;
use ieee.std_logic_1164.ALL;
entity test_divider is
end;
architecture test_divider of test_divider is
component c_divider
generic(width : INTEGER ; const :INTEGER
);
port(Input: in std_logic_vector((width - 1) downto 0);
Output : out std_logic_vector((width... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Package: ... |
divisor2_inst : divisor2 PORT MAP (
clock => clock_sig,
cout => cout_sig,
q => q_sig
);
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_comps_info_dc_tbl_no is
port (
wa0_data : in std_logic;
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic;
wa0_en : in ... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_comps_info_dc_tbl_no is
port (
wa0_data : in std_logic;
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic;
wa0_en : in ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity array1 is
end entity;
architecture test of array1 is
type matrix_t is array (integer range <>, integer range <>) of integer;
constant c : matrix_t(0 to 1, 0 to 1) := (
( 1, 2 ),
( 3, 4 ) );
begin
process is
variable m : matrix_t(1 to 3, 1 to 3) := (
( 1, 2, 3 ),... |
--!
--! Copyright (C) 2010 - 2013 Creonic GmbH
--!
--! @file: periodic_stimuli.vhd
--! @brief: write and simulate a vhdl code that generates the signs sig1 and sig2 and signal y
--! @author: Antonio Gutierrez
--! @date: 2014-04-01
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all... |
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This ... |
--!
--! Copyright 2019 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(Packet_length, source, destination, packet_id: integ... |
entity case13 is
end entity;
architecture test of case13 is
function get_bits (n : natural; b : bit) return bit_vector is
variable v : bit_vector(1 to n);
begin
v := (others => b);
return v;
end function;
signal n : natural := 3;
signal b : bit;
begin
p1: process (n, ... |
-- NEED RESULT: ARCH00657: Multiple interface declarations in correct order passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:04:21 05/02/2016
-- Design Name:
-- Module Name: contatore_4_cifre - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later ver... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity func21 is
end entity;
architecture test of func21 is
type rec is record
x, y : integer;
end record;
function func (r : rec) return integer is
begin
return r.x + r.y;
end function;
begin
p1: process is
variable a, b : integer;
begin
assert func(r.x =>... |
-- Test case from Brian Padalino
--
library ieee ;
use ieee.std_logic_1164.all ;
package pack is
type iface_t is record
cs : std_logic ;
addr : std_logic_vector ;
rdata : std_logic_vector ;
wdata : std_logic_vector ;
end record ;
function init_iface_sig... |
entity ent is
port (
i : in bit
);
end ent;
architecture a of ent is
begin
end;
|
-- -a --ieee=synopsis -fexplicit -Wc,-m32 -Wa,--32
-- -e -Wa,--32 -Wl,-m32
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dmem is
port (a: in std_logic_vector(31 downto 0);
wd: in std_logic_vector(31 downto 0);
clk, we: in bit;
rd: out std_logic_vector... |
----
-- This file is part of etip-ss11-g07.
--
-- Copyright (C) 2011 Lukas Märdian <lukasmaerdian@gmail.com>
-- Copyright (C) 2011 M. S.
-- Copyright (C) 2011 Orest Tarasiuk <orest.tarasiuk@tum.de>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the G... |
use std.textio.all;
package broken_module is
type prot_t is protected
procedure proc;
end protected;
end package;
package body broken_module is
type prot_t is protected body
variable var : natural := 0;
procedure file_proc is
file fwrite : text;
begin
file_open(fwrite, "ou... |
use std.textio.all;
package broken_module is
type prot_t is protected
procedure proc;
end protected;
end package;
package body broken_module is
type prot_t is protected body
variable var : natural := 0;
procedure file_proc is
file fwrite : text;
begin
file_open(fwrite, "ou... |
use std.textio.all;
package broken_module is
type prot_t is protected
procedure proc;
end protected;
end package;
package body broken_module is
type prot_t is protected body
variable var : natural := 0;
procedure file_proc is
file fwrite : text;
begin
file_open(fwrite, "ou... |
use std.textio.all;
package broken_module is
type prot_t is protected
procedure proc;
end protected;
end package;
package body broken_module is
type prot_t is protected body
variable var : natural := 0;
procedure file_proc is
file fwrite : text;
begin
file_open(fwrite, "ou... |
architecture RTL of FIFO is
signal sig1 : std_logic_vector(31 downto 0);
signal sig2 : std_logic_vector( 3 downto 0);
signal sig3 : std_logic_vector(c_width downto 0);
-- Violations
signal sig1 : std_logic_vector( 31 downto 0);
signal sig2 : std_logic_vector(3 downto 0);
signal sig3 : std_logic_vector... |
Library ieee;
Use ieee.std_logic_1164.all;
Entity nreg is
Generic ( n : integer := 16);
port( Clk,Rst,enable : in std_logic;
d : in std_logic_vector(n-1 downto 0);
q : out std_logic_vector(n-1 downto 0));
end nreg;
Architecture arch_nreg of nreg is
begin
Process (Clk,Rst)
begin
if Rst = '1' then
q <= (others=>'0');
e... |
--
-- WISHBONE revB2 compiant I2C master core
--
-- author: Richard Herveille
-- rev. 0.1 based on simple_i2c
-- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman)
-- rev. 0.3 may 4th 2001, fixed typo rev.0.2 txt -> txr
-- rev. 0.4 may 8th, added some remarks, fix... |
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