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|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2462.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02462ent IS
END c07s03b02x02p03n02i02462ent;
ARCHITECTURE c07s03b02x02p03n02i02462arch OF c07s03b02x02p03n02i02462ent IS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 3 );
type AGGREGATE_ARRAY is array (1 to 2) of CONSTRAINED_ARRAY;
signal V, W : CONSTRAINED_ARRAY;
BEGIN
TESTING: PROCESS
BEGIN
(W,V) <= (AGGREGATE_ARRAY'((others => '$'),( others => '$' )));
wait for 1 ns;
assert NOT( V(1)='$' and V(2)='$' and V(3)='$' and W=(('$','$','$')))
report "***PASSED TEST: c07s03b02x02p03n02i02462"
severity NOTE;
assert ( V(1)='$' and V(2)='$' and V(3)='$' and W=(('$','$','$')))
report "***FAILED TEST: c07s03b02x02p03n02i02462 - An array aggregate with an others choice may appear as a value expression in an assignment statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02462arch;
|
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Default definitions
--
-- Dependencies: -
-- Tool versions: xst 8.1-14.7; viv 2014.4-2018.2; ghdl 0.18-0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-09-22 1051 1.1.3 add missing config's
-- 2016-05-28 770 1.1.2 sys_conf_mem_losize now type natural
-- 2015-06-26 695 1.1.1 add sys_conf_dmscnt
-- 2015-05-01 672 1.1 adopt to pdp11_sys70
-- 2008-02-23 118 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache
constant sys_conf_bram_awidth : integer := 15; -- 32 kB BRAM
constant sys_conf_mem_losize : natural := 8#000777#;-- 32 kByte
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon
constant sys_conf_dmscnt : boolean := true;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable, 8 to use
end package sys_conf;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.15:39:22)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY jpegsd_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4));
END jpegsd_asap_entity;
ARCHITECTURE jpegsd_asap_description OF jpegsd_asap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register13: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register14: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register15: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register16: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := ((NOT input1) + 1) XOR input1;
register2 := input2 + 2;
register3 := input3 + 3;
register4 := input4 + 4;
register5 := input5 + 5;
register6 := input6 + 6;
output1 <= input7 + 7;
output2 <= input8 + 8;
register7 := ((NOT input9) + 1) XOR input9;
register8 := input10 + 10;
register9 := input11 + 11;
register10 := input12 + 12;
register11 := input13 + 13;
register12 := input14 + 14;
register13 := ((NOT input15) + 1) XOR input15;
register14 := ((NOT input16) + 1) XOR input16;
register15 := input17 + 17;
register16 := input18 + 18;
WHEN "00000010" =>
register2 := ((NOT register2) + 1) XOR register2;
register3 := ((NOT register3) + 1) XOR register3;
register4 := ((NOT register4) + 1) XOR register4;
register5 := ((NOT register5) + 1) XOR register5;
register6 := ((NOT register6) + 1) XOR register6;
register8 := ((NOT register8) + 1) XOR register8;
register9 := ((NOT register9) + 1) XOR register9;
register10 := ((NOT register10) + 1) XOR register10;
register11 := ((NOT register11) + 1) XOR register11;
register12 := ((NOT register12) + 1) XOR register12;
register15 := ((NOT register15) + 1) XOR register15;
register16 := ((NOT register16) + 1) XOR register16;
WHEN "00000011" =>
register2 := register8 + register2;
register3 := register7 + register3;
register1 := register1 + register12;
WHEN "00000100" =>
register2 := register2 + register16;
register3 := register3 + register14;
register1 := register1 + register13;
WHEN "00000101" =>
register2 := register2 + register15;
register3 := register3 + register10;
register1 := register1 + register4;
WHEN "00000110" =>
register3 := register3 + register5;
register4 := register1 * 44;
WHEN "00000111" =>
register3 := register3 + register9;
WHEN "00001000" =>
register3 := register3 + register11;
WHEN "00001001" =>
register3 := register3 + register6;
WHEN "00001010" =>
register5 := register3 + 46;
WHEN "00001011" =>
register2 := register3 + register5 + register2;
WHEN "00001100" =>
register2 := register3 * register5 * register2;
WHEN "00001101" =>
register2 := register4 + register2;
WHEN "00001110" =>
register1 := register1 + register2;
WHEN "00001111" =>
register1 := register1 srl 48;
WHEN "00010000" =>
output3 <= register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END jpegsd_asap_description; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity offset_adjust is
port(
ramp_in: in std_logic_vector(11 downto 0);
ramp_out: out std_logic_vector(11 downto 0);
adjust: in std_logic_vector(11 downto 0)
);
end offset_adjust;
architecture Behavioral of offset_adjust is
begin
ramp_out <= std_logic_vector(unsigned(ramp_in) + unsigned(adjust));
end Behavioral;
|
package pack is
function add4(x : in integer) return integer;
function add1(x : in integer) return integer;
function log2(x : in integer) return integer;
function case1(x : in integer) return integer;
function adddef(x, y : in integer := 5) return integer;
function chain1(x : string) return boolean;
function chain2(x, y : string) return boolean;
function flip(x : bit_vector(3 downto 0)) return bit_vector;
type real_vector is array (natural range <>) of real;
function lookup(index : integer) return real;
function get_bitvec(x, y : integer) return bit_vector;
function approx(x, y : real; t : real := 0.001) return boolean;
function get_string(x : integer) return string;
function get_string(x : real) return string;
function get_string(x : character) return string;
function get_string(x : time) return string;
function needs_heap(x : integer) return integer;
function sum_left_right(x : bit_vector) return integer;
procedure p5(x : in integer; y : out integer);
function call_proc(x : in integer) return integer;
type rec is record
x : bit_vector(1 to 3);
y : integer;
end record;
function make_rec(x : bit_vector(1 to 3); y : integer) return rec;
function min(x, y : integer) return integer;
function get_left(x : bit_vector) return bit;
function test_alloc_proc(a, b, c : string) return boolean;
function test_logic(x, y : bit) return bit;
function test_div(x, y : integer) return integer;
end package;
package body pack is
function add4(x : in integer) return integer is
begin
return x + 4;
end function;
function add1(x : in integer) return integer is
begin
return x + 1;
end function;
function log2(x : in integer) return integer is
variable r : integer := 0;
variable c : integer := 1;
begin
--while true loop
--end loop;
if x <= 1 then
r := 1;
else
while c < x loop
r := r + 1;
c := c * 2;
end loop;
end if;
return r;
end function;
function case1(x : in integer) return integer is
begin
case x is
when 1 =>
return 2;
when 2 =>
return 3;
when others =>
return 5;
end case;
end function;
function adddef(x, y : in integer := 5) return integer is
begin
return x + y;
end function;
function chain1(x : string) return boolean is
variable r : boolean := false;
begin
if x = "hello" then
r := true;
end if;
return r;
end function;
function chain2(x, y : string) return boolean is
variable r : boolean := false;
begin
if chain1(x) or chain1(y) then
r := true;
end if;
return r;
end function;
function flip(x : bit_vector(3 downto 0)) return bit_vector is
variable r : bit_vector(3 downto 0);
begin
r(0) := x(3);
r(1) := x(2);
r(2) := x(1);
r(3) := x(0);
return r;
end function;
function lookup(index : integer) return real is
constant table : real_vector := (
0.62, 61.62, 71.7, 17.25, 26.15, 651.6, 0.45, 5.761 );
begin
return table(index);
end function;
function get_bitvec(x, y : integer) return bit_vector is
variable r : bit_vector(x to y) := "00";
begin
return r;
end function;
function approx(x, y : real; t : real := 0.001) return boolean is
begin
return abs(x - y) < t;
end function;
function get_string(x : integer) return string is
begin
return integer'image(x);
end function;
function get_string(x : real) return string is
begin
return real'image(x);
end function;
function get_string(x : character) return string is
begin
return character'image(x);
end function;
function get_string(x : time) return string is
begin
return time'image(x);
end function;
function needs_heap(x : integer) return integer is
begin
if integer'image(x)'length = 2 then
return x * 2;
else
return x / 2;
end if;
end function;
function sum_left_right(x : bit_vector) return integer is
begin
return x'left + x'right;
end function;
procedure p5(x : in integer; y : out integer) is
variable k : integer := x + 1;
begin
y := k;
end procedure;
function call_proc(x : in integer) return integer is
variable y : integer;
begin
p5(x, y);
return y;
end function;
function make_rec(x : bit_vector(1 to 3); y : integer) return rec is
variable r : rec;
begin
r.x := x;
r.y := y;
return r;
end function;
function min(x, y : integer) return integer is
begin
if x > y then
return y;
else
return x;
end if;
end function;
function get_left(x : bit_vector) return bit is
constant l : integer := x'left;
variable v : bit_vector(1 to x'right);
constant m : integer := min(x'length, v'length) + 1;
begin
return x(l);
end function;
type line is access string;
procedure cat_str(x : inout line; s : in string) is
variable tmp : line := x;
variable len : integer := 0;
begin
if x /= null then
len := x.all'length;
end if;
x := new string(1 to s'length + len);
if tmp /= null then
x.all(1 to len) := tmp.all;
end if;
x.all(1 + len to s'length + len) := s;
if tmp /= null then
deallocate(tmp);
end if;
end procedure;
function test_alloc_proc(a, b, c : string) return boolean is
variable l : line;
variable r : boolean;
begin
cat_str(l, a);
cat_str(l, b);
r := l.all = c;
deallocate(l);
return r;
end function;
function test_logic(x, y : bit) return bit is
begin
return (x and y) xor (x or y) xor (x nand y)
xor (x nor y) xor (x xnor y);
end function;
function test_div(x, y : integer) return integer is
begin
return x / y; -- Need to evaluate zero check
end function;
end package body;
-------------------------------------------------------------------------------
entity ffold is
end entity;
use work.pack.all;
architecture a of ffold is
begin
b1: block is
signal s0 : integer := add1(5);
signal s1 : integer := add4(1);
signal s2 : integer := log2(11);
signal s3 : integer := log2(integer(real'(5.5)));
signal s4 : integer := case1(1);
signal s5 : integer := case1(7);
signal s6 : integer := adddef;
signal s7 : boolean := chain2("foo", "hello");
signal s8 : boolean := flip("1010") = "0101";
signal s9 : boolean := flip("1010") = "0111";
signal s10 : real := lookup(0); -- 0.62;
signal s11 : real := lookup(2); -- 71.7;
signal s12 : boolean := get_bitvec(1, 2) = "00";
signal s13 : boolean := approx(1.0000, 1.0001);
signal s14 : boolean := approx(1.0000, 1.01);
signal s15 : boolean := get_string(5) = "5";
signal s16 : boolean := get_string(2.5) = "2.5";
signal s17 : boolean := get_string('F') = "'F'";
signal s18 : boolean := get_string(1 fs) = "1 fs";
signal s19 : integer := needs_heap(40);
signal s20 : integer := sum_left_right("101010");
signal s21 : integer := call_proc(1);
signal s22 : boolean := make_rec("010", 20).y = 20;
signal s23 : boolean := get_left("1010") = '1';
signal s24 : boolean := make_rec("010", 4).x = "010";
signal s25 : boolean := test_alloc_proc("hello", "world", "helloworld");
signal s26 : boolean := test_alloc_proc("hello", "moo", "hellomoowee");
signal s27 : bit := test_logic('1', '0');
signal s28 : integer := test_div(5, 2);
begin
end block;
end architecture;
|
library verilog;
use verilog.vl_types.all;
entity rotate_shift_register_vlg_sample_tst is
port(
clk : in vl_logic;
reset : in vl_logic;
sampler_tx : out vl_logic
);
end rotate_shift_register_vlg_sample_tst;
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_cast is
end entity alt_dspbuilder_cast;
architecture rtl of alt_dspbuilder_cast is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_cast is
end entity alt_dspbuilder_cast;
architecture rtl of alt_dspbuilder_cast is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_cast is
end entity alt_dspbuilder_cast;
architecture rtl of alt_dspbuilder_cast is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_cast is
end entity alt_dspbuilder_cast;
architecture rtl of alt_dspbuilder_cast is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_cast is
end entity alt_dspbuilder_cast;
architecture rtl of alt_dspbuilder_cast is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_cast is
end entity alt_dspbuilder_cast;
architecture rtl of alt_dspbuilder_cast is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_cast is
end entity alt_dspbuilder_cast;
architecture rtl of alt_dspbuilder_cast is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_cast is
end entity alt_dspbuilder_cast;
architecture rtl of alt_dspbuilder_cast is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_cast is
end entity alt_dspbuilder_cast;
architecture rtl of alt_dspbuilder_cast is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_cast is
end entity alt_dspbuilder_cast;
architecture rtl of alt_dspbuilder_cast is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_601 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_601;
architecture augh of add_601 is
signal carry_inA : std_logic_vector(28 downto 0);
signal carry_inB : std_logic_vector(28 downto 0);
signal carry_res : std_logic_vector(28 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(27 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_601 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_601;
architecture augh of add_601 is
signal carry_inA : std_logic_vector(28 downto 0);
signal carry_inB : std_logic_vector(28 downto 0);
signal carry_res : std_logic_vector(28 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(27 downto 1);
end architecture;
|
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
-- ZyEHW is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ZyEHW. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use work.zyehw_pkg.all;
entity image_window is
port (
clk: in std_logic;
en: in std_logic;
input: in cgp_t;
redundant_kernel_pixels: out cgp_input_redundant_t
);
end image_window;
architecture behav_image_window of image_window is
signal serial_img: serial_img_t;
signal tmp_pixels: cgp_input_redundant_t;
-- The don_touch attribute should be on the signal which is duplicated
-- into redundant registers. However cannot be placed on the inner
-- registers because the synthesizer would add weird proxy LUTs.
-- Therefore, an individual registered temporary signal should be used.
attribute dont_touch: string;
attribute dont_touch of tmp_pixels: signal is "true";
begin
process (clk)
begin
if clk'event and clk = '1' then
if en = '1' then
serial_img(0) <= input;
for i in 1 to (serial_img_t'length-1) loop
serial_img(i) <= serial_img(i-1);
end loop;
-- This will generate the actual redundant registers
redundant_kernel_pixels <= tmp_pixels;
end if;
end if;
end process;
-- We generate a temporary signal which is a predecessor of the output
-- register.
kernel_row: for i in 0 to (img_kernel-1) generate
kernel_column: for j in 0 to (img_kernel-1) generate
constant src_ind: integer:= serial_img_t'length-1-j-i*img_size;
constant dst_ind: integer:= j+i*img_kernel;
begin
kernel_redundant: for k in tmp_pixels'range generate
redund_from_input: if src_ind = 0 generate
tmp_pixels(k)(dst_ind) <= input;
-- because previously this was used:
-- serial_img(0) <= input;
end generate;
other_redundats: if src_ind > 0 generate
tmp_pixels(k)(dst_ind) <= serial_img(src_ind - 1);
-- minus one because serial_image is generated
-- like this: serial_img(i) <= serial_img(i-1)
end generate;
end generate;
end generate;
end generate;
end behav_image_window;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library vunit_lib;
context vunit_lib.vunit_context;
context vunit_lib.vc_context;
library src;
use src.bus_pkg.all;
entity bus_pkg_tb is
generic (
runner_cfg : string);
end entity;
architecture tb of bus_pkg_tb is
begin
main : process
begin
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("Bus pkg sanity") then
CHECK(bus_data_width_log2b >= bus_byte_size_log2b);
CHECK(bus_address_type'length = 2**bus_address_width_log2b);
CHECK(bus_data_type'length = 2**bus_data_width_log2b);
end if;
end loop;
test_runner_cleanup(runner);
wait;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc732.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x00p04n01i00732ent IS
-- A basic entity with a port
port ( signal s : bit) --Failure_here
END c01s01b01x00p04n01i00732ent;
ARCHITECTURE c01s01b01x00p04n01i00732arch OF c01s01b01x00p04n01i00732ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x00p04n01i00732 - Missing semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x00p04n01i00732arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc732.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x00p04n01i00732ent IS
-- A basic entity with a port
port ( signal s : bit) --Failure_here
END c01s01b01x00p04n01i00732ent;
ARCHITECTURE c01s01b01x00p04n01i00732arch OF c01s01b01x00p04n01i00732ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x00p04n01i00732 - Missing semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x00p04n01i00732arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc732.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x00p04n01i00732ent IS
-- A basic entity with a port
port ( signal s : bit) --Failure_here
END c01s01b01x00p04n01i00732ent;
ARCHITECTURE c01s01b01x00p04n01i00732arch OF c01s01b01x00p04n01i00732ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x00p04n01i00732 - Missing semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x00p04n01i00732arch;
|
library ieee;
use ieee.std_logic_1164.all;
-- a goes through with s = '1', b with s = '0'
entity mux21 is
generic(
NBIT : integer := 32
);
Port (
a: in std_logic_vector(NBIT - 1 downto 0);
b: in std_logic_vector(NBIT - 1 downto 0);
s: in std_logic;
y: out std_logic_vector(NBIT - 1 downto 0)
);
end mux21;
architecture beh of mux21 is
begin
y <= a when S='1' else b;
end beh;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity static_debouncer is
generic (
debounce_ticks : natural range 1 to natural'high
);
port (
clk : in STD_LOGIC;
pulse_in : in STD_LOGIC;
pulse_out : out STD_LOGIC
);
end static_debouncer;
architecture behavioral of static_debouncer is
type state_type is (start, wait_for_edge_change, wait_for_debounce);
signal state : state_type := start;
signal read_input : boolean;
signal counter_rst : boolean;
signal counter_run : boolean;
signal counter_done : boolean;
signal output_signal : std_logic;
signal cur_different : boolean;
signal difference_detected : boolean;
signal detector_rst : boolean;
begin
cur_different <= output_signal /= pulse_in;
pulse_out <= output_signal;
difference_detector : process(cur_different, detector_rst)
variable d : boolean;
begin
if detector_rst then
d := false;
elsif cur_different then
d := true;
end if;
difference_detected <= d;
end process;
rising_edge_counter : process(clk, counter_rst, counter_run)
variable cur_count : natural range 0 to natural'high;
variable count_done : boolean;
begin
if counter_rst then
cur_count := 0;
count_done := false;
elsif rising_edge(clk) and counter_run then
cur_count := cur_count + 1;
end if;
if cur_count = (debounce_ticks - 1) then
count_done := true;
end if;
counter_done <= count_done;
end process;
output_control : process(clk, read_input)
variable cur_output : std_logic;
begin
if rising_edge(clk) and read_input then
cur_output := pulse_in;
end if;
output_signal <= cur_output;
end process;
state_selector : process(clk)
begin
if rising_edge(clk) then
case state is
when start =>
state <= wait_for_edge_change;
when wait_for_edge_change =>
if difference_detected then
state <= wait_for_debounce;
else
state <= wait_for_edge_change;
end if;
when wait_for_debounce =>
if counter_done then
state <= wait_for_edge_change;
else
state <= wait_for_debounce;
end if;
end case;
end if;
end process;
state_output : process(state, counter_done, cur_different)
begin
case state is
when start =>
read_input <= true;
counter_rst <= true;
counter_run <= false;
detector_rst <= true;
when wait_for_edge_change =>
read_input <= false;
counter_rst <= true;
counter_run <= false;
detector_rst <= false;
when wait_for_debounce =>
if (counter_done and cur_different) then
read_input <= true;
else
read_input <= false;
end if;
counter_rst <= false;
counter_run <= true;
detector_rst <= true;
end case;
end process;
end behavioral;
|
-- -------------------------------------------------------------------------
-- High Level Design Compiler for Intel(R) FPGAs Version 17.0 (Release Build #595)
-- Quartus Prime development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly
-- subject to the terms and conditions of the Intel FPGA Software License
-- Agreement, Intel MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by Intel
-- and sold by Intel or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- ---------------------------------------------------------------------------
-- VHDL created from fp_mul_0002
-- VHDL created on Thu Feb 15 13:10:22 2018
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_mul_0002 is
port (
a : in std_logic_vector(31 downto 0); -- float32_m23
b : in std_logic_vector(31 downto 0); -- float32_m23
q : out std_logic_vector(31 downto 0); -- float32_m23
clk : in std_logic;
areset : in std_logic
);
end fp_mul_0002;
architecture normal of fp_mul_0002 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007";
signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
signal VCC_q : STD_LOGIC_VECTOR (0 downto 0);
signal expX_uid6_fpMulTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal expY_uid7_fpMulTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal signX_uid8_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal signY_uid9_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal cstAllOWE_uid10_fpMulTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal cstZeroWF_uid11_fpMulTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal cstAllZWE_uid12_fpMulTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal frac_x_uid14_fpMulTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal excZ_x_uid15_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal excZ_x_uid15_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid16_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid16_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid17_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid17_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid18_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excI_x_uid19_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_x_uid20_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid21_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid22_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excR_x_uid23_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal frac_y_uid28_fpMulTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal excZ_y_uid29_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal excZ_y_uid29_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid30_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid30_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid31_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid31_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid32_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excI_y_uid33_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_y_uid34_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid35_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid36_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excR_y_uid37_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal ofracX_uid40_fpMulTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal ofracY_uid43_fpMulTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal expSum_uid44_fpMulTest_a : STD_LOGIC_VECTOR (8 downto 0);
signal expSum_uid44_fpMulTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal expSum_uid44_fpMulTest_o : STD_LOGIC_VECTOR (8 downto 0);
signal expSum_uid44_fpMulTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal biasInc_uid45_fpMulTest_q : STD_LOGIC_VECTOR (9 downto 0);
signal expSumMBias_uid46_fpMulTest_a : STD_LOGIC_VECTOR (11 downto 0);
signal expSumMBias_uid46_fpMulTest_b : STD_LOGIC_VECTOR (11 downto 0);
signal expSumMBias_uid46_fpMulTest_o : STD_LOGIC_VECTOR (11 downto 0);
signal expSumMBias_uid46_fpMulTest_q : STD_LOGIC_VECTOR (10 downto 0);
signal signR_uid48_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal signR_uid48_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal normalizeBit_uid49_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal fracRPostNormHigh_uid51_fpMulTest_in : STD_LOGIC_VECTOR (25 downto 0);
signal fracRPostNormHigh_uid51_fpMulTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal fracRPostNormLow_uid52_fpMulTest_in : STD_LOGIC_VECTOR (24 downto 0);
signal fracRPostNormLow_uid52_fpMulTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal fracRPostNorm_uid53_fpMulTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal fracRPostNorm_uid53_fpMulTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal expFracPreRound_uid55_fpMulTest_q : STD_LOGIC_VECTOR (34 downto 0);
signal roundBitAndNormalizationOp_uid57_fpMulTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal expFracRPostRounding_uid58_fpMulTest_a : STD_LOGIC_VECTOR (36 downto 0);
signal expFracRPostRounding_uid58_fpMulTest_b : STD_LOGIC_VECTOR (36 downto 0);
signal expFracRPostRounding_uid58_fpMulTest_o : STD_LOGIC_VECTOR (36 downto 0);
signal expFracRPostRounding_uid58_fpMulTest_q : STD_LOGIC_VECTOR (35 downto 0);
signal fracRPreExc_uid59_fpMulTest_in : STD_LOGIC_VECTOR (23 downto 0);
signal fracRPreExc_uid59_fpMulTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal expRPreExcExt_uid60_fpMulTest_b : STD_LOGIC_VECTOR (11 downto 0);
signal expRPreExc_uid61_fpMulTest_in : STD_LOGIC_VECTOR (7 downto 0);
signal expRPreExc_uid61_fpMulTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal expUdf_uid62_fpMulTest_a : STD_LOGIC_VECTOR (13 downto 0);
signal expUdf_uid62_fpMulTest_b : STD_LOGIC_VECTOR (13 downto 0);
signal expUdf_uid62_fpMulTest_o : STD_LOGIC_VECTOR (13 downto 0);
signal expUdf_uid62_fpMulTest_n : STD_LOGIC_VECTOR (0 downto 0);
signal expOvf_uid64_fpMulTest_a : STD_LOGIC_VECTOR (13 downto 0);
signal expOvf_uid64_fpMulTest_b : STD_LOGIC_VECTOR (13 downto 0);
signal expOvf_uid64_fpMulTest_o : STD_LOGIC_VECTOR (13 downto 0);
signal expOvf_uid64_fpMulTest_n : STD_LOGIC_VECTOR (0 downto 0);
signal excXZAndExcYZ_uid65_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXZAndExcYR_uid66_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excYZAndExcXR_uid67_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excZC3_uid68_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRZero_uid69_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXIAndExcYI_uid70_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXRAndExcYI_uid71_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excYRAndExcXI_uid72_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal ExcROvfAndInReg_uid73_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRInf_uid74_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excYZAndExcXI_uid75_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXZAndExcYI_uid76_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal ZeroTimesInf_uid77_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRNaN_uid78_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal concExc_uid79_fpMulTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal excREnc_uid80_fpMulTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal oneFracRPostExc2_uid81_fpMulTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal fracRPostExc_uid84_fpMulTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal fracRPostExc_uid84_fpMulTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal expRPostExc_uid89_fpMulTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal expRPostExc_uid89_fpMulTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal invExcRNaN_uid90_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signRPostExc_uid91_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal R_uid92_fpMulTest_q : STD_LOGIC_VECTOR (31 downto 0);
signal topRangeX_uid102_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (17 downto 0);
signal topRangeY_uid103_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (17 downto 0);
signal aboveLeftX_uid108_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal aboveLeftY_bottomExtension_uid109_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal aboveLeftY_bottomRange_uid110_prod_uid47_fpMulTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal aboveLeftY_bottomRange_uid110_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (5 downto 0);
signal aboveLeftY_mergedSignalTM_uid111_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal rightBottomX_bottomRange_uid114_prod_uid47_fpMulTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal rightBottomX_bottomRange_uid114_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (5 downto 0);
signal rightBottomX_mergedSignalTM_uid115_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal rightBottomY_uid117_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal rightBottomX_uid121_prod_uid47_fpMulTest_in : STD_LOGIC_VECTOR (14 downto 0);
signal rightBottomX_uid121_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal rightBottomY_uid122_prod_uid47_fpMulTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal rightBottomY_uid122_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal aboveLeftX_uid123_prod_uid47_fpMulTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal aboveLeftX_uid123_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal aboveLeftY_uid124_prod_uid47_fpMulTest_in : STD_LOGIC_VECTOR (14 downto 0);
signal aboveLeftY_uid124_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal n0_uid130_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n1_uid131_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n0_uid132_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n1_uid133_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n0_uid138_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n1_uid139_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n0_uid140_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n1_uid141_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n0_uid146_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal n1_uid147_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal n0_uid148_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal n1_uid149_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal sm0_uid160_prod_uid47_fpMulTest_a0 : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid160_prod_uid47_fpMulTest_b0 : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid160_prod_uid47_fpMulTest_s1 : STD_LOGIC_VECTOR (35 downto 0);
signal sm0_uid160_prod_uid47_fpMulTest_reset : std_logic;
signal sm0_uid160_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (35 downto 0);
signal sm0_uid161_prod_uid47_fpMulTest_a0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm0_uid161_prod_uid47_fpMulTest_b0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm0_uid161_prod_uid47_fpMulTest_s1 : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid161_prod_uid47_fpMulTest_reset : std_logic;
signal sm0_uid161_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (17 downto 0);
signal sm1_uid162_prod_uid47_fpMulTest_a0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm1_uid162_prod_uid47_fpMulTest_b0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm1_uid162_prod_uid47_fpMulTest_s1 : STD_LOGIC_VECTOR (17 downto 0);
signal sm1_uid162_prod_uid47_fpMulTest_reset : std_logic;
signal sm1_uid162_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid163_prod_uid47_fpMulTest_a0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm0_uid163_prod_uid47_fpMulTest_b0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm0_uid163_prod_uid47_fpMulTest_s1 : STD_LOGIC_VECTOR (3 downto 0);
signal sm0_uid163_prod_uid47_fpMulTest_reset : std_logic;
signal sm0_uid163_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (3 downto 0);
signal sm1_uid164_prod_uid47_fpMulTest_a0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm1_uid164_prod_uid47_fpMulTest_b0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm1_uid164_prod_uid47_fpMulTest_s1 : STD_LOGIC_VECTOR (3 downto 0);
signal sm1_uid164_prod_uid47_fpMulTest_reset : std_logic;
signal sm1_uid164_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (3 downto 0);
signal lev1_a0_uid165_prod_uid47_fpMulTest_a : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a0_uid165_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a0_uid165_prod_uid47_fpMulTest_o : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a0_uid165_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a1high_uid168_prod_uid47_fpMulTest_a : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1high_uid168_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1high_uid168_prod_uid47_fpMulTest_o : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1high_uid168_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1_uid169_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (18 downto 0);
signal lev2_a0_uid170_prod_uid47_fpMulTest_a : STD_LOGIC_VECTOR (37 downto 0);
signal lev2_a0_uid170_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (37 downto 0);
signal lev2_a0_uid170_prod_uid47_fpMulTest_o : STD_LOGIC_VECTOR (37 downto 0);
signal lev2_a0_uid170_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (37 downto 0);
signal lev3_a0high_uid173_prod_uid47_fpMulTest_a : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0high_uid173_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0high_uid173_prod_uid47_fpMulTest_o : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0high_uid173_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0_uid174_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (38 downto 0);
signal osig_uid175_prod_uid47_fpMulTest_in : STD_LOGIC_VECTOR (35 downto 0);
signal osig_uid175_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (26 downto 0);
signal lowRangeA_uid166_prod_uid47_fpMulTest_merged_bit_select_b : STD_LOGIC_VECTOR (4 downto 0);
signal lowRangeA_uid166_prod_uid47_fpMulTest_merged_bit_select_c : STD_LOGIC_VECTOR (12 downto 0);
signal lowRangeA_uid171_prod_uid47_fpMulTest_merged_bit_select_b : STD_LOGIC_VECTOR (4 downto 0);
signal lowRangeA_uid171_prod_uid47_fpMulTest_merged_bit_select_c : STD_LOGIC_VECTOR (32 downto 0);
signal redist0_signR_uid48_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist1_expSum_uid44_fpMulTest_q_2_q : STD_LOGIC_VECTOR (8 downto 0);
signal redist2_fracXIsZero_uid31_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist3_expXIsMax_uid30_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist4_excZ_y_uid29_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist5_fracXIsZero_uid17_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist6_expXIsMax_uid16_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist7_excZ_x_uid15_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
begin
-- frac_x_uid14_fpMulTest(BITSELECT,13)@0
frac_x_uid14_fpMulTest_b <= a(22 downto 0);
-- cstZeroWF_uid11_fpMulTest(CONSTANT,10)
cstZeroWF_uid11_fpMulTest_q <= "00000000000000000000000";
-- fracXIsZero_uid17_fpMulTest(LOGICAL,16)@0 + 1
fracXIsZero_uid17_fpMulTest_qi <= "1" WHEN cstZeroWF_uid11_fpMulTest_q = frac_x_uid14_fpMulTest_b ELSE "0";
fracXIsZero_uid17_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid17_fpMulTest_qi, xout => fracXIsZero_uid17_fpMulTest_q, clk => clk, aclr => areset );
-- redist5_fracXIsZero_uid17_fpMulTest_q_2(DELAY,183)
redist5_fracXIsZero_uid17_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid17_fpMulTest_q, xout => redist5_fracXIsZero_uid17_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- cstAllOWE_uid10_fpMulTest(CONSTANT,9)
cstAllOWE_uid10_fpMulTest_q <= "11111111";
-- expX_uid6_fpMulTest(BITSELECT,5)@0
expX_uid6_fpMulTest_b <= a(30 downto 23);
-- expXIsMax_uid16_fpMulTest(LOGICAL,15)@0 + 1
expXIsMax_uid16_fpMulTest_qi <= "1" WHEN expX_uid6_fpMulTest_b = cstAllOWE_uid10_fpMulTest_q ELSE "0";
expXIsMax_uid16_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid16_fpMulTest_qi, xout => expXIsMax_uid16_fpMulTest_q, clk => clk, aclr => areset );
-- redist6_expXIsMax_uid16_fpMulTest_q_2(DELAY,184)
redist6_expXIsMax_uid16_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid16_fpMulTest_q, xout => redist6_expXIsMax_uid16_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- excI_x_uid19_fpMulTest(LOGICAL,18)@2
excI_x_uid19_fpMulTest_q <= redist6_expXIsMax_uid16_fpMulTest_q_2_q and redist5_fracXIsZero_uid17_fpMulTest_q_2_q;
-- cstAllZWE_uid12_fpMulTest(CONSTANT,11)
cstAllZWE_uid12_fpMulTest_q <= "00000000";
-- expY_uid7_fpMulTest(BITSELECT,6)@0
expY_uid7_fpMulTest_b <= b(30 downto 23);
-- excZ_y_uid29_fpMulTest(LOGICAL,28)@0 + 1
excZ_y_uid29_fpMulTest_qi <= "1" WHEN expY_uid7_fpMulTest_b = cstAllZWE_uid12_fpMulTest_q ELSE "0";
excZ_y_uid29_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_y_uid29_fpMulTest_qi, xout => excZ_y_uid29_fpMulTest_q, clk => clk, aclr => areset );
-- redist4_excZ_y_uid29_fpMulTest_q_2(DELAY,182)
redist4_excZ_y_uid29_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_y_uid29_fpMulTest_q, xout => redist4_excZ_y_uid29_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- excYZAndExcXI_uid75_fpMulTest(LOGICAL,74)@2
excYZAndExcXI_uid75_fpMulTest_q <= redist4_excZ_y_uid29_fpMulTest_q_2_q and excI_x_uid19_fpMulTest_q;
-- frac_y_uid28_fpMulTest(BITSELECT,27)@0
frac_y_uid28_fpMulTest_b <= b(22 downto 0);
-- fracXIsZero_uid31_fpMulTest(LOGICAL,30)@0 + 1
fracXIsZero_uid31_fpMulTest_qi <= "1" WHEN cstZeroWF_uid11_fpMulTest_q = frac_y_uid28_fpMulTest_b ELSE "0";
fracXIsZero_uid31_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid31_fpMulTest_qi, xout => fracXIsZero_uid31_fpMulTest_q, clk => clk, aclr => areset );
-- redist2_fracXIsZero_uid31_fpMulTest_q_2(DELAY,180)
redist2_fracXIsZero_uid31_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid31_fpMulTest_q, xout => redist2_fracXIsZero_uid31_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- expXIsMax_uid30_fpMulTest(LOGICAL,29)@0 + 1
expXIsMax_uid30_fpMulTest_qi <= "1" WHEN expY_uid7_fpMulTest_b = cstAllOWE_uid10_fpMulTest_q ELSE "0";
expXIsMax_uid30_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid30_fpMulTest_qi, xout => expXIsMax_uid30_fpMulTest_q, clk => clk, aclr => areset );
-- redist3_expXIsMax_uid30_fpMulTest_q_2(DELAY,181)
redist3_expXIsMax_uid30_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid30_fpMulTest_q, xout => redist3_expXIsMax_uid30_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- excI_y_uid33_fpMulTest(LOGICAL,32)@2
excI_y_uid33_fpMulTest_q <= redist3_expXIsMax_uid30_fpMulTest_q_2_q and redist2_fracXIsZero_uid31_fpMulTest_q_2_q;
-- excZ_x_uid15_fpMulTest(LOGICAL,14)@0 + 1
excZ_x_uid15_fpMulTest_qi <= "1" WHEN expX_uid6_fpMulTest_b = cstAllZWE_uid12_fpMulTest_q ELSE "0";
excZ_x_uid15_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_x_uid15_fpMulTest_qi, xout => excZ_x_uid15_fpMulTest_q, clk => clk, aclr => areset );
-- redist7_excZ_x_uid15_fpMulTest_q_2(DELAY,185)
redist7_excZ_x_uid15_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_x_uid15_fpMulTest_q, xout => redist7_excZ_x_uid15_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- excXZAndExcYI_uid76_fpMulTest(LOGICAL,75)@2
excXZAndExcYI_uid76_fpMulTest_q <= redist7_excZ_x_uid15_fpMulTest_q_2_q and excI_y_uid33_fpMulTest_q;
-- ZeroTimesInf_uid77_fpMulTest(LOGICAL,76)@2
ZeroTimesInf_uid77_fpMulTest_q <= excXZAndExcYI_uid76_fpMulTest_q or excYZAndExcXI_uid75_fpMulTest_q;
-- fracXIsNotZero_uid32_fpMulTest(LOGICAL,31)@2
fracXIsNotZero_uid32_fpMulTest_q <= not (redist2_fracXIsZero_uid31_fpMulTest_q_2_q);
-- excN_y_uid34_fpMulTest(LOGICAL,33)@2
excN_y_uid34_fpMulTest_q <= redist3_expXIsMax_uid30_fpMulTest_q_2_q and fracXIsNotZero_uid32_fpMulTest_q;
-- fracXIsNotZero_uid18_fpMulTest(LOGICAL,17)@2
fracXIsNotZero_uid18_fpMulTest_q <= not (redist5_fracXIsZero_uid17_fpMulTest_q_2_q);
-- excN_x_uid20_fpMulTest(LOGICAL,19)@2
excN_x_uid20_fpMulTest_q <= redist6_expXIsMax_uid16_fpMulTest_q_2_q and fracXIsNotZero_uid18_fpMulTest_q;
-- excRNaN_uid78_fpMulTest(LOGICAL,77)@2
excRNaN_uid78_fpMulTest_q <= excN_x_uid20_fpMulTest_q or excN_y_uid34_fpMulTest_q or ZeroTimesInf_uid77_fpMulTest_q;
-- invExcRNaN_uid90_fpMulTest(LOGICAL,89)@2
invExcRNaN_uid90_fpMulTest_q <= not (excRNaN_uid78_fpMulTest_q);
-- signY_uid9_fpMulTest(BITSELECT,8)@0
signY_uid9_fpMulTest_b <= STD_LOGIC_VECTOR(b(31 downto 31));
-- signX_uid8_fpMulTest(BITSELECT,7)@0
signX_uid8_fpMulTest_b <= STD_LOGIC_VECTOR(a(31 downto 31));
-- signR_uid48_fpMulTest(LOGICAL,47)@0 + 1
signR_uid48_fpMulTest_qi <= signX_uid8_fpMulTest_b xor signY_uid9_fpMulTest_b;
signR_uid48_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => signR_uid48_fpMulTest_qi, xout => signR_uid48_fpMulTest_q, clk => clk, aclr => areset );
-- redist0_signR_uid48_fpMulTest_q_2(DELAY,178)
redist0_signR_uid48_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => signR_uid48_fpMulTest_q, xout => redist0_signR_uid48_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- VCC(CONSTANT,1)
VCC_q <= "1";
-- signRPostExc_uid91_fpMulTest(LOGICAL,90)@2
signRPostExc_uid91_fpMulTest_q <= redist0_signR_uid48_fpMulTest_q_2_q and invExcRNaN_uid90_fpMulTest_q;
-- GND(CONSTANT,0)
GND_q <= "0";
-- ofracY_uid43_fpMulTest(BITJOIN,42)@0
ofracY_uid43_fpMulTest_q <= VCC_q & frac_y_uid28_fpMulTest_b;
-- aboveLeftY_uid124_prod_uid47_fpMulTest(BITSELECT,123)@0
aboveLeftY_uid124_prod_uid47_fpMulTest_in <= ofracY_uid43_fpMulTest_q(14 downto 0);
aboveLeftY_uid124_prod_uid47_fpMulTest_b <= aboveLeftY_uid124_prod_uid47_fpMulTest_in(14 downto 10);
-- n1_uid133_prod_uid47_fpMulTest(BITSELECT,132)@0
n1_uid133_prod_uid47_fpMulTest_b <= aboveLeftY_uid124_prod_uid47_fpMulTest_b(4 downto 1);
-- n1_uid141_prod_uid47_fpMulTest(BITSELECT,140)@0
n1_uid141_prod_uid47_fpMulTest_b <= n1_uid133_prod_uid47_fpMulTest_b(3 downto 1);
-- n1_uid149_prod_uid47_fpMulTest(BITSELECT,148)@0
n1_uid149_prod_uid47_fpMulTest_b <= n1_uid141_prod_uid47_fpMulTest_b(2 downto 1);
-- ofracX_uid40_fpMulTest(BITJOIN,39)@0
ofracX_uid40_fpMulTest_q <= VCC_q & frac_x_uid14_fpMulTest_b;
-- aboveLeftX_uid123_prod_uid47_fpMulTest(BITSELECT,122)@0
aboveLeftX_uid123_prod_uid47_fpMulTest_in <= ofracX_uid40_fpMulTest_q(5 downto 0);
aboveLeftX_uid123_prod_uid47_fpMulTest_b <= aboveLeftX_uid123_prod_uid47_fpMulTest_in(5 downto 1);
-- n0_uid132_prod_uid47_fpMulTest(BITSELECT,131)@0
n0_uid132_prod_uid47_fpMulTest_b <= aboveLeftX_uid123_prod_uid47_fpMulTest_b(4 downto 1);
-- n0_uid140_prod_uid47_fpMulTest(BITSELECT,139)@0
n0_uid140_prod_uid47_fpMulTest_b <= n0_uid132_prod_uid47_fpMulTest_b(3 downto 1);
-- n0_uid148_prod_uid47_fpMulTest(BITSELECT,147)@0
n0_uid148_prod_uid47_fpMulTest_b <= n0_uid140_prod_uid47_fpMulTest_b(2 downto 1);
-- sm1_uid164_prod_uid47_fpMulTest(MULT,163)@0 + 2
sm1_uid164_prod_uid47_fpMulTest_a0 <= n0_uid148_prod_uid47_fpMulTest_b;
sm1_uid164_prod_uid47_fpMulTest_b0 <= n1_uid149_prod_uid47_fpMulTest_b;
sm1_uid164_prod_uid47_fpMulTest_reset <= areset;
sm1_uid164_prod_uid47_fpMulTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 2,
lpm_widthb => 2,
lpm_widthp => 4,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm1_uid164_prod_uid47_fpMulTest_a0,
datab => sm1_uid164_prod_uid47_fpMulTest_b0,
clken => VCC_q(0),
aclr => sm1_uid164_prod_uid47_fpMulTest_reset,
clock => clk,
result => sm1_uid164_prod_uid47_fpMulTest_s1
);
sm1_uid164_prod_uid47_fpMulTest_q <= sm1_uid164_prod_uid47_fpMulTest_s1;
-- lev3_a0high_uid173_prod_uid47_fpMulTest(ADD,172)@2
lev3_a0high_uid173_prod_uid47_fpMulTest_a <= STD_LOGIC_VECTOR("0" & lowRangeA_uid171_prod_uid47_fpMulTest_merged_bit_select_c);
lev3_a0high_uid173_prod_uid47_fpMulTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000" & sm1_uid164_prod_uid47_fpMulTest_q);
lev3_a0high_uid173_prod_uid47_fpMulTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev3_a0high_uid173_prod_uid47_fpMulTest_a) + UNSIGNED(lev3_a0high_uid173_prod_uid47_fpMulTest_b));
lev3_a0high_uid173_prod_uid47_fpMulTest_q <= lev3_a0high_uid173_prod_uid47_fpMulTest_o(33 downto 0);
-- rightBottomY_uid122_prod_uid47_fpMulTest(BITSELECT,121)@0
rightBottomY_uid122_prod_uid47_fpMulTest_in <= ofracY_uid43_fpMulTest_q(5 downto 0);
rightBottomY_uid122_prod_uid47_fpMulTest_b <= rightBottomY_uid122_prod_uid47_fpMulTest_in(5 downto 1);
-- n1_uid131_prod_uid47_fpMulTest(BITSELECT,130)@0
n1_uid131_prod_uid47_fpMulTest_b <= rightBottomY_uid122_prod_uid47_fpMulTest_b(4 downto 1);
-- n1_uid139_prod_uid47_fpMulTest(BITSELECT,138)@0
n1_uid139_prod_uid47_fpMulTest_b <= n1_uid131_prod_uid47_fpMulTest_b(3 downto 1);
-- n1_uid147_prod_uid47_fpMulTest(BITSELECT,146)@0
n1_uid147_prod_uid47_fpMulTest_b <= n1_uid139_prod_uid47_fpMulTest_b(2 downto 1);
-- rightBottomX_uid121_prod_uid47_fpMulTest(BITSELECT,120)@0
rightBottomX_uid121_prod_uid47_fpMulTest_in <= ofracX_uid40_fpMulTest_q(14 downto 0);
rightBottomX_uid121_prod_uid47_fpMulTest_b <= rightBottomX_uid121_prod_uid47_fpMulTest_in(14 downto 10);
-- n0_uid130_prod_uid47_fpMulTest(BITSELECT,129)@0
n0_uid130_prod_uid47_fpMulTest_b <= rightBottomX_uid121_prod_uid47_fpMulTest_b(4 downto 1);
-- n0_uid138_prod_uid47_fpMulTest(BITSELECT,137)@0
n0_uid138_prod_uid47_fpMulTest_b <= n0_uid130_prod_uid47_fpMulTest_b(3 downto 1);
-- n0_uid146_prod_uid47_fpMulTest(BITSELECT,145)@0
n0_uid146_prod_uid47_fpMulTest_b <= n0_uid138_prod_uid47_fpMulTest_b(2 downto 1);
-- sm0_uid163_prod_uid47_fpMulTest(MULT,162)@0 + 2
sm0_uid163_prod_uid47_fpMulTest_a0 <= n0_uid146_prod_uid47_fpMulTest_b;
sm0_uid163_prod_uid47_fpMulTest_b0 <= n1_uid147_prod_uid47_fpMulTest_b;
sm0_uid163_prod_uid47_fpMulTest_reset <= areset;
sm0_uid163_prod_uid47_fpMulTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 2,
lpm_widthb => 2,
lpm_widthp => 4,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid163_prod_uid47_fpMulTest_a0,
datab => sm0_uid163_prod_uid47_fpMulTest_b0,
clken => VCC_q(0),
aclr => sm0_uid163_prod_uid47_fpMulTest_reset,
clock => clk,
result => sm0_uid163_prod_uid47_fpMulTest_s1
);
sm0_uid163_prod_uid47_fpMulTest_q <= sm0_uid163_prod_uid47_fpMulTest_s1;
-- lev1_a1high_uid168_prod_uid47_fpMulTest(ADD,167)@2
lev1_a1high_uid168_prod_uid47_fpMulTest_a <= STD_LOGIC_VECTOR("0" & lowRangeA_uid166_prod_uid47_fpMulTest_merged_bit_select_c);
lev1_a1high_uid168_prod_uid47_fpMulTest_b <= STD_LOGIC_VECTOR("0000000000" & sm0_uid163_prod_uid47_fpMulTest_q);
lev1_a1high_uid168_prod_uid47_fpMulTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev1_a1high_uid168_prod_uid47_fpMulTest_a) + UNSIGNED(lev1_a1high_uid168_prod_uid47_fpMulTest_b));
lev1_a1high_uid168_prod_uid47_fpMulTest_q <= lev1_a1high_uid168_prod_uid47_fpMulTest_o(13 downto 0);
-- rightBottomY_uid117_prod_uid47_fpMulTest(BITSELECT,116)@0
rightBottomY_uid117_prod_uid47_fpMulTest_b <= ofracY_uid43_fpMulTest_q(23 downto 15);
-- rightBottomX_bottomRange_uid114_prod_uid47_fpMulTest(BITSELECT,113)@0
rightBottomX_bottomRange_uid114_prod_uid47_fpMulTest_in <= ofracX_uid40_fpMulTest_q(5 downto 0);
rightBottomX_bottomRange_uid114_prod_uid47_fpMulTest_b <= rightBottomX_bottomRange_uid114_prod_uid47_fpMulTest_in(5 downto 0);
-- aboveLeftY_bottomExtension_uid109_prod_uid47_fpMulTest(CONSTANT,108)
aboveLeftY_bottomExtension_uid109_prod_uid47_fpMulTest_q <= "000";
-- rightBottomX_mergedSignalTM_uid115_prod_uid47_fpMulTest(BITJOIN,114)@0
rightBottomX_mergedSignalTM_uid115_prod_uid47_fpMulTest_q <= rightBottomX_bottomRange_uid114_prod_uid47_fpMulTest_b & aboveLeftY_bottomExtension_uid109_prod_uid47_fpMulTest_q;
-- sm1_uid162_prod_uid47_fpMulTest(MULT,161)@0 + 2
sm1_uid162_prod_uid47_fpMulTest_a0 <= rightBottomX_mergedSignalTM_uid115_prod_uid47_fpMulTest_q;
sm1_uid162_prod_uid47_fpMulTest_b0 <= rightBottomY_uid117_prod_uid47_fpMulTest_b;
sm1_uid162_prod_uid47_fpMulTest_reset <= areset;
sm1_uid162_prod_uid47_fpMulTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 9,
lpm_widthb => 9,
lpm_widthp => 18,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm1_uid162_prod_uid47_fpMulTest_a0,
datab => sm1_uid162_prod_uid47_fpMulTest_b0,
clken => VCC_q(0),
aclr => sm1_uid162_prod_uid47_fpMulTest_reset,
clock => clk,
result => sm1_uid162_prod_uid47_fpMulTest_s1
);
sm1_uid162_prod_uid47_fpMulTest_q <= sm1_uid162_prod_uid47_fpMulTest_s1;
-- lowRangeA_uid166_prod_uid47_fpMulTest_merged_bit_select(BITSELECT,176)@2
lowRangeA_uid166_prod_uid47_fpMulTest_merged_bit_select_b <= sm1_uid162_prod_uid47_fpMulTest_q(4 downto 0);
lowRangeA_uid166_prod_uid47_fpMulTest_merged_bit_select_c <= sm1_uid162_prod_uid47_fpMulTest_q(17 downto 5);
-- lev1_a1_uid169_prod_uid47_fpMulTest(BITJOIN,168)@2
lev1_a1_uid169_prod_uid47_fpMulTest_q <= lev1_a1high_uid168_prod_uid47_fpMulTest_q & lowRangeA_uid166_prod_uid47_fpMulTest_merged_bit_select_b;
-- aboveLeftY_bottomRange_uid110_prod_uid47_fpMulTest(BITSELECT,109)@0
aboveLeftY_bottomRange_uid110_prod_uid47_fpMulTest_in <= ofracY_uid43_fpMulTest_q(5 downto 0);
aboveLeftY_bottomRange_uid110_prod_uid47_fpMulTest_b <= aboveLeftY_bottomRange_uid110_prod_uid47_fpMulTest_in(5 downto 0);
-- aboveLeftY_mergedSignalTM_uid111_prod_uid47_fpMulTest(BITJOIN,110)@0
aboveLeftY_mergedSignalTM_uid111_prod_uid47_fpMulTest_q <= aboveLeftY_bottomRange_uid110_prod_uid47_fpMulTest_b & aboveLeftY_bottomExtension_uid109_prod_uid47_fpMulTest_q;
-- aboveLeftX_uid108_prod_uid47_fpMulTest(BITSELECT,107)@0
aboveLeftX_uid108_prod_uid47_fpMulTest_b <= ofracX_uid40_fpMulTest_q(23 downto 15);
-- sm0_uid161_prod_uid47_fpMulTest(MULT,160)@0 + 2
sm0_uid161_prod_uid47_fpMulTest_a0 <= aboveLeftX_uid108_prod_uid47_fpMulTest_b;
sm0_uid161_prod_uid47_fpMulTest_b0 <= aboveLeftY_mergedSignalTM_uid111_prod_uid47_fpMulTest_q;
sm0_uid161_prod_uid47_fpMulTest_reset <= areset;
sm0_uid161_prod_uid47_fpMulTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 9,
lpm_widthb => 9,
lpm_widthp => 18,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid161_prod_uid47_fpMulTest_a0,
datab => sm0_uid161_prod_uid47_fpMulTest_b0,
clken => VCC_q(0),
aclr => sm0_uid161_prod_uid47_fpMulTest_reset,
clock => clk,
result => sm0_uid161_prod_uid47_fpMulTest_s1
);
sm0_uid161_prod_uid47_fpMulTest_q <= sm0_uid161_prod_uid47_fpMulTest_s1;
-- topRangeY_uid103_prod_uid47_fpMulTest(BITSELECT,102)@0
topRangeY_uid103_prod_uid47_fpMulTest_b <= ofracY_uid43_fpMulTest_q(23 downto 6);
-- topRangeX_uid102_prod_uid47_fpMulTest(BITSELECT,101)@0
topRangeX_uid102_prod_uid47_fpMulTest_b <= ofracX_uid40_fpMulTest_q(23 downto 6);
-- sm0_uid160_prod_uid47_fpMulTest(MULT,159)@0 + 2
sm0_uid160_prod_uid47_fpMulTest_a0 <= topRangeX_uid102_prod_uid47_fpMulTest_b;
sm0_uid160_prod_uid47_fpMulTest_b0 <= topRangeY_uid103_prod_uid47_fpMulTest_b;
sm0_uid160_prod_uid47_fpMulTest_reset <= areset;
sm0_uid160_prod_uid47_fpMulTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 18,
lpm_widthb => 18,
lpm_widthp => 36,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid160_prod_uid47_fpMulTest_a0,
datab => sm0_uid160_prod_uid47_fpMulTest_b0,
clken => VCC_q(0),
aclr => sm0_uid160_prod_uid47_fpMulTest_reset,
clock => clk,
result => sm0_uid160_prod_uid47_fpMulTest_s1
);
sm0_uid160_prod_uid47_fpMulTest_q <= sm0_uid160_prod_uid47_fpMulTest_s1;
-- lev1_a0_uid165_prod_uid47_fpMulTest(ADD,164)@2
lev1_a0_uid165_prod_uid47_fpMulTest_a <= STD_LOGIC_VECTOR("0" & sm0_uid160_prod_uid47_fpMulTest_q);
lev1_a0_uid165_prod_uid47_fpMulTest_b <= STD_LOGIC_VECTOR("0000000000000000000" & sm0_uid161_prod_uid47_fpMulTest_q);
lev1_a0_uid165_prod_uid47_fpMulTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev1_a0_uid165_prod_uid47_fpMulTest_a) + UNSIGNED(lev1_a0_uid165_prod_uid47_fpMulTest_b));
lev1_a0_uid165_prod_uid47_fpMulTest_q <= lev1_a0_uid165_prod_uid47_fpMulTest_o(36 downto 0);
-- lev2_a0_uid170_prod_uid47_fpMulTest(ADD,169)@2
lev2_a0_uid170_prod_uid47_fpMulTest_a <= STD_LOGIC_VECTOR("0" & lev1_a0_uid165_prod_uid47_fpMulTest_q);
lev2_a0_uid170_prod_uid47_fpMulTest_b <= STD_LOGIC_VECTOR("0000000000000000000" & lev1_a1_uid169_prod_uid47_fpMulTest_q);
lev2_a0_uid170_prod_uid47_fpMulTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev2_a0_uid170_prod_uid47_fpMulTest_a) + UNSIGNED(lev2_a0_uid170_prod_uid47_fpMulTest_b));
lev2_a0_uid170_prod_uid47_fpMulTest_q <= lev2_a0_uid170_prod_uid47_fpMulTest_o(37 downto 0);
-- lowRangeA_uid171_prod_uid47_fpMulTest_merged_bit_select(BITSELECT,177)@2
lowRangeA_uid171_prod_uid47_fpMulTest_merged_bit_select_b <= lev2_a0_uid170_prod_uid47_fpMulTest_q(4 downto 0);
lowRangeA_uid171_prod_uid47_fpMulTest_merged_bit_select_c <= lev2_a0_uid170_prod_uid47_fpMulTest_q(37 downto 5);
-- lev3_a0_uid174_prod_uid47_fpMulTest(BITJOIN,173)@2
lev3_a0_uid174_prod_uid47_fpMulTest_q <= lev3_a0high_uid173_prod_uid47_fpMulTest_q & lowRangeA_uid171_prod_uid47_fpMulTest_merged_bit_select_b;
-- osig_uid175_prod_uid47_fpMulTest(BITSELECT,174)@2
osig_uid175_prod_uid47_fpMulTest_in <= lev3_a0_uid174_prod_uid47_fpMulTest_q(35 downto 0);
osig_uid175_prod_uid47_fpMulTest_b <= osig_uid175_prod_uid47_fpMulTest_in(35 downto 9);
-- normalizeBit_uid49_fpMulTest(BITSELECT,48)@2
normalizeBit_uid49_fpMulTest_b <= STD_LOGIC_VECTOR(osig_uid175_prod_uid47_fpMulTest_b(26 downto 26));
-- roundBitAndNormalizationOp_uid57_fpMulTest(BITJOIN,56)@2
roundBitAndNormalizationOp_uid57_fpMulTest_q <= GND_q & normalizeBit_uid49_fpMulTest_b & cstZeroWF_uid11_fpMulTest_q & VCC_q;
-- biasInc_uid45_fpMulTest(CONSTANT,44)
biasInc_uid45_fpMulTest_q <= "0001111111";
-- expSum_uid44_fpMulTest(ADD,43)@0 + 1
expSum_uid44_fpMulTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpMulTest_b);
expSum_uid44_fpMulTest_b <= STD_LOGIC_VECTOR("0" & expY_uid7_fpMulTest_b);
expSum_uid44_fpMulTest_clkproc: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid44_fpMulTest_o <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
expSum_uid44_fpMulTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid44_fpMulTest_a) + UNSIGNED(expSum_uid44_fpMulTest_b));
END IF;
END PROCESS;
expSum_uid44_fpMulTest_q <= expSum_uid44_fpMulTest_o(8 downto 0);
-- redist1_expSum_uid44_fpMulTest_q_2(DELAY,179)
redist1_expSum_uid44_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 9, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expSum_uid44_fpMulTest_q, xout => redist1_expSum_uid44_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- expSumMBias_uid46_fpMulTest(SUB,45)@2
expSumMBias_uid46_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "00" & redist1_expSum_uid44_fpMulTest_q_2_q));
expSumMBias_uid46_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid45_fpMulTest_q(9)) & biasInc_uid45_fpMulTest_q));
expSumMBias_uid46_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid46_fpMulTest_a) - SIGNED(expSumMBias_uid46_fpMulTest_b));
expSumMBias_uid46_fpMulTest_q <= expSumMBias_uid46_fpMulTest_o(10 downto 0);
-- fracRPostNormHigh_uid51_fpMulTest(BITSELECT,50)@2
fracRPostNormHigh_uid51_fpMulTest_in <= osig_uid175_prod_uid47_fpMulTest_b(25 downto 0);
fracRPostNormHigh_uid51_fpMulTest_b <= fracRPostNormHigh_uid51_fpMulTest_in(25 downto 2);
-- fracRPostNormLow_uid52_fpMulTest(BITSELECT,51)@2
fracRPostNormLow_uid52_fpMulTest_in <= osig_uid175_prod_uid47_fpMulTest_b(24 downto 0);
fracRPostNormLow_uid52_fpMulTest_b <= fracRPostNormLow_uid52_fpMulTest_in(24 downto 1);
-- fracRPostNorm_uid53_fpMulTest(MUX,52)@2
fracRPostNorm_uid53_fpMulTest_s <= normalizeBit_uid49_fpMulTest_b;
fracRPostNorm_uid53_fpMulTest_combproc: PROCESS (fracRPostNorm_uid53_fpMulTest_s, fracRPostNormLow_uid52_fpMulTest_b, fracRPostNormHigh_uid51_fpMulTest_b)
BEGIN
CASE (fracRPostNorm_uid53_fpMulTest_s) IS
WHEN "0" => fracRPostNorm_uid53_fpMulTest_q <= fracRPostNormLow_uid52_fpMulTest_b;
WHEN "1" => fracRPostNorm_uid53_fpMulTest_q <= fracRPostNormHigh_uid51_fpMulTest_b;
WHEN OTHERS => fracRPostNorm_uid53_fpMulTest_q <= (others => '0');
END CASE;
END PROCESS;
-- expFracPreRound_uid55_fpMulTest(BITJOIN,54)@2
expFracPreRound_uid55_fpMulTest_q <= expSumMBias_uid46_fpMulTest_q & fracRPostNorm_uid53_fpMulTest_q;
-- expFracRPostRounding_uid58_fpMulTest(ADD,57)@2
expFracRPostRounding_uid58_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((36 downto 35 => expFracPreRound_uid55_fpMulTest_q(34)) & expFracPreRound_uid55_fpMulTest_q));
expFracRPostRounding_uid58_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "0000000000" & roundBitAndNormalizationOp_uid57_fpMulTest_q));
expFracRPostRounding_uid58_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid58_fpMulTest_a) + SIGNED(expFracRPostRounding_uid58_fpMulTest_b));
expFracRPostRounding_uid58_fpMulTest_q <= expFracRPostRounding_uid58_fpMulTest_o(35 downto 0);
-- expRPreExcExt_uid60_fpMulTest(BITSELECT,59)@2
expRPreExcExt_uid60_fpMulTest_b <= STD_LOGIC_VECTOR(expFracRPostRounding_uid58_fpMulTest_q(35 downto 24));
-- expRPreExc_uid61_fpMulTest(BITSELECT,60)@2
expRPreExc_uid61_fpMulTest_in <= expRPreExcExt_uid60_fpMulTest_b(7 downto 0);
expRPreExc_uid61_fpMulTest_b <= expRPreExc_uid61_fpMulTest_in(7 downto 0);
-- expOvf_uid64_fpMulTest(COMPARE,63)@2
expOvf_uid64_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((13 downto 12 => expRPreExcExt_uid60_fpMulTest_b(11)) & expRPreExcExt_uid60_fpMulTest_b));
expOvf_uid64_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "00000" & cstAllOWE_uid10_fpMulTest_q));
expOvf_uid64_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid64_fpMulTest_a) - SIGNED(expOvf_uid64_fpMulTest_b));
expOvf_uid64_fpMulTest_n(0) <= not (expOvf_uid64_fpMulTest_o(13));
-- invExpXIsMax_uid35_fpMulTest(LOGICAL,34)@2
invExpXIsMax_uid35_fpMulTest_q <= not (redist3_expXIsMax_uid30_fpMulTest_q_2_q);
-- InvExpXIsZero_uid36_fpMulTest(LOGICAL,35)@2
InvExpXIsZero_uid36_fpMulTest_q <= not (redist4_excZ_y_uid29_fpMulTest_q_2_q);
-- excR_y_uid37_fpMulTest(LOGICAL,36)@2
excR_y_uid37_fpMulTest_q <= InvExpXIsZero_uid36_fpMulTest_q and invExpXIsMax_uid35_fpMulTest_q;
-- invExpXIsMax_uid21_fpMulTest(LOGICAL,20)@2
invExpXIsMax_uid21_fpMulTest_q <= not (redist6_expXIsMax_uid16_fpMulTest_q_2_q);
-- InvExpXIsZero_uid22_fpMulTest(LOGICAL,21)@2
InvExpXIsZero_uid22_fpMulTest_q <= not (redist7_excZ_x_uid15_fpMulTest_q_2_q);
-- excR_x_uid23_fpMulTest(LOGICAL,22)@2
excR_x_uid23_fpMulTest_q <= InvExpXIsZero_uid22_fpMulTest_q and invExpXIsMax_uid21_fpMulTest_q;
-- ExcROvfAndInReg_uid73_fpMulTest(LOGICAL,72)@2
ExcROvfAndInReg_uid73_fpMulTest_q <= excR_x_uid23_fpMulTest_q and excR_y_uid37_fpMulTest_q and expOvf_uid64_fpMulTest_n;
-- excYRAndExcXI_uid72_fpMulTest(LOGICAL,71)@2
excYRAndExcXI_uid72_fpMulTest_q <= excR_y_uid37_fpMulTest_q and excI_x_uid19_fpMulTest_q;
-- excXRAndExcYI_uid71_fpMulTest(LOGICAL,70)@2
excXRAndExcYI_uid71_fpMulTest_q <= excR_x_uid23_fpMulTest_q and excI_y_uid33_fpMulTest_q;
-- excXIAndExcYI_uid70_fpMulTest(LOGICAL,69)@2
excXIAndExcYI_uid70_fpMulTest_q <= excI_x_uid19_fpMulTest_q and excI_y_uid33_fpMulTest_q;
-- excRInf_uid74_fpMulTest(LOGICAL,73)@2
excRInf_uid74_fpMulTest_q <= excXIAndExcYI_uid70_fpMulTest_q or excXRAndExcYI_uid71_fpMulTest_q or excYRAndExcXI_uid72_fpMulTest_q or ExcROvfAndInReg_uid73_fpMulTest_q;
-- expUdf_uid62_fpMulTest(COMPARE,61)@2
expUdf_uid62_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "000000000000" & GND_q));
expUdf_uid62_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((13 downto 12 => expRPreExcExt_uid60_fpMulTest_b(11)) & expRPreExcExt_uid60_fpMulTest_b));
expUdf_uid62_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid62_fpMulTest_a) - SIGNED(expUdf_uid62_fpMulTest_b));
expUdf_uid62_fpMulTest_n(0) <= not (expUdf_uid62_fpMulTest_o(13));
-- excZC3_uid68_fpMulTest(LOGICAL,67)@2
excZC3_uid68_fpMulTest_q <= excR_x_uid23_fpMulTest_q and excR_y_uid37_fpMulTest_q and expUdf_uid62_fpMulTest_n;
-- excYZAndExcXR_uid67_fpMulTest(LOGICAL,66)@2
excYZAndExcXR_uid67_fpMulTest_q <= redist4_excZ_y_uid29_fpMulTest_q_2_q and excR_x_uid23_fpMulTest_q;
-- excXZAndExcYR_uid66_fpMulTest(LOGICAL,65)@2
excXZAndExcYR_uid66_fpMulTest_q <= redist7_excZ_x_uid15_fpMulTest_q_2_q and excR_y_uid37_fpMulTest_q;
-- excXZAndExcYZ_uid65_fpMulTest(LOGICAL,64)@2
excXZAndExcYZ_uid65_fpMulTest_q <= redist7_excZ_x_uid15_fpMulTest_q_2_q and redist4_excZ_y_uid29_fpMulTest_q_2_q;
-- excRZero_uid69_fpMulTest(LOGICAL,68)@2
excRZero_uid69_fpMulTest_q <= excXZAndExcYZ_uid65_fpMulTest_q or excXZAndExcYR_uid66_fpMulTest_q or excYZAndExcXR_uid67_fpMulTest_q or excZC3_uid68_fpMulTest_q;
-- concExc_uid79_fpMulTest(BITJOIN,78)@2
concExc_uid79_fpMulTest_q <= excRNaN_uid78_fpMulTest_q & excRInf_uid74_fpMulTest_q & excRZero_uid69_fpMulTest_q;
-- excREnc_uid80_fpMulTest(LOOKUP,79)@2
excREnc_uid80_fpMulTest_combproc: PROCESS (concExc_uid79_fpMulTest_q)
BEGIN
-- Begin reserved scope level
CASE (concExc_uid79_fpMulTest_q) IS
WHEN "000" => excREnc_uid80_fpMulTest_q <= "01";
WHEN "001" => excREnc_uid80_fpMulTest_q <= "00";
WHEN "010" => excREnc_uid80_fpMulTest_q <= "10";
WHEN "011" => excREnc_uid80_fpMulTest_q <= "00";
WHEN "100" => excREnc_uid80_fpMulTest_q <= "11";
WHEN "101" => excREnc_uid80_fpMulTest_q <= "00";
WHEN "110" => excREnc_uid80_fpMulTest_q <= "00";
WHEN "111" => excREnc_uid80_fpMulTest_q <= "00";
WHEN OTHERS => -- unreachable
excREnc_uid80_fpMulTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
-- expRPostExc_uid89_fpMulTest(MUX,88)@2
expRPostExc_uid89_fpMulTest_s <= excREnc_uid80_fpMulTest_q;
expRPostExc_uid89_fpMulTest_combproc: PROCESS (expRPostExc_uid89_fpMulTest_s, cstAllZWE_uid12_fpMulTest_q, expRPreExc_uid61_fpMulTest_b, cstAllOWE_uid10_fpMulTest_q)
BEGIN
CASE (expRPostExc_uid89_fpMulTest_s) IS
WHEN "00" => expRPostExc_uid89_fpMulTest_q <= cstAllZWE_uid12_fpMulTest_q;
WHEN "01" => expRPostExc_uid89_fpMulTest_q <= expRPreExc_uid61_fpMulTest_b;
WHEN "10" => expRPostExc_uid89_fpMulTest_q <= cstAllOWE_uid10_fpMulTest_q;
WHEN "11" => expRPostExc_uid89_fpMulTest_q <= cstAllOWE_uid10_fpMulTest_q;
WHEN OTHERS => expRPostExc_uid89_fpMulTest_q <= (others => '0');
END CASE;
END PROCESS;
-- oneFracRPostExc2_uid81_fpMulTest(CONSTANT,80)
oneFracRPostExc2_uid81_fpMulTest_q <= "00000000000000000000001";
-- fracRPreExc_uid59_fpMulTest(BITSELECT,58)@2
fracRPreExc_uid59_fpMulTest_in <= expFracRPostRounding_uid58_fpMulTest_q(23 downto 0);
fracRPreExc_uid59_fpMulTest_b <= fracRPreExc_uid59_fpMulTest_in(23 downto 1);
-- fracRPostExc_uid84_fpMulTest(MUX,83)@2
fracRPostExc_uid84_fpMulTest_s <= excREnc_uid80_fpMulTest_q;
fracRPostExc_uid84_fpMulTest_combproc: PROCESS (fracRPostExc_uid84_fpMulTest_s, cstZeroWF_uid11_fpMulTest_q, fracRPreExc_uid59_fpMulTest_b, oneFracRPostExc2_uid81_fpMulTest_q)
BEGIN
CASE (fracRPostExc_uid84_fpMulTest_s) IS
WHEN "00" => fracRPostExc_uid84_fpMulTest_q <= cstZeroWF_uid11_fpMulTest_q;
WHEN "01" => fracRPostExc_uid84_fpMulTest_q <= fracRPreExc_uid59_fpMulTest_b;
WHEN "10" => fracRPostExc_uid84_fpMulTest_q <= cstZeroWF_uid11_fpMulTest_q;
WHEN "11" => fracRPostExc_uid84_fpMulTest_q <= oneFracRPostExc2_uid81_fpMulTest_q;
WHEN OTHERS => fracRPostExc_uid84_fpMulTest_q <= (others => '0');
END CASE;
END PROCESS;
-- R_uid92_fpMulTest(BITJOIN,91)@2
R_uid92_fpMulTest_q <= signRPostExc_uid91_fpMulTest_q & expRPostExc_uid89_fpMulTest_q & fracRPostExc_uid84_fpMulTest_q;
-- xOut(GPOUT,4)@2
q <= R_uid92_fpMulTest_q;
END normal;
|
-- Find a object in the middle and try to track it
-- Erik Zachrisson - erik@zachrisson.info, copyright 2014
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
use work.OV76X0Pack.all;
entity ObjectFinder is
generic (
DataW : positive
);
port (
RstN : in bit1;
Clk : in bit1;
--
Vsync : in bit1;
--
PixelIn : in word(DataW-1 downto 0);
PixelInVal : in bit1;
-- Vga if
PixelOut : out word(DataW-1 downto 0);
PixelOutVal : out bit1;
RectAct : out bit1;
-- Box if
TopLeft : out Cord;
BottomRight : out Cord
);
end entity;
architecture rtl of ObjectFinder is
signal TopLeft_N, TopLeft_D : Cord;
signal BottomRight_N, BottomRight_D : Cord;
--
signal PixelCnt_N, PixelCnt_D : word(FrameWW-1 downto 0);
signal LineCnt_N, LineCnt_D : word(FrameHW-1 downto 0);
--
signal PixelOut_N, PixelOut_D : word(DataW-1 downto 0);
--
-- Set low threshold for now
constant Threshold : natural := 2;
--
constant Levels : positive := 3;
signal IncY0_N, IncY0_D : word(Levels downto 0);
signal IncY1_N, IncY1_D : word(Levels downto 0);
signal IncX0_N, IncX0_D : word(Levels downto 0);
signal IncX1_N, IncX1_D : word(Levels downto 0);
--
signal DecY0_N, DecY0_D : word(Levels-1 downto 0);
signal DecY1_N, DecY1_D : word(Levels-1 downto 0);
signal DecX0_N, DecX0_D : word(Levels-1 downto 0);
signal DecX1_N, DecX1_D : word(Levels-1 downto 0);
signal TrackLost_N, TrackLost_D : bit1;
function calcDelta(D : word) return word is
variable delta : word(bits(D'length)-1 downto 0);
variable NormD : word(D'length-1 downto 0);
begin
NormD := D;
delta := (others => '0');
for i in 0 to D'length-1 loop
if NormD(i) = '1' then
delta := delta + 1;
end if;
end loop;
return delta;
end function;
begin
SyncProc : process (Clk, RstN)
begin
if RstN = '0' then
TopLeft_D <= MiddleOfScreen;
BottomRight_D <= MiddleOfScreen;
--
PixelCnt_D <= (others => '0');
LineCnt_D <= (others => '0');
--
IncY0_D <= (others => '0');
IncY1_D <= (others => '0');
IncX0_D <= (others => '0');
IncX1_D <= (others => '0');
DecY0_D <= (others => '0');
DecY1_D <= (others => '0');
DecX0_D <= (others => '0');
DecX1_D <= (others => '0');
TrackLost_D <= '0';
elsif rising_edge(Clk) then
TopLeft_D <= TopLeft_N;
BottomRight_D <= BottomRight_N;
--
PixelCnt_D <= PixelCnt_N;
LineCnt_D <= LineCnt_N;
--
IncY0_D <= IncY0_N;
IncY1_D <= IncY1_N;
IncX0_D <= IncX0_N;
IncX1_D <= IncX1_N;
DecY0_D <= DecY0_N;
DecY1_D <= DecY1_N;
DecX0_D <= DecX0_N;
DecX1_D <= DecX1_N;
TrackLost_D <= TrackLost_N;
end if;
end process;
AsyncProc : process (TopLeft_D, BottomRight_D, PixelIn, PixelInVal, PixelCnt_D, LineCnt_D, IncY0_D, IncY1_D, IncX0_D, IncX1_D, DecY0_D, DecY1_D, DecX0_D, DecX1_D, TrackLost_D)
variable TmpRectAct : bit1;
variable delta : word(bits(Levels)-1 downto 0);
begin
TopLeft_N <= TopLeft_D;
BottomRight_N <= BottomRight_D;
PixelCnt_N <= PixelCnt_D;
LineCnt_N <= LineCnt_D;
RectAct <= '0';
--
IncY0_N <= IncY0_D;
IncY1_N <= IncY1_D;
IncX0_N <= IncX0_D;
IncX1_N <= IncX1_D;
--
DecY0_N <= DecY0_D;
DecY1_N <= DecY1_D;
DecX0_N <= DecX0_D;
DecX1_N <= DecX1_D;
--
TrackLost_N <= TrackLost_D;
TmpRectAct := '0';
if PixelInVal = '1' then
-- Pixel counting
PixelCnt_N <= PixelCnt_D + 1;
if PixelCnt_D + 1 = FrameW then
-- End of line
PixelCnt_N <= (others => '0');
LineCnt_N <= LineCnt_D + 1;
if LineCnt_D + 1 = FrameH then
LineCnt_N <= (others => '0');
-- End of frame
-- Clear frame history
IncY0_N <= (others => '0');
IncY1_N <= (others => '0');
IncX0_N <= (others => '0');
IncX1_N <= (others => '0');
--
DecY0_N <= (others => '0');
DecY1_N <= (others => '0');
DecX0_N <= (others => '0');
DecX1_N <= (others => '0');
if IncY0_D > 0 then
if TopLeft_D.Y - IncY0_D(Levels downto 1) > 0 then
TopLeft_N.Y <= TopLeft_D.Y - calcDelta(IncY0_D(Levels downto 1));
end if;
elsif DecY0_D > 0 then
if (TopLeft_D.Y + DecY0_D < FrameH) and (TopLeft_D.Y + DecY0_D < BottomRight_D.Y) then
TopLeft_N.Y <= TopLeft_D.Y + calcDelta(DecY0_D);
end if;
else
-- If inactive, try to crawl back to middle
if TopLeft_D.Y > MiddleYOfScreen then
TopLeft_N.Y <= TopLeft_D.Y - 1;
else
TopLeft_N.Y <= TopLeft_D.Y + 1;
end if;
end if;
if IncY1_D > 0 then
if BottomRight_D.Y + IncY1_D(Levels downto 1) < FrameH then
BottomRight_N.Y <= BottomRight_D.Y + calcDelta(IncY1_D(Levels downto 1));
end if;
elsif DecY1_D > 0 then
if (BottomRight_D.Y - DecY1_D > 0) and (BottomRight_D.Y - DecY1_D > TopLeft_D.Y) then
BottomRight_N.Y <= BottomRight_D.Y - calcDelta(DecY1_D);
end if;
else
if BottomRight_D.Y > MiddleYOfScreen then
BottomRight_N.Y <= BottomRight_D.Y - 1;
else
BottomRight_N.Y <= BottomRight_D.Y + 1;
end if;
end if;
if IncX0_D > 0 then
if TopLeft_D.X - IncX0_D(Levels downto 1) > 0 then
TopLeft_N.X <= TopLeft_D.X - calcDelta(IncX0_D(Levels downto 1));
end if;
elsif DecX0_D > 0 then
if (TopLeft_D.X + DecX0_D < FrameW) and (TopLeft_D.X + DecX0_D < BottomRight_D.X) then
TopLeft_N.X <= TopLeft_D.X + calcDelta(DecX0_D);
end if;
else
if TopLeft_D.X > MiddleXOfScreen then
TopLeft_N.X <= TopLeft_D.X - 1;
else
TopLeft_N.X <= TopLeft_D.X + 1;
end if;
end if;
if IncX1_D > 0 then
if BottomRight_D.X + IncX1_D(Levels downto 1) < FrameW then
BottomRight_N.X <= BottomRight_D.X + calcDelta(IncX1_D(Levels downto 1));
end if;
elsif DecX1_D > 0 then
if (BottomRight_D.X - DecX1_D > 0) and (BottomRight_D.X - DecX1_D > TopLeft_D.X) then
BottomRight_N.X <= BottomRight_D.X - calcDelta(DecX1_D);
end if;
else
if BottomRight_D.X > MiddleXOfScreen then
BottomRight_N.X <= BottomRight_D.X - 1;
else
BottomRight_N.X <= BottomRight_D.X + 1;
end if;
end if;
-- No rect was drawn this frame. We've lost track, reset to default
if TrackLost_D = '1' then
TopLeft_N <= MiddleOfScreen;
BottomRight_N <= MiddleOfScreen;
end if;
-- Set trap for next frame
TrackLost_N <= '1';
end if;
end if;
-- Try to grow upper boundary, y0
for i in Levels downto 0 loop
if ((LineCnt_D = TopLeft_D.Y-i) and ((PixelCnt_D >= TopLeft_D.X) and (PixelCnt_D <= BottomRight_D.X))) then
if PixelIn >= Threshold then
IncY0_N(i) <= '1';
end if;
end if;
-- Try to grow lower boundary, y1
if ((LineCnt_D = BottomRight_D.Y+i) and ((PixelCnt_D >= TopLeft_D.X) and (PixelCnt_D <= BottomRight_D.X))) then
if PixelIn >= Threshold then
IncY1_N(i) <= '1';
end if;
end if;
-- Try to grow left boundary, x0
if ((PixelCnt_D = TopLeft_D.X-i) and ((LineCnt_D >= TopLeft_D.Y) and (LineCnt_D <= BottomRight_D.Y))) then
if PixelIn >= Threshold then
IncX0_N(i) <= '1';
end if;
end if;
-- Try to grow right boundary, x1
if ((PixelCnt_D = BottomRight_D.X+i) and ((LineCnt_D >= TopLeft_D.Y) and (LineCnt_D <= BottomRight_D.Y))) then
if PixelIn >= Threshold then
IncX1_N(i) <= '1';
end if;
end if;
end loop;
for i in Levels downto 1 loop
if ((LineCnt_D = TopLeft_D.Y+i) and ((PixelCnt_D >= TopLeft_D.X) and (PixelCnt_D <= BottomRight_D.X))) then
if PixelIn < Threshold then
DecY0_N(i-1) <= '1';
end if;
end if;
if ((LineCnt_D = BottomRight_D.Y-i) and ((PixelCnt_D >= TopLeft_D.X) and (PixelCnt_D <= BottomRight_D.X))) then
if PixelIn < Threshold then
DecY1_N(i-1) <= '1';
end if;
end if;
if ((PixelCnt_D = TopLeft_D.X+i) and ((LineCnt_D >= TopLeft_D.Y) and (LineCnt_D <= BottomRight_D.Y))) then
if PixelIn < Threshold then
DecX0_N(i-1) <= '1';
end if;
end if;
if ((PixelCnt_D = BottomRight_D.X-i) and ((LineCnt_D >= TopLeft_D.Y) and (LineCnt_D <= BottomRight_D.Y))) then
if PixelIn < Threshold then
DecX1_N(i-1) <= '1';
end if;
end if;
end loop;
end if;
-- Draw rectangle
-- Top, y0 line
if (LineCnt_D = TopLeft_D.Y) and ((PixelCnt_D >= TopLeft_D.X) and (PixelCnt_D <= BottomRight_D.X)) then
TmpRectAct := '1';
end if;
-- Bottom, y1 line
if (LineCnt_D = BottomRight_D.Y) and ((PixelCnt_D >= TopLeft_D.X) and (PixelCnt_D <= BottomRight_D.X)) then
TmpRectAct := '1';
end if;
-- Left, x0 line
if (PixelCnt_D = TopLeft_D.X) and ((LineCnt_D >= TopLeft_D.Y) and (LineCnt_D <= BottomRight_D.Y)) then
TmpRectAct := '1';
end if;
-- Right, x1 line
if (PixelCnt_D = BottomRight_D.X) and ((LineCnt_D >= TopLeft_D.Y) and (LineCnt_D <= BottomRight_D.Y)) then
TmpRectAct := '1';
end if;
if TmpRectAct = '1' then
TrackLost_N <= '0';
end if;
RectAct <= TmpRectAct;
end process;
TopLeftAssign : TopLeft <= TopLeft_D;
BottomRightAssign : BottomRight <= BottomRight_D;
PixelOutAssign : PixelOut <= PixelIn;
PixelOutValAssign : PixelOutVal <= PixelInVal;
end architecture rtl;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity modulo12_nov is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(0 downto 0)
);
end modulo12_nov;
architecture behaviour of modulo12_nov is
constant st0: std_logic_vector(3 downto 0) := "0000";
constant st1: std_logic_vector(3 downto 0) := "1111";
constant st2: std_logic_vector(3 downto 0) := "0001";
constant st3: std_logic_vector(3 downto 0) := "1110";
constant st4: std_logic_vector(3 downto 0) := "0010";
constant st5: std_logic_vector(3 downto 0) := "1101";
constant st6: std_logic_vector(3 downto 0) := "0011";
constant st7: std_logic_vector(3 downto 0) := "1100";
constant st8: std_logic_vector(3 downto 0) := "0100";
constant st9: std_logic_vector(3 downto 0) := "1011";
constant st10: std_logic_vector(3 downto 0) := "0101";
constant st11: std_logic_vector(3 downto 0) := "1010";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "0") then next_state <= st0; output <= "0";
elsif std_match(input, "1") then next_state <= st1; output <= "0";
end if;
when st1 =>
if std_match(input, "0") then next_state <= st1; output <= "0";
elsif std_match(input, "1") then next_state <= st2; output <= "0";
end if;
when st2 =>
if std_match(input, "0") then next_state <= st2; output <= "0";
elsif std_match(input, "1") then next_state <= st3; output <= "0";
end if;
when st3 =>
if std_match(input, "0") then next_state <= st3; output <= "0";
elsif std_match(input, "1") then next_state <= st4; output <= "0";
end if;
when st4 =>
if std_match(input, "0") then next_state <= st4; output <= "0";
elsif std_match(input, "1") then next_state <= st5; output <= "0";
end if;
when st5 =>
if std_match(input, "0") then next_state <= st5; output <= "0";
elsif std_match(input, "1") then next_state <= st6; output <= "0";
end if;
when st6 =>
if std_match(input, "0") then next_state <= st6; output <= "0";
elsif std_match(input, "1") then next_state <= st7; output <= "0";
end if;
when st7 =>
if std_match(input, "0") then next_state <= st7; output <= "0";
elsif std_match(input, "1") then next_state <= st8; output <= "0";
end if;
when st8 =>
if std_match(input, "0") then next_state <= st8; output <= "0";
elsif std_match(input, "1") then next_state <= st9; output <= "0";
end if;
when st9 =>
if std_match(input, "0") then next_state <= st9; output <= "0";
elsif std_match(input, "1") then next_state <= st10; output <= "0";
end if;
when st10 =>
if std_match(input, "0") then next_state <= st10; output <= "0";
elsif std_match(input, "1") then next_state <= st11; output <= "0";
end if;
when st11 =>
if std_match(input, "0") then next_state <= st11; output <= "0";
elsif std_match(input, "1") then next_state <= st0; output <= "0";
end if;
when others => next_state <= "----"; output <= "-";
end case;
end process;
end behaviour;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 25.06.2015 15:54:30
-- Design Name:
-- Module Name: IFFT_completa - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity IFFT_completa is
Port (
clk: in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (15 downto 0);
address_read : out STD_LOGIC_VECTOR(6 downto 0);
IfftEnable: in STD_LOGIC;
reset: in STD_LOGIC;
address_write :out STD_LOGIC_VECTOR(8 downto 0);
EnableTxserie :out STD_LOGIC;
datos_salida :out STD_LOGIC_VECTOR(31 downto 0);
we :out STD_LOGIC );
end IFFT_completa;
architecture Behavioral of IFFT_completa is
signal s_start, s_cp_len_we, s_unload,s_fwd_inv, s_fwd_inv_we, s_rfd, s_cpv,s_dv,s_edone: STD_LOGIC;
signal s_cp_len,s_xk_index : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal s_xk_re, s_xk_im : STD_LOGIC_VECTOR (15 downto 0);
COMPONENT ifft is
PORT (
clk : IN STD_LOGIC;
sclr : IN STD_LOGIC;
start : IN STD_LOGIC;
unload : IN STD_LOGIC;
cp_len : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
cp_len_we : IN STD_LOGIC;
xn_re : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
xn_im : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
fwd_inv : IN STD_LOGIC;
fwd_inv_we : IN STD_LOGIC;
rfd : OUT STD_LOGIC;
xn_index : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
busy : OUT STD_LOGIC;
edone : OUT STD_LOGIC;
done : OUT STD_LOGIC;
dv : OUT STD_LOGIC;
xk_index : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
cpv : OUT STD_LOGIC;
xk_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
xk_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
COMPONENT ifftcontrol is
GENERIC (
CARRIERS : INTEGER :=128 );
PORT (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
IfftEnable: in STD_LOGIC;
start : out STD_LOGIC;
cp_len : out STD_LOGIC_VECTOR(6 DOWNTO 0);
cp_len_we: out STD_LOGIC;
fwd_inv : out STD_LOGIC;
fwd_inv_we : out STD_LOGIC;
unload : out STD_LOGIC;
rfd : in STD_LOGIC
);
END COMPONENT;
COMPONENT guardaifft is
PORT (
reset : IN std_logic;
clk : IN std_logic;
dv : IN std_logic;
edone: in STD_LOGIC;
cpv : IN std_logic;
xk_index : IN std_logic_vector(6 downto 0);
xk_re : IN std_logic_vector(15 downto 0);
xk_im : IN std_logic_vector(15 downto 0);
we : OUT std_logic;
EnableTxserie : OUT std_logic;
dato_out : OUT std_logic_vector(31 downto 0);
addresout : OUT std_logic_vector(8 downto 0)
);
END COMPONENT;
begin
core1 : ifft
PORT MAP (
clk => clk,
sclr => reset,
start => s_start,
unload => s_unload,
cp_len => s_cp_len,
cp_len_we => s_cp_len_we,
xn_re => data_in (15 downto 8),
xn_im => data_in (7 downto 0),
fwd_inv => s_fwd_inv,
fwd_inv_we => s_fwd_inv_we,
rfd => s_rfd ,
xn_index => address_read,
busy => open,
edone => open,
done => s_edone,
dv => s_dv,
xk_index => s_xk_index ,
cpv => s_cpv,
xk_re => s_xk_re,
xk_im => s_xk_im
);
control: IfftControl
PORT MAP (
reset => reset,
clk => clk,
IfftEnable => IfftEnable,
start =>s_start,
cp_len => s_cp_len ,
cp_len_we => s_cp_len_we,
fwd_inv => s_fwd_inv,
fwd_inv_we=> s_fwd_inv_we ,
unload => s_unload,
rfd =>s_rfd
);
Inst_guardaifft : guardaifft
PORT MAP(
reset => reset ,
clk => clk ,
dv => s_dv,
edone => s_edone,
cpv =>s_cpv,
xk_index => s_xk_index,
we => we ,
xk_re => s_xk_re,
xk_im => s_xk_im,
EnableTxserie => EnableTxserie,
dato_out => datos_salida,
addresout => address_write
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:11:26 09/20/2013
-- Design Name:
-- Module Name: sdram_model - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_textio.all;
library STD;
use STD.textio.all;
entity sdram_model is
generic (
RamFileName : string := "";
mode : string := "N";
DRAM_pagesize : natural :=256
);
Port ( CLK : in STD_LOGIC;
CKE : in STD_LOGIC;
CS_N : in STD_LOGIC;
RAS_N : in STD_LOGIC;
CAS_N : in STD_LOGIC;
WE_N : in STD_LOGIC;
BA : in STD_LOGIC_VECTOR (1 downto 0);
DQM : in STD_LOGIC_VECTOR (1 downto 0);
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
DQ : inout STD_LOGIC_VECTOR (15 downto 0));
end sdram_model;
architecture Behavioral of sdram_model is
function LOG2(C:INTEGER) return INTEGER is -- C should be >0
variable TEMP,COUNT:INTEGER;
begin
TEMP:=0;
COUNT:=C;
while COUNT>1 loop
TEMP:=TEMP+1;
COUNT:=COUNT/2;
end loop;
return TEMP;
end;
type decode is (unsel_c, lmr_c, ref_c, pre_c, act_c, wr_c, rd_c, term_c, nop_c);
signal command : decode;
signal dqm_sr : std_logic_vector(3 downto 0) := (others => '0');
signal selected_bank : std_logic_vector( 1 downto 0);
signal column : std_logic_vector( log2(DRAM_pagesize)-1 downto 0) := (others => '0');
-- Only eight rows of four banks are modeled
type memory_array is array (0 to 8 * DRAM_pagesize * 4 -1 ) of std_logic_vector( 15 downto 0);
type row_array is array (0 to 3) of std_logic_vector(2 downto 0);
signal active_row : row_array;
signal is_row_active : std_logic_vector(3 downto 0);
signal mode_reg : std_logic_vector(12 downto 0);
signal data_delay1 : std_logic_vector(15 downto 0);
signal data_delay2 : std_logic_vector(15 downto 0);
signal data_delay3 : std_logic_vector(15 downto 0);
signal addr_index : STD_LOGIC_VECTOR(log2(memory_array'length)-1 downto 0);
signal wr_mask : std_logic_vector( 1 downto 0);
signal wr_data : std_logic_vector(15 downto 0);
signal wr_burst : std_logic_vector( 8 downto 0);
signal rd_burst : std_logic_vector( 9 downto 0);
impure function InitFromFile return memory_array is
FILE RamFile : text; -- is in RamFileName;
variable RamFileLine : line;
variable word : std_logic_vector(31 downto 0);
variable r : memory_array;
variable I : natural;
begin
if (mode="H" or mode="B") and RamFileName'length>0 then
file_open(RamFile,RamFileName,READ_MODE);
I:=0;
while not endfile(RamFile) loop
readline (RamFile, RamFileLine);
if mode="H" then
hread (RamFileLine, word); -- alternative: HEX read
else
read(RamFileLine,word); -- Binary read
end if;
r(I) := word(15 downto 0);
r(I+1) := word(31 downto 16);
I:=I+2;
end loop;
file_close(RamFile);
end if;
return r;
end function;
signal memory : memory_array:=InitFromFile;
begin
addr_index <= active_row(to_integer(unsigned(selected_bank))) & selected_bank & column;
decode_proc: process(CS_N, RAS_N, CAS_N, WE_N)
variable cmd : std_logic_vector(2 downto 0);
begin
if CS_N = '1' then
command <= unsel_c;
else
cmd := RAS_N & CAS_N & WE_N;
case cmd is
when "000" => command <= LMR_c;
when "001" => command <= REF_c;
when "010" => command <= PRE_c;
when "011" => command <= ACT_c;
when "100" => command <= WR_c;
when "101" => command <= RD_c;
when "110" => command <= TERM_c;
when others => command <= NOP_c;
end case;
end if;
end process;
data_process : process(clk)
begin
if rising_edge(clk) then
-- this implements the data masks, gets updated when a read command is sent
rd_burst(8 downto 0) <= rd_burst(9 downto 1);
column <= std_logic_vector(unsigned(column)+1);
wr_burst(7 downto 0) <= wr_burst(8 downto 1);
-- Process any pending writes
if wr_burst(0) = '1' and wr_mask(0) = '1' then
memory(to_integer(unsigned(addr_index)))(7 downto 0) <= wr_data(7 downto 0);
end if;
if wr_burst(0) = '1' and wr_mask(1) = '1' then
memory(to_integer(unsigned(addr_index)))(15 downto 8) <= wr_data(15 downto 8);
end if;
wr_data <= dq;
-- default is not to write
wr_mask <= "00";
if command = wr_c then
rd_burst <= (others => '0');
column <= addr(column'high downto 0);
selected_bank <= ba;
if mode_reg(9) = '1' then
wr_burst <= "000000001";
else
case mode_reg(2 downto 0) is
when "000" => wr_burst <= "000000001";
when "001" => wr_burst <= "000000011";
when "010" => wr_burst <= "000001111";
when "011" => wr_burst <= "011111111";
when "111" => wr_burst <= "111111111"; -- full page
when others =>
end case;
end if;
elsif command = lmr_c then
mode_reg <= addr;
elsif command = act_c then
-- Open a row in a bank
active_row(to_integer(unsigned(ba))) <= addr(2 downto 0);
is_row_active(to_integer(unsigned(ba))) <= '1';
elsif command = pre_c then
-- Close off the row
active_row(to_integer(unsigned(ba))) <= (others => 'X');
is_row_active(to_integer(unsigned(ba))) <= '0';
elsif command = RD_c then
wr_burst <= (others => '0');
column <= addr(column'high downto 0);
selected_bank <= ba;
-- This sets the bust length
case mode_reg(2 downto 0) is
when "000" => rd_burst <= "000000001" & rd_burst(1);
when "001" => rd_burst <= "000000011" & rd_burst(1);
when "010" => rd_burst <= "000001111" & rd_burst(1);
when "011" => rd_burst <= "011111111" & rd_burst(1);
when "111" => rd_burst <= "111111111" & rd_burst(1); -- full page
when others =>
-- full page not implemnted
end case;
end if;
-- This is the logic that implements the CAS delay. Here is enough for CAS=2
if mode_reg(6 downto 4) = "010" then
data_delay1 <= memory(to_integer(unsigned(addr_index)));
elsif mode_reg(6 downto 4) = "011" then
data_delay1 <= data_delay2;
data_delay2 <= memory(to_integer(unsigned(addr_index)));
else
data_delay1 <= data_delay2;
data_delay2 <= data_delay3;
data_delay3 <= memory(to_integer(unsigned(addr_index)));
end if;
-- Output masks lag a cycle
dqm_sr <= dqm & dqm_sr(3 downto 2);
wr_mask <= not dqm;
end if;
end process;
data2_process : process(clk)
begin
if rising_edge(clk) then
if rd_burst(0) = '1' and dqm_sr(0) = '0' then
dq( 7 downto 0) <= data_delay1(7 downto 0) after 4 ns;
else
dq( 7 downto 0) <= "ZZZZZZZZ" after 4.0 ns;
end if;
if rd_burst(0) = '1' and dqm_sr(1) = '0' then
dq(15 downto 8) <= data_delay1(15 downto 8) after 4.0 ns;
-- Move onto the next address in the active row
else
dq(15 downto 8) <= "ZZZZZZZZ" after 4.0 ns;
end if;
elsif falling_edge(clk) then
dq <= (others => 'Z') after 4.5 ns;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity radio is
port(
clk : in std_logic;
rst : in std_logic;
rf : in std_logic;
lo_out : out std_logic;
mixer_out : out std_logic;
--Frequency control input
frequency : in std_logic_vector(31 downto 0);
frequency_stb : in std_logic;
frequency_ack : out std_logic;
--Average samples
average_samples : in std_logic_vector(31 downto 0);
average_samples_stb : in std_logic;
average_samples_ack : out std_logic;
--Audio output
audio : out std_logic_vector(31 downto 0);
audio_stb : out std_logic;
audio_ack : in std_logic
);
end entity radio;
architecture rtl of radio is
signal rf_d1 : std_logic;
signal rf_d2 : std_logic;
signal s_audio_stb : std_logic;
signal lo : std_logic;
signal lo_times_rf : std_logic;
signal t : unsigned(31 downto 0) := (others => '0');
signal wt : unsigned(31 downto 0) := (others => '0');
signal frequency_reg : unsigned(31 downto 0) := (others => '0');
signal average_samples : unsigned(31 downto 0) := (others => '0');
signal average_samples_reg : unsigned(31 downto 0) := (others => '0');
signal sample_count : unsigned(31 downto 0) := (others => '0');
begin
process
begin
wait until rising_edge(clk);
rf_d1 <= rf;
rf_d2 <= rf_d1;
t <= t + 1;
wt <= t * frequency_reg;
lo <= wt(31);
lo_times_rf <= rf_d1 xor lo;
if sample_count = average_samples_reg - 1 then
average <= (others => '0');
audio <= average;
s_audio_stb <= '1';
sample_count <= 0;
else
average <= average + lo_times_rf;
sample_count <= sample_count + 1;
end if;
if frequency_stb = '1' then
frequency_reg <= unsigned(frequency);
end if;
if average_samples_stb = '1' then
average_samples_reg <= unsigned(average_samples);
end if;
if s_audio_stb = '1' and audio_ack = '1' then
s_audio_stb <= '0';
end if;
if rst = '1' then
s_audio_stb <= '0';
end if;
end process;
audio_stb <= s_audio_stb;
frequency_ack <= '1';
average_samples_ack <= '1';
lo_out <= lo;
mixer_out <= lo_times_rf;
end rtl;
|
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.packetprocessordf_types.all;
entity packetprocessordf_packetprocessor is
port(memop : in std_logic_vector(28 downto 0);
en : in boolean;
-- clock
system1000 : in std_logic;
-- asynchronous reset: active low
system1000_rstn : in std_logic;
result : out packetprocessordf_types.counterstate);
end;
architecture structural of packetprocessordf_packetprocessor is
signal app_arg : std_logic_vector(28 downto 0);
signal case_alt : std_logic_vector(28 downto 0);
signal case_alt_0 : std_logic_vector(28 downto 0);
signal case_alt_1 : std_logic_vector(28 downto 0);
signal x : unsigned(7 downto 0);
signal a : unsigned(10 downto 0);
signal ms : unsigned(7 downto 0);
signal p : unsigned(7 downto 0);
begin
app_arg <= case_alt when en else
std_logic_vector'("11" & "000000000000000000000000000");
with (memop(28 downto 27)) select
case_alt <= std_logic_vector'("11" & "000000000000000000000000000") when "00",
case_alt_0 when "01",
case_alt_1 when "10",
std_logic_vector'("10" & "000000000000000000000000000") when others;
case_alt_0 <= std_logic_vector'("00" & std_logic_vector(x) & "0000000000000000000");
case_alt_1 <= std_logic_vector'("01" & std_logic_vector(a) & std_logic_vector(ms) & std_logic_vector(p));
x <= unsigned(memop(26 downto 19));
a <= unsigned(memop(26 downto 16));
ms <= unsigned(memop(15 downto 8));
p <= unsigned(memop(7 downto 0));
packetprocessordf_moore_result : entity packetprocessordf_moore
port map
(s1 => result
,system1000 => system1000
,system1000_rstn => system1000_rstn
,w3 => app_arg);
end;
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01400_bad.vhd
-- File Creation date : 2015-04-14
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of generic port name: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity CNE_01400_bad is
generic (Width : positive := 3);
port (
i_D0 : in std_logic_vector(Width downto 0); -- First Mux input
i_D1 : in std_logic_vector(Width downto 0); -- Second Mux input
i_Sel : in std_logic; -- Mux select input
o_D : out std_logic_vector(Width downto 0) -- Mux output
);
end CNE_01400_bad;
--CODE
architecture Behavioral of CNE_01400_bad is
begin
-- Simple Mux, output depends on select value
o_D <= i_D1 when i_Sel='1'
else i_D0;
end Behavioral; |
--# picoblaze_rom.vhdl - Flexible synthesizable ROM for Picoblaze
--#
--# Freely available from Opbasm (http://code.google.com/p/opbasm)
--#
--# Copyright © 2014 Kevin Thibedeau
--# (kevin 'period' thibedeau 'at' gmail 'punto' com)
--#
--# Permission is hereby granted, free of charge, to any person obtaining a
--# copy of this software and associated documentation files (the "Software"),
--# to deal in the Software without restriction, including without limitation
--# the rights to use, copy, modify, merge, publish, distribute, sublicense,
--# and/or sell copies of the Software, and to permit persons to whom the
--# Software is furnished to do so, subject to the following conditions:
--#
--# The above copyright notice and this permission notice shall be included in
--# all copies or substantial portions of the Software.
--#
--# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
--# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
--# DEALINGS IN THE SOFTWARE.
--#
--# DEPENDENCIES: none
--#
--# DESCRIPTION:
--# This is a generic synthesizable ROM for the Picoblaze-3 and Picoblaze-6
--# processors. It can be used as an alternative to the templating ROM system
--# normally used by the Picoblaze assemblers. Instead of generating a custom
--# ROM component from a template, this package provides a general purpose ROM
--# that can read the .mem or .hex memory listings during synthesis. It is
--# known to work correctly with ISE XST 14.5.
--#
--# For simulation, this component has the advantage that it doesn't have to be
--# recompiled for every change to the Picoblaze source code in a design. It
--# automatically re-reads the latest .mem or .hex whenever the simulation is
--# reset.
--#
--# The picoblaze_rom component provides a similar port interface as the KCPSM
--# templates with the following differences:
--# * ROM_FILE generic is used to specify the name of the .mem or .hex file
--# with the ROM contents.
--# * Address is an unconstrained array. The size of the inferred ROM is
--# established by the size of the signal connected to the Address input. for
--# 1K it must be (9 downto 0), for 2K (10 downto 0), and 4K (11 downto 0).
--# With KCPSM6, the 12-bit address bus must be sliced down to implement ROMs
--# smaller than 4K.
--# * For Picoblaze-3 the Enable input must be tied high.
--#
--# An additional picoblaze_dp_rom component is available which is a
--# dual-ported implementation with a second read/write port. Both ports run
--# on the same clock domain for simplicity but the design can be trivially
--# altered to use separate clocks if desired. The second port provides access
--# to data packed with INST directives and the ability to use a portion of the
--# memory as RAM.
--#
--# The ROM can be implemented as a block RAM (BRAM) or as LUT-based distributed
--# RAM for use when BRAMs have been exhausted or only a small ROM is needed. The
--# STYLE generic is used to control the inferred RAM style. It defaults to the
--# string "BLOCK". Set it to "DISTRIBUTED" to infer distributed RAM. Any size
--# distributed RAM can be created that is a power of 2.
--#
--# Supported BRAM-based ROM configurations:
--#
--# ROM size
--# Architecture 1K 2K 4K
--# -------------------------------------------------------------
--# __
--# Spartan-3 1K |HL|
--# '--'
--# 18
--# __ _ _
--# Spartan-6 1K |HL| 2K |H| |L| 4K || || || || ||
--# '--' |H| |L| || || || || ||
--# 18 '-' '-' || || || || ||
--# 9 9 || || || || ||
--# 4 4 4 4 2
--# __ __ _ _
--# Virtex-6 1K |HL| 2K |HL| 4K |H| |L|
--# 7-Series '--' |HL| |H| |L|
--# 18 '--' |H| |L|
--# 18 |H| |L|
--# '-' '-'
--# 9 9
--#
--# Note: XST doesn't infer the most efficient partition for 4Kx18 ROM on
--# Spartan-6. The ROM_form_S6_4K_<date>.vhd template distributed with KCPSM6
--# uses only 4 BRAMs and may be a better option.
library ieee;
use ieee.std_logic_1164.all;
package picoblaze_rom_pkg is
component picoblaze_rom is
generic (
ROM_FILE : string; -- ROM memory contents in .mem or .hex format
STYLE : string := "BLOCK" -- Set to "DISTRIBUTED" to use distributed RAM
);
port (
Clock : in std_logic;
Enable : in std_logic;
Address : in std_logic_vector;
Instruction : out std_logic_vector(17 downto 0)
);
end component;
component picoblaze_dp_rom is
generic (
ROM_FILE : string; -- ROM memory contents in .mem or .hex format
STYLE : string := "BLOCK" -- Set to "DISTRIBUTED" to use distributed RAM
);
port (
Clock : in std_logic;
Enable : in std_logic;
Address : in std_logic_vector;
Instruction : out std_logic_vector(17 downto 0);
-- Second Read/Write port
Address2 : in std_logic_vector;
Instruction2 : out std_logic_vector(17 downto 0);
We : in std_logic;
Wr_instruction2 : in std_logic_vector(17 downto 0)
);
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity picoblaze_rom is
generic (
ROM_FILE : string; -- ROM memory contents in .mem or .hex format
STYLE : string := "BLOCK" -- Set to "DISTRIBUTED" to use distributed RAM
);
port (
Clock : in std_logic;
Enable : in std_logic;
Address : in std_logic_vector;
Instruction : out std_logic_vector(17 downto 0)
);
end entity;
architecture rtl of picoblaze_rom is
constant MEM_SIZE : positive := 2 ** Address'length;
type rom_mem is array (0 to MEM_SIZE-1) of bit_vector(Instruction'length-1 downto 0);
impure function read_mem_file(File_name: string) return rom_mem is
-- Read a .mem or .hex file as produced by KCPSM3 and KCPSM6 assemblers
file fh : text open read_mode is File_name;
variable ln : line;
variable word : std_logic_vector(Instruction'length-1 downto 0);
variable rom : rom_mem;
procedure read_hex(ln : inout line; hex : out std_logic_vector) is
-- The hread() procedure doesn't work well when the target bit vector
-- is not a multiple of four. This wrapper provides better behavior.
variable hex4 : std_logic_vector(((hex'length + 3) / 4) * 4 - 1 downto 0);
begin
hread(ln, hex4);
hex := hex4(hex'length-1 downto 0); -- Trim upper bits
end procedure;
-- Convert a string to lower case
function to_lower( source : string ) return string is
variable r : string(source'range) := source;
begin
for c in r'range loop
if character'pos(r(c)) >= character'pos('A')
or character'pos(r(c)) <= character'pos('Z') then
-- This would work except that XST has regressed into not supporting
-- character'val. Presumably this is "fixed" in Vivado and will never get
-- corrected in poor old XST.
r(c) := character'val(character'pos(r(c)) + 16#20#);
end if;
end loop;
return r;
end function;
begin
-- Can't call to_lower() for case-insensitive comparison because of XST limitation
--if to_lower(File_name(File_name'length-3 to File_name'length)) = ".mem" then
if File_name(File_name'length-3 to File_name'length) = ".mem" then
-- Read the first address line of a .mem file and discard it
-- Assume memory starts at 0
readline(fh, ln);
end if;
-- XST isn't happy with a while loop because of its low default iteration limit setting
-- so we have to use a for loop.
for addr in 0 to MEM_SIZE-1 loop
if endfile(fh) then
exit;
end if;
readline(fh, ln);
read_hex(ln, word); -- Convert hex string to bits
rom(addr) := to_bitvector(word);
end loop;
return rom;
end function;
-- Initialize ROM with file contents
signal pb_rom : rom_mem := read_mem_file(ROM_FILE);
attribute RAM_STYLE : string;
attribute RAM_STYLE of pb_rom : signal is STYLE;
begin
-- Infer BRAM-based ROM with synchronous enable and read port
rd: process(Clock)
begin
if rising_edge(Clock) then
if Enable = '1' then
Instruction <= to_stdlogicvector(pb_rom(to_integer(unsigned(Address))));
end if;
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity picoblaze_dp_rom is
generic (
ROM_FILE : string; -- ROM memory contents in .mem or .hex format
STYLE : string := "BLOCK" -- Set to "DISTRIBUTED" to use distributed RAM
);
port (
Clock : in std_logic;
Enable : in std_logic;
Address : in std_logic_vector;
Instruction : out std_logic_vector(17 downto 0);
-- Second Read/Write port
Address2 : in std_logic_vector;
Instruction2 : out std_logic_vector(17 downto 0);
We : in std_logic;
Wr_instruction2 : in std_logic_vector(17 downto 0)
);
end entity;
architecture rtl of picoblaze_dp_rom is
constant MEM_SIZE : positive := 2 ** Address'length;
type rom_mem is array (0 to MEM_SIZE-1) of bit_vector(Instruction'length-1 downto 0);
impure function read_mem_file(File_name: string) return rom_mem is
-- Read a .mem or .hex file as produced by KCPSM3 and KCPSM6 assemblers
file fh : text open read_mode is File_name;
variable ln : line;
variable word : std_logic_vector(Instruction'length-1 downto 0);
variable rom : rom_mem;
procedure read_hex(ln : inout line; hex : out std_logic_vector) is
-- The hread() procedure doesn't work well when the target bit vector
-- is not a multiple of four. This wrapper provides better behavior.
variable hex4 : std_logic_vector(((hex'length + 3) / 4) * 4 - 1 downto 0);
begin
hread(ln, hex4);
hex := hex4(hex'length-1 downto 0); -- Trim upper bits
end procedure;
-- Convert a string to lower case
function to_lower( source : string ) return string is
variable r : string(source'range) := source;
begin
for c in r'range loop
if character'pos(r(c)) >= character'pos('A')
or character'pos(r(c)) <= character'pos('Z') then
-- This would work except that XST has regressed into not supporting
-- character'val. Presumably this is "fixed" in Vivado and will never get
-- corrected in poor old XST.
r(c) := character'val(character'pos(r(c)) + 16#20#);
end if;
end loop;
return r;
end function;
begin
-- Can't call to_lower() for case-insensitive comparison because of XST limitation
--if to_lower(File_name(File_name'length-3 to File_name'length)) = ".mem" then
if File_name(File_name'length-3 to File_name'length) = ".mem" then
-- Read the first address line of a .mem file and discard it
-- Assume memory starts at 0
readline(fh, ln);
end if;
-- XST isn't happy with a while loop because of its low default iteration limit setting
-- so we have to use a for loop.
for addr in 0 to MEM_SIZE-1 loop
if endfile(fh) then
exit;
end if;
readline(fh, ln);
read_hex(ln, word); -- Convert hex string to bits
rom(addr) := to_bitvector(word);
end loop;
return rom;
end function;
-- Initialize ROM with file contents
signal pb_rom : rom_mem := read_mem_file(ROM_FILE);
attribute RAM_STYLE : string;
attribute RAM_STYLE of pb_rom : signal is STYLE;
begin
-- Infer ROM with synchronous enable and dual read port
rd: process(Clock)
begin
if rising_edge(Clock) then
if Enable = '1' then
-- Read port 1
Instruction <= to_stdlogicvector(pb_rom(to_integer(unsigned(Address))));
-- Read/write port 2
Instruction2 <= to_stdlogicvector(pb_rom(to_integer(unsigned(Address2))));
if We = '1' then
pb_rom(to_integer(unsigned(Address2))) <= to_bitvector(Wr_instruction2);
end if;
end if;
end if;
end process;
end architecture;
|
----- Libraries------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----- Entity ------
entity multi_counter is
port( clk, reset : in std_logic;
count : out std_logic_vector(3 downto 0);
cout : out std_logic_vector(0 downto 0);
mode : in std_logic_vector(17 downto 16)
);
end multi_counter;
-----Architecture-----
architecture counter of multi_counter is
signal num : unsigned(3 downto 0) := "0000";
begin
po: process(clk, reset)
begin
if reset = '0' then
num <= "0000";
cout <= "0";
elsif rising_edge(clk) then
case mode is
when "00" =>
if num < "1001" then
num <= num + "0001";
cout <= "0";
else
num <= "0000";
cout <= "1";
end if;
when "01" =>
if num < "0101" then
num <= num + "0001";
cout <= "0";
else
num <= "0000";
cout <= "1";
end if;
when others =>
if num < "0010" then
num <= num + "0001";
cout <= "0";
else
num <= "0000";
cout <= "1";
end if;
end case;
else
null;
end if;
end process po;
count <= std_logic_vector(num);
end counter; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcitb_monitor
-- File: pcitb_monitor.vhd
-- Author:
-- Description: PCI Monitor.
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.pt_pkg.all;
library grlib;
use grlib.stdlib.xorv;
entity pt_pci_monitor is
generic (dbglevel : integer := 1);
port (pciin : in pci_type);
end pt_pci_monitor;
architecture tb of pt_pci_monitor is
constant T_O : integer := 9;
type pci_array_type is array(0 to 2) of pci_type;
type reg_type is record
pci : pci_array_type;
frame_deass : boolean;
m_wait_data_phase : boolean;
t_wait_data_phase : boolean;
stop_asserted : boolean;
device_sel : boolean;
first : boolean;
current_master : integer;
master_cnt : integer;
irdy_cnt : integer;
trdy_cnt : integer;
end record;
signal r,rin : reg_type;
signal init_done : boolean := false;
begin
init : process
begin
if init_done = false then
wait until pciin.syst.rst = '0';
wait until pciin.syst.rst = '1';
init_done <= true;
else
wait until pciin.syst.rst = '0';
init_done <= false;
end if;
end process;
comb : process(pciin)
variable i : integer;
variable v : reg_type;
begin
v := r;
v.pci(0) := pciin; v.pci(1) := r.pci(0); v.pci(2) := r.pci(1);
if r.pci(0).ifc.frame = 'H' then v.frame_deass := false;
elsif (r.pci(0).ifc.frame and not r.pci(1).ifc.frame) = '1' then v.frame_deass := true; end if;
if ((r.pci(0).ifc.trdy and r.pci(0).ifc.stop) or r.pci(0).ifc.irdy) = '0' then v.m_wait_data_phase := false;
elsif r.pci(0).ifc.irdy = '0' then v.m_wait_data_phase := true; end if;
if ((r.pci(0).ifc.trdy and r.pci(0).ifc.stop) or r.pci(0).ifc.irdy) = '0' then v.t_wait_data_phase := false;
elsif (r.pci(0).ifc.trdy and r.pci(0).ifc.stop) = '0' then v.t_wait_data_phase := true; end if;
if r.pci(0).ifc.frame = '0' and r.pci(1).ifc.frame = 'H' then
for i in 0 to 20 loop
if r.pci(0).arb.gnt(i) = '0' then v.current_master := i; end if;
end loop;
end if;
if (r.pci(0).ifc.frame and r.pci(0).ifc.irdy) = '0' then
if (r.pci(0).ifc.trdy and r.pci(0).ifc.stop) = '1' then
v.master_cnt := r.master_cnt+1;
else v.master_cnt := 0; end if;
else v.master_cnt := 0; end if;
if (r.pci(0).ifc.irdy and not r.pci(0).ifc.frame) = '1' then
v.irdy_cnt := r.irdy_cnt+1;
else v.irdy_cnt := 0; end if;
if ((r.pci(0).ifc.trdy and r.pci(0).ifc.stop) and not (r.pci(0).ifc.frame and r.pci(0).ifc.irdy)) = '1' then
v.trdy_cnt := r.trdy_cnt+1;
else v.trdy_cnt := 0; end if;
if r.pci(0).ifc.devsel = '0' then v.device_sel := true;
elsif (to_x01(r.pci(1).ifc.devsel) and not (r.pci(0).ifc.frame and r.pci(0).ifc.irdy)) = '1' then v.device_sel := false; end if;
if r.pci(0).ifc.stop = '0' then v.stop_asserted := true;
elsif r.pci(0).ifc.frame = '0' then v.stop_asserted := false; end if;
if (r.pci(1).ifc.frame = 'H' and r.pci(0).ifc.frame = '0') then v.first := true;
elsif (r.pci(0).ifc.trdy and r.pci(0).ifc.stop) = '0' then v.first := false; end if;
rin <= v;
end process;
clkprc : process(pciin.syst)
begin
if rising_edge(pciin.syst.clk) then
r <= rin;
if init_done then
if (r.pci(0).ifc.frame = '0' and r.frame_deass = true) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: FRAME# was reasserted during the same transaction.");
end if;
end if;
if (r.pci(0).ifc.frame and r.pci(0).ifc.irdy and not r.pci(1).ifc.frame) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: FRAME# was deasserted without IRDY# asserted.");
end if;
end if;
if (r.m_wait_data_phase and r.device_sel) then
if (r.pci(0).ifc.frame /= r.pci(1).ifc.frame) or (r.pci(0).ifc.irdy /= r.pci(1).ifc.irdy) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current master changed IRDY# or FRAME# before current data phase was completed.");
end if;
end if;
end if;
if ((r.pci(1).ifc.irdy and r.pci(1).ifc.frame and not r.pci(2).ifc.irdy) = '1' and r.stop_asserted = true) then
if not ((r.pci(1).arb.req(r.current_master) and (r.pci(0).arb.req(r.current_master) or r.pci(2).arb.req(r.current_master))) = '1') then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current master at slot %d did not release its REQ# when the bus returned to idle state.",r.current_master);
end if;
end if;
end if;
if (r.pci(0).ifc.stop and not r.pci(1).ifc.stop and not r.pci(0).ifc.frame) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not keep STOP# asserted until FRAME# was deasserted.");
end if;
end if;
if (r.pci(0).ifc.frame and r.pci(1).ifc.frame and not r.pci(0).ifc.stop and not r.pci(1).ifc.stop) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not release STOP# after FRAME# was deasserted.");
end if;
end if;
if r.t_wait_data_phase = true then
if (r.pci(0).ifc.devsel /= r.pci(1).ifc.devsel) or (r.pci(0).ifc.trdy /= r.pci(1).ifc.trdy) or (r.pci(0).ifc.stop /= r.pci(1).ifc.stop) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current target changed DEVSEL#, STOP# or TRDY# before current data phase was completed.");
end if;
end if;
end if;
if (r.pci(0).ifc.frame and r.pci(0).ifc.stop and not r.pci(1).ifc.frame and not r.pci(1).ifc.stop) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not keep STOP# asserted until the last data phase.");
end if;
end if;
if (r.pci(2).ifc.frame and not (r.pci(2).ifc.trdy and r.pci(2).ifc.stop)) = '1' then
if r.pci(1).ifc.irdy = '0' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master kept IRDY# asserted after last data phase.");
end if;
end if;
if r.pci(1).ifc.trdy = '0' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target kept TRDY# asserted after last data phase.");
end if;
end if;
if r.pci(1).ifc.stop = '0' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target kept STOP# asserted after last data phase.");
end if;
end if;
if r.pci(1).ifc.frame /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master did not tri-state FRAME# after turn-around cycle.");
end if;
end if;
if r.pci(0).ifc.irdy /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master did not tri-state IRDY# after turn-around cycle.");
end if;
end if;
if r.pci(0).ifc.trdy /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not tri-state TRDY# after turn-around cycle.");
end if;
end if;
if r.pci(0).ifc.stop /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not tri-state STOP# after turn-around cycle.");
end if;
end if;
end if;
if (r.master_cnt > 16 and r.first = true) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not complete its initial data phase in 16 clkc.");
end if;
end if;
if r.irdy_cnt > 8 then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master did not complete its initial data phase in 8 clkc.");
end if;
end if;
if (r.trdy_cnt > 8 and r.device_sel = true and r.first = false) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not complete a data phase in 8 clkc.");
end if;
end if;
if not r.device_sel then
if (r.pci(0).ifc.irdy and not r.pci(1).ifc.irdy) = '1' then
if dbglevel > 0 then
assert false
report "**"
severity note;
printf("PCI_MONITOR: Master abort detected.");
end if;
end if;
end if;
if ((r.pci(1).ifc.irdy = 'H' and r.pci(1).ifc.frame = '0')
or (r.pci(1).ifc.irdy or r.pci(1).ifc.trdy) = '0') then
if r.pci(0).ad.par = 'Z' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current Master/Target is not generating parity during a data phase.");
end if;
elsif r.pci(0).ad.par /= xorv(r.pci(1).ad.ad & r.pci(1).ad.cbe) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Parity error detected.");
end if;
end if;
end if;
end if;
end if;
end process;
adchk : process(pciin.ad)
begin
if init_done then
-- for i in 0 to 31 loop
-- if pciin.ad.ad(i) = 'X' then
-- if dbglevel > 0 then
-- assert false
-- report " **"
-- severity warning;
-- printf("PCI_MONITOR: AD lines have multiple drivers.");
-- end if;
-- end if;
-- end loop;
for i in 0 to 3 loop
if pciin.ad.cbe(i) = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: CBE# lines have multiple drivers.");
end if;
end if;
end loop;
-- if pciin.ad.par = 'X' then
-- if dbglevel > 0 then
-- assert false
-- report " **"
-- severity warning;
-- printf("PCI_MONITOR: PAR line has multiple drivers.");
-- end if;
-- end if;
end if;
end process;
ifcchk : process(pciin.ifc)
begin
if init_done then
if pciin.ifc.frame = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: FRAME# line has multiple drivers.");
end if;
end if;
if pciin.ifc.irdy = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: IRDY# line has multiple drivers.");
end if;
end if;
if pciin.ifc.trdy = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: TRDY# line has multiple drivers.");
end if;
end if;
if pciin.ifc.stop = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: STOP# line has multiple drivers.");
end if;
end if;
if pciin.ifc.devsel = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: DEVSEL# line has multiple drivers.");
end if;
end if;
end if;
end process;
arbchk : process(pciin.arb)
variable gnt_set : boolean;
begin
gnt_set := false;
if init_done then
for i in 0 to 20 loop
if pciin.arb.gnt(i) = '0' then
if gnt_set then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: GNT# is asserted for more than one PCI master.");
end if;
else gnt_set := true; end if;
end if;
end loop;
end if;
end process;
end;
-- pragma translate_on
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ims;
use ims.coprocessor.all;
ENTITY INTERFACE_COMB_3 IS
PORT (
inp : IN custom32_in_type;
outp : OUT custom32_out_type
);
END;
ARCHITECTURE RTL OF INTERFACE_COMB_3 IS
-------------------------------------------------------------------------
-- PRAGMA BEGIN DECLARATION
-- PRAGMA END DECLARATION
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- PRAGMA BEGIN SIGNAL
-- PRAGMA END SIGNAL
-------------------------------------------------------------------------
BEGIN
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
WAIT FOR 1 ns;
printmsg("(IMS) INTERFACE_COMB_3 : ALLOCATION OK !");
WAIT;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- PRAGMA BEGIN INSTANCIATION
-- PRAGMA END INSTANCIATION
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- PRAGMA BEGIN RESULT SELECTION
outp.result <= inp.op1(31 downto 0) AND inp.op2(31 downto 0);
-- PRAGMA END RESULT SELECTION
-------------------------------------------------------------------------
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TLC is
Port (
-- The crystal:
CLK : in STD_LOGIC;
-- LED:
LED : out STD_LOGIC_VECTOR ( 7 downto 0);
-- VGA Connector
R : out STD_LOGIC_VECTOR ( 2 downto 0);
G : out STD_LOGIC_VECTOR ( 2 downto 0);
B : out STD_LOGIC_VECTOR ( 1 downto 0);
HS : out STD_LOGIC;
VS : out STD_LOGIC;
-- Memory Bus:
ADDR : out STD_LOGIC_VECTOR (23 downto 0);
DATA : inout STD_LOGIC_VECTOR (15 downto 0);
OE : out STD_LOGIC := '1';
WE : out STD_LOGIC := '1';
MT_ADV : out STD_LOGIC := '0';
MT_CLK : out STD_LOGIC := '0';
MT_UB : out STD_LOGIC := '1';
MT_LB : out STD_LOGIC := '1';
MT_CE : out STD_LOGIC := '1';
MT_CRE : out STD_LOGIC := '0';
MT_WAIT : in STD_LOGIC := '0';
ST_STS : in STD_LOGIC := '0';
RP : out STD_LOGIC := '1';
ST_CE : out STD_LOGIC := '1';
-- PS/2 port:
PS2CLK : in STD_LOGIC := '0';
PS2DATA : in STD_LOGIC := '0'
);
end TLC;
architecture Structural of TLC is
component cpu is
Port (
CLK : in STD_LOGIC;
IRQ : in STD_LOGIC;
NMI : in STD_LOGIC;
IAK : out STD_LOGIC;
NAK : out STD_LOGIC;
-- system bus
MEME : out STD_LOGIC;
RW : out STD_LOGIC;
ADDR : out STD_LOGIC_VECTOR (31 downto 0);
Din : in STD_LOGIC_VECTOR (31 downto 0);
Dout : out STD_LOGIC_VECTOR (31 downto 0);
DTYPE : out STD_LOGIC_VECTOR ( 2 downto 0);
RDY : in STD_LOGIC
);
end component;
component memif is
Port (
CLK : in STD_LOGIC;
-- Interface
RAM_CS : in STD_LOGIC; -- RAM chip enable
ROM_CS : in STD_LOGIC; -- ROM chip enable
RW : in STD_LOGIC; -- 0: read, 1: write
A : in STD_LOGIC_VECTOR (23 downto 0);
Din : in STD_LOGIC_VECTOR (31 downto 0);
Dout : out STD_LOGIC_VECTOR (31 downto 0);
DTYPE : in STD_LOGIC_VECTOR ( 2 downto 0);
RDY : out STD_LOGIC;
-- External Memory Bus:
ADDR : out STD_LOGIC_VECTOR (23 downto 0);
DATA : inout STD_LOGIC_VECTOR (15 downto 0);
OE : out STD_LOGIC := '1'; -- active low
WE : out STD_LOGIC := '1'; -- active low
MT_ADV : out STD_LOGIC := '0'; -- active low
MT_CLK : out STD_LOGIC := '0';
MT_UB : out STD_LOGIC := '1'; -- active low
MT_LB : out STD_LOGIC := '1'; -- active low
MT_CE : out STD_LOGIC := '1'; -- active low
MT_CRE : out STD_LOGIC := '0'; -- active high
MT_WAIT : in STD_LOGIC;
ST_STS : in STD_LOGIC;
RP : out STD_LOGIC := '1'; -- active low
ST_CE : out STD_LOGIC := '1' -- active low
);
end component;
component vga is
Port ( CLK : in STD_LOGIC; -- 50MHz clock input
-- System Bus
CS : in STD_LOGIC;
RW : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (13 downto 0);
Din : in STD_LOGIC_VECTOR (15 downto 0);
Dout : out STD_LOGIC_VECTOR (15 downto 0);
RDY : out STD_LOGIC := '0';
INT : out STD_LOGIC := '0';
IAK : in STD_LOGIC;
-- VGA Port
R : out STD_LOGIC_VECTOR (2 downto 0);
G : out STD_LOGIC_VECTOR (2 downto 0);
B : out STD_LOGIC_VECTOR (1 downto 0);
HS : out STD_LOGIC;
VS : out STD_LOGIC);
end component;
component kbdctl is
Port (
-- Crystal:
CLK : in STD_LOGIC;
-- Inputs from PS/2 keyboard:
PS2CLK : in STD_LOGIC;
PS2DATA : in STD_LOGIC;
-- Output:
LED : out STD_LOGIC_VECTOR (7 downto 0);
-- System bus interface:
EN : in STD_LOGIC;
RW : in STD_LOGIC;
DATA : out STD_LOGIC_VECTOR (7 downto 0);
RDY : out STD_LOGIC;
-- Interrupt Logic:
INT : out STD_LOGIC;
IAK : in STD_LOGIC
);
end component;
component pit is
Port (
CLK : in STD_LOGIC;
IRQ : out STD_LOGIC;
IAK : in STD_LOGIC;
CS : in STD_LOGIC;
RW : in STD_LOGIC; -- 0: read, 1: write
Din : in STD_LOGIC_VECTOR (31 downto 0);
Dout : out STD_LOGIC_VECTOR (31 downto 0);
DTYPE : in STD_LOGIC_VECTOR ( 2 downto 0);
RDY : out STD_LOGIC := '1');
end component;
component pic is
Port (
CLK : in STD_LOGIC;
IRQ_in : in STD_LOGIC_VECTOR (7 downto 0);
IAK_out : out STD_LOGIC_VECTOR (7 downto 0);
IRQ_out : out STD_LOGIC := '0';
IAK_in : in STD_LOGIC;
CS : in STD_LOGIC;
RW : in STD_LOGIC; -- 0: read, 1: write
Din : in STD_LOGIC_VECTOR (31 downto 0);
Dout : out STD_LOGIC_VECTOR (31 downto 0);
DTYPE : in STD_LOGIC_VECTOR ( 2 downto 0);
RDY : out STD_LOGIC := '1'
);
end component;
-- CPU signals
signal IRQ : STD_LOGIC := '0';
signal NMI : STD_LOGIC := '0';
signal IAK : STD_LOGIC := '0';
signal NAK : STD_LOGIC := '0';
-- System bus:
signal MEME : STD_LOGIC := '0';
signal RW : STD_LOGIC := '0';
signal Address : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DataCPUToMem : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DataMemToCPU : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DataRAMToCPU : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DataVGAToCPU : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DataKBDToCPU : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DataPITToCPU : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DataPICToCPU : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DTYPE : STD_LOGIC_VECTOR ( 2 downto 0) := "000";
signal RAM_CS : STD_LOGIC := '0';
signal ROM_CS : STD_LOGIC := '0';
signal VGA_CS : STD_LOGIC := '0';
signal KBD_CS : STD_LOGIC := '0';
signal PIT_CS : STD_LOGIC := '0';
signal PIC_CS : STD_LOGIC := '0';
signal MEM_RDY : STD_LOGIC := '0';
signal VGA_RDY : STD_LOGIC := '0';
signal KBD_RDY : STD_LOGIC := '0';
signal PIT_RDY : STD_LOGIC := '0';
signal PIC_RDY : STD_LOGIC := '0';
signal RDY : STD_LOGIC := '0';
signal IRQ_to_PIC : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal IAK_from_PIC : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
begin
------------- memory map -------------
-- 0x00000000 - 0x00FFFFFF : RAM
-- 0x1E000000 - 0x1E003FFF : VGA
-- 0x1E800000 - 0x1E800FFF : KBD
-- 0x1E801000 - 0x1E801FFF : PIT
-- 0x1E802000 - 0x1E802FFF : PIC
-- 0x1EC02000 - 0x1EC02007 : PPU
-- 0x1F000000 - 0x1FFFFFFF : ROM
-- memory decoding
RAM_CS <= MEME when Address(31 downto 24) = x"00" else '0';
ROM_CS <= MEME when Address(31 downto 24) = x"1F" else '0';
VGA_CS <= MEME when Address(31 downto 14) = x"1E00"&"00" or
Address(31 downto 12) = x"1EC02" else '0';
KBD_CS <= MEME when Address(31 downto 12) = x"1E800" else '0';
PIT_CS <= MEME when Address(31 downto 12) = x"1E801" else '0';
PIC_CS <= MEME when Address(31 downto 12) = x"1E802" else '0';
DataMemToCPU <= DataRAMToCPU when ROM_CS = '1' or RAM_CS = '1' else
DataVGAToCPU when VGA_CS = '1' else
DataKBDToCPU when KBD_CS = '1' else
DataPITToCPU when PIT_CS = '1' else
DataPICToCPU when PIC_CS = '1' else
x"00000000";
RDY <= MEM_RDY when ROM_CS = '1' or RAM_CS = '1' else
VGA_RDY when VGA_CS = '1' else
KBD_RDY when KBD_CS = '1' else
PIT_RDY when PIT_CS = '1' else
PIC_RDY when PIC_CS = '1' else
'0';
-- subblocks
U1: cpu port map (CLK, IRQ, NMI, IAK, NAK,
MEME, RW, Address, DataMemToCPU, DataCPUToMem, DTYPE, RDY);
U2: memif port map (CLK,
RAM_CS, ROM_CS, RW, Address(23 downto 0),
DataCPUToMem(31 downto 0), DataRAMToCPU(31 downto 0),
DTYPE, MEM_RDY, ADDR, DATA, OE, WE,
MT_ADV, MT_CLK, MT_UB, MT_LB, MT_CE, MT_CRE, MT_WAIT,
ST_STS, RP, ST_CE);
U3: vga port map (CLK, VGA_CS, RW,
Address(13 downto 0), DataCPUToMem(15 downto 0),
DataVGAToCPU(15 downto 0), VGA_RDY,
IRQ_to_PIC(3), IAK_from_PIC(3),
R, G, B, HS, VS);
U4: kbdctl port map (CLK, PS2CLK, PS2DATA, LED,
KBD_CS, RW, DataKBDToCPU(7 downto 0), KBD_RDY,
IRQ_to_PIC(1), IAK_from_PIC(1));
U5: pit port map (CLK, IRQ_to_PIC(0), IAK_from_PIC(0),
PIT_CS, RW, DataCPUToMem, DataPITToCPU, DTYPE, PIT_RDY);
U6: pic port map (CLK, IRQ_to_PIC, IAK_from_PIC, IRQ, IAK,
PIC_CS, RW, DataCPUToMem, DataPICToCPU, DTYPE, PIC_RDY);
end Structural;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc486.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00486ent IS
END c03s02b01x01p19n01i00486ent;
ARCHITECTURE c03s02b01x01p19n01i00486arch OF c03s02b01x01p19n01i00486ent IS
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type column is range 1 to 2;
type row is range 1 to 8;
type s2boolean_cons_vector is array (row,column) of boolean;
type s2bit_cons_vector is array (row,column) of bit;
type s2char_cons_vector is array (row,column) of character;
type s2severity_level_cons_vector is array (row,column) of severity_level;
type s2integer_cons_vector is array (row,column) of integer;
type s2real_cons_vector is array (row,column) of real;
type s2time_cons_vector is array (row,column) of time;
type s2natural_cons_vector is array (row,column) of natural;
type s2positive_cons_vector is array (row,column) of positive;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector ;
type real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_2cons_array is record
a:s2boolean_cons_vector;
b:s2bit_cons_vector;
c:s2char_cons_vector;
d:s2severity_level_cons_vector;
e:s2integer_cons_vector;
f:s2real_cons_vector;
g:s2time_cons_vector;
h:s2natural_cons_vector;
i:s2positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
e: record_2cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
end record;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C41 : s2boolean_cons_vector := (others => (others => C1));
constant C42 : s2bit_cons_vector := (others => (others => C2));
constant C43 : s2char_cons_vector := (others => (others => C3));
constant C44 : s2severity_level_cons_vector := (others => (others => C4));
constant C45 : s2integer_cons_vector := (others => (others => C5));
constant C46 : s2real_cons_vector := (others => (others => C6));
constant C47 : s2time_cons_vector := (others => (others => C7));
constant C48 : s2natural_cons_vector := (others => (others => C8));
constant C49 : s2positive_cons_vector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st :=(others => C4);
constant C72 : integer_vector_st :=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st :=(others => C8);
constant C76 : positive_vector_st :=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C52,C53,C77);
type array_rec_rec is array (integer range <>) of record_of_records;
function resolution13(i:in array_rec_rec) return record_of_records is
variable temp : record_of_records :=C55 ;
begin
return temp;
end resolution13;
subtype array_rec_rec_state is resolution13 record_of_records;
constant C66 : array_rec_rec_state := C55;
function complex_scalar(s : array_rec_rec_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return array_rec_rec_state is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : array_rec_rec_state;
signal S2 : array_rec_rec_state;
signal S3 : array_rec_rec_state:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00486"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00486 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00486arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc486.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00486ent IS
END c03s02b01x01p19n01i00486ent;
ARCHITECTURE c03s02b01x01p19n01i00486arch OF c03s02b01x01p19n01i00486ent IS
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type column is range 1 to 2;
type row is range 1 to 8;
type s2boolean_cons_vector is array (row,column) of boolean;
type s2bit_cons_vector is array (row,column) of bit;
type s2char_cons_vector is array (row,column) of character;
type s2severity_level_cons_vector is array (row,column) of severity_level;
type s2integer_cons_vector is array (row,column) of integer;
type s2real_cons_vector is array (row,column) of real;
type s2time_cons_vector is array (row,column) of time;
type s2natural_cons_vector is array (row,column) of natural;
type s2positive_cons_vector is array (row,column) of positive;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector ;
type real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_2cons_array is record
a:s2boolean_cons_vector;
b:s2bit_cons_vector;
c:s2char_cons_vector;
d:s2severity_level_cons_vector;
e:s2integer_cons_vector;
f:s2real_cons_vector;
g:s2time_cons_vector;
h:s2natural_cons_vector;
i:s2positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
e: record_2cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
end record;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C41 : s2boolean_cons_vector := (others => (others => C1));
constant C42 : s2bit_cons_vector := (others => (others => C2));
constant C43 : s2char_cons_vector := (others => (others => C3));
constant C44 : s2severity_level_cons_vector := (others => (others => C4));
constant C45 : s2integer_cons_vector := (others => (others => C5));
constant C46 : s2real_cons_vector := (others => (others => C6));
constant C47 : s2time_cons_vector := (others => (others => C7));
constant C48 : s2natural_cons_vector := (others => (others => C8));
constant C49 : s2positive_cons_vector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st :=(others => C4);
constant C72 : integer_vector_st :=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st :=(others => C8);
constant C76 : positive_vector_st :=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C52,C53,C77);
type array_rec_rec is array (integer range <>) of record_of_records;
function resolution13(i:in array_rec_rec) return record_of_records is
variable temp : record_of_records :=C55 ;
begin
return temp;
end resolution13;
subtype array_rec_rec_state is resolution13 record_of_records;
constant C66 : array_rec_rec_state := C55;
function complex_scalar(s : array_rec_rec_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return array_rec_rec_state is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : array_rec_rec_state;
signal S2 : array_rec_rec_state;
signal S3 : array_rec_rec_state:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00486"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00486 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00486arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc486.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00486ent IS
END c03s02b01x01p19n01i00486ent;
ARCHITECTURE c03s02b01x01p19n01i00486arch OF c03s02b01x01p19n01i00486ent IS
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type column is range 1 to 2;
type row is range 1 to 8;
type s2boolean_cons_vector is array (row,column) of boolean;
type s2bit_cons_vector is array (row,column) of bit;
type s2char_cons_vector is array (row,column) of character;
type s2severity_level_cons_vector is array (row,column) of severity_level;
type s2integer_cons_vector is array (row,column) of integer;
type s2real_cons_vector is array (row,column) of real;
type s2time_cons_vector is array (row,column) of time;
type s2natural_cons_vector is array (row,column) of natural;
type s2positive_cons_vector is array (row,column) of positive;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector ;
type real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_2cons_array is record
a:s2boolean_cons_vector;
b:s2bit_cons_vector;
c:s2char_cons_vector;
d:s2severity_level_cons_vector;
e:s2integer_cons_vector;
f:s2real_cons_vector;
g:s2time_cons_vector;
h:s2natural_cons_vector;
i:s2positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
e: record_2cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
end record;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C41 : s2boolean_cons_vector := (others => (others => C1));
constant C42 : s2bit_cons_vector := (others => (others => C2));
constant C43 : s2char_cons_vector := (others => (others => C3));
constant C44 : s2severity_level_cons_vector := (others => (others => C4));
constant C45 : s2integer_cons_vector := (others => (others => C5));
constant C46 : s2real_cons_vector := (others => (others => C6));
constant C47 : s2time_cons_vector := (others => (others => C7));
constant C48 : s2natural_cons_vector := (others => (others => C8));
constant C49 : s2positive_cons_vector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st :=(others => C4);
constant C72 : integer_vector_st :=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st :=(others => C8);
constant C76 : positive_vector_st :=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C52,C53,C77);
type array_rec_rec is array (integer range <>) of record_of_records;
function resolution13(i:in array_rec_rec) return record_of_records is
variable temp : record_of_records :=C55 ;
begin
return temp;
end resolution13;
subtype array_rec_rec_state is resolution13 record_of_records;
constant C66 : array_rec_rec_state := C55;
function complex_scalar(s : array_rec_rec_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return array_rec_rec_state is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : array_rec_rec_state;
signal S2 : array_rec_rec_state;
signal S3 : array_rec_rec_state:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00486"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00486 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00486arch;
|
-------------------------------------------------------------------------------
-- LPM 220 Component Declaration Package (Support string type generic)
-- These models are based on LPM version 220 (EIA-IS103 October 1998).
-------------------------------------------------------------------------------
-- Assumptions:
--
-- LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, and LPM_NUMWORDS, LPM_HINT,
-- LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE default value is
-- string "UNUSED".
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package LPM_COMPONENTS is
constant L_CONSTANT : string := "LPM_CONSTANT";
constant L_INV : string := "LPM_INV";
constant L_AND : string := "LPM_AND";
constant L_OR : string := "LPM_OR";
constant L_XOR : string := "LPM_XOR";
constant L_BUSTRI : string := "LPM_BUSTRI";
constant L_MUX : string := "LPM_MUX";
constant L_DECODE : string := "LPM_DECODE";
constant L_CLSHIFT : string := "LPM_CLSHIFT";
constant L_ADD_SUB : string := "LPM_ADD_SUB";
constant L_COMPARE : string := "LPM_COMPARE";
constant L_MULT : string := "LPM_MULT";
constant L_DIVIDE : string := "LPM_DIVIDE";
constant L_ABS : string := "LPM_ABS";
constant L_COUNTER : string := "LPM_COUNTER";
constant L_LATCH : string := "LPM_LATCH";
constant L_FF : string := "LPM_FF";
constant L_SHIFTREG : string := "LPM_SHIFTREG";
constant L_RAM_DQ : string := "LPM_RAM_DQ";
constant L_RAM_DP : string := "LPM_RAM_DP";
constant L_RAM_IO : string := "LPM_RAM_IO";
constant L_ROM : string := "LPM_ROM";
constant L_FIFO : string := "LPM_FIFO";
constant L_FIFO_DC : string := "LPM_FIFO_DC";
constant L_TTABLE : string := "LPM_TTABLE";
constant L_FSM : string := "LPM_FSM";
constant L_INPAD : string := "LPM_INPAD";
constant L_OUTPAD : string := "LPM_OUTPAD";
constant L_BIPAD : string := "LPM_BIPAD";
type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
------------------------------------------------------------------------
-- GATES ---------------------------------------------------------------
------------------------------------------------------------------------
component LPM_CONSTANT
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_CVALUE : natural;
LPM_STRENGTH : string := "UNUSED";
LPM_TYPE : string := L_CONSTANT;
LPM_HINT : string := "UNUSED");
port (RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_INV
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_TYPE : string := L_INV;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_AND
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_SIZE : natural; -- MUST be greater than 0
LPM_TYPE : string := L_AND;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_2D(LPM_SIZE-1 downto 0, LPM_WIDTH-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_OR
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_SIZE : natural; -- MUST be greater than 0
LPM_TYPE : string := L_OR;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_2D(LPM_SIZE-1 downto 0, LPM_WIDTH-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_XOR
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_SIZE : natural; -- MUST be greater than 0
LPM_TYPE : string := L_XOR;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_2D(LPM_SIZE-1 downto 0, LPM_WIDTH-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_BUSTRI
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_TYPE : string := L_BUSTRI;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ENABLEDT : in std_logic := '1';
ENABLETR : in std_logic := '1';
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
TRIDATA : inout std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_MUX
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_SIZE : natural; -- MUST be greater than 0
LPM_WIDTHS : natural; -- MUST be greater than 0
LPM_PIPELINE : natural := 0;
LPM_TYPE : string := L_MUX;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_2D(LPM_SIZE-1 downto 0, LPM_WIDTH-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
SEL : in std_logic_vector(LPM_WIDTHS-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_DECODE
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_DECODES : natural; -- MUST be greater than 0
LPM_PIPELINE : natural := 0;
LPM_TYPE : string := L_DECODE;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
ACLR : in std_logic := '0';
ENABLE : in std_logic := '1';
EQ : out std_logic_vector(LPM_DECODES-1 downto 0));
end component;
component LPM_CLSHIFT
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHDIST : natural; -- MUST be greater than 0
LPM_SHIFTTYPE : string := "LOGICAL";
LPM_PIPELINE : natural := 0;
LPM_TYPE : string := L_CLSHIFT;
LPM_HINT : string := "UNUSED");
port (DATA : in STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0);
DISTANCE : in STD_LOGIC_VECTOR(LPM_WIDTHDIST-1 downto 0);
DIRECTION : in STD_LOGIC := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
ACLR : in std_logic := '0';
RESULT : out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0);
UNDERFLOW : out STD_LOGIC;
OVERFLOW : out STD_LOGIC);
end component;
------------------------------------------------------------------------
-- ARITHMETIC COMPONENTS -----------------------------------------------
------------------------------------------------------------------------
component LPM_ADD_SUB
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_DIRECTION : string := "UNUSED";
LPM_REPRESENTATION: string := "SIGNED";
LPM_PIPELINE : natural := 0;
LPM_TYPE : string := L_ADD_SUB;
LPM_HINT : string := "UNUSED");
port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
CIN : in std_logic := 'Z';
ADD_SUB : in std_logic := '1';
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
COUT : out std_logic;
OVERFLOW : out std_logic);
end component;
component LPM_COMPARE
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_REPRESENTATION : string := "UNSIGNED";
LPM_PIPELINE : natural := 0;
LPM_TYPE: string := L_COMPARE;
LPM_HINT : string := "UNUSED");
port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
AGB : out std_logic;
AGEB : out std_logic;
AEB : out std_logic;
ANEB : out std_logic;
ALB : out std_logic;
ALEB : out std_logic);
end component;
component LPM_MULT
generic(LPM_WIDTHA : natural; -- MUST be greater than 0
LPM_WIDTHB : natural; -- MUST be greater than 0
LPM_WIDTHS : natural := 1;
LPM_WIDTHP : natural; -- MUST be greater than 0
LPM_REPRESENTATION : string := "UNSIGNED";
LPM_PIPELINE : natural := 0;
LPM_TYPE: string := L_MULT;
LPM_HINT : string := "UNUSED");
port (DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0) := (OTHERS => '0');
RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));
end component;
component LPM_DIVIDE
generic(LPM_WIDTHN : natural; -- MUST be greater than 0
LPM_WIDTHD : natural; -- MUST be greater than 0
LPM_NREPRESENTATION : string := "UNSIGNED";
LPM_DREPRESENTATION : string := "UNSIGNED";
LPM_PIPELINE : natural := 0;
LPM_TYPE : string := L_DIVIDE;
LPM_HINT : string := "LPM_REMAINDERPOSITIVE=TRUE");
port (NUMER : in std_logic_vector(LPM_WIDTHN-1 downto 0);
DENOM : in std_logic_vector(LPM_WIDTHD-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
QUOTIENT : out std_logic_vector(LPM_WIDTHN-1 downto 0);
REMAIN : out std_logic_vector(LPM_WIDTHD-1 downto 0));
end component;
component LPM_ABS
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_TYPE: string := L_ABS;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
OVERFLOW : out std_logic);
end component;
component LPM_COUNTER
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_MODULUS : natural := 0;
LPM_DIRECTION : string := "UNUSED";
LPM_AVALUE : string := "UNUSED";
LPM_SVALUE : string := "UNUSED";
LPM_PVALUE : string := "UNUSED";
LPM_PORT_UPDOWN : string := "PORT_CONNECTIVITY";
LPM_TYPE: string := L_COUNTER;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0):= (OTHERS => '0');
CLOCK : in std_logic ;
CLK_EN : in std_logic := '1';
CNT_EN : in std_logic := '1';
UPDOWN : in std_logic := '1';
SLOAD : in std_logic := '0';
SSET : in std_logic := '0';
SCLR : in std_logic := '0';
ALOAD : in std_logic := '0';
ASET : in std_logic := '0';
ACLR : in std_logic := '0';
CIN : in std_logic := '1';
COUT : out std_logic := '0';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
------------------------------------------------------------------------
-- STORAGE COMPONENTS --------------------------------------------------
------------------------------------------------------------------------
component LPM_LATCH
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_AVALUE : string := "UNUSED";
LPM_PVALUE : string := "UNUSED";
LPM_TYPE: string := L_LATCH;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0) := (OTHERS => '0');
GATE : in std_logic;
ASET : in std_logic := '0';
ACLR : in std_logic := '0';
ACONST : in std_logic := '0';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_FF
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_AVALUE : string := "UNUSED";
LPM_SVALUE : string := "UNUSED";
LPM_PVALUE : string := "UNUSED";
LPM_FFTYPE: string := "DFF";
LPM_TYPE: string := L_FF;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0) := (OTHERS => '1');
CLOCK : in std_logic;
ENABLE : in std_logic := '1';
SLOAD : in std_logic := '0';
SCLR : in std_logic := '0';
SSET : in std_logic := '0';
ALOAD : in std_logic := '0';
ACLR : in std_logic := '0';
ASET : in std_logic := '0';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_SHIFTREG
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_AVALUE : string := "UNUSED";
LPM_SVALUE : string := "UNUSED";
LPM_PVALUE : string := "UNUSED";
LPM_DIRECTION: string := "UNUSED";
LPM_TYPE: string := L_SHIFTREG;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0) := (OTHERS => '0');
CLOCK : in std_logic;
ENABLE : in std_logic := '1';
SHIFTIN : in std_logic := '1';
LOAD : in std_logic := '0';
SCLR : in std_logic := '0';
SSET : in std_logic := '0';
ACLR : in std_logic := '0';
ASET : in std_logic := '0';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0);
SHIFTOUT : out std_logic);
end component;
component LPM_RAM_DQ
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := L_RAM_DQ;
USE_EAB : string := "ON";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_RAM_DP
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_RDADDRESS_CONTROL : string := "REGISTERED";
LPM_WRADDRESS_CONTROL : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := L_RAM_DP;
USE_EAB : string := "ON";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
RDEN_USED : string := "TRUE";
LPM_HINT : string := "UNUSED");
port (RDCLOCK : in std_logic := '0';
RDCLKEN : in std_logic := '1';
RDADDRESS : in std_logic_vector(LPM_WIDTHad-1 downto 0);
RDEN : in std_logic := '1';
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
WRADDRESS : in std_logic_vector(LPM_WIDTHad-1 downto 0);
WREN : in std_logic;
WRCLOCK : in std_logic := '0';
WRCLKEN : in std_logic := '1';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_RAM_IO
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := L_RAM_IO;
INTENDED_DEVICE_FAMILY : string := "UNUSED";
USE_EAB : string := "ON";
LPM_HINT : string := "UNUSED");
port (ADDRESS : in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
INCLOCK : in STD_LOGIC := '0';
OUTCLOCK : in STD_LOGIC := '0';
MEMENAB : in STD_LOGIC := '1';
OUTENAB : in STD_LOGIC := 'Z';
WE : in STD_LOGIC := 'Z';
DIO : inout STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0));
end component;
component LPM_ROM
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string;
LPM_TYPE : string := L_ROM;
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port (ADDRESS : in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
INCLOCK : in STD_LOGIC := '0';
OUTCLOCK : in STD_LOGIC := '0';
MEMENAB : in STD_LOGIC := '1';
Q : out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0));
end component;
component LPM_FIFO
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHU : natural := 1; -- MUST be greater than 0
LPM_NUMWORDS : natural; -- MUST be greater than 0
LPM_SHOWAHEAD : string := "OFF";
LPM_TYPE : string := L_FIFO;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
CLOCK : in std_logic;
WRREQ : in std_logic;
RDREQ : in std_logic;
ACLR : in std_logic := '0';
SCLR : in std_logic := '0';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0);
USEDW : out std_logic_vector(LPM_WIDTHU-1 downto 0);
FULL : out std_logic;
EMPTY : out std_logic);
end component;
component LPM_FIFO_DC
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHU : natural := 1; -- MUST be greater than 0
LPM_NUMWORDS : natural; -- MUST be greater than 0
LPM_SHOWAHEAD : string := "OFF";
LPM_TYPE : string := L_FIFO_DC;
UNDERFLOW_CHECKING : string := "ON";
OVERFLOW_CHECKING : string := "ON";
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
WRCLOCK : in std_logic;
RDCLOCK : in std_logic;
WRREQ : in std_logic;
RDREQ : in std_logic;
ACLR : in std_logic := '0';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0);
WRUSEDW : out std_logic_vector(LPM_WIDTHU-1 downto 0);
RDUSEDW : out std_logic_vector(LPM_WIDTHU-1 downto 0);
WRFULL : out std_logic;
RDFULL : out std_logic;
WREMPTY : out std_logic;
RDEMPTY : out std_logic);
end component;
------------------------------------------------------------------------
-- TABLE PRIMITIVES ----------------------------------------------------
------------------------------------------------------------------------
component LPM_TTABLE
generic(LPM_WIDTHIN : natural; -- MUST be greater than 0
LPM_WIDTHOUT : natural; -- MUST be greater than 0
LPM_FILE : string;
LPM_TRUTHTYPE : string := "FD";
LPM_TYPE : string := L_TTABLE;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTHIN-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTHOUT-1 downto 0));
end component;
component LPM_FSM
generic(LPM_WIDTHIN : natural; -- MUST be greater than 0
LPM_WIDTHOUT : natural; -- MUST be greater than 0
LPM_WIDTHS : natural := 1; -- MUST be greater than 0
LPM_FILE : string ;
LPM_PVALUE : string := "UNUSED";
LPM_AVALUE : string := "UNUSED";
LPM_TRUTHTYPE : string := "FD";
LPM_TYPE : string := L_FSM;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTHIN-1 downto 0);
CLOCK : in std_logic;
ASET : in std_logic := '0';
TESTENAB : in std_logic := '0';
TESTIN : in std_logic := '0';
TESTOUT : out std_logic;
STATE : out std_logic_vector(LPM_WIDTHS-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTHOUT-1 downto 0));
end component;
------------------------------------------------------------------------
-- PAD PRIMITIVES ------------------------------------------------------
------------------------------------------------------------------------
component LPM_INPAD
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_TYPE : string := L_INPAD;
LPM_HINT : string := "UNUSED");
port (PAD : in std_logic_vector(LPM_WIDTH-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_OUTPAD
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_TYPE : string := L_OUTPAD;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
PAD : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_BIPAD
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_TYPE : string := L_BIPAD;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ENABLE : in std_logic;
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
PAD : inout std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1319.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p08n01i01319ent IS
END c08s04b00x00p08n01i01319ent;
ARCHITECTURE c08s04b00x00p08n01i01319arch OF c08s04b00x00p08n01i01319ent IS
type aggsig is array (1 to 4) of bit;
signal S : aggsig;
signal S1 : bit;
signal S2 : bit;
signal S3 : bit;
signal S4 : bit;
BEGIN
TESTING: PROCESS
BEGIN
S <= (bit'('0'), bit'('1'), bit'('0'),bit'('1'));
(S1, S2, S1, S4) <= S;
assert FALSE
report "***FAILED TEST: c08s04b00x00p08n01i01319 - Signal is identified as target more than once in the same assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p08n01i01319arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1319.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p08n01i01319ent IS
END c08s04b00x00p08n01i01319ent;
ARCHITECTURE c08s04b00x00p08n01i01319arch OF c08s04b00x00p08n01i01319ent IS
type aggsig is array (1 to 4) of bit;
signal S : aggsig;
signal S1 : bit;
signal S2 : bit;
signal S3 : bit;
signal S4 : bit;
BEGIN
TESTING: PROCESS
BEGIN
S <= (bit'('0'), bit'('1'), bit'('0'),bit'('1'));
(S1, S2, S1, S4) <= S;
assert FALSE
report "***FAILED TEST: c08s04b00x00p08n01i01319 - Signal is identified as target more than once in the same assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p08n01i01319arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1319.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p08n01i01319ent IS
END c08s04b00x00p08n01i01319ent;
ARCHITECTURE c08s04b00x00p08n01i01319arch OF c08s04b00x00p08n01i01319ent IS
type aggsig is array (1 to 4) of bit;
signal S : aggsig;
signal S1 : bit;
signal S2 : bit;
signal S3 : bit;
signal S4 : bit;
BEGIN
TESTING: PROCESS
BEGIN
S <= (bit'('0'), bit'('1'), bit'('0'),bit'('1'));
(S1, S2, S1, S4) <= S;
assert FALSE
report "***FAILED TEST: c08s04b00x00p08n01i01319 - Signal is identified as target more than once in the same assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p08n01i01319arch;
|
-------------------------------------------------------------------------------
--
-- File: rgb2dpvid.vhd
-- Author: Mihaita Nagy
-- Original Project: RGB to Displayport Video
-- Date: 12 November 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- Converts a kDataWidth-bit RGB interface (VGA compatible) given as input to a
-- Displayport Video interface
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity rgb2dpvid is
generic(
-- Width of the input data bus
kDataWidth : integer := 24
);
port(
-- RGB interface
PixelClk : in std_logic;
pData : in std_logic_vector((kDataWidth-1) downto 0);
pHSync : in std_logic;
pVSync : in std_logic;
pVde : in std_logic;
-- Displayport Video interface
pVidClk : out std_logic;
pVidPixel0 : out std_logic_vector(47 downto 0);
pVidHSync : out std_logic;
pVidVSync : out std_logic;
pVidOddEven : out std_logic;
pVidRst : out std_logic;
pVidEnable : out std_logic
);
end rgb2dpvid;
architecture rtl of rgb2dpvid is
begin
-- Video clock the same as the pixel clock
pVidClk <= PixelClk;
-- Odd/Even qualifier not used
pVidOddEven <= '0';
-- Also reset is not used
pVidRst <= '0';
-- Synchronous process to distribute the video data
SyncIns: process(PixelClk)
begin
if rising_edge(PixelClk) then
pVidHSync <= pHSync;
pVidVSync <= pVSync;
pVidEnable <= pVde;
-- Red component
pVidPixel0(47 downto 47-((kDataWidth/3)-1)) <= pData((kDataWidth-1) downto (kDataWidth-kDataWidth/3));
pVidPixel0(39 downto 32) <= (others => '0');
-- Green component
pVidPixel0(31 downto 31-((kDataWidth/3)-1)) <= pData(((kDataWidth-2*kDataWidth/3)-1) downto 0);
pVidPixel0(23 downto 16) <= (others => '0');
-- Blue component
pVidPixel0(15 downto 15-((kDataWidth/3)-1)) <= pData(((kDataWidth-kDataWidth/3)-1) downto (kDataWidth-2*kDataWidth/3));
pVidPixel0(7 downto 0) <= (others => '0');
end if;
end process SyncIns;
end rtl;
|
-------------------------------------------------------------------------------
--
-- File: rgb2dpvid.vhd
-- Author: Mihaita Nagy
-- Original Project: RGB to Displayport Video
-- Date: 12 November 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- Converts a kDataWidth-bit RGB interface (VGA compatible) given as input to a
-- Displayport Video interface
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity rgb2dpvid is
generic(
-- Width of the input data bus
kDataWidth : integer := 24
);
port(
-- RGB interface
PixelClk : in std_logic;
pData : in std_logic_vector((kDataWidth-1) downto 0);
pHSync : in std_logic;
pVSync : in std_logic;
pVde : in std_logic;
-- Displayport Video interface
pVidClk : out std_logic;
pVidPixel0 : out std_logic_vector(47 downto 0);
pVidHSync : out std_logic;
pVidVSync : out std_logic;
pVidOddEven : out std_logic;
pVidRst : out std_logic;
pVidEnable : out std_logic
);
end rgb2dpvid;
architecture rtl of rgb2dpvid is
begin
-- Video clock the same as the pixel clock
pVidClk <= PixelClk;
-- Odd/Even qualifier not used
pVidOddEven <= '0';
-- Also reset is not used
pVidRst <= '0';
-- Synchronous process to distribute the video data
SyncIns: process(PixelClk)
begin
if rising_edge(PixelClk) then
pVidHSync <= pHSync;
pVidVSync <= pVSync;
pVidEnable <= pVde;
-- Red component
pVidPixel0(47 downto 47-((kDataWidth/3)-1)) <= pData((kDataWidth-1) downto (kDataWidth-kDataWidth/3));
pVidPixel0(39 downto 32) <= (others => '0');
-- Green component
pVidPixel0(31 downto 31-((kDataWidth/3)-1)) <= pData(((kDataWidth-2*kDataWidth/3)-1) downto 0);
pVidPixel0(23 downto 16) <= (others => '0');
-- Blue component
pVidPixel0(15 downto 15-((kDataWidth/3)-1)) <= pData(((kDataWidth-kDataWidth/3)-1) downto (kDataWidth-2*kDataWidth/3));
pVidPixel0(7 downto 0) <= (others => '0');
end if;
end process SyncIns;
end rtl;
|
--- Entity Mnot
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Mnot IS
PORT (
A: IN STD_LOGIC;
R: OUT STD_LOGIC
);
END Mnot;
ARCHITECTURE pure_logic OF Mnot IS
BEGIN
R <= (NOT A);
END pure_logic;
|
architecture RTL of FIFO is
begin
process
variable var1 : integer;
begin
end process;
process (a, b)
variable var1 : integer;
begin
end process;
process is
variable var1 : integer;
begin
end process;
-- Violations below
process
variable var1 : integer;
begin
end process;
process (a, b)
variable var1 : integer;
begin
end process;
process is
variable var1 : integer;
begin
end process;
process
begin
end process;
end architecture RTL;
|
-------------------------------------------------------------------------------
-- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, wait.
entity ENT00001_Test_Bench is
end entity ENT00001_Test_Bench;
architecture ARCH00001_Test_Bench of ENT00001_Test_Bench is
begin
main: process
begin
report "Start.";
wait for 10 fs;
report "Ten femtoseconds.";
wait for 990 fs;
report "One picosecond.";
wait ;
end process;
end;
|
entity FIFO is
end entity fifo;
entity FIFO is
end ENTITY FIFO;
entity FIFO is
end Entity FIFO;
|
entity ent is
end entity;
architecture a of ent is
type protected_t is protected
procedure proc;
end protected;
type protected_t is protected body
procedure proc is
begin
report "tick";
wait for 1 ns;
report "tock";
end procedure;
end protected body;
begin
main : process
variable prot : protected_t;
begin
prot.proc;
wait;
end process;
end architecture;
|
entity ent is
end entity;
architecture a of ent is
type protected_t is protected
procedure proc;
end protected;
type protected_t is protected body
procedure proc is
begin
report "tick";
wait for 1 ns;
report "tock";
end procedure;
end protected body;
begin
main : process
variable prot : protected_t;
begin
prot.proc;
wait;
end process;
end architecture;
|
entity ent is
end entity;
architecture a of ent is
type protected_t is protected
procedure proc;
end protected;
type protected_t is protected body
procedure proc is
begin
report "tick";
wait for 1 ns;
report "tock";
end procedure;
end protected body;
begin
main : process
variable prot : protected_t;
begin
prot.proc;
wait;
end process;
end architecture;
|
entity ent is
end entity;
architecture a of ent is
type protected_t is protected
procedure proc;
end protected;
type protected_t is protected body
procedure proc is
begin
report "tick";
wait for 1 ns;
report "tock";
end procedure;
end protected body;
begin
main : process
variable prot : protected_t;
begin
prot.proc;
wait;
end process;
end architecture;
|
entity ent is
end entity;
architecture a of ent is
type protected_t is protected
procedure proc;
end protected;
type protected_t is protected body
procedure proc is
begin
report "tick";
wait for 1 ns;
report "tock";
end procedure;
end protected body;
begin
main : process
variable prot : protected_t;
begin
prot.proc;
wait;
end process;
end architecture;
|
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
ENTITY rc4_crypto_tb IS
END rc4_crypto_tb;
ARCHITECTURE behavior OF rc4_crypto_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT rc4_crypto
PORT(
enc_input : IN std_logic_vector(7 downto 0);
perm_input : IN std_logic_vector(7 downto 0);
go : IN std_logic;
clk : IN std_logic;
enc_output : OUT std_logic_vector(7 downto 0);
perm_ctrl : OUT std_logic;
perm_index : OUT std_logic_vector(7 downto 0);
perm_output : OUT std_logic_vector(7 downto 0);
rdy : OUT std_logic
);
END COMPONENT;
--Inputs
signal enc_input : std_logic_vector(7 downto 0) := (others => '0');
signal perm_input : std_logic_vector(7 downto 0);
signal go : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal enc_output : std_logic_vector(7 downto 0);
signal perm_ctrl : std_logic;
signal perm_index : std_logic_vector(7 downto 0);
signal perm_output : std_logic_vector(7 downto 0);
signal rdy : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
subtype rc4int is integer range 0 to 255;
type my_array is array (0 to 255) of rc4int;
shared variable sarr : my_array := (
185, 126, 115, 175, 200, 169, 108, 155,
013, 041, 091, 189, 046, 116, 109, 163,
120, 020, 078, 049, 012, 038, 213, 142,
096, 094, 001, 178, 206, 067, 105, 148,
156, 055, 158, 073, 081, 145, 009, 132,
002, 050, 039, 172, 244, 243, 139, 166,
040, 201, 063, 164, 165, 207, 170, 167,
159, 118, 061, 010, 222, 247, 104, 089,
223, 087, 193, 110, 099, 071, 031, 128,
203, 135, 034, 015, 161, 174, 029, 225,
019, 103, 080, 162, 056, 154, 058, 133,
234, 209, 236, 023, 151, 051, 060, 232,
090, 176, 113, 121, 230, 212, 251, 093,
026, 245, 097, 003, 035, 191, 238, 199,
249, 181, 188, 192, 205, 182, 027, 146,
184, 195, 119, 028, 112, 235, 079, 048,
086, 018, 171, 198, 007, 130, 043, 254,
092, 076, 025, 147, 054, 150, 014, 123,
030, 211, 084, 229, 037, 237, 000, 168,
044, 157, 083, 246, 088, 137, 253, 064,
075, 069, 017, 057, 047, 036, 059, 220,
242, 006, 153, 129, 004, 052, 202, 042,
085, 144, 106, 177, 190, 117, 187, 008,
204, 070, 226, 194, 186, 127, 033, 138,
136, 024, 100, 124, 180, 095, 173, 045,
239, 072, 005, 219, 066, 149, 228, 179,
210, 141, 143, 082, 208, 217, 215, 218,
053, 125, 021, 131, 214, 231, 022, 250,
074, 224, 252, 102, 107, 221, 077, 240,
140, 068, 062, 248, 255, 233, 227, 122,
114, 016, 065, 160, 111, 101, 196, 098,
197, 032, 183, 152, 216, 241, 011, 134);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: rc4_crypto PORT MAP (
enc_input => enc_input,
perm_input => perm_input,
go => go,
clk => clk,
enc_output => enc_output,
perm_ctrl => perm_ctrl,
perm_index => perm_index,
perm_output => perm_output,
rdy => rdy
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
array_proc: process(clk, perm_ctrl, perm_index, perm_output)
begin
if rising_edge(clk) then
if perm_ctrl = '1' then
sarr(conv_integer(unsigned(perm_index))) := conv_integer(unsigned(perm_output));
else
perm_input <= conv_std_logic_vector(sarr(conv_integer(unsigned(perm_index))), 8);
end if;
end if;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
go <= '1';
wait;
end process;
END;
|
-- Inertial assignment
entity ENT00001_Test_Bench is
end entity ENT00001_Test_Bench;
architecture arch of ENT00001_Test_Bench is
constant c : integer := 1;
type arr is array (0 to c) of integer;
constant c33 : arr := (others => 33);
signal i : arr;
begin
terminator : process
begin
i <= c33 after 5 us, (0=>0, 1=>1) after 10 us;
wait for 100 us;
assert false report "end of simulation" severity failure;
end process;
end;
|
--------------------------------------------------------------------------------
--
-- Title : cl_timer_data.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Test example for DS1302 timer settings and LCD1602 RAM loading
-- DS1302 -> LCD1602
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity cl_timer_data is
generic (
TIME_SECS : in integer range 0 to 59:=12; --! Seconds
TIME_MINS : in integer range 0 to 59:=35; --! Minutes
TIME_HRS : in integer range 0 to 23:=17; --! Hours
TIME_DTS : in integer range 0 to 30:=13; --! Dates
TIME_MTHS : in integer range 0 to 11:=07; --! Months
TIME_DAYS : in integer range 0 to 59:=17; --! Days
TIME_YRS : in integer range 0 to 99:=16; --! Years
TD : in time := 1 ns --! simulation time;
);
port(
---- Global signals ----
reset : in std_logic; --! asycnchronous reset
clk : in std_logic; --! clock 50 MHz
restart : in std_logic; --! restart timer
---- DS1302 signals ----
addr : out std_logic_vector(7 downto 0); --! address for timer
data_o : out std_logic_vector(7 downto 0); --! input data (to timer)
data_i : in std_logic_vector(7 downto 0); --! output data (from timer)
data_v : in std_logic; --! valid data (from timer)
ready : in std_logic; --! timer is ready for data
enable : out std_logic; --! timer enable
---- LCD1602 signals ----
load_ena : out std_logic; --! enable writing to LCD RAM
load_dat : out std_logic_vector(7 downto 0); --! data to LCD RAM
load_addr : out std_logic_vector(4 downto 0) --! address to LCD RAM
);
end cl_timer_data;
architecture cl_timer_data of cl_timer_data is
signal sec0_lcd : std_logic_vector(3 downto 0);
signal sec1_lcd : std_logic_vector(3 downto 0);
signal min0_lcd : std_logic_vector(3 downto 0);
signal min1_lcd : std_logic_vector(3 downto 0);
signal hrs0_lcd : std_logic_vector(3 downto 0);
signal hrs1_lcd : std_logic_vector(3 downto 0);
signal dts0_lcd : std_logic_vector(3 downto 0);
signal dts1_lcd : std_logic_vector(3 downto 0);
signal mth0_lcd : std_logic_vector(3 downto 0);
signal mth1_lcd : std_logic_vector(3 downto 0);
signal days_lcd : std_logic_vector(3 downto 0);
signal yrs0_lcd : std_logic_vector(3 downto 0);
signal yrs1_lcd : std_logic_vector(3 downto 0);
signal data_rom : std_logic_vector(3 downto 0);
signal time_addr : std_logic_vector(3 downto 0);
signal timer_v : std_logic_vector(3 downto 0);
type tdata_timer is (secs, mins, hours, dates, months, days, years, nulls); --days,
signal time_code : tdata_timer;
signal time_codex : tdata_timer;
signal time_set : std_logic_vector(4 downto 0);
signal time_get : std_logic_vector(3 downto 0);
signal mode : std_logic;
signal timer_conf : std_logic;
signal readyz : std_logic;
signal ena : std_logic;
signal load : std_logic;
signal lcd_addr : std_logic_vector(4 downto 0);
---------------- INTEGER TO STD_LOGIC_VECTOR TO BCD CONVERTER ----------------
constant n : integer:=8;
constant q : integer:=2;
function to_bcd ( bin : std_logic_vector((n-1) downto 0) ) return std_logic_vector is
variable i : integer:=0;
variable j : integer:=1;
variable bcd : std_logic_vector(((4*q)-1) downto 0) := (others => '0');
variable bint : std_logic_vector((n-1) downto 0) := bin;
begin
for i in 0 to n-1 loop -- repeating 8 times.
bcd(((4*q)-1) downto 1) := bcd(((4*q)-2) downto 0); --shifting the bits.
bcd(0) := bint(n-1);
bint((n-1) downto 1) := bint((n-2) downto 0);
bint(0) :='0';
l1: for j in 1 to q loop
if(i < n-1 and bcd(((4*j)-1) downto ((4*j)-4)) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(((4*j)-1) downto ((4*j)-4)) := bcd(((4*j)-1) downto ((4*j)-4)) + "0011";
end if;
end loop l1;
end loop;
return bcd;
end to_bcd;
constant temp_secs : std_logic_vector(7 downto 0):=to_bcd(conv_std_logic_vector(TIME_SECS, 8)); -- Seconds
constant temp_mins : std_logic_vector(7 downto 0):=to_bcd(conv_std_logic_vector(TIME_MINS, 8)); -- Minutes
constant temp_hrs : std_logic_vector(7 downto 0):=to_bcd(conv_std_logic_vector(TIME_HRS, 8)); -- Hours
constant temp_dts : std_logic_vector(7 downto 0):=to_bcd(conv_std_logic_vector(TIME_DTS, 8)); -- Dates
constant temp_mths : std_logic_vector(7 downto 0):=to_bcd(conv_std_logic_vector(TIME_MTHS, 8)); -- Months
constant temp_days : std_logic_vector(7 downto 0):=to_bcd(conv_std_logic_vector(TIME_DAYS, 8)); -- Days
constant temp_yrs : std_logic_vector(7 downto 0):=to_bcd(conv_std_logic_vector(TIME_YRS, 8)); -- Years
begin
readyz <= not ready after td when rising_edge(clk);
ena <= ready and readyz after td when rising_edge(clk);
enable <= ena when rising_edge(clk);
--addr <= x"8" & time_addr after td when rising_edge(clk);
pr_addr: process(clk, reset) is
begin
if (reset = '0') then
addr <= x"00";
elsif (rising_edge(clk)) then
addr <= x"8" & time_addr after td;
end if;
end process;
load_dat <= x"3" & data_rom after td when rising_edge(clk);
load_addr <= lcd_addr after td when rising_edge(clk);
load_ena <= load after td when rising_edge(clk);
timer_v <= timer_v(2 downto 0) & data_v after td when rising_edge(clk);
---------------- TIMER CONFIGURE DATA ----------------
pr_conf: process(clk, reset) is
begin
if (reset = '0') then
data_o <= x"00";
time_set <= "00000";
timer_conf <= '0';
elsif (rising_edge(clk)) then
if (restart = '0') then
time_set <= "00000" after td;
end if;
timer_conf <= time_set(4) after td;
if (ena = '1') then
if time_set(4) = '0' then
time_set <= time_set + '1' after td;
else
null;
end if;
end if;
case time_set(3 downto 0) is
when x"1" => data_o <= x"00"; -- WP: (7) bit should be '0' to enable writing data
when x"2" => data_o <= temp_yrs;--temp_yrs;
when x"3" => data_o <= temp_days;
when x"4" => data_o <= temp_mths;
when x"5" => data_o <= temp_dts;
when x"6" => data_o <= temp_hrs;
when x"7" => data_o <= temp_mins;
when x"8" => data_o <= temp_secs; -- CH: (7) bit should be '0' to start clocking
when others => data_o <= x"80"; --null;
end case;
end if;
end process;
---------------- TIMER GETTING DATA ----------------
pr_timeget: process(clk, reset) is
begin
if (reset = '0') then
time_get <= x"0";
mode <= '1';
elsif (rising_edge(clk)) then
if ((ena = '1') and (timer_conf = '1')) then
time_get <= time_get + '1' after td;
mode <= not mode after td;
end if;
end if;
end process;
pr_rom_load: process(clk, reset) is
begin
if (reset = '0') then
load <= '0';
elsif (rising_edge(clk)) then
if (timer_conf = '0') then
load <= '0' after td;
else
load <= timer_v(3) after td;
end if;
end if;
end process;
---------------- TIMER READING DATA ----------------
pr_readback: process(clk, reset) is
begin
if (reset = '0') then
time_addr <= x"0";
elsif (rising_edge(clk)) then
if (restart = '0') then
time_addr <= x"0" after td;
end if;
if (timer_conf = '0') then
case time_set(3 downto 0) is
when x"1" => time_addr <= x"E"; -- set write protect
when x"2" => time_addr <= x"C"; -- year
when x"3" => time_addr <= x"A"; -- day
when x"4" => time_addr <= x"8"; -- month
when x"5" => time_addr <= x"6"; -- date
when x"6" => time_addr <= x"4"; -- hour
when x"7" => time_addr <= x"2"; -- minute
when x"8" => time_addr <= x"0"; -- second
when others => time_addr <= x"E";
end case;
else
case time_get is
when x"1" | x"2" => time_addr <= x"D"; -- year
when x"3" | x"4" => time_addr <= x"B"; -- day
when x"5" | x"6" => time_addr <= x"9"; -- month
when x"7" | x"8" => time_addr <= x"7"; -- date
when x"9" | x"A" => time_addr <= x"5"; -- hour
when x"B" | x"C" => time_addr <= x"3"; -- minute
when x"D" | x"E" => time_addr <= x"1"; -- second
when others => null;
end case;
end if;
end if;
end process;
---------------- TIMER CODES ----------------
time_codex <= secs when time_addr(3 downto 1) = "000" else
mins when time_addr(3 downto 1) = "001" else
hours when time_addr(3 downto 1) = "010" else
dates when time_addr(3 downto 1) = "011" else
months when time_addr(3 downto 1) = "100" else
days when time_addr(3 downto 1) = "101" else
years when time_addr(3 downto 1) = "110" else
nulls;
time_code <= time_codex after td when rising_edge(clk);
---------------- TIMER WRITE ROM ----------------
pr_data_rom: process(clk, reset) is
begin
if (reset = '0') then
data_rom <= x"0";
elsif (rising_edge(clk)) then
if (restart = '0') then
data_rom <= x"0" after td;
end if;
if (timer_v(2) = '1') then
case time_code is
when secs =>
if mode = '0' then
lcd_addr <= "11100" after td;
data_rom <= sec0_lcd after td;
else
lcd_addr <= "11011" after td;
data_rom <= sec1_lcd after td;
end if;
when mins =>
if mode = '0' then
lcd_addr <= "11001" after td;
data_rom <= min0_lcd after td;
else
lcd_addr <= "11000" after td;
data_rom <= min1_lcd after td;
end if;
when hours =>
if mode = '0' then
lcd_addr <= "10110" after td;
data_rom <= hrs0_lcd after td;
else
lcd_addr <= "10101" after td;
data_rom <= hrs1_lcd after td;
end if;
when dates =>
if mode = '0' then
lcd_addr <= "00110" after td;
data_rom <= dts0_lcd after td;
else
lcd_addr <= "00101" after td;
data_rom <= dts1_lcd after td;
end if;
when months =>
if mode = '0' then
lcd_addr <= "01001" after td;
data_rom <= mth0_lcd after td;
else
lcd_addr <= "01000" after td;
data_rom <= mth1_lcd after td;
end if;
-- when days =>
-- data_rom <= days_lcd after td;
when years =>
if mode = '0' then
lcd_addr <= "01100" after td;
data_rom <= yrs0_lcd after td;
else
lcd_addr <= "01011" after td;
data_rom <= yrs1_lcd after td;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
---------------- SECONDS LSB ----------------
pr_conv_sec0: process(clk, reset) is
begin
if (reset = '0') then
sec0_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = secs)) then
sec0_lcd <= data_i(3 downto 0) after td;
end if;
end if;
end process;
---------------- SECONDS MSB ----------------
pr_conv_sec1: process(clk, reset) is
begin
if (reset = '0') then
sec1_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = secs)) then
case data_i(6 downto 4) is
when "000" => sec1_lcd <= x"0" after td;
when "001" => sec1_lcd <= x"1" after td;
when "010" => sec1_lcd <= x"2" after td;
when "011" => sec1_lcd <= x"3" after td;
when "100" => sec1_lcd <= x"4" after td;
when "101" => sec1_lcd <= x"5" after td;
when others => null;
end case;
end if;
end if;
end process;
---------------- MINUTES LSB ----------------
pr_conv_min0: process(clk, reset) is
begin
if (reset = '0') then
min0_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = mins)) then
min0_lcd <= data_i(3 downto 0) after td;
end if;
end if;
end process;
---------------- MINUTES MSB ----------------
pr_conv_min1: process(clk, reset) is
begin
if (reset = '0') then
min1_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = mins)) then
case data_i(6 downto 4) is
when "000" => min1_lcd <= x"0" after td;
when "001" => min1_lcd <= x"1" after td;
when "010" => min1_lcd <= x"2" after td;
when "011" => min1_lcd <= x"3" after td;
when "100" => min1_lcd <= x"4" after td;
when "101" => min1_lcd <= x"5" after td;
when others => null;
end case;
end if;
end if;
end process;
---------------- DATES LSB ----------------
pr_conv_dts0: process(clk, reset) is
begin
if (reset = '0') then
dts0_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = dates)) then
dts0_lcd <= data_i(3 downto 0) after td;
end if;
end if;
end process;
---------------- DATES MSB ----------------
pr_conv_dts1: process(clk, reset) is
begin
if (reset = '0') then
dts1_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = dates)) then
case data_i(5 downto 4) is
when "00" => dts1_lcd <= x"0" after td;
when "01" => dts1_lcd <= x"1" after td;
when "10" => dts1_lcd <= x"2" after td;
when "11" => dts1_lcd <= x"3" after td;
when others => null;
end case;
end if;
end if;
end process;
---------------- MONTHS LSB ----------------
pr_conv_mth0: process(clk, reset) is
begin
if (reset = '0') then
mth0_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = months)) then
mth0_lcd <= data_i(3 downto 0) after td;
end if;
end if;
end process;
---------------- MONTHS MSB ----------------
pr_conv_mth1: process(clk, reset) is
begin
if (reset = '0') then
mth1_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = months)) then
case data_i(4) is
when '0' => mth1_lcd <= x"0" after td;
when '1' => mth1_lcd <= x"1" after td;
when others => null;
end case;
end if;
end if;
end process;
---------------- DAYS ----------------
pr_conv_days: process(clk, reset) is
begin
if (reset = '0') then
days_lcd <= x"0";
elsif (rising_edge(clk)) then
if (time_code = days) then
case data_i(2 downto 0) is
when "000" => days_lcd <= x"1" after td;
when "001" => days_lcd <= x"2" after td;
when "010" => days_lcd <= x"3" after td;
when "011" => days_lcd <= x"4" after td;
when "100" => days_lcd <= x"5" after td;
when "101" => days_lcd <= x"6" after td;
when "110" => days_lcd <= x"7" after td;
--when "111" => days_lcd <= x"7" after td;
when others => null;
end case;
end if;
end if;
end process;
---------------- HOURS LSB ----------------
pr_conv_hrs: process(clk, reset) is
begin
if (reset = '0') then
hrs0_lcd <= x"0";
hrs1_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = hours)) then
hrs0_lcd <= data_i(3 downto 0) after td;
hrs1_lcd <= data_i(7 downto 4) after td;
end if;
end if;
end process;
---------------- YEARS LSB ----------------
pr_conv_yrs: process(clk, reset) is
begin
if (reset = '0') then
yrs0_lcd <= x"0";
yrs1_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = years)) then
yrs0_lcd <= data_i(3 downto 0) after td;
yrs1_lcd <= data_i(7 downto 4) after td;
-- case data_i(3 downto 0) is
-- when x"0" => yrs0_lcd <= x"0" after td;
-- when x"1" => yrs0_lcd <= x"1" after td;
-- when x"2" => yrs0_lcd <= x"2" after td;
-- when x"3" => yrs0_lcd <= x"3" after td;
-- when x"4" => yrs0_lcd <= x"4" after td;
-- when x"5" => yrs0_lcd <= x"5" after td;
-- when x"6" => yrs0_lcd <= x"6" after td;
-- when x"7" => yrs0_lcd <= x"7" after td;
-- when x"8" => yrs0_lcd <= x"8" after td;
-- when x"9" => yrs0_lcd <= x"9" after td;
-- when others => null;
-- end case;
-- case data_i(7 downto 4) is
-- when x"0" => yrs1_lcd <= x"0" after td;
-- when x"1" => yrs1_lcd <= x"1" after td;
-- when x"2" => yrs1_lcd <= x"2" after td;
-- when x"3" => yrs1_lcd <= x"3" after td;
-- when x"4" => yrs1_lcd <= x"4" after td;
-- when x"5" => yrs1_lcd <= x"5" after td;
-- when x"6" => yrs1_lcd <= x"6" after td;
-- when x"7" => yrs1_lcd <= x"7" after td;
-- when x"8" => yrs1_lcd <= x"8" after td;
-- when x"9" => yrs1_lcd <= x"9" after td;
-- when others => null;
-- end case;
end if;
end if;
end process;
end cl_timer_data; |
--------------------------------------------------------------------------------
-- UART Transceiver 19200/8N1 --
--------------------------------------------------------------------------------
-- This minimal implementation of an Universal Asynchronous Receiver and --
-- Transmitter (UART) suits a baud rate of 19200 baud/sec as well as 8 bits --
-- of data, no parity bit and one stop bit configuration only. It comprises --
-- two seperate baud generators to receive and transmit simultanously. --
-- --
-- REFERENCES --
-- --
-- [1] Chu Pong P., FPGA Prototyping By VHDL Examples, --
-- John Wiley & Sons Inc., Hoboken, New Jersy, 2008, --
-- ISBN: 978-0470185315 --
-- --
--------------------------------------------------------------------------------
-- Copyright (C)2011 Mathias Hörtnagl <mathias.hoertnagl@gmail.comt> --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iwb.all;
package iuart is
component uartr is
port(
si : in slave_in_t;
so : out slave_out_t;
-- Non-Wishbone Signals
RS232_DCE_RXD : in std_logic
);
end component;
component uartt is
port(
si : in slave_in_t;
so : out slave_out_t;
-- Non-Wishbone Signals
RS232_DCE_TXD : out std_logic
);
end component;
component counter is
generic(
FREQ : positive := 50; -- Clock frequency in MHz.
RATE : positive := 19200 -- Baud rate.
);
port(
clk : in std_logic;
rst : in std_logic;
tick : out std_logic
);
end component;
end iuart; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbonepkg.all;
use work.xtcpkg.all;
entity xtc_ioctrl is
port (
syscon: in wb_syscon_type;
wbi: in wb_mosi_type;
wbo: out wb_miso_type;
-- Slaves
swbi: in slot_wbi;
swbo: out slot_wbo;
sids: in slot_ids
);
end entity xtc_ioctrl;
architecture behave of xtc_ioctrl is
signal selector: std_logic_vector(15 downto 0);
signal selnum: integer range 0 to 15;
signal ackint: std_logic := '0';
signal trans_valid: std_logic := '1';
signal tagi: std_logic_vector(31 downto 0);
begin
process(wbi.adr)
variable num: integer range 0 to 15;
begin
num := to_integer(unsigned(wbi.adr(30 downto 28)));
selector<=(others => '0');
selector(num)<='1';
selnum<=num;
end process;
direct: if not IO_REGISTER_INPUTS generate
wbo.dat <= swbi(selnum).dat;
ackint <= swbi(selnum).ack;
wbo.err <= swbi(selnum).err;
wbo.tag <= tagi;
end generate;
indirect: if IO_REGISTER_INPUTS generate
trans_valid<='1' when ackint='0' else '0';
process(syscon.clk)
begin
if rising_edge(syscon.clk) then
if syscon.rst='1' then
wbo.dat <= (others => 'X');
ackint <= '0';
wbo.err <= '0';
wbo.tag <= (others => 'X');
else
wbo.dat <= swbi(selnum).dat;
ackint <= swbi(selnum).ack;
wbo.err <= swbi(selnum).err;
wbo.tag <= tagi;
end if;
end if;
end process;
end generate;
wbo.stall <= '0';
wbo.ack <= ackint;
-- Simple tag generator. Also resynchronizer
process(syscon.clk)
begin
if rising_edge(syscon.clk) then
--if syscon.rst='1' then
-- wbo.tag <= (others => '0');
--else
tagi <= wbi.tag;
--end if;
end if;
end process;
slavegen: for i in 0 to 15 generate
swbo(i).adr <= wbi.adr;
swbo(i).dat <= wbi.dat;
swbo(i).we <= wbi.we;
--swbo(i).tag <= wbi.tag;
swbo(i).cyc <= wbi.cyc and selector(i) and trans_valid;
swbo(i).stb <= wbi.stb and selector(i) and trans_valid;
end generate;
end behave;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc688.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:03 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:35 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:42 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00688ent IS
END c03s04b01x00p23n01i00688ent;
ARCHITECTURE c03s04b01x00p23n01i00688arch OF c03s04b01x00p23n01i00688ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of TIME;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.52";
-- Declare a variable into which we will read.
constant CON : TIME := 1 ns;
variable VAR : TIME;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00688"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00688 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00688arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc688.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:03 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:35 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:42 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00688ent IS
END c03s04b01x00p23n01i00688ent;
ARCHITECTURE c03s04b01x00p23n01i00688arch OF c03s04b01x00p23n01i00688ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of TIME;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.52";
-- Declare a variable into which we will read.
constant CON : TIME := 1 ns;
variable VAR : TIME;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00688"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00688 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00688arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc688.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:03 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:35 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:42 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00688ent IS
END c03s04b01x00p23n01i00688ent;
ARCHITECTURE c03s04b01x00p23n01i00688arch OF c03s04b01x00p23n01i00688ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of TIME;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.52";
-- Declare a variable into which we will read.
constant CON : TIME := 1 ns;
variable VAR : TIME;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00688"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00688 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00688arch;
|
library verilog;
use verilog.vl_types.all;
entity usb_system_jtag_uart_sim_scfifo_w is
port(
clk : in vl_logic;
fifo_wdata : in vl_logic_vector(7 downto 0);
fifo_wr : in vl_logic;
fifo_FF : out vl_logic;
r_dat : out vl_logic_vector(7 downto 0);
wfifo_empty : out vl_logic;
wfifo_used : out vl_logic_vector(5 downto 0)
);
end usb_system_jtag_uart_sim_scfifo_w;
|
-- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop_s3 (for test bench)
--
-- Dependencies: -
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-05 420 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- in simulation a usec is shortened to 12 cycles (0.2 usec) and a msec
-- to 60 cycles (1 usec). This affects the pulse generators (usec) and
-- mainly the autobauder. A break will be detected after 128 msec periods,
-- this in simulation after 128 usec or 6400 cycles. This is compatible with
-- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles)
constant sys_conf_clkdiv_usecdiv : integer := 12; -- shortened !
constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened !
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
end package sys_conf;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_t
--
-- Generated
-- by: wig
-- on: Fri Jun 9 05:15:53 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../highlow.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-e.vhd,v 1.2 2006/06/22 07:19:59 wig Exp $
-- $Date: 2006/06/22 07:19:59 $
-- $Log: ent_t-e.vhd,v $
-- Revision 1.2 2006/06/22 07:19:59 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.45 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_t
--
entity ent_t is
-- Generics:
-- No Generated Generics for Entity ent_t
-- Generated Port Declaration:
-- No Generated Port for Entity ent_t
end ent_t;
--
-- End of Generated Entity ent_t
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
---------------------------------------------------------------------------------
-- Title : 1000 BASE X MAC RX Layer
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : Eth1000BaseXMacRx.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Connects to GTP interface to 1000 BASE X Ethernet.
-- Receiver passes bytes out.
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.Eth1000BaseXPkg.all;
use work.GigabitEthPkg.all;
entity Eth1000BaseXMacRx is
generic (
GATE_DELAY_G : time := 1 ns
);
port (
-- 125 MHz ethernet clock in
ethRxClk : in sl;
ethRxRst : in sl := '0';
-- Incoming data from the 16-to-8 mux
macDataIn : in EthMacDataType;
-- Outgoing bytes and flags to the applications
macRxData : out slv(7 downto 0);
macRxDataValid : out sl;
macRxDataLast : out sl;
macRxBadFrame : out sl;
-- Monitoring flags
macBadCrcCount : out slv(15 downto 0)
);
end Eth1000BaseXMacRx;
-- Define architecture
architecture rtl of Eth1000BaseXMacRx is
type StateType is (S_IDLE, S_PREAMBLE, S_FRAME_DATA, S_WAIT_CRC,
S_CHECK_CRC);
type RegType is record
state : StateType;
rxDataValid : sl;
rxDataLast : sl;
rxDataOut : slv(7 downto 0);
rxBadFrame : sl;
crcReset : sl;
crcDataValid : sl;
byteCount : slv(15 downto 0);
badCrcCount : slv(15 downto 0);
end record RegType;
constant REG_INIT_C : RegType := (
state => S_IDLE,
rxDataOut => (others => '0'),
rxDataValid => '0',
rxDataLast => '0',
rxBadFrame => '0',
crcReset => '0',
crcDataValid => '0',
byteCount => (others => '0'),
badCrcCount => (others => '0')
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
signal crcOut : slv(31 downto 0);
-- signal crcData : slv(31 downto 0);
signal crcDataWidth : slv(2 downto 0);
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
begin
-- crcData <= x"000000" & r.rxDataOut;
crcDataWidth <= "000";
U_Crc32 : entity work.Crc32
generic map (
BYTE_WIDTH_G => 1,
CRC_INIT_G => x"FFFFFFFF",
GATE_DELAY_G => GATE_DELAY_G
)
port map (
crcOut => crcOut,
crcClk => ethRxClk,
crcDataValid => r.crcDataValid,
crcDataWidth => crcDataWidth,
crcIn => r.rxDataOut,
crcReset => r.crcReset
);
comb : process(r,macDataIn,ethRxRst,crcOut) is
variable v : RegType;
begin
v := r;
v.rxDataOut := macDataIn.data;
case(r.state) is
when S_IDLE =>
v.crcReset := '1';
v.crcDataValid := '0';
v.rxDataValid := '0';
v.rxDataLast := '0';
v.rxBadFrame := '0';
v.byteCount := (others => '0');
-- If we see start of packet then we should move on to accept preamble
if (macDataIn.dataValid = '1' and macDataIn.dataK = '1' and macDataIn.data = K_SOP_C) then
v.state := S_PREAMBLE;
end if;
when S_PREAMBLE =>
v.crcReset := '0';
if (macDataIn.dataValid = '1' and macDataIn.dataK = '0' and macDataIn.data = ETH_SOF_C) then
v.state := S_FRAME_DATA;
-- Bail out if we see a comma, error, carrier
elsif (macDataIn.dataValid = '1' and macDataIn.dataK = '1' and
(macDataIn.data = K_COM_C or macDataIn.data = K_EOP_C or macDataIn.data = K_CAR_C or macDataIn.data = K_ERR_C)) then
v.state := S_IDLE;
end if;
when S_FRAME_DATA =>
v.rxDataValid := macDataIn.dataValid;
v.crcDataValid := '1';
v.byteCount := r.byteCount + 1;
-- Possible errors: K_ERR_C, misplaced comma (K_COM_C)
if (macDataIn.dataValid = '1' and macDataIn.dataK = '1' and
(macDataIn.data = K_ERR_C or macDataIn.data = K_COM_C)) then
v.rxDataValid := '0';
v.rxBadFrame := '1';
v.rxDataLast := '1';
v.state := S_IDLE;
-- Otherwise, should be frame data until we see end of packet
elsif (macDataIn.dataValid = '1' and macDataIn.dataK = '1' and macDataIn.data = K_EOP_C) then
v.rxDataValid := '0';
v.crcDataValid := '0';
v.state := S_WAIT_CRC;
end if;
-- Wait one cycle to account for latency of the CRC module
when S_WAIT_CRC =>
v.state := S_CHECK_CRC;
-- Check whether the CRC is valid
when S_CHECK_CRC =>
v.rxDataLast := '1';
-- Check for packet length and valid CRC
if (crcOut = CRC_CHECK_C and r.byteCount >= 46) then
v.rxBadFrame := '0';
-- Otherwise, it's a bad frame
else
v.rxBadFrame := '1';
v.badCrcCount := r.badCrcCount + 1;
end if;
v.state := S_IDLE;
when others =>
v.state := S_IDLE;
end case;
-- Reset logic
if (ethRxRst = '1') then
v := REG_INIT_C;
end if;
-- Outputs to ports
macRxData <= r.rxDataOut;
macRxDataValid <= r.rxDataValid;
macRxDataLast <= r.rxDataLast;
macRxBadFrame <= r.rxBadFrame;
macBadCrcCount <= r.badCrcCount;
rin <= v;
end process;
seq : process (ethRxClk) is
begin
if (rising_edge(ethRxClk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
|
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is
begin
end block;
BLOCK_LABEL : block is
signal sig1 : std_logic;
begin
end block;
-- Violations below
BLOCK_LABEL : block is
signal sig1 : std_logic;
begin
end block;
end architecture RTL;
|
-- Somador 8_bits --
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY RCA IS
PORT (
CarryIn: in std_logic;
val1,val2: in std_logic_vector (31 downto 0);
SomaResult: out std_logic_vector (31 downto 0);
CarryOut: out std_logic
);
END RCA ;
ARCHITECTURE strc_RCA OF RCA IS
signal carry: std_logic_vector (31 downto 1);
COMPONENT Soma1
port (
CarryIn,val1,val2: in std_logic ;
SomaResult,CarryOut: out std_logic
);
END COMPONENT ;
BEGIN
--somador--
Som0: Soma1 PORT MAP (
CarryIn,
val1(0),
val2(0),
SomaResult(0),
carry(1)
);
SOM: FOR i IN 1 TO 30 GENERATE
Som1: Soma1 PORT MAP (
carry(i),
val1(i),
val2(i),
SomaResult(i),
carry(i+1)
);
END GENERATE;
Som7: Soma1 PORT MAP (
carry(31),
val1(31),
val2(31),
SomaResult(31),
CarryOut
);
END strc_RCA ; |
--
-- Sends the given RGB data to a VGA interface.
--
-- Original author: unknown
--
-- Peter Heatwole, Aaron Barton
-- CPE233, Winter 2012, CalPoly
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity VGAdrive is
port( clock : in std_logic; -- 25.175 Mhz clock
red, green : in std_logic_vector(2 downto 0);
blue : in std_logic_vector(1 downto 0);
row, column : out std_logic_vector(9 downto 0); -- for current pixel
Rout, Gout : out std_logic_vector(2 downto 0);
Bout : out std_logic_vector(1 downto 0);
H, V : out std_logic); -- VGA drive signals
-- The signals Rout, Gout, Bout, H and V are output to the monitor.
-- The row and column outputs are used to know when to assert red,
-- green and blue to color the current pixel. For VGA, the column
-- values that are valid are from 0 to 639, all other values should
-- be ignored. The row values that are valid are from 0 to 479 and
-- again, all other values are ignored. To turn on a pixel on the
-- VGA monitor, some combination of red, green and blue should be
-- asserted before the rising edge of the clock. Objects which are
-- displayed on the monitor, assert their combination of red, green and
-- blue when they detect the row and column values are within their
-- range. For multiple objects sharing a screen, they must be combined
-- using logic to create single red, green, and blue signals.
end VGAdrive;
architecture Behavioral of VGAdrive is
subtype counter is std_logic_vector(9 downto 0);
constant B : natural := 93; -- horizontal blank: 3.77 us
constant C : natural := 45; -- front guard: 1.89 us
constant D : natural := 640; -- horizontal columns: 25.17 us
constant E : natural := 22; -- rear guard: 0.94 us
constant A : natural := B + C + D + E; -- one horizontal sync cycle: 31.77 us
constant P : natural := 2; -- vertical blank: 64 us
constant Q : natural := 32; -- front guard: 1.02 ms
constant R : natural := 480; -- vertical rows: 15.25 ms
constant S : natural := 11; -- rear guard: 0.35 ms
constant O : natural := P + Q + R + S; -- one vertical sync cycle: 16.6 ms
begin
-- Rout <= red;
-- Gout <= green;
-- Bout <= blue;
process
variable vertical, horizontal : counter; -- define counters
begin
wait until clock = '1';
-- increment counters
if horizontal < A - 1 then
horizontal := horizontal + 1;
else
horizontal := (others => '0');
if vertical < O - 1 then -- less than oh
vertical := vertical + 1;
else
vertical := (others => '0'); -- is set to zero
end if;
end if;
-- define H pulse
if horizontal >= (D + E) and horizontal < (D + E + B) then
H <= '0';
else
H <= '1';
end if;
-- define V pulse
if vertical >= (R + S) and vertical < (R + S + P) then
V <= '0';
else
V <= '1';
end if;
-- mapping of the variable to the signals
-- negative signs are because the conversion bits are reversed
if vertical <= 479 and horizontal <= 639 then
Rout <= red;
Gout <= green;
Bout <= blue;
else
Rout <= "000";
Gout <= "000";
Bout <= "00";
end if;
row <= vertical;
column <= horizontal;
end process;
end Behavioral;
|
--
-- Sends the given RGB data to a VGA interface.
--
-- Original author: unknown
--
-- Peter Heatwole, Aaron Barton
-- CPE233, Winter 2012, CalPoly
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity VGAdrive is
port( clock : in std_logic; -- 25.175 Mhz clock
red, green : in std_logic_vector(2 downto 0);
blue : in std_logic_vector(1 downto 0);
row, column : out std_logic_vector(9 downto 0); -- for current pixel
Rout, Gout : out std_logic_vector(2 downto 0);
Bout : out std_logic_vector(1 downto 0);
H, V : out std_logic); -- VGA drive signals
-- The signals Rout, Gout, Bout, H and V are output to the monitor.
-- The row and column outputs are used to know when to assert red,
-- green and blue to color the current pixel. For VGA, the column
-- values that are valid are from 0 to 639, all other values should
-- be ignored. The row values that are valid are from 0 to 479 and
-- again, all other values are ignored. To turn on a pixel on the
-- VGA monitor, some combination of red, green and blue should be
-- asserted before the rising edge of the clock. Objects which are
-- displayed on the monitor, assert their combination of red, green and
-- blue when they detect the row and column values are within their
-- range. For multiple objects sharing a screen, they must be combined
-- using logic to create single red, green, and blue signals.
end VGAdrive;
architecture Behavioral of VGAdrive is
subtype counter is std_logic_vector(9 downto 0);
constant B : natural := 93; -- horizontal blank: 3.77 us
constant C : natural := 45; -- front guard: 1.89 us
constant D : natural := 640; -- horizontal columns: 25.17 us
constant E : natural := 22; -- rear guard: 0.94 us
constant A : natural := B + C + D + E; -- one horizontal sync cycle: 31.77 us
constant P : natural := 2; -- vertical blank: 64 us
constant Q : natural := 32; -- front guard: 1.02 ms
constant R : natural := 480; -- vertical rows: 15.25 ms
constant S : natural := 11; -- rear guard: 0.35 ms
constant O : natural := P + Q + R + S; -- one vertical sync cycle: 16.6 ms
begin
-- Rout <= red;
-- Gout <= green;
-- Bout <= blue;
process
variable vertical, horizontal : counter; -- define counters
begin
wait until clock = '1';
-- increment counters
if horizontal < A - 1 then
horizontal := horizontal + 1;
else
horizontal := (others => '0');
if vertical < O - 1 then -- less than oh
vertical := vertical + 1;
else
vertical := (others => '0'); -- is set to zero
end if;
end if;
-- define H pulse
if horizontal >= (D + E) and horizontal < (D + E + B) then
H <= '0';
else
H <= '1';
end if;
-- define V pulse
if vertical >= (R + S) and vertical < (R + S + P) then
V <= '0';
else
V <= '1';
end if;
-- mapping of the variable to the signals
-- negative signs are because the conversion bits are reversed
if vertical <= 479 and horizontal <= 639 then
Rout <= red;
Gout <= green;
Bout <= blue;
else
Rout <= "000";
Gout <= "000";
Bout <= "00";
end if;
row <= vertical;
column <= horizontal;
end process;
end Behavioral;
|
--
-- Sends the given RGB data to a VGA interface.
--
-- Original author: unknown
--
-- Peter Heatwole, Aaron Barton
-- CPE233, Winter 2012, CalPoly
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity VGAdrive is
port( clock : in std_logic; -- 25.175 Mhz clock
red, green : in std_logic_vector(2 downto 0);
blue : in std_logic_vector(1 downto 0);
row, column : out std_logic_vector(9 downto 0); -- for current pixel
Rout, Gout : out std_logic_vector(2 downto 0);
Bout : out std_logic_vector(1 downto 0);
H, V : out std_logic); -- VGA drive signals
-- The signals Rout, Gout, Bout, H and V are output to the monitor.
-- The row and column outputs are used to know when to assert red,
-- green and blue to color the current pixel. For VGA, the column
-- values that are valid are from 0 to 639, all other values should
-- be ignored. The row values that are valid are from 0 to 479 and
-- again, all other values are ignored. To turn on a pixel on the
-- VGA monitor, some combination of red, green and blue should be
-- asserted before the rising edge of the clock. Objects which are
-- displayed on the monitor, assert their combination of red, green and
-- blue when they detect the row and column values are within their
-- range. For multiple objects sharing a screen, they must be combined
-- using logic to create single red, green, and blue signals.
end VGAdrive;
architecture Behavioral of VGAdrive is
subtype counter is std_logic_vector(9 downto 0);
constant B : natural := 93; -- horizontal blank: 3.77 us
constant C : natural := 45; -- front guard: 1.89 us
constant D : natural := 640; -- horizontal columns: 25.17 us
constant E : natural := 22; -- rear guard: 0.94 us
constant A : natural := B + C + D + E; -- one horizontal sync cycle: 31.77 us
constant P : natural := 2; -- vertical blank: 64 us
constant Q : natural := 32; -- front guard: 1.02 ms
constant R : natural := 480; -- vertical rows: 15.25 ms
constant S : natural := 11; -- rear guard: 0.35 ms
constant O : natural := P + Q + R + S; -- one vertical sync cycle: 16.6 ms
begin
-- Rout <= red;
-- Gout <= green;
-- Bout <= blue;
process
variable vertical, horizontal : counter; -- define counters
begin
wait until clock = '1';
-- increment counters
if horizontal < A - 1 then
horizontal := horizontal + 1;
else
horizontal := (others => '0');
if vertical < O - 1 then -- less than oh
vertical := vertical + 1;
else
vertical := (others => '0'); -- is set to zero
end if;
end if;
-- define H pulse
if horizontal >= (D + E) and horizontal < (D + E + B) then
H <= '0';
else
H <= '1';
end if;
-- define V pulse
if vertical >= (R + S) and vertical < (R + S + P) then
V <= '0';
else
V <= '1';
end if;
-- mapping of the variable to the signals
-- negative signs are because the conversion bits are reversed
if vertical <= 479 and horizontal <= 639 then
Rout <= red;
Gout <= green;
Bout <= blue;
else
Rout <= "000";
Gout <= "000";
Bout <= "00";
end if;
row <= vertical;
column <= horizontal;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Miscelaneous mathematic operations
-------------------------------------------------------------------------------
-- Description: This file contains math functions
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package tl_math_pkg is
---------------------------------------------------------------------------
-- increment/decrement functions
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- wrapping decrement/increment
---------------------------------------------------------------------------
-- Description: These functions give an increment/decrement that wraps when
-- the maximal vector range is reached.
---------------------------------------------------------------------------
function incr(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector;
function incr(old_value: unsigned; increment: natural := 1) return unsigned;
function incr(old_value: signed; increment: natural := 1) return signed;
function decr(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector;
function decr(old_value: unsigned; decrement: natural := 1) return unsigned;
function decr(old_value: signed; decrement: natural := 1) return signed;
---------------------------------------------------------------------------
-- clipping decrement/increment
---------------------------------------------------------------------------
-- Description: These functions give an increment/decrement that clips when
-- the maximal vector range is reached.
---------------------------------------------------------------------------
function incr_clip(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector;
function incr_clip(old_value: unsigned; increment: natural := 1) return unsigned;
function incr_clip(old_value: signed; increment: natural := 1) return signed;
function decr_clip(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector;
function decr_clip(old_value: unsigned; decrement: natural := 1) return unsigned;
function decr_clip(old_value: signed; decrement: natural := 1) return signed;
---------------------------------------------------------------------------
-- log functions
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- log2
---------------------------------------------------------------------------
-- Description: This functions returns the log2 value of a number. The
-- result is in the natural range and rounded depended on the
-- selected mode.
-- NOTE: use an argument of type unsigned when using this function for
-- synthesis
---------------------------------------------------------------------------
type log2mode is (ceil, floor);
function log2(arg: integer) return natural;
function log2(arg: integer; mode: log2mode) return natural;
function log2_floor(arg: integer) return natural;
function log2_ceil(arg: integer) return natural;
function log2(arg: unsigned) return natural;
function log2(arg: unsigned; mode: log2mode) return natural;
function log2_floor(arg: unsigned) return natural;
function log2_ceil(arg: unsigned) return natural;
---------------------------------------------------------------------------
-- min/max
---------------------------------------------------------------------------
-- Description: These functions return the minimum/maximum of two values
---------------------------------------------------------------------------
function max(a, b: integer) return integer;
function max(a, b: unsigned) return unsigned;
function min(a, b: integer) return integer;
function min(a, b: unsigned) return unsigned;
end tl_math_pkg;
library work;
use work.tl_vector_pkg.all;
package body tl_math_pkg is
---------------------------------------------------------------------------
-- increment/decrement functions
---------------------------------------------------------------------------
function incr(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector is
begin
return std_logic_vector(incr(unsigned(old_value), increment));
end function;
function incr(old_value: unsigned; increment: natural := 1) return unsigned is
variable v_result : unsigned(old_value'range);
begin
v_result := (old_value + increment) mod 2**old_value'length;
return v_result;
end function;
function incr(old_value: signed; increment: natural := 1) return signed is
begin
return signed(incr(unsigned(old_value), increment));
end function;
function decr(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector is
begin
return std_logic_vector(decr(unsigned(old_value), decrement));
end function;
function decr(old_value: unsigned; decrement: natural := 1) return unsigned is
constant c_norm_decrement : integer := decrement mod 2**old_value'length;
variable v_result : unsigned(old_value'range);
begin
v_result := (2**old_value'length + (old_value - c_norm_decrement)) mod 2**old_value'length;
return v_result;
end function;
function decr(old_value: signed; decrement: natural := 1) return signed is
begin
return signed(decr(unsigned(old_value), decrement));
end function;
---------------------------------------------------------------------------
-- clipping decrement/increment
---------------------------------------------------------------------------
-- Description: These functions give an increment/decrement that clips when
-- the maximal vector range is reached.
---------------------------------------------------------------------------
function incr_clip(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector is
begin
return std_logic_vector(incr_clip(unsigned(old_value), increment));
end function;
function incr_clip(old_value: unsigned; increment: natural := 1) return unsigned is
constant c_max_value : unsigned(old_value'range) := (others => '1');
variable v_result : unsigned(old_value'range);
begin
assert increment < 2**old_value'length report "ERROR: Increment value is larger than vector range" severity error;
if old_value <= (c_max_value - increment) then
v_result := old_value + increment;
else
v_result := c_max_value;
end if;
return v_result;
end function;
function incr_clip(old_value: signed; increment: natural := 1) return signed is
variable c_max_value : signed(old_value'range) := to_signed(2**old_value'length / 2 - 1, old_value'length);
variable v_result : signed(old_value'range);
begin
if old_value <= (c_max_value - increment) then
v_result := old_value + increment;
else
v_result := c_max_value;
end if;
return v_result;
end function;
function decr_clip(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector is
begin
return std_logic_vector(decr_clip(unsigned(old_value), decrement));
end function;
function decr_clip(old_value: unsigned; decrement: natural := 1) return unsigned is
constant c_min_value : unsigned(old_value'range) := (others => '0');
variable v_result : unsigned(old_value'range);
begin
if old_value >= (c_min_value + decrement) then
v_result := old_value - decrement;
else
v_result := c_min_value;
end if;
return v_result;
end function;
function decr_clip(old_value: signed; decrement: natural := 1) return signed is
constant c_min_value : signed(old_value'range) := to_signed(2**old_value'length / 2, old_value'length);
variable v_result : signed(old_value'range);
begin
if old_value >= (c_min_value + decrement) then
v_result := old_value - decrement;
else
v_result := c_min_value;
end if;
return v_result;
end function;
---------------------------------------------------------------------------
-- log functions
---------------------------------------------------------------------------
function log2(arg: integer) return natural is
begin
return log2_ceil(arg);
end function;
function log2(arg: integer; mode: log2mode) return natural is
begin
if mode = floor then
return log2_floor(arg);
else
return log2_ceil(arg);
end if;
end;
function log2_ceil(arg: integer) return natural is
variable v_temp : integer;
variable v_result : natural;
begin
v_result := log2_floor(arg);
if 2**v_result < arg then
return v_result + 1;
else
return v_result;
end if;
end function;
function log2_floor(arg: integer) return natural is
variable v_temp : integer;
variable v_result : natural;
begin
v_result := 0;
v_temp := arg / 2;
while v_temp /= 0 loop
v_temp := v_temp / 2;
v_result := v_result + 1;
end loop;
return v_result;
end function;
function log2(arg: unsigned) return natural is
begin
return log2_ceil(arg);
end function;
function log2(arg: unsigned; mode: log2mode) return natural is
begin
if mode = ceil then
return log2_ceil(arg);
else
return log2_floor(arg);
end if;
end function;
function log2_floor(arg: unsigned) return natural is
alias w : unsigned(arg'length - 1 downto 0) is arg;
begin
return highest_bit(w);
end function;
function log2_ceil(arg: unsigned) return natural is
alias w : unsigned(arg'length - 1 downto 0) is arg;
begin
if ones(arg) > 1 then
return highest_bit(w) + 1;
else
return highest_bit(w);
end if;
end function;
---------------------------------------------------------------------------
-- min/max
---------------------------------------------------------------------------
-- Description: These functions return the minimum/maximum of two values
---------------------------------------------------------------------------
function max(a, b: integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
end function;
function max(a, b: unsigned) return unsigned is
begin
if a > b then
return a;
else
return b;
end if;
end function;
function min(a, b: integer) return integer is
begin
if a < b then
return a;
else
return b;
end if;
end function;
function min(a, b: unsigned) return unsigned is
begin
if a < b then
return a;
else
return b;
end if;
end function;
end tl_math_pkg;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Miscelaneous mathematic operations
-------------------------------------------------------------------------------
-- Description: This file contains math functions
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package tl_math_pkg is
---------------------------------------------------------------------------
-- increment/decrement functions
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- wrapping decrement/increment
---------------------------------------------------------------------------
-- Description: These functions give an increment/decrement that wraps when
-- the maximal vector range is reached.
---------------------------------------------------------------------------
function incr(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector;
function incr(old_value: unsigned; increment: natural := 1) return unsigned;
function incr(old_value: signed; increment: natural := 1) return signed;
function decr(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector;
function decr(old_value: unsigned; decrement: natural := 1) return unsigned;
function decr(old_value: signed; decrement: natural := 1) return signed;
---------------------------------------------------------------------------
-- clipping decrement/increment
---------------------------------------------------------------------------
-- Description: These functions give an increment/decrement that clips when
-- the maximal vector range is reached.
---------------------------------------------------------------------------
function incr_clip(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector;
function incr_clip(old_value: unsigned; increment: natural := 1) return unsigned;
function incr_clip(old_value: signed; increment: natural := 1) return signed;
function decr_clip(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector;
function decr_clip(old_value: unsigned; decrement: natural := 1) return unsigned;
function decr_clip(old_value: signed; decrement: natural := 1) return signed;
---------------------------------------------------------------------------
-- log functions
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- log2
---------------------------------------------------------------------------
-- Description: This functions returns the log2 value of a number. The
-- result is in the natural range and rounded depended on the
-- selected mode.
-- NOTE: use an argument of type unsigned when using this function for
-- synthesis
---------------------------------------------------------------------------
type log2mode is (ceil, floor);
function log2(arg: integer) return natural;
function log2(arg: integer; mode: log2mode) return natural;
function log2_floor(arg: integer) return natural;
function log2_ceil(arg: integer) return natural;
function log2(arg: unsigned) return natural;
function log2(arg: unsigned; mode: log2mode) return natural;
function log2_floor(arg: unsigned) return natural;
function log2_ceil(arg: unsigned) return natural;
---------------------------------------------------------------------------
-- min/max
---------------------------------------------------------------------------
-- Description: These functions return the minimum/maximum of two values
---------------------------------------------------------------------------
function max(a, b: integer) return integer;
function max(a, b: unsigned) return unsigned;
function min(a, b: integer) return integer;
function min(a, b: unsigned) return unsigned;
end tl_math_pkg;
library work;
use work.tl_vector_pkg.all;
package body tl_math_pkg is
---------------------------------------------------------------------------
-- increment/decrement functions
---------------------------------------------------------------------------
function incr(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector is
begin
return std_logic_vector(incr(unsigned(old_value), increment));
end function;
function incr(old_value: unsigned; increment: natural := 1) return unsigned is
variable v_result : unsigned(old_value'range);
begin
v_result := (old_value + increment) mod 2**old_value'length;
return v_result;
end function;
function incr(old_value: signed; increment: natural := 1) return signed is
begin
return signed(incr(unsigned(old_value), increment));
end function;
function decr(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector is
begin
return std_logic_vector(decr(unsigned(old_value), decrement));
end function;
function decr(old_value: unsigned; decrement: natural := 1) return unsigned is
constant c_norm_decrement : integer := decrement mod 2**old_value'length;
variable v_result : unsigned(old_value'range);
begin
v_result := (2**old_value'length + (old_value - c_norm_decrement)) mod 2**old_value'length;
return v_result;
end function;
function decr(old_value: signed; decrement: natural := 1) return signed is
begin
return signed(decr(unsigned(old_value), decrement));
end function;
---------------------------------------------------------------------------
-- clipping decrement/increment
---------------------------------------------------------------------------
-- Description: These functions give an increment/decrement that clips when
-- the maximal vector range is reached.
---------------------------------------------------------------------------
function incr_clip(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector is
begin
return std_logic_vector(incr_clip(unsigned(old_value), increment));
end function;
function incr_clip(old_value: unsigned; increment: natural := 1) return unsigned is
constant c_max_value : unsigned(old_value'range) := (others => '1');
variable v_result : unsigned(old_value'range);
begin
assert increment < 2**old_value'length report "ERROR: Increment value is larger than vector range" severity error;
if old_value <= (c_max_value - increment) then
v_result := old_value + increment;
else
v_result := c_max_value;
end if;
return v_result;
end function;
function incr_clip(old_value: signed; increment: natural := 1) return signed is
variable c_max_value : signed(old_value'range) := to_signed(2**old_value'length / 2 - 1, old_value'length);
variable v_result : signed(old_value'range);
begin
if old_value <= (c_max_value - increment) then
v_result := old_value + increment;
else
v_result := c_max_value;
end if;
return v_result;
end function;
function decr_clip(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector is
begin
return std_logic_vector(decr_clip(unsigned(old_value), decrement));
end function;
function decr_clip(old_value: unsigned; decrement: natural := 1) return unsigned is
constant c_min_value : unsigned(old_value'range) := (others => '0');
variable v_result : unsigned(old_value'range);
begin
if old_value >= (c_min_value + decrement) then
v_result := old_value - decrement;
else
v_result := c_min_value;
end if;
return v_result;
end function;
function decr_clip(old_value: signed; decrement: natural := 1) return signed is
constant c_min_value : signed(old_value'range) := to_signed(2**old_value'length / 2, old_value'length);
variable v_result : signed(old_value'range);
begin
if old_value >= (c_min_value + decrement) then
v_result := old_value - decrement;
else
v_result := c_min_value;
end if;
return v_result;
end function;
---------------------------------------------------------------------------
-- log functions
---------------------------------------------------------------------------
function log2(arg: integer) return natural is
begin
return log2_ceil(arg);
end function;
function log2(arg: integer; mode: log2mode) return natural is
begin
if mode = floor then
return log2_floor(arg);
else
return log2_ceil(arg);
end if;
end;
function log2_ceil(arg: integer) return natural is
variable v_temp : integer;
variable v_result : natural;
begin
v_result := log2_floor(arg);
if 2**v_result < arg then
return v_result + 1;
else
return v_result;
end if;
end function;
function log2_floor(arg: integer) return natural is
variable v_temp : integer;
variable v_result : natural;
begin
v_result := 0;
v_temp := arg / 2;
while v_temp /= 0 loop
v_temp := v_temp / 2;
v_result := v_result + 1;
end loop;
return v_result;
end function;
function log2(arg: unsigned) return natural is
begin
return log2_ceil(arg);
end function;
function log2(arg: unsigned; mode: log2mode) return natural is
begin
if mode = ceil then
return log2_ceil(arg);
else
return log2_floor(arg);
end if;
end function;
function log2_floor(arg: unsigned) return natural is
alias w : unsigned(arg'length - 1 downto 0) is arg;
begin
return highest_bit(w);
end function;
function log2_ceil(arg: unsigned) return natural is
alias w : unsigned(arg'length - 1 downto 0) is arg;
begin
if ones(arg) > 1 then
return highest_bit(w) + 1;
else
return highest_bit(w);
end if;
end function;
---------------------------------------------------------------------------
-- min/max
---------------------------------------------------------------------------
-- Description: These functions return the minimum/maximum of two values
---------------------------------------------------------------------------
function max(a, b: integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
end function;
function max(a, b: unsigned) return unsigned is
begin
if a > b then
return a;
else
return b;
end if;
end function;
function min(a, b: integer) return integer is
begin
if a < b then
return a;
else
return b;
end if;
end function;
function min(a, b: unsigned) return unsigned is
begin
if a < b then
return a;
else
return b;
end if;
end function;
end tl_math_pkg;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Miscelaneous mathematic operations
-------------------------------------------------------------------------------
-- Description: This file contains math functions
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package tl_math_pkg is
---------------------------------------------------------------------------
-- increment/decrement functions
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- wrapping decrement/increment
---------------------------------------------------------------------------
-- Description: These functions give an increment/decrement that wraps when
-- the maximal vector range is reached.
---------------------------------------------------------------------------
function incr(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector;
function incr(old_value: unsigned; increment: natural := 1) return unsigned;
function incr(old_value: signed; increment: natural := 1) return signed;
function decr(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector;
function decr(old_value: unsigned; decrement: natural := 1) return unsigned;
function decr(old_value: signed; decrement: natural := 1) return signed;
---------------------------------------------------------------------------
-- clipping decrement/increment
---------------------------------------------------------------------------
-- Description: These functions give an increment/decrement that clips when
-- the maximal vector range is reached.
---------------------------------------------------------------------------
function incr_clip(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector;
function incr_clip(old_value: unsigned; increment: natural := 1) return unsigned;
function incr_clip(old_value: signed; increment: natural := 1) return signed;
function decr_clip(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector;
function decr_clip(old_value: unsigned; decrement: natural := 1) return unsigned;
function decr_clip(old_value: signed; decrement: natural := 1) return signed;
---------------------------------------------------------------------------
-- log functions
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- log2
---------------------------------------------------------------------------
-- Description: This functions returns the log2 value of a number. The
-- result is in the natural range and rounded depended on the
-- selected mode.
-- NOTE: use an argument of type unsigned when using this function for
-- synthesis
---------------------------------------------------------------------------
type log2mode is (ceil, floor);
function log2(arg: integer) return natural;
function log2(arg: integer; mode: log2mode) return natural;
function log2_floor(arg: integer) return natural;
function log2_ceil(arg: integer) return natural;
function log2(arg: unsigned) return natural;
function log2(arg: unsigned; mode: log2mode) return natural;
function log2_floor(arg: unsigned) return natural;
function log2_ceil(arg: unsigned) return natural;
---------------------------------------------------------------------------
-- min/max
---------------------------------------------------------------------------
-- Description: These functions return the minimum/maximum of two values
---------------------------------------------------------------------------
function max(a, b: integer) return integer;
function max(a, b: unsigned) return unsigned;
function min(a, b: integer) return integer;
function min(a, b: unsigned) return unsigned;
end tl_math_pkg;
library work;
use work.tl_vector_pkg.all;
package body tl_math_pkg is
---------------------------------------------------------------------------
-- increment/decrement functions
---------------------------------------------------------------------------
function incr(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector is
begin
return std_logic_vector(incr(unsigned(old_value), increment));
end function;
function incr(old_value: unsigned; increment: natural := 1) return unsigned is
variable v_result : unsigned(old_value'range);
begin
v_result := (old_value + increment) mod 2**old_value'length;
return v_result;
end function;
function incr(old_value: signed; increment: natural := 1) return signed is
begin
return signed(incr(unsigned(old_value), increment));
end function;
function decr(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector is
begin
return std_logic_vector(decr(unsigned(old_value), decrement));
end function;
function decr(old_value: unsigned; decrement: natural := 1) return unsigned is
constant c_norm_decrement : integer := decrement mod 2**old_value'length;
variable v_result : unsigned(old_value'range);
begin
v_result := (2**old_value'length + (old_value - c_norm_decrement)) mod 2**old_value'length;
return v_result;
end function;
function decr(old_value: signed; decrement: natural := 1) return signed is
begin
return signed(decr(unsigned(old_value), decrement));
end function;
---------------------------------------------------------------------------
-- clipping decrement/increment
---------------------------------------------------------------------------
-- Description: These functions give an increment/decrement that clips when
-- the maximal vector range is reached.
---------------------------------------------------------------------------
function incr_clip(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector is
begin
return std_logic_vector(incr_clip(unsigned(old_value), increment));
end function;
function incr_clip(old_value: unsigned; increment: natural := 1) return unsigned is
constant c_max_value : unsigned(old_value'range) := (others => '1');
variable v_result : unsigned(old_value'range);
begin
assert increment < 2**old_value'length report "ERROR: Increment value is larger than vector range" severity error;
if old_value <= (c_max_value - increment) then
v_result := old_value + increment;
else
v_result := c_max_value;
end if;
return v_result;
end function;
function incr_clip(old_value: signed; increment: natural := 1) return signed is
variable c_max_value : signed(old_value'range) := to_signed(2**old_value'length / 2 - 1, old_value'length);
variable v_result : signed(old_value'range);
begin
if old_value <= (c_max_value - increment) then
v_result := old_value + increment;
else
v_result := c_max_value;
end if;
return v_result;
end function;
function decr_clip(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector is
begin
return std_logic_vector(decr_clip(unsigned(old_value), decrement));
end function;
function decr_clip(old_value: unsigned; decrement: natural := 1) return unsigned is
constant c_min_value : unsigned(old_value'range) := (others => '0');
variable v_result : unsigned(old_value'range);
begin
if old_value >= (c_min_value + decrement) then
v_result := old_value - decrement;
else
v_result := c_min_value;
end if;
return v_result;
end function;
function decr_clip(old_value: signed; decrement: natural := 1) return signed is
constant c_min_value : signed(old_value'range) := to_signed(2**old_value'length / 2, old_value'length);
variable v_result : signed(old_value'range);
begin
if old_value >= (c_min_value + decrement) then
v_result := old_value - decrement;
else
v_result := c_min_value;
end if;
return v_result;
end function;
---------------------------------------------------------------------------
-- log functions
---------------------------------------------------------------------------
function log2(arg: integer) return natural is
begin
return log2_ceil(arg);
end function;
function log2(arg: integer; mode: log2mode) return natural is
begin
if mode = floor then
return log2_floor(arg);
else
return log2_ceil(arg);
end if;
end;
function log2_ceil(arg: integer) return natural is
variable v_temp : integer;
variable v_result : natural;
begin
v_result := log2_floor(arg);
if 2**v_result < arg then
return v_result + 1;
else
return v_result;
end if;
end function;
function log2_floor(arg: integer) return natural is
variable v_temp : integer;
variable v_result : natural;
begin
v_result := 0;
v_temp := arg / 2;
while v_temp /= 0 loop
v_temp := v_temp / 2;
v_result := v_result + 1;
end loop;
return v_result;
end function;
function log2(arg: unsigned) return natural is
begin
return log2_ceil(arg);
end function;
function log2(arg: unsigned; mode: log2mode) return natural is
begin
if mode = ceil then
return log2_ceil(arg);
else
return log2_floor(arg);
end if;
end function;
function log2_floor(arg: unsigned) return natural is
alias w : unsigned(arg'length - 1 downto 0) is arg;
begin
return highest_bit(w);
end function;
function log2_ceil(arg: unsigned) return natural is
alias w : unsigned(arg'length - 1 downto 0) is arg;
begin
if ones(arg) > 1 then
return highest_bit(w) + 1;
else
return highest_bit(w);
end if;
end function;
---------------------------------------------------------------------------
-- min/max
---------------------------------------------------------------------------
-- Description: These functions return the minimum/maximum of two values
---------------------------------------------------------------------------
function max(a, b: integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
end function;
function max(a, b: unsigned) return unsigned is
begin
if a > b then
return a;
else
return b;
end if;
end function;
function min(a, b: integer) return integer is
begin
if a < b then
return a;
else
return b;
end if;
end function;
function min(a, b: unsigned) return unsigned is
begin
if a < b then
return a;
else
return b;
end if;
end function;
end tl_math_pkg;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Miscelaneous mathematic operations
-------------------------------------------------------------------------------
-- Description: This file contains math functions
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package tl_math_pkg is
---------------------------------------------------------------------------
-- increment/decrement functions
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- wrapping decrement/increment
---------------------------------------------------------------------------
-- Description: These functions give an increment/decrement that wraps when
-- the maximal vector range is reached.
---------------------------------------------------------------------------
function incr(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector;
function incr(old_value: unsigned; increment: natural := 1) return unsigned;
function incr(old_value: signed; increment: natural := 1) return signed;
function decr(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector;
function decr(old_value: unsigned; decrement: natural := 1) return unsigned;
function decr(old_value: signed; decrement: natural := 1) return signed;
---------------------------------------------------------------------------
-- clipping decrement/increment
---------------------------------------------------------------------------
-- Description: These functions give an increment/decrement that clips when
-- the maximal vector range is reached.
---------------------------------------------------------------------------
function incr_clip(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector;
function incr_clip(old_value: unsigned; increment: natural := 1) return unsigned;
function incr_clip(old_value: signed; increment: natural := 1) return signed;
function decr_clip(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector;
function decr_clip(old_value: unsigned; decrement: natural := 1) return unsigned;
function decr_clip(old_value: signed; decrement: natural := 1) return signed;
---------------------------------------------------------------------------
-- log functions
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- log2
---------------------------------------------------------------------------
-- Description: This functions returns the log2 value of a number. The
-- result is in the natural range and rounded depended on the
-- selected mode.
-- NOTE: use an argument of type unsigned when using this function for
-- synthesis
---------------------------------------------------------------------------
type log2mode is (ceil, floor);
function log2(arg: integer) return natural;
function log2(arg: integer; mode: log2mode) return natural;
function log2_floor(arg: integer) return natural;
function log2_ceil(arg: integer) return natural;
function log2(arg: unsigned) return natural;
function log2(arg: unsigned; mode: log2mode) return natural;
function log2_floor(arg: unsigned) return natural;
function log2_ceil(arg: unsigned) return natural;
---------------------------------------------------------------------------
-- min/max
---------------------------------------------------------------------------
-- Description: These functions return the minimum/maximum of two values
---------------------------------------------------------------------------
function max(a, b: integer) return integer;
function max(a, b: unsigned) return unsigned;
function min(a, b: integer) return integer;
function min(a, b: unsigned) return unsigned;
end tl_math_pkg;
library work;
use work.tl_vector_pkg.all;
package body tl_math_pkg is
---------------------------------------------------------------------------
-- increment/decrement functions
---------------------------------------------------------------------------
function incr(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector is
begin
return std_logic_vector(incr(unsigned(old_value), increment));
end function;
function incr(old_value: unsigned; increment: natural := 1) return unsigned is
variable v_result : unsigned(old_value'range);
begin
v_result := (old_value + increment) mod 2**old_value'length;
return v_result;
end function;
function incr(old_value: signed; increment: natural := 1) return signed is
begin
return signed(incr(unsigned(old_value), increment));
end function;
function decr(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector is
begin
return std_logic_vector(decr(unsigned(old_value), decrement));
end function;
function decr(old_value: unsigned; decrement: natural := 1) return unsigned is
constant c_norm_decrement : integer := decrement mod 2**old_value'length;
variable v_result : unsigned(old_value'range);
begin
v_result := (2**old_value'length + (old_value - c_norm_decrement)) mod 2**old_value'length;
return v_result;
end function;
function decr(old_value: signed; decrement: natural := 1) return signed is
begin
return signed(decr(unsigned(old_value), decrement));
end function;
---------------------------------------------------------------------------
-- clipping decrement/increment
---------------------------------------------------------------------------
-- Description: These functions give an increment/decrement that clips when
-- the maximal vector range is reached.
---------------------------------------------------------------------------
function incr_clip(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector is
begin
return std_logic_vector(incr_clip(unsigned(old_value), increment));
end function;
function incr_clip(old_value: unsigned; increment: natural := 1) return unsigned is
constant c_max_value : unsigned(old_value'range) := (others => '1');
variable v_result : unsigned(old_value'range);
begin
assert increment < 2**old_value'length report "ERROR: Increment value is larger than vector range" severity error;
if old_value <= (c_max_value - increment) then
v_result := old_value + increment;
else
v_result := c_max_value;
end if;
return v_result;
end function;
function incr_clip(old_value: signed; increment: natural := 1) return signed is
variable c_max_value : signed(old_value'range) := to_signed(2**old_value'length / 2 - 1, old_value'length);
variable v_result : signed(old_value'range);
begin
if old_value <= (c_max_value - increment) then
v_result := old_value + increment;
else
v_result := c_max_value;
end if;
return v_result;
end function;
function decr_clip(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector is
begin
return std_logic_vector(decr_clip(unsigned(old_value), decrement));
end function;
function decr_clip(old_value: unsigned; decrement: natural := 1) return unsigned is
constant c_min_value : unsigned(old_value'range) := (others => '0');
variable v_result : unsigned(old_value'range);
begin
if old_value >= (c_min_value + decrement) then
v_result := old_value - decrement;
else
v_result := c_min_value;
end if;
return v_result;
end function;
function decr_clip(old_value: signed; decrement: natural := 1) return signed is
constant c_min_value : signed(old_value'range) := to_signed(2**old_value'length / 2, old_value'length);
variable v_result : signed(old_value'range);
begin
if old_value >= (c_min_value + decrement) then
v_result := old_value - decrement;
else
v_result := c_min_value;
end if;
return v_result;
end function;
---------------------------------------------------------------------------
-- log functions
---------------------------------------------------------------------------
function log2(arg: integer) return natural is
begin
return log2_ceil(arg);
end function;
function log2(arg: integer; mode: log2mode) return natural is
begin
if mode = floor then
return log2_floor(arg);
else
return log2_ceil(arg);
end if;
end;
function log2_ceil(arg: integer) return natural is
variable v_temp : integer;
variable v_result : natural;
begin
v_result := log2_floor(arg);
if 2**v_result < arg then
return v_result + 1;
else
return v_result;
end if;
end function;
function log2_floor(arg: integer) return natural is
variable v_temp : integer;
variable v_result : natural;
begin
v_result := 0;
v_temp := arg / 2;
while v_temp /= 0 loop
v_temp := v_temp / 2;
v_result := v_result + 1;
end loop;
return v_result;
end function;
function log2(arg: unsigned) return natural is
begin
return log2_ceil(arg);
end function;
function log2(arg: unsigned; mode: log2mode) return natural is
begin
if mode = ceil then
return log2_ceil(arg);
else
return log2_floor(arg);
end if;
end function;
function log2_floor(arg: unsigned) return natural is
alias w : unsigned(arg'length - 1 downto 0) is arg;
begin
return highest_bit(w);
end function;
function log2_ceil(arg: unsigned) return natural is
alias w : unsigned(arg'length - 1 downto 0) is arg;
begin
if ones(arg) > 1 then
return highest_bit(w) + 1;
else
return highest_bit(w);
end if;
end function;
---------------------------------------------------------------------------
-- min/max
---------------------------------------------------------------------------
-- Description: These functions return the minimum/maximum of two values
---------------------------------------------------------------------------
function max(a, b: integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
end function;
function max(a, b: unsigned) return unsigned is
begin
if a > b then
return a;
else
return b;
end if;
end function;
function min(a, b: integer) return integer is
begin
if a < b then
return a;
else
return b;
end if;
end function;
function min(a, b: unsigned) return unsigned is
begin
if a < b then
return a;
else
return b;
end if;
end function;
end tl_math_pkg;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Miscelaneous mathematic operations
-------------------------------------------------------------------------------
-- Description: This file contains math functions
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package tl_math_pkg is
---------------------------------------------------------------------------
-- increment/decrement functions
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- wrapping decrement/increment
---------------------------------------------------------------------------
-- Description: These functions give an increment/decrement that wraps when
-- the maximal vector range is reached.
---------------------------------------------------------------------------
function incr(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector;
function incr(old_value: unsigned; increment: natural := 1) return unsigned;
function incr(old_value: signed; increment: natural := 1) return signed;
function decr(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector;
function decr(old_value: unsigned; decrement: natural := 1) return unsigned;
function decr(old_value: signed; decrement: natural := 1) return signed;
---------------------------------------------------------------------------
-- clipping decrement/increment
---------------------------------------------------------------------------
-- Description: These functions give an increment/decrement that clips when
-- the maximal vector range is reached.
---------------------------------------------------------------------------
function incr_clip(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector;
function incr_clip(old_value: unsigned; increment: natural := 1) return unsigned;
function incr_clip(old_value: signed; increment: natural := 1) return signed;
function decr_clip(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector;
function decr_clip(old_value: unsigned; decrement: natural := 1) return unsigned;
function decr_clip(old_value: signed; decrement: natural := 1) return signed;
---------------------------------------------------------------------------
-- log functions
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- log2
---------------------------------------------------------------------------
-- Description: This functions returns the log2 value of a number. The
-- result is in the natural range and rounded depended on the
-- selected mode.
-- NOTE: use an argument of type unsigned when using this function for
-- synthesis
---------------------------------------------------------------------------
type log2mode is (ceil, floor);
function log2(arg: integer) return natural;
function log2(arg: integer; mode: log2mode) return natural;
function log2_floor(arg: integer) return natural;
function log2_ceil(arg: integer) return natural;
function log2(arg: unsigned) return natural;
function log2(arg: unsigned; mode: log2mode) return natural;
function log2_floor(arg: unsigned) return natural;
function log2_ceil(arg: unsigned) return natural;
---------------------------------------------------------------------------
-- min/max
---------------------------------------------------------------------------
-- Description: These functions return the minimum/maximum of two values
---------------------------------------------------------------------------
function max(a, b: integer) return integer;
function max(a, b: unsigned) return unsigned;
function min(a, b: integer) return integer;
function min(a, b: unsigned) return unsigned;
end tl_math_pkg;
library work;
use work.tl_vector_pkg.all;
package body tl_math_pkg is
---------------------------------------------------------------------------
-- increment/decrement functions
---------------------------------------------------------------------------
function incr(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector is
begin
return std_logic_vector(incr(unsigned(old_value), increment));
end function;
function incr(old_value: unsigned; increment: natural := 1) return unsigned is
variable v_result : unsigned(old_value'range);
begin
v_result := (old_value + increment) mod 2**old_value'length;
return v_result;
end function;
function incr(old_value: signed; increment: natural := 1) return signed is
begin
return signed(incr(unsigned(old_value), increment));
end function;
function decr(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector is
begin
return std_logic_vector(decr(unsigned(old_value), decrement));
end function;
function decr(old_value: unsigned; decrement: natural := 1) return unsigned is
constant c_norm_decrement : integer := decrement mod 2**old_value'length;
variable v_result : unsigned(old_value'range);
begin
v_result := (2**old_value'length + (old_value - c_norm_decrement)) mod 2**old_value'length;
return v_result;
end function;
function decr(old_value: signed; decrement: natural := 1) return signed is
begin
return signed(decr(unsigned(old_value), decrement));
end function;
---------------------------------------------------------------------------
-- clipping decrement/increment
---------------------------------------------------------------------------
-- Description: These functions give an increment/decrement that clips when
-- the maximal vector range is reached.
---------------------------------------------------------------------------
function incr_clip(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector is
begin
return std_logic_vector(incr_clip(unsigned(old_value), increment));
end function;
function incr_clip(old_value: unsigned; increment: natural := 1) return unsigned is
constant c_max_value : unsigned(old_value'range) := (others => '1');
variable v_result : unsigned(old_value'range);
begin
assert increment < 2**old_value'length report "ERROR: Increment value is larger than vector range" severity error;
if old_value <= (c_max_value - increment) then
v_result := old_value + increment;
else
v_result := c_max_value;
end if;
return v_result;
end function;
function incr_clip(old_value: signed; increment: natural := 1) return signed is
variable c_max_value : signed(old_value'range) := to_signed(2**old_value'length / 2 - 1, old_value'length);
variable v_result : signed(old_value'range);
begin
if old_value <= (c_max_value - increment) then
v_result := old_value + increment;
else
v_result := c_max_value;
end if;
return v_result;
end function;
function decr_clip(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector is
begin
return std_logic_vector(decr_clip(unsigned(old_value), decrement));
end function;
function decr_clip(old_value: unsigned; decrement: natural := 1) return unsigned is
constant c_min_value : unsigned(old_value'range) := (others => '0');
variable v_result : unsigned(old_value'range);
begin
if old_value >= (c_min_value + decrement) then
v_result := old_value - decrement;
else
v_result := c_min_value;
end if;
return v_result;
end function;
function decr_clip(old_value: signed; decrement: natural := 1) return signed is
constant c_min_value : signed(old_value'range) := to_signed(2**old_value'length / 2, old_value'length);
variable v_result : signed(old_value'range);
begin
if old_value >= (c_min_value + decrement) then
v_result := old_value - decrement;
else
v_result := c_min_value;
end if;
return v_result;
end function;
---------------------------------------------------------------------------
-- log functions
---------------------------------------------------------------------------
function log2(arg: integer) return natural is
begin
return log2_ceil(arg);
end function;
function log2(arg: integer; mode: log2mode) return natural is
begin
if mode = floor then
return log2_floor(arg);
else
return log2_ceil(arg);
end if;
end;
function log2_ceil(arg: integer) return natural is
variable v_temp : integer;
variable v_result : natural;
begin
v_result := log2_floor(arg);
if 2**v_result < arg then
return v_result + 1;
else
return v_result;
end if;
end function;
function log2_floor(arg: integer) return natural is
variable v_temp : integer;
variable v_result : natural;
begin
v_result := 0;
v_temp := arg / 2;
while v_temp /= 0 loop
v_temp := v_temp / 2;
v_result := v_result + 1;
end loop;
return v_result;
end function;
function log2(arg: unsigned) return natural is
begin
return log2_ceil(arg);
end function;
function log2(arg: unsigned; mode: log2mode) return natural is
begin
if mode = ceil then
return log2_ceil(arg);
else
return log2_floor(arg);
end if;
end function;
function log2_floor(arg: unsigned) return natural is
alias w : unsigned(arg'length - 1 downto 0) is arg;
begin
return highest_bit(w);
end function;
function log2_ceil(arg: unsigned) return natural is
alias w : unsigned(arg'length - 1 downto 0) is arg;
begin
if ones(arg) > 1 then
return highest_bit(w) + 1;
else
return highest_bit(w);
end if;
end function;
---------------------------------------------------------------------------
-- min/max
---------------------------------------------------------------------------
-- Description: These functions return the minimum/maximum of two values
---------------------------------------------------------------------------
function max(a, b: integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
end function;
function max(a, b: unsigned) return unsigned is
begin
if a > b then
return a;
else
return b;
end if;
end function;
function min(a, b: integer) return integer is
begin
if a < b then
return a;
else
return b;
end if;
end function;
function min(a, b: unsigned) return unsigned is
begin
if a < b then
return a;
else
return b;
end if;
end function;
end tl_math_pkg;
|
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Basic test for the unbounded arrays in VHDL.
library ieee;
use ieee.std_logic_1164.all;
entity vhdl_unbounded_array is
end vhdl_unbounded_array;
architecture test of vhdl_unbounded_array is
-- This can be translated as an unpacked array in SystemVerilog
type unb_logic is array (integer range <>) of std_logic;
-- These have to be packed arrays
type unb_integer is array (natural range <>) of integer;
type unb_real is array (integer range <>) of real;
signal sig_logic : unb_logic(7 downto 0);
signal sig_integer : unb_integer(3 downto 0);
signal sig_real : unb_real(0 to 3);
begin
sig_logic <= "01010101";
sig_integer(2) <= 1;
sig_real(1) <= 2.5;
end architecture test;
|
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Basic test for the unbounded arrays in VHDL.
library ieee;
use ieee.std_logic_1164.all;
entity vhdl_unbounded_array is
end vhdl_unbounded_array;
architecture test of vhdl_unbounded_array is
-- This can be translated as an unpacked array in SystemVerilog
type unb_logic is array (integer range <>) of std_logic;
-- These have to be packed arrays
type unb_integer is array (natural range <>) of integer;
type unb_real is array (integer range <>) of real;
signal sig_logic : unb_logic(7 downto 0);
signal sig_integer : unb_integer(3 downto 0);
signal sig_real : unb_real(0 to 3);
begin
sig_logic <= "01010101";
sig_integer(2) <= 1;
sig_real(1) <= 2.5;
end architecture test;
|
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Basic test for the unbounded arrays in VHDL.
library ieee;
use ieee.std_logic_1164.all;
entity vhdl_unbounded_array is
end vhdl_unbounded_array;
architecture test of vhdl_unbounded_array is
-- This can be translated as an unpacked array in SystemVerilog
type unb_logic is array (integer range <>) of std_logic;
-- These have to be packed arrays
type unb_integer is array (natural range <>) of integer;
type unb_real is array (integer range <>) of real;
signal sig_logic : unb_logic(7 downto 0);
signal sig_integer : unb_integer(3 downto 0);
signal sig_real : unb_real(0 to 3);
begin
sig_logic <= "01010101";
sig_integer(2) <= 1;
sig_real(1) <= 2.5;
end architecture test;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity fpdiv_tb is
end fpdiv_tb;
architecture Behavioral of fpdiv_tb is
constant clk_period : time := 10 ns;
signal clk : std_logic := '0';
signal rst : std_logic;
constant precision : integer := 13;
constant inputbits : integer := precision + 5;
constant timerbits : integer := 18;
constant nscalestages : integer := 6;
signal dividend : unsigned (inputbits-1 downto 0);
signal divisor : unsigned (timerbits-1 downto 0);
signal ratio : unsigned (precision-1 downto 0);
signal scale : signed (nscalestages-1 downto 0);
signal busy : std_logic;
signal overflow : std_logic;
signal strobe : std_logic := '0';
begin
clk <= not clk after clk_period/2;
stim : process
begin
rst <= '1';
wait for clk_period * 10;
rst <= '0';
wait for clk_period;
assert busy = '0' report "Divider is still busy" severity error;
dividend <= to_unsigned(1, dividend'length);
divisor <= to_unsigned(262143, divisor'length);
strobe <= '1';
wait for clk_period;
strobe <= '0';
wait for clk_period * 24;
assert overflow = '1' report "Test should have overflowed" severity error;
assert busy = '0' report "Divider is still busy" severity error;
dividend <= to_unsigned(0, dividend'length);
divisor <= to_unsigned(262143, divisor'length);
strobe <= '1';
wait for clk_period;
strobe <= '0';
wait for clk_period * 24;
assert overflow = '0' report "Test should have overflowed" severity error;
assert ratio = 0 report "Bad quotient" severity error;
assert scale = 0 report "Bad scale" severity error;
assert busy = '0' report "Divider is still busy" severity error;
dividend <= to_unsigned(27, dividend'length);
divisor <= to_unsigned(4, divisor'length);
strobe <= '1';
wait for clk_period;
strobe <= '0';
wait for clk_period * 24;
assert ratio = 6912 report "Bad quotient" severity error;
assert scale = -10 report "Bad scale" severity error;
assert busy = '0' report "Divider is still busy" severity error;
dividend <= to_unsigned(3277, dividend'length);
divisor <= to_unsigned(8192, divisor'length);
strobe <= '1';
wait for clk_period;
strobe <= '0';
wait for clk_period * 24;
assert ratio = 6554 report "Bad quotient" severity error;
assert scale = -14 report "Bad scale" severity error;
assert busy = '0' report "Divider is still busy" severity error;
dividend <= to_unsigned(1, dividend'length);
divisor <= to_unsigned(8193, divisor'length);
strobe <= '1';
wait for clk_period;
strobe <= '0';
wait for clk_period * 36;
assert overflow = '1' report "Test should overflow" severity error;
assert busy = '0' report "Divider is still busy" severity error;
dividend <= to_unsigned(1, dividend'length);
divisor <= to_unsigned(9, divisor'length);
strobe <= '1';
wait for clk_period;
strobe <= '0';
wait for clk_period * 24;
assert ratio = 7280 report "Bad quotient" severity error;
assert scale = -16 report "Bad scale" severity error;
assert busy = '0' report "Divider is still busy" severity error;
dividend <= (others => '1');
divisor <= to_unsigned(1, divisor'length);
strobe <= '1';
wait for clk_period;
strobe <= '0';
wait for clk_period * 24;
assert overflow = '1' report "Test should have overflowed" severity error;
-- FIXME formulate a divisor overflow test
wait;
end process;
dut : entity work.fpdiv
generic map (
size => divisor'length,
precision => ratio'length,
pscale => scale'length )
port map (
dividend => dividend,
divisor => divisor,
quotient => ratio,
scale => scale,
busy => busy,
overflow => overflow,
strobe => strobe,
clk => clk,
rst => rst );
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_in_one_hot_with_checkers_top is
port ( req_X_N, req_X_E, req_X_W, req_X_S, req_X_L:in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_in's FSM
X_N, X_E, X_W, X_S, X_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: out std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in_one_hot_with_checkers_top;
architecture behavior of Arbiter_in_one_hot_with_checkers_top is
component arbiter_in_one_hot_pseudo is
port ( req_X_N, req_X_E, req_X_W, req_X_S, req_X_L:in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_in's FSM
X_N, X_E, X_W, X_S, X_L : out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: out std_logic_vector (5 downto 0) -- 6 states for Arbiter's FSM
);
end component;
component Arbiter_in_one_hot_checkers is
port (
req_X_N :in std_logic;
req_X_E :in std_logic;
req_X_W :in std_logic;
req_X_S :in std_logic;
req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N :in std_logic;
X_E :in std_logic;
X_W :in std_logic;
X_S :in std_logic;
X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end component;
signal X_N_sig, X_E_sig, X_W_sig, X_S_sig, X_L_sig: std_logic;
signal state_in_sig: std_logic_vector (5 downto 0);
begin
X_N <= X_N_sig;
X_E <= X_E_sig;
X_W <= X_W_sig;
X_S <= X_S_sig;
X_L <= X_L_sig;
state_in <= state_in_sig;
-- Arbiter instantiation
ARBITER_IN_ONE_HOT: arbiter_in_one_hot_pseudo port map (
req_X_N => req_X_N,
req_X_E => req_X_E,
req_X_W => req_X_W,
req_X_S => req_X_S,
req_X_L => req_X_L,
state => state,
X_N => X_N_sig,
X_E => X_E_sig,
X_W => X_W_sig,
X_S => X_S_sig,
X_L => X_L_sig,
state_in => state_in_sig
);
-- Checkers instantiation
CHECKERS: Arbiter_in_one_hot_checkers port map (
req_X_N => req_X_N,
req_X_E => req_X_E,
req_X_W => req_X_W,
req_X_S => req_X_S,
req_X_L => req_X_L,
state => state,
state_in => state_in_sig,
X_N => X_N_sig,
X_E => X_E_sig,
X_W => X_W_sig,
X_S => X_S_sig,
X_L => X_L_sig,
err_Requests_state_in_state_not_equal => err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => err_IDLE_Req_N,
err_IDLE_grant_N => err_IDLE_grant_N,
err_North_Req_N => err_North_Req_N,
err_North_grant_N => err_North_grant_N,
err_East_Req_E => err_East_Req_E,
err_East_grant_E => err_East_grant_E,
err_West_Req_W => err_West_Req_W,
err_West_grant_W => err_West_grant_W,
err_South_Req_S => err_South_Req_S,
err_South_grant_S => err_South_grant_S,
err_Local_Req_L => err_Local_Req_L,
err_Local_grant_L => err_Local_grant_L,
err_IDLE_Req_E => err_IDLE_Req_E,
err_IDLE_grant_E => err_IDLE_grant_E,
err_North_Req_E => err_North_Req_E,
err_North_grant_E => err_North_grant_E,
err_East_Req_W => err_East_Req_W,
err_East_grant_W => err_East_grant_W,
err_West_Req_S => err_West_Req_S,
err_West_grant_S => err_West_grant_S,
err_South_Req_L => err_South_Req_L,
err_South_grant_L => err_South_grant_L,
err_Local_Req_N => err_Local_Req_N,
err_Local_grant_N => err_Local_grant_N,
err_IDLE_Req_W => err_IDLE_Req_W,
err_IDLE_grant_W => err_IDLE_grant_W,
err_North_Req_W => err_North_Req_W,
err_North_grant_W => err_North_grant_W,
err_East_Req_S => err_East_Req_S,
err_East_grant_S => err_East_grant_S,
err_West_Req_L => err_West_Req_L,
err_West_grant_L => err_West_grant_L,
err_South_Req_N => err_South_Req_N,
err_South_grant_N => err_South_grant_N,
err_Local_Req_E => err_Local_Req_E,
err_Local_grant_E => err_Local_grant_E,
err_IDLE_Req_S => err_IDLE_Req_S,
err_IDLE_grant_S => err_IDLE_grant_S,
err_North_Req_S => err_North_Req_S,
err_North_grant_S => err_North_grant_S,
err_East_Req_L => err_East_Req_L,
err_East_grant_L => err_East_grant_L,
err_West_Req_N => err_West_Req_N,
err_West_grant_N => err_West_grant_N,
err_South_Req_E => err_South_Req_E,
err_South_grant_E => err_South_grant_E,
err_Local_Req_W => err_Local_Req_W,
err_Local_grant_W => err_Local_grant_W,
err_IDLE_Req_L => err_IDLE_Req_L,
err_IDLE_grant_L => err_IDLE_grant_L,
err_North_Req_L => err_North_Req_L,
err_North_grant_L => err_North_grant_L,
err_East_Req_N => err_East_Req_N,
err_East_grant_N => err_East_grant_N,
err_West_Req_E => err_West_Req_E,
err_West_grant_E => err_West_grant_E,
err_South_Req_W => err_South_Req_W,
err_South_grant_W => err_South_grant_W,
err_Local_Req_S => err_Local_Req_S,
err_Local_grant_S => err_Local_grant_S,
err_state_in_onehot => err_state_in_onehot,
err_no_request_grants => err_no_request_grants,
err_request_no_grants => err_request_no_grants,
err_no_Req_N_grant_N => err_no_Req_N_grant_N,
err_no_Req_E_grant_E => err_no_Req_E_grant_E,
err_no_Req_W_grant_W => err_no_Req_W_grant_W,
err_no_Req_S_grant_S => err_no_Req_S_grant_S,
err_no_Req_L_grant_L => err_no_Req_L_grant_L
);
end behavior; |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_in_one_hot_with_checkers_top is
port ( req_X_N, req_X_E, req_X_W, req_X_S, req_X_L:in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_in's FSM
X_N, X_E, X_W, X_S, X_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: out std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in_one_hot_with_checkers_top;
architecture behavior of Arbiter_in_one_hot_with_checkers_top is
component arbiter_in_one_hot_pseudo is
port ( req_X_N, req_X_E, req_X_W, req_X_S, req_X_L:in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_in's FSM
X_N, X_E, X_W, X_S, X_L : out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: out std_logic_vector (5 downto 0) -- 6 states for Arbiter's FSM
);
end component;
component Arbiter_in_one_hot_checkers is
port (
req_X_N :in std_logic;
req_X_E :in std_logic;
req_X_W :in std_logic;
req_X_S :in std_logic;
req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N :in std_logic;
X_E :in std_logic;
X_W :in std_logic;
X_S :in std_logic;
X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end component;
signal X_N_sig, X_E_sig, X_W_sig, X_S_sig, X_L_sig: std_logic;
signal state_in_sig: std_logic_vector (5 downto 0);
begin
X_N <= X_N_sig;
X_E <= X_E_sig;
X_W <= X_W_sig;
X_S <= X_S_sig;
X_L <= X_L_sig;
state_in <= state_in_sig;
-- Arbiter instantiation
ARBITER_IN_ONE_HOT: arbiter_in_one_hot_pseudo port map (
req_X_N => req_X_N,
req_X_E => req_X_E,
req_X_W => req_X_W,
req_X_S => req_X_S,
req_X_L => req_X_L,
state => state,
X_N => X_N_sig,
X_E => X_E_sig,
X_W => X_W_sig,
X_S => X_S_sig,
X_L => X_L_sig,
state_in => state_in_sig
);
-- Checkers instantiation
CHECKERS: Arbiter_in_one_hot_checkers port map (
req_X_N => req_X_N,
req_X_E => req_X_E,
req_X_W => req_X_W,
req_X_S => req_X_S,
req_X_L => req_X_L,
state => state,
state_in => state_in_sig,
X_N => X_N_sig,
X_E => X_E_sig,
X_W => X_W_sig,
X_S => X_S_sig,
X_L => X_L_sig,
err_Requests_state_in_state_not_equal => err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => err_IDLE_Req_N,
err_IDLE_grant_N => err_IDLE_grant_N,
err_North_Req_N => err_North_Req_N,
err_North_grant_N => err_North_grant_N,
err_East_Req_E => err_East_Req_E,
err_East_grant_E => err_East_grant_E,
err_West_Req_W => err_West_Req_W,
err_West_grant_W => err_West_grant_W,
err_South_Req_S => err_South_Req_S,
err_South_grant_S => err_South_grant_S,
err_Local_Req_L => err_Local_Req_L,
err_Local_grant_L => err_Local_grant_L,
err_IDLE_Req_E => err_IDLE_Req_E,
err_IDLE_grant_E => err_IDLE_grant_E,
err_North_Req_E => err_North_Req_E,
err_North_grant_E => err_North_grant_E,
err_East_Req_W => err_East_Req_W,
err_East_grant_W => err_East_grant_W,
err_West_Req_S => err_West_Req_S,
err_West_grant_S => err_West_grant_S,
err_South_Req_L => err_South_Req_L,
err_South_grant_L => err_South_grant_L,
err_Local_Req_N => err_Local_Req_N,
err_Local_grant_N => err_Local_grant_N,
err_IDLE_Req_W => err_IDLE_Req_W,
err_IDLE_grant_W => err_IDLE_grant_W,
err_North_Req_W => err_North_Req_W,
err_North_grant_W => err_North_grant_W,
err_East_Req_S => err_East_Req_S,
err_East_grant_S => err_East_grant_S,
err_West_Req_L => err_West_Req_L,
err_West_grant_L => err_West_grant_L,
err_South_Req_N => err_South_Req_N,
err_South_grant_N => err_South_grant_N,
err_Local_Req_E => err_Local_Req_E,
err_Local_grant_E => err_Local_grant_E,
err_IDLE_Req_S => err_IDLE_Req_S,
err_IDLE_grant_S => err_IDLE_grant_S,
err_North_Req_S => err_North_Req_S,
err_North_grant_S => err_North_grant_S,
err_East_Req_L => err_East_Req_L,
err_East_grant_L => err_East_grant_L,
err_West_Req_N => err_West_Req_N,
err_West_grant_N => err_West_grant_N,
err_South_Req_E => err_South_Req_E,
err_South_grant_E => err_South_grant_E,
err_Local_Req_W => err_Local_Req_W,
err_Local_grant_W => err_Local_grant_W,
err_IDLE_Req_L => err_IDLE_Req_L,
err_IDLE_grant_L => err_IDLE_grant_L,
err_North_Req_L => err_North_Req_L,
err_North_grant_L => err_North_grant_L,
err_East_Req_N => err_East_Req_N,
err_East_grant_N => err_East_grant_N,
err_West_Req_E => err_West_Req_E,
err_West_grant_E => err_West_grant_E,
err_South_Req_W => err_South_Req_W,
err_South_grant_W => err_South_grant_W,
err_Local_Req_S => err_Local_Req_S,
err_Local_grant_S => err_Local_grant_S,
err_state_in_onehot => err_state_in_onehot,
err_no_request_grants => err_no_request_grants,
err_request_no_grants => err_request_no_grants,
err_no_Req_N_grant_N => err_no_Req_N_grant_N,
err_no_Req_E_grant_E => err_no_Req_E_grant_E,
err_no_Req_W_grant_W => err_no_Req_W_grant_W,
err_no_Req_S_grant_S => err_no_Req_S_grant_S,
err_no_Req_L_grant_L => err_no_Req_L_grant_L
);
end behavior; |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_in_one_hot_with_checkers_top is
port ( req_X_N, req_X_E, req_X_W, req_X_S, req_X_L:in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_in's FSM
X_N, X_E, X_W, X_S, X_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: out std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in_one_hot_with_checkers_top;
architecture behavior of Arbiter_in_one_hot_with_checkers_top is
component arbiter_in_one_hot_pseudo is
port ( req_X_N, req_X_E, req_X_W, req_X_S, req_X_L:in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_in's FSM
X_N, X_E, X_W, X_S, X_L : out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: out std_logic_vector (5 downto 0) -- 6 states for Arbiter's FSM
);
end component;
component Arbiter_in_one_hot_checkers is
port (
req_X_N :in std_logic;
req_X_E :in std_logic;
req_X_W :in std_logic;
req_X_S :in std_logic;
req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N :in std_logic;
X_E :in std_logic;
X_W :in std_logic;
X_S :in std_logic;
X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end component;
signal X_N_sig, X_E_sig, X_W_sig, X_S_sig, X_L_sig: std_logic;
signal state_in_sig: std_logic_vector (5 downto 0);
begin
X_N <= X_N_sig;
X_E <= X_E_sig;
X_W <= X_W_sig;
X_S <= X_S_sig;
X_L <= X_L_sig;
state_in <= state_in_sig;
-- Arbiter instantiation
ARBITER_IN_ONE_HOT: arbiter_in_one_hot_pseudo port map (
req_X_N => req_X_N,
req_X_E => req_X_E,
req_X_W => req_X_W,
req_X_S => req_X_S,
req_X_L => req_X_L,
state => state,
X_N => X_N_sig,
X_E => X_E_sig,
X_W => X_W_sig,
X_S => X_S_sig,
X_L => X_L_sig,
state_in => state_in_sig
);
-- Checkers instantiation
CHECKERS: Arbiter_in_one_hot_checkers port map (
req_X_N => req_X_N,
req_X_E => req_X_E,
req_X_W => req_X_W,
req_X_S => req_X_S,
req_X_L => req_X_L,
state => state,
state_in => state_in_sig,
X_N => X_N_sig,
X_E => X_E_sig,
X_W => X_W_sig,
X_S => X_S_sig,
X_L => X_L_sig,
err_Requests_state_in_state_not_equal => err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => err_IDLE_Req_N,
err_IDLE_grant_N => err_IDLE_grant_N,
err_North_Req_N => err_North_Req_N,
err_North_grant_N => err_North_grant_N,
err_East_Req_E => err_East_Req_E,
err_East_grant_E => err_East_grant_E,
err_West_Req_W => err_West_Req_W,
err_West_grant_W => err_West_grant_W,
err_South_Req_S => err_South_Req_S,
err_South_grant_S => err_South_grant_S,
err_Local_Req_L => err_Local_Req_L,
err_Local_grant_L => err_Local_grant_L,
err_IDLE_Req_E => err_IDLE_Req_E,
err_IDLE_grant_E => err_IDLE_grant_E,
err_North_Req_E => err_North_Req_E,
err_North_grant_E => err_North_grant_E,
err_East_Req_W => err_East_Req_W,
err_East_grant_W => err_East_grant_W,
err_West_Req_S => err_West_Req_S,
err_West_grant_S => err_West_grant_S,
err_South_Req_L => err_South_Req_L,
err_South_grant_L => err_South_grant_L,
err_Local_Req_N => err_Local_Req_N,
err_Local_grant_N => err_Local_grant_N,
err_IDLE_Req_W => err_IDLE_Req_W,
err_IDLE_grant_W => err_IDLE_grant_W,
err_North_Req_W => err_North_Req_W,
err_North_grant_W => err_North_grant_W,
err_East_Req_S => err_East_Req_S,
err_East_grant_S => err_East_grant_S,
err_West_Req_L => err_West_Req_L,
err_West_grant_L => err_West_grant_L,
err_South_Req_N => err_South_Req_N,
err_South_grant_N => err_South_grant_N,
err_Local_Req_E => err_Local_Req_E,
err_Local_grant_E => err_Local_grant_E,
err_IDLE_Req_S => err_IDLE_Req_S,
err_IDLE_grant_S => err_IDLE_grant_S,
err_North_Req_S => err_North_Req_S,
err_North_grant_S => err_North_grant_S,
err_East_Req_L => err_East_Req_L,
err_East_grant_L => err_East_grant_L,
err_West_Req_N => err_West_Req_N,
err_West_grant_N => err_West_grant_N,
err_South_Req_E => err_South_Req_E,
err_South_grant_E => err_South_grant_E,
err_Local_Req_W => err_Local_Req_W,
err_Local_grant_W => err_Local_grant_W,
err_IDLE_Req_L => err_IDLE_Req_L,
err_IDLE_grant_L => err_IDLE_grant_L,
err_North_Req_L => err_North_Req_L,
err_North_grant_L => err_North_grant_L,
err_East_Req_N => err_East_Req_N,
err_East_grant_N => err_East_grant_N,
err_West_Req_E => err_West_Req_E,
err_West_grant_E => err_West_grant_E,
err_South_Req_W => err_South_Req_W,
err_South_grant_W => err_South_grant_W,
err_Local_Req_S => err_Local_Req_S,
err_Local_grant_S => err_Local_grant_S,
err_state_in_onehot => err_state_in_onehot,
err_no_request_grants => err_no_request_grants,
err_request_no_grants => err_request_no_grants,
err_no_Req_N_grant_N => err_no_Req_N_grant_N,
err_no_Req_E_grant_E => err_no_Req_E_grant_E,
err_no_Req_W_grant_W => err_no_Req_W_grant_W,
err_no_Req_S_grant_S => err_no_Req_S_grant_S,
err_no_Req_L_grant_L => err_no_Req_L_grant_L
);
end behavior; |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_in_one_hot_with_checkers_top is
port ( req_X_N, req_X_E, req_X_W, req_X_S, req_X_L:in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_in's FSM
X_N, X_E, X_W, X_S, X_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: out std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in_one_hot_with_checkers_top;
architecture behavior of Arbiter_in_one_hot_with_checkers_top is
component arbiter_in_one_hot_pseudo is
port ( req_X_N, req_X_E, req_X_W, req_X_S, req_X_L:in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_in's FSM
X_N, X_E, X_W, X_S, X_L : out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: out std_logic_vector (5 downto 0) -- 6 states for Arbiter's FSM
);
end component;
component Arbiter_in_one_hot_checkers is
port (
req_X_N :in std_logic;
req_X_E :in std_logic;
req_X_W :in std_logic;
req_X_S :in std_logic;
req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N :in std_logic;
X_E :in std_logic;
X_W :in std_logic;
X_S :in std_logic;
X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end component;
signal X_N_sig, X_E_sig, X_W_sig, X_S_sig, X_L_sig: std_logic;
signal state_in_sig: std_logic_vector (5 downto 0);
begin
X_N <= X_N_sig;
X_E <= X_E_sig;
X_W <= X_W_sig;
X_S <= X_S_sig;
X_L <= X_L_sig;
state_in <= state_in_sig;
-- Arbiter instantiation
ARBITER_IN_ONE_HOT: arbiter_in_one_hot_pseudo port map (
req_X_N => req_X_N,
req_X_E => req_X_E,
req_X_W => req_X_W,
req_X_S => req_X_S,
req_X_L => req_X_L,
state => state,
X_N => X_N_sig,
X_E => X_E_sig,
X_W => X_W_sig,
X_S => X_S_sig,
X_L => X_L_sig,
state_in => state_in_sig
);
-- Checkers instantiation
CHECKERS: Arbiter_in_one_hot_checkers port map (
req_X_N => req_X_N,
req_X_E => req_X_E,
req_X_W => req_X_W,
req_X_S => req_X_S,
req_X_L => req_X_L,
state => state,
state_in => state_in_sig,
X_N => X_N_sig,
X_E => X_E_sig,
X_W => X_W_sig,
X_S => X_S_sig,
X_L => X_L_sig,
err_Requests_state_in_state_not_equal => err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => err_IDLE_Req_N,
err_IDLE_grant_N => err_IDLE_grant_N,
err_North_Req_N => err_North_Req_N,
err_North_grant_N => err_North_grant_N,
err_East_Req_E => err_East_Req_E,
err_East_grant_E => err_East_grant_E,
err_West_Req_W => err_West_Req_W,
err_West_grant_W => err_West_grant_W,
err_South_Req_S => err_South_Req_S,
err_South_grant_S => err_South_grant_S,
err_Local_Req_L => err_Local_Req_L,
err_Local_grant_L => err_Local_grant_L,
err_IDLE_Req_E => err_IDLE_Req_E,
err_IDLE_grant_E => err_IDLE_grant_E,
err_North_Req_E => err_North_Req_E,
err_North_grant_E => err_North_grant_E,
err_East_Req_W => err_East_Req_W,
err_East_grant_W => err_East_grant_W,
err_West_Req_S => err_West_Req_S,
err_West_grant_S => err_West_grant_S,
err_South_Req_L => err_South_Req_L,
err_South_grant_L => err_South_grant_L,
err_Local_Req_N => err_Local_Req_N,
err_Local_grant_N => err_Local_grant_N,
err_IDLE_Req_W => err_IDLE_Req_W,
err_IDLE_grant_W => err_IDLE_grant_W,
err_North_Req_W => err_North_Req_W,
err_North_grant_W => err_North_grant_W,
err_East_Req_S => err_East_Req_S,
err_East_grant_S => err_East_grant_S,
err_West_Req_L => err_West_Req_L,
err_West_grant_L => err_West_grant_L,
err_South_Req_N => err_South_Req_N,
err_South_grant_N => err_South_grant_N,
err_Local_Req_E => err_Local_Req_E,
err_Local_grant_E => err_Local_grant_E,
err_IDLE_Req_S => err_IDLE_Req_S,
err_IDLE_grant_S => err_IDLE_grant_S,
err_North_Req_S => err_North_Req_S,
err_North_grant_S => err_North_grant_S,
err_East_Req_L => err_East_Req_L,
err_East_grant_L => err_East_grant_L,
err_West_Req_N => err_West_Req_N,
err_West_grant_N => err_West_grant_N,
err_South_Req_E => err_South_Req_E,
err_South_grant_E => err_South_grant_E,
err_Local_Req_W => err_Local_Req_W,
err_Local_grant_W => err_Local_grant_W,
err_IDLE_Req_L => err_IDLE_Req_L,
err_IDLE_grant_L => err_IDLE_grant_L,
err_North_Req_L => err_North_Req_L,
err_North_grant_L => err_North_grant_L,
err_East_Req_N => err_East_Req_N,
err_East_grant_N => err_East_grant_N,
err_West_Req_E => err_West_Req_E,
err_West_grant_E => err_West_grant_E,
err_South_Req_W => err_South_Req_W,
err_South_grant_W => err_South_grant_W,
err_Local_Req_S => err_Local_Req_S,
err_Local_grant_S => err_Local_grant_S,
err_state_in_onehot => err_state_in_onehot,
err_no_request_grants => err_no_request_grants,
err_request_no_grants => err_request_no_grants,
err_no_Req_N_grant_N => err_no_Req_N_grant_N,
err_no_Req_E_grant_E => err_no_Req_E_grant_E,
err_no_Req_W_grant_W => err_no_Req_W_grant_W,
err_no_Req_S_grant_S => err_no_Req_S_grant_S,
err_no_Req_L_grant_L => err_no_Req_L_grant_L
);
end behavior; |
--Copyright 2014 by Emmanuel D. Bello <emabello42@gmail.com>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:37:23 11/26/2013
-- Design Name:
-- Module Name: /media/DATA42/Projects/ComputerVision/RetinaDescriptors/tb_AddressGenerator.vhd
-- Project Name: RetinaDescriptors
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: AddressGenerator
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.RetinaParameters.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_AddressGenerator IS
END tb_AddressGenerator;
ARCHITECTURE behavior OF tb_AddressGenerator IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT AddressGenerator
PORT(
clk : IN std_logic;
en : IN std_logic;
rst : IN std_logic;
coord_x : IN std_logic_vector(KPT_COORD_BW-1 downto 0);
coord_y : IN std_logic_vector(KPT_COORD_BW-1 downto 0);
image_base_addr : IN std_logic_vector(31 downto 0);
mem_addr : OUT std_logic_vector(31 downto 0);
out_en : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal en : std_logic := '0';
signal rst : std_logic := '0';
signal coord_x : std_logic_vector(KPT_COORD_BW-1 downto 0) := (others => '0');
signal coord_y : std_logic_vector(KPT_COORD_BW-1 downto 0) := (others => '0');
signal image_base_addr : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal mem_addr : std_logic_vector(31 downto 0);
signal out_en : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: AddressGenerator PORT MAP (
clk => clk,
en => en,
rst => rst,
coord_x => coord_x,
coord_y => coord_y,
image_base_addr => image_base_addr,
mem_addr => mem_addr,
out_en => out_en
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
rst <= '1';
wait for 100 ns;
rst <= '0';
wait for clk_period*10;
coord_x <= "0001000000";
coord_y <= "0001000001";
image_base_addr <= "00000000000000000000000000000000";
en <= '1';
-- insert stimulus here
wait;
end process;
END;
|
--Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct 4 19:58:22 MDT 2017
--Date : Fri Nov 17 16:04:47 2017
--Host : egk-pc running 64-bit major release (build 9200)
--Command : generate_target DemoInterconnect.bd
--Design : DemoInterconnect
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_4EB6IN is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_4EB6IN;
architecture STRUCTURE of m00_couplers_imp_4EB6IN is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m00_couplers_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m00_couplers_to_m00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m00_couplers_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m00_couplers_to_m00_couplers_AWVALID;
M_AXI_bready <= m00_couplers_to_m00_couplers_BREADY;
M_AXI_rready <= m00_couplers_to_m00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m00_couplers_to_m00_couplers_WVALID;
S_AXI_arready <= m00_couplers_to_m00_couplers_ARREADY;
S_AXI_awready <= m00_couplers_to_m00_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_m00_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_m00_couplers_RVALID;
S_AXI_wready <= m00_couplers_to_m00_couplers_WREADY;
m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_m00_couplers_ARREADY <= M_AXI_arready;
m00_couplers_to_m00_couplers_ARVALID <= S_AXI_arvalid;
m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_m00_couplers_AWREADY <= M_AXI_awready;
m00_couplers_to_m00_couplers_AWVALID <= S_AXI_awvalid;
m00_couplers_to_m00_couplers_BREADY <= S_AXI_bready;
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID <= M_AXI_bvalid;
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY <= S_AXI_rready;
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID <= M_AXI_rvalid;
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_1SL2GIW is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m01_couplers_imp_1SL2GIW;
architecture STRUCTURE of m01_couplers_imp_1SL2GIW is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m01_couplers_to_m01_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m01_couplers_to_m01_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m01_couplers_to_m01_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m01_couplers_to_m01_couplers_AWVALID;
M_AXI_bready <= m01_couplers_to_m01_couplers_BREADY;
M_AXI_rready <= m01_couplers_to_m01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m01_couplers_to_m01_couplers_WVALID;
S_AXI_arready <= m01_couplers_to_m01_couplers_ARREADY;
S_AXI_awready <= m01_couplers_to_m01_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m01_couplers_to_m01_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m01_couplers_to_m01_couplers_RVALID;
S_AXI_wready <= m01_couplers_to_m01_couplers_WREADY;
m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m01_couplers_to_m01_couplers_ARREADY <= M_AXI_arready;
m01_couplers_to_m01_couplers_ARVALID <= S_AXI_arvalid;
m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m01_couplers_to_m01_couplers_AWREADY <= M_AXI_awready;
m01_couplers_to_m01_couplers_AWVALID <= S_AXI_awvalid;
m01_couplers_to_m01_couplers_BREADY <= S_AXI_bready;
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID <= M_AXI_bvalid;
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY <= S_AXI_rready;
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID <= M_AXI_rvalid;
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY <= M_AXI_wready;
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_7DG2C0 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m02_couplers_imp_7DG2C0;
architecture STRUCTURE of m02_couplers_imp_7DG2C0 is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m02_couplers_to_m02_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m02_couplers_to_m02_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m02_couplers_to_m02_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m02_couplers_to_m02_couplers_AWVALID;
M_AXI_bready <= m02_couplers_to_m02_couplers_BREADY;
M_AXI_rready <= m02_couplers_to_m02_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m02_couplers_to_m02_couplers_WVALID;
S_AXI_arready <= m02_couplers_to_m02_couplers_ARREADY;
S_AXI_awready <= m02_couplers_to_m02_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m02_couplers_to_m02_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m02_couplers_to_m02_couplers_RVALID;
S_AXI_wready <= m02_couplers_to_m02_couplers_WREADY;
m02_couplers_to_m02_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m02_couplers_to_m02_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m02_couplers_to_m02_couplers_ARREADY <= M_AXI_arready;
m02_couplers_to_m02_couplers_ARVALID <= S_AXI_arvalid;
m02_couplers_to_m02_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m02_couplers_to_m02_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m02_couplers_to_m02_couplers_AWREADY <= M_AXI_awready;
m02_couplers_to_m02_couplers_AWVALID <= S_AXI_awvalid;
m02_couplers_to_m02_couplers_BREADY <= S_AXI_bready;
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID <= M_AXI_bvalid;
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY <= S_AXI_rready;
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID <= M_AXI_rvalid;
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY <= M_AXI_wready;
m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m02_couplers_to_m02_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m03_couplers_imp_1YCPS1Z is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m03_couplers_imp_1YCPS1Z;
architecture STRUCTURE of m03_couplers_imp_1YCPS1Z is
signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m03_couplers_to_m03_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m03_couplers_to_m03_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m03_couplers_to_m03_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m03_couplers_to_m03_couplers_AWVALID;
M_AXI_bready <= m03_couplers_to_m03_couplers_BREADY;
M_AXI_rready <= m03_couplers_to_m03_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m03_couplers_to_m03_couplers_WVALID;
S_AXI_arready <= m03_couplers_to_m03_couplers_ARREADY;
S_AXI_awready <= m03_couplers_to_m03_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m03_couplers_to_m03_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m03_couplers_to_m03_couplers_RVALID;
S_AXI_wready <= m03_couplers_to_m03_couplers_WREADY;
m03_couplers_to_m03_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m03_couplers_to_m03_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m03_couplers_to_m03_couplers_ARREADY <= M_AXI_arready;
m03_couplers_to_m03_couplers_ARVALID <= S_AXI_arvalid;
m03_couplers_to_m03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m03_couplers_to_m03_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m03_couplers_to_m03_couplers_AWREADY <= M_AXI_awready;
m03_couplers_to_m03_couplers_AWVALID <= S_AXI_awvalid;
m03_couplers_to_m03_couplers_BREADY <= S_AXI_bready;
m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m03_couplers_to_m03_couplers_BVALID <= M_AXI_bvalid;
m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m03_couplers_to_m03_couplers_RREADY <= S_AXI_rready;
m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m03_couplers_to_m03_couplers_RVALID <= M_AXI_rvalid;
m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m03_couplers_to_m03_couplers_WREADY <= M_AXI_wready;
m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m03_couplers_to_m03_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m04_couplers_imp_ACM7VL is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m04_couplers_imp_ACM7VL;
architecture STRUCTURE of m04_couplers_imp_ACM7VL is
signal m04_couplers_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_ARREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_ARVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_AWREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_BVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_RREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_RVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_WREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_m04_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m04_couplers_to_m04_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m04_couplers_to_m04_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m04_couplers_to_m04_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m04_couplers_to_m04_couplers_AWVALID;
M_AXI_bready <= m04_couplers_to_m04_couplers_BREADY;
M_AXI_rready <= m04_couplers_to_m04_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m04_couplers_to_m04_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m04_couplers_to_m04_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m04_couplers_to_m04_couplers_WVALID;
S_AXI_arready <= m04_couplers_to_m04_couplers_ARREADY;
S_AXI_awready <= m04_couplers_to_m04_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m04_couplers_to_m04_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m04_couplers_to_m04_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m04_couplers_to_m04_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m04_couplers_to_m04_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m04_couplers_to_m04_couplers_RVALID;
S_AXI_wready <= m04_couplers_to_m04_couplers_WREADY;
m04_couplers_to_m04_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m04_couplers_to_m04_couplers_ARREADY <= M_AXI_arready;
m04_couplers_to_m04_couplers_ARVALID <= S_AXI_arvalid;
m04_couplers_to_m04_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m04_couplers_to_m04_couplers_AWREADY <= M_AXI_awready;
m04_couplers_to_m04_couplers_AWVALID <= S_AXI_awvalid;
m04_couplers_to_m04_couplers_BREADY <= S_AXI_bready;
m04_couplers_to_m04_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m04_couplers_to_m04_couplers_BVALID <= M_AXI_bvalid;
m04_couplers_to_m04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m04_couplers_to_m04_couplers_RREADY <= S_AXI_rready;
m04_couplers_to_m04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m04_couplers_to_m04_couplers_RVALID <= M_AXI_rvalid;
m04_couplers_to_m04_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m04_couplers_to_m04_couplers_WREADY <= M_AXI_wready;
m04_couplers_to_m04_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m04_couplers_to_m04_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m05_couplers_imp_1HWY5FA is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m05_couplers_imp_1HWY5FA;
architecture STRUCTURE of m05_couplers_imp_1HWY5FA is
signal m05_couplers_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_ARREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_ARVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_AWREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_AWVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_BREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_BVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_RREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_RVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_WREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_m05_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m05_couplers_to_m05_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m05_couplers_to_m05_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m05_couplers_to_m05_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m05_couplers_to_m05_couplers_AWVALID;
M_AXI_bready <= m05_couplers_to_m05_couplers_BREADY;
M_AXI_rready <= m05_couplers_to_m05_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m05_couplers_to_m05_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m05_couplers_to_m05_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m05_couplers_to_m05_couplers_WVALID;
S_AXI_arready <= m05_couplers_to_m05_couplers_ARREADY;
S_AXI_awready <= m05_couplers_to_m05_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m05_couplers_to_m05_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m05_couplers_to_m05_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m05_couplers_to_m05_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m05_couplers_to_m05_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m05_couplers_to_m05_couplers_RVALID;
S_AXI_wready <= m05_couplers_to_m05_couplers_WREADY;
m05_couplers_to_m05_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m05_couplers_to_m05_couplers_ARREADY <= M_AXI_arready;
m05_couplers_to_m05_couplers_ARVALID <= S_AXI_arvalid;
m05_couplers_to_m05_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m05_couplers_to_m05_couplers_AWREADY <= M_AXI_awready;
m05_couplers_to_m05_couplers_AWVALID <= S_AXI_awvalid;
m05_couplers_to_m05_couplers_BREADY <= S_AXI_bready;
m05_couplers_to_m05_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m05_couplers_to_m05_couplers_BVALID <= M_AXI_bvalid;
m05_couplers_to_m05_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m05_couplers_to_m05_couplers_RREADY <= S_AXI_rready;
m05_couplers_to_m05_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m05_couplers_to_m05_couplers_RVALID <= M_AXI_rvalid;
m05_couplers_to_m05_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m05_couplers_to_m05_couplers_WREADY <= M_AXI_wready;
m05_couplers_to_m05_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m05_couplers_to_m05_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m06_couplers_imp_DBR4EM is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m06_couplers_imp_DBR4EM;
architecture STRUCTURE of m06_couplers_imp_DBR4EM is
signal m06_couplers_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_ARREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_ARVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_AWREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_AWVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_BREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_BVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_RREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_RVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_WREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_m06_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m06_couplers_to_m06_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m06_couplers_to_m06_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m06_couplers_to_m06_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m06_couplers_to_m06_couplers_AWVALID;
M_AXI_bready <= m06_couplers_to_m06_couplers_BREADY;
M_AXI_rready <= m06_couplers_to_m06_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m06_couplers_to_m06_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m06_couplers_to_m06_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m06_couplers_to_m06_couplers_WVALID;
S_AXI_arready <= m06_couplers_to_m06_couplers_ARREADY;
S_AXI_awready <= m06_couplers_to_m06_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m06_couplers_to_m06_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m06_couplers_to_m06_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m06_couplers_to_m06_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m06_couplers_to_m06_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m06_couplers_to_m06_couplers_RVALID;
S_AXI_wready <= m06_couplers_to_m06_couplers_WREADY;
m06_couplers_to_m06_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m06_couplers_to_m06_couplers_ARREADY <= M_AXI_arready;
m06_couplers_to_m06_couplers_ARVALID <= S_AXI_arvalid;
m06_couplers_to_m06_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m06_couplers_to_m06_couplers_AWREADY <= M_AXI_awready;
m06_couplers_to_m06_couplers_AWVALID <= S_AXI_awvalid;
m06_couplers_to_m06_couplers_BREADY <= S_AXI_bready;
m06_couplers_to_m06_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m06_couplers_to_m06_couplers_BVALID <= M_AXI_bvalid;
m06_couplers_to_m06_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m06_couplers_to_m06_couplers_RREADY <= S_AXI_rready;
m06_couplers_to_m06_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m06_couplers_to_m06_couplers_RVALID <= M_AXI_rvalid;
m06_couplers_to_m06_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m06_couplers_to_m06_couplers_WREADY <= M_AXI_wready;
m06_couplers_to_m06_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m06_couplers_to_m06_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_7XIH8P is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_7XIH8P;
architecture STRUCTURE of s00_couplers_imp_7XIH8P is
signal s00_couplers_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARREADY : STD_LOGIC;
signal s00_couplers_to_s00_couplers_ARVALID : STD_LOGIC;
signal s00_couplers_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_AWREADY : STD_LOGIC;
signal s00_couplers_to_s00_couplers_AWVALID : STD_LOGIC;
signal s00_couplers_to_s00_couplers_BREADY : STD_LOGIC;
signal s00_couplers_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_BVALID : STD_LOGIC;
signal s00_couplers_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_RREADY : STD_LOGIC;
signal s00_couplers_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_RVALID : STD_LOGIC;
signal s00_couplers_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_WREADY : STD_LOGIC;
signal s00_couplers_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= s00_couplers_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= s00_couplers_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= s00_couplers_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= s00_couplers_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= s00_couplers_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= s00_couplers_to_s00_couplers_AWVALID;
M_AXI_bready <= s00_couplers_to_s00_couplers_BREADY;
M_AXI_rready <= s00_couplers_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= s00_couplers_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= s00_couplers_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= s00_couplers_to_s00_couplers_WVALID;
S_AXI_arready <= s00_couplers_to_s00_couplers_ARREADY;
S_AXI_awready <= s00_couplers_to_s00_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= s00_couplers_to_s00_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_s00_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_s00_couplers_RVALID;
S_AXI_wready <= s00_couplers_to_s00_couplers_WREADY;
s00_couplers_to_s00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_s00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_s00_couplers_ARREADY <= M_AXI_arready;
s00_couplers_to_s00_couplers_ARVALID <= S_AXI_arvalid;
s00_couplers_to_s00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_s00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_s00_couplers_AWREADY <= M_AXI_awready;
s00_couplers_to_s00_couplers_AWVALID <= S_AXI_awvalid;
s00_couplers_to_s00_couplers_BREADY <= S_AXI_bready;
s00_couplers_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s00_couplers_to_s00_couplers_BVALID <= M_AXI_bvalid;
s00_couplers_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s00_couplers_to_s00_couplers_RREADY <= S_AXI_rready;
s00_couplers_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s00_couplers_to_s00_couplers_RVALID <= M_AXI_rvalid;
s00_couplers_to_s00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_s00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_s00_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s01_couplers_imp_1XSI6OU is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s01_couplers_imp_1XSI6OU;
architecture STRUCTURE of s01_couplers_imp_1XSI6OU is
signal s01_couplers_to_s01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_ARREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_ARVALID : STD_LOGIC;
signal s01_couplers_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_AWREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_AWVALID : STD_LOGIC;
signal s01_couplers_to_s01_couplers_BREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_BVALID : STD_LOGIC;
signal s01_couplers_to_s01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_RREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_RVALID : STD_LOGIC;
signal s01_couplers_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_WREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= s01_couplers_to_s01_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= s01_couplers_to_s01_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= s01_couplers_to_s01_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= s01_couplers_to_s01_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= s01_couplers_to_s01_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= s01_couplers_to_s01_couplers_AWVALID;
M_AXI_bready <= s01_couplers_to_s01_couplers_BREADY;
M_AXI_rready <= s01_couplers_to_s01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= s01_couplers_to_s01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= s01_couplers_to_s01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= s01_couplers_to_s01_couplers_WVALID;
S_AXI_arready <= s01_couplers_to_s01_couplers_ARREADY;
S_AXI_awready <= s01_couplers_to_s01_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= s01_couplers_to_s01_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= s01_couplers_to_s01_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= s01_couplers_to_s01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= s01_couplers_to_s01_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= s01_couplers_to_s01_couplers_RVALID;
S_AXI_wready <= s01_couplers_to_s01_couplers_WREADY;
s01_couplers_to_s01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s01_couplers_to_s01_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s01_couplers_to_s01_couplers_ARREADY <= M_AXI_arready;
s01_couplers_to_s01_couplers_ARVALID <= S_AXI_arvalid;
s01_couplers_to_s01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s01_couplers_to_s01_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s01_couplers_to_s01_couplers_AWREADY <= M_AXI_awready;
s01_couplers_to_s01_couplers_AWVALID <= S_AXI_awvalid;
s01_couplers_to_s01_couplers_BREADY <= S_AXI_bready;
s01_couplers_to_s01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s01_couplers_to_s01_couplers_BVALID <= M_AXI_bvalid;
s01_couplers_to_s01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s01_couplers_to_s01_couplers_RREADY <= S_AXI_rready;
s01_couplers_to_s01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s01_couplers_to_s01_couplers_RVALID <= M_AXI_rvalid;
s01_couplers_to_s01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s01_couplers_to_s01_couplers_WREADY <= M_AXI_wready;
s01_couplers_to_s01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s01_couplers_to_s01_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s02_couplers_imp_2QLUHY is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC;
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC;
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s02_couplers_imp_2QLUHY;
architecture STRUCTURE of s02_couplers_imp_2QLUHY is
component DemoInterconnect_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component DemoInterconnect_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_pc_to_s02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s02_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s02_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s02_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s02_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s02_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s02_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s02_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s02_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s02_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s02_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s02_couplers_WVALID : STD_LOGIC;
signal s02_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s02_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s02_couplers_to_auto_pc_ARLOCK : STD_LOGIC;
signal s02_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s02_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s02_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s02_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s02_couplers_to_auto_pc_AWLOCK : STD_LOGIC;
signal s02_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s02_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s02_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s02_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s02_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s02_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s02_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s02_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s02_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s02_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s02_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s02_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s02_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s02_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s02_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s02_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s02_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s02_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s02_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s02_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s02_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= s02_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s02_couplers_to_auto_pc_AWREADY;
S_AXI_bid(0) <= s02_couplers_to_auto_pc_BID(0);
S_AXI_bresp(1 downto 0) <= s02_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s02_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s02_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(0) <= s02_couplers_to_auto_pc_RID(0);
S_AXI_rlast <= s02_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s02_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s02_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s02_couplers_to_auto_pc_WREADY;
auto_pc_to_s02_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s02_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s02_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s02_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s02_couplers_WREADY <= M_AXI_wready;
s02_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s02_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s02_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s02_couplers_to_auto_pc_ARID(0) <= S_AXI_arid(0);
s02_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s02_couplers_to_auto_pc_ARLOCK <= S_AXI_arlock;
s02_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s02_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s02_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s02_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s02_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s02_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s02_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s02_couplers_to_auto_pc_AWID(0) <= S_AXI_awid(0);
s02_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s02_couplers_to_auto_pc_AWLOCK <= S_AXI_awlock;
s02_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s02_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s02_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s02_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s02_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s02_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s02_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s02_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s02_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s02_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component DemoInterconnect_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1,
m_axi_araddr(31 downto 0) => auto_pc_to_s02_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s02_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s02_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s02_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s02_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s02_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s02_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s02_couplers_AWVALID,
m_axi_bready => auto_pc_to_s02_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s02_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s02_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s02_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s02_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s02_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s02_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s02_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s02_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s02_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s02_couplers_WVALID,
s_axi_araddr(31 downto 0) => s02_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s02_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s02_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(0) => s02_couplers_to_auto_pc_ARID(0),
s_axi_arlen(7 downto 0) => s02_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => s02_couplers_to_auto_pc_ARLOCK,
s_axi_arprot(2 downto 0) => s02_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s02_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s02_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s02_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s02_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s02_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s02_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s02_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(0) => s02_couplers_to_auto_pc_AWID(0),
s_axi_awlen(7 downto 0) => s02_couplers_to_auto_pc_AWLEN(7 downto 0),
s_axi_awlock(0) => s02_couplers_to_auto_pc_AWLOCK,
s_axi_awprot(2 downto 0) => s02_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s02_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s02_couplers_to_auto_pc_AWREADY,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s02_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s02_couplers_to_auto_pc_AWVALID,
s_axi_bid(0) => s02_couplers_to_auto_pc_BID(0),
s_axi_bready => s02_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s02_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s02_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s02_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(0) => s02_couplers_to_auto_pc_RID(0),
s_axi_rlast => s02_couplers_to_auto_pc_RLAST,
s_axi_rready => s02_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s02_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s02_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s02_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wlast => s02_couplers_to_auto_pc_WLAST,
s_axi_wready => s02_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s02_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s02_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity DemoInterconnect_axi_interconnect_0_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC;
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_arready : in STD_LOGIC;
M01_AXI_arvalid : out STD_LOGIC;
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_awready : in STD_LOGIC;
M01_AXI_awvalid : out STD_LOGIC;
M01_AXI_bready : out STD_LOGIC;
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC;
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC;
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC;
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC;
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC;
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC;
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M02_AXI_arready : in STD_LOGIC;
M02_AXI_arvalid : out STD_LOGIC;
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M02_AXI_awready : in STD_LOGIC;
M02_AXI_awvalid : out STD_LOGIC;
M02_AXI_bready : out STD_LOGIC;
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC;
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC;
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC;
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC;
M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_wvalid : out STD_LOGIC;
M03_ACLK : in STD_LOGIC;
M03_ARESETN : in STD_LOGIC;
M03_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M03_AXI_arready : in STD_LOGIC;
M03_AXI_arvalid : out STD_LOGIC;
M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M03_AXI_awready : in STD_LOGIC;
M03_AXI_awvalid : out STD_LOGIC;
M03_AXI_bready : out STD_LOGIC;
M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_bvalid : in STD_LOGIC;
M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_rready : out STD_LOGIC;
M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_rvalid : in STD_LOGIC;
M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_wready : in STD_LOGIC;
M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M03_AXI_wvalid : out STD_LOGIC;
M04_ACLK : in STD_LOGIC;
M04_ARESETN : in STD_LOGIC;
M04_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_arready : in STD_LOGIC;
M04_AXI_arvalid : out STD_LOGIC;
M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_awready : in STD_LOGIC;
M04_AXI_awvalid : out STD_LOGIC;
M04_AXI_bready : out STD_LOGIC;
M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_bvalid : in STD_LOGIC;
M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_rready : out STD_LOGIC;
M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_rvalid : in STD_LOGIC;
M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_wready : in STD_LOGIC;
M04_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M04_AXI_wvalid : out STD_LOGIC;
M05_ACLK : in STD_LOGIC;
M05_ARESETN : in STD_LOGIC;
M05_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_arready : in STD_LOGIC;
M05_AXI_arvalid : out STD_LOGIC;
M05_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_awready : in STD_LOGIC;
M05_AXI_awvalid : out STD_LOGIC;
M05_AXI_bready : out STD_LOGIC;
M05_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_bvalid : in STD_LOGIC;
M05_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_rready : out STD_LOGIC;
M05_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_rvalid : in STD_LOGIC;
M05_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_wready : in STD_LOGIC;
M05_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M05_AXI_wvalid : out STD_LOGIC;
M06_ACLK : in STD_LOGIC;
M06_ARESETN : in STD_LOGIC;
M06_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_arready : in STD_LOGIC;
M06_AXI_arvalid : out STD_LOGIC;
M06_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_awready : in STD_LOGIC;
M06_AXI_awvalid : out STD_LOGIC;
M06_AXI_bready : out STD_LOGIC;
M06_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_bvalid : in STD_LOGIC;
M06_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_rready : out STD_LOGIC;
M06_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_rvalid : in STD_LOGIC;
M06_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_wready : in STD_LOGIC;
M06_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M06_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC;
S01_ACLK : in STD_LOGIC;
S01_ARESETN : in STD_LOGIC;
S01_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_arready : out STD_LOGIC;
S01_AXI_arvalid : in STD_LOGIC;
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awready : out STD_LOGIC;
S01_AXI_awvalid : in STD_LOGIC;
S01_AXI_bready : in STD_LOGIC;
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_bvalid : out STD_LOGIC;
S01_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_rready : in STD_LOGIC;
S01_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_rvalid : out STD_LOGIC;
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_wready : out STD_LOGIC;
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_wvalid : in STD_LOGIC;
S02_ACLK : in STD_LOGIC;
S02_ARESETN : in STD_LOGIC;
S02_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_arlock : in STD_LOGIC;
S02_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arready : out STD_LOGIC;
S02_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arvalid : in STD_LOGIC;
S02_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_awlock : in STD_LOGIC;
S02_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awready : out STD_LOGIC;
S02_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_awvalid : in STD_LOGIC;
S02_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_bready : in STD_LOGIC;
S02_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_bvalid : out STD_LOGIC;
S02_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_rlast : out STD_LOGIC;
S02_AXI_rready : in STD_LOGIC;
S02_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_rvalid : out STD_LOGIC;
S02_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_wlast : in STD_LOGIC;
S02_AXI_wready : out STD_LOGIC;
S02_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_wvalid : in STD_LOGIC
);
end DemoInterconnect_axi_interconnect_0_0;
architecture STRUCTURE of DemoInterconnect_axi_interconnect_0_0 is
component DemoInterconnect_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 20 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 20 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 6 downto 0 )
);
end component DemoInterconnect_xbar_0;
signal interconnect_ACLK_net : STD_LOGIC;
signal interconnect_ARESETN_net : STD_LOGIC;
signal interconnect_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s00_couplers_ARREADY : STD_LOGIC;
signal interconnect_to_s00_couplers_ARVALID : STD_LOGIC;
signal interconnect_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s00_couplers_AWREADY : STD_LOGIC;
signal interconnect_to_s00_couplers_AWVALID : STD_LOGIC;
signal interconnect_to_s00_couplers_BREADY : STD_LOGIC;
signal interconnect_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s00_couplers_BVALID : STD_LOGIC;
signal interconnect_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s00_couplers_RREADY : STD_LOGIC;
signal interconnect_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s00_couplers_RVALID : STD_LOGIC;
signal interconnect_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s00_couplers_WREADY : STD_LOGIC;
signal interconnect_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s00_couplers_WVALID : STD_LOGIC;
signal interconnect_to_s01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s01_couplers_ARREADY : STD_LOGIC;
signal interconnect_to_s01_couplers_ARVALID : STD_LOGIC;
signal interconnect_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s01_couplers_AWREADY : STD_LOGIC;
signal interconnect_to_s01_couplers_AWVALID : STD_LOGIC;
signal interconnect_to_s01_couplers_BREADY : STD_LOGIC;
signal interconnect_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s01_couplers_BVALID : STD_LOGIC;
signal interconnect_to_s01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s01_couplers_RREADY : STD_LOGIC;
signal interconnect_to_s01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s01_couplers_RVALID : STD_LOGIC;
signal interconnect_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s01_couplers_WREADY : STD_LOGIC;
signal interconnect_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s01_couplers_WVALID : STD_LOGIC;
signal interconnect_to_s02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s02_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s02_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s02_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal interconnect_to_s02_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal interconnect_to_s02_couplers_ARLOCK : STD_LOGIC;
signal interconnect_to_s02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s02_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s02_couplers_ARREADY : STD_LOGIC;
signal interconnect_to_s02_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s02_couplers_ARVALID : STD_LOGIC;
signal interconnect_to_s02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s02_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s02_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s02_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal interconnect_to_s02_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal interconnect_to_s02_couplers_AWLOCK : STD_LOGIC;
signal interconnect_to_s02_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s02_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s02_couplers_AWREADY : STD_LOGIC;
signal interconnect_to_s02_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s02_couplers_AWVALID : STD_LOGIC;
signal interconnect_to_s02_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal interconnect_to_s02_couplers_BREADY : STD_LOGIC;
signal interconnect_to_s02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s02_couplers_BVALID : STD_LOGIC;
signal interconnect_to_s02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s02_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal interconnect_to_s02_couplers_RLAST : STD_LOGIC;
signal interconnect_to_s02_couplers_RREADY : STD_LOGIC;
signal interconnect_to_s02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s02_couplers_RVALID : STD_LOGIC;
signal interconnect_to_s02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s02_couplers_WLAST : STD_LOGIC;
signal interconnect_to_s02_couplers_WREADY : STD_LOGIC;
signal interconnect_to_s02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s02_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_interconnect_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m00_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m00_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_interconnect_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m00_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m00_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m00_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m00_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m00_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m00_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m00_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m01_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_interconnect_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m01_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m01_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_interconnect_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m01_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m01_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m01_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m01_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m01_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m01_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m01_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m02_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_interconnect_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m02_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m02_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_interconnect_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m02_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m02_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m02_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m02_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m02_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m02_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m02_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m03_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_interconnect_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m03_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m03_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_interconnect_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m03_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m03_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m03_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m03_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m03_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m03_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m03_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m04_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m04_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m04_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m04_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m04_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m04_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m04_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m04_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m04_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m04_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m05_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m05_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m05_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m05_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m05_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m05_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m05_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m05_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m05_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m05_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m06_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m06_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m06_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m06_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m06_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m06_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m06_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m06_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m06_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m06_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_interconnect_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal s01_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s01_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s01_couplers_to_xbar_BREADY : STD_LOGIC;
signal s01_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal s01_couplers_to_xbar_RREADY : STD_LOGIC;
signal s01_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_WVALID : STD_LOGIC;
signal s02_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s02_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s02_couplers_to_xbar_BREADY : STD_LOGIC;
signal s02_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 5 downto 4 );
signal s02_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal s02_couplers_to_xbar_RREADY : STD_LOGIC;
signal s02_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 5 downto 4 );
signal s02_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC;
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC;
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC;
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARPROT : STD_LOGIC_VECTOR ( 8 downto 6 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWPROT : STD_LOGIC_VECTOR ( 8 downto 6 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC;
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC;
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC;
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_ARPROT : STD_LOGIC_VECTOR ( 11 downto 9 );
signal xbar_to_m03_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_AWPROT : STD_LOGIC_VECTOR ( 11 downto 9 );
signal xbar_to_m03_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_BVALID : STD_LOGIC;
signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_RVALID : STD_LOGIC;
signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_WREADY : STD_LOGIC;
signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 );
signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_BVALID : STD_LOGIC;
signal xbar_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_RVALID : STD_LOGIC;
signal xbar_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_WREADY : STD_LOGIC;
signal xbar_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 19 downto 16 );
signal xbar_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m05_couplers_ARVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m05_couplers_AWVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_BVALID : STD_LOGIC;
signal xbar_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m05_couplers_RREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_RVALID : STD_LOGIC;
signal xbar_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_WREADY : STD_LOGIC;
signal xbar_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 23 downto 20 );
signal xbar_to_m05_couplers_WVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m06_couplers_ARVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m06_couplers_AWVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_BVALID : STD_LOGIC;
signal xbar_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m06_couplers_RREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_RVALID : STD_LOGIC;
signal xbar_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_WREADY : STD_LOGIC;
signal xbar_to_m06_couplers_WSTRB : STD_LOGIC_VECTOR ( 27 downto 24 );
signal xbar_to_m06_couplers_WVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 20 downto 12 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 20 downto 12 );
begin
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_interconnect_ARADDR(31 downto 0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_interconnect_ARPROT(2 downto 0);
M00_AXI_arvalid <= m00_couplers_to_interconnect_ARVALID;
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_interconnect_AWADDR(31 downto 0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_interconnect_AWPROT(2 downto 0);
M00_AXI_awvalid <= m00_couplers_to_interconnect_AWVALID;
M00_AXI_bready <= m00_couplers_to_interconnect_BREADY;
M00_AXI_rready <= m00_couplers_to_interconnect_RREADY;
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_interconnect_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_interconnect_WSTRB(3 downto 0);
M00_AXI_wvalid <= m00_couplers_to_interconnect_WVALID;
M01_AXI_araddr(31 downto 0) <= m01_couplers_to_interconnect_ARADDR(31 downto 0);
M01_AXI_arprot(2 downto 0) <= m01_couplers_to_interconnect_ARPROT(2 downto 0);
M01_AXI_arvalid <= m01_couplers_to_interconnect_ARVALID;
M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_interconnect_AWADDR(31 downto 0);
M01_AXI_awprot(2 downto 0) <= m01_couplers_to_interconnect_AWPROT(2 downto 0);
M01_AXI_awvalid <= m01_couplers_to_interconnect_AWVALID;
M01_AXI_bready <= m01_couplers_to_interconnect_BREADY;
M01_AXI_rready <= m01_couplers_to_interconnect_RREADY;
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_interconnect_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_interconnect_WSTRB(3 downto 0);
M01_AXI_wvalid <= m01_couplers_to_interconnect_WVALID;
M02_AXI_araddr(31 downto 0) <= m02_couplers_to_interconnect_ARADDR(31 downto 0);
M02_AXI_arprot(2 downto 0) <= m02_couplers_to_interconnect_ARPROT(2 downto 0);
M02_AXI_arvalid <= m02_couplers_to_interconnect_ARVALID;
M02_AXI_awaddr(31 downto 0) <= m02_couplers_to_interconnect_AWADDR(31 downto 0);
M02_AXI_awprot(2 downto 0) <= m02_couplers_to_interconnect_AWPROT(2 downto 0);
M02_AXI_awvalid <= m02_couplers_to_interconnect_AWVALID;
M02_AXI_bready <= m02_couplers_to_interconnect_BREADY;
M02_AXI_rready <= m02_couplers_to_interconnect_RREADY;
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_interconnect_WDATA(31 downto 0);
M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_interconnect_WSTRB(3 downto 0);
M02_AXI_wvalid <= m02_couplers_to_interconnect_WVALID;
M03_AXI_araddr(31 downto 0) <= m03_couplers_to_interconnect_ARADDR(31 downto 0);
M03_AXI_arprot(2 downto 0) <= m03_couplers_to_interconnect_ARPROT(2 downto 0);
M03_AXI_arvalid <= m03_couplers_to_interconnect_ARVALID;
M03_AXI_awaddr(31 downto 0) <= m03_couplers_to_interconnect_AWADDR(31 downto 0);
M03_AXI_awprot(2 downto 0) <= m03_couplers_to_interconnect_AWPROT(2 downto 0);
M03_AXI_awvalid <= m03_couplers_to_interconnect_AWVALID;
M03_AXI_bready <= m03_couplers_to_interconnect_BREADY;
M03_AXI_rready <= m03_couplers_to_interconnect_RREADY;
M03_AXI_wdata(31 downto 0) <= m03_couplers_to_interconnect_WDATA(31 downto 0);
M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_interconnect_WSTRB(3 downto 0);
M03_AXI_wvalid <= m03_couplers_to_interconnect_WVALID;
M04_AXI_araddr(31 downto 0) <= m04_couplers_to_interconnect_ARADDR(31 downto 0);
M04_AXI_arvalid <= m04_couplers_to_interconnect_ARVALID;
M04_AXI_awaddr(31 downto 0) <= m04_couplers_to_interconnect_AWADDR(31 downto 0);
M04_AXI_awvalid <= m04_couplers_to_interconnect_AWVALID;
M04_AXI_bready <= m04_couplers_to_interconnect_BREADY;
M04_AXI_rready <= m04_couplers_to_interconnect_RREADY;
M04_AXI_wdata(31 downto 0) <= m04_couplers_to_interconnect_WDATA(31 downto 0);
M04_AXI_wstrb(3 downto 0) <= m04_couplers_to_interconnect_WSTRB(3 downto 0);
M04_AXI_wvalid <= m04_couplers_to_interconnect_WVALID;
M05_AXI_araddr(31 downto 0) <= m05_couplers_to_interconnect_ARADDR(31 downto 0);
M05_AXI_arvalid <= m05_couplers_to_interconnect_ARVALID;
M05_AXI_awaddr(31 downto 0) <= m05_couplers_to_interconnect_AWADDR(31 downto 0);
M05_AXI_awvalid <= m05_couplers_to_interconnect_AWVALID;
M05_AXI_bready <= m05_couplers_to_interconnect_BREADY;
M05_AXI_rready <= m05_couplers_to_interconnect_RREADY;
M05_AXI_wdata(31 downto 0) <= m05_couplers_to_interconnect_WDATA(31 downto 0);
M05_AXI_wstrb(3 downto 0) <= m05_couplers_to_interconnect_WSTRB(3 downto 0);
M05_AXI_wvalid <= m05_couplers_to_interconnect_WVALID;
M06_AXI_araddr(31 downto 0) <= m06_couplers_to_interconnect_ARADDR(31 downto 0);
M06_AXI_arvalid <= m06_couplers_to_interconnect_ARVALID;
M06_AXI_awaddr(31 downto 0) <= m06_couplers_to_interconnect_AWADDR(31 downto 0);
M06_AXI_awvalid <= m06_couplers_to_interconnect_AWVALID;
M06_AXI_bready <= m06_couplers_to_interconnect_BREADY;
M06_AXI_rready <= m06_couplers_to_interconnect_RREADY;
M06_AXI_wdata(31 downto 0) <= m06_couplers_to_interconnect_WDATA(31 downto 0);
M06_AXI_wstrb(3 downto 0) <= m06_couplers_to_interconnect_WSTRB(3 downto 0);
M06_AXI_wvalid <= m06_couplers_to_interconnect_WVALID;
S00_AXI_arready <= interconnect_to_s00_couplers_ARREADY;
S00_AXI_awready <= interconnect_to_s00_couplers_AWREADY;
S00_AXI_bresp(1 downto 0) <= interconnect_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= interconnect_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= interconnect_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rresp(1 downto 0) <= interconnect_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= interconnect_to_s00_couplers_RVALID;
S00_AXI_wready <= interconnect_to_s00_couplers_WREADY;
S01_AXI_arready <= interconnect_to_s01_couplers_ARREADY;
S01_AXI_awready <= interconnect_to_s01_couplers_AWREADY;
S01_AXI_bresp(1 downto 0) <= interconnect_to_s01_couplers_BRESP(1 downto 0);
S01_AXI_bvalid <= interconnect_to_s01_couplers_BVALID;
S01_AXI_rdata(31 downto 0) <= interconnect_to_s01_couplers_RDATA(31 downto 0);
S01_AXI_rresp(1 downto 0) <= interconnect_to_s01_couplers_RRESP(1 downto 0);
S01_AXI_rvalid <= interconnect_to_s01_couplers_RVALID;
S01_AXI_wready <= interconnect_to_s01_couplers_WREADY;
S02_AXI_arready <= interconnect_to_s02_couplers_ARREADY;
S02_AXI_awready <= interconnect_to_s02_couplers_AWREADY;
S02_AXI_bid(0) <= interconnect_to_s02_couplers_BID(0);
S02_AXI_bresp(1 downto 0) <= interconnect_to_s02_couplers_BRESP(1 downto 0);
S02_AXI_bvalid <= interconnect_to_s02_couplers_BVALID;
S02_AXI_rdata(31 downto 0) <= interconnect_to_s02_couplers_RDATA(31 downto 0);
S02_AXI_rid(0) <= interconnect_to_s02_couplers_RID(0);
S02_AXI_rlast <= interconnect_to_s02_couplers_RLAST;
S02_AXI_rresp(1 downto 0) <= interconnect_to_s02_couplers_RRESP(1 downto 0);
S02_AXI_rvalid <= interconnect_to_s02_couplers_RVALID;
S02_AXI_wready <= interconnect_to_s02_couplers_WREADY;
interconnect_ACLK_net <= ACLK;
interconnect_ARESETN_net <= ARESETN;
interconnect_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
interconnect_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
interconnect_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
interconnect_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
interconnect_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
interconnect_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
interconnect_to_s00_couplers_BREADY <= S00_AXI_bready;
interconnect_to_s00_couplers_RREADY <= S00_AXI_rready;
interconnect_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
interconnect_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
interconnect_to_s00_couplers_WVALID <= S00_AXI_wvalid;
interconnect_to_s01_couplers_ARADDR(31 downto 0) <= S01_AXI_araddr(31 downto 0);
interconnect_to_s01_couplers_ARPROT(2 downto 0) <= S01_AXI_arprot(2 downto 0);
interconnect_to_s01_couplers_ARVALID <= S01_AXI_arvalid;
interconnect_to_s01_couplers_AWADDR(31 downto 0) <= S01_AXI_awaddr(31 downto 0);
interconnect_to_s01_couplers_AWPROT(2 downto 0) <= S01_AXI_awprot(2 downto 0);
interconnect_to_s01_couplers_AWVALID <= S01_AXI_awvalid;
interconnect_to_s01_couplers_BREADY <= S01_AXI_bready;
interconnect_to_s01_couplers_RREADY <= S01_AXI_rready;
interconnect_to_s01_couplers_WDATA(31 downto 0) <= S01_AXI_wdata(31 downto 0);
interconnect_to_s01_couplers_WSTRB(3 downto 0) <= S01_AXI_wstrb(3 downto 0);
interconnect_to_s01_couplers_WVALID <= S01_AXI_wvalid;
interconnect_to_s02_couplers_ARADDR(31 downto 0) <= S02_AXI_araddr(31 downto 0);
interconnect_to_s02_couplers_ARBURST(1 downto 0) <= S02_AXI_arburst(1 downto 0);
interconnect_to_s02_couplers_ARCACHE(3 downto 0) <= S02_AXI_arcache(3 downto 0);
interconnect_to_s02_couplers_ARID(0) <= S02_AXI_arid(0);
interconnect_to_s02_couplers_ARLEN(7 downto 0) <= S02_AXI_arlen(7 downto 0);
interconnect_to_s02_couplers_ARLOCK <= S02_AXI_arlock;
interconnect_to_s02_couplers_ARPROT(2 downto 0) <= S02_AXI_arprot(2 downto 0);
interconnect_to_s02_couplers_ARQOS(3 downto 0) <= S02_AXI_arqos(3 downto 0);
interconnect_to_s02_couplers_ARSIZE(2 downto 0) <= S02_AXI_arsize(2 downto 0);
interconnect_to_s02_couplers_ARVALID <= S02_AXI_arvalid;
interconnect_to_s02_couplers_AWADDR(31 downto 0) <= S02_AXI_awaddr(31 downto 0);
interconnect_to_s02_couplers_AWBURST(1 downto 0) <= S02_AXI_awburst(1 downto 0);
interconnect_to_s02_couplers_AWCACHE(3 downto 0) <= S02_AXI_awcache(3 downto 0);
interconnect_to_s02_couplers_AWID(0) <= S02_AXI_awid(0);
interconnect_to_s02_couplers_AWLEN(7 downto 0) <= S02_AXI_awlen(7 downto 0);
interconnect_to_s02_couplers_AWLOCK <= S02_AXI_awlock;
interconnect_to_s02_couplers_AWPROT(2 downto 0) <= S02_AXI_awprot(2 downto 0);
interconnect_to_s02_couplers_AWQOS(3 downto 0) <= S02_AXI_awqos(3 downto 0);
interconnect_to_s02_couplers_AWSIZE(2 downto 0) <= S02_AXI_awsize(2 downto 0);
interconnect_to_s02_couplers_AWVALID <= S02_AXI_awvalid;
interconnect_to_s02_couplers_BREADY <= S02_AXI_bready;
interconnect_to_s02_couplers_RREADY <= S02_AXI_rready;
interconnect_to_s02_couplers_WDATA(31 downto 0) <= S02_AXI_wdata(31 downto 0);
interconnect_to_s02_couplers_WLAST <= S02_AXI_wlast;
interconnect_to_s02_couplers_WSTRB(3 downto 0) <= S02_AXI_wstrb(3 downto 0);
interconnect_to_s02_couplers_WVALID <= S02_AXI_wvalid;
m00_couplers_to_interconnect_ARREADY <= M00_AXI_arready;
m00_couplers_to_interconnect_AWREADY <= M00_AXI_awready;
m00_couplers_to_interconnect_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_interconnect_BVALID <= M00_AXI_bvalid;
m00_couplers_to_interconnect_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_interconnect_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_interconnect_RVALID <= M00_AXI_rvalid;
m00_couplers_to_interconnect_WREADY <= M00_AXI_wready;
m01_couplers_to_interconnect_ARREADY <= M01_AXI_arready;
m01_couplers_to_interconnect_AWREADY <= M01_AXI_awready;
m01_couplers_to_interconnect_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_interconnect_BVALID <= M01_AXI_bvalid;
m01_couplers_to_interconnect_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_interconnect_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_interconnect_RVALID <= M01_AXI_rvalid;
m01_couplers_to_interconnect_WREADY <= M01_AXI_wready;
m02_couplers_to_interconnect_ARREADY <= M02_AXI_arready;
m02_couplers_to_interconnect_AWREADY <= M02_AXI_awready;
m02_couplers_to_interconnect_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_interconnect_BVALID <= M02_AXI_bvalid;
m02_couplers_to_interconnect_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_interconnect_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_interconnect_RVALID <= M02_AXI_rvalid;
m02_couplers_to_interconnect_WREADY <= M02_AXI_wready;
m03_couplers_to_interconnect_ARREADY <= M03_AXI_arready;
m03_couplers_to_interconnect_AWREADY <= M03_AXI_awready;
m03_couplers_to_interconnect_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
m03_couplers_to_interconnect_BVALID <= M03_AXI_bvalid;
m03_couplers_to_interconnect_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
m03_couplers_to_interconnect_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
m03_couplers_to_interconnect_RVALID <= M03_AXI_rvalid;
m03_couplers_to_interconnect_WREADY <= M03_AXI_wready;
m04_couplers_to_interconnect_ARREADY <= M04_AXI_arready;
m04_couplers_to_interconnect_AWREADY <= M04_AXI_awready;
m04_couplers_to_interconnect_BRESP(1 downto 0) <= M04_AXI_bresp(1 downto 0);
m04_couplers_to_interconnect_BVALID <= M04_AXI_bvalid;
m04_couplers_to_interconnect_RDATA(31 downto 0) <= M04_AXI_rdata(31 downto 0);
m04_couplers_to_interconnect_RRESP(1 downto 0) <= M04_AXI_rresp(1 downto 0);
m04_couplers_to_interconnect_RVALID <= M04_AXI_rvalid;
m04_couplers_to_interconnect_WREADY <= M04_AXI_wready;
m05_couplers_to_interconnect_ARREADY <= M05_AXI_arready;
m05_couplers_to_interconnect_AWREADY <= M05_AXI_awready;
m05_couplers_to_interconnect_BRESP(1 downto 0) <= M05_AXI_bresp(1 downto 0);
m05_couplers_to_interconnect_BVALID <= M05_AXI_bvalid;
m05_couplers_to_interconnect_RDATA(31 downto 0) <= M05_AXI_rdata(31 downto 0);
m05_couplers_to_interconnect_RRESP(1 downto 0) <= M05_AXI_rresp(1 downto 0);
m05_couplers_to_interconnect_RVALID <= M05_AXI_rvalid;
m05_couplers_to_interconnect_WREADY <= M05_AXI_wready;
m06_couplers_to_interconnect_ARREADY <= M06_AXI_arready;
m06_couplers_to_interconnect_AWREADY <= M06_AXI_awready;
m06_couplers_to_interconnect_BRESP(1 downto 0) <= M06_AXI_bresp(1 downto 0);
m06_couplers_to_interconnect_BVALID <= M06_AXI_bvalid;
m06_couplers_to_interconnect_RDATA(31 downto 0) <= M06_AXI_rdata(31 downto 0);
m06_couplers_to_interconnect_RRESP(1 downto 0) <= M06_AXI_rresp(1 downto 0);
m06_couplers_to_interconnect_RVALID <= M06_AXI_rvalid;
m06_couplers_to_interconnect_WREADY <= M06_AXI_wready;
m00_couplers: entity work.m00_couplers_imp_4EB6IN
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m00_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_interconnect_ARPROT(2 downto 0),
M_AXI_arready => m00_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m00_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m00_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_interconnect_AWPROT(2 downto 0),
M_AXI_awready => m00_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m00_couplers_to_interconnect_AWVALID,
M_AXI_bready => m00_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m00_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m00_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m00_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m00_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m00_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m00_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_1SL2GIW
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m01_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m01_couplers_to_interconnect_ARPROT(2 downto 0),
M_AXI_arready => m01_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m01_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m01_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m01_couplers_to_interconnect_AWPROT(2 downto 0),
M_AXI_awready => m01_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m01_couplers_to_interconnect_AWVALID,
M_AXI_bready => m01_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m01_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m01_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m01_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m01_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m01_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m01_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m01_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m01_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m01_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m01_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arprot(2 downto 0) => xbar_to_m01_couplers_ARPROT(5 downto 3),
S_AXI_arready => xbar_to_m01_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awprot(2 downto 0) => xbar_to_m01_couplers_AWPROT(5 downto 3),
S_AXI_awready => xbar_to_m01_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready => xbar_to_m01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_7DG2C0
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m02_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m02_couplers_to_interconnect_ARPROT(2 downto 0),
M_AXI_arready => m02_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m02_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m02_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m02_couplers_to_interconnect_AWPROT(2 downto 0),
M_AXI_awready => m02_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m02_couplers_to_interconnect_AWVALID,
M_AXI_bready => m02_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m02_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m02_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m02_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m02_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m02_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m02_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m02_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m02_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m02_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m02_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m02_couplers_ARADDR(95 downto 64),
S_AXI_arprot(2 downto 0) => xbar_to_m02_couplers_ARPROT(8 downto 6),
S_AXI_arready => xbar_to_m02_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(31 downto 0) => xbar_to_m02_couplers_AWADDR(95 downto 64),
S_AXI_awprot(2 downto 0) => xbar_to_m02_couplers_AWPROT(8 downto 6),
S_AXI_awready => xbar_to_m02_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready => xbar_to_m02_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2)
);
m03_couplers: entity work.m03_couplers_imp_1YCPS1Z
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m03_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m03_couplers_to_interconnect_ARPROT(2 downto 0),
M_AXI_arready => m03_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m03_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m03_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m03_couplers_to_interconnect_AWPROT(2 downto 0),
M_AXI_awready => m03_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m03_couplers_to_interconnect_AWVALID,
M_AXI_bready => m03_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m03_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m03_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m03_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m03_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m03_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m03_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m03_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m03_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m03_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m03_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m03_couplers_ARADDR(127 downto 96),
S_AXI_arprot(2 downto 0) => xbar_to_m03_couplers_ARPROT(11 downto 9),
S_AXI_arready => xbar_to_m03_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m03_couplers_ARVALID(3),
S_AXI_awaddr(31 downto 0) => xbar_to_m03_couplers_AWADDR(127 downto 96),
S_AXI_awprot(2 downto 0) => xbar_to_m03_couplers_AWPROT(11 downto 9),
S_AXI_awready => xbar_to_m03_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m03_couplers_AWVALID(3),
S_AXI_bready => xbar_to_m03_couplers_BREADY(3),
S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m03_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m03_couplers_RREADY(3),
S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m03_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
S_AXI_wready => xbar_to_m03_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12),
S_AXI_wvalid => xbar_to_m03_couplers_WVALID(3)
);
m04_couplers: entity work.m04_couplers_imp_ACM7VL
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m04_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arready => m04_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m04_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m04_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awready => m04_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m04_couplers_to_interconnect_AWVALID,
M_AXI_bready => m04_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m04_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m04_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m04_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m04_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m04_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m04_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m04_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m04_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m04_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m04_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m04_couplers_ARADDR(159 downto 128),
S_AXI_arready => xbar_to_m04_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m04_couplers_ARVALID(4),
S_AXI_awaddr(31 downto 0) => xbar_to_m04_couplers_AWADDR(159 downto 128),
S_AXI_awready => xbar_to_m04_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m04_couplers_AWVALID(4),
S_AXI_bready => xbar_to_m04_couplers_BREADY(4),
S_AXI_bresp(1 downto 0) => xbar_to_m04_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m04_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m04_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m04_couplers_RREADY(4),
S_AXI_rresp(1 downto 0) => xbar_to_m04_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m04_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m04_couplers_WDATA(159 downto 128),
S_AXI_wready => xbar_to_m04_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m04_couplers_WSTRB(19 downto 16),
S_AXI_wvalid => xbar_to_m04_couplers_WVALID(4)
);
m05_couplers: entity work.m05_couplers_imp_1HWY5FA
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m05_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arready => m05_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m05_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m05_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awready => m05_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m05_couplers_to_interconnect_AWVALID,
M_AXI_bready => m05_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m05_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m05_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m05_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m05_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m05_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m05_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m05_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m05_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m05_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m05_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m05_couplers_ARADDR(191 downto 160),
S_AXI_arready => xbar_to_m05_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m05_couplers_ARVALID(5),
S_AXI_awaddr(31 downto 0) => xbar_to_m05_couplers_AWADDR(191 downto 160),
S_AXI_awready => xbar_to_m05_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m05_couplers_AWVALID(5),
S_AXI_bready => xbar_to_m05_couplers_BREADY(5),
S_AXI_bresp(1 downto 0) => xbar_to_m05_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m05_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m05_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m05_couplers_RREADY(5),
S_AXI_rresp(1 downto 0) => xbar_to_m05_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m05_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m05_couplers_WDATA(191 downto 160),
S_AXI_wready => xbar_to_m05_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m05_couplers_WSTRB(23 downto 20),
S_AXI_wvalid => xbar_to_m05_couplers_WVALID(5)
);
m06_couplers: entity work.m06_couplers_imp_DBR4EM
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m06_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arready => m06_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m06_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m06_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awready => m06_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m06_couplers_to_interconnect_AWVALID,
M_AXI_bready => m06_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m06_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m06_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m06_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m06_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m06_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m06_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m06_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m06_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m06_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m06_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m06_couplers_ARADDR(223 downto 192),
S_AXI_arready => xbar_to_m06_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m06_couplers_ARVALID(6),
S_AXI_awaddr(31 downto 0) => xbar_to_m06_couplers_AWADDR(223 downto 192),
S_AXI_awready => xbar_to_m06_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m06_couplers_AWVALID(6),
S_AXI_bready => xbar_to_m06_couplers_BREADY(6),
S_AXI_bresp(1 downto 0) => xbar_to_m06_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m06_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m06_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m06_couplers_RREADY(6),
S_AXI_rresp(1 downto 0) => xbar_to_m06_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m06_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m06_couplers_WDATA(223 downto 192),
S_AXI_wready => xbar_to_m06_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m06_couplers_WSTRB(27 downto 24),
S_AXI_wvalid => xbar_to_m06_couplers_WVALID(6)
);
s00_couplers: entity work.s00_couplers_imp_7XIH8P
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => interconnect_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => interconnect_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready => interconnect_to_s00_couplers_ARREADY,
S_AXI_arvalid => interconnect_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => interconnect_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => interconnect_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awready => interconnect_to_s00_couplers_AWREADY,
S_AXI_awvalid => interconnect_to_s00_couplers_AWVALID,
S_AXI_bready => interconnect_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => interconnect_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => interconnect_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => interconnect_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rready => interconnect_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => interconnect_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => interconnect_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => interconnect_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wready => interconnect_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => interconnect_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => interconnect_to_s00_couplers_WVALID
);
s01_couplers: entity work.s01_couplers_imp_1XSI6OU
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => s01_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s01_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s01_couplers_to_xbar_ARREADY(1),
M_AXI_arvalid => s01_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s01_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s01_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s01_couplers_to_xbar_AWREADY(1),
M_AXI_awvalid => s01_couplers_to_xbar_AWVALID,
M_AXI_bready => s01_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s01_couplers_to_xbar_BRESP(3 downto 2),
M_AXI_bvalid => s01_couplers_to_xbar_BVALID(1),
M_AXI_rdata(31 downto 0) => s01_couplers_to_xbar_RDATA(63 downto 32),
M_AXI_rready => s01_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s01_couplers_to_xbar_RRESP(3 downto 2),
M_AXI_rvalid => s01_couplers_to_xbar_RVALID(1),
M_AXI_wdata(31 downto 0) => s01_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s01_couplers_to_xbar_WREADY(1),
M_AXI_wstrb(3 downto 0) => s01_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s01_couplers_to_xbar_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => interconnect_to_s01_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => interconnect_to_s01_couplers_ARPROT(2 downto 0),
S_AXI_arready => interconnect_to_s01_couplers_ARREADY,
S_AXI_arvalid => interconnect_to_s01_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => interconnect_to_s01_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => interconnect_to_s01_couplers_AWPROT(2 downto 0),
S_AXI_awready => interconnect_to_s01_couplers_AWREADY,
S_AXI_awvalid => interconnect_to_s01_couplers_AWVALID,
S_AXI_bready => interconnect_to_s01_couplers_BREADY,
S_AXI_bresp(1 downto 0) => interconnect_to_s01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => interconnect_to_s01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => interconnect_to_s01_couplers_RDATA(31 downto 0),
S_AXI_rready => interconnect_to_s01_couplers_RREADY,
S_AXI_rresp(1 downto 0) => interconnect_to_s01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => interconnect_to_s01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => interconnect_to_s01_couplers_WDATA(31 downto 0),
S_AXI_wready => interconnect_to_s01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => interconnect_to_s01_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => interconnect_to_s01_couplers_WVALID
);
s02_couplers: entity work.s02_couplers_imp_2QLUHY
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => s02_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s02_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s02_couplers_to_xbar_ARREADY(2),
M_AXI_arvalid => s02_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s02_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s02_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s02_couplers_to_xbar_AWREADY(2),
M_AXI_awvalid => s02_couplers_to_xbar_AWVALID,
M_AXI_bready => s02_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s02_couplers_to_xbar_BRESP(5 downto 4),
M_AXI_bvalid => s02_couplers_to_xbar_BVALID(2),
M_AXI_rdata(31 downto 0) => s02_couplers_to_xbar_RDATA(95 downto 64),
M_AXI_rready => s02_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s02_couplers_to_xbar_RRESP(5 downto 4),
M_AXI_rvalid => s02_couplers_to_xbar_RVALID(2),
M_AXI_wdata(31 downto 0) => s02_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s02_couplers_to_xbar_WREADY(2),
M_AXI_wstrb(3 downto 0) => s02_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s02_couplers_to_xbar_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => interconnect_to_s02_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => interconnect_to_s02_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => interconnect_to_s02_couplers_ARCACHE(3 downto 0),
S_AXI_arid(0) => interconnect_to_s02_couplers_ARID(0),
S_AXI_arlen(7 downto 0) => interconnect_to_s02_couplers_ARLEN(7 downto 0),
S_AXI_arlock => interconnect_to_s02_couplers_ARLOCK,
S_AXI_arprot(2 downto 0) => interconnect_to_s02_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => interconnect_to_s02_couplers_ARQOS(3 downto 0),
S_AXI_arready => interconnect_to_s02_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => interconnect_to_s02_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => interconnect_to_s02_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => interconnect_to_s02_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => interconnect_to_s02_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => interconnect_to_s02_couplers_AWCACHE(3 downto 0),
S_AXI_awid(0) => interconnect_to_s02_couplers_AWID(0),
S_AXI_awlen(7 downto 0) => interconnect_to_s02_couplers_AWLEN(7 downto 0),
S_AXI_awlock => interconnect_to_s02_couplers_AWLOCK,
S_AXI_awprot(2 downto 0) => interconnect_to_s02_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => interconnect_to_s02_couplers_AWQOS(3 downto 0),
S_AXI_awready => interconnect_to_s02_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => interconnect_to_s02_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => interconnect_to_s02_couplers_AWVALID,
S_AXI_bid(0) => interconnect_to_s02_couplers_BID(0),
S_AXI_bready => interconnect_to_s02_couplers_BREADY,
S_AXI_bresp(1 downto 0) => interconnect_to_s02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => interconnect_to_s02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => interconnect_to_s02_couplers_RDATA(31 downto 0),
S_AXI_rid(0) => interconnect_to_s02_couplers_RID(0),
S_AXI_rlast => interconnect_to_s02_couplers_RLAST,
S_AXI_rready => interconnect_to_s02_couplers_RREADY,
S_AXI_rresp(1 downto 0) => interconnect_to_s02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => interconnect_to_s02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => interconnect_to_s02_couplers_WDATA(31 downto 0),
S_AXI_wlast => interconnect_to_s02_couplers_WLAST,
S_AXI_wready => interconnect_to_s02_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => interconnect_to_s02_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => interconnect_to_s02_couplers_WVALID
);
xbar: component DemoInterconnect_xbar_0
port map (
aclk => interconnect_ACLK_net,
aresetn => interconnect_ARESETN_net,
m_axi_araddr(223 downto 192) => xbar_to_m06_couplers_ARADDR(223 downto 192),
m_axi_araddr(191 downto 160) => xbar_to_m05_couplers_ARADDR(191 downto 160),
m_axi_araddr(159 downto 128) => xbar_to_m04_couplers_ARADDR(159 downto 128),
m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(20 downto 12) => NLW_xbar_m_axi_arprot_UNCONNECTED(20 downto 12),
m_axi_arprot(11 downto 9) => xbar_to_m03_couplers_ARPROT(11 downto 9),
m_axi_arprot(8 downto 6) => xbar_to_m02_couplers_ARPROT(8 downto 6),
m_axi_arprot(5 downto 3) => xbar_to_m01_couplers_ARPROT(5 downto 3),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arready(6) => xbar_to_m06_couplers_ARREADY,
m_axi_arready(5) => xbar_to_m05_couplers_ARREADY,
m_axi_arready(4) => xbar_to_m04_couplers_ARREADY,
m_axi_arready(3) => xbar_to_m03_couplers_ARREADY,
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY,
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arvalid(6) => xbar_to_m06_couplers_ARVALID(6),
m_axi_arvalid(5) => xbar_to_m05_couplers_ARVALID(5),
m_axi_arvalid(4) => xbar_to_m04_couplers_ARVALID(4),
m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(223 downto 192) => xbar_to_m06_couplers_AWADDR(223 downto 192),
m_axi_awaddr(191 downto 160) => xbar_to_m05_couplers_AWADDR(191 downto 160),
m_axi_awaddr(159 downto 128) => xbar_to_m04_couplers_AWADDR(159 downto 128),
m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(20 downto 12) => NLW_xbar_m_axi_awprot_UNCONNECTED(20 downto 12),
m_axi_awprot(11 downto 9) => xbar_to_m03_couplers_AWPROT(11 downto 9),
m_axi_awprot(8 downto 6) => xbar_to_m02_couplers_AWPROT(8 downto 6),
m_axi_awprot(5 downto 3) => xbar_to_m01_couplers_AWPROT(5 downto 3),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awready(6) => xbar_to_m06_couplers_AWREADY,
m_axi_awready(5) => xbar_to_m05_couplers_AWREADY,
m_axi_awready(4) => xbar_to_m04_couplers_AWREADY,
m_axi_awready(3) => xbar_to_m03_couplers_AWREADY,
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY,
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awvalid(6) => xbar_to_m06_couplers_AWVALID(6),
m_axi_awvalid(5) => xbar_to_m05_couplers_AWVALID(5),
m_axi_awvalid(4) => xbar_to_m04_couplers_AWVALID(4),
m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(6) => xbar_to_m06_couplers_BREADY(6),
m_axi_bready(5) => xbar_to_m05_couplers_BREADY(5),
m_axi_bready(4) => xbar_to_m04_couplers_BREADY(4),
m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(13 downto 12) => xbar_to_m06_couplers_BRESP(1 downto 0),
m_axi_bresp(11 downto 10) => xbar_to_m05_couplers_BRESP(1 downto 0),
m_axi_bresp(9 downto 8) => xbar_to_m04_couplers_BRESP(1 downto 0),
m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(6) => xbar_to_m06_couplers_BVALID,
m_axi_bvalid(5) => xbar_to_m05_couplers_BVALID,
m_axi_bvalid(4) => xbar_to_m04_couplers_BVALID,
m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID,
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID,
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(223 downto 192) => xbar_to_m06_couplers_RDATA(31 downto 0),
m_axi_rdata(191 downto 160) => xbar_to_m05_couplers_RDATA(31 downto 0),
m_axi_rdata(159 downto 128) => xbar_to_m04_couplers_RDATA(31 downto 0),
m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(6) => xbar_to_m06_couplers_RREADY(6),
m_axi_rready(5) => xbar_to_m05_couplers_RREADY(5),
m_axi_rready(4) => xbar_to_m04_couplers_RREADY(4),
m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(13 downto 12) => xbar_to_m06_couplers_RRESP(1 downto 0),
m_axi_rresp(11 downto 10) => xbar_to_m05_couplers_RRESP(1 downto 0),
m_axi_rresp(9 downto 8) => xbar_to_m04_couplers_RRESP(1 downto 0),
m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(6) => xbar_to_m06_couplers_RVALID,
m_axi_rvalid(5) => xbar_to_m05_couplers_RVALID,
m_axi_rvalid(4) => xbar_to_m04_couplers_RVALID,
m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID,
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID,
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(223 downto 192) => xbar_to_m06_couplers_WDATA(223 downto 192),
m_axi_wdata(191 downto 160) => xbar_to_m05_couplers_WDATA(191 downto 160),
m_axi_wdata(159 downto 128) => xbar_to_m04_couplers_WDATA(159 downto 128),
m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(6) => xbar_to_m06_couplers_WREADY,
m_axi_wready(5) => xbar_to_m05_couplers_WREADY,
m_axi_wready(4) => xbar_to_m04_couplers_WREADY,
m_axi_wready(3) => xbar_to_m03_couplers_WREADY,
m_axi_wready(2) => xbar_to_m02_couplers_WREADY,
m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(27 downto 24) => xbar_to_m06_couplers_WSTRB(27 downto 24),
m_axi_wstrb(23 downto 20) => xbar_to_m05_couplers_WSTRB(23 downto 20),
m_axi_wstrb(19 downto 16) => xbar_to_m04_couplers_WSTRB(19 downto 16),
m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(6) => xbar_to_m06_couplers_WVALID(6),
m_axi_wvalid(5) => xbar_to_m05_couplers_WVALID(5),
m_axi_wvalid(4) => xbar_to_m04_couplers_WVALID(4),
m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(95 downto 64) => s02_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_araddr(63 downto 32) => s01_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(8 downto 6) => s02_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arprot(5 downto 3) => s01_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(2) => s02_couplers_to_xbar_ARREADY(2),
s_axi_arready(1) => s01_couplers_to_xbar_ARREADY(1),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(2) => s02_couplers_to_xbar_ARVALID,
s_axi_arvalid(1) => s01_couplers_to_xbar_ARVALID,
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(95 downto 64) => s02_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(63 downto 32) => s01_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(8 downto 6) => s02_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(5 downto 3) => s01_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(2) => s02_couplers_to_xbar_AWREADY(2),
s_axi_awready(1) => s01_couplers_to_xbar_AWREADY(1),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(2) => s02_couplers_to_xbar_AWVALID,
s_axi_awvalid(1) => s01_couplers_to_xbar_AWVALID,
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(2) => s02_couplers_to_xbar_BREADY,
s_axi_bready(1) => s01_couplers_to_xbar_BREADY,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(5 downto 4) => s02_couplers_to_xbar_BRESP(5 downto 4),
s_axi_bresp(3 downto 2) => s01_couplers_to_xbar_BRESP(3 downto 2),
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(2) => s02_couplers_to_xbar_BVALID(2),
s_axi_bvalid(1) => s01_couplers_to_xbar_BVALID(1),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(95 downto 64) => s02_couplers_to_xbar_RDATA(95 downto 64),
s_axi_rdata(63 downto 32) => s01_couplers_to_xbar_RDATA(63 downto 32),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(2) => s02_couplers_to_xbar_RREADY,
s_axi_rready(1) => s01_couplers_to_xbar_RREADY,
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(5 downto 4) => s02_couplers_to_xbar_RRESP(5 downto 4),
s_axi_rresp(3 downto 2) => s01_couplers_to_xbar_RRESP(3 downto 2),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(2) => s02_couplers_to_xbar_RVALID(2),
s_axi_rvalid(1) => s01_couplers_to_xbar_RVALID(1),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(95 downto 64) => s02_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wdata(63 downto 32) => s01_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(2) => s02_couplers_to_xbar_WREADY(2),
s_axi_wready(1) => s01_couplers_to_xbar_WREADY(1),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(11 downto 8) => s02_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wstrb(7 downto 4) => s01_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(2) => s02_couplers_to_xbar_WVALID,
s_axi_wvalid(1) => s01_couplers_to_xbar_WVALID,
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity DemoInterconnect is
port (
LED0_pll_aclk : out STD_LOGIC;
LED1_pll_uart : out STD_LOGIC;
LED2_pll_lock : out STD_LOGIC;
UART_RX_0 : in STD_LOGIC;
UART_RX_1 : in STD_LOGIC;
UART_TX_0 : out STD_LOGIC;
UART_TX_1 : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_miso_1 : in STD_LOGIC;
m_spi_miso_2 : in STD_LOGIC;
m_spi_miso_3 : in STD_LOGIC;
m_spi_mosi : out STD_LOGIC;
m_spi_mosi_1 : out STD_LOGIC;
m_spi_mosi_2 : out STD_LOGIC;
m_spi_mosi_3 : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
m_spi_sclk_1 : out STD_LOGIC;
m_spi_sclk_2 : out STD_LOGIC;
m_spi_sclk_3 : out STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_ss_1 : out STD_LOGIC;
m_spi_ss_2 : out STD_LOGIC;
m_spi_ss_3 : out STD_LOGIC;
sys_clk : in STD_LOGIC;
sys_reset : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of DemoInterconnect : entity is "DemoInterconnect,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=DemoInterconnect,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=25,numReposBlks=14,numNonXlnxBlks=8,numHierBlks=11,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=6,da_board_cnt=5,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of DemoInterconnect : entity is "DemoInterconnect.hwdef";
end DemoInterconnect;
architecture STRUCTURE of DemoInterconnect is
component DemoInterconnect_clk_wiz_0_0 is
port (
reset : in STD_LOGIC;
clk_in1 : in STD_LOGIC;
aclk : out STD_LOGIC;
uart : out STD_LOGIC;
locked : out STD_LOGIC
);
end component DemoInterconnect_clk_wiz_0_0;
component DemoInterconnect_jtag_axi_0_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC;
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC;
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component DemoInterconnect_jtag_axi_0_0;
component DemoInterconnect_mutex_0_0 is
port (
S0_AXI_ACLK : in STD_LOGIC;
S0_AXI_ARESETN : in STD_LOGIC;
S0_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S0_AXI_AWVALID : in STD_LOGIC;
S0_AXI_AWREADY : out STD_LOGIC;
S0_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S0_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S0_AXI_WVALID : in STD_LOGIC;
S0_AXI_WREADY : out STD_LOGIC;
S0_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S0_AXI_BVALID : out STD_LOGIC;
S0_AXI_BREADY : in STD_LOGIC;
S0_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S0_AXI_ARVALID : in STD_LOGIC;
S0_AXI_ARREADY : out STD_LOGIC;
S0_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S0_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S0_AXI_RVALID : out STD_LOGIC;
S0_AXI_RREADY : in STD_LOGIC;
S1_AXI_ACLK : in STD_LOGIC;
S1_AXI_ARESETN : in STD_LOGIC;
S1_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S1_AXI_AWVALID : in STD_LOGIC;
S1_AXI_AWREADY : out STD_LOGIC;
S1_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S1_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S1_AXI_WVALID : in STD_LOGIC;
S1_AXI_WREADY : out STD_LOGIC;
S1_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S1_AXI_BVALID : out STD_LOGIC;
S1_AXI_BREADY : in STD_LOGIC;
S1_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S1_AXI_ARVALID : in STD_LOGIC;
S1_AXI_ARREADY : out STD_LOGIC;
S1_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S1_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S1_AXI_RVALID : out STD_LOGIC;
S1_AXI_RREADY : in STD_LOGIC;
S2_AXI_ACLK : in STD_LOGIC;
S2_AXI_ARESETN : in STD_LOGIC;
S2_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S2_AXI_AWVALID : in STD_LOGIC;
S2_AXI_AWREADY : out STD_LOGIC;
S2_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S2_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S2_AXI_WVALID : in STD_LOGIC;
S2_AXI_WREADY : out STD_LOGIC;
S2_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S2_AXI_BVALID : out STD_LOGIC;
S2_AXI_BREADY : in STD_LOGIC;
S2_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S2_AXI_ARVALID : in STD_LOGIC;
S2_AXI_ARREADY : out STD_LOGIC;
S2_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S2_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S2_AXI_RVALID : out STD_LOGIC;
S2_AXI_RREADY : in STD_LOGIC
);
end component DemoInterconnect_mutex_0_0;
component DemoInterconnect_uart_transceiver_0_0 is
port (
i_Clk : in STD_LOGIC;
i_RX_Serial : in STD_LOGIC;
o_RX_Done : out STD_LOGIC;
o_RX_Byte : out STD_LOGIC_VECTOR ( 7 downto 0 );
i_TX_Load : in STD_LOGIC;
i_TX_Byte : in STD_LOGIC_VECTOR ( 7 downto 0 );
o_TX_Active : out STD_LOGIC;
o_TX_Serial : out STD_LOGIC;
o_TX_Done : out STD_LOGIC
);
end component DemoInterconnect_uart_transceiver_0_0;
component DemoInterconnect_uart_transceiver_0_1 is
port (
i_Clk : in STD_LOGIC;
i_RX_Serial : in STD_LOGIC;
o_RX_Done : out STD_LOGIC;
o_RX_Byte : out STD_LOGIC_VECTOR ( 7 downto 0 );
i_TX_Load : in STD_LOGIC;
i_TX_Byte : in STD_LOGIC_VECTOR ( 7 downto 0 );
o_TX_Active : out STD_LOGIC;
o_TX_Serial : out STD_LOGIC;
o_TX_Done : out STD_LOGIC
);
end component DemoInterconnect_uart_transceiver_0_1;
component DemoInterconnect_axi_spi_master_0_0 is
port (
m_spi_mosi : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_axi_spi_master_0_0;
component DemoInterconnect_axi_spi_master_0_1 is
port (
m_spi_mosi : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_axi_spi_master_0_1;
component DemoInterconnect_axi_spi_master_1_0 is
port (
m_spi_mosi : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_axi_spi_master_1_0;
component DemoInterconnect_axi_spi_master_1_1 is
port (
m_spi_mosi : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_axi_spi_master_1_1;
component DemoInterconnect_ila_0_0 is
port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component DemoInterconnect_ila_0_0;
component DemoInterconnect_internoc_ni_axi_master_0_0 is
port (
if00_data_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
if00_load_in : in STD_LOGIC;
if00_data_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
if00_load_out : out STD_LOGIC;
if00_send_done : in STD_LOGIC;
if00_send_busy : in STD_LOGIC;
m00_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m00_axi_awvalid : out STD_LOGIC;
m00_axi_awready : in STD_LOGIC;
m00_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m00_axi_wvalid : out STD_LOGIC;
m00_axi_wready : in STD_LOGIC;
m00_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m00_axi_bvalid : in STD_LOGIC;
m00_axi_bready : out STD_LOGIC;
m00_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m00_axi_arvalid : out STD_LOGIC;
m00_axi_arready : in STD_LOGIC;
m00_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m00_axi_rvalid : in STD_LOGIC;
m00_axi_rready : out STD_LOGIC;
m00_axi_aclk : in STD_LOGIC;
m00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_internoc_ni_axi_master_0_0;
component DemoInterconnect_internoc_ni_axi_master_1_0 is
port (
if00_data_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
if00_load_in : in STD_LOGIC;
if00_data_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
if00_load_out : out STD_LOGIC;
if00_send_done : in STD_LOGIC;
if00_send_busy : in STD_LOGIC;
m00_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m00_axi_awvalid : out STD_LOGIC;
m00_axi_awready : in STD_LOGIC;
m00_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m00_axi_wvalid : out STD_LOGIC;
m00_axi_wready : in STD_LOGIC;
m00_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m00_axi_bvalid : in STD_LOGIC;
m00_axi_bready : out STD_LOGIC;
m00_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m00_axi_arvalid : out STD_LOGIC;
m00_axi_arready : in STD_LOGIC;
m00_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m00_axi_rvalid : in STD_LOGIC;
m00_axi_rready : out STD_LOGIC;
m00_axi_aclk : in STD_LOGIC;
m00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_internoc_ni_axi_master_1_0;
signal UART_RX_0_1 : STD_LOGIC;
signal UART_RX_1_1 : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M01_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M01_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M01_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M01_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M01_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M02_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M02_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M02_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M02_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M02_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M03_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M03_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M03_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M03_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M03_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M04_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M04_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M04_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M05_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M05_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M05_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M05_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M05_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M05_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M05_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M06_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M06_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M06_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M06_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M06_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M06_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M06_AXI_WVALID : STD_LOGIC;
signal axi_spi_master_0_m_spi_mosi : STD_LOGIC;
signal axi_spi_master_0_m_spi_sclk : STD_LOGIC;
signal axi_spi_master_0_m_spi_ss : STD_LOGIC;
signal axi_spi_master_1_m_spi_mosi : STD_LOGIC;
signal axi_spi_master_1_m_spi_sclk : STD_LOGIC;
signal axi_spi_master_1_m_spi_ss : STD_LOGIC;
signal axi_spi_master_2_m_spi_mosi : STD_LOGIC;
signal axi_spi_master_2_m_spi_sclk : STD_LOGIC;
signal axi_spi_master_2_m_spi_ss : STD_LOGIC;
signal axi_spi_master_3_m_spi_mosi : STD_LOGIC;
signal axi_spi_master_3_m_spi_sclk : STD_LOGIC;
signal axi_spi_master_3_m_spi_ss : STD_LOGIC;
signal clk_wiz_0_clk_out1 : STD_LOGIC;
signal clk_wiz_0_locked : STD_LOGIC;
signal clk_wiz_0_uart : STD_LOGIC;
signal interface_axi_master_0_if00_data_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal interface_axi_master_0_if00_load_out : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_ARREADY : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_ARVALID : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_AWREADY : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_AWVALID : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_BREADY : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_BVALID : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_RREADY : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_RVALID : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_WREADY : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_WVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_ARREADY : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_ARVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_AWREADY : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_AWVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_BREADY : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_BVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_RREADY : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_RVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_WREADY : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_WVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_if00_data_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal internoc_ni_axi_master_1_if00_load_out : STD_LOGIC;
signal jtag_axi_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal jtag_axi_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal jtag_axi_0_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal jtag_axi_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal jtag_axi_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal jtag_axi_0_M_AXI_ARLOCK : STD_LOGIC;
signal jtag_axi_0_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal jtag_axi_0_M_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal jtag_axi_0_M_AXI_ARREADY : STD_LOGIC;
signal jtag_axi_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal jtag_axi_0_M_AXI_ARVALID : STD_LOGIC;
signal jtag_axi_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal jtag_axi_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal jtag_axi_0_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal jtag_axi_0_M_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal jtag_axi_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal jtag_axi_0_M_AXI_AWLOCK : STD_LOGIC;
signal jtag_axi_0_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal jtag_axi_0_M_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal jtag_axi_0_M_AXI_AWREADY : STD_LOGIC;
signal jtag_axi_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal jtag_axi_0_M_AXI_AWVALID : STD_LOGIC;
signal jtag_axi_0_M_AXI_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal jtag_axi_0_M_AXI_BREADY : STD_LOGIC;
signal jtag_axi_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal jtag_axi_0_M_AXI_BVALID : STD_LOGIC;
signal jtag_axi_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal jtag_axi_0_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal jtag_axi_0_M_AXI_RLAST : STD_LOGIC;
signal jtag_axi_0_M_AXI_RREADY : STD_LOGIC;
signal jtag_axi_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal jtag_axi_0_M_AXI_RVALID : STD_LOGIC;
signal jtag_axi_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal jtag_axi_0_M_AXI_WLAST : STD_LOGIC;
signal jtag_axi_0_M_AXI_WREADY : STD_LOGIC;
signal jtag_axi_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal jtag_axi_0_M_AXI_WVALID : STD_LOGIC;
signal \^m_spi_miso_1\ : STD_LOGIC;
signal m_spi_miso_1_1 : STD_LOGIC;
signal m_spi_miso_2_1 : STD_LOGIC;
signal m_spi_miso_3_1 : STD_LOGIC;
signal sys_clk_1 : STD_LOGIC;
signal uart_transceiver_0_o_RX_Byte : STD_LOGIC_VECTOR ( 7 downto 0 );
signal uart_transceiver_0_o_RX_Done : STD_LOGIC;
signal uart_transceiver_0_o_TX_Active : STD_LOGIC;
signal uart_transceiver_0_o_TX_Done : STD_LOGIC;
signal uart_transceiver_0_o_TX_Serial : STD_LOGIC;
signal uart_transceiver_1_o_RX_Byte : STD_LOGIC_VECTOR ( 7 downto 0 );
signal uart_transceiver_1_o_RX_Done : STD_LOGIC;
signal uart_transceiver_1_o_TX_Active : STD_LOGIC;
signal uart_transceiver_1_o_TX_Done : STD_LOGIC;
signal uart_transceiver_1_o_TX_Serial : STD_LOGIC;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of UART_RX_0 : signal is "xilinx.com:signal:data:1.0 DATA.UART_RX_0 DATA";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of UART_RX_0 : signal is "XIL_INTERFACENAME DATA.UART_RX_0, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of UART_RX_1 : signal is "xilinx.com:signal:data:1.0 DATA.UART_RX_1 DATA";
attribute X_INTERFACE_PARAMETER of UART_RX_1 : signal is "XIL_INTERFACENAME DATA.UART_RX_1, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of UART_TX_1 : signal is "xilinx.com:signal:data:1.0 DATA.UART_TX_1 DATA";
attribute X_INTERFACE_PARAMETER of UART_TX_1 : signal is "XIL_INTERFACENAME DATA.UART_TX_1, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_miso : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MISO DATA";
attribute X_INTERFACE_PARAMETER of m_spi_miso : signal is "XIL_INTERFACENAME DATA.M_SPI_MISO, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_miso_1 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MISO_1 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_miso_1 : signal is "XIL_INTERFACENAME DATA.M_SPI_MISO_1, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_miso_2 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MISO_2 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_miso_2 : signal is "XIL_INTERFACENAME DATA.M_SPI_MISO_2, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_miso_3 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MISO_3 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_miso_3 : signal is "XIL_INTERFACENAME DATA.M_SPI_MISO_3, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_mosi : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MOSI DATA";
attribute X_INTERFACE_PARAMETER of m_spi_mosi : signal is "XIL_INTERFACENAME DATA.M_SPI_MOSI, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_mosi_1 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MOSI_1 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_mosi_1 : signal is "XIL_INTERFACENAME DATA.M_SPI_MOSI_1, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_mosi_2 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MOSI_2 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_mosi_2 : signal is "XIL_INTERFACENAME DATA.M_SPI_MOSI_2, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_mosi_3 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MOSI_3 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_mosi_3 : signal is "XIL_INTERFACENAME DATA.M_SPI_MOSI_3, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_sclk : signal is "xilinx.com:signal:clock:1.0 CLK.M_SPI_SCLK CLK";
attribute X_INTERFACE_PARAMETER of m_spi_sclk : signal is "XIL_INTERFACENAME CLK.M_SPI_SCLK, CLK_DOMAIN DemoInterconnect_axi_spi_master_0_0_m_spi_sclk, FREQ_HZ 100000000, PHASE 0.000";
attribute X_INTERFACE_INFO of m_spi_sclk_1 : signal is "xilinx.com:signal:clock:1.0 CLK.M_SPI_SCLK_1 CLK";
attribute X_INTERFACE_PARAMETER of m_spi_sclk_1 : signal is "XIL_INTERFACENAME CLK.M_SPI_SCLK_1, CLK_DOMAIN DemoInterconnect_axi_spi_master_0_1_m_spi_sclk, FREQ_HZ 100000000, PHASE 0.000";
attribute X_INTERFACE_INFO of m_spi_sclk_2 : signal is "xilinx.com:signal:clock:1.0 CLK.M_SPI_SCLK_2 CLK";
attribute X_INTERFACE_PARAMETER of m_spi_sclk_2 : signal is "XIL_INTERFACENAME CLK.M_SPI_SCLK_2, CLK_DOMAIN DemoInterconnect_axi_spi_master_1_0_m_spi_sclk, FREQ_HZ 100000000, PHASE 0.000";
attribute X_INTERFACE_INFO of m_spi_sclk_3 : signal is "xilinx.com:signal:clock:1.0 CLK.M_SPI_SCLK_3 CLK";
attribute X_INTERFACE_PARAMETER of m_spi_sclk_3 : signal is "XIL_INTERFACENAME CLK.M_SPI_SCLK_3, CLK_DOMAIN DemoInterconnect_axi_spi_master_1_1_m_spi_sclk, FREQ_HZ 100000000, PHASE 0.000";
attribute X_INTERFACE_INFO of m_spi_ss : signal is "xilinx.com:signal:clockenable:1.0 CE.M_SPI_SS CE";
attribute X_INTERFACE_PARAMETER of m_spi_ss : signal is "XIL_INTERFACENAME CE.M_SPI_SS, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of m_spi_ss_1 : signal is "xilinx.com:signal:clockenable:1.0 CE.M_SPI_SS_1 CE";
attribute X_INTERFACE_PARAMETER of m_spi_ss_1 : signal is "XIL_INTERFACENAME CE.M_SPI_SS_1, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of m_spi_ss_2 : signal is "xilinx.com:signal:clockenable:1.0 CE.M_SPI_SS_2 CE";
attribute X_INTERFACE_PARAMETER of m_spi_ss_2 : signal is "XIL_INTERFACENAME CE.M_SPI_SS_2, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of m_spi_ss_3 : signal is "xilinx.com:signal:clockenable:1.0 CE.M_SPI_SS_3 CE";
attribute X_INTERFACE_PARAMETER of m_spi_ss_3 : signal is "XIL_INTERFACENAME CE.M_SPI_SS_3, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of sys_clk : signal is "xilinx.com:signal:clock:1.0 CLK.SYS_CLK CLK";
attribute X_INTERFACE_PARAMETER of sys_clk : signal is "XIL_INTERFACENAME CLK.SYS_CLK, ASSOCIATED_RESET sys_reset, CLK_DOMAIN DemoInterconnect_sys_clk, FREQ_HZ 12000000, PHASE 0.000";
attribute X_INTERFACE_INFO of sys_reset : signal is "xilinx.com:signal:reset:1.0 RST.SYS_RESET RST";
attribute X_INTERFACE_PARAMETER of sys_reset : signal is "XIL_INTERFACENAME RST.SYS_RESET, POLARITY ACTIVE_HIGH";
begin
LED0_pll_aclk <= clk_wiz_0_clk_out1;
LED1_pll_uart <= clk_wiz_0_uart;
LED2_pll_lock <= clk_wiz_0_locked;
UART_RX_0_1 <= UART_RX_0;
UART_RX_1_1 <= UART_RX_1;
UART_TX_0 <= uart_transceiver_0_o_TX_Serial;
UART_TX_1 <= uart_transceiver_1_o_TX_Serial;
\^m_spi_miso_1\ <= m_spi_miso;
m_spi_miso_1_1 <= m_spi_miso_1;
m_spi_miso_2_1 <= m_spi_miso_2;
m_spi_miso_3_1 <= m_spi_miso_3;
m_spi_mosi <= axi_spi_master_0_m_spi_mosi;
m_spi_mosi_1 <= axi_spi_master_1_m_spi_mosi;
m_spi_mosi_2 <= axi_spi_master_2_m_spi_mosi;
m_spi_mosi_3 <= axi_spi_master_3_m_spi_mosi;
m_spi_sclk <= axi_spi_master_0_m_spi_sclk;
m_spi_sclk_1 <= axi_spi_master_1_m_spi_sclk;
m_spi_sclk_2 <= axi_spi_master_2_m_spi_sclk;
m_spi_sclk_3 <= axi_spi_master_3_m_spi_sclk;
m_spi_ss <= axi_spi_master_0_m_spi_ss;
m_spi_ss_1 <= axi_spi_master_1_m_spi_ss;
m_spi_ss_2 <= axi_spi_master_2_m_spi_ss;
m_spi_ss_3 <= axi_spi_master_3_m_spi_ss;
sys_clk_1 <= sys_clk;
axi_spi_master_0: component DemoInterconnect_axi_spi_master_0_0
port map (
m_spi_miso => \^m_spi_miso_1\,
m_spi_mosi => axi_spi_master_0_m_spi_mosi,
m_spi_sclk => axi_spi_master_0_m_spi_sclk,
m_spi_ss => axi_spi_master_0_m_spi_ss,
s00_axi_aclk => clk_wiz_0_clk_out1,
s00_axi_araddr(3 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => clk_wiz_0_locked,
s00_axi_arprot(2 downto 0) => axi_interconnect_0_M00_AXI_ARPROT(2 downto 0),
s00_axi_arready => axi_interconnect_0_M00_AXI_ARREADY,
s00_axi_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
s00_axi_awaddr(3 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => axi_interconnect_0_M00_AXI_AWPROT(2 downto 0),
s00_axi_awready => axi_interconnect_0_M00_AXI_AWREADY,
s00_axi_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
s00_axi_bready => axi_interconnect_0_M00_AXI_BREADY,
s00_axi_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
s00_axi_bvalid => axi_interconnect_0_M00_AXI_BVALID,
s00_axi_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
s00_axi_rready => axi_interconnect_0_M00_AXI_RREADY,
s00_axi_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
s00_axi_rvalid => axi_interconnect_0_M00_AXI_RVALID,
s00_axi_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
s00_axi_wready => axi_interconnect_0_M00_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => axi_interconnect_0_M00_AXI_WVALID
);
axi_spi_master_1: component DemoInterconnect_axi_spi_master_0_1
port map (
m_spi_miso => m_spi_miso_1_1,
m_spi_mosi => axi_spi_master_1_m_spi_mosi,
m_spi_sclk => axi_spi_master_1_m_spi_sclk,
m_spi_ss => axi_spi_master_1_m_spi_ss,
s00_axi_aclk => clk_wiz_0_clk_out1,
s00_axi_araddr(3 downto 0) => axi_interconnect_0_M01_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => clk_wiz_0_locked,
s00_axi_arprot(2 downto 0) => axi_interconnect_0_M01_AXI_ARPROT(2 downto 0),
s00_axi_arready => axi_interconnect_0_M01_AXI_ARREADY,
s00_axi_arvalid => axi_interconnect_0_M01_AXI_ARVALID,
s00_axi_awaddr(3 downto 0) => axi_interconnect_0_M01_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => axi_interconnect_0_M01_AXI_AWPROT(2 downto 0),
s00_axi_awready => axi_interconnect_0_M01_AXI_AWREADY,
s00_axi_awvalid => axi_interconnect_0_M01_AXI_AWVALID,
s00_axi_bready => axi_interconnect_0_M01_AXI_BREADY,
s00_axi_bresp(1 downto 0) => axi_interconnect_0_M01_AXI_BRESP(1 downto 0),
s00_axi_bvalid => axi_interconnect_0_M01_AXI_BVALID,
s00_axi_rdata(31 downto 0) => axi_interconnect_0_M01_AXI_RDATA(31 downto 0),
s00_axi_rready => axi_interconnect_0_M01_AXI_RREADY,
s00_axi_rresp(1 downto 0) => axi_interconnect_0_M01_AXI_RRESP(1 downto 0),
s00_axi_rvalid => axi_interconnect_0_M01_AXI_RVALID,
s00_axi_wdata(31 downto 0) => axi_interconnect_0_M01_AXI_WDATA(31 downto 0),
s00_axi_wready => axi_interconnect_0_M01_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => axi_interconnect_0_M01_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => axi_interconnect_0_M01_AXI_WVALID
);
axi_spi_master_2: component DemoInterconnect_axi_spi_master_1_0
port map (
m_spi_miso => m_spi_miso_2_1,
m_spi_mosi => axi_spi_master_2_m_spi_mosi,
m_spi_sclk => axi_spi_master_2_m_spi_sclk,
m_spi_ss => axi_spi_master_2_m_spi_ss,
s00_axi_aclk => clk_wiz_0_clk_out1,
s00_axi_araddr(3 downto 0) => axi_interconnect_0_M02_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => clk_wiz_0_locked,
s00_axi_arprot(2 downto 0) => axi_interconnect_0_M02_AXI_ARPROT(2 downto 0),
s00_axi_arready => axi_interconnect_0_M02_AXI_ARREADY,
s00_axi_arvalid => axi_interconnect_0_M02_AXI_ARVALID,
s00_axi_awaddr(3 downto 0) => axi_interconnect_0_M02_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => axi_interconnect_0_M02_AXI_AWPROT(2 downto 0),
s00_axi_awready => axi_interconnect_0_M02_AXI_AWREADY,
s00_axi_awvalid => axi_interconnect_0_M02_AXI_AWVALID,
s00_axi_bready => axi_interconnect_0_M02_AXI_BREADY,
s00_axi_bresp(1 downto 0) => axi_interconnect_0_M02_AXI_BRESP(1 downto 0),
s00_axi_bvalid => axi_interconnect_0_M02_AXI_BVALID,
s00_axi_rdata(31 downto 0) => axi_interconnect_0_M02_AXI_RDATA(31 downto 0),
s00_axi_rready => axi_interconnect_0_M02_AXI_RREADY,
s00_axi_rresp(1 downto 0) => axi_interconnect_0_M02_AXI_RRESP(1 downto 0),
s00_axi_rvalid => axi_interconnect_0_M02_AXI_RVALID,
s00_axi_wdata(31 downto 0) => axi_interconnect_0_M02_AXI_WDATA(31 downto 0),
s00_axi_wready => axi_interconnect_0_M02_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => axi_interconnect_0_M02_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => axi_interconnect_0_M02_AXI_WVALID
);
axi_spi_master_3: component DemoInterconnect_axi_spi_master_1_1
port map (
m_spi_miso => m_spi_miso_3_1,
m_spi_mosi => axi_spi_master_3_m_spi_mosi,
m_spi_sclk => axi_spi_master_3_m_spi_sclk,
m_spi_ss => axi_spi_master_3_m_spi_ss,
s00_axi_aclk => clk_wiz_0_clk_out1,
s00_axi_araddr(3 downto 0) => axi_interconnect_0_M03_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => clk_wiz_0_locked,
s00_axi_arprot(2 downto 0) => axi_interconnect_0_M03_AXI_ARPROT(2 downto 0),
s00_axi_arready => axi_interconnect_0_M03_AXI_ARREADY,
s00_axi_arvalid => axi_interconnect_0_M03_AXI_ARVALID,
s00_axi_awaddr(3 downto 0) => axi_interconnect_0_M03_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => axi_interconnect_0_M03_AXI_AWPROT(2 downto 0),
s00_axi_awready => axi_interconnect_0_M03_AXI_AWREADY,
s00_axi_awvalid => axi_interconnect_0_M03_AXI_AWVALID,
s00_axi_bready => axi_interconnect_0_M03_AXI_BREADY,
s00_axi_bresp(1 downto 0) => axi_interconnect_0_M03_AXI_BRESP(1 downto 0),
s00_axi_bvalid => axi_interconnect_0_M03_AXI_BVALID,
s00_axi_rdata(31 downto 0) => axi_interconnect_0_M03_AXI_RDATA(31 downto 0),
s00_axi_rready => axi_interconnect_0_M03_AXI_RREADY,
s00_axi_rresp(1 downto 0) => axi_interconnect_0_M03_AXI_RRESP(1 downto 0),
s00_axi_rvalid => axi_interconnect_0_M03_AXI_RVALID,
s00_axi_wdata(31 downto 0) => axi_interconnect_0_M03_AXI_WDATA(31 downto 0),
s00_axi_wready => axi_interconnect_0_M03_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => axi_interconnect_0_M03_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => axi_interconnect_0_M03_AXI_WVALID
);
clk_wiz_0: component DemoInterconnect_clk_wiz_0_0
port map (
aclk => clk_wiz_0_clk_out1,
clk_in1 => sys_clk_1,
locked => clk_wiz_0_locked,
reset => sys_reset,
uart => clk_wiz_0_uart
);
ila_0: component DemoInterconnect_ila_0_0
port map (
clk => clk_wiz_0_clk_out1,
probe0(0) => uart_transceiver_0_o_RX_Done,
probe1(7 downto 0) => uart_transceiver_0_o_RX_Byte(7 downto 0),
probe2(0) => interface_axi_master_0_if00_load_out,
probe3(7 downto 0) => interface_axi_master_0_if00_data_out(7 downto 0)
);
interconnect: entity work.DemoInterconnect_axi_interconnect_0_0
port map (
ACLK => clk_wiz_0_clk_out1,
ARESETN => clk_wiz_0_locked,
M00_ACLK => clk_wiz_0_clk_out1,
M00_ARESETN => clk_wiz_0_locked,
M00_AXI_araddr(31 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arprot(2 downto 0) => axi_interconnect_0_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arready => axi_interconnect_0_M00_AXI_ARREADY,
M00_AXI_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awprot(2 downto 0) => axi_interconnect_0_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awready => axi_interconnect_0_M00_AXI_AWREADY,
M00_AXI_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
M00_AXI_bready => axi_interconnect_0_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_interconnect_0_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready => axi_interconnect_0_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_interconnect_0_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready => axi_interconnect_0_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => axi_interconnect_0_M00_AXI_WVALID,
M01_ACLK => clk_wiz_0_clk_out1,
M01_ARESETN => clk_wiz_0_locked,
M01_AXI_araddr(31 downto 0) => axi_interconnect_0_M01_AXI_ARADDR(31 downto 0),
M01_AXI_arprot(2 downto 0) => axi_interconnect_0_M01_AXI_ARPROT(2 downto 0),
M01_AXI_arready => axi_interconnect_0_M01_AXI_ARREADY,
M01_AXI_arvalid => axi_interconnect_0_M01_AXI_ARVALID,
M01_AXI_awaddr(31 downto 0) => axi_interconnect_0_M01_AXI_AWADDR(31 downto 0),
M01_AXI_awprot(2 downto 0) => axi_interconnect_0_M01_AXI_AWPROT(2 downto 0),
M01_AXI_awready => axi_interconnect_0_M01_AXI_AWREADY,
M01_AXI_awvalid => axi_interconnect_0_M01_AXI_AWVALID,
M01_AXI_bready => axi_interconnect_0_M01_AXI_BREADY,
M01_AXI_bresp(1 downto 0) => axi_interconnect_0_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid => axi_interconnect_0_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => axi_interconnect_0_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready => axi_interconnect_0_M01_AXI_RREADY,
M01_AXI_rresp(1 downto 0) => axi_interconnect_0_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid => axi_interconnect_0_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => axi_interconnect_0_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready => axi_interconnect_0_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => axi_interconnect_0_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid => axi_interconnect_0_M01_AXI_WVALID,
M02_ACLK => clk_wiz_0_clk_out1,
M02_ARESETN => clk_wiz_0_locked,
M02_AXI_araddr(31 downto 0) => axi_interconnect_0_M02_AXI_ARADDR(31 downto 0),
M02_AXI_arprot(2 downto 0) => axi_interconnect_0_M02_AXI_ARPROT(2 downto 0),
M02_AXI_arready => axi_interconnect_0_M02_AXI_ARREADY,
M02_AXI_arvalid => axi_interconnect_0_M02_AXI_ARVALID,
M02_AXI_awaddr(31 downto 0) => axi_interconnect_0_M02_AXI_AWADDR(31 downto 0),
M02_AXI_awprot(2 downto 0) => axi_interconnect_0_M02_AXI_AWPROT(2 downto 0),
M02_AXI_awready => axi_interconnect_0_M02_AXI_AWREADY,
M02_AXI_awvalid => axi_interconnect_0_M02_AXI_AWVALID,
M02_AXI_bready => axi_interconnect_0_M02_AXI_BREADY,
M02_AXI_bresp(1 downto 0) => axi_interconnect_0_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid => axi_interconnect_0_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => axi_interconnect_0_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready => axi_interconnect_0_M02_AXI_RREADY,
M02_AXI_rresp(1 downto 0) => axi_interconnect_0_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid => axi_interconnect_0_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => axi_interconnect_0_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready => axi_interconnect_0_M02_AXI_WREADY,
M02_AXI_wstrb(3 downto 0) => axi_interconnect_0_M02_AXI_WSTRB(3 downto 0),
M02_AXI_wvalid => axi_interconnect_0_M02_AXI_WVALID,
M03_ACLK => clk_wiz_0_clk_out1,
M03_ARESETN => clk_wiz_0_locked,
M03_AXI_araddr(31 downto 0) => axi_interconnect_0_M03_AXI_ARADDR(31 downto 0),
M03_AXI_arprot(2 downto 0) => axi_interconnect_0_M03_AXI_ARPROT(2 downto 0),
M03_AXI_arready => axi_interconnect_0_M03_AXI_ARREADY,
M03_AXI_arvalid => axi_interconnect_0_M03_AXI_ARVALID,
M03_AXI_awaddr(31 downto 0) => axi_interconnect_0_M03_AXI_AWADDR(31 downto 0),
M03_AXI_awprot(2 downto 0) => axi_interconnect_0_M03_AXI_AWPROT(2 downto 0),
M03_AXI_awready => axi_interconnect_0_M03_AXI_AWREADY,
M03_AXI_awvalid => axi_interconnect_0_M03_AXI_AWVALID,
M03_AXI_bready => axi_interconnect_0_M03_AXI_BREADY,
M03_AXI_bresp(1 downto 0) => axi_interconnect_0_M03_AXI_BRESP(1 downto 0),
M03_AXI_bvalid => axi_interconnect_0_M03_AXI_BVALID,
M03_AXI_rdata(31 downto 0) => axi_interconnect_0_M03_AXI_RDATA(31 downto 0),
M03_AXI_rready => axi_interconnect_0_M03_AXI_RREADY,
M03_AXI_rresp(1 downto 0) => axi_interconnect_0_M03_AXI_RRESP(1 downto 0),
M03_AXI_rvalid => axi_interconnect_0_M03_AXI_RVALID,
M03_AXI_wdata(31 downto 0) => axi_interconnect_0_M03_AXI_WDATA(31 downto 0),
M03_AXI_wready => axi_interconnect_0_M03_AXI_WREADY,
M03_AXI_wstrb(3 downto 0) => axi_interconnect_0_M03_AXI_WSTRB(3 downto 0),
M03_AXI_wvalid => axi_interconnect_0_M03_AXI_WVALID,
M04_ACLK => clk_wiz_0_clk_out1,
M04_ARESETN => clk_wiz_0_locked,
M04_AXI_araddr(31 downto 0) => axi_interconnect_0_M04_AXI_ARADDR(31 downto 0),
M04_AXI_arready => axi_interconnect_0_M04_AXI_ARREADY,
M04_AXI_arvalid => axi_interconnect_0_M04_AXI_ARVALID,
M04_AXI_awaddr(31 downto 0) => axi_interconnect_0_M04_AXI_AWADDR(31 downto 0),
M04_AXI_awready => axi_interconnect_0_M04_AXI_AWREADY,
M04_AXI_awvalid => axi_interconnect_0_M04_AXI_AWVALID,
M04_AXI_bready => axi_interconnect_0_M04_AXI_BREADY,
M04_AXI_bresp(1 downto 0) => axi_interconnect_0_M04_AXI_BRESP(1 downto 0),
M04_AXI_bvalid => axi_interconnect_0_M04_AXI_BVALID,
M04_AXI_rdata(31 downto 0) => axi_interconnect_0_M04_AXI_RDATA(31 downto 0),
M04_AXI_rready => axi_interconnect_0_M04_AXI_RREADY,
M04_AXI_rresp(1 downto 0) => axi_interconnect_0_M04_AXI_RRESP(1 downto 0),
M04_AXI_rvalid => axi_interconnect_0_M04_AXI_RVALID,
M04_AXI_wdata(31 downto 0) => axi_interconnect_0_M04_AXI_WDATA(31 downto 0),
M04_AXI_wready => axi_interconnect_0_M04_AXI_WREADY,
M04_AXI_wstrb(3 downto 0) => axi_interconnect_0_M04_AXI_WSTRB(3 downto 0),
M04_AXI_wvalid => axi_interconnect_0_M04_AXI_WVALID,
M05_ACLK => clk_wiz_0_clk_out1,
M05_ARESETN => clk_wiz_0_locked,
M05_AXI_araddr(31 downto 0) => axi_interconnect_0_M05_AXI_ARADDR(31 downto 0),
M05_AXI_arready => axi_interconnect_0_M05_AXI_ARREADY,
M05_AXI_arvalid => axi_interconnect_0_M05_AXI_ARVALID,
M05_AXI_awaddr(31 downto 0) => axi_interconnect_0_M05_AXI_AWADDR(31 downto 0),
M05_AXI_awready => axi_interconnect_0_M05_AXI_AWREADY,
M05_AXI_awvalid => axi_interconnect_0_M05_AXI_AWVALID,
M05_AXI_bready => axi_interconnect_0_M05_AXI_BREADY,
M05_AXI_bresp(1 downto 0) => axi_interconnect_0_M05_AXI_BRESP(1 downto 0),
M05_AXI_bvalid => axi_interconnect_0_M05_AXI_BVALID,
M05_AXI_rdata(31 downto 0) => axi_interconnect_0_M05_AXI_RDATA(31 downto 0),
M05_AXI_rready => axi_interconnect_0_M05_AXI_RREADY,
M05_AXI_rresp(1 downto 0) => axi_interconnect_0_M05_AXI_RRESP(1 downto 0),
M05_AXI_rvalid => axi_interconnect_0_M05_AXI_RVALID,
M05_AXI_wdata(31 downto 0) => axi_interconnect_0_M05_AXI_WDATA(31 downto 0),
M05_AXI_wready => axi_interconnect_0_M05_AXI_WREADY,
M05_AXI_wstrb(3 downto 0) => axi_interconnect_0_M05_AXI_WSTRB(3 downto 0),
M05_AXI_wvalid => axi_interconnect_0_M05_AXI_WVALID,
M06_ACLK => clk_wiz_0_clk_out1,
M06_ARESETN => clk_wiz_0_locked,
M06_AXI_araddr(31 downto 0) => axi_interconnect_0_M06_AXI_ARADDR(31 downto 0),
M06_AXI_arready => axi_interconnect_0_M06_AXI_ARREADY,
M06_AXI_arvalid => axi_interconnect_0_M06_AXI_ARVALID,
M06_AXI_awaddr(31 downto 0) => axi_interconnect_0_M06_AXI_AWADDR(31 downto 0),
M06_AXI_awready => axi_interconnect_0_M06_AXI_AWREADY,
M06_AXI_awvalid => axi_interconnect_0_M06_AXI_AWVALID,
M06_AXI_bready => axi_interconnect_0_M06_AXI_BREADY,
M06_AXI_bresp(1 downto 0) => axi_interconnect_0_M06_AXI_BRESP(1 downto 0),
M06_AXI_bvalid => axi_interconnect_0_M06_AXI_BVALID,
M06_AXI_rdata(31 downto 0) => axi_interconnect_0_M06_AXI_RDATA(31 downto 0),
M06_AXI_rready => axi_interconnect_0_M06_AXI_RREADY,
M06_AXI_rresp(1 downto 0) => axi_interconnect_0_M06_AXI_RRESP(1 downto 0),
M06_AXI_rvalid => axi_interconnect_0_M06_AXI_RVALID,
M06_AXI_wdata(31 downto 0) => axi_interconnect_0_M06_AXI_WDATA(31 downto 0),
M06_AXI_wready => axi_interconnect_0_M06_AXI_WREADY,
M06_AXI_wstrb(3 downto 0) => axi_interconnect_0_M06_AXI_WSTRB(3 downto 0),
M06_AXI_wvalid => axi_interconnect_0_M06_AXI_WVALID,
S00_ACLK => clk_wiz_0_clk_out1,
S00_ARESETN => clk_wiz_0_locked,
S00_AXI_araddr(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_ARADDR(31 downto 0),
S00_AXI_arprot(2 downto 0) => internoc_ni_axi_master_0_M00_AXI_ARPROT(2 downto 0),
S00_AXI_arready => internoc_ni_axi_master_0_M00_AXI_ARREADY,
S00_AXI_arvalid => internoc_ni_axi_master_0_M00_AXI_ARVALID,
S00_AXI_awaddr(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_AWADDR(31 downto 0),
S00_AXI_awprot(2 downto 0) => internoc_ni_axi_master_0_M00_AXI_AWPROT(2 downto 0),
S00_AXI_awready => internoc_ni_axi_master_0_M00_AXI_AWREADY,
S00_AXI_awvalid => internoc_ni_axi_master_0_M00_AXI_AWVALID,
S00_AXI_bready => internoc_ni_axi_master_0_M00_AXI_BREADY,
S00_AXI_bresp(1 downto 0) => internoc_ni_axi_master_0_M00_AXI_BRESP(1 downto 0),
S00_AXI_bvalid => internoc_ni_axi_master_0_M00_AXI_BVALID,
S00_AXI_rdata(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_RDATA(31 downto 0),
S00_AXI_rready => internoc_ni_axi_master_0_M00_AXI_RREADY,
S00_AXI_rresp(1 downto 0) => internoc_ni_axi_master_0_M00_AXI_RRESP(1 downto 0),
S00_AXI_rvalid => internoc_ni_axi_master_0_M00_AXI_RVALID,
S00_AXI_wdata(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_WDATA(31 downto 0),
S00_AXI_wready => internoc_ni_axi_master_0_M00_AXI_WREADY,
S00_AXI_wstrb(3 downto 0) => internoc_ni_axi_master_0_M00_AXI_WSTRB(3 downto 0),
S00_AXI_wvalid => internoc_ni_axi_master_0_M00_AXI_WVALID,
S01_ACLK => clk_wiz_0_clk_out1,
S01_ARESETN => clk_wiz_0_locked,
S01_AXI_araddr(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_ARADDR(31 downto 0),
S01_AXI_arprot(2 downto 0) => internoc_ni_axi_master_1_M00_AXI_ARPROT(2 downto 0),
S01_AXI_arready => internoc_ni_axi_master_1_M00_AXI_ARREADY,
S01_AXI_arvalid => internoc_ni_axi_master_1_M00_AXI_ARVALID,
S01_AXI_awaddr(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_AWADDR(31 downto 0),
S01_AXI_awprot(2 downto 0) => internoc_ni_axi_master_1_M00_AXI_AWPROT(2 downto 0),
S01_AXI_awready => internoc_ni_axi_master_1_M00_AXI_AWREADY,
S01_AXI_awvalid => internoc_ni_axi_master_1_M00_AXI_AWVALID,
S01_AXI_bready => internoc_ni_axi_master_1_M00_AXI_BREADY,
S01_AXI_bresp(1 downto 0) => internoc_ni_axi_master_1_M00_AXI_BRESP(1 downto 0),
S01_AXI_bvalid => internoc_ni_axi_master_1_M00_AXI_BVALID,
S01_AXI_rdata(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_RDATA(31 downto 0),
S01_AXI_rready => internoc_ni_axi_master_1_M00_AXI_RREADY,
S01_AXI_rresp(1 downto 0) => internoc_ni_axi_master_1_M00_AXI_RRESP(1 downto 0),
S01_AXI_rvalid => internoc_ni_axi_master_1_M00_AXI_RVALID,
S01_AXI_wdata(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_WDATA(31 downto 0),
S01_AXI_wready => internoc_ni_axi_master_1_M00_AXI_WREADY,
S01_AXI_wstrb(3 downto 0) => internoc_ni_axi_master_1_M00_AXI_WSTRB(3 downto 0),
S01_AXI_wvalid => internoc_ni_axi_master_1_M00_AXI_WVALID,
S02_ACLK => clk_wiz_0_clk_out1,
S02_ARESETN => clk_wiz_0_locked,
S02_AXI_araddr(31 downto 0) => jtag_axi_0_M_AXI_ARADDR(31 downto 0),
S02_AXI_arburst(1 downto 0) => jtag_axi_0_M_AXI_ARBURST(1 downto 0),
S02_AXI_arcache(3 downto 0) => jtag_axi_0_M_AXI_ARCACHE(3 downto 0),
S02_AXI_arid(0) => jtag_axi_0_M_AXI_ARID(0),
S02_AXI_arlen(7 downto 0) => jtag_axi_0_M_AXI_ARLEN(7 downto 0),
S02_AXI_arlock => jtag_axi_0_M_AXI_ARLOCK,
S02_AXI_arprot(2 downto 0) => jtag_axi_0_M_AXI_ARPROT(2 downto 0),
S02_AXI_arqos(3 downto 0) => jtag_axi_0_M_AXI_ARQOS(3 downto 0),
S02_AXI_arready => jtag_axi_0_M_AXI_ARREADY,
S02_AXI_arsize(2 downto 0) => jtag_axi_0_M_AXI_ARSIZE(2 downto 0),
S02_AXI_arvalid => jtag_axi_0_M_AXI_ARVALID,
S02_AXI_awaddr(31 downto 0) => jtag_axi_0_M_AXI_AWADDR(31 downto 0),
S02_AXI_awburst(1 downto 0) => jtag_axi_0_M_AXI_AWBURST(1 downto 0),
S02_AXI_awcache(3 downto 0) => jtag_axi_0_M_AXI_AWCACHE(3 downto 0),
S02_AXI_awid(0) => jtag_axi_0_M_AXI_AWID(0),
S02_AXI_awlen(7 downto 0) => jtag_axi_0_M_AXI_AWLEN(7 downto 0),
S02_AXI_awlock => jtag_axi_0_M_AXI_AWLOCK,
S02_AXI_awprot(2 downto 0) => jtag_axi_0_M_AXI_AWPROT(2 downto 0),
S02_AXI_awqos(3 downto 0) => jtag_axi_0_M_AXI_AWQOS(3 downto 0),
S02_AXI_awready => jtag_axi_0_M_AXI_AWREADY,
S02_AXI_awsize(2 downto 0) => jtag_axi_0_M_AXI_AWSIZE(2 downto 0),
S02_AXI_awvalid => jtag_axi_0_M_AXI_AWVALID,
S02_AXI_bid(0) => jtag_axi_0_M_AXI_BID(0),
S02_AXI_bready => jtag_axi_0_M_AXI_BREADY,
S02_AXI_bresp(1 downto 0) => jtag_axi_0_M_AXI_BRESP(1 downto 0),
S02_AXI_bvalid => jtag_axi_0_M_AXI_BVALID,
S02_AXI_rdata(31 downto 0) => jtag_axi_0_M_AXI_RDATA(31 downto 0),
S02_AXI_rid(0) => jtag_axi_0_M_AXI_RID(0),
S02_AXI_rlast => jtag_axi_0_M_AXI_RLAST,
S02_AXI_rready => jtag_axi_0_M_AXI_RREADY,
S02_AXI_rresp(1 downto 0) => jtag_axi_0_M_AXI_RRESP(1 downto 0),
S02_AXI_rvalid => jtag_axi_0_M_AXI_RVALID,
S02_AXI_wdata(31 downto 0) => jtag_axi_0_M_AXI_WDATA(31 downto 0),
S02_AXI_wlast => jtag_axi_0_M_AXI_WLAST,
S02_AXI_wready => jtag_axi_0_M_AXI_WREADY,
S02_AXI_wstrb(3 downto 0) => jtag_axi_0_M_AXI_WSTRB(3 downto 0),
S02_AXI_wvalid => jtag_axi_0_M_AXI_WVALID
);
internoc_ni_axi_master_0: component DemoInterconnect_internoc_ni_axi_master_0_0
port map (
if00_data_in(7 downto 0) => uart_transceiver_0_o_RX_Byte(7 downto 0),
if00_data_out(7 downto 0) => interface_axi_master_0_if00_data_out(7 downto 0),
if00_load_in => uart_transceiver_0_o_RX_Done,
if00_load_out => interface_axi_master_0_if00_load_out,
if00_send_busy => uart_transceiver_0_o_TX_Active,
if00_send_done => uart_transceiver_0_o_TX_Done,
m00_axi_aclk => clk_wiz_0_clk_out1,
m00_axi_araddr(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_ARADDR(31 downto 0),
m00_axi_aresetn => clk_wiz_0_locked,
m00_axi_arprot(2 downto 0) => internoc_ni_axi_master_0_M00_AXI_ARPROT(2 downto 0),
m00_axi_arready => internoc_ni_axi_master_0_M00_AXI_ARREADY,
m00_axi_arvalid => internoc_ni_axi_master_0_M00_AXI_ARVALID,
m00_axi_awaddr(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_AWADDR(31 downto 0),
m00_axi_awprot(2 downto 0) => internoc_ni_axi_master_0_M00_AXI_AWPROT(2 downto 0),
m00_axi_awready => internoc_ni_axi_master_0_M00_AXI_AWREADY,
m00_axi_awvalid => internoc_ni_axi_master_0_M00_AXI_AWVALID,
m00_axi_bready => internoc_ni_axi_master_0_M00_AXI_BREADY,
m00_axi_bresp(1 downto 0) => internoc_ni_axi_master_0_M00_AXI_BRESP(1 downto 0),
m00_axi_bvalid => internoc_ni_axi_master_0_M00_AXI_BVALID,
m00_axi_rdata(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_RDATA(31 downto 0),
m00_axi_rready => internoc_ni_axi_master_0_M00_AXI_RREADY,
m00_axi_rresp(1 downto 0) => internoc_ni_axi_master_0_M00_AXI_RRESP(1 downto 0),
m00_axi_rvalid => internoc_ni_axi_master_0_M00_AXI_RVALID,
m00_axi_wdata(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_WDATA(31 downto 0),
m00_axi_wready => internoc_ni_axi_master_0_M00_AXI_WREADY,
m00_axi_wstrb(3 downto 0) => internoc_ni_axi_master_0_M00_AXI_WSTRB(3 downto 0),
m00_axi_wvalid => internoc_ni_axi_master_0_M00_AXI_WVALID
);
internoc_ni_axi_master_1: component DemoInterconnect_internoc_ni_axi_master_1_0
port map (
if00_data_in(7 downto 0) => uart_transceiver_1_o_RX_Byte(7 downto 0),
if00_data_out(7 downto 0) => internoc_ni_axi_master_1_if00_data_out(7 downto 0),
if00_load_in => uart_transceiver_1_o_RX_Done,
if00_load_out => internoc_ni_axi_master_1_if00_load_out,
if00_send_busy => uart_transceiver_1_o_TX_Active,
if00_send_done => uart_transceiver_1_o_TX_Done,
m00_axi_aclk => clk_wiz_0_clk_out1,
m00_axi_araddr(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_ARADDR(31 downto 0),
m00_axi_aresetn => clk_wiz_0_locked,
m00_axi_arprot(2 downto 0) => internoc_ni_axi_master_1_M00_AXI_ARPROT(2 downto 0),
m00_axi_arready => internoc_ni_axi_master_1_M00_AXI_ARREADY,
m00_axi_arvalid => internoc_ni_axi_master_1_M00_AXI_ARVALID,
m00_axi_awaddr(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_AWADDR(31 downto 0),
m00_axi_awprot(2 downto 0) => internoc_ni_axi_master_1_M00_AXI_AWPROT(2 downto 0),
m00_axi_awready => internoc_ni_axi_master_1_M00_AXI_AWREADY,
m00_axi_awvalid => internoc_ni_axi_master_1_M00_AXI_AWVALID,
m00_axi_bready => internoc_ni_axi_master_1_M00_AXI_BREADY,
m00_axi_bresp(1 downto 0) => internoc_ni_axi_master_1_M00_AXI_BRESP(1 downto 0),
m00_axi_bvalid => internoc_ni_axi_master_1_M00_AXI_BVALID,
m00_axi_rdata(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_RDATA(31 downto 0),
m00_axi_rready => internoc_ni_axi_master_1_M00_AXI_RREADY,
m00_axi_rresp(1 downto 0) => internoc_ni_axi_master_1_M00_AXI_RRESP(1 downto 0),
m00_axi_rvalid => internoc_ni_axi_master_1_M00_AXI_RVALID,
m00_axi_wdata(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_WDATA(31 downto 0),
m00_axi_wready => internoc_ni_axi_master_1_M00_AXI_WREADY,
m00_axi_wstrb(3 downto 0) => internoc_ni_axi_master_1_M00_AXI_WSTRB(3 downto 0),
m00_axi_wvalid => internoc_ni_axi_master_1_M00_AXI_WVALID
);
jtag_axi_0: component DemoInterconnect_jtag_axi_0_0
port map (
aclk => clk_wiz_0_clk_out1,
aresetn => clk_wiz_0_locked,
m_axi_araddr(31 downto 0) => jtag_axi_0_M_AXI_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => jtag_axi_0_M_AXI_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => jtag_axi_0_M_AXI_ARCACHE(3 downto 0),
m_axi_arid(0) => jtag_axi_0_M_AXI_ARID(0),
m_axi_arlen(7 downto 0) => jtag_axi_0_M_AXI_ARLEN(7 downto 0),
m_axi_arlock => jtag_axi_0_M_AXI_ARLOCK,
m_axi_arprot(2 downto 0) => jtag_axi_0_M_AXI_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => jtag_axi_0_M_AXI_ARQOS(3 downto 0),
m_axi_arready => jtag_axi_0_M_AXI_ARREADY,
m_axi_arsize(2 downto 0) => jtag_axi_0_M_AXI_ARSIZE(2 downto 0),
m_axi_arvalid => jtag_axi_0_M_AXI_ARVALID,
m_axi_awaddr(31 downto 0) => jtag_axi_0_M_AXI_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => jtag_axi_0_M_AXI_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => jtag_axi_0_M_AXI_AWCACHE(3 downto 0),
m_axi_awid(0) => jtag_axi_0_M_AXI_AWID(0),
m_axi_awlen(7 downto 0) => jtag_axi_0_M_AXI_AWLEN(7 downto 0),
m_axi_awlock => jtag_axi_0_M_AXI_AWLOCK,
m_axi_awprot(2 downto 0) => jtag_axi_0_M_AXI_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => jtag_axi_0_M_AXI_AWQOS(3 downto 0),
m_axi_awready => jtag_axi_0_M_AXI_AWREADY,
m_axi_awsize(2 downto 0) => jtag_axi_0_M_AXI_AWSIZE(2 downto 0),
m_axi_awvalid => jtag_axi_0_M_AXI_AWVALID,
m_axi_bid(0) => jtag_axi_0_M_AXI_BID(0),
m_axi_bready => jtag_axi_0_M_AXI_BREADY,
m_axi_bresp(1 downto 0) => jtag_axi_0_M_AXI_BRESP(1 downto 0),
m_axi_bvalid => jtag_axi_0_M_AXI_BVALID,
m_axi_rdata(31 downto 0) => jtag_axi_0_M_AXI_RDATA(31 downto 0),
m_axi_rid(0) => jtag_axi_0_M_AXI_RID(0),
m_axi_rlast => jtag_axi_0_M_AXI_RLAST,
m_axi_rready => jtag_axi_0_M_AXI_RREADY,
m_axi_rresp(1 downto 0) => jtag_axi_0_M_AXI_RRESP(1 downto 0),
m_axi_rvalid => jtag_axi_0_M_AXI_RVALID,
m_axi_wdata(31 downto 0) => jtag_axi_0_M_AXI_WDATA(31 downto 0),
m_axi_wlast => jtag_axi_0_M_AXI_WLAST,
m_axi_wready => jtag_axi_0_M_AXI_WREADY,
m_axi_wstrb(3 downto 0) => jtag_axi_0_M_AXI_WSTRB(3 downto 0),
m_axi_wvalid => jtag_axi_0_M_AXI_WVALID
);
master_comm_mutex: component DemoInterconnect_mutex_0_0
port map (
S0_AXI_ACLK => clk_wiz_0_clk_out1,
S0_AXI_ARADDR(31 downto 0) => axi_interconnect_0_M04_AXI_ARADDR(31 downto 0),
S0_AXI_ARESETN => clk_wiz_0_locked,
S0_AXI_ARREADY => axi_interconnect_0_M04_AXI_ARREADY,
S0_AXI_ARVALID => axi_interconnect_0_M04_AXI_ARVALID,
S0_AXI_AWADDR(31 downto 0) => axi_interconnect_0_M04_AXI_AWADDR(31 downto 0),
S0_AXI_AWREADY => axi_interconnect_0_M04_AXI_AWREADY,
S0_AXI_AWVALID => axi_interconnect_0_M04_AXI_AWVALID,
S0_AXI_BREADY => axi_interconnect_0_M04_AXI_BREADY,
S0_AXI_BRESP(1 downto 0) => axi_interconnect_0_M04_AXI_BRESP(1 downto 0),
S0_AXI_BVALID => axi_interconnect_0_M04_AXI_BVALID,
S0_AXI_RDATA(31 downto 0) => axi_interconnect_0_M04_AXI_RDATA(31 downto 0),
S0_AXI_RREADY => axi_interconnect_0_M04_AXI_RREADY,
S0_AXI_RRESP(1 downto 0) => axi_interconnect_0_M04_AXI_RRESP(1 downto 0),
S0_AXI_RVALID => axi_interconnect_0_M04_AXI_RVALID,
S0_AXI_WDATA(31 downto 0) => axi_interconnect_0_M04_AXI_WDATA(31 downto 0),
S0_AXI_WREADY => axi_interconnect_0_M04_AXI_WREADY,
S0_AXI_WSTRB(3 downto 0) => axi_interconnect_0_M04_AXI_WSTRB(3 downto 0),
S0_AXI_WVALID => axi_interconnect_0_M04_AXI_WVALID,
S1_AXI_ACLK => clk_wiz_0_clk_out1,
S1_AXI_ARADDR(31 downto 0) => axi_interconnect_0_M05_AXI_ARADDR(31 downto 0),
S1_AXI_ARESETN => clk_wiz_0_locked,
S1_AXI_ARREADY => axi_interconnect_0_M05_AXI_ARREADY,
S1_AXI_ARVALID => axi_interconnect_0_M05_AXI_ARVALID,
S1_AXI_AWADDR(31 downto 0) => axi_interconnect_0_M05_AXI_AWADDR(31 downto 0),
S1_AXI_AWREADY => axi_interconnect_0_M05_AXI_AWREADY,
S1_AXI_AWVALID => axi_interconnect_0_M05_AXI_AWVALID,
S1_AXI_BREADY => axi_interconnect_0_M05_AXI_BREADY,
S1_AXI_BRESP(1 downto 0) => axi_interconnect_0_M05_AXI_BRESP(1 downto 0),
S1_AXI_BVALID => axi_interconnect_0_M05_AXI_BVALID,
S1_AXI_RDATA(31 downto 0) => axi_interconnect_0_M05_AXI_RDATA(31 downto 0),
S1_AXI_RREADY => axi_interconnect_0_M05_AXI_RREADY,
S1_AXI_RRESP(1 downto 0) => axi_interconnect_0_M05_AXI_RRESP(1 downto 0),
S1_AXI_RVALID => axi_interconnect_0_M05_AXI_RVALID,
S1_AXI_WDATA(31 downto 0) => axi_interconnect_0_M05_AXI_WDATA(31 downto 0),
S1_AXI_WREADY => axi_interconnect_0_M05_AXI_WREADY,
S1_AXI_WSTRB(3 downto 0) => axi_interconnect_0_M05_AXI_WSTRB(3 downto 0),
S1_AXI_WVALID => axi_interconnect_0_M05_AXI_WVALID,
S2_AXI_ACLK => clk_wiz_0_clk_out1,
S2_AXI_ARADDR(31 downto 0) => axi_interconnect_0_M06_AXI_ARADDR(31 downto 0),
S2_AXI_ARESETN => clk_wiz_0_locked,
S2_AXI_ARREADY => axi_interconnect_0_M06_AXI_ARREADY,
S2_AXI_ARVALID => axi_interconnect_0_M06_AXI_ARVALID,
S2_AXI_AWADDR(31 downto 0) => axi_interconnect_0_M06_AXI_AWADDR(31 downto 0),
S2_AXI_AWREADY => axi_interconnect_0_M06_AXI_AWREADY,
S2_AXI_AWVALID => axi_interconnect_0_M06_AXI_AWVALID,
S2_AXI_BREADY => axi_interconnect_0_M06_AXI_BREADY,
S2_AXI_BRESP(1 downto 0) => axi_interconnect_0_M06_AXI_BRESP(1 downto 0),
S2_AXI_BVALID => axi_interconnect_0_M06_AXI_BVALID,
S2_AXI_RDATA(31 downto 0) => axi_interconnect_0_M06_AXI_RDATA(31 downto 0),
S2_AXI_RREADY => axi_interconnect_0_M06_AXI_RREADY,
S2_AXI_RRESP(1 downto 0) => axi_interconnect_0_M06_AXI_RRESP(1 downto 0),
S2_AXI_RVALID => axi_interconnect_0_M06_AXI_RVALID,
S2_AXI_WDATA(31 downto 0) => axi_interconnect_0_M06_AXI_WDATA(31 downto 0),
S2_AXI_WREADY => axi_interconnect_0_M06_AXI_WREADY,
S2_AXI_WSTRB(3 downto 0) => axi_interconnect_0_M06_AXI_WSTRB(3 downto 0),
S2_AXI_WVALID => axi_interconnect_0_M06_AXI_WVALID
);
uart_transceiver_0: component DemoInterconnect_uart_transceiver_0_0
port map (
i_Clk => clk_wiz_0_uart,
i_RX_Serial => UART_RX_0_1,
i_TX_Byte(7 downto 0) => interface_axi_master_0_if00_data_out(7 downto 0),
i_TX_Load => interface_axi_master_0_if00_load_out,
o_RX_Byte(7 downto 0) => uart_transceiver_0_o_RX_Byte(7 downto 0),
o_RX_Done => uart_transceiver_0_o_RX_Done,
o_TX_Active => uart_transceiver_0_o_TX_Active,
o_TX_Done => uart_transceiver_0_o_TX_Done,
o_TX_Serial => uart_transceiver_0_o_TX_Serial
);
uart_transceiver_1: component DemoInterconnect_uart_transceiver_0_1
port map (
i_Clk => clk_wiz_0_uart,
i_RX_Serial => UART_RX_1_1,
i_TX_Byte(7 downto 0) => internoc_ni_axi_master_1_if00_data_out(7 downto 0),
i_TX_Load => internoc_ni_axi_master_1_if00_load_out,
o_RX_Byte(7 downto 0) => uart_transceiver_1_o_RX_Byte(7 downto 0),
o_RX_Done => uart_transceiver_1_o_RX_Done,
o_TX_Active => uart_transceiver_1_o_TX_Active,
o_TX_Done => uart_transceiver_1_o_TX_Done,
o_TX_Serial => uart_transceiver_1_o_TX_Serial
);
end STRUCTURE;
|
--Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct 4 19:58:22 MDT 2017
--Date : Fri Nov 17 16:04:47 2017
--Host : egk-pc running 64-bit major release (build 9200)
--Command : generate_target DemoInterconnect.bd
--Design : DemoInterconnect
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_4EB6IN is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_4EB6IN;
architecture STRUCTURE of m00_couplers_imp_4EB6IN is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m00_couplers_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m00_couplers_to_m00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m00_couplers_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m00_couplers_to_m00_couplers_AWVALID;
M_AXI_bready <= m00_couplers_to_m00_couplers_BREADY;
M_AXI_rready <= m00_couplers_to_m00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m00_couplers_to_m00_couplers_WVALID;
S_AXI_arready <= m00_couplers_to_m00_couplers_ARREADY;
S_AXI_awready <= m00_couplers_to_m00_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_m00_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_m00_couplers_RVALID;
S_AXI_wready <= m00_couplers_to_m00_couplers_WREADY;
m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_m00_couplers_ARREADY <= M_AXI_arready;
m00_couplers_to_m00_couplers_ARVALID <= S_AXI_arvalid;
m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_m00_couplers_AWREADY <= M_AXI_awready;
m00_couplers_to_m00_couplers_AWVALID <= S_AXI_awvalid;
m00_couplers_to_m00_couplers_BREADY <= S_AXI_bready;
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID <= M_AXI_bvalid;
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY <= S_AXI_rready;
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID <= M_AXI_rvalid;
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_1SL2GIW is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m01_couplers_imp_1SL2GIW;
architecture STRUCTURE of m01_couplers_imp_1SL2GIW is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m01_couplers_to_m01_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m01_couplers_to_m01_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m01_couplers_to_m01_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m01_couplers_to_m01_couplers_AWVALID;
M_AXI_bready <= m01_couplers_to_m01_couplers_BREADY;
M_AXI_rready <= m01_couplers_to_m01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m01_couplers_to_m01_couplers_WVALID;
S_AXI_arready <= m01_couplers_to_m01_couplers_ARREADY;
S_AXI_awready <= m01_couplers_to_m01_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m01_couplers_to_m01_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m01_couplers_to_m01_couplers_RVALID;
S_AXI_wready <= m01_couplers_to_m01_couplers_WREADY;
m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m01_couplers_to_m01_couplers_ARREADY <= M_AXI_arready;
m01_couplers_to_m01_couplers_ARVALID <= S_AXI_arvalid;
m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m01_couplers_to_m01_couplers_AWREADY <= M_AXI_awready;
m01_couplers_to_m01_couplers_AWVALID <= S_AXI_awvalid;
m01_couplers_to_m01_couplers_BREADY <= S_AXI_bready;
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID <= M_AXI_bvalid;
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY <= S_AXI_rready;
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID <= M_AXI_rvalid;
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY <= M_AXI_wready;
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_7DG2C0 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m02_couplers_imp_7DG2C0;
architecture STRUCTURE of m02_couplers_imp_7DG2C0 is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m02_couplers_to_m02_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m02_couplers_to_m02_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m02_couplers_to_m02_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m02_couplers_to_m02_couplers_AWVALID;
M_AXI_bready <= m02_couplers_to_m02_couplers_BREADY;
M_AXI_rready <= m02_couplers_to_m02_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m02_couplers_to_m02_couplers_WVALID;
S_AXI_arready <= m02_couplers_to_m02_couplers_ARREADY;
S_AXI_awready <= m02_couplers_to_m02_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m02_couplers_to_m02_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m02_couplers_to_m02_couplers_RVALID;
S_AXI_wready <= m02_couplers_to_m02_couplers_WREADY;
m02_couplers_to_m02_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m02_couplers_to_m02_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m02_couplers_to_m02_couplers_ARREADY <= M_AXI_arready;
m02_couplers_to_m02_couplers_ARVALID <= S_AXI_arvalid;
m02_couplers_to_m02_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m02_couplers_to_m02_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m02_couplers_to_m02_couplers_AWREADY <= M_AXI_awready;
m02_couplers_to_m02_couplers_AWVALID <= S_AXI_awvalid;
m02_couplers_to_m02_couplers_BREADY <= S_AXI_bready;
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID <= M_AXI_bvalid;
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY <= S_AXI_rready;
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID <= M_AXI_rvalid;
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY <= M_AXI_wready;
m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m02_couplers_to_m02_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m03_couplers_imp_1YCPS1Z is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m03_couplers_imp_1YCPS1Z;
architecture STRUCTURE of m03_couplers_imp_1YCPS1Z is
signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m03_couplers_to_m03_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m03_couplers_to_m03_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m03_couplers_to_m03_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m03_couplers_to_m03_couplers_AWVALID;
M_AXI_bready <= m03_couplers_to_m03_couplers_BREADY;
M_AXI_rready <= m03_couplers_to_m03_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m03_couplers_to_m03_couplers_WVALID;
S_AXI_arready <= m03_couplers_to_m03_couplers_ARREADY;
S_AXI_awready <= m03_couplers_to_m03_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m03_couplers_to_m03_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m03_couplers_to_m03_couplers_RVALID;
S_AXI_wready <= m03_couplers_to_m03_couplers_WREADY;
m03_couplers_to_m03_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m03_couplers_to_m03_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m03_couplers_to_m03_couplers_ARREADY <= M_AXI_arready;
m03_couplers_to_m03_couplers_ARVALID <= S_AXI_arvalid;
m03_couplers_to_m03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m03_couplers_to_m03_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m03_couplers_to_m03_couplers_AWREADY <= M_AXI_awready;
m03_couplers_to_m03_couplers_AWVALID <= S_AXI_awvalid;
m03_couplers_to_m03_couplers_BREADY <= S_AXI_bready;
m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m03_couplers_to_m03_couplers_BVALID <= M_AXI_bvalid;
m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m03_couplers_to_m03_couplers_RREADY <= S_AXI_rready;
m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m03_couplers_to_m03_couplers_RVALID <= M_AXI_rvalid;
m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m03_couplers_to_m03_couplers_WREADY <= M_AXI_wready;
m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m03_couplers_to_m03_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m04_couplers_imp_ACM7VL is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m04_couplers_imp_ACM7VL;
architecture STRUCTURE of m04_couplers_imp_ACM7VL is
signal m04_couplers_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_ARREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_ARVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_AWREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_BVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_RREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_RVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_WREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_m04_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m04_couplers_to_m04_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m04_couplers_to_m04_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m04_couplers_to_m04_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m04_couplers_to_m04_couplers_AWVALID;
M_AXI_bready <= m04_couplers_to_m04_couplers_BREADY;
M_AXI_rready <= m04_couplers_to_m04_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m04_couplers_to_m04_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m04_couplers_to_m04_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m04_couplers_to_m04_couplers_WVALID;
S_AXI_arready <= m04_couplers_to_m04_couplers_ARREADY;
S_AXI_awready <= m04_couplers_to_m04_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m04_couplers_to_m04_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m04_couplers_to_m04_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m04_couplers_to_m04_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m04_couplers_to_m04_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m04_couplers_to_m04_couplers_RVALID;
S_AXI_wready <= m04_couplers_to_m04_couplers_WREADY;
m04_couplers_to_m04_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m04_couplers_to_m04_couplers_ARREADY <= M_AXI_arready;
m04_couplers_to_m04_couplers_ARVALID <= S_AXI_arvalid;
m04_couplers_to_m04_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m04_couplers_to_m04_couplers_AWREADY <= M_AXI_awready;
m04_couplers_to_m04_couplers_AWVALID <= S_AXI_awvalid;
m04_couplers_to_m04_couplers_BREADY <= S_AXI_bready;
m04_couplers_to_m04_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m04_couplers_to_m04_couplers_BVALID <= M_AXI_bvalid;
m04_couplers_to_m04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m04_couplers_to_m04_couplers_RREADY <= S_AXI_rready;
m04_couplers_to_m04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m04_couplers_to_m04_couplers_RVALID <= M_AXI_rvalid;
m04_couplers_to_m04_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m04_couplers_to_m04_couplers_WREADY <= M_AXI_wready;
m04_couplers_to_m04_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m04_couplers_to_m04_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m05_couplers_imp_1HWY5FA is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m05_couplers_imp_1HWY5FA;
architecture STRUCTURE of m05_couplers_imp_1HWY5FA is
signal m05_couplers_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_ARREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_ARVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_AWREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_AWVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_BREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_BVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_RREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_RVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_WREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_m05_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m05_couplers_to_m05_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m05_couplers_to_m05_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m05_couplers_to_m05_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m05_couplers_to_m05_couplers_AWVALID;
M_AXI_bready <= m05_couplers_to_m05_couplers_BREADY;
M_AXI_rready <= m05_couplers_to_m05_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m05_couplers_to_m05_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m05_couplers_to_m05_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m05_couplers_to_m05_couplers_WVALID;
S_AXI_arready <= m05_couplers_to_m05_couplers_ARREADY;
S_AXI_awready <= m05_couplers_to_m05_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m05_couplers_to_m05_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m05_couplers_to_m05_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m05_couplers_to_m05_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m05_couplers_to_m05_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m05_couplers_to_m05_couplers_RVALID;
S_AXI_wready <= m05_couplers_to_m05_couplers_WREADY;
m05_couplers_to_m05_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m05_couplers_to_m05_couplers_ARREADY <= M_AXI_arready;
m05_couplers_to_m05_couplers_ARVALID <= S_AXI_arvalid;
m05_couplers_to_m05_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m05_couplers_to_m05_couplers_AWREADY <= M_AXI_awready;
m05_couplers_to_m05_couplers_AWVALID <= S_AXI_awvalid;
m05_couplers_to_m05_couplers_BREADY <= S_AXI_bready;
m05_couplers_to_m05_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m05_couplers_to_m05_couplers_BVALID <= M_AXI_bvalid;
m05_couplers_to_m05_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m05_couplers_to_m05_couplers_RREADY <= S_AXI_rready;
m05_couplers_to_m05_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m05_couplers_to_m05_couplers_RVALID <= M_AXI_rvalid;
m05_couplers_to_m05_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m05_couplers_to_m05_couplers_WREADY <= M_AXI_wready;
m05_couplers_to_m05_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m05_couplers_to_m05_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m06_couplers_imp_DBR4EM is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m06_couplers_imp_DBR4EM;
architecture STRUCTURE of m06_couplers_imp_DBR4EM is
signal m06_couplers_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_ARREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_ARVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_AWREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_AWVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_BREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_BVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_RREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_RVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_WREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_m06_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m06_couplers_to_m06_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m06_couplers_to_m06_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m06_couplers_to_m06_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m06_couplers_to_m06_couplers_AWVALID;
M_AXI_bready <= m06_couplers_to_m06_couplers_BREADY;
M_AXI_rready <= m06_couplers_to_m06_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m06_couplers_to_m06_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m06_couplers_to_m06_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m06_couplers_to_m06_couplers_WVALID;
S_AXI_arready <= m06_couplers_to_m06_couplers_ARREADY;
S_AXI_awready <= m06_couplers_to_m06_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m06_couplers_to_m06_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m06_couplers_to_m06_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m06_couplers_to_m06_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m06_couplers_to_m06_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m06_couplers_to_m06_couplers_RVALID;
S_AXI_wready <= m06_couplers_to_m06_couplers_WREADY;
m06_couplers_to_m06_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m06_couplers_to_m06_couplers_ARREADY <= M_AXI_arready;
m06_couplers_to_m06_couplers_ARVALID <= S_AXI_arvalid;
m06_couplers_to_m06_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m06_couplers_to_m06_couplers_AWREADY <= M_AXI_awready;
m06_couplers_to_m06_couplers_AWVALID <= S_AXI_awvalid;
m06_couplers_to_m06_couplers_BREADY <= S_AXI_bready;
m06_couplers_to_m06_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m06_couplers_to_m06_couplers_BVALID <= M_AXI_bvalid;
m06_couplers_to_m06_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m06_couplers_to_m06_couplers_RREADY <= S_AXI_rready;
m06_couplers_to_m06_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m06_couplers_to_m06_couplers_RVALID <= M_AXI_rvalid;
m06_couplers_to_m06_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m06_couplers_to_m06_couplers_WREADY <= M_AXI_wready;
m06_couplers_to_m06_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m06_couplers_to_m06_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_7XIH8P is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_7XIH8P;
architecture STRUCTURE of s00_couplers_imp_7XIH8P is
signal s00_couplers_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARREADY : STD_LOGIC;
signal s00_couplers_to_s00_couplers_ARVALID : STD_LOGIC;
signal s00_couplers_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_AWREADY : STD_LOGIC;
signal s00_couplers_to_s00_couplers_AWVALID : STD_LOGIC;
signal s00_couplers_to_s00_couplers_BREADY : STD_LOGIC;
signal s00_couplers_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_BVALID : STD_LOGIC;
signal s00_couplers_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_RREADY : STD_LOGIC;
signal s00_couplers_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_RVALID : STD_LOGIC;
signal s00_couplers_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_WREADY : STD_LOGIC;
signal s00_couplers_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= s00_couplers_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= s00_couplers_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= s00_couplers_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= s00_couplers_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= s00_couplers_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= s00_couplers_to_s00_couplers_AWVALID;
M_AXI_bready <= s00_couplers_to_s00_couplers_BREADY;
M_AXI_rready <= s00_couplers_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= s00_couplers_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= s00_couplers_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= s00_couplers_to_s00_couplers_WVALID;
S_AXI_arready <= s00_couplers_to_s00_couplers_ARREADY;
S_AXI_awready <= s00_couplers_to_s00_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= s00_couplers_to_s00_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_s00_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_s00_couplers_RVALID;
S_AXI_wready <= s00_couplers_to_s00_couplers_WREADY;
s00_couplers_to_s00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_s00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_s00_couplers_ARREADY <= M_AXI_arready;
s00_couplers_to_s00_couplers_ARVALID <= S_AXI_arvalid;
s00_couplers_to_s00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_s00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_s00_couplers_AWREADY <= M_AXI_awready;
s00_couplers_to_s00_couplers_AWVALID <= S_AXI_awvalid;
s00_couplers_to_s00_couplers_BREADY <= S_AXI_bready;
s00_couplers_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s00_couplers_to_s00_couplers_BVALID <= M_AXI_bvalid;
s00_couplers_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s00_couplers_to_s00_couplers_RREADY <= S_AXI_rready;
s00_couplers_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s00_couplers_to_s00_couplers_RVALID <= M_AXI_rvalid;
s00_couplers_to_s00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_s00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_s00_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s01_couplers_imp_1XSI6OU is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s01_couplers_imp_1XSI6OU;
architecture STRUCTURE of s01_couplers_imp_1XSI6OU is
signal s01_couplers_to_s01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_ARREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_ARVALID : STD_LOGIC;
signal s01_couplers_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_AWREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_AWVALID : STD_LOGIC;
signal s01_couplers_to_s01_couplers_BREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_BVALID : STD_LOGIC;
signal s01_couplers_to_s01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_RREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_RVALID : STD_LOGIC;
signal s01_couplers_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_WREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= s01_couplers_to_s01_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= s01_couplers_to_s01_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= s01_couplers_to_s01_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= s01_couplers_to_s01_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= s01_couplers_to_s01_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= s01_couplers_to_s01_couplers_AWVALID;
M_AXI_bready <= s01_couplers_to_s01_couplers_BREADY;
M_AXI_rready <= s01_couplers_to_s01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= s01_couplers_to_s01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= s01_couplers_to_s01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= s01_couplers_to_s01_couplers_WVALID;
S_AXI_arready <= s01_couplers_to_s01_couplers_ARREADY;
S_AXI_awready <= s01_couplers_to_s01_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= s01_couplers_to_s01_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= s01_couplers_to_s01_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= s01_couplers_to_s01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= s01_couplers_to_s01_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= s01_couplers_to_s01_couplers_RVALID;
S_AXI_wready <= s01_couplers_to_s01_couplers_WREADY;
s01_couplers_to_s01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s01_couplers_to_s01_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s01_couplers_to_s01_couplers_ARREADY <= M_AXI_arready;
s01_couplers_to_s01_couplers_ARVALID <= S_AXI_arvalid;
s01_couplers_to_s01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s01_couplers_to_s01_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s01_couplers_to_s01_couplers_AWREADY <= M_AXI_awready;
s01_couplers_to_s01_couplers_AWVALID <= S_AXI_awvalid;
s01_couplers_to_s01_couplers_BREADY <= S_AXI_bready;
s01_couplers_to_s01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s01_couplers_to_s01_couplers_BVALID <= M_AXI_bvalid;
s01_couplers_to_s01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s01_couplers_to_s01_couplers_RREADY <= S_AXI_rready;
s01_couplers_to_s01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s01_couplers_to_s01_couplers_RVALID <= M_AXI_rvalid;
s01_couplers_to_s01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s01_couplers_to_s01_couplers_WREADY <= M_AXI_wready;
s01_couplers_to_s01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s01_couplers_to_s01_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s02_couplers_imp_2QLUHY is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC;
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC;
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s02_couplers_imp_2QLUHY;
architecture STRUCTURE of s02_couplers_imp_2QLUHY is
component DemoInterconnect_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component DemoInterconnect_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_pc_to_s02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s02_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s02_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s02_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s02_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s02_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s02_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s02_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s02_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s02_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s02_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s02_couplers_WVALID : STD_LOGIC;
signal s02_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s02_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s02_couplers_to_auto_pc_ARLOCK : STD_LOGIC;
signal s02_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s02_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s02_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s02_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s02_couplers_to_auto_pc_AWLOCK : STD_LOGIC;
signal s02_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s02_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s02_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s02_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s02_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s02_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s02_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s02_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s02_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s02_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s02_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s02_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s02_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s02_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s02_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s02_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s02_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s02_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s02_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s02_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s02_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= s02_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s02_couplers_to_auto_pc_AWREADY;
S_AXI_bid(0) <= s02_couplers_to_auto_pc_BID(0);
S_AXI_bresp(1 downto 0) <= s02_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s02_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s02_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(0) <= s02_couplers_to_auto_pc_RID(0);
S_AXI_rlast <= s02_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s02_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s02_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s02_couplers_to_auto_pc_WREADY;
auto_pc_to_s02_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s02_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s02_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s02_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s02_couplers_WREADY <= M_AXI_wready;
s02_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s02_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s02_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s02_couplers_to_auto_pc_ARID(0) <= S_AXI_arid(0);
s02_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s02_couplers_to_auto_pc_ARLOCK <= S_AXI_arlock;
s02_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s02_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s02_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s02_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s02_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s02_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s02_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s02_couplers_to_auto_pc_AWID(0) <= S_AXI_awid(0);
s02_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s02_couplers_to_auto_pc_AWLOCK <= S_AXI_awlock;
s02_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s02_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s02_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s02_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s02_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s02_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s02_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s02_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s02_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s02_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component DemoInterconnect_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1,
m_axi_araddr(31 downto 0) => auto_pc_to_s02_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s02_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s02_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s02_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s02_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s02_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s02_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s02_couplers_AWVALID,
m_axi_bready => auto_pc_to_s02_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s02_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s02_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s02_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s02_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s02_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s02_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s02_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s02_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s02_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s02_couplers_WVALID,
s_axi_araddr(31 downto 0) => s02_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s02_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s02_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(0) => s02_couplers_to_auto_pc_ARID(0),
s_axi_arlen(7 downto 0) => s02_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => s02_couplers_to_auto_pc_ARLOCK,
s_axi_arprot(2 downto 0) => s02_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s02_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s02_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s02_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s02_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s02_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s02_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s02_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(0) => s02_couplers_to_auto_pc_AWID(0),
s_axi_awlen(7 downto 0) => s02_couplers_to_auto_pc_AWLEN(7 downto 0),
s_axi_awlock(0) => s02_couplers_to_auto_pc_AWLOCK,
s_axi_awprot(2 downto 0) => s02_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s02_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s02_couplers_to_auto_pc_AWREADY,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s02_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s02_couplers_to_auto_pc_AWVALID,
s_axi_bid(0) => s02_couplers_to_auto_pc_BID(0),
s_axi_bready => s02_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s02_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s02_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s02_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(0) => s02_couplers_to_auto_pc_RID(0),
s_axi_rlast => s02_couplers_to_auto_pc_RLAST,
s_axi_rready => s02_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s02_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s02_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s02_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wlast => s02_couplers_to_auto_pc_WLAST,
s_axi_wready => s02_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s02_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s02_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity DemoInterconnect_axi_interconnect_0_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC;
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_arready : in STD_LOGIC;
M01_AXI_arvalid : out STD_LOGIC;
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_awready : in STD_LOGIC;
M01_AXI_awvalid : out STD_LOGIC;
M01_AXI_bready : out STD_LOGIC;
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC;
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC;
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC;
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC;
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC;
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC;
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M02_AXI_arready : in STD_LOGIC;
M02_AXI_arvalid : out STD_LOGIC;
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M02_AXI_awready : in STD_LOGIC;
M02_AXI_awvalid : out STD_LOGIC;
M02_AXI_bready : out STD_LOGIC;
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC;
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC;
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC;
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC;
M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_wvalid : out STD_LOGIC;
M03_ACLK : in STD_LOGIC;
M03_ARESETN : in STD_LOGIC;
M03_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M03_AXI_arready : in STD_LOGIC;
M03_AXI_arvalid : out STD_LOGIC;
M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M03_AXI_awready : in STD_LOGIC;
M03_AXI_awvalid : out STD_LOGIC;
M03_AXI_bready : out STD_LOGIC;
M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_bvalid : in STD_LOGIC;
M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_rready : out STD_LOGIC;
M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_rvalid : in STD_LOGIC;
M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_wready : in STD_LOGIC;
M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M03_AXI_wvalid : out STD_LOGIC;
M04_ACLK : in STD_LOGIC;
M04_ARESETN : in STD_LOGIC;
M04_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_arready : in STD_LOGIC;
M04_AXI_arvalid : out STD_LOGIC;
M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_awready : in STD_LOGIC;
M04_AXI_awvalid : out STD_LOGIC;
M04_AXI_bready : out STD_LOGIC;
M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_bvalid : in STD_LOGIC;
M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_rready : out STD_LOGIC;
M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_rvalid : in STD_LOGIC;
M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_wready : in STD_LOGIC;
M04_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M04_AXI_wvalid : out STD_LOGIC;
M05_ACLK : in STD_LOGIC;
M05_ARESETN : in STD_LOGIC;
M05_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_arready : in STD_LOGIC;
M05_AXI_arvalid : out STD_LOGIC;
M05_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_awready : in STD_LOGIC;
M05_AXI_awvalid : out STD_LOGIC;
M05_AXI_bready : out STD_LOGIC;
M05_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_bvalid : in STD_LOGIC;
M05_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_rready : out STD_LOGIC;
M05_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_rvalid : in STD_LOGIC;
M05_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_wready : in STD_LOGIC;
M05_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M05_AXI_wvalid : out STD_LOGIC;
M06_ACLK : in STD_LOGIC;
M06_ARESETN : in STD_LOGIC;
M06_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_arready : in STD_LOGIC;
M06_AXI_arvalid : out STD_LOGIC;
M06_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_awready : in STD_LOGIC;
M06_AXI_awvalid : out STD_LOGIC;
M06_AXI_bready : out STD_LOGIC;
M06_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_bvalid : in STD_LOGIC;
M06_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_rready : out STD_LOGIC;
M06_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_rvalid : in STD_LOGIC;
M06_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_wready : in STD_LOGIC;
M06_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M06_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC;
S01_ACLK : in STD_LOGIC;
S01_ARESETN : in STD_LOGIC;
S01_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_arready : out STD_LOGIC;
S01_AXI_arvalid : in STD_LOGIC;
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awready : out STD_LOGIC;
S01_AXI_awvalid : in STD_LOGIC;
S01_AXI_bready : in STD_LOGIC;
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_bvalid : out STD_LOGIC;
S01_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_rready : in STD_LOGIC;
S01_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_rvalid : out STD_LOGIC;
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_wready : out STD_LOGIC;
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_wvalid : in STD_LOGIC;
S02_ACLK : in STD_LOGIC;
S02_ARESETN : in STD_LOGIC;
S02_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_arlock : in STD_LOGIC;
S02_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arready : out STD_LOGIC;
S02_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arvalid : in STD_LOGIC;
S02_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_awlock : in STD_LOGIC;
S02_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awready : out STD_LOGIC;
S02_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_awvalid : in STD_LOGIC;
S02_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_bready : in STD_LOGIC;
S02_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_bvalid : out STD_LOGIC;
S02_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_rlast : out STD_LOGIC;
S02_AXI_rready : in STD_LOGIC;
S02_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_rvalid : out STD_LOGIC;
S02_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_wlast : in STD_LOGIC;
S02_AXI_wready : out STD_LOGIC;
S02_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_wvalid : in STD_LOGIC
);
end DemoInterconnect_axi_interconnect_0_0;
architecture STRUCTURE of DemoInterconnect_axi_interconnect_0_0 is
component DemoInterconnect_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 20 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 20 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 6 downto 0 )
);
end component DemoInterconnect_xbar_0;
signal interconnect_ACLK_net : STD_LOGIC;
signal interconnect_ARESETN_net : STD_LOGIC;
signal interconnect_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s00_couplers_ARREADY : STD_LOGIC;
signal interconnect_to_s00_couplers_ARVALID : STD_LOGIC;
signal interconnect_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s00_couplers_AWREADY : STD_LOGIC;
signal interconnect_to_s00_couplers_AWVALID : STD_LOGIC;
signal interconnect_to_s00_couplers_BREADY : STD_LOGIC;
signal interconnect_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s00_couplers_BVALID : STD_LOGIC;
signal interconnect_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s00_couplers_RREADY : STD_LOGIC;
signal interconnect_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s00_couplers_RVALID : STD_LOGIC;
signal interconnect_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s00_couplers_WREADY : STD_LOGIC;
signal interconnect_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s00_couplers_WVALID : STD_LOGIC;
signal interconnect_to_s01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s01_couplers_ARREADY : STD_LOGIC;
signal interconnect_to_s01_couplers_ARVALID : STD_LOGIC;
signal interconnect_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s01_couplers_AWREADY : STD_LOGIC;
signal interconnect_to_s01_couplers_AWVALID : STD_LOGIC;
signal interconnect_to_s01_couplers_BREADY : STD_LOGIC;
signal interconnect_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s01_couplers_BVALID : STD_LOGIC;
signal interconnect_to_s01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s01_couplers_RREADY : STD_LOGIC;
signal interconnect_to_s01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s01_couplers_RVALID : STD_LOGIC;
signal interconnect_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s01_couplers_WREADY : STD_LOGIC;
signal interconnect_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s01_couplers_WVALID : STD_LOGIC;
signal interconnect_to_s02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s02_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s02_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s02_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal interconnect_to_s02_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal interconnect_to_s02_couplers_ARLOCK : STD_LOGIC;
signal interconnect_to_s02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s02_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s02_couplers_ARREADY : STD_LOGIC;
signal interconnect_to_s02_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s02_couplers_ARVALID : STD_LOGIC;
signal interconnect_to_s02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s02_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s02_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s02_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal interconnect_to_s02_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal interconnect_to_s02_couplers_AWLOCK : STD_LOGIC;
signal interconnect_to_s02_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s02_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s02_couplers_AWREADY : STD_LOGIC;
signal interconnect_to_s02_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s02_couplers_AWVALID : STD_LOGIC;
signal interconnect_to_s02_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal interconnect_to_s02_couplers_BREADY : STD_LOGIC;
signal interconnect_to_s02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s02_couplers_BVALID : STD_LOGIC;
signal interconnect_to_s02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s02_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal interconnect_to_s02_couplers_RLAST : STD_LOGIC;
signal interconnect_to_s02_couplers_RREADY : STD_LOGIC;
signal interconnect_to_s02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s02_couplers_RVALID : STD_LOGIC;
signal interconnect_to_s02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s02_couplers_WLAST : STD_LOGIC;
signal interconnect_to_s02_couplers_WREADY : STD_LOGIC;
signal interconnect_to_s02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s02_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_interconnect_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m00_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m00_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_interconnect_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m00_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m00_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m00_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m00_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m00_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m00_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m00_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m01_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_interconnect_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m01_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m01_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_interconnect_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m01_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m01_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m01_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m01_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m01_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m01_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m01_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m02_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_interconnect_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m02_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m02_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_interconnect_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m02_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m02_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m02_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m02_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m02_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m02_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m02_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m03_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_interconnect_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m03_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m03_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_interconnect_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m03_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m03_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m03_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m03_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m03_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m03_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m03_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m04_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m04_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m04_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m04_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m04_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m04_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m04_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m04_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m04_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m04_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m05_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m05_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m05_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m05_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m05_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m05_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m05_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m05_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m05_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m05_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m06_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m06_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m06_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m06_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m06_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m06_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m06_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m06_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m06_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m06_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_interconnect_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal s01_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s01_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s01_couplers_to_xbar_BREADY : STD_LOGIC;
signal s01_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal s01_couplers_to_xbar_RREADY : STD_LOGIC;
signal s01_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_WVALID : STD_LOGIC;
signal s02_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s02_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s02_couplers_to_xbar_BREADY : STD_LOGIC;
signal s02_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 5 downto 4 );
signal s02_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal s02_couplers_to_xbar_RREADY : STD_LOGIC;
signal s02_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 5 downto 4 );
signal s02_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC;
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC;
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC;
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARPROT : STD_LOGIC_VECTOR ( 8 downto 6 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWPROT : STD_LOGIC_VECTOR ( 8 downto 6 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC;
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC;
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC;
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_ARPROT : STD_LOGIC_VECTOR ( 11 downto 9 );
signal xbar_to_m03_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_AWPROT : STD_LOGIC_VECTOR ( 11 downto 9 );
signal xbar_to_m03_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_BVALID : STD_LOGIC;
signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_RVALID : STD_LOGIC;
signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_WREADY : STD_LOGIC;
signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 );
signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_BVALID : STD_LOGIC;
signal xbar_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_RVALID : STD_LOGIC;
signal xbar_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_WREADY : STD_LOGIC;
signal xbar_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 19 downto 16 );
signal xbar_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m05_couplers_ARVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m05_couplers_AWVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_BVALID : STD_LOGIC;
signal xbar_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m05_couplers_RREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_RVALID : STD_LOGIC;
signal xbar_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_WREADY : STD_LOGIC;
signal xbar_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 23 downto 20 );
signal xbar_to_m05_couplers_WVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m06_couplers_ARVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m06_couplers_AWVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_BVALID : STD_LOGIC;
signal xbar_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m06_couplers_RREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_RVALID : STD_LOGIC;
signal xbar_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_WREADY : STD_LOGIC;
signal xbar_to_m06_couplers_WSTRB : STD_LOGIC_VECTOR ( 27 downto 24 );
signal xbar_to_m06_couplers_WVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 20 downto 12 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 20 downto 12 );
begin
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_interconnect_ARADDR(31 downto 0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_interconnect_ARPROT(2 downto 0);
M00_AXI_arvalid <= m00_couplers_to_interconnect_ARVALID;
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_interconnect_AWADDR(31 downto 0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_interconnect_AWPROT(2 downto 0);
M00_AXI_awvalid <= m00_couplers_to_interconnect_AWVALID;
M00_AXI_bready <= m00_couplers_to_interconnect_BREADY;
M00_AXI_rready <= m00_couplers_to_interconnect_RREADY;
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_interconnect_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_interconnect_WSTRB(3 downto 0);
M00_AXI_wvalid <= m00_couplers_to_interconnect_WVALID;
M01_AXI_araddr(31 downto 0) <= m01_couplers_to_interconnect_ARADDR(31 downto 0);
M01_AXI_arprot(2 downto 0) <= m01_couplers_to_interconnect_ARPROT(2 downto 0);
M01_AXI_arvalid <= m01_couplers_to_interconnect_ARVALID;
M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_interconnect_AWADDR(31 downto 0);
M01_AXI_awprot(2 downto 0) <= m01_couplers_to_interconnect_AWPROT(2 downto 0);
M01_AXI_awvalid <= m01_couplers_to_interconnect_AWVALID;
M01_AXI_bready <= m01_couplers_to_interconnect_BREADY;
M01_AXI_rready <= m01_couplers_to_interconnect_RREADY;
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_interconnect_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_interconnect_WSTRB(3 downto 0);
M01_AXI_wvalid <= m01_couplers_to_interconnect_WVALID;
M02_AXI_araddr(31 downto 0) <= m02_couplers_to_interconnect_ARADDR(31 downto 0);
M02_AXI_arprot(2 downto 0) <= m02_couplers_to_interconnect_ARPROT(2 downto 0);
M02_AXI_arvalid <= m02_couplers_to_interconnect_ARVALID;
M02_AXI_awaddr(31 downto 0) <= m02_couplers_to_interconnect_AWADDR(31 downto 0);
M02_AXI_awprot(2 downto 0) <= m02_couplers_to_interconnect_AWPROT(2 downto 0);
M02_AXI_awvalid <= m02_couplers_to_interconnect_AWVALID;
M02_AXI_bready <= m02_couplers_to_interconnect_BREADY;
M02_AXI_rready <= m02_couplers_to_interconnect_RREADY;
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_interconnect_WDATA(31 downto 0);
M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_interconnect_WSTRB(3 downto 0);
M02_AXI_wvalid <= m02_couplers_to_interconnect_WVALID;
M03_AXI_araddr(31 downto 0) <= m03_couplers_to_interconnect_ARADDR(31 downto 0);
M03_AXI_arprot(2 downto 0) <= m03_couplers_to_interconnect_ARPROT(2 downto 0);
M03_AXI_arvalid <= m03_couplers_to_interconnect_ARVALID;
M03_AXI_awaddr(31 downto 0) <= m03_couplers_to_interconnect_AWADDR(31 downto 0);
M03_AXI_awprot(2 downto 0) <= m03_couplers_to_interconnect_AWPROT(2 downto 0);
M03_AXI_awvalid <= m03_couplers_to_interconnect_AWVALID;
M03_AXI_bready <= m03_couplers_to_interconnect_BREADY;
M03_AXI_rready <= m03_couplers_to_interconnect_RREADY;
M03_AXI_wdata(31 downto 0) <= m03_couplers_to_interconnect_WDATA(31 downto 0);
M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_interconnect_WSTRB(3 downto 0);
M03_AXI_wvalid <= m03_couplers_to_interconnect_WVALID;
M04_AXI_araddr(31 downto 0) <= m04_couplers_to_interconnect_ARADDR(31 downto 0);
M04_AXI_arvalid <= m04_couplers_to_interconnect_ARVALID;
M04_AXI_awaddr(31 downto 0) <= m04_couplers_to_interconnect_AWADDR(31 downto 0);
M04_AXI_awvalid <= m04_couplers_to_interconnect_AWVALID;
M04_AXI_bready <= m04_couplers_to_interconnect_BREADY;
M04_AXI_rready <= m04_couplers_to_interconnect_RREADY;
M04_AXI_wdata(31 downto 0) <= m04_couplers_to_interconnect_WDATA(31 downto 0);
M04_AXI_wstrb(3 downto 0) <= m04_couplers_to_interconnect_WSTRB(3 downto 0);
M04_AXI_wvalid <= m04_couplers_to_interconnect_WVALID;
M05_AXI_araddr(31 downto 0) <= m05_couplers_to_interconnect_ARADDR(31 downto 0);
M05_AXI_arvalid <= m05_couplers_to_interconnect_ARVALID;
M05_AXI_awaddr(31 downto 0) <= m05_couplers_to_interconnect_AWADDR(31 downto 0);
M05_AXI_awvalid <= m05_couplers_to_interconnect_AWVALID;
M05_AXI_bready <= m05_couplers_to_interconnect_BREADY;
M05_AXI_rready <= m05_couplers_to_interconnect_RREADY;
M05_AXI_wdata(31 downto 0) <= m05_couplers_to_interconnect_WDATA(31 downto 0);
M05_AXI_wstrb(3 downto 0) <= m05_couplers_to_interconnect_WSTRB(3 downto 0);
M05_AXI_wvalid <= m05_couplers_to_interconnect_WVALID;
M06_AXI_araddr(31 downto 0) <= m06_couplers_to_interconnect_ARADDR(31 downto 0);
M06_AXI_arvalid <= m06_couplers_to_interconnect_ARVALID;
M06_AXI_awaddr(31 downto 0) <= m06_couplers_to_interconnect_AWADDR(31 downto 0);
M06_AXI_awvalid <= m06_couplers_to_interconnect_AWVALID;
M06_AXI_bready <= m06_couplers_to_interconnect_BREADY;
M06_AXI_rready <= m06_couplers_to_interconnect_RREADY;
M06_AXI_wdata(31 downto 0) <= m06_couplers_to_interconnect_WDATA(31 downto 0);
M06_AXI_wstrb(3 downto 0) <= m06_couplers_to_interconnect_WSTRB(3 downto 0);
M06_AXI_wvalid <= m06_couplers_to_interconnect_WVALID;
S00_AXI_arready <= interconnect_to_s00_couplers_ARREADY;
S00_AXI_awready <= interconnect_to_s00_couplers_AWREADY;
S00_AXI_bresp(1 downto 0) <= interconnect_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= interconnect_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= interconnect_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rresp(1 downto 0) <= interconnect_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= interconnect_to_s00_couplers_RVALID;
S00_AXI_wready <= interconnect_to_s00_couplers_WREADY;
S01_AXI_arready <= interconnect_to_s01_couplers_ARREADY;
S01_AXI_awready <= interconnect_to_s01_couplers_AWREADY;
S01_AXI_bresp(1 downto 0) <= interconnect_to_s01_couplers_BRESP(1 downto 0);
S01_AXI_bvalid <= interconnect_to_s01_couplers_BVALID;
S01_AXI_rdata(31 downto 0) <= interconnect_to_s01_couplers_RDATA(31 downto 0);
S01_AXI_rresp(1 downto 0) <= interconnect_to_s01_couplers_RRESP(1 downto 0);
S01_AXI_rvalid <= interconnect_to_s01_couplers_RVALID;
S01_AXI_wready <= interconnect_to_s01_couplers_WREADY;
S02_AXI_arready <= interconnect_to_s02_couplers_ARREADY;
S02_AXI_awready <= interconnect_to_s02_couplers_AWREADY;
S02_AXI_bid(0) <= interconnect_to_s02_couplers_BID(0);
S02_AXI_bresp(1 downto 0) <= interconnect_to_s02_couplers_BRESP(1 downto 0);
S02_AXI_bvalid <= interconnect_to_s02_couplers_BVALID;
S02_AXI_rdata(31 downto 0) <= interconnect_to_s02_couplers_RDATA(31 downto 0);
S02_AXI_rid(0) <= interconnect_to_s02_couplers_RID(0);
S02_AXI_rlast <= interconnect_to_s02_couplers_RLAST;
S02_AXI_rresp(1 downto 0) <= interconnect_to_s02_couplers_RRESP(1 downto 0);
S02_AXI_rvalid <= interconnect_to_s02_couplers_RVALID;
S02_AXI_wready <= interconnect_to_s02_couplers_WREADY;
interconnect_ACLK_net <= ACLK;
interconnect_ARESETN_net <= ARESETN;
interconnect_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
interconnect_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
interconnect_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
interconnect_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
interconnect_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
interconnect_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
interconnect_to_s00_couplers_BREADY <= S00_AXI_bready;
interconnect_to_s00_couplers_RREADY <= S00_AXI_rready;
interconnect_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
interconnect_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
interconnect_to_s00_couplers_WVALID <= S00_AXI_wvalid;
interconnect_to_s01_couplers_ARADDR(31 downto 0) <= S01_AXI_araddr(31 downto 0);
interconnect_to_s01_couplers_ARPROT(2 downto 0) <= S01_AXI_arprot(2 downto 0);
interconnect_to_s01_couplers_ARVALID <= S01_AXI_arvalid;
interconnect_to_s01_couplers_AWADDR(31 downto 0) <= S01_AXI_awaddr(31 downto 0);
interconnect_to_s01_couplers_AWPROT(2 downto 0) <= S01_AXI_awprot(2 downto 0);
interconnect_to_s01_couplers_AWVALID <= S01_AXI_awvalid;
interconnect_to_s01_couplers_BREADY <= S01_AXI_bready;
interconnect_to_s01_couplers_RREADY <= S01_AXI_rready;
interconnect_to_s01_couplers_WDATA(31 downto 0) <= S01_AXI_wdata(31 downto 0);
interconnect_to_s01_couplers_WSTRB(3 downto 0) <= S01_AXI_wstrb(3 downto 0);
interconnect_to_s01_couplers_WVALID <= S01_AXI_wvalid;
interconnect_to_s02_couplers_ARADDR(31 downto 0) <= S02_AXI_araddr(31 downto 0);
interconnect_to_s02_couplers_ARBURST(1 downto 0) <= S02_AXI_arburst(1 downto 0);
interconnect_to_s02_couplers_ARCACHE(3 downto 0) <= S02_AXI_arcache(3 downto 0);
interconnect_to_s02_couplers_ARID(0) <= S02_AXI_arid(0);
interconnect_to_s02_couplers_ARLEN(7 downto 0) <= S02_AXI_arlen(7 downto 0);
interconnect_to_s02_couplers_ARLOCK <= S02_AXI_arlock;
interconnect_to_s02_couplers_ARPROT(2 downto 0) <= S02_AXI_arprot(2 downto 0);
interconnect_to_s02_couplers_ARQOS(3 downto 0) <= S02_AXI_arqos(3 downto 0);
interconnect_to_s02_couplers_ARSIZE(2 downto 0) <= S02_AXI_arsize(2 downto 0);
interconnect_to_s02_couplers_ARVALID <= S02_AXI_arvalid;
interconnect_to_s02_couplers_AWADDR(31 downto 0) <= S02_AXI_awaddr(31 downto 0);
interconnect_to_s02_couplers_AWBURST(1 downto 0) <= S02_AXI_awburst(1 downto 0);
interconnect_to_s02_couplers_AWCACHE(3 downto 0) <= S02_AXI_awcache(3 downto 0);
interconnect_to_s02_couplers_AWID(0) <= S02_AXI_awid(0);
interconnect_to_s02_couplers_AWLEN(7 downto 0) <= S02_AXI_awlen(7 downto 0);
interconnect_to_s02_couplers_AWLOCK <= S02_AXI_awlock;
interconnect_to_s02_couplers_AWPROT(2 downto 0) <= S02_AXI_awprot(2 downto 0);
interconnect_to_s02_couplers_AWQOS(3 downto 0) <= S02_AXI_awqos(3 downto 0);
interconnect_to_s02_couplers_AWSIZE(2 downto 0) <= S02_AXI_awsize(2 downto 0);
interconnect_to_s02_couplers_AWVALID <= S02_AXI_awvalid;
interconnect_to_s02_couplers_BREADY <= S02_AXI_bready;
interconnect_to_s02_couplers_RREADY <= S02_AXI_rready;
interconnect_to_s02_couplers_WDATA(31 downto 0) <= S02_AXI_wdata(31 downto 0);
interconnect_to_s02_couplers_WLAST <= S02_AXI_wlast;
interconnect_to_s02_couplers_WSTRB(3 downto 0) <= S02_AXI_wstrb(3 downto 0);
interconnect_to_s02_couplers_WVALID <= S02_AXI_wvalid;
m00_couplers_to_interconnect_ARREADY <= M00_AXI_arready;
m00_couplers_to_interconnect_AWREADY <= M00_AXI_awready;
m00_couplers_to_interconnect_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_interconnect_BVALID <= M00_AXI_bvalid;
m00_couplers_to_interconnect_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_interconnect_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_interconnect_RVALID <= M00_AXI_rvalid;
m00_couplers_to_interconnect_WREADY <= M00_AXI_wready;
m01_couplers_to_interconnect_ARREADY <= M01_AXI_arready;
m01_couplers_to_interconnect_AWREADY <= M01_AXI_awready;
m01_couplers_to_interconnect_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_interconnect_BVALID <= M01_AXI_bvalid;
m01_couplers_to_interconnect_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_interconnect_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_interconnect_RVALID <= M01_AXI_rvalid;
m01_couplers_to_interconnect_WREADY <= M01_AXI_wready;
m02_couplers_to_interconnect_ARREADY <= M02_AXI_arready;
m02_couplers_to_interconnect_AWREADY <= M02_AXI_awready;
m02_couplers_to_interconnect_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_interconnect_BVALID <= M02_AXI_bvalid;
m02_couplers_to_interconnect_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_interconnect_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_interconnect_RVALID <= M02_AXI_rvalid;
m02_couplers_to_interconnect_WREADY <= M02_AXI_wready;
m03_couplers_to_interconnect_ARREADY <= M03_AXI_arready;
m03_couplers_to_interconnect_AWREADY <= M03_AXI_awready;
m03_couplers_to_interconnect_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
m03_couplers_to_interconnect_BVALID <= M03_AXI_bvalid;
m03_couplers_to_interconnect_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
m03_couplers_to_interconnect_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
m03_couplers_to_interconnect_RVALID <= M03_AXI_rvalid;
m03_couplers_to_interconnect_WREADY <= M03_AXI_wready;
m04_couplers_to_interconnect_ARREADY <= M04_AXI_arready;
m04_couplers_to_interconnect_AWREADY <= M04_AXI_awready;
m04_couplers_to_interconnect_BRESP(1 downto 0) <= M04_AXI_bresp(1 downto 0);
m04_couplers_to_interconnect_BVALID <= M04_AXI_bvalid;
m04_couplers_to_interconnect_RDATA(31 downto 0) <= M04_AXI_rdata(31 downto 0);
m04_couplers_to_interconnect_RRESP(1 downto 0) <= M04_AXI_rresp(1 downto 0);
m04_couplers_to_interconnect_RVALID <= M04_AXI_rvalid;
m04_couplers_to_interconnect_WREADY <= M04_AXI_wready;
m05_couplers_to_interconnect_ARREADY <= M05_AXI_arready;
m05_couplers_to_interconnect_AWREADY <= M05_AXI_awready;
m05_couplers_to_interconnect_BRESP(1 downto 0) <= M05_AXI_bresp(1 downto 0);
m05_couplers_to_interconnect_BVALID <= M05_AXI_bvalid;
m05_couplers_to_interconnect_RDATA(31 downto 0) <= M05_AXI_rdata(31 downto 0);
m05_couplers_to_interconnect_RRESP(1 downto 0) <= M05_AXI_rresp(1 downto 0);
m05_couplers_to_interconnect_RVALID <= M05_AXI_rvalid;
m05_couplers_to_interconnect_WREADY <= M05_AXI_wready;
m06_couplers_to_interconnect_ARREADY <= M06_AXI_arready;
m06_couplers_to_interconnect_AWREADY <= M06_AXI_awready;
m06_couplers_to_interconnect_BRESP(1 downto 0) <= M06_AXI_bresp(1 downto 0);
m06_couplers_to_interconnect_BVALID <= M06_AXI_bvalid;
m06_couplers_to_interconnect_RDATA(31 downto 0) <= M06_AXI_rdata(31 downto 0);
m06_couplers_to_interconnect_RRESP(1 downto 0) <= M06_AXI_rresp(1 downto 0);
m06_couplers_to_interconnect_RVALID <= M06_AXI_rvalid;
m06_couplers_to_interconnect_WREADY <= M06_AXI_wready;
m00_couplers: entity work.m00_couplers_imp_4EB6IN
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m00_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_interconnect_ARPROT(2 downto 0),
M_AXI_arready => m00_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m00_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m00_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_interconnect_AWPROT(2 downto 0),
M_AXI_awready => m00_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m00_couplers_to_interconnect_AWVALID,
M_AXI_bready => m00_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m00_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m00_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m00_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m00_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m00_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m00_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_1SL2GIW
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m01_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m01_couplers_to_interconnect_ARPROT(2 downto 0),
M_AXI_arready => m01_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m01_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m01_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m01_couplers_to_interconnect_AWPROT(2 downto 0),
M_AXI_awready => m01_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m01_couplers_to_interconnect_AWVALID,
M_AXI_bready => m01_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m01_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m01_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m01_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m01_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m01_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m01_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m01_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m01_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m01_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m01_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arprot(2 downto 0) => xbar_to_m01_couplers_ARPROT(5 downto 3),
S_AXI_arready => xbar_to_m01_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awprot(2 downto 0) => xbar_to_m01_couplers_AWPROT(5 downto 3),
S_AXI_awready => xbar_to_m01_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready => xbar_to_m01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_7DG2C0
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m02_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m02_couplers_to_interconnect_ARPROT(2 downto 0),
M_AXI_arready => m02_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m02_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m02_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m02_couplers_to_interconnect_AWPROT(2 downto 0),
M_AXI_awready => m02_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m02_couplers_to_interconnect_AWVALID,
M_AXI_bready => m02_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m02_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m02_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m02_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m02_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m02_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m02_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m02_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m02_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m02_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m02_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m02_couplers_ARADDR(95 downto 64),
S_AXI_arprot(2 downto 0) => xbar_to_m02_couplers_ARPROT(8 downto 6),
S_AXI_arready => xbar_to_m02_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(31 downto 0) => xbar_to_m02_couplers_AWADDR(95 downto 64),
S_AXI_awprot(2 downto 0) => xbar_to_m02_couplers_AWPROT(8 downto 6),
S_AXI_awready => xbar_to_m02_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready => xbar_to_m02_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2)
);
m03_couplers: entity work.m03_couplers_imp_1YCPS1Z
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m03_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m03_couplers_to_interconnect_ARPROT(2 downto 0),
M_AXI_arready => m03_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m03_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m03_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m03_couplers_to_interconnect_AWPROT(2 downto 0),
M_AXI_awready => m03_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m03_couplers_to_interconnect_AWVALID,
M_AXI_bready => m03_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m03_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m03_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m03_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m03_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m03_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m03_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m03_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m03_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m03_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m03_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m03_couplers_ARADDR(127 downto 96),
S_AXI_arprot(2 downto 0) => xbar_to_m03_couplers_ARPROT(11 downto 9),
S_AXI_arready => xbar_to_m03_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m03_couplers_ARVALID(3),
S_AXI_awaddr(31 downto 0) => xbar_to_m03_couplers_AWADDR(127 downto 96),
S_AXI_awprot(2 downto 0) => xbar_to_m03_couplers_AWPROT(11 downto 9),
S_AXI_awready => xbar_to_m03_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m03_couplers_AWVALID(3),
S_AXI_bready => xbar_to_m03_couplers_BREADY(3),
S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m03_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m03_couplers_RREADY(3),
S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m03_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
S_AXI_wready => xbar_to_m03_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12),
S_AXI_wvalid => xbar_to_m03_couplers_WVALID(3)
);
m04_couplers: entity work.m04_couplers_imp_ACM7VL
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m04_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arready => m04_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m04_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m04_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awready => m04_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m04_couplers_to_interconnect_AWVALID,
M_AXI_bready => m04_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m04_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m04_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m04_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m04_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m04_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m04_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m04_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m04_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m04_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m04_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m04_couplers_ARADDR(159 downto 128),
S_AXI_arready => xbar_to_m04_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m04_couplers_ARVALID(4),
S_AXI_awaddr(31 downto 0) => xbar_to_m04_couplers_AWADDR(159 downto 128),
S_AXI_awready => xbar_to_m04_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m04_couplers_AWVALID(4),
S_AXI_bready => xbar_to_m04_couplers_BREADY(4),
S_AXI_bresp(1 downto 0) => xbar_to_m04_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m04_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m04_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m04_couplers_RREADY(4),
S_AXI_rresp(1 downto 0) => xbar_to_m04_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m04_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m04_couplers_WDATA(159 downto 128),
S_AXI_wready => xbar_to_m04_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m04_couplers_WSTRB(19 downto 16),
S_AXI_wvalid => xbar_to_m04_couplers_WVALID(4)
);
m05_couplers: entity work.m05_couplers_imp_1HWY5FA
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m05_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arready => m05_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m05_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m05_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awready => m05_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m05_couplers_to_interconnect_AWVALID,
M_AXI_bready => m05_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m05_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m05_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m05_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m05_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m05_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m05_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m05_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m05_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m05_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m05_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m05_couplers_ARADDR(191 downto 160),
S_AXI_arready => xbar_to_m05_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m05_couplers_ARVALID(5),
S_AXI_awaddr(31 downto 0) => xbar_to_m05_couplers_AWADDR(191 downto 160),
S_AXI_awready => xbar_to_m05_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m05_couplers_AWVALID(5),
S_AXI_bready => xbar_to_m05_couplers_BREADY(5),
S_AXI_bresp(1 downto 0) => xbar_to_m05_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m05_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m05_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m05_couplers_RREADY(5),
S_AXI_rresp(1 downto 0) => xbar_to_m05_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m05_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m05_couplers_WDATA(191 downto 160),
S_AXI_wready => xbar_to_m05_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m05_couplers_WSTRB(23 downto 20),
S_AXI_wvalid => xbar_to_m05_couplers_WVALID(5)
);
m06_couplers: entity work.m06_couplers_imp_DBR4EM
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m06_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arready => m06_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m06_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m06_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awready => m06_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m06_couplers_to_interconnect_AWVALID,
M_AXI_bready => m06_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m06_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m06_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m06_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m06_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m06_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m06_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m06_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m06_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m06_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m06_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m06_couplers_ARADDR(223 downto 192),
S_AXI_arready => xbar_to_m06_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m06_couplers_ARVALID(6),
S_AXI_awaddr(31 downto 0) => xbar_to_m06_couplers_AWADDR(223 downto 192),
S_AXI_awready => xbar_to_m06_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m06_couplers_AWVALID(6),
S_AXI_bready => xbar_to_m06_couplers_BREADY(6),
S_AXI_bresp(1 downto 0) => xbar_to_m06_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m06_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m06_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m06_couplers_RREADY(6),
S_AXI_rresp(1 downto 0) => xbar_to_m06_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m06_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m06_couplers_WDATA(223 downto 192),
S_AXI_wready => xbar_to_m06_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m06_couplers_WSTRB(27 downto 24),
S_AXI_wvalid => xbar_to_m06_couplers_WVALID(6)
);
s00_couplers: entity work.s00_couplers_imp_7XIH8P
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => interconnect_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => interconnect_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready => interconnect_to_s00_couplers_ARREADY,
S_AXI_arvalid => interconnect_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => interconnect_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => interconnect_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awready => interconnect_to_s00_couplers_AWREADY,
S_AXI_awvalid => interconnect_to_s00_couplers_AWVALID,
S_AXI_bready => interconnect_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => interconnect_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => interconnect_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => interconnect_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rready => interconnect_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => interconnect_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => interconnect_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => interconnect_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wready => interconnect_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => interconnect_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => interconnect_to_s00_couplers_WVALID
);
s01_couplers: entity work.s01_couplers_imp_1XSI6OU
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => s01_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s01_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s01_couplers_to_xbar_ARREADY(1),
M_AXI_arvalid => s01_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s01_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s01_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s01_couplers_to_xbar_AWREADY(1),
M_AXI_awvalid => s01_couplers_to_xbar_AWVALID,
M_AXI_bready => s01_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s01_couplers_to_xbar_BRESP(3 downto 2),
M_AXI_bvalid => s01_couplers_to_xbar_BVALID(1),
M_AXI_rdata(31 downto 0) => s01_couplers_to_xbar_RDATA(63 downto 32),
M_AXI_rready => s01_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s01_couplers_to_xbar_RRESP(3 downto 2),
M_AXI_rvalid => s01_couplers_to_xbar_RVALID(1),
M_AXI_wdata(31 downto 0) => s01_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s01_couplers_to_xbar_WREADY(1),
M_AXI_wstrb(3 downto 0) => s01_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s01_couplers_to_xbar_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => interconnect_to_s01_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => interconnect_to_s01_couplers_ARPROT(2 downto 0),
S_AXI_arready => interconnect_to_s01_couplers_ARREADY,
S_AXI_arvalid => interconnect_to_s01_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => interconnect_to_s01_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => interconnect_to_s01_couplers_AWPROT(2 downto 0),
S_AXI_awready => interconnect_to_s01_couplers_AWREADY,
S_AXI_awvalid => interconnect_to_s01_couplers_AWVALID,
S_AXI_bready => interconnect_to_s01_couplers_BREADY,
S_AXI_bresp(1 downto 0) => interconnect_to_s01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => interconnect_to_s01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => interconnect_to_s01_couplers_RDATA(31 downto 0),
S_AXI_rready => interconnect_to_s01_couplers_RREADY,
S_AXI_rresp(1 downto 0) => interconnect_to_s01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => interconnect_to_s01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => interconnect_to_s01_couplers_WDATA(31 downto 0),
S_AXI_wready => interconnect_to_s01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => interconnect_to_s01_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => interconnect_to_s01_couplers_WVALID
);
s02_couplers: entity work.s02_couplers_imp_2QLUHY
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => s02_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s02_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s02_couplers_to_xbar_ARREADY(2),
M_AXI_arvalid => s02_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s02_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s02_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s02_couplers_to_xbar_AWREADY(2),
M_AXI_awvalid => s02_couplers_to_xbar_AWVALID,
M_AXI_bready => s02_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s02_couplers_to_xbar_BRESP(5 downto 4),
M_AXI_bvalid => s02_couplers_to_xbar_BVALID(2),
M_AXI_rdata(31 downto 0) => s02_couplers_to_xbar_RDATA(95 downto 64),
M_AXI_rready => s02_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s02_couplers_to_xbar_RRESP(5 downto 4),
M_AXI_rvalid => s02_couplers_to_xbar_RVALID(2),
M_AXI_wdata(31 downto 0) => s02_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s02_couplers_to_xbar_WREADY(2),
M_AXI_wstrb(3 downto 0) => s02_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s02_couplers_to_xbar_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => interconnect_to_s02_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => interconnect_to_s02_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => interconnect_to_s02_couplers_ARCACHE(3 downto 0),
S_AXI_arid(0) => interconnect_to_s02_couplers_ARID(0),
S_AXI_arlen(7 downto 0) => interconnect_to_s02_couplers_ARLEN(7 downto 0),
S_AXI_arlock => interconnect_to_s02_couplers_ARLOCK,
S_AXI_arprot(2 downto 0) => interconnect_to_s02_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => interconnect_to_s02_couplers_ARQOS(3 downto 0),
S_AXI_arready => interconnect_to_s02_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => interconnect_to_s02_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => interconnect_to_s02_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => interconnect_to_s02_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => interconnect_to_s02_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => interconnect_to_s02_couplers_AWCACHE(3 downto 0),
S_AXI_awid(0) => interconnect_to_s02_couplers_AWID(0),
S_AXI_awlen(7 downto 0) => interconnect_to_s02_couplers_AWLEN(7 downto 0),
S_AXI_awlock => interconnect_to_s02_couplers_AWLOCK,
S_AXI_awprot(2 downto 0) => interconnect_to_s02_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => interconnect_to_s02_couplers_AWQOS(3 downto 0),
S_AXI_awready => interconnect_to_s02_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => interconnect_to_s02_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => interconnect_to_s02_couplers_AWVALID,
S_AXI_bid(0) => interconnect_to_s02_couplers_BID(0),
S_AXI_bready => interconnect_to_s02_couplers_BREADY,
S_AXI_bresp(1 downto 0) => interconnect_to_s02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => interconnect_to_s02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => interconnect_to_s02_couplers_RDATA(31 downto 0),
S_AXI_rid(0) => interconnect_to_s02_couplers_RID(0),
S_AXI_rlast => interconnect_to_s02_couplers_RLAST,
S_AXI_rready => interconnect_to_s02_couplers_RREADY,
S_AXI_rresp(1 downto 0) => interconnect_to_s02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => interconnect_to_s02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => interconnect_to_s02_couplers_WDATA(31 downto 0),
S_AXI_wlast => interconnect_to_s02_couplers_WLAST,
S_AXI_wready => interconnect_to_s02_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => interconnect_to_s02_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => interconnect_to_s02_couplers_WVALID
);
xbar: component DemoInterconnect_xbar_0
port map (
aclk => interconnect_ACLK_net,
aresetn => interconnect_ARESETN_net,
m_axi_araddr(223 downto 192) => xbar_to_m06_couplers_ARADDR(223 downto 192),
m_axi_araddr(191 downto 160) => xbar_to_m05_couplers_ARADDR(191 downto 160),
m_axi_araddr(159 downto 128) => xbar_to_m04_couplers_ARADDR(159 downto 128),
m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(20 downto 12) => NLW_xbar_m_axi_arprot_UNCONNECTED(20 downto 12),
m_axi_arprot(11 downto 9) => xbar_to_m03_couplers_ARPROT(11 downto 9),
m_axi_arprot(8 downto 6) => xbar_to_m02_couplers_ARPROT(8 downto 6),
m_axi_arprot(5 downto 3) => xbar_to_m01_couplers_ARPROT(5 downto 3),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arready(6) => xbar_to_m06_couplers_ARREADY,
m_axi_arready(5) => xbar_to_m05_couplers_ARREADY,
m_axi_arready(4) => xbar_to_m04_couplers_ARREADY,
m_axi_arready(3) => xbar_to_m03_couplers_ARREADY,
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY,
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arvalid(6) => xbar_to_m06_couplers_ARVALID(6),
m_axi_arvalid(5) => xbar_to_m05_couplers_ARVALID(5),
m_axi_arvalid(4) => xbar_to_m04_couplers_ARVALID(4),
m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(223 downto 192) => xbar_to_m06_couplers_AWADDR(223 downto 192),
m_axi_awaddr(191 downto 160) => xbar_to_m05_couplers_AWADDR(191 downto 160),
m_axi_awaddr(159 downto 128) => xbar_to_m04_couplers_AWADDR(159 downto 128),
m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(20 downto 12) => NLW_xbar_m_axi_awprot_UNCONNECTED(20 downto 12),
m_axi_awprot(11 downto 9) => xbar_to_m03_couplers_AWPROT(11 downto 9),
m_axi_awprot(8 downto 6) => xbar_to_m02_couplers_AWPROT(8 downto 6),
m_axi_awprot(5 downto 3) => xbar_to_m01_couplers_AWPROT(5 downto 3),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awready(6) => xbar_to_m06_couplers_AWREADY,
m_axi_awready(5) => xbar_to_m05_couplers_AWREADY,
m_axi_awready(4) => xbar_to_m04_couplers_AWREADY,
m_axi_awready(3) => xbar_to_m03_couplers_AWREADY,
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY,
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awvalid(6) => xbar_to_m06_couplers_AWVALID(6),
m_axi_awvalid(5) => xbar_to_m05_couplers_AWVALID(5),
m_axi_awvalid(4) => xbar_to_m04_couplers_AWVALID(4),
m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(6) => xbar_to_m06_couplers_BREADY(6),
m_axi_bready(5) => xbar_to_m05_couplers_BREADY(5),
m_axi_bready(4) => xbar_to_m04_couplers_BREADY(4),
m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(13 downto 12) => xbar_to_m06_couplers_BRESP(1 downto 0),
m_axi_bresp(11 downto 10) => xbar_to_m05_couplers_BRESP(1 downto 0),
m_axi_bresp(9 downto 8) => xbar_to_m04_couplers_BRESP(1 downto 0),
m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(6) => xbar_to_m06_couplers_BVALID,
m_axi_bvalid(5) => xbar_to_m05_couplers_BVALID,
m_axi_bvalid(4) => xbar_to_m04_couplers_BVALID,
m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID,
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID,
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(223 downto 192) => xbar_to_m06_couplers_RDATA(31 downto 0),
m_axi_rdata(191 downto 160) => xbar_to_m05_couplers_RDATA(31 downto 0),
m_axi_rdata(159 downto 128) => xbar_to_m04_couplers_RDATA(31 downto 0),
m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(6) => xbar_to_m06_couplers_RREADY(6),
m_axi_rready(5) => xbar_to_m05_couplers_RREADY(5),
m_axi_rready(4) => xbar_to_m04_couplers_RREADY(4),
m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(13 downto 12) => xbar_to_m06_couplers_RRESP(1 downto 0),
m_axi_rresp(11 downto 10) => xbar_to_m05_couplers_RRESP(1 downto 0),
m_axi_rresp(9 downto 8) => xbar_to_m04_couplers_RRESP(1 downto 0),
m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(6) => xbar_to_m06_couplers_RVALID,
m_axi_rvalid(5) => xbar_to_m05_couplers_RVALID,
m_axi_rvalid(4) => xbar_to_m04_couplers_RVALID,
m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID,
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID,
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(223 downto 192) => xbar_to_m06_couplers_WDATA(223 downto 192),
m_axi_wdata(191 downto 160) => xbar_to_m05_couplers_WDATA(191 downto 160),
m_axi_wdata(159 downto 128) => xbar_to_m04_couplers_WDATA(159 downto 128),
m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(6) => xbar_to_m06_couplers_WREADY,
m_axi_wready(5) => xbar_to_m05_couplers_WREADY,
m_axi_wready(4) => xbar_to_m04_couplers_WREADY,
m_axi_wready(3) => xbar_to_m03_couplers_WREADY,
m_axi_wready(2) => xbar_to_m02_couplers_WREADY,
m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(27 downto 24) => xbar_to_m06_couplers_WSTRB(27 downto 24),
m_axi_wstrb(23 downto 20) => xbar_to_m05_couplers_WSTRB(23 downto 20),
m_axi_wstrb(19 downto 16) => xbar_to_m04_couplers_WSTRB(19 downto 16),
m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(6) => xbar_to_m06_couplers_WVALID(6),
m_axi_wvalid(5) => xbar_to_m05_couplers_WVALID(5),
m_axi_wvalid(4) => xbar_to_m04_couplers_WVALID(4),
m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(95 downto 64) => s02_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_araddr(63 downto 32) => s01_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(8 downto 6) => s02_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arprot(5 downto 3) => s01_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(2) => s02_couplers_to_xbar_ARREADY(2),
s_axi_arready(1) => s01_couplers_to_xbar_ARREADY(1),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(2) => s02_couplers_to_xbar_ARVALID,
s_axi_arvalid(1) => s01_couplers_to_xbar_ARVALID,
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(95 downto 64) => s02_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(63 downto 32) => s01_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(8 downto 6) => s02_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(5 downto 3) => s01_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(2) => s02_couplers_to_xbar_AWREADY(2),
s_axi_awready(1) => s01_couplers_to_xbar_AWREADY(1),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(2) => s02_couplers_to_xbar_AWVALID,
s_axi_awvalid(1) => s01_couplers_to_xbar_AWVALID,
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(2) => s02_couplers_to_xbar_BREADY,
s_axi_bready(1) => s01_couplers_to_xbar_BREADY,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(5 downto 4) => s02_couplers_to_xbar_BRESP(5 downto 4),
s_axi_bresp(3 downto 2) => s01_couplers_to_xbar_BRESP(3 downto 2),
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(2) => s02_couplers_to_xbar_BVALID(2),
s_axi_bvalid(1) => s01_couplers_to_xbar_BVALID(1),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(95 downto 64) => s02_couplers_to_xbar_RDATA(95 downto 64),
s_axi_rdata(63 downto 32) => s01_couplers_to_xbar_RDATA(63 downto 32),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(2) => s02_couplers_to_xbar_RREADY,
s_axi_rready(1) => s01_couplers_to_xbar_RREADY,
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(5 downto 4) => s02_couplers_to_xbar_RRESP(5 downto 4),
s_axi_rresp(3 downto 2) => s01_couplers_to_xbar_RRESP(3 downto 2),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(2) => s02_couplers_to_xbar_RVALID(2),
s_axi_rvalid(1) => s01_couplers_to_xbar_RVALID(1),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(95 downto 64) => s02_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wdata(63 downto 32) => s01_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(2) => s02_couplers_to_xbar_WREADY(2),
s_axi_wready(1) => s01_couplers_to_xbar_WREADY(1),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(11 downto 8) => s02_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wstrb(7 downto 4) => s01_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(2) => s02_couplers_to_xbar_WVALID,
s_axi_wvalid(1) => s01_couplers_to_xbar_WVALID,
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity DemoInterconnect is
port (
LED0_pll_aclk : out STD_LOGIC;
LED1_pll_uart : out STD_LOGIC;
LED2_pll_lock : out STD_LOGIC;
UART_RX_0 : in STD_LOGIC;
UART_RX_1 : in STD_LOGIC;
UART_TX_0 : out STD_LOGIC;
UART_TX_1 : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_miso_1 : in STD_LOGIC;
m_spi_miso_2 : in STD_LOGIC;
m_spi_miso_3 : in STD_LOGIC;
m_spi_mosi : out STD_LOGIC;
m_spi_mosi_1 : out STD_LOGIC;
m_spi_mosi_2 : out STD_LOGIC;
m_spi_mosi_3 : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
m_spi_sclk_1 : out STD_LOGIC;
m_spi_sclk_2 : out STD_LOGIC;
m_spi_sclk_3 : out STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_ss_1 : out STD_LOGIC;
m_spi_ss_2 : out STD_LOGIC;
m_spi_ss_3 : out STD_LOGIC;
sys_clk : in STD_LOGIC;
sys_reset : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of DemoInterconnect : entity is "DemoInterconnect,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=DemoInterconnect,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=25,numReposBlks=14,numNonXlnxBlks=8,numHierBlks=11,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=6,da_board_cnt=5,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of DemoInterconnect : entity is "DemoInterconnect.hwdef";
end DemoInterconnect;
architecture STRUCTURE of DemoInterconnect is
component DemoInterconnect_clk_wiz_0_0 is
port (
reset : in STD_LOGIC;
clk_in1 : in STD_LOGIC;
aclk : out STD_LOGIC;
uart : out STD_LOGIC;
locked : out STD_LOGIC
);
end component DemoInterconnect_clk_wiz_0_0;
component DemoInterconnect_jtag_axi_0_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC;
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC;
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component DemoInterconnect_jtag_axi_0_0;
component DemoInterconnect_mutex_0_0 is
port (
S0_AXI_ACLK : in STD_LOGIC;
S0_AXI_ARESETN : in STD_LOGIC;
S0_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S0_AXI_AWVALID : in STD_LOGIC;
S0_AXI_AWREADY : out STD_LOGIC;
S0_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S0_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S0_AXI_WVALID : in STD_LOGIC;
S0_AXI_WREADY : out STD_LOGIC;
S0_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S0_AXI_BVALID : out STD_LOGIC;
S0_AXI_BREADY : in STD_LOGIC;
S0_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S0_AXI_ARVALID : in STD_LOGIC;
S0_AXI_ARREADY : out STD_LOGIC;
S0_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S0_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S0_AXI_RVALID : out STD_LOGIC;
S0_AXI_RREADY : in STD_LOGIC;
S1_AXI_ACLK : in STD_LOGIC;
S1_AXI_ARESETN : in STD_LOGIC;
S1_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S1_AXI_AWVALID : in STD_LOGIC;
S1_AXI_AWREADY : out STD_LOGIC;
S1_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S1_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S1_AXI_WVALID : in STD_LOGIC;
S1_AXI_WREADY : out STD_LOGIC;
S1_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S1_AXI_BVALID : out STD_LOGIC;
S1_AXI_BREADY : in STD_LOGIC;
S1_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S1_AXI_ARVALID : in STD_LOGIC;
S1_AXI_ARREADY : out STD_LOGIC;
S1_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S1_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S1_AXI_RVALID : out STD_LOGIC;
S1_AXI_RREADY : in STD_LOGIC;
S2_AXI_ACLK : in STD_LOGIC;
S2_AXI_ARESETN : in STD_LOGIC;
S2_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S2_AXI_AWVALID : in STD_LOGIC;
S2_AXI_AWREADY : out STD_LOGIC;
S2_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S2_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S2_AXI_WVALID : in STD_LOGIC;
S2_AXI_WREADY : out STD_LOGIC;
S2_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S2_AXI_BVALID : out STD_LOGIC;
S2_AXI_BREADY : in STD_LOGIC;
S2_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S2_AXI_ARVALID : in STD_LOGIC;
S2_AXI_ARREADY : out STD_LOGIC;
S2_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S2_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S2_AXI_RVALID : out STD_LOGIC;
S2_AXI_RREADY : in STD_LOGIC
);
end component DemoInterconnect_mutex_0_0;
component DemoInterconnect_uart_transceiver_0_0 is
port (
i_Clk : in STD_LOGIC;
i_RX_Serial : in STD_LOGIC;
o_RX_Done : out STD_LOGIC;
o_RX_Byte : out STD_LOGIC_VECTOR ( 7 downto 0 );
i_TX_Load : in STD_LOGIC;
i_TX_Byte : in STD_LOGIC_VECTOR ( 7 downto 0 );
o_TX_Active : out STD_LOGIC;
o_TX_Serial : out STD_LOGIC;
o_TX_Done : out STD_LOGIC
);
end component DemoInterconnect_uart_transceiver_0_0;
component DemoInterconnect_uart_transceiver_0_1 is
port (
i_Clk : in STD_LOGIC;
i_RX_Serial : in STD_LOGIC;
o_RX_Done : out STD_LOGIC;
o_RX_Byte : out STD_LOGIC_VECTOR ( 7 downto 0 );
i_TX_Load : in STD_LOGIC;
i_TX_Byte : in STD_LOGIC_VECTOR ( 7 downto 0 );
o_TX_Active : out STD_LOGIC;
o_TX_Serial : out STD_LOGIC;
o_TX_Done : out STD_LOGIC
);
end component DemoInterconnect_uart_transceiver_0_1;
component DemoInterconnect_axi_spi_master_0_0 is
port (
m_spi_mosi : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_axi_spi_master_0_0;
component DemoInterconnect_axi_spi_master_0_1 is
port (
m_spi_mosi : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_axi_spi_master_0_1;
component DemoInterconnect_axi_spi_master_1_0 is
port (
m_spi_mosi : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_axi_spi_master_1_0;
component DemoInterconnect_axi_spi_master_1_1 is
port (
m_spi_mosi : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_axi_spi_master_1_1;
component DemoInterconnect_ila_0_0 is
port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component DemoInterconnect_ila_0_0;
component DemoInterconnect_internoc_ni_axi_master_0_0 is
port (
if00_data_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
if00_load_in : in STD_LOGIC;
if00_data_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
if00_load_out : out STD_LOGIC;
if00_send_done : in STD_LOGIC;
if00_send_busy : in STD_LOGIC;
m00_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m00_axi_awvalid : out STD_LOGIC;
m00_axi_awready : in STD_LOGIC;
m00_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m00_axi_wvalid : out STD_LOGIC;
m00_axi_wready : in STD_LOGIC;
m00_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m00_axi_bvalid : in STD_LOGIC;
m00_axi_bready : out STD_LOGIC;
m00_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m00_axi_arvalid : out STD_LOGIC;
m00_axi_arready : in STD_LOGIC;
m00_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m00_axi_rvalid : in STD_LOGIC;
m00_axi_rready : out STD_LOGIC;
m00_axi_aclk : in STD_LOGIC;
m00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_internoc_ni_axi_master_0_0;
component DemoInterconnect_internoc_ni_axi_master_1_0 is
port (
if00_data_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
if00_load_in : in STD_LOGIC;
if00_data_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
if00_load_out : out STD_LOGIC;
if00_send_done : in STD_LOGIC;
if00_send_busy : in STD_LOGIC;
m00_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m00_axi_awvalid : out STD_LOGIC;
m00_axi_awready : in STD_LOGIC;
m00_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m00_axi_wvalid : out STD_LOGIC;
m00_axi_wready : in STD_LOGIC;
m00_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m00_axi_bvalid : in STD_LOGIC;
m00_axi_bready : out STD_LOGIC;
m00_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m00_axi_arvalid : out STD_LOGIC;
m00_axi_arready : in STD_LOGIC;
m00_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m00_axi_rvalid : in STD_LOGIC;
m00_axi_rready : out STD_LOGIC;
m00_axi_aclk : in STD_LOGIC;
m00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_internoc_ni_axi_master_1_0;
signal UART_RX_0_1 : STD_LOGIC;
signal UART_RX_1_1 : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M01_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M01_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M01_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M01_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M01_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M02_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M02_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M02_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M02_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M02_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M03_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M03_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M03_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M03_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M03_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M04_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M04_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M04_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M05_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M05_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M05_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M05_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M05_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M05_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M05_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M06_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M06_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M06_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M06_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M06_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M06_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M06_AXI_WVALID : STD_LOGIC;
signal axi_spi_master_0_m_spi_mosi : STD_LOGIC;
signal axi_spi_master_0_m_spi_sclk : STD_LOGIC;
signal axi_spi_master_0_m_spi_ss : STD_LOGIC;
signal axi_spi_master_1_m_spi_mosi : STD_LOGIC;
signal axi_spi_master_1_m_spi_sclk : STD_LOGIC;
signal axi_spi_master_1_m_spi_ss : STD_LOGIC;
signal axi_spi_master_2_m_spi_mosi : STD_LOGIC;
signal axi_spi_master_2_m_spi_sclk : STD_LOGIC;
signal axi_spi_master_2_m_spi_ss : STD_LOGIC;
signal axi_spi_master_3_m_spi_mosi : STD_LOGIC;
signal axi_spi_master_3_m_spi_sclk : STD_LOGIC;
signal axi_spi_master_3_m_spi_ss : STD_LOGIC;
signal clk_wiz_0_clk_out1 : STD_LOGIC;
signal clk_wiz_0_locked : STD_LOGIC;
signal clk_wiz_0_uart : STD_LOGIC;
signal interface_axi_master_0_if00_data_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal interface_axi_master_0_if00_load_out : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_ARREADY : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_ARVALID : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_AWREADY : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_AWVALID : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_BREADY : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_BVALID : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_RREADY : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_RVALID : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_WREADY : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_WVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_ARREADY : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_ARVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_AWREADY : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_AWVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_BREADY : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_BVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_RREADY : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_RVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_WREADY : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_WVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_if00_data_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal internoc_ni_axi_master_1_if00_load_out : STD_LOGIC;
signal jtag_axi_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal jtag_axi_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal jtag_axi_0_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal jtag_axi_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal jtag_axi_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal jtag_axi_0_M_AXI_ARLOCK : STD_LOGIC;
signal jtag_axi_0_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal jtag_axi_0_M_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal jtag_axi_0_M_AXI_ARREADY : STD_LOGIC;
signal jtag_axi_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal jtag_axi_0_M_AXI_ARVALID : STD_LOGIC;
signal jtag_axi_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal jtag_axi_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal jtag_axi_0_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal jtag_axi_0_M_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal jtag_axi_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal jtag_axi_0_M_AXI_AWLOCK : STD_LOGIC;
signal jtag_axi_0_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal jtag_axi_0_M_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal jtag_axi_0_M_AXI_AWREADY : STD_LOGIC;
signal jtag_axi_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal jtag_axi_0_M_AXI_AWVALID : STD_LOGIC;
signal jtag_axi_0_M_AXI_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal jtag_axi_0_M_AXI_BREADY : STD_LOGIC;
signal jtag_axi_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal jtag_axi_0_M_AXI_BVALID : STD_LOGIC;
signal jtag_axi_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal jtag_axi_0_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal jtag_axi_0_M_AXI_RLAST : STD_LOGIC;
signal jtag_axi_0_M_AXI_RREADY : STD_LOGIC;
signal jtag_axi_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal jtag_axi_0_M_AXI_RVALID : STD_LOGIC;
signal jtag_axi_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal jtag_axi_0_M_AXI_WLAST : STD_LOGIC;
signal jtag_axi_0_M_AXI_WREADY : STD_LOGIC;
signal jtag_axi_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal jtag_axi_0_M_AXI_WVALID : STD_LOGIC;
signal \^m_spi_miso_1\ : STD_LOGIC;
signal m_spi_miso_1_1 : STD_LOGIC;
signal m_spi_miso_2_1 : STD_LOGIC;
signal m_spi_miso_3_1 : STD_LOGIC;
signal sys_clk_1 : STD_LOGIC;
signal uart_transceiver_0_o_RX_Byte : STD_LOGIC_VECTOR ( 7 downto 0 );
signal uart_transceiver_0_o_RX_Done : STD_LOGIC;
signal uart_transceiver_0_o_TX_Active : STD_LOGIC;
signal uart_transceiver_0_o_TX_Done : STD_LOGIC;
signal uart_transceiver_0_o_TX_Serial : STD_LOGIC;
signal uart_transceiver_1_o_RX_Byte : STD_LOGIC_VECTOR ( 7 downto 0 );
signal uart_transceiver_1_o_RX_Done : STD_LOGIC;
signal uart_transceiver_1_o_TX_Active : STD_LOGIC;
signal uart_transceiver_1_o_TX_Done : STD_LOGIC;
signal uart_transceiver_1_o_TX_Serial : STD_LOGIC;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of UART_RX_0 : signal is "xilinx.com:signal:data:1.0 DATA.UART_RX_0 DATA";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of UART_RX_0 : signal is "XIL_INTERFACENAME DATA.UART_RX_0, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of UART_RX_1 : signal is "xilinx.com:signal:data:1.0 DATA.UART_RX_1 DATA";
attribute X_INTERFACE_PARAMETER of UART_RX_1 : signal is "XIL_INTERFACENAME DATA.UART_RX_1, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of UART_TX_1 : signal is "xilinx.com:signal:data:1.0 DATA.UART_TX_1 DATA";
attribute X_INTERFACE_PARAMETER of UART_TX_1 : signal is "XIL_INTERFACENAME DATA.UART_TX_1, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_miso : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MISO DATA";
attribute X_INTERFACE_PARAMETER of m_spi_miso : signal is "XIL_INTERFACENAME DATA.M_SPI_MISO, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_miso_1 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MISO_1 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_miso_1 : signal is "XIL_INTERFACENAME DATA.M_SPI_MISO_1, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_miso_2 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MISO_2 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_miso_2 : signal is "XIL_INTERFACENAME DATA.M_SPI_MISO_2, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_miso_3 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MISO_3 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_miso_3 : signal is "XIL_INTERFACENAME DATA.M_SPI_MISO_3, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_mosi : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MOSI DATA";
attribute X_INTERFACE_PARAMETER of m_spi_mosi : signal is "XIL_INTERFACENAME DATA.M_SPI_MOSI, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_mosi_1 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MOSI_1 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_mosi_1 : signal is "XIL_INTERFACENAME DATA.M_SPI_MOSI_1, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_mosi_2 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MOSI_2 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_mosi_2 : signal is "XIL_INTERFACENAME DATA.M_SPI_MOSI_2, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_mosi_3 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MOSI_3 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_mosi_3 : signal is "XIL_INTERFACENAME DATA.M_SPI_MOSI_3, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_sclk : signal is "xilinx.com:signal:clock:1.0 CLK.M_SPI_SCLK CLK";
attribute X_INTERFACE_PARAMETER of m_spi_sclk : signal is "XIL_INTERFACENAME CLK.M_SPI_SCLK, CLK_DOMAIN DemoInterconnect_axi_spi_master_0_0_m_spi_sclk, FREQ_HZ 100000000, PHASE 0.000";
attribute X_INTERFACE_INFO of m_spi_sclk_1 : signal is "xilinx.com:signal:clock:1.0 CLK.M_SPI_SCLK_1 CLK";
attribute X_INTERFACE_PARAMETER of m_spi_sclk_1 : signal is "XIL_INTERFACENAME CLK.M_SPI_SCLK_1, CLK_DOMAIN DemoInterconnect_axi_spi_master_0_1_m_spi_sclk, FREQ_HZ 100000000, PHASE 0.000";
attribute X_INTERFACE_INFO of m_spi_sclk_2 : signal is "xilinx.com:signal:clock:1.0 CLK.M_SPI_SCLK_2 CLK";
attribute X_INTERFACE_PARAMETER of m_spi_sclk_2 : signal is "XIL_INTERFACENAME CLK.M_SPI_SCLK_2, CLK_DOMAIN DemoInterconnect_axi_spi_master_1_0_m_spi_sclk, FREQ_HZ 100000000, PHASE 0.000";
attribute X_INTERFACE_INFO of m_spi_sclk_3 : signal is "xilinx.com:signal:clock:1.0 CLK.M_SPI_SCLK_3 CLK";
attribute X_INTERFACE_PARAMETER of m_spi_sclk_3 : signal is "XIL_INTERFACENAME CLK.M_SPI_SCLK_3, CLK_DOMAIN DemoInterconnect_axi_spi_master_1_1_m_spi_sclk, FREQ_HZ 100000000, PHASE 0.000";
attribute X_INTERFACE_INFO of m_spi_ss : signal is "xilinx.com:signal:clockenable:1.0 CE.M_SPI_SS CE";
attribute X_INTERFACE_PARAMETER of m_spi_ss : signal is "XIL_INTERFACENAME CE.M_SPI_SS, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of m_spi_ss_1 : signal is "xilinx.com:signal:clockenable:1.0 CE.M_SPI_SS_1 CE";
attribute X_INTERFACE_PARAMETER of m_spi_ss_1 : signal is "XIL_INTERFACENAME CE.M_SPI_SS_1, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of m_spi_ss_2 : signal is "xilinx.com:signal:clockenable:1.0 CE.M_SPI_SS_2 CE";
attribute X_INTERFACE_PARAMETER of m_spi_ss_2 : signal is "XIL_INTERFACENAME CE.M_SPI_SS_2, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of m_spi_ss_3 : signal is "xilinx.com:signal:clockenable:1.0 CE.M_SPI_SS_3 CE";
attribute X_INTERFACE_PARAMETER of m_spi_ss_3 : signal is "XIL_INTERFACENAME CE.M_SPI_SS_3, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of sys_clk : signal is "xilinx.com:signal:clock:1.0 CLK.SYS_CLK CLK";
attribute X_INTERFACE_PARAMETER of sys_clk : signal is "XIL_INTERFACENAME CLK.SYS_CLK, ASSOCIATED_RESET sys_reset, CLK_DOMAIN DemoInterconnect_sys_clk, FREQ_HZ 12000000, PHASE 0.000";
attribute X_INTERFACE_INFO of sys_reset : signal is "xilinx.com:signal:reset:1.0 RST.SYS_RESET RST";
attribute X_INTERFACE_PARAMETER of sys_reset : signal is "XIL_INTERFACENAME RST.SYS_RESET, POLARITY ACTIVE_HIGH";
begin
LED0_pll_aclk <= clk_wiz_0_clk_out1;
LED1_pll_uart <= clk_wiz_0_uart;
LED2_pll_lock <= clk_wiz_0_locked;
UART_RX_0_1 <= UART_RX_0;
UART_RX_1_1 <= UART_RX_1;
UART_TX_0 <= uart_transceiver_0_o_TX_Serial;
UART_TX_1 <= uart_transceiver_1_o_TX_Serial;
\^m_spi_miso_1\ <= m_spi_miso;
m_spi_miso_1_1 <= m_spi_miso_1;
m_spi_miso_2_1 <= m_spi_miso_2;
m_spi_miso_3_1 <= m_spi_miso_3;
m_spi_mosi <= axi_spi_master_0_m_spi_mosi;
m_spi_mosi_1 <= axi_spi_master_1_m_spi_mosi;
m_spi_mosi_2 <= axi_spi_master_2_m_spi_mosi;
m_spi_mosi_3 <= axi_spi_master_3_m_spi_mosi;
m_spi_sclk <= axi_spi_master_0_m_spi_sclk;
m_spi_sclk_1 <= axi_spi_master_1_m_spi_sclk;
m_spi_sclk_2 <= axi_spi_master_2_m_spi_sclk;
m_spi_sclk_3 <= axi_spi_master_3_m_spi_sclk;
m_spi_ss <= axi_spi_master_0_m_spi_ss;
m_spi_ss_1 <= axi_spi_master_1_m_spi_ss;
m_spi_ss_2 <= axi_spi_master_2_m_spi_ss;
m_spi_ss_3 <= axi_spi_master_3_m_spi_ss;
sys_clk_1 <= sys_clk;
axi_spi_master_0: component DemoInterconnect_axi_spi_master_0_0
port map (
m_spi_miso => \^m_spi_miso_1\,
m_spi_mosi => axi_spi_master_0_m_spi_mosi,
m_spi_sclk => axi_spi_master_0_m_spi_sclk,
m_spi_ss => axi_spi_master_0_m_spi_ss,
s00_axi_aclk => clk_wiz_0_clk_out1,
s00_axi_araddr(3 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => clk_wiz_0_locked,
s00_axi_arprot(2 downto 0) => axi_interconnect_0_M00_AXI_ARPROT(2 downto 0),
s00_axi_arready => axi_interconnect_0_M00_AXI_ARREADY,
s00_axi_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
s00_axi_awaddr(3 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => axi_interconnect_0_M00_AXI_AWPROT(2 downto 0),
s00_axi_awready => axi_interconnect_0_M00_AXI_AWREADY,
s00_axi_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
s00_axi_bready => axi_interconnect_0_M00_AXI_BREADY,
s00_axi_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
s00_axi_bvalid => axi_interconnect_0_M00_AXI_BVALID,
s00_axi_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
s00_axi_rready => axi_interconnect_0_M00_AXI_RREADY,
s00_axi_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
s00_axi_rvalid => axi_interconnect_0_M00_AXI_RVALID,
s00_axi_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
s00_axi_wready => axi_interconnect_0_M00_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => axi_interconnect_0_M00_AXI_WVALID
);
axi_spi_master_1: component DemoInterconnect_axi_spi_master_0_1
port map (
m_spi_miso => m_spi_miso_1_1,
m_spi_mosi => axi_spi_master_1_m_spi_mosi,
m_spi_sclk => axi_spi_master_1_m_spi_sclk,
m_spi_ss => axi_spi_master_1_m_spi_ss,
s00_axi_aclk => clk_wiz_0_clk_out1,
s00_axi_araddr(3 downto 0) => axi_interconnect_0_M01_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => clk_wiz_0_locked,
s00_axi_arprot(2 downto 0) => axi_interconnect_0_M01_AXI_ARPROT(2 downto 0),
s00_axi_arready => axi_interconnect_0_M01_AXI_ARREADY,
s00_axi_arvalid => axi_interconnect_0_M01_AXI_ARVALID,
s00_axi_awaddr(3 downto 0) => axi_interconnect_0_M01_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => axi_interconnect_0_M01_AXI_AWPROT(2 downto 0),
s00_axi_awready => axi_interconnect_0_M01_AXI_AWREADY,
s00_axi_awvalid => axi_interconnect_0_M01_AXI_AWVALID,
s00_axi_bready => axi_interconnect_0_M01_AXI_BREADY,
s00_axi_bresp(1 downto 0) => axi_interconnect_0_M01_AXI_BRESP(1 downto 0),
s00_axi_bvalid => axi_interconnect_0_M01_AXI_BVALID,
s00_axi_rdata(31 downto 0) => axi_interconnect_0_M01_AXI_RDATA(31 downto 0),
s00_axi_rready => axi_interconnect_0_M01_AXI_RREADY,
s00_axi_rresp(1 downto 0) => axi_interconnect_0_M01_AXI_RRESP(1 downto 0),
s00_axi_rvalid => axi_interconnect_0_M01_AXI_RVALID,
s00_axi_wdata(31 downto 0) => axi_interconnect_0_M01_AXI_WDATA(31 downto 0),
s00_axi_wready => axi_interconnect_0_M01_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => axi_interconnect_0_M01_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => axi_interconnect_0_M01_AXI_WVALID
);
axi_spi_master_2: component DemoInterconnect_axi_spi_master_1_0
port map (
m_spi_miso => m_spi_miso_2_1,
m_spi_mosi => axi_spi_master_2_m_spi_mosi,
m_spi_sclk => axi_spi_master_2_m_spi_sclk,
m_spi_ss => axi_spi_master_2_m_spi_ss,
s00_axi_aclk => clk_wiz_0_clk_out1,
s00_axi_araddr(3 downto 0) => axi_interconnect_0_M02_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => clk_wiz_0_locked,
s00_axi_arprot(2 downto 0) => axi_interconnect_0_M02_AXI_ARPROT(2 downto 0),
s00_axi_arready => axi_interconnect_0_M02_AXI_ARREADY,
s00_axi_arvalid => axi_interconnect_0_M02_AXI_ARVALID,
s00_axi_awaddr(3 downto 0) => axi_interconnect_0_M02_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => axi_interconnect_0_M02_AXI_AWPROT(2 downto 0),
s00_axi_awready => axi_interconnect_0_M02_AXI_AWREADY,
s00_axi_awvalid => axi_interconnect_0_M02_AXI_AWVALID,
s00_axi_bready => axi_interconnect_0_M02_AXI_BREADY,
s00_axi_bresp(1 downto 0) => axi_interconnect_0_M02_AXI_BRESP(1 downto 0),
s00_axi_bvalid => axi_interconnect_0_M02_AXI_BVALID,
s00_axi_rdata(31 downto 0) => axi_interconnect_0_M02_AXI_RDATA(31 downto 0),
s00_axi_rready => axi_interconnect_0_M02_AXI_RREADY,
s00_axi_rresp(1 downto 0) => axi_interconnect_0_M02_AXI_RRESP(1 downto 0),
s00_axi_rvalid => axi_interconnect_0_M02_AXI_RVALID,
s00_axi_wdata(31 downto 0) => axi_interconnect_0_M02_AXI_WDATA(31 downto 0),
s00_axi_wready => axi_interconnect_0_M02_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => axi_interconnect_0_M02_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => axi_interconnect_0_M02_AXI_WVALID
);
axi_spi_master_3: component DemoInterconnect_axi_spi_master_1_1
port map (
m_spi_miso => m_spi_miso_3_1,
m_spi_mosi => axi_spi_master_3_m_spi_mosi,
m_spi_sclk => axi_spi_master_3_m_spi_sclk,
m_spi_ss => axi_spi_master_3_m_spi_ss,
s00_axi_aclk => clk_wiz_0_clk_out1,
s00_axi_araddr(3 downto 0) => axi_interconnect_0_M03_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => clk_wiz_0_locked,
s00_axi_arprot(2 downto 0) => axi_interconnect_0_M03_AXI_ARPROT(2 downto 0),
s00_axi_arready => axi_interconnect_0_M03_AXI_ARREADY,
s00_axi_arvalid => axi_interconnect_0_M03_AXI_ARVALID,
s00_axi_awaddr(3 downto 0) => axi_interconnect_0_M03_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => axi_interconnect_0_M03_AXI_AWPROT(2 downto 0),
s00_axi_awready => axi_interconnect_0_M03_AXI_AWREADY,
s00_axi_awvalid => axi_interconnect_0_M03_AXI_AWVALID,
s00_axi_bready => axi_interconnect_0_M03_AXI_BREADY,
s00_axi_bresp(1 downto 0) => axi_interconnect_0_M03_AXI_BRESP(1 downto 0),
s00_axi_bvalid => axi_interconnect_0_M03_AXI_BVALID,
s00_axi_rdata(31 downto 0) => axi_interconnect_0_M03_AXI_RDATA(31 downto 0),
s00_axi_rready => axi_interconnect_0_M03_AXI_RREADY,
s00_axi_rresp(1 downto 0) => axi_interconnect_0_M03_AXI_RRESP(1 downto 0),
s00_axi_rvalid => axi_interconnect_0_M03_AXI_RVALID,
s00_axi_wdata(31 downto 0) => axi_interconnect_0_M03_AXI_WDATA(31 downto 0),
s00_axi_wready => axi_interconnect_0_M03_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => axi_interconnect_0_M03_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => axi_interconnect_0_M03_AXI_WVALID
);
clk_wiz_0: component DemoInterconnect_clk_wiz_0_0
port map (
aclk => clk_wiz_0_clk_out1,
clk_in1 => sys_clk_1,
locked => clk_wiz_0_locked,
reset => sys_reset,
uart => clk_wiz_0_uart
);
ila_0: component DemoInterconnect_ila_0_0
port map (
clk => clk_wiz_0_clk_out1,
probe0(0) => uart_transceiver_0_o_RX_Done,
probe1(7 downto 0) => uart_transceiver_0_o_RX_Byte(7 downto 0),
probe2(0) => interface_axi_master_0_if00_load_out,
probe3(7 downto 0) => interface_axi_master_0_if00_data_out(7 downto 0)
);
interconnect: entity work.DemoInterconnect_axi_interconnect_0_0
port map (
ACLK => clk_wiz_0_clk_out1,
ARESETN => clk_wiz_0_locked,
M00_ACLK => clk_wiz_0_clk_out1,
M00_ARESETN => clk_wiz_0_locked,
M00_AXI_araddr(31 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arprot(2 downto 0) => axi_interconnect_0_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arready => axi_interconnect_0_M00_AXI_ARREADY,
M00_AXI_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awprot(2 downto 0) => axi_interconnect_0_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awready => axi_interconnect_0_M00_AXI_AWREADY,
M00_AXI_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
M00_AXI_bready => axi_interconnect_0_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_interconnect_0_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready => axi_interconnect_0_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_interconnect_0_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready => axi_interconnect_0_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => axi_interconnect_0_M00_AXI_WVALID,
M01_ACLK => clk_wiz_0_clk_out1,
M01_ARESETN => clk_wiz_0_locked,
M01_AXI_araddr(31 downto 0) => axi_interconnect_0_M01_AXI_ARADDR(31 downto 0),
M01_AXI_arprot(2 downto 0) => axi_interconnect_0_M01_AXI_ARPROT(2 downto 0),
M01_AXI_arready => axi_interconnect_0_M01_AXI_ARREADY,
M01_AXI_arvalid => axi_interconnect_0_M01_AXI_ARVALID,
M01_AXI_awaddr(31 downto 0) => axi_interconnect_0_M01_AXI_AWADDR(31 downto 0),
M01_AXI_awprot(2 downto 0) => axi_interconnect_0_M01_AXI_AWPROT(2 downto 0),
M01_AXI_awready => axi_interconnect_0_M01_AXI_AWREADY,
M01_AXI_awvalid => axi_interconnect_0_M01_AXI_AWVALID,
M01_AXI_bready => axi_interconnect_0_M01_AXI_BREADY,
M01_AXI_bresp(1 downto 0) => axi_interconnect_0_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid => axi_interconnect_0_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => axi_interconnect_0_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready => axi_interconnect_0_M01_AXI_RREADY,
M01_AXI_rresp(1 downto 0) => axi_interconnect_0_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid => axi_interconnect_0_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => axi_interconnect_0_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready => axi_interconnect_0_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => axi_interconnect_0_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid => axi_interconnect_0_M01_AXI_WVALID,
M02_ACLK => clk_wiz_0_clk_out1,
M02_ARESETN => clk_wiz_0_locked,
M02_AXI_araddr(31 downto 0) => axi_interconnect_0_M02_AXI_ARADDR(31 downto 0),
M02_AXI_arprot(2 downto 0) => axi_interconnect_0_M02_AXI_ARPROT(2 downto 0),
M02_AXI_arready => axi_interconnect_0_M02_AXI_ARREADY,
M02_AXI_arvalid => axi_interconnect_0_M02_AXI_ARVALID,
M02_AXI_awaddr(31 downto 0) => axi_interconnect_0_M02_AXI_AWADDR(31 downto 0),
M02_AXI_awprot(2 downto 0) => axi_interconnect_0_M02_AXI_AWPROT(2 downto 0),
M02_AXI_awready => axi_interconnect_0_M02_AXI_AWREADY,
M02_AXI_awvalid => axi_interconnect_0_M02_AXI_AWVALID,
M02_AXI_bready => axi_interconnect_0_M02_AXI_BREADY,
M02_AXI_bresp(1 downto 0) => axi_interconnect_0_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid => axi_interconnect_0_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => axi_interconnect_0_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready => axi_interconnect_0_M02_AXI_RREADY,
M02_AXI_rresp(1 downto 0) => axi_interconnect_0_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid => axi_interconnect_0_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => axi_interconnect_0_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready => axi_interconnect_0_M02_AXI_WREADY,
M02_AXI_wstrb(3 downto 0) => axi_interconnect_0_M02_AXI_WSTRB(3 downto 0),
M02_AXI_wvalid => axi_interconnect_0_M02_AXI_WVALID,
M03_ACLK => clk_wiz_0_clk_out1,
M03_ARESETN => clk_wiz_0_locked,
M03_AXI_araddr(31 downto 0) => axi_interconnect_0_M03_AXI_ARADDR(31 downto 0),
M03_AXI_arprot(2 downto 0) => axi_interconnect_0_M03_AXI_ARPROT(2 downto 0),
M03_AXI_arready => axi_interconnect_0_M03_AXI_ARREADY,
M03_AXI_arvalid => axi_interconnect_0_M03_AXI_ARVALID,
M03_AXI_awaddr(31 downto 0) => axi_interconnect_0_M03_AXI_AWADDR(31 downto 0),
M03_AXI_awprot(2 downto 0) => axi_interconnect_0_M03_AXI_AWPROT(2 downto 0),
M03_AXI_awready => axi_interconnect_0_M03_AXI_AWREADY,
M03_AXI_awvalid => axi_interconnect_0_M03_AXI_AWVALID,
M03_AXI_bready => axi_interconnect_0_M03_AXI_BREADY,
M03_AXI_bresp(1 downto 0) => axi_interconnect_0_M03_AXI_BRESP(1 downto 0),
M03_AXI_bvalid => axi_interconnect_0_M03_AXI_BVALID,
M03_AXI_rdata(31 downto 0) => axi_interconnect_0_M03_AXI_RDATA(31 downto 0),
M03_AXI_rready => axi_interconnect_0_M03_AXI_RREADY,
M03_AXI_rresp(1 downto 0) => axi_interconnect_0_M03_AXI_RRESP(1 downto 0),
M03_AXI_rvalid => axi_interconnect_0_M03_AXI_RVALID,
M03_AXI_wdata(31 downto 0) => axi_interconnect_0_M03_AXI_WDATA(31 downto 0),
M03_AXI_wready => axi_interconnect_0_M03_AXI_WREADY,
M03_AXI_wstrb(3 downto 0) => axi_interconnect_0_M03_AXI_WSTRB(3 downto 0),
M03_AXI_wvalid => axi_interconnect_0_M03_AXI_WVALID,
M04_ACLK => clk_wiz_0_clk_out1,
M04_ARESETN => clk_wiz_0_locked,
M04_AXI_araddr(31 downto 0) => axi_interconnect_0_M04_AXI_ARADDR(31 downto 0),
M04_AXI_arready => axi_interconnect_0_M04_AXI_ARREADY,
M04_AXI_arvalid => axi_interconnect_0_M04_AXI_ARVALID,
M04_AXI_awaddr(31 downto 0) => axi_interconnect_0_M04_AXI_AWADDR(31 downto 0),
M04_AXI_awready => axi_interconnect_0_M04_AXI_AWREADY,
M04_AXI_awvalid => axi_interconnect_0_M04_AXI_AWVALID,
M04_AXI_bready => axi_interconnect_0_M04_AXI_BREADY,
M04_AXI_bresp(1 downto 0) => axi_interconnect_0_M04_AXI_BRESP(1 downto 0),
M04_AXI_bvalid => axi_interconnect_0_M04_AXI_BVALID,
M04_AXI_rdata(31 downto 0) => axi_interconnect_0_M04_AXI_RDATA(31 downto 0),
M04_AXI_rready => axi_interconnect_0_M04_AXI_RREADY,
M04_AXI_rresp(1 downto 0) => axi_interconnect_0_M04_AXI_RRESP(1 downto 0),
M04_AXI_rvalid => axi_interconnect_0_M04_AXI_RVALID,
M04_AXI_wdata(31 downto 0) => axi_interconnect_0_M04_AXI_WDATA(31 downto 0),
M04_AXI_wready => axi_interconnect_0_M04_AXI_WREADY,
M04_AXI_wstrb(3 downto 0) => axi_interconnect_0_M04_AXI_WSTRB(3 downto 0),
M04_AXI_wvalid => axi_interconnect_0_M04_AXI_WVALID,
M05_ACLK => clk_wiz_0_clk_out1,
M05_ARESETN => clk_wiz_0_locked,
M05_AXI_araddr(31 downto 0) => axi_interconnect_0_M05_AXI_ARADDR(31 downto 0),
M05_AXI_arready => axi_interconnect_0_M05_AXI_ARREADY,
M05_AXI_arvalid => axi_interconnect_0_M05_AXI_ARVALID,
M05_AXI_awaddr(31 downto 0) => axi_interconnect_0_M05_AXI_AWADDR(31 downto 0),
M05_AXI_awready => axi_interconnect_0_M05_AXI_AWREADY,
M05_AXI_awvalid => axi_interconnect_0_M05_AXI_AWVALID,
M05_AXI_bready => axi_interconnect_0_M05_AXI_BREADY,
M05_AXI_bresp(1 downto 0) => axi_interconnect_0_M05_AXI_BRESP(1 downto 0),
M05_AXI_bvalid => axi_interconnect_0_M05_AXI_BVALID,
M05_AXI_rdata(31 downto 0) => axi_interconnect_0_M05_AXI_RDATA(31 downto 0),
M05_AXI_rready => axi_interconnect_0_M05_AXI_RREADY,
M05_AXI_rresp(1 downto 0) => axi_interconnect_0_M05_AXI_RRESP(1 downto 0),
M05_AXI_rvalid => axi_interconnect_0_M05_AXI_RVALID,
M05_AXI_wdata(31 downto 0) => axi_interconnect_0_M05_AXI_WDATA(31 downto 0),
M05_AXI_wready => axi_interconnect_0_M05_AXI_WREADY,
M05_AXI_wstrb(3 downto 0) => axi_interconnect_0_M05_AXI_WSTRB(3 downto 0),
M05_AXI_wvalid => axi_interconnect_0_M05_AXI_WVALID,
M06_ACLK => clk_wiz_0_clk_out1,
M06_ARESETN => clk_wiz_0_locked,
M06_AXI_araddr(31 downto 0) => axi_interconnect_0_M06_AXI_ARADDR(31 downto 0),
M06_AXI_arready => axi_interconnect_0_M06_AXI_ARREADY,
M06_AXI_arvalid => axi_interconnect_0_M06_AXI_ARVALID,
M06_AXI_awaddr(31 downto 0) => axi_interconnect_0_M06_AXI_AWADDR(31 downto 0),
M06_AXI_awready => axi_interconnect_0_M06_AXI_AWREADY,
M06_AXI_awvalid => axi_interconnect_0_M06_AXI_AWVALID,
M06_AXI_bready => axi_interconnect_0_M06_AXI_BREADY,
M06_AXI_bresp(1 downto 0) => axi_interconnect_0_M06_AXI_BRESP(1 downto 0),
M06_AXI_bvalid => axi_interconnect_0_M06_AXI_BVALID,
M06_AXI_rdata(31 downto 0) => axi_interconnect_0_M06_AXI_RDATA(31 downto 0),
M06_AXI_rready => axi_interconnect_0_M06_AXI_RREADY,
M06_AXI_rresp(1 downto 0) => axi_interconnect_0_M06_AXI_RRESP(1 downto 0),
M06_AXI_rvalid => axi_interconnect_0_M06_AXI_RVALID,
M06_AXI_wdata(31 downto 0) => axi_interconnect_0_M06_AXI_WDATA(31 downto 0),
M06_AXI_wready => axi_interconnect_0_M06_AXI_WREADY,
M06_AXI_wstrb(3 downto 0) => axi_interconnect_0_M06_AXI_WSTRB(3 downto 0),
M06_AXI_wvalid => axi_interconnect_0_M06_AXI_WVALID,
S00_ACLK => clk_wiz_0_clk_out1,
S00_ARESETN => clk_wiz_0_locked,
S00_AXI_araddr(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_ARADDR(31 downto 0),
S00_AXI_arprot(2 downto 0) => internoc_ni_axi_master_0_M00_AXI_ARPROT(2 downto 0),
S00_AXI_arready => internoc_ni_axi_master_0_M00_AXI_ARREADY,
S00_AXI_arvalid => internoc_ni_axi_master_0_M00_AXI_ARVALID,
S00_AXI_awaddr(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_AWADDR(31 downto 0),
S00_AXI_awprot(2 downto 0) => internoc_ni_axi_master_0_M00_AXI_AWPROT(2 downto 0),
S00_AXI_awready => internoc_ni_axi_master_0_M00_AXI_AWREADY,
S00_AXI_awvalid => internoc_ni_axi_master_0_M00_AXI_AWVALID,
S00_AXI_bready => internoc_ni_axi_master_0_M00_AXI_BREADY,
S00_AXI_bresp(1 downto 0) => internoc_ni_axi_master_0_M00_AXI_BRESP(1 downto 0),
S00_AXI_bvalid => internoc_ni_axi_master_0_M00_AXI_BVALID,
S00_AXI_rdata(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_RDATA(31 downto 0),
S00_AXI_rready => internoc_ni_axi_master_0_M00_AXI_RREADY,
S00_AXI_rresp(1 downto 0) => internoc_ni_axi_master_0_M00_AXI_RRESP(1 downto 0),
S00_AXI_rvalid => internoc_ni_axi_master_0_M00_AXI_RVALID,
S00_AXI_wdata(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_WDATA(31 downto 0),
S00_AXI_wready => internoc_ni_axi_master_0_M00_AXI_WREADY,
S00_AXI_wstrb(3 downto 0) => internoc_ni_axi_master_0_M00_AXI_WSTRB(3 downto 0),
S00_AXI_wvalid => internoc_ni_axi_master_0_M00_AXI_WVALID,
S01_ACLK => clk_wiz_0_clk_out1,
S01_ARESETN => clk_wiz_0_locked,
S01_AXI_araddr(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_ARADDR(31 downto 0),
S01_AXI_arprot(2 downto 0) => internoc_ni_axi_master_1_M00_AXI_ARPROT(2 downto 0),
S01_AXI_arready => internoc_ni_axi_master_1_M00_AXI_ARREADY,
S01_AXI_arvalid => internoc_ni_axi_master_1_M00_AXI_ARVALID,
S01_AXI_awaddr(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_AWADDR(31 downto 0),
S01_AXI_awprot(2 downto 0) => internoc_ni_axi_master_1_M00_AXI_AWPROT(2 downto 0),
S01_AXI_awready => internoc_ni_axi_master_1_M00_AXI_AWREADY,
S01_AXI_awvalid => internoc_ni_axi_master_1_M00_AXI_AWVALID,
S01_AXI_bready => internoc_ni_axi_master_1_M00_AXI_BREADY,
S01_AXI_bresp(1 downto 0) => internoc_ni_axi_master_1_M00_AXI_BRESP(1 downto 0),
S01_AXI_bvalid => internoc_ni_axi_master_1_M00_AXI_BVALID,
S01_AXI_rdata(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_RDATA(31 downto 0),
S01_AXI_rready => internoc_ni_axi_master_1_M00_AXI_RREADY,
S01_AXI_rresp(1 downto 0) => internoc_ni_axi_master_1_M00_AXI_RRESP(1 downto 0),
S01_AXI_rvalid => internoc_ni_axi_master_1_M00_AXI_RVALID,
S01_AXI_wdata(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_WDATA(31 downto 0),
S01_AXI_wready => internoc_ni_axi_master_1_M00_AXI_WREADY,
S01_AXI_wstrb(3 downto 0) => internoc_ni_axi_master_1_M00_AXI_WSTRB(3 downto 0),
S01_AXI_wvalid => internoc_ni_axi_master_1_M00_AXI_WVALID,
S02_ACLK => clk_wiz_0_clk_out1,
S02_ARESETN => clk_wiz_0_locked,
S02_AXI_araddr(31 downto 0) => jtag_axi_0_M_AXI_ARADDR(31 downto 0),
S02_AXI_arburst(1 downto 0) => jtag_axi_0_M_AXI_ARBURST(1 downto 0),
S02_AXI_arcache(3 downto 0) => jtag_axi_0_M_AXI_ARCACHE(3 downto 0),
S02_AXI_arid(0) => jtag_axi_0_M_AXI_ARID(0),
S02_AXI_arlen(7 downto 0) => jtag_axi_0_M_AXI_ARLEN(7 downto 0),
S02_AXI_arlock => jtag_axi_0_M_AXI_ARLOCK,
S02_AXI_arprot(2 downto 0) => jtag_axi_0_M_AXI_ARPROT(2 downto 0),
S02_AXI_arqos(3 downto 0) => jtag_axi_0_M_AXI_ARQOS(3 downto 0),
S02_AXI_arready => jtag_axi_0_M_AXI_ARREADY,
S02_AXI_arsize(2 downto 0) => jtag_axi_0_M_AXI_ARSIZE(2 downto 0),
S02_AXI_arvalid => jtag_axi_0_M_AXI_ARVALID,
S02_AXI_awaddr(31 downto 0) => jtag_axi_0_M_AXI_AWADDR(31 downto 0),
S02_AXI_awburst(1 downto 0) => jtag_axi_0_M_AXI_AWBURST(1 downto 0),
S02_AXI_awcache(3 downto 0) => jtag_axi_0_M_AXI_AWCACHE(3 downto 0),
S02_AXI_awid(0) => jtag_axi_0_M_AXI_AWID(0),
S02_AXI_awlen(7 downto 0) => jtag_axi_0_M_AXI_AWLEN(7 downto 0),
S02_AXI_awlock => jtag_axi_0_M_AXI_AWLOCK,
S02_AXI_awprot(2 downto 0) => jtag_axi_0_M_AXI_AWPROT(2 downto 0),
S02_AXI_awqos(3 downto 0) => jtag_axi_0_M_AXI_AWQOS(3 downto 0),
S02_AXI_awready => jtag_axi_0_M_AXI_AWREADY,
S02_AXI_awsize(2 downto 0) => jtag_axi_0_M_AXI_AWSIZE(2 downto 0),
S02_AXI_awvalid => jtag_axi_0_M_AXI_AWVALID,
S02_AXI_bid(0) => jtag_axi_0_M_AXI_BID(0),
S02_AXI_bready => jtag_axi_0_M_AXI_BREADY,
S02_AXI_bresp(1 downto 0) => jtag_axi_0_M_AXI_BRESP(1 downto 0),
S02_AXI_bvalid => jtag_axi_0_M_AXI_BVALID,
S02_AXI_rdata(31 downto 0) => jtag_axi_0_M_AXI_RDATA(31 downto 0),
S02_AXI_rid(0) => jtag_axi_0_M_AXI_RID(0),
S02_AXI_rlast => jtag_axi_0_M_AXI_RLAST,
S02_AXI_rready => jtag_axi_0_M_AXI_RREADY,
S02_AXI_rresp(1 downto 0) => jtag_axi_0_M_AXI_RRESP(1 downto 0),
S02_AXI_rvalid => jtag_axi_0_M_AXI_RVALID,
S02_AXI_wdata(31 downto 0) => jtag_axi_0_M_AXI_WDATA(31 downto 0),
S02_AXI_wlast => jtag_axi_0_M_AXI_WLAST,
S02_AXI_wready => jtag_axi_0_M_AXI_WREADY,
S02_AXI_wstrb(3 downto 0) => jtag_axi_0_M_AXI_WSTRB(3 downto 0),
S02_AXI_wvalid => jtag_axi_0_M_AXI_WVALID
);
internoc_ni_axi_master_0: component DemoInterconnect_internoc_ni_axi_master_0_0
port map (
if00_data_in(7 downto 0) => uart_transceiver_0_o_RX_Byte(7 downto 0),
if00_data_out(7 downto 0) => interface_axi_master_0_if00_data_out(7 downto 0),
if00_load_in => uart_transceiver_0_o_RX_Done,
if00_load_out => interface_axi_master_0_if00_load_out,
if00_send_busy => uart_transceiver_0_o_TX_Active,
if00_send_done => uart_transceiver_0_o_TX_Done,
m00_axi_aclk => clk_wiz_0_clk_out1,
m00_axi_araddr(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_ARADDR(31 downto 0),
m00_axi_aresetn => clk_wiz_0_locked,
m00_axi_arprot(2 downto 0) => internoc_ni_axi_master_0_M00_AXI_ARPROT(2 downto 0),
m00_axi_arready => internoc_ni_axi_master_0_M00_AXI_ARREADY,
m00_axi_arvalid => internoc_ni_axi_master_0_M00_AXI_ARVALID,
m00_axi_awaddr(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_AWADDR(31 downto 0),
m00_axi_awprot(2 downto 0) => internoc_ni_axi_master_0_M00_AXI_AWPROT(2 downto 0),
m00_axi_awready => internoc_ni_axi_master_0_M00_AXI_AWREADY,
m00_axi_awvalid => internoc_ni_axi_master_0_M00_AXI_AWVALID,
m00_axi_bready => internoc_ni_axi_master_0_M00_AXI_BREADY,
m00_axi_bresp(1 downto 0) => internoc_ni_axi_master_0_M00_AXI_BRESP(1 downto 0),
m00_axi_bvalid => internoc_ni_axi_master_0_M00_AXI_BVALID,
m00_axi_rdata(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_RDATA(31 downto 0),
m00_axi_rready => internoc_ni_axi_master_0_M00_AXI_RREADY,
m00_axi_rresp(1 downto 0) => internoc_ni_axi_master_0_M00_AXI_RRESP(1 downto 0),
m00_axi_rvalid => internoc_ni_axi_master_0_M00_AXI_RVALID,
m00_axi_wdata(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_WDATA(31 downto 0),
m00_axi_wready => internoc_ni_axi_master_0_M00_AXI_WREADY,
m00_axi_wstrb(3 downto 0) => internoc_ni_axi_master_0_M00_AXI_WSTRB(3 downto 0),
m00_axi_wvalid => internoc_ni_axi_master_0_M00_AXI_WVALID
);
internoc_ni_axi_master_1: component DemoInterconnect_internoc_ni_axi_master_1_0
port map (
if00_data_in(7 downto 0) => uart_transceiver_1_o_RX_Byte(7 downto 0),
if00_data_out(7 downto 0) => internoc_ni_axi_master_1_if00_data_out(7 downto 0),
if00_load_in => uart_transceiver_1_o_RX_Done,
if00_load_out => internoc_ni_axi_master_1_if00_load_out,
if00_send_busy => uart_transceiver_1_o_TX_Active,
if00_send_done => uart_transceiver_1_o_TX_Done,
m00_axi_aclk => clk_wiz_0_clk_out1,
m00_axi_araddr(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_ARADDR(31 downto 0),
m00_axi_aresetn => clk_wiz_0_locked,
m00_axi_arprot(2 downto 0) => internoc_ni_axi_master_1_M00_AXI_ARPROT(2 downto 0),
m00_axi_arready => internoc_ni_axi_master_1_M00_AXI_ARREADY,
m00_axi_arvalid => internoc_ni_axi_master_1_M00_AXI_ARVALID,
m00_axi_awaddr(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_AWADDR(31 downto 0),
m00_axi_awprot(2 downto 0) => internoc_ni_axi_master_1_M00_AXI_AWPROT(2 downto 0),
m00_axi_awready => internoc_ni_axi_master_1_M00_AXI_AWREADY,
m00_axi_awvalid => internoc_ni_axi_master_1_M00_AXI_AWVALID,
m00_axi_bready => internoc_ni_axi_master_1_M00_AXI_BREADY,
m00_axi_bresp(1 downto 0) => internoc_ni_axi_master_1_M00_AXI_BRESP(1 downto 0),
m00_axi_bvalid => internoc_ni_axi_master_1_M00_AXI_BVALID,
m00_axi_rdata(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_RDATA(31 downto 0),
m00_axi_rready => internoc_ni_axi_master_1_M00_AXI_RREADY,
m00_axi_rresp(1 downto 0) => internoc_ni_axi_master_1_M00_AXI_RRESP(1 downto 0),
m00_axi_rvalid => internoc_ni_axi_master_1_M00_AXI_RVALID,
m00_axi_wdata(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_WDATA(31 downto 0),
m00_axi_wready => internoc_ni_axi_master_1_M00_AXI_WREADY,
m00_axi_wstrb(3 downto 0) => internoc_ni_axi_master_1_M00_AXI_WSTRB(3 downto 0),
m00_axi_wvalid => internoc_ni_axi_master_1_M00_AXI_WVALID
);
jtag_axi_0: component DemoInterconnect_jtag_axi_0_0
port map (
aclk => clk_wiz_0_clk_out1,
aresetn => clk_wiz_0_locked,
m_axi_araddr(31 downto 0) => jtag_axi_0_M_AXI_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => jtag_axi_0_M_AXI_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => jtag_axi_0_M_AXI_ARCACHE(3 downto 0),
m_axi_arid(0) => jtag_axi_0_M_AXI_ARID(0),
m_axi_arlen(7 downto 0) => jtag_axi_0_M_AXI_ARLEN(7 downto 0),
m_axi_arlock => jtag_axi_0_M_AXI_ARLOCK,
m_axi_arprot(2 downto 0) => jtag_axi_0_M_AXI_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => jtag_axi_0_M_AXI_ARQOS(3 downto 0),
m_axi_arready => jtag_axi_0_M_AXI_ARREADY,
m_axi_arsize(2 downto 0) => jtag_axi_0_M_AXI_ARSIZE(2 downto 0),
m_axi_arvalid => jtag_axi_0_M_AXI_ARVALID,
m_axi_awaddr(31 downto 0) => jtag_axi_0_M_AXI_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => jtag_axi_0_M_AXI_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => jtag_axi_0_M_AXI_AWCACHE(3 downto 0),
m_axi_awid(0) => jtag_axi_0_M_AXI_AWID(0),
m_axi_awlen(7 downto 0) => jtag_axi_0_M_AXI_AWLEN(7 downto 0),
m_axi_awlock => jtag_axi_0_M_AXI_AWLOCK,
m_axi_awprot(2 downto 0) => jtag_axi_0_M_AXI_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => jtag_axi_0_M_AXI_AWQOS(3 downto 0),
m_axi_awready => jtag_axi_0_M_AXI_AWREADY,
m_axi_awsize(2 downto 0) => jtag_axi_0_M_AXI_AWSIZE(2 downto 0),
m_axi_awvalid => jtag_axi_0_M_AXI_AWVALID,
m_axi_bid(0) => jtag_axi_0_M_AXI_BID(0),
m_axi_bready => jtag_axi_0_M_AXI_BREADY,
m_axi_bresp(1 downto 0) => jtag_axi_0_M_AXI_BRESP(1 downto 0),
m_axi_bvalid => jtag_axi_0_M_AXI_BVALID,
m_axi_rdata(31 downto 0) => jtag_axi_0_M_AXI_RDATA(31 downto 0),
m_axi_rid(0) => jtag_axi_0_M_AXI_RID(0),
m_axi_rlast => jtag_axi_0_M_AXI_RLAST,
m_axi_rready => jtag_axi_0_M_AXI_RREADY,
m_axi_rresp(1 downto 0) => jtag_axi_0_M_AXI_RRESP(1 downto 0),
m_axi_rvalid => jtag_axi_0_M_AXI_RVALID,
m_axi_wdata(31 downto 0) => jtag_axi_0_M_AXI_WDATA(31 downto 0),
m_axi_wlast => jtag_axi_0_M_AXI_WLAST,
m_axi_wready => jtag_axi_0_M_AXI_WREADY,
m_axi_wstrb(3 downto 0) => jtag_axi_0_M_AXI_WSTRB(3 downto 0),
m_axi_wvalid => jtag_axi_0_M_AXI_WVALID
);
master_comm_mutex: component DemoInterconnect_mutex_0_0
port map (
S0_AXI_ACLK => clk_wiz_0_clk_out1,
S0_AXI_ARADDR(31 downto 0) => axi_interconnect_0_M04_AXI_ARADDR(31 downto 0),
S0_AXI_ARESETN => clk_wiz_0_locked,
S0_AXI_ARREADY => axi_interconnect_0_M04_AXI_ARREADY,
S0_AXI_ARVALID => axi_interconnect_0_M04_AXI_ARVALID,
S0_AXI_AWADDR(31 downto 0) => axi_interconnect_0_M04_AXI_AWADDR(31 downto 0),
S0_AXI_AWREADY => axi_interconnect_0_M04_AXI_AWREADY,
S0_AXI_AWVALID => axi_interconnect_0_M04_AXI_AWVALID,
S0_AXI_BREADY => axi_interconnect_0_M04_AXI_BREADY,
S0_AXI_BRESP(1 downto 0) => axi_interconnect_0_M04_AXI_BRESP(1 downto 0),
S0_AXI_BVALID => axi_interconnect_0_M04_AXI_BVALID,
S0_AXI_RDATA(31 downto 0) => axi_interconnect_0_M04_AXI_RDATA(31 downto 0),
S0_AXI_RREADY => axi_interconnect_0_M04_AXI_RREADY,
S0_AXI_RRESP(1 downto 0) => axi_interconnect_0_M04_AXI_RRESP(1 downto 0),
S0_AXI_RVALID => axi_interconnect_0_M04_AXI_RVALID,
S0_AXI_WDATA(31 downto 0) => axi_interconnect_0_M04_AXI_WDATA(31 downto 0),
S0_AXI_WREADY => axi_interconnect_0_M04_AXI_WREADY,
S0_AXI_WSTRB(3 downto 0) => axi_interconnect_0_M04_AXI_WSTRB(3 downto 0),
S0_AXI_WVALID => axi_interconnect_0_M04_AXI_WVALID,
S1_AXI_ACLK => clk_wiz_0_clk_out1,
S1_AXI_ARADDR(31 downto 0) => axi_interconnect_0_M05_AXI_ARADDR(31 downto 0),
S1_AXI_ARESETN => clk_wiz_0_locked,
S1_AXI_ARREADY => axi_interconnect_0_M05_AXI_ARREADY,
S1_AXI_ARVALID => axi_interconnect_0_M05_AXI_ARVALID,
S1_AXI_AWADDR(31 downto 0) => axi_interconnect_0_M05_AXI_AWADDR(31 downto 0),
S1_AXI_AWREADY => axi_interconnect_0_M05_AXI_AWREADY,
S1_AXI_AWVALID => axi_interconnect_0_M05_AXI_AWVALID,
S1_AXI_BREADY => axi_interconnect_0_M05_AXI_BREADY,
S1_AXI_BRESP(1 downto 0) => axi_interconnect_0_M05_AXI_BRESP(1 downto 0),
S1_AXI_BVALID => axi_interconnect_0_M05_AXI_BVALID,
S1_AXI_RDATA(31 downto 0) => axi_interconnect_0_M05_AXI_RDATA(31 downto 0),
S1_AXI_RREADY => axi_interconnect_0_M05_AXI_RREADY,
S1_AXI_RRESP(1 downto 0) => axi_interconnect_0_M05_AXI_RRESP(1 downto 0),
S1_AXI_RVALID => axi_interconnect_0_M05_AXI_RVALID,
S1_AXI_WDATA(31 downto 0) => axi_interconnect_0_M05_AXI_WDATA(31 downto 0),
S1_AXI_WREADY => axi_interconnect_0_M05_AXI_WREADY,
S1_AXI_WSTRB(3 downto 0) => axi_interconnect_0_M05_AXI_WSTRB(3 downto 0),
S1_AXI_WVALID => axi_interconnect_0_M05_AXI_WVALID,
S2_AXI_ACLK => clk_wiz_0_clk_out1,
S2_AXI_ARADDR(31 downto 0) => axi_interconnect_0_M06_AXI_ARADDR(31 downto 0),
S2_AXI_ARESETN => clk_wiz_0_locked,
S2_AXI_ARREADY => axi_interconnect_0_M06_AXI_ARREADY,
S2_AXI_ARVALID => axi_interconnect_0_M06_AXI_ARVALID,
S2_AXI_AWADDR(31 downto 0) => axi_interconnect_0_M06_AXI_AWADDR(31 downto 0),
S2_AXI_AWREADY => axi_interconnect_0_M06_AXI_AWREADY,
S2_AXI_AWVALID => axi_interconnect_0_M06_AXI_AWVALID,
S2_AXI_BREADY => axi_interconnect_0_M06_AXI_BREADY,
S2_AXI_BRESP(1 downto 0) => axi_interconnect_0_M06_AXI_BRESP(1 downto 0),
S2_AXI_BVALID => axi_interconnect_0_M06_AXI_BVALID,
S2_AXI_RDATA(31 downto 0) => axi_interconnect_0_M06_AXI_RDATA(31 downto 0),
S2_AXI_RREADY => axi_interconnect_0_M06_AXI_RREADY,
S2_AXI_RRESP(1 downto 0) => axi_interconnect_0_M06_AXI_RRESP(1 downto 0),
S2_AXI_RVALID => axi_interconnect_0_M06_AXI_RVALID,
S2_AXI_WDATA(31 downto 0) => axi_interconnect_0_M06_AXI_WDATA(31 downto 0),
S2_AXI_WREADY => axi_interconnect_0_M06_AXI_WREADY,
S2_AXI_WSTRB(3 downto 0) => axi_interconnect_0_M06_AXI_WSTRB(3 downto 0),
S2_AXI_WVALID => axi_interconnect_0_M06_AXI_WVALID
);
uart_transceiver_0: component DemoInterconnect_uart_transceiver_0_0
port map (
i_Clk => clk_wiz_0_uart,
i_RX_Serial => UART_RX_0_1,
i_TX_Byte(7 downto 0) => interface_axi_master_0_if00_data_out(7 downto 0),
i_TX_Load => interface_axi_master_0_if00_load_out,
o_RX_Byte(7 downto 0) => uart_transceiver_0_o_RX_Byte(7 downto 0),
o_RX_Done => uart_transceiver_0_o_RX_Done,
o_TX_Active => uart_transceiver_0_o_TX_Active,
o_TX_Done => uart_transceiver_0_o_TX_Done,
o_TX_Serial => uart_transceiver_0_o_TX_Serial
);
uart_transceiver_1: component DemoInterconnect_uart_transceiver_0_1
port map (
i_Clk => clk_wiz_0_uart,
i_RX_Serial => UART_RX_1_1,
i_TX_Byte(7 downto 0) => internoc_ni_axi_master_1_if00_data_out(7 downto 0),
i_TX_Load => internoc_ni_axi_master_1_if00_load_out,
o_RX_Byte(7 downto 0) => uart_transceiver_1_o_RX_Byte(7 downto 0),
o_RX_Done => uart_transceiver_1_o_RX_Done,
o_TX_Active => uart_transceiver_1_o_TX_Active,
o_TX_Done => uart_transceiver_1_o_TX_Done,
o_TX_Serial => uart_transceiver_1_o_TX_Serial
);
end STRUCTURE;
|
--Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct 4 19:58:22 MDT 2017
--Date : Fri Nov 17 16:04:47 2017
--Host : egk-pc running 64-bit major release (build 9200)
--Command : generate_target DemoInterconnect.bd
--Design : DemoInterconnect
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_4EB6IN is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_4EB6IN;
architecture STRUCTURE of m00_couplers_imp_4EB6IN is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m00_couplers_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m00_couplers_to_m00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m00_couplers_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m00_couplers_to_m00_couplers_AWVALID;
M_AXI_bready <= m00_couplers_to_m00_couplers_BREADY;
M_AXI_rready <= m00_couplers_to_m00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m00_couplers_to_m00_couplers_WVALID;
S_AXI_arready <= m00_couplers_to_m00_couplers_ARREADY;
S_AXI_awready <= m00_couplers_to_m00_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_m00_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_m00_couplers_RVALID;
S_AXI_wready <= m00_couplers_to_m00_couplers_WREADY;
m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_m00_couplers_ARREADY <= M_AXI_arready;
m00_couplers_to_m00_couplers_ARVALID <= S_AXI_arvalid;
m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_m00_couplers_AWREADY <= M_AXI_awready;
m00_couplers_to_m00_couplers_AWVALID <= S_AXI_awvalid;
m00_couplers_to_m00_couplers_BREADY <= S_AXI_bready;
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID <= M_AXI_bvalid;
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY <= S_AXI_rready;
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID <= M_AXI_rvalid;
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_1SL2GIW is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m01_couplers_imp_1SL2GIW;
architecture STRUCTURE of m01_couplers_imp_1SL2GIW is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m01_couplers_to_m01_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m01_couplers_to_m01_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m01_couplers_to_m01_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m01_couplers_to_m01_couplers_AWVALID;
M_AXI_bready <= m01_couplers_to_m01_couplers_BREADY;
M_AXI_rready <= m01_couplers_to_m01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m01_couplers_to_m01_couplers_WVALID;
S_AXI_arready <= m01_couplers_to_m01_couplers_ARREADY;
S_AXI_awready <= m01_couplers_to_m01_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m01_couplers_to_m01_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m01_couplers_to_m01_couplers_RVALID;
S_AXI_wready <= m01_couplers_to_m01_couplers_WREADY;
m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m01_couplers_to_m01_couplers_ARREADY <= M_AXI_arready;
m01_couplers_to_m01_couplers_ARVALID <= S_AXI_arvalid;
m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m01_couplers_to_m01_couplers_AWREADY <= M_AXI_awready;
m01_couplers_to_m01_couplers_AWVALID <= S_AXI_awvalid;
m01_couplers_to_m01_couplers_BREADY <= S_AXI_bready;
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID <= M_AXI_bvalid;
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY <= S_AXI_rready;
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID <= M_AXI_rvalid;
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY <= M_AXI_wready;
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_7DG2C0 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m02_couplers_imp_7DG2C0;
architecture STRUCTURE of m02_couplers_imp_7DG2C0 is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m02_couplers_to_m02_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m02_couplers_to_m02_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m02_couplers_to_m02_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m02_couplers_to_m02_couplers_AWVALID;
M_AXI_bready <= m02_couplers_to_m02_couplers_BREADY;
M_AXI_rready <= m02_couplers_to_m02_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m02_couplers_to_m02_couplers_WVALID;
S_AXI_arready <= m02_couplers_to_m02_couplers_ARREADY;
S_AXI_awready <= m02_couplers_to_m02_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m02_couplers_to_m02_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m02_couplers_to_m02_couplers_RVALID;
S_AXI_wready <= m02_couplers_to_m02_couplers_WREADY;
m02_couplers_to_m02_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m02_couplers_to_m02_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m02_couplers_to_m02_couplers_ARREADY <= M_AXI_arready;
m02_couplers_to_m02_couplers_ARVALID <= S_AXI_arvalid;
m02_couplers_to_m02_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m02_couplers_to_m02_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m02_couplers_to_m02_couplers_AWREADY <= M_AXI_awready;
m02_couplers_to_m02_couplers_AWVALID <= S_AXI_awvalid;
m02_couplers_to_m02_couplers_BREADY <= S_AXI_bready;
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID <= M_AXI_bvalid;
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY <= S_AXI_rready;
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID <= M_AXI_rvalid;
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY <= M_AXI_wready;
m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m02_couplers_to_m02_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m03_couplers_imp_1YCPS1Z is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m03_couplers_imp_1YCPS1Z;
architecture STRUCTURE of m03_couplers_imp_1YCPS1Z is
signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m03_couplers_to_m03_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m03_couplers_to_m03_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m03_couplers_to_m03_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m03_couplers_to_m03_couplers_AWVALID;
M_AXI_bready <= m03_couplers_to_m03_couplers_BREADY;
M_AXI_rready <= m03_couplers_to_m03_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m03_couplers_to_m03_couplers_WVALID;
S_AXI_arready <= m03_couplers_to_m03_couplers_ARREADY;
S_AXI_awready <= m03_couplers_to_m03_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m03_couplers_to_m03_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m03_couplers_to_m03_couplers_RVALID;
S_AXI_wready <= m03_couplers_to_m03_couplers_WREADY;
m03_couplers_to_m03_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m03_couplers_to_m03_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m03_couplers_to_m03_couplers_ARREADY <= M_AXI_arready;
m03_couplers_to_m03_couplers_ARVALID <= S_AXI_arvalid;
m03_couplers_to_m03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m03_couplers_to_m03_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m03_couplers_to_m03_couplers_AWREADY <= M_AXI_awready;
m03_couplers_to_m03_couplers_AWVALID <= S_AXI_awvalid;
m03_couplers_to_m03_couplers_BREADY <= S_AXI_bready;
m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m03_couplers_to_m03_couplers_BVALID <= M_AXI_bvalid;
m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m03_couplers_to_m03_couplers_RREADY <= S_AXI_rready;
m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m03_couplers_to_m03_couplers_RVALID <= M_AXI_rvalid;
m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m03_couplers_to_m03_couplers_WREADY <= M_AXI_wready;
m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m03_couplers_to_m03_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m04_couplers_imp_ACM7VL is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m04_couplers_imp_ACM7VL;
architecture STRUCTURE of m04_couplers_imp_ACM7VL is
signal m04_couplers_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_ARREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_ARVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_AWREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_BVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_RREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_RVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_WREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_m04_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m04_couplers_to_m04_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m04_couplers_to_m04_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m04_couplers_to_m04_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m04_couplers_to_m04_couplers_AWVALID;
M_AXI_bready <= m04_couplers_to_m04_couplers_BREADY;
M_AXI_rready <= m04_couplers_to_m04_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m04_couplers_to_m04_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m04_couplers_to_m04_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m04_couplers_to_m04_couplers_WVALID;
S_AXI_arready <= m04_couplers_to_m04_couplers_ARREADY;
S_AXI_awready <= m04_couplers_to_m04_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m04_couplers_to_m04_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m04_couplers_to_m04_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m04_couplers_to_m04_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m04_couplers_to_m04_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m04_couplers_to_m04_couplers_RVALID;
S_AXI_wready <= m04_couplers_to_m04_couplers_WREADY;
m04_couplers_to_m04_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m04_couplers_to_m04_couplers_ARREADY <= M_AXI_arready;
m04_couplers_to_m04_couplers_ARVALID <= S_AXI_arvalid;
m04_couplers_to_m04_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m04_couplers_to_m04_couplers_AWREADY <= M_AXI_awready;
m04_couplers_to_m04_couplers_AWVALID <= S_AXI_awvalid;
m04_couplers_to_m04_couplers_BREADY <= S_AXI_bready;
m04_couplers_to_m04_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m04_couplers_to_m04_couplers_BVALID <= M_AXI_bvalid;
m04_couplers_to_m04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m04_couplers_to_m04_couplers_RREADY <= S_AXI_rready;
m04_couplers_to_m04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m04_couplers_to_m04_couplers_RVALID <= M_AXI_rvalid;
m04_couplers_to_m04_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m04_couplers_to_m04_couplers_WREADY <= M_AXI_wready;
m04_couplers_to_m04_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m04_couplers_to_m04_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m05_couplers_imp_1HWY5FA is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m05_couplers_imp_1HWY5FA;
architecture STRUCTURE of m05_couplers_imp_1HWY5FA is
signal m05_couplers_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_ARREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_ARVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_AWREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_AWVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_BREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_BVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_RREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_RVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_WREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_m05_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m05_couplers_to_m05_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m05_couplers_to_m05_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m05_couplers_to_m05_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m05_couplers_to_m05_couplers_AWVALID;
M_AXI_bready <= m05_couplers_to_m05_couplers_BREADY;
M_AXI_rready <= m05_couplers_to_m05_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m05_couplers_to_m05_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m05_couplers_to_m05_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m05_couplers_to_m05_couplers_WVALID;
S_AXI_arready <= m05_couplers_to_m05_couplers_ARREADY;
S_AXI_awready <= m05_couplers_to_m05_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m05_couplers_to_m05_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m05_couplers_to_m05_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m05_couplers_to_m05_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m05_couplers_to_m05_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m05_couplers_to_m05_couplers_RVALID;
S_AXI_wready <= m05_couplers_to_m05_couplers_WREADY;
m05_couplers_to_m05_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m05_couplers_to_m05_couplers_ARREADY <= M_AXI_arready;
m05_couplers_to_m05_couplers_ARVALID <= S_AXI_arvalid;
m05_couplers_to_m05_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m05_couplers_to_m05_couplers_AWREADY <= M_AXI_awready;
m05_couplers_to_m05_couplers_AWVALID <= S_AXI_awvalid;
m05_couplers_to_m05_couplers_BREADY <= S_AXI_bready;
m05_couplers_to_m05_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m05_couplers_to_m05_couplers_BVALID <= M_AXI_bvalid;
m05_couplers_to_m05_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m05_couplers_to_m05_couplers_RREADY <= S_AXI_rready;
m05_couplers_to_m05_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m05_couplers_to_m05_couplers_RVALID <= M_AXI_rvalid;
m05_couplers_to_m05_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m05_couplers_to_m05_couplers_WREADY <= M_AXI_wready;
m05_couplers_to_m05_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m05_couplers_to_m05_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m06_couplers_imp_DBR4EM is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m06_couplers_imp_DBR4EM;
architecture STRUCTURE of m06_couplers_imp_DBR4EM is
signal m06_couplers_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_ARREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_ARVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_AWREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_AWVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_BREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_BVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_RREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_RVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_WREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_m06_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m06_couplers_to_m06_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m06_couplers_to_m06_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m06_couplers_to_m06_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m06_couplers_to_m06_couplers_AWVALID;
M_AXI_bready <= m06_couplers_to_m06_couplers_BREADY;
M_AXI_rready <= m06_couplers_to_m06_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m06_couplers_to_m06_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m06_couplers_to_m06_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m06_couplers_to_m06_couplers_WVALID;
S_AXI_arready <= m06_couplers_to_m06_couplers_ARREADY;
S_AXI_awready <= m06_couplers_to_m06_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m06_couplers_to_m06_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m06_couplers_to_m06_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m06_couplers_to_m06_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m06_couplers_to_m06_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m06_couplers_to_m06_couplers_RVALID;
S_AXI_wready <= m06_couplers_to_m06_couplers_WREADY;
m06_couplers_to_m06_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m06_couplers_to_m06_couplers_ARREADY <= M_AXI_arready;
m06_couplers_to_m06_couplers_ARVALID <= S_AXI_arvalid;
m06_couplers_to_m06_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m06_couplers_to_m06_couplers_AWREADY <= M_AXI_awready;
m06_couplers_to_m06_couplers_AWVALID <= S_AXI_awvalid;
m06_couplers_to_m06_couplers_BREADY <= S_AXI_bready;
m06_couplers_to_m06_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m06_couplers_to_m06_couplers_BVALID <= M_AXI_bvalid;
m06_couplers_to_m06_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m06_couplers_to_m06_couplers_RREADY <= S_AXI_rready;
m06_couplers_to_m06_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m06_couplers_to_m06_couplers_RVALID <= M_AXI_rvalid;
m06_couplers_to_m06_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m06_couplers_to_m06_couplers_WREADY <= M_AXI_wready;
m06_couplers_to_m06_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m06_couplers_to_m06_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_7XIH8P is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_7XIH8P;
architecture STRUCTURE of s00_couplers_imp_7XIH8P is
signal s00_couplers_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARREADY : STD_LOGIC;
signal s00_couplers_to_s00_couplers_ARVALID : STD_LOGIC;
signal s00_couplers_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_AWREADY : STD_LOGIC;
signal s00_couplers_to_s00_couplers_AWVALID : STD_LOGIC;
signal s00_couplers_to_s00_couplers_BREADY : STD_LOGIC;
signal s00_couplers_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_BVALID : STD_LOGIC;
signal s00_couplers_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_RREADY : STD_LOGIC;
signal s00_couplers_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_RVALID : STD_LOGIC;
signal s00_couplers_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_WREADY : STD_LOGIC;
signal s00_couplers_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= s00_couplers_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= s00_couplers_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= s00_couplers_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= s00_couplers_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= s00_couplers_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= s00_couplers_to_s00_couplers_AWVALID;
M_AXI_bready <= s00_couplers_to_s00_couplers_BREADY;
M_AXI_rready <= s00_couplers_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= s00_couplers_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= s00_couplers_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= s00_couplers_to_s00_couplers_WVALID;
S_AXI_arready <= s00_couplers_to_s00_couplers_ARREADY;
S_AXI_awready <= s00_couplers_to_s00_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= s00_couplers_to_s00_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_s00_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_s00_couplers_RVALID;
S_AXI_wready <= s00_couplers_to_s00_couplers_WREADY;
s00_couplers_to_s00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_s00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_s00_couplers_ARREADY <= M_AXI_arready;
s00_couplers_to_s00_couplers_ARVALID <= S_AXI_arvalid;
s00_couplers_to_s00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_s00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_s00_couplers_AWREADY <= M_AXI_awready;
s00_couplers_to_s00_couplers_AWVALID <= S_AXI_awvalid;
s00_couplers_to_s00_couplers_BREADY <= S_AXI_bready;
s00_couplers_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s00_couplers_to_s00_couplers_BVALID <= M_AXI_bvalid;
s00_couplers_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s00_couplers_to_s00_couplers_RREADY <= S_AXI_rready;
s00_couplers_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s00_couplers_to_s00_couplers_RVALID <= M_AXI_rvalid;
s00_couplers_to_s00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_s00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_s00_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s01_couplers_imp_1XSI6OU is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s01_couplers_imp_1XSI6OU;
architecture STRUCTURE of s01_couplers_imp_1XSI6OU is
signal s01_couplers_to_s01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_ARREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_ARVALID : STD_LOGIC;
signal s01_couplers_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_AWREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_AWVALID : STD_LOGIC;
signal s01_couplers_to_s01_couplers_BREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_BVALID : STD_LOGIC;
signal s01_couplers_to_s01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_RREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_RVALID : STD_LOGIC;
signal s01_couplers_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_WREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= s01_couplers_to_s01_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= s01_couplers_to_s01_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= s01_couplers_to_s01_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= s01_couplers_to_s01_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= s01_couplers_to_s01_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= s01_couplers_to_s01_couplers_AWVALID;
M_AXI_bready <= s01_couplers_to_s01_couplers_BREADY;
M_AXI_rready <= s01_couplers_to_s01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= s01_couplers_to_s01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= s01_couplers_to_s01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= s01_couplers_to_s01_couplers_WVALID;
S_AXI_arready <= s01_couplers_to_s01_couplers_ARREADY;
S_AXI_awready <= s01_couplers_to_s01_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= s01_couplers_to_s01_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= s01_couplers_to_s01_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= s01_couplers_to_s01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= s01_couplers_to_s01_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= s01_couplers_to_s01_couplers_RVALID;
S_AXI_wready <= s01_couplers_to_s01_couplers_WREADY;
s01_couplers_to_s01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s01_couplers_to_s01_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s01_couplers_to_s01_couplers_ARREADY <= M_AXI_arready;
s01_couplers_to_s01_couplers_ARVALID <= S_AXI_arvalid;
s01_couplers_to_s01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s01_couplers_to_s01_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s01_couplers_to_s01_couplers_AWREADY <= M_AXI_awready;
s01_couplers_to_s01_couplers_AWVALID <= S_AXI_awvalid;
s01_couplers_to_s01_couplers_BREADY <= S_AXI_bready;
s01_couplers_to_s01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s01_couplers_to_s01_couplers_BVALID <= M_AXI_bvalid;
s01_couplers_to_s01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s01_couplers_to_s01_couplers_RREADY <= S_AXI_rready;
s01_couplers_to_s01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s01_couplers_to_s01_couplers_RVALID <= M_AXI_rvalid;
s01_couplers_to_s01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s01_couplers_to_s01_couplers_WREADY <= M_AXI_wready;
s01_couplers_to_s01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s01_couplers_to_s01_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s02_couplers_imp_2QLUHY is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC;
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC;
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s02_couplers_imp_2QLUHY;
architecture STRUCTURE of s02_couplers_imp_2QLUHY is
component DemoInterconnect_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component DemoInterconnect_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_pc_to_s02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s02_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s02_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s02_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s02_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s02_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s02_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s02_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s02_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s02_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s02_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s02_couplers_WVALID : STD_LOGIC;
signal s02_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s02_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s02_couplers_to_auto_pc_ARLOCK : STD_LOGIC;
signal s02_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s02_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s02_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s02_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s02_couplers_to_auto_pc_AWLOCK : STD_LOGIC;
signal s02_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s02_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s02_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s02_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s02_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s02_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s02_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s02_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s02_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s02_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s02_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s02_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s02_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s02_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s02_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s02_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s02_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s02_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s02_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s02_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s02_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= s02_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s02_couplers_to_auto_pc_AWREADY;
S_AXI_bid(0) <= s02_couplers_to_auto_pc_BID(0);
S_AXI_bresp(1 downto 0) <= s02_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s02_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s02_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(0) <= s02_couplers_to_auto_pc_RID(0);
S_AXI_rlast <= s02_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s02_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s02_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s02_couplers_to_auto_pc_WREADY;
auto_pc_to_s02_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s02_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s02_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s02_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s02_couplers_WREADY <= M_AXI_wready;
s02_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s02_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s02_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s02_couplers_to_auto_pc_ARID(0) <= S_AXI_arid(0);
s02_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s02_couplers_to_auto_pc_ARLOCK <= S_AXI_arlock;
s02_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s02_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s02_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s02_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s02_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s02_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s02_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s02_couplers_to_auto_pc_AWID(0) <= S_AXI_awid(0);
s02_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s02_couplers_to_auto_pc_AWLOCK <= S_AXI_awlock;
s02_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s02_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s02_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s02_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s02_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s02_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s02_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s02_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s02_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s02_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component DemoInterconnect_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1,
m_axi_araddr(31 downto 0) => auto_pc_to_s02_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s02_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s02_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s02_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s02_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s02_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s02_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s02_couplers_AWVALID,
m_axi_bready => auto_pc_to_s02_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s02_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s02_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s02_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s02_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s02_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s02_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s02_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s02_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s02_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s02_couplers_WVALID,
s_axi_araddr(31 downto 0) => s02_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s02_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s02_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(0) => s02_couplers_to_auto_pc_ARID(0),
s_axi_arlen(7 downto 0) => s02_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => s02_couplers_to_auto_pc_ARLOCK,
s_axi_arprot(2 downto 0) => s02_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s02_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s02_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s02_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s02_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s02_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s02_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s02_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(0) => s02_couplers_to_auto_pc_AWID(0),
s_axi_awlen(7 downto 0) => s02_couplers_to_auto_pc_AWLEN(7 downto 0),
s_axi_awlock(0) => s02_couplers_to_auto_pc_AWLOCK,
s_axi_awprot(2 downto 0) => s02_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s02_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s02_couplers_to_auto_pc_AWREADY,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s02_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s02_couplers_to_auto_pc_AWVALID,
s_axi_bid(0) => s02_couplers_to_auto_pc_BID(0),
s_axi_bready => s02_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s02_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s02_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s02_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(0) => s02_couplers_to_auto_pc_RID(0),
s_axi_rlast => s02_couplers_to_auto_pc_RLAST,
s_axi_rready => s02_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s02_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s02_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s02_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wlast => s02_couplers_to_auto_pc_WLAST,
s_axi_wready => s02_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s02_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s02_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity DemoInterconnect_axi_interconnect_0_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC;
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_arready : in STD_LOGIC;
M01_AXI_arvalid : out STD_LOGIC;
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_awready : in STD_LOGIC;
M01_AXI_awvalid : out STD_LOGIC;
M01_AXI_bready : out STD_LOGIC;
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC;
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC;
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC;
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC;
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC;
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC;
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M02_AXI_arready : in STD_LOGIC;
M02_AXI_arvalid : out STD_LOGIC;
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M02_AXI_awready : in STD_LOGIC;
M02_AXI_awvalid : out STD_LOGIC;
M02_AXI_bready : out STD_LOGIC;
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC;
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC;
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC;
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC;
M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_wvalid : out STD_LOGIC;
M03_ACLK : in STD_LOGIC;
M03_ARESETN : in STD_LOGIC;
M03_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M03_AXI_arready : in STD_LOGIC;
M03_AXI_arvalid : out STD_LOGIC;
M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M03_AXI_awready : in STD_LOGIC;
M03_AXI_awvalid : out STD_LOGIC;
M03_AXI_bready : out STD_LOGIC;
M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_bvalid : in STD_LOGIC;
M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_rready : out STD_LOGIC;
M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_rvalid : in STD_LOGIC;
M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_wready : in STD_LOGIC;
M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M03_AXI_wvalid : out STD_LOGIC;
M04_ACLK : in STD_LOGIC;
M04_ARESETN : in STD_LOGIC;
M04_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_arready : in STD_LOGIC;
M04_AXI_arvalid : out STD_LOGIC;
M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_awready : in STD_LOGIC;
M04_AXI_awvalid : out STD_LOGIC;
M04_AXI_bready : out STD_LOGIC;
M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_bvalid : in STD_LOGIC;
M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_rready : out STD_LOGIC;
M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_rvalid : in STD_LOGIC;
M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_wready : in STD_LOGIC;
M04_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M04_AXI_wvalid : out STD_LOGIC;
M05_ACLK : in STD_LOGIC;
M05_ARESETN : in STD_LOGIC;
M05_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_arready : in STD_LOGIC;
M05_AXI_arvalid : out STD_LOGIC;
M05_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_awready : in STD_LOGIC;
M05_AXI_awvalid : out STD_LOGIC;
M05_AXI_bready : out STD_LOGIC;
M05_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_bvalid : in STD_LOGIC;
M05_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_rready : out STD_LOGIC;
M05_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_rvalid : in STD_LOGIC;
M05_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_wready : in STD_LOGIC;
M05_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M05_AXI_wvalid : out STD_LOGIC;
M06_ACLK : in STD_LOGIC;
M06_ARESETN : in STD_LOGIC;
M06_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_arready : in STD_LOGIC;
M06_AXI_arvalid : out STD_LOGIC;
M06_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_awready : in STD_LOGIC;
M06_AXI_awvalid : out STD_LOGIC;
M06_AXI_bready : out STD_LOGIC;
M06_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_bvalid : in STD_LOGIC;
M06_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_rready : out STD_LOGIC;
M06_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_rvalid : in STD_LOGIC;
M06_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_wready : in STD_LOGIC;
M06_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M06_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC;
S01_ACLK : in STD_LOGIC;
S01_ARESETN : in STD_LOGIC;
S01_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_arready : out STD_LOGIC;
S01_AXI_arvalid : in STD_LOGIC;
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awready : out STD_LOGIC;
S01_AXI_awvalid : in STD_LOGIC;
S01_AXI_bready : in STD_LOGIC;
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_bvalid : out STD_LOGIC;
S01_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_rready : in STD_LOGIC;
S01_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_rvalid : out STD_LOGIC;
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_wready : out STD_LOGIC;
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_wvalid : in STD_LOGIC;
S02_ACLK : in STD_LOGIC;
S02_ARESETN : in STD_LOGIC;
S02_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_arlock : in STD_LOGIC;
S02_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arready : out STD_LOGIC;
S02_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arvalid : in STD_LOGIC;
S02_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_awlock : in STD_LOGIC;
S02_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awready : out STD_LOGIC;
S02_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_awvalid : in STD_LOGIC;
S02_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_bready : in STD_LOGIC;
S02_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_bvalid : out STD_LOGIC;
S02_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_rlast : out STD_LOGIC;
S02_AXI_rready : in STD_LOGIC;
S02_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_rvalid : out STD_LOGIC;
S02_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_wlast : in STD_LOGIC;
S02_AXI_wready : out STD_LOGIC;
S02_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_wvalid : in STD_LOGIC
);
end DemoInterconnect_axi_interconnect_0_0;
architecture STRUCTURE of DemoInterconnect_axi_interconnect_0_0 is
component DemoInterconnect_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 20 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 20 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 6 downto 0 )
);
end component DemoInterconnect_xbar_0;
signal interconnect_ACLK_net : STD_LOGIC;
signal interconnect_ARESETN_net : STD_LOGIC;
signal interconnect_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s00_couplers_ARREADY : STD_LOGIC;
signal interconnect_to_s00_couplers_ARVALID : STD_LOGIC;
signal interconnect_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s00_couplers_AWREADY : STD_LOGIC;
signal interconnect_to_s00_couplers_AWVALID : STD_LOGIC;
signal interconnect_to_s00_couplers_BREADY : STD_LOGIC;
signal interconnect_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s00_couplers_BVALID : STD_LOGIC;
signal interconnect_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s00_couplers_RREADY : STD_LOGIC;
signal interconnect_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s00_couplers_RVALID : STD_LOGIC;
signal interconnect_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s00_couplers_WREADY : STD_LOGIC;
signal interconnect_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s00_couplers_WVALID : STD_LOGIC;
signal interconnect_to_s01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s01_couplers_ARREADY : STD_LOGIC;
signal interconnect_to_s01_couplers_ARVALID : STD_LOGIC;
signal interconnect_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s01_couplers_AWREADY : STD_LOGIC;
signal interconnect_to_s01_couplers_AWVALID : STD_LOGIC;
signal interconnect_to_s01_couplers_BREADY : STD_LOGIC;
signal interconnect_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s01_couplers_BVALID : STD_LOGIC;
signal interconnect_to_s01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s01_couplers_RREADY : STD_LOGIC;
signal interconnect_to_s01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s01_couplers_RVALID : STD_LOGIC;
signal interconnect_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s01_couplers_WREADY : STD_LOGIC;
signal interconnect_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s01_couplers_WVALID : STD_LOGIC;
signal interconnect_to_s02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s02_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s02_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s02_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal interconnect_to_s02_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal interconnect_to_s02_couplers_ARLOCK : STD_LOGIC;
signal interconnect_to_s02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s02_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s02_couplers_ARREADY : STD_LOGIC;
signal interconnect_to_s02_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s02_couplers_ARVALID : STD_LOGIC;
signal interconnect_to_s02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s02_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s02_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s02_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal interconnect_to_s02_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal interconnect_to_s02_couplers_AWLOCK : STD_LOGIC;
signal interconnect_to_s02_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s02_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s02_couplers_AWREADY : STD_LOGIC;
signal interconnect_to_s02_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s02_couplers_AWVALID : STD_LOGIC;
signal interconnect_to_s02_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal interconnect_to_s02_couplers_BREADY : STD_LOGIC;
signal interconnect_to_s02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s02_couplers_BVALID : STD_LOGIC;
signal interconnect_to_s02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s02_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal interconnect_to_s02_couplers_RLAST : STD_LOGIC;
signal interconnect_to_s02_couplers_RREADY : STD_LOGIC;
signal interconnect_to_s02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s02_couplers_RVALID : STD_LOGIC;
signal interconnect_to_s02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s02_couplers_WLAST : STD_LOGIC;
signal interconnect_to_s02_couplers_WREADY : STD_LOGIC;
signal interconnect_to_s02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s02_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_interconnect_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m00_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m00_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_interconnect_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m00_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m00_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m00_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m00_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m00_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m00_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m00_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m01_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_interconnect_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m01_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m01_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_interconnect_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m01_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m01_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m01_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m01_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m01_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m01_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m01_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m02_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_interconnect_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m02_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m02_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_interconnect_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m02_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m02_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m02_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m02_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m02_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m02_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m02_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m03_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_interconnect_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m03_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m03_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_interconnect_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m03_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m03_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m03_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m03_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m03_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m03_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m03_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m04_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m04_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m04_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m04_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m04_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m04_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m04_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m04_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m04_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m04_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m05_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m05_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m05_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m05_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m05_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m05_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m05_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m05_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m05_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m05_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m06_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m06_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m06_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m06_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m06_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m06_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m06_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m06_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m06_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m06_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_interconnect_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal s01_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s01_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s01_couplers_to_xbar_BREADY : STD_LOGIC;
signal s01_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal s01_couplers_to_xbar_RREADY : STD_LOGIC;
signal s01_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_WVALID : STD_LOGIC;
signal s02_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s02_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s02_couplers_to_xbar_BREADY : STD_LOGIC;
signal s02_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 5 downto 4 );
signal s02_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal s02_couplers_to_xbar_RREADY : STD_LOGIC;
signal s02_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 5 downto 4 );
signal s02_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC;
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC;
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC;
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARPROT : STD_LOGIC_VECTOR ( 8 downto 6 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWPROT : STD_LOGIC_VECTOR ( 8 downto 6 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC;
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC;
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC;
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_ARPROT : STD_LOGIC_VECTOR ( 11 downto 9 );
signal xbar_to_m03_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_AWPROT : STD_LOGIC_VECTOR ( 11 downto 9 );
signal xbar_to_m03_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_BVALID : STD_LOGIC;
signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_RVALID : STD_LOGIC;
signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_WREADY : STD_LOGIC;
signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 );
signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_BVALID : STD_LOGIC;
signal xbar_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_RVALID : STD_LOGIC;
signal xbar_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_WREADY : STD_LOGIC;
signal xbar_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 19 downto 16 );
signal xbar_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m05_couplers_ARVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m05_couplers_AWVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_BVALID : STD_LOGIC;
signal xbar_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m05_couplers_RREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_RVALID : STD_LOGIC;
signal xbar_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_WREADY : STD_LOGIC;
signal xbar_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 23 downto 20 );
signal xbar_to_m05_couplers_WVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m06_couplers_ARVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m06_couplers_AWVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_BVALID : STD_LOGIC;
signal xbar_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m06_couplers_RREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_RVALID : STD_LOGIC;
signal xbar_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_WREADY : STD_LOGIC;
signal xbar_to_m06_couplers_WSTRB : STD_LOGIC_VECTOR ( 27 downto 24 );
signal xbar_to_m06_couplers_WVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 20 downto 12 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 20 downto 12 );
begin
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_interconnect_ARADDR(31 downto 0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_interconnect_ARPROT(2 downto 0);
M00_AXI_arvalid <= m00_couplers_to_interconnect_ARVALID;
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_interconnect_AWADDR(31 downto 0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_interconnect_AWPROT(2 downto 0);
M00_AXI_awvalid <= m00_couplers_to_interconnect_AWVALID;
M00_AXI_bready <= m00_couplers_to_interconnect_BREADY;
M00_AXI_rready <= m00_couplers_to_interconnect_RREADY;
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_interconnect_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_interconnect_WSTRB(3 downto 0);
M00_AXI_wvalid <= m00_couplers_to_interconnect_WVALID;
M01_AXI_araddr(31 downto 0) <= m01_couplers_to_interconnect_ARADDR(31 downto 0);
M01_AXI_arprot(2 downto 0) <= m01_couplers_to_interconnect_ARPROT(2 downto 0);
M01_AXI_arvalid <= m01_couplers_to_interconnect_ARVALID;
M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_interconnect_AWADDR(31 downto 0);
M01_AXI_awprot(2 downto 0) <= m01_couplers_to_interconnect_AWPROT(2 downto 0);
M01_AXI_awvalid <= m01_couplers_to_interconnect_AWVALID;
M01_AXI_bready <= m01_couplers_to_interconnect_BREADY;
M01_AXI_rready <= m01_couplers_to_interconnect_RREADY;
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_interconnect_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_interconnect_WSTRB(3 downto 0);
M01_AXI_wvalid <= m01_couplers_to_interconnect_WVALID;
M02_AXI_araddr(31 downto 0) <= m02_couplers_to_interconnect_ARADDR(31 downto 0);
M02_AXI_arprot(2 downto 0) <= m02_couplers_to_interconnect_ARPROT(2 downto 0);
M02_AXI_arvalid <= m02_couplers_to_interconnect_ARVALID;
M02_AXI_awaddr(31 downto 0) <= m02_couplers_to_interconnect_AWADDR(31 downto 0);
M02_AXI_awprot(2 downto 0) <= m02_couplers_to_interconnect_AWPROT(2 downto 0);
M02_AXI_awvalid <= m02_couplers_to_interconnect_AWVALID;
M02_AXI_bready <= m02_couplers_to_interconnect_BREADY;
M02_AXI_rready <= m02_couplers_to_interconnect_RREADY;
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_interconnect_WDATA(31 downto 0);
M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_interconnect_WSTRB(3 downto 0);
M02_AXI_wvalid <= m02_couplers_to_interconnect_WVALID;
M03_AXI_araddr(31 downto 0) <= m03_couplers_to_interconnect_ARADDR(31 downto 0);
M03_AXI_arprot(2 downto 0) <= m03_couplers_to_interconnect_ARPROT(2 downto 0);
M03_AXI_arvalid <= m03_couplers_to_interconnect_ARVALID;
M03_AXI_awaddr(31 downto 0) <= m03_couplers_to_interconnect_AWADDR(31 downto 0);
M03_AXI_awprot(2 downto 0) <= m03_couplers_to_interconnect_AWPROT(2 downto 0);
M03_AXI_awvalid <= m03_couplers_to_interconnect_AWVALID;
M03_AXI_bready <= m03_couplers_to_interconnect_BREADY;
M03_AXI_rready <= m03_couplers_to_interconnect_RREADY;
M03_AXI_wdata(31 downto 0) <= m03_couplers_to_interconnect_WDATA(31 downto 0);
M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_interconnect_WSTRB(3 downto 0);
M03_AXI_wvalid <= m03_couplers_to_interconnect_WVALID;
M04_AXI_araddr(31 downto 0) <= m04_couplers_to_interconnect_ARADDR(31 downto 0);
M04_AXI_arvalid <= m04_couplers_to_interconnect_ARVALID;
M04_AXI_awaddr(31 downto 0) <= m04_couplers_to_interconnect_AWADDR(31 downto 0);
M04_AXI_awvalid <= m04_couplers_to_interconnect_AWVALID;
M04_AXI_bready <= m04_couplers_to_interconnect_BREADY;
M04_AXI_rready <= m04_couplers_to_interconnect_RREADY;
M04_AXI_wdata(31 downto 0) <= m04_couplers_to_interconnect_WDATA(31 downto 0);
M04_AXI_wstrb(3 downto 0) <= m04_couplers_to_interconnect_WSTRB(3 downto 0);
M04_AXI_wvalid <= m04_couplers_to_interconnect_WVALID;
M05_AXI_araddr(31 downto 0) <= m05_couplers_to_interconnect_ARADDR(31 downto 0);
M05_AXI_arvalid <= m05_couplers_to_interconnect_ARVALID;
M05_AXI_awaddr(31 downto 0) <= m05_couplers_to_interconnect_AWADDR(31 downto 0);
M05_AXI_awvalid <= m05_couplers_to_interconnect_AWVALID;
M05_AXI_bready <= m05_couplers_to_interconnect_BREADY;
M05_AXI_rready <= m05_couplers_to_interconnect_RREADY;
M05_AXI_wdata(31 downto 0) <= m05_couplers_to_interconnect_WDATA(31 downto 0);
M05_AXI_wstrb(3 downto 0) <= m05_couplers_to_interconnect_WSTRB(3 downto 0);
M05_AXI_wvalid <= m05_couplers_to_interconnect_WVALID;
M06_AXI_araddr(31 downto 0) <= m06_couplers_to_interconnect_ARADDR(31 downto 0);
M06_AXI_arvalid <= m06_couplers_to_interconnect_ARVALID;
M06_AXI_awaddr(31 downto 0) <= m06_couplers_to_interconnect_AWADDR(31 downto 0);
M06_AXI_awvalid <= m06_couplers_to_interconnect_AWVALID;
M06_AXI_bready <= m06_couplers_to_interconnect_BREADY;
M06_AXI_rready <= m06_couplers_to_interconnect_RREADY;
M06_AXI_wdata(31 downto 0) <= m06_couplers_to_interconnect_WDATA(31 downto 0);
M06_AXI_wstrb(3 downto 0) <= m06_couplers_to_interconnect_WSTRB(3 downto 0);
M06_AXI_wvalid <= m06_couplers_to_interconnect_WVALID;
S00_AXI_arready <= interconnect_to_s00_couplers_ARREADY;
S00_AXI_awready <= interconnect_to_s00_couplers_AWREADY;
S00_AXI_bresp(1 downto 0) <= interconnect_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= interconnect_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= interconnect_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rresp(1 downto 0) <= interconnect_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= interconnect_to_s00_couplers_RVALID;
S00_AXI_wready <= interconnect_to_s00_couplers_WREADY;
S01_AXI_arready <= interconnect_to_s01_couplers_ARREADY;
S01_AXI_awready <= interconnect_to_s01_couplers_AWREADY;
S01_AXI_bresp(1 downto 0) <= interconnect_to_s01_couplers_BRESP(1 downto 0);
S01_AXI_bvalid <= interconnect_to_s01_couplers_BVALID;
S01_AXI_rdata(31 downto 0) <= interconnect_to_s01_couplers_RDATA(31 downto 0);
S01_AXI_rresp(1 downto 0) <= interconnect_to_s01_couplers_RRESP(1 downto 0);
S01_AXI_rvalid <= interconnect_to_s01_couplers_RVALID;
S01_AXI_wready <= interconnect_to_s01_couplers_WREADY;
S02_AXI_arready <= interconnect_to_s02_couplers_ARREADY;
S02_AXI_awready <= interconnect_to_s02_couplers_AWREADY;
S02_AXI_bid(0) <= interconnect_to_s02_couplers_BID(0);
S02_AXI_bresp(1 downto 0) <= interconnect_to_s02_couplers_BRESP(1 downto 0);
S02_AXI_bvalid <= interconnect_to_s02_couplers_BVALID;
S02_AXI_rdata(31 downto 0) <= interconnect_to_s02_couplers_RDATA(31 downto 0);
S02_AXI_rid(0) <= interconnect_to_s02_couplers_RID(0);
S02_AXI_rlast <= interconnect_to_s02_couplers_RLAST;
S02_AXI_rresp(1 downto 0) <= interconnect_to_s02_couplers_RRESP(1 downto 0);
S02_AXI_rvalid <= interconnect_to_s02_couplers_RVALID;
S02_AXI_wready <= interconnect_to_s02_couplers_WREADY;
interconnect_ACLK_net <= ACLK;
interconnect_ARESETN_net <= ARESETN;
interconnect_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
interconnect_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
interconnect_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
interconnect_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
interconnect_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
interconnect_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
interconnect_to_s00_couplers_BREADY <= S00_AXI_bready;
interconnect_to_s00_couplers_RREADY <= S00_AXI_rready;
interconnect_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
interconnect_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
interconnect_to_s00_couplers_WVALID <= S00_AXI_wvalid;
interconnect_to_s01_couplers_ARADDR(31 downto 0) <= S01_AXI_araddr(31 downto 0);
interconnect_to_s01_couplers_ARPROT(2 downto 0) <= S01_AXI_arprot(2 downto 0);
interconnect_to_s01_couplers_ARVALID <= S01_AXI_arvalid;
interconnect_to_s01_couplers_AWADDR(31 downto 0) <= S01_AXI_awaddr(31 downto 0);
interconnect_to_s01_couplers_AWPROT(2 downto 0) <= S01_AXI_awprot(2 downto 0);
interconnect_to_s01_couplers_AWVALID <= S01_AXI_awvalid;
interconnect_to_s01_couplers_BREADY <= S01_AXI_bready;
interconnect_to_s01_couplers_RREADY <= S01_AXI_rready;
interconnect_to_s01_couplers_WDATA(31 downto 0) <= S01_AXI_wdata(31 downto 0);
interconnect_to_s01_couplers_WSTRB(3 downto 0) <= S01_AXI_wstrb(3 downto 0);
interconnect_to_s01_couplers_WVALID <= S01_AXI_wvalid;
interconnect_to_s02_couplers_ARADDR(31 downto 0) <= S02_AXI_araddr(31 downto 0);
interconnect_to_s02_couplers_ARBURST(1 downto 0) <= S02_AXI_arburst(1 downto 0);
interconnect_to_s02_couplers_ARCACHE(3 downto 0) <= S02_AXI_arcache(3 downto 0);
interconnect_to_s02_couplers_ARID(0) <= S02_AXI_arid(0);
interconnect_to_s02_couplers_ARLEN(7 downto 0) <= S02_AXI_arlen(7 downto 0);
interconnect_to_s02_couplers_ARLOCK <= S02_AXI_arlock;
interconnect_to_s02_couplers_ARPROT(2 downto 0) <= S02_AXI_arprot(2 downto 0);
interconnect_to_s02_couplers_ARQOS(3 downto 0) <= S02_AXI_arqos(3 downto 0);
interconnect_to_s02_couplers_ARSIZE(2 downto 0) <= S02_AXI_arsize(2 downto 0);
interconnect_to_s02_couplers_ARVALID <= S02_AXI_arvalid;
interconnect_to_s02_couplers_AWADDR(31 downto 0) <= S02_AXI_awaddr(31 downto 0);
interconnect_to_s02_couplers_AWBURST(1 downto 0) <= S02_AXI_awburst(1 downto 0);
interconnect_to_s02_couplers_AWCACHE(3 downto 0) <= S02_AXI_awcache(3 downto 0);
interconnect_to_s02_couplers_AWID(0) <= S02_AXI_awid(0);
interconnect_to_s02_couplers_AWLEN(7 downto 0) <= S02_AXI_awlen(7 downto 0);
interconnect_to_s02_couplers_AWLOCK <= S02_AXI_awlock;
interconnect_to_s02_couplers_AWPROT(2 downto 0) <= S02_AXI_awprot(2 downto 0);
interconnect_to_s02_couplers_AWQOS(3 downto 0) <= S02_AXI_awqos(3 downto 0);
interconnect_to_s02_couplers_AWSIZE(2 downto 0) <= S02_AXI_awsize(2 downto 0);
interconnect_to_s02_couplers_AWVALID <= S02_AXI_awvalid;
interconnect_to_s02_couplers_BREADY <= S02_AXI_bready;
interconnect_to_s02_couplers_RREADY <= S02_AXI_rready;
interconnect_to_s02_couplers_WDATA(31 downto 0) <= S02_AXI_wdata(31 downto 0);
interconnect_to_s02_couplers_WLAST <= S02_AXI_wlast;
interconnect_to_s02_couplers_WSTRB(3 downto 0) <= S02_AXI_wstrb(3 downto 0);
interconnect_to_s02_couplers_WVALID <= S02_AXI_wvalid;
m00_couplers_to_interconnect_ARREADY <= M00_AXI_arready;
m00_couplers_to_interconnect_AWREADY <= M00_AXI_awready;
m00_couplers_to_interconnect_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_interconnect_BVALID <= M00_AXI_bvalid;
m00_couplers_to_interconnect_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_interconnect_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_interconnect_RVALID <= M00_AXI_rvalid;
m00_couplers_to_interconnect_WREADY <= M00_AXI_wready;
m01_couplers_to_interconnect_ARREADY <= M01_AXI_arready;
m01_couplers_to_interconnect_AWREADY <= M01_AXI_awready;
m01_couplers_to_interconnect_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_interconnect_BVALID <= M01_AXI_bvalid;
m01_couplers_to_interconnect_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_interconnect_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_interconnect_RVALID <= M01_AXI_rvalid;
m01_couplers_to_interconnect_WREADY <= M01_AXI_wready;
m02_couplers_to_interconnect_ARREADY <= M02_AXI_arready;
m02_couplers_to_interconnect_AWREADY <= M02_AXI_awready;
m02_couplers_to_interconnect_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_interconnect_BVALID <= M02_AXI_bvalid;
m02_couplers_to_interconnect_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_interconnect_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_interconnect_RVALID <= M02_AXI_rvalid;
m02_couplers_to_interconnect_WREADY <= M02_AXI_wready;
m03_couplers_to_interconnect_ARREADY <= M03_AXI_arready;
m03_couplers_to_interconnect_AWREADY <= M03_AXI_awready;
m03_couplers_to_interconnect_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
m03_couplers_to_interconnect_BVALID <= M03_AXI_bvalid;
m03_couplers_to_interconnect_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
m03_couplers_to_interconnect_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
m03_couplers_to_interconnect_RVALID <= M03_AXI_rvalid;
m03_couplers_to_interconnect_WREADY <= M03_AXI_wready;
m04_couplers_to_interconnect_ARREADY <= M04_AXI_arready;
m04_couplers_to_interconnect_AWREADY <= M04_AXI_awready;
m04_couplers_to_interconnect_BRESP(1 downto 0) <= M04_AXI_bresp(1 downto 0);
m04_couplers_to_interconnect_BVALID <= M04_AXI_bvalid;
m04_couplers_to_interconnect_RDATA(31 downto 0) <= M04_AXI_rdata(31 downto 0);
m04_couplers_to_interconnect_RRESP(1 downto 0) <= M04_AXI_rresp(1 downto 0);
m04_couplers_to_interconnect_RVALID <= M04_AXI_rvalid;
m04_couplers_to_interconnect_WREADY <= M04_AXI_wready;
m05_couplers_to_interconnect_ARREADY <= M05_AXI_arready;
m05_couplers_to_interconnect_AWREADY <= M05_AXI_awready;
m05_couplers_to_interconnect_BRESP(1 downto 0) <= M05_AXI_bresp(1 downto 0);
m05_couplers_to_interconnect_BVALID <= M05_AXI_bvalid;
m05_couplers_to_interconnect_RDATA(31 downto 0) <= M05_AXI_rdata(31 downto 0);
m05_couplers_to_interconnect_RRESP(1 downto 0) <= M05_AXI_rresp(1 downto 0);
m05_couplers_to_interconnect_RVALID <= M05_AXI_rvalid;
m05_couplers_to_interconnect_WREADY <= M05_AXI_wready;
m06_couplers_to_interconnect_ARREADY <= M06_AXI_arready;
m06_couplers_to_interconnect_AWREADY <= M06_AXI_awready;
m06_couplers_to_interconnect_BRESP(1 downto 0) <= M06_AXI_bresp(1 downto 0);
m06_couplers_to_interconnect_BVALID <= M06_AXI_bvalid;
m06_couplers_to_interconnect_RDATA(31 downto 0) <= M06_AXI_rdata(31 downto 0);
m06_couplers_to_interconnect_RRESP(1 downto 0) <= M06_AXI_rresp(1 downto 0);
m06_couplers_to_interconnect_RVALID <= M06_AXI_rvalid;
m06_couplers_to_interconnect_WREADY <= M06_AXI_wready;
m00_couplers: entity work.m00_couplers_imp_4EB6IN
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m00_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_interconnect_ARPROT(2 downto 0),
M_AXI_arready => m00_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m00_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m00_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_interconnect_AWPROT(2 downto 0),
M_AXI_awready => m00_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m00_couplers_to_interconnect_AWVALID,
M_AXI_bready => m00_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m00_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m00_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m00_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m00_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m00_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m00_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_1SL2GIW
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m01_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m01_couplers_to_interconnect_ARPROT(2 downto 0),
M_AXI_arready => m01_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m01_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m01_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m01_couplers_to_interconnect_AWPROT(2 downto 0),
M_AXI_awready => m01_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m01_couplers_to_interconnect_AWVALID,
M_AXI_bready => m01_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m01_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m01_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m01_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m01_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m01_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m01_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m01_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m01_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m01_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m01_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arprot(2 downto 0) => xbar_to_m01_couplers_ARPROT(5 downto 3),
S_AXI_arready => xbar_to_m01_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awprot(2 downto 0) => xbar_to_m01_couplers_AWPROT(5 downto 3),
S_AXI_awready => xbar_to_m01_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready => xbar_to_m01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_7DG2C0
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m02_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m02_couplers_to_interconnect_ARPROT(2 downto 0),
M_AXI_arready => m02_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m02_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m02_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m02_couplers_to_interconnect_AWPROT(2 downto 0),
M_AXI_awready => m02_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m02_couplers_to_interconnect_AWVALID,
M_AXI_bready => m02_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m02_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m02_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m02_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m02_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m02_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m02_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m02_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m02_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m02_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m02_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m02_couplers_ARADDR(95 downto 64),
S_AXI_arprot(2 downto 0) => xbar_to_m02_couplers_ARPROT(8 downto 6),
S_AXI_arready => xbar_to_m02_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(31 downto 0) => xbar_to_m02_couplers_AWADDR(95 downto 64),
S_AXI_awprot(2 downto 0) => xbar_to_m02_couplers_AWPROT(8 downto 6),
S_AXI_awready => xbar_to_m02_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready => xbar_to_m02_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2)
);
m03_couplers: entity work.m03_couplers_imp_1YCPS1Z
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m03_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m03_couplers_to_interconnect_ARPROT(2 downto 0),
M_AXI_arready => m03_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m03_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m03_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m03_couplers_to_interconnect_AWPROT(2 downto 0),
M_AXI_awready => m03_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m03_couplers_to_interconnect_AWVALID,
M_AXI_bready => m03_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m03_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m03_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m03_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m03_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m03_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m03_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m03_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m03_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m03_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m03_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m03_couplers_ARADDR(127 downto 96),
S_AXI_arprot(2 downto 0) => xbar_to_m03_couplers_ARPROT(11 downto 9),
S_AXI_arready => xbar_to_m03_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m03_couplers_ARVALID(3),
S_AXI_awaddr(31 downto 0) => xbar_to_m03_couplers_AWADDR(127 downto 96),
S_AXI_awprot(2 downto 0) => xbar_to_m03_couplers_AWPROT(11 downto 9),
S_AXI_awready => xbar_to_m03_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m03_couplers_AWVALID(3),
S_AXI_bready => xbar_to_m03_couplers_BREADY(3),
S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m03_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m03_couplers_RREADY(3),
S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m03_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
S_AXI_wready => xbar_to_m03_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12),
S_AXI_wvalid => xbar_to_m03_couplers_WVALID(3)
);
m04_couplers: entity work.m04_couplers_imp_ACM7VL
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m04_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arready => m04_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m04_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m04_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awready => m04_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m04_couplers_to_interconnect_AWVALID,
M_AXI_bready => m04_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m04_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m04_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m04_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m04_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m04_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m04_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m04_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m04_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m04_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m04_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m04_couplers_ARADDR(159 downto 128),
S_AXI_arready => xbar_to_m04_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m04_couplers_ARVALID(4),
S_AXI_awaddr(31 downto 0) => xbar_to_m04_couplers_AWADDR(159 downto 128),
S_AXI_awready => xbar_to_m04_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m04_couplers_AWVALID(4),
S_AXI_bready => xbar_to_m04_couplers_BREADY(4),
S_AXI_bresp(1 downto 0) => xbar_to_m04_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m04_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m04_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m04_couplers_RREADY(4),
S_AXI_rresp(1 downto 0) => xbar_to_m04_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m04_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m04_couplers_WDATA(159 downto 128),
S_AXI_wready => xbar_to_m04_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m04_couplers_WSTRB(19 downto 16),
S_AXI_wvalid => xbar_to_m04_couplers_WVALID(4)
);
m05_couplers: entity work.m05_couplers_imp_1HWY5FA
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m05_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arready => m05_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m05_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m05_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awready => m05_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m05_couplers_to_interconnect_AWVALID,
M_AXI_bready => m05_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m05_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m05_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m05_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m05_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m05_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m05_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m05_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m05_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m05_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m05_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m05_couplers_ARADDR(191 downto 160),
S_AXI_arready => xbar_to_m05_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m05_couplers_ARVALID(5),
S_AXI_awaddr(31 downto 0) => xbar_to_m05_couplers_AWADDR(191 downto 160),
S_AXI_awready => xbar_to_m05_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m05_couplers_AWVALID(5),
S_AXI_bready => xbar_to_m05_couplers_BREADY(5),
S_AXI_bresp(1 downto 0) => xbar_to_m05_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m05_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m05_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m05_couplers_RREADY(5),
S_AXI_rresp(1 downto 0) => xbar_to_m05_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m05_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m05_couplers_WDATA(191 downto 160),
S_AXI_wready => xbar_to_m05_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m05_couplers_WSTRB(23 downto 20),
S_AXI_wvalid => xbar_to_m05_couplers_WVALID(5)
);
m06_couplers: entity work.m06_couplers_imp_DBR4EM
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m06_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arready => m06_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m06_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m06_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awready => m06_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m06_couplers_to_interconnect_AWVALID,
M_AXI_bready => m06_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m06_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m06_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m06_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m06_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m06_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m06_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m06_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m06_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m06_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m06_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m06_couplers_ARADDR(223 downto 192),
S_AXI_arready => xbar_to_m06_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m06_couplers_ARVALID(6),
S_AXI_awaddr(31 downto 0) => xbar_to_m06_couplers_AWADDR(223 downto 192),
S_AXI_awready => xbar_to_m06_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m06_couplers_AWVALID(6),
S_AXI_bready => xbar_to_m06_couplers_BREADY(6),
S_AXI_bresp(1 downto 0) => xbar_to_m06_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m06_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m06_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m06_couplers_RREADY(6),
S_AXI_rresp(1 downto 0) => xbar_to_m06_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m06_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m06_couplers_WDATA(223 downto 192),
S_AXI_wready => xbar_to_m06_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m06_couplers_WSTRB(27 downto 24),
S_AXI_wvalid => xbar_to_m06_couplers_WVALID(6)
);
s00_couplers: entity work.s00_couplers_imp_7XIH8P
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => interconnect_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => interconnect_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready => interconnect_to_s00_couplers_ARREADY,
S_AXI_arvalid => interconnect_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => interconnect_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => interconnect_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awready => interconnect_to_s00_couplers_AWREADY,
S_AXI_awvalid => interconnect_to_s00_couplers_AWVALID,
S_AXI_bready => interconnect_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => interconnect_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => interconnect_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => interconnect_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rready => interconnect_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => interconnect_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => interconnect_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => interconnect_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wready => interconnect_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => interconnect_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => interconnect_to_s00_couplers_WVALID
);
s01_couplers: entity work.s01_couplers_imp_1XSI6OU
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => s01_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s01_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s01_couplers_to_xbar_ARREADY(1),
M_AXI_arvalid => s01_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s01_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s01_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s01_couplers_to_xbar_AWREADY(1),
M_AXI_awvalid => s01_couplers_to_xbar_AWVALID,
M_AXI_bready => s01_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s01_couplers_to_xbar_BRESP(3 downto 2),
M_AXI_bvalid => s01_couplers_to_xbar_BVALID(1),
M_AXI_rdata(31 downto 0) => s01_couplers_to_xbar_RDATA(63 downto 32),
M_AXI_rready => s01_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s01_couplers_to_xbar_RRESP(3 downto 2),
M_AXI_rvalid => s01_couplers_to_xbar_RVALID(1),
M_AXI_wdata(31 downto 0) => s01_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s01_couplers_to_xbar_WREADY(1),
M_AXI_wstrb(3 downto 0) => s01_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s01_couplers_to_xbar_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => interconnect_to_s01_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => interconnect_to_s01_couplers_ARPROT(2 downto 0),
S_AXI_arready => interconnect_to_s01_couplers_ARREADY,
S_AXI_arvalid => interconnect_to_s01_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => interconnect_to_s01_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => interconnect_to_s01_couplers_AWPROT(2 downto 0),
S_AXI_awready => interconnect_to_s01_couplers_AWREADY,
S_AXI_awvalid => interconnect_to_s01_couplers_AWVALID,
S_AXI_bready => interconnect_to_s01_couplers_BREADY,
S_AXI_bresp(1 downto 0) => interconnect_to_s01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => interconnect_to_s01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => interconnect_to_s01_couplers_RDATA(31 downto 0),
S_AXI_rready => interconnect_to_s01_couplers_RREADY,
S_AXI_rresp(1 downto 0) => interconnect_to_s01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => interconnect_to_s01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => interconnect_to_s01_couplers_WDATA(31 downto 0),
S_AXI_wready => interconnect_to_s01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => interconnect_to_s01_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => interconnect_to_s01_couplers_WVALID
);
s02_couplers: entity work.s02_couplers_imp_2QLUHY
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => s02_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s02_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s02_couplers_to_xbar_ARREADY(2),
M_AXI_arvalid => s02_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s02_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s02_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s02_couplers_to_xbar_AWREADY(2),
M_AXI_awvalid => s02_couplers_to_xbar_AWVALID,
M_AXI_bready => s02_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s02_couplers_to_xbar_BRESP(5 downto 4),
M_AXI_bvalid => s02_couplers_to_xbar_BVALID(2),
M_AXI_rdata(31 downto 0) => s02_couplers_to_xbar_RDATA(95 downto 64),
M_AXI_rready => s02_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s02_couplers_to_xbar_RRESP(5 downto 4),
M_AXI_rvalid => s02_couplers_to_xbar_RVALID(2),
M_AXI_wdata(31 downto 0) => s02_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s02_couplers_to_xbar_WREADY(2),
M_AXI_wstrb(3 downto 0) => s02_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s02_couplers_to_xbar_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => interconnect_to_s02_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => interconnect_to_s02_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => interconnect_to_s02_couplers_ARCACHE(3 downto 0),
S_AXI_arid(0) => interconnect_to_s02_couplers_ARID(0),
S_AXI_arlen(7 downto 0) => interconnect_to_s02_couplers_ARLEN(7 downto 0),
S_AXI_arlock => interconnect_to_s02_couplers_ARLOCK,
S_AXI_arprot(2 downto 0) => interconnect_to_s02_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => interconnect_to_s02_couplers_ARQOS(3 downto 0),
S_AXI_arready => interconnect_to_s02_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => interconnect_to_s02_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => interconnect_to_s02_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => interconnect_to_s02_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => interconnect_to_s02_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => interconnect_to_s02_couplers_AWCACHE(3 downto 0),
S_AXI_awid(0) => interconnect_to_s02_couplers_AWID(0),
S_AXI_awlen(7 downto 0) => interconnect_to_s02_couplers_AWLEN(7 downto 0),
S_AXI_awlock => interconnect_to_s02_couplers_AWLOCK,
S_AXI_awprot(2 downto 0) => interconnect_to_s02_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => interconnect_to_s02_couplers_AWQOS(3 downto 0),
S_AXI_awready => interconnect_to_s02_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => interconnect_to_s02_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => interconnect_to_s02_couplers_AWVALID,
S_AXI_bid(0) => interconnect_to_s02_couplers_BID(0),
S_AXI_bready => interconnect_to_s02_couplers_BREADY,
S_AXI_bresp(1 downto 0) => interconnect_to_s02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => interconnect_to_s02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => interconnect_to_s02_couplers_RDATA(31 downto 0),
S_AXI_rid(0) => interconnect_to_s02_couplers_RID(0),
S_AXI_rlast => interconnect_to_s02_couplers_RLAST,
S_AXI_rready => interconnect_to_s02_couplers_RREADY,
S_AXI_rresp(1 downto 0) => interconnect_to_s02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => interconnect_to_s02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => interconnect_to_s02_couplers_WDATA(31 downto 0),
S_AXI_wlast => interconnect_to_s02_couplers_WLAST,
S_AXI_wready => interconnect_to_s02_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => interconnect_to_s02_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => interconnect_to_s02_couplers_WVALID
);
xbar: component DemoInterconnect_xbar_0
port map (
aclk => interconnect_ACLK_net,
aresetn => interconnect_ARESETN_net,
m_axi_araddr(223 downto 192) => xbar_to_m06_couplers_ARADDR(223 downto 192),
m_axi_araddr(191 downto 160) => xbar_to_m05_couplers_ARADDR(191 downto 160),
m_axi_araddr(159 downto 128) => xbar_to_m04_couplers_ARADDR(159 downto 128),
m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(20 downto 12) => NLW_xbar_m_axi_arprot_UNCONNECTED(20 downto 12),
m_axi_arprot(11 downto 9) => xbar_to_m03_couplers_ARPROT(11 downto 9),
m_axi_arprot(8 downto 6) => xbar_to_m02_couplers_ARPROT(8 downto 6),
m_axi_arprot(5 downto 3) => xbar_to_m01_couplers_ARPROT(5 downto 3),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arready(6) => xbar_to_m06_couplers_ARREADY,
m_axi_arready(5) => xbar_to_m05_couplers_ARREADY,
m_axi_arready(4) => xbar_to_m04_couplers_ARREADY,
m_axi_arready(3) => xbar_to_m03_couplers_ARREADY,
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY,
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arvalid(6) => xbar_to_m06_couplers_ARVALID(6),
m_axi_arvalid(5) => xbar_to_m05_couplers_ARVALID(5),
m_axi_arvalid(4) => xbar_to_m04_couplers_ARVALID(4),
m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(223 downto 192) => xbar_to_m06_couplers_AWADDR(223 downto 192),
m_axi_awaddr(191 downto 160) => xbar_to_m05_couplers_AWADDR(191 downto 160),
m_axi_awaddr(159 downto 128) => xbar_to_m04_couplers_AWADDR(159 downto 128),
m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(20 downto 12) => NLW_xbar_m_axi_awprot_UNCONNECTED(20 downto 12),
m_axi_awprot(11 downto 9) => xbar_to_m03_couplers_AWPROT(11 downto 9),
m_axi_awprot(8 downto 6) => xbar_to_m02_couplers_AWPROT(8 downto 6),
m_axi_awprot(5 downto 3) => xbar_to_m01_couplers_AWPROT(5 downto 3),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awready(6) => xbar_to_m06_couplers_AWREADY,
m_axi_awready(5) => xbar_to_m05_couplers_AWREADY,
m_axi_awready(4) => xbar_to_m04_couplers_AWREADY,
m_axi_awready(3) => xbar_to_m03_couplers_AWREADY,
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY,
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awvalid(6) => xbar_to_m06_couplers_AWVALID(6),
m_axi_awvalid(5) => xbar_to_m05_couplers_AWVALID(5),
m_axi_awvalid(4) => xbar_to_m04_couplers_AWVALID(4),
m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(6) => xbar_to_m06_couplers_BREADY(6),
m_axi_bready(5) => xbar_to_m05_couplers_BREADY(5),
m_axi_bready(4) => xbar_to_m04_couplers_BREADY(4),
m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(13 downto 12) => xbar_to_m06_couplers_BRESP(1 downto 0),
m_axi_bresp(11 downto 10) => xbar_to_m05_couplers_BRESP(1 downto 0),
m_axi_bresp(9 downto 8) => xbar_to_m04_couplers_BRESP(1 downto 0),
m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(6) => xbar_to_m06_couplers_BVALID,
m_axi_bvalid(5) => xbar_to_m05_couplers_BVALID,
m_axi_bvalid(4) => xbar_to_m04_couplers_BVALID,
m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID,
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID,
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(223 downto 192) => xbar_to_m06_couplers_RDATA(31 downto 0),
m_axi_rdata(191 downto 160) => xbar_to_m05_couplers_RDATA(31 downto 0),
m_axi_rdata(159 downto 128) => xbar_to_m04_couplers_RDATA(31 downto 0),
m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(6) => xbar_to_m06_couplers_RREADY(6),
m_axi_rready(5) => xbar_to_m05_couplers_RREADY(5),
m_axi_rready(4) => xbar_to_m04_couplers_RREADY(4),
m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(13 downto 12) => xbar_to_m06_couplers_RRESP(1 downto 0),
m_axi_rresp(11 downto 10) => xbar_to_m05_couplers_RRESP(1 downto 0),
m_axi_rresp(9 downto 8) => xbar_to_m04_couplers_RRESP(1 downto 0),
m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(6) => xbar_to_m06_couplers_RVALID,
m_axi_rvalid(5) => xbar_to_m05_couplers_RVALID,
m_axi_rvalid(4) => xbar_to_m04_couplers_RVALID,
m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID,
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID,
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(223 downto 192) => xbar_to_m06_couplers_WDATA(223 downto 192),
m_axi_wdata(191 downto 160) => xbar_to_m05_couplers_WDATA(191 downto 160),
m_axi_wdata(159 downto 128) => xbar_to_m04_couplers_WDATA(159 downto 128),
m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(6) => xbar_to_m06_couplers_WREADY,
m_axi_wready(5) => xbar_to_m05_couplers_WREADY,
m_axi_wready(4) => xbar_to_m04_couplers_WREADY,
m_axi_wready(3) => xbar_to_m03_couplers_WREADY,
m_axi_wready(2) => xbar_to_m02_couplers_WREADY,
m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(27 downto 24) => xbar_to_m06_couplers_WSTRB(27 downto 24),
m_axi_wstrb(23 downto 20) => xbar_to_m05_couplers_WSTRB(23 downto 20),
m_axi_wstrb(19 downto 16) => xbar_to_m04_couplers_WSTRB(19 downto 16),
m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(6) => xbar_to_m06_couplers_WVALID(6),
m_axi_wvalid(5) => xbar_to_m05_couplers_WVALID(5),
m_axi_wvalid(4) => xbar_to_m04_couplers_WVALID(4),
m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(95 downto 64) => s02_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_araddr(63 downto 32) => s01_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(8 downto 6) => s02_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arprot(5 downto 3) => s01_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(2) => s02_couplers_to_xbar_ARREADY(2),
s_axi_arready(1) => s01_couplers_to_xbar_ARREADY(1),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(2) => s02_couplers_to_xbar_ARVALID,
s_axi_arvalid(1) => s01_couplers_to_xbar_ARVALID,
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(95 downto 64) => s02_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(63 downto 32) => s01_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(8 downto 6) => s02_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(5 downto 3) => s01_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(2) => s02_couplers_to_xbar_AWREADY(2),
s_axi_awready(1) => s01_couplers_to_xbar_AWREADY(1),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(2) => s02_couplers_to_xbar_AWVALID,
s_axi_awvalid(1) => s01_couplers_to_xbar_AWVALID,
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(2) => s02_couplers_to_xbar_BREADY,
s_axi_bready(1) => s01_couplers_to_xbar_BREADY,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(5 downto 4) => s02_couplers_to_xbar_BRESP(5 downto 4),
s_axi_bresp(3 downto 2) => s01_couplers_to_xbar_BRESP(3 downto 2),
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(2) => s02_couplers_to_xbar_BVALID(2),
s_axi_bvalid(1) => s01_couplers_to_xbar_BVALID(1),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(95 downto 64) => s02_couplers_to_xbar_RDATA(95 downto 64),
s_axi_rdata(63 downto 32) => s01_couplers_to_xbar_RDATA(63 downto 32),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(2) => s02_couplers_to_xbar_RREADY,
s_axi_rready(1) => s01_couplers_to_xbar_RREADY,
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(5 downto 4) => s02_couplers_to_xbar_RRESP(5 downto 4),
s_axi_rresp(3 downto 2) => s01_couplers_to_xbar_RRESP(3 downto 2),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(2) => s02_couplers_to_xbar_RVALID(2),
s_axi_rvalid(1) => s01_couplers_to_xbar_RVALID(1),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(95 downto 64) => s02_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wdata(63 downto 32) => s01_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(2) => s02_couplers_to_xbar_WREADY(2),
s_axi_wready(1) => s01_couplers_to_xbar_WREADY(1),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(11 downto 8) => s02_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wstrb(7 downto 4) => s01_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(2) => s02_couplers_to_xbar_WVALID,
s_axi_wvalid(1) => s01_couplers_to_xbar_WVALID,
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity DemoInterconnect is
port (
LED0_pll_aclk : out STD_LOGIC;
LED1_pll_uart : out STD_LOGIC;
LED2_pll_lock : out STD_LOGIC;
UART_RX_0 : in STD_LOGIC;
UART_RX_1 : in STD_LOGIC;
UART_TX_0 : out STD_LOGIC;
UART_TX_1 : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_miso_1 : in STD_LOGIC;
m_spi_miso_2 : in STD_LOGIC;
m_spi_miso_3 : in STD_LOGIC;
m_spi_mosi : out STD_LOGIC;
m_spi_mosi_1 : out STD_LOGIC;
m_spi_mosi_2 : out STD_LOGIC;
m_spi_mosi_3 : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
m_spi_sclk_1 : out STD_LOGIC;
m_spi_sclk_2 : out STD_LOGIC;
m_spi_sclk_3 : out STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_ss_1 : out STD_LOGIC;
m_spi_ss_2 : out STD_LOGIC;
m_spi_ss_3 : out STD_LOGIC;
sys_clk : in STD_LOGIC;
sys_reset : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of DemoInterconnect : entity is "DemoInterconnect,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=DemoInterconnect,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=25,numReposBlks=14,numNonXlnxBlks=8,numHierBlks=11,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=6,da_board_cnt=5,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of DemoInterconnect : entity is "DemoInterconnect.hwdef";
end DemoInterconnect;
architecture STRUCTURE of DemoInterconnect is
component DemoInterconnect_clk_wiz_0_0 is
port (
reset : in STD_LOGIC;
clk_in1 : in STD_LOGIC;
aclk : out STD_LOGIC;
uart : out STD_LOGIC;
locked : out STD_LOGIC
);
end component DemoInterconnect_clk_wiz_0_0;
component DemoInterconnect_jtag_axi_0_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC;
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC;
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component DemoInterconnect_jtag_axi_0_0;
component DemoInterconnect_mutex_0_0 is
port (
S0_AXI_ACLK : in STD_LOGIC;
S0_AXI_ARESETN : in STD_LOGIC;
S0_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S0_AXI_AWVALID : in STD_LOGIC;
S0_AXI_AWREADY : out STD_LOGIC;
S0_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S0_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S0_AXI_WVALID : in STD_LOGIC;
S0_AXI_WREADY : out STD_LOGIC;
S0_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S0_AXI_BVALID : out STD_LOGIC;
S0_AXI_BREADY : in STD_LOGIC;
S0_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S0_AXI_ARVALID : in STD_LOGIC;
S0_AXI_ARREADY : out STD_LOGIC;
S0_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S0_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S0_AXI_RVALID : out STD_LOGIC;
S0_AXI_RREADY : in STD_LOGIC;
S1_AXI_ACLK : in STD_LOGIC;
S1_AXI_ARESETN : in STD_LOGIC;
S1_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S1_AXI_AWVALID : in STD_LOGIC;
S1_AXI_AWREADY : out STD_LOGIC;
S1_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S1_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S1_AXI_WVALID : in STD_LOGIC;
S1_AXI_WREADY : out STD_LOGIC;
S1_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S1_AXI_BVALID : out STD_LOGIC;
S1_AXI_BREADY : in STD_LOGIC;
S1_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S1_AXI_ARVALID : in STD_LOGIC;
S1_AXI_ARREADY : out STD_LOGIC;
S1_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S1_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S1_AXI_RVALID : out STD_LOGIC;
S1_AXI_RREADY : in STD_LOGIC;
S2_AXI_ACLK : in STD_LOGIC;
S2_AXI_ARESETN : in STD_LOGIC;
S2_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S2_AXI_AWVALID : in STD_LOGIC;
S2_AXI_AWREADY : out STD_LOGIC;
S2_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S2_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S2_AXI_WVALID : in STD_LOGIC;
S2_AXI_WREADY : out STD_LOGIC;
S2_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S2_AXI_BVALID : out STD_LOGIC;
S2_AXI_BREADY : in STD_LOGIC;
S2_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S2_AXI_ARVALID : in STD_LOGIC;
S2_AXI_ARREADY : out STD_LOGIC;
S2_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S2_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S2_AXI_RVALID : out STD_LOGIC;
S2_AXI_RREADY : in STD_LOGIC
);
end component DemoInterconnect_mutex_0_0;
component DemoInterconnect_uart_transceiver_0_0 is
port (
i_Clk : in STD_LOGIC;
i_RX_Serial : in STD_LOGIC;
o_RX_Done : out STD_LOGIC;
o_RX_Byte : out STD_LOGIC_VECTOR ( 7 downto 0 );
i_TX_Load : in STD_LOGIC;
i_TX_Byte : in STD_LOGIC_VECTOR ( 7 downto 0 );
o_TX_Active : out STD_LOGIC;
o_TX_Serial : out STD_LOGIC;
o_TX_Done : out STD_LOGIC
);
end component DemoInterconnect_uart_transceiver_0_0;
component DemoInterconnect_uart_transceiver_0_1 is
port (
i_Clk : in STD_LOGIC;
i_RX_Serial : in STD_LOGIC;
o_RX_Done : out STD_LOGIC;
o_RX_Byte : out STD_LOGIC_VECTOR ( 7 downto 0 );
i_TX_Load : in STD_LOGIC;
i_TX_Byte : in STD_LOGIC_VECTOR ( 7 downto 0 );
o_TX_Active : out STD_LOGIC;
o_TX_Serial : out STD_LOGIC;
o_TX_Done : out STD_LOGIC
);
end component DemoInterconnect_uart_transceiver_0_1;
component DemoInterconnect_axi_spi_master_0_0 is
port (
m_spi_mosi : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_axi_spi_master_0_0;
component DemoInterconnect_axi_spi_master_0_1 is
port (
m_spi_mosi : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_axi_spi_master_0_1;
component DemoInterconnect_axi_spi_master_1_0 is
port (
m_spi_mosi : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_axi_spi_master_1_0;
component DemoInterconnect_axi_spi_master_1_1 is
port (
m_spi_mosi : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_axi_spi_master_1_1;
component DemoInterconnect_ila_0_0 is
port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component DemoInterconnect_ila_0_0;
component DemoInterconnect_internoc_ni_axi_master_0_0 is
port (
if00_data_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
if00_load_in : in STD_LOGIC;
if00_data_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
if00_load_out : out STD_LOGIC;
if00_send_done : in STD_LOGIC;
if00_send_busy : in STD_LOGIC;
m00_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m00_axi_awvalid : out STD_LOGIC;
m00_axi_awready : in STD_LOGIC;
m00_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m00_axi_wvalid : out STD_LOGIC;
m00_axi_wready : in STD_LOGIC;
m00_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m00_axi_bvalid : in STD_LOGIC;
m00_axi_bready : out STD_LOGIC;
m00_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m00_axi_arvalid : out STD_LOGIC;
m00_axi_arready : in STD_LOGIC;
m00_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m00_axi_rvalid : in STD_LOGIC;
m00_axi_rready : out STD_LOGIC;
m00_axi_aclk : in STD_LOGIC;
m00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_internoc_ni_axi_master_0_0;
component DemoInterconnect_internoc_ni_axi_master_1_0 is
port (
if00_data_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
if00_load_in : in STD_LOGIC;
if00_data_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
if00_load_out : out STD_LOGIC;
if00_send_done : in STD_LOGIC;
if00_send_busy : in STD_LOGIC;
m00_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m00_axi_awvalid : out STD_LOGIC;
m00_axi_awready : in STD_LOGIC;
m00_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m00_axi_wvalid : out STD_LOGIC;
m00_axi_wready : in STD_LOGIC;
m00_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m00_axi_bvalid : in STD_LOGIC;
m00_axi_bready : out STD_LOGIC;
m00_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m00_axi_arvalid : out STD_LOGIC;
m00_axi_arready : in STD_LOGIC;
m00_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m00_axi_rvalid : in STD_LOGIC;
m00_axi_rready : out STD_LOGIC;
m00_axi_aclk : in STD_LOGIC;
m00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_internoc_ni_axi_master_1_0;
signal UART_RX_0_1 : STD_LOGIC;
signal UART_RX_1_1 : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M01_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M01_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M01_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M01_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M01_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M02_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M02_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M02_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M02_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M02_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M03_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M03_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M03_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M03_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M03_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M04_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M04_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M04_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M05_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M05_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M05_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M05_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M05_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M05_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M05_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M06_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M06_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M06_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M06_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M06_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M06_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M06_AXI_WVALID : STD_LOGIC;
signal axi_spi_master_0_m_spi_mosi : STD_LOGIC;
signal axi_spi_master_0_m_spi_sclk : STD_LOGIC;
signal axi_spi_master_0_m_spi_ss : STD_LOGIC;
signal axi_spi_master_1_m_spi_mosi : STD_LOGIC;
signal axi_spi_master_1_m_spi_sclk : STD_LOGIC;
signal axi_spi_master_1_m_spi_ss : STD_LOGIC;
signal axi_spi_master_2_m_spi_mosi : STD_LOGIC;
signal axi_spi_master_2_m_spi_sclk : STD_LOGIC;
signal axi_spi_master_2_m_spi_ss : STD_LOGIC;
signal axi_spi_master_3_m_spi_mosi : STD_LOGIC;
signal axi_spi_master_3_m_spi_sclk : STD_LOGIC;
signal axi_spi_master_3_m_spi_ss : STD_LOGIC;
signal clk_wiz_0_clk_out1 : STD_LOGIC;
signal clk_wiz_0_locked : STD_LOGIC;
signal clk_wiz_0_uart : STD_LOGIC;
signal interface_axi_master_0_if00_data_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal interface_axi_master_0_if00_load_out : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_ARREADY : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_ARVALID : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_AWREADY : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_AWVALID : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_BREADY : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_BVALID : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_RREADY : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_RVALID : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_WREADY : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_WVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_ARREADY : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_ARVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_AWREADY : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_AWVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_BREADY : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_BVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_RREADY : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_RVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_WREADY : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_WVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_if00_data_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal internoc_ni_axi_master_1_if00_load_out : STD_LOGIC;
signal jtag_axi_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal jtag_axi_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal jtag_axi_0_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal jtag_axi_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal jtag_axi_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal jtag_axi_0_M_AXI_ARLOCK : STD_LOGIC;
signal jtag_axi_0_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal jtag_axi_0_M_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal jtag_axi_0_M_AXI_ARREADY : STD_LOGIC;
signal jtag_axi_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal jtag_axi_0_M_AXI_ARVALID : STD_LOGIC;
signal jtag_axi_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal jtag_axi_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal jtag_axi_0_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal jtag_axi_0_M_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal jtag_axi_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal jtag_axi_0_M_AXI_AWLOCK : STD_LOGIC;
signal jtag_axi_0_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal jtag_axi_0_M_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal jtag_axi_0_M_AXI_AWREADY : STD_LOGIC;
signal jtag_axi_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal jtag_axi_0_M_AXI_AWVALID : STD_LOGIC;
signal jtag_axi_0_M_AXI_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal jtag_axi_0_M_AXI_BREADY : STD_LOGIC;
signal jtag_axi_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal jtag_axi_0_M_AXI_BVALID : STD_LOGIC;
signal jtag_axi_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal jtag_axi_0_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal jtag_axi_0_M_AXI_RLAST : STD_LOGIC;
signal jtag_axi_0_M_AXI_RREADY : STD_LOGIC;
signal jtag_axi_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal jtag_axi_0_M_AXI_RVALID : STD_LOGIC;
signal jtag_axi_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal jtag_axi_0_M_AXI_WLAST : STD_LOGIC;
signal jtag_axi_0_M_AXI_WREADY : STD_LOGIC;
signal jtag_axi_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal jtag_axi_0_M_AXI_WVALID : STD_LOGIC;
signal \^m_spi_miso_1\ : STD_LOGIC;
signal m_spi_miso_1_1 : STD_LOGIC;
signal m_spi_miso_2_1 : STD_LOGIC;
signal m_spi_miso_3_1 : STD_LOGIC;
signal sys_clk_1 : STD_LOGIC;
signal uart_transceiver_0_o_RX_Byte : STD_LOGIC_VECTOR ( 7 downto 0 );
signal uart_transceiver_0_o_RX_Done : STD_LOGIC;
signal uart_transceiver_0_o_TX_Active : STD_LOGIC;
signal uart_transceiver_0_o_TX_Done : STD_LOGIC;
signal uart_transceiver_0_o_TX_Serial : STD_LOGIC;
signal uart_transceiver_1_o_RX_Byte : STD_LOGIC_VECTOR ( 7 downto 0 );
signal uart_transceiver_1_o_RX_Done : STD_LOGIC;
signal uart_transceiver_1_o_TX_Active : STD_LOGIC;
signal uart_transceiver_1_o_TX_Done : STD_LOGIC;
signal uart_transceiver_1_o_TX_Serial : STD_LOGIC;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of UART_RX_0 : signal is "xilinx.com:signal:data:1.0 DATA.UART_RX_0 DATA";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of UART_RX_0 : signal is "XIL_INTERFACENAME DATA.UART_RX_0, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of UART_RX_1 : signal is "xilinx.com:signal:data:1.0 DATA.UART_RX_1 DATA";
attribute X_INTERFACE_PARAMETER of UART_RX_1 : signal is "XIL_INTERFACENAME DATA.UART_RX_1, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of UART_TX_1 : signal is "xilinx.com:signal:data:1.0 DATA.UART_TX_1 DATA";
attribute X_INTERFACE_PARAMETER of UART_TX_1 : signal is "XIL_INTERFACENAME DATA.UART_TX_1, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_miso : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MISO DATA";
attribute X_INTERFACE_PARAMETER of m_spi_miso : signal is "XIL_INTERFACENAME DATA.M_SPI_MISO, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_miso_1 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MISO_1 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_miso_1 : signal is "XIL_INTERFACENAME DATA.M_SPI_MISO_1, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_miso_2 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MISO_2 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_miso_2 : signal is "XIL_INTERFACENAME DATA.M_SPI_MISO_2, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_miso_3 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MISO_3 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_miso_3 : signal is "XIL_INTERFACENAME DATA.M_SPI_MISO_3, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_mosi : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MOSI DATA";
attribute X_INTERFACE_PARAMETER of m_spi_mosi : signal is "XIL_INTERFACENAME DATA.M_SPI_MOSI, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_mosi_1 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MOSI_1 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_mosi_1 : signal is "XIL_INTERFACENAME DATA.M_SPI_MOSI_1, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_mosi_2 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MOSI_2 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_mosi_2 : signal is "XIL_INTERFACENAME DATA.M_SPI_MOSI_2, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_mosi_3 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MOSI_3 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_mosi_3 : signal is "XIL_INTERFACENAME DATA.M_SPI_MOSI_3, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_sclk : signal is "xilinx.com:signal:clock:1.0 CLK.M_SPI_SCLK CLK";
attribute X_INTERFACE_PARAMETER of m_spi_sclk : signal is "XIL_INTERFACENAME CLK.M_SPI_SCLK, CLK_DOMAIN DemoInterconnect_axi_spi_master_0_0_m_spi_sclk, FREQ_HZ 100000000, PHASE 0.000";
attribute X_INTERFACE_INFO of m_spi_sclk_1 : signal is "xilinx.com:signal:clock:1.0 CLK.M_SPI_SCLK_1 CLK";
attribute X_INTERFACE_PARAMETER of m_spi_sclk_1 : signal is "XIL_INTERFACENAME CLK.M_SPI_SCLK_1, CLK_DOMAIN DemoInterconnect_axi_spi_master_0_1_m_spi_sclk, FREQ_HZ 100000000, PHASE 0.000";
attribute X_INTERFACE_INFO of m_spi_sclk_2 : signal is "xilinx.com:signal:clock:1.0 CLK.M_SPI_SCLK_2 CLK";
attribute X_INTERFACE_PARAMETER of m_spi_sclk_2 : signal is "XIL_INTERFACENAME CLK.M_SPI_SCLK_2, CLK_DOMAIN DemoInterconnect_axi_spi_master_1_0_m_spi_sclk, FREQ_HZ 100000000, PHASE 0.000";
attribute X_INTERFACE_INFO of m_spi_sclk_3 : signal is "xilinx.com:signal:clock:1.0 CLK.M_SPI_SCLK_3 CLK";
attribute X_INTERFACE_PARAMETER of m_spi_sclk_3 : signal is "XIL_INTERFACENAME CLK.M_SPI_SCLK_3, CLK_DOMAIN DemoInterconnect_axi_spi_master_1_1_m_spi_sclk, FREQ_HZ 100000000, PHASE 0.000";
attribute X_INTERFACE_INFO of m_spi_ss : signal is "xilinx.com:signal:clockenable:1.0 CE.M_SPI_SS CE";
attribute X_INTERFACE_PARAMETER of m_spi_ss : signal is "XIL_INTERFACENAME CE.M_SPI_SS, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of m_spi_ss_1 : signal is "xilinx.com:signal:clockenable:1.0 CE.M_SPI_SS_1 CE";
attribute X_INTERFACE_PARAMETER of m_spi_ss_1 : signal is "XIL_INTERFACENAME CE.M_SPI_SS_1, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of m_spi_ss_2 : signal is "xilinx.com:signal:clockenable:1.0 CE.M_SPI_SS_2 CE";
attribute X_INTERFACE_PARAMETER of m_spi_ss_2 : signal is "XIL_INTERFACENAME CE.M_SPI_SS_2, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of m_spi_ss_3 : signal is "xilinx.com:signal:clockenable:1.0 CE.M_SPI_SS_3 CE";
attribute X_INTERFACE_PARAMETER of m_spi_ss_3 : signal is "XIL_INTERFACENAME CE.M_SPI_SS_3, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of sys_clk : signal is "xilinx.com:signal:clock:1.0 CLK.SYS_CLK CLK";
attribute X_INTERFACE_PARAMETER of sys_clk : signal is "XIL_INTERFACENAME CLK.SYS_CLK, ASSOCIATED_RESET sys_reset, CLK_DOMAIN DemoInterconnect_sys_clk, FREQ_HZ 12000000, PHASE 0.000";
attribute X_INTERFACE_INFO of sys_reset : signal is "xilinx.com:signal:reset:1.0 RST.SYS_RESET RST";
attribute X_INTERFACE_PARAMETER of sys_reset : signal is "XIL_INTERFACENAME RST.SYS_RESET, POLARITY ACTIVE_HIGH";
begin
LED0_pll_aclk <= clk_wiz_0_clk_out1;
LED1_pll_uart <= clk_wiz_0_uart;
LED2_pll_lock <= clk_wiz_0_locked;
UART_RX_0_1 <= UART_RX_0;
UART_RX_1_1 <= UART_RX_1;
UART_TX_0 <= uart_transceiver_0_o_TX_Serial;
UART_TX_1 <= uart_transceiver_1_o_TX_Serial;
\^m_spi_miso_1\ <= m_spi_miso;
m_spi_miso_1_1 <= m_spi_miso_1;
m_spi_miso_2_1 <= m_spi_miso_2;
m_spi_miso_3_1 <= m_spi_miso_3;
m_spi_mosi <= axi_spi_master_0_m_spi_mosi;
m_spi_mosi_1 <= axi_spi_master_1_m_spi_mosi;
m_spi_mosi_2 <= axi_spi_master_2_m_spi_mosi;
m_spi_mosi_3 <= axi_spi_master_3_m_spi_mosi;
m_spi_sclk <= axi_spi_master_0_m_spi_sclk;
m_spi_sclk_1 <= axi_spi_master_1_m_spi_sclk;
m_spi_sclk_2 <= axi_spi_master_2_m_spi_sclk;
m_spi_sclk_3 <= axi_spi_master_3_m_spi_sclk;
m_spi_ss <= axi_spi_master_0_m_spi_ss;
m_spi_ss_1 <= axi_spi_master_1_m_spi_ss;
m_spi_ss_2 <= axi_spi_master_2_m_spi_ss;
m_spi_ss_3 <= axi_spi_master_3_m_spi_ss;
sys_clk_1 <= sys_clk;
axi_spi_master_0: component DemoInterconnect_axi_spi_master_0_0
port map (
m_spi_miso => \^m_spi_miso_1\,
m_spi_mosi => axi_spi_master_0_m_spi_mosi,
m_spi_sclk => axi_spi_master_0_m_spi_sclk,
m_spi_ss => axi_spi_master_0_m_spi_ss,
s00_axi_aclk => clk_wiz_0_clk_out1,
s00_axi_araddr(3 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => clk_wiz_0_locked,
s00_axi_arprot(2 downto 0) => axi_interconnect_0_M00_AXI_ARPROT(2 downto 0),
s00_axi_arready => axi_interconnect_0_M00_AXI_ARREADY,
s00_axi_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
s00_axi_awaddr(3 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => axi_interconnect_0_M00_AXI_AWPROT(2 downto 0),
s00_axi_awready => axi_interconnect_0_M00_AXI_AWREADY,
s00_axi_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
s00_axi_bready => axi_interconnect_0_M00_AXI_BREADY,
s00_axi_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
s00_axi_bvalid => axi_interconnect_0_M00_AXI_BVALID,
s00_axi_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
s00_axi_rready => axi_interconnect_0_M00_AXI_RREADY,
s00_axi_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
s00_axi_rvalid => axi_interconnect_0_M00_AXI_RVALID,
s00_axi_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
s00_axi_wready => axi_interconnect_0_M00_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => axi_interconnect_0_M00_AXI_WVALID
);
axi_spi_master_1: component DemoInterconnect_axi_spi_master_0_1
port map (
m_spi_miso => m_spi_miso_1_1,
m_spi_mosi => axi_spi_master_1_m_spi_mosi,
m_spi_sclk => axi_spi_master_1_m_spi_sclk,
m_spi_ss => axi_spi_master_1_m_spi_ss,
s00_axi_aclk => clk_wiz_0_clk_out1,
s00_axi_araddr(3 downto 0) => axi_interconnect_0_M01_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => clk_wiz_0_locked,
s00_axi_arprot(2 downto 0) => axi_interconnect_0_M01_AXI_ARPROT(2 downto 0),
s00_axi_arready => axi_interconnect_0_M01_AXI_ARREADY,
s00_axi_arvalid => axi_interconnect_0_M01_AXI_ARVALID,
s00_axi_awaddr(3 downto 0) => axi_interconnect_0_M01_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => axi_interconnect_0_M01_AXI_AWPROT(2 downto 0),
s00_axi_awready => axi_interconnect_0_M01_AXI_AWREADY,
s00_axi_awvalid => axi_interconnect_0_M01_AXI_AWVALID,
s00_axi_bready => axi_interconnect_0_M01_AXI_BREADY,
s00_axi_bresp(1 downto 0) => axi_interconnect_0_M01_AXI_BRESP(1 downto 0),
s00_axi_bvalid => axi_interconnect_0_M01_AXI_BVALID,
s00_axi_rdata(31 downto 0) => axi_interconnect_0_M01_AXI_RDATA(31 downto 0),
s00_axi_rready => axi_interconnect_0_M01_AXI_RREADY,
s00_axi_rresp(1 downto 0) => axi_interconnect_0_M01_AXI_RRESP(1 downto 0),
s00_axi_rvalid => axi_interconnect_0_M01_AXI_RVALID,
s00_axi_wdata(31 downto 0) => axi_interconnect_0_M01_AXI_WDATA(31 downto 0),
s00_axi_wready => axi_interconnect_0_M01_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => axi_interconnect_0_M01_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => axi_interconnect_0_M01_AXI_WVALID
);
axi_spi_master_2: component DemoInterconnect_axi_spi_master_1_0
port map (
m_spi_miso => m_spi_miso_2_1,
m_spi_mosi => axi_spi_master_2_m_spi_mosi,
m_spi_sclk => axi_spi_master_2_m_spi_sclk,
m_spi_ss => axi_spi_master_2_m_spi_ss,
s00_axi_aclk => clk_wiz_0_clk_out1,
s00_axi_araddr(3 downto 0) => axi_interconnect_0_M02_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => clk_wiz_0_locked,
s00_axi_arprot(2 downto 0) => axi_interconnect_0_M02_AXI_ARPROT(2 downto 0),
s00_axi_arready => axi_interconnect_0_M02_AXI_ARREADY,
s00_axi_arvalid => axi_interconnect_0_M02_AXI_ARVALID,
s00_axi_awaddr(3 downto 0) => axi_interconnect_0_M02_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => axi_interconnect_0_M02_AXI_AWPROT(2 downto 0),
s00_axi_awready => axi_interconnect_0_M02_AXI_AWREADY,
s00_axi_awvalid => axi_interconnect_0_M02_AXI_AWVALID,
s00_axi_bready => axi_interconnect_0_M02_AXI_BREADY,
s00_axi_bresp(1 downto 0) => axi_interconnect_0_M02_AXI_BRESP(1 downto 0),
s00_axi_bvalid => axi_interconnect_0_M02_AXI_BVALID,
s00_axi_rdata(31 downto 0) => axi_interconnect_0_M02_AXI_RDATA(31 downto 0),
s00_axi_rready => axi_interconnect_0_M02_AXI_RREADY,
s00_axi_rresp(1 downto 0) => axi_interconnect_0_M02_AXI_RRESP(1 downto 0),
s00_axi_rvalid => axi_interconnect_0_M02_AXI_RVALID,
s00_axi_wdata(31 downto 0) => axi_interconnect_0_M02_AXI_WDATA(31 downto 0),
s00_axi_wready => axi_interconnect_0_M02_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => axi_interconnect_0_M02_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => axi_interconnect_0_M02_AXI_WVALID
);
axi_spi_master_3: component DemoInterconnect_axi_spi_master_1_1
port map (
m_spi_miso => m_spi_miso_3_1,
m_spi_mosi => axi_spi_master_3_m_spi_mosi,
m_spi_sclk => axi_spi_master_3_m_spi_sclk,
m_spi_ss => axi_spi_master_3_m_spi_ss,
s00_axi_aclk => clk_wiz_0_clk_out1,
s00_axi_araddr(3 downto 0) => axi_interconnect_0_M03_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => clk_wiz_0_locked,
s00_axi_arprot(2 downto 0) => axi_interconnect_0_M03_AXI_ARPROT(2 downto 0),
s00_axi_arready => axi_interconnect_0_M03_AXI_ARREADY,
s00_axi_arvalid => axi_interconnect_0_M03_AXI_ARVALID,
s00_axi_awaddr(3 downto 0) => axi_interconnect_0_M03_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => axi_interconnect_0_M03_AXI_AWPROT(2 downto 0),
s00_axi_awready => axi_interconnect_0_M03_AXI_AWREADY,
s00_axi_awvalid => axi_interconnect_0_M03_AXI_AWVALID,
s00_axi_bready => axi_interconnect_0_M03_AXI_BREADY,
s00_axi_bresp(1 downto 0) => axi_interconnect_0_M03_AXI_BRESP(1 downto 0),
s00_axi_bvalid => axi_interconnect_0_M03_AXI_BVALID,
s00_axi_rdata(31 downto 0) => axi_interconnect_0_M03_AXI_RDATA(31 downto 0),
s00_axi_rready => axi_interconnect_0_M03_AXI_RREADY,
s00_axi_rresp(1 downto 0) => axi_interconnect_0_M03_AXI_RRESP(1 downto 0),
s00_axi_rvalid => axi_interconnect_0_M03_AXI_RVALID,
s00_axi_wdata(31 downto 0) => axi_interconnect_0_M03_AXI_WDATA(31 downto 0),
s00_axi_wready => axi_interconnect_0_M03_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => axi_interconnect_0_M03_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => axi_interconnect_0_M03_AXI_WVALID
);
clk_wiz_0: component DemoInterconnect_clk_wiz_0_0
port map (
aclk => clk_wiz_0_clk_out1,
clk_in1 => sys_clk_1,
locked => clk_wiz_0_locked,
reset => sys_reset,
uart => clk_wiz_0_uart
);
ila_0: component DemoInterconnect_ila_0_0
port map (
clk => clk_wiz_0_clk_out1,
probe0(0) => uart_transceiver_0_o_RX_Done,
probe1(7 downto 0) => uart_transceiver_0_o_RX_Byte(7 downto 0),
probe2(0) => interface_axi_master_0_if00_load_out,
probe3(7 downto 0) => interface_axi_master_0_if00_data_out(7 downto 0)
);
interconnect: entity work.DemoInterconnect_axi_interconnect_0_0
port map (
ACLK => clk_wiz_0_clk_out1,
ARESETN => clk_wiz_0_locked,
M00_ACLK => clk_wiz_0_clk_out1,
M00_ARESETN => clk_wiz_0_locked,
M00_AXI_araddr(31 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arprot(2 downto 0) => axi_interconnect_0_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arready => axi_interconnect_0_M00_AXI_ARREADY,
M00_AXI_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awprot(2 downto 0) => axi_interconnect_0_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awready => axi_interconnect_0_M00_AXI_AWREADY,
M00_AXI_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
M00_AXI_bready => axi_interconnect_0_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_interconnect_0_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready => axi_interconnect_0_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_interconnect_0_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready => axi_interconnect_0_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => axi_interconnect_0_M00_AXI_WVALID,
M01_ACLK => clk_wiz_0_clk_out1,
M01_ARESETN => clk_wiz_0_locked,
M01_AXI_araddr(31 downto 0) => axi_interconnect_0_M01_AXI_ARADDR(31 downto 0),
M01_AXI_arprot(2 downto 0) => axi_interconnect_0_M01_AXI_ARPROT(2 downto 0),
M01_AXI_arready => axi_interconnect_0_M01_AXI_ARREADY,
M01_AXI_arvalid => axi_interconnect_0_M01_AXI_ARVALID,
M01_AXI_awaddr(31 downto 0) => axi_interconnect_0_M01_AXI_AWADDR(31 downto 0),
M01_AXI_awprot(2 downto 0) => axi_interconnect_0_M01_AXI_AWPROT(2 downto 0),
M01_AXI_awready => axi_interconnect_0_M01_AXI_AWREADY,
M01_AXI_awvalid => axi_interconnect_0_M01_AXI_AWVALID,
M01_AXI_bready => axi_interconnect_0_M01_AXI_BREADY,
M01_AXI_bresp(1 downto 0) => axi_interconnect_0_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid => axi_interconnect_0_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => axi_interconnect_0_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready => axi_interconnect_0_M01_AXI_RREADY,
M01_AXI_rresp(1 downto 0) => axi_interconnect_0_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid => axi_interconnect_0_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => axi_interconnect_0_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready => axi_interconnect_0_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => axi_interconnect_0_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid => axi_interconnect_0_M01_AXI_WVALID,
M02_ACLK => clk_wiz_0_clk_out1,
M02_ARESETN => clk_wiz_0_locked,
M02_AXI_araddr(31 downto 0) => axi_interconnect_0_M02_AXI_ARADDR(31 downto 0),
M02_AXI_arprot(2 downto 0) => axi_interconnect_0_M02_AXI_ARPROT(2 downto 0),
M02_AXI_arready => axi_interconnect_0_M02_AXI_ARREADY,
M02_AXI_arvalid => axi_interconnect_0_M02_AXI_ARVALID,
M02_AXI_awaddr(31 downto 0) => axi_interconnect_0_M02_AXI_AWADDR(31 downto 0),
M02_AXI_awprot(2 downto 0) => axi_interconnect_0_M02_AXI_AWPROT(2 downto 0),
M02_AXI_awready => axi_interconnect_0_M02_AXI_AWREADY,
M02_AXI_awvalid => axi_interconnect_0_M02_AXI_AWVALID,
M02_AXI_bready => axi_interconnect_0_M02_AXI_BREADY,
M02_AXI_bresp(1 downto 0) => axi_interconnect_0_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid => axi_interconnect_0_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => axi_interconnect_0_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready => axi_interconnect_0_M02_AXI_RREADY,
M02_AXI_rresp(1 downto 0) => axi_interconnect_0_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid => axi_interconnect_0_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => axi_interconnect_0_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready => axi_interconnect_0_M02_AXI_WREADY,
M02_AXI_wstrb(3 downto 0) => axi_interconnect_0_M02_AXI_WSTRB(3 downto 0),
M02_AXI_wvalid => axi_interconnect_0_M02_AXI_WVALID,
M03_ACLK => clk_wiz_0_clk_out1,
M03_ARESETN => clk_wiz_0_locked,
M03_AXI_araddr(31 downto 0) => axi_interconnect_0_M03_AXI_ARADDR(31 downto 0),
M03_AXI_arprot(2 downto 0) => axi_interconnect_0_M03_AXI_ARPROT(2 downto 0),
M03_AXI_arready => axi_interconnect_0_M03_AXI_ARREADY,
M03_AXI_arvalid => axi_interconnect_0_M03_AXI_ARVALID,
M03_AXI_awaddr(31 downto 0) => axi_interconnect_0_M03_AXI_AWADDR(31 downto 0),
M03_AXI_awprot(2 downto 0) => axi_interconnect_0_M03_AXI_AWPROT(2 downto 0),
M03_AXI_awready => axi_interconnect_0_M03_AXI_AWREADY,
M03_AXI_awvalid => axi_interconnect_0_M03_AXI_AWVALID,
M03_AXI_bready => axi_interconnect_0_M03_AXI_BREADY,
M03_AXI_bresp(1 downto 0) => axi_interconnect_0_M03_AXI_BRESP(1 downto 0),
M03_AXI_bvalid => axi_interconnect_0_M03_AXI_BVALID,
M03_AXI_rdata(31 downto 0) => axi_interconnect_0_M03_AXI_RDATA(31 downto 0),
M03_AXI_rready => axi_interconnect_0_M03_AXI_RREADY,
M03_AXI_rresp(1 downto 0) => axi_interconnect_0_M03_AXI_RRESP(1 downto 0),
M03_AXI_rvalid => axi_interconnect_0_M03_AXI_RVALID,
M03_AXI_wdata(31 downto 0) => axi_interconnect_0_M03_AXI_WDATA(31 downto 0),
M03_AXI_wready => axi_interconnect_0_M03_AXI_WREADY,
M03_AXI_wstrb(3 downto 0) => axi_interconnect_0_M03_AXI_WSTRB(3 downto 0),
M03_AXI_wvalid => axi_interconnect_0_M03_AXI_WVALID,
M04_ACLK => clk_wiz_0_clk_out1,
M04_ARESETN => clk_wiz_0_locked,
M04_AXI_araddr(31 downto 0) => axi_interconnect_0_M04_AXI_ARADDR(31 downto 0),
M04_AXI_arready => axi_interconnect_0_M04_AXI_ARREADY,
M04_AXI_arvalid => axi_interconnect_0_M04_AXI_ARVALID,
M04_AXI_awaddr(31 downto 0) => axi_interconnect_0_M04_AXI_AWADDR(31 downto 0),
M04_AXI_awready => axi_interconnect_0_M04_AXI_AWREADY,
M04_AXI_awvalid => axi_interconnect_0_M04_AXI_AWVALID,
M04_AXI_bready => axi_interconnect_0_M04_AXI_BREADY,
M04_AXI_bresp(1 downto 0) => axi_interconnect_0_M04_AXI_BRESP(1 downto 0),
M04_AXI_bvalid => axi_interconnect_0_M04_AXI_BVALID,
M04_AXI_rdata(31 downto 0) => axi_interconnect_0_M04_AXI_RDATA(31 downto 0),
M04_AXI_rready => axi_interconnect_0_M04_AXI_RREADY,
M04_AXI_rresp(1 downto 0) => axi_interconnect_0_M04_AXI_RRESP(1 downto 0),
M04_AXI_rvalid => axi_interconnect_0_M04_AXI_RVALID,
M04_AXI_wdata(31 downto 0) => axi_interconnect_0_M04_AXI_WDATA(31 downto 0),
M04_AXI_wready => axi_interconnect_0_M04_AXI_WREADY,
M04_AXI_wstrb(3 downto 0) => axi_interconnect_0_M04_AXI_WSTRB(3 downto 0),
M04_AXI_wvalid => axi_interconnect_0_M04_AXI_WVALID,
M05_ACLK => clk_wiz_0_clk_out1,
M05_ARESETN => clk_wiz_0_locked,
M05_AXI_araddr(31 downto 0) => axi_interconnect_0_M05_AXI_ARADDR(31 downto 0),
M05_AXI_arready => axi_interconnect_0_M05_AXI_ARREADY,
M05_AXI_arvalid => axi_interconnect_0_M05_AXI_ARVALID,
M05_AXI_awaddr(31 downto 0) => axi_interconnect_0_M05_AXI_AWADDR(31 downto 0),
M05_AXI_awready => axi_interconnect_0_M05_AXI_AWREADY,
M05_AXI_awvalid => axi_interconnect_0_M05_AXI_AWVALID,
M05_AXI_bready => axi_interconnect_0_M05_AXI_BREADY,
M05_AXI_bresp(1 downto 0) => axi_interconnect_0_M05_AXI_BRESP(1 downto 0),
M05_AXI_bvalid => axi_interconnect_0_M05_AXI_BVALID,
M05_AXI_rdata(31 downto 0) => axi_interconnect_0_M05_AXI_RDATA(31 downto 0),
M05_AXI_rready => axi_interconnect_0_M05_AXI_RREADY,
M05_AXI_rresp(1 downto 0) => axi_interconnect_0_M05_AXI_RRESP(1 downto 0),
M05_AXI_rvalid => axi_interconnect_0_M05_AXI_RVALID,
M05_AXI_wdata(31 downto 0) => axi_interconnect_0_M05_AXI_WDATA(31 downto 0),
M05_AXI_wready => axi_interconnect_0_M05_AXI_WREADY,
M05_AXI_wstrb(3 downto 0) => axi_interconnect_0_M05_AXI_WSTRB(3 downto 0),
M05_AXI_wvalid => axi_interconnect_0_M05_AXI_WVALID,
M06_ACLK => clk_wiz_0_clk_out1,
M06_ARESETN => clk_wiz_0_locked,
M06_AXI_araddr(31 downto 0) => axi_interconnect_0_M06_AXI_ARADDR(31 downto 0),
M06_AXI_arready => axi_interconnect_0_M06_AXI_ARREADY,
M06_AXI_arvalid => axi_interconnect_0_M06_AXI_ARVALID,
M06_AXI_awaddr(31 downto 0) => axi_interconnect_0_M06_AXI_AWADDR(31 downto 0),
M06_AXI_awready => axi_interconnect_0_M06_AXI_AWREADY,
M06_AXI_awvalid => axi_interconnect_0_M06_AXI_AWVALID,
M06_AXI_bready => axi_interconnect_0_M06_AXI_BREADY,
M06_AXI_bresp(1 downto 0) => axi_interconnect_0_M06_AXI_BRESP(1 downto 0),
M06_AXI_bvalid => axi_interconnect_0_M06_AXI_BVALID,
M06_AXI_rdata(31 downto 0) => axi_interconnect_0_M06_AXI_RDATA(31 downto 0),
M06_AXI_rready => axi_interconnect_0_M06_AXI_RREADY,
M06_AXI_rresp(1 downto 0) => axi_interconnect_0_M06_AXI_RRESP(1 downto 0),
M06_AXI_rvalid => axi_interconnect_0_M06_AXI_RVALID,
M06_AXI_wdata(31 downto 0) => axi_interconnect_0_M06_AXI_WDATA(31 downto 0),
M06_AXI_wready => axi_interconnect_0_M06_AXI_WREADY,
M06_AXI_wstrb(3 downto 0) => axi_interconnect_0_M06_AXI_WSTRB(3 downto 0),
M06_AXI_wvalid => axi_interconnect_0_M06_AXI_WVALID,
S00_ACLK => clk_wiz_0_clk_out1,
S00_ARESETN => clk_wiz_0_locked,
S00_AXI_araddr(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_ARADDR(31 downto 0),
S00_AXI_arprot(2 downto 0) => internoc_ni_axi_master_0_M00_AXI_ARPROT(2 downto 0),
S00_AXI_arready => internoc_ni_axi_master_0_M00_AXI_ARREADY,
S00_AXI_arvalid => internoc_ni_axi_master_0_M00_AXI_ARVALID,
S00_AXI_awaddr(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_AWADDR(31 downto 0),
S00_AXI_awprot(2 downto 0) => internoc_ni_axi_master_0_M00_AXI_AWPROT(2 downto 0),
S00_AXI_awready => internoc_ni_axi_master_0_M00_AXI_AWREADY,
S00_AXI_awvalid => internoc_ni_axi_master_0_M00_AXI_AWVALID,
S00_AXI_bready => internoc_ni_axi_master_0_M00_AXI_BREADY,
S00_AXI_bresp(1 downto 0) => internoc_ni_axi_master_0_M00_AXI_BRESP(1 downto 0),
S00_AXI_bvalid => internoc_ni_axi_master_0_M00_AXI_BVALID,
S00_AXI_rdata(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_RDATA(31 downto 0),
S00_AXI_rready => internoc_ni_axi_master_0_M00_AXI_RREADY,
S00_AXI_rresp(1 downto 0) => internoc_ni_axi_master_0_M00_AXI_RRESP(1 downto 0),
S00_AXI_rvalid => internoc_ni_axi_master_0_M00_AXI_RVALID,
S00_AXI_wdata(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_WDATA(31 downto 0),
S00_AXI_wready => internoc_ni_axi_master_0_M00_AXI_WREADY,
S00_AXI_wstrb(3 downto 0) => internoc_ni_axi_master_0_M00_AXI_WSTRB(3 downto 0),
S00_AXI_wvalid => internoc_ni_axi_master_0_M00_AXI_WVALID,
S01_ACLK => clk_wiz_0_clk_out1,
S01_ARESETN => clk_wiz_0_locked,
S01_AXI_araddr(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_ARADDR(31 downto 0),
S01_AXI_arprot(2 downto 0) => internoc_ni_axi_master_1_M00_AXI_ARPROT(2 downto 0),
S01_AXI_arready => internoc_ni_axi_master_1_M00_AXI_ARREADY,
S01_AXI_arvalid => internoc_ni_axi_master_1_M00_AXI_ARVALID,
S01_AXI_awaddr(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_AWADDR(31 downto 0),
S01_AXI_awprot(2 downto 0) => internoc_ni_axi_master_1_M00_AXI_AWPROT(2 downto 0),
S01_AXI_awready => internoc_ni_axi_master_1_M00_AXI_AWREADY,
S01_AXI_awvalid => internoc_ni_axi_master_1_M00_AXI_AWVALID,
S01_AXI_bready => internoc_ni_axi_master_1_M00_AXI_BREADY,
S01_AXI_bresp(1 downto 0) => internoc_ni_axi_master_1_M00_AXI_BRESP(1 downto 0),
S01_AXI_bvalid => internoc_ni_axi_master_1_M00_AXI_BVALID,
S01_AXI_rdata(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_RDATA(31 downto 0),
S01_AXI_rready => internoc_ni_axi_master_1_M00_AXI_RREADY,
S01_AXI_rresp(1 downto 0) => internoc_ni_axi_master_1_M00_AXI_RRESP(1 downto 0),
S01_AXI_rvalid => internoc_ni_axi_master_1_M00_AXI_RVALID,
S01_AXI_wdata(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_WDATA(31 downto 0),
S01_AXI_wready => internoc_ni_axi_master_1_M00_AXI_WREADY,
S01_AXI_wstrb(3 downto 0) => internoc_ni_axi_master_1_M00_AXI_WSTRB(3 downto 0),
S01_AXI_wvalid => internoc_ni_axi_master_1_M00_AXI_WVALID,
S02_ACLK => clk_wiz_0_clk_out1,
S02_ARESETN => clk_wiz_0_locked,
S02_AXI_araddr(31 downto 0) => jtag_axi_0_M_AXI_ARADDR(31 downto 0),
S02_AXI_arburst(1 downto 0) => jtag_axi_0_M_AXI_ARBURST(1 downto 0),
S02_AXI_arcache(3 downto 0) => jtag_axi_0_M_AXI_ARCACHE(3 downto 0),
S02_AXI_arid(0) => jtag_axi_0_M_AXI_ARID(0),
S02_AXI_arlen(7 downto 0) => jtag_axi_0_M_AXI_ARLEN(7 downto 0),
S02_AXI_arlock => jtag_axi_0_M_AXI_ARLOCK,
S02_AXI_arprot(2 downto 0) => jtag_axi_0_M_AXI_ARPROT(2 downto 0),
S02_AXI_arqos(3 downto 0) => jtag_axi_0_M_AXI_ARQOS(3 downto 0),
S02_AXI_arready => jtag_axi_0_M_AXI_ARREADY,
S02_AXI_arsize(2 downto 0) => jtag_axi_0_M_AXI_ARSIZE(2 downto 0),
S02_AXI_arvalid => jtag_axi_0_M_AXI_ARVALID,
S02_AXI_awaddr(31 downto 0) => jtag_axi_0_M_AXI_AWADDR(31 downto 0),
S02_AXI_awburst(1 downto 0) => jtag_axi_0_M_AXI_AWBURST(1 downto 0),
S02_AXI_awcache(3 downto 0) => jtag_axi_0_M_AXI_AWCACHE(3 downto 0),
S02_AXI_awid(0) => jtag_axi_0_M_AXI_AWID(0),
S02_AXI_awlen(7 downto 0) => jtag_axi_0_M_AXI_AWLEN(7 downto 0),
S02_AXI_awlock => jtag_axi_0_M_AXI_AWLOCK,
S02_AXI_awprot(2 downto 0) => jtag_axi_0_M_AXI_AWPROT(2 downto 0),
S02_AXI_awqos(3 downto 0) => jtag_axi_0_M_AXI_AWQOS(3 downto 0),
S02_AXI_awready => jtag_axi_0_M_AXI_AWREADY,
S02_AXI_awsize(2 downto 0) => jtag_axi_0_M_AXI_AWSIZE(2 downto 0),
S02_AXI_awvalid => jtag_axi_0_M_AXI_AWVALID,
S02_AXI_bid(0) => jtag_axi_0_M_AXI_BID(0),
S02_AXI_bready => jtag_axi_0_M_AXI_BREADY,
S02_AXI_bresp(1 downto 0) => jtag_axi_0_M_AXI_BRESP(1 downto 0),
S02_AXI_bvalid => jtag_axi_0_M_AXI_BVALID,
S02_AXI_rdata(31 downto 0) => jtag_axi_0_M_AXI_RDATA(31 downto 0),
S02_AXI_rid(0) => jtag_axi_0_M_AXI_RID(0),
S02_AXI_rlast => jtag_axi_0_M_AXI_RLAST,
S02_AXI_rready => jtag_axi_0_M_AXI_RREADY,
S02_AXI_rresp(1 downto 0) => jtag_axi_0_M_AXI_RRESP(1 downto 0),
S02_AXI_rvalid => jtag_axi_0_M_AXI_RVALID,
S02_AXI_wdata(31 downto 0) => jtag_axi_0_M_AXI_WDATA(31 downto 0),
S02_AXI_wlast => jtag_axi_0_M_AXI_WLAST,
S02_AXI_wready => jtag_axi_0_M_AXI_WREADY,
S02_AXI_wstrb(3 downto 0) => jtag_axi_0_M_AXI_WSTRB(3 downto 0),
S02_AXI_wvalid => jtag_axi_0_M_AXI_WVALID
);
internoc_ni_axi_master_0: component DemoInterconnect_internoc_ni_axi_master_0_0
port map (
if00_data_in(7 downto 0) => uart_transceiver_0_o_RX_Byte(7 downto 0),
if00_data_out(7 downto 0) => interface_axi_master_0_if00_data_out(7 downto 0),
if00_load_in => uart_transceiver_0_o_RX_Done,
if00_load_out => interface_axi_master_0_if00_load_out,
if00_send_busy => uart_transceiver_0_o_TX_Active,
if00_send_done => uart_transceiver_0_o_TX_Done,
m00_axi_aclk => clk_wiz_0_clk_out1,
m00_axi_araddr(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_ARADDR(31 downto 0),
m00_axi_aresetn => clk_wiz_0_locked,
m00_axi_arprot(2 downto 0) => internoc_ni_axi_master_0_M00_AXI_ARPROT(2 downto 0),
m00_axi_arready => internoc_ni_axi_master_0_M00_AXI_ARREADY,
m00_axi_arvalid => internoc_ni_axi_master_0_M00_AXI_ARVALID,
m00_axi_awaddr(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_AWADDR(31 downto 0),
m00_axi_awprot(2 downto 0) => internoc_ni_axi_master_0_M00_AXI_AWPROT(2 downto 0),
m00_axi_awready => internoc_ni_axi_master_0_M00_AXI_AWREADY,
m00_axi_awvalid => internoc_ni_axi_master_0_M00_AXI_AWVALID,
m00_axi_bready => internoc_ni_axi_master_0_M00_AXI_BREADY,
m00_axi_bresp(1 downto 0) => internoc_ni_axi_master_0_M00_AXI_BRESP(1 downto 0),
m00_axi_bvalid => internoc_ni_axi_master_0_M00_AXI_BVALID,
m00_axi_rdata(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_RDATA(31 downto 0),
m00_axi_rready => internoc_ni_axi_master_0_M00_AXI_RREADY,
m00_axi_rresp(1 downto 0) => internoc_ni_axi_master_0_M00_AXI_RRESP(1 downto 0),
m00_axi_rvalid => internoc_ni_axi_master_0_M00_AXI_RVALID,
m00_axi_wdata(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_WDATA(31 downto 0),
m00_axi_wready => internoc_ni_axi_master_0_M00_AXI_WREADY,
m00_axi_wstrb(3 downto 0) => internoc_ni_axi_master_0_M00_AXI_WSTRB(3 downto 0),
m00_axi_wvalid => internoc_ni_axi_master_0_M00_AXI_WVALID
);
internoc_ni_axi_master_1: component DemoInterconnect_internoc_ni_axi_master_1_0
port map (
if00_data_in(7 downto 0) => uart_transceiver_1_o_RX_Byte(7 downto 0),
if00_data_out(7 downto 0) => internoc_ni_axi_master_1_if00_data_out(7 downto 0),
if00_load_in => uart_transceiver_1_o_RX_Done,
if00_load_out => internoc_ni_axi_master_1_if00_load_out,
if00_send_busy => uart_transceiver_1_o_TX_Active,
if00_send_done => uart_transceiver_1_o_TX_Done,
m00_axi_aclk => clk_wiz_0_clk_out1,
m00_axi_araddr(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_ARADDR(31 downto 0),
m00_axi_aresetn => clk_wiz_0_locked,
m00_axi_arprot(2 downto 0) => internoc_ni_axi_master_1_M00_AXI_ARPROT(2 downto 0),
m00_axi_arready => internoc_ni_axi_master_1_M00_AXI_ARREADY,
m00_axi_arvalid => internoc_ni_axi_master_1_M00_AXI_ARVALID,
m00_axi_awaddr(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_AWADDR(31 downto 0),
m00_axi_awprot(2 downto 0) => internoc_ni_axi_master_1_M00_AXI_AWPROT(2 downto 0),
m00_axi_awready => internoc_ni_axi_master_1_M00_AXI_AWREADY,
m00_axi_awvalid => internoc_ni_axi_master_1_M00_AXI_AWVALID,
m00_axi_bready => internoc_ni_axi_master_1_M00_AXI_BREADY,
m00_axi_bresp(1 downto 0) => internoc_ni_axi_master_1_M00_AXI_BRESP(1 downto 0),
m00_axi_bvalid => internoc_ni_axi_master_1_M00_AXI_BVALID,
m00_axi_rdata(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_RDATA(31 downto 0),
m00_axi_rready => internoc_ni_axi_master_1_M00_AXI_RREADY,
m00_axi_rresp(1 downto 0) => internoc_ni_axi_master_1_M00_AXI_RRESP(1 downto 0),
m00_axi_rvalid => internoc_ni_axi_master_1_M00_AXI_RVALID,
m00_axi_wdata(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_WDATA(31 downto 0),
m00_axi_wready => internoc_ni_axi_master_1_M00_AXI_WREADY,
m00_axi_wstrb(3 downto 0) => internoc_ni_axi_master_1_M00_AXI_WSTRB(3 downto 0),
m00_axi_wvalid => internoc_ni_axi_master_1_M00_AXI_WVALID
);
jtag_axi_0: component DemoInterconnect_jtag_axi_0_0
port map (
aclk => clk_wiz_0_clk_out1,
aresetn => clk_wiz_0_locked,
m_axi_araddr(31 downto 0) => jtag_axi_0_M_AXI_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => jtag_axi_0_M_AXI_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => jtag_axi_0_M_AXI_ARCACHE(3 downto 0),
m_axi_arid(0) => jtag_axi_0_M_AXI_ARID(0),
m_axi_arlen(7 downto 0) => jtag_axi_0_M_AXI_ARLEN(7 downto 0),
m_axi_arlock => jtag_axi_0_M_AXI_ARLOCK,
m_axi_arprot(2 downto 0) => jtag_axi_0_M_AXI_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => jtag_axi_0_M_AXI_ARQOS(3 downto 0),
m_axi_arready => jtag_axi_0_M_AXI_ARREADY,
m_axi_arsize(2 downto 0) => jtag_axi_0_M_AXI_ARSIZE(2 downto 0),
m_axi_arvalid => jtag_axi_0_M_AXI_ARVALID,
m_axi_awaddr(31 downto 0) => jtag_axi_0_M_AXI_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => jtag_axi_0_M_AXI_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => jtag_axi_0_M_AXI_AWCACHE(3 downto 0),
m_axi_awid(0) => jtag_axi_0_M_AXI_AWID(0),
m_axi_awlen(7 downto 0) => jtag_axi_0_M_AXI_AWLEN(7 downto 0),
m_axi_awlock => jtag_axi_0_M_AXI_AWLOCK,
m_axi_awprot(2 downto 0) => jtag_axi_0_M_AXI_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => jtag_axi_0_M_AXI_AWQOS(3 downto 0),
m_axi_awready => jtag_axi_0_M_AXI_AWREADY,
m_axi_awsize(2 downto 0) => jtag_axi_0_M_AXI_AWSIZE(2 downto 0),
m_axi_awvalid => jtag_axi_0_M_AXI_AWVALID,
m_axi_bid(0) => jtag_axi_0_M_AXI_BID(0),
m_axi_bready => jtag_axi_0_M_AXI_BREADY,
m_axi_bresp(1 downto 0) => jtag_axi_0_M_AXI_BRESP(1 downto 0),
m_axi_bvalid => jtag_axi_0_M_AXI_BVALID,
m_axi_rdata(31 downto 0) => jtag_axi_0_M_AXI_RDATA(31 downto 0),
m_axi_rid(0) => jtag_axi_0_M_AXI_RID(0),
m_axi_rlast => jtag_axi_0_M_AXI_RLAST,
m_axi_rready => jtag_axi_0_M_AXI_RREADY,
m_axi_rresp(1 downto 0) => jtag_axi_0_M_AXI_RRESP(1 downto 0),
m_axi_rvalid => jtag_axi_0_M_AXI_RVALID,
m_axi_wdata(31 downto 0) => jtag_axi_0_M_AXI_WDATA(31 downto 0),
m_axi_wlast => jtag_axi_0_M_AXI_WLAST,
m_axi_wready => jtag_axi_0_M_AXI_WREADY,
m_axi_wstrb(3 downto 0) => jtag_axi_0_M_AXI_WSTRB(3 downto 0),
m_axi_wvalid => jtag_axi_0_M_AXI_WVALID
);
master_comm_mutex: component DemoInterconnect_mutex_0_0
port map (
S0_AXI_ACLK => clk_wiz_0_clk_out1,
S0_AXI_ARADDR(31 downto 0) => axi_interconnect_0_M04_AXI_ARADDR(31 downto 0),
S0_AXI_ARESETN => clk_wiz_0_locked,
S0_AXI_ARREADY => axi_interconnect_0_M04_AXI_ARREADY,
S0_AXI_ARVALID => axi_interconnect_0_M04_AXI_ARVALID,
S0_AXI_AWADDR(31 downto 0) => axi_interconnect_0_M04_AXI_AWADDR(31 downto 0),
S0_AXI_AWREADY => axi_interconnect_0_M04_AXI_AWREADY,
S0_AXI_AWVALID => axi_interconnect_0_M04_AXI_AWVALID,
S0_AXI_BREADY => axi_interconnect_0_M04_AXI_BREADY,
S0_AXI_BRESP(1 downto 0) => axi_interconnect_0_M04_AXI_BRESP(1 downto 0),
S0_AXI_BVALID => axi_interconnect_0_M04_AXI_BVALID,
S0_AXI_RDATA(31 downto 0) => axi_interconnect_0_M04_AXI_RDATA(31 downto 0),
S0_AXI_RREADY => axi_interconnect_0_M04_AXI_RREADY,
S0_AXI_RRESP(1 downto 0) => axi_interconnect_0_M04_AXI_RRESP(1 downto 0),
S0_AXI_RVALID => axi_interconnect_0_M04_AXI_RVALID,
S0_AXI_WDATA(31 downto 0) => axi_interconnect_0_M04_AXI_WDATA(31 downto 0),
S0_AXI_WREADY => axi_interconnect_0_M04_AXI_WREADY,
S0_AXI_WSTRB(3 downto 0) => axi_interconnect_0_M04_AXI_WSTRB(3 downto 0),
S0_AXI_WVALID => axi_interconnect_0_M04_AXI_WVALID,
S1_AXI_ACLK => clk_wiz_0_clk_out1,
S1_AXI_ARADDR(31 downto 0) => axi_interconnect_0_M05_AXI_ARADDR(31 downto 0),
S1_AXI_ARESETN => clk_wiz_0_locked,
S1_AXI_ARREADY => axi_interconnect_0_M05_AXI_ARREADY,
S1_AXI_ARVALID => axi_interconnect_0_M05_AXI_ARVALID,
S1_AXI_AWADDR(31 downto 0) => axi_interconnect_0_M05_AXI_AWADDR(31 downto 0),
S1_AXI_AWREADY => axi_interconnect_0_M05_AXI_AWREADY,
S1_AXI_AWVALID => axi_interconnect_0_M05_AXI_AWVALID,
S1_AXI_BREADY => axi_interconnect_0_M05_AXI_BREADY,
S1_AXI_BRESP(1 downto 0) => axi_interconnect_0_M05_AXI_BRESP(1 downto 0),
S1_AXI_BVALID => axi_interconnect_0_M05_AXI_BVALID,
S1_AXI_RDATA(31 downto 0) => axi_interconnect_0_M05_AXI_RDATA(31 downto 0),
S1_AXI_RREADY => axi_interconnect_0_M05_AXI_RREADY,
S1_AXI_RRESP(1 downto 0) => axi_interconnect_0_M05_AXI_RRESP(1 downto 0),
S1_AXI_RVALID => axi_interconnect_0_M05_AXI_RVALID,
S1_AXI_WDATA(31 downto 0) => axi_interconnect_0_M05_AXI_WDATA(31 downto 0),
S1_AXI_WREADY => axi_interconnect_0_M05_AXI_WREADY,
S1_AXI_WSTRB(3 downto 0) => axi_interconnect_0_M05_AXI_WSTRB(3 downto 0),
S1_AXI_WVALID => axi_interconnect_0_M05_AXI_WVALID,
S2_AXI_ACLK => clk_wiz_0_clk_out1,
S2_AXI_ARADDR(31 downto 0) => axi_interconnect_0_M06_AXI_ARADDR(31 downto 0),
S2_AXI_ARESETN => clk_wiz_0_locked,
S2_AXI_ARREADY => axi_interconnect_0_M06_AXI_ARREADY,
S2_AXI_ARVALID => axi_interconnect_0_M06_AXI_ARVALID,
S2_AXI_AWADDR(31 downto 0) => axi_interconnect_0_M06_AXI_AWADDR(31 downto 0),
S2_AXI_AWREADY => axi_interconnect_0_M06_AXI_AWREADY,
S2_AXI_AWVALID => axi_interconnect_0_M06_AXI_AWVALID,
S2_AXI_BREADY => axi_interconnect_0_M06_AXI_BREADY,
S2_AXI_BRESP(1 downto 0) => axi_interconnect_0_M06_AXI_BRESP(1 downto 0),
S2_AXI_BVALID => axi_interconnect_0_M06_AXI_BVALID,
S2_AXI_RDATA(31 downto 0) => axi_interconnect_0_M06_AXI_RDATA(31 downto 0),
S2_AXI_RREADY => axi_interconnect_0_M06_AXI_RREADY,
S2_AXI_RRESP(1 downto 0) => axi_interconnect_0_M06_AXI_RRESP(1 downto 0),
S2_AXI_RVALID => axi_interconnect_0_M06_AXI_RVALID,
S2_AXI_WDATA(31 downto 0) => axi_interconnect_0_M06_AXI_WDATA(31 downto 0),
S2_AXI_WREADY => axi_interconnect_0_M06_AXI_WREADY,
S2_AXI_WSTRB(3 downto 0) => axi_interconnect_0_M06_AXI_WSTRB(3 downto 0),
S2_AXI_WVALID => axi_interconnect_0_M06_AXI_WVALID
);
uart_transceiver_0: component DemoInterconnect_uart_transceiver_0_0
port map (
i_Clk => clk_wiz_0_uart,
i_RX_Serial => UART_RX_0_1,
i_TX_Byte(7 downto 0) => interface_axi_master_0_if00_data_out(7 downto 0),
i_TX_Load => interface_axi_master_0_if00_load_out,
o_RX_Byte(7 downto 0) => uart_transceiver_0_o_RX_Byte(7 downto 0),
o_RX_Done => uart_transceiver_0_o_RX_Done,
o_TX_Active => uart_transceiver_0_o_TX_Active,
o_TX_Done => uart_transceiver_0_o_TX_Done,
o_TX_Serial => uart_transceiver_0_o_TX_Serial
);
uart_transceiver_1: component DemoInterconnect_uart_transceiver_0_1
port map (
i_Clk => clk_wiz_0_uart,
i_RX_Serial => UART_RX_1_1,
i_TX_Byte(7 downto 0) => internoc_ni_axi_master_1_if00_data_out(7 downto 0),
i_TX_Load => internoc_ni_axi_master_1_if00_load_out,
o_RX_Byte(7 downto 0) => uart_transceiver_1_o_RX_Byte(7 downto 0),
o_RX_Done => uart_transceiver_1_o_RX_Done,
o_TX_Active => uart_transceiver_1_o_TX_Active,
o_TX_Done => uart_transceiver_1_o_TX_Done,
o_TX_Serial => uart_transceiver_1_o_TX_Serial
);
end STRUCTURE;
|
entity FIFO is
port (
i_wr_en : in std_logic;
i_data : out std_logic_vector(31 downto 0);
i_rd_en : in std_logic;
o_data : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
i_wr_en : in std_logic;
i_data : out std_logic_vector(31 downto 0);
i_rd_en : in std_logic;
o_data : out std_logic_vector(31 downto 0)
);
end entity FIFO;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_comparator is
end tb_comparator;
architecture TB_comparator of tb_comparator is
-- Component declarations
-- Signal declarations
terminal in_src : electrical;
signal cmp_out : std_logic;
begin
-- Signal assignments
-- Component instances
vio : entity work.v_sine(ideal)
generic map(
freq => 100.0,
amplitude => 5.0
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
C1 : entity work.comparator(ideal)
port map(
a => in_src,
d => cmp_out
);
end TB_comparator;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_comparator is
end tb_comparator;
architecture TB_comparator of tb_comparator is
-- Component declarations
-- Signal declarations
terminal in_src : electrical;
signal cmp_out : std_logic;
begin
-- Signal assignments
-- Component instances
vio : entity work.v_sine(ideal)
generic map(
freq => 100.0,
amplitude => 5.0
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
C1 : entity work.comparator(ideal)
port map(
a => in_src,
d => cmp_out
);
end TB_comparator;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_comparator is
end tb_comparator;
architecture TB_comparator of tb_comparator is
-- Component declarations
-- Signal declarations
terminal in_src : electrical;
signal cmp_out : std_logic;
begin
-- Signal assignments
-- Component instances
vio : entity work.v_sine(ideal)
generic map(
freq => 100.0,
amplitude => 5.0
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
C1 : entity work.comparator(ideal)
port map(
a => in_src,
d => cmp_out
);
end TB_comparator;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w8_d2_A_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w8_d2_A_shiftReg;
architecture rtl of fifo_w8_d2_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity fifo_w8_d2_A is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w8_d2_A is
component fifo_w8_d2_A_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - conv_std_logic_vector(1, 2);
if (mOutPtr = conv_std_logic_vector(0, 2)) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + conv_std_logic_vector(1, 2);
internal_empty_n <= '1';
if (mOutPtr = conv_std_logic_vector(DEPTH, 2) - conv_std_logic_vector(2, 2)) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w8_d2_A_shiftReg : fifo_w8_d2_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
--------------------------------------------------------------------------------
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the FIR Compiler IP core.
-- The testbench has been generated by Vivado to accompany the IP core
-- instance you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with your core.
--
-- See the FIR Compiler product guide for further information
-- about this core.
--
--------------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated FIR Compiler core
-- instance named "fir".
--
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
-- documentation for details.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_fir is
end tb_fir;
architecture tb of tb_fir is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
-----------------------------------------------------------------------
-- DUT signals
-----------------------------------------------------------------------
-- General signals
signal aclk : std_logic := '0'; -- the master clock
-- Data slave channel signals
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal s_axis_data_tready : std_logic := '1'; -- slave is ready
signal s_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
-- Data master channel signals
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tdata : std_logic_vector(39 downto 0) := (others => '0'); -- data payload
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA and TUSER fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
-- Data slave channel alias signals
signal s_axis_data_tdata_data : std_logic_vector(15 downto 0) := (others => '0');
-- Data master channel alias signals
signal m_axis_data_tdata_data : std_logic_vector(37 downto 0) := (others => '0');
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.fir
port map (
aclk => aclk,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tdata => m_axis_data_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
-- Procedure to drive a number of input samples with specific data
-- data is the data value to drive on the tdata signal
-- samples is the number of zero-data input samples to drive
procedure drive_data ( data : std_logic_vector(15 downto 0);
samples : natural := 1 ) is
variable ip_count : integer := 0;
begin
ip_count := 0;
loop
s_axis_data_tvalid <= '1';
s_axis_data_tdata <= data;
loop
wait until rising_edge(aclk);
exit when s_axis_data_tready = '1';
end loop;
ip_count := ip_count + 1;
wait for T_HOLD;
exit when ip_count >= samples;
end loop;
end procedure drive_data;
-- Procedure to drive a number of zero-data input samples
-- samples is the number of zero-data input samples to drive
procedure drive_zeros ( samples : natural := 1 ) is
begin
drive_data((others => '0'), samples);
end procedure drive_zeros;
-- Procedure to drive an impulse and let the impulse response emerge on the data master channel
-- samples is the number of input samples to drive; default is enough for impulse response output to emerge
procedure drive_impulse ( samples : natural := 408 ) is
variable impulse : std_logic_vector(15 downto 0);
begin
impulse := (others => '0'); -- initialize unused bits to zero
impulse(15 downto 0) := "0100000000000000";
drive_data(impulse);
if samples > 1 then
drive_zeros(samples-1);
end if;
end procedure drive_impulse;
begin
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Drive a single impulse and let the impulse response emerge
drive_impulse;
-- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
drive_impulse(2); -- start of impulse; data is now zero
s_axis_data_tvalid <= '0';
wait for CLOCK_PERIOD * 5; -- provide no data for 5 input samples worth
drive_zeros(406); -- back to normal operation
-- End of test
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
wait;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the master DATA channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_data_tvalid = '1' then
if is_x(m_axis_data_tdata) then
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
-- Data slave channel alias signals
s_axis_data_tdata_data <= s_axis_data_tdata(15 downto 0);
-- Data master channel alias signals: update these only when they are valid
m_axis_data_tdata_data <= m_axis_data_tdata(37 downto 0) when m_axis_data_tvalid = '1';
end tb;
|
--------------------------------------------------------------------------------
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the FIR Compiler IP core.
-- The testbench has been generated by Vivado to accompany the IP core
-- instance you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with your core.
--
-- See the FIR Compiler product guide for further information
-- about this core.
--
--------------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated FIR Compiler core
-- instance named "fir".
--
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
-- documentation for details.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_fir is
end tb_fir;
architecture tb of tb_fir is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
-----------------------------------------------------------------------
-- DUT signals
-----------------------------------------------------------------------
-- General signals
signal aclk : std_logic := '0'; -- the master clock
-- Data slave channel signals
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal s_axis_data_tready : std_logic := '1'; -- slave is ready
signal s_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
-- Data master channel signals
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tdata : std_logic_vector(39 downto 0) := (others => '0'); -- data payload
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA and TUSER fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
-- Data slave channel alias signals
signal s_axis_data_tdata_data : std_logic_vector(15 downto 0) := (others => '0');
-- Data master channel alias signals
signal m_axis_data_tdata_data : std_logic_vector(37 downto 0) := (others => '0');
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.fir
port map (
aclk => aclk,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tdata => m_axis_data_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
-- Procedure to drive a number of input samples with specific data
-- data is the data value to drive on the tdata signal
-- samples is the number of zero-data input samples to drive
procedure drive_data ( data : std_logic_vector(15 downto 0);
samples : natural := 1 ) is
variable ip_count : integer := 0;
begin
ip_count := 0;
loop
s_axis_data_tvalid <= '1';
s_axis_data_tdata <= data;
loop
wait until rising_edge(aclk);
exit when s_axis_data_tready = '1';
end loop;
ip_count := ip_count + 1;
wait for T_HOLD;
exit when ip_count >= samples;
end loop;
end procedure drive_data;
-- Procedure to drive a number of zero-data input samples
-- samples is the number of zero-data input samples to drive
procedure drive_zeros ( samples : natural := 1 ) is
begin
drive_data((others => '0'), samples);
end procedure drive_zeros;
-- Procedure to drive an impulse and let the impulse response emerge on the data master channel
-- samples is the number of input samples to drive; default is enough for impulse response output to emerge
procedure drive_impulse ( samples : natural := 408 ) is
variable impulse : std_logic_vector(15 downto 0);
begin
impulse := (others => '0'); -- initialize unused bits to zero
impulse(15 downto 0) := "0100000000000000";
drive_data(impulse);
if samples > 1 then
drive_zeros(samples-1);
end if;
end procedure drive_impulse;
begin
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Drive a single impulse and let the impulse response emerge
drive_impulse;
-- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
drive_impulse(2); -- start of impulse; data is now zero
s_axis_data_tvalid <= '0';
wait for CLOCK_PERIOD * 5; -- provide no data for 5 input samples worth
drive_zeros(406); -- back to normal operation
-- End of test
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
wait;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the master DATA channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_data_tvalid = '1' then
if is_x(m_axis_data_tdata) then
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
-- Data slave channel alias signals
s_axis_data_tdata_data <= s_axis_data_tdata(15 downto 0);
-- Data master channel alias signals: update these only when they are valid
m_axis_data_tdata_data <= m_axis_data_tdata(37 downto 0) when m_axis_data_tvalid = '1';
end tb;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Package: ftlib
-- File: ftlib.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Library of fault-tolerant (TMR) registers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package ftlib is
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Package: ftlib
-- File: ftlib.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Library of fault-tolerant (TMR) registers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package ftlib is
end;
|
-- PCI interface
constant CFG_PCI : integer := CFG_PCITYPE;
constant CFG_PCIVID : integer := 16#CONFIG_PCI_VENDORID#;
constant CFG_PCIDID : integer := 16#CONFIG_PCI_DEVICEID#;
constant CFG_PCIDEPTH : integer := CFG_PCIFIFO;
constant CFG_PCI_MTF : integer := CFG_PCI_ENFIFO;
|
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