content stringlengths 1 1.04M ⌀ |
|---|
-- PCI interface
constant CFG_PCI : integer := CFG_PCITYPE;
constant CFG_PCIVID : integer := 16#CONFIG_PCI_VENDORID#;
constant CFG_PCIDID : integer := 16#CONFIG_PCI_DEVICEID#;
constant CFG_PCIDEPTH : integer := CFG_PCIFIFO;
constant CFG_PCI_MTF : integer := CFG_PCI_ENFIFO;
|
-- PCI interface
constant CFG_PCI : integer := CFG_PCITYPE;
constant CFG_PCIVID : integer := 16#CONFIG_PCI_VENDORID#;
constant CFG_PCIDID : integer := 16#CONFIG_PCI_DEVICEID#;
constant CFG_PCIDEPTH : integer := CFG_PCIFIFO;
constant CFG_PCI_MTF : integer := CFG_PCI_ENFIFO;
|
-- PCI interface
constant CFG_PCI : integer := CFG_PCITYPE;
constant CFG_PCIVID : integer := 16#CONFIG_PCI_VENDORID#;
constant CFG_PCIDID : integer := 16#CONFIG_PCI_DEVICEID#;
constant CFG_PCIDEPTH : integer := CFG_PCIFIFO;
constant CFG_PCI_MTF : integer := CFG_PCI_ENFIFO;
|
-- #############################################################################
-- DE1_SoC_TRDB_D5M_top_level.vhd
-- ==============================
--
-- BOARD : DE1-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.8
-- Last updated : 2017-06-11 12:48:26 UTC
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE1_SoC_TRDB_D5M_top_level is
port(
-- ADC
ADC_CS_n : out std_logic;
ADC_DIN : out std_logic;
ADC_DOUT : in std_logic;
ADC_SCLK : out std_logic;
-- Audio
AUD_ADCDAT : in std_logic;
AUD_ADCLRCK : inout std_logic;
AUD_BCLK : inout std_logic;
AUD_DACDAT : out std_logic;
AUD_DACLRCK : inout std_logic;
AUD_XCK : out std_logic;
-- CLOCK
CLOCK_50 : in std_logic;
CLOCK2_50 : in std_logic;
CLOCK3_50 : in std_logic;
CLOCK4_50 : in std_logic;
-- SDRAM
DRAM_ADDR : out std_logic_vector(12 downto 0);
DRAM_BA : out std_logic_vector(1 downto 0);
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_LDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_WE_N : out std_logic;
-- I2C for Audio and Video-In
FPGA_I2C_SCLK : out std_logic;
FPGA_I2C_SDAT : inout std_logic;
-- SEG7
HEX0_N : out std_logic_vector(6 downto 0);
HEX1_N : out std_logic_vector(6 downto 0);
HEX2_N : out std_logic_vector(6 downto 0);
HEX3_N : out std_logic_vector(6 downto 0);
HEX4_N : out std_logic_vector(6 downto 0);
HEX5_N : out std_logic_vector(6 downto 0);
-- IR
IRDA_RXD : in std_logic;
IRDA_TXD : out std_logic;
-- KEY_N
KEY_N : in std_logic_vector(3 downto 0);
-- LED
LEDR : out std_logic_vector(9 downto 0);
-- PS2
PS2_CLK : inout std_logic;
PS2_CLK2 : inout std_logic;
PS2_DAT : inout std_logic;
PS2_DAT2 : inout std_logic;
-- SW
SW : in std_logic_vector(9 downto 0);
-- Video-In
TD_CLK27 : inout std_logic;
TD_DATA : out std_logic_vector(7 downto 0);
TD_HS : out std_logic;
TD_RESET_N : out std_logic;
TD_VS : out std_logic;
-- VGA
VGA_B : out std_logic_vector(7 downto 0);
VGA_BLANK_N : out std_logic;
VGA_CLK : out std_logic;
VGA_G : out std_logic_vector(7 downto 0);
VGA_HS : out std_logic;
VGA_R : out std_logic_vector(7 downto 0);
VGA_SYNC_N : out std_logic;
VGA_VS : out std_logic;
-- GPIO_0
GPIO_0_D5M_D : in std_logic_vector(11 downto 0);
GPIO_0_D5M_FVAL : in std_logic;
GPIO_0_D5M_LVAL : in std_logic;
GPIO_0_D5M_PIXCLK : in std_logic;
GPIO_0_D5M_RESET_N : out std_logic;
GPIO_0_D5M_SCLK : inout std_logic;
GPIO_0_D5M_SDATA : inout std_logic;
GPIO_0_D5M_STROBE : in std_logic;
GPIO_0_D5M_TRIGGER : out std_logic;
GPIO_0_D5M_XCLKIN : out std_logic;
-- GPIO_1
GPIO_1 : inout std_logic_vector(35 downto 0);
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_FLASH_DATA : inout std_logic_vector(3 downto 0);
HPS_FLASH_DCLK : out std_logic;
HPS_FLASH_NCSO : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C_CONTROL : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_I2C2_SCLK : inout std_logic;
HPS_I2C2_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity DE1_SoC_TRDB_D5M_top_level;
architecture rtl of DE1_SoC_TRDB_D5M_top_level is
begin
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity UART_TX is
PORT( CLK_I : in std_logic;
CLR : in std_logic; -- RESET
CE_16 : in std_logic; -- BUAD rate clock
DATA : in std_logic_vector(7 downto 0); -- DATA to be sent
DATA_FLAG : in std_logic; -- toggle to send data
SER_OUT : out std_logic; -- Serial output line
DATA_FLAGQ : out std_logic -- Transmitting Flag
);
end UART_TX;
architecture TX_UART_arch of UART_TX is
signal BUF : std_logic_vector(7 downto 0);
signal TODO : integer range 0 to 9; -- bits to send
signal FLAGQ : std_logic;
signal CE_1 : std_logic;
signal C16 : std_logic_vector(3 downto 0);
begin
DATA_FLAGQ <= FLAGQ;
-- generate a CE_1 every 16 CE_16...
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
CE_1 <= '0';
if (CLR = '1') then
C16 <= "0000";
elsif (CE_16 = '1') then
if (C16 = "1111") then
CE_1 <= '1';
end if;
C16 <= C16 + "0001";
end if;
end if;
end process;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (CLR = '1') then
SER_OUT <= '1';
BUF <= "11111111";
TODO <= 0;
FLAGQ <= DATA_FLAG; -- idle
elsif (CE_1 = '1') then
if (TODO > 0) then -- transmitting
SER_OUT <= BUF(0); -- next bit
BUF <= '1' & BUF(7 downto 1);
if (TODO = 1) then
FLAGQ <= DATA_FLAG;
end if;
TODO <= TODO - 1;
elsif (FLAGQ /= DATA_FLAG) then -- new byte
SER_OUT <= '0'; -- start bit
TODO <= 9;
BUF <= DATA;
end if;
end if;
end if;
end process;
end TX_UART_arch;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_160 is
port (
le : out std_logic;
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0);
sign : in std_logic
);
end sub_160;
architecture augh of sub_160 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= carry_inA(32) & carry_inB(32) & carry_res(32);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
le <= tmp_le;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_160 is
port (
le : out std_logic;
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0);
sign : in std_logic
);
end sub_160;
architecture augh of sub_160 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= carry_inA(32) & carry_inB(32) & carry_res(32);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
le <= tmp_le;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2654.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02654ent IS
END c13s03b01x00p02n01i02654ent;
ARCHITECTURE c13s03b01x00p02n01i02654arch OF c13s03b01x00p02n01i02654ent IS
BEGIN
TESTING: PROCESS
variable /k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02654 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02654arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2654.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02654ent IS
END c13s03b01x00p02n01i02654ent;
ARCHITECTURE c13s03b01x00p02n01i02654arch OF c13s03b01x00p02n01i02654ent IS
BEGIN
TESTING: PROCESS
variable /k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02654 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02654arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2654.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02654ent IS
END c13s03b01x00p02n01i02654ent;
ARCHITECTURE c13s03b01x00p02n01i02654arch OF c13s03b01x00p02n01i02654ent IS
BEGIN
TESTING: PROCESS
variable /k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02654 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02654arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:01:17 11/27/2013
-- Design Name:
-- Module Name: MISC_zpuino_sa_splitter2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MISC_zpuino_sa_splitter2 is
Port ( in1 : in STD_LOGIC;
out1 : out STD_LOGIC;
out2 : out STD_LOGIC);
end MISC_zpuino_sa_splitter2;
architecture Behavioral of MISC_zpuino_sa_splitter2 is
begin
out1 <= in1;
out2 <= in1;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:01:17 11/27/2013
-- Design Name:
-- Module Name: MISC_zpuino_sa_splitter2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MISC_zpuino_sa_splitter2 is
Port ( in1 : in STD_LOGIC;
out1 : out STD_LOGIC;
out2 : out STD_LOGIC);
end MISC_zpuino_sa_splitter2;
architecture Behavioral of MISC_zpuino_sa_splitter2 is
begin
out1 <= in1;
out2 <= in1;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:01:17 11/27/2013
-- Design Name:
-- Module Name: MISC_zpuino_sa_splitter2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MISC_zpuino_sa_splitter2 is
Port ( in1 : in STD_LOGIC;
out1 : out STD_LOGIC;
out2 : out STD_LOGIC);
end MISC_zpuino_sa_splitter2;
architecture Behavioral of MISC_zpuino_sa_splitter2 is
begin
out1 <= in1;
out2 <= in1;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:01:17 11/27/2013
-- Design Name:
-- Module Name: MISC_zpuino_sa_splitter2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MISC_zpuino_sa_splitter2 is
Port ( in1 : in STD_LOGIC;
out1 : out STD_LOGIC;
out2 : out STD_LOGIC);
end MISC_zpuino_sa_splitter2;
architecture Behavioral of MISC_zpuino_sa_splitter2 is
begin
out1 <= in1;
out2 <= in1;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:01:17 11/27/2013
-- Design Name:
-- Module Name: MISC_zpuino_sa_splitter2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MISC_zpuino_sa_splitter2 is
Port ( in1 : in STD_LOGIC;
out1 : out STD_LOGIC;
out2 : out STD_LOGIC);
end MISC_zpuino_sa_splitter2;
architecture Behavioral of MISC_zpuino_sa_splitter2 is
begin
out1 <= in1;
out2 <= in1;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:01:17 11/27/2013
-- Design Name:
-- Module Name: MISC_zpuino_sa_splitter2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MISC_zpuino_sa_splitter2 is
Port ( in1 : in STD_LOGIC;
out1 : out STD_LOGIC;
out2 : out STD_LOGIC);
end MISC_zpuino_sa_splitter2;
architecture Behavioral of MISC_zpuino_sa_splitter2 is
begin
out1 <= in1;
out2 <= in1;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:01:17 11/27/2013
-- Design Name:
-- Module Name: MISC_zpuino_sa_splitter2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MISC_zpuino_sa_splitter2 is
Port ( in1 : in STD_LOGIC;
out1 : out STD_LOGIC;
out2 : out STD_LOGIC);
end MISC_zpuino_sa_splitter2;
architecture Behavioral of MISC_zpuino_sa_splitter2 is
begin
out1 <= in1;
out2 <= in1;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:01:17 11/27/2013
-- Design Name:
-- Module Name: MISC_zpuino_sa_splitter2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MISC_zpuino_sa_splitter2 is
Port ( in1 : in STD_LOGIC;
out1 : out STD_LOGIC;
out2 : out STD_LOGIC);
end MISC_zpuino_sa_splitter2;
architecture Behavioral of MISC_zpuino_sa_splitter2 is
begin
out1 <= in1;
out2 <= in1;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:01:17 11/27/2013
-- Design Name:
-- Module Name: MISC_zpuino_sa_splitter2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MISC_zpuino_sa_splitter2 is
Port ( in1 : in STD_LOGIC;
out1 : out STD_LOGIC;
out2 : out STD_LOGIC);
end MISC_zpuino_sa_splitter2;
architecture Behavioral of MISC_zpuino_sa_splitter2 is
begin
out1 <= in1;
out2 <= in1;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:01:17 11/27/2013
-- Design Name:
-- Module Name: MISC_zpuino_sa_splitter2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MISC_zpuino_sa_splitter2 is
Port ( in1 : in STD_LOGIC;
out1 : out STD_LOGIC;
out2 : out STD_LOGIC);
end MISC_zpuino_sa_splitter2;
architecture Behavioral of MISC_zpuino_sa_splitter2 is
begin
out1 <= in1;
out2 <= in1;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:01:17 11/27/2013
-- Design Name:
-- Module Name: MISC_zpuino_sa_splitter2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MISC_zpuino_sa_splitter2 is
Port ( in1 : in STD_LOGIC;
out1 : out STD_LOGIC;
out2 : out STD_LOGIC);
end MISC_zpuino_sa_splitter2;
architecture Behavioral of MISC_zpuino_sa_splitter2 is
begin
out1 <= in1;
out2 <= in1;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:01:17 11/27/2013
-- Design Name:
-- Module Name: MISC_zpuino_sa_splitter2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MISC_zpuino_sa_splitter2 is
Port ( in1 : in STD_LOGIC;
out1 : out STD_LOGIC;
out2 : out STD_LOGIC);
end MISC_zpuino_sa_splitter2;
architecture Behavioral of MISC_zpuino_sa_splitter2 is
begin
out1 <= in1;
out2 <= in1;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:01:17 11/27/2013
-- Design Name:
-- Module Name: MISC_zpuino_sa_splitter2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MISC_zpuino_sa_splitter2 is
Port ( in1 : in STD_LOGIC;
out1 : out STD_LOGIC;
out2 : out STD_LOGIC);
end MISC_zpuino_sa_splitter2;
architecture Behavioral of MISC_zpuino_sa_splitter2 is
begin
out1 <= in1;
out2 <= in1;
end Behavioral;
|
entity \t\\\est\ is end;
|
component TimeHoldOver_Qsys is
port (
clk_clk : in std_logic := 'X'; -- clk
epcs_flash_controller_dclk : out std_logic; -- dclk
epcs_flash_controller_sce : out std_logic; -- sce
epcs_flash_controller_sdo : out std_logic; -- sdo
epcs_flash_controller_data0 : in std_logic := 'X'; -- data0
on_chip_rst_and_pps_switch_export : out std_logic_vector(8 downto 0); -- export
io_update_ctrl_export : out std_logic; -- export
ocxo_lock_export : in std_logic := 'X'; -- export
pps_interrupt_export : in std_logic := 'X'; -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_controller_addr : out std_logic_vector(11 downto 0); -- addr
sdram_controller_ba : out std_logic_vector(1 downto 0); -- ba
sdram_controller_cas_n : out std_logic; -- cas_n
sdram_controller_cke : out std_logic; -- cke
sdram_controller_cs_n : out std_logic; -- cs_n
sdram_controller_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
sdram_controller_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_controller_ras_n : out std_logic; -- ras_n
sdram_controller_we_n : out std_logic; -- we_n
timer_ecc_fault_itr_export : in std_logic := 'X'; -- export
timer_interface_coe_sec_cnt_set_data_out : out std_logic_vector(192 downto 0); -- coe_sec_cnt_set_data_out
timer_interface_coe_sec_cnt_get_data_in : in std_logic_vector(191 downto 0) := (others => 'X'); -- coe_sec_cnt_get_data_in
timer_interface_coe_ns_cnt_set_data_out : out std_logic_vector(96 downto 0); -- coe_ns_cnt_set_data_out
timer_interface_coe_ns_cnt_get_data_in : in std_logic_vector(95 downto 0) := (others => 'X'); -- coe_ns_cnt_get_data_in
timer_interface_coe_ctrl_cnt_set_out : out std_logic_vector(24 downto 0); -- coe_ctrl_cnt_set_out
timer_interface_coe_ctrl_cnt_get_in : in std_logic_vector(23 downto 0) := (others => 'X'); -- coe_ctrl_cnt_get_in
timer_interface_coe_err_cnt_in : in std_logic_vector(23 downto 0) := (others => 'X'); -- coe_err_cnt_in
timer_interface_coe_utc_time_in : in std_logic_vector(55 downto 0) := (others => 'X'); -- coe_utc_time_in
timer_interface_coe_time_zone_set_out : out std_logic_vector(8 downto 0); -- coe_time_zone_set_out
timer_interface_coe_time_zone_get_in : in std_logic_vector(7 downto 0) := (others => 'X'); -- coe_time_zone_get_in
timer_interface_coe_leap_cnt_set_out : out std_logic_vector(16 downto 0); -- coe_leap_cnt_set_out
timer_interface_coe_leap_cnt_get_in : in std_logic_vector(15 downto 0) := (others => 'X'); -- coe_leap_cnt_get_in
timer_interface_coe_leap_occur_set_out : out std_logic_vector(64 downto 0); -- coe_leap_occur_set_out
timer_interface_coe_leap_occur_get_in : in std_logic_vector(63 downto 0) := (others => 'X'); -- coe_leap_occur_get_in
timer_interface_coe_dst_ingress_set_out : out std_logic_vector(64 downto 0); -- coe_dst_ingress_set_out
timer_interface_coe_dst_ingress_get_in : in std_logic_vector(63 downto 0) := (others => 'X'); -- coe_dst_ingress_get_in
timer_interface_coe_dst_engress_set_out : out std_logic_vector(64 downto 0); -- coe_dst_engress_set_out
timer_interface_coe_dst_engress_get_in : in std_logic_vector(63 downto 0) := (others => 'X'); -- coe_dst_engress_get_in
timer_interface_coe_leap_direct_get_in : in std_logic_vector(7 downto 0) := (others => 'X'); -- coe_leap_direct_get_in
timer_interface_coe_leap_direct_set_out : out std_logic_vector(8 downto 0); -- coe_leap_direct_set_out
timer_interface_coe_io_update_in : in std_logic := 'X'; -- coe_io_update_in
timer_interface_coe_time_quality_get_in : in std_logic_vector(7 downto 0) := (others => 'X'); -- coe_time_quality_get_in
timer_interface_coe_time_quality_set_out : out std_logic_vector(8 downto 0); -- coe_time_quality_set_out
uart_0_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_0_external_connection_txd : out std_logic; -- txd
uart_1_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_1_external_connection_txd : out std_logic; -- txd
uart_2_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_2_external_connection_txd : out std_logic; -- txd
uart_3_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_3_external_connection_txd : out std_logic -- txd
);
end component TimeHoldOver_Qsys;
u0 : component TimeHoldOver_Qsys
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
epcs_flash_controller_dclk => CONNECTED_TO_epcs_flash_controller_dclk, -- epcs_flash_controller.dclk
epcs_flash_controller_sce => CONNECTED_TO_epcs_flash_controller_sce, -- .sce
epcs_flash_controller_sdo => CONNECTED_TO_epcs_flash_controller_sdo, -- .sdo
epcs_flash_controller_data0 => CONNECTED_TO_epcs_flash_controller_data0, -- .data0
on_chip_rst_and_pps_switch_export => CONNECTED_TO_on_chip_rst_and_pps_switch_export, -- on_chip_rst_and_pps_switch.export
io_update_ctrl_export => CONNECTED_TO_io_update_ctrl_export, -- io_update_ctrl.export
ocxo_lock_export => CONNECTED_TO_ocxo_lock_export, -- ocxo_lock.export
pps_interrupt_export => CONNECTED_TO_pps_interrupt_export, -- pps_interrupt.export
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sdram_controller_addr => CONNECTED_TO_sdram_controller_addr, -- sdram_controller.addr
sdram_controller_ba => CONNECTED_TO_sdram_controller_ba, -- .ba
sdram_controller_cas_n => CONNECTED_TO_sdram_controller_cas_n, -- .cas_n
sdram_controller_cke => CONNECTED_TO_sdram_controller_cke, -- .cke
sdram_controller_cs_n => CONNECTED_TO_sdram_controller_cs_n, -- .cs_n
sdram_controller_dq => CONNECTED_TO_sdram_controller_dq, -- .dq
sdram_controller_dqm => CONNECTED_TO_sdram_controller_dqm, -- .dqm
sdram_controller_ras_n => CONNECTED_TO_sdram_controller_ras_n, -- .ras_n
sdram_controller_we_n => CONNECTED_TO_sdram_controller_we_n, -- .we_n
timer_ecc_fault_itr_export => CONNECTED_TO_timer_ecc_fault_itr_export, -- timer_ecc_fault_itr.export
timer_interface_coe_sec_cnt_set_data_out => CONNECTED_TO_timer_interface_coe_sec_cnt_set_data_out, -- timer_interface.coe_sec_cnt_set_data_out
timer_interface_coe_sec_cnt_get_data_in => CONNECTED_TO_timer_interface_coe_sec_cnt_get_data_in, -- .coe_sec_cnt_get_data_in
timer_interface_coe_ns_cnt_set_data_out => CONNECTED_TO_timer_interface_coe_ns_cnt_set_data_out, -- .coe_ns_cnt_set_data_out
timer_interface_coe_ns_cnt_get_data_in => CONNECTED_TO_timer_interface_coe_ns_cnt_get_data_in, -- .coe_ns_cnt_get_data_in
timer_interface_coe_ctrl_cnt_set_out => CONNECTED_TO_timer_interface_coe_ctrl_cnt_set_out, -- .coe_ctrl_cnt_set_out
timer_interface_coe_ctrl_cnt_get_in => CONNECTED_TO_timer_interface_coe_ctrl_cnt_get_in, -- .coe_ctrl_cnt_get_in
timer_interface_coe_err_cnt_in => CONNECTED_TO_timer_interface_coe_err_cnt_in, -- .coe_err_cnt_in
timer_interface_coe_utc_time_in => CONNECTED_TO_timer_interface_coe_utc_time_in, -- .coe_utc_time_in
timer_interface_coe_time_zone_set_out => CONNECTED_TO_timer_interface_coe_time_zone_set_out, -- .coe_time_zone_set_out
timer_interface_coe_time_zone_get_in => CONNECTED_TO_timer_interface_coe_time_zone_get_in, -- .coe_time_zone_get_in
timer_interface_coe_leap_cnt_set_out => CONNECTED_TO_timer_interface_coe_leap_cnt_set_out, -- .coe_leap_cnt_set_out
timer_interface_coe_leap_cnt_get_in => CONNECTED_TO_timer_interface_coe_leap_cnt_get_in, -- .coe_leap_cnt_get_in
timer_interface_coe_leap_occur_set_out => CONNECTED_TO_timer_interface_coe_leap_occur_set_out, -- .coe_leap_occur_set_out
timer_interface_coe_leap_occur_get_in => CONNECTED_TO_timer_interface_coe_leap_occur_get_in, -- .coe_leap_occur_get_in
timer_interface_coe_dst_ingress_set_out => CONNECTED_TO_timer_interface_coe_dst_ingress_set_out, -- .coe_dst_ingress_set_out
timer_interface_coe_dst_ingress_get_in => CONNECTED_TO_timer_interface_coe_dst_ingress_get_in, -- .coe_dst_ingress_get_in
timer_interface_coe_dst_engress_set_out => CONNECTED_TO_timer_interface_coe_dst_engress_set_out, -- .coe_dst_engress_set_out
timer_interface_coe_dst_engress_get_in => CONNECTED_TO_timer_interface_coe_dst_engress_get_in, -- .coe_dst_engress_get_in
timer_interface_coe_leap_direct_get_in => CONNECTED_TO_timer_interface_coe_leap_direct_get_in, -- .coe_leap_direct_get_in
timer_interface_coe_leap_direct_set_out => CONNECTED_TO_timer_interface_coe_leap_direct_set_out, -- .coe_leap_direct_set_out
timer_interface_coe_io_update_in => CONNECTED_TO_timer_interface_coe_io_update_in, -- .coe_io_update_in
timer_interface_coe_time_quality_get_in => CONNECTED_TO_timer_interface_coe_time_quality_get_in, -- .coe_time_quality_get_in
timer_interface_coe_time_quality_set_out => CONNECTED_TO_timer_interface_coe_time_quality_set_out, -- .coe_time_quality_set_out
uart_0_external_connection_rxd => CONNECTED_TO_uart_0_external_connection_rxd, -- uart_0_external_connection.rxd
uart_0_external_connection_txd => CONNECTED_TO_uart_0_external_connection_txd, -- .txd
uart_1_external_connection_rxd => CONNECTED_TO_uart_1_external_connection_rxd, -- uart_1_external_connection.rxd
uart_1_external_connection_txd => CONNECTED_TO_uart_1_external_connection_txd, -- .txd
uart_2_external_connection_rxd => CONNECTED_TO_uart_2_external_connection_rxd, -- uart_2_external_connection.rxd
uart_2_external_connection_txd => CONNECTED_TO_uart_2_external_connection_txd, -- .txd
uart_3_external_connection_rxd => CONNECTED_TO_uart_3_external_connection_rxd, -- uart_3_external_connection.rxd
uart_3_external_connection_txd => CONNECTED_TO_uart_3_external_connection_txd -- .txd
);
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 25-04-2016
-- Module Name: p9.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity robot is
port (key1, key2, key3, clk : in std_logic);
end entity;
architecture rtl of robot is
type state is (stop, move_forward_slowly, move_forward_fast,
move_backward_fast, move_backward_slowly, turn_right,
turn_left);
signal current_state, next_state : state;
signal command : std_logic_vector (2 downto 0);
begin
command <= key1 & key2 & key3;
process (command)
begin
case command is
when "000" => next_state <= stop;
when "001" => next_state <= move_forward_slowly;
when "010" => next_state <= move_forward_fast;
when "011" => next_state <= move_backward_slowly;
when "100" => next_state <= move_backward_fast;
when "101" => next_state <= turn_right;
when "110" => next_state <= turn_left;
when "111" => next_state <= current_state;
when others => next_state <= stop;
end case;
end process;
process (clk)
begin
if clk'event and clk = '1' then
current_state <= next_state;
end if;
end process;
end architecture;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mul_pipe is
generic (
stages : positive := 3;
src1_bits : natural := 32;
src2_bits : natural := 32
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
unsgnd : in std_ulogic;
src1 : in std_ulogic_vector(src1_bits-1 downto 0);
src2 : in std_ulogic_vector(src2_bits-1 downto 0);
result : out std_ulogic_vector(src1_bits+src2_bits-1 downto 0)
);
end;
|
--
-- Copyright 2019 The Project Oak Authors
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- A simple test program for the Xilinx ZCU104605 development board that
-- makes the user GPIO LEDs flash for the binary sequence 0..7, with a
-- reset from the push button GPIO_PB_SW3 SW18 at a 1 second frequency.
package counter_package is
subtype count_type is natural range 0 to 15;
end package counter_package;
library ieee;
use ieee.std_logic_1164.all;
use work.counter_package.all;
entity leds is
port (signal CLK_125_P : in std_ulogic; -- 125MHz clock P at pin H11 LVDS
signal CLK_125_N : in std_ulogic; -- 125MHz clock N at pin G11 LVDS
signal GPIO_PB_SW3 : in std_ulogic; -- pin C3 LVCMOS33 connected to push-button GPIO_PB_SW3 SW18
signal GPIO_LED : out count_type -- LEDs at pins D5 (LSB), D6, A5, B5 (MSB) LVCMOS33
);
end entity leds;
library unisim;
use unisim.vcomponents.all;
architecture behavioral of leds is
signal count : count_type := 0 ;
signal clk : std_ulogic;
begin
clock_buffer : ibufgds port map (o => clk, i => CLK_125_P, ib => CLK_125_N);
clock_divider : process is
variable divider_count : natural := 0;
begin
wait until clk'event and clk = '1';
if GPIO_PB_SW3 = '1' then
count <= 0;
divider_count := 0;
else
if divider_count = 125000000 then
divider_count := 0;
count <= (count + 1) mod 16;
else
divider_count := divider_count + 1;
end if;
end if;
end process clock_divider;
GPIO_LED <= count;
end architecture behavioral;
|
-- (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_2_0;
USE fifo_generator_v13_2_0.fifo_generator_v13_2_0;
ENTITY aurora_64b66b_25p4G_fifo_gen_master IS
PORT (
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
full : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC
);
END aurora_64b66b_25p4G_fifo_gen_master;
ARCHITECTURE aurora_64b66b_25p4G_fifo_gen_master_arch OF aurora_64b66b_25p4G_fifo_gen_master IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF aurora_64b66b_25p4G_fifo_gen_master_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_2_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_2_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF aurora_64b66b_25p4G_fifo_gen_master_arch: ARCHITECTURE IS "fifo_generator_v13_2_0,Vivado 2017.3.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF aurora_64b66b_25p4G_fifo_gen_master_arch : ARCHITECTURE IS "aurora_64b66b_25p4G_fifo_gen_master,fifo_generator_v13_2_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF aurora_64b66b_25p4G_fifo_gen_master_arch: ARCHITECTURE IS "aurora_64b66b_25p4G_fifo_gen_master,fifo_generator_v13_2_0,{x_ipProduct=Vivado 2017.3.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.2,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_COMMON_CLOCK=0,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=9,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=72,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=72,C_ENABLE_RLOCS=0,C_FAMILY=virtexuplus,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DAT" &
"A_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=1,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=1,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=6,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=4,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=2,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=8,C_PROG_EMPTY_THRESH_NEGATE_VAL=9,C_PROG_EMPTY_TYPE=1,C_PROG_FULL_THR" &
"ESH_ASSERT_VAL=450,C_PROG_FULL_THRESH_NEGATE_VAL=449,C_PROG_FULL_TYPE=1,C_RD_DATA_COUNT_WIDTH=9,C_RD_DEPTH=512,C_RD_FREQ=1,C_RD_PNTR_WIDTH=9,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=1,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=9,C_WR_DEPTH=512,C_WR_FREQ=1,C_WR_PNTR_WIDTH=9,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SY" &
"NCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BU" &
"SER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_" &
"RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=512x72,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=512x72,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ER" &
"ROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_R" &
"ACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_F" &
"ULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=" &
"1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF rd_clk: SIGNAL IS "XIL_INTERFACENAME read_clk, FREQ_HZ 1000000, PHASE 0.000";
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF wr_clk: SIGNAL IS "XIL_INTERFACENAME write_clk, FREQ_HZ 1000000, PHASE 0.000";
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
BEGIN
U0 : fifo_generator_v13_2_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 9,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 72,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 72,
C_ENABLE_RLOCS => 0,
C_FAMILY => "virtexuplus",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 1,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => 1,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 6,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 4,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 2,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "512x72",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 8,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 9,
C_PROG_EMPTY_TYPE => 1,
C_PROG_FULL_THRESH_ASSERT_VAL => 450,
C_PROG_FULL_THRESH_NEGATE_VAL => 449,
C_PROG_FULL_TYPE => 1,
C_RD_DATA_COUNT_WIDTH => 9,
C_RD_DEPTH => 512,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 9,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 1,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 9,
C_WR_DEPTH => 512,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 9,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "512x72",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "512x72",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 1,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => srst,
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
overflow => overflow,
empty => empty,
underflow => underflow,
prog_full => prog_full,
prog_empty => prog_empty,
wr_rst_busy => wr_rst_busy,
rd_rst_busy => rd_rst_busy,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END aurora_64b66b_25p4G_fifo_gen_master_arch;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 24176)
`protect data_block
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Yc+UePo0Eog=
`protect end_protected
|
entity test is
subtype t is bar foo'subtype range 0 to 2;
end;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_t
--
-- Generated
-- by: wig
-- on: Wed Dec 14 12:17:36 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../configuration.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-e.vhd,v 1.4 2005/12/14 12:38:06 wig Exp $
-- $Date: 2005/12/14 12:38:06 $
-- $Log: ent_t-e.vhd,v $
-- Revision 1.4 2005/12/14 12:38:06 wig
-- Updated some testcases (verilog, padio)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.72 2005/11/30 14:01:21 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.43 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
-- adding to vhdl_use_enty
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
typedef use_enty_private std_ulogic_vector;
--
--
-- Start of Generated Entity ent_t
--
entity ent_t is
-- Generics:
-- No Generated Generics for Entity ent_t
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_t
sig_i_a : in std_ulogic;
sig_i_a2 : in std_ulogic;
sig_i_ae : in std_ulogic_vector(6 downto 0);
sig_o_a : out std_ulogic;
sig_o_a2 : out std_ulogic;
sig_o_ae : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ent_t
);
end ent_t;
--
-- End of Generated Entity ent_t
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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wKr/p3+6Ew==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23952)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23952)
`protect data_block
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23952)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23952)
`protect data_block
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|
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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xOPQq7Miux15hQ3NjzMUkI+jW9TlIrydpafneHkti99E/ol2UiE7lkt12OdX+zOK54Rs49W50CNC
Xjl34OM1jgnx8Qs2xNJ47mM47Vk2lsWiEX2qi+3PHoA4oWjfUTcCeyAMocczWEKizj/pamWw4WBf
rd2OMmlXxTEDwwi/imeT1S4TeakHS6hbTIqXUsqScydUZE2X5CJBKtZZNBSZNiqhCUtQmvNcSiyu
WsLp9I8KOi+5a7NYrjQ/BxrXR0TIrJUVmky/IH1pFbb7zDyOHSvdSzs46t36ThS7I8omznDlvW/c
p7EebyV/R76e0W8WyyTshCNRdBfi46w9fCNENDglhxszug09xE/qi5p/FAVBSrArpEmM92ZpTJfi
wPKVTySvYZTyEIpS5Q0RxG+j+Ln+3FmmTwJizmO4PMkhimPyQJWDYM/xtwaRPrkfXJ8gVspgN3UP
8p2RoJlR05YJWJLaVF/tsBEvqCnBkpbFVd2U99HwmMz4ZJI52cAgejAwmXbjqZXTKoajPxpqL/5q
kf/TFzl+8jcCRzsJ
`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2726.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b02x00p07n02i02726ent IS
END c13s04b02x00p07n02i02726ent;
ARCHITECTURE c13s04b02x00p07n02i02726arch OF c13s04b02x00p07n02i02726ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( 16#E#E1 = 224 )
report "***PASSED TEST: c13s04b02x00p07n02i02726"
severity NOTE;
assert ( 16#E#E1 = 224 )
report "***FAILED TEST: c13s04b02x00p07n02i02726 - Value of a based literal with the exponent test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b02x00p07n02i02726arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2726.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b02x00p07n02i02726ent IS
END c13s04b02x00p07n02i02726ent;
ARCHITECTURE c13s04b02x00p07n02i02726arch OF c13s04b02x00p07n02i02726ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( 16#E#E1 = 224 )
report "***PASSED TEST: c13s04b02x00p07n02i02726"
severity NOTE;
assert ( 16#E#E1 = 224 )
report "***FAILED TEST: c13s04b02x00p07n02i02726 - Value of a based literal with the exponent test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b02x00p07n02i02726arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2726.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b02x00p07n02i02726ent IS
END c13s04b02x00p07n02i02726ent;
ARCHITECTURE c13s04b02x00p07n02i02726arch OF c13s04b02x00p07n02i02726ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( 16#E#E1 = 224 )
report "***PASSED TEST: c13s04b02x00p07n02i02726"
severity NOTE;
assert ( 16#E#E1 = 224 )
report "***FAILED TEST: c13s04b02x00p07n02i02726 - Value of a based literal with the exponent test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b02x00p07n02i02726arch;
|
---------------------------------------------------------------
-- Title : Testbench A25
-- Project :
---------------------------------------------------------------
-- File : a25_tb.vhd
-- Author : michael.miehling@men.de
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 31/01/12
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.fpga_pkg_2.ALL;
USE work.vme_sim_pack.all;
USE work.terminal_pkg.all;
use work.pcie_sim_pkg.all;
ENTITY a25_tb IS
generic(
BFM_LANE_WIDTH : integer range 8 downto 0 := 1 -- set configuration: 1=x1, 2=x2, 4=x4 and 8=x8
);
END a25_tb;
ARCHITECTURE a25_tb_arch OF a25_tb IS
COMPONENT A25_top
GENERIC (
SIMULATION : boolean := FALSE;
FPGA_FAMILY : family_type := CYCLONE4;
BFM_LANE_WIDTH : integer range 8 downto 0 := 1; -- set configuration: 1=x1, 2=x2, 4=x4 and 8=x8
sets : std_logic_vector(3 DOWNTO 0) := "1110";
timeout : integer := 5000 );
PORT (
clk_16mhz : IN std_logic;
led_green_n : OUT std_logic;
led_red_n : OUT std_logic;
hreset_n : IN std_logic; -- reset
v2p_rstn : OUT std_logic; -- connected to hreset_req1_n
fpga_test : INOUT std_logic_vector(5 DOWNTO 1);
-- pcie
refclk : IN std_logic; -- 100 MHz pcie clock
pcie_rx : IN std_logic_vector(3 DOWNTO 0); -- PCIe receive line
pcie_tx : OUT std_logic_vector(3 DOWNTO 0); -- PCIe transmit line
-- sram bus
sr_clk : OUT std_logic;
sr_a : OUT std_logic_vector(18 DOWNTO 0);
sr_d : INOUT std_logic_vector(15 DOWNTO 0);
sr_bwa_n : OUT std_logic;
sr_bwb_n : OUT std_logic;
sr_bw_n : OUT std_logic;
sr_cs1_n : OUT std_logic;
sr_adsc_n : OUT std_logic;
sr_oe_n : OUT std_logic;
-- vmebus
vme_ga : IN std_logic_vector(4 DOWNTO 0); -- geographical addresses
vme_gap : IN std_logic; -- geographical addresses
vme_a : INOUT std_logic_vector(31 DOWNTO 0);
vme_a_dir : OUT std_logic;
vme_a_oe_n : OUT std_logic;
vme_d : INOUT std_logic_vector(31 DOWNTO 0);
vme_d_dir : OUT std_logic;
vme_d_oe_n : OUT std_logic;
vme_am_dir : OUT std_logic;
vme_am : INOUT std_logic_vector(5 DOWNTO 0);
vme_am_oe_n : OUT std_logic;
vme_write_n : INOUT std_logic;
vme_iack_n : INOUT std_logic;
vme_irq_i_n : IN std_logic_vector(7 DOWNTO 1);
vme_irq_o : OUT std_logic_vector(7 DOWNTO 1); -- high active on A25
vme_as_i_n : IN std_logic;
vme_as_o_n : OUT std_logic;
vme_as_oe : OUT std_logic; -- high active on A25
vme_retry_o_n : OUT std_logic;
vme_retry_oe : OUT std_logic; -- high active on A25
vme_retry_i_n : IN std_logic;
vme_sysres_i_n : IN std_logic;
vme_sysres_o : OUT std_logic; -- high active on A25
vme_ds_i_n : IN std_logic_vector(1 DOWNTO 0);
vme_ds_o_n : OUT std_logic_vector(1 DOWNTO 0);
vme_ds_oe : OUT std_logic; -- high active on A25
vme_berr_i_n : IN std_logic;
vme_berr_o : OUT std_logic; -- high active on A25
vme_dtack_i_n : IN std_logic;
vme_dtack_o : OUT std_logic; -- high active on A25
vme_scon : OUT std_logic; -- high active on A25
vme_sysfail_i_n : IN std_logic;
vme_sysfail_o : OUT std_logic; -- high active on A25
vme_bbsy_i_n : IN std_logic;
vme_bbsy_o : OUT std_logic; -- high active on A25
vme_bclr_i_n : IN std_logic; -- bus clear input
vme_bclr_o_n : OUT std_logic; -- bus clear output
vme_br_i_n : IN std_logic_vector(3 DOWNTO 0);
vme_br_o : OUT std_logic_vector(3 DOWNTO 0); -- high active on A25
vme_iack_i_n : IN std_logic;
vme_iack_o_n : OUT std_logic;
vme_acfail_i_n : IN std_logic;
vme_sysclk : OUT std_logic;
vme_bg_i_n : IN std_logic_vector(3 DOWNTO 0);
vme_bg_o_n : OUT std_logic_vector(3 DOWNTO 0);
-- Hard IP BFM connections
ep_rxvalid_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxstatus_i : in std_logic_vector(3*BFM_LANE_WIDTH -1 downto 0); -- 3bits per lane, [2:0]=lane0, [5:3]=lane1 etc.
ep_rxdatak_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bits per lane, [0]=lane0, [1]=lane1 etc.
ep_rxdata_i : in std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_rxelecidle_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_phystatus_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_clk250_o : out std_logic; -- endpoint SERDES 250MHz clk output
ep_clk500_o : out std_logic; -- endpoint SERDES 500MHz clk output
ep_rate_ext_o : out std_logic; -- endpoint rate_ext
ep_powerdown_ext_o : out std_logic_vector(2*BFM_LANE_WIDTH -1 downto 0); -- 2bits per lane, [1:0]=lane0, [3:2]=lane1 etc.
ep_txdatak_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdata_o : out std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_txcompl_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txelecidle_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdetectrx_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxpolarity_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_ltssm_o : out std_logic_vector(4 downto 0)
);
END COMPONENT;
COMPONENT MT58L512L18F
GENERIC (
-- Clock
tKC : TIME := 8.0 ns; -- Timing are for -6.8
tKH : TIME := 1.8 ns;
tKL : TIME := 1.8 ns;
-- Output Times
tKQHZ : TIME := 3.8 ns;
-- Setup Times
tAS : TIME := 1.8 ns;
tADSS : TIME := 1.8 ns;
tAAS : TIME := 1.8 ns;
tWS : TIME := 1.8 ns;
tDS : TIME := 1.8 ns;
tCES : TIME := 1.8 ns;
-- Hold Times
tAH : TIME := 0.5 ns;
tADSH : TIME := 0.5 ns;
tAAH : TIME := 0.5 ns;
tWH : TIME := 0.5 ns;
tDH : TIME := 0.5 ns;
tCEH : TIME := 0.5 ns;
-- Bus Width and Data Bus
addr_bits : INTEGER := 19;
data_bits : INTEGER := 18
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Mode : IN STD_LOGIC;
Adv_n : IN STD_LOGIC;
Clk : IN STD_LOGIC;
Adsc_n : IN STD_LOGIC;
Adsp_n : IN STD_LOGIC;
Bwa_n : IN STD_LOGIC;
Bwb_n : IN STD_LOGIC;
Bwe_n : IN STD_LOGIC;
Gw_n : IN STD_LOGIC;
Ce_n : IN STD_LOGIC;
Ce2 : IN STD_LOGIC;
Ce2_n : IN STD_LOGIC;
Oe_n : IN STD_LOGIC;
Zz : IN STD_LOGIC
);
END COMPONENT;
COMPONENT vmebus
PORT (
slot1 : IN boolean:=TRUE; -- if true dut is in slot1
vme_slv_in : IN vme_slv_in_type;
vme_slv_out : OUT vme_slv_out_type;
vme_mon_out : OUT vme_mon_out_type;
terminal_in_x : OUT terminal_in_type;
terminal_out_x : IN terminal_out_type;
-- the VME signals:
vb_am : INOUT std_logic_vector(5 DOWNTO 0);
vb_data : INOUT std_logic_vector(31 DOWNTO 0);
vb_adr : INOUT std_logic_vector(31 DOWNTO 0);
vb_writen : INOUT std_logic;
vb_iackn : INOUT std_logic;
vb_asn : INOUT std_logic;
vb_dsan : INOUT std_logic;
vb_dsbn : INOUT std_logic;
vb_bbsyn : INOUT std_logic;
vb_berrn : INOUT std_logic;
vb_brn : INOUT std_logic_vector(3 DOWNTO 0);
vb_dtackn : INOUT std_logic;
vb_sysresn : INOUT std_logic;
vb_irq1n : INOUT std_logic;
vb_irq2n : INOUT std_logic;
vb_irq3n : INOUT std_logic;
vb_irq4n : INOUT std_logic;
vb_irq5n : INOUT std_logic;
vb_irq6n : INOUT std_logic;
vb_irq7n : INOUT std_logic;
vb_bgin : OUT std_logic_vector(3 DOWNTO 0);
vb_bgout : IN std_logic_vector(3 DOWNTO 0);
vb_iackin : OUT std_logic;
vb_iackout : IN std_logic;
vb_acfailn : INOUT std_logic
);
END COMPONENT;
COMPONENT SN74LVTH245
GENERIC (
OP_COND : integer:=1; -- 0=min, 1=typ, 2=max
WIDTH : integer:=8
);
PORT (
dir : IN std_logic; -- direction: 0= B data to A, 1= A data to B
oe_n : IN std_logic; -- output enable: 0= driver is active, 1= tri-state
a : INOUT std_logic_vector(WIDTH-1 DOWNTO 0); -- port A
b : INOUT std_logic_vector(WIDTH-1 DOWNTO 0) -- port B
);
END COMPONENT;
COMPONENT SN74ABT125
GENERIC (
OP_COND : integer:=1; -- 0=min, 1=typ, 2=max
WIDTH : integer:=8
);
PORT (
oe_n : IN std_logic_vector(WIDTH-1 DOWNTO 0); -- output enable: 0= driver is active, 1= tri-state
a : IN std_logic_vector(WIDTH-1 DOWNTO 0); -- port A
b : OUT std_logic_vector(WIDTH-1 DOWNTO 0) -- port B
);
END COMPONENT;
COMPONENT terminal
PORT (
hreset_n : OUT std_logic;
slot1 : OUT boolean:=TRUE; -- if true dut is in slot1
en_clk : OUT boolean;
terminal_in_0 : IN terminal_in_type;
terminal_out_0 : OUT terminal_out_type;
terminal_in_1 : IN terminal_in_type;
terminal_out_1 : OUT terminal_out_type;
v2p_rstn : IN std_logic; -- connected to hreset_req1_n
vme_slv_in : OUT vme_slv_in_type;
vme_slv_out : IN vme_slv_out_type;
vme_mon_out : IN vme_mon_out_type;
vme_ga : OUT std_logic_vector(4 DOWNTO 0); -- geographical addresses
vme_gap : OUT std_logic -- geographical addresses
);
END COMPONENT;
component pcie_sim
generic(
BFM_LANE_WIDTH : integer range 8 downto 0 := 1 -- set configuration: 1=x1, 2=x2, 4=x4 and 8=x8
);
port(
rst_i : in std_logic;
pcie_rstn_i : in std_logic;
clk_i : in std_logic;
ep_clk250_i : in std_logic; -- endpoint SERDES 250MHz clk output
ep_clk500_i : in std_logic; -- endpoint SERDES 500MHz clk output
-- PCIe lanes
bfm_tx_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
bfm_rx_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
-- PCIe SERDES connection, in/out references are BFM view
ep_rate_ext_i : in std_logic; -- endpoint rate_ext
ep_powerdown_ext_i : in std_logic_vector(2*BFM_LANE_WIDTH -1 downto 0); -- 2bits per lane, [1:0]=lane0, [3:2]=lane1 etc.
ep_txdatak_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdata_i : in std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_txcompl_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txelecidle_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdetectrx_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxpolarity_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_ltssm_i : in std_logic_vector(4 downto 0);
ep_rxvalid_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxstatus_o : out std_logic_vector(3*BFM_LANE_WIDTH -1 downto 0); -- 3bits per lane, [2:0]=lane0, [5:3]=lane1 etc.
ep_rxdatak_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bits per lane, [0]=lane0, [1]=lane1 etc.
ep_rxdata_o : out std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_rxelecidle_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_phystatus_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
-- MEN terminal connection, in/out references are terminal view
term_out : in terminal_out_type;
term_in : out terminal_in_type
);
end component;
CONSTANT T_FPGA_TO_SRAM : time := 0 ns;
SIGNAL clk_125 : std_logic:='1';
SIGNAL clk_250 : std_logic:='0';
SIGNAL clk_16mhz_int : std_logic:='0';
SIGNAL clk_16mhz : std_logic:='0';
SIGNAL en_clk : boolean;
SIGNAL led_green_n : std_logic;
SIGNAL led_red_n : std_logic;
SIGNAL hreset_n : std_logic; -- reset
SIGNAL hreset : std_logic; -- reset
SIGNAL v2p_rstn : std_logic; -- connected to hreset_req1_n
SIGNAL refclk : std_logic:='0'; -- 100 MHz pcie clock
SIGNAL pcie_rx : std_logic_vector(3 DOWNTO 0); -- PCIe receive line
SIGNAL pcie_tx : std_logic_vector(3 DOWNTO 0); -- PCIe transmit line
SIGNAL sr_clk : std_logic;
SIGNAL trans_sr_clk : std_logic;
SIGNAL sr_a : std_logic_vector(18 DOWNTO 0);
SIGNAL sr_d : std_logic_vector(15 DOWNTO 0);
SIGNAL sr_bwa_n : std_logic;
SIGNAL sr_bwb_n : std_logic;
SIGNAL sr_bw_n : std_logic;
SIGNAL sr_cs1_n : std_logic;
SIGNAL sr_adsc_n : std_logic;
SIGNAL sr_oe_n : std_logic;
SIGNAL vme_ga : std_logic_vector(4 DOWNTO 0);
SIGNAL vme_gap : std_logic;
SIGNAL vme_a : std_logic_vector(31 DOWNTO 0);
SIGNAL vme_a_dir : std_logic;
SIGNAL vme_a_oe_n : std_logic;
SIGNAL vme_d : std_logic_vector(31 DOWNTO 0);
SIGNAL vme_d_dir : std_logic;
SIGNAL vme_d_oe_n : std_logic;
SIGNAL vme_am_dir : std_logic;
SIGNAL vme_am : std_logic_vector(5 DOWNTO 0);
SIGNAL vme_am_oe_n : std_logic;
SIGNAL vme_write_n : std_logic;
SIGNAL vme_iack_n : std_logic;
SIGNAL vme_irq_i_n : std_logic_vector(7 DOWNTO 1);
SIGNAL vme_irq_o_n : std_logic_vector(7 DOWNTO 1);
SIGNAL vme_as_i_n : std_logic;
SIGNAL vme_as_o_n : std_logic;
SIGNAL vme_as_oe : std_logic;
SIGNAL vme_as_oe_n : std_logic;
SIGNAL vme_retry_o_n : std_logic;
SIGNAL vme_retry_oe_n : std_logic;
SIGNAL vme_retry_i_n : std_logic;
SIGNAL vme_sysres_i_n : std_logic;
SIGNAL vme_sysres_o_n : std_logic;
SIGNAL vme_ds_i_n : std_logic_vector(1 DOWNTO 0);
SIGNAL vme_ds_o_n : std_logic_vector(1 DOWNTO 0);
SIGNAL vme_ds_oe_n : std_logic;
SIGNAL vme_berr_i_n : std_logic;
SIGNAL vme_berr_o_n : std_logic;
SIGNAL vme_berr_o : std_logic;
SIGNAL vme_dtack_i_n : std_logic;
SIGNAL vme_dtack_o_n : std_logic;
SIGNAL vme_dtack_o : std_logic;
SIGNAL vme_scon_n : std_logic;
SIGNAL vme_sysfail_i_n : std_logic;
SIGNAL vme_sysfail_o_n : std_logic;
SIGNAL vme_bbsy_i_n : std_logic;
SIGNAL vme_bbsy_o_n : std_logic;
SIGNAL vme_bclr_i_n : std_logic; -- bus clear input
SIGNAL vme_bclr_o_n : std_logic; -- bus clear output
SIGNAL vme_br_i_n : std_logic_vector(3 DOWNTO 0);
SIGNAL vme_br_o_n : std_logic_vector(3 DOWNTO 0);
SIGNAL vme_iack_i_n : std_logic;
SIGNAL vme_iack_o_n : std_logic;
SIGNAL vme_acfail_i_n : std_logic;
SIGNAL vme_sysclk : std_logic;
SIGNAL vme_bg_i_n : std_logic_vector(3 DOWNTO 0);
SIGNAL vme_bg_o_n : std_logic_vector(3 DOWNTO 0);
-- high active signals on A25
SIGNAL vme_irq_o : std_logic_vector(7 DOWNTO 1);
SIGNAL vme_retry_oe : std_logic;
SIGNAL vme_sysres_o : std_logic;
SIGNAL vme_ds_oe : std_logic;
SIGNAL vme_scon : std_logic;
SIGNAL vme_sysfail_o : std_logic;
SIGNAL vme_bbsy_o : std_logic;
SIGNAL vme_br_o : std_logic_vector(3 DOWNTO 0);
SIGNAL terminal_in_0 : terminal_in_type;
SIGNAL terminal_out_0 : terminal_out_type;
SIGNAL terminal_in_1 : terminal_in_type;
SIGNAL terminal_out_1 : terminal_out_type;
SIGNAL vme_slv_in : vme_slv_in_type;
SIGNAL vme_slv_out : vme_slv_out_type;
SIGNAL vme_mon_out : vme_mon_out_type;
SIGNAL Addr : std_logic_vector(18 DOWNTO 0);
SIGNAL Adsc_n : std_logic;
SIGNAL Bwa_n : std_logic;
SIGNAL Bwb_n : std_logic;
SIGNAL Bwe_n : std_logic;
SIGNAL Oe_n : std_logic;
SIGNAL ce_n : std_logic;
SIGNAL vb_am : std_logic_vector(5 DOWNTO 0);
SIGNAL vb_data : std_logic_vector(31 DOWNTO 0);
SIGNAL vb_adr : std_logic_vector(31 DOWNTO 0);
SIGNAL vb_writen : std_logic;
SIGNAL vb_iackn : std_logic;
SIGNAL vb_asn : std_logic;
SIGNAL vb_dsan : std_logic;
SIGNAL vb_dsbn : std_logic;
SIGNAL vb_bbsyn : std_logic;
SIGNAL vb_berrn : std_logic;
SIGNAL vb_brn : std_logic_vector(3 DOWNTO 0);
SIGNAL vb_dtackn : std_logic;
SIGNAL vb_sysresn : std_logic;
SIGNAL vb_irq1n : std_logic;
SIGNAL vb_irq2n : std_logic;
SIGNAL vb_irq3n : std_logic;
SIGNAL vb_irq4n : std_logic;
SIGNAL vb_irq5n : std_logic;
SIGNAL vb_irq6n : std_logic;
SIGNAL vb_irq7n : std_logic;
SIGNAL vb_bgin : std_logic_vector(3 DOWNTO 0);
SIGNAL vb_bgout : std_logic_vector(3 DOWNTO 0);
SIGNAL vb_iackin : std_logic;
SIGNAL vb_iackout : std_logic;
SIGNAL vb_acfailn : std_logic;
SIGNAL vb_sysclk : std_logic;
SIGNAL vb_sysfailn : std_logic;
SIGNAL dummy : std_logic:='1';
SIGNAL slot1 : boolean;
-- Hard IP BFM connections
signal ep_rxvalid_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_rxstatus_int : std_logic_vector(3*BFM_LANE_WIDTH -1 downto 0);
signal ep_rxdatak_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_rxdata_int : std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0);
signal ep_rxelecidle_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_phystatus_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_clk250_int : std_logic;
signal ep_clk500_int : std_logic;
signal ep_rate_ext_int : std_logic;
signal ep_powerdown_ext_int : std_logic_vector(2*BFM_LANE_WIDTH -1 downto 0);
signal ep_txdatak_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_txdata_int : std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0);
signal ep_txcompl_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_txelecidle_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_txdetectrx_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_rxpolarity_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_ltssm_int : std_logic_vector(4 downto 0);
BEGIN
-- high active signals on A25
vme_irq_o_n <= NOT vme_irq_o ;
vme_retry_oe_n <= NOT vme_retry_oe ;
vme_sysres_o_n <= NOT vme_sysres_o ;
vme_ds_oe_n <= NOT vme_ds_oe ;
vme_scon_n <= NOT vme_scon ;
vme_sysfail_o_n <= NOT vme_sysfail_o ;
vme_bbsy_o_n <= NOT vme_bbsy_o ;
vme_br_o_n <= NOT vme_br_o ;
vme_as_oe_n <= NOT vme_as_oe;
vme_dtack_o_n <= NOT vme_dtack_o;
vme_berr_o_n <= NOT vme_berr_o;
a25: A25_top
GENERIC MAP (
SIMULATION => TRUE,
FPGA_FAMILY => CYCLONE4,
BFM_LANE_WIDTH => BFM_LANE_WIDTH,
sets => "1110",
timeout => 5000
)
PORT MAP (
clk_16mhz => clk_16mhz ,
led_green_n => led_green_n ,
led_red_n => led_red_n ,
hreset_n => hreset_n ,
v2p_rstn => v2p_rstn ,
fpga_test => open,
refclk => refclk ,
pcie_rx => pcie_rx ,
pcie_tx => pcie_tx ,
sr_clk => sr_clk ,
sr_a => sr_a ,
sr_d => sr_d ,
sr_bwa_n => sr_bwa_n ,
sr_bwb_n => sr_bwb_n ,
sr_bw_n => sr_bw_n ,
sr_cs1_n => sr_cs1_n ,
sr_adsc_n => sr_adsc_n ,
sr_oe_n => sr_oe_n ,
vme_ga => vme_ga,
vme_gap => vme_gap,
vme_a => vme_a ,
vme_a_dir => vme_a_dir ,
vme_a_oe_n => vme_a_oe_n ,
vme_d => vme_d ,
vme_d_dir => vme_d_dir ,
vme_d_oe_n => vme_d_oe_n ,
vme_am_dir => vme_am_dir ,
vme_am => vme_am ,
vme_am_oe_n => vme_am_oe_n ,
vme_write_n => vme_write_n ,
vme_iack_n => vme_iack_n ,
vme_irq_i_n => vme_irq_i_n ,
vme_irq_o => vme_irq_o ,
vme_as_i_n => vme_as_i_n ,
vme_as_o_n => vme_as_o_n ,
vme_as_oe => vme_as_oe ,
vme_retry_o_n => vme_retry_o_n ,
vme_retry_oe => vme_retry_oe ,
vme_retry_i_n => vme_retry_i_n ,
vme_sysres_i_n => vme_sysres_i_n ,
vme_sysres_o => vme_sysres_o ,
vme_ds_i_n => vme_ds_i_n ,
vme_ds_o_n => vme_ds_o_n ,
vme_ds_oe => vme_ds_oe ,
vme_berr_i_n => vme_berr_i_n ,
vme_berr_o => vme_berr_o ,
vme_dtack_i_n => vme_dtack_i_n ,
vme_dtack_o => vme_dtack_o ,
vme_scon => vme_scon ,
vme_sysfail_i_n => vme_sysfail_i_n ,
vme_sysfail_o => vme_sysfail_o ,
vme_bbsy_i_n => vme_bbsy_i_n ,
vme_bbsy_o => vme_bbsy_o ,
vme_bclr_i_n => vme_bclr_i_n ,
vme_bclr_o_n => vme_bclr_o_n ,
vme_br_i_n => vme_br_i_n ,
vme_br_o => vme_br_o ,
vme_iack_i_n => vme_iack_i_n ,
vme_iack_o_n => vme_iack_o_n ,
vme_acfail_i_n => vme_acfail_i_n ,
vme_sysclk => vme_sysclk ,
vme_bg_i_n => vme_bg_i_n ,
vme_bg_o_n => vme_bg_o_n,
-- Hard IP BFM connections
ep_rxvalid_i => ep_rxvalid_int,
ep_rxstatus_i => ep_rxstatus_int,
ep_rxdatak_i => ep_rxdatak_int,
ep_rxdata_i => ep_rxdata_int,
ep_rxelecidle_i => ep_rxelecidle_int,
ep_phystatus_i => ep_phystatus_int,
ep_clk250_o => ep_clk250_int,
ep_clk500_o => ep_clk500_int,
ep_rate_ext_o => ep_rate_ext_int,
ep_powerdown_ext_o => ep_powerdown_ext_int,
ep_txdatak_o => ep_txdatak_int,
ep_txdata_o => ep_txdata_int,
ep_txcompl_o => ep_txcompl_int,
ep_txelecidle_o => ep_txelecidle_int,
ep_txdetectrx_o => ep_txdetectrx_int,
ep_rxpolarity_o => ep_rxpolarity_int,
ep_ltssm_o => ep_ltssm_int
);
clk_16mhz_int <= NOT clk_16mhz_int AFTER 31.25 ns;
clk_16mhz <= clk_16mhz_int WHEN en_clk ELSE '0';
refclk <= NOT refclk AFTER 5 ns;
clk_125 <= NOT clk_125 AFTER 4 ns; -- 125 MHz
clk_250 <= NOT clk_250 AFTER 2 ns; -- 250 MHz
hreset <= NOT hreset_n;
pcie_sim_inst: pcie_sim
generic map(
BFM_LANE_WIDTH => BFM_LANE_WIDTH
)
port map(
rst_i => hreset,
pcie_rstn_i => hreset_n,
clk_i => refclk,
ep_clk250_i => ep_clk250_int,
ep_clk500_i => ep_clk500_int,
-- PCIe lanes
bfm_tx_i => pcie_tx(BFM_LANE_WIDTH -1 downto 0),
bfm_rx_o => pcie_rx(BFM_LANE_WIDTH -1 downto 0),
-- PCIe SERDES connection, in/out references are BFM view
ep_rate_ext_i => ep_rate_ext_int,
ep_powerdown_ext_i => ep_powerdown_ext_int,
ep_txdatak_i => ep_txdatak_int,
ep_txdata_i => ep_txdata_int,
ep_txcompl_i => ep_txcompl_int,
ep_txelecidle_i => ep_txelecidle_int,
ep_txdetectrx_i => ep_txdetectrx_int,
ep_rxpolarity_i => ep_rxpolarity_int,
ep_ltssm_i => ep_ltssm_int,
ep_rxvalid_o => ep_rxvalid_int,
ep_rxstatus_o => ep_rxstatus_int,
ep_rxdatak_o => ep_rxdatak_int,
ep_rxdata_o => ep_rxdata_int,
ep_rxelecidle_o => ep_rxelecidle_int,
ep_phystatus_o => ep_phystatus_int,
-- MEN terminal connection, in/out references are terminal view
term_out => terminal_out_0,
term_in => terminal_in_0
);
trans_sr_clk <= transport sr_clk AFTER 12 ns;
Addr <= transport sr_a AFTER (T_FPGA_TO_SRAM);
Adsc_n <= transport sr_adsc_n AFTER (T_FPGA_TO_SRAM);
Bwa_n <= transport sr_bwa_n AFTER (T_FPGA_TO_SRAM);
Bwb_n <= transport sr_bwb_n AFTER (T_FPGA_TO_SRAM);
Bwe_n <= transport sr_bw_n AFTER (T_FPGA_TO_SRAM);
Oe_n <= transport sr_oe_n AFTER (T_FPGA_TO_SRAM);
ce_n <= '1', '0' AFTER 28 ns;
sram : MT58L512L18F
GENERIC MAP (
addr_bits => 19,
data_bits => 16
)
PORT MAP(
Clk => trans_sr_clk,
Dq => sr_d ,
Addr => Addr ,
Adsc_n => adsc_n,
Bwa_n => Bwa_n ,
Bwb_n => Bwb_n ,
Bwe_n => Bwe_n ,
Oe_n => Oe_n ,
Adsp_n => '1',
Mode => '0',
Adv_n => '1',
Gw_n => '1',
Ce_n => ce_n,
Ce2 => '1',
Ce2_n => '0',
Zz => '0'
);
vme_bus : vmebus
PORT MAP (
slot1 => slot1, -- if true dut is in slot1
vme_slv_in => vme_slv_in ,
vme_slv_out => vme_slv_out,
vme_mon_out => vme_mon_out,
terminal_in_x => terminal_in_1 ,
terminal_out_x => terminal_out_1 ,
vb_am => vb_am ,
vb_data => vb_data ,
vb_adr => vb_adr ,
vb_writen => vb_writen ,
vb_iackn => vb_iackn ,
vb_asn => vb_asn ,
vb_dsan => vb_dsan ,
vb_dsbn => vb_dsbn ,
vb_bbsyn => vb_bbsyn ,
vb_berrn => vb_berrn ,
vb_brn => vb_brn ,
vb_dtackn => vb_dtackn ,
vb_sysresn => vb_sysresn ,
vb_irq1n => vb_irq1n ,
vb_irq2n => vb_irq2n ,
vb_irq3n => vb_irq3n ,
vb_irq4n => vb_irq4n ,
vb_irq5n => vb_irq5n ,
vb_irq6n => vb_irq6n ,
vb_irq7n => vb_irq7n ,
vb_bgin => vb_bgin ,
vb_bgout => vb_bgout ,
vb_iackin => vb_iackin ,
vb_iackout => vb_iackout ,
vb_acfailn => vb_acfailn
);
bus_drv_ctrl_out: SN74ABT125
GENERIC MAP (
OP_COND => 2,
WIDTH => 21
)
PORT MAP (
oe_n(0) => vme_irq_o_n(1),
oe_n(1) => vme_irq_o_n(2),
oe_n(2) => vme_irq_o_n(3),
oe_n(3) => vme_irq_o_n(4),
oe_n(4) => vme_irq_o_n(5),
oe_n(5) => vme_irq_o_n(6),
oe_n(6) => vme_irq_o_n(7),
oe_n(7) => vme_as_oe_n,
oe_n(8) => vme_dtack_o_n,
oe_n(9) => vme_ds_o_n(0),
oe_n(10) => vme_ds_o_n(1),
oe_n(11) => vme_sysclk,
oe_n(12) => vme_berr_o_n,
oe_n(13) => vme_sysres_o_n,
oe_n(14) => vme_sysfail_o_n,
oe_n(15) => vme_br_o_n(0),
oe_n(16) => vme_br_o_n(1),
oe_n(17) => vme_br_o_n(2),
oe_n(18) => vme_br_o_n(3),
oe_n(19) => '1',
oe_n(20) => vme_bbsy_o_n,
a(0) => vme_irq_o_n(1),
a(1) => vme_irq_o_n(2),
a(2) => vme_irq_o_n(3),
a(3) => vme_irq_o_n(4),
a(4) => vme_irq_o_n(5),
a(5) => vme_irq_o_n(6),
a(6) => vme_irq_o_n(7),
a(7) => vme_as_o_n,
a(8) => vme_dtack_o_n,
a(9) => vme_ds_o_n(0),
a(10) => vme_ds_o_n(1),
a(11) => vme_sysclk,
a(12) => vme_berr_o_n,
a(13) => vme_sysres_o_n,
a(14) => vme_sysfail_o_n,
a(15) => vme_br_o_n(0),
a(16) => vme_br_o_n(1),
a(17) => vme_br_o_n(2),
a(18) => vme_br_o_n(3),
a(19) => '1',
a(20) => vme_bbsy_o_n,
b(0) => vb_irq1n,
b(1) => vb_irq2n,
b(2) => vb_irq3n,
b(3) => vb_irq4n,
b(4) => vb_irq5n,
b(5) => vb_irq6n,
b(6) => vb_irq7n,
b(7) => vb_asn,
b(8) => vb_dtackn,
b(9) => vb_dsan,
b(10) => vb_dsbn,
b(11) => vb_sysclk,
b(12) => vb_berrn,
b(13) => vb_sysresn,
b(14) => vb_sysfailn,
b(15) => vb_brn(0),
b(16) => vb_brn(1),
b(17) => vb_brn(2),
b(18) => vb_brn(3),
b(19) => vb_acfailn,
b(20) => vb_bbsyn
);
vb_irq1n <= 'H';
bus_drv_ctrl_in: SN74LVTH245
GENERIC MAP (
OP_COND => 2,
WIDTH => 29
)
PORT MAP(
dir => '1', -- a->b
oe_n => '0',
a(0) => vb_irq1n,
a(1) => vb_irq2n,
a(2) => vb_irq3n,
a(3) => vb_irq4n,
a(4) => vb_irq5n,
a(5) => vb_irq6n,
a(6) => vb_irq7n,
a(7) => vb_iackin,
a(8) => vme_iack_o_n,
a(9) => vb_asn,
a(10) => vb_dtackn,
a(11) => vb_dsan,
a(12) => vb_dsbn,
a(13) => vb_berrn,
a(14) => vb_sysresn,
a(15) => dummy,
a(16) => vme_bg_o_n(0),
a(17) => vme_bg_o_n(1),
a(18) => vme_bg_o_n(2),
a(19) => vme_bg_o_n(3),
a(20) => vb_bgin(0),
a(21) => vb_bgin(1),
a(22) => vb_bgin(2),
a(23) => vb_bgin(3),
a(24) => vb_bbsyn,
a(25) => vb_brn(0),
a(26) => vb_brn(1),
a(27) => vb_brn(2),
a(28) => vb_brn(3),
b(0) => vme_irq_i_n(1),
b(1) => vme_irq_i_n(2),
b(2) => vme_irq_i_n(3),
b(3) => vme_irq_i_n(4),
b(4) => vme_irq_i_n(5),
b(5) => vme_irq_i_n(6),
b(6) => vme_irq_i_n(7),
b(7) => vme_iack_i_n,
b(8) => vb_iackout,
b(9) => vme_as_i_n,
b(10) => vme_dtack_i_n,
b(11) => vme_ds_i_n(0),
b(12) => vme_ds_i_n(1),
b(13) => vme_berr_i_n,
b(14) => vme_sysres_i_n,
b(15) => vme_sysfail_i_n,
b(16) => vb_bgout(0),
b(17) => vb_bgout(1),
b(18) => vb_bgout(2),
b(19) => vb_bgout(3),
b(20) => vme_bg_i_n(0),
b(21) => vme_bg_i_n(1),
b(22) => vme_bg_i_n(2),
b(23) => vme_bg_i_n(3),
b(24) => vme_bbsy_i_n,
b(25) => vme_br_i_n(0),
b(26) => vme_br_i_n(1),
b(27) => vme_br_i_n(2),
b(28) => vme_br_i_n(3)
);
bus_drv_am: SN74LVTH245
GENERIC MAP (
OP_COND => 2,
WIDTH => 8
)
PORT MAP(
dir => vme_am_dir,
oe_n => vme_am_oe_n,
a(0) => vme_am(0),
a(1) => vme_am(1),
a(2) => vme_am(2),
a(3) => vme_am(3),
a(4) => vme_am(4),
a(5) => vme_am(5),
a(6) => vme_iack_n,
a(7) => vme_write_n,
b(0) => vb_am(0),
b(1) => vb_am(1),
b(2) => vb_am(2),
b(3) => vb_am(3),
b(4) => vb_am(4),
b(5) => vb_am(5),
b(6) => vb_iackn,
b(7) => vb_writen
);
bus_drv_adr: SN74LVTH245
GENERIC MAP (
OP_COND => 2,
WIDTH => 32
)
PORT MAP(
dir => vme_a_dir,
oe_n => vme_a_oe_n,
a => vme_a,
b => vb_adr
);
bus_drv_dat: SN74LVTH245
GENERIC MAP (
OP_COND => 2,
WIDTH => 32
)
PORT MAP(
dir => vme_d_dir,
oe_n => vme_d_oe_n,
a => vme_d,
b => vb_data
);
term: terminal
PORT MAP (
hreset_n => hreset_n ,
slot1 => slot1,
en_clk => en_clk,
terminal_in_0 => terminal_in_0 ,
terminal_out_0 => terminal_out_0,
terminal_in_1 => terminal_in_1 ,
terminal_out_1 => terminal_out_1,
vme_slv_in => vme_slv_in ,
vme_slv_out => vme_slv_out,
vme_mon_out => vme_mon_out,
v2p_rstn => v2p_rstn ,
vme_ga => vme_ga,
vme_gap => vme_gap
);
END a25_tb_arch;
CONFIGURATION a25_tb_conf of a25_tb IS
FOR a25_tb_arch
FOR a25 : A25_top
USE CONFIGURATION work.top_cfg;
END FOR;
END FOR;
END CONFIGURATION a25_tb_conf;
|
library ieee;
use ieee.std_logic_1164.all;
entity dff06 is
port (q : out std_logic;
d : std_logic;
clk : std_logic);
end dff06;
architecture behav of dff06 is
begin
process (clk) is
variable a, b : std_logic;
begin
if rising_edge (clk) then
q <= b;
b := a;
a := d;
end if;
end process;
end behav;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RegN is
generic (
INITREG: std_logic_vector := "1001");
port (
Din: in std_logic_vector (INITREG'range);
EN: in std_logic;
INIT: in std_logic;
CLK: in std_logic;
OE: in std_logic;
Dout: out std_logic_vector(INITREG'range));
end RegN;
architecture Beh of RegN is
signal reg: std_logic_vector(INITREG'range);
constant ALLZ: std_logic_vector(INITREG'range) := (others => 'Z');
Begin
Main: process (Din, En, Init, CLK)
begin
if INIT = '1' then
reg <= INITREG;
elsif EN = '1' then
if rising_edge(CLK) then
reg <= Din;
end if;
end if;
end process;
Dout <= reg when OE = '1' else ALLZ;
end Beh; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RegN is
generic (
INITREG: std_logic_vector := "1001");
port (
Din: in std_logic_vector (INITREG'range);
EN: in std_logic;
INIT: in std_logic;
CLK: in std_logic;
OE: in std_logic;
Dout: out std_logic_vector(INITREG'range));
end RegN;
architecture Beh of RegN is
signal reg: std_logic_vector(INITREG'range);
constant ALLZ: std_logic_vector(INITREG'range) := (others => 'Z');
Begin
Main: process (Din, En, Init, CLK)
begin
if INIT = '1' then
reg <= INITREG;
elsif EN = '1' then
if rising_edge(CLK) then
reg <= Din;
end if;
end if;
end process;
Dout <= reg when OE = '1' else ALLZ;
end Beh; |
-- File: gray_counter_16.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Feb 3 17:16:41 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity gray_counter_16 is
port (
gray_count: out unsigned(15 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity gray_counter_16;
architecture MyHDL of gray_counter_16 is
signal even: std_logic;
signal gray: unsigned(15 downto 0);
begin
GRAY_COUNTER_16_SEQ: process (clock, reset) is
variable found: std_logic;
variable word: unsigned(15 downto 0);
begin
if (reset = '1') then
even <= '1';
gray <= (others => '0');
elsif rising_edge(clock) then
word := unsigned'("1" & gray((16 - 2)-1 downto 0) & even);
if bool(enable) then
found := '0';
for i in 0 to 16-1 loop
if ((word(i) = '1') and (not bool(found))) then
gray(i) <= stdl((not bool(gray(i))));
found := '1';
end if;
end loop;
even <= stdl((not bool(even)));
end if;
end if;
end process GRAY_COUNTER_16_SEQ;
gray_count <= gray;
end architecture MyHDL;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Mem_B_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY Mem_B_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END Mem_B_exdes;
ARCHITECTURE xilinx OF Mem_B_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT Mem_B IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : Mem_B
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Tue Jun 27 15:34:40 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_UAMN ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-a.vhd,v 1.3 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: ent_t-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_t
--
architecture rtl of ent_t is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_a
-- No Generated Generics
-- Generated Generics for Entity ent_a
-- End of Generated Generics for Entity ent_a
port (
-- Generated Port for Entity ent_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic; -- Input Port
port_o_a : out std_ulogic; -- Output Port
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : out std_ulogic_vector(8 downto 2); -- VHDL intermediate needed (port name)
sig_13 : out std_ulogic_vector(4 downto 0); -- Create internal signal name
sig_i_a2 : in std_ulogic; -- Input Port
sig_o_a2 : out std_ulogic -- Output Port
-- End of Generated Port for Entity ent_a
);
end component;
-- ---------
component ent_b
-- No Generated Generics
port (
-- Generated Port for Entity ent_b
port_b_1 : in std_ulogic; -- Will create p_mix_sig_1_go port
port_b_3 : in std_ulogic; -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 : out std_ulogic; -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 : in std_ulogic; -- Bus, single bits go to outside, will create p_mix_sig_5_2_2_go __I_AUTO_REDUCED_BUS2SIGNAL
port_b_5_2 : in std_ulogic; -- Bus, single bits go to outside, will create P_MIX_sound_alarm_test5_1_1_GO __I_AUTO_REDUCED_BUS2SIGNAL
port_b_6i : in std_ulogic_vector(3 downto 0); -- Conflicting definition
port_b_6o : out std_ulogic_vector(3 downto 0); -- Conflicting definition
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : in std_ulogic_vector(8 downto 2) -- VHDL intermediate needed (port name)
-- End of Generated Port for Entity ent_b
);
end component;
-- ---------
--
-- Generated Signal List
--
signal sig_01 : std_ulogic;
signal sig_03 : std_ulogic;
signal sig_04 : std_ulogic;
signal sig_05 : std_ulogic_vector(3 downto 0);
signal sig_06 : std_ulogic_vector(3 downto 0);
signal sig_07 : std_ulogic_vector(5 downto 0);
signal sig_08 : std_ulogic_vector(8 downto 2);
-- __I_OUT_OPEN signal sig_13 : std_ulogic_vector(4 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: ent_a
port map (
p_mix_sig_01_go => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
p_mix_sig_03_go => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
p_mix_sig_04_gi => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
p_mix_sig_05_2_1_go => sig_05(2 downto 1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
p_mix_sig_06_gi => sig_06, -- Conflicting definition (X2)
p_mix_sig_i_ae_gi => sig_i_ae, -- Input Bus
p_mix_sig_o_ae_go => sig_o_ae, -- Output Bus
port_i_a => sig_i_a, -- Input Port
port_o_a => sig_o_a, -- Output Port
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08, -- VHDL intermediate needed (port name)
sig_13 => open, -- Create internal signal name -- __I_OUT_OPEN
sig_i_a2 => sig_i_a2, -- Input Port
sig_o_a2 => sig_o_a2 -- Output Port
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: ent_b
port map (
port_b_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_b_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 => sig_05(2), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_5_2 => sig_05(1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_6i => sig_06, -- Conflicting definition (X2)
port_b_6o => sig_06, -- Conflicting definition (X2)
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08 -- VHDL intermediate needed (port name)
);
-- End of Generated Instance Port Map for inst_b
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- 2-input 32-bit multiplexer
-- this circuit takes 2 32-bit inputs and selects one to output based on a select signal
-- all code (c) copyright 2016 Jay Valentine, released under the MIT license
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux_2_32_bit is
port (
-- inputs
in_32_0 : in std_logic_vector(31 downto 0);
in_32_1 : in std_logic_vector(31 downto 0);
-- select signal
input_select : in std_logic;
-- output
out_32 : out std_logic_vector(31 downto 0)
);
end entity mux_2_32_bit;
architecture mux_2_32_bit_arch of mux_2_32_bit is
-- this circuit requires no internal signals
begin
-- design implementation
mux : process(input_select, in_32_0, in_32_1)
begin
-- select 0 is input 0
if input_select = '0' then
out_32 <= in_32_0;
-- select 1 is input 1
elsif input_select = '1' then
out_32 <= in_32_1;
-- otherwise invalid input signal, output 0
else
out_32 <= (others => '0');
end if;
end process mux;
end architecture mux_2_32_bit_arch;
|
-------------------------------------------------------
-- Author: Hugues CREUSY
--February 2004
-- VHDL model
-- project: M25P32 50 MHz,
-- release: 1.0
-----------------------------------------------------
-- Unit : Internal logic
-----------------------------------------------------
-------------------------------------------------------------
-- These VHDL models are provided "as is" without warranty
-- of any kind, included but not limited to, implied warranty
-- of merchantability and fitness for a particular purpose.
-------------------------------------------------------------
------------------------------------------------------------------
--
-- INTERNAL LOGIC
--
------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library STD;
use STD.textio.ALL;
library WORK;
use WORK.MEM_UTIL_PKG.ALL;
-----------------------------------------------------------------------
-- Entity
-----------------------------------------------------------------------
-- This entity modelizes data reception and treatment by the SPI bus --
-----------------------------------------------------------------------
ENTITY Internal_Logic IS
GENERIC ( SIZE : positive;
Plength : positive;
SSIZE : positive;
Nb_BPi: positive;
signature : STD_LOGIC_VECTOR (7 downto 0);
manufacturerID : STD_LOGIC_VECTOR (7 downto 0);
memtype : STD_LOGIC_VECTOR (7 downto 0);
density : STD_LOGIC_VECTOR (7 downto 0);
NB_BIT_DATA: positive;
NB_BIT_ADD: positive;
NB_BIT_ADD_MEM: positive;
Tc: TIME;
tSLCH: TIME;
tCHSL: TIME;
tCH: TIME;
tCL: TIME;
tDVCH: TIME;
tCHDX: TIME;
tCHSH: TIME;
tSHCH: TIME;
tSHSL: TIME;
tSHQZ: TIME;
tCLQV: TIME;
tHLCH: TIME;
tCHHH: TIME;
tHHCH: TIME;
tCHHL: TIME;
tHHQX: TIME;
tHLQZ: TIME;
tWHSL: TIME;
tSHWL: TIME;
tDP:TIME;
tRES1:TIME;
tRES2:TIME;
tW: TIME;
tPP:TIME;
tSE:TIME;
tBE:TIME
);
PORT ( C, D,W,S,hold: IN std_logic;
data_to_read: IN std_logic_vector (NB_BIT_DATA-1 downto 0);
Power_up: IN boolean;
Q: OUT std_logic;
p_prog: OUT page(0 TO (Plength-1));
add_mem: OUT std_logic_vector(NB_BIT_ADD_MEM-1 downto 0);
write_op,read_op,BE_enable,SE_enable,add_pp_enable,PP_enable,READ_enable,data_request: OUT boolean;
wrsr: INOUT boolean;
srwd_wrsr: INOUT boolean;
write_protect: INOUT boolean
);
END Internal_Logic;
-----------------------------------------------------------------------------
-- Architecture
-----------------------------------------------------------------------------
-- The architecture contains a process count_bit which counts the bits and --
-- bytes received, a process data_in which latches the data on data_latch. --
-- After that an asynchronous decode process makes data, operation codes --
-- and adresses treatment, and give instructions to a synchronous process --
-- (on clock c) which contains further instructions, warnings and failures --
-- concerning each one of the functions. --
-----------------------------------------------------------------------------
ARCHITECTURE behavioral OF Internal_Logic IS
SIGNAL only_rdsr, only_res,select_ok,raz, byte_ok,add_overflow,add_overflow_1,add_overflow_2: boolean:= false;
SIGNAL write_protect_toggle: boolean:= false;
SIGNAL cpt: integer:=0;
SIGNAL byte_cpt: integer:=0;
SIGNAL data_latch: std_logic_vector(NB_BIT_DATA-1 downto 0):="00000000";
SIGNAL wren, wrdi, rdsr, read_data,fast_read, pp, se, be, dp, res, rdid: boolean:=false; --HC 24/09/03
SIGNAL Q_bis:std_logic:='Z';
SIGNAL register_bis, status_register,wr_latch: std_logic_vector(7 downto 0):="00000000";
SIGNAL protect,wr_cycle,hold_cond: boolean:=false;
SIGNAL inhib_wren,inhib_wrdi,inhib_rdsr,inhib_WRSR,inhib_READ,inhib_PP,
inhib_SE,inhib_BE,inhib_DP,inhib_RES, inhib_RDID :boolean:=false; --HC 24/09/03
SIGNAL reset_WEL,WEL,WIP:std_logic:='0';
SIGNAL c_int : std_logic;
CONSTANT LSB_TO_CODE_PAGE:natural:=to_bit_code(Plength);
CONSTANT top_mem:positive:=size/NB_BIT_DATA-1;
SIGNAL t_write_protect_toggle: TIME:=0 ns;
BEGIN
Status_register<=register_bis;
-------------------------------------------------------------
-- This process generates the Hold condition when it is valid
hold_com: PROCESS
-------------------------------------------------------------
BEGIN
WAIT ON HOLD;
IF (HOLD = '0' AND S='0') THEN
IF (C='0') THEN
hold_cond <= true;
REPORT " HOLD: COMMUNICATION PAUSED "
SEVERITY NOTE;
ELSE WAIT ON C,hold;
IF (C='0') THEN
hold_cond <= true;
REPORT " HOLD: COMMUNICATION PAUSED "
SEVERITY NOTE;
END IF;
END IF;
ELSIF (HOLD = '1') THEN
IF (C='0') THEN
hold_cond <= false;
REPORT " HOLD: COMMUNICATION STARTS "
SEVERITY NOTE;
ELSE WAIT ON C,hold;
IF (C='0') THEN
hold_cond <= false;
REPORT " HOLD: COMMUNICATION STARTS "
SEVERITY NOTE;
END IF;
END IF;
END IF;
END PROCESS hold_com ;
------------------------------------------------------------------------
-- This process inhibits the internal clock when hold condition is valid
horloge: PROCESS
------------------------------------------------------------------------
BEGIN
WAIT ON C;
IF (NOT hold_cond) THEN
C_int<=C;
ELSIF (hold_cond) THEN
C_int<='0';
END IF;
END PROCESS horloge;
-----------------------------------------------------------------
-- This process inhibits data output when hold condition is valid
data_output: PROCESS
-----------------------------------------------------------------
BEGIN
WAIT ON hold_cond,Q_bis,S;
IF (hold_cond'event) THEN
IF (hold_cond) THEN
Q<='Z' after tHLQZ;
ELSIF (NOT hold_cond) THEN
Q<=Q_bis after tHHQX;
END IF;
ELSIF (NOT hold_cond) THEN
Q<=Q_bis;
END IF;
END PROCESS data_output;
------------------------------------------------------------
-- This process increments 2 counters: one bit counter (cpt)
-- one byte counter (byte_cpt)
count_bit: PROCESS
------------------------------------------------------------
VARIABLE count_enable: boolean := false;
BEGIN
WAIT ON C_int,raz;
IF (raz or NOT select_ok) THEN
cpt <= 0;
byte_cpt <= 0;
count_enable := false;
ELSE
IF (C_int = '1') THEN
-- count enable is an intermediate variable which allows cpt to be
-- constant during a whole period
count_enable := true;
END IF;
IF(count_enable AND C_int'event AND C_int = '0')THEN
cpt <= (cpt +1) MOD 8;
END IF;
IF(C_int = '0' AND byte_ok)THEN
byte_cpt <= (byte_cpt+1);
END IF;
END IF;
END PROCESS count_bit;
-----------------------------------------------------------------------
-- This process latches every byte of data received and returns byte_ok
data_in: PROCESS
-----------------------------------------------------------------------
VARIABLE data: std_logic_vector (7 downto 0):="00000000";
BEGIN
WAIT ON C_int,Select_ok;
IF (NOT select_ok) then
raz<=true;
byte_ok<=false;
data_latch<="00000000";
data:="00000000";
ELSIF (C_int'event and C_int='1') THEN
raz<=false;
IF (cpt=0) THEN
data_latch<="00000000";
byte_ok<=false;
END IF;
data(7-cpt):=D;
IF (cpt=7) THEN
byte_ok<=true;
data_latch<=data;
END IF;
END IF;
END PROCESS data_in;
---------------------------------------------------------------
----------------- ASYNCHRONOUS DECODE PROCESS -----------------
---------------------------------------------------------------
decode : PROCESS
VARIABLE LSB_adress:std_logic_vector(LSB_to_code_page-1 downto 0);
VARIABLE j:natural:=0;
VARIABLE adress:std_logic_vector (nb_bit_add_mem-1 downto 0);
VARIABLE adress_1, adress_2, adress_3: std_logic_vector(7 downto 0);
VARIABLE bit_to_code_mem:natural:=TO_bit_code(size/NB_BIT_DATA);
VARIABLE cut_add:std_logic_vector(bit_to_code_mem-1 downto 0);
VARIABLE register_temp:std_logic_vector ((NB_BIT_DATA-1) downto 0);
VARIABLE int_add:natural:=0;
VARIABLE first_run: boolean:=true;
VARIABLE message: LINE;
VARIABLE BP:std_logic_vector(NB_BPi-1 downto 0);
VARIABLE SR_MASK:std_logic_vector(7 downto 0):="10000000";
CONSTANT page_ini:std_logic_vector ((NB_BIT_DATA-1) downto 0):="11111111";
----------------------------------------------------------------------
-- Read and write status register procedures
-- PROCEDURE read_status (file_name:STRING; status: OUT std_logic_vector(7 downto 0)) IS
-- file data_file : text open read_mode is file_name;
-- VARIABLE L:LINE;
-- VARIABLE bit_status:bit_vector(7 downto 0);
-- BEGIN
-- readline (data_file,L);
-- READ(L,bit_status);
-- status:=to_StdLogicVector(bit_status) AND SR_Mask;
-- END read_status;
-- PROCEDURE write_status (file_name:STRING; status: IN std_logic_vector(7 downto 0)) IS
-- file data_file : text open write_mode is file_name;
-- VARIABLE L:LINE;
-- VARIABLE bit_status: bit_vector(7 downto 0);
-- BEGIN
-- bit_status:=to_BitVector(status);
-- WRITE(L,bit_status);
-- writeline (data_file,L);
-- END write_status;
---------------------------------------------------------------------
BEGIN
----------------------------------------------------------
-- Status Register initialization
----------------------------------------------------------
-- IF first_run THEN
-- WRITE (message,string'("Trying to load status_register.txt"));
-- writeline (output,message);
-- read_status("status_register.txt",register_temp);
-- register_bis<=register_temp;
-- first_run:=false;
-- END IF;
-------------------------------------------
-- wait statements
-------------------------------------------
WAIT ON Power_up,byte_ok,wr_cycle,WEL,reset_WEL,WIP,
inhib_WRSR,inhib_READ,inhib_PP,inhib_SE,
inhib_BE,inhib_rdsr,inhib_DP,inhib_RES, inhib_RDID;
---------------------------
-- status register mask ini
---------------------------
FOR i IN 0 TO NB_BPi-1 LOOP
SR_Mask(i+2):='1';
END LOOP;
-------------------------------------------
-- adresses initialization and reset
-------------------------------------------
IF (byte_cpt=0) THEN
FOR i IN 0 TO NB_BIT_ADD-1 LOOP
adress_1(i):='0';
adress_2(i):='0';
adress_3(i):='0';
END LOOP;
FOR i IN 0 TO NB_BIT_ADD_MEM-1 LOOP
adress(i):='0';
END LOOP;
add_mem<=adress;
END IF;
----------------------------------
-- page to program reset (FFh)
----------------------------------
IF (NOT PP) THEN
FOR i IN 0 TO (Plength-1) LOOP
P_prog(i)<=page_ini;
END LOOP;
END IF;
-----------------------------------------------------------
-- op_code decode
-----------------------------------------------------------
IF ((byte_ok'event AND byte_ok) AND (byte_cpt=0)) THEN
IF (data_latch="00000110") THEN
IF(only_rdsr) THEN
REPORT "This Opcode is not decoded during a Prog. Cycle"
SEVERITY ERROR;
ELSIF (only_res) THEN
REPORT "This Opcode is not decoded during a DEEP POWER DOWN"
SEVERITY ERROR;
ELSE wren<=true;
write_op<=true;
END IF;
ELSIF (data_latch="00000100") THEN
IF(only_rdsr) THEN
REPORT "This Opcode is not decoded during a Prog. Cycle"
SEVERITY ERROR;
ELSIF (only_res) THEN
REPORT "This Opcode is not decoded during a DEEP POWER DOWN"
SEVERITY ERROR;
ELSE wrdi<=true;
write_op<=true;
END IF;
ELSIF (data_latch="00000101") THEN
IF (only_res) THEN
REPORT "This Opcode is not decoded during a DEEP POWER DOWN"
SEVERITY ERROR;
ELSE rdsr<=true;
END IF;
ELSIF (data_latch="00000001") THEN
IF(only_rdsr) THEN
REPORT "This Opcode is not decoded during a Prog. Cycle"
SEVERITY ERROR;
ELSIF (only_res) THEN
REPORT "This Opcode is not decoded during a DEEP POWER DOWN"
SEVERITY ERROR;
ELSE wrsr<=true;
write_op<=true;
END IF;
ELSIF (data_latch="00000011") THEN
IF (only_rdsr) THEN
REPORT "This Opcode is not decoded during a Prog. Cycle"
SEVERITY ERROR;
ELSIF (only_res) THEN
REPORT "This Opcode is not decoded during a DEEP POWER DOWN"
SEVERITY ERROR;
ELSE read_data<=true;
read_op<=true;
END IF;
ELSIF (data_latch="00001011") THEN
IF (only_rdsr) THEN
REPORT "This Opcode is not decoded during a Prog. Cycle"
SEVERITY ERROR;
ELSIF (only_res) THEN
REPORT "This Opcode is not decoded during a DEEP POWER DOWN"
SEVERITY ERROR;
ELSE fast_read<=true;
END IF;
ELSIF (data_latch="00000010") THEN
IF (only_rdsr) THEN
REPORT "This Opcode is not decoded during a Prog. Cycle"
SEVERITY ERROR;
ELSIF (only_res) THEN
REPORT "This Opcode is not decoded during a DEEP POWER DOWN"
SEVERITY ERROR;
ELSE pp<=true;
write_op<=true;
END IF;
ELSIF (data_latch="11011000") THEN
IF (only_rdsr) THEN
REPORT "This Opcode is not decoded during a Prog. Cycle"
SEVERITY ERROR;
ELSIF (only_res) THEN
REPORT "This Opcode is not decoded during a DEEP POWER DOWN"
SEVERITY ERROR;
ELSE se<=true;
write_op<=true;
END IF;
ELSIF (data_latch="11000111") THEN
IF (only_rdsr) THEN
REPORT "This Opcode is not decoded during a Prog. Cycle"
SEVERITY ERROR;
ELSIF (only_res) THEN
REPORT "This Opcode is not decoded during a DEEP POWER DOWN"
SEVERITY ERROR;
ELSE be<=true;
write_op<=true;
FOR i IN 0 TO NB_BPi-1 LOOP
BP(i):=status_register(i+2);
END LOOP;
IF (BP/="000") THEN
protect<=true;
write_op <= false;
END IF;
END IF;
ELSIF (data_latch="10111001") THEN
IF (only_rdsr) THEN
REPORT "This Opcode is not decoded during a Prog. Cycle"
SEVERITY ERROR;
ELSIF (only_res) THEN
REPORT "This Opcode is not decoded during a DEEP POWER DOWN"
SEVERITY ERROR;
ELSE dp<=true;
END IF;
ELSIF (data_latch="10101011") THEN
IF (only_rdsr) THEN
REPORT "This Opcode is not decoded during a Prog. Cycle"
SEVERITY ERROR;
ELSE res<=true;
END IF;
ELSIF (data_latch="10011111") THEN -- HC 24/09/03
IF (only_rdsr) THEN
REPORT "This Opcode is not decoded during a Prog. Cycle"
SEVERITY ERROR;
ELSIF (only_res) THEN
REPORT "This Opcode is not decoded during a DEEP POWER DOWN"
SEVERITY ERROR;
ELSE rdid<=true;
END IF;
ELSE report " False instruction, please retry "
severity ERROR;
END IF;
END IF;
-----------------------------------------------------------------------
-- addresses and data reception and treatment
-----------------------------------------------------------------------
IF ((byte_ok'event AND byte_ok)AND(byte_cpt=1)AND(NOT only_rdsr)AND(NOT (only_res))) THEN
IF (((read_data) or (fast_read) or (se) or (pp)) AND (NOT rdsr)) THEN adress_1:=data_latch;
ELSIF (wrsr AND (NOT rdsr)) THEN
wr_latch<=data_latch;
END IF;
END IF;
IF ((byte_ok'event AND byte_ok)AND(byte_cpt=2)AND(NOT only_rdsr)AND(NOT (only_res))) THEN
IF (((read_data) or (fast_read) or (se) or (pp)) AND (NOT rdsr)) THEN
adress_2:=data_latch;
END IF;
END IF;
IF ((byte_ok'event AND byte_ok)AND(byte_cpt=3)AND(NOT only_rdsr)AND(NOT (only_res))) THEN
IF (((read_data) or (fast_read) or (se) or (pp)) AND (NOT rdsr)) THEN adress_3:=data_latch;
FOR i IN 0 TO (NB_BIT_ADD-1) LOOP
adress(i):=adress_3(i);
adress(i+NB_BIT_ADD):=adress_2(i);
adress(i+2*NB_BIT_ADD):=adress_1(i);
add_mem<=adress;
END LOOP;
FOR i in (LSB_TO_CODE_PAGE-1) downto 0 LOOP
LSB_adress(i):=adress(i);
END LOOP;
END IF;
IF ((se or pp) AND (NOT rdsr)) THEN
-------------------------------------------
-- To ignore "don't care MSB" of the adress
-------------------------------------------
FOR i IN 0 TO bit_to_code_mem-1 LOOP
cut_add(i):=adress(i);
END LOOP;
int_add:=to_natural(cut_add);
--------------------------------------------------
-- Sector protection detection
--------------------------------------------------
FOR i IN 0 TO NB_BPi-1 LOOP
BP(i):=status_register(i+2);
END LOOP;
IF (BP="111" or BP="110") THEN
protect<=true;
write_op <= false;
ELSIF BP="101" THEN
IF int_add>=((TOP_MEM+1)/2) THEN
protect<=true;
write_op <= false;
END IF;
ELSIF BP="100" THEN
IF int_add>=((TOP_MEM+1)*3/4) THEN
protect<=true;
write_op <= false;
END IF;
ELSIF BP="011" THEN
IF int_add>=((TOP_MEM+1)*7/8) THEN
protect<=true;
write_op <= false;
END IF;
ELSIF BP="010" THEN
IF int_add>=((TOP_MEM+1)*15/16) THEN
protect<=true;
write_op <= false;
END IF;
ELSIF BP="001" THEN
IF int_add>=((TOP_MEM+1)*31/32) THEN
protect<=true;
write_op <= false;
END IF;
ELSE protect<=false;
END IF;
END IF;
END IF;
-----------------------------------------------------------------------------
-- PAGE PROGRAM
-- The adress's LSBs necessary to code a whole page are converted to a natural
-- and used to fullfill the page buffer p_prog the same way as the memory page
-- will be fullfilled.
----------------------------------------------------------------------------
IF (byte_ok'event and byte_ok and (byte_cpt>=4)AND(PP)AND(NOT only_rdsr)AND(NOT rdsr)) THEN
j:=(byte_cpt - 1 - NB_BIT_ADD_MEM/NB_BIT_ADD + to_natural(LSB_adress)) MOD(Plength);
p_prog(j)<=data_latch;
END IF;
----------------------------------------------
--- READ INSTRUCTIONS
----------------------------------------------
-- to inhib READ instruction
IF (inhib_read) THEN
read_op <= false;
READ_data<=false;
fast_READ<=false;
READ_enable<=false;
data_request<=false;
END IF;
-- to launch adress treatment in memory access
IF ( ((byte_ok'event AND byte_ok) AND READ_data AND (byte_cpt=3))
OR ((byte_ok'event AND byte_ok) AND fast_READ AND (byte_cpt=4)) ) THEN
READ_enable<=true;
END IF;
-- to send a request for the data pointed by the adress
IF ( ((byte_ok'event AND byte_ok) AND READ_data AND (byte_cpt>=3) )
OR ((byte_ok'event AND byte_ok) AND fast_READ AND (byte_cpt>=4)) ) THEN
data_request<=true;
END IF;
IF ( (READ_data AND (byte_cpt>3) AND (NOT byte_ok)) OR
(fast_READ AND (byte_cpt>4) AND (NOT byte_ok)) ) THEN
data_request<=false;
END IF;
--------------------------------------------------------
-- STATUS REGISTER INSTRUCTIONS
--------------------------------------------------------
-- WREN/WRDI instructions
-------------------------
IF (WEL'event AND WEL='1') THEN
register_bis(1)<='1';
END IF;
IF (inhib_wren'event and inhib_wren) THEN
WREN<=false;
write_op<=false;
END IF;
IF (inhib_wrdi'event and inhib_wrdi) THEN
WRDI<=false;
write_op<=false;
END IF;
------------------------
-- RESET WEL instruction
------------------------
IF (reset_WEL'event AND reset_WEL='1') THEN
register_bis(1)<='0';
END IF;
IF (Power_up'event AND Power_up) THEN
register_bis(1)<='0';
END IF;
---------------------
-- WRSR instructions
---------------------
IF (wr_cycle'event AND (wr_cycle))THEN
REPORT "Write status register cycle has begun"
severity NOTE;
register_bis<=((register_bis) or ("00000011"));
END IF;
IF (wr_cycle'event AND (NOT wr_cycle)) THEN
REPORT "Write status register cycle is finished"
severity NOTE;
register_bis<=((wr_latch) and SR_Mask);
-- register_temp:=wr_latch and SR_Mask;
-- write_status("status_register.txt",register_temp);
wrsr<=false;
END IF;
IF (inhib_WRSR'event and inhib_WRSR) THEN
wrsr<=false;
END IF;
IF (NOT wrsr) THEN
wr_latch<="00000000";
END IF;
--------
-- PROG
--------
IF (WIP'event AND WIP='1') THEN
register_bis(0)<='1';
END IF;
IF (WIP'event AND WIP='0') THEN
register_bis(0)<='0';
write_op<=false;
END IF;
--------------------
-- rdsr instruction
--------------------
IF (inhib_rdsr'event AND inhib_rdsr) THEN
rdsr<=false;
END IF;
------------------------------------------------------------
-- BULK/SECTOR ERASE INSTRUCTIONS
------------------------------------------------------------
IF (inhib_BE) THEN
protect<=false;
BE<=false;
END IF;
IF (inhib_SE) THEN
protect<=false;
SE<=false;
END IF;
------------------------------------------------------------
-- PAGE PROGRAM INSTRUCTIONS
------------------------------------------------------------
IF (inhib_PP) THEN
protect<=false;
PP<=false;
END IF;
------------------------------------------------------------
-- DEEP POWER DOWN
-- RELEASE FROM DEEP POWER DOWN AND READ ELECTRONIC SIGNATURE
-------------------------------------------------------------
IF (inhib_DP) THEN DP <=false; END IF;
IF (inhib_RES) THEN RES<=false; END IF;
-----------------------------
-- Read Jedec ID --HC 24/03/09
-----------------------------
IF (inhib_RDID) THEN RDID <= FALSE; END IF;
END PROCESS decode;
----------------------------------------------------------
----------------- SYNCHRONOUS PROCESS ----------------
----------------------------------------------------------
sync_instructions: PROCESS
VARIABLE i,j,k:natural:=0;
BEGIN
WAIT ON C_int, select_ok;
WEL<='0';
reset_WEL<='0';
---------------------------------------------
-- READ_data
---------------------------------------------
IF ((NOT READ_data) AND (NOT fast_read)) THEN
inhib_READ<=false;
END IF;
IF (((byte_cpt=0)
or (byte_cpt=1)
or (byte_cpt=2)
or (byte_cpt=3 AND cpt/=7))
AND READ_data AND (NOT select_ok)) THEN
REPORT "Instruction canceled because the chip is deselected"
SEVERITY WARNING;
inhib_READ<=true;
END IF;
IF (READ_data AND ((byte_cpt=3 AND cpt=7) OR (byte_cpt>=4))) THEN
IF (NOT select_ok) THEN
inhib_READ<=true;
i:=0;
Q_bis<='Z' after tSHQZ;
ELSIF (C_int'event AND C_int='0')THEN
Q_bis<=data_to_read(7-i) after tCLQV;
i:=(i+1) mod 8;
END IF;
END IF;
--------------------------------------------------------------------
-- Fast_Read
--------------------------------------------------------------------
IF (((byte_cpt=0)
or (byte_cpt=1)
or (byte_cpt=2)
or (byte_cpt=3)
or (byte_cpt=4 AND cpt/=7))
AND fast_READ AND (NOT select_ok)) THEN
REPORT "Instruction canceled because the chip is deselected"
SEVERITY WARNING;
inhib_READ<=true;
END IF;
IF (fast_READ AND ((byte_cpt=4 AND cpt=7) OR (byte_cpt>=5))) THEN
IF (NOT select_ok) THEN
inhib_READ<=true;
i:=0;
Q_bis<='Z' after tSHQZ;
ELSIF (C_int'event AND C_int='0')THEN
Q_bis<=data_to_read(7-i) after tCLQV;
i:=(i+1) mod 8;
END IF;
END IF;
-------------------------------------------
-- Write_enable
-------------------------------------------
IF (NOT WREN) THEN
inhib_WREN<=false;
END IF;
IF (WREN AND (NOT only_rdsr) AND (NOT only_res)) THEN
IF (C_int'event AND C_int='1') THEN
inhib_wren<=true;
report "Instruction canceled because the chip is still selected."
severity WARNING;
ELSIF (NOT select_ok) THEN
WEL<=('1');
inhib_wren<=true;
END IF;
END IF;
---------------------------------------------
-- Write_disable
---------------------------------------------
IF (NOT WRDI) THEN
inhib_WRDI<=false;
END IF;
IF (WRDI AND (NOT only_rdsr) AND (NOT only_res)) THEN
IF (C_int'event AND C_int='1') THEN
inhib_wrdi<=true;
report "Instruction canceled because the chip is still selected."
severity WARNING;
ELSIF (NOT select_ok) THEN
reset_WEL<=('1');
inhib_wrdi<=true;
END IF;
END IF;
-------------------------------------------
-- Write_status_register
-------------------------------------------
IF (NOT WRSR) THEN
inhib_WRSR<=false;
END IF;
IF (WRSR AND (NOT only_rdsr) AND (NOT only_res)) THEN
IF (byte_cpt=1 AND (cpt /=7 OR not byte_ok) AND (NOT wr_cycle)) THEN
IF (NOT select_ok) THEN
REPORT "Instruction canceled because the chip is deselected"
SEVERITY WARNING;
inhib_WRSR<=true;
END IF;
ELSIF (byte_cpt=1 AND cpt=7 AND byte_ok) THEN
IF (write_protect) THEN
REPORT "Instruction canceled because status register is hardware protected"
SEVERITY warning;
inhib_WRSR<=true;
ELSIF (select_ok'event AND (NOT select_ok)) THEN
IF (status_register(1)='0') THEN
REPORT "Instruction canceled because WEL is reset"
SEVERITY WARNING;
inhib_WRSR<=true;
ELSE wr_cycle<=true;
WIP <= '1';
WAIT FOR tW;
WIP <= '0';
wr_cycle<=false;
END IF;
END IF;
ELSIF (byte_cpt=2)THEN
IF ((C_int'event AND C_int='1') AND (NOT rdsr)) THEN
REPORT "Instruction canceled because the chip is still selected"
SEVERITY WARNING;
inhib_WRSR<=true;
ELSIF (select_ok'event AND (NOT select_ok)) THEN
IF (status_register(1)='0') THEN
REPORT "Instruction canceled because WEL is reset"
SEVERITY WARNING;
inhib_WRSR<=true;
ELSE wr_cycle<=true;
WIP <= '1';
WAIT FOR tW;
WIP <= '0';
wr_cycle<=false;
END IF;
END IF;
END IF;
END IF;
---------------------------------------------
-- Bulk_erase
---------------------------------------------
IF (NOT BE) THEN
inhib_BE<=false;
END IF;
IF (BE AND (NOT only_rdsr) AND (NOT only_res)) THEN
IF (C_int'event AND C_int='1') THEN
REPORT "Instruction canceled because the chip is still selected"
SEVERITY WARNING;
inhib_BE<=true;
ELSIF (NOT select_ok) THEN
IF (status_register(1)='0') THEN
REPORT "Instruction canceled because WEL is reset"
SEVERITY WARNING;
BE_enable<=false;
inhib_BE<=true;
ELSIF (protect AND BE) THEN
REPORT "Instruction canceled because at least one sector is protected"
SEVERITY WARNING;
BE_enable<=false;
inhib_BE<=true;
ELSE REPORT "Bulk erase cycle has begun"
severity NOTE;
BE_enable<=true;
WIP<='1';
WAIT for tBE;
REPORT "Bulk erase cycle is finished"
severity NOTE;
BE_enable<=false;
inhib_BE<=true;
WIP<='0';
reset_WEL<='1';
END IF;
END IF;
END IF;
---------------------------------------------
-- Sector_erase
---------------------------------------------
IF (NOT SE) THEN
inhib_SE<=false;
END IF;
IF ((byte_cpt=0 or byte_cpt=1 or byte_cpt=2 or (byte_cpt=3 AND (cpt/=7 OR not byte_ok)))
AND SE AND (NOT only_rdsr) AND (NOT only_res)) THEN
IF (NOT select_ok) THEN
REPORT "Instruction canceled because the chip is deselected"
SEVERITY WARNING;
inhib_SE<=true;
END IF;
END IF;
IF ((byte_cpt=4 OR (byte_cpt=3 AND cpt=7 AND byte_ok)) AND SE AND (NOT only_RDSR) AND (NOT only_res)) THEN
IF (byte_cpt=4 AND (C_int'event AND C_int='1')) THEN
REPORT "Instruction canceled because the chip is still selected"
SEVERITY WARNING;
inhib_SE<=true;
ELSIF (NOT select_ok) THEN
IF (status_register(1)='0') THEN
REPORT "Instruction canceled because WEL is reset"
SEVERITY warning;
SE_enable<=false;
inhib_SE<=true;
ELSIF (protect AND SE) THEN
REPORT "Instruction canceled because the SE sector is protected"
SEVERITY WARNING;
SE_enable<=false;
inhib_SE<=true;
ELSE REPORT "Sector erase cycle has begun"
severity NOTE;
SE_enable<=true;
WIP<='1';
WAIT for tSE;
REPORT "Sector erase cycle is finished"
severity NOTE;
SE_enable<=false;
inhib_SE<=true;
WIP<='0';
reset_WEL<='1';
END IF;
END IF;
END IF;
---------------------------------------------
-- Page_Program
---------------------------------------------
IF (NOT PP) THEN
inhib_PP<=false;
add_pp_enable<=false;
pp_enable<=false;
END IF;
IF ((byte_cpt=0 or byte_cpt=1 or byte_cpt=2 or byte_cpt=3 or (byte_cpt=4 AND (cpt/=7 OR NOT byte_ok)))
AND PP AND (NOT only_rdsr) AND (NOT only_res) AND (NOT select_ok)) THEN
REPORT "Instruction canceled because the chip is deselected"
SEVERITY WARNING;
inhib_PP<=true;
END IF;
IF ((byte_cpt=5 OR (byte_cpt=4 AND cpt=7)) AND PP AND (NOT only_rdsr) AND (NOT only_res)) THEN
add_pp_enable<=true;
IF (status_register(1)='0') THEN
REPORT "Instruction canceled because WEL is reset"
SEVERITY warning;
PP_enable<=false;
inhib_PP<=true;
ELSIF (protect AND PP) THEN
REPORT "Instruction canceled because the PP sector is protected"
SEVERITY WARNING;
PP_enable<=false;
inhib_PP<=true;
END IF;
IF (select_ok'event AND (NOT select_ok) AND PP) THEN
REPORT "Page program cycle has begun"
severity NOTE;
WIP<='1';
WAIT for tPP;
REPORT "Page program cycle is finished"
SEVERITY NOTE;
PP_enable<=true;
WIP<='0';
inhib_PP<=true;
reset_WEL<='1';
END IF;
END IF;
IF (byte_cpt>5 AND PP AND (NOT only_rdsr) AND (NOT only_res) AND byte_ok) THEN
IF (select_ok'event AND (NOT select_ok)) THEN
REPORT "Page program cycle has begun"
severity NOTE;
WIP<='1';
WAIT for tPP;
REPORT "Page program cycle is finished"
SEVERITY NOTE;
PP_enable<=true;
WIP<='0';
inhib_PP<=true;
reset_WEL<='1';
END IF;
END IF;
IF (byte_cpt>5 AND PP AND (NOT only_rdsr) AND (NOT only_res) AND (NOT byte_ok)) THEN
IF (select_ok'event AND (NOT select_ok)) THEN
REPORT "Instruction canceled because the chip is deselected"
SEVERITY WARNING;
inhib_PP<=true;
PP_enable<=false;
END IF;
END IF;
-------------------------------------------
-- Deep Power Down
-------------------------------------------
IF (NOT DP) THEN
inhib_DP<=false;
only_res<=false;
END IF;
IF (DP AND (NOT only_rdsr) AND (NOT only_res) AND (NOT RES)) THEN
IF (C_int'event AND C_int='1') THEN
report "Instruction canceled because the chip is still selected."
severity WARNING;
inhib_DP<=true;
only_res<=false;
ELSIF (select_ok'event AND (NOT select_ok)) THEN
REPORT "Chip is entering deep power down mode"
SEVERITY NOTE;
-- useful when chip is selected again to inhib every op_code except RES
-- and to check tDP
only_res<=true;
END IF;
END IF;
-----------------------------------------------------------------------
-- Release from Deep Power Down Mode and Read Electronic Signature
-----------------------------------------------------------------------
IF (NOT RES) THEN
inhib_RES<=false;
j:=0;
END IF;
IF (RES AND (byte_cpt=1 and cpt=0) AND (NOT only_rdsr) AND (NOT select_ok) ) THEN
IF (only_res) THEN -- HC 22/09/03
REPORT "The chip is releasing from DEEP POWER DOWN"
SEVERITY NOTE;
inhib_RES<=false, true after tRES1;
inhib_DP<=false, true after tRES1;
ELSE
inhib_RES<=true; --HC 22/09/03
inhib_DP<=true; --HC 22/09/03
END IF;
ELSIF (((byte_cpt=1 AND cpt>0) OR (byte_cpt=2) OR (byte_cpt=3) OR (byte_cpt=4 AND (cpt<7 OR NOT byte_ok)))
AND RES AND (NOT only_rdsr) AND (NOT select_ok)) THEN
REPORT "Electronic Signature must be read at least once. Instruction not valid"
severity ERROR;
ELSIF (((byte_cpt=4 AND cpt=7 AND byte_ok) OR (byte_cpt>4)) AND RES AND (NOT only_rdsr)AND (NOT select_ok)) THEN
IF ( only_res) THEN -- HC 22/09/03
inhib_RES<=true after tRES2;
inhib_DP<=true after tRES2;
REPORT "The Chip is releasing from DEEP POWER DOWN" SEVERITY NOTE;
ELSE
inhib_RES<=true after tRES2; -- HC 22/09/03
inhib_DP<=true after tRES2; -- HC 22/09/03
END IF;
Q_bis<='Z';
ELSIF (((byte_cpt=3 AND cpt=7) OR byte_cpt>=4)
AND RES AND (NOT only_rdsr) AND (C_int'event AND C_int='0')) THEN
Q_bis<=signature(7-j) after tCLQV;
j:=(j+1) mod 8;
END IF;
-----------------------------------------------------------------------
-- Read Jedec Signature -- HC 24/09/03
-----------------------------------------------------------------------
IF (NOT RDID) THEN
inhib_RDID<=false;
END IF;
IF ((byte_cpt=0) AND RDID AND (NOT select_ok))
THEN REPORT "Instuction canceled because the chip is deselected" SEVERITY WARNING;
inhib_RDID <= true;
END IF;
IF (RDID AND ((byte_cpt=0 AND cpt=7) OR (byte_cpt>=1))) THEN
IF (NOT select_ok) THEN
inhib_RDID <= true;
k:=0;
Q_bis <='Z' after tSHQZ;
ELSIF (C_int'event AND C_int='0' AND byte_cpt<=1) THEN
Q_bis <= manufacturerID(7-k) after tCLQV;
k:=(k+1) MOD 8;
ELSIF (C_int'event AND C_int='0' AND byte_cpt=2) THEN
Q_bis <= memtype(7-k) after tCLQV;
k:=(k+1) MOD 8;
ELSIF (C_int'event AND C_int='0' AND byte_cpt=3) THEN
Q_bis <= density(7-k) after tCLQV;
k:=(k+1) MOD 8;
ELSIF (C_int'event AND C_int='0' AND byte_cpt>3) THEN
Q_bis <= '0' after tCLQV;
END IF;
END IF;
END PROCESS sync_instructions;
---------------------------------------------------------
-- This process shifts out status register on data output
Read_status_register: PROCESS
---------------------------------------------------------
VARIABLE j:integer:=0;
BEGIN
WAIT ON C_int,select_ok, rdsr;
IF (NOT rdsr) THEN
inhib_rdsr<=false;
END IF;
IF (RDSR AND (NOT select_ok)) THEN
j:=0;
Q_bis<= 'Z' after tSHQZ;
inhib_rdsr<=true;
ELSIF (RDSR AND (C_int'event AND C_int='0')) THEN
Q_bis<=status_register(7-j) after tCLQV;
j:=(j+1) mod 8;
END IF;
END PROCESS read_status_register;
----------------------------------------------------------------------------------------
-- This process checks select and deselect conditions. Some other conditions are tested:
-- prog cycle, deep power down mode and read electronic signature.
pin_S: PROCESS
----------------------------------------------------------------------------------------
BEGIN
WAIT ON S;
IF (S='0') THEN
IF (RES AND only_res) THEN -- HC 22/09/03
REPORT "The chip must be deselected during tRES"
severity ERROR;
ELSIF (DP) THEN
IF (NOT only_res'stable(tDP)) THEN
REPORT "The chip must be deselected during tDP"
severity ERROR;
ELSE
REPORT "Only a read electronic signature instruction will be valid !"
SEVERITY NOTE;
END IF;
END IF;
IF Power_up THEN select_ok<=true;
END IF;
IF(pp or wrsr or be or se) THEN
REPORT "Only a read status register instruction will be valid !"
SEVERITY NOTE;
only_rdsr<=true;
END IF;
END IF;
IF (S='1') THEN
select_ok<=false;
only_rdsr<=false;
END IF;
END PROCESS pin_S;
----------------------------------------------------------------
-- This Process detects the hardware protection mode
HPM_detect: PROCESS
----------------------------------------------------------------
BEGIN
WAIT ON W,C_int;
IF (W = '0'AND status_REGISTER(7) ='1') THEN
write_protect <= true;
END IF;
IF (W = '1') THEN
write_protect <= false;
END IF;
END PROCESS HPM_detect ;
----------------------------------------------------------------------
-- This process detects if Write_protect toggles during an instruction
write_protect_toggle_detect: PROCESS
----------------------------------------------------------------------
BEGIN
WAIT ON select_ok,write_protect;
IF (write_protect AND select_ok) THEN
write_protect_toggle <= true;
IF (now /= 0 ns) THEN t_write_protect_toggle <= now; END IF;
END IF;
IF (NOT select_ok) THEN write_protect_toggle <= false; END IF;
END PROCESS write_protect_toggle_detect;
---------------------------------------------------------------------
-- This process returns an error if SRWD=1 and Wc is swithed during a
-- WRSR instruction
---------------------------------------------------------------------
wc_error_detect: PROCESS
BEGIN
WAIT ON wrsr, write_protect_toggle;
IF (wrsr AND write_protect_toggle) THEN
IF (NOW /= 0 ns) THEN
REPORT "It is not allowed to switch the Wc pin during a WRSR instruction"
severity FAILURE;
END IF;
END IF;
IF (wrsr AND (status_REGISTER(7) ='1')) THEN
srwd_wrsr <= TRUE; -- becomes one when WRSR is decoded and WIP=1
END IF;
IF (NOT wrsr) THEN srwd_wrsr <= FALSE; END IF;
END PROCESS wc_error_detect;
END behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1644.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s13b00x00p02n01i01644ent IS
END c08s13b00x00p02n01i01644ent;
ARCHITECTURE c08s13b00x00p02n01i01644arch OF c08s13b00x00p02n01i01644ent IS
BEGIN
TESTING: PROCESS
BEGIN
if TRUE then
NULL;
end if;
assert FALSE
report "***PASSED TEST: c08s13b00x00p02n01i01644"
severity NOTE;
wait;
END PROCESS TESTING;
END c08s13b00x00p02n01i01644arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1644.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s13b00x00p02n01i01644ent IS
END c08s13b00x00p02n01i01644ent;
ARCHITECTURE c08s13b00x00p02n01i01644arch OF c08s13b00x00p02n01i01644ent IS
BEGIN
TESTING: PROCESS
BEGIN
if TRUE then
NULL;
end if;
assert FALSE
report "***PASSED TEST: c08s13b00x00p02n01i01644"
severity NOTE;
wait;
END PROCESS TESTING;
END c08s13b00x00p02n01i01644arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1644.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s13b00x00p02n01i01644ent IS
END c08s13b00x00p02n01i01644ent;
ARCHITECTURE c08s13b00x00p02n01i01644arch OF c08s13b00x00p02n01i01644ent IS
BEGIN
TESTING: PROCESS
BEGIN
if TRUE then
NULL;
end if;
assert FALSE
report "***PASSED TEST: c08s13b00x00p02n01i01644"
severity NOTE;
wait;
END PROCESS TESTING;
END c08s13b00x00p02n01i01644arch;
|
package pack is
type rec is record
x : integer;
end record;
impure function get_field (r : rec) return integer;
end package;
package body pack is
impure function get_field (r : rec) return integer is
begin
return r.x;
end function;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
generic ( r : rec );
port ( o : out bit_vector(1 to get_field(r)) );
end entity;
architecture test of sub is
begin
end architecture;
-------------------------------------------------------------------------------
entity wave8 is
end entity;
use work.pack.all;
architecture test of wave8 is
function new_rec return rec is
begin
return (x => 4);
end function;
constant r : rec := new_rec;
signal x : bit_vector(1 to 4);
begin
u: entity work.sub
generic map ( r )
port map ( x );
end architecture;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: EXTERNAL_MEMORY_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 16384
-- C_READ_DEPTH_A : 16384
-- C_ADDRA_WIDTH : 14
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 16384
-- C_READ_DEPTH_B : 16384
-- C_ADDRB_WIDTH : 14
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY EXTERNAL_MEMORY_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END EXTERNAL_MEMORY_prod;
ARCHITECTURE xilinx OF EXTERNAL_MEMORY_prod IS
COMPONENT EXTERNAL_MEMORY_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : EXTERNAL_MEMORY_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: EXTERNAL_MEMORY_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 16384
-- C_READ_DEPTH_A : 16384
-- C_ADDRA_WIDTH : 14
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 16384
-- C_READ_DEPTH_B : 16384
-- C_ADDRB_WIDTH : 14
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY EXTERNAL_MEMORY_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END EXTERNAL_MEMORY_prod;
ARCHITECTURE xilinx OF EXTERNAL_MEMORY_prod IS
COMPONENT EXTERNAL_MEMORY_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : EXTERNAL_MEMORY_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
PACKAGE avalon_dacad5668_interface_pkg IS
CONSTANT c_analog_output_interface_address_width : INTEGER := 5;
COMPONENT avalon_dacad5668_interface IS
GENERIC (
BASE_CLK: INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 10000000;
INTERNAL_REFERENCE : STD_LOGIC := '0'; -- '0' = set to internal reference, '1' set to external reference
UNIQUE_ID: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0')
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(c_analog_output_interface_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
osl_avs_waitrequest : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC;
osl_LDAC_n : OUT STD_LOGIC;
osl_CLR_n : OUT STD_LOGIC
);
END COMPONENT;
CONSTANT c_dacad5668_subtype_id : STD_LOGIC_VECTOR(c_fLink_subtype_length-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(1,c_fLink_subtype_length));
CONSTANT c_dacad5668_interface_version : STD_LOGIC_VECTOR(c_fLink_interface_version_length-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(0,c_fLink_interface_version_length));
END PACKAGE avalon_dacad5668_interface_pkg;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.avalon_dacad5668_interface_pkg.ALL;
USE work.fLink_definitions.ALL;
USE work.dacad5668_pkg.ALL;
ENTITY avalon_dacad5668_interface IS
GENERIC (
BASE_CLK: INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 10000000;
INTERNAL_REFERENCE : STD_LOGIC := '0'; -- '0' = set to internal reference, '1' set to external reference
UNIQUE_ID: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0')
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(c_analog_output_interface_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
osl_avs_waitrequest : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC;
osl_LDAC_n : OUT STD_LOGIC;
osl_CLR_n : OUT STD_LOGIC
);
CONSTANT c_configuration_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_configuration_address,c_analog_output_interface_address_width);
CONSTANT c_typdef_address : UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_typdef_address,c_analog_output_interface_address_width);
CONSTANT c_mem_size_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_mem_size_address,c_analog_output_interface_address_width);
CONSTANT c_number_of_channels_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_number_of_channels_address,c_analog_output_interface_address_width);
CONSTANT c_unique_id_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_unique_id_address,c_analog_output_interface_address_width);
CONSTANT c_usig_resolution_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_number_of_std_registers,c_analog_output_interface_address_width);
CONSTANT c_usig_value_0_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := c_usig_resolution_address + 1;
CONSTANT c_usig_last_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := c_usig_value_0_address + NUMBER_OF_CHANNELS;
END ENTITY avalon_dacad5668_interface;
ARCHITECTURE rtl OF avalon_dacad5668_interface IS
TYPE t_internal_register IS RECORD
global_reset_n : STD_LOGIC;
adc_reset_n : STD_LOGIC;
set_values : t_value_regs;
END RECORD;
SIGNAL ri,ri_next : t_internal_register;
BEGIN
my_dacad5668 : dacad5668
GENERIC MAP (BASE_CLK,SCLK_FREQUENCY,INTERNAL_REFERENCE)
PORT MAP (isl_clk,ri.adc_reset_n,ri.set_values,osl_LDAC_n,osl_CLR_n,osl_sclk,oslv_Ss,osl_mosi);
-- cobinatoric process
comb_proc : PROCESS (isl_reset_n,ri,isl_avs_write,islv_avs_address,isl_avs_read,islv_avs_write_data)
VARIABLE vi : t_internal_register;
VARIABLE dacad5668_part_nr: INTEGER := 0;
VARIABLE address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(0,c_analog_output_interface_address_width);
BEGIN
-- keep variables stable
vi := ri;
--standard values
oslv_avs_read_data <= (OTHERS => '0');
vi.global_reset_n := '1';
vi.adc_reset_n := '1';
address := UNSIGNED(islv_avs_address);
--avalon slave interface write part
IF isl_avs_write = '1' THEN
IF address = c_configuration_address THEN
IF islv_avs_byteenable(0) = '1' THEN
vi.global_reset_n := NOT islv_avs_write_data(c_fLink_reset_bit_num);
END IF;
ELSIF address>= c_usig_value_0_address AND address< c_usig_last_address THEN
dacad5668_part_nr := to_integer(UNSIGNED(islv_avs_address) - c_usig_value_0_address);
--only 16 bit are needed cause adc resolution is 16
IF islv_avs_byteenable(0) = '1' THEN
vi.set_values(dacad5668_part_nr)(7 DOWNTO 0) := islv_avs_write_data(7 DOWNTO 0);
END IF;
IF islv_avs_byteenable(1) = '1' THEN
vi.set_values(dacad5668_part_nr)(15 DOWNTO 8) := islv_avs_write_data(15 DOWNTO 8);
END IF;
END IF;
END IF;
--avalon slave interface read part
IF isl_avs_read = '1' THEN
CASE address IS
WHEN c_typdef_address =>
oslv_avs_read_data ((c_fLink_interface_version_length + c_fLink_subtype_length + c_fLink_id_length - 1) DOWNTO
(c_fLink_interface_version_length + c_fLink_subtype_length)) <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_analog_output_id,c_fLink_id_length));
oslv_avs_read_data((c_fLink_interface_version_length + c_fLink_subtype_length - 1) DOWNTO c_fLink_interface_version_length) <= c_dacad5668_subtype_id;
oslv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) <= c_dacad5668_interface_version;
WHEN c_mem_size_address =>
oslv_avs_read_data(c_analog_output_interface_address_width+2) <= '1';
WHEN c_number_of_channels_address =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(NUMBER_OF_CHANNELS,c_fLink_avs_data_width));
WHEN c_unique_id_address =>
oslv_avs_read_data <= UNIQUE_ID;
WHEN c_usig_resolution_address =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(RESOLUTION,c_fLink_avs_data_width));
WHEN OTHERS =>
IF address >= c_usig_value_0_address AND address < c_usig_last_address THEN
dacad5668_part_nr := to_integer(address - c_usig_value_0_address);
oslv_avs_read_data(RESOLUTION-1 DOWNTO 0) <= std_logic_vector(vi.set_values(dacad5668_part_nr));
END IF;
END CASE;
END IF;
IF isl_reset_n = '0' OR vi.global_reset_n = '0' THEN
vi.adc_reset_n := '0';
FOR i IN 0 TO NUMBER_OF_CHANNELS-1 LOOP
vi.set_values(i) := (OTHERS => '0');
END LOOP;
END IF;
--keep variables stable
ri_next <= vi;
END PROCESS comb_proc;
reg_proc : PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_proc;
osl_avs_waitrequest <= '0';
END rtl;
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
PACKAGE avalon_dacad5668_interface_pkg IS
CONSTANT c_analog_output_interface_address_width : INTEGER := 5;
COMPONENT avalon_dacad5668_interface IS
GENERIC (
BASE_CLK: INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 10000000;
INTERNAL_REFERENCE : STD_LOGIC := '0'; -- '0' = set to internal reference, '1' set to external reference
UNIQUE_ID: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0')
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(c_analog_output_interface_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
osl_avs_waitrequest : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC;
osl_LDAC_n : OUT STD_LOGIC;
osl_CLR_n : OUT STD_LOGIC
);
END COMPONENT;
CONSTANT c_dacad5668_subtype_id : STD_LOGIC_VECTOR(c_fLink_subtype_length-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(1,c_fLink_subtype_length));
CONSTANT c_dacad5668_interface_version : STD_LOGIC_VECTOR(c_fLink_interface_version_length-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(0,c_fLink_interface_version_length));
END PACKAGE avalon_dacad5668_interface_pkg;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.avalon_dacad5668_interface_pkg.ALL;
USE work.fLink_definitions.ALL;
USE work.dacad5668_pkg.ALL;
ENTITY avalon_dacad5668_interface IS
GENERIC (
BASE_CLK: INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 10000000;
INTERNAL_REFERENCE : STD_LOGIC := '0'; -- '0' = set to internal reference, '1' set to external reference
UNIQUE_ID: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0')
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(c_analog_output_interface_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
osl_avs_waitrequest : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC;
osl_LDAC_n : OUT STD_LOGIC;
osl_CLR_n : OUT STD_LOGIC
);
CONSTANT c_configuration_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_configuration_address,c_analog_output_interface_address_width);
CONSTANT c_typdef_address : UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_typdef_address,c_analog_output_interface_address_width);
CONSTANT c_mem_size_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_mem_size_address,c_analog_output_interface_address_width);
CONSTANT c_number_of_channels_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_number_of_channels_address,c_analog_output_interface_address_width);
CONSTANT c_unique_id_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_unique_id_address,c_analog_output_interface_address_width);
CONSTANT c_usig_resolution_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_number_of_std_registers,c_analog_output_interface_address_width);
CONSTANT c_usig_value_0_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := c_usig_resolution_address + 1;
CONSTANT c_usig_last_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := c_usig_value_0_address + NUMBER_OF_CHANNELS;
END ENTITY avalon_dacad5668_interface;
ARCHITECTURE rtl OF avalon_dacad5668_interface IS
TYPE t_internal_register IS RECORD
global_reset_n : STD_LOGIC;
adc_reset_n : STD_LOGIC;
set_values : t_value_regs;
END RECORD;
SIGNAL ri,ri_next : t_internal_register;
BEGIN
my_dacad5668 : dacad5668
GENERIC MAP (BASE_CLK,SCLK_FREQUENCY,INTERNAL_REFERENCE)
PORT MAP (isl_clk,ri.adc_reset_n,ri.set_values,osl_LDAC_n,osl_CLR_n,osl_sclk,oslv_Ss,osl_mosi);
-- cobinatoric process
comb_proc : PROCESS (isl_reset_n,ri,isl_avs_write,islv_avs_address,isl_avs_read,islv_avs_write_data)
VARIABLE vi : t_internal_register;
VARIABLE dacad5668_part_nr: INTEGER := 0;
VARIABLE address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(0,c_analog_output_interface_address_width);
BEGIN
-- keep variables stable
vi := ri;
--standard values
oslv_avs_read_data <= (OTHERS => '0');
vi.global_reset_n := '1';
vi.adc_reset_n := '1';
address := UNSIGNED(islv_avs_address);
--avalon slave interface write part
IF isl_avs_write = '1' THEN
IF address = c_configuration_address THEN
IF islv_avs_byteenable(0) = '1' THEN
vi.global_reset_n := NOT islv_avs_write_data(c_fLink_reset_bit_num);
END IF;
ELSIF address>= c_usig_value_0_address AND address< c_usig_last_address THEN
dacad5668_part_nr := to_integer(UNSIGNED(islv_avs_address) - c_usig_value_0_address);
--only 16 bit are needed cause adc resolution is 16
IF islv_avs_byteenable(0) = '1' THEN
vi.set_values(dacad5668_part_nr)(7 DOWNTO 0) := islv_avs_write_data(7 DOWNTO 0);
END IF;
IF islv_avs_byteenable(1) = '1' THEN
vi.set_values(dacad5668_part_nr)(15 DOWNTO 8) := islv_avs_write_data(15 DOWNTO 8);
END IF;
END IF;
END IF;
--avalon slave interface read part
IF isl_avs_read = '1' THEN
CASE address IS
WHEN c_typdef_address =>
oslv_avs_read_data ((c_fLink_interface_version_length + c_fLink_subtype_length + c_fLink_id_length - 1) DOWNTO
(c_fLink_interface_version_length + c_fLink_subtype_length)) <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_analog_output_id,c_fLink_id_length));
oslv_avs_read_data((c_fLink_interface_version_length + c_fLink_subtype_length - 1) DOWNTO c_fLink_interface_version_length) <= c_dacad5668_subtype_id;
oslv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) <= c_dacad5668_interface_version;
WHEN c_mem_size_address =>
oslv_avs_read_data(c_analog_output_interface_address_width+2) <= '1';
WHEN c_number_of_channels_address =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(NUMBER_OF_CHANNELS,c_fLink_avs_data_width));
WHEN c_unique_id_address =>
oslv_avs_read_data <= UNIQUE_ID;
WHEN c_usig_resolution_address =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(RESOLUTION,c_fLink_avs_data_width));
WHEN OTHERS =>
IF address >= c_usig_value_0_address AND address < c_usig_last_address THEN
dacad5668_part_nr := to_integer(address - c_usig_value_0_address);
oslv_avs_read_data(RESOLUTION-1 DOWNTO 0) <= std_logic_vector(vi.set_values(dacad5668_part_nr));
END IF;
END CASE;
END IF;
IF isl_reset_n = '0' OR vi.global_reset_n = '0' THEN
vi.adc_reset_n := '0';
FOR i IN 0 TO NUMBER_OF_CHANNELS-1 LOOP
vi.set_values(i) := (OTHERS => '0');
END LOOP;
END IF;
--keep variables stable
ri_next <= vi;
END PROCESS comb_proc;
reg_proc : PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_proc;
osl_avs_waitrequest <= '0';
END rtl;
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
PACKAGE avalon_dacad5668_interface_pkg IS
CONSTANT c_analog_output_interface_address_width : INTEGER := 5;
COMPONENT avalon_dacad5668_interface IS
GENERIC (
BASE_CLK: INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 10000000;
INTERNAL_REFERENCE : STD_LOGIC := '0'; -- '0' = set to internal reference, '1' set to external reference
UNIQUE_ID: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0')
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(c_analog_output_interface_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
osl_avs_waitrequest : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC;
osl_LDAC_n : OUT STD_LOGIC;
osl_CLR_n : OUT STD_LOGIC
);
END COMPONENT;
CONSTANT c_dacad5668_subtype_id : STD_LOGIC_VECTOR(c_fLink_subtype_length-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(1,c_fLink_subtype_length));
CONSTANT c_dacad5668_interface_version : STD_LOGIC_VECTOR(c_fLink_interface_version_length-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(0,c_fLink_interface_version_length));
END PACKAGE avalon_dacad5668_interface_pkg;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.avalon_dacad5668_interface_pkg.ALL;
USE work.fLink_definitions.ALL;
USE work.dacad5668_pkg.ALL;
ENTITY avalon_dacad5668_interface IS
GENERIC (
BASE_CLK: INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 10000000;
INTERNAL_REFERENCE : STD_LOGIC := '0'; -- '0' = set to internal reference, '1' set to external reference
UNIQUE_ID: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0')
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(c_analog_output_interface_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
osl_avs_waitrequest : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC;
osl_LDAC_n : OUT STD_LOGIC;
osl_CLR_n : OUT STD_LOGIC
);
CONSTANT c_configuration_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_configuration_address,c_analog_output_interface_address_width);
CONSTANT c_typdef_address : UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_typdef_address,c_analog_output_interface_address_width);
CONSTANT c_mem_size_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_mem_size_address,c_analog_output_interface_address_width);
CONSTANT c_number_of_channels_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_number_of_channels_address,c_analog_output_interface_address_width);
CONSTANT c_unique_id_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_unique_id_address,c_analog_output_interface_address_width);
CONSTANT c_usig_resolution_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_number_of_std_registers,c_analog_output_interface_address_width);
CONSTANT c_usig_value_0_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := c_usig_resolution_address + 1;
CONSTANT c_usig_last_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := c_usig_value_0_address + NUMBER_OF_CHANNELS;
END ENTITY avalon_dacad5668_interface;
ARCHITECTURE rtl OF avalon_dacad5668_interface IS
TYPE t_internal_register IS RECORD
global_reset_n : STD_LOGIC;
adc_reset_n : STD_LOGIC;
set_values : t_value_regs;
END RECORD;
SIGNAL ri,ri_next : t_internal_register;
BEGIN
my_dacad5668 : dacad5668
GENERIC MAP (BASE_CLK,SCLK_FREQUENCY,INTERNAL_REFERENCE)
PORT MAP (isl_clk,ri.adc_reset_n,ri.set_values,osl_LDAC_n,osl_CLR_n,osl_sclk,oslv_Ss,osl_mosi);
-- cobinatoric process
comb_proc : PROCESS (isl_reset_n,ri,isl_avs_write,islv_avs_address,isl_avs_read,islv_avs_write_data)
VARIABLE vi : t_internal_register;
VARIABLE dacad5668_part_nr: INTEGER := 0;
VARIABLE address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(0,c_analog_output_interface_address_width);
BEGIN
-- keep variables stable
vi := ri;
--standard values
oslv_avs_read_data <= (OTHERS => '0');
vi.global_reset_n := '1';
vi.adc_reset_n := '1';
address := UNSIGNED(islv_avs_address);
--avalon slave interface write part
IF isl_avs_write = '1' THEN
IF address = c_configuration_address THEN
IF islv_avs_byteenable(0) = '1' THEN
vi.global_reset_n := NOT islv_avs_write_data(c_fLink_reset_bit_num);
END IF;
ELSIF address>= c_usig_value_0_address AND address< c_usig_last_address THEN
dacad5668_part_nr := to_integer(UNSIGNED(islv_avs_address) - c_usig_value_0_address);
--only 16 bit are needed cause adc resolution is 16
IF islv_avs_byteenable(0) = '1' THEN
vi.set_values(dacad5668_part_nr)(7 DOWNTO 0) := islv_avs_write_data(7 DOWNTO 0);
END IF;
IF islv_avs_byteenable(1) = '1' THEN
vi.set_values(dacad5668_part_nr)(15 DOWNTO 8) := islv_avs_write_data(15 DOWNTO 8);
END IF;
END IF;
END IF;
--avalon slave interface read part
IF isl_avs_read = '1' THEN
CASE address IS
WHEN c_typdef_address =>
oslv_avs_read_data ((c_fLink_interface_version_length + c_fLink_subtype_length + c_fLink_id_length - 1) DOWNTO
(c_fLink_interface_version_length + c_fLink_subtype_length)) <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_analog_output_id,c_fLink_id_length));
oslv_avs_read_data((c_fLink_interface_version_length + c_fLink_subtype_length - 1) DOWNTO c_fLink_interface_version_length) <= c_dacad5668_subtype_id;
oslv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) <= c_dacad5668_interface_version;
WHEN c_mem_size_address =>
oslv_avs_read_data(c_analog_output_interface_address_width+2) <= '1';
WHEN c_number_of_channels_address =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(NUMBER_OF_CHANNELS,c_fLink_avs_data_width));
WHEN c_unique_id_address =>
oslv_avs_read_data <= UNIQUE_ID;
WHEN c_usig_resolution_address =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(RESOLUTION,c_fLink_avs_data_width));
WHEN OTHERS =>
IF address >= c_usig_value_0_address AND address < c_usig_last_address THEN
dacad5668_part_nr := to_integer(address - c_usig_value_0_address);
oslv_avs_read_data(RESOLUTION-1 DOWNTO 0) <= std_logic_vector(vi.set_values(dacad5668_part_nr));
END IF;
END CASE;
END IF;
IF isl_reset_n = '0' OR vi.global_reset_n = '0' THEN
vi.adc_reset_n := '0';
FOR i IN 0 TO NUMBER_OF_CHANNELS-1 LOOP
vi.set_values(i) := (OTHERS => '0');
END LOOP;
END IF;
--keep variables stable
ri_next <= vi;
END PROCESS comb_proc;
reg_proc : PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_proc;
osl_avs_waitrequest <= '0';
END rtl;
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
PACKAGE avalon_dacad5668_interface_pkg IS
CONSTANT c_analog_output_interface_address_width : INTEGER := 5;
COMPONENT avalon_dacad5668_interface IS
GENERIC (
BASE_CLK: INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 10000000;
INTERNAL_REFERENCE : STD_LOGIC := '0'; -- '0' = set to internal reference, '1' set to external reference
UNIQUE_ID: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0')
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(c_analog_output_interface_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
osl_avs_waitrequest : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC;
osl_LDAC_n : OUT STD_LOGIC;
osl_CLR_n : OUT STD_LOGIC
);
END COMPONENT;
CONSTANT c_dacad5668_subtype_id : STD_LOGIC_VECTOR(c_fLink_subtype_length-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(1,c_fLink_subtype_length));
CONSTANT c_dacad5668_interface_version : STD_LOGIC_VECTOR(c_fLink_interface_version_length-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(0,c_fLink_interface_version_length));
END PACKAGE avalon_dacad5668_interface_pkg;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.avalon_dacad5668_interface_pkg.ALL;
USE work.fLink_definitions.ALL;
USE work.dacad5668_pkg.ALL;
ENTITY avalon_dacad5668_interface IS
GENERIC (
BASE_CLK: INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 10000000;
INTERNAL_REFERENCE : STD_LOGIC := '0'; -- '0' = set to internal reference, '1' set to external reference
UNIQUE_ID: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0')
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(c_analog_output_interface_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
osl_avs_waitrequest : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC;
osl_LDAC_n : OUT STD_LOGIC;
osl_CLR_n : OUT STD_LOGIC
);
CONSTANT c_configuration_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_configuration_address,c_analog_output_interface_address_width);
CONSTANT c_typdef_address : UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_typdef_address,c_analog_output_interface_address_width);
CONSTANT c_mem_size_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_mem_size_address,c_analog_output_interface_address_width);
CONSTANT c_number_of_channels_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_number_of_channels_address,c_analog_output_interface_address_width);
CONSTANT c_unique_id_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_unique_id_address,c_analog_output_interface_address_width);
CONSTANT c_usig_resolution_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_number_of_std_registers,c_analog_output_interface_address_width);
CONSTANT c_usig_value_0_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := c_usig_resolution_address + 1;
CONSTANT c_usig_last_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := c_usig_value_0_address + NUMBER_OF_CHANNELS;
END ENTITY avalon_dacad5668_interface;
ARCHITECTURE rtl OF avalon_dacad5668_interface IS
TYPE t_internal_register IS RECORD
global_reset_n : STD_LOGIC;
adc_reset_n : STD_LOGIC;
set_values : t_value_regs;
END RECORD;
SIGNAL ri,ri_next : t_internal_register;
BEGIN
my_dacad5668 : dacad5668
GENERIC MAP (BASE_CLK,SCLK_FREQUENCY,INTERNAL_REFERENCE)
PORT MAP (isl_clk,ri.adc_reset_n,ri.set_values,osl_LDAC_n,osl_CLR_n,osl_sclk,oslv_Ss,osl_mosi);
-- cobinatoric process
comb_proc : PROCESS (isl_reset_n,ri,isl_avs_write,islv_avs_address,isl_avs_read,islv_avs_write_data)
VARIABLE vi : t_internal_register;
VARIABLE dacad5668_part_nr: INTEGER := 0;
VARIABLE address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(0,c_analog_output_interface_address_width);
BEGIN
-- keep variables stable
vi := ri;
--standard values
oslv_avs_read_data <= (OTHERS => '0');
vi.global_reset_n := '1';
vi.adc_reset_n := '1';
address := UNSIGNED(islv_avs_address);
--avalon slave interface write part
IF isl_avs_write = '1' THEN
IF address = c_configuration_address THEN
IF islv_avs_byteenable(0) = '1' THEN
vi.global_reset_n := NOT islv_avs_write_data(c_fLink_reset_bit_num);
END IF;
ELSIF address>= c_usig_value_0_address AND address< c_usig_last_address THEN
dacad5668_part_nr := to_integer(UNSIGNED(islv_avs_address) - c_usig_value_0_address);
--only 16 bit are needed cause adc resolution is 16
IF islv_avs_byteenable(0) = '1' THEN
vi.set_values(dacad5668_part_nr)(7 DOWNTO 0) := islv_avs_write_data(7 DOWNTO 0);
END IF;
IF islv_avs_byteenable(1) = '1' THEN
vi.set_values(dacad5668_part_nr)(15 DOWNTO 8) := islv_avs_write_data(15 DOWNTO 8);
END IF;
END IF;
END IF;
--avalon slave interface read part
IF isl_avs_read = '1' THEN
CASE address IS
WHEN c_typdef_address =>
oslv_avs_read_data ((c_fLink_interface_version_length + c_fLink_subtype_length + c_fLink_id_length - 1) DOWNTO
(c_fLink_interface_version_length + c_fLink_subtype_length)) <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_analog_output_id,c_fLink_id_length));
oslv_avs_read_data((c_fLink_interface_version_length + c_fLink_subtype_length - 1) DOWNTO c_fLink_interface_version_length) <= c_dacad5668_subtype_id;
oslv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) <= c_dacad5668_interface_version;
WHEN c_mem_size_address =>
oslv_avs_read_data(c_analog_output_interface_address_width+2) <= '1';
WHEN c_number_of_channels_address =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(NUMBER_OF_CHANNELS,c_fLink_avs_data_width));
WHEN c_unique_id_address =>
oslv_avs_read_data <= UNIQUE_ID;
WHEN c_usig_resolution_address =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(RESOLUTION,c_fLink_avs_data_width));
WHEN OTHERS =>
IF address >= c_usig_value_0_address AND address < c_usig_last_address THEN
dacad5668_part_nr := to_integer(address - c_usig_value_0_address);
oslv_avs_read_data(RESOLUTION-1 DOWNTO 0) <= std_logic_vector(vi.set_values(dacad5668_part_nr));
END IF;
END CASE;
END IF;
IF isl_reset_n = '0' OR vi.global_reset_n = '0' THEN
vi.adc_reset_n := '0';
FOR i IN 0 TO NUMBER_OF_CHANNELS-1 LOOP
vi.set_values(i) := (OTHERS => '0');
END LOOP;
END IF;
--keep variables stable
ri_next <= vi;
END PROCESS comb_proc;
reg_proc : PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_proc;
osl_avs_waitrequest <= '0';
END rtl;
|
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is
attribute mark_debug of wr_en : signal is "true";
attribute mark_debug of almost_empty : signal is "true";
attribute mark_debug of full : signal is "true";
begin
end block BLOCK_LABEL;
end architecture RTL;
|
----------------------------------------------------------------------------------
--MIPS Register File Test Bench
--By: Kevin Mottler
--Camel Clarkson 32 Bit MIPS Design Group
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Declares the entity Reg_Depth. This is the 32-bit memory/depth at each address of the register
entity Reg_Depth is
Port (
i_Clk : in std_logic; --Input clock
i_Data : in std_logic_vector(31 downto 0); --Input Data
i_Rst : in std_logic; --Input Reset (Active High)
i_w_en : in std_logic; --Read/Write enable
i_rA_sel : in std_logic; --Select bit for tri state buffer for data A
i_rB_sel : in std_logic; --Select bit for tri state buffer for Data B
o_Data_A : out std_logic_vector(31 downto 0);
o_Data_B : out std_logic_vector(31 downto 0)
);
end Reg_Depth;
architecture structural of Reg_Depth is
--Declares the RFC component
component RFC is
Port (
iClk : in std_logic;
i_Rst : in std_logic;
w_sel : in std_logic;
i_data : in std_logic;
R_sel_A : in std_logic;
R_sel_B : in std_logic;
A : out std_logic;
B : out std_logic
);
end component;
begin
--Instatiates 32 RFCs that control the memory. 32 of them are instatiated because there are 32-bits at each depth
--because they are 1 bit each. 32 bit values are routed to i_data, R_sel_A, and R_sel_B to select which data is outputted,
--or written to.
Inst_RFC31: RFC
port map(
iClk => i_Clk, --Input Clock
i_Rst => i_Rst, --asynchronous reset
w_sel => i_w_en, --Read/Write enable
i_data => i_Data(31),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(31),
B => o_Data_B(31)
);
Inst_RFC30: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(30),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(30),
B => o_Data_B(30)
);
Inst_RFC29: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(29),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(29),
B => o_Data_B(29)
);
Inst_RFC28: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(28),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(28),
B => o_Data_B(28)
);
Inst_RFC27: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(27),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(27),
B => o_Data_B(27)
);
Inst_RFC26: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(26),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(26),
B => o_Data_B(26)
);
Inst_RFC25: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(25),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(25),
B => o_Data_B(25)
);
Inst_RFC24: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(24),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(24),
B => o_Data_B(24)
);
Inst_RFC23: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(23),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(23),
B => o_Data_B(23)
);
Inst_RFC22: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(22),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(22),
B => o_Data_B(22)
);
Inst_RFC21: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(21),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(21),
B => o_Data_B(21)
);
Inst_RFC20: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(20),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(20),
B => o_Data_B(20)
);
Inst_RFC19: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(19),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(19),
B => o_Data_B(19)
);
Inst_RFC18: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(18),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(18),
B => o_Data_B(18)
);
Inst_RFC17: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(17),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(17),
B => o_Data_B(17)
);
Inst_RFC16: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(16),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(16),
B => o_Data_B(16)
);
Inst_RFC15: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(15),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(15),
B => o_Data_B(15)
);
Inst_RFC14: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(14),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(14),
B => o_Data_B(14)
);
Inst_RFC13: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(13),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(13),
B => o_Data_B(13)
);
Inst_RFC12: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(12),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(12),
B => o_Data_B(12)
);
Inst_RFC11: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(11),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(11),
B => o_Data_B(11)
);
Inst_RFC10: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(10),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(10),
B => o_Data_B(10)
);
Inst_RFC9: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(9),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(9),
B => o_Data_B(9)
);
Inst_RFC8: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(8),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(8),
B => o_Data_B(8)
);
Inst_RFC7: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(7),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(7),
B => o_Data_B(7)
);
Inst_RFC6: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(6),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(6),
B => o_Data_B(6)
);
Inst_RFC5: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(5),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(5),
B => o_Data_B(5)
);
Inst_RFC4: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(4),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(4),
B => o_Data_B(4)
);
Inst_RFC3: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(3),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(3),
B => o_Data_B(3)
);
Inst_RFC2: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(2),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(2),
B => o_Data_B(2)
);
Inst_RFC1: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(1),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(1),
B => o_Data_B(1)
);
Inst_RFC0: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(0),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(0),
B => o_Data_B(0)
);
end structural;
|
----------------------------------------------------------------------------------
--MIPS Register File Test Bench
--By: Kevin Mottler
--Camel Clarkson 32 Bit MIPS Design Group
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Declares the entity Reg_Depth. This is the 32-bit memory/depth at each address of the register
entity Reg_Depth is
Port (
i_Clk : in std_logic; --Input clock
i_Data : in std_logic_vector(31 downto 0); --Input Data
i_Rst : in std_logic; --Input Reset (Active High)
i_w_en : in std_logic; --Read/Write enable
i_rA_sel : in std_logic; --Select bit for tri state buffer for data A
i_rB_sel : in std_logic; --Select bit for tri state buffer for Data B
o_Data_A : out std_logic_vector(31 downto 0);
o_Data_B : out std_logic_vector(31 downto 0)
);
end Reg_Depth;
architecture structural of Reg_Depth is
--Declares the RFC component
component RFC is
Port (
iClk : in std_logic;
i_Rst : in std_logic;
w_sel : in std_logic;
i_data : in std_logic;
R_sel_A : in std_logic;
R_sel_B : in std_logic;
A : out std_logic;
B : out std_logic
);
end component;
begin
--Instatiates 32 RFCs that control the memory. 32 of them are instatiated because there are 32-bits at each depth
--because they are 1 bit each. 32 bit values are routed to i_data, R_sel_A, and R_sel_B to select which data is outputted,
--or written to.
Inst_RFC31: RFC
port map(
iClk => i_Clk, --Input Clock
i_Rst => i_Rst, --asynchronous reset
w_sel => i_w_en, --Read/Write enable
i_data => i_Data(31),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(31),
B => o_Data_B(31)
);
Inst_RFC30: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(30),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(30),
B => o_Data_B(30)
);
Inst_RFC29: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(29),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(29),
B => o_Data_B(29)
);
Inst_RFC28: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(28),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(28),
B => o_Data_B(28)
);
Inst_RFC27: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(27),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(27),
B => o_Data_B(27)
);
Inst_RFC26: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(26),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(26),
B => o_Data_B(26)
);
Inst_RFC25: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(25),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(25),
B => o_Data_B(25)
);
Inst_RFC24: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(24),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(24),
B => o_Data_B(24)
);
Inst_RFC23: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(23),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(23),
B => o_Data_B(23)
);
Inst_RFC22: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(22),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(22),
B => o_Data_B(22)
);
Inst_RFC21: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(21),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(21),
B => o_Data_B(21)
);
Inst_RFC20: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(20),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(20),
B => o_Data_B(20)
);
Inst_RFC19: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(19),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(19),
B => o_Data_B(19)
);
Inst_RFC18: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(18),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(18),
B => o_Data_B(18)
);
Inst_RFC17: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(17),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(17),
B => o_Data_B(17)
);
Inst_RFC16: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(16),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(16),
B => o_Data_B(16)
);
Inst_RFC15: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(15),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(15),
B => o_Data_B(15)
);
Inst_RFC14: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(14),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(14),
B => o_Data_B(14)
);
Inst_RFC13: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(13),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(13),
B => o_Data_B(13)
);
Inst_RFC12: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(12),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(12),
B => o_Data_B(12)
);
Inst_RFC11: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(11),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(11),
B => o_Data_B(11)
);
Inst_RFC10: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(10),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(10),
B => o_Data_B(10)
);
Inst_RFC9: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(9),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(9),
B => o_Data_B(9)
);
Inst_RFC8: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(8),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(8),
B => o_Data_B(8)
);
Inst_RFC7: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(7),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(7),
B => o_Data_B(7)
);
Inst_RFC6: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(6),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(6),
B => o_Data_B(6)
);
Inst_RFC5: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(5),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(5),
B => o_Data_B(5)
);
Inst_RFC4: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(4),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(4),
B => o_Data_B(4)
);
Inst_RFC3: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(3),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(3),
B => o_Data_B(3)
);
Inst_RFC2: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(2),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(2),
B => o_Data_B(2)
);
Inst_RFC1: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(1),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(1),
B => o_Data_B(1)
);
Inst_RFC0: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(0),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(0),
B => o_Data_B(0)
);
end structural;
|
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Counter9 is
port( clk : in std_logic;
reset : in std_logic;
up : in std_logic;
down : in std_logic;
count : out std_logic_vector(3 downto 0));
end Counter9;
-- Contador de um algarismo decimal com entrada de clock, reset, up e down
architecture Behavioral of Counter9 is
signal s_count : unsigned (3 downto 0);
begin
process(clk)
begin
if(rising_edge(clk)) then
if(not(s_count(0)='0') and not(s_count(0)='1')) then
s_count <= (others => '0');
elsif(reset='1') then
s_count <= (others => '0');
elsif (up = '1') then
if(s_count = "1001") then
s_count <= (others => '0');
else
s_count <= s_count + 1;
end if;
elsif(down = '1') then
if(s_count = "0000") then
s_count <= "1001";
else
s_count <= s_count - 1;
end if;
else
s_count <= s_count;
end if;
end if;
end process;
count <= std_logic_vector(s_count);
end Behavioral; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2494.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p04n02i02494ent IS
END c07s03b03x00p04n02i02494ent;
ARCHITECTURE c07s03b03x00p04n02i02494arch OF c07s03b03x00p04n02i02494ent IS
BEGIN
TESTING: PROCESS
function check (x : integer) return integer is
begin
return (10 * x);
end;
variable q1: integer := 12;
variable q2: integer ;
BEGIN
q2 := check (q1) + 24 - check (2);
assert NOT( q2 = 124 )
report "***PASSED TEST: c07s03b03x00p04n02i02494"
severity NOTE;
assert ( q2=124 )
report "***FAILED TEST: c07s03b03x00p04n02i02494 - The actual parameter can be specified explicitly by an association element in the association list."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p04n02i02494arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2494.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p04n02i02494ent IS
END c07s03b03x00p04n02i02494ent;
ARCHITECTURE c07s03b03x00p04n02i02494arch OF c07s03b03x00p04n02i02494ent IS
BEGIN
TESTING: PROCESS
function check (x : integer) return integer is
begin
return (10 * x);
end;
variable q1: integer := 12;
variable q2: integer ;
BEGIN
q2 := check (q1) + 24 - check (2);
assert NOT( q2 = 124 )
report "***PASSED TEST: c07s03b03x00p04n02i02494"
severity NOTE;
assert ( q2=124 )
report "***FAILED TEST: c07s03b03x00p04n02i02494 - The actual parameter can be specified explicitly by an association element in the association list."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p04n02i02494arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2494.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p04n02i02494ent IS
END c07s03b03x00p04n02i02494ent;
ARCHITECTURE c07s03b03x00p04n02i02494arch OF c07s03b03x00p04n02i02494ent IS
BEGIN
TESTING: PROCESS
function check (x : integer) return integer is
begin
return (10 * x);
end;
variable q1: integer := 12;
variable q2: integer ;
BEGIN
q2 := check (q1) + 24 - check (2);
assert NOT( q2 = 124 )
report "***PASSED TEST: c07s03b03x00p04n02i02494"
severity NOTE;
assert ( q2=124 )
report "***FAILED TEST: c07s03b03x00p04n02i02494 - The actual parameter can be specified explicitly by an association element in the association list."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p04n02i02494arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity rotKey is
generic(
CNT : integer := 5000 -- 30 ms at 50 MHz
);
port(
clk : in std_logic;
rotA : in std_logic;
rotB : in std_logic;
rotPush : in std_logic;
rotRightEvent : out std_logic;
rotLeftEvent : out std_logic;
rotPushEvent : out std_logic
);
end entity rotKey;
architecture beh of rotKey is
signal rotA_d : std_logic;
signal rotB_d : std_logic;
signal rotA_rise : std_logic;
signal rotB_rise : std_logic;
begin
deb_rotA: entity work.debounce
generic map(
CNT => CNT)
port map(
clk => clk,
input => rotA,
output => rotA_d,
riseedge => rotA_rise,
falledge => open
);
deb_rotB: entity work.debounce
generic map(
CNT => CNT)
port map(
clk => clk,
input => rotB,
output => rotB_d,
riseedge => rotB_rise,
falledge => open
);
deb_rotPush: entity work.debounce
generic map(
CNT => CNT)
port map(
clk => clk,
input => rotPush,
output => open,
riseedge => rotPushEvent,
falledge => open
);
rotRightEvent <= '1' when rotA_rise = '1' and rotB_d = '0' else
'0';
rotLeftEvent <= '1' when rotB_rise = '1' and rotA_d = '0' else
'0';
end architecture beh;
|
entity tb_test2 is
end tb_test2;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_test2 is
signal v : std_logic_vector(1 downto 0);
signal s : std_logic_vector(1 downto 0);
begin
dut: entity work.test2
port map (s, v);
process
begin
s <= "00";
wait for 1 ns;
assert v = "00" severity failure;
s <= "11";
wait for 1 ns;
assert v = "10" severity failure;
wait;
end process;
end behav;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.math_real.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
entity tb_debounce is
end tb_debounce;
architecture behav of tb_debounce is
signal clk : std_logic := '0';
signal io_i : std_logic := '0';
signal io_o : std_logic := '0';
signal noise : std_logic := '0';
signal fixed : std_logic := '0';
signal toggling : std_logic := '0';
signal riseedge : std_logic := '0';
signal falledge: std_logic := '0';
begin
process
begin
clk <= '1', '0' after 10 ns;
wait for 20 ns;
end process;
process
VARIABLE seed1: positive := 1;
VARIABLE seed2: positive := 1;
VARIABLE rand: real;
VARIABLE t_rand: time;
begin
noise <= not noise;
UNIFORM(seed1, seed2, rand);
t_rand := (rand*100.0)*1 ns;
wait for t_rand;
end process;
process
begin
wait for 1400 ns;
toggling <= '1';
wait for 600 ns;
toggling <= '0';
fixed <= '1';
wait for 2000 ns;
toggling <= '1';
fixed <= '0';
wait for 1000 ns;
toggling <= '0';
wait for 3000 ns;
assert false report "done" severity failure;
wait;
end process;
io_i <= noise when toggling = '1' else
fixed;
debounce : entity work.debounce
generic map(
CNT => 15 -- 1500000 = 30 ms at 50 MHz; hier 300ns
)
port map(
clk => clk,
input => io_i,
output => io_o,
riseedge => riseedge,
falledge => falledge
);
end behav;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => W_0,
W_0init => 4e-07
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.3e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net2,
G => vbias2,
S => net6
);
subnet0_subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.8e-06,
W => Wcm_2,
Wcm_2init => 3.5e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net6,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.8e-06,
W => Wcmout_2,
Wcmout_2init => 8e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net7,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m4 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.3e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => vbias2,
S => net7
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.3e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net3,
G => vbias2,
S => net8
);
subnet0_subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.8e-06,
W => Wcm_2,
Wcm_2init => 3.5e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net8,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.8e-06,
W => Wcmout_2,
Wcmout_2init => 8e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net9,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_m4 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.3e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias2,
S => net9
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1e-05,
W => Wcm_1,
Wcm_1init => 7.935e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1e-05,
W => Wcmcout_1,
Wcmcout_1init => 3.735e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 2.6e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 2.6e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.6e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.6e-06
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.6e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.6e-06
)
port map(
D => net10,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net11,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net11,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net11,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
|
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- lfsr_serial.vhd : LFSR based serial output pseudorandom generator module
-- Copyright (C) 2009 CESNET
-- Author(s): Pavol Korcek <korcek@liberouter.org>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: lfsr_serial.vhd 12095 2009-11-24 15:12:11Z kastovsky $
--
library ieee;
use ieee.std_logic_1164.all;
use work.lfsr_pkg.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity lfsr_serial is
generic (
LFSR_LENGTH : integer := 16; -- internal LFSR width
TAPS : LFSR_TAPS :=(16,15,13,4) -- polynomial
);
port (
CLK : in std_logic; -- clock signal
S_EN : in std_logic; -- shift enable
F_EN : in std_logic; -- fill enable
DIN : in std_logic_vector(LFSR_LENGTH-1 downto 0); -- seed
DOUT : out std_logic -- data out
);
end entity lfsr_serial;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture beh of lfsr_serial is
signal reg : std_logic_vector((LFSR_LENGTH-1) downto 0);
begin
lfsr1 : process (CLK)
variable fb : std_logic;
begin
if (CLK'event and CLK ='1') then
-- rising edge
if S_EN='1' then
-- shift enable
-- compute new bit (xor)
fb := '0';
for j in TAPS'range loop
if fb=reg(TAPS(j)-1) then
fb := '0';
else
fb := '1';
end if;
end loop; -- j
for k in reg'left downto 1 loop
reg(k) <= reg(k-1);
end loop; -- k
reg(0) <= fb;
elsif F_EN ='1' then
-- for insert seed
reg <= DIN;
end if;
DOUT <= reg(LFSR_LENGTH-1);
end if;
end process lfsr1;
end architecture beh;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity kirkman_hot is
port(
clock: in std_logic;
input: in std_logic_vector(11 downto 0);
output: out std_logic_vector(5 downto 0)
);
end kirkman_hot;
architecture behaviour of kirkman_hot is
constant rst0: std_logic_vector(15 downto 0) := "1000000000000000";
constant bit1: std_logic_vector(15 downto 0) := "0100000000000000";
constant bit2: std_logic_vector(15 downto 0) := "0010000000000000";
constant bit3: std_logic_vector(15 downto 0) := "0001000000000000";
constant bit4: std_logic_vector(15 downto 0) := "0000100000000000";
constant bit5: std_logic_vector(15 downto 0) := "0000010000000000";
constant bit6: std_logic_vector(15 downto 0) := "0000001000000000";
constant bit7: std_logic_vector(15 downto 0) := "0000000100000000";
constant bit8: std_logic_vector(15 downto 0) := "0000000010000000";
constant bit9: std_logic_vector(15 downto 0) := "0000000001000000";
constant bitA: std_logic_vector(15 downto 0) := "0000000000100000";
constant bitB: std_logic_vector(15 downto 0) := "0000000000010000";
constant bitC: std_logic_vector(15 downto 0) := "0000000000001000";
constant bitD: std_logic_vector(15 downto 0) := "0000000000000100";
constant bitE: std_logic_vector(15 downto 0) := "0000000000000010";
constant bitF: std_logic_vector(15 downto 0) := "0000000000000001";
signal current_state, next_state: std_logic_vector(15 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----------------"; output <= "------";
if std_match(input, "--------1---") then next_state <= rst0; output <= "1-----";
else
case current_state is
when rst0 =>
if std_match(input, "--------0000") then next_state <= rst0; output <= "0----0";
elsif std_match(input, "--------0001") then next_state <= bit1; output <= "0---00";
elsif std_match(input, "-----0--0111") then next_state <= bit1; output <= "0--010";
elsif std_match(input, "-----1--0111") then next_state <= bit1; output <= "0--110";
elsif std_match(input, "--------0010") then next_state <= bit1; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bit1; output <= "0---00";
end if;
when bit1 =>
if std_match(input, "--------0001") then next_state <= bit2; output <= "0---10";
elsif std_match(input, "-----0--0111") then next_state <= bit2; output <= "0--010";
elsif std_match(input, "-----1--0111") then next_state <= bit2; output <= "0--110";
elsif std_match(input, "--------0010") then next_state <= bit2; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bit2; output <= "0---00";
end if;
when bit2 =>
if std_match(input, "--------0001") then next_state <= bit3; output <= "0---00";
elsif std_match(input, "-----0--0111") then next_state <= bit3; output <= "0--000";
elsif std_match(input, "-----1--0111") then next_state <= bit3; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bit3; output <= "0---10";
elsif std_match(input, "--------0100") then next_state <= bit3; output <= "0---10";
end if;
when bit3 =>
if std_match(input, "0-------0001") then next_state <= bit4; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit4; output <= "1---10";
elsif std_match(input, "-00--00-0111") then next_state <= bit4; output <= "100000";
elsif std_match(input, "-01--00-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-10--00-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-11--00-0111") then next_state <= bit4; output <= "110000";
elsif std_match(input, "-00--01-0111") then next_state <= bit4; output <= "101000";
elsif std_match(input, "-01--01-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-10--01-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-11--01-0111") then next_state <= bit4; output <= "111000";
elsif std_match(input, "-----10-0111") then next_state <= bit4; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit4; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit4; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit4; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit4; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit4; output <= "1---10";
end if;
when bit4 =>
if std_match(input, "0-------0001") then next_state <= bit5; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit5; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit5; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit5; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit5; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit5; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit5; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit5; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit5; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit5; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit5; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit5; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit5; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit5; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit5; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit5; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit5; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit5; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit5; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit5; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit5; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit5; output <= "1---10";
end if;
when bit5 =>
if std_match(input, "0-------0001") then next_state <= bit6; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit6; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit6; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit6; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit6; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit6; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit6; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit6; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit6; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit6; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit6; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit6; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit6; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit6; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit6; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit6; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit6; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit6; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit6; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit6; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit6; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit6; output <= "1---10";
end if;
when bit6 =>
if std_match(input, "0-------0001") then next_state <= bit7; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit7; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit7; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit7; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit7; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit7; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit7; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit7; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit7; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit7; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit7; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit7; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit7; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit7; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit7; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit7; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit7; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit7; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit7; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit7; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit7; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit7; output <= "1---10";
end if;
when bit7 =>
if std_match(input, "0-------0001") then next_state <= bit8; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit8; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit8; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit8; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit8; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit8; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit8; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit8; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit8; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit8; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit8; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit8; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit8; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit8; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit8; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit8; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit8; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit8; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit8; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit8; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit8; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit8; output <= "1---10";
end if;
when bit8 =>
if std_match(input, "0-------0001") then next_state <= bit9; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit9; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit9; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit9; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit9; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit9; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit9; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit9; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit9; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit9; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit9; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit9; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit9; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit9; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit9; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit9; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit9; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit9; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit9; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit9; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit9; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit9; output <= "1---10";
end if;
when bit9 =>
if std_match(input, "0-------0001") then next_state <= bitA; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bitA; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bitA; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bitA; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bitA; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bitA; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bitA; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bitA; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bitA; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bitA; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bitA; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bitA; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bitA; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bitA; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bitA; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bitA; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bitA; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bitA; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bitA; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bitA; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bitA; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bitA; output <= "1---10";
end if;
when bitA =>
if std_match(input, "0-------0001") then next_state <= bitB; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bitB; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bitB; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bitB; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bitB; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bitB; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bitB; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bitB; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bitB; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bitB; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bitB; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bitB; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bitB; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bitB; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bitB; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bitB; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bitB; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bitB; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bitB; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bitB; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bitB; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bitB; output <= "1---10";
end if;
when bitB =>
if std_match(input, "--------0001") then next_state <= bitC; output <= "0---00";
elsif std_match(input, "--0000--0111") then next_state <= bitC; output <= "000000";
elsif std_match(input, "--0100--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1000--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1100--0111") then next_state <= bitC; output <= "010000";
elsif std_match(input, "--0010--0111") then next_state <= bitC; output <= "001000";
elsif std_match(input, "--0110--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1010--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1110--0111") then next_state <= bitC; output <= "011000";
elsif std_match(input, "-----1--0111") then next_state <= bitC; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bitC; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bitC; output <= "0---00";
end if;
when bitC =>
if std_match(input, "--------0001") then next_state <= bitD; output <= "0---00";
elsif std_match(input, "--0000--0111") then next_state <= bitD; output <= "000000";
elsif std_match(input, "--0100--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1000--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1100--0111") then next_state <= bitD; output <= "010000";
elsif std_match(input, "--0010--0111") then next_state <= bitD; output <= "001000";
elsif std_match(input, "--0110--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1010--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1110--0111") then next_state <= bitD; output <= "011000";
elsif std_match(input, "-----1--0111") then next_state <= bitD; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bitD; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bitD; output <= "0---00";
end if;
when bitD =>
if std_match(input, "--------0001") then next_state <= bitE; output <= "0---00";
elsif std_match(input, "--0000--0111") then next_state <= bitE; output <= "000000";
elsif std_match(input, "--0100--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1000--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1100--0111") then next_state <= bitE; output <= "010000";
elsif std_match(input, "--0010--0111") then next_state <= bitE; output <= "001000";
elsif std_match(input, "--0110--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1010--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1110--0111") then next_state <= bitE; output <= "011000";
elsif std_match(input, "-----1--0111") then next_state <= bitE; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bitE; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bitE; output <= "0---00";
end if;
when bitE =>
if std_match(input, "--------0001") then next_state <= bitF; output <= "0---01";
elsif std_match(input, "--0000--0111") then next_state <= bitF; output <= "000001";
elsif std_match(input, "--0100--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1000--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1100--0111") then next_state <= bitF; output <= "010001";
elsif std_match(input, "--0010--0111") then next_state <= bitF; output <= "001100";
elsif std_match(input, "--0110--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1010--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1110--0111") then next_state <= bitF; output <= "011001";
elsif std_match(input, "-----1--0111") then next_state <= bitF; output <= "0--001";
elsif std_match(input, "--------0010") then next_state <= bitF; output <= "0---01";
elsif std_match(input, "--------0100") then next_state <= bitF; output <= "0---01";
end if;
when bitF =>
if std_match(input, "--------0001") then next_state <= rst0; output <= "0---00";
elsif std_match(input, "---0-0--0111") then next_state <= rst0; output <= "0--000";
elsif std_match(input, "---1-0--0111") then next_state <= rst0; output <= "0--010";
elsif std_match(input, "-----1--0111") then next_state <= rst0; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= rst0; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= rst0; output <= "0---00";
end if;
when others => next_state <= "----------------"; output <= "------";
end case;
end if;
end process;
end behaviour;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_05 is
end entity inline_05;
----------------------------------------------------------------
architecture test of inline_05 is
type stimulus_list is array (natural range <>) of integer;
-- code from book:
function "&" ( a, b : stimulus_list ) return stimulus_list;
attribute debug : string;
attribute debug of
"&" [ stimulus_list, stimulus_list return stimulus_list ] : function is
"source_statement_step";
type mvl is ('X', '0', '1', 'Z');
type mvl_vector is array ( integer range <>) of mvl;
function resolve_mvl ( drivers : mvl_vector ) return mvl;
subtype resolved_mvl is resolve_mvl mvl;
type builtin_types is (builtin_bit, builtin_mvl, builtin_integer);
attribute builtin : builtin_types;
attribute builtin of resolved_mvl : subtype is builtin_mvl;
-- end of code from book
function "&" ( a, b : stimulus_list ) return stimulus_list is
begin
return stimulus_list'(1 to 0 => 0);
end function "&";
function resolve_mvl ( drivers : mvl_vector ) return mvl is
begin
return drivers(drivers'left);
end function resolve_mvl;
begin
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_05 is
end entity inline_05;
----------------------------------------------------------------
architecture test of inline_05 is
type stimulus_list is array (natural range <>) of integer;
-- code from book:
function "&" ( a, b : stimulus_list ) return stimulus_list;
attribute debug : string;
attribute debug of
"&" [ stimulus_list, stimulus_list return stimulus_list ] : function is
"source_statement_step";
type mvl is ('X', '0', '1', 'Z');
type mvl_vector is array ( integer range <>) of mvl;
function resolve_mvl ( drivers : mvl_vector ) return mvl;
subtype resolved_mvl is resolve_mvl mvl;
type builtin_types is (builtin_bit, builtin_mvl, builtin_integer);
attribute builtin : builtin_types;
attribute builtin of resolved_mvl : subtype is builtin_mvl;
-- end of code from book
function "&" ( a, b : stimulus_list ) return stimulus_list is
begin
return stimulus_list'(1 to 0 => 0);
end function "&";
function resolve_mvl ( drivers : mvl_vector ) return mvl is
begin
return drivers(drivers'left);
end function resolve_mvl;
begin
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_05 is
end entity inline_05;
----------------------------------------------------------------
architecture test of inline_05 is
type stimulus_list is array (natural range <>) of integer;
-- code from book:
function "&" ( a, b : stimulus_list ) return stimulus_list;
attribute debug : string;
attribute debug of
"&" [ stimulus_list, stimulus_list return stimulus_list ] : function is
"source_statement_step";
type mvl is ('X', '0', '1', 'Z');
type mvl_vector is array ( integer range <>) of mvl;
function resolve_mvl ( drivers : mvl_vector ) return mvl;
subtype resolved_mvl is resolve_mvl mvl;
type builtin_types is (builtin_bit, builtin_mvl, builtin_integer);
attribute builtin : builtin_types;
attribute builtin of resolved_mvl : subtype is builtin_mvl;
-- end of code from book
function "&" ( a, b : stimulus_list ) return stimulus_list is
begin
return stimulus_list'(1 to 0 => 0);
end function "&";
function resolve_mvl ( drivers : mvl_vector ) return mvl is
begin
return drivers(drivers'left);
end function resolve_mvl;
begin
end architecture test;
|
-- pseudo random bit sequence with 31-bit register
-- CLK: max speed given by 2 random bits each clock cycle
-- RESET: reset the internal register all to 1
-- SPEED: the speed of the output
-- "11" output each clock cycle two random bits on Y
-- "10" output each clock cycle the same random bit on Y
-- "01" output every second clock cycle the same random bit on Y
-- "00" output every fourth clock cycle the same random bit on Y
-------------------------------------------------------------------
entity PRBS31 is
port (CLK: in bit;
RESET: in bit;
EN: in bit;
SPEED: in bit_vector(1 downto 0);
Y: out bit_vector(1 downto 0));
end PRBS31;
entity DIVIDER_FSM is
port (CLK: in bit;
SPEED: in bit_vector(1 downto 0);
Y: out bit);
end DIVIDER_FSM;
architecture PRBS31_ARCH of PRBS31 is
signal CIN: bit; -- Internal FF enable signal for Shift register
component DIVIDER_FSM is port(CLK: in bit; SPEED: in bit_vector(1 downto 0); Y: out bit); end component;
begin
-- CLOCK DIVIDER FSM
I0: DIVIDER_FSM port map(CLK,SPEED,CIN);
process(CLK,RESET)
variable REG: bit_vector(30 downto 0) := (others => '1');
begin
if RESET='1' then
REG := (others => '1');
elsif CLK'event and CLK='1' then
if EN='0' then
REG := (others => '1');
elsif CIN='1' then
if SPEED="11" then
REG := REG(28 downto 0) & (REG(30) xor REG(27)) & (REG(29) xor REG(26));
else
REG := REG(29 downto 0) & (REG(30) xor REG(27));
end if;
end if;
end if;
case SPEED is
when "11" => Y <= REG(30 downto 29);
when others => Y <= REG(30) & REG(30);
end case;
end process;
end PRBS31_ARCH;
architecture DIVIDER_FSM_ARCH of DIVIDER_FSM is
begin
FSM: process(CLK)
variable STATE: bit_vector(1 downto 0) := (others => '0');
variable DECISION: bit_vector(3 downto 0);
begin
-- change state
if CLK'event and CLK='1' then
DECISION := STATE & SPEED;
case DECISION is
when "1100" => STATE := "00";
when "0000" | "1101" => STATE := "01";
when "0001" | "0100" => STATE := "10";
when others => STATE := "11";
end case;
end if;
-- output depending on state
case STATE is
when "11" => Y <= '1';
when others => Y <= '0';
end case;
end process FSM;
end DIVIDER_FSM_ARCH;
|
-- pseudo random bit sequence with 31-bit register
-- CLK: max speed given by 2 random bits each clock cycle
-- RESET: reset the internal register all to 1
-- SPEED: the speed of the output
-- "11" output each clock cycle two random bits on Y
-- "10" output each clock cycle the same random bit on Y
-- "01" output every second clock cycle the same random bit on Y
-- "00" output every fourth clock cycle the same random bit on Y
-------------------------------------------------------------------
entity PRBS31 is
port (CLK: in bit;
RESET: in bit;
EN: in bit;
SPEED: in bit_vector(1 downto 0);
Y: out bit_vector(1 downto 0));
end PRBS31;
entity DIVIDER_FSM is
port (CLK: in bit;
SPEED: in bit_vector(1 downto 0);
Y: out bit);
end DIVIDER_FSM;
architecture PRBS31_ARCH of PRBS31 is
signal CIN: bit; -- Internal FF enable signal for Shift register
component DIVIDER_FSM is port(CLK: in bit; SPEED: in bit_vector(1 downto 0); Y: out bit); end component;
begin
-- CLOCK DIVIDER FSM
I0: DIVIDER_FSM port map(CLK,SPEED,CIN);
process(CLK,RESET)
variable REG: bit_vector(30 downto 0) := (others => '1');
begin
if RESET='1' then
REG := (others => '1');
elsif CLK'event and CLK='1' then
if EN='0' then
REG := (others => '1');
elsif CIN='1' then
if SPEED="11" then
REG := REG(28 downto 0) & (REG(30) xor REG(27)) & (REG(29) xor REG(26));
else
REG := REG(29 downto 0) & (REG(30) xor REG(27));
end if;
end if;
end if;
case SPEED is
when "11" => Y <= REG(30 downto 29);
when others => Y <= REG(30) & REG(30);
end case;
end process;
end PRBS31_ARCH;
architecture DIVIDER_FSM_ARCH of DIVIDER_FSM is
begin
FSM: process(CLK)
variable STATE: bit_vector(1 downto 0) := (others => '0');
variable DECISION: bit_vector(3 downto 0);
begin
-- change state
if CLK'event and CLK='1' then
DECISION := STATE & SPEED;
case DECISION is
when "1100" => STATE := "00";
when "0000" | "1101" => STATE := "01";
when "0001" | "0100" => STATE := "10";
when others => STATE := "11";
end case;
end if;
-- output depending on state
case STATE is
when "11" => Y <= '1';
when others => Y <= '0';
end case;
end process FSM;
end DIVIDER_FSM_ARCH;
|
-- pseudo random bit sequence with 31-bit register
-- CLK: max speed given by 2 random bits each clock cycle
-- RESET: reset the internal register all to 1
-- SPEED: the speed of the output
-- "11" output each clock cycle two random bits on Y
-- "10" output each clock cycle the same random bit on Y
-- "01" output every second clock cycle the same random bit on Y
-- "00" output every fourth clock cycle the same random bit on Y
-------------------------------------------------------------------
entity PRBS31 is
port (CLK: in bit;
RESET: in bit;
EN: in bit;
SPEED: in bit_vector(1 downto 0);
Y: out bit_vector(1 downto 0));
end PRBS31;
entity DIVIDER_FSM is
port (CLK: in bit;
SPEED: in bit_vector(1 downto 0);
Y: out bit);
end DIVIDER_FSM;
architecture PRBS31_ARCH of PRBS31 is
signal CIN: bit; -- Internal FF enable signal for Shift register
component DIVIDER_FSM is port(CLK: in bit; SPEED: in bit_vector(1 downto 0); Y: out bit); end component;
begin
-- CLOCK DIVIDER FSM
I0: DIVIDER_FSM port map(CLK,SPEED,CIN);
process(CLK,RESET)
variable REG: bit_vector(30 downto 0) := (others => '1');
begin
if RESET='1' then
REG := (others => '1');
elsif CLK'event and CLK='1' then
if EN='0' then
REG := (others => '1');
elsif CIN='1' then
if SPEED="11" then
REG := REG(28 downto 0) & (REG(30) xor REG(27)) & (REG(29) xor REG(26));
else
REG := REG(29 downto 0) & (REG(30) xor REG(27));
end if;
end if;
end if;
case SPEED is
when "11" => Y <= REG(30 downto 29);
when others => Y <= REG(30) & REG(30);
end case;
end process;
end PRBS31_ARCH;
architecture DIVIDER_FSM_ARCH of DIVIDER_FSM is
begin
FSM: process(CLK)
variable STATE: bit_vector(1 downto 0) := (others => '0');
variable DECISION: bit_vector(3 downto 0);
begin
-- change state
if CLK'event and CLK='1' then
DECISION := STATE & SPEED;
case DECISION is
when "1100" => STATE := "00";
when "0000" | "1101" => STATE := "01";
when "0001" | "0100" => STATE := "10";
when others => STATE := "11";
end case;
end if;
-- output depending on state
case STATE is
when "11" => Y <= '1';
when others => Y <= '0';
end case;
end process FSM;
end DIVIDER_FSM_ARCH;
|
-- Copyright (c) 2016 Federico Madotto and Coline Doebelin
-- federico.madotto (at) gmail.com
-- coline.doebelin (at) gmail.com
-- https://github.com/fmadotto/DS_bitcoin_miner
-- fsm_tb.vhd is part of DS_bitcoin_miner.
-- DS_bitcoin_miner is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- DS_bitcoin_miner is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all; -- std_logic
use ieee.std_logic_arith.all; -- signed/unsigned, conv_integer(), conv_std_logic_vector(signal, no. bit)
use ieee.numeric_std.all; -- to_integer()
entity fsm_tb is
end entity fsm_tb;
architecture behav of fsm_tb is
signal s_clk : std_ulogic;
signal s_rstn : std_ulogic;
signal s_start : std_ulogic;
signal s_exp_sel1 : std_ulogic;
signal s_com_sel1 : std_ulogic;
signal s_M_j_memory_rcs_n : std_ulogic;
signal s_M_j_memory_r_addr : std_ulogic_vector(3 downto 0);
signal s_reg_H_minus_1_en : std_ulogic;
signal s_reg_H_minus_1_sel : std_ulogic;
signal s_K_j_init : std_ulogic;
signal s_done : std_ulogic;
begin
-- Instantiate the Unit Under Test (UUT)
UUT : entity work.fsm
port map (
clk => s_clk,
rstn => s_rstn,
start => s_start,
exp_sel1 => s_exp_sel1,
com_sel1 => s_com_sel1,
M_j_memory_rcs_n => s_M_j_memory_rcs_n,
M_j_memory_r_addr => s_M_j_memory_r_addr,
reg_H_minus_1_en => s_reg_H_minus_1_en,
reg_H_minus_1_sel => s_reg_H_minus_1_sel,
K_j_init => s_K_j_init,
done => s_done
);
-- s_clk signal generation
s_clk_proc : process
begin
s_clk <= '1',
'0' after 10 ns; --50MHz
wait for 20 ns;
end process;
-- s_rstn signal generation
s_rstn_proc : process
begin
s_rstn <= '0',
'1' after 25 ns;
wait;
end process;
-- s_start signal generation
s_start_proc : process
begin
s_start <= '0',
'1' after 42 ns,
'0' after 62 ns;
wait;
end process;
end architecture behav;
|
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_n_data_ddr_s8_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: D-bit generic 1:n data receiver module with differential inputs for DDR systems
-- Takes in 1 bit of differential data and deserialises this to n bits
-- data is received LSB first
-- Serial input words
-- Line0 : 0, ...... DS-(S+1)
-- Line1 : 1, ...... DS-(S+2)
-- Line(D-1) : . .
-- Line(D) : D-1, ...... DS
-- Parallel output word
-- DS, DS-1 ..... 1, 0
--
-- Includes state machine to control calibration only
-- Data inversion can be accomplished via the RX_RX_SWAP_MASK parameter if required
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_1_to_n_data_ddr_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16 ; -- Set the number of inputs and outputs
DIFF_TERM : boolean := FALSE) ; -- Enable or disable internal differential termination
port (
use_phase_detector : in std_logic ; -- '1' enables the phase detector logic if USE_PD = TRUE
datain_p : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
datain_n : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
rxioclkp : in std_logic ; -- IO Clock network
rxioclkn : in std_logic ; -- IO Clock network
rxserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset line
gclk : in std_logic ; -- Global clock
bitslip : in std_logic ; -- Bitslip control line
data_out : out std_logic_vector((D*S)-1 downto 0) ; -- Output data
debug_in : in std_logic_vector(1 downto 0) ; -- Debug Inputs, set to '0' if not required
debug : out std_logic_vector((2*D)+6 downto 0)) ; -- Debug output bus, 2D+6 = 2 lines per input (from mux and ce) + 7, leave nc if debug not required
end serdes_1_to_n_data_ddr_s8_diff ;
architecture arch_serdes_1_to_n_data_ddr_s8_diff of serdes_1_to_n_data_ddr_s8_diff is
signal ddly_m : std_logic_vector(D-1 downto 0) ; -- Master output from IODELAY1
signal ddly_s : std_logic_vector(D-1 downto 0) ; -- Slave output from IODELAY1
signal mdataout : std_logic_vector((8*D)-1 downto 0) ;
signal cascade : std_logic_vector(D-1 downto 0) ;
signal pd_edge : std_logic_vector(D-1 downto 0) ;
signal busys : std_logic_vector(D-1 downto 0) ;
signal busym : std_logic_vector(D-1 downto 0) ;
signal rx_data_in : std_logic_vector(D-1 downto 0) ;
signal rx_data_in_fix : std_logic_vector(D-1 downto 0) ;
signal state : integer range 0 to 8 ;
signal busy_data_d : std_logic ;
signal busy_data : std_logic_vector(D-1 downto 0) ;
signal inc_data : std_logic ;
signal ce_data : std_logic_vector(D-1 downto 0) ;
signal incdec_data_d : std_logic ;
signal valid_data_d : std_logic ;
signal counter : std_logic_vector(8 downto 0) ;
signal enable : std_logic ;
signal cal_data_master : std_logic ;
signal rst_data : std_logic ;
signal pdcounter : std_logic_vector(4 downto 0) ;
signal ce_data_int : std_logic_vector(D-1 downto 0) ;
signal inc_data_int : std_logic ;
signal incdec_data : std_logic_vector(D-1 downto 0) ;
signal cal_data_slave : std_logic ;
signal valid_data : std_logic_vector(D-1 downto 0) ;
signal mux : std_logic_vector(D-1 downto 0) ;
signal ce_data_inta : std_logic ;
signal flag : std_logic ;
signal cal_data_sint : std_logic ;
signal incdec_data_or : std_logic_vector(D downto 0) ;
signal incdec_data_im : std_logic_vector(D-1 downto 0) ;
signal valid_data_or : std_logic_vector(D downto 0) ;
signal valid_data_im : std_logic_vector(D-1 downto 0) ;
signal busy_data_or : std_logic_vector(D downto 0) ;
signal all_ce : std_logic_vector(D-1 downto 0) ;
constant RX_SWAP_MASK : std_logic_vector(D-1 downto 0) := (others => '0') ; -- pinswap mask for input bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
begin
cal_data_slave <= cal_data_sint ;
debug <= mux & cal_data_master & rst_data & cal_data_slave & busy_data_d & inc_data & ce_data & valid_data_d & incdec_data_d ;
process (gclk, reset)
begin
if reset = '1' then
state <= 0 ;
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
counter <= (others => '0') ;
enable <= '0' ;
counter <= (others => '0') ;
mux <= (0 => '1', others => '0') ;
elsif gclk'event and gclk = '1' then
counter <= counter + 1 ;
if counter(8) = '1' then
counter <= "000000000" ;
end if ;
if counter(5) = '1' then
enable <= '1' ;
end if ;
if state = 0 and enable = '1' then -- Wait for all IODELAYs to be available
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
rst_data <= '0' ;
if busy_data_d = '0' then
state <= 1 ;
end if ;
elsif state = 1 then -- Issue calibrate command to both master and slave
cal_data_master <= '1' ;
cal_data_sint <= '1' ;
if busy_data_d = '1' then -- and wait for command to be accepted
state <= 2 ;
end if ;
elsif state = 2 then -- Now RST all master and slave IODELAYs
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
if busy_data_d = '0' then
rst_data <= '1' ;
state <= 3 ;
end if ;
elsif state = 3 then -- Wait for all IODELAYs to be available
rst_data <= '0' ;
if busy_data_d = '0' then
state <= 4 ;
end if ;
elsif state = 4 then -- Hang around
if counter(8) = '1' then
state <= 5 ;
end if ;
elsif state = 5 then -- Calibrate slave only
if busy_data_d = '0' then
cal_data_sint <= '1' ;
state <= 6 ;
if D /= 1 then
mux <= mux(D-2 downto 0) & mux(D-1) ;
end if ;
end if ;
elsif state = 6 then -- Wait for command to be accepted
if busy_data_d = '1' then
cal_data_sint <= '0' ;
state <= 7 ;
end if ;
elsif state = 7 then -- Wait for all IODELAYs to be available, ie CAL command finished
cal_data_sint <= '0' ;
if busy_data_d = '0' then
state <= 4 ;
end if ;
end if ;
end if ;
end process ;
process (gclk, reset)
begin
if reset = '1' then
pdcounter <= "10000" ;
ce_data_inta <= '0' ;
flag <= '0' ;
elsif gclk'event and gclk = '1' then
busy_data_d <= busy_data_or(D) ;
if use_phase_detector = '1' then -- decide whther pd is used
incdec_data_d <= incdec_data_or(D) ;
valid_data_d <= valid_data_or(D) ;
if ce_data_inta = '1' then
ce_data <= mux ;
else
ce_data <= (others => '0') ;
end if ;
if state = 7 then
flag <= '0' ;
elsif state /= 4 or busy_data_d = '1' then -- Reset filter if state machine issues a cal command or unit is busy
pdcounter <= "10000" ;
ce_data_inta <= '0' ;
elsif pdcounter = "11111" and flag = '0' then -- Filter has reached positive max - increment the tap count
ce_data_inta <= '1' ;
inc_data_int <= '1' ;
pdcounter <= "10000" ;
flag <= '0' ;
elsif pdcounter = "00000" and flag = '0' then -- Filter has reached negative max - decrement the tap count
ce_data_inta <= '1' ;
inc_data_int <= '0' ;
pdcounter <= "10000" ;
flag <= '0' ;
elsif valid_data_d = '1' then -- increment filter
ce_data_inta <= '0' ;
if incdec_data_d = '1' and pdcounter /= "11111" then
pdcounter <= pdcounter + 1 ;
elsif incdec_data_d = '0' and pdcounter /= "00000" then -- decrement filter
pdcounter <= pdcounter - 1 ;
end if ;
else
ce_data_inta <= '0' ;
end if ;
else
ce_data <= all_ce ;
inc_data_int <= debug_in(1) ;
end if ;
end if ;
end process ;
inc_data <= inc_data_int ;
incdec_data_or(0) <= '0' ; -- Input Mux - Initialise generate loop OR gates
valid_data_or(0) <= '0' ;
busy_data_or(0) <= '0' ;
loop0 : for i in 0 to (D - 1) generate
busy_data(i) <= busys(i) ;
incdec_data_im(i) <= incdec_data(i) and mux(i) ; -- Input muxes
incdec_data_or(i+1) <= incdec_data_im(i) or incdec_data_or(i) ; -- AND gates to allow just one signal through at a tome
valid_data_im(i) <= valid_data(i) and mux(i) ; -- followed by an OR
valid_data_or(i+1) <= valid_data_im(i) or valid_data_or(i) ; -- for the three inputs from each PD
busy_data_or(i+1) <= busy_data(i) or busy_data_or(i) ; -- The busy signals just need an OR gate
all_ce(i) <= debug_in(0) ;
rx_data_in_fix(i) <= rx_data_in(i) xor RX_SWAP_MASK(i) ; -- Invert signals as required
iob_clk_in : IBUFGDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => datain_p(i),
IB => datain_n(i),
O => rx_data_in(i));
iodelay_m : IODELAY2 generic map(
DATA_RATE => "DDR", -- <SDR>, DDR
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL" , -- NORMAL, PCI
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_TYPE => "DIFF_PHASE_DETECTOR",-- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "WRAPAROUND", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN", -- "IO", "IDATAIN", "ODATAIN"
SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
SIM_TAPDELAY_VALUE => 49) --
port map (
IDATAIN => rx_data_in_fix(i), -- data from primary IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m(i), -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclkp, -- High speed clock for calibration
IOCLK1 => rxioclkn, -- High speed clock for calibration
CLK => gclk, -- Fabric clock (GCLK) for control signals
CAL => cal_data_master, -- Calibrate control signal
INC => inc_data, -- Increment counter
CE => ce_data(i), -- Clock Enable
RST => rst_data, -- Reset delay line
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
iodelay_s : IODELAY2 generic map(
DATA_RATE => "DDR", -- <SDR>, DDR
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL" , -- NORMAL, PCI
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_TYPE => "DIFF_PHASE_DETECTOR",-- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "WRAPAROUND", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN", -- "IO", "IDATAIN", "ODATAIN"
SERDES_MODE => "SLAVE", -- <NONE>, MASTER, SLAVE
SIM_TAPDELAY_VALUE => 49) --
port map (
IDATAIN => rx_data_in_fix(i), -- data from primary IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_s(i), -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclkp, -- High speed clock for calibration
IOCLK1 => rxioclkn, -- High speed clock for calibration
CLK => gclk, -- Fabric clock (GCLK) for control signals
CAL => cal_data_slave, -- Calibrate control signal
INC => inc_data, -- Increment counter
CE => ce_data(i), -- Clock Enable
RST => rst_data, -- Reset delay line
BUSY => busys(i)) ; -- output signal indicating sync circuit has finished / calibration has finished
iserdes_m : ISERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "DDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_m(i),
CE0 => '1',
CLK0 => rxioclkp,
CLK1 => rxioclkn,
IOCE => rxserdesstrobe,
RST => reset,
CLKDIV => gclk,
SHIFTIN => pd_edge(i),
BITSLIP => bitslip,
FABRICOUT => open,
Q4 => mdataout((8*i)+7),
Q3 => mdataout((8*i)+6),
Q2 => mdataout((8*i)+5),
Q1 => mdataout((8*i)+4),
DFB => open, -- are these the same as above? These were in Johns design
CFB0 => open,
CFB1 => open,
VALID => valid_data(i),
INCDEC => incdec_data(i),
SHIFTOUT => cascade(i));
iserdes_s : ISERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "DDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_s(i),
CE0 => '1',
CLK0 => rxioclkp,
CLK1 => rxioclkn,
IOCE => rxserdesstrobe,
RST => reset,
CLKDIV => gclk,
SHIFTIN => cascade(i),
BITSLIP => bitslip,
FABRICOUT => open,
Q4 => mdataout((8*i)+3),
Q3 => mdataout((8*i)+2),
Q2 => mdataout((8*i)+1),
Q1 => mdataout((8*i)+0),
DFB => open, -- are these the same as above? These were in Johns design
CFB0 => open,
CFB1 => open,
VALID => open,
INCDEC => open,
SHIFTOUT => pd_edge(i));
loop1 : for j in 7 downto (8-S) generate
data_out(((D*(j+S-8))+i)) <= mdataout((8*i)+j) ;
end generate ;
end generate ;
end arch_serdes_1_to_n_data_ddr_s8_diff ;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity datapath_averager is
Port ( mem_addr : in STD_LOGIC_VECTOR(5 downto 0);
window_val : in STD_LOGIC_VECTOR(1 downto 0);
overflow : out STD_LOGIC;
clk : in STD_LOGIC;
masterReset : in STD_LOGIC;
input_val : out std_logic_vector (7 downto 0);
average_val : out STD_LOGIC_VECTOR(7 downto 0));
end datapath_averager;
architecture Behavioral of datapath_averager is
type DATA_MEM is array (0 to 63) of integer range 0 to 255;
signal V : DATA_MEM := ( 12, 23, 222, 12, 231, 42, 56, 121, 78, 76,
23, 119, 12, 45, 55, 100, 21, 3, 96, 34,
67, 1, 1, 54, 133, 55, 0, 5, 88, 64,
88, 123, 123, 24, 133, 99, 25, 44, 98, 66,
200, 255, 20, 45, 255, 255, 255, 255, 255, 54,
1, 251, 49, 234, 77, 23, 33, 94, 66, 88,
222, 12, 73, 75 );
type DATA_BUFF is array (0 to 15) of integer range 0 to 255;
signal window : integer range 0 to 16 := 4;
signal fetch_addr : integer range 0 to 64 := 0;
signal layered_division : integer range 0 to 4 := 2;
signal average_buff : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
begin
with window_val select
window <= 4 when "01",
8 when "10",
16 when "11",
4 when others;
with window_val select
layered_division <= 2 when "01",
3 when "10",
4 when "11",
2 when others;
fetch_addr <= conv_integer( IEEE.std_logic_arith.unsigned(mem_addr) );
--average_val <= average_buff;
process (clk, masterReset)
variable buffer_counter : integer range 0 to 16 := 0;
variable sum : integer range 0 to 511 := 0;
variable window_buffer : DATA_BUFF := ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0);
variable temp : std_logic_vector( 8 downto 0);
variable layered_buffer : DATA_BUFF := ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0);
variable limit : integer range 0 to 4 := 0;
begin
if (masterReset = '1') then
window_buffer := (0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0);
layered_buffer := (0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0);
buffer_counter := 0;
sum := 0;
elsif (clk'event and clk = '1') then
window_buffer(buffer_counter) := V(fetch_addr);
input_val <= std_logic_vector(IEEE.numeric_std.to_unsigned(window_buffer(buffer_counter), 8));
--layered_buffer := window_buffer;
layered_buffer(0) := window_buffer(0);
layered_buffer(1) := window_buffer(1);
layered_buffer(2) := window_buffer(2);
layered_buffer(3) := window_buffer(3);
layered_buffer(4) := window_buffer(4);
layered_buffer(5) := window_buffer(5);
layered_buffer(6) := window_buffer(6);
layered_buffer(7) := window_buffer(7);
layered_buffer(8) := window_buffer(8);
layered_buffer(9) := window_buffer(9);
layered_buffer(10) := window_buffer(10);
layered_buffer(11) := window_buffer(11);
layered_buffer(12) := window_buffer(12);
layered_buffer(13) := window_buffer(13);
layered_buffer(14) := window_buffer(14);
layered_buffer(15) := window_buffer(15);
--Test
-- limit := (layered_division-1);
-- for I in 0 to 4 loop
-- if (limit >= 0) then
-- layered_buffer(0) := ( (layered_buffer(0) + layered_buffer(1)) /2 );
-- layered_buffer(1) := ( (layered_buffer(2) + layered_buffer(3)) /2 );
-- layered_buffer(2) := ( (layered_buffer(4) + layered_buffer(5)) /2 );
-- layered_buffer(3) := ( (layered_buffer(6) + layered_buffer(7)) /2 );
-- layered_buffer(4) := ( (layered_buffer(8) + layered_buffer(9)) /2 );
-- layered_buffer(5) := ( (layered_buffer(10) + layered_buffer(11)) /2 );
-- layered_buffer(6) := ( (layered_buffer(12) + layered_buffer(13)) /2 );
-- layered_buffer(7) := ( (layered_buffer(14) + layered_buffer(15)) /2 );
-- end if;
-- limit := limit - 1;
-- end loop;
if (window_val = "01") then
layered_buffer(0) := ( (layered_buffer(0) + layered_buffer(1)) /2 );
layered_buffer(1) := ( (layered_buffer(2) + layered_buffer(3)) /2 );
layered_buffer(2) := ( (layered_buffer(4) + layered_buffer(5)) /2 );
layered_buffer(3) := ( (layered_buffer(6) + layered_buffer(7)) /2 );
layered_buffer(4) := ( (layered_buffer(8) + layered_buffer(9)) /2 );
layered_buffer(5) := ( (layered_buffer(10) + layered_buffer(11)) /2 );
layered_buffer(6) := ( (layered_buffer(12) + layered_buffer(13)) /2 );
layered_buffer(7) := ( (layered_buffer(14) + layered_buffer(15)) /2 );
layered_buffer(0) := ( (layered_buffer(0) + layered_buffer(1)) /2 );
layered_buffer(1) := ( (layered_buffer(2) + layered_buffer(3)) /2 );
layered_buffer(2) := ( (layered_buffer(4) + layered_buffer(5)) /2 );
layered_buffer(3) := ( (layered_buffer(6) + layered_buffer(7)) /2 );
layered_buffer(4) := ( (layered_buffer(8) + layered_buffer(9)) /2 );
layered_buffer(5) := ( (layered_buffer(10) + layered_buffer(11)) /2 );
layered_buffer(6) := ( (layered_buffer(12) + layered_buffer(13)) /2 );
layered_buffer(7) := ( (layered_buffer(14) + layered_buffer(15)) /2 );
elsif (window_val = "10") then
layered_buffer(0) := ( (layered_buffer(0) + layered_buffer(1)) /2 );
layered_buffer(1) := ( (layered_buffer(2) + layered_buffer(3)) /2 );
layered_buffer(2) := ( (layered_buffer(4) + layered_buffer(5)) /2 );
layered_buffer(3) := ( (layered_buffer(6) + layered_buffer(7)) /2 );
layered_buffer(4) := ( (layered_buffer(8) + layered_buffer(9)) /2 );
layered_buffer(5) := ( (layered_buffer(10) + layered_buffer(11)) /2 );
layered_buffer(6) := ( (layered_buffer(12) + layered_buffer(13)) /2 );
layered_buffer(7) := ( (layered_buffer(14) + layered_buffer(15)) /2 );
layered_buffer(0) := ( (layered_buffer(0) + layered_buffer(1)) /2 );
layered_buffer(1) := ( (layered_buffer(2) + layered_buffer(3)) /2 );
layered_buffer(2) := ( (layered_buffer(4) + layered_buffer(5)) /2 );
layered_buffer(3) := ( (layered_buffer(6) + layered_buffer(7)) /2 );
layered_buffer(4) := ( (layered_buffer(8) + layered_buffer(9)) /2 );
layered_buffer(5) := ( (layered_buffer(10) + layered_buffer(11)) /2 );
layered_buffer(6) := ( (layered_buffer(12) + layered_buffer(13)) /2 );
layered_buffer(7) := ( (layered_buffer(14) + layered_buffer(15)) /2 );
layered_buffer(0) := ( (layered_buffer(0) + layered_buffer(1)) /2 );
layered_buffer(1) := ( (layered_buffer(2) + layered_buffer(3)) /2 );
layered_buffer(2) := ( (layered_buffer(4) + layered_buffer(5)) /2 );
layered_buffer(3) := ( (layered_buffer(6) + layered_buffer(7)) /2 );
layered_buffer(4) := ( (layered_buffer(8) + layered_buffer(9)) /2 );
layered_buffer(5) := ( (layered_buffer(10) + layered_buffer(11)) /2 );
layered_buffer(6) := ( (layered_buffer(12) + layered_buffer(13)) /2 );
layered_buffer(7) := ( (layered_buffer(14) + layered_buffer(15)) /2 );
elsif (window_val = "11") then
layered_buffer(0) := ( (layered_buffer(0) + layered_buffer(1)) /2 );
layered_buffer(1) := ( (layered_buffer(2) + layered_buffer(3)) /2 );
layered_buffer(2) := ( (layered_buffer(4) + layered_buffer(5)) /2 );
layered_buffer(3) := ( (layered_buffer(6) + layered_buffer(7)) /2 );
layered_buffer(4) := ( (layered_buffer(8) + layered_buffer(9)) /2 );
layered_buffer(5) := ( (layered_buffer(10) + layered_buffer(11)) /2 );
layered_buffer(6) := ( (layered_buffer(12) + layered_buffer(13)) /2 );
layered_buffer(7) := ( (layered_buffer(14) + layered_buffer(15)) /2 );
layered_buffer(0) := ( (layered_buffer(0) + layered_buffer(1)) /2 );
layered_buffer(1) := ( (layered_buffer(2) + layered_buffer(3)) /2 );
layered_buffer(2) := ( (layered_buffer(4) + layered_buffer(5)) /2 );
layered_buffer(3) := ( (layered_buffer(6) + layered_buffer(7)) /2 );
layered_buffer(4) := ( (layered_buffer(8) + layered_buffer(9)) /2 );
layered_buffer(5) := ( (layered_buffer(10) + layered_buffer(11)) /2 );
layered_buffer(6) := ( (layered_buffer(12) + layered_buffer(13)) /2 );
layered_buffer(7) := ( (layered_buffer(14) + layered_buffer(15)) /2 );
layered_buffer(0) := ( (layered_buffer(0) + layered_buffer(1)) /2 );
layered_buffer(1) := ( (layered_buffer(2) + layered_buffer(3)) /2 );
layered_buffer(2) := ( (layered_buffer(4) + layered_buffer(5)) /2 );
layered_buffer(3) := ( (layered_buffer(6) + layered_buffer(7)) /2 );
layered_buffer(4) := ( (layered_buffer(8) + layered_buffer(9)) /2 );
layered_buffer(5) := ( (layered_buffer(10) + layered_buffer(11)) /2 );
layered_buffer(6) := ( (layered_buffer(12) + layered_buffer(13)) /2 );
layered_buffer(7) := ( (layered_buffer(14) + layered_buffer(15)) /2 );
layered_buffer(0) := ( (layered_buffer(0) + layered_buffer(1)) /2 );
layered_buffer(1) := ( (layered_buffer(2) + layered_buffer(3)) /2 );
layered_buffer(2) := ( (layered_buffer(4) + layered_buffer(5)) /2 );
layered_buffer(3) := ( (layered_buffer(6) + layered_buffer(7)) /2 );
layered_buffer(4) := ( (layered_buffer(8) + layered_buffer(9)) /2 );
layered_buffer(5) := ( (layered_buffer(10) + layered_buffer(11)) /2 );
layered_buffer(6) := ( (layered_buffer(12) + layered_buffer(13)) /2 );
layered_buffer(7) := ( (layered_buffer(14) + layered_buffer(15)) /2 );
end if;
sum := layered_buffer(0);
--buffer_counter := 0;
buffer_counter := buffer_counter + 1;
--buffer_counter := buffer_counter mod window;
if (buffer_counter >= window) then
buffer_counter := buffer_counter - window;
end if;
temp := std_logic_vector(IEEE.numeric_std.to_unsigned(sum,9));
average_val <= temp (7 downto 0);
--overflow <= temp(8);
if ( sum = 255 ) then
overflow <= '1';
else
overflow <= '0';
end if;
end if;
end process;
--overflow <= '1' when ( average_val = "111111") else '0';
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci_target
-- File: pci_target.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Simple PCI target interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.pci.all;
entity pci_target is
generic (
hindex : integer := 0;
abits : integer := 21;
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
nsync : integer range 1 to 2 := 1; -- 1 or 2 sync regs between clocks
oepol : integer := 0);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end;
architecture rtl of pci_target is
constant REVISION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_PCITRG, 0, REVISION, 0),
others => zero32);
constant CSYNC : integer := nsync-1;
constant MADDR_WIDTH : integer := abits;
constant zero : std_logic_vector(31 downto 0) := (others => '0');
subtype word4 is std_logic_vector(3 downto 0);
subtype word32 is std_logic_vector(31 downto 0);
constant pci_memory_read : word4 := "0110";
constant pci_memory_write : word4 := "0111";
constant pci_config_read : word4 := "1010";
constant pci_config_write : word4 := "1011";
constant pci_memory_read_m : word4 := "1100"; -- Aliased to Memory Read
constant pci_memory_read_l : word4 := "1110"; -- Aliased to Memory Read
constant pci_memory_write_i: word4 := "1111"; -- Aliased to Memory Write
type pci_input_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_logic;
devsel : std_logic;
idsel : std_logic;
trdy : std_logic;
irdy : std_logic;
par : std_logic;
stop : std_logic;
rst : std_logic;
end record;
type pci_target_state_type is (idle, b_busy, s_data, backoff, turn_ar);
type pci_reg_type is record
addr : std_logic_vector(MADDR_WIDTH-1 downto 0);
data : std_logic_vector(31 downto 0);
cmd : std_logic_vector(3 downto 0);
state : pci_target_state_type;
csel : std_logic;
msel : std_logic;
read : std_logic;
devsel : std_logic;
trdy : std_logic;
stop : std_logic;
par : std_logic;
oe_par : std_logic;
oe_ad : std_logic;
oe_ctrl : std_logic;
noe_par : std_logic;
noe_ad : std_logic;
noe_ctrl : std_logic;
bar0 : std_logic_vector(31 downto MADDR_WIDTH);
page : std_logic_vector(31 downto MADDR_WIDTH-1);
men : std_logic;
twist : std_logic;
laddr : std_logic_vector(31 downto 0);
ldata : std_logic_vector(31 downto 0);
lsize : std_logic_vector(2 downto 0);
lwrite : std_logic;
start : std_logic;
rready : std_logic_vector(csync downto 0);
wready : std_logic_vector(csync downto 0);
sync : std_logic_vector(csync downto 0);
end record;
type cpu_state_type is (idle, sync1, busy, sync2);
type cpu_reg_type is record
data : std_logic_vector(31 downto 0);
state : cpu_state_type;
start : std_logic_vector(csync downto 0);
sync : std_logic;
rready : std_logic;
wready : std_logic;
end record;
signal clk_int : std_logic;
signal pr : pci_input_type;
signal r, rin : pci_reg_type;
signal r2, r2in : cpu_reg_type;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal roe_ad, rioe_ad : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of roe_ad : signal is true;
function byte_twist(di : in std_logic_vector(31 downto 0); twist : in std_logic) return std_logic_vector is
variable do : std_logic_vector(31 downto 0);
begin
if twist = '1' then
for i in 0 to 3 loop
do(31-i*8 downto 24-i*8) := di(31-(3-i)*8 downto 24-(3-i)*8);
end loop;
else
do := di;
end if;
return do;
end function;
function set_size_from_cbe(cbe : in std_logic_vector(3 downto 0))
return std_logic_vector is
variable res : std_logic_vector(1 downto 0);
begin
case cbe is -- FIXME: this may need to be swaped
when "0111" => res := "00";
when "1011" => res := "00";
when "1101" => res := "00";
when "1110" => res := "00";
when "0011" => res := "01";
when "1100" => res := "01";
when others => res := "10";
end case;
return res;
end function;
function set_addr_from_cbe(cbe : in std_logic_vector(3 downto 0);
twist: in std_logic)
return std_logic_vector is
variable res : std_logic_vector(1 downto 0);
begin
if twist = '1' then -- Little (PCI) to big (AHB) endian
case cbe is
when "0111" => res := "11";
when "1011" => res := "10";
when "1101" => res := "01";
when "1110" => res := "00";
when "0011" => res := "10";
when "1100" => res := "00";
when others => res := "00";
end case;
else -- Big (PCI) to big (AHB) endian
case cbe is
when "0111" => res := "00";
when "1011" => res := "01";
when "1101" => res := "10";
when "1110" => res := "11";
when "0011" => res := "00";
when "1100" => res := "10";
when others => res := "00";
end case;
end if;
return res;
end function;
begin
-- Back-end state machine (AHB clock domain)
comb : process (rst, r2, r, dmao)
variable vdmai : ahb_dma_in_type;
variable v : cpu_reg_type;
begin
v := r2;
vdmai.start := '0'; vdmai.burst := '0'; vdmai.size := r.lsize; --"010";
vdmai.address := r.laddr; v.sync := '1';
vdmai.wdata := ahbdrivedata(r.ldata); vdmai.write := r.lwrite; vdmai.irq := '0';
v.start(0) := r2.start(csync); v.start(csync) := r.start;
case r2.state is
when idle =>
v.sync := '0';
if r2.start(0) = '1' then
if r.lwrite = '1' then v.state := sync1; v.wready := '0';
else v.state := busy; vdmai.start := '1'; end if;
end if;
when sync1 =>
if r2.start(0) = '0' then v.state := busy; vdmai.start := '1'; end if;
when busy =>
if dmao.active = '1' then
if dmao.ready = '1' then
v.rready := not r.lwrite; v.data := dmao.rdata(31 downto 0); v.state := sync2;
end if;
else vdmai.start := '1'; end if;
when sync2 =>
if r2.start(0) = '0' then
v.state := idle; v.wready := '1'; v.rready := '0';
end if;
end case;
if rst = '0' then
v.state := idle; v.rready := '0'; v.wready := '1';
end if;
r2in <= v; dmai <= vdmai;
end process;
-- PCI target core (PCI clock domain)
pcicomb : process(pr, pcii, r, r2, roe_ad)
variable v : pci_reg_type;
variable chit, mhit, hit, ready, cwrite, mwrite : std_logic;
variable cdata, cwdata : std_logic_vector(31 downto 0);
variable caddr : std_logic_vector(7 downto 2);
variable voe_ad : std_logic_vector(31 downto 0);
variable oe_ctrl, oe_par, oe_ad : std_ulogic;
begin
v := r; v.trdy := '1'; v.stop := '1'; voe_ad := roe_ad;
v.oe_ad := '1'; v.devsel := '1'; mwrite := '0';
v.rready(0) := r.rready(csync); v.rready(csync) := r2.rready;
v.wready(0) := r.wready(csync); v.wready(csync) := r2.wready;
v.sync(0) := r.sync(csync); v.sync(csync) := r2.sync;
-- address decoding
--if (r.state = s_data) and ((pr.irdy or r.trdy or r.read) = '0') then
if (r.state = turn_ar) and ((pr.irdy or pr.trdy or r.read) = '0') then
cwrite := r.csel;
if ((r.msel and r.addr(MADDR_WIDTH-1)) = '1') and (pr.cbe = "0000") then
v.page := pr.ad(31 downto MADDR_WIDTH-1);
v.twist := pr.ad(0);
end if;
if (pr.cbe = "0000") and (r.addr(MADDR_WIDTH-1) = '1') then
mwrite := r.msel;
end if;
else cwrite := '0'; end if;
cdata := (others => '0'); caddr := r.addr(7 downto 2);
case caddr is
when "000000" => -- 0x00, device & vendor id
cdata := conv_std_logic_vector(DEVICE_ID, 16) &
conv_std_logic_vector(VENDOR_ID, 16);
when "000001" => -- 0x04, status & command
cdata(1) := r.men; cdata(26) := '1';
when "000010" => -- 0x08, class code & revision
when "000011" => -- 0x0c, latency & cacheline size
when "000100" => -- 0x10, BAR0
cdata(31 downto MADDR_WIDTH) := r.bar0;
when others =>
end case;
cwdata := pr.ad;
if pr.cbe(3) = '1' then cwdata(31 downto 24) := cdata(31 downto 24); end if;
if pr.cbe(2) = '1' then cwdata(23 downto 16) := cdata(23 downto 16); end if;
if pr.cbe(1) = '1' then cwdata(15 downto 8) := cdata(15 downto 8); end if;
if pr.cbe(0) = '1' then cwdata( 7 downto 0) := cdata( 7 downto 0); end if;
if cwrite = '1' then
case caddr is
when "000001" => -- 0x04, status & command
v.men := cwdata(1);
when "000100" => -- 0x10, BAR0
v.bar0 := cwdata(31 downto MADDR_WIDTH);
when others =>
end case;
end if;
if (((pr.cbe = pci_config_read) or (pr.cbe = pci_config_write))
and (pr.ad(1 downto 0) = "00"))
then chit := '1'; else chit := '0'; end if;
if ((pr.cbe = pci_memory_read) or (pr.cbe = pci_memory_write)
or (pr.cbe = pci_memory_read_m) or (pr.cbe = pci_memory_read_l) or (pr.cbe = pci_memory_write_i))
and (r.bar0 = pr.ad(31 downto MADDR_WIDTH))
and (r.bar0 /= zero(31 downto MADDR_WIDTH))
then mhit := '1'; else mhit := '0'; end if;
hit := r.csel or r.msel;
ready := r.csel or (r.rready(0) and r.read) or (r.wready(0) and not r.read and not r.start) or
r.addr(MADDR_WIDTH-1);
-- target state machine
case r.state is
when idle =>
if pr.frame = '0' then v.state := b_busy; end if; -- !HIT ?
v.addr := pr.ad(MADDR_WIDTH-1 downto 0); v.cmd := pr.cbe;
v.csel := pr.idsel and chit;
v.msel := r.men and mhit; v.read := not pr.cbe(0);
if (r.sync(0) and r.start and r.lwrite) = '1' then v.start := '0'; end if;
when turn_ar =>
if pr.frame = '1' then v.state := idle; end if;
if pr.frame = '0' then v.state := b_busy; end if; -- !HIT ?
v.addr := pr.ad(MADDR_WIDTH-1 downto 0); v.cmd := pr.cbe;
v.csel := pr.idsel and chit;
v.msel := r.men and mhit; v.read := not pr.cbe(0);
if (r.sync(0) and r.start and r.lwrite) = '1' then v.start := '0'; end if;
when b_busy =>
if hit = '1' then
v.state := s_data; v.trdy := not ready; v.stop := pr.frame and ready;
v.devsel := '0';
else
v.state := backoff;
end if;
when s_data =>
v.stop := r.stop; v.devsel := '0';
v.trdy := r.trdy or not pcii.irdy;
if (pcii.frame and not pcii.irdy) = '1' then
v.state := turn_ar; v.stop := '1'; v.trdy := '1'; v.devsel := '1';
end if;
when backoff =>
if pr.frame = '1' then v.state := idle; end if;
end case;
if ((r.state = s_data) or (r.state = turn_ar)) and
(((pr.irdy or pr.trdy) = '0') or
((not pr.irdy and not pr.stop and pr.trdy and not r.start and r.wready(0)) = '1'))
then
if (pr.trdy and r.read)= '0' then v.start := '0'; end if;
if (r.start = '0') and ((r.msel and not r.addr(MADDR_WIDTH-1)) = '1') and
(((pr.trdy and r.read and not r.rready(0)) or (not pr.trdy and not r.read)) = '1')
then
v.laddr := r.page & r.addr(MADDR_WIDTH-2 downto 0);
v.ldata := pr.ad; v.lwrite := not r.read; v.start := '1';
-- Added little/big endian support
v.laddr := v.laddr(31 downto 2) & set_addr_from_cbe(pr.cbe, r.twist);
v.ldata := byte_twist(v.ldata, r.twist);
v.lsize := '0' & set_size_from_cbe(pr.cbe);
end if;
end if;
if (v.state = s_data) and (r.read = '1') then v.oe_ad := '0'; end if;
v.oe_par := r.oe_ad;
if r.csel = '1' then v.data := cdata;
elsif r.addr(MADDR_WIDTH-1) = '1' then
v.data(31 downto MADDR_WIDTH-1) := r.page;
v.data(MADDR_WIDTH-2 downto 0) := (others => '0');
v.data(0) := r.twist; -- Addded little/bit endian support
--else v.data := r2.data; end if;
else v.data := byte_twist(r2.data, r.twist); end if;
v.par := xorv(r.data & pcii.cbe);
if (v.state = s_data) or (r.state = s_data) then
v.oe_ctrl := '0';
else v.oe_ctrl := '1'; end if;
v.noe_ctrl := not v.oe_ctrl; v.noe_ad := not v.oe_ad; v.noe_par := not v.oe_par;
if oepol = 1 then
oe_ctrl := r.noe_ctrl; oe_ad := r.noe_ad; oe_par := r.noe_par;
voe_ad := (others => v.noe_ad);
else
oe_ctrl := r.oe_ctrl; oe_ad := r.oe_ad; oe_par := r.oe_par;
voe_ad := (others => v.oe_ad);
end if;
if pr.rst = '0' then
v.state := idle; v.men := '0'; v.start := '0';
v.bar0 := (others => '0'); v.msel := '0'; v.csel := '0';
v.page := (others => '0');
v.page(31 downto 30) := "01";
v.twist := '0';
end if;
rin <= v;
rioe_ad <= voe_ad;
pcio.ctrlen <= oe_ctrl;
pcio.trdy <= r.trdy;
pcio.trdyen <= oe_ctrl;
pcio.stop <= r.stop;
pcio.stopen <= oe_ctrl;
pcio.devsel <= r.devsel;
pcio.devselen <= oe_ctrl;
pcio.par <= r.par;
pcio.paren <= oe_par;
pcio.aden <= oe_ad;
pcio.ad <= r.data;
pcio.rst <= '1';
end process;
pcir : process (pciclk, pcii.rst, r2)
begin
if rising_edge (pciclk) then
pr.ad <= to_x01(pcii.ad);
pr.cbe <= to_x01(pcii.cbe);
pr.devsel <= to_x01(pcii.devsel);
pr.frame <= to_x01(pcii.frame);
pr.idsel <= to_x01(pcii.idsel);
pr.irdy <= to_x01(pcii.irdy);
pr.trdy <= to_x01(pcii.trdy);
pr.par <= to_x01(pcii.par);
pr.stop <= to_x01(pcii.stop);
pr.rst <= to_x01(pcii.rst);
r <= rin;
roe_ad <= rioe_ad;
end if;
if pcii.rst = '0' then -- asynch reset required
r.oe_ctrl <= '1'; r.oe_par <= '1'; r.oe_ad <= '1';
r.noe_ctrl <= '0'; r.noe_par <= '0'; r.noe_ad <= '0';
if oepol = 0 then roe_ad <= (others => '1');
else roe_ad <= (others => '0'); end if;
end if;
end process;
cpur : process (clk)
begin
if rising_edge (clk) then
r2 <= r2in;
end if;
end process;
oe0 : if oepol = 0 generate
pcio.perren <= '1';
pcio.cbeen <= (others => '1');
pcio.serren <= '1';
pcio.inten <= '1';
pcio.vinten <= (others => '1');
pcio.reqen <= not pcii.rst;
pcio.frameen <= '1';
pcio.irdyen <= '1';
pcio.locken <= '1';
end generate;
oe1 : if oepol = 1 generate
pcio.perren <= '0';
pcio.cbeen <= (others => '0');
pcio.serren <= '0';
pcio.inten <= '0';
pcio.vinten <= (others => '0');
pcio.reqen <= pcii.rst;
pcio.frameen <= '0';
pcio.irdyen <= '0';
pcio.locken <= '0';
end generate;
pcio.vaden <= roe_ad;
pcio.cbe <= "1111";
pcio.perr <= '1';
pcio.serr <= '1';
pcio.int <= '1';
pcio.req <= '1';
pcio.frame <= '1';
pcio.irdy <= '1';
ahbmst0 : ahbmst generic map (hindex => hindex, devid => GAISLER_PCITRG)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
-- pragma translate_off
bootmsg : report_version
generic map ("pci_target" & tost(hindex) &
": 32-bit PCI Target rev " & tost(REVISION) &
", " & tost(abits) & "-bit PCI memory BAR" );
-- pragma translate_on
end;
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