content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
library ieee;
use ieee.std_logic_1164.all;
entity processor_tb is
end entity processor_tb;
architecture tb of processor_tb is
constant T : time := 20 ns;
signal clk, rst : std_logic;
begin
uut : entity work.processor
port map(clk => clk,
rst => rst);
clk_gen : process is
begin
clk <= '0';
wai... |
entity entity_a is
end entity;
entity entity_a is
end entity;
entity entity_b is
end entity;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Sun Jun 18 18:22:31 2017
-- Host : DESKTOP-GKPSR1F running 64-bit m... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity complemento1 is
Port ( entrada : in STD_LOGIC_VECTOR (2 downto 0) := "000";
sel : in STD_LOGIC := '1';
saida : out STD_LOGIC_VECTOR (2 downto 0)
);
end complemento1;
architecture Behavioral of complemento1 is
signal aux : STD_LOGIC_VECTO... |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 02:34:31 2019
-- Host : varun-laptop running 64-bit Service ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DataMemory is
Port ( Rst : in STD_LOGIC;
cRD : in STD_LOGIC_VECTOR (31 downto 0);
AluResult : in STD_LOGIC_VECTOR (31 downto 0);
WrENMem : in STD_LOGIC;
R... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 28 09:34:25 2017
-- Host : vldmr-PC running 64-bit Service Pack... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- Company: Texas State University
-- Engineer: Preston Maness
--
-- Create Date: 15:20:39 02/11/2014
-- Design Name: BCD_XS3
-- Module Name: /home/preston/Dropbox/EE4321-VHDL/Project-1/testBenchVector.vhd
-- Project Name: BCD_XS3
-... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
-----------------------------------------------------------------------
-----------------------------DESLOCADOR--------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity deslocador is
port (
a: in std_logic_vector(31 dow... |
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY CDiv IS
PORT ( Cin : IN STD_LOGIC ;
Cout : OUT STD_LOGIC ) ;
END CDiv ;
ARCHITECTURE Behavior OF CDiv IS
constant TC: integer := 71; --Time Constant
signal c0,c1,c2,c3: integer range 0 to 1000;
signal D: std_logic := '0';
BEGIN
PROCESS(Cin)
B... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity zigzag_index is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(5 downto 0);
ra0_data : out std_logic_vector(5 downto 0)
);
end zigzag_index;
architecture augh of zigzag_index is
-- Embedded RAM
type ram... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity zigzag_index is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(5 downto 0);
ra0_data : out std_logic_vector(5 downto 0)
);
end zigzag_index;
architecture augh of zigzag_index is
-- Embedded RAM
type ram... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity div_frecuencia_motor is
Port ( CLK : in STD_LOGIC;
b : out STD_LOGIC);
end div_frecuencia_motor;
architecture Behavioral of div_frecuencia_motor is
signal contador : integer := 2500000;
begin
process begin
wait until rising_edge(CLK);
b <= '0';
if ... |
-- Based on the Quartus II VHDL Template for True Dual-Port RAM with single clock
-- Read-during-write on port A or B returns newly written data
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_textio.all;
use std.textio.all;
entity dpram is
generic(g_data_widt... |
-- Based on the Quartus II VHDL Template for True Dual-Port RAM with single clock
-- Read-during-write on port A or B returns newly written data
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_textio.all;
use std.textio.all;
entity dpram is
generic(g_data_widt... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu Jun 01 02:22:05 2017
-- Host : GILAMONSTER running 64-bit major rel... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY invert_logic IS
GENERIC
(
length : integer
);
PORT
(
input : IN std_logic_vector(length-1 downto 0);
output : OUT std_logic_vector(length-1 downto 0)
);
END invert_logic;
ARCHITECTURE behavior OF invert_logic IS
BEGIN
output <= not inp... |
constant bitdataLength : integer := 1282;
constant bitdataCfg : std_logic_vector(bitdataLength-1 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000100000000000000000000010000010000000000000000000000000000000000000000001000000000000000000000000000000000010001000100000000000000000000000... |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 03:32:36 2019
-- Host : varun-laptop running 64-bit Serv... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00648
--
-- AUTHOR:
--
-- G. Tomi... |
entity TestAnd2
end entity TestAnd2
architecture test2 of TestAnd2 is
signal a, b, c: BIT;
begin
g1: entity WORK.And2(arch2) port map (x => a, y => b, z => c);
process is
begin
a <= '0';
b <= '0';
wait for 100ns;
a <= '1';
wait for 150ns;
b <= '1';
... |
package body my_pkg is
procedure some_proc (
a : integer;
b : integer
) is
constant some_const : integer_vector :=
some_proc(
arg1, arg2, arg3, arg4,
... |
-- This is the implementation of the complex filter C^{-1}_{-30/-150}(z) = (1 + j z^{-1} - z^{-2})
-- which creates zeros at e^-j30 [deg] and e^-j150 [deg]
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Softwar... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity FullAdder is
port( a, b, cin : in std_logic;
s, cout : out std_logic);
end FullAdder;
architecture Behavioral of FullAdder is
begin
s <= a xor b xor cin;
cout <= (a and b) or (cin and (a xor b));
end Behavioral; |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
library IEEE;
use IEEE.Std_Logic_1164.all;
entity myAnd16 is
port(a: in std_logic_vector(15 downto 0); b: in std_logic_vector(15 downto 0); s: out std_logic_vector(15 downto 0));
end myAnd16;
architecture behavioral of myAnd16 is
component myAnd2
port(a: in std_logic; b: in std_logic; s: out std_logi... |
-- NEED RESULT: ARCH00332.Check_s6: Concurrent signal assignment may have a label passed
-- NEED RESULT: ARCH00332.Check_s5: Concurrent signal assignment need not have a label passed
-- NEED RESULT: ARCH00332.Check_s4: Concurrent signal assignment may have a label passed
-- NEED RESULT: ARCH00332.Check_s3: Concurren... |
-- ======================================================================
-- DES encryption/decryption
-- algorithm according to FIPS 46-3 specification
-- Copyright (C) 2007 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute... |
-------------------------------------------------------------------------------
--
-- Module : ll_fifo_pkg.vhd
--
-- Version : 1.2
--
-- Last Update : 2005-06-29
-- ... |
architecture RTL of FIFO is
begin
-- These are passing
ret <= (
data => (others => '-'),
valid => '0',
sop => '0',
eop => '0',
empty => (others => '0'),
error => (others => '0')
);
-- These are failing
ret <= (data => (others => '-'), valid => '0', s... |
-- NEED RESULT: ARCH00122.P1: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00122.P2: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00122.P3: Multi tr... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright ... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
-- Date : Tue Mar 22 03:45:28 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- NEED RESULT: *** 10 assertion messages should follow
-- NEED RESULT: Assertion # 1
-- NEED RESULT: Assertion # 2
-- NEED RESULT: Assertion # 3
-- NEED RESULT: Assertion # 4
-- NEED RESULT: Assertion # 5
-- NEED RESULT: Assertion # 6
-- NEED RESULT: Assertion # 7
-- NEED RESULT: Assertion # 8
-- NEED RESULT:... |
----------------------------------------------------------------------------------
-- Company: TU Wien - ECS Group --
-- Engineer: Thomas Polzer --
-- ... |
----------------------------------------------------------------------------------
-- Company: TU Wien - ECS Group --
-- Engineer: Thomas Polzer --
-- ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:23:33 02/02/2011
-- Design Name:
-- Module Name: wingbutled - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:22:35 11/21/2016
-- Design Name:
-- Module Name: Adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... |
library ieee; use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
entity uart_rx is
generic (
CLK_HZ : natural := 10000000; -- in Hz
BAUD : natural := 115200 -- Baud rate
);
port(
clk_i : in std_logic;
rst_i : in s... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This progra... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This progra... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This progra... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This progra... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This progra... |
--/**************************************************************************************************************
--*
--* B i t H o u n d - A n F P G A B a s e d L o g i c A n a l y z e r
--*
--* FPGA Design
--*
--* Copyright 2012 Mario Mauerer (MM), Lukas Schrittwieser (LS), ETH Zurich
--*
--* ... |
--
-- LinearTable.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity LinearTable is port (
clk : in std_logic;
reset : in std_logic;
addr : in SIGNED_DB_TYPE;
data : out SIGNED_LI_TYPE
);
end LinearTable;
architecture ... |
--
-- LinearTable.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity LinearTable is port (
clk : in std_logic;
reset : in std_logic;
addr : in SIGNED_DB_TYPE;
data : out SIGNED_LI_TYPE
);
end LinearTable;
architecture ... |
-------------------------------------------------------------------------------
--
-- Design : Dispatch Unit
-- Project : Tomasulo Processor
-- Entity : dispatch_unit
-- Author : Manpreet Billing
-- Company : University of Southern California
-- Last Updated : March 2, 2010
-------------------------------... |
-------------------------------------------------------------------------------
--
-- Design : Dispatch Unit
-- Project : Tomasulo Processor
-- Entity : dispatch_unit
-- Author : Manpreet Billing
-- Company : University of Southern California
-- Last Updated : March 2, 2010
-------------------------------... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
... |
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have ... |
-------------------------------------------------------------------------------
-- Title : IR Remote Shutter release for Canon DSLR
-------------------------------------------------------------------------------
-- Author : cjt@users.sourceforge.net
-------------------------------------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--
-- This should pass
--| This should pass
----------This should pass
--==================
--This should fail
--|This should fail
----------This should pass
--
--==================
--¨
-- pragmas should be ignored
--vhdl_comp_off
--vhdl_comp_on
|
-- Machine generated from ram.img.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package bootrom is
type rom_t is array (0 to 127) of std_logic_vector(31 downto 0);
constant rom : rom_t := (
x"00000110",
x"00001ffc",
x"00000110",
-- more stuff, doesn't matter as long as it fits..... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity D_TRIGER is
port
(
D, CLK, NRST, NST: in std_logic;
Q, NQ: out std_logic
);
end D_TRIGER;
architecture arch of D_TRIGER is
signal r: std_logic := '0';
begin
Q <= r;
NQ <= not r;
process(CLK, NRST, NST)
begin
if NST = '0' then
r <= '1';
elsif NRST = '0'... |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the F... |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the F... |
architecture rtl of fifo is
type t_record is record
a : std_logic;
b : std_logic;
end record t_record;
type t_record is record
a : std_logic;
b : std_logic;
end record t_record;
type t_record is record
a : std_logic;
b : std_logic;
end record t_record;
type t_record is record... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
architecture rtl of StateRegister is
begin -- rtl
StoreState: process (Clk_i, Reset_n_i)
begin -- process StoreState
if Reset_n_i = '0' then -- asynchronous reset (active low)
State_o <= (others => '0');
elsif Clk_i'event and Clk_i = '1' then -- rising clock edge
State_o <= Next... |
architecture rtl of StateRegister is
begin -- rtl
StoreState: process (Clk_i, Reset_n_i)
begin -- process StoreState
if Reset_n_i = '0' then -- asynchronous reset (active low)
State_o <= (others => '0');
elsif Clk_i'event and Clk_i = '1' then -- rising clock edge
State_o <= Next... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.NUMERIC_STD.all;
LIBRARY unisim;
USE unisim.vcomponents.all;
ENTITY radio_dac_if IS
PORT(
DCLKIO : IN std_logic;
S_AXIS_DAC_A_tdata : IN std_logic_vector (15 DOWNTO 0);
S_AXIS_DAC_A_tvalid : IN std_logic;
S_AXIS_DAC_B... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity UART_TX is
PORT( CLK_I : in std_logic;
RST_I : in std_logic; -- RESET
CE_16 : in std_logic; -- BUAD rate clock
DATA : in std_logic_vector(7 downto 0); -- DATA to be sent
DATA_FLAG : ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity UART_TX is
PORT( CLK_I : in std_logic;
RST_I : in std_logic; -- RESET
CE_16 : in std_logic; -- BUAD rate clock
DATA : in std_logic_vector(7 downto 0); -- DATA to be sent
DATA_FLAG : ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity UART_TX is
PORT( CLK_I : in std_logic;
RST_I : in std_logic; -- RESET
CE_16 : in std_logic; -- BUAD rate clock
DATA : in std_logic_vector(7 downto 0); -- DATA to be sent
DATA_FLAG : ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:01:43 11/30/2015
-- Design Name:
-- Module Name: State_Reg_Ultrasonic - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for OBP
---------------------------------------------------------------------------------------
-- File : obp_wb_slave.vhd
-- Author : auto-generated by wbgen2 from obp_wb_sl... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
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