content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:37:59 02/28/2017
-- Design Name:
-- Module Name: /home/julian/Projekt/Xilinx Projects/present-vhdl/src/present_tb.vhd
-- Project Name: present-vhdl
-- Target Device:
-- Tool versions:
-- ... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-------------------------------------------------------------------------------
-- axi_vdma_reg_module
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rig... |
-------------------------------------------------------------------------------
-- axi_vdma_reg_module
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rig... |
-------------------------------------------------------------------------------
-- axi_vdma_reg_module
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rig... |
-------------------------------------------------------------------------------
-- axi_vdma_reg_module
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rig... |
-- RESOLUTION 160x100
--library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
--
--
--package CONFIG_MANDELBROT is
--constant XSTART : SIGNED(31 downto 0) :=x"E0000000";
--constant XSTOP : SIGNED(31 downto 0) :=x"10000000";
--constant YSTART : SIGNED(31 downto 0) :=x"F0000000";
--constant YSTOP : SI... |
-------------------------------------------------------------------------------
--! @file mixColumn.vhd
--! @brief AES MixColumn operation (single column)
--! @project VLSI Book - AES-128 Example
--! @author Michael Muehlberghuber (mbgh@iis.ee.ethz.ch)
--! @company Integrated Systems Laboratory, ET... |
-- kb_code.vhd - Modul pro dekodovani kodu klavesy
-- Autori: Jakub Cabal
-- Posledni zmena: 14.10.2014
-- Popis: Tato komponenta generuje kod prave zmackle klavesy
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.A... |
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Gener... |
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Gener... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library ieee;
use ieee.std_logic_1164.all;
entity dff02 is
port (q : out std_logic;
d : std_logic;
en1 : std_logic;
en2 : std_logic;
clk : std_logic);
end dff02;
architecture behav of dff02 is
begin
process (clk) is
begin
if rising_edge (clk) and en1 = '1' then
q <= d;
... |
-------------------------------------------------------------------------------
-- File Name : FDCT.vhd
--
-- Project : JPEG_ENC
--
-- Module : FDCT
--
-- Content : FDCT
--
-- Description : 2D Discrete Cosine Transform
--
-- Spec. :
--
-- Author : Michal Krepa
--
----------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : FDCT.vhd
--
-- Project : JPEG_ENC
--
-- Module : FDCT
--
-- Content : FDCT
--
-- Description : 2D Discrete Cosine Transform
--
-- Spec. :
--
-- Author : Michal Krepa
--
----------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : FDCT.vhd
--
-- Project : JPEG_ENC
--
-- Module : FDCT
--
-- Content : FDCT
--
-- Description : 2D Discrete Cosine Transform
--
-- Spec. :
--
-- Author : Michal Krepa
--
----------------------------------------... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.10:16:46)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesahb_femo_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 30);
output1, output2: OUT unsigned(0 TO 31));
... |
architecture ARCH of ENTITY1 is
begin
LABEL : assert boolean report "Something" severity FAILURE;
LABEL : assert boolean
report "Something" severity FAILURE;
LABEL : assert boolean report "Something"
severity FAILURE;
LABEL : assert boolean
report "Something"
severity FAILURE;
assert bo... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY system IS
PORT(rst: IN std_logic; -- system reset, high active
clk: IN std_logic; -- system clock, 50 MHz, rising edge active
btn0: IN std_logic; -- push button, low active
... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use work.Global.all;
package sin_4096 is
-- sin table with 4096 values
constant sin_table_c : fract_set_t := (
0.00076699, 0.00230097, 0.00383494, 0.00536891, 0.00690286, 0.00843679, 0.00997071, 0.01150460, 0.01303847, 0.01457230,
0.01610610, 0.01763986, 0.01917... |
architecture RTL of ENT is
begin
end architecture RTL;
architecture RTL of ENT is
begin
end rtl;
architecture RTL of ENT is
begin
end architecture Rtl;
architecture RTL of ENT is
begin
end;
architecture RTL of ENT is
begin
end architecture;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- megafunction wizard: %LPM_OR%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_or
-- ============================================================
-- File Name: gl_or16b.vhd
-- Megafunction Name(s):
-- lpm_or
--
-- Simulation Library Files(s):
-- lpm
-- ================================================... |
-- megafunction wizard: %LPM_OR%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_or
-- ============================================================
-- File Name: gl_or16b.vhd
-- Megafunction Name(s):
-- lpm_or
--
-- Simulation Library Files(s):
-- lpm
-- ================================================... |
-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.0.111.2
-- Module Version: 5.8
--/usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n fmexg_fifo_8k_2049 -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo3c00f -type ebfifo -depth 8192 -width 12 -rwidth 12 -no_enable -pe 10 -pf 2049
-- Thu May 9 17:13:5... |
-------------------------------------------------------------------------------
-- $Id: bram_fifo.vhd,v 1.1 2005/02/18 15:30:22 wirthlin Exp $
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-----------------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: bram_fifo.vhd,v 1.1 2005/02/18 15:30:22 wirthlin Exp $
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-----------------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: bram_fifo.vhd,v 1.1 2005/02/18 15:30:22 wirthlin Exp $
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-----------------------------------------------------------------------------... |
-- ps7_uart_monitor.vhd
--
-- Monitor the PS7 interface, print to console in simulation, and
-- return valid readdata if the UART is being bypassed.
-- If bypass is hardwired to 0 should get trivially synthesized away.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library STD;
use STD.textio.al... |
-------------------------------------------------------------------------------
-- Title : IGMP Controller
-- Project :
-------------------------------------------------------------------------------
--! @file : igmp_controller.vhd
-- Author : Colin W. Shea
-- Company
-- Last update : 2010-03-... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_vdma_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ******************... |
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_vdma_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ******************... |
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_vdma_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ******************... |
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_vdma_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ******************... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
... |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_si... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_async_rx is
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
baud8_tick_i: in std_logic;
rxd_i : in std_logic;
rx_ready_o : out std_logic;
rx_error_o : out std_logic;
rx_da... |
-------------------------------------------------------------------------------
--! @file ipifMasterHandler-rtl-ea.vhd
--
--! @brief IPIF Master handler
--
--! @details This is the IPIF master handler converting generic master interface
--! to IPIF.
-------------------------------------------------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--MIPI CSI-2 10bit pixel unpacker
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
--This receives 32-bit words from the long video packet payload in; and unpacks them
--into 40 bits of output (which is only active - signified with t... |
---------------------------------------------------------------
-- Title : External driver simulation model
-- Project : A15
---------------------------------------------------------------
-- File : vmebus.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dec_mem is
port (CLK,reset : in std_logic;
WE : in std_logic;
RE : in std_logic;
--ADDR : in std_logic_vector(5 downto 0);
DI : in std_logic_vector(3 downto 0);
DO : out std... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ALU is
port(
-- inputs
alu_op : in std_logic_vector(4 downto 0); -- specifies alu operation to be performed (from CU in ID stage)
a : in std_logic_vector(31 downto 0); -- operand 1
b : in std_logic_... |
----------------------------------------------------------------------------------
-- ------------------- --
-- | | --
-- UP ---------| UP | ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
entity gxor is
port (a, b: in std_logic;
z : out std_logic);
end gxor;
architecture gxor_rtl of gxor is
begin
z <= a xor b;
end architecture gxor_rtl;
library ieee;
use ieee.std_logic_1164.all;
entity gxor_reduce is
generic (half_width: integer := 4);
... |
library ieee;
use ieee.std_logic_1164.all;
entity gxor is
port (a, b: in std_logic;
z : out std_logic);
end gxor;
architecture gxor_rtl of gxor is
begin
z <= a xor b;
end architecture gxor_rtl;
library ieee;
use ieee.std_logic_1164.all;
entity gxor_reduce is
generic (half_width: integer := 4);
... |
library ieee;
use ieee.std_logic_1164.all;
entity gxor is
port (a, b: in std_logic;
z : out std_logic);
end gxor;
architecture gxor_rtl of gxor is
begin
z <= a xor b;
end architecture gxor_rtl;
library ieee;
use ieee.std_logic_1164.all;
entity gxor_reduce is
generic (half_width: integer := 4);
... |
library ieee;
use ieee.std_logic_1164.all;
entity gxor is
port (a, b: in std_logic;
z : out std_logic);
end gxor;
architecture gxor_rtl of gxor is
begin
z <= a xor b;
end architecture gxor_rtl;
library ieee;
use ieee.std_logic_1164.all;
entity gxor_reduce is
generic (half_width: integer := 4);
... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
entity ent is
end;
architecture behav of ent is
shared variable v : integer;
begin
process
begin
v := 2;
wait for 2 ns;
assert v = 5 severity failure;
wait;
end process;
process
begin
wait for 1 ns;
assert v = 2 severity failure;
v := 5;
wait;
end process;
end;
|
entity ent is
end;
architecture behav of ent is
shared variable v : integer;
begin
process
begin
v := 2;
wait for 2 ns;
assert v = 5 severity failure;
wait;
end process;
process
begin
wait for 1 ns;
assert v = 2 severity failure;
v := 5;
wait;
end process;
end;
|
entity ent is
end;
architecture behav of ent is
shared variable v : integer;
begin
process
begin
v := 2;
wait for 2 ns;
assert v = 5 severity failure;
wait;
end process;
process
begin
wait for 1 ns;
assert v = 2 severity failure;
v := 5;
wait;
end process;
end;
|
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
-- Violation below
entity FIFO is
generic(g_size: integer := 10;
g_width : integer := 256;
g_depth: integer := 32
);
port(
i_port1 : in std_logic;
i_port2 : in std_logic
);
end entity ... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_b
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:08:19 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_MIXED -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autoge... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:58:21 01/15/2015
-- Design Name:
-- Module Name: porteAND_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:58:21 01/15/2015
-- Design Name:
-- Module Name: porteAND_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies... |
----------------------------------------------------------------------
-- brdConst_pkg (for Kickstart Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Package to declare board specific constants.
--
-- LEDs & PushButton SW polarity XOR constants
-- Handling e... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ok_5_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY bat IS
PORT ( clr, CLKBAT : IN STD_LOGIC;
scan_code : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
scan_ready : IN std_logic;
read : OUT std_logic;
paddle_1, paddle_2 : OUT INTEGER RANGE 0 to 48);
END ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNUJT4YY5I is
port(
input : in std_logic_vector(47 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNUJT4YY5I is
port(
input : in std_logic_vector(47 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNUJT4YY5I is
port(
input : in std_logic_vector(47 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNUJT4YY5I is
port(
input : in std_logic_vector(47 downto 0);
output : out std_log... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
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