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--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: RegsGpibFasade
-- Date:2011-11-17
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.gpibComponents.all;
use work.helperComponents.all;
use work.wrapperComponents.all;
entity RegsGpibFasade is
port (
reset : std_logic;
clk : in std_logic;
-----------------------------------------------------------------------
------------ GPIB interface signals -----------------------------------
-----------------------------------------------------------------------
DI : in std_logic_vector (7 downto 0);
DO : out std_logic_vector (7 downto 0);
output_valid : out std_logic;
-- attention
ATN_in : in std_logic;
ATN_out : out std_logic;
-- data valid
DAV_in : in std_logic;
DAV_out : out std_logic;
-- not ready for data
NRFD_in : in std_logic;
NRFD_out : out std_logic;
-- no data accepted
NDAC_in : in std_logic;
NDAC_out : out std_logic;
-- end or identify
EOI_in : in std_logic;
EOI_out : out std_logic;
-- service request
SRQ_in : in std_logic;
SRQ_out : out std_logic;
-- interface clear
IFC_in : in std_logic;
IFC_out : out std_logic;
-- remote enable
REN_in : in std_logic;
REN_out : out std_logic;
-----------------------------------------------------------------------
---------------- registers access -------------------------------------
-----------------------------------------------------------------------
data_in : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(15 downto 0);
reg_addr : in std_logic_vector(14 downto 0);
strobe_read : in std_logic;
strobe_write : in std_logic;
-----------------------------------------------------------------------
---------------- additional lines -------------------------------------
-----------------------------------------------------------------------
interrupt_line : out std_logic
;debug1 : out std_logic
;debug2 : out std_logic
);
end RegsGpibFasade;
architecture arch of RegsGpibFasade is
constant MEM_NATIVE_DATA_WIDTH : integer := 16;
-- gpib
signal g_isLE, g_isTE : std_logic;
signal g_lpeUsed : std_logic;
signal g_fixedPpLine : std_logic_vector (2 downto 0);
signal g_eosUsed : std_logic;
signal g_eosMark : std_logic_vector (7 downto 0);
signal g_myListAddr, g_myTalkAddr : std_logic_vector (4 downto 0);
signal g_secAddrMask : std_logic_vector (31 downto 0);
signal g_data : std_logic_vector (7 downto 0);
signal g_status_byte : std_logic_vector (7 downto 0);
signal g_T1 : std_logic_vector (7 downto 0);
signal g_rdy, g_nba, g_ltn, g_lun, g_lon, g_ton, g_endOf, g_gts, g_rpp,
g_tcs, g_tca, g_sic, g_rsc, g_sre, g_rtl, g_rsv, g_ist, g_lpe, g_dvd,
g_wnc, g_tac, g_lac, g_cwrc, g_cwrd, g_clr, g_trg, g_atl, g_att, g_mla,
g_lsb, g_spa, g_ppr, g_sreq, g_isLocal : std_logic;
signal g_currentSecAddr : std_logic_vector (4 downto 0);
signal g_output_valid : std_logic;
signal g_ATN_out : std_logic;
-- reader
signal r_isLE : std_logic;
signal r_dataSecAddr : std_logic_vector (4 downto 0);
signal r_buf_interrupt : std_logic;
signal r_data_available : std_logic;
signal r_end_of_stream : std_logic;
signal r_reset_buffer : std_logic;
signal r_strobe : std_logic;
signal r_fifo_full : std_logic;
signal r_fifo_ready_to_write : std_logic;
signal r_at_least_one_byte_in_fifo : std_logic;
-- writer
signal w_isTE : std_logic;
signal w_dataSecAddr : std_logic_vector (4 downto 0);
signal w_end_of_stream : std_logic;
signal w_data_available : std_logic;
signal w_buf_interrupt : std_logic;
signal w_reset_buffer : std_logic;
-- serial poll coordinator
signal s_rec_stb : std_logic;
signal s_stb_received : std_logic;
-- reader fifo
signal rm_reset : std_logic;
signal rm_byte_in : std_logic_vector(7 downto 0);
signal rm_byte_out : std_logic_vector(15 downto 0);
-------------- fifo --------------------
signal rm_availableBytesCount : std_logic_vector(10 downto 0);
signal rm_strobe_read : std_logic;
-- writer fifo
signal wm_reset : std_logic;
signal wm_write_strobe : std_logic;
signal wm_data_in : std_logic_vector(15 downto 0);
signal wm_byte_in : std_logic_vector(7 downto 0);
signal wm_ready_to_read : std_logic;
signal wm_bytesAvailable : std_logic;
signal wm_availableBytesCount : std_logic_vector(10 downto 0);
signal wm_bufferFull : std_logic;
signal wm_ready_to_write : std_logic;
signal wm_strobe_read : std_logic;
-- settings reg
signal set0_strobe : std_logic;
signal set0_data_in, set0_data_out :
std_logic_vector((MEM_NATIVE_DATA_WIDTH-1) downto 0);
signal set1_strobe : std_logic;
signal set1_data_in, set1_data_out :
std_logic_vector((MEM_NATIVE_DATA_WIDTH-1) downto 0);
signal set0_isLE_TE : std_logic;
signal set1_myAddr : std_logic_vector(4 downto 0);
-- sec addr mask reg
signal sec0_strobe : std_logic;
signal sec0_data_in, sec0_data_out :
std_logic_vector((MEM_NATIVE_DATA_WIDTH-1) downto 0);
signal sec0_secAddrMask :
std_logic_vector ((MEM_NATIVE_DATA_WIDTH-1) downto 0);
signal sec1_strobe : std_logic;
signal sec1_data_in, sec1_data_out :
std_logic_vector((MEM_NATIVE_DATA_WIDTH-1) downto 0);
signal sec1_secAddrMask :
std_logic_vector ((MEM_NATIVE_DATA_WIDTH-1) downto 0);
-- gpib bus reg
signal gbs_data_out : std_logic_vector ((MEM_NATIVE_DATA_WIDTH-1) downto 0);
-- event reg
signal ev_strobe : std_logic;
signal ev_data_in, ev_data_out :
std_logic_vector((MEM_NATIVE_DATA_WIDTH-1) downto 0);
-- gpib status
signal gs_data_out : std_logic_vector ((MEM_NATIVE_DATA_WIDTH-1) downto 0);
-- gpib control reg
signal gc_strobe : std_logic;
signal gc_data_in, gc_data_out :
std_logic_vector((MEM_NATIVE_DATA_WIDTH-1) downto 0);
-- reader control reg
signal rc0_strobe : std_logic;
signal rc0_data_in, rc0_data_out :
std_logic_vector((MEM_NATIVE_DATA_WIDTH-1) downto 0);
signal rc1_data_out :
std_logic_vector((MEM_NATIVE_DATA_WIDTH-1) downto 0);
-- writer control reg
signal wc0_strobe : std_logic;
signal wc0_data_in, wc0_data_out :
std_logic_vector((MEM_NATIVE_DATA_WIDTH-1) downto 0);
signal wc0_status_byte : std_logic_vector (6 downto 0);
signal wc1_strobe : std_logic;
signal wc1_data_in, wc1_data_out :
std_logic_vector((MEM_NATIVE_DATA_WIDTH-1) downto 0);
begin
debug1 <= g_nba;
debug2 <= g_wnc;
-- settings reg
g_isLE <= set0_isLE_TE;
g_isTE <= set0_isLE_TE;
r_isLE <= set0_isLE_TE;
w_isTE <= set0_isLE_TE;
g_myListAddr <= set1_myAddr;
g_myTalkAddr <= set1_myAddr;
-- sec addr reg
g_secAddrMask (15 downto 0) <= sec0_secAddrMask;
g_secAddrMask (31 downto 16) <= sec1_secAddrMask;
g_status_byte(7) <= wc0_status_byte(6);
g_status_byte(6) <= '0';
g_status_byte(5 downto 0) <= wc0_status_byte(5 downto 0);
-- writer fifo
wm_reset <= w_reset_buffer;
-- reader fifo
rm_reset <= r_reset_buffer;
gpib: gpibInterface port map (
clk => clk, reset => reset,
-- application interface
isLE => g_isLE, isTE => g_isTE, lpeUsed => g_lpeUsed,
fixedPpLine => g_fixedPpLine, eosUsed => g_eosUsed,
eosMark => g_eosMark, myListAddr => g_myListAddr,
myTalkAddr => g_myTalkAddr, secAddrMask => g_secAddrMask,
data => g_data, status_byte => g_status_byte, T1 => g_T1,
rdy => g_rdy, nba => g_nba, ltn => g_ltn, lun => g_lun, lon => g_lon,
ton => g_ton, endOf => g_endOf, gts => g_gts, rpp => g_rpp,
tcs => g_tcs, tca => g_tca, sic => g_sic, rsc => g_rsc, sre => g_sre,
rtl => g_rtl, rsv => g_rsv, ist => g_ist, lpe => g_lpe,
dvd => g_dvd, wnc => g_wnc, tac => g_tac, lac => g_lac, cwrc => g_cwrc,
cwrd => g_cwrd, clr => g_clr, trg => g_trg, atl => g_atl, att => g_att,
mla => g_mla, lsb => g_lsb, spa => g_spa, ppr => g_ppr, sreq => g_sreq,
isLocal => g_isLocal, currentSecAddr => g_currentSecAddr,
DI => DI, DO => DO, output_valid => g_output_valid,
ATN_in => ATN_in, ATN_out => g_ATN_out, DAV_in => DAV_in,
DAV_out => DAV_out, NRFD_in => NRFD_in, NRFD_out => NRFD_out,
NDAC_in => NDAC_in, NDAC_out => NDAC_out, EOI_in => EOI_in,
EOI_out => EOI_out, SRQ_in => SRQ_in, SRQ_out => SRQ_out,
IFC_in => IFC_in, IFC_out => IFC_out, REN_in => REN_in,
REN_out => REN_out, debug1 => open
);
reader: gpibReader port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_in => DI, dvd => g_dvd, lac => g_lac, lsb => g_lsb,
rdy => g_rdy,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isLE => r_isLE, secAddr => g_currentSecAddr,
dataSecAddr => r_dataSecAddr, buf_interrupt => r_buf_interrupt,
end_of_stream => r_end_of_stream,
reset_reader => r_reset_buffer,
------------------ fifo --------------------------------------
fifo_full => r_fifo_full, fifo_ready_to_write => r_fifo_ready_to_write,
at_least_one_byte_in_fifo => r_at_least_one_byte_in_fifo,
data_out => rm_byte_in, fifo_strobe => r_strobe
);
writer: gpibWriter port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_out => g_data, wnc => g_wnc, spa => g_spa, nba => g_nba,
endOf => g_endOf, tac => g_tac, cwrc => g_cwrc,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isTE => w_isTE,
secAddr => g_currentSecAddr, dataSecAddr => w_dataSecAddr,
buf_interrupt => w_buf_interrupt, end_of_stream => w_end_of_stream,
reset_writer => w_reset_buffer,
writer_enable => w_data_available,
---------------- fifo ---------------------------
availableFifoBytesCount => wm_availableBytesCount,
fifo_read_strobe => wm_strobe_read,
fifo_ready_to_read => wm_ready_to_read,
fifo_data_in => wm_byte_in
);
spc: SerialPollCoordinator port map (
clk => clk, reset => reset,
DAC => NDAC_in, rec_stb => s_rec_stb, ATN_in => g_ATN_out,
ATN_out => ATN_out, output_valid_in => g_output_valid,
output_valid_out => output_valid, stb_received => s_stb_received
);
readerFifo: Fifo8b port map (
reset => reset, clk => clk,
-------------- fifo --------------------
bytesAvailable => r_at_least_one_byte_in_fifo,
availableBytesCount => rm_availableBytesCount,
bufferFull => r_fifo_full,
resetFifo => rm_reset,
----------------------------------------
data_in => rm_byte_in, ready_to_write => r_fifo_ready_to_write,
strobe_write => r_strobe,
----------------------------------------
data_out => rm_byte_out(7 downto 0), ready_to_read => r_data_available,
strobe_read => rm_strobe_read
);
writerFifo: Fifo8b port map (
reset => reset, clk => clk,
-------------- fifo --------------------
bytesAvailable => wm_bytesAvailable,
availableBytesCount => wm_availableBytesCount,
bufferFull => wm_bufferFull,
resetFifo => wm_reset,
----------------------------------------
data_in => wm_data_in(7 downto 0),
ready_to_write => wm_ready_to_write,
strobe_write => wm_write_strobe,
----------------------------------------
data_out => wm_byte_in,
ready_to_read => wm_ready_to_read,
strobe_read => wm_strobe_read
);
--Clk2x_0: Clk2x port map (
-- reset => reset,
-- clk => clk,
-- clk2x => clk2x
--);
set0: SettingsReg0 port map (
reset => reset,
strobe => set0_strobe, data_in => set0_data_in,
data_out => set0_data_out,
------------- gpib -----------------------------
isLE_TE => set0_isLE_TE, lpeUsed => g_lpeUsed,
fixedPpLine => g_fixedPpLine, eosUsed => g_eosUsed,
eosMark => g_eosMark, lon => g_lon, ton => g_ton
);
set1: SettingsReg1 port map (
reset => reset,
strobe => set1_strobe, data_in => set1_data_in,
data_out => set1_data_out,
-- gpib
myAddr => set1_myAddr, T1 => g_T1
);
sec0: SecAddrReg port map (
reset => reset,
strobe => sec0_strobe, data_in => sec0_data_in,
data_out => sec0_data_out,
-- gpib
secAddrMask => sec0_secAddrMask
);
sec1: SecAddrReg port map (
reset => reset,
strobe => sec1_strobe, data_in => sec1_data_in,
data_out => sec1_data_out,
-- gpib
secAddrMask => sec1_secAddrMask
);
gbs: gpibBusReg port map (
data_out => gbs_data_out,
----------- gpib ---------------------------------
DIO => DI, ATN => ATN_in, DAV => DAV_in, NRFD => NRFD_in,
NDAC => NDAC_in, EOI => EOI_in, SRQ => SRQ_in, IFC => IFC_in,
REN => REN_in
);
ev: EventReg port map (
reset => reset, clk => clk,
strobe => ev_strobe, data_in => ev_data_in, data_out => ev_data_out,
-------------------- gpib device ---------------------
isLocal => g_isLocal, in_buf_ready => r_buf_interrupt,
out_buf_ready => w_buf_interrupt, clr => g_clr, trg => g_trg,
att => g_att, atl => g_atl, spa => g_spa,
-------------------- gpib controller ---------------------
cwrc => g_cwrc, cwrd => g_cwrd, srq => g_sreq, ppr => g_ppr,
-- stb received
stb_received => s_stb_received,
REN => REN_in, ATN => ATN_in, IFC => IFC_in
);
gs: GpibStatusReg port map (
data_out => gs_data_out,
--------------------- gpib ---------------------
currentSecAddr => g_currentSecAddr,
att => g_att, tac => g_tac, atl => g_atl, lac => g_lac,
cwrc => g_cwrc, cwrd => g_cwrd, spa => g_spa,
isLocal => g_isLocal
);
gc: gpibControlReg port map (
reset => reset,
strobe => gc_strobe, data_in => gc_data_in,
data_out => gc_data_out,
------------------ gpib ------------------------
ltn => g_ltn, lun => g_lun, rtl => g_rtl, rsv => g_rsv,
ist => g_ist, lpe => g_lpe,
------------------------------------------------
rsc => g_rsc, sic => g_sic, sre => g_sre, gts => g_gts,
tcs => g_tcs, tca => g_tca, rpp => g_rpp, rec_stb => s_rec_stb
);
rc0: ReaderControlReg0 port map (
clk => clk, reset => reset,
strobe => rc0_strobe, data_in => rc0_data_in, data_out => rc0_data_out,
------------------- gpib -------------------------
buf_interrupt => r_buf_interrupt, data_available => r_data_available,
end_of_stream => r_end_of_stream, reset_buffer => r_reset_buffer,
dataSecAddr => r_dataSecAddr
);
rc1: ReaderControlReg1 port map (
data_out => rc1_data_out,
------------------ gpib --------------------
bytes_available_in_fifo => rm_availableBytesCount
);
wc0: WriterControlReg0 port map (
clk => clk, reset => reset,
strobe => wc0_strobe, data_in => wc0_data_in, data_out => wc0_data_out,
------------------- gpib -------------------------
buf_interrupt => w_buf_interrupt, data_available => w_data_available,
end_of_stream => w_end_of_stream, reset_buffer => w_reset_buffer,
dataSecAddr => w_dataSecAddr, status_byte => wc0_status_byte
);
wc1: WriterControlReg1 port map (
reset => reset,
strobe => wc1_strobe, data_in => wc1_data_in,
data_out => wc1_data_out,
------------------ gpib --------------------
bytes_available_in_fifo => wm_availableBytesCount
);
ig: InterruptGenerator port map (
reset => reset, clk => clk, interrupt => interrupt_line,
-------------------- gpib device ---------------------
isLocal => g_isLocal, in_buf_ready => r_buf_interrupt,
out_buf_ready => w_buf_interrupt, clr => g_clr, trg => g_trg,
att => g_att, atl => g_atl, spa => g_spa, cwrc => g_cwrc,
cwrd => g_cwrd, srq => g_sreq, ppr => g_ppr,
stb_received => s_stb_received, REN => REN_in, ATN => ATN_in,
IFC => IFC_in
);
rml: RegMultiplexer generic map (ADDR_WIDTH => 15) port map (
strobe_read => strobe_read, strobe_write => strobe_write,
data_in => data_in, data_out => data_out,
--------------------------------------------------------
reg_addr => reg_addr,
--------------------------------------------------------
reg_strobe_0 => set0_strobe,
reg_in_0 => set0_data_in, reg_out_0 => set0_data_out,
reg_strobe_1 => set1_strobe,
reg_in_1 => set1_data_in, reg_out_1 => set1_data_out,
reg_strobe_2 => sec0_strobe,
reg_in_2 => sec0_data_in, reg_out_2 => sec0_data_out,
reg_strobe_3 => sec1_strobe,
reg_in_3 => sec1_data_in, reg_out_3 => sec1_data_out,
--reg_strobe_4 =>
--reg_in_4 =>
reg_out_4 => gbs_data_out,
reg_strobe_5 => ev_strobe,
reg_in_5 => ev_data_in, reg_out_5 => ev_data_out,
--reg_strobe_6 =>
--reg_in_6 =>
reg_out_6 => gs_data_out,
reg_strobe_7 => gc_strobe,
reg_in_7 => gc_data_in, reg_out_7 => gc_data_out,
reg_strobe_8 => rc0_strobe,
reg_in_8 => rc0_data_in, reg_out_8 => rc0_data_out,
--reg_strobe_9 => rc1_strobe,
--reg_in_9 => rc1_data_in,
reg_out_9 => rc1_data_out,
reg_strobe_10 => wc0_strobe,
reg_in_10 => wc0_data_in, reg_out_10 => wc0_data_out,
reg_strobe_11 => wc1_strobe,
reg_in_11 => wc1_data_in, reg_out_11 => wc1_data_out,
reg_strobe_other0 => rm_strobe_read,
--reg_in_other0 => ,
reg_out_other0 => rm_byte_out,
reg_strobe_other1 => wm_write_strobe,
reg_in_other1 => wm_data_in,
reg_out_other1 => "0000000000000000"
);
end arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:03:35 11/02/2009
-- Design Name:
-- Module Name: etapas - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity montgomery_mult is
port(
clk : in std_logic;
reset : in std_logic;
valid_in : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
n : in std_logic_vector(15 downto 0);
s_prev : in std_logic_vector(15 downto 0);
n_c : in std_logic_vector(15 downto 0);
s : out std_logic_vector( 15 downto 0);
valid_out : out std_logic -- es le valid out TODO : cambiar nombre
);
end montgomery_mult;
architecture Behavioral of montgomery_mult is
component montgomery_step is
port(
clk : in std_logic;
reset : in std_logic;
valid_in : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
n : in std_logic_vector(15 downto 0);
s_prev : in std_logic_vector(15 downto 0);
n_c : in std_logic_vector(15 downto 0);
s : out std_logic_vector( 15 downto 0);
valid_out : out std_logic; -- es le valid out TODO : cambiar nombre
busy : out std_logic;
b_req : out std_logic;
a_out : out std_logic_vector(15 downto 0);
n_out : out std_logic_vector(15 downto 0); --señal que indica que el modulo está ocupado y no puede procesar nuevas peticiones
c_step : out std_logic; --genera un pulso cuando termina su computo para avisar al modulo superior
stop : in std_logic
);
end component;
component fifo_512_bram
port (
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(15 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(15 downto 0);
full : out std_logic;
empty : out std_logic);
end component;
component fifo_256_feedback
port (
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(48 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(48 downto 0);
full : out std_logic;
empty : out std_logic);
end component;
type arr_dat_out is array(0 to 7) of std_logic_vector(15 downto 0);
type arr_val is array(0 to 7) of std_logic;
type arr_b is array(0 to 7) of std_logic_vector(15 downto 0);
signal b_reg, next_b_reg : arr_b;
signal valid_mid, fifo_reqs, fifo_reqs_reg, next_fifo_reqs_reg, stops : arr_val;
signal a_out_mid, n_out_mid, s_out_mid : arr_dat_out; --std_logic_vector(15 downto 0);
--Señales a la fifo
signal wr_en, rd_en, empty : std_logic;
signal fifo_out : std_logic_vector(15 downto 0);
signal fifo_out_feedback, fifo_in_feedback : std_logic_vector(48 downto 0);
signal read_fifo_feedback, empty_feedback : std_logic;
--Señales de entrada al primer PE
signal a_in, s_in, n_in : std_logic_vector(15 downto 0);
signal f_valid, busy_pe : std_logic;
--salida c_step del primer PE para ir contando y saber cuando sacar el valor correcto.
signal c_step, reg_c_step : std_logic;
--contador para saber cuando coño acabamos :)
signal count, next_count : std_logic_vector(7 downto 0);
--señal para escribir el loopback en la fifo de entrada de feedback
signal wr_fifofeed : std_logic;
type state_type is (rst_fifos, wait_start, process_data, dump_feed);
signal state, next_state : state_type;
signal reg_busy : std_logic;
signal reset_fifos : std_logic;
signal count_feedback, next_count_feedback : std_logic_vector(15 downto 0);
begin
--Fifo para almacenar b
fifo_b : fifo_512_bram port map (
clk => clk,
rst => reset_fifos,
din => b,
wr_en => wr_en,
rd_en => rd_en,
dout => fifo_out,
empty => empty
);
--Fifo para el feedback al primer PE
fifo_feed : fifo_256_feedback port map (
clk => clk,
rst => reset_fifos,
din => fifo_in_feedback,
wr_en => wr_fifofeed,
rd_en => read_fifo_feedback,
dout => fifo_out_feedback,
empty => empty_feedback
);
--Primer PE
et_first : montgomery_step port map(
clk => clk,
reset => reset,
valid_in => f_valid,
a => a_in,
b => b_reg(0),
n => n_in,
s_prev => s_in,
n_c => n_c,
s => s_out_mid(0),
valid_out => valid_mid(0),
busy => busy_pe,
b_req => fifo_reqs(0),
a_out => a_out_mid(0),
n_out => n_out_mid(0),
c_step => c_step,
stop => stops(0)
);
--Ultimo PE
et_last : montgomery_step port map(
clk => clk,
reset => reset,
valid_in => valid_mid(6),
a => a_out_mid(6),
b => b_reg(7),
n => n_out_mid(6),
s_prev => s_out_mid(6),
n_c => n_c,
s => s_out_mid(7),
valid_out => valid_mid(7),
b_req => fifo_reqs(7),
a_out => a_out_mid(7),
n_out => n_out_mid(7),
stop => stops(7)
);
g1 : for i in 1 to 6 generate
et_i : montgomery_step port map(
clk => clk,
reset => reset,
valid_in => valid_mid(i-1),
a => a_out_mid(i-1),
b => b_reg(i),
n => n_out_mid(i-1),
s_prev => s_out_mid(i-1),
n_c => n_c,
s => s_out_mid(i),
valid_out => valid_mid(i),
b_req => fifo_reqs(i),
a_out => a_out_mid(i),
n_out => n_out_mid(i),
stop => stops(i)
);
end generate g1;
process(clk, reset)
begin
if(clk = '1' and clk'event) then
if(reset = '1')then
state <= wait_start;
count_feedback <= (others => '0');
reg_busy <= '0';
for i in 0 to 7 loop
b_reg(i) <= (others => '0');
fifo_reqs_reg (i) <= '0';
count <= (others => '0');
reg_c_step <= '0';
end loop;
else
state <= next_state;
reg_busy <= busy_pe;
count_feedback <= next_count_feedback;
for i in 0 to 7 loop
b_reg(i) <= next_b_reg(i);
fifo_reqs_reg (i) <= next_fifo_reqs_reg(i);
count <= next_count;
reg_c_step <= c_step;
end loop;
end if;
end if;
end process;
--Proceso combinacional que controla las lecturas a la fifo
process(fifo_reqs_reg, fifo_out, b, fifo_reqs, b_reg, state, empty)
begin
for i in 0 to 7 loop
next_b_reg(i) <= b_reg(i);
next_fifo_reqs_reg(i) <= fifo_reqs(i);
end loop;
if(state = wait_start) then
next_b_reg(0) <= b;
next_fifo_reqs_reg(0) <= '0'; --anulamos la peticion de b
for i in 1 to 7 loop
next_b_reg(i) <= (others => '0');
next_fifo_reqs_reg(i) <= '0';
end loop;
else
for i in 0 to 7 loop
if(fifo_reqs_reg(i) = '1' and empty = '0') then
next_b_reg(i) <= fifo_out;
end if;
end loop;
end if;
end process;
--Proceso combinacional fsm principal
process( valid_in, b, state, fifo_reqs, a_out_mid, n_out_mid, s_out_mid, valid_mid, a, s_prev, n, busy_pe, empty_feedback, fifo_out_feedback, count, reg_c_step, reset, reg_busy, count_feedback )
begin
--las peticiones a la fifo son las or de los modulos
rd_en <= fifo_reqs(0) or fifo_reqs(1) or fifo_reqs(2) or fifo_reqs(3) or fifo_reqs(4) or fifo_reqs(5) or fifo_reqs(6) or fifo_reqs(7);
next_state <= state;
wr_en <= '0';
fifo_in_feedback <= a_out_mid(7)&n_out_mid(7)&s_out_mid(7)&valid_mid(7);
read_fifo_feedback <= '0';
wr_fifofeed <= '0';
--Controlamos el primer PE
a_in <= a;
s_in <= s_prev;
n_in <= n;
f_valid <= valid_in;
reset_fifos <= reset;
--ponemos las salidas
s <= (others => '0');
valid_out <= '0';
--Incrementamos el contador solo cuando el primer PE termina su cuenta
next_count <= count;
next_count_feedback <= count_feedback;
--El contador solo se incrementa una vez por ciclo de la pipeline, así me evito que cada PE lo incremente
if(reg_c_step = '1') then
next_count <= count + 8;
end if;
--durante el ciclo de la pipeline que sea considerado el ultimo, sacamos los datos
if( count = x"20") then
s <= s_out_mid(0);
valid_out <= valid_mid(0);
end if;
for i in 0 to 7 loop
stops(i) <= '0';
end loop;
case state is
--Esperamos a que tengamos un input y vamos cargando las b's
when wait_start =>
--reset_fifos <= '1';
if(valid_in = '1') then
reset_fifos <= '0';
--next_b_reg(0) <= b;
next_state <= process_data;
--wr_en <= '1';
end if;
when process_data =>
wr_fifofeed <= valid_mid(7);
if(valid_in = '1') then
wr_en <= '1';
end if;
--Miramos si hay que volver a meter datos a la b
if(empty_feedback = '0' and reg_busy = '0') then
read_fifo_feedback <= '1';
next_state <= dump_feed;
next_count_feedback <= x"0000";
end if;
--Si ya hemos sobrepasado el limite paramos y volvemos a la espera
if( count > x"23") then
next_state <= wait_start;
--y
for i in 0 to 7 loop
stops(i) <= '1';
end loop;
next_count <= (others => '0');
end if;
--Vacia la fifo de feedback
when dump_feed =>
if(empty_feedback = '0')
then
next_count_feedback <= count_feedback+1;
end if;
wr_fifofeed <= valid_mid(7);
read_fifo_feedback <= '1';
a_in <= fifo_out_feedback(48 downto 33);
n_in <= fifo_out_feedback(32 downto 17);
s_in <= fifo_out_feedback(16 downto 1);
f_valid <= fifo_out_feedback(0);
if(empty_feedback = '1') then
next_state <= process_data;
end if;
if(count_feedback = x"22") then
read_fifo_feedback <= '0';
next_state <= process_data;
end if;
when rst_fifos =>
next_state <= wait_start;
reset_fifos <= '1';
end case;
end process;
end Behavioral;
|
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A.
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 1-408-826-6000 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: techsupport@latticesemi.com
--
-- --------------------------------------------------------------------
--
-- Simulation Library File for EC/XP
--
-- $Header: G:\\CVS_REPOSITORY\\CVS_MACROS/LEON3SDE/ALTERA/grlib-eval-1.0.4/lib/tech/ec/ec/ORCACOMP.vhd,v 1.1 2005/12/06 13:00:22 tame Exp $
--
---
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE components IS
function str2std(L: string) return std_logic_vector;
function Str2int( L : string) return integer;
function Str2real( L : string) return REAL;
-----functions for Multipliers (for ECP)----------
function INT2VEC(INT: INTEGER; BWIDTH: INTEGER) RETURN STD_LOGIC_VECTOR;
function VEC2INT(v: std_logic_vector) return integer;
function ADDVECT(A, B: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
function SUBVECT(A, B: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
function TSCOMP(VECT: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
function BITX (VECT: std_logic) return boolean;
function VECX (VECT: std_logic_vector) return boolean;
--
COMPONENT ageb2
PORT(
a0, a1: IN std_logic := 'X';
b0, b1: IN std_logic := 'X';
ci: IN std_logic := 'X';
ge: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT aleb2
PORT(
a0, a1: IN std_logic := 'X';
b0, b1: IN std_logic := 'X';
ci: IN std_logic := 'X';
le: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT aneb2
PORT(
a0, a1: IN std_logic := 'X';
b0, b1: IN std_logic := 'X';
ci: IN std_logic := 'X';
ne: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT and2
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT and3
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT and4
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT and5
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
e: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT cd2
PORT(
ci : IN std_logic := 'X';
pc0, pc1 : IN std_logic := 'X';
co : OUT std_logic := 'X';
nc0, nc1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT cu2
PORT(
ci : IN std_logic := 'X';
pc0, pc1 : IN std_logic := 'X';
co : OUT std_logic := 'X';
nc0, nc1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT cb2
PORT(
ci : IN std_logic := 'X';
pc0, pc1 : IN std_logic := 'X';
con: IN std_logic := 'X';
co : OUT std_logic := 'X';
nc0, nc1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb2p3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb2p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb2p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb2p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb2p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb2p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb4p3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb4p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb4p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb4p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb4p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb4p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld2p3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld2p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld2p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld2p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld2p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld2p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu2p3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu2p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu2p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu2p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu2p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu2p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld4p3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld4p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld4p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld4p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld4p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld4p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu4p3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu4p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu4p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu4p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu4p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu4p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fadd2
PORT(
a0, a1 : IN std_logic := 'X';
b0, b1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
cout0, cout1 : OUT std_logic := 'X';
s0, s1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fsub2
PORT(
a0, a1 : IN std_logic := 'X';
b0, b1 : IN std_logic := 'X';
bi: IN std_logic := 'X';
bout0, bout1 : OUT std_logic := 'X';
s0, s1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fadsu2
PORT(
a0, a1 : IN std_logic := 'X';
b0, b1 : IN std_logic := 'X';
bci: IN std_logic := 'X';
con: IN std_logic := 'X';
bco: OUT std_logic := 'X';
s0, s1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s1a
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s1ay
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s1b
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s1d
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s1i
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s1j
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1p3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d: IN std_logic := 'X';
ck: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1p3az
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1p3iy
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1p3jy
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s1a
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s1ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s1b
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s1d
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s1i
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s1j
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT gsr
PORT(
gsr: IN std_logic := 'X'
);
END COMPONENT;
--
COMPONENT inv
PORT(
a: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp : IN std_logic := 'X';
sclk: IN std_logic := 'X';
pd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp : IN std_logic := 'X';
sclk: IN std_logic := 'X';
cd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp : IN std_logic := 'X';
sclk: IN std_logic := 'X';
cd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp : IN std_logic := 'X';
sclk: IN std_logic := 'X';
pd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1s1b
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sclk: IN std_logic := 'X';
pd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1s1d
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sclk: IN std_logic := 'X';
cd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1s1i
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sclk: IN std_logic := 'X';
cd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1s1j
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sclk: IN std_logic := 'X';
pd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT mux21
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sd: IN std_logic := 'X';
z : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT l6mux21
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sd: IN std_logic := 'X';
z : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT mux41
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
d2: IN std_logic := 'X';
d3: IN std_logic := 'X';
sd1: IN std_logic := 'X';
sd2: IN std_logic := 'X';
z : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT mux81
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
d2: IN std_logic := 'X';
d3: IN std_logic := 'X';
d4: IN std_logic := 'X';
d5: IN std_logic := 'X';
d6: IN std_logic := 'X';
d7: IN std_logic := 'X';
sd1: IN std_logic := 'X';
sd2: IN std_logic := 'X';
sd3: IN std_logic := 'X';
z : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT mux161
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
d2: IN std_logic := 'X';
d3: IN std_logic := 'X';
d4: IN std_logic := 'X';
d5: IN std_logic := 'X';
d6: IN std_logic := 'X';
d7: IN std_logic := 'X';
d8: IN std_logic := 'X';
d9: IN std_logic := 'X';
d10: IN std_logic := 'X';
d11: IN std_logic := 'X';
d12: IN std_logic := 'X';
d13: IN std_logic := 'X';
d14: IN std_logic := 'X';
d15: IN std_logic := 'X';
sd1: IN std_logic := 'X';
sd2: IN std_logic := 'X';
sd3: IN std_logic := 'X';
sd4: IN std_logic := 'X';
z : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT mux321
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
d2: IN std_logic := 'X';
d3: IN std_logic := 'X';
d4: IN std_logic := 'X';
d5: IN std_logic := 'X';
d6: IN std_logic := 'X';
d7: IN std_logic := 'X';
d8: IN std_logic := 'X';
d9: IN std_logic := 'X';
d10: IN std_logic := 'X';
d11: IN std_logic := 'X';
d12: IN std_logic := 'X';
d13: IN std_logic := 'X';
d14: IN std_logic := 'X';
d15: IN std_logic := 'X';
d16: IN std_logic := 'X';
d17: IN std_logic := 'X';
d18: IN std_logic := 'X';
d19: IN std_logic := 'X';
d20: IN std_logic := 'X';
d21: IN std_logic := 'X';
d22: IN std_logic := 'X';
d23: IN std_logic := 'X';
d24: IN std_logic := 'X';
d25: IN std_logic := 'X';
d26: IN std_logic := 'X';
d27: IN std_logic := 'X';
d28: IN std_logic := 'X';
d29: IN std_logic := 'X';
d30: IN std_logic := 'X';
d31: IN std_logic := 'X';
sd1: IN std_logic := 'X';
sd2: IN std_logic := 'X';
sd3: IN std_logic := 'X';
sd4: IN std_logic := 'X';
sd5: IN std_logic := 'X';
z : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nd2
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nd3
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nd4
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nd5
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
e: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nr2
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nr3
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nr4
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nr5
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
e: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofe1p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
eclk: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofe1p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
eclk: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofe1p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
eclk: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofe1p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
eclk: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofs1p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
sclk: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofs1p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
sclk: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofs1p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
sclk: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofs1p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
sclk: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT or2
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT or3
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT or4
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT or5
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
e: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT pfumx
PORT(
alut: IN std_logic := 'X';
blut: IN std_logic := 'X';
c0 : IN std_logic := 'X';
z : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT pur
PORT(
pur: IN std_logic := 'X'
);
END COMPONENT;
--
COMPONENT rom32x1
GENERIC(
initval : string := "0x00000000"
);
PORT(
ad0, ad1, ad2, ad3, ad4: IN std_logic := 'X';
do0: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT rom16x1
GENERIC(
initval : string := "0x0000"
);
PORT(
ad0, ad1, ad2, ad3: IN std_logic := 'X';
do0: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT rom64x1
GENERIC(
initval : string := "0x0000000000000000"
);
PORT(
ad0, ad1, ad2, ad3, ad4, ad5 : IN std_logic := 'X';
do0: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT rom128x1
GENERIC(
initval : string := "0x00000000000000000000000000000000"
);
PORT(
ad0, ad1, ad2, ad3, ad4, ad5, ad6 : IN std_logic := 'X';
do0: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT rom256x1
GENERIC(
initval : string := "0x0000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7 : IN std_logic := 'X';
do0: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT strtup
PORT(
uclk : IN std_logic := 'X'
);
END COMPONENT;
--
COMPONENT tsall
PORT(
tsall: IN std_logic := 'X'
);
END COMPONENT;
--
COMPONENT vhi
PORT(
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT vlo
PORT(
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xor2
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xor3
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xor4
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xor5
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
e: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xor11
PORT(
a, b, c, d, e, f, g, h, i, j, k: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xor21
PORT(
a, b, c, d, e, f, g, h, i, j, k: IN std_logic := 'X';
l, m, n, o, p, q, r, s, t, u: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xnor2
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xnor3
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xnor4
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xnor5
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
e: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT bufba
PORT(
a: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
--
COMPONENT pdp8ka
GENERIC(
DATA_WIDTH_W : in Integer := 18;
DATA_WIDTH_R : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_W : String := "000";
CSDECODE_R : String := "000";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
di18, di19, di20, di21, di22, di23, di24, di25, di26 : in std_logic := 'X';
di27, di28, di29, di30, di31, di32, di33, di34, di35 : in std_logic := 'X';
adw0, adw1, adw2, adw3, adw4, adw5, adw6, adw7, adw8 : in std_logic := 'X';
adw9, adw10, adw11, adw12 : in std_logic := 'X';
cew, clkw, we, csw0, csw1, csw2 : in std_logic := 'X';
adr0, adr1, adr2, adr3, adr4, adr5, adr6, adr7, adr8 : in std_logic := 'X';
adr9, adr10, adr11, adr12 : in std_logic := 'X';
cer, clkr, csr0, csr1, csr2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X';
do18, do19, do20, do21, do22, do23, do24, do25, do26 : out std_logic := 'X';
do27, do28, do29, do30, do31, do32, do33, do34, do35 : out std_logic := 'X'
);
END COMPONENT;
--
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
--
COMPONENT bbw
PORT(
b: INOUT std_logic := 'X';
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT obw
PORT(
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT ilvds
PORT(
a : IN std_logic := 'X';
an: IN std_logic := 'X';
z : OUT std_logic
);
END COMPONENT;
--
COMPONENT olvds
PORT(
a : IN std_logic := 'X';
z : OUT std_logic ;
zn : OUT std_logic
);
END COMPONENT;
--
COMPONENT bb
PORT(
b: INOUT std_logic := 'X';
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT bbpd
PORT(
b: INOUT std_logic := 'X';
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT bbpu
PORT(
b: INOUT std_logic := 'X';
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT ib
PORT(
i: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT ibpd
PORT(
i: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT ibpu
PORT(
i: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT ob
PORT(
i: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT obz
PORT(
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT obzpd
PORT(
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT obzpu
PORT(
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT dcs
GENERIC(
DCSMODE : String := "POS");
PORT(
clk0 : IN std_logic;
clk1 : IN std_logic;
sel : IN std_logic;
dcsout : OUT std_logic);
END COMPONENT;
--
component EPLLB
generic(
FIN : string := "100.0";
CLKI_DIV : string := "1";
CLKOP_DIV : string := "8";
CLKFB_DIV : string := "1";
FDEL : string := "1";
FB_MODE : string := "CLOCKTREE";
WAKE_ON_LOCK : string := "off");
port(
CLKI : in STD_ULOGIC;
RST : in STD_ULOGIC;
CLKFB : in STD_ULOGIC;
CLKOP : out STD_ULOGIC;
LOCK : out STD_ULOGIC
);
end component;
--
component EHXPLLB
generic(
FIN : string := "100.0";
CLKI_DIV : string := "1";
CLKOP_DIV : string := "1";
CLKFB_DIV : string := "1";
FDEL : string := "1";
FB_MODE : string := "CLOCKTREE";
CLKOK_DIV : string := "2";
WAKE_ON_LOCK : string := "off";
DELAY_CNTL : string := "STATIC";
PHASEADJ : string := "0";
DUTY : string := "4");
port(
CLKI : in STD_ULOGIC;
CLKFB : in STD_ULOGIC;
RST : in STD_ULOGIC := '0';
DDAMODE : in STD_ULOGIC;
DDAIZR : in STD_ULOGIC;
DDAILAG : in STD_ULOGIC;
DDAIDEL0 : in STD_ULOGIC;
DDAIDEL1 : in STD_ULOGIC;
DDAIDEL2 : in STD_ULOGIC;
CLKOP : out STD_ULOGIC;
CLKOS : out STD_ULOGIC;
CLKOK : out STD_ULOGIC;
LOCK : out STD_ULOGIC;
DDAOZR : out STD_ULOGIC;
DDAOLAG : out STD_ULOGIC;
DDAODEL0 : out STD_ULOGIC;
DDAODEL1 : out STD_ULOGIC;
DDAODEL2 : out STD_ULOGIC
);
end component;
--
------Component ORCALUT4------
component ORCALUT4
generic( INIT : bit_vector);
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Z : out STD_ULOGIC
);
end component;
------Component ORCALUT5------
component ORCALUT5
generic( INIT : bit_vector);
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
Z : out STD_ULOGIC
);
end component;
------Component ORCALUT6------
component ORCALUT6
generic( INIT : bit_vector);
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
F : in STD_ULOGIC;
Z : out STD_ULOGIC
);
end component;
------Component ORCALUT7------
component ORCALUT7
generic( INIT : bit_vector);
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
F : in STD_ULOGIC;
G : in STD_ULOGIC;
Z : out STD_ULOGIC
);
end component;
------Component ORCALUT8------
component ORCALUT8
generic( INIT : bit_vector);
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
F : in STD_ULOGIC;
G : in STD_ULOGIC;
H : in STD_ULOGIC;
Z : out STD_ULOGIC
);
end component;
--
component MULT2
port(
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
B0 : in STD_ULOGIC;
B1 : in STD_ULOGIC;
B2 : in STD_ULOGIC;
B3 : in STD_ULOGIC;
CI : in STD_ULOGIC;
P0 : out STD_ULOGIC;
P1 : out STD_ULOGIC;
CO : out STD_ULOGIC);
end component;
--
component IDDRXB
generic( REGSET : string := "RESET");
port(
D : in STD_LOGIC;
ECLK : in STD_LOGIC;
SCLK : in STD_LOGIC;
LSR : in STD_LOGIC;
CE : in STD_LOGIC;
DDRCLKPOL : in STD_LOGIC;
QA : out STD_LOGIC;
QB : out STD_LOGIC
);
end component;
--
component ODDRXB
generic( REGSET : string := "RESET");
port(
DA : in STD_LOGIC;
DB : in STD_LOGIC;
CLK : in STD_LOGIC;
LSR : in STD_LOGIC;
Q : out STD_LOGIC
);
end component;
--
component CCU2
generic (
inject1_0 : string := "YES";
inject1_1 : string := "YES";
init0: string := "0x0000";
init1: string := "0x0000"
);
port (
A0,A1 : in std_ulogic;
B0,B1 : in std_ulogic;
C0,C1 : in std_ulogic;
D0,D1 : in std_ulogic;
CIN : in std_ulogic;
S0,S1 : out std_ulogic;
COUT0,COUT1 : out std_ulogic
);
end component;
--
component DQSBUFB
generic(DEL_ADJ : string := "PLUS";
DEL_VAL : string := "0");
port(
DQSI : in STD_LOGIC;
CLK : in STD_LOGIC;
READ : in STD_LOGIC;
DQSDEL : in STD_LOGIC;
DQSO : out STD_LOGIC;
DDRCLKPOL : out STD_LOGIC;
DQSC : out STD_LOGIC;
PRMBDET : out STD_LOGIC
);
end component;
--
component DQSDLL
generic(DEL_ADJ : string := "PLUS";
DEL_VAL : string := "0";
LOCK_SENSITIVITY : string := "LOW");
port(
CLK : in STD_ULOGIC;
RST : in STD_ULOGIC;
UDDCNTL : in STD_ULOGIC;
LOCK : out STD_ULOGIC;
DQSDEL : out STD_ULOGIC
);
end component;
--
-- 18x18 MULT for ECP
component MULT18X18
generic(
REG_INPUTA_CLK : string := "NONE";
REG_INPUTA_CE : string := "CE0";
REG_INPUTA_RST : string := "RST0";
REG_INPUTB_CLK : string := "NONE";
REG_INPUTB_CE : string := "CE0";
REG_INPUTB_RST : string := "RST0";
REG_PIPELINE_CLK : string := "NONE";
REG_PIPELINE_CE : string := "CE0";
REG_PIPELINE_RST : string := "RST0";
REG_OUTPUT_CLK : string := "NONE";
REG_OUTPUT_CE : string := "CE0";
REG_OUTPUT_RST : string := "RST0";
REG_SIGNEDAB_0_CLK : string := "NONE";
REG_SIGNEDAB_0_CE : string := "CE0";
REG_SIGNEDAB_0_RST : string := "RST0";
REG_SIGNEDAB_1_CLK : string := "NONE";
REG_SIGNEDAB_1_CE : string := "CE0";
REG_SIGNEDAB_1_RST : string := "RST0";
SHIFT_IN_A : string := "FALSE";
SHIFT_IN_B : string := "FALSE";
GSR : string := "ENABLED");
port (
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
A4 : in STD_ULOGIC;
A5 : in STD_ULOGIC;
A6 : in STD_ULOGIC;
A7 : in STD_ULOGIC;
A8 : in STD_ULOGIC;
A9 : in STD_ULOGIC;
A10 : in STD_ULOGIC;
A11 : in STD_ULOGIC;
A12 : in STD_ULOGIC;
A13 : in STD_ULOGIC;
A14 : in STD_ULOGIC;
A15 : in STD_ULOGIC;
A16 : in STD_ULOGIC;
A17 : in STD_ULOGIC;
SRIA0 : in STD_ULOGIC;
SRIA1 : in STD_ULOGIC;
SRIA2 : in STD_ULOGIC;
SRIA3 : in STD_ULOGIC;
SRIA4 : in STD_ULOGIC;
SRIA5 : in STD_ULOGIC;
SRIA6 : in STD_ULOGIC;
SRIA7 : in STD_ULOGIC;
SRIA8 : in STD_ULOGIC;
SRIA9 : in STD_ULOGIC;
SRIA10 : in STD_ULOGIC;
SRIA11 : in STD_ULOGIC;
SRIA12 : in STD_ULOGIC;
SRIA13 : in STD_ULOGIC;
SRIA14 : in STD_ULOGIC;
SRIA15 : in STD_ULOGIC;
SRIA16 : in STD_ULOGIC;
SRIA17 : in STD_ULOGIC;
B0 : in STD_ULOGIC;
B1 : in STD_ULOGIC;
B2 : in STD_ULOGIC;
B3 : in STD_ULOGIC;
B4 : in STD_ULOGIC;
B5 : in STD_ULOGIC;
B6 : in STD_ULOGIC;
B7 : in STD_ULOGIC;
B8 : in STD_ULOGIC;
B9 : in STD_ULOGIC;
B10 : in STD_ULOGIC;
B11 : in STD_ULOGIC;
B12 : in STD_ULOGIC;
B13 : in STD_ULOGIC;
B14 : in STD_ULOGIC;
B15 : in STD_ULOGIC;
B16 : in STD_ULOGIC;
B17 : in STD_ULOGIC;
SRIB0 : in STD_ULOGIC;
SRIB1 : in STD_ULOGIC;
SRIB2 : in STD_ULOGIC;
SRIB3 : in STD_ULOGIC;
SRIB4 : in STD_ULOGIC;
SRIB5 : in STD_ULOGIC;
SRIB6 : in STD_ULOGIC;
SRIB7 : in STD_ULOGIC;
SRIB8 : in STD_ULOGIC;
SRIB9 : in STD_ULOGIC;
SRIB10 : in STD_ULOGIC;
SRIB11 : in STD_ULOGIC;
SRIB12 : in STD_ULOGIC;
SRIB13 : in STD_ULOGIC;
SRIB14 : in STD_ULOGIC;
SRIB15 : in STD_ULOGIC;
SRIB16 : in STD_ULOGIC;
SRIB17 : in STD_ULOGIC;
SIGNEDAB : in STD_ULOGIC;
CE0 : in STD_ULOGIC;
CE1 : in STD_ULOGIC;
CE2 : in STD_ULOGIC;
CE3 : in STD_ULOGIC;
CLK0 : in STD_ULOGIC;
CLK1 : in STD_ULOGIC;
CLK2 : in STD_ULOGIC;
CLK3 : in STD_ULOGIC;
RST0 : in STD_ULOGIC;
RST1 : in STD_ULOGIC;
RST2 : in STD_ULOGIC;
RST3 : in STD_ULOGIC;
SROA0 : out STD_ULOGIC;
SROA1 : out STD_ULOGIC;
SROA2 : out STD_ULOGIC;
SROA3 : out STD_ULOGIC;
SROA4 : out STD_ULOGIC;
SROA5 : out STD_ULOGIC;
SROA6 : out STD_ULOGIC;
SROA7 : out STD_ULOGIC;
SROA8 : out STD_ULOGIC;
SROA9 : out STD_ULOGIC;
SROA10 : out STD_ULOGIC;
SROA11 : out STD_ULOGIC;
SROA12 : out STD_ULOGIC;
SROA13 : out STD_ULOGIC;
SROA14 : out STD_ULOGIC;
SROA15 : out STD_ULOGIC;
SROA16 : out STD_ULOGIC;
SROA17 : out STD_ULOGIC;
SROB0 : out STD_ULOGIC;
SROB1 : out STD_ULOGIC;
SROB2 : out STD_ULOGIC;
SROB3 : out STD_ULOGIC;
SROB4 : out STD_ULOGIC;
SROB5 : out STD_ULOGIC;
SROB6 : out STD_ULOGIC;
SROB7 : out STD_ULOGIC;
SROB8 : out STD_ULOGIC;
SROB9 : out STD_ULOGIC;
SROB10 : out STD_ULOGIC;
SROB11 : out STD_ULOGIC;
SROB12 : out STD_ULOGIC;
SROB13 : out STD_ULOGIC;
SROB14 : out STD_ULOGIC;
SROB15 : out STD_ULOGIC;
SROB16 : out STD_ULOGIC;
SROB17 : out STD_ULOGIC;
P0 : out STD_ULOGIC;
P1 : out STD_ULOGIC;
P2 : out STD_ULOGIC;
P3 : out STD_ULOGIC;
P4 : out STD_ULOGIC;
P5 : out STD_ULOGIC;
P6 : out STD_ULOGIC;
P7 : out STD_ULOGIC;
P8 : out STD_ULOGIC;
P9 : out STD_ULOGIC;
P10 : out STD_ULOGIC;
P11 : out STD_ULOGIC;
P12 : out STD_ULOGIC;
P13 : out STD_ULOGIC;
P14 : out STD_ULOGIC;
P15 : out STD_ULOGIC;
P16 : out STD_ULOGIC;
P17 : out STD_ULOGIC;
P18 : out STD_ULOGIC;
P19 : out STD_ULOGIC;
P20 : out STD_ULOGIC;
P21 : out STD_ULOGIC;
P22 : out STD_ULOGIC;
P23 : out STD_ULOGIC;
P24 : out STD_ULOGIC;
P25 : out STD_ULOGIC;
P26 : out STD_ULOGIC;
P27 : out STD_ULOGIC;
P28 : out STD_ULOGIC;
P29 : out STD_ULOGIC;
P30 : out STD_ULOGIC;
P31 : out STD_ULOGIC;
P32 : out STD_ULOGIC;
P33 : out STD_ULOGIC;
P34 : out STD_ULOGIC;
P35 : out STD_ULOGIC
);
end component;
end Components;
package body Components is
function str2std(L: string) return std_logic_vector is
variable vpos : integer := 0; -- Index of last valid bit in val.
variable lpos : integer; -- Index of next unused char in L.
variable val : std_logic_vector(1 to L'right); -- lenth of the vector.
begin
lpos := L'left;
while lpos <= L'right and vpos < VAL'length loop
if L(lpos) = '0' then
vpos := vpos + 1;
val(vpos) := '0';
elsif L(lpos) = '1' then
vpos := vpos + 1;
val(vpos) := '1';
else
exit; -- Bit values must be '0' or '1'.
end if;
lpos := lpos + 1;
end loop;
return val;
end str2std;
function str2int( L : string) return integer is
variable ok: boolean;
variable pos: integer:=1;
variable sign: integer := 1;
variable rval: integer := 0;
variable value: integer := 0;
begin
ok := FALSE;
if pos < L'right and (L(pos) = '-' or L(pos) = '+') then
if L(pos) = '-' then
sign := -1;
end if;
pos := pos + 1;
end if;
-- Once the optional leading sign is removed, an integer can
-- contain only the digits '0' through '9' and the '_'
-- (underscore) character. VHDL disallows two successive
-- underscores, and leading or trailing underscores.
if pos <= L'right and L(pos) >= '0' and L(pos) <= '9' then
while pos <= L'right loop
if L(pos) >= '0' and L(pos) <= '9' then
rval := rval * 10
+ character'pos(L(pos)) - character'pos('0');
ok := TRUE;
elsif L(pos) = '_' then
if pos = L'right
or L(pos + 1) < '0'
or L(pos + 1) > '9' then
ok := FALSE;
exit;
end if;
else
exit;
end if;
pos := pos + 1;
end loop;
end if;
value := sign * rval;
RETURN(value);
end str2int;
function str2real( L: string) return real is
variable pos: integer;
variable value: real;
variable ok: boolean;
variable sign: real := 1.0;
variable rval: real := 0.0;
variable powerten: real := 0.1;
begin
pos := L'left;
if (pos <= L'right) and (L(pos) = '-') then
sign := -1.0;
pos := pos + 1;
end if;
ok := FALSE;
rval := 0.0;
if pos <= L'right and L(pos) >= '0' and L(pos) <= '9' then
while pos <= L'right and L(pos) /= '.' and L(pos) /= ' ' and L(pos) /= HT
loop
if L(pos) >= '0' and L(pos) <= '9' then
rval := rval*10.0 + real(character'pos(L(pos)) - character'pos('0'));
pos := pos+1;
ok := true;
else
ok := false;
exit;
end if;
end loop;
end if;
if ok and pos <= L'right and L(pos) = '.' then
pos := pos + 1;
end if;
if pos <= L'right then
while pos <= L'right and ((L(pos) >= '0' and L(pos) <= '9') or L(pos) = '_') loop
rval := rval + (real(character'pos(L(pos))-character'pos('0'))*powerten);
powerten := powerten*0.1;
pos := pos+1;
ok := true;
end loop;
end if;
if ok then
value := rval * sign;
end if;
return (value);
end str2real;
function INT2VEC(INT: INTEGER; BWIDTH: INTEGER) RETURN STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (BWIDTH-1 downto 0);
variable tmp : integer := INT;
begin
tmp := INT;
for i in 0 to BWIDTH-1 loop
if (tmp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if tmp > 0 then
tmp := tmp /2 ;
elsif (tmp > integer'low) then
tmp := (tmp-1) / 2;
else
tmp := tmp / 2;
end if;
end loop;
return result;
end;
function VEC2INT(v: std_logic_vector) return integer is
variable result: integer := 0;
variable addition: integer := 1;
begin
for b in v'reverse_range loop
if v(b) = '1' then
result := result + addition;
end if;
addition := addition * 2;
end loop;
return result;
end VEC2INT;
function VECX (VECT: std_logic_vector) return boolean is
begin
for b in VECT'range loop
if bitX (VECT (b)) then
return true;
end if;
end loop;
return false;
end VECX;
function TSCOMP(VECT: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (VECT'left downto 0);
variable is1 : std_ulogic := '0';
begin
for i in 0 to VECT'left loop
if (is1 = '0') then
result(i) := VECT(i);
if (VECT(i) = '1' ) then
is1 := '1';
end if;
else
result(i) := NOT VECT(i);
end if;
end loop;
return result;
end;
function ADDVECT(A, B: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR is
variable cout: STD_ULOGIC;
variable BVect, result: STD_LOGIC_VECTOR(A'left downto 0);
begin
for i in 0 to A'left loop
if (A(i) = 'X') then
result := (others => 'X');
return(result);
end if;
end loop;
for i in 0 to B'left loop
if (B(i) = 'X') then
result := (others => 'X');
return(result);
end if;
end loop;
cout := '0';
BVEct := B;
for i in 0 to A'left loop
result(i) := A(i) xor BVect(i) xor cout;
cout := (A(i) and BVect(i)) or
(A(i) and cout) or
(cout and BVect(i));
end loop;
return result;
end;
function SUBVECT(A, B: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR is
variable cout: STD_ULOGIC;
variable result: STD_LOGIC_VECTOR(A'left downto 0);
begin
for i in 0 to A'left loop
if (A(i) = 'X') then
result := (others => 'X');
return(result);
end if;
end loop;
for i in 0 to B'left loop
if (B(i) = 'X') then
result := (others => 'X');
return(result);
end if;
end loop;
cout := '1';
for i in 0 to A'left loop
result(i) := A(i) xor not B(i) xor cout;
cout := (A(i) and not B(i)) or
(A(i) and cout) or
(cout and not B(i));
end loop;
return result;
end;
function BITX (VECT: std_logic) return boolean is
begin
case VECT is
when 'X' => return true;
when others => return false;
end case;
end BITX;
END components;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity carry_tree is
generic (
N : integer := 32;
logN : integer := 5);
Port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Cin : In std_logic;
Cout: Out std_logic_vector(N/4-1 downto 0));
end carry_tree;
architecture arch of carry_tree is
signal g_net : std_logic_vector(N-1 downto 0);
signal p_net : std_logic_vector(N-1 downto 0);
type pg_couples_n is array (N/4-1 downto 0) of std_logic_vector(1 downto 0); -- propagate 1 -- generate 0
type pg_couples_1 is array (N/2-1 downto 0) of std_logic_vector(1 downto 0); -- propagate 1 -- generate 0
type pg_type is array (logN downto 2) of pg_couples_n;
signal pg_1 : pg_couples_1;
signal pg_n : pg_type;
signal magic_pro : std_logic_vector(1 downto 0); -- propagate 1 -- generate 0
component pg
Port ( g: In std_logic;
p: In std_logic;
g_prec: In std_logic;
p_prec: In std_logic;
g_out: Out std_logic;
p_out: Out std_logic);
end component;
component g
Port ( g: In std_logic;
p: In std_logic;
g_prec: In std_logic;
g_out: Out std_logic);
end component;
component pg_net
Port ( a: In std_logic;
b: In std_logic;
g_out: Out std_logic;
p_out: Out std_logic);
end component;
begin
pg_net_loop: for i in 1 to N-1 generate
pg_net_x : pg_net port map(a(i),b(i),g_net(i),p_net(i));
end generate pg_net_loop;
pg_net_0_MAGIC : pg_net port map (a(0),b(0),magic_pro(0),magic_pro(1));
xG_0_0_MAGIC : g port map (magic_pro(0),magic_pro(1),Cin,g_net(0)); --
xG_1_0 : g port map(g_net(1),p_net(1), g_net(0),pg_1(0)(0)); --level =1
pg_0_loop: for j in 1 to N/2-1 generate
xPG_1 : pg port map (g_net(j*2+1),p_net(j*2+1),g_net(j*2),p_net(j*2), pg_1(j)(0), pg_1(j)(1));
end generate pg_0_loop;
xG_2_0 : g port map(pg_1(1)(0),pg_1(1)(1),pg_1(0)(0),pg_n(2)(0)(0)); --level =2
pg_1_loop: for j in 1 to N/4-1 generate
xPG_2 : pg port map (pg_1(j*2+1)(0),pg_1(j*2+1)(1),pg_1(j*2)(0),pg_1(j*2)(1), pg_n(2)(j)(0), pg_n(2)(j)(1));
end generate pg_1_loop;
for_loop_g: for level in 3 to logN generate
inner_loop_g: for j in 0 to (2**(level-2)-1) generate
if_ok_g: if((j rem (2**(level-2))) >= (2**(level-3))) generate
xG : g port map (pg_n(level-1)(j)(0),pg_n(level-1)(j)(1),pg_n(level-1)(2**(level-3)-1)(0),pg_n(level)(j)(0));
end generate if_ok_g;
if_fake_g: if(j rem (2**(level-2)) < (2**(level-3))) generate
pg_n(level)(j)<=pg_n(level-1)(j);
end generate if_fake_g;
end generate inner_loop_g;
end generate for_loop_g;
for_loop_pg: for level in 3 to logN-1 generate
inner_loop_pg: for j in (2**(level-2)) to ((N/4)-1) generate
if_ok_pg: if(j mod (2**(level-2)) >= (2**(level-3))) generate
xPG : pg port map (pg_n(level-1)(j)(0),pg_n(level-1)(j)(1),pg_n(level-1)(j-(j mod (2**(level-3)))-1)(0),pg_n(level-1)(j-(j mod (2**(level-3)))-1)(1),pg_n(level)(j)(0),pg_n(level)(j)(1));
end generate if_ok_pg;
if_fake_pg: if(j mod (2**(level-2)) < (2**(level-3))) generate
pg_n(level)(j)<=pg_n(level-1)(j);
end generate if_fake_pg;
end generate inner_loop_pg;
end generate for_loop_pg;
final: for i in 0 to N/4-1 generate
Cout(i)<=pg_n(logN)(i)(0);
end generate;
end arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity carry_tree is
generic (
N : integer := 32;
logN : integer := 5);
Port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Cin : In std_logic;
Cout: Out std_logic_vector(N/4-1 downto 0));
end carry_tree;
architecture arch of carry_tree is
signal g_net : std_logic_vector(N-1 downto 0);
signal p_net : std_logic_vector(N-1 downto 0);
type pg_couples_n is array (N/4-1 downto 0) of std_logic_vector(1 downto 0); -- propagate 1 -- generate 0
type pg_couples_1 is array (N/2-1 downto 0) of std_logic_vector(1 downto 0); -- propagate 1 -- generate 0
type pg_type is array (logN downto 2) of pg_couples_n;
signal pg_1 : pg_couples_1;
signal pg_n : pg_type;
signal magic_pro : std_logic_vector(1 downto 0); -- propagate 1 -- generate 0
component pg
Port ( g: In std_logic;
p: In std_logic;
g_prec: In std_logic;
p_prec: In std_logic;
g_out: Out std_logic;
p_out: Out std_logic);
end component;
component g
Port ( g: In std_logic;
p: In std_logic;
g_prec: In std_logic;
g_out: Out std_logic);
end component;
component pg_net
Port ( a: In std_logic;
b: In std_logic;
g_out: Out std_logic;
p_out: Out std_logic);
end component;
begin
pg_net_loop: for i in 1 to N-1 generate
pg_net_x : pg_net port map(a(i),b(i),g_net(i),p_net(i));
end generate pg_net_loop;
pg_net_0_MAGIC : pg_net port map (a(0),b(0),magic_pro(0),magic_pro(1));
xG_0_0_MAGIC : g port map (magic_pro(0),magic_pro(1),Cin,g_net(0)); --
xG_1_0 : g port map(g_net(1),p_net(1), g_net(0),pg_1(0)(0)); --level =1
pg_0_loop: for j in 1 to N/2-1 generate
xPG_1 : pg port map (g_net(j*2+1),p_net(j*2+1),g_net(j*2),p_net(j*2), pg_1(j)(0), pg_1(j)(1));
end generate pg_0_loop;
xG_2_0 : g port map(pg_1(1)(0),pg_1(1)(1),pg_1(0)(0),pg_n(2)(0)(0)); --level =2
pg_1_loop: for j in 1 to N/4-1 generate
xPG_2 : pg port map (pg_1(j*2+1)(0),pg_1(j*2+1)(1),pg_1(j*2)(0),pg_1(j*2)(1), pg_n(2)(j)(0), pg_n(2)(j)(1));
end generate pg_1_loop;
for_loop_g: for level in 3 to logN generate
inner_loop_g: for j in 0 to (2**(level-2)-1) generate
if_ok_g: if((j rem (2**(level-2))) >= (2**(level-3))) generate
xG : g port map (pg_n(level-1)(j)(0),pg_n(level-1)(j)(1),pg_n(level-1)(2**(level-3)-1)(0),pg_n(level)(j)(0));
end generate if_ok_g;
if_fake_g: if(j rem (2**(level-2)) < (2**(level-3))) generate
pg_n(level)(j)<=pg_n(level-1)(j);
end generate if_fake_g;
end generate inner_loop_g;
end generate for_loop_g;
for_loop_pg: for level in 3 to logN-1 generate
inner_loop_pg: for j in (2**(level-2)) to ((N/4)-1) generate
if_ok_pg: if(j mod (2**(level-2)) >= (2**(level-3))) generate
xPG : pg port map (pg_n(level-1)(j)(0),pg_n(level-1)(j)(1),pg_n(level-1)(j-(j mod (2**(level-3)))-1)(0),pg_n(level-1)(j-(j mod (2**(level-3)))-1)(1),pg_n(level)(j)(0),pg_n(level)(j)(1));
end generate if_ok_pg;
if_fake_pg: if(j mod (2**(level-2)) < (2**(level-3))) generate
pg_n(level)(j)<=pg_n(level-1)(j);
end generate if_fake_pg;
end generate inner_loop_pg;
end generate for_loop_pg;
final: for i in 0 to N/4-1 generate
Cout(i)<=pg_n(logN)(i)(0);
end generate;
end arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity LeftShift is
port (
c_in : in unsigned(3 downto 0) := "0001";
c_out : out unsigned(3 downto 0);
data_in : in unsigned(3 downto 0) := "0000";
data_out : out unsigned(3 downto 0)
);
end entity LeftShift;
architecture Behavioural of LeftShift is
begin
c_out <= c_in;
data_out <= data_in sll to_integer(c_in(1 downto 0));
end architecture Behavioural;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc754.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00754pkg is
subtype hi_to_low_range is integer range 0 to 7;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector ;
type real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(1 to 7);
k:bit_vector(0 to 3);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(0 to 15);
b:severity_level_vector(0 to 15);
c:integer_vector(0 to 15);
d:real_vector(0 to 15);
e:time_vector(0 to 15);
f:natural_vector(0 to 15);
g:positive_vector(0 to 15);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
type array_rec_rec is array (integer range <>) of record_of_records;
subtype array_rec_std_st is array_rec_std (hi_to_low_range);
subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
type record_of_arr_of_record is record
a: array_rec_std(0 to 7);
b: array_rec_cons(0 to 7);
c: array_rec_rec(0 to 7);
end record;
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_vector is array (natural range <>) of current;
subtype current_vector_range is current_vector(hi_to_low_range);
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_vector is array (natural range <>) of resistance;
subtype resistance_vector_range is resistance_vector(hi_to_low_range);
type byte is array(0 to 7) of bit;
subtype word is bit_vector(0 to 15); --constrained array
constant size :integer := 7;
type primary_memory is array(0 to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:bit;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
subtype delay is integer range 1 to 10;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C10 : string := "shishir";
constant C11 : bit_vector := B"0011";
constant C12 : boolean_vector := (C1,false);
constant C13 : severity_level_vector := (C4,error);
constant C14 : integer_vector := (1,2,3,4);
constant C15 : real_vector := (1.0,2.0,C6,4.0);
constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
constant C17 : natural_vector := (1,2,3,4);
constant C18 : positive_vector := (1,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st:= (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st:=(others => C6);
constant C74 : time_vector_st:=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54b : record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
constant C78 : boolean_vector_range := (others => C1);
constant C79 : severity_level_vector_range := (others => C4) ;
constant C80 : integer_vector_range :=(others => C5) ;
constant C81 : real_vector_range :=(others => C6);
constant C82 : time_vector_range :=(others => C7);
constant C83 : natural_vector_range :=(others => C8);
constant C84 : positive_vector_range :=(others => C9);
constant C85 : array_rec_std(0 to 7) :=(others => C50) ;
constant C86 : array_rec_cons (0 to 7) :=(others => C51);
constant C88 : array_rec_rec(0 to 7) :=(others => C55);
constant C102 : record_of_arr_of_record:= (C85,C86,C88);
end c01s01b01x01p05n02i00754pkg;
use work.c01s01b01x01p05n02i00754pkg.all;
ENTITY vests12 IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level := note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
port(
S1 : boolean_vector(zero to fifteen);
S2 : severity_level_vector(zero to fifteen);
S3 : integer_vector(zero to fifteen);
S4 : real_vector(zero to fifteen);
S5 : time_vector (zero to fifteen);
S6 : natural_vector(zero to fifteen);
S7 : positive_vector(zero to fifteen);
S8 : boolean_cons_vector;
S9 : severity_level_cons_vector ;
S10 : integer_cons_vector;
S11 : real_cons_vector;
S12 : time_cons_vector ;
S13 : natural_cons_vector ;
S14 : positive_cons_vector ;
S15 : boolean_cons_vectorofvector;
S16 : severity_level_cons_vectorofvector;
S17 : integer_cons_vectorofvector;
S18 : real_cons_vectorofvector;
S19 : time_cons_vectorofvector;
S20 : natural_cons_vectorofvector;
S21 : positive_cons_vectorofvector;
S22 : record_std_package;
S23 : record_cons_array;
S24 : record_cons_arrayofarray ;
S25 : boolean_vector_st;
S26 : severity_level_vector_st;
S27 : integer_vector_st;
S28 : real_vector_st;
S29 : time_vector_st;
S30 : natural_vector_st;
S31 : positive_vector_st;
S32 : record_array_st;
S33 : record_array_st;
S34 : record_array_new;
S35 : record_of_records;
S36 : byte;
S37 : word;
S38 : current_vector(zero to three);
S39 : resistance_vector(zero to three);
S40 : delay;
S41 : boolean_vector_range;
S42 : severity_level_vector_range ;
S43 : integer_vector_range ;
S44 : real_vector_range ;
S45 : time_vector_range ;
S46 : natural_vector_range ;
S47 : positive_vector_range ;
S48 : array_rec_std(zero to seven);
S49 : array_rec_cons(zero to seven);
S50 : array_rec_rec(zero to seven);
S51 : record_of_arr_of_record
);
END vests12;
ARCHITECTURE c01s01b01x01p05n02i00754arch OF vests12 IS
BEGIN
assert (S1'left = 0) report " boolean_vector(zero to fifteen) error in the left generic value" severity error;
assert (S2'left = 0) report " severity_level_vector(zero to fifteen) error in the left generic value" severity error;
assert (S3'left = 0) report " integer_vector(zero to fifteen) error in the left generic value" severity error;
assert (S4'left = 0) report " real_vector(zero to fifteen) error in the left generic value" severity error;
assert (S5'left = 0) report " time_vector (zero to fifteen) error in the left generic value" severity error;
assert (S6'left = 0) report " natural_vector(zero to fifteen) error in the left generic value" severity error;
assert (S7'left = 0) report " positive_vector(zero to fifteen) error in the left generic value" severity error;
assert (S8'left = 15) report " boolean_cons_vector error in the left generic value" severity error;
assert (S9'left = 15) report " severity_level_cons_vector error in the left generic value" severity error;
assert (S10'left = 15) report " integer_cons_vector error in the left generic value" severity error;
assert (S11'left = 15) report " real_cons_vector error in the left generic value" severity error;
assert (S12'left = 15) report " time_cons_vector error in the left generic value" severity error;
assert (S13'left = 15) report " natural_cons_vector error in the left generic value" severity error;
assert (S14'left = 15) report " positive_cons_vector error in the left generic value" severity error;
assert (S15'left = 0) report " boolean_cons_vectorofvector error in the left generic value" severity error;
assert (S16'left = 0) report " severity_level_cons_vectorofvector error in the left generic value" severity error;
assert (S17'left = 0) report " integer_cons_vectorofvector error in the left generic value" severity error;
assert (S18'left = 0) report " real_cons_vectorofvector error in the left generic value" severity error;
assert (S19'left = 0) report " time_cons_vectorofvector error in the left generic value" severity error;
assert (S20'left = 0) report " natural_cons_vectorofvector error in the left generic value" severity error;
assert (S21'left = 0) report " positive_cons_vectorofvector error in the left generic value" severity error;
assert (S22.j'left = 1) report " record_std_package error in the left generic value" severity error;
assert (S22.k'left = 0) report " record_std_package error in the left generic value" severity error;
assert (S23.a'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.b'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.c'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.d'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.e'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.f'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.g'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S24.a'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.b'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.c'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.d'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.e'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.f'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.g'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S25'left = 0) report " boolean_vector_st error in the left generic value" severity error;
assert (S26'left = 0) report " severity_level_vector_st error in the left generic value" severity error;
assert (S27'left = 0) report " integer_vector_st error in the left generic value" severity error;
assert (S28'left = 0) report " real_vector_st error in the left generic value" severity error;
assert (S29'left = 0) report " time_vector_st error in the left generic value" severity error;
assert (S30'left = 0) report " natural_vector_st error in the left generic value" severity error;
assert (S31'left = 0) report " positive_vector_st error in the left generic value" severity error;
assert (S32.a'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.b'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.c'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.d'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.e'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.f'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.g'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S34.a'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.b'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.c'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.d'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.e'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.f'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.g'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S36'left = 0) report " byte error in the left generic value" severity error;
assert (S37'left = 0) report " word error in the left generic value" severity error;
assert (S38'left = 0) report " current_vector(zero to three) error in the left generic value" severity error;
assert (S39'left = 0) report " resistance_vector(zero to three) error in the left generic value" severity error;
--assert (S40'left = 1) report " delay error in the left generic value" severity error;
assert (S41'left = 0) report " boolean_vector_range error in the left generic value" severity error;
assert (S42'left = 0) report " severity_level_vector_range error in the left generic value" severity error;
assert (S43'left = 0) report " integer_vector_range error in the left generic value" severity error;
assert (S44'left = 0) report " real_vector_range error in the left generic value" severity error;
assert (S45'left = 0) report " time_vector_range error in the left generic value" severity error;
assert (S46'left = 0) report " natural_vector_range error in the left generic value" severity error;
assert (S47'left = 0) report " positive_vector_range error in the left generic value" severity error;
assert (S48'left = 0) report " array_rec_std(zero to seven) error in the left generic value" severity error;
assert (S49'left = 0) report " array_rec_cons(zero to seven) error in the left generic value" severity error;
assert (S50'left = 0) report " array_rec_rec(zero to seven) error in the left generic value" severity error;
assert (S51.a'left = 0) report " record_of_arr_of_record error in the left generic value" severity error;
assert (S51.b'left = 0) report " record_of_arr_of_record error in the left generic value" severity error;
assert (S51.c'left = 0) report " record_of_arr_of_record error in the left generic value" severity error;
assert (S1'right = 15) report " boolean_vector(zero to fifteen) error in the right generic value" severity error;
assert (S2'right = 15) report " severity_level_vector(zero to fifteen) error in the right generic value" severity error;
assert (S3'right = 15) report " integer_vector(zero to fifteen) error in the right generic value" severity error;
assert (S4'right = 15) report " real_vector(zero to fifteen) error in the right generic value" severity error;
assert (S5'right = 15) report " time_vector (zero to fifteen) error in the right generic value" severity error;
assert (S6'right = 15) report " natural_vector(zero to fifteen) error in the right generic value" severity error;
assert (S7'right = 15) report " positive_vector(zero to fifteen) error in the right generic value" severity error;
assert (S8'right = 0) report " boolean_cons_vector error in the right generic value" severity error;
assert (S9'right = 0) report " severity_level_cons_vector error in the right generic value" severity error;
assert (S10'right = 0) report " integer_cons_vector error in the right generic value" severity error;
assert (S11'right = 0) report " real_cons_vector error in the right generic value" severity error;
assert (S12'right = 0) report " time_cons_vector error in the right generic value" severity error;
assert (S13'right = 0) report " natural_cons_vector error in the right generic value" severity error;
assert (S14'right = 0) report " positive_cons_vector error in the right generic value" severity error;
assert (S15'right = 15) report " boolean_cons_vectorofvector error in the right generic value" severity error;
assert (S16'right = 15) report " severity_level_cons_vectorofvector error in the right generic value" severity error;
assert (S17'right = 15) report " integer_cons_vectorofvector error in the right generic value" severity error;
assert (S18'right = 15) report " real_cons_vectorofvector error in the right generic value" severity error;
assert (S19'right = 15) report " time_cons_vectorofvector error in the right generic value" severity error;
assert (S20'right = 15) report " natural_cons_vectorofvector error in the right generic value" severity error;
assert (S21'right = 15) report " positive_cons_vectorofvector error in the right generic value" severity error;
assert (S22.j'right = 7) report " record_std_package error in the right generic value" severity error;
assert (S22.k'right = 3) report " record_std_package error in the right generic value" severity error;
assert (S23.a'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.b'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.c'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.d'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.e'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.f'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.g'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S24.a'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.b'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.c'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.d'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.e'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.f'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.g'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S25'right = 15) report " boolean_vector_st error in the right generic value" severity error;
assert (S26'right = 15) report " severity_level_vector_st error in the right generic value" severity error;
assert (S27'right = 15) report " integer_vector_st error in the right generic value" severity error;
assert (S28'right = 15) report " real_vector_st error in the right generic value" severity error;
assert (S29'right = 15) report " time_vector_st error in the right generic value" severity error;
assert (S30'right = 15) report " natural_vector_st error in the right generic value" severity error;
assert (S31'right = 15) report " positive_vector_st error in the right generic value" severity error;
assert (S32.a'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.b'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.c'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.d'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.e'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.f'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.g'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S34.a'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.b'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.c'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.d'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.e'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.f'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.g'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S36'right = 7) report " byte error in the right generic value" severity error;
assert (S37'right = 15) report " word error in the right generic value" severity error;
assert (S38'right = 3) report " current_vector(zero to three) error in the right generic value" severity error;
assert (S39'right = 3) report " resistance_vector(zero to three) error in the right generic value" severity error;
--assert (S40'right = 1) report " delay error in the right generic value" severity error;
assert (S41'right = 7) report " boolean_vector_range error in the right generic value" severity error;
assert (S42'right = 7) report " severity_level_vector_range error in the right generic value" severity error;
assert (S43'right = 7) report " integer_vector_range error in the right generic value" severity error;
assert (S44'right = 7) report " real_vector_range error in the right generic value" severity error;
assert (S45'right = 7) report " time_vector_range error in the right generic value" severity error;
assert (S46'right = 7) report " natural_vector_range error in the right generic value" severity error;
assert (S47'right = 7) report " positive_vector_range error in the right generic value" severity error;
assert (S48'right = 7) report " array_rec_std(zero to seven) error in the right generic value" severity error;
assert (S49'right = 7) report " array_rec_cons(zero to seven) error in the right generic value" severity error;
assert (S50'right = 7) report " array_rec_rec(zero to seven) error in the right generic value" severity error;
assert (S51.a'right = 7) report " record_of_arr_of_record error in the right generic value" severity error;
assert (S51.b'right = 7) report " record_of_arr_of_record error in the right generic value" severity error;
assert (S51.c'right = 7) report " record_of_arr_of_record error in the right generic value" severity error;
assert (S1'length = 16) report " boolean_vector(zero to fifteen) error in the length generic value" severity error;
assert (S2'length = 16) report " severity_level_vector(zero to fifteen) error in the length generic value" severity error;
assert (S3'length = 16) report " integer_vector(zero to fifteen) error in the length generic value" severity error;
assert (S4'length = 16) report " real_vector(zero to fifteen) error in the length generic value" severity error;
assert (S5'length = 16) report " time_vector (zero to fifteen) error in the length generic value" severity error;
assert (S6'length = 16) report " natural_vector(zero to fifteen) error in the length generic value" severity error;
assert (S7'length = 16) report " positive_vector(zero to fifteen) error in the length generic value" severity error;
assert (S8'length = 16) report " boolean_cons_vector error in the length generic value" severity error;
assert (S9'length = 16) report " severity_level_cons_vector error in the length generic value" severity error;
assert (S10'length = 16) report " integer_cons_vector error in the length generic value" severity error;
assert (S11'length = 16) report " real_cons_vector error in the length generic value" severity error;
assert (S12'length = 16) report " time_cons_vector error in the length generic value" severity error;
assert (S13'length = 16) report " natural_cons_vector error in the length generic value" severity error;
assert (S14'length = 16) report " positive_cons_vector error in the length generic value" severity error;
assert (S15'length = 16) report " boolean_cons_vectorofvector error in the length generic value" severity error;
assert (S16'length = 16) report " severity_level_cons_vectorofvector error in the length generic value" severity error;
assert (S17'length = 16) report " integer_cons_vectorofvector error in the length generic value" severity error;
assert (S18'length = 16) report " real_cons_vectorofvector error in the length generic value" severity error;
assert (S19'length = 16) report " time_cons_vectorofvector error in the length generic value" severity error;
assert (S20'length = 16) report " natural_cons_vectorofvector error in the length generic value" severity error;
assert (S21'length = 16) report " positive_cons_vectorofvector error in the length generic value" severity error;
assert (S22.j'length = 7) report " record_std_package error in the length generic value" severity error;
assert (S22.k'length = 4) report " record_std_package error in the length generic value" severity error;
assert (S23.a'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.b'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.c'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.d'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.e'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.f'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.g'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S24.a'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.b'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.c'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.d'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.e'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.f'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.g'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S25'length = 16) report " boolean_vector_st error in the length generic value" severity error;
assert (S26'length = 16) report " severity_level_vector_st error in the length generic value" severity error;
assert (S27'length = 16) report " integer_vector_st error in the length generic value" severity error;
assert (S28'length = 16) report " real_vector_st error in the length generic value" severity error;
assert (S29'length = 16) report " time_vector_st error in the length generic value" severity error;
assert (S30'length = 16) report " natural_vector_st error in the length generic value" severity error;
assert (S31'length = 16) report " positive_vector_st error in the length generic value" severity error;
assert (S32.a'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.b'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.c'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.d'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.e'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.f'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.g'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S34.a'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.b'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.c'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.d'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.e'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.f'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.g'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S36'length = 8) report " byte error in the length generic value" severity error;
assert (S37'length = 16) report " word error in the length generic value" severity error;
assert (S38'length = 4) report " current_vector(zero to three) error in the length generic value" severity error;
assert (S39'length = 4) report " resistance_vector(zero to three) error in the length generic value" severity error;
--assert (S40'length = 1) report " delay error in the length generic value" severity error;
assert (S41'length = 8) report " boolean_vector_range error in the length generic value" severity error;
assert (S42'length = 8) report " severity_level_vector_range error in the length generic value" severity error;
assert (S43'length = 8) report " integer_vector_range error in the length generic value" severity error;
assert (S44'length = 8) report " real_vector_range error in the length generic value" severity error;
assert (S45'length = 8) report " time_vector_range error in the length generic value" severity error;
assert (S46'length = 8) report " natural_vector_range error in the length generic value" severity error;
assert (S48'length = 8) report " positive_vector_range error in the length generic value" severity error;
assert (S48'length = 8) report " array_rec_std(zero to seven) error in the length generic value" severity error;
assert (S49'length = 8) report " array_rec_cons(zero to seven) error in the length generic value" severity error;
assert (S50'length = 8) report " array_rec_rec(zero to seven) error in the length generic value" severity error;
assert (S51.a'length = 8) report " record_of_arr_of_record error in the length generic value" severity error;
assert (S51.b'length = 8) report " record_of_arr_of_record error in the length generic value" severity error;
assert (S51.c'length = 8) report " record_of_arr_of_record error in the length generic value" severity error;
TESTING: PROCESS
BEGIN
assert NOT( (S1'left = 0) and
(S2'left = 0) and
(S3'left = 0) and
(S4'left = 0) and
(S5'left = 0) and
(S6'left = 0) and
(S7'left = 0) and
(S8'left = 15) and
(S9'left = 15) and
(S10'left = 15) and
(S11'left = 15) and
(S12'left = 15) and
(S13'left = 15) and
(S14'left = 15) and
(S15'left = 0) and
(S16'left = 0) and
(S17'left = 0) and
(S18'left = 0) and
(S19'left = 0) and
(S20'left = 0) and
(S21'left = 0) and
(S22.j'left = 1) and
(S22.k'left = 0) and
(S23.a'left = 15) and
(S23.b'left = 15) and
(S23.c'left = 15) and
(S23.d'left = 15) and
(S23.e'left = 15) and
(S23.f'left = 15) and
(S23.g'left = 15) and
(S24.a'left = 0) and
(S24.b'left = 0) and
(S24.c'left = 0) and
(S24.d'left = 0) and
(S24.e'left = 0) and
(S24.f'left = 0) and
(S24.g'left = 0) and
(S25'left = 0) and
(S26'left = 0) and
(S27'left = 0) and
(S28'left = 0) and
(S29'left = 0) and
(S30'left = 0) and
(S31'left = 0) and
(S32.a'left = 0) and
(S32.b'left = 0) and
(S32.c'left = 0) and
(S32.d'left = 0) and
(S32.e'left = 0) and
(S32.f'left = 0) and
(S32.g'left = 0) and
(S34.a'left = 0) and
(S34.b'left = 0) and
(S34.c'left = 0) and
(S34.d'left = 0) and
(S34.e'left = 0) and
(S34.f'left = 0) and
(S34.g'left = 0) and
(S36'left = 0) and
(S37'left = 0) and
(S38'left = 0) and
(S39'left = 0) and
-- (S40'left = 1) and
(S42'left = 0) and
(S43'left = 0) and
(S44'left = 0) and
(S45'left = 0) and
(S46'left = 0) and
(S47'left = 0) and
(S48'left = 0) and
(S49'left = 0) and
(S50'left = 0) and
(S51.a'left = 0) and
(S51.b'left = 0) and
(S51.c'left = 0) and
(S1'right = 15) and
(S2'right = 15) and
(S3'right = 15) and
(S4'right = 15) and
(S5'right = 15) and
(S6'right = 15) and
(S7'right = 15) and
(S8'right = 0) and
(S9'right = 0) and
(S10'right = 0)and
(S11'right = 0) and
(S12'right = 0) and
(S13'right = 0) and
(S14'right = 0) and
(S15'right = 15) and
(S16'right = 15) and
(S17'right = 15) and
(S18'right = 15) and
(S19'right = 15) and
(S20'right = 15) and
(S21'right = 15) and
(S22.j'right = 7) and
(S22.k'right = 3) and
(S23.a'right = 0) and
(S23.b'right = 0) and
(S23.c'right = 0) and
(S23.d'right = 0) and
(S23.e'right = 0) and
(S23.f'right = 0) and
(S23.g'right = 0) and
(S24.a'right = 15) and
(S24.b'right = 15) and
(S24.c'right = 15) and
(S24.d'right = 15) and
(S24.e'right = 15) and
(S24.f'right = 15) and
(S24.g'right = 15) and
(S25'right = 15) and
(S26'right = 15) and
(S27'right = 15) and
(S28'right = 15) and
(S29'right = 15) and
(S30'right = 15) and
(S31'right = 15) and
(S32.a'right = 15) and
(S32.b'right = 15) and
(S32.c'right = 15) and
(S32.d'right = 15) and
(S32.e'right = 15) and
(S32.f'right = 15) and
(S32.g'right = 15) and
(S34.a'right = 15) and
(S34.b'right = 15) and
(S34.c'right = 15) and
(S34.d'right = 15) and
(S34.e'right = 15) and
(S34.f'right = 15) and
(S34.g'right = 15) and
(S36'right = 7) and
(S37'right = 15) and
(S38'right = 3) and
(S39'right = 3) and
-- (S40'right = 1) and
(S41'right = 7) and
(S42'right = 7) and
(S43'right = 7) and
(S44'right = 7) and
(S45'right = 7) and
(S46'right = 7) and
(S47'right = 7) and
(S48'right = 7) and
(S49'right = 7) and
(S50'right = 7) and
(S51.a'right = 7) and
(S51.b'right = 7) and
(S51.c'right = 7) and
(S1'length = 16) and
(S2'length = 16) and
(S3'length = 16) and
(S4'length = 16) and
(S5'length = 16) and
(S6'length = 16) and
(S7'length = 16) and
(S8'length = 16) and
(S9'length = 16) and
(S10'length = 16) and
(S11'length = 16) and
(S12'length = 16) and
(S13'length = 16) and
(S14'length = 16) and
(S15'length = 16) and
(S16'length = 16) and
(S17'length = 16) and
(S18'length = 16) and
(S19'length = 16) and
(S20'length = 16) and
(S21'length = 16) and
(S22.j'length = 7)and
(S22.k'length = 4) and
(S23.a'length = 16) and
(S23.b'length = 16) and
(S23.c'length = 16) and
(S23.d'length = 16) and
(S23.e'length = 16) and
(S23.f'length = 16) and
(S23.g'length = 16) and
(S24.a'length = 16) and
(S24.b'length = 16) and
(S24.c'length = 16) and
(S24.d'length = 16) and
(S24.e'length = 16) and
(S24.f'length = 16) and
(S24.g'length = 16) and
(S25'length = 16) and
(S26'length = 16) and
(S27'length = 16) and
(S28'length = 16) and
(S29'length = 16) and
(S30'length = 16) and
(S31'length = 16) and
(S32.a'length = 16) and
(S32.b'length = 16) and
(S32.c'length = 16) and
(S32.d'length = 16) and
(S32.e'length = 16) and
(S32.f'length = 16) and
(S32.g'length = 16) and
(S34.a'length = 16) and
(S34.b'length = 16) and
(S34.c'length = 16) and
(S34.d'length = 16) and
(S34.e'length = 16) and
(S34.f'length = 16) and
(S34.g'length = 16) and
(S36'length = 8) and
(S37'length = 16) and
(S38'length = 4) and
(S39'length = 4) and
-- (S40'length = 1) and
(S41'length = 8) and
(S42'length = 8) and
(S43'length = 8) and
(S44'length = 8) and
(S45'length = 8) and
(S46'length = 8) and
(S48'length = 8) and
(S48'length = 8) and
(S49'length = 8) and
(S50'length = 8) and
(S51.a'length = 8) and
(S51.b'length = 8) and
(S51.c'length = 8) )
report "***PASSED TEST: c01s01b01x01p05n02i00754"
severity NOTE;
assert ((S1'left = 0) and
(S2'left = 0) and
(S3'left = 0) and
(S4'left = 0) and
(S5'left = 0) and
(S6'left = 0) and
(S7'left = 0) and
(S8'left = 15) and
(S9'left = 15) and
(S10'left = 15) and
(S11'left = 15) and
(S12'left = 15) and
(S13'left = 15) and
(S14'left = 15) and
(S15'left = 0) and
(S16'left = 0) and
(S17'left = 0) and
(S18'left = 0) and
(S19'left = 0) and
(S20'left = 0) and
(S21'left = 0) and
(S22.j'left = 1) and
(S22.k'left = 0) and
(S23.a'left = 15) and
(S23.b'left = 15) and
(S23.c'left = 15) and
(S23.d'left = 15) and
(S23.e'left = 15) and
(S23.f'left = 15) and
(S23.g'left = 15) and
(S24.a'left = 0) and
(S24.b'left = 0) and
(S24.c'left = 0) and
(S24.d'left = 0) and
(S24.e'left = 0) and
(S24.f'left = 0) and
(S24.g'left = 0) and
(S25'left = 0) and
(S26'left = 0) and
(S27'left = 0) and
(S28'left = 0) and
(S29'left = 0) and
(S30'left = 0) and
(S31'left = 0) and
(S32.a'left = 0) and
(S32.b'left = 0) and
(S32.c'left = 0) and
(S32.d'left = 0) and
(S32.e'left = 0) and
(S32.f'left = 0) and
(S32.g'left = 0) and
(S34.a'left = 0) and
(S34.b'left = 0) and
(S34.c'left = 0) and
(S34.d'left = 0) and
(S34.e'left = 0) and
(S34.f'left = 0) and
(S34.g'left = 0) and
(S36'left = 0) and
(S37'left = 0) and
(S38'left = 0) and
(S39'left = 0) and
-- (S40'left = 1) and
(S42'left = 0) and
(S43'left = 0) and
(S44'left = 0) and
(S45'left = 0) and
(S46'left = 0) and
(S47'left = 0) and
(S48'left = 0) and
(S49'left = 0) and
(S50'left = 0) and
(S51.a'left = 0) and
(S51.b'left = 0) and
(S51.c'left = 0) and
(S1'right = 15) and
(S2'right = 15) and
(S3'right = 15) and
(S4'right = 15) and
(S5'right = 15) and
(S6'right = 15) and
(S7'right = 15) and
(S8'right = 0) and
(S9'right = 0) and
(S10'right = 0)and
(S11'right = 0) and
(S12'right = 0) and
(S13'right = 0) and
(S14'right = 0) and
(S15'right = 15) and
(S16'right = 15) and
(S17'right = 15) and
(S18'right = 15) and
(S19'right = 15) and
(S20'right = 15) and
(S21'right = 15) and
(S22.j'right = 7) and
(S22.k'right = 3) and
(S23.a'right = 0) and
(S23.b'right = 0) and
(S23.c'right = 0) and
(S23.d'right = 0) and
(S23.e'right = 0) and
(S23.f'right = 0) and
(S23.g'right = 0) and
(S24.a'right = 15) and
(S24.b'right = 15) and
(S24.c'right = 15) and
(S24.d'right = 15) and
(S24.e'right = 15) and
(S24.f'right = 15) and
(S24.g'right = 15) and
(S25'right = 15) and
(S26'right = 15) and
(S27'right = 15) and
(S28'right = 15) and
(S29'right = 15) and
(S30'right = 15) and
(S31'right = 15) and
(S32.a'right = 15) and
(S32.b'right = 15) and
(S32.c'right = 15) and
(S32.d'right = 15) and
(S32.e'right = 15) and
(S32.f'right = 15) and
(S32.g'right = 15) and
(S34.a'right = 15) and
(S34.b'right = 15) and
(S34.c'right = 15) and
(S34.d'right = 15) and
(S34.e'right = 15) and
(S34.f'right = 15) and
(S34.g'right = 15) and
(S36'right = 7) and
(S37'right = 15) and
(S38'right = 3) and
(S39'right = 3) and
-- (S40'right = 1) and
(S41'right = 7) and
(S42'right = 7) and
(S43'right = 7) and
(S44'right = 7) and
(S45'right = 7) and
(S46'right = 7) and
(S47'right = 7) and
(S48'right = 7) and
(S49'right = 7) and
(S50'right = 7) and
(S51.a'right = 7) and
(S51.b'right = 7) and
(S51.c'right = 7) and
(S1'length = 16) and
(S2'length = 16) and
(S3'length = 16) and
(S4'length = 16) and
(S5'length = 16) and
(S6'length = 16) and
(S7'length = 16) and
(S8'length = 16) and
(S9'length = 16) and
(S10'length = 16) and
(S11'length = 16) and
(S12'length = 16) and
(S13'length = 16) and
(S14'length = 16) and
(S15'length = 16) and
(S16'length = 16) and
(S17'length = 16) and
(S18'length = 16) and
(S19'length = 16) and
(S20'length = 16) and
(S21'length = 16) and
(S22.j'length = 7)and
(S22.k'length = 4) and
(S23.a'length = 16) and
(S23.b'length = 16) and
(S23.c'length = 16) and
(S23.d'length = 16) and
(S23.e'length = 16) and
(S23.f'length = 16) and
(S23.g'length = 16) and
(S24.a'length = 16) and
(S24.b'length = 16) and
(S24.c'length = 16) and
(S24.d'length = 16) and
(S24.e'length = 16) and
(S24.f'length = 16) and
(S24.g'length = 16) and
(S25'length = 16) and
(S26'length = 16) and
(S27'length = 16) and
(S28'length = 16) and
(S29'length = 16) and
(S30'length = 16) and
(S31'length = 16) and
(S32.a'length = 16) and
(S32.b'length = 16) and
(S32.c'length = 16) and
(S32.d'length = 16) and
(S32.e'length = 16) and
(S32.f'length = 16) and
(S32.g'length = 16) and
(S34.a'length = 16) and
(S34.b'length = 16) and
(S34.c'length = 16) and
(S34.d'length = 16) and
(S34.e'length = 16) and
(S34.f'length = 16) and
(S34.g'length = 16) and
(S36'length = 8) and
(S37'length = 16) and
(S38'length = 4) and
(S39'length = 4) and
-- (S40'length = 1) and
(S41'length = 8) and
(S42'length = 8) and
(S43'length = 8) and
(S44'length = 8) and
(S45'length = 8) and
(S46'length = 8) and
(S48'length = 8) and
(S48'length = 8) and
(S49'length = 8) and
(S50'length = 8) and
(S51.a'length = 8) and
(S51.b'length = 8) and
(S51.c'length = 8) )
report "***FAILED TEST: c01s01b01x01p05n02i00754 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00754arch;
|
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Used for calculation of h_count and v_count port width
use ieee.math_real.all;
use work.config_const_pkg.all;
use work.curves_pkg.all;
--======================================================================================--
entity vignette_tb is
generic (
input_file: string := "tst/input/amersfoort_gray.pgm"; --! Input file of test
output_file: string := "tst/output/vignette_output.pgm"; --! Output file of test
image_width: integer := const_imagewidth; --! Width of input image
image_height: integer := const_imageheight; --! Height of input image
vignette_x_c: real := 1.0; --! Strength of vignette in x direction
vignette_y_c: real := 1.0 --! Strength of vignette in y direction
);
end entity;
--======================================================================================--
architecture structural of vignette_tb is
--===================component declaration===================--
component test_bench_driver is
generic (
wordsize: integer := const_wordsize;
input_file: string := input_file;
output_file: string := output_file;
clk_period_ns: time := 1 ns;
rst_after: time := 9 ns;
rst_duration: time := 8 ns;
dut_delay: integer := 4
);
port (
clk: out std_logic;
rst: out std_logic;
enable: out std_logic;
h_count: out std_logic_vector;
v_count: out std_logic_vector;
pixel_from_file: out std_logic_vector;
pixel_to_file: in std_logic_vector
);
end component;
----------------------------------------------------------------------------------------------
component vignette is
generic (
wordsize: integer := const_wordsize;
width: integer := image_width;
height: integer := image_height;
lut_x: array_pixel := create_sine_lut(image_width, vignette_x_c);
lut_y: array_pixel := create_sine_lut(image_height, vignette_y_c)
);
port (
clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
h_count: in std_logic_vector;
v_count: in std_logic_vector;
pixel_i: in std_logic_vector;
pixel_o: out std_logic_vector
);
end component;
----------------------------------------------------------------------------------------------
--===================signal declaration===================--
signal clk: std_logic := '0';
signal rst: std_logic := '0';
signal enable: std_logic := '0';
signal h_count: std_logic_vector((integer(ceil(log2(real(image_width))))-1) downto 0) := (others => '0');
signal v_count: std_logic_vector((integer(ceil(log2(real(image_height))))-1) downto 0) := (others => '0');
signal pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
begin
--===================component instantiation===================--
tst_driver: test_bench_driver
port map(
clk => clk,
rst => rst,
enable => enable,
h_count => h_count,
v_count => v_count,
pixel_from_file => pixel_from_file,
pixel_to_file => pixel_to_file
);
device_under_test: vignette
port map(
clk => clk,
rst => rst,
enable => enable,
h_count => h_count,
v_count => v_count,
pixel_i => pixel_from_file,
pixel_o => pixel_to_file
);
end architecture;
|
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Used for calculation of h_count and v_count port width
use ieee.math_real.all;
use work.config_const_pkg.all;
use work.curves_pkg.all;
--======================================================================================--
entity vignette_tb is
generic (
input_file: string := "tst/input/amersfoort_gray.pgm"; --! Input file of test
output_file: string := "tst/output/vignette_output.pgm"; --! Output file of test
image_width: integer := const_imagewidth; --! Width of input image
image_height: integer := const_imageheight; --! Height of input image
vignette_x_c: real := 1.0; --! Strength of vignette in x direction
vignette_y_c: real := 1.0 --! Strength of vignette in y direction
);
end entity;
--======================================================================================--
architecture structural of vignette_tb is
--===================component declaration===================--
component test_bench_driver is
generic (
wordsize: integer := const_wordsize;
input_file: string := input_file;
output_file: string := output_file;
clk_period_ns: time := 1 ns;
rst_after: time := 9 ns;
rst_duration: time := 8 ns;
dut_delay: integer := 4
);
port (
clk: out std_logic;
rst: out std_logic;
enable: out std_logic;
h_count: out std_logic_vector;
v_count: out std_logic_vector;
pixel_from_file: out std_logic_vector;
pixel_to_file: in std_logic_vector
);
end component;
----------------------------------------------------------------------------------------------
component vignette is
generic (
wordsize: integer := const_wordsize;
width: integer := image_width;
height: integer := image_height;
lut_x: array_pixel := create_sine_lut(image_width, vignette_x_c);
lut_y: array_pixel := create_sine_lut(image_height, vignette_y_c)
);
port (
clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
h_count: in std_logic_vector;
v_count: in std_logic_vector;
pixel_i: in std_logic_vector;
pixel_o: out std_logic_vector
);
end component;
----------------------------------------------------------------------------------------------
--===================signal declaration===================--
signal clk: std_logic := '0';
signal rst: std_logic := '0';
signal enable: std_logic := '0';
signal h_count: std_logic_vector((integer(ceil(log2(real(image_width))))-1) downto 0) := (others => '0');
signal v_count: std_logic_vector((integer(ceil(log2(real(image_height))))-1) downto 0) := (others => '0');
signal pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
begin
--===================component instantiation===================--
tst_driver: test_bench_driver
port map(
clk => clk,
rst => rst,
enable => enable,
h_count => h_count,
v_count => v_count,
pixel_from_file => pixel_from_file,
pixel_to_file => pixel_to_file
);
device_under_test: vignette
port map(
clk => clk,
rst => rst,
enable => enable,
h_count => h_count,
v_count => v_count,
pixel_i => pixel_from_file,
pixel_o => pixel_to_file
);
end architecture;
|
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|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30400)
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|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30400)
`protect data_block
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30400)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30400)
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30400)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30400)
`protect data_block
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`protect begin_protected
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`protect end_protected
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.15:39:49)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY jpegsd_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4));
END jpegsd_random_entity;
ARCHITECTURE jpegsd_random_description OF jpegsd_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register13: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register14: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register15: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
WHEN "00000010" =>
register2 := input2 + 2;
WHEN "00000011" =>
register3 := input3 + 3;
register4 := ((NOT input4) + 1) XOR input4;
WHEN "00000100" =>
register5 := input5 + 5;
register2 := ((NOT register2) + 1) XOR register2;
register6 := ((NOT input6) + 1) XOR input6;
register3 := ((NOT register3) + 1) XOR register3;
WHEN "00000101" =>
output1 <= input7 + 11;
WHEN "00000110" =>
register7 := input8 + 12;
WHEN "00000111" =>
register8 := input9 + 13;
WHEN "00001000" =>
register9 := input10 + 14;
WHEN "00001001" =>
register10 := input11 + 15;
WHEN "00001010" =>
register11 := input12 + 16;
WHEN "00001011" =>
register12 := input13 + 17;
register10 := ((NOT register10) + 1) XOR register10;
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00001100" =>
register13 := input14 + 22;
register11 := ((NOT register11) + 1) XOR register11;
register8 := ((NOT register8) + 1) XOR register8;
WHEN "00001101" =>
output2 <= input15 + 27;
register5 := ((NOT register5) + 1) XOR register5;
register9 := ((NOT register9) + 1) XOR register9;
register14 := ((NOT input16) + 1) XOR input16;
register12 := ((NOT register12) + 1) XOR register12;
WHEN "00001110" =>
register15 := input17 + 35;
WHEN "00001111" =>
register15 := ((NOT register15) + 1) XOR register15;
register11 := register11 + register12;
register12 := ((NOT input18) + 1) XOR input18;
register7 := ((NOT register7) + 1) XOR register7;
WHEN "00010000" =>
register7 := register11 + register7;
WHEN "00010001" =>
register7 := register7 + register9;
WHEN "00010010" =>
register5 := register12 + register5;
register9 := ((NOT register13) + 1) XOR register13;
WHEN "00010011" =>
register4 := register5 + register4;
WHEN "00010100" =>
register4 := register4 + register10;
WHEN "00010101" =>
register5 := register4 * 44;
register6 := register6 + register9;
WHEN "00010110" =>
register6 := register6 + register14;
WHEN "00010111" =>
register6 := register6 + register8;
WHEN "00011000" =>
register1 := register6 + register1;
WHEN "00011001" =>
register1 := register1 + register2;
WHEN "00011010" =>
register1 := register1 + register3;
WHEN "00011011" =>
register1 := register1 + register15;
WHEN "00011100" =>
register2 := register1 + 46;
WHEN "00011101" =>
register3 := register1 + register2 + register7;
WHEN "00011110" =>
register1 := register1 * register2 * register3;
WHEN "00011111" =>
register1 := register5 + register1;
WHEN "00100000" =>
register1 := register4 + register1;
WHEN "00100001" =>
register1 := register1 srl 48;
WHEN "00100010" =>
output3 <= register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END jpegsd_random_description; |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.40xd
-- \ \ Application: netgen
-- / / Filename: bram_x64.vhd
-- /___/ /\ Timestamp: Wed Oct 24 18:09:27 2012
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/adrian/praca/pcie_brazil/PC/hdlmake/ip_cores/7k325ffg900/tmp/_cg/bram_x64.ngc /home/adrian/praca/pcie_brazil/PC/hdlmake/ip_cores/7k325ffg900/tmp/_cg/bram_x64.vhd
-- Device : 7k325tffg900-2
-- Input file : /home/adrian/praca/pcie_brazil/PC/hdlmake/ip_cores/7k325ffg900/tmp/_cg/bram_x64.ngc
-- Output file : /home/adrian/praca/pcie_brazil/PC/hdlmake/ip_cores/7k325ffg900/tmp/_cg/bram_x64.vhd
-- # of Entities : 1
-- Design Name : bram_x64
-- Xilinx : /opt/Xilinx/14.3/ISE_DS/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity bram_x64 is
port (
clka : in STD_LOGIC := 'X';
clkb : in STD_LOGIC := 'X';
wea : in STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 63 downto 0 );
web : in STD_LOGIC_VECTOR ( 7 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 63 downto 0 );
douta : out STD_LOGIC_VECTOR ( 63 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
);
end bram_x64;
architecture STRUCTURE of bram_x64 is
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
begin
XST_VCC : VCC
port map (
P => N0
);
XST_GND : GND
port map (
G => N1
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(63),
DIADI(6) => dina(62),
DIADI(5) => dina(61),
DIADI(4) => dina(60),
DIADI(3) => dina(59),
DIADI(2) => dina(58),
DIADI(1) => dina(57),
DIADI(0) => dina(56),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(63),
DIBDI(6) => dinb(62),
DIBDI(5) => dinb(61),
DIBDI(4) => dinb(60),
DIBDI(3) => dinb(59),
DIBDI(2) => dinb(58),
DIBDI(1) => dinb(57),
DIBDI(0) => dinb(56),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(63),
DOADO(6) => douta(62),
DOADO(5) => douta(61),
DOADO(4) => douta(60),
DOADO(3) => douta(59),
DOADO(2) => douta(58),
DOADO(1) => douta(57),
DOADO(0) => douta(56),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(63),
DOBDO(6) => doutb(62),
DOBDO(5) => doutb(61),
DOBDO(4) => doutb(60),
DOBDO(3) => doutb(59),
DOBDO(2) => doutb(58),
DOBDO(1) => doutb(57),
DOBDO(0) => doutb(56),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(7),
WEA(2) => wea(7),
WEA(1) => wea(7),
WEA(0) => wea(7),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(7),
WEBWE(2) => web(7),
WEBWE(1) => web(7),
WEBWE(0) => web(7)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(55),
DIADI(6) => dina(54),
DIADI(5) => dina(53),
DIADI(4) => dina(52),
DIADI(3) => dina(51),
DIADI(2) => dina(50),
DIADI(1) => dina(49),
DIADI(0) => dina(48),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(55),
DIBDI(6) => dinb(54),
DIBDI(5) => dinb(53),
DIBDI(4) => dinb(52),
DIBDI(3) => dinb(51),
DIBDI(2) => dinb(50),
DIBDI(1) => dinb(49),
DIBDI(0) => dinb(48),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(55),
DOADO(6) => douta(54),
DOADO(5) => douta(53),
DOADO(4) => douta(52),
DOADO(3) => douta(51),
DOADO(2) => douta(50),
DOADO(1) => douta(49),
DOADO(0) => douta(48),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(55),
DOBDO(6) => doutb(54),
DOBDO(5) => doutb(53),
DOBDO(4) => doutb(52),
DOBDO(3) => doutb(51),
DOBDO(2) => doutb(50),
DOBDO(1) => doutb(49),
DOBDO(0) => doutb(48),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(6),
WEA(2) => wea(6),
WEA(1) => wea(6),
WEA(0) => wea(6),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(6),
WEBWE(2) => web(6),
WEBWE(1) => web(6),
WEBWE(0) => web(6)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(47),
DIADI(6) => dina(46),
DIADI(5) => dina(45),
DIADI(4) => dina(44),
DIADI(3) => dina(43),
DIADI(2) => dina(42),
DIADI(1) => dina(41),
DIADI(0) => dina(40),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(47),
DIBDI(6) => dinb(46),
DIBDI(5) => dinb(45),
DIBDI(4) => dinb(44),
DIBDI(3) => dinb(43),
DIBDI(2) => dinb(42),
DIBDI(1) => dinb(41),
DIBDI(0) => dinb(40),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(47),
DOADO(6) => douta(46),
DOADO(5) => douta(45),
DOADO(4) => douta(44),
DOADO(3) => douta(43),
DOADO(2) => douta(42),
DOADO(1) => douta(41),
DOADO(0) => douta(40),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(47),
DOBDO(6) => doutb(46),
DOBDO(5) => doutb(45),
DOBDO(4) => doutb(44),
DOBDO(3) => doutb(43),
DOBDO(2) => doutb(42),
DOBDO(1) => doutb(41),
DOBDO(0) => doutb(40),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(5),
WEA(2) => wea(5),
WEA(1) => wea(5),
WEA(0) => wea(5),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(5),
WEBWE(2) => web(5),
WEBWE(1) => web(5),
WEBWE(0) => web(5)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(39),
DIADI(6) => dina(38),
DIADI(5) => dina(37),
DIADI(4) => dina(36),
DIADI(3) => dina(35),
DIADI(2) => dina(34),
DIADI(1) => dina(33),
DIADI(0) => dina(32),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(39),
DIBDI(6) => dinb(38),
DIBDI(5) => dinb(37),
DIBDI(4) => dinb(36),
DIBDI(3) => dinb(35),
DIBDI(2) => dinb(34),
DIBDI(1) => dinb(33),
DIBDI(0) => dinb(32),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(39),
DOADO(6) => douta(38),
DOADO(5) => douta(37),
DOADO(4) => douta(36),
DOADO(3) => douta(35),
DOADO(2) => douta(34),
DOADO(1) => douta(33),
DOADO(0) => douta(32),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(39),
DOBDO(6) => doutb(38),
DOBDO(5) => doutb(37),
DOBDO(4) => doutb(36),
DOBDO(3) => doutb(35),
DOBDO(2) => doutb(34),
DOBDO(1) => doutb(33),
DOBDO(0) => doutb(32),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(4),
WEA(2) => wea(4),
WEA(1) => wea(4),
WEA(0) => wea(4),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(4),
WEBWE(2) => web(4),
WEBWE(1) => web(4),
WEBWE(0) => web(4)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(31),
DIADI(6) => dina(30),
DIADI(5) => dina(29),
DIADI(4) => dina(28),
DIADI(3) => dina(27),
DIADI(2) => dina(26),
DIADI(1) => dina(25),
DIADI(0) => dina(24),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(31),
DIBDI(6) => dinb(30),
DIBDI(5) => dinb(29),
DIBDI(4) => dinb(28),
DIBDI(3) => dinb(27),
DIBDI(2) => dinb(26),
DIBDI(1) => dinb(25),
DIBDI(0) => dinb(24),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(31),
DOADO(6) => douta(30),
DOADO(5) => douta(29),
DOADO(4) => douta(28),
DOADO(3) => douta(27),
DOADO(2) => douta(26),
DOADO(1) => douta(25),
DOADO(0) => douta(24),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(31),
DOBDO(6) => doutb(30),
DOBDO(5) => doutb(29),
DOBDO(4) => doutb(28),
DOBDO(3) => doutb(27),
DOBDO(2) => doutb(26),
DOBDO(1) => doutb(25),
DOBDO(0) => doutb(24),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(3),
WEA(2) => wea(3),
WEA(1) => wea(3),
WEA(0) => wea(3),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(3),
WEBWE(2) => web(3),
WEBWE(1) => web(3),
WEBWE(0) => web(3)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(23),
DIADI(6) => dina(22),
DIADI(5) => dina(21),
DIADI(4) => dina(20),
DIADI(3) => dina(19),
DIADI(2) => dina(18),
DIADI(1) => dina(17),
DIADI(0) => dina(16),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(23),
DIBDI(6) => dinb(22),
DIBDI(5) => dinb(21),
DIBDI(4) => dinb(20),
DIBDI(3) => dinb(19),
DIBDI(2) => dinb(18),
DIBDI(1) => dinb(17),
DIBDI(0) => dinb(16),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(23),
DOADO(6) => douta(22),
DOADO(5) => douta(21),
DOADO(4) => douta(20),
DOADO(3) => douta(19),
DOADO(2) => douta(18),
DOADO(1) => douta(17),
DOADO(0) => douta(16),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(23),
DOBDO(6) => doutb(22),
DOBDO(5) => doutb(21),
DOBDO(4) => doutb(20),
DOBDO(3) => doutb(19),
DOBDO(2) => doutb(18),
DOBDO(1) => doutb(17),
DOBDO(0) => doutb(16),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(2),
WEA(2) => wea(2),
WEA(1) => wea(2),
WEA(0) => wea(2),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(2),
WEBWE(2) => web(2),
WEBWE(1) => web(2),
WEBWE(0) => web(2)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(15),
DIADI(6) => dina(14),
DIADI(5) => dina(13),
DIADI(4) => dina(12),
DIADI(3) => dina(11),
DIADI(2) => dina(10),
DIADI(1) => dina(9),
DIADI(0) => dina(8),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(15),
DIBDI(6) => dinb(14),
DIBDI(5) => dinb(13),
DIBDI(4) => dinb(12),
DIBDI(3) => dinb(11),
DIBDI(2) => dinb(10),
DIBDI(1) => dinb(9),
DIBDI(0) => dinb(8),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(15),
DOADO(6) => douta(14),
DOADO(5) => douta(13),
DOADO(4) => douta(12),
DOADO(3) => douta(11),
DOADO(2) => douta(10),
DOADO(1) => douta(9),
DOADO(0) => douta(8),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(15),
DOBDO(6) => doutb(14),
DOBDO(5) => doutb(13),
DOBDO(4) => doutb(12),
DOBDO(3) => doutb(11),
DOBDO(2) => doutb(10),
DOBDO(1) => doutb(9),
DOBDO(0) => doutb(8),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(1),
WEA(2) => wea(1),
WEA(1) => wea(1),
WEA(0) => wea(1),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(1),
WEBWE(2) => web(1),
WEBWE(1) => web(1),
WEBWE(0) => web(1)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(7),
DIADI(6) => dina(6),
DIADI(5) => dina(5),
DIADI(4) => dina(4),
DIADI(3) => dina(3),
DIADI(2) => dina(2),
DIADI(1) => dina(1),
DIADI(0) => dina(0),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(7),
DIBDI(6) => dinb(6),
DIBDI(5) => dinb(5),
DIBDI(4) => dinb(4),
DIBDI(3) => dinb(3),
DIBDI(2) => dinb(2),
DIBDI(1) => dinb(1),
DIBDI(0) => dinb(0),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(7),
DOADO(6) => douta(6),
DOADO(5) => douta(5),
DOADO(4) => douta(4),
DOADO(3) => douta(3),
DOADO(2) => douta(2),
DOADO(1) => douta(1),
DOADO(0) => douta(0),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(7),
DOBDO(6) => doutb(6),
DOBDO(5) => doutb(5),
DOBDO(4) => doutb(4),
DOBDO(3) => doutb(3),
DOBDO(2) => doutb(2),
DOBDO(1) => doutb(1),
DOBDO(0) => doutb(0),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
-- synthesis translate_on
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_oc
-- File: can_oc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB interface for the OpenCores CAN MAC
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.can.all;
entity can_oc is
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
syncrst : integer := 0;
ft : integer := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic;
can_txo : out std_logic
);
end;
architecture rtl of can_oc is
constant ncores : integer := 1;
constant sepirq : integer := 0;
constant REVISION : amba_version_type := ncores-1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_CANAHB, 0, REVISION, irq),
4 => ahb_iobar(ioaddr, iomask), others => zero32);
type ahbregs is record
hsel : std_ulogic;
hwrite : std_ulogic;
hwrite2 : std_ulogic;
htrans : std_logic_vector(1 downto 0);
haddr : std_logic_vector(10 downto 0);
hwdata : std_logic_vector(7 downto 0);
herr : std_ulogic;
hready : std_ulogic;
ws : std_logic_vector(1 downto 0);
irqi : std_logic_vector(ncores-1 downto 0);
irqo : std_logic_vector(ncores-1 downto 0);
end record;
subtype cdata is std_logic_vector(7 downto 0);
type cdataarr is array (0 to 7) of cdata;
signal data_out : cdataarr;
signal reset : std_logic;
signal irqo : std_logic_vector(ncores-1 downto 0);
signal vcc, gnd : std_ulogic;
signal r, rin : ahbregs;
attribute sync_set_reset : string;
attribute sync_set_reset of reset : signal is "true";
begin
gnd <= '0'; vcc <= '1'; reset <= not resetn;
comb : process(ahbsi, r, resetn, data_out, irqo)
variable v : ahbregs;
variable hresp : std_logic_vector(1 downto 0);
variable dataout : std_logic_vector(7 downto 0);
variable irqvec : std_logic_vector(NAHBIRQ-1 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
begin
v := r;
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
if (r.hsel = '1' ) and (r.ws /= "11") then v.ws := r.ws + 1; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(slvndx);
v.haddr := ahbsi.haddr(10 downto 0);
v.htrans := ahbsi.htrans;
v.hwrite := ahbsi.hwrite;
v.herr := orv(ahbsi.hsize) and ahbsi.hwrite;
v.ws := "00";
end if;
v.hready := (r.hsel and r.ws(1) and not r.ws(0)) or not resetn
or (ahbsi.hready and not ahbsi.htrans(1)) or not v.hsel;
v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and not r.herr;
if (r.herr and r.ws(1)) = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
case r.haddr(1 downto 0) is
when "00" => v.hwdata := hwdata(31 downto 24);
when "01" => v.hwdata := hwdata(23 downto 16);
when "10" => v.hwdata := hwdata(15 downto 8);
when others => v.hwdata := hwdata(7 downto 0);
end case;
dataout := data_out(0);
-- Interrupt goes to low when appeard and is normal high
-- but the irq controller from leon is active high and the interrupt should appear only
-- for 1 Clk cycle,
v.irqi := irqo; v.irqo:= (r.irqi and not irqo);
irqvec := (others => '0');
if sepirq = 1 then irqvec(ncores-1+irq downto irq) := r.irqo;
else irqvec(irq) := orv(r.irqo); end if;
ahbso.hirq <= irqvec;
ahbso.hrdata <= ahbdrivedata(dataout);
ahbso.hresp <= hresp; rin <= v;
end process;
reg : process(clk)
begin if clk'event and clk = '1' then r <= rin; end if; end process;
cmod : can_mod generic map (memtech, syncrst, ft)
port map (reset, clk, r.hsel, r.hwrite2, r.haddr(7 downto 0), r.hwdata,
data_out(0), irqo(0), can_rxi, can_txo, ahbsi.testen);
ahbso.hconfig <= hconfig;
ahbso.hindex <= slvndx;
ahbso.hsplit <= (others => '0');
ahbso.hready <= r.hready;
-- pragma translate_off
bootmsg : report_version
generic map (
"can_oc" & tost(slvndx) &
": SJA1000 Compatible CAN MAC, revision " & tost(REVISION) &
", irq " & tost(irq));
-- pragma translate_on
end;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
kldB520mqnbfcwzuIVclXuW+6V5vvpmz91Igf7FoZKp/CUxyBKTRlVoTkC5cMm4Sk+inC3VxbZA6
C+YBKLNkvA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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WIXc3kwm9pBpDsFGLz8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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bN3PtEpCsE6vBbOb01ofrS/w1yov5YbyM7Aslw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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rbGAVG7aO25M0FaNuC8=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15424)
`protect data_block
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|
`protect begin_protected
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|
`protect begin_protected
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`protect end_protected
|
-------------------------------------------------------------------------------------
-- FILE NAME : .vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity - delay_bit
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : May 21, 2014
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
-- Delay a pulse by a a given number of cycles. While delaying we CAN'T accept
-- a new pulse.
--
--------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity delay_bit is
generic (
CYCLES : std_logic_vector(15 downto 0) := x"000F"
);
port (
clk : in std_logic;
rst : in std_logic;
bit_in : in std_logic;
bit_out : out std_logic
);
end delay_bit;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of delay_bit is
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
type DELAY_STATES is (
DELAY_IDLE,
DELAY_CNT,
DELAY_ASSERT
);
-----------------------------------------------------------------------------------
-- SIGNALS
-----------------------------------------------------------------------------------
signal state : DELAY_STATES;
signal count : std_logic_vector(15 downto 0);
--***********************************************************************************
begin
--***********************************************************************************
process (clk, rst) is
begin
if rising_edge(clk) then
if rst = '1' then
state <= DELAY_IDLE;
bit_out <= '0';
count <= (others=>'0');
else
-- default output
bit_out <= '0';
case state is
when DELAY_IDLE =>
if bit_in = '1' then
state <= DELAY_CNT;
end if;
when DELAY_CNT =>
if count /= CYCLES then
count <= count + 1;
else
count <= (others=>'0');
state <= DELAY_ASSERT;
end if;
when DELAY_ASSERT =>
bit_out <= '1';
state <= DELAY_IDLE;
when others =>
state <= DELAY_IDLE;
end case;
end if;
end if;
end process;
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Inv is
port (
a: in std_logic;
z : out std_logic
);
end Inv;
architecture Arch of Inv is
begin
Z <= not a;
end Arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Inv is
port (
a: in std_logic;
z : out std_logic
);
end Inv;
architecture Arch of Inv is
begin
Z <= not a;
end Arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Inv is
port (
a: in std_logic;
z : out std_logic
);
end Inv;
architecture Arch of Inv is
begin
Z <= not a;
end Arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc683.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:01 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:33 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:40 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00683ent IS
END c03s04b01x00p23n01i00683ent;
ARCHITECTURE c03s04b01x00p23n01i00683arch OF c03s04b01x00p23n01i00683ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type POSITIVE_R is range 0.0 to REAL'HIGH;
type FT is file of POSITIVE_R;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.54";
-- Declare a variable into which we will read.
constant CON : POSITIVE_R := 1.0;
variable VAR : POSITIVE_R;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00683"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00683 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00683arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc683.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:01 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:33 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:40 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00683ent IS
END c03s04b01x00p23n01i00683ent;
ARCHITECTURE c03s04b01x00p23n01i00683arch OF c03s04b01x00p23n01i00683ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type POSITIVE_R is range 0.0 to REAL'HIGH;
type FT is file of POSITIVE_R;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.54";
-- Declare a variable into which we will read.
constant CON : POSITIVE_R := 1.0;
variable VAR : POSITIVE_R;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00683"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00683 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00683arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc683.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:01 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:33 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:40 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00683ent IS
END c03s04b01x00p23n01i00683ent;
ARCHITECTURE c03s04b01x00p23n01i00683arch OF c03s04b01x00p23n01i00683ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type POSITIVE_R is range 0.0 to REAL'HIGH;
type FT is file of POSITIVE_R;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.54";
-- Declare a variable into which we will read.
constant CON : POSITIVE_R := 1.0;
variable VAR : POSITIVE_R;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00683"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00683 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00683arch;
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- syncronous ROM; FPGA version, word-indexed
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity ROM is
generic (LOAD_FILE_NAME : string := "prog.bin"); -- not used with FPGA
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
rdy : out std_logic; -- active in '0'
strobe : in std_logic;
addr : in reg32;
data : out reg32);
-- FPGA version
constant INST_ADDRS_BITS : natural := log2_ceil(INST_MEM_SZ);
subtype rom_address is natural range 0 to ((INST_MEM_SZ / 4) - 1);
end entity ROM;
architecture rtl of ROM is
component wait_states is
generic (NUM_WAIT_STATES :integer := 0);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
component single_port_rom is
generic (N_WORDS : integer);
port (address : in rom_address;
clken : in std_logic;
clock : in std_logic;
q : out std_logic_vector);
end component single_port_rom;
component alt_mf_rom
port (address : IN STD_LOGIC_VECTOR ((INST_ADDRS_BITS-1) DOWNTO 0);
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
end component alt_mf_rom;
signal instrn : reg32;
signal index : rom_address := 0;
signal waiting, clken : std_logic;
signal raw_addr : std_logic_vector((INST_ADDRS_BITS-1) downto 0);
begin -- rtl
U_BUS_WAIT: wait_states generic map (ROM_WAIT_STATES)
port map (rst, clk, sel, waiting);
rdy <= not(waiting);
clken <= not(sel);
-- >>2 = /4: byte addressed but word indexed
index <= to_integer(unsigned(addr((INST_ADDRS_BITS-1)+2 downto 2)));
-- U_ROM: single_port_rom generic map (INST_MEM_SZ / 4)
-- port map (index, clken, strobe, instrn);
raw_addr <= addr((INST_ADDRS_BITS-1)+2 downto 2);
U_RTL_ROM: alt_mf_rom port map (raw_addr, clken, strobe, instrn);
U_ROM_ACCESS: process (instrn, sel, index)
begin
if sel = '0' then
data <= instrn;
assert (index >= 0) and (index < INST_MEM_SZ/4)
report "rom index out of bounds: " & natural'image(index)
severity failure;
assert TRUE -- DEBUG
report "romRD["& natural'image(index) &"]="& SLV32HEX(instrn);
else
data <= (others => 'X');
end if;
end process U_ROM_ACCESS;
end architecture rtl;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Adapted from Altera's design for a ROM that may be synthesized
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.p_wires.all;
entity single_port_rom is
generic (N_WORDS : integer := 32);
port (address : in natural range 0 to (N_WORDS - 1);
clken : in std_logic;
clock : in std_logic;
q : out reg32);
end entity;
architecture rtl of single_port_rom is
-- Build a 2-D array type for the RoM
subtype word_t is std_logic_vector(31 downto 0);
type memory_t is array(0 to (N_WORDS-1)) of word_t;
-- assemble.sh -v mac_lcd.s |\
-- sed -e '1,6d' -e '/^$/d' -e '/^ /!d' -e 's:\t: :g' \
-- -e 's#\(^ *[a-f0-9]*:\) *\(........\) *\(.*\)$#x"\2", -- \1 \3#' \
-- -e '$s:,: :'
constant test_prog : memory_t := (others => (others => '0'));
function init_rom
return memory_t is
variable tmp : memory_t := (others => (others => '0'));
variable i_addr : integer;
begin
for addr_pos in test_prog'range loop
tmp(addr_pos) := test_prog(addr_pos);
-- i_addr := addr_pos;
end loop;
for addr_pos in test_prog'high to (N_WORDS - 1) loop
tmp(addr_pos) := x"00000000"; -- nop
end loop;
return tmp;
end init_rom;
-- Declare the ROM signal and specify a default value. Quartus II
-- will create a memory initialization file (ROM.mif) based on the
-- default value.
signal rom : memory_t := init_rom;
begin
process(clock,clken)
begin
if(clken = '1' and rising_edge(clock)) then
q <= rom(address);
end if;
end process;
end architecture rtl;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- syncronous ROM; MIPS executable loaded into ROM at CPU reset, wd-indexed
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture simulation of ROM is
component wait_states is
generic (NUM_WAIT_STATES :integer := 0);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
component FFT is
port(clk, rst, T : in std_logic; Q : out std_logic);
end component FFT;
constant WAIT_COUNT : max_wait_states := (NUM_MAX_W_STS - ROM_WAIT_STATES);
constant WAIT_FOR : reg10 := std_logic_vector(to_signed(WAIT_COUNT, 10));
signal waiting, do_wait : std_logic;
begin -- behavioral
U_BUS_WAIT: wait_states generic map (ROM_WAIT_STATES)
port map (rst, clk, sel, waiting);
rdy <= not(waiting);
U_ROM: process (rst, sel, strobe, addr)
subtype t_address is unsigned((INST_ADDRS_BITS - 1) downto 0);
variable u_addr : t_address;
subtype word is std_logic_vector(data'length - 1 downto 0);
type storage_array is
array( natural range 0 to (INST_MEM_SZ - 1) ) of word;
variable storage : storage_array;
variable index, latched : natural;
type binary_file is file of integer;
file load_file: binary_file open read_mode is LOAD_FILE_NAME;
variable instr: integer; -- := to_integer(unsigned(NULL_INSTRUCTION));
variable s_instr : signed(31 downto 0);
begin
if rst = '0' then -- reset, read binary executable
index := 0; -- indexed by word
for i in 0 to (INST_MEM_SZ - 1) loop
if not endfile(load_file) then
read(load_file, instr);
s_instr := to_signed(instr, 32);
assert TRUE report "romINIT["& natural'image(index*4) &"]= " &
SLV32HEX(std_logic_vector(s_instr)); -- DEBUG
storage(index) := std_logic_vector(s_instr);
index := index + 1;
end if;
end loop; -- i
else -- normal operation
if sel = '0' and rising_edge(strobe) then
u_addr := unsigned(addr((2+(INST_ADDRS_BITS-1)) downto 2)); -- >>2 = /4
index := to_integer(u_addr); -- indexed by word, not by byte
assert (index >= 0) and (index < INST_MEM_SZ/4)
report "romRDindex out of bounds: " & SLV32HEX(addr) & " = " &
natural'image(index) severity warning; -- failure;
latched := index;
end if;
if sel = '0' then
data <= storage(latched);
assert TRUE -- DEBUG
report
"romRD["& natural'image(index) &"]="& SLV32HEX(storage(index));
else
data <= (others => 'X');
end if;
end if;
end process;
end architecture simulation;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 10.12.2013 15:14:45
-- Design Name:
-- Module Name: output_queue_fifo - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013
--
-- Description: wrapper for the output queue fifo
-- the output queue fifo stores the length and output queue memory address of frames received
-- from the switching fabric temporarily until they can be tranismitted via the mac
--
-- further information can be found in switch_port_txpath_output_queue.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
entity output_queue_fifo is
Generic (
OQ_FIFO_DATA_WIDTH : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
oqfifo_in_enable : in std_logic;
oqfifo_in_data : in std_logic_vector(OQ_FIFO_DATA_WIDTH-1 downto 0);
oqfifo_in_wr_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
oqfifo_out_enable : in std_logic;
oqfifo_out_data : out std_logic_vector(NR_OQ_FIFOS*OQ_FIFO_DATA_WIDTH-1 downto 0);
oqfifo_out_rd_prio : in std_logic;
oqfifo_out_full : out std_logic_vector(NR_OQ_FIFOS-1 downto 0);
oqfifo_out_empty : out std_logic_vector(NR_OQ_FIFOS-1 downto 0)
);
end output_queue_fifo;
architecture rtl of output_queue_fifo is
component fifo_generator_2 is
port (
clk : in std_logic;
rst : in std_logic;
wr_en : in std_logic;
rd_en : in std_logic;
din : in std_logic_vector(OQ_FIFO_DATA_WIDTH-1 downto 0);
dout : out std_logic_vector(OQ_FIFO_DATA_WIDTH-1 downto 0);
full : out std_logic;
empty : out std_logic
);
end component;
signal rd_en_sig : std_logic_vector(NR_OQ_FIFOS-1 downto 0) := (others => '0');
signal wr_en_sig : std_logic_vector(NR_OQ_FIFOS-1 downto 0) := (others => '0');
signal high_priority_border_value_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0) := "001";
begin
init_p : process(oqfifo_out_enable, oqfifo_in_wr_prio, oqfifo_in_enable, oqfifo_out_rd_prio, high_priority_border_value_reg)
variable wr_temp : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0) := (others => '0');
variable rd_temp : std_logic_vector(0 downto 0) := (others => '0');
begin
rd_temp(0) := oqfifo_out_rd_prio;
wr_temp := oqfifo_in_wr_prio;
for i in 0 to NR_OQ_FIFOS-1 loop
-- read access
if (oqfifo_out_enable = '1' and to_integer(unsigned(rd_temp)) = i) then
rd_en_sig(i) <= '1';
else
rd_en_sig(i) <= '0';
end if;
-- write access
if NR_OQ_FIFOS = 1 then
wr_en_sig(0) <= oqfifo_in_enable;
else
if i = 0 then
if wr_temp >= high_priority_border_value_reg then
wr_en_sig(i) <= '0';
else
wr_en_sig(i) <= oqfifo_in_enable;
end if;
else
if wr_temp >= high_priority_border_value_reg then
wr_en_sig(i) <= oqfifo_in_enable;
else
wr_en_sig(i) <= '0';
end if;
end if;
end if;
end loop;
end process;
Xfifo : for i in 0 to NR_OQ_FIFOS-1 generate
output_queue_fifo_ip : fifo_generator_2
PORT MAP (
clk => clk,
rst => reset,
wr_en => wr_en_sig(i),
rd_en => rd_en_sig(i),
din => oqfifo_in_data,
dout => oqfifo_out_data((i+1)*OQ_FIFO_DATA_WIDTH-1 downto i*OQ_FIFO_DATA_WIDTH),
full => oqfifo_out_full(i),
empty => oqfifo_out_empty(i)
);
end generate Xfifo;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 10.12.2013 15:14:45
-- Design Name:
-- Module Name: output_queue_fifo - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013
--
-- Description: wrapper for the output queue fifo
-- the output queue fifo stores the length and output queue memory address of frames received
-- from the switching fabric temporarily until they can be tranismitted via the mac
--
-- further information can be found in switch_port_txpath_output_queue.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
entity output_queue_fifo is
Generic (
OQ_FIFO_DATA_WIDTH : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
oqfifo_in_enable : in std_logic;
oqfifo_in_data : in std_logic_vector(OQ_FIFO_DATA_WIDTH-1 downto 0);
oqfifo_in_wr_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
oqfifo_out_enable : in std_logic;
oqfifo_out_data : out std_logic_vector(NR_OQ_FIFOS*OQ_FIFO_DATA_WIDTH-1 downto 0);
oqfifo_out_rd_prio : in std_logic;
oqfifo_out_full : out std_logic_vector(NR_OQ_FIFOS-1 downto 0);
oqfifo_out_empty : out std_logic_vector(NR_OQ_FIFOS-1 downto 0)
);
end output_queue_fifo;
architecture rtl of output_queue_fifo is
component fifo_generator_2 is
port (
clk : in std_logic;
rst : in std_logic;
wr_en : in std_logic;
rd_en : in std_logic;
din : in std_logic_vector(OQ_FIFO_DATA_WIDTH-1 downto 0);
dout : out std_logic_vector(OQ_FIFO_DATA_WIDTH-1 downto 0);
full : out std_logic;
empty : out std_logic
);
end component;
signal rd_en_sig : std_logic_vector(NR_OQ_FIFOS-1 downto 0) := (others => '0');
signal wr_en_sig : std_logic_vector(NR_OQ_FIFOS-1 downto 0) := (others => '0');
signal high_priority_border_value_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0) := "001";
begin
init_p : process(oqfifo_out_enable, oqfifo_in_wr_prio, oqfifo_in_enable, oqfifo_out_rd_prio, high_priority_border_value_reg)
variable wr_temp : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0) := (others => '0');
variable rd_temp : std_logic_vector(0 downto 0) := (others => '0');
begin
rd_temp(0) := oqfifo_out_rd_prio;
wr_temp := oqfifo_in_wr_prio;
for i in 0 to NR_OQ_FIFOS-1 loop
-- read access
if (oqfifo_out_enable = '1' and to_integer(unsigned(rd_temp)) = i) then
rd_en_sig(i) <= '1';
else
rd_en_sig(i) <= '0';
end if;
-- write access
if NR_OQ_FIFOS = 1 then
wr_en_sig(0) <= oqfifo_in_enable;
else
if i = 0 then
if wr_temp >= high_priority_border_value_reg then
wr_en_sig(i) <= '0';
else
wr_en_sig(i) <= oqfifo_in_enable;
end if;
else
if wr_temp >= high_priority_border_value_reg then
wr_en_sig(i) <= oqfifo_in_enable;
else
wr_en_sig(i) <= '0';
end if;
end if;
end if;
end loop;
end process;
Xfifo : for i in 0 to NR_OQ_FIFOS-1 generate
output_queue_fifo_ip : fifo_generator_2
PORT MAP (
clk => clk,
rst => reset,
wr_en => wr_en_sig(i),
rd_en => rd_en_sig(i),
din => oqfifo_in_data,
dout => oqfifo_out_data((i+1)*OQ_FIFO_DATA_WIDTH-1 downto i*OQ_FIFO_DATA_WIDTH),
full => oqfifo_out_full(i),
empty => oqfifo_out_empty(i)
);
end generate Xfifo;
end rtl;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Martin Zabel
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This files bases on template lib/PoC/src/common/my_project.vhdl.template
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_project is
-- Change these lines to setup configuration.
constant MY_PROJECT_DIR : string := "CHANGE THIS"; -- e.g. "d:/vhdl/myproject/", "/home/me/projects/myproject/"
constant MY_OPERATING_SYSTEM : string := "CHANGE THIS"; -- e.g. "WINDOWS", "LINUX"
end package;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Martin Zabel
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This files bases on template lib/PoC/src/common/my_project.vhdl.template
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_project is
-- Change these lines to setup configuration.
constant MY_PROJECT_DIR : string := "CHANGE THIS"; -- e.g. "d:/vhdl/myproject/", "/home/me/projects/myproject/"
constant MY_OPERATING_SYSTEM : string := "CHANGE THIS"; -- e.g. "WINDOWS", "LINUX"
end package;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Martin Zabel
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This files bases on template lib/PoC/src/common/my_project.vhdl.template
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_project is
-- Change these lines to setup configuration.
constant MY_PROJECT_DIR : string := "CHANGE THIS"; -- e.g. "d:/vhdl/myproject/", "/home/me/projects/myproject/"
constant MY_OPERATING_SYSTEM : string := "CHANGE THIS"; -- e.g. "WINDOWS", "LINUX"
end package;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1204.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p08n03i01204ent IS
port ( signal O : out BIT );
END c08s01b00x00p08n03i01204ent;
ARCHITECTURE c08s01b00x00p08n03i01204arch OF c08s01b00x00p08n03i01204ent IS
BEGIN
TESTING: PROCESS
variable k : integer;
BEGIN
O <= '1';
wait on O;
assert FALSE
report "***FAILED TEST: c08s01b00x00p08n03i01204 - Signal name in the ON expression is not static."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p08n03i01204arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1204.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p08n03i01204ent IS
port ( signal O : out BIT );
END c08s01b00x00p08n03i01204ent;
ARCHITECTURE c08s01b00x00p08n03i01204arch OF c08s01b00x00p08n03i01204ent IS
BEGIN
TESTING: PROCESS
variable k : integer;
BEGIN
O <= '1';
wait on O;
assert FALSE
report "***FAILED TEST: c08s01b00x00p08n03i01204 - Signal name in the ON expression is not static."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p08n03i01204arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1204.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p08n03i01204ent IS
port ( signal O : out BIT );
END c08s01b00x00p08n03i01204ent;
ARCHITECTURE c08s01b00x00p08n03i01204arch OF c08s01b00x00p08n03i01204ent IS
BEGIN
TESTING: PROCESS
variable k : integer;
BEGIN
O <= '1';
wait on O;
assert FALSE
report "***FAILED TEST: c08s01b00x00p08n03i01204 - Signal name in the ON expression is not static."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p08n03i01204arch;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
use gaisler.i2c.all;
use gaisler.net.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
-- Clock and reset
diff_clkin_top_125_p: in std_ulogic;
diff_clkin_bot_125_p: in std_ulogic;
clkin_50_fpga_right: in std_ulogic;
clkin_50_fpga_top: in std_ulogic;
clkout_sma: out std_ulogic;
cpu_resetn: in std_ulogic;
-- DDR3
ddr3_ck_p: out std_ulogic;
ddr3_ck_n: out std_ulogic;
ddr3_cke: out std_ulogic;
ddr3_rstn: out std_ulogic;
ddr3_csn: out std_ulogic;
ddr3_rasn: out std_ulogic;
ddr3_casn: out std_ulogic;
ddr3_wen: out std_ulogic;
ddr3_ba: out std_logic_vector(2 downto 0);
ddr3_a : out std_logic_vector(13 downto 0);
ddr3_dqs_p: inout std_logic_vector(3 downto 0);
ddr3_dqs_n: inout std_logic_vector(3 downto 0);
ddr3_dq: inout std_logic_vector(31 downto 0);
ddr3_dm: out std_logic_vector(3 downto 0);
ddr3_odt: out std_ulogic;
ddr3_oct_rzq: in std_ulogic;
-- LPDDR2
lpddr2_ck_p: out std_ulogic;
lpddr2_ck_n: out std_ulogic;
lpddr2_cke: out std_ulogic;
lpddr2_a: out std_logic_vector(9 downto 0);
lpddr2_dqs_p: inout std_logic_vector(1 downto 0);
lpddr2_dqs_n: inout std_logic_vector(1 downto 0);
lpddr2_dq: inout std_logic_vector(15 downto 0);
lpddr2_dm: out std_logic_vector(1 downto 0);
lpddr2_csn: out std_ulogic;
lpddr2_oct_rzq: in std_ulogic;
-- Flash and SSRAM interface
fm_a: out std_logic_vector(26 downto 1);
fm_d: in std_logic_vector(15 downto 0);
flash_clk: out std_ulogic;
flash_resetn: out std_ulogic;
flash_cen: out std_ulogic; -- Driven const low by MAXV CPLD?
flash_advn: out std_ulogic;
flash_wen: out std_ulogic;
flash_oen: out std_ulogic;
flash_rdybsyn: in std_ulogic;
ssram_clk: out std_ulogic;
ssram_oen: out std_ulogic;
sram_cen: out std_ulogic;
ssram_bwen: out std_ulogic;
ssram_bwan: out std_ulogic;
ssram_bwbn: out std_ulogic;
ssram_adscn: out std_ulogic;
ssram_adspn: out std_ulogic;
ssram_zzn: out std_ulogic; -- Name incorrect, this is active high
ssram_advn: out std_ulogic;
-- EEPROM
eeprom_scl : inout std_ulogic;
eeprom_sda : inout std_ulogic;
-- UART
uart_rxd : in std_ulogic;
uart_rts : in std_ulogic; -- Note CTS and RTS mixed up on PCB
uart_txd : out std_ulogic;
uart_cts : out std_ulogic;
-- USB UART Interface
usb_uart_rstn : in std_ulogic; -- inout
usb_uart_ri : in std_ulogic;
usb_uart_dcd : in std_ulogic;
usb_uart_dtr : out std_ulogic;
usb_uart_dsr : in std_ulogic;
usb_uart_txd : out std_ulogic;
usb_uart_rxd : in std_ulogic;
usb_uart_rts : in std_ulogic;
usb_uart_cts : out std_ulogic;
usb_uart_gpio2 : in std_ulogic;
usb_uart_suspend : in std_ulogic;
usb_uart_suspendn : in std_ulogic;
-- Ethernet port A
eneta_rx_clk: in std_ulogic;
eneta_tx_clk: in std_ulogic;
eneta_intn: in std_ulogic;
eneta_resetn: out std_ulogic;
eneta_mdio: inout std_ulogic;
eneta_mdc: out std_ulogic;
eneta_rx_er: in std_ulogic;
eneta_tx_er: out std_ulogic;
eneta_rx_col: in std_ulogic;
eneta_rx_crs: in std_ulogic;
eneta_tx_d: out std_logic_vector(3 downto 0);
eneta_rx_d: in std_logic_vector(3 downto 0);
eneta_gtx_clk: out std_ulogic;
eneta_tx_en: out std_ulogic;
eneta_rx_dv: in std_ulogic;
-- Ethernet port B
enetb_rx_clk: in std_ulogic;
enetb_tx_clk: in std_ulogic;
enetb_intn: in std_ulogic;
enetb_resetn: out std_ulogic;
enetb_mdio: inout std_ulogic;
enetb_mdc: out std_ulogic;
enetb_rx_er: in std_ulogic;
enetb_tx_er: out std_ulogic;
enetb_rx_col: in std_ulogic;
enetb_rx_crs: in std_ulogic;
enetb_tx_d: out std_logic_vector(3 downto 0);
enetb_rx_d: in std_logic_vector(3 downto 0);
enetb_gtx_clk: out std_ulogic;
enetb_tx_en: out std_ulogic;
enetb_rx_dv: in std_ulogic;
-- LEDs, switches, GPIO
user_led : out std_logic_vector(3 downto 0);
user_dipsw : in std_logic_vector(3 downto 0);
dip_3p3V : in std_ulogic;
user_pb : in std_logic_vector(3 downto 0);
overtemp_fpga : out std_ulogic;
header_p : in std_logic_vector(5 downto 0); -- inout
header_n : in std_logic_vector(5 downto 0); -- inout
header_d : in std_logic_vector(7 downto 0); -- inout
-- LCD
lcd_data : in std_logic_vector(7 downto 0); -- inout
lcd_wen : out std_ulogic;
lcd_csn : out std_ulogic;
lcd_d_cn : out std_ulogic;
-- HIGH-SPEED-MEZZANINE-CARD Interface
-- This has been commented out as some pins have been placed in
-- violation with the Altera diff pad keep-out rules.
-- hsmc_clk_in0: in std_ulogic;
-- hsmc_clk_out0: out std_ulogic; -- changed due to placement rule
-- hsmc_clk_in_p: in std_logic_vector(2 downto 1);
-- hsmc_clk_out_p: out std_logic_vector(2 downto 1);
-- hsmc_d: in std_logic_vector(3 downto 0); -- inout
-- hsmc_tx_d_p: out std_logic_vector(16 downto 0);
-- hsmc_rx_d_p: in std_logic_vector(16 downto 0);
-- hsmc_rx_led: out std_ulogic;
-- hsmc_tx_led: out std_ulogic;
-- hsmc_scl: out std_ulogic; -- in due to placement rule
-- hsmc_sda: in std_ulogic; -- inout
-- hsmc_prsntn: in std_ulogic;
-- MAX V CPLD interface
max5_csn: out std_ulogic;
max5_wen: out std_ulogic;
max5_oen: out std_ulogic;
max5_ben: out std_logic_vector(3 downto 0);
max5_clk: out std_ulogic;
-- USB Blaster II
usb_clk : in std_ulogic;
usb_data : in std_logic_vector(7 downto 0); -- inout
usb_addr : in std_logic_vector(1 downto 0); -- inout
usb_scl : in std_ulogic; -- inout
usb_sda : in std_ulogic; -- inout
usb_resetn : in std_ulogic;
usb_oen : in std_ulogic;
usb_rdn : in std_ulogic;
usb_wrn : in std_ulogic;
usb_full : out std_ulogic;
usb_empty : out std_ulogic;
fx2_resetn : in std_ulogic
);
end;
architecture rtl of leon3mp is
constant USE_AHBREP: integer := 0
--pragma translate_off
+1
--pragma translate_on
;
-- Bus indexes
constant hmi_cpu : integer := 0;
constant hmi_greth1 : integer := hmi_cpu + CFG_NCPU;
constant hmi_greth2 : integer := hmi_greth1 + CFG_GRETH;
constant hmi_ahbuart : integer := hmi_greth2 + CFG_GRETH2;
constant hmi_ahbjtag : integer := hmi_ahbuart + CFG_AHB_UART;
constant nahbm : integer := hmi_ahbjtag + CFG_AHB_JTAG;
constant hsi_ssrctrl : integer := 0;
constant hsi_apbctrl : integer := hsi_ssrctrl + (CFG_SSCTRL + CFG_AHBROMEN + 1)/2;
constant hsi_dsu : integer := hsi_apbctrl + 1;
constant hsi_ddr3 : integer := hsi_dsu + CFG_DSU;
constant hsi_lpddr2 : integer := hsi_ddr3 + 1;
constant hsi_ahbrep : integer := hsi_lpddr2 + 1;
constant nahbs : integer := hsi_ahbrep + USE_AHBREP;
constant pi_irqmp : integer := 0;
constant pi_apbuart : integer := pi_irqmp + CFG_IRQ3_ENABLE;
constant pi_gpt : integer := pi_apbuart + CFG_UART1_ENABLE;
constant pi_ahbuart : integer := pi_gpt + CFG_GPT_ENABLE;
constant pi_ssrctrl : integer := pi_ahbuart + CFG_AHB_UART;
constant pi_greth1 : integer := pi_ssrctrl + CFG_SSCTRL;
constant pi_greth2 : integer := pi_greth1 + CFG_GRETH;
constant pi_i2cmst : integer := pi_greth2 + CFG_GRETH2;
constant napbs : integer := pi_i2cmst + CFG_I2C_ENABLE;
constant CPU_FREQ : integer := 75000;
signal clklock: std_ulogic;
signal clkm: std_ulogic;
signal ssclk: std_ulogic;
signal rstn: std_ulogic;
signal ahbmi: ahb_mst_in_type;
signal ahbmo: ahb_mst_out_vector;
signal ahbsi: ahb_slv_in_type;
signal ahbso: ahb_slv_out_vector;
signal apbi: apb_slv_in_type;
signal apbo: apb_slv_out_vector;
signal irqi: irq_in_vector(CFG_NCPU-1 downto 0);
signal irqo: irq_out_vector(CFG_NCPU-1 downto 0);
signal dbgi: l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo: l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui: dsu_in_type;
signal dsuo: dsu_out_type;
signal gpti: gptimer_in_type;
signal sri: memory_in_type;
signal sro: memory_out_type;
signal del_addr: std_logic_vector(26 downto 1);
signal del_ce: std_logic;
signal del_bwe, del_bwa, del_bwb: std_logic_vector(1 downto 0);
signal ui_serial, ui_usb, ui, dui: uart_in_type;
signal uo_serial, uo_usb, uo, duo: uart_out_type;
signal ethi1,ethi2: eth_in_type;
signal etho1,etho2: eth_out_type;
signal i2ci: i2c_in_type;
signal i2co: i2c_out_type;
signal vcc, gnd: std_ulogic;
-- signal logsig: std_logic_vector(31 downto 0);
begin
vcc <= '1';
gnd <= '0';
-----------------------------------------------------------------------------
-- Clocking and reset
-----------------------------------------------------------------------------
user_led(0) <= not clklock;
clkgen0: entity work.clkgen_c5ekit
port map (clkin_50_fpga_right, clkm, open, clklock);
rstgen0: rstgen
generic map (syncrst => CFG_NOASYNC)
port map (cpu_resetn, clkm, clklock, rstn);
-----------------------------------------------------------------------------
-- AMBA bus fabric
-----------------------------------------------------------------------------
ahbctrl0: ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN,ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
enbusmon => CFG_AHB_MON, assertwarn => CFG_AHB_MONWAR,
asserterr => CFG_AHB_MONERR, ahbtrace => CFG_AHB_DTRACE,
nahbm => nahbm, nahbs => nahbs)
port map (rstn,clkm,ahbmi,ahbmo,ahbsi,ahbso);
apbctrl0: apbctrl
generic map (hindex => hsi_apbctrl, haddr => CFG_APBADDR, nslaves => napbs)
port map (rstn,clkm,ahbsi,ahbso(hsi_apbctrl),apbi,apbo);
ahbmo(ahbmo'high downto nahbm) <= (others => ahbm_none);
ahbso(ahbso'high downto nahbs) <= (others => ahbs_none);
apbo(napbs to apbo'high) <= (others => apb_none);
-----------------------------------------------------------------------------
-- LEON3 Processor(s), DSU, timer and IRQ controller
-----------------------------------------------------------------------------
errorn_pad : outpad generic map (tech => padtech) port map (user_led(3), dbgo(0).error);
dsubre_pad : inpad generic map (tech => padtech) port map (user_pb(3), dsui.break);
user_led(2) <= not dsuo.active;
dsui.enable <= '1';
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => hsi_dsu, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(hsi_dsu), dbgo, dbgi, dsui, dsuo);
end generate;
end generate;
noleon: if CFG_LEON3 = 0 generate
irqo <= (others => ('0',"0000",'0','0','0'));
dbgo <= (others => dbgo_none);
end generate;
nodsu : if CFG_DSU = 0 or CFG_LEON3 = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; dsuo.pwd <= (others => '0');
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => pi_irqmp, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(pi_irqmp), irqo, irqi);
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => pi_gpt, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(pi_gpt), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
-----------------------------------------------------------------------------
-- Debug links
-----------------------------------------------------------------------------
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => hmi_ahbuart, pindex => pi_ahbuart, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(pi_ahbuart), ahbmi, ahbmo(hmi_ahbuart));
end generate;
nouah : if CFG_AHB_UART = 0 generate
duo.rtsn <= '0'; duo.txd <= '0';
duo.scaler <= (others => '0'); duo.txen <= '0';
duo.flow <= '0'; duo.rxen <= '0';
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => hmi_ahbjtag, nsync => 2)
port map(rstn, clkm, gnd, gnd, gnd, open, ahbmi, ahbmo(hmi_ahbjtag),
open, open, open, open, open, open, open, gnd);
end generate;
-- EDCL included in Ethernet below
-----------------------------------------------------------------------------
-- Memory controllers
-----------------------------------------------------------------------------
fm_a <= del_addr; -- sro.address(26 downto 1);
-- fm_d_pad: iopadvv
-- generic map (tech => padtech, width => 16)
-- port map (pad => fm_d, i => sro.data(31 downto 16),
-- en => sro.vbdrive(31 downto 16), o => sri.data(31 downto 16));
sri.data(31 downto 16) <= fm_d;
flash_clk <= '0';
flash_resetn <= '1';
flash_cen <= '0'; -- sro.romsn(0);
flash_advn <= '0';
flash_wen <= sro.writen or sro.romsn(0);
flash_oen <= sro.oen or sro.romsn(0);
ssram_clk <= clkm;
ssram_oen <= sro.oen;
sram_cen <= del_ce; -- sro.ramsn(0);
ssram_bwen <= del_bwe(1); -- sro.writen;
ssram_bwan <= del_bwa(1); -- sro.wrn(0);
ssram_bwbn <= del_bwb(1); -- sro.wrn(1);
ssram_adscn <= '1';
ssram_adspn <= '0';
ssram_zzn <= '0';
ssram_advn <= '1';
sri.data(15 downto 0) <= sri.data(31 downto 16);
sri.brdyn <= '1';
sri.bexcn <= '1';
sri.writen <= '1';
sri.wrn <= (others => '1');
sri.bwidth <= "01";
sri.sd <= (others => '0');
sri.cb <= (others => '0');
sri.scb <= (others => '0');
sri.edac <= '0';
delproc: process(clkm)
begin
if rising_edge(clkm) then
del_addr <= sro.address(26 downto 1);
del_ce <= sro.ramsn(0);
del_bwe <= del_bwe(0) & sro.writen;
del_bwa <= del_bwa(0) & sro.wrn(0);
del_bwb <= del_bwb(0) & sro.wrn(1);
end if;
end process;
ssrctrl: if CFG_SSCTRL = 1 generate
ssrctrl0: gaisler.memctrl.ssrctrl
generic map (hindex => hsi_ssrctrl, pindex => pi_ssrctrl,
romaddr => 16#000#, rommask => 16#fc0#,
ioaddr => 0, iomask => 0,
ramaddr => 0, rammask => 0,
bus16 => CFG_SSCTRLP16
)
port map (rstn, clkm, ahbsi, ahbso(hsi_ssrctrl), apbi, apbo(pi_ssrctrl), sri, sro);
end generate;
nossrctrl: if CFG_SSCTRL = 0 generate
sro <= memory_out_none;
end generate;
bpromgen : if CFG_AHBROMEN /= 0 and CFG_SSCTRL = 0 generate
brom : entity work.ahbrom
generic map (hindex => hsi_ssrctrl, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(hsi_ssrctrl));
end generate;
ddr3if0: entity work.ddr3if
generic map (
hindex => hsi_ddr3,
haddr => 16#400#, hmask => 16#E00#
) port map (
pll_ref_clk => diff_clkin_top_125_p,
global_reset_n => cpu_resetn,
mem_a => ddr3_a,
mem_ba => ddr3_ba,
mem_ck => ddr3_ck_p,
mem_ck_n => ddr3_ck_n,
mem_cke => ddr3_cke,
mem_reset_n => ddr3_rstn,
mem_cs_n => ddr3_csn,
mem_dm => ddr3_dm,
mem_ras_n => ddr3_rasn,
mem_cas_n => ddr3_casn,
mem_we_n => ddr3_wen,
mem_dq => ddr3_dq,
mem_dqs => ddr3_dqs_p,
mem_dqs_n => ddr3_dqs_n,
mem_odt => ddr3_odt,
oct_rzqin => ddr3_oct_rzq,
ahb_clk => clkm,
ahb_rst => rstn,
ahbsi => ahbsi,
ahbso => ahbso(hsi_ddr3)
);
lpddr2if0: entity work.lpddr2if
generic map (
hindex => hsi_lpddr2,
haddr => 16#600#, hmask => 16#F00#
) port map (
pll_ref_clk => diff_clkin_bot_125_p,
global_reset_n => cpu_resetn,
mem_ca => lpddr2_a,
mem_ck => lpddr2_ck_p,
mem_ck_n => lpddr2_ck_n,
mem_cke => lpddr2_cke,
mem_cs_n => lpddr2_csn,
mem_dm => lpddr2_dm,
mem_dq => lpddr2_dq,
mem_dqs => lpddr2_dqs_p,
mem_dqs_n => lpddr2_dqs_n,
oct_rzqin => lpddr2_oct_rzq,
ahb_clk => clkm,
ahb_rst => rstn,
ahbsi => ahbsi,
ahbso => ahbso(hsi_lpddr2)
);
-----------------------------------------------------------------------------
-- UART
-----------------------------------------------------------------------------
srx_pad : inpad generic map (tech => padtech) port map (uart_rxd, ui_serial.rxd);
srts_pad : inpad generic map (tech => padtech) port map (uart_rts, ui_serial.ctsn);
stx_pad : outpad generic map (tech => padtech) port map (uart_txd, uo_serial.txd);
scts_pad : outpad generic map (tech => padtech) port map (uart_cts, uo_serial.rtsn);
urx_pad : inpad generic map (tech => padtech) port map (usb_uart_rxd, ui_usb.rxd);
urts_pad : inpad generic map (tech => padtech) port map (usb_uart_rts, ui_usb.ctsn);
utx_pad : outpad generic map (tech => padtech) port map (usb_uart_txd, uo_usb.txd);
ucts_pad : outpad generic map (tech => padtech) port map (usb_uart_cts, uo_usb.rtsn);
usb_uart_dtr <= '0';
ui_serial.extclk <= '0'; ui_usb.extclk <= '0';
-- UART switch
ui <= ui_serial when user_dipsw(0)='0' else ui_usb;
dui <= ui_usb when user_dipsw(0)='0' else ui_serial;
uo_serial <= uo when user_dipsw(0)='0' else duo;
uo_usb <= duo when user_dipsw(0)='0' else uo;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => pi_apbuart, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(pi_apbuart), ui, uo);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate
uo.rtsn <= '0'; uo.txd <= '0'; uo.scaler <= (others => '0');
uo.txen <= '0'; uo.flow <= '0'; uo.rxen <= '0';
end generate;
-- AHBUART, see under Debug links above
-----------------------------------------------------------------------------
-- Ethernet
-----------------------------------------------------------------------------
emdio_pad : iopad generic map (tech => padtech)
port map (eneta_mdio, etho1.mdio_o, etho1.mdio_oe, ethi1.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (eneta_tx_clk, ethi1.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (eneta_rx_clk, ethi1.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (eneta_rx_d, ethi1.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (eneta_rx_dv, ethi1.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (eneta_rx_er, ethi1.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (eneta_rx_col, ethi1.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (eneta_rx_crs, ethi1.rx_crs);
emdint_pad : inpad generic map (tech => padtech)
port map (eneta_intn, ethi1.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (eneta_tx_d, etho1.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (eneta_tx_en, etho1.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (eneta_tx_er, etho1.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (eneta_mdc, etho1.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (eneta_resetn, rstn);
ethi1.rxd(ethi1.rxd'high downto 4) <= (others => '0');
ethi1.gtx_clk <= '0'; ethi1.rmii_clk <= '0';
emdio_pad2 : iopad generic map (tech => padtech)
port map (enetb_mdio, etho2.mdio_o, etho2.mdio_oe, ethi2.mdio_i);
etxc_pad2 : clkpad generic map (tech => padtech, arch => 2)
port map (enetb_tx_clk, ethi2.tx_clk);
erxc_pad2 : clkpad generic map (tech => padtech, arch => 2)
port map (enetb_rx_clk, ethi2.rx_clk);
erxd_pad2 : inpadv generic map (tech => padtech, width => 4)
port map (enetb_rx_d, ethi2.rxd(3 downto 0));
erxdv_pad2 : inpad generic map (tech => padtech)
port map (enetb_rx_dv, ethi2.rx_dv);
erxer_pad2 : inpad generic map (tech => padtech)
port map (enetb_rx_er, ethi2.rx_er);
erxco_pad2 : inpad generic map (tech => padtech)
port map (enetb_rx_col, ethi2.rx_col);
erxcr_pad2 : inpad generic map (tech => padtech)
port map (enetb_rx_crs, ethi2.rx_crs);
emdint_pad2 : inpad generic map (tech => padtech)
port map (enetb_intn, ethi2.mdint);
etxd_pad2 : outpadv generic map (tech => padtech, width => 4)
port map (enetb_tx_d, etho2.txd(3 downto 0));
etxen_pad2 : outpad generic map (tech => padtech)
port map (enetb_tx_en, etho2.tx_en);
etxer_pad2 : outpad generic map (tech => padtech)
port map (enetb_tx_er, etho2.tx_er);
emdc_pad2 : outpad generic map (tech => padtech)
port map (enetb_mdc, etho2.mdc);
erst_pad2 : outpad generic map (tech => padtech)
port map (enetb_resetn, rstn);
ethi2.rxd(ethi1.rxd'high downto 4) <= (others => '0');
ethi2.gtx_clk <= '0'; ethi2.rmii_clk <= '0';
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => hmi_greth1,
pindex => pi_greth1, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 0,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(hmi_greth1),
apbi => apbi, apbo => apbo(pi_greth1), ethi => ethi1, etho => etho1);
end generate;
noeth1 : if CFG_GRETH = 0 generate
etho1 <= eth_out_none;
end generate;
eth2 : if CFG_GRETH2 = 1 generate -- Secondary ethernet MAC
e2 : grethm generic map(hindex => hmi_greth2,
pindex => pi_greth2, paddr => 12, pirq => 13, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH2_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH21G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(hmi_greth2),
apbi => apbi, apbo => apbo(pi_greth2), ethi => ethi2, etho => etho2);
end generate;
noeth2 : if CFG_GRETH2 = 0 generate
etho2 <= eth_out_none;
end generate;
-----------------------------------------------------------------------------
-- GPIO
-----------------------------------------------------------------------------
-- TO DO
-----------------------------------------------------------------------------
-- Other
-----------------------------------------------------------------------------
max5_csn <= '1';
sclpad: iopad generic map (tech => padtech) port map (eeprom_scl, i2co.scl, i2co.scloen, i2ci.scl);
sdapad: iopad generic map (tech => padtech) port map (eeprom_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
i2c: if CFG_I2C_ENABLE=1 generate
i2cmst0: i2cmst
generic map (pindex => pi_i2cmst, paddr => 4, pmask => 16#FFF#, pirq => 4)
port map (rstn,clkm,apbi,apbo(pi_i2cmst),i2ci,i2co);
end generate;
noi2c: if CFG_I2C_ENABLE=0 generate
i2co <= (others => '1');
end generate;
-- logan0: logan
-- generic map (pindex => napbs-1, paddr => 16#100#, memtech => memtech)
-- port map (rstn, clkm, clkm, apbi, apbo(napbs-1), logsig);
--
-- logsig(31 downto 6) <= (others => '0');
-- logsig(5 downto 0) <= i2co.scl & i2co.scloen & i2ci.scl & i2co.sda & i2co.sdaoen & i2ci.sda;
-- pragma translate_off
rep: if USE_AHBREP/=0 generate
ahbrep0: ahbrep
generic map (hindex => hsi_ahbrep, haddr => 16#200#)
port map (rstn,clkm,ahbsi,ahbso(hsi_ahbrep));
end generate;
x : report_version
generic map (
msg1 => "LEON3 Altera CycloneV E Demonstration design",
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
-------------------------------------------------------------------------------
-- system_sram_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_mch_emc_v3_01_a;
use xps_mch_emc_v3_01_a.all;
entity system_sram_wrapper is
port (
MCH_SPLB_Clk : in std_logic;
RdClk : in std_logic;
MCH_SPLB_Rst : in std_logic;
MCH0_Access_Control : in std_logic;
MCH0_Access_Data : in std_logic_vector(0 to 31);
MCH0_Access_Write : in std_logic;
MCH0_Access_Full : out std_logic;
MCH0_ReadData_Control : out std_logic;
MCH0_ReadData_Data : out std_logic_vector(0 to 31);
MCH0_ReadData_Read : in std_logic;
MCH0_ReadData_Exists : out std_logic;
MCH1_Access_Control : in std_logic;
MCH1_Access_Data : in std_logic_vector(0 to 31);
MCH1_Access_Write : in std_logic;
MCH1_Access_Full : out std_logic;
MCH1_ReadData_Control : out std_logic;
MCH1_ReadData_Data : out std_logic_vector(0 to 31);
MCH1_ReadData_Read : in std_logic;
MCH1_ReadData_Exists : out std_logic;
MCH2_Access_Control : in std_logic;
MCH2_Access_Data : in std_logic_vector(0 to 31);
MCH2_Access_Write : in std_logic;
MCH2_Access_Full : out std_logic;
MCH2_ReadData_Control : out std_logic;
MCH2_ReadData_Data : out std_logic_vector(0 to 31);
MCH2_ReadData_Read : in std_logic;
MCH2_ReadData_Exists : out std_logic;
MCH3_Access_Control : in std_logic;
MCH3_Access_Data : in std_logic_vector(0 to 31);
MCH3_Access_Write : in std_logic;
MCH3_Access_Full : out std_logic;
MCH3_ReadData_Control : out std_logic;
MCH3_ReadData_Data : out std_logic_vector(0 to 31);
MCH3_ReadData_Read : in std_logic;
MCH3_ReadData_Exists : out std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 2);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 5);
Sl_MWrErr : out std_logic_vector(0 to 5);
Sl_MRdErr : out std_logic_vector(0 to 5);
Sl_MIRQ : out std_logic_vector(0 to 5);
Mem_DQ_I : in std_logic_vector(0 to 31);
Mem_DQ_O : out std_logic_vector(0 to 31);
Mem_DQ_T : out std_logic_vector(0 to 31);
Mem_A : out std_logic_vector(0 to 31);
Mem_RPN : out std_logic;
Mem_CEN : out std_logic_vector(0 to 0);
Mem_OEN : out std_logic_vector(0 to 0);
Mem_WEN : out std_logic;
Mem_QWEN : out std_logic_vector(0 to 3);
Mem_BEN : out std_logic_vector(0 to 3);
Mem_CE : out std_logic_vector(0 to 0);
Mem_ADV_LDN : out std_logic;
Mem_LBON : out std_logic;
Mem_CKEN : out std_logic;
Mem_RNW : out std_logic
);
end system_sram_wrapper;
architecture STRUCTURE of system_sram_wrapper is
component xps_mch_emc is
generic (
C_FAMILY : STRING;
C_NUM_BANKS_MEM : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_PRIORITY_MODE : INTEGER;
C_INCLUDE_PLB_IPIF : INTEGER;
C_INCLUDE_WRBUF : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_MCH_SPLB_AWIDTH : INTEGER;
C_SPLB_SMALLEST_MASTER : INTEGER;
C_MCH_NATIVE_DWIDTH : INTEGER;
C_MCH_SPLB_CLK_PERIOD_PS : INTEGER;
C_MEM0_BASEADDR : std_logic_vector;
C_MEM0_HIGHADDR : std_logic_vector;
C_MEM1_BASEADDR : std_logic_vector;
C_MEM1_HIGHADDR : std_logic_vector;
C_MEM2_BASEADDR : std_logic_vector;
C_MEM2_HIGHADDR : std_logic_vector;
C_MEM3_BASEADDR : std_logic_vector;
C_MEM3_HIGHADDR : std_logic_vector;
C_PAGEMODE_FLASH_0 : INTEGER;
C_PAGEMODE_FLASH_1 : INTEGER;
C_PAGEMODE_FLASH_2 : INTEGER;
C_PAGEMODE_FLASH_3 : INTEGER;
C_INCLUDE_NEGEDGE_IOREGS : INTEGER;
C_MEM0_WIDTH : INTEGER;
C_MEM1_WIDTH : INTEGER;
C_MEM2_WIDTH : INTEGER;
C_MEM3_WIDTH : INTEGER;
C_MAX_MEM_WIDTH : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_0 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_1 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_2 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_3 : INTEGER;
C_SYNCH_MEM_0 : INTEGER;
C_SYNCH_PIPEDELAY_0 : INTEGER;
C_TCEDV_PS_MEM_0 : INTEGER;
C_TAVDV_PS_MEM_0 : INTEGER;
C_TPACC_PS_FLASH_0 : INTEGER;
C_THZCE_PS_MEM_0 : INTEGER;
C_THZOE_PS_MEM_0 : INTEGER;
C_TWC_PS_MEM_0 : INTEGER;
C_TWP_PS_MEM_0 : INTEGER;
C_TLZWE_PS_MEM_0 : INTEGER;
C_SYNCH_MEM_1 : INTEGER;
C_SYNCH_PIPEDELAY_1 : INTEGER;
C_TCEDV_PS_MEM_1 : INTEGER;
C_TAVDV_PS_MEM_1 : INTEGER;
C_TPACC_PS_FLASH_1 : INTEGER;
C_THZCE_PS_MEM_1 : INTEGER;
C_THZOE_PS_MEM_1 : INTEGER;
C_TWC_PS_MEM_1 : INTEGER;
C_TWP_PS_MEM_1 : INTEGER;
C_TLZWE_PS_MEM_1 : INTEGER;
C_SYNCH_MEM_2 : INTEGER;
C_SYNCH_PIPEDELAY_2 : INTEGER;
C_TCEDV_PS_MEM_2 : INTEGER;
C_TAVDV_PS_MEM_2 : INTEGER;
C_TPACC_PS_FLASH_2 : INTEGER;
C_THZCE_PS_MEM_2 : INTEGER;
C_THZOE_PS_MEM_2 : INTEGER;
C_TWC_PS_MEM_2 : INTEGER;
C_TWP_PS_MEM_2 : INTEGER;
C_TLZWE_PS_MEM_2 : INTEGER;
C_SYNCH_MEM_3 : INTEGER;
C_SYNCH_PIPEDELAY_3 : INTEGER;
C_TCEDV_PS_MEM_3 : INTEGER;
C_TAVDV_PS_MEM_3 : INTEGER;
C_TPACC_PS_FLASH_3 : INTEGER;
C_THZCE_PS_MEM_3 : INTEGER;
C_THZOE_PS_MEM_3 : INTEGER;
C_TWC_PS_MEM_3 : INTEGER;
C_TWP_PS_MEM_3 : INTEGER;
C_TLZWE_PS_MEM_3 : INTEGER;
C_MCH0_PROTOCOL : INTEGER;
C_MCH0_ACCESSBUF_DEPTH : INTEGER;
C_MCH0_RDDATABUF_DEPTH : INTEGER;
C_MCH1_PROTOCOL : INTEGER;
C_MCH1_ACCESSBUF_DEPTH : INTEGER;
C_MCH1_RDDATABUF_DEPTH : INTEGER;
C_MCH2_PROTOCOL : INTEGER;
C_MCH2_ACCESSBUF_DEPTH : INTEGER;
C_MCH2_RDDATABUF_DEPTH : INTEGER;
C_MCH3_PROTOCOL : INTEGER;
C_MCH3_ACCESSBUF_DEPTH : INTEGER;
C_MCH3_RDDATABUF_DEPTH : INTEGER;
C_XCL0_LINESIZE : INTEGER;
C_XCL0_WRITEXFER : INTEGER;
C_XCL1_LINESIZE : INTEGER;
C_XCL1_WRITEXFER : INTEGER;
C_XCL2_LINESIZE : INTEGER;
C_XCL2_WRITEXFER : INTEGER;
C_XCL3_LINESIZE : INTEGER;
C_XCL3_WRITEXFER : INTEGER
);
port (
MCH_SPLB_Clk : in std_logic;
RdClk : in std_logic;
MCH_SPLB_Rst : in std_logic;
MCH0_Access_Control : in std_logic;
MCH0_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH0_Access_Write : in std_logic;
MCH0_Access_Full : out std_logic;
MCH0_ReadData_Control : out std_logic;
MCH0_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH0_ReadData_Read : in std_logic;
MCH0_ReadData_Exists : out std_logic;
MCH1_Access_Control : in std_logic;
MCH1_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH1_Access_Write : in std_logic;
MCH1_Access_Full : out std_logic;
MCH1_ReadData_Control : out std_logic;
MCH1_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH1_ReadData_Read : in std_logic;
MCH1_ReadData_Exists : out std_logic;
MCH2_Access_Control : in std_logic;
MCH2_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH2_Access_Write : in std_logic;
MCH2_Access_Full : out std_logic;
MCH2_ReadData_Control : out std_logic;
MCH2_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH2_ReadData_Read : in std_logic;
MCH2_ReadData_Exists : out std_logic;
MCH3_Access_Control : in std_logic;
MCH3_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH3_Access_Write : in std_logic;
MCH3_Access_Full : out std_logic;
MCH3_ReadData_Control : out std_logic;
MCH3_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH3_ReadData_Read : in std_logic;
MCH3_ReadData_Exists : out std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Mem_DQ_I : in std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
Mem_DQ_O : out std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
Mem_DQ_T : out std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
Mem_A : out std_logic_vector(0 to (C_MCH_SPLB_AWIDTH-1));
Mem_RPN : out std_logic;
Mem_CEN : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
Mem_OEN : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
Mem_WEN : out std_logic;
Mem_QWEN : out std_logic_vector(0 to ((C_MAX_MEM_WIDTH/8)-1));
Mem_BEN : out std_logic_vector(0 to ((C_MAX_MEM_WIDTH/8)-1));
Mem_CE : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
Mem_ADV_LDN : out std_logic;
Mem_LBON : out std_logic;
Mem_CKEN : out std_logic;
Mem_RNW : out std_logic
);
end component;
begin
SRAM : xps_mch_emc
generic map (
C_FAMILY => "virtex5",
C_NUM_BANKS_MEM => 1,
C_NUM_CHANNELS => 0,
C_PRIORITY_MODE => 0,
C_INCLUDE_PLB_IPIF => 1,
C_INCLUDE_WRBUF => 1,
C_SPLB_MID_WIDTH => 3,
C_SPLB_NUM_MASTERS => 6,
C_SPLB_P2P => 0,
C_SPLB_DWIDTH => 64,
C_MCH_SPLB_AWIDTH => 32,
C_SPLB_SMALLEST_MASTER => 32,
C_MCH_NATIVE_DWIDTH => 32,
C_MCH_SPLB_CLK_PERIOD_PS => 8000,
C_MEM0_BASEADDR => X"9af00000",
C_MEM0_HIGHADDR => X"9affffff",
C_MEM1_BASEADDR => X"ffffffff",
C_MEM1_HIGHADDR => X"00000000",
C_MEM2_BASEADDR => X"ffffffff",
C_MEM2_HIGHADDR => X"00000000",
C_MEM3_BASEADDR => X"ffffffff",
C_MEM3_HIGHADDR => X"00000000",
C_PAGEMODE_FLASH_0 => 0,
C_PAGEMODE_FLASH_1 => 0,
C_PAGEMODE_FLASH_2 => 0,
C_PAGEMODE_FLASH_3 => 0,
C_INCLUDE_NEGEDGE_IOREGS => 0,
C_MEM0_WIDTH => 32,
C_MEM1_WIDTH => 32,
C_MEM2_WIDTH => 32,
C_MEM3_WIDTH => 32,
C_MAX_MEM_WIDTH => 32,
C_INCLUDE_DATAWIDTH_MATCHING_0 => 0,
C_INCLUDE_DATAWIDTH_MATCHING_1 => 0,
C_INCLUDE_DATAWIDTH_MATCHING_2 => 0,
C_INCLUDE_DATAWIDTH_MATCHING_3 => 0,
C_SYNCH_MEM_0 => 1,
C_SYNCH_PIPEDELAY_0 => 2,
C_TCEDV_PS_MEM_0 => 0,
C_TAVDV_PS_MEM_0 => 0,
C_TPACC_PS_FLASH_0 => 25000,
C_THZCE_PS_MEM_0 => 0,
C_THZOE_PS_MEM_0 => 0,
C_TWC_PS_MEM_0 => 0,
C_TWP_PS_MEM_0 => 0,
C_TLZWE_PS_MEM_0 => 0,
C_SYNCH_MEM_1 => 0,
C_SYNCH_PIPEDELAY_1 => 2,
C_TCEDV_PS_MEM_1 => 15000,
C_TAVDV_PS_MEM_1 => 15000,
C_TPACC_PS_FLASH_1 => 25000,
C_THZCE_PS_MEM_1 => 7000,
C_THZOE_PS_MEM_1 => 7000,
C_TWC_PS_MEM_1 => 15000,
C_TWP_PS_MEM_1 => 12000,
C_TLZWE_PS_MEM_1 => 0,
C_SYNCH_MEM_2 => 0,
C_SYNCH_PIPEDELAY_2 => 2,
C_TCEDV_PS_MEM_2 => 15000,
C_TAVDV_PS_MEM_2 => 15000,
C_TPACC_PS_FLASH_2 => 25000,
C_THZCE_PS_MEM_2 => 7000,
C_THZOE_PS_MEM_2 => 7000,
C_TWC_PS_MEM_2 => 15000,
C_TWP_PS_MEM_2 => 12000,
C_TLZWE_PS_MEM_2 => 0,
C_SYNCH_MEM_3 => 0,
C_SYNCH_PIPEDELAY_3 => 2,
C_TCEDV_PS_MEM_3 => 15000,
C_TAVDV_PS_MEM_3 => 15000,
C_TPACC_PS_FLASH_3 => 25000,
C_THZCE_PS_MEM_3 => 7000,
C_THZOE_PS_MEM_3 => 7000,
C_TWC_PS_MEM_3 => 15000,
C_TWP_PS_MEM_3 => 12000,
C_TLZWE_PS_MEM_3 => 0,
C_MCH0_PROTOCOL => 0,
C_MCH0_ACCESSBUF_DEPTH => 16,
C_MCH0_RDDATABUF_DEPTH => 16,
C_MCH1_PROTOCOL => 0,
C_MCH1_ACCESSBUF_DEPTH => 16,
C_MCH1_RDDATABUF_DEPTH => 16,
C_MCH2_PROTOCOL => 0,
C_MCH2_ACCESSBUF_DEPTH => 16,
C_MCH2_RDDATABUF_DEPTH => 16,
C_MCH3_PROTOCOL => 0,
C_MCH3_ACCESSBUF_DEPTH => 16,
C_MCH3_RDDATABUF_DEPTH => 16,
C_XCL0_LINESIZE => 4,
C_XCL0_WRITEXFER => 1,
C_XCL1_LINESIZE => 4,
C_XCL1_WRITEXFER => 1,
C_XCL2_LINESIZE => 4,
C_XCL2_WRITEXFER => 1,
C_XCL3_LINESIZE => 4,
C_XCL3_WRITEXFER => 1
)
port map (
MCH_SPLB_Clk => MCH_SPLB_Clk,
RdClk => RdClk,
MCH_SPLB_Rst => MCH_SPLB_Rst,
MCH0_Access_Control => MCH0_Access_Control,
MCH0_Access_Data => MCH0_Access_Data,
MCH0_Access_Write => MCH0_Access_Write,
MCH0_Access_Full => MCH0_Access_Full,
MCH0_ReadData_Control => MCH0_ReadData_Control,
MCH0_ReadData_Data => MCH0_ReadData_Data,
MCH0_ReadData_Read => MCH0_ReadData_Read,
MCH0_ReadData_Exists => MCH0_ReadData_Exists,
MCH1_Access_Control => MCH1_Access_Control,
MCH1_Access_Data => MCH1_Access_Data,
MCH1_Access_Write => MCH1_Access_Write,
MCH1_Access_Full => MCH1_Access_Full,
MCH1_ReadData_Control => MCH1_ReadData_Control,
MCH1_ReadData_Data => MCH1_ReadData_Data,
MCH1_ReadData_Read => MCH1_ReadData_Read,
MCH1_ReadData_Exists => MCH1_ReadData_Exists,
MCH2_Access_Control => MCH2_Access_Control,
MCH2_Access_Data => MCH2_Access_Data,
MCH2_Access_Write => MCH2_Access_Write,
MCH2_Access_Full => MCH2_Access_Full,
MCH2_ReadData_Control => MCH2_ReadData_Control,
MCH2_ReadData_Data => MCH2_ReadData_Data,
MCH2_ReadData_Read => MCH2_ReadData_Read,
MCH2_ReadData_Exists => MCH2_ReadData_Exists,
MCH3_Access_Control => MCH3_Access_Control,
MCH3_Access_Data => MCH3_Access_Data,
MCH3_Access_Write => MCH3_Access_Write,
MCH3_Access_Full => MCH3_Access_Full,
MCH3_ReadData_Control => MCH3_ReadData_Control,
MCH3_ReadData_Data => MCH3_ReadData_Data,
MCH3_ReadData_Read => MCH3_ReadData_Read,
MCH3_ReadData_Exists => MCH3_ReadData_Exists,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Mem_DQ_I => Mem_DQ_I,
Mem_DQ_O => Mem_DQ_O,
Mem_DQ_T => Mem_DQ_T,
Mem_A => Mem_A,
Mem_RPN => Mem_RPN,
Mem_CEN => Mem_CEN,
Mem_OEN => Mem_OEN,
Mem_WEN => Mem_WEN,
Mem_QWEN => Mem_QWEN,
Mem_BEN => Mem_BEN,
Mem_CE => Mem_CE,
Mem_ADV_LDN => Mem_ADV_LDN,
Mem_LBON => Mem_LBON,
Mem_CKEN => Mem_CKEN,
Mem_RNW => Mem_RNW
);
end architecture STRUCTURE;
|
----------------------------------------------------------------------------|
-- Author : Miguel Morales-Sandoval Copyrights (R) |
-- Project : " Reconfigurable ECC" |
-- Organization : INAOE, Computer Science Department |
-- Date : Originally created March, 2007. |
----------------------------------------------------------------------------|
-- / o o \ This the binary method to compute |
-- / - o o - \ scalar multiplication in affine |
-- / --- o o --- \ coordinates. It uses a module that |
-- / ---- o o ---- \ implements the ECC-ADD and ECC-DOUBLE |
-- /------ o o ----- \ at the same time. The operations are |
-- / ----- o o ----- \ performed serially. This is a 163 bit |
-- / o o o o o o \ implementation. |
-- x x x |
-- x ----- x |
-- x ------- x |
-- x --------- x |
-- x --------- x |
-- ------------- |
-- _ _ _ _ ___ ___ |
-- | || \ | | / _ \ | _ || __| |
-- | || \| || |_| ||| ||||__ |
-- | || \ | || _ |||_||||__ |
-- |_||_|\__||_| |_||___||___| |
----------------------------------------------------------------------------|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity binaryMethod is
generic(
--------------------------------------------------------------
-- para la entrada y salida
CW : positive := 29; -- 15 29 29, 23, 11, 5, 7, 5 :- bits que "faltan" para ser multiplo de 32
WORD : positive := 32; -- 32 32 32, 32, 32, 32, 32, 32 :- Numero de palabra de entrada
ITR : positive := 5; -- 4 5 6, 8, 9, 9, 13, 18 :- No. de iteraciones en la máquina de estados
--------------------------------------------------------------
-- 113 131 163, 233, 277, 283, 409, 571
-- para el squarer
--------------------------------------------------------------
-- D : positive := 10; -- 11 10 9, 76, 14, 14, 89, 12 -- el "grado mas grande" para el polinomio en el campo m + 2
-- NUM2_BITS: positive := 261; --225 261 325, 465, 553, 565, 817, 1141 -- 2*NUMBITS -1
--------------------------------------------------------------
--113 131 163, 233, 277, 283, 409, 571
-- El nivel de seguridad
NUM_BITS: positive := 131
);
port(
valid_data_in :in std_logic;
valid_data_out :out std_logic;
ack_master :in std_logic;
ack_slave :out std_logic;
data_in : in std_logic_vector(WORD-1 downto 0);
data_out : out std_logic_vector(WORD-1 downto 0);
op : in std_logic; -- 0 -> Scalar multiplication, 1 -> SUM of points
clk : in std_logic;
rst : in std_logic
);
end;
------------------------------------------------------------------
architecture behave of BinaryMethod is
------------------------------------------------------------------
-- se agregaron mas estados para controlar la carga de los
-- operadores de la multiplicación escalar o de la suma
type CurrentState_type is (END_STATE, WAIT_DATA, WAIT_MORE, SEND_MORE, SEND_DATA, MODE0, WAIT_FINISH);
signal CurrentState: CurrentState_type;
------------------------------------------------------------------
signal Q_X: std_logic_vector(NUM_BITS-1 downto 0); -- Registros para manterner las operaciones ADD y Double
signal Q_Y: std_logic_vector(NUM_BITS-1 downto 0);
signal P_X: std_logic_vector(NUM_BITS-1 downto 0);
signal P_Y: std_logic_vector(NUM_BITS-1 downto 0);
signal counter: std_logic_vector(7 downto 0); -- Counter, indicates the number of iterations (m)
------------------------------------------------------------------
signal RstADD : std_logic; -- Interface signals for the ADD-Double module
signal ADD_X : std_logic_vector(NUM_BITS-1 downto 0);
signal ADD_Y : std_logic_vector(NUM_BITS-1 downto 0);
signal DoneADD: std_logic;
signal op_ADD: std_logic;
------------------------------------------------------------------
signal internal_regk : std_logic_vector(NUM_BITS-1 downto 0); -- Register to keep the shifth value of the scalar
signal K_SHIFT : std_logic_vector(NUM_BITS-1 downto 0); -- The combinatorial shifter for the scalar
------------------------------------------------------------------
-- Estas señales se agregaron para controlar y carga y salida de
-- valores desde/hacia el modulo KP
signal B_x_in : std_logic_vector((NUM_BITS+CW)-1 downto 0); -- 1 Registros de NUM_BITS bits para el siguiente corrimiento
signal B_X_shift : std_logic_vector((NUM_BITS+CW)-1 downto 0); -- Corrimiento combinacional
signal counter_word : std_logic_vector(4 downto 0); -- Contador para la carga del dato
signal mux_input : std_logic_vector(WORD-1 downto 0); -- Contador para la carga del dato
------------------------------------------------------------------
begin
------------------------------------------------------------------
-- The ADD module
ECC_ADD: entity ECC_add_serial_131(behave)
--Generic Map (D, NUM2_BITS, NUM_BITS)
Generic Map (NUM_BITS)
Port Map(Q_X, Q_Y, P_X, P_Y, clk, RstADD, op_ADD, ADD_X, ADD_Y, DoneADD);
k_shift <= internal_regk(NUM_BITS-2 downto 0) & '0'; -- Shift the scalar every time
mux_input <= data_in when currentState = WAIT_DATA else
(others => '0');
B_x_shift <= B_x_in((NUM_BITS+CW)-WORD-1 downto 0) & mux_input;
data_out <= B_x_in(NUM_BITS+CW-1 downto NUM_BITS+CW-WORD);
------------------------------------------------------------------
-- Finite state machine that implements the LEFT-TO-RIGTH
-- binary method, ADD and DOUBLING are performed serially
------------------------------------------------------------------
SCALAR_MUL_FSM: process (CLK)
Begin -- Inferencias de 6 registros de m y m+CW bits
if CLK'event and CLK = '1' then
if Rst = '1' then -- synchronous reset
Q_X <= (others => '0'); -- registros internos
Q_Y <= (others => '0'); -- para suma y double
P_X <= (others => '0');
P_Y <= (others => '0');
B_x_in <= (others => '0');
internal_regk <= (others => '0'); -- registro de corrimiento del escalar k
RstADD <= '0'; -- Señales de control para los bloques ADD y DOUBLE
counter_word <= (others => '0'); -- contador para capturar las palabras de entrada
counter <= (others => '0'); -- contador para la multiplicación escalar
CurrentState <= WAIT_DATA; -- El estado para esperar la primera secuencia de WORDS
ack_slave <= '0';
valid_data_out <= '0'; -- Señal de salida que habilida WORDs validos a la salida
else
case CurrentState is
----------------------------------------------------
when WAIT_DATA =>
if valid_data_in = '1' then
B_X_in <= B_x_shift;
ack_slave <= '1';
if counter_word = "00101" then -- ITR
P_X <= B_X_in(NUM_BITS-1 downto 0);
CurrentState <= WAIT_MORE;
elsif counter_word = "01010" then -- 2*ITR
P_Y <= B_X_in(NUM_BITS-1 downto 0);
CurrentState <= WAIT_MORE;
elsif counter_word = "01111" then -- 3*ITR
if op = '0' then -- multiplicación escalar
internal_regk <= B_x_in(NUM_BITS-1 downto 0); -- Lo que se leyo es el escalar, comenzar a ejecutar kP
op_ADD <= '0'; --Double
RstADD <= '1';
CurrentState <= MODE0;
else
Q_x <= B_X_in(NUM_BITS-1 downto 0);
CurrentState <= WAIT_MORE;
end if;
elsif counter_word = "10100" then --4*ITR
Q_Y <= B_X_in(NUM_BITS-1 downto 0); -- Ya tenemos los dos puntos, hacemos la suma
op_ADD <= '1'; --ADD
RstADD <= '1';
CurrentState <= MODE0;
else
CurrentState <= WAIT_MORE;
end if;
end if;
----------------------------------------------------
when WAIT_MORE => -- Espera a que el host regrese subtype señal de dato valido a cero
if valid_data_in = '0' then
ack_slave <= '0';
CurrentState <= WAIT_DATA;
Counter_word <= Counter_word + "00001";
end if;
----------------------------------------------------
when MODE0 =>
RstADD <= '0'; -- Emite el pulso al Modulo de suma y espera a que termine la operacion
CurrentState <= WAIT_FINISH;
----------------------------------------------------
when WAIT_FINISH =>
if DoneADD = '1' then -- Espera hasta que la operacion ADD termina
if op = '1' then -- solo esta suma, terminar
B_x_in <= "00000000000000000000000000000" & ADD_X;
counter_word <= (others => '0');
CurrentState <= SEND_DATA;
valid_data_out <= '1';
else
Q_X <= ADD_X; -- Almacenar el resultado actual
Q_Y <= ADD_Y;
if internal_regk(NUM_BITS-1) = '1' and op_ADD = '0' then-- se comienza una nueva operacion si es qu es necesario realizar una suma
op_ADD <= '1'; -- add
RSTADD <= '1';
CurrentState <= MODE0;
else
counter <= counter + 1; -- incrementa el counter para indicar que ya se consumio un bit del escalar
if counter = "10000010" then --130 = NUM_BITS-1, if all iterations has been performed, then the operation is compleated
B_x_in <= "00000000000000000000000000000" & ADD_X;
counter_word <= (others => '0');
valid_data_out <= '1';
CurrentState <= SEND_DATA;
else -- if not all iterations have been performed, do the following
internal_regk <= k_shift; -- update the scalar shifted
op_ADD <= '0'; -- operacion double
RstADD <= '1';
CurrentState <= MODE0;
end if;
end if;
end if;
end if;
----------------------------------------------------
when SEND_DATA => -- ya hay una palabra valida a la salida, esperar a que el host la lea
--espera el ack del receptor
if ack_master = '1' then
Counter_word <= Counter_word + "00001";
valid_data_out <= '0';
CurrentState <= SEND_MORE;
end if;
----------------------------------------------------
when SEND_MORE => -- pone una palabra valida mas
if ack_master = '0' then
if counter_word = "00101" then -- ITR = 5
B_x_in <= "00000000000000000000000000000" & ADD_Y;
valid_data_out <= '1';
CurrentState <= SEND_DATA;
elsif counter_word = "01010" then -- 2*ITR = 10
CurrentState <= END_STATE;
else
B_x_in <= B_x_shift;
valid_data_out <= '1';
CurrentState <= SEND_DATA;
end if;
end if;
when END_STATE => -- do nothing, wait until the reset signal goes to '1'
valid_data_out <= '0';
----------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave; |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:22:04 12/17/2013
-- Design Name:
-- Module Name: logi_virtual_led - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity logi_virtual_led is
generic(
wb_size : natural := 16 -- Data port size for wishbone
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
led : in std_logic_vector(15 downto 0)
);
end logi_virtual_led;
architecture Behavioral of logi_virtual_led is
signal read_ack : std_logic ;
signal write_ack : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
wbs_readdata <= led ; -- this is not clear if this should only happen in the read part
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
end Behavioral;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:22:04 12/17/2013
-- Design Name:
-- Module Name: logi_virtual_led - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity logi_virtual_led is
generic(
wb_size : natural := 16 -- Data port size for wishbone
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
led : in std_logic_vector(15 downto 0)
);
end logi_virtual_led;
architecture Behavioral of logi_virtual_led is
signal read_ack : std_logic ;
signal write_ack : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
wbs_readdata <= led ; -- this is not clear if this should only happen in the read part
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity l1_data_cache_64entry_4way_line64b_bus_8b is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iREMOVE : in vl_logic;
iRD_REQ : in vl_logic;
oRD_BUSY : out vl_logic;
iRD_ADDR : in vl_logic_vector(31 downto 0);
oRD_VALID : out vl_logic;
oRD_HIT : out vl_logic;
iRD_BUSY : in vl_logic;
oRD_DATA : out vl_logic_vector(31 downto 0);
oRD_MMU_FLAGS : out vl_logic_vector(13 downto 0);
iUP_REQ : in vl_logic;
oUP_BUSY : out vl_logic;
iUP_ORDER : in vl_logic_vector(1 downto 0);
iUP_MASK : in vl_logic_vector(3 downto 0);
iUP_ADDR : in vl_logic_vector(31 downto 0);
iUP_DATA : in vl_logic_vector(31 downto 0);
iWR_REQ : in vl_logic;
oWR_BUSY : out vl_logic;
iWR_ADDR : in vl_logic_vector(31 downto 0);
iWR_DATA : in vl_logic_vector(511 downto 0);
iWR_MMU_FLAGS : in vl_logic_vector(255 downto 0)
);
end l1_data_cache_64entry_4way_line64b_bus_8b;
|
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7392)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7392)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7392)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7392)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7392)
`protect data_block
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`protect end_protected
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mul_pipe_inferred is
generic (
stages : positive := 3;
src1_bits : natural := 32;
src2_bits : natural := 32
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
unsgnd : in std_ulogic;
src1 : in std_ulogic_vector(src1_bits-1 downto 0);
src2 : in std_ulogic_vector(src2_bits-1 downto 0);
result : out std_ulogic_vector(src1_bits+src2_bits-1 downto 0)
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
-- synthesis translate_off
use work.txt_util.all;
-- synthesis translate_on
entity memory is
port (
clk: in std_logic;
rst: in std_logic;
-- Memory interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(31 downto 0);
wb_dat_o: out std_logic_vector(31 downto 0);
wb_adr_o: out std_logic_vector(31 downto 0);
wb_tag_o: out std_logic_vector(31 downto 0);
wb_tag_i: in std_logic_vector(31 downto 0);
wb_err_i: in std_logic;
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_stall_i: in std_logic;
busy: out std_logic;
refetch: out std_logic;
dbgo: out memory_debug_type;
protw: in std_logic_vector(31 downto 0);
proten: in std_logic;
-- Input for previous stages
eui: in execute_output_type;
-- Output for next stages
muo: out memory_output_type
);
end entity memory;
architecture behave of memory is
signal mr: memory_regs_type;
signal mreg_q: regaddress_type;
signal wb_ack_i_q: std_logic;
signal cycle_fault:std_logic;
component reqcnt is
port (
clk: in std_logic;
rst: in std_logic;
stb: in std_logic;
cyc: in std_logic;
stall:in std_logic;
ack: in std_logic;
req: out std_logic;
count: out unsigned(2 downto 0)
);
end component;
signal req_pending: std_logic;
signal endcycle: std_logic;
-- debug only
signal busycnt: unsigned(31 downto 0);
signal faultw: std_logic;
begin
muo.r <= mr;
muo.fault <= mr.fault;
process(eui,mr,clk,rst,wb_ack_i, wb_ack_i_q, wb_dat_i, wb_stall_i, wb_tag_i, wb_err_i,
req_pending)
variable mw: memory_regs_type;
variable wmask: std_logic_vector(3 downto 0);
variable wdata: std_logic_vector(31 downto 0);
variable mdata: std_logic_vector(31 downto 0);
variable queue_request: boolean;
variable mrsel: std_logic_vector(4 downto 0);
begin
mw:=mr;
wdata := (others => DontCareValue);
wmask := (others => DontCareValue);
mw.fault := '0';
case eui.macc is
when M_BYTE | M_BYTE_POSTINC =>
case eui.data_address(1 downto 0) is
when "11" => wdata(7 downto 0) := eui.data_write(7 downto 0); wmask:="0001"; mrsel:="11X00";
when "10" => wdata(15 downto 8) := eui.data_write(7 downto 0); wmask:="0010"; mrsel:="11X01";
when "01" => wdata(23 downto 16) := eui.data_write(7 downto 0); wmask:="0100"; mrsel:="11X10";
when "00" => wdata(31 downto 24) := eui.data_write(7 downto 0); wmask:="1000"; mrsel:="11X11";
when others => null;
end case;
when M_HWORD | M_HWORD_POSTINC =>
case eui.data_address(1) is
when '1' => wdata(15 downto 0) := eui.data_write(15 downto 0); wmask:="0011"; mrsel:="10000";
when '0' => wdata(31 downto 16) := eui.data_write(15 downto 0); wmask:="1100"; mrsel:="10110";
when others => null;
end case;
when others =>
wdata := eui.data_write; wmask:="1111"; mrsel := "00000";
end case;
-- queue_request := false;
muo.mregwe <= '0';
muo.msprwe <= '0';
queue_request := true;
busy<='0';
if wb_stall_i='1' and mr.wb_stb='1' then
queue_request := false;
busy<='1';
end if;
-- Simplify tag.
case wb_tag_i(6 downto 5) is
when "00" => mdata(7 downto 0) := wb_dat_i(7 downto 0);
when "01" => mdata(7 downto 0) := wb_dat_i(15 downto 8);
when "10" => mdata(7 downto 0) := wb_dat_i(23 downto 16);
when "11" => mdata(7 downto 0) := wb_dat_i(31 downto 24);
when others =>
end case;
case wb_tag_i(8 downto 7) is
when "00" => mdata(15 downto 8) := wb_dat_i(15 downto 8);
when "01" => mdata(15 downto 8) := wb_dat_i(31 downto 24);
when others => mdata(15 downto 8) := (others => '0');-- Zero
end case;
case wb_tag_i(9) is
when '0' => mdata(31 downto 16) := wb_dat_i(31 downto 16);
when others => mdata(31 downto 16) := (others => '0');
end case;
if mr.wb_cyc='1' and wb_stall_i='0' then
mw.wb_cyc:='0';
end if;
if queue_request then
mw.wb_we := eui.data_writeenable;
mw.wb_dat := wdata;
mw.wb_adr := eui.data_address;
mw.wb_tago := (others => 'X');
mw.wb_tago(3 downto 0) := eui.mwreg(3 downto 0);
mw.wb_tago(4) := not eui.data_writeenable;
mw.wb_tago(9 downto 5) := mrsel;
mw.wb_tago(10) := eui.mwreg(4);
mw.macc := eui.macc;
mw.wb_sel := wmask;
mw.wb_stb := eui.data_access;
mw.wb_cyc := eui.data_access;
mw.sprwe := eui.sprwe and not eui.data_writeenable;
mw.regwe := (not eui.sprwe) and not eui.data_writeenable;
mw.dreg := eui.mwreg;
mw.pc := eui.npc;
if proten='1' and LOWPROTECTENABLE then
if eui.data_writeenable='1' and eui.data_access='1' then
if (unsigned(eui.data_address)<unsigned(protw)) then
mw.fault := '1';
mw.wb_stb := '0';
mw.faddr := std_logic_vector(eui.npc);
end if;
end if;
end if;
end if;
muo.mdata <= mdata;
muo.mreg <= wb_tag_i(10) & wb_tag_i(3 downto 0);
muo.mregwe <= wb_ack_i and wb_tag_i(4);
refetch <= wb_ack_i and wb_tag_i(4);
if queue_request and eui.clrreg='1' then
muo.mregwe<='1';
muo.mreg<=eui.mwreg;
end if;
if wb_err_i='1' then
mw.fault := '1';
end if;
if rst='1' then
mw.wb_cyc := '0';
mw.wb_stb := '0';
mw.fault := '0';
end if;
if rising_edge(clk) then
mr<=mw;
end if;
end process;
-- debug
dbgo.strobe <= mr.wb_stb and not wb_stall_i;
dbgo.write <= mr.wb_we;
dbgo.address <= unsigned(mr.wb_adr);
dbgo.data <= unsigned(mr.wb_dat);
dbgo.pc <= unsigned(mr.pc);
dbgo.faddr <= unsigned(mr.faddr);
-- Counter
endcycle <= wb_ack_i or wb_err_i;
cnt0: reqcnt port map (
clk => clk,
rst => rst,
stb => mr.wb_stb,
cyc => '1',
stall => wb_stall_i,
ack => endcycle,
req => req_pending,
count => open
);
wb_adr_o <= mr.wb_adr;
wb_stb_o <= mr.wb_stb;
wb_dat_o <= mr.wb_dat;
wb_we_o <= mr.wb_we;
wb_sel_o <= mr.wb_sel;
wb_tag_o <= mr.wb_tago;
wb_cyc_o <= req_pending or mr.wb_cyc;
faultcheck: if FAULTCHECKS generate
-- Internal fault...
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
busycnt<=(others =>'0');
else
if mr.wb_cyc='1' and endcycle='0' then
busycnt<=busycnt+1;
else
busycnt<=(others =>'0');
end if;
end if;
end if;
end process;
-- Cycle check.
cycle_fault<='1' when (req_pending or mr.wb_cyc) /= (req_pending or mr.wb_stb) else '0';
muo.internalfault<='1' when busycnt > 65535 or cycle_fault='1' else '0';
end generate;
nofaultcheck: if not FAULTCHECKS generate
cycle_fault<='0';
muo.internalfault<='0';
end generate;
end behave;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc735.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x00p05n01i00735pkg is
type actype is access integer;
end c01s01b01x00p05n01i00735pkg;
use work.c01s01b01x00p05n01i00735pkg.all;
entity c01s01b01x00p05n01i00735ent_a is
generic (
constant gc1 : integer;
constant gc2 : actype;
constant gc3 : integer
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x00p05n01i00735ent_a;
architecture arch of c01s01b01x00p05n01i00735ent_a is
begin
assert false
report "FAIL: should not compile";
end arch;
use work.c01s01b01x00p05n01i00735pkg.all;
ENTITY c01s01b01x00p05n01i00735ent IS
generic ( constant gen_con : natural := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x00p05n01i00735ent;
ARCHITECTURE c01s01b01x00p05n01i00735arch OF c01s01b01x00p05n01i00735ent IS
signal s1 : integer;
signal s2 : natural;
signal s3 : positive;
component comp1
generic (
constant dgc1 : integer;
constant dgc2 : actype;
constant dgc3 : integer
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use
entity work.c01s01b01x00p05n01i00735ent_a
generic map (dgc1, dgc2.all, dgc3)
port map ( dcent1, dcent2 );
BEGIN
u1 : comp1
generic map (acint,3,3)
port map (ee1,ee2);
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x00p05n01i00735 - Formal generic can not be of type access."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x00p05n01i00735arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc735.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x00p05n01i00735pkg is
type actype is access integer;
end c01s01b01x00p05n01i00735pkg;
use work.c01s01b01x00p05n01i00735pkg.all;
entity c01s01b01x00p05n01i00735ent_a is
generic (
constant gc1 : integer;
constant gc2 : actype;
constant gc3 : integer
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x00p05n01i00735ent_a;
architecture arch of c01s01b01x00p05n01i00735ent_a is
begin
assert false
report "FAIL: should not compile";
end arch;
use work.c01s01b01x00p05n01i00735pkg.all;
ENTITY c01s01b01x00p05n01i00735ent IS
generic ( constant gen_con : natural := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x00p05n01i00735ent;
ARCHITECTURE c01s01b01x00p05n01i00735arch OF c01s01b01x00p05n01i00735ent IS
signal s1 : integer;
signal s2 : natural;
signal s3 : positive;
component comp1
generic (
constant dgc1 : integer;
constant dgc2 : actype;
constant dgc3 : integer
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use
entity work.c01s01b01x00p05n01i00735ent_a
generic map (dgc1, dgc2.all, dgc3)
port map ( dcent1, dcent2 );
BEGIN
u1 : comp1
generic map (acint,3,3)
port map (ee1,ee2);
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x00p05n01i00735 - Formal generic can not be of type access."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x00p05n01i00735arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc735.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x00p05n01i00735pkg is
type actype is access integer;
end c01s01b01x00p05n01i00735pkg;
use work.c01s01b01x00p05n01i00735pkg.all;
entity c01s01b01x00p05n01i00735ent_a is
generic (
constant gc1 : integer;
constant gc2 : actype;
constant gc3 : integer
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x00p05n01i00735ent_a;
architecture arch of c01s01b01x00p05n01i00735ent_a is
begin
assert false
report "FAIL: should not compile";
end arch;
use work.c01s01b01x00p05n01i00735pkg.all;
ENTITY c01s01b01x00p05n01i00735ent IS
generic ( constant gen_con : natural := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x00p05n01i00735ent;
ARCHITECTURE c01s01b01x00p05n01i00735arch OF c01s01b01x00p05n01i00735ent IS
signal s1 : integer;
signal s2 : natural;
signal s3 : positive;
component comp1
generic (
constant dgc1 : integer;
constant dgc2 : actype;
constant dgc3 : integer
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use
entity work.c01s01b01x00p05n01i00735ent_a
generic map (dgc1, dgc2.all, dgc3)
port map ( dcent1, dcent2 );
BEGIN
u1 : comp1
generic map (acint,3,3)
port map (ee1,ee2);
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x00p05n01i00735 - Formal generic can not be of type access."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x00p05n01i00735arch;
|
--------------------------------------------------------------------------------
-- FILE: Types
-- DESC: Define all types.
--
-- Author:
-- Create: 2015-05-20
-- Update: 2015-05-20
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package Types is
end Types;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1802.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p05n01i01802ent IS
END c07s01b00x00p05n01i01802ent;
ARCHITECTURE c07s01b00x00p05n01i01802arch OF c07s01b00x00p05n01i01802ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 3;
variable y : integer := 5;
variable z : integer := 9;
BEGIN
if ((x + -z) < (y + x)) then -- Failure_here
-- sign can appear only before the first term.
x := y * z;
end if;
assert FALSE
report "***FAILED TEST: c07s01b00x00p05n01i01802 - Sign can appear only before the first term in a simple expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p05n01i01802arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1802.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p05n01i01802ent IS
END c07s01b00x00p05n01i01802ent;
ARCHITECTURE c07s01b00x00p05n01i01802arch OF c07s01b00x00p05n01i01802ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 3;
variable y : integer := 5;
variable z : integer := 9;
BEGIN
if ((x + -z) < (y + x)) then -- Failure_here
-- sign can appear only before the first term.
x := y * z;
end if;
assert FALSE
report "***FAILED TEST: c07s01b00x00p05n01i01802 - Sign can appear only before the first term in a simple expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p05n01i01802arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1802.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p05n01i01802ent IS
END c07s01b00x00p05n01i01802ent;
ARCHITECTURE c07s01b00x00p05n01i01802arch OF c07s01b00x00p05n01i01802ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 3;
variable y : integer := 5;
variable z : integer := 9;
BEGIN
if ((x + -z) < (y + x)) then -- Failure_here
-- sign can appear only before the first term.
x := y * z;
end if;
assert FALSE
report "***FAILED TEST: c07s01b00x00p05n01i01802 - Sign can appear only before the first term in a simple expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p05n01i01802arch;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CvtColor_1_sectorncg_rom is
generic(
dwidth : integer := 2;
awidth : integer := 3;
mem_size : integer := 6
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of CvtColor_1_sectorncg_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array := (
0 => "11", 1 to 2=> "00", 3 => "10", 4 to 5=> "01" );
attribute syn_rom_style : string;
attribute syn_rom_style of mem : signal is "select_rom";
attribute ROM_STYLE : string;
attribute ROM_STYLE of mem : signal is "distributed";
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity CvtColor_1_sectorncg is
generic (
DataWidth : INTEGER := 2;
AddressRange : INTEGER := 6;
AddressWidth : INTEGER := 3);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of CvtColor_1_sectorncg is
component CvtColor_1_sectorncg_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
CvtColor_1_sectorncg_rom_U : component CvtColor_1_sectorncg_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0);
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci_mt
-- File: pci_mt.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Alf Vaerneus - Gaisler Research
-- Description: Simple PCI master and target interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.pci.all;
use gaisler.misc.all;
use gaisler.pcilib.all;
entity pci_mt is
generic (
hmstndx : integer := 0;
abits : integer := 21;
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
master : integer := 1; -- Enable PCI Master
hslvndx : integer := 0;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
nsync : integer range 1 to 2 := 1; -- 1 or 2 sync regs between clocks
oepol : integer := 0
);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of pci_mt is
constant REVISION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCISBRG, 0, REVISION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
5 => ahb_iobar (ioaddr, 16#E00#),
others => zero32);
constant CSYNC : integer := nsync-1;
constant MADDR_WIDTH : integer := abits;
constant HADDR_WIDTH : integer := 28;
type pci_input_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_logic;
devsel : std_logic;
idsel : std_logic;
trdy : std_logic;
irdy : std_logic;
par : std_logic;
stop : std_logic;
rst : std_logic;
gnt : std_logic;
end record;
type ahbs_input_type is record
haddr : std_logic_vector(HADDR_WIDTH - 1 downto 0);
htrans : std_logic_vector(1 downto 0);
hwrite : std_logic;
hsize : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hwdata : std_logic_vector(31 downto 0);
hsel : std_logic;
hiosel : std_logic;
hready : std_logic;
end record;
type pci_target_state_type is (idle, b_busy, s_data, backoff, turn_ar);
type pci_master_state_type is (idle, addr, m_data, turn_ar, s_tar, dr_bus);
type pci_config_command_type is record
ioen : std_logic; -- I/O access enable
men : std_logic; -- Memory access enable
msen : std_logic; -- Master enable
spcen : std_logic; -- Special cycle enable
mwie : std_logic; -- Memory write and invalidate enable
vgaps : std_logic; -- VGA palette snooping enable
per : std_logic; -- Parity error response enable
wcc : std_logic; -- Address stepping enable
serre : std_logic; -- Enable SERR# driver
fbtbe : std_logic; -- Fast back-to-back enable
end record;
type pci_config_status_type is record
c66mhz : std_logic; -- 66MHz capability
udf : std_logic; -- UDF supported
fbtbc : std_logic; -- Fast back-to-back capability
dped : std_logic; -- Data parity error detected
dst : std_logic_vector(1 downto 0); -- DEVSEL timing
sta : std_logic; -- Signaled target abort
rta : std_logic; -- Received target abort
rma : std_logic; -- Received master abort
sse : std_logic; -- Signaled system error
dpe : std_logic; -- Detected parity error
end record;
type pci_reg_type is record
addr : std_logic_vector(MADDR_WIDTH-1 downto 0);
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
lcbe : std_logic_vector(3 downto 0);
t_state : pci_target_state_type; -- PCI target state machine
m_state : pci_master_state_type; -- PCI master state machine
csel : std_logic; -- Configuration chip select
msel : std_logic; -- Memory hit
read : std_logic;
devsel : std_logic; -- PCI device select
trdy : std_logic; -- Target ready
irdy : std_logic; -- Master ready
stop : std_logic; -- Target stop request
par : std_logic; -- PCI bus parity
req : std_logic; -- Master bus request
oe_par : std_logic;
oe_ad : std_logic;
oe_trdy : std_logic;
oe_devsel: std_logic;
oe_ctrl : std_logic;
oe_cbe : std_logic;
oe_stop : std_logic;
oe_frame : std_logic;
oe_irdy : std_logic;
oe_req : std_logic;
noe_par : std_logic;
noe_ad : std_logic;
noe_trdy : std_logic;
noe_devsel: std_logic;
noe_ctrl : std_logic;
noe_cbe : std_logic;
noe_stop : std_logic;
noe_frame : std_logic;
noe_irdy : std_logic;
noe_req : std_logic;
request : std_logic; -- Request from Back-end
frame : std_logic; -- Master frame
bar0 : std_logic_vector(31 downto MADDR_WIDTH);
page : std_logic_vector(31 downto MADDR_WIDTH-1);
comm : pci_config_command_type;
stat : pci_config_status_type;
laddr : std_logic_vector(31 downto 0);
ldata : std_logic_vector(31 downto 0);
pwrite : std_logic;
hwrite : std_logic;
start : std_logic;
hreq : std_logic;
hreq_ack : std_logic_vector(csync downto 0);
preq : std_logic_vector(csync downto 0);
preq_ack : std_logic;
rready : std_logic_vector(csync downto 0);
wready : std_logic_vector(csync downto 0);
sync : std_logic_vector(csync downto 0);
pabort : std_logic;
mcnt : std_logic_vector(2 downto 0);
maddr : std_logic_vector(31 downto 0);
mdata : std_logic_vector(31 downto 0);
stop_req : std_logic;
end record;
type cpu_master_state_type is (idle, sync1, busy, sync2);
type cpu_slave_state_type is (idle, getd, req, sync, read, sync2, t_done);
type cpu_reg_type is record
tdata : std_logic_vector(31 downto 0); -- Target data
maddr : std_logic_vector(31 downto 0); -- Master data
mdata : std_logic_vector(31 downto 0); -- Master data
be : std_logic_vector(3 downto 0);
m_state : cpu_master_state_type; -- AMBA master state machine
s_state : cpu_slave_state_type; -- AMBA slave state machine
start : std_logic_vector(csync downto 0);
hreq : std_logic_vector(csync downto 0);
hreq_ack : std_logic;
preq : std_logic;
preq_ack : std_logic_vector(csync downto 0);
sync : std_logic;
hwrite : std_logic; -- AHB write on PCI
pabort : std_logic_vector(csync downto 0);
perror : std_logic;
rready : std_logic;
wready : std_logic;
hrdata : std_logic_vector(31 downto 0);
hresp : std_logic_vector(1 downto 0);
pciba : std_logic_vector(3 downto 0);
end record;
signal clk_int : std_logic;
signal pr : pci_input_type;
signal hr : ahbs_input_type;
signal r, rin : pci_reg_type;
signal r2, r2in : cpu_reg_type;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal roe_ad, rioe_ad : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of roe_ad : signal is true;
begin
-- Back-end state machine (AHB clock domain)
comb : process (rst, r2, r, dmao, hr, ahbsi)
variable vdmai : ahb_dma_in_type;
variable v : cpu_reg_type;
variable request : std_logic;
variable hready : std_logic;
variable hresp, hsize, htrans : std_logic_vector(1 downto 0);
variable p_done : std_logic;
begin
v := r2;
vdmai.start := '0'; vdmai.burst := '0'; vdmai.size := "10";
vdmai.address := r.laddr; v.sync := '1';
vdmai.wdata := r.ldata; vdmai.write := r.pwrite;
v.start(0) := r2.start(csync); v.start(csync) := r.start;
v.hreq(0) := r2.hreq(csync); v.hreq(csync) := r.hreq;
v.pabort(0) := r2.pabort(csync); v.pabort(csync) := r.pabort;
v.preq_ack(0) := r2.preq_ack(csync); v.preq_ack(csync) := r.preq_ack;
hready := '1'; hresp := HRESP_OKAY; request := '0';
hsize := "10"; htrans := "00";
p_done := r2.hreq(0) or r2.pabort(0);
---- *** APB register access *** ----
--if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
--v.pciba := apbi.pwdata(31 downto 28);
--end if;
--apbo.prdata <= r2.pciba & addzero;
if hr.hiosel = '1' then
if hr.hwrite = '1' then v.pciba := ahbsi.hwdata(31 downto 28); end if;
v.hrdata := r2.pciba & addzero(27 downto 0);
end if;
---- *** AHB MASTER *** ----
case r2.m_state is
when idle =>
v.sync := '0';
if r2.start(0) = '1' then
if r.pwrite = '1' then v.m_state := sync1; v.wready := '0';
else v.m_state := busy; vdmai.start := '1'; end if;
end if;
when sync1 =>
if r2.start(0) = '0' then v.m_state := busy; vdmai.start := '1'; end if;
when busy =>
if dmao.active = '1' then
if dmao.ready = '1' then
v.rready := not r.pwrite; v.tdata := dmao.rdata; v.m_state := sync2;
end if;
else vdmai.start := '1'; end if;
when sync2 =>
if r2.start(0) = '0' then
v.m_state := idle; v.wready := '1'; v.rready := '0';
end if;
end case;
---- *** AHB MASTER END *** ----
---- *** AHB SLAVE *** ----
if MASTER = 1 then
if (hr.hready and hr.hsel) = '1' then
hsize := hr.hsize; htrans := hr.htrans;
if (hr.htrans(1) and r.comm.msen) = '1' then request := '1'; end if;
end if;
if (request = '1' and r2.s_state = idle) then
v.maddr := r2.pciba & hr.haddr;
v.hwrite := hr.hwrite;
case hsize is
when "00" => v.be := "1110"; -- Decode byte enable
when "01" => v.be := "1100";
when "10" => v.be := "0000";
when others => v.be := "1111";
end case;
elsif r2.s_state = getd and r2.hwrite = '1' then
v.mdata := hr.hwdata;
end if;
if r2.hreq(0) = '1' then v.hrdata := r.ldata; end if;
if r2.preq_ack(0) = '1' then v.preq := '0'; end if;
if r2.pabort(0) = '1' then v.perror := '1'; end if;
if p_done = '0' then v.hreq_ack := '0'; end if;
-- AHB slave state machine
case r2.s_state is
when idle => if request = '1' then v.s_state := getd; end if;
when getd => v.s_state := req; v.preq := '1';
when req => if r2.preq_ack(0) = '1' then v.s_state := sync; end if;
when sync => if r2.preq_ack(0) = '0' then v.s_state := read; end if;
when read =>
if p_done = '1' then v.hreq_ack := '1'; v.s_state := sync2; end if;
when sync2 => if p_done = '0' then v.s_state := t_done; end if;
when t_done => if request = '1' then v.s_state := idle; end if;
when others => v.s_state := idle;
end case;
if request = '1' then
if r2.s_state = t_done then
if r2.perror = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
v.perror := '0';
else hresp := HRESP_RETRY; end if;
end if;
if r.comm.msen = '0' then hresp := HRESP_ERROR; end if; -- Master disabled
if htrans(1) = '0' then hresp := HRESP_OKAY; end if; -- Response OK for BUSY and IDLE
if (hresp /= HRESP_OKAY and (hr.hready and hr.hsel) = '1') then -- insert one wait cycle
hready := '0';
end if;
if hr.hready = '0' then hresp := r2.hresp; end if;
v.hresp := hresp;
end if;
---- *** AHB SLAVE END *** ----
if rst = '0' then
v.s_state := idle; v.rready := '0'; v.wready := '1';
v.m_state := idle; v.preq := '0'; v.hreq_ack := '0';
v.perror := '0'; v.be := (others => '1');
v.pciba := (others => '0'); v.hresp := (others => '0');
end if;
r2in <= v; dmai <= vdmai;
ahbso.hready <= hready;
ahbso.hresp <= hresp;
ahbso.hrdata <= r2.hrdata;
end process;
ahbso.hconfig <= hconfig when MASTER = 1 else (others => zero32);
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hindex <= hslvndx;
-- PCI target core (PCI clock domain)
pcicomb : process(pcii.rst, pr, pcii, r, r2, roe_ad)
variable v : pci_reg_type;
variable chit, mhit, hit, ready, cwrite : std_logic;
variable cdata, cwdata : std_logic_vector(31 downto 0);
variable comp : std_logic; -- Last transaction cycle on PCI bus
variable iready : std_logic;
variable mto : std_logic;
variable tad, mad : std_logic_vector(31 downto 0);
-- variable cbe : std_logic_vector(3 downto 0);
variable caddr : std_logic_vector(7 downto 2);
variable voe_ad : std_logic_vector(31 downto 0);
variable oe_par : std_logic;
variable oe_ad : std_logic;
variable oe_ctrl : std_logic;
variable oe_trdy : std_logic;
variable oe_devsel: std_logic;
variable oe_cbe : std_logic;
variable oe_stop : std_logic;
variable oe_frame : std_logic;
variable oe_irdy : std_logic;
variable oe_req : std_logic;
begin
-- Process defaults
v := r; v.trdy := '1'; v.stop := '1'; v.frame := '1';
v.oe_ad := '1'; v.devsel := '1'; v.oe_frame := '1';
v.irdy := '1'; v.req := '1'; voe_ad := roe_ad;
v.oe_req := '0'; v.oe_cbe := '1'; v.oe_irdy := '1';
v.rready(0) := r.rready(csync); v.rready(csync) := r2.rready;
v.wready(0) := r.wready(csync); v.wready(csync) := r2.wready;
v.sync(0) := r.sync(csync); v.sync(csync) := r2.sync;
v.preq(0) := r.preq(csync); v.preq(csync) := r2.preq;
v.hreq_ack(0) := r.hreq_ack(csync); v.hreq_ack(csync) := r2.hreq_ack;
comp := '0'; mto := '0'; tad := r.ad; mad := r.ad; v.stop_req := '0';
--cbe := r.cbe;
----- *** PCI TARGET *** --------
-- address decoding
if (r.t_state = s_data) and ((pr.irdy or r.trdy or r.read) = '0') then
cwrite := r.csel;
if ((r.msel and r.addr(MADDR_WIDTH-1)) = '1') and (pr.cbe = "0000") then
v.page := pr.ad(31 downto MADDR_WIDTH-1);
end if;
if (pr.cbe = "0000") and (r.addr(MADDR_WIDTH-1) = '1') then
end if;
else cwrite := '0'; end if;
cdata := (others => '0'); caddr := r.addr(7 downto 2);
case caddr is
when "000000" => -- 0x00, device & vendor id
cdata := conv_std_logic_vector(DEVICE_ID, 16) &
conv_std_logic_vector(VENDOR_ID, 16);
when "000001" => -- 0x04, status & command
cdata(1) := r.comm.men; cdata(2) := r.comm.msen; cdata(25) := '1';
cdata(28) := r.stat.rta; cdata(29) := r.stat.rma;
when "000010" => -- 0x08, class code & revision
when "000011" => -- 0x0c, latency & cacheline size
when "000100" => -- 0x10, BAR0
cdata(31 downto MADDR_WIDTH) := r.bar0;
when others =>
end case;
cwdata := pr.ad;
if pr.cbe(3) = '1' then cwdata(31 downto 24) := cdata(31 downto 24); end if;
if pr.cbe(2) = '1' then cwdata(23 downto 16) := cdata(23 downto 16); end if;
if pr.cbe(1) = '1' then cwdata(15 downto 8) := cdata(15 downto 8); end if;
if pr.cbe(0) = '1' then cwdata( 7 downto 0) := cdata( 7 downto 0); end if;
if cwrite = '1' then
case caddr is
when "000001" => -- 0x04, status & command
v.comm.men := cwdata(1);
v.comm.msen := cwdata(2);
v.stat.rta := r.stat.rta and not cwdata(28);
v.stat.rma := r.stat.rma and not cwdata(29);
when "000100" => -- 0x10, BAR0
v.bar0 := cwdata(31 downto MADDR_WIDTH);
when others =>
end case;
end if;
if (((pr.cbe = pci_config_read) or (pr.cbe = pci_config_write))
and (pr.ad(1 downto 0) = "00"))
then chit := '1'; else chit := '0'; end if;
if ((pr.cbe = pci_memory_read) or (pr.cbe = pci_memory_write))
and (r.bar0 = pr.ad(31 downto MADDR_WIDTH))
and (r.bar0 /= zero(31 downto MADDR_WIDTH))
then mhit := '1'; else mhit := '0'; end if;
hit := r.csel or r.msel;
ready := r.csel or (r.rready(0) and r.read) or (r.wready(0) and not r.read and not r.start) or
r.addr(MADDR_WIDTH-1);
-- target state machine
case r.t_state is
when idle =>
if pr.frame = '0' then v.t_state := b_busy; end if; -- !HIT ?
v.addr := pr.ad(MADDR_WIDTH-1 downto 0); -- v.cbe := pr.cbe;
v.csel := pr.idsel and chit;
v.msel := r.comm.men and mhit; v.read := not pr.cbe(0);
if (r.sync(0) and r.start and r.pwrite) = '1' then v.start := '0'; end if;
when turn_ar =>
if pr.frame = '1' then v.t_state := idle; end if;
if pr.frame = '0' then v.t_state := b_busy; end if; -- !HIT ?
v.addr := pr.ad(MADDR_WIDTH-1 downto 0); -- v.cbe := pr.cbe;
v.csel := pr.idsel and chit;
v.msel := r.comm.men and mhit; v.read := not pr.cbe(0);
if (r.sync(0) and r.start and r.pwrite) = '1' then v.start := '0'; end if;
when b_busy =>
if hit = '1' then
v.t_state := s_data; v.trdy := not ready; v.stop := pr.frame and ready;
v.devsel := '0';
else
v.t_state := backoff;
end if;
when s_data =>
v.stop := r.stop; v.devsel := '0';
v.trdy := r.trdy or not pcii.irdy;
if (pcii.frame and not pcii.irdy) = '1' then
v.t_state := turn_ar; v.stop := '1'; v.trdy := '1'; v.devsel := '1';
end if;
when backoff =>
if pr.frame = '1' then v.t_state := idle; end if;
end case;
if ((r.t_state = s_data) or (r.t_state = turn_ar)) and
(((pr.irdy or pr.trdy) = '0') or
((not pr.irdy and not pr.stop and pr.trdy and not r.start and r.wready(0)) = '1'))
then
if (pr.trdy and r.read)= '0' then v.start := '0'; end if;
if (r.start = '0') and ((r.msel and not r.addr(MADDR_WIDTH-1)) = '1') and
(((pr.trdy and r.read and not r.rready(0)) or (not pr.trdy and not r.read)) = '1')
then
v.laddr := r.page & r.addr(MADDR_WIDTH-2 downto 0);
v.ldata := pr.ad; v.pwrite := not r.read; v.start := '1';
end if;
end if;
-- if (v.t_state = s_data) and (r.read = '1') then v.oe_ad := '0'; end if;
-- v.oe_par := r.oe_ad;
if r.csel = '1' then tad := cdata;
elsif r.addr(MADDR_WIDTH-1) = '1' then
tad(31 downto MADDR_WIDTH-1) := r.page;
tad(MADDR_WIDTH-2 downto 0) := (others => '0');
else tad := r2.tdata; end if;
if (v.t_state = s_data) or (r.t_state = s_data) then
v.oe_ctrl := '0';
else v.oe_ctrl := '1'; end if;
----- *** PCI TARGET END*** --------
----- *** PCI MASTER *** --------
if MASTER = 1 then
if r.preq(0) = '1' then
if (r.m_state = idle or r.m_state = dr_bus) and r.request = '0' and r.hreq = '0' then
v.request := '1';
v.hwrite := r2.hwrite;
v.lcbe := r2.be;
v.mdata := r2.mdata;
v.maddr :=r2.maddr;
end if;
end if;
if r.hreq_ack(0) = '1' then v.hreq := '0'; v.pabort := '0'; end if;
if r.preq(0) = '0' then v.preq_ack := '0'; end if;
comp := not(pcii.trdy or pcii.irdy);
if ((pr.irdy and not pr.frame) or (pr.devsel and r.frame and not r.oe_frame)) = '1' then -- Covers both master timeout and devsel timeout
if r.mcnt /= "000" then v.mcnt := r.mcnt - 1;
else mto := '1'; end if;
else v.mcnt := (others => '1'); end if;
-- PCI master state machine
case r.m_state is
when idle => -- Master idle
if (pr.gnt = '0' and (pr.frame and pr.irdy) = '1') then
if r.request = '1' then v.m_state := addr; v.preq_ack := '1';
else v.m_state := dr_bus; end if;
end if;
when addr => -- Always one address cycle at the beginning of an transaction
v.m_state := m_data;
when m_data => -- Master transfers data
--if (r.request and not pr.gnt and pr.frame and not pr.trdy -- Not supporting address stepping!
--and pr.stop and l_cycle and sa) = '1' then
--v.m_state <= addr;
v.hreq := comp;
if (pr.frame = '0') or ((pr.frame and pcii.trdy and pcii.stop and not mto) = '1') then
v.m_state := m_data;
elsif ((pr.frame and (mto or not pcii.stop)) = '1') then
v.m_state := s_tar;
else v.m_state := turn_ar; v.request := '0'; end if;
when turn_ar => -- Transaction complete
if (r.request and not pr.gnt) = '1' then v.m_state := addr;
elsif (r.request or pr.gnt) = '0' then v.m_state := dr_bus;
else v.m_state := idle; end if;
when s_tar => -- Stop was asserted
v.request := pr.trdy and not pr.stop and not pr.devsel;
v.stop_req := '1';
if (pr.stop or pr.devsel or pr.trdy) = '0' then -- Disconnect with data
v.m_state := turn_ar;
elsif pr.gnt = '0' then
v.pabort := not v.request;
v.m_state := dr_bus;
else v.m_state := idle; v.pabort := not v.request; end if;
when dr_bus => -- Drive bus when parked on this agent
if (r.request = '1' and (pcii.gnt or r.req) = '0') then v.m_state := addr; v.preq_ack := '1';
elsif pcii.gnt = '1' then v.m_state := idle; end if;
end case;
if v.m_state = addr then mad := r.maddr; else mad := r.mdata; end if;
if (pr.irdy or pr.trdy or r.hwrite) = '0' then v.ldata := pr.ad; end if;
-- Target abort
if ((pr.devsel and pr.trdy and not pr.gnt and not pr.stop) = '1') then v.stat.rta := '1'; end if;
-- Master abort
if mto = '1' then v.stat.rma := '1'; end if;
-- Drive FRAME# and IRDY#
if (v.m_state = addr or v.m_state = m_data) then v.oe_frame := '0'; end if;
-- Drive CBE#
if (v.m_state = addr or v.m_state = m_data or v.m_state = dr_bus) then v.oe_cbe := '0'; end if;
-- Drive IRDY# (FRAME# delayed one pciclk)
v.oe_irdy := r.oe_frame;
-- FRAME# assert
if v.m_state = addr then v.frame := '0'; end if; -- Only single transfers valid
-- IRDY# assert
if v.m_state = m_data then v.irdy := '0'; end if;
-- REQ# assert
if (v.request = '1' and (v.m_state = idle or r.m_state = idle) and (v.stop_req or r.stop_req) = '0') then v.req := '0'; end if;
-- C/BE# assert
if v.m_state = addr then v.cbe := "011" & r.hwrite; else v.cbe := r.lcbe; end if;
end if;
----- *** PCI MASTER END *** --------
----- *** SHARED BUS SIGNALS *** -------
-- Drive PAR
v.oe_par := r.oe_ad; --Delayed one clock
v.par := xorv(r.ad & r.cbe); -- Default asserted by master
v.ad := mad; -- Default asserted by master
-- Master
if (v.m_state = addr or (v.m_state = m_data and r.hwrite = '1') or v.m_state = dr_bus) then
v.oe_ad := '0';
end if;
-- Drive AD
-- Target
if r.read = '1' then
if v.t_state = s_data then
v.oe_ad := '0';
v.ad := tad;
elsif r.t_state = s_data then
v.par := xorv(r.ad & pcii.cbe);
end if;
end if;
v.oe_stop := v.oe_ctrl; v.oe_devsel := v.oe_ctrl; v.oe_trdy := v.oe_ctrl;
v.noe_ad := not v.oe_ad; v.noe_ctrl := not v.oe_ctrl;
v.noe_par := not v.oe_par; v.noe_req := not v.oe_req;
v.noe_frame := not v.oe_frame; v.noe_cbe := not v.oe_cbe;
v.noe_irdy := not v.oe_irdy;
v.noe_stop := not v.oe_ctrl; v.noe_devsel := not v.oe_ctrl;
v.noe_trdy := not v.oe_ctrl;
if oepol = 0 then
voe_ad := (others => v.oe_ad);
oe_ad := r.oe_ad; oe_ctrl := r.oe_ctrl; oe_par := r.oe_par;
oe_req := r.oe_req; oe_frame := r.oe_frame; oe_cbe := r.oe_cbe;
oe_irdy := r.oe_irdy; oe_stop := r.oe_stop; oe_trdy := r.oe_trdy;
oe_devsel := r.oe_devsel;
else
voe_ad := (others => v.noe_ad);
oe_ad := r.noe_ad; oe_ctrl := r.noe_ctrl; oe_par := r.noe_par;
oe_req := r.noe_req; oe_frame := r.noe_frame; oe_cbe := r.noe_cbe;
oe_irdy := r.noe_irdy; oe_stop := r.noe_stop; oe_trdy := r.noe_trdy;
oe_devsel := r.noe_devsel;
end if;
----- *** SHARED BUS SIGNALS END *** -------
if pr.rst = '0' then
v.t_state := idle; v.m_state := idle; v.comm.men := '0'; v.start := '0';
v.bar0 := (others => '0'); v.msel := '0'; v.csel := '0';
v.page := (others => '0'); v.page(31 downto 30) := "01"; v.par := '0';
v.hwrite := '0'; v.request := '0'; v.comm.msen := '0';
v.laddr := (others => '0'); v.ldata := (others => '0');
v.hreq := '0'; v.preq_ack := '0'; v.pabort := '0';
v.mcnt := (others => '1'); v.maddr := (others => '0');
v.lcbe := (others => '0'); v.mdata := (others => '0');
v.pwrite := '0'; v.stop_req := '0';
v.stat.rta := '0'; v.stat.rma := '0';
end if;
rin <= v;
rioe_ad <= voe_ad;
pcio.reqen <= oe_req;
pcio.req <= r.req;
pcio.frameen <= oe_frame;
pcio.frame <= r.frame;
pcio.irdyen <= oe_irdy;
pcio.irdy <= r.irdy;
pcio.cbeen <= (others => oe_cbe);
pcio.cbe <= r.cbe;
pcio.vaden <= roe_ad;
pcio.aden <= oe_ad;
pcio.ad <= r.ad;
pcio.trdy <= r.trdy;
pcio.ctrlen <= oe_ctrl;
pcio.trdyen <= oe_trdy;
pcio.devselen <= oe_devsel;
pcio.stopen <= oe_stop;
pcio.stop <= r.stop;
pcio.devsel <= r.devsel;
pcio.par <= r.par;
pcio.paren <= oe_par;
end process;
pcir : process (pciclk, pcii.rst)
begin
if rising_edge (pciclk) then
pr.ad <= to_x01(pcii.ad);
pr.cbe <= to_x01(pcii.cbe);
pr.devsel <= to_x01(pcii.devsel);
pr.frame <= to_x01(pcii.frame);
pr.idsel <= to_x01(pcii.idsel);
pr.irdy <= to_x01(pcii.irdy);
pr.trdy <= to_x01(pcii.trdy);
pr.par <= to_x01(pcii.par);
pr.stop <= to_x01(pcii.stop);
pr.rst <= to_x01(pcii.rst);
pr.gnt <= to_x01(pcii.gnt);
r <= rin;
roe_ad <= rioe_ad;
end if;
if pcii.rst = '0' then -- asynch reset required
r.oe_ad <= '1'; r.oe_ctrl <= '1'; r.oe_par <= '1'; r.oe_stop <= '1';
r.oe_req <= '1'; r.oe_frame <= '1'; r.oe_cbe <= '1'; r.oe_irdy <= '1';
r.oe_trdy <= '1'; r.oe_devsel <= '1';
r.noe_ad <= '0'; r.noe_ctrl <= '0'; r.noe_par <= '0'; r.noe_req <= '0';
r.noe_frame <= '0'; r.noe_cbe <= '0'; r.noe_irdy <= '0'; r.noe_stop <= '0';
r.noe_trdy <= '0'; r.noe_devsel <= '0';
if oepol = 0 then roe_ad <= (others => '1');
else roe_ad <= (others => '0'); end if;
end if;
end process;
cpur : process (rst,clk)
begin
if rising_edge (clk) then
hr.haddr <= ahbsi.haddr(HADDR_WIDTH - 1 downto 0);
hr.htrans <= ahbsi.htrans;
hr.hwrite <= ahbsi.hwrite;
hr.hsize <= ahbsi.hsize(1 downto 0);
hr.hburst <= ahbsi.hburst;
hr.hwdata <= ahbsi.hwdata;
hr.hsel <= ahbsi.hsel(hslvndx) and ahbsi.hmbsel(0);
hr.hiosel <= ahbsi.hsel(hslvndx) and ahbsi.hmbsel(1);
hr.hready <= ahbsi.hready;
r2 <= r2in;
end if;
end process;
oe0 : if oepol = 0 generate
pcio.perren <= '1';
pcio.serren <= '1';
pcio.inten <= '1';
pcio.locken <= '1';
end generate;
oe1 : if oepol = 1 generate
pcio.perren <= '0';
pcio.serren <= '0';
pcio.inten <= '0';
pcio.locken <= '0';
end generate;
pcio.perr <= '1';
pcio.serr <= '1';
pcio.int <= '1';
msttgt : if MASTER = 1 generate
ahbmst0 : ahbmst generic map (hindex => hmstndx, devid => GAISLER_PCISBRG)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mt" & tost(hslvndx) &
": Simple 32-bit PCI Bridge, rev " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR" );
-- pragma translate_on
end generate;
tgtonly : if MASTER = 0 generate
ahbmst0 : ahbmst generic map (hindex => hmstndx, devid => GAISLER_PCITRG)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mt" & tost(hmstndx) &
": Simple 32-bit Bridge, target-only, rev " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR" );
-- pragma translate_on
end generate;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci_mt
-- File: pci_mt.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Alf Vaerneus - Gaisler Research
-- Description: Simple PCI master and target interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.pci.all;
use gaisler.misc.all;
use gaisler.pcilib.all;
entity pci_mt is
generic (
hmstndx : integer := 0;
abits : integer := 21;
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
master : integer := 1; -- Enable PCI Master
hslvndx : integer := 0;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
nsync : integer range 1 to 2 := 1; -- 1 or 2 sync regs between clocks
oepol : integer := 0
);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of pci_mt is
constant REVISION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCISBRG, 0, REVISION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
5 => ahb_iobar (ioaddr, 16#E00#),
others => zero32);
constant CSYNC : integer := nsync-1;
constant MADDR_WIDTH : integer := abits;
constant HADDR_WIDTH : integer := 28;
type pci_input_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_logic;
devsel : std_logic;
idsel : std_logic;
trdy : std_logic;
irdy : std_logic;
par : std_logic;
stop : std_logic;
rst : std_logic;
gnt : std_logic;
end record;
type ahbs_input_type is record
haddr : std_logic_vector(HADDR_WIDTH - 1 downto 0);
htrans : std_logic_vector(1 downto 0);
hwrite : std_logic;
hsize : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hwdata : std_logic_vector(31 downto 0);
hsel : std_logic;
hiosel : std_logic;
hready : std_logic;
end record;
type pci_target_state_type is (idle, b_busy, s_data, backoff, turn_ar);
type pci_master_state_type is (idle, addr, m_data, turn_ar, s_tar, dr_bus);
type pci_config_command_type is record
ioen : std_logic; -- I/O access enable
men : std_logic; -- Memory access enable
msen : std_logic; -- Master enable
spcen : std_logic; -- Special cycle enable
mwie : std_logic; -- Memory write and invalidate enable
vgaps : std_logic; -- VGA palette snooping enable
per : std_logic; -- Parity error response enable
wcc : std_logic; -- Address stepping enable
serre : std_logic; -- Enable SERR# driver
fbtbe : std_logic; -- Fast back-to-back enable
end record;
type pci_config_status_type is record
c66mhz : std_logic; -- 66MHz capability
udf : std_logic; -- UDF supported
fbtbc : std_logic; -- Fast back-to-back capability
dped : std_logic; -- Data parity error detected
dst : std_logic_vector(1 downto 0); -- DEVSEL timing
sta : std_logic; -- Signaled target abort
rta : std_logic; -- Received target abort
rma : std_logic; -- Received master abort
sse : std_logic; -- Signaled system error
dpe : std_logic; -- Detected parity error
end record;
type pci_reg_type is record
addr : std_logic_vector(MADDR_WIDTH-1 downto 0);
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
lcbe : std_logic_vector(3 downto 0);
t_state : pci_target_state_type; -- PCI target state machine
m_state : pci_master_state_type; -- PCI master state machine
csel : std_logic; -- Configuration chip select
msel : std_logic; -- Memory hit
read : std_logic;
devsel : std_logic; -- PCI device select
trdy : std_logic; -- Target ready
irdy : std_logic; -- Master ready
stop : std_logic; -- Target stop request
par : std_logic; -- PCI bus parity
req : std_logic; -- Master bus request
oe_par : std_logic;
oe_ad : std_logic;
oe_trdy : std_logic;
oe_devsel: std_logic;
oe_ctrl : std_logic;
oe_cbe : std_logic;
oe_stop : std_logic;
oe_frame : std_logic;
oe_irdy : std_logic;
oe_req : std_logic;
noe_par : std_logic;
noe_ad : std_logic;
noe_trdy : std_logic;
noe_devsel: std_logic;
noe_ctrl : std_logic;
noe_cbe : std_logic;
noe_stop : std_logic;
noe_frame : std_logic;
noe_irdy : std_logic;
noe_req : std_logic;
request : std_logic; -- Request from Back-end
frame : std_logic; -- Master frame
bar0 : std_logic_vector(31 downto MADDR_WIDTH);
page : std_logic_vector(31 downto MADDR_WIDTH-1);
comm : pci_config_command_type;
stat : pci_config_status_type;
laddr : std_logic_vector(31 downto 0);
ldata : std_logic_vector(31 downto 0);
pwrite : std_logic;
hwrite : std_logic;
start : std_logic;
hreq : std_logic;
hreq_ack : std_logic_vector(csync downto 0);
preq : std_logic_vector(csync downto 0);
preq_ack : std_logic;
rready : std_logic_vector(csync downto 0);
wready : std_logic_vector(csync downto 0);
sync : std_logic_vector(csync downto 0);
pabort : std_logic;
mcnt : std_logic_vector(2 downto 0);
maddr : std_logic_vector(31 downto 0);
mdata : std_logic_vector(31 downto 0);
stop_req : std_logic;
end record;
type cpu_master_state_type is (idle, sync1, busy, sync2);
type cpu_slave_state_type is (idle, getd, req, sync, read, sync2, t_done);
type cpu_reg_type is record
tdata : std_logic_vector(31 downto 0); -- Target data
maddr : std_logic_vector(31 downto 0); -- Master data
mdata : std_logic_vector(31 downto 0); -- Master data
be : std_logic_vector(3 downto 0);
m_state : cpu_master_state_type; -- AMBA master state machine
s_state : cpu_slave_state_type; -- AMBA slave state machine
start : std_logic_vector(csync downto 0);
hreq : std_logic_vector(csync downto 0);
hreq_ack : std_logic;
preq : std_logic;
preq_ack : std_logic_vector(csync downto 0);
sync : std_logic;
hwrite : std_logic; -- AHB write on PCI
pabort : std_logic_vector(csync downto 0);
perror : std_logic;
rready : std_logic;
wready : std_logic;
hrdata : std_logic_vector(31 downto 0);
hresp : std_logic_vector(1 downto 0);
pciba : std_logic_vector(3 downto 0);
end record;
signal clk_int : std_logic;
signal pr : pci_input_type;
signal hr : ahbs_input_type;
signal r, rin : pci_reg_type;
signal r2, r2in : cpu_reg_type;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal roe_ad, rioe_ad : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of roe_ad : signal is true;
begin
-- Back-end state machine (AHB clock domain)
comb : process (rst, r2, r, dmao, hr, ahbsi)
variable vdmai : ahb_dma_in_type;
variable v : cpu_reg_type;
variable request : std_logic;
variable hready : std_logic;
variable hresp, hsize, htrans : std_logic_vector(1 downto 0);
variable p_done : std_logic;
begin
v := r2;
vdmai.start := '0'; vdmai.burst := '0'; vdmai.size := "10";
vdmai.address := r.laddr; v.sync := '1';
vdmai.wdata := r.ldata; vdmai.write := r.pwrite;
v.start(0) := r2.start(csync); v.start(csync) := r.start;
v.hreq(0) := r2.hreq(csync); v.hreq(csync) := r.hreq;
v.pabort(0) := r2.pabort(csync); v.pabort(csync) := r.pabort;
v.preq_ack(0) := r2.preq_ack(csync); v.preq_ack(csync) := r.preq_ack;
hready := '1'; hresp := HRESP_OKAY; request := '0';
hsize := "10"; htrans := "00";
p_done := r2.hreq(0) or r2.pabort(0);
---- *** APB register access *** ----
--if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
--v.pciba := apbi.pwdata(31 downto 28);
--end if;
--apbo.prdata <= r2.pciba & addzero;
if hr.hiosel = '1' then
if hr.hwrite = '1' then v.pciba := ahbsi.hwdata(31 downto 28); end if;
v.hrdata := r2.pciba & addzero(27 downto 0);
end if;
---- *** AHB MASTER *** ----
case r2.m_state is
when idle =>
v.sync := '0';
if r2.start(0) = '1' then
if r.pwrite = '1' then v.m_state := sync1; v.wready := '0';
else v.m_state := busy; vdmai.start := '1'; end if;
end if;
when sync1 =>
if r2.start(0) = '0' then v.m_state := busy; vdmai.start := '1'; end if;
when busy =>
if dmao.active = '1' then
if dmao.ready = '1' then
v.rready := not r.pwrite; v.tdata := dmao.rdata; v.m_state := sync2;
end if;
else vdmai.start := '1'; end if;
when sync2 =>
if r2.start(0) = '0' then
v.m_state := idle; v.wready := '1'; v.rready := '0';
end if;
end case;
---- *** AHB MASTER END *** ----
---- *** AHB SLAVE *** ----
if MASTER = 1 then
if (hr.hready and hr.hsel) = '1' then
hsize := hr.hsize; htrans := hr.htrans;
if (hr.htrans(1) and r.comm.msen) = '1' then request := '1'; end if;
end if;
if (request = '1' and r2.s_state = idle) then
v.maddr := r2.pciba & hr.haddr;
v.hwrite := hr.hwrite;
case hsize is
when "00" => v.be := "1110"; -- Decode byte enable
when "01" => v.be := "1100";
when "10" => v.be := "0000";
when others => v.be := "1111";
end case;
elsif r2.s_state = getd and r2.hwrite = '1' then
v.mdata := hr.hwdata;
end if;
if r2.hreq(0) = '1' then v.hrdata := r.ldata; end if;
if r2.preq_ack(0) = '1' then v.preq := '0'; end if;
if r2.pabort(0) = '1' then v.perror := '1'; end if;
if p_done = '0' then v.hreq_ack := '0'; end if;
-- AHB slave state machine
case r2.s_state is
when idle => if request = '1' then v.s_state := getd; end if;
when getd => v.s_state := req; v.preq := '1';
when req => if r2.preq_ack(0) = '1' then v.s_state := sync; end if;
when sync => if r2.preq_ack(0) = '0' then v.s_state := read; end if;
when read =>
if p_done = '1' then v.hreq_ack := '1'; v.s_state := sync2; end if;
when sync2 => if p_done = '0' then v.s_state := t_done; end if;
when t_done => if request = '1' then v.s_state := idle; end if;
when others => v.s_state := idle;
end case;
if request = '1' then
if r2.s_state = t_done then
if r2.perror = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
v.perror := '0';
else hresp := HRESP_RETRY; end if;
end if;
if r.comm.msen = '0' then hresp := HRESP_ERROR; end if; -- Master disabled
if htrans(1) = '0' then hresp := HRESP_OKAY; end if; -- Response OK for BUSY and IDLE
if (hresp /= HRESP_OKAY and (hr.hready and hr.hsel) = '1') then -- insert one wait cycle
hready := '0';
end if;
if hr.hready = '0' then hresp := r2.hresp; end if;
v.hresp := hresp;
end if;
---- *** AHB SLAVE END *** ----
if rst = '0' then
v.s_state := idle; v.rready := '0'; v.wready := '1';
v.m_state := idle; v.preq := '0'; v.hreq_ack := '0';
v.perror := '0'; v.be := (others => '1');
v.pciba := (others => '0'); v.hresp := (others => '0');
end if;
r2in <= v; dmai <= vdmai;
ahbso.hready <= hready;
ahbso.hresp <= hresp;
ahbso.hrdata <= r2.hrdata;
end process;
ahbso.hconfig <= hconfig when MASTER = 1 else (others => zero32);
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hindex <= hslvndx;
-- PCI target core (PCI clock domain)
pcicomb : process(pcii.rst, pr, pcii, r, r2, roe_ad)
variable v : pci_reg_type;
variable chit, mhit, hit, ready, cwrite : std_logic;
variable cdata, cwdata : std_logic_vector(31 downto 0);
variable comp : std_logic; -- Last transaction cycle on PCI bus
variable iready : std_logic;
variable mto : std_logic;
variable tad, mad : std_logic_vector(31 downto 0);
-- variable cbe : std_logic_vector(3 downto 0);
variable caddr : std_logic_vector(7 downto 2);
variable voe_ad : std_logic_vector(31 downto 0);
variable oe_par : std_logic;
variable oe_ad : std_logic;
variable oe_ctrl : std_logic;
variable oe_trdy : std_logic;
variable oe_devsel: std_logic;
variable oe_cbe : std_logic;
variable oe_stop : std_logic;
variable oe_frame : std_logic;
variable oe_irdy : std_logic;
variable oe_req : std_logic;
begin
-- Process defaults
v := r; v.trdy := '1'; v.stop := '1'; v.frame := '1';
v.oe_ad := '1'; v.devsel := '1'; v.oe_frame := '1';
v.irdy := '1'; v.req := '1'; voe_ad := roe_ad;
v.oe_req := '0'; v.oe_cbe := '1'; v.oe_irdy := '1';
v.rready(0) := r.rready(csync); v.rready(csync) := r2.rready;
v.wready(0) := r.wready(csync); v.wready(csync) := r2.wready;
v.sync(0) := r.sync(csync); v.sync(csync) := r2.sync;
v.preq(0) := r.preq(csync); v.preq(csync) := r2.preq;
v.hreq_ack(0) := r.hreq_ack(csync); v.hreq_ack(csync) := r2.hreq_ack;
comp := '0'; mto := '0'; tad := r.ad; mad := r.ad; v.stop_req := '0';
--cbe := r.cbe;
----- *** PCI TARGET *** --------
-- address decoding
if (r.t_state = s_data) and ((pr.irdy or r.trdy or r.read) = '0') then
cwrite := r.csel;
if ((r.msel and r.addr(MADDR_WIDTH-1)) = '1') and (pr.cbe = "0000") then
v.page := pr.ad(31 downto MADDR_WIDTH-1);
end if;
if (pr.cbe = "0000") and (r.addr(MADDR_WIDTH-1) = '1') then
end if;
else cwrite := '0'; end if;
cdata := (others => '0'); caddr := r.addr(7 downto 2);
case caddr is
when "000000" => -- 0x00, device & vendor id
cdata := conv_std_logic_vector(DEVICE_ID, 16) &
conv_std_logic_vector(VENDOR_ID, 16);
when "000001" => -- 0x04, status & command
cdata(1) := r.comm.men; cdata(2) := r.comm.msen; cdata(25) := '1';
cdata(28) := r.stat.rta; cdata(29) := r.stat.rma;
when "000010" => -- 0x08, class code & revision
when "000011" => -- 0x0c, latency & cacheline size
when "000100" => -- 0x10, BAR0
cdata(31 downto MADDR_WIDTH) := r.bar0;
when others =>
end case;
cwdata := pr.ad;
if pr.cbe(3) = '1' then cwdata(31 downto 24) := cdata(31 downto 24); end if;
if pr.cbe(2) = '1' then cwdata(23 downto 16) := cdata(23 downto 16); end if;
if pr.cbe(1) = '1' then cwdata(15 downto 8) := cdata(15 downto 8); end if;
if pr.cbe(0) = '1' then cwdata( 7 downto 0) := cdata( 7 downto 0); end if;
if cwrite = '1' then
case caddr is
when "000001" => -- 0x04, status & command
v.comm.men := cwdata(1);
v.comm.msen := cwdata(2);
v.stat.rta := r.stat.rta and not cwdata(28);
v.stat.rma := r.stat.rma and not cwdata(29);
when "000100" => -- 0x10, BAR0
v.bar0 := cwdata(31 downto MADDR_WIDTH);
when others =>
end case;
end if;
if (((pr.cbe = pci_config_read) or (pr.cbe = pci_config_write))
and (pr.ad(1 downto 0) = "00"))
then chit := '1'; else chit := '0'; end if;
if ((pr.cbe = pci_memory_read) or (pr.cbe = pci_memory_write))
and (r.bar0 = pr.ad(31 downto MADDR_WIDTH))
and (r.bar0 /= zero(31 downto MADDR_WIDTH))
then mhit := '1'; else mhit := '0'; end if;
hit := r.csel or r.msel;
ready := r.csel or (r.rready(0) and r.read) or (r.wready(0) and not r.read and not r.start) or
r.addr(MADDR_WIDTH-1);
-- target state machine
case r.t_state is
when idle =>
if pr.frame = '0' then v.t_state := b_busy; end if; -- !HIT ?
v.addr := pr.ad(MADDR_WIDTH-1 downto 0); -- v.cbe := pr.cbe;
v.csel := pr.idsel and chit;
v.msel := r.comm.men and mhit; v.read := not pr.cbe(0);
if (r.sync(0) and r.start and r.pwrite) = '1' then v.start := '0'; end if;
when turn_ar =>
if pr.frame = '1' then v.t_state := idle; end if;
if pr.frame = '0' then v.t_state := b_busy; end if; -- !HIT ?
v.addr := pr.ad(MADDR_WIDTH-1 downto 0); -- v.cbe := pr.cbe;
v.csel := pr.idsel and chit;
v.msel := r.comm.men and mhit; v.read := not pr.cbe(0);
if (r.sync(0) and r.start and r.pwrite) = '1' then v.start := '0'; end if;
when b_busy =>
if hit = '1' then
v.t_state := s_data; v.trdy := not ready; v.stop := pr.frame and ready;
v.devsel := '0';
else
v.t_state := backoff;
end if;
when s_data =>
v.stop := r.stop; v.devsel := '0';
v.trdy := r.trdy or not pcii.irdy;
if (pcii.frame and not pcii.irdy) = '1' then
v.t_state := turn_ar; v.stop := '1'; v.trdy := '1'; v.devsel := '1';
end if;
when backoff =>
if pr.frame = '1' then v.t_state := idle; end if;
end case;
if ((r.t_state = s_data) or (r.t_state = turn_ar)) and
(((pr.irdy or pr.trdy) = '0') or
((not pr.irdy and not pr.stop and pr.trdy and not r.start and r.wready(0)) = '1'))
then
if (pr.trdy and r.read)= '0' then v.start := '0'; end if;
if (r.start = '0') and ((r.msel and not r.addr(MADDR_WIDTH-1)) = '1') and
(((pr.trdy and r.read and not r.rready(0)) or (not pr.trdy and not r.read)) = '1')
then
v.laddr := r.page & r.addr(MADDR_WIDTH-2 downto 0);
v.ldata := pr.ad; v.pwrite := not r.read; v.start := '1';
end if;
end if;
-- if (v.t_state = s_data) and (r.read = '1') then v.oe_ad := '0'; end if;
-- v.oe_par := r.oe_ad;
if r.csel = '1' then tad := cdata;
elsif r.addr(MADDR_WIDTH-1) = '1' then
tad(31 downto MADDR_WIDTH-1) := r.page;
tad(MADDR_WIDTH-2 downto 0) := (others => '0');
else tad := r2.tdata; end if;
if (v.t_state = s_data) or (r.t_state = s_data) then
v.oe_ctrl := '0';
else v.oe_ctrl := '1'; end if;
----- *** PCI TARGET END*** --------
----- *** PCI MASTER *** --------
if MASTER = 1 then
if r.preq(0) = '1' then
if (r.m_state = idle or r.m_state = dr_bus) and r.request = '0' and r.hreq = '0' then
v.request := '1';
v.hwrite := r2.hwrite;
v.lcbe := r2.be;
v.mdata := r2.mdata;
v.maddr :=r2.maddr;
end if;
end if;
if r.hreq_ack(0) = '1' then v.hreq := '0'; v.pabort := '0'; end if;
if r.preq(0) = '0' then v.preq_ack := '0'; end if;
comp := not(pcii.trdy or pcii.irdy);
if ((pr.irdy and not pr.frame) or (pr.devsel and r.frame and not r.oe_frame)) = '1' then -- Covers both master timeout and devsel timeout
if r.mcnt /= "000" then v.mcnt := r.mcnt - 1;
else mto := '1'; end if;
else v.mcnt := (others => '1'); end if;
-- PCI master state machine
case r.m_state is
when idle => -- Master idle
if (pr.gnt = '0' and (pr.frame and pr.irdy) = '1') then
if r.request = '1' then v.m_state := addr; v.preq_ack := '1';
else v.m_state := dr_bus; end if;
end if;
when addr => -- Always one address cycle at the beginning of an transaction
v.m_state := m_data;
when m_data => -- Master transfers data
--if (r.request and not pr.gnt and pr.frame and not pr.trdy -- Not supporting address stepping!
--and pr.stop and l_cycle and sa) = '1' then
--v.m_state <= addr;
v.hreq := comp;
if (pr.frame = '0') or ((pr.frame and pcii.trdy and pcii.stop and not mto) = '1') then
v.m_state := m_data;
elsif ((pr.frame and (mto or not pcii.stop)) = '1') then
v.m_state := s_tar;
else v.m_state := turn_ar; v.request := '0'; end if;
when turn_ar => -- Transaction complete
if (r.request and not pr.gnt) = '1' then v.m_state := addr;
elsif (r.request or pr.gnt) = '0' then v.m_state := dr_bus;
else v.m_state := idle; end if;
when s_tar => -- Stop was asserted
v.request := pr.trdy and not pr.stop and not pr.devsel;
v.stop_req := '1';
if (pr.stop or pr.devsel or pr.trdy) = '0' then -- Disconnect with data
v.m_state := turn_ar;
elsif pr.gnt = '0' then
v.pabort := not v.request;
v.m_state := dr_bus;
else v.m_state := idle; v.pabort := not v.request; end if;
when dr_bus => -- Drive bus when parked on this agent
if (r.request = '1' and (pcii.gnt or r.req) = '0') then v.m_state := addr; v.preq_ack := '1';
elsif pcii.gnt = '1' then v.m_state := idle; end if;
end case;
if v.m_state = addr then mad := r.maddr; else mad := r.mdata; end if;
if (pr.irdy or pr.trdy or r.hwrite) = '0' then v.ldata := pr.ad; end if;
-- Target abort
if ((pr.devsel and pr.trdy and not pr.gnt and not pr.stop) = '1') then v.stat.rta := '1'; end if;
-- Master abort
if mto = '1' then v.stat.rma := '1'; end if;
-- Drive FRAME# and IRDY#
if (v.m_state = addr or v.m_state = m_data) then v.oe_frame := '0'; end if;
-- Drive CBE#
if (v.m_state = addr or v.m_state = m_data or v.m_state = dr_bus) then v.oe_cbe := '0'; end if;
-- Drive IRDY# (FRAME# delayed one pciclk)
v.oe_irdy := r.oe_frame;
-- FRAME# assert
if v.m_state = addr then v.frame := '0'; end if; -- Only single transfers valid
-- IRDY# assert
if v.m_state = m_data then v.irdy := '0'; end if;
-- REQ# assert
if (v.request = '1' and (v.m_state = idle or r.m_state = idle) and (v.stop_req or r.stop_req) = '0') then v.req := '0'; end if;
-- C/BE# assert
if v.m_state = addr then v.cbe := "011" & r.hwrite; else v.cbe := r.lcbe; end if;
end if;
----- *** PCI MASTER END *** --------
----- *** SHARED BUS SIGNALS *** -------
-- Drive PAR
v.oe_par := r.oe_ad; --Delayed one clock
v.par := xorv(r.ad & r.cbe); -- Default asserted by master
v.ad := mad; -- Default asserted by master
-- Master
if (v.m_state = addr or (v.m_state = m_data and r.hwrite = '1') or v.m_state = dr_bus) then
v.oe_ad := '0';
end if;
-- Drive AD
-- Target
if r.read = '1' then
if v.t_state = s_data then
v.oe_ad := '0';
v.ad := tad;
elsif r.t_state = s_data then
v.par := xorv(r.ad & pcii.cbe);
end if;
end if;
v.oe_stop := v.oe_ctrl; v.oe_devsel := v.oe_ctrl; v.oe_trdy := v.oe_ctrl;
v.noe_ad := not v.oe_ad; v.noe_ctrl := not v.oe_ctrl;
v.noe_par := not v.oe_par; v.noe_req := not v.oe_req;
v.noe_frame := not v.oe_frame; v.noe_cbe := not v.oe_cbe;
v.noe_irdy := not v.oe_irdy;
v.noe_stop := not v.oe_ctrl; v.noe_devsel := not v.oe_ctrl;
v.noe_trdy := not v.oe_ctrl;
if oepol = 0 then
voe_ad := (others => v.oe_ad);
oe_ad := r.oe_ad; oe_ctrl := r.oe_ctrl; oe_par := r.oe_par;
oe_req := r.oe_req; oe_frame := r.oe_frame; oe_cbe := r.oe_cbe;
oe_irdy := r.oe_irdy; oe_stop := r.oe_stop; oe_trdy := r.oe_trdy;
oe_devsel := r.oe_devsel;
else
voe_ad := (others => v.noe_ad);
oe_ad := r.noe_ad; oe_ctrl := r.noe_ctrl; oe_par := r.noe_par;
oe_req := r.noe_req; oe_frame := r.noe_frame; oe_cbe := r.noe_cbe;
oe_irdy := r.noe_irdy; oe_stop := r.noe_stop; oe_trdy := r.noe_trdy;
oe_devsel := r.noe_devsel;
end if;
----- *** SHARED BUS SIGNALS END *** -------
if pr.rst = '0' then
v.t_state := idle; v.m_state := idle; v.comm.men := '0'; v.start := '0';
v.bar0 := (others => '0'); v.msel := '0'; v.csel := '0';
v.page := (others => '0'); v.page(31 downto 30) := "01"; v.par := '0';
v.hwrite := '0'; v.request := '0'; v.comm.msen := '0';
v.laddr := (others => '0'); v.ldata := (others => '0');
v.hreq := '0'; v.preq_ack := '0'; v.pabort := '0';
v.mcnt := (others => '1'); v.maddr := (others => '0');
v.lcbe := (others => '0'); v.mdata := (others => '0');
v.pwrite := '0'; v.stop_req := '0';
v.stat.rta := '0'; v.stat.rma := '0';
end if;
rin <= v;
rioe_ad <= voe_ad;
pcio.reqen <= oe_req;
pcio.req <= r.req;
pcio.frameen <= oe_frame;
pcio.frame <= r.frame;
pcio.irdyen <= oe_irdy;
pcio.irdy <= r.irdy;
pcio.cbeen <= (others => oe_cbe);
pcio.cbe <= r.cbe;
pcio.vaden <= roe_ad;
pcio.aden <= oe_ad;
pcio.ad <= r.ad;
pcio.trdy <= r.trdy;
pcio.ctrlen <= oe_ctrl;
pcio.trdyen <= oe_trdy;
pcio.devselen <= oe_devsel;
pcio.stopen <= oe_stop;
pcio.stop <= r.stop;
pcio.devsel <= r.devsel;
pcio.par <= r.par;
pcio.paren <= oe_par;
end process;
pcir : process (pciclk, pcii.rst)
begin
if rising_edge (pciclk) then
pr.ad <= to_x01(pcii.ad);
pr.cbe <= to_x01(pcii.cbe);
pr.devsel <= to_x01(pcii.devsel);
pr.frame <= to_x01(pcii.frame);
pr.idsel <= to_x01(pcii.idsel);
pr.irdy <= to_x01(pcii.irdy);
pr.trdy <= to_x01(pcii.trdy);
pr.par <= to_x01(pcii.par);
pr.stop <= to_x01(pcii.stop);
pr.rst <= to_x01(pcii.rst);
pr.gnt <= to_x01(pcii.gnt);
r <= rin;
roe_ad <= rioe_ad;
end if;
if pcii.rst = '0' then -- asynch reset required
r.oe_ad <= '1'; r.oe_ctrl <= '1'; r.oe_par <= '1'; r.oe_stop <= '1';
r.oe_req <= '1'; r.oe_frame <= '1'; r.oe_cbe <= '1'; r.oe_irdy <= '1';
r.oe_trdy <= '1'; r.oe_devsel <= '1';
r.noe_ad <= '0'; r.noe_ctrl <= '0'; r.noe_par <= '0'; r.noe_req <= '0';
r.noe_frame <= '0'; r.noe_cbe <= '0'; r.noe_irdy <= '0'; r.noe_stop <= '0';
r.noe_trdy <= '0'; r.noe_devsel <= '0';
if oepol = 0 then roe_ad <= (others => '1');
else roe_ad <= (others => '0'); end if;
end if;
end process;
cpur : process (rst,clk)
begin
if rising_edge (clk) then
hr.haddr <= ahbsi.haddr(HADDR_WIDTH - 1 downto 0);
hr.htrans <= ahbsi.htrans;
hr.hwrite <= ahbsi.hwrite;
hr.hsize <= ahbsi.hsize(1 downto 0);
hr.hburst <= ahbsi.hburst;
hr.hwdata <= ahbsi.hwdata;
hr.hsel <= ahbsi.hsel(hslvndx) and ahbsi.hmbsel(0);
hr.hiosel <= ahbsi.hsel(hslvndx) and ahbsi.hmbsel(1);
hr.hready <= ahbsi.hready;
r2 <= r2in;
end if;
end process;
oe0 : if oepol = 0 generate
pcio.perren <= '1';
pcio.serren <= '1';
pcio.inten <= '1';
pcio.locken <= '1';
end generate;
oe1 : if oepol = 1 generate
pcio.perren <= '0';
pcio.serren <= '0';
pcio.inten <= '0';
pcio.locken <= '0';
end generate;
pcio.perr <= '1';
pcio.serr <= '1';
pcio.int <= '1';
msttgt : if MASTER = 1 generate
ahbmst0 : ahbmst generic map (hindex => hmstndx, devid => GAISLER_PCISBRG)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mt" & tost(hslvndx) &
": Simple 32-bit PCI Bridge, rev " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR" );
-- pragma translate_on
end generate;
tgtonly : if MASTER = 0 generate
ahbmst0 : ahbmst generic map (hindex => hmstndx, devid => GAISLER_PCITRG)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mt" & tost(hmstndx) &
": Simple 32-bit Bridge, target-only, rev " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR" );
-- pragma translate_on
end generate;
end;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
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